From: Randy Dunlap Many Linux kernel style cleanups. Summary of general issues for this driver: I'm not addressing SCSI or MM/DMA API issues, if there are any. 0. some Kconfig and Makefile cleanups 1. fix arcmsr_device_id_table[] inits; 2. fix return (value); -- don't use parenethese 3. fix one-line-ifs-with-braces -- remove braces 4. struct _XYZ & typedef XYZ, PXYZ -- convert to struct XYZ only 5. check NULL usage, use NULL instead of 0 for pointers 6. no "return;" at end of func; -- removed 7. return -ENXIO instead of ENXIO; 8. don't indent cases in a switch block. 9. don't use // comments; Patch for above items is below. More issues, not yet patched: 10. use printk levels 11. pPCI_DEV: bad naming (throughout driver; don't use mixed case) 12. some comments are unreadable (non-ASCII ?) 13. uintNN_t int types: use kernel types except for userspace interfaces 14. use kernel-doc 15. try to fit source files into 80 columns (lots fixed, lots to go) 16. Tab size in Linux kernel is 8 (not less). 17. Don't put changelog comments in source files. That's what SCMs are for (source code manager tools). 18. Put arcmsr.txt in Documentation/scsi/, not in scsi/arcmsr/. 19. Maybe use sysfs (/sys) instead of /proc. 20. check sparse warnings, stack usage, init/exit sections; (No stack size problems found; some sparse warnings fixed, more to be done.) Signed-off-by: Randy Dunlap Cc: Signed-off-by: Andrew Morton --- drivers/scsi/Kconfig | 28 drivers/scsi/arcmsr/Makefile | 4 drivers/scsi/arcmsr/arcmsr.c | 1590 +++++++++++++------------------ drivers/scsi/arcmsr/arcmsr.h | 1330 ++++++++++++------------- drivers/scsi/arcmsr/arcmsr.txt | 34 5 files changed, 1383 insertions(+), 1603 deletions(-) diff -puN drivers/scsi/arcmsr/arcmsr.c~areca-raid-driver-arcmsr-cleanups drivers/scsi/arcmsr/arcmsr.c --- devel/drivers/scsi/arcmsr/arcmsr.c~areca-raid-driver-arcmsr-cleanups 2006-01-07 00:16:26.000000000 -0800 +++ devel-akpm/drivers/scsi/arcmsr/arcmsr.c 2006-01-07 00:16:26.000000000 -0800 @@ -1,5 +1,5 @@ /* -****************************************************************************************** +*************************************************************************** ** O.S : Linux ** FILE NAME : arcmsr.c ** BY : Erich Chen @@ -19,27 +19,27 @@ ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ** GNU General Public License for more details. ************************************************************************ -** Redistribution and use in source and binary forms,with or without -** modification,are permitted provided that the following conditions +** Redistribution and use in source and binary forms, with or without +** modification, are permitted provided that the following conditions ** are met: ** 1. Redistributions of source code must retain the above copyright -** notice,this list of conditions and the following disclaimer. +** notice, this list of conditions and the following disclaimer. ** 2. Redistributions in binary form must reproduce the above copyright -** notice,this list of conditions and the following disclaimer in the +** notice, this list of conditions and the following disclaimer in the ** documentation and/or other materials provided with the distribution. ** 3. The name of the author may not be used to endorse or promote products ** derived from this software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, -** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT -** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY -** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT +** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT +** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY +** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF -** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ************************************************************************** ** History ** @@ -53,23 +53,23 @@ ** 1.20.00.02 12/09/2004 Erich Chen bug fix with over 2T bytes RAID Volume ** 1.20.00.04 1/09/2005 Erich Chen fits for Debian linux kernel version 2.2.xx ** 1.20.00.05 2/20/2005 Erich Chen cleanly as look like a Linux driver at 2.6.x -** thanks for peoples kindness comment -** Kornel Wieliczek -** Christoph Hellwig -** Adrian Bunk -** Andrew Morton -** Christoph Hellwig -** James Bottomley -** Arjan van de Ven +** thanks for peoples kindness comment +** Kornel Wieliczek +** Christoph Hellwig +** Adrian Bunk +** Andrew Morton +** Christoph Hellwig +** James Bottomley +** Arjan van de Ven ** 1.20.00.06 3/12/2005 Erich Chen fix with arcmsr_pci_unmap_dma "unsigned long" cast, ** modify PCCB POOL allocated by "dma_alloc_coherent" ** (Kornel Wieliczek's comment) ** 1.20.00.07 3/23/2005 Erich Chen bug fix with arcmsr_scsi_host_template_init occur segmentation fault, ** if RAID adapter does not on PCI slot and modprobe/rmmod this driver twice. ** bug fix enormous stack usage (Adrian Bunk's comment) -** 1.20.00.08 6/23/2005 Erich Chen bug fix with abort command,in case of heavy loading when sata cable +** 1.20.00.08 6/23/2005 Erich Chen bug fix with abort command, in case of heavy loading when sata cable ** working on low quality connection -** 1.20.00.09 9/12/2005 Erich Chen bug fix with abort command handling,firmware version check +** 1.20.00.09 9/12/2005 Erich Chen bug fix with abort command handling, firmware version check ** and firmware update notify for hardware bug fix ** 1.20.00.10 9/23/2005 Erich Chen enhance sysfs function for change driver's max tag Q number. ** add DMA_64BIT_MASK for backward compatible with all 2.6.x @@ -77,19 +77,19 @@ ** add ioctl code 'ARCMSR_IOCTL_FLUSH_ADAPTER_CACHE' ** customer can send this command for sync raid volume data ** 1.20.00.11 9/29/2005 Erich Chen by comment of Arjan van de Ven fix incorrect msleep redefine -** cast off sizeof(dma_addr_t) condition for 64bit pci_set_dma_mask -** 1.20.00.12 9/30/2005 Erich Chen bug fix with 64bit platform's ccbs using if over 4G system memory -** change 64bit pci_set_consistent_dma_mask into 32bit +** cast off sizeof(dma_addr_t) condition for 64-bit pci_set_dma_mask +** 1.20.00.12 9/30/2005 Erich Chen bug fix with 64-bit platform's ccbs using if over 4G system memory +** change 64-bit pci_set_consistent_dma_mask into 32-bit ** increcct adapter count if adapter initialize fail. ** miss edit at arcmsr_build_ccb.... -** psge += sizeof(struct _SG64ENTRY *) => psge += sizeof(struct _SG64ENTRY) +** psge += sizeof(struct SG64ENTRY *) => psge += sizeof(struct SG64ENTRY) ** 64 bits sg entry would be incorrectly calculated ** thanks Kornel Wieliczek give me kindly notify and detail description ** 1.20.00.13 11/15/2005 Erich Chen scheduling pending ccb with FIFO ** change the architecture of arcmsr command queue list ** for linux standard list ** enable usage of pci message signal interrupt -****************************************************************************************** +*************************************************************************** */ #include #include @@ -99,6 +99,7 @@ #include #include #include +#include #include #include #include @@ -118,14 +119,12 @@ MODULE_DESCRIPTION("ARECA (ARC11xx/12xx) MODULE_LICENSE("Dual BSD/GPL"); /* -********************************************************************************** -********************************************************************************** +*************************************************************************** */ static uint8_t arcmsr_adapterCnt = 0; -static struct _HCBARC arcmsr_host_control_block; +static struct HCBARC arcmsr_host_control_block; /* -********************************************************************************** -********************************************************************************** +*************************************************************************** */ static int arcmsr_fops_ioctl(struct inode *inode, struct file *filep, unsigned int ioctl_cmd, unsigned long arg); @@ -133,8 +132,8 @@ static int arcmsr_fops_close(struct inod static int arcmsr_fops_open(struct inode *inode, struct file *filep); static int arcmsr_halt_notify(struct notifier_block *nb, unsigned long event, void *buf); -static int arcmsr_initialize(struct _ACB *pACB, struct pci_dev *pPCI_DEV); -static int arcmsr_iop_ioctlcmd(struct _ACB *pACB, int ioctl_cmd, void *arg); +static int arcmsr_initialize(struct ACB *pACB, struct pci_dev *pPCI_DEV); +static int arcmsr_iop_ioctlcmd(struct ACB *pACB, int ioctl_cmd, void __user *arg); static int arcmsr_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset, int length, int inout); static int arcmsr_bios_param(struct scsi_device *sdev, @@ -145,25 +144,23 @@ static int arcmsr_queue_command(struct s void (*done) (struct scsi_cmnd *)); static int arcmsr_cmd_abort(struct scsi_cmnd *); static int arcmsr_bus_reset(struct scsi_cmnd *); -static int arcmsr_ioctl(struct scsi_device *dev, int ioctl_cmd, void *arg); +static int arcmsr_ioctl(struct scsi_device *dev, int ioctl_cmd, void __user *arg); static int __devinit arcmsr_device_probe(struct pci_dev *pPCI_DEV, const struct pci_device_id *id); static void arcmsr_device_remove(struct pci_dev *pPCI_DEV); -static void arcmsr_pcidev_disattach(struct _ACB *pACB); -static void arcmsr_iop_init(struct _ACB *pACB); -static void arcmsr_free_ccb_pool(struct _ACB *pACB); -static irqreturn_t arcmsr_interrupt(struct _ACB *pACB); -static uint8_t arcmsr_wait_msgint_ready(struct _ACB *pACB); +static void arcmsr_pcidev_disattach(struct ACB *pACB); +static void arcmsr_iop_init(struct ACB *pACB); +static void arcmsr_free_ccb_pool(struct ACB *pACB); +static irqreturn_t arcmsr_interrupt(struct ACB *pACB); +static uint8_t arcmsr_wait_msgint_ready(struct ACB *pACB); static const char *arcmsr_info(struct Scsi_Host *); /* -********************************************************************************** -** -********************************************************************************** +*************************************************************************** */ static ssize_t arcmsr_show_firmware_info(struct class_device *dev, char *buf) { struct Scsi_Host *host = class_to_shost(dev); - struct _ACB *pACB = (struct _ACB *)host->hostdata; + struct ACB *pACB = (struct ACB *)host->hostdata; unsigned long flags = 0; ssize_t len; @@ -188,7 +185,7 @@ static ssize_t arcmsr_show_firmware_info static ssize_t arcmsr_show_driver_state(struct class_device *dev, char *buf) { struct Scsi_Host *host = class_to_shost(dev); - struct _ACB *pACB = (struct _ACB *)host->hostdata; + struct ACB *pACB = (struct ACB *)host->hostdata; unsigned long flags = 0; ssize_t len; @@ -238,9 +235,8 @@ static struct class_device_attribute *ar static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth) { - if (queue_depth > ARCMSR_MAX_CMD_PERLUN) { + if (queue_depth > ARCMSR_MAX_CMD_PERLUN) queue_depth = ARCMSR_MAX_CMD_PERLUN; - } scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth); return queue_depth; } @@ -248,16 +244,13 @@ static struct scsi_host_template arcmsr_ .module = THIS_MODULE, .proc_name = "arcmsr", .proc_info = arcmsr_proc_info, - .name = "ARCMSR ARECA SATA RAID HOST Adapter" ARCMSR_DRIVER_VERSION, /* *name */ + .name = "ARCMSR ARECA SATA RAID HOST Adapter" ARCMSR_DRIVER_VERSION, .release = arcmsr_release, .info = arcmsr_info, .ioctl = arcmsr_ioctl, .queuecommand = arcmsr_queue_command, - .eh_strategy_handler = NULL, .eh_abort_handler = arcmsr_cmd_abort, - .eh_device_reset_handler = NULL, .eh_bus_reset_handler = arcmsr_bus_reset, - .eh_host_reset_handler = NULL, .bios_param = arcmsr_bios_param, .change_queue_depth = arcmsr_adjust_disk_queue_depth, .can_queue = ARCMSR_MAX_OUTSTANDING_CMD, @@ -271,12 +264,13 @@ static struct scsi_host_template arcmsr_ }; /* -********************************************************************************** +*************************************************************************** ** notifier block to get a notify on system shutdown/halt/reboot -********************************************************************************** +*************************************************************************** */ static struct notifier_block arcmsr_event_notifier = - { arcmsr_halt_notify, NULL, 0 }; + { .notifier_call = arcmsr_halt_notify }; + static struct file_operations arcmsr_file_operations = { .owner = THIS_MODULE, .ioctl = arcmsr_fops_ioctl, @@ -286,28 +280,17 @@ static struct file_operations arcmsr_fil /* We do our own ID filtering. So, grab all SCSI storage class devices. */ static struct pci_device_id arcmsr_device_id_table[] __devinitdata = { - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1110,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1120,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1130,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1160,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1170,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1210,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1220,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1230,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1260,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCIDeviceIDARC1270,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, - {.vendor = PCIVendorIDARECA,.device = PCI_ANY_ID,.subvendor = - PCI_ANY_ID,.subdevice = PCI_ANY_ID,}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1110)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1120)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1130)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1160)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1170)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1210)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1220)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1230)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1260)}, + {PCI_DEVICE(PCIVendorIDARECA, PCIDeviceIDARC1270)}, + {PCI_DEVICE(PCIVendorIDARECA, PCI_ANY_ID)}, {0, 0}, /* Terminating entry */ }; @@ -319,39 +302,35 @@ static struct pci_driver arcmsr_pci_driv .remove = arcmsr_device_remove, }; -/* -********************************************************************* -********************************************************************* -*/ +/********************************************************************/ + static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id, struct pt_regs *regs) { irqreturn_t handle_state; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; - struct _ACB *pACB; - struct _ACB *pACBtmp; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; + struct ACB *pACBtmp; unsigned long flags; int i = 0; - pACB = (struct _ACB *)dev_id; + pACB = (struct ACB *)dev_id; pACBtmp = pHCBARC->pACB[i]; while ((pACB != pACBtmp) && pACBtmp && (i < ARCMSR_MAX_ADAPTER)) { i++; pACBtmp = pHCBARC->pACB[i]; } - if (!pACBtmp) { + if (!pACBtmp) return IRQ_NONE; - } + spin_lock_irqsave(pACB->host->host_lock, flags); handle_state = arcmsr_interrupt(pACB); spin_unlock_irqrestore(pACB->host->host_lock, flags); - return (handle_state); + return handle_state; } -/* -********************************************************************* -********************************************************************* -*/ +/********************************************************************/ + static int arcmsr_bios_param(struct scsi_device *sdev, struct block_device *bdev, sector_t capacity, int *geom) @@ -365,9 +344,8 @@ static int arcmsr_bios_param(struct scsi scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]); kfree(buffer); - if (ret != -1) { - return (ret); - } + if (ret != -1) + return ret; } total_capacity = capacity; heads = 64; @@ -381,19 +359,17 @@ static int arcmsr_bios_param(struct scsi geom[0] = heads; geom[1] = sectors; geom[2] = cylinders; - return (0); + return 0; } -/* -************************************************************************ -************************************************************************ -*/ +/********************************************************************/ + static int __devinit arcmsr_device_probe(struct pci_dev *pPCI_DEV, const struct pci_device_id *id) { struct Scsi_Host *host; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; - struct _ACB *pACB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; uint8_t bus, dev_fun; if (pci_enable_device(pPCI_DEV)) { @@ -401,23 +377,23 @@ static int __devinit arcmsr_device_probe arcmsr_adapterCnt); return -ENODEV; } - /* allocate scsi host information (includes out adapter) scsi_host_alloc==scsi_register */ - if ((host = - scsi_host_alloc(&arcmsr_scsi_host_template, - sizeof(struct _ACB))) == 0) { + /* allocate scsi host information (includes our adapter) + * scsi_host_alloc==scsi_register */ + if ((host = scsi_host_alloc(&arcmsr_scsi_host_template, + sizeof(struct ACB))) == NULL) { printk("arcmsr%d: adapter probe: scsi_host_alloc error \n", arcmsr_adapterCnt); return -ENODEV; } - if (!pci_set_dma_mask(pPCI_DEV, DMA_64BIT_MASK)) { + if (!pci_set_dma_mask(pPCI_DEV, DMA_64BIT_MASK)) printk ("ARECA RAID ADAPTER%d: 64BITS PCI BUS DMA ADDRESSING SUPPORTED\n", arcmsr_adapterCnt); - } else if (!pci_set_dma_mask(pPCI_DEV, DMA_32BIT_MASK)) { + else if (!pci_set_dma_mask(pPCI_DEV, DMA_32BIT_MASK)) printk ("ARECA RAID ADAPTER%d: 32BITS PCI BUS DMA ADDRESSING SUPPORTED\n", arcmsr_adapterCnt); - } else { + else { printk("ARECA RAID ADAPTER%d: No suitable DMA available.\n", arcmsr_adapterCnt); return -ENOMEM; @@ -430,8 +406,8 @@ static int __devinit arcmsr_device_probe } bus = pPCI_DEV->bus->number; dev_fun = pPCI_DEV->devfn; - pACB = (struct _ACB *)host->hostdata; - memset(pACB, 0, sizeof(struct _ACB)); + pACB = (struct ACB *)host->hostdata; + memset(pACB, 0, sizeof(struct ACB)); spin_lock_init(&pACB->qbuffer_lock); spin_lock_init(&pACB->pending_list_lock); spin_lock_init(&pACB->working_list_lock); @@ -441,9 +417,9 @@ static int __devinit arcmsr_device_probe host->max_sectors = ARCMSR_MAX_XFER_SECTORS; host->max_lun = ARCMSR_MAX_TARGETLUN; host->max_id = ARCMSR_MAX_TARGETID; /*16:8 */ - host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte */ + host->max_cmd_len = 16; /* this is issue of 64-bit LBA, over 2T byte */ host->sg_tablesize = ARCMSR_MAX_SG_ENTRIES; - host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */ + host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */ host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN; host->this_id = ARCMSR_SCSI_INITIATOR_ID; host->unique_id = (bus << 8) | dev_fun; @@ -467,9 +443,8 @@ static int __devinit arcmsr_device_probe return -ENODEV; } #ifdef CONFIG_PCI_MSI - if (pci_enable_msi(pPCI_DEV) == 0) { + if (pci_enable_msi(pPCI_DEV) == 0) pACB->acb_flags |= ACB_F_HAVE_MSI; - } #endif if (request_irq (pPCI_DEV->irq, arcmsr_do_interrupt, SA_INTERRUPT | SA_SHIRQ, @@ -494,45 +469,39 @@ static int __devinit arcmsr_device_probe return 0; } -/* -************************************************************************ -************************************************************************ -*/ +/********************************************************************/ + static void arcmsr_device_remove(struct pci_dev *pPCI_DEV) { struct Scsi_Host *host = pci_get_drvdata(pPCI_DEV); - struct _ACB *pACB = (struct _ACB *)host->hostdata; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB = (struct ACB *)host->hostdata; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; int i; arcmsr_pcidev_disattach(pACB); - /*if this is last pACB */ + /* if this is last pACB */ for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { - if (pHCBARC->pACB[i] != NULL) { + if (pHCBARC->pACB[i]) return; /* this is not last adapter's release */ - } } unregister_chrdev(pHCBARC->arcmsr_major_number, "arcmsr"); unregister_reboot_notifier(&arcmsr_event_notifier); - return; } -/* -************************************************************************ -************************************************************************ -*/ +/********************************************************************/ + static int arcmsr_scsi_host_template_init(struct scsi_host_template *host_template) { int error; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; /* ** register as a PCI hot-plug driver module */ - memset(pHCBARC, 0, sizeof(struct _HCBARC)); + memset(pHCBARC, 0, sizeof(struct HCBARC)); error = pci_module_init(&arcmsr_pci_driver); - if (pHCBARC->pACB[0] != NULL) { + if (pHCBARC->pACB[0]) { host_template->proc_name = "arcmsr"; register_reboot_notifier(&arcmsr_event_notifier); pHCBARC->arcmsr_major_number = @@ -540,194 +509,158 @@ static int arcmsr_scsi_host_template_ini printk("arcmsr device major number %d \n", pHCBARC->arcmsr_major_number); } - return (error); + return error; } -/* -************************************************************************ -************************************************************************ -*/ +/********************************************************************/ + static int arcmsr_module_init(void) { - return (arcmsr_scsi_host_template_init(&arcmsr_scsi_host_template)); + return arcmsr_scsi_host_template_init(&arcmsr_scsi_host_template); } -/* -************************************************************************ -************************************************************************ -*/ +/********************************************************************/ + static void arcmsr_module_exit(void) { pci_unregister_driver(&arcmsr_pci_driver); - return; } module_init(arcmsr_module_init); module_exit(arcmsr_module_exit); -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_pci_unmap_dma(struct _CCB *pCCB) + +/********************************************************************/ + +static void arcmsr_pci_unmap_dma(struct CCB *pCCB) { - struct _ACB *pACB = pCCB->pACB; + struct ACB *pACB = pCCB->pACB; struct scsi_cmnd *pcmd = pCCB->pcmd; - if (pcmd->use_sg != 0) { + if (pcmd->use_sg) { struct scatterlist *sl; sl = (struct scatterlist *)pcmd->request_buffer; pci_unmap_sg(pACB->pPCI_DEV, sl, pcmd->use_sg, pcmd->sc_data_direction); - } else if (pcmd->request_bufflen != 0) { + } else if (pcmd->request_bufflen) pci_unmap_single(pACB->pPCI_DEV, (dma_addr_t) (unsigned long)pcmd->SCp.ptr, pcmd->request_bufflen, pcmd->sc_data_direction); - } - return; } -/* -********************************************************************************** -********************************************************************************** -*/ +/********************************************************************/ + static int arcmsr_fops_open(struct inode *inode, struct file *filep) { int i, minor; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; - struct _ACB *pACB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; minor = MINOR(inode->i_rdev); - if (minor >= pHCBARC->adapterCnt) { + if (minor >= pHCBARC->adapterCnt) return -ENXIO; - } for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { - if ((pACB = pHCBARC->pACB[i]) != NULL) { - if (pACB->adapter_index == minor) { + if ((pACB = pHCBARC->pACB[i])) + if (pACB->adapter_index == minor) break; - } - } } - if (i >= ARCMSR_MAX_ADAPTER) { + if (i >= ARCMSR_MAX_ADAPTER) return -ENXIO; - } return 0; /* success */ } -/* -********************************************************************************** -********************************************************************************** -*/ +/********************************************************************/ + static int arcmsr_fops_close(struct inode *inode, struct file *filep) { int i, minor; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; - struct _ACB *pACB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; minor = MINOR(inode->i_rdev); - if (minor >= pHCBARC->adapterCnt) { + if (minor >= pHCBARC->adapterCnt) return -ENXIO; - } for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { - if ((pACB = pHCBARC->pACB[i]) != NULL) { - if (pACB->adapter_index == minor) { + if ((pACB = pHCBARC->pACB[i])) + if (pACB->adapter_index == minor) break; - } - } } - if (i >= ARCMSR_MAX_ADAPTER) { + if (i >= ARCMSR_MAX_ADAPTER) return -ENXIO; - } return 0; } -/* -********************************************************************************** -********************************************************************************** -*/ +/********************************************************************/ + static int arcmsr_fops_ioctl(struct inode *inode, struct file *filep, unsigned int ioctl_cmd, unsigned long arg) { int i, minor; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; - struct _ACB *pACB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; minor = MINOR(inode->i_rdev); - if (minor >= pHCBARC->adapterCnt) { + if (minor >= pHCBARC->adapterCnt) return -ENXIO; - } for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { - if ((pACB = pHCBARC->pACB[i]) != NULL) { - if (pACB->adapter_index == minor) { + if ((pACB = pHCBARC->pACB[i])) + if (pACB->adapter_index == minor) break; - } - } } - if (i >= ARCMSR_MAX_ADAPTER) { + if (i >= ARCMSR_MAX_ADAPTER) return -ENXIO; - } /* ************************************************************ - ** We do not allow muti ioctls to the driver at the same duration. + ** We do not allow multi ioctls to the driver at the same time. ************************************************************ */ - return arcmsr_iop_ioctlcmd(pACB, ioctl_cmd, (void *)arg); + return arcmsr_iop_ioctlcmd(pACB, ioctl_cmd, (void __user *)arg); } -/* -************************************************************************ -************************************************************************ -*/ -static void arcmsr_flush_adapter_cache(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_flush_adapter_cache(struct ACB *pACB) { writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &pACB->pmu->inbound_msgaddr0); - if (arcmsr_wait_msgint_ready(pACB)) { + if (arcmsr_wait_msgint_ready(pACB)) printk("arcmsr%d: wait 'flush adapter cache' timeout \n", pACB->adapter_index); - } - return; } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_ccb_complete(struct _CCB *pCCB, int stand_flag) +/********************************************************************/ + +static void arcmsr_ccb_complete(struct CCB *pCCB, int stand_flag) { unsigned long flags; - struct _ACB *pACB = pCCB->pACB; + struct ACB *pACB = pCCB->pACB; struct scsi_cmnd *pcmd = pCCB->pcmd; arcmsr_pci_unmap_dma(pCCB); spin_lock_irqsave(&pACB->done_list_lock, flags); - if (stand_flag == 1) { + if (stand_flag == 1) atomic_dec(&pACB->ccboutstandingcount); - } pCCB->startdone = ARCMSR_CCB_DONE; pCCB->ccb_flags = 0; list_add_tail(&pCCB->list, &pACB->ccb_free_list); spin_unlock_irqrestore(&pACB->done_list_lock, flags); pcmd->scsi_done(pcmd); - return; } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_report_sense_info(struct _CCB *pCCB) +/********************************************************************/ + +static void arcmsr_report_sense_info(struct CCB *pCCB) { struct scsi_cmnd *pcmd = pCCB->pcmd; - struct _SENSE_DATA *psenseBuffer = - (struct _SENSE_DATA *)pcmd->sense_buffer; + struct SENSE_DATA *psenseBuffer = + (struct SENSE_DATA *)pcmd->sense_buffer; pcmd->result = DID_OK << 16; if (psenseBuffer) { int sense_data_length = - sizeof(struct _SENSE_DATA) < + sizeof(struct SENSE_DATA) < sizeof(pcmd-> - sense_buffer) ? sizeof(struct _SENSE_DATA) : + sense_buffer) ? sizeof(struct SENSE_DATA) : sizeof(pcmd->sense_buffer); memset(psenseBuffer, 0, sizeof(pcmd->sense_buffer)); memcpy(psenseBuffer, pCCB->arcmsr_cdb.SenseData, @@ -735,7 +668,6 @@ static void arcmsr_report_sense_info(str psenseBuffer->ErrorCode = 0x70; psenseBuffer->Valid = 1; } - return; } /* @@ -743,7 +675,7 @@ static void arcmsr_report_sense_info(str ** to insert pCCB into tail of pACB wait exec ccbQ ********************************************************************* */ -static void arcmsr_queue_pendingccb(struct _ACB *pACB, struct _CCB *pCCB) +static void arcmsr_queue_pendingccb(struct ACB *pACB, struct CCB *pCCB) { unsigned long flags; @@ -751,64 +683,56 @@ static void arcmsr_queue_pendingccb(stru list_add_tail(&pCCB->list, &pACB->ccb_pending_list); atomic_inc(&pACB->ccbpendingcount); spin_unlock_irqrestore(&pACB->pending_list_lock, flags); - return; } -/* -********************************************************************* -********************************************************************* -*/ -static void arcmsr_abort_allcmd(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_abort_allcmd(struct ACB *pACB) { writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &pACB->pmu->inbound_msgaddr0); - if (arcmsr_wait_msgint_ready(pACB)) { + if (arcmsr_wait_msgint_ready(pACB)) printk ("arcmsr%d: wait 'abort all outstanding command' timeout \n", pACB->adapter_index); - } - return; } -/* -********************************************************************** -********************************************************************** -*/ -static uint8_t arcmsr_wait_msgint_ready(struct _ACB *pACB) +/********************************************************************/ + +static uint8_t arcmsr_wait_msgint_ready(struct ACB *pACB) { uint32_t Index; uint8_t Retries = 0x00; + do { for (Index = 0; Index < 100; Index++) { if (readl(&pACB->pmu->outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { - writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &pACB->pmu->outbound_intstatus); /*clear interrupt */ + writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &pACB->pmu->outbound_intstatus); /* clear interrupt */ return 0x00; } msleep_interruptible(10); - } /*max 1 seconds */ - } while (Retries++ < 20); /*max 20 sec */ + } /* max 1 seconds */ + } while (Retries++ < 20); /* max 20 sec */ return 0xff; } -/* -************************************************************************** -************************************************************************** -*/ -static struct _CCB *arcmsr_get_pendingccb(struct _ACB *pACB) +/********************************************************************/ + +static struct CCB *arcmsr_get_pendingccb(struct ACB *pACB) { unsigned long flags; struct list_head *head = &pACB->ccb_pending_list; - struct _CCB *pCCB = NULL; + struct CCB *pCCB = NULL; if (spin_trylock_irqsave(&pACB->pending_list_lock, flags)) { if (!list_empty(head)) { - pCCB = list_entry(head->next, struct _CCB, list); + pCCB = list_entry(head->next, struct CCB, list); atomic_dec(&pACB->ccbpendingcount); list_del(head->next); } spin_unlock_irqrestore(&pACB->pending_list_lock, flags); } - return (pCCB); + return pCCB; } /* @@ -818,9 +742,9 @@ static struct _CCB *arcmsr_get_pendingcc ** Return Value: Nothing. **************************************************************************** */ -static void arcmsr_iop_reset(struct _ACB *pACB) +static void arcmsr_iop_reset(struct ACB *pACB) { - struct _CCB *pCCB; + struct CCB *pCCB; uint32_t intmask_org, mask; int i = 0; @@ -853,7 +777,7 @@ static void arcmsr_iop_reset(struct _ACB } while (atomic_read(&pACB->ccbpendingcount) != 0) { pCCB = arcmsr_get_pendingccb(pACB); - if (pCCB != NULL) { + if (pCCB) { printk ("arcmsr%d:iop reset abort command ccbpendingcount=%d \n", pACB->adapter_index, @@ -862,30 +786,26 @@ static void arcmsr_iop_reset(struct _ACB pCCB->pcmd->result = DID_ABORT << 16; arcmsr_ccb_complete(pCCB, 0); atomic_dec(&pACB->ccbpendingcount); - } else { + } else break; - } } atomic_set(&pACB->ccboutstandingcount, 0); atomic_set(&pACB->ccbpendingcount, 0); - return; } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_build_ccb(struct _ACB *pACB, struct _CCB *pCCB, +/********************************************************************/ + +static void arcmsr_build_ccb(struct ACB *pACB, struct CCB *pCCB, struct scsi_cmnd *pcmd) { - struct _ARCMSR_CDB *pARCMSR_CDB = - (struct _ARCMSR_CDB *)&pCCB->arcmsr_cdb; + struct ARCMSR_CDB *pARCMSR_CDB = + (struct ARCMSR_CDB *)&pCCB->arcmsr_cdb; int8_t *psge = (int8_t *) & pARCMSR_CDB->u; uint32_t address_lo, address_hi; int arccdbsize = 0x30; pCCB->pcmd = pcmd; - memset(pARCMSR_CDB, 0, sizeof(struct _ARCMSR_CDB)); + memset(pARCMSR_CDB, 0, sizeof(struct ARCMSR_CDB)); pARCMSR_CDB->Bus = 0; pARCMSR_CDB->TargetID = pcmd->device->id; pARCMSR_CDB->LUN = pcmd->device->lun; @@ -911,31 +831,30 @@ static void arcmsr_build_ccb(struct _ACB address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sl))); if (address_hi == 0) { - struct _SG32ENTRY *pdma_sg = - (struct _SG32ENTRY *)psge; + struct SG32ENTRY *pdma_sg = + (struct SG32ENTRY *)psge; pdma_sg->address = address_lo; pdma_sg->length = length; - psge += sizeof(struct _SG32ENTRY); - arccdbsize += sizeof(struct _SG32ENTRY); + psge += sizeof(struct SG32ENTRY); + arccdbsize += sizeof(struct SG32ENTRY); } else { - struct _SG64ENTRY *pdma_sg = - (struct _SG64ENTRY *)psge; + struct SG64ENTRY *pdma_sg = + (struct SG64ENTRY *)psge; pdma_sg->addresshigh = address_hi; pdma_sg->address = address_lo; pdma_sg->length = length | IS_SG64_ADDR; - psge += sizeof(struct _SG64ENTRY); - arccdbsize += sizeof(struct _SG64ENTRY); + psge += sizeof(struct SG64ENTRY); + arccdbsize += sizeof(struct SG64ENTRY); } sl++; cdb_sgcount++; } pARCMSR_CDB->sgcount = (uint8_t) cdb_sgcount; pARCMSR_CDB->DataLength = pcmd->request_bufflen; - if (arccdbsize > 256) { + if (arccdbsize > 256) pARCMSR_CDB->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; - } } else if (pcmd->request_bufflen) { dma_addr_t dma_addr; dma_addr = @@ -946,11 +865,11 @@ static void arcmsr_build_ccb(struct _ACB address_lo = cpu_to_le32(dma_addr_lo32(dma_addr)); address_hi = cpu_to_le32(dma_addr_hi32(dma_addr)); if (address_hi == 0) { - struct _SG32ENTRY *pdma_sg = (struct _SG32ENTRY *)psge; + struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; pdma_sg->address = address_lo; pdma_sg->length = pcmd->request_bufflen; } else { - struct _SG64ENTRY *pdma_sg = (struct _SG64ENTRY *)psge; + struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; pdma_sg->addresshigh = address_hi; pdma_sg->address = address_lo; pdma_sg->length = pcmd->request_bufflen | IS_SG64_ADDR; @@ -962,59 +881,48 @@ static void arcmsr_build_ccb(struct _ACB pARCMSR_CDB->Flags |= ARCMSR_CDB_FLAG_WRITE; pCCB->ccb_flags |= CCB_FLAG_WRITE; } - return; } -/* -************************************************************************** -************************************************************************** -*/ -static void arcmsr_post_ccb(struct _ACB *pACB, struct _CCB *pCCB) +/********************************************************************/ + +static void arcmsr_post_ccb(struct ACB *pACB, struct CCB *pCCB) { uint32_t cdb_shifted_phyaddr = pCCB->cdb_shifted_phyaddr; - struct _ARCMSR_CDB *pARCMSR_CDB = - (struct _ARCMSR_CDB *)&pCCB->arcmsr_cdb; + struct ARCMSR_CDB *pARCMSR_CDB = + (struct ARCMSR_CDB *)&pCCB->arcmsr_cdb; atomic_inc(&pACB->ccboutstandingcount); pCCB->startdone = ARCMSR_CCB_START; - if (pARCMSR_CDB->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { + if (pARCMSR_CDB->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE, &pACB->pmu->inbound_queueport); - } else { + else writel(cdb_shifted_phyaddr, &pACB->pmu->inbound_queueport); - } - return; } -/* -************************************************************************** -************************************************************************** -*/ -static void arcmsr_post_pendingccb(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_post_pendingccb(struct ACB *pACB) { - struct _CCB *pCCB; + struct CCB *pCCB; while ((atomic_read(&pACB->ccbpendingcount) > 0) && (atomic_read(&pACB->ccboutstandingcount) < ARCMSR_MAX_OUTSTANDING_CMD)) { pCCB = arcmsr_get_pendingccb(pACB); - if (pCCB == NULL) { + if (!pCCB) break; - } arcmsr_post_ccb(pACB, pCCB); } - return; } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_post_Qbuffer(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_post_Qbuffer(struct ACB *pACB) { uint8_t *pQbuffer; - struct _QBUFFER *pwbuffer = - (struct _QBUFFER *)&pACB->pmu->ioctl_wbuffer; + struct QBUFFER *pwbuffer = + (struct QBUFFER *)&pACB->pmu->ioctl_wbuffer; uint8_t *iop_data = (uint8_t *) pwbuffer->data; int32_t allxfer_len = 0; @@ -1025,55 +933,47 @@ static void arcmsr_post_Qbuffer(struct _ pQbuffer = &pACB->wqbuffer[pACB->wqbuf_firstindex]; memcpy(iop_data, pQbuffer, 1); pACB->wqbuf_firstindex++; - pACB->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */ + /* if last index number set it to 0: */ + pACB->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; iop_data++; allxfer_len++; } pwbuffer->data_len = allxfer_len; /* - ** push inbound doorbell and wait reply at hwinterrupt routine for next Qbuffer post + * push inbound doorbell and wait reply at hwinterrupt + * routine for next Qbuffer post */ writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &pACB->pmu->inbound_doorbell); } - return; } -/* -************************************************************************ -************************************************************************ -*/ -static void arcmsr_stop_adapter_bgrb(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_stop_adapter_bgrb(struct ACB *pACB) { pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &pACB->pmu->inbound_msgaddr0); - if (arcmsr_wait_msgint_ready(pACB)) { + if (arcmsr_wait_msgint_ready(pACB)) printk ("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", pACB->adapter_index); - } - return; } -/* -************************************************************************ -************************************************************************ -*/ -static void arcmsr_free_ccb_pool(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_free_ccb_pool(struct ACB *pACB) { dma_free_coherent(&pACB->pPCI_DEV->dev, - ARCMSR_MAX_FREECCB_NUM * sizeof(struct _CCB) + 0x20, + ARCMSR_MAX_FREECCB_NUM * sizeof(struct CCB) + 0x20, pACB->dma_coherent, pACB->dma_coherent_handle); - return; } -/* -********************************************************************** -********************************************************************** -*/ -static irqreturn_t arcmsr_interrupt(struct _ACB *pACB) +/********************************************************************/ + +static irqreturn_t arcmsr_interrupt(struct ACB *pACB) { - struct _CCB *pCCB; + struct CCB *pCCB; uint32_t flag_ccb, outbound_intstatus, outbound_doorbell; outbound_intstatus = @@ -1083,8 +983,8 @@ static irqreturn_t arcmsr_interrupt(stru outbound_doorbell = readl(&pACB->pmu->outbound_doorbell); writel(outbound_doorbell, &pACB->pmu->outbound_doorbell); if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { - struct _QBUFFER *prbuffer = - (struct _QBUFFER *)&pACB->pmu->ioctl_rbuffer; + struct QBUFFER *prbuffer = + (struct QBUFFER *)&pACB->pmu->ioctl_rbuffer; uint8_t *iop_data = (uint8_t *) prbuffer->data; uint8_t *pQbuffer; int32_t my_empty_len, iop_len, rqbuf_firstindex, @@ -1110,17 +1010,15 @@ static irqreturn_t arcmsr_interrupt(stru } writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &pACB->pmu->inbound_doorbell); - } else { + } else pACB->acb_flags |= ACB_F_IOPDATA_OVERFLOW; - } } if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { pACB->acb_flags |= ACB_F_IOCTL_WQBUFFER_READED; if (pACB->wqbuf_firstindex != pACB->wqbuf_lastindex) { uint8_t *pQbuffer; - struct _QBUFFER *pwbuffer = - (struct _QBUFFER *)&pACB->pmu-> - ioctl_wbuffer; + struct QBUFFER *pwbuffer = + (struct QBUFFER *)&pACB->pmu-> ioctl_wbuffer; uint8_t *iop_data = (uint8_t *) pwbuffer->data; int32_t allxfer_len = 0; @@ -1143,26 +1041,25 @@ static irqreturn_t arcmsr_interrupt(stru writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &pACB->pmu->inbound_doorbell); } - if (pACB->wqbuf_firstindex == pACB->wqbuf_lastindex) { + if (pACB->wqbuf_firstindex == pACB->wqbuf_lastindex) pACB->acb_flags |= ACB_F_IOCTL_WQBUFFER_CLEARED; - } } } if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { int id, lun; /* - ***************************************************************************** + ********************************************************** ** areca cdb command done - ***************************************************************************** + ********************************************************** */ while (1) { if ((flag_ccb = readl(&pACB->pmu->outbound_queueport)) == - 0xFFFFFFFF) { - break; /*chip FIFO no ccb for completion already */ - } + 0xFFFFFFFF) + break; /* chip FIFO no ccb for completion already */ /* check if command done with no error */ - pCCB = (struct _CCB *)(pACB->vir2phy_offset + (flag_ccb << 5)); /*frame must be 32 bytes aligned */ + /* frame must be 32 bytes aligned */ + pCCB = (struct CCB *)(pACB->vir2phy_offset + (flag_ccb << 5)); if ((pCCB->pACB != pACB) || (pCCB->startdone != ARCMSR_CCB_START)) { if (pCCB->startdone == ARCMSR_CCB_ABORTED) { @@ -1181,70 +1078,61 @@ static irqreturn_t arcmsr_interrupt(stru id = pCCB->pcmd->device->id; lun = pCCB->pcmd->device->lun; if ((flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR) == 0) { - if (pACB->devstate[id][lun] == ARECA_RAID_GONE) { + if (pACB->devstate[id][lun] == ARECA_RAID_GONE) pACB->devstate[id][lun] = ARECA_RAID_GOOD; - } pCCB->pcmd->result = DID_OK << 16; arcmsr_ccb_complete(pCCB, 1); } else { switch (pCCB->arcmsr_cdb.DeviceStatus) { case ARCMSR_DEV_SELECT_TIMEOUT: - { - pACB->devstate[id][lun] = - ARECA_RAID_GONE; - pCCB->pcmd->result = - DID_TIME_OUT << 16; - arcmsr_ccb_complete(pCCB, 1); - } + pACB->devstate[id][lun] = + ARECA_RAID_GONE; + pCCB->pcmd->result = + DID_TIME_OUT << 16; + arcmsr_ccb_complete(pCCB, 1); break; case ARCMSR_DEV_ABORTED: case ARCMSR_DEV_INIT_FAIL: - { - pACB->devstate[id][lun] = - ARECA_RAID_GONE; - pCCB->pcmd->result = - DID_BAD_TARGET << 16; - arcmsr_ccb_complete(pCCB, 1); - } + pACB->devstate[id][lun] = + ARECA_RAID_GONE; + pCCB->pcmd->result = + DID_BAD_TARGET << 16; + arcmsr_ccb_complete(pCCB, 1); break; case SCSISTAT_CHECK_CONDITION: - { - pACB->devstate[id][lun] = - ARECA_RAID_GOOD; - arcmsr_report_sense_info(pCCB); - arcmsr_ccb_complete(pCCB, 1); - } + pACB->devstate[id][lun] = + ARECA_RAID_GOOD; + arcmsr_report_sense_info(pCCB); + arcmsr_ccb_complete(pCCB, 1); break; default: printk - ("arcmsr%d: scsi id=%d lun=%d isr get command error done, but got unknow DeviceStatus=0x%x \n", + ("arcmsr%d: scsi id=%d lun=%d isr get command error done, but got unknown DeviceStatus=0x%x \n", pACB->adapter_index, id, lun, pCCB->arcmsr_cdb.DeviceStatus); pACB->devstate[id][lun] = ARECA_RAID_GONE; - pCCB->pcmd->result = DID_NO_CONNECT << 16; /*unknow error or crc error just for retry */ + pCCB->pcmd->result = DID_NO_CONNECT << 16; /* unknown error or crc error just for retry */ arcmsr_ccb_complete(pCCB, 1); break; } } - } /*drain reply FIFO */ + } /* drain reply FIFO */ } if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) { - /*it must be share irq */ + /* it must be shared irq */ return IRQ_NONE; } - arcmsr_post_pendingccb(pACB); /*try to post all pending ccb */ + arcmsr_post_pendingccb(pACB); /* try to post all pending ccb */ return IRQ_HANDLED; } -/* -******************************************************************************* -******************************************************************************* -*/ -static void arcmsr_iop_parking(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_iop_parking(struct ACB *pACB) { - if (pACB != NULL) { + if (pACB) { /* stop adapter background rebuild */ if (pACB->acb_flags & ACB_F_MSG_START_BGRB) { pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; @@ -1254,13 +1142,11 @@ static void arcmsr_iop_parking(struct _A } } -/* -*********************************************************************** -************************************************************************ -*/ -static int arcmsr_iop_ioctlcmd(struct _ACB *pACB, int ioctl_cmd, void *arg) +/********************************************************************/ + +static int arcmsr_iop_ioctlcmd(struct ACB *pACB, int ioctl_cmd, void __user *arg) { - struct _CMD_IOCTL_FIELD *pcmdioctlfld; + struct CMD_IOCTL_FIELD *pcmdioctlfld; dma_addr_t cmd_handle; unsigned long flag; int retvalue = 0; @@ -1268,13 +1154,12 @@ static int arcmsr_iop_ioctlcmd(struct _A spin_lock_irqsave(&pACB->qbuffer_lock, flag); pcmdioctlfld = pci_alloc_consistent(pACB->pPCI_DEV, - sizeof(struct _CMD_IOCTL_FIELD), &cmd_handle); - if (pcmdioctlfld == NULL) { + sizeof(struct CMD_IOCTL_FIELD), &cmd_handle); + if (!pcmdioctlfld) { spin_unlock_irqrestore(&pACB->qbuffer_lock, flag); return -ENOMEM; } - if (copy_from_user(pcmdioctlfld, arg, sizeof(struct _CMD_IOCTL_FIELD)) - != 0) { + if (copy_from_user(pcmdioctlfld, arg, sizeof(struct CMD_IOCTL_FIELD))) { retvalue = -EFAULT; goto ioctl_out; } @@ -1284,330 +1169,299 @@ static int arcmsr_iop_ioctlcmd(struct _A } switch (ioctl_cmd) { case ARCMSR_IOCTL_READ_RQBUFFER: - { - unsigned long *ver_addr; - dma_addr_t buf_handle; - uint8_t *pQbuffer, *ptmpQbuffer; - int32_t allxfer_len = 0; - - ver_addr = - pci_alloc_consistent(pACB->pPCI_DEV, 1032, - &buf_handle); - if (ver_addr == NULL) { - retvalue = -ENOMEM; - goto ioctl_out; - } - ptmpQbuffer = (uint8_t *) ver_addr; - while ((pACB->rqbuf_firstindex != pACB->rqbuf_lastindex) - && (allxfer_len < 1031)) { - pQbuffer = - &pACB->rqbuffer[pACB->rqbuf_firstindex]; - memcpy(ptmpQbuffer, pQbuffer, 1); - pACB->rqbuf_firstindex++; - pACB->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; - ptmpQbuffer++; - allxfer_len++; - } - if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { - struct _QBUFFER *prbuffer = - (struct _QBUFFER *)&pACB->pmu-> - ioctl_rbuffer; - uint8_t *pQbuffer; - uint8_t *iop_data = (uint8_t *) prbuffer->data; - int32_t iop_len; + { + unsigned long *ver_addr; + dma_addr_t buf_handle; + uint8_t *pQbuffer, *ptmpQbuffer; + int32_t allxfer_len = 0; + + ver_addr = pci_alloc_consistent(pACB->pPCI_DEV, 1032, + &buf_handle); + if (!ver_addr) { + retvalue = -ENOMEM; + goto ioctl_out; + } + ptmpQbuffer = (uint8_t *) ver_addr; + while ((pACB->rqbuf_firstindex != pACB->rqbuf_lastindex) + && (allxfer_len < 1031)) { + pQbuffer = &pACB->rqbuffer[pACB->rqbuf_firstindex]; + memcpy(ptmpQbuffer, pQbuffer, 1); + pACB->rqbuf_firstindex++; + pACB->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; + ptmpQbuffer++; + allxfer_len++; + } + if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { + struct QBUFFER *prbuffer = + (struct QBUFFER *)&pACB->pmu->ioctl_rbuffer; + uint8_t *pQbuffer; + uint8_t *iop_data = (uint8_t *) prbuffer->data; + int32_t iop_len; - pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; - iop_len = (int32_t) prbuffer->data_len; - while (iop_len > 0) { + pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; + iop_len = (int32_t) prbuffer->data_len; + while (iop_len > 0) { + pQbuffer = + &pACB->rqbuffer[pACB-> + rqbuf_lastindex]; + memcpy(pQbuffer, iop_data, 1); + pACB->rqbuf_lastindex++; + pACB->rqbuf_lastindex %= + ARCMSR_MAX_QBUFFER; + iop_data++; + iop_len--; + } + writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, + &pACB->pmu->inbound_doorbell); + } + memcpy(pcmdioctlfld->ioctldatabuffer, + (uint8_t *) ver_addr, allxfer_len); + pcmdioctlfld->cmdioctl.Length = allxfer_len; + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_OK; + if (copy_to_user(arg, pcmdioctlfld, + sizeof(struct CMD_IOCTL_FIELD))) + retvalue = -EFAULT; + pci_free_consistent(pACB->pPCI_DEV, 1032, ver_addr, + buf_handle); + break; + } + case ARCMSR_IOCTL_WRITE_WQBUFFER: + { + unsigned long *ver_addr; + dma_addr_t buf_handle; + int32_t my_empty_len, user_len, wqbuf_firstindex, + wqbuf_lastindex; + uint8_t *pQbuffer, *ptmpuserbuffer; + + ver_addr = pci_alloc_consistent(pACB->pPCI_DEV, 1032, + &buf_handle); + if (!ver_addr) { + retvalue = -ENOMEM; + goto ioctl_out; + } + ptmpuserbuffer = (uint8_t *) ver_addr; + user_len = pcmdioctlfld->cmdioctl.Length; + memcpy(ptmpuserbuffer, pcmdioctlfld->ioctldatabuffer, + user_len); + wqbuf_lastindex = pACB->wqbuf_lastindex; + wqbuf_firstindex = pACB->wqbuf_firstindex; + if (wqbuf_lastindex != wqbuf_firstindex) { + arcmsr_post_Qbuffer(pACB); + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_ERROR; + } else { + my_empty_len = + (wqbuf_firstindex - wqbuf_lastindex - + 1) & (ARCMSR_MAX_QBUFFER - 1); + if (my_empty_len >= user_len) { + while (user_len > 0) { pQbuffer = - &pACB->rqbuffer[pACB-> - rqbuf_lastindex]; - memcpy(pQbuffer, iop_data, 1); - pACB->rqbuf_lastindex++; - pACB->rqbuf_lastindex %= + &pACB->wqbuffer[pACB-> + wqbuf_lastindex]; + memcpy(pQbuffer, ptmpuserbuffer, 1); + pACB->wqbuf_lastindex++; + pACB->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; - iop_data++; - iop_len--; + ptmpuserbuffer++; + user_len--; } - writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, - &pACB->pmu->inbound_doorbell); - } - memcpy(pcmdioctlfld->ioctldatabuffer, - (uint8_t *) ver_addr, allxfer_len); - pcmdioctlfld->cmdioctl.Length = allxfer_len; - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_OK; - if (copy_to_user - (arg, pcmdioctlfld, - sizeof(struct _CMD_IOCTL_FIELD)) != 0) { - retvalue = -EFAULT; - } - pci_free_consistent(pACB->pPCI_DEV, 1032, ver_addr, - buf_handle); - } - break; - case ARCMSR_IOCTL_WRITE_WQBUFFER: - { - unsigned long *ver_addr; - dma_addr_t buf_handle; - int32_t my_empty_len, user_len, wqbuf_firstindex, - wqbuf_lastindex; - uint8_t *pQbuffer, *ptmpuserbuffer; - - ver_addr = - pci_alloc_consistent(pACB->pPCI_DEV, 1032, - &buf_handle); - if (ver_addr == NULL) { - retvalue = -ENOMEM; - goto ioctl_out; - } - ptmpuserbuffer = (uint8_t *) ver_addr; - user_len = pcmdioctlfld->cmdioctl.Length; - memcpy(ptmpuserbuffer, pcmdioctlfld->ioctldatabuffer, - user_len); - wqbuf_lastindex = pACB->wqbuf_lastindex; - wqbuf_firstindex = pACB->wqbuf_firstindex; - if (wqbuf_lastindex != wqbuf_firstindex) { - arcmsr_post_Qbuffer(pACB); + if (pACB->acb_flags & + ACB_F_IOCTL_WQBUFFER_CLEARED) { + pACB->acb_flags &= + ~ACB_F_IOCTL_WQBUFFER_CLEARED; + arcmsr_post_Qbuffer(pACB); + } + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_OK; + } else pcmdioctlfld->cmdioctl.ReturnCode = ARCMSR_IOCTL_RETURNCODE_ERROR; - } else { - my_empty_len = - (wqbuf_firstindex - wqbuf_lastindex - - 1) & (ARCMSR_MAX_QBUFFER - 1); - if (my_empty_len >= user_len) { - while (user_len > 0) { - pQbuffer = - &pACB->wqbuffer[pACB-> - wqbuf_lastindex]; - memcpy(pQbuffer, ptmpuserbuffer, - 1); - pACB->wqbuf_lastindex++; - pACB->wqbuf_lastindex %= - ARCMSR_MAX_QBUFFER; - ptmpuserbuffer++; - user_len--; - } - if (pACB-> - acb_flags & - ACB_F_IOCTL_WQBUFFER_CLEARED) { - pACB->acb_flags &= - ~ACB_F_IOCTL_WQBUFFER_CLEARED; - arcmsr_post_Qbuffer(pACB); - } - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_OK; - } else { - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_ERROR; - } - } - if (copy_to_user - (arg, pcmdioctlfld, - sizeof(struct _CMD_IOCTL_FIELD)) != 0) { - retvalue = -EFAULT; - } - pci_free_consistent(pACB->pPCI_DEV, 1032, ver_addr, - buf_handle); } + if (copy_to_user(arg, pcmdioctlfld, + sizeof(struct CMD_IOCTL_FIELD))) + retvalue = -EFAULT; + pci_free_consistent(pACB->pPCI_DEV, 1032, ver_addr, + buf_handle); break; + } case ARCMSR_IOCTL_CLEAR_RQBUFFER: - { - uint8_t *pQbuffer = pACB->rqbuffer; + { + uint8_t *pQbuffer = pACB->rqbuffer; - if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { - pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; - writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, - &pACB->pmu->inbound_doorbell); - } - pACB->acb_flags |= ACB_F_IOCTL_RQBUFFER_CLEARED; - pACB->rqbuf_firstindex = 0; - pACB->rqbuf_lastindex = 0; - memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_OK; - if (copy_to_user - (arg, pcmdioctlfld, - sizeof(struct _CMD_IOCTL_FIELD)) != 0) { - retvalue = -EFAULT; - } - } + if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { + pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; + writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, + &pACB->pmu->inbound_doorbell); + } + pACB->acb_flags |= ACB_F_IOCTL_RQBUFFER_CLEARED; + pACB->rqbuf_firstindex = 0; + pACB->rqbuf_lastindex = 0; + memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_OK; + if (copy_to_user(arg, pcmdioctlfld, + sizeof(struct CMD_IOCTL_FIELD))) + retvalue = -EFAULT; break; + } case ARCMSR_IOCTL_CLEAR_WQBUFFER: - { - uint8_t *pQbuffer = pACB->wqbuffer; + { + uint8_t *pQbuffer = pACB->wqbuffer; - if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { - pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; - writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, - &pACB->pmu->inbound_doorbell); - } - pACB->acb_flags |= - (ACB_F_IOCTL_WQBUFFER_CLEARED | - ACB_F_IOCTL_WQBUFFER_READED); - pACB->wqbuf_firstindex = 0; - pACB->wqbuf_lastindex = 0; - memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_OK; - if (copy_to_user - (arg, pcmdioctlfld, - sizeof(struct _CMD_IOCTL_FIELD)) != 0) { - retvalue = -EFAULT; - } - } + if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { + pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; + writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, + &pACB->pmu->inbound_doorbell); + } + pACB->acb_flags |= + (ACB_F_IOCTL_WQBUFFER_CLEARED | + ACB_F_IOCTL_WQBUFFER_READED); + pACB->wqbuf_firstindex = 0; + pACB->wqbuf_lastindex = 0; + memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_OK; + if (copy_to_user(arg, pcmdioctlfld, + sizeof(struct CMD_IOCTL_FIELD))) + retvalue = -EFAULT; break; + } case ARCMSR_IOCTL_CLEAR_ALLQBUFFER: - { - uint8_t *pQbuffer; + { + uint8_t *pQbuffer; - if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { - pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; - writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, - &pACB->pmu->inbound_doorbell); - } - pACB->acb_flags |= - (ACB_F_IOCTL_WQBUFFER_CLEARED | - ACB_F_IOCTL_RQBUFFER_CLEARED | - ACB_F_IOCTL_WQBUFFER_READED); - pACB->rqbuf_firstindex = 0; - pACB->rqbuf_lastindex = 0; - pACB->wqbuf_firstindex = 0; - pACB->wqbuf_lastindex = 0; - pQbuffer = pACB->rqbuffer; - memset(pQbuffer, 0, sizeof(struct _QBUFFER)); - pQbuffer = pACB->wqbuffer; - memset(pQbuffer, 0, sizeof(struct _QBUFFER)); - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_OK; - if (copy_to_user - (arg, pcmdioctlfld, - sizeof(struct _CMD_IOCTL_FIELD)) != 0) { - retvalue = -EFAULT; - } - } + if (pACB->acb_flags & ACB_F_IOPDATA_OVERFLOW) { + pACB->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; + writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, + &pACB->pmu->inbound_doorbell); + } + pACB->acb_flags |= + (ACB_F_IOCTL_WQBUFFER_CLEARED | + ACB_F_IOCTL_RQBUFFER_CLEARED | + ACB_F_IOCTL_WQBUFFER_READED); + pACB->rqbuf_firstindex = 0; + pACB->rqbuf_lastindex = 0; + pACB->wqbuf_firstindex = 0; + pACB->wqbuf_lastindex = 0; + pQbuffer = pACB->rqbuffer; + memset(pQbuffer, 0, sizeof(struct QBUFFER)); + pQbuffer = pACB->wqbuffer; + memset(pQbuffer, 0, sizeof(struct QBUFFER)); + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_OK; + if (copy_to_user(arg, pcmdioctlfld, + sizeof(struct CMD_IOCTL_FIELD))) + retvalue = -EFAULT; break; + } case ARCMSR_IOCTL_RETURN_CODE_3F: - { - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_3F; - if (copy_to_user - (arg, pcmdioctlfld, - sizeof(struct _CMD_IOCTL_FIELD)) != 0) { - retvalue = -EFAULT; - } - } + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_3F; + if (copy_to_user(arg, pcmdioctlfld, + sizeof(struct CMD_IOCTL_FIELD))) + retvalue = -EFAULT; break; case ARCMSR_IOCTL_SAY_HELLO: - { - int8_t *hello_string = "Hello! I am ARCMSR"; + { + int8_t *hello_string = "Hello! I am ARCMSR"; - memcpy(pcmdioctlfld->ioctldatabuffer, hello_string, - (int16_t) strlen(hello_string)); - pcmdioctlfld->cmdioctl.ReturnCode = - ARCMSR_IOCTL_RETURNCODE_OK; - if (copy_to_user - (arg, pcmdioctlfld, - sizeof(struct _CMD_IOCTL_FIELD)) != 0) { - retvalue = -EFAULT; - } - } + memcpy(pcmdioctlfld->ioctldatabuffer, hello_string, + (int16_t) strlen(hello_string)); + pcmdioctlfld->cmdioctl.ReturnCode = + ARCMSR_IOCTL_RETURNCODE_OK; + if (copy_to_user(arg, pcmdioctlfld, + sizeof(struct CMD_IOCTL_FIELD))) + retvalue = -EFAULT; break; + } case ARCMSR_IOCTL_SAY_GOODBYE: - { - arcmsr_iop_parking(pACB); - } + arcmsr_iop_parking(pACB); break; case ARCMSR_IOCTL_FLUSH_ADAPTER_CACHE: - { - arcmsr_flush_adapter_cache(pACB); - } + arcmsr_flush_adapter_cache(pACB); break; default: retvalue = -EFAULT; } - ioctl_out: - pci_free_consistent(pACB->pPCI_DEV, sizeof(struct _CMD_IOCTL_FIELD), +ioctl_out: + pci_free_consistent(pACB->pPCI_DEV, sizeof(struct CMD_IOCTL_FIELD), pcmdioctlfld, cmd_handle); spin_unlock_irqrestore(&pACB->qbuffer_lock, flag); return retvalue; } -/* -************************************************************************ -************************************************************************ -*/ -static int arcmsr_ioctl(struct scsi_device *dev, int ioctl_cmd, void *arg) +/********************************************************************/ + +static int arcmsr_ioctl(struct scsi_device *dev, int ioctl_cmd, void __user *arg) { - struct _ACB *pACB; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; int32_t match = 0x55AA, i; for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { - if ((pACB = pHCBARC->pACB[i]) != NULL) { + if ((pACB = pHCBARC->pACB[i])) { if (pACB->host == dev->host) { match = i; break; } } } - if (match == 0x55AA) { + if (match == 0x55AA) return -ENXIO; - } - if (!arg) { + if (!arg) return -EINVAL; - } - return (arcmsr_iop_ioctlcmd(pACB, ioctl_cmd, arg)); + + return arcmsr_iop_ioctlcmd(pACB, ioctl_cmd, arg); } -/* -************************************************************************** -************************************************************************** -*/ -static struct _CCB *arcmsr_get_freeccb(struct _ACB *pACB) +/********************************************************************/ + +static struct CCB *arcmsr_get_freeccb(struct ACB *pACB) { unsigned long flags; struct list_head *head = &pACB->ccb_free_list; - struct _CCB *pCCB = NULL; + struct CCB *pCCB = NULL; spin_lock_irqsave(&pACB->working_list_lock, flags); if (!list_empty(head)) { - pCCB = list_entry(head->next, struct _CCB, list); + pCCB = list_entry(head->next, struct CCB, list); list_del(head->next); } spin_unlock_irqrestore(&pACB->working_list_lock, flags); - return (pCCB); + return pCCB; } -/* -*********************************************************************** -*********************************************************************** -*/ +/********************************************************************/ + static int arcmsr_queue_command(struct scsi_cmnd *cmd, void (*done) (struct scsi_cmnd *)) { struct Scsi_Host *host = cmd->device->host; - struct _ACB *pACB = (struct _ACB *)host->hostdata; - struct _CCB *pCCB; + struct ACB *pACB = (struct ACB *)host->hostdata; + struct CCB *pCCB; int target = cmd->device->id; int lun = cmd->device->lun; cmd->scsi_done = done; cmd->host_scribble = NULL; cmd->result = 0; - if (cmd->cmnd[0] == SYNCHRONIZE_CACHE) { /* 0x35 avoid synchronizing disk cache cmd after .remove : arcmsr_device_remove (linux bug) */ - if (pACB->devstate[target][lun] == ARECA_RAID_GONE) { + if (cmd->cmnd[0] == SYNCHRONIZE_CACHE) { + /* + * 0x35 avoid synchronizing disk cache cmd after .remove: + * arcmsr_device_remove (linux bug) + */ + if (pACB->devstate[target][lun] == ARECA_RAID_GONE) cmd->result = (DID_NO_CONNECT << 16); - } cmd->scsi_done(cmd); - return (0); + return 0; } if (pACB->acb_flags & ACB_F_BUS_RESET) { printk("arcmsr%d: bus reset and return busy \n", pACB->adapter_index); cmd->result = (DID_BUS_BUSY << 16); cmd->scsi_done(cmd); - return (0); + return 0; } if (pACB->devstate[target][lun] == ARECA_RAID_GONE) { uint8_t block_cmd; @@ -1619,19 +1473,19 @@ static int arcmsr_queue_command(struct s pACB->adapter_index, cmd->cmnd[0], target, lun); cmd->result = (DID_NO_CONNECT << 16); cmd->scsi_done(cmd); - return (0); + return 0; } } arcmsr_post_pendingccb(pACB); - if ((pCCB = arcmsr_get_freeccb(pACB)) != NULL) { + if ((pCCB = arcmsr_get_freeccb(pACB))) { arcmsr_build_ccb(pACB, pCCB, cmd); if (atomic_read(&pACB->ccboutstandingcount) < ARCMSR_MAX_OUTSTANDING_CMD) { arcmsr_post_ccb(pACB, pCCB); - return (0); + return 0; } arcmsr_queue_pendingccb(pACB, pCCB); - return (0); + return 0; } printk ("arcmsr%d: 'out of ccbs resource' ccb outstanding=%d pending=%d \n", @@ -1639,19 +1493,17 @@ static int arcmsr_queue_command(struct s atomic_read(&pACB->ccbpendingcount)); cmd->result = (DID_BUS_BUSY << 16); cmd->scsi_done(cmd); - return (0); + return 0; } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_get_firmware_spec(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_get_firmware_spec(struct ACB *pACB) { char *acb_firm_model = pACB->firm_model; char *acb_firm_version = pACB->firm_version; - char *iop_firm_model = (char *)(&pACB->pmu->message_rwbuffer[15]); /*firm_model,15,60-67 */ - char *iop_firm_version = (char *)(&pACB->pmu->message_rwbuffer[17]); /*firm_version,17,68-83 */ + char *iop_firm_model = (char *)(&pACB->pmu->message_rwbuffer[15]); /* firm_model,15,60-67 */ + char *iop_firm_version = (char *)(&pACB->pmu->message_rwbuffer[17]); /* firm_version,17,68-83 */ int count; writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &pACB->pmu->inbound_msgaddr0); @@ -1676,59 +1528,57 @@ static void arcmsr_get_firmware_spec(str } printk("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", pACB->adapter_index, pACB->firm_version); - pACB->firm_request_len = readl(&pACB->pmu->message_rwbuffer[1]); /*firm_request_len,1,04-07 */ - pACB->firm_numbers_queue = readl(&pACB->pmu->message_rwbuffer[2]); /*firm_numbers_queue,2,08-11 */ - pACB->firm_sdram_size = readl(&pACB->pmu->message_rwbuffer[3]); /*firm_sdram_size,3,12-15 */ - pACB->firm_ide_channels = readl(&pACB->pmu->message_rwbuffer[4]); /*firm_ide_channels,4,16-19 */ - return; + /* firm_request_len,1,04-07 */ + pACB->firm_request_len = readl(&pACB->pmu->message_rwbuffer[1]); + /* firm_numbers_queue,2,08-11 */ + pACB->firm_numbers_queue = readl(&pACB->pmu->message_rwbuffer[2]); + /* firm_sdram_size,3,12-15 */ + pACB->firm_sdram_size = readl(&pACB->pmu->message_rwbuffer[3]); + /* firm_ide_channels,4,16-19 */ + pACB->firm_ide_channels = readl(&pACB->pmu->message_rwbuffer[4]); } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_start_adapter_bgrb(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_start_adapter_bgrb(struct ACB *pACB) { pACB->acb_flags |= ACB_F_MSG_START_BGRB; writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pACB->pmu->inbound_msgaddr0); - if (arcmsr_wait_msgint_ready(pACB)) { + if (arcmsr_wait_msgint_ready(pACB)) printk ("arcmsr%d: wait 'start adapter background rebulid' timeout \n", pACB->adapter_index); - } - return; } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_polling_ccbdone(struct _ACB *pACB, struct _CCB *poll_ccb) +/********************************************************************/ + +static void arcmsr_polling_ccbdone(struct ACB *pACB, struct CCB *poll_ccb) { - struct _CCB *pCCB; - uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = - 0; + struct CCB *pCCB; + uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, + poll_count = 0; int id, lun; - polling_ccb_retry: +polling_ccb_retry: poll_count++; outbound_intstatus = readl(&pACB->pmu->outbound_intstatus) & pACB->outbound_int_enable; - writel(outbound_intstatus, &pACB->pmu->outbound_intstatus); /*clear interrupt */ + /* clear interrupt: */ + writel(outbound_intstatus, &pACB->pmu->outbound_intstatus); while (1) { if ((flag_ccb = readl(&pACB->pmu->outbound_queueport)) == 0xFFFFFFFF) { - if (poll_ccb_done) { - break; /*chip FIFO no ccb for completion already */ - } else { + if (poll_ccb_done) + break; /* chip FIFO no ccb for completion already */ + else { msleep(25); - if (poll_count > 100) { + if (poll_count > 100) break; - } goto polling_ccb_retry; } } - pCCB = (struct _CCB *)(pACB->vir2phy_offset + (flag_ccb << 5)); /*frame must be 32 bytes aligned */ + /* frame must be 32 bytes aligned: */ + pCCB = (struct CCB *)(pACB->vir2phy_offset + (flag_ccb << 5)); if ((pCCB->pACB != pACB) || (pCCB->startdone != ARCMSR_CCB_START)) { if ((pCCB->startdone == ARCMSR_CCB_ABORTED) @@ -1752,59 +1602,45 @@ static void arcmsr_polling_ccbdone(struc id = pCCB->pcmd->device->id; lun = pCCB->pcmd->device->lun; if ((flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR) == 0) { - if (pACB->devstate[id][lun] == ARECA_RAID_GONE) { + if (pACB->devstate[id][lun] == ARECA_RAID_GONE) pACB->devstate[id][lun] = ARECA_RAID_GOOD; - } pCCB->pcmd->result = DID_OK << 16; arcmsr_ccb_complete(pCCB, 1); } else { switch (pCCB->arcmsr_cdb.DeviceStatus) { case ARCMSR_DEV_SELECT_TIMEOUT: - { - pACB->devstate[id][lun] = - ARECA_RAID_GONE; - pCCB->pcmd->result = DID_TIME_OUT << 16; - arcmsr_ccb_complete(pCCB, 1); - } + pACB->devstate[id][lun] = ARECA_RAID_GONE; + pCCB->pcmd->result = DID_TIME_OUT << 16; + arcmsr_ccb_complete(pCCB, 1); break; case ARCMSR_DEV_ABORTED: case ARCMSR_DEV_INIT_FAIL: - { - pACB->devstate[id][lun] = - ARECA_RAID_GONE; - pCCB->pcmd->result = - DID_BAD_TARGET << 16; - arcmsr_ccb_complete(pCCB, 1); - } + pACB->devstate[id][lun] = ARECA_RAID_GONE; + pCCB->pcmd->result = DID_BAD_TARGET << 16; + arcmsr_ccb_complete(pCCB, 1); break; case SCSISTAT_CHECK_CONDITION: - { - pACB->devstate[id][lun] = - ARECA_RAID_GOOD; - arcmsr_report_sense_info(pCCB); - arcmsr_ccb_complete(pCCB, 1); - } + pACB->devstate[id][lun] = ARECA_RAID_GOOD; + arcmsr_report_sense_info(pCCB); + arcmsr_ccb_complete(pCCB, 1); break; default: printk - ("arcmsr%d: scsi id=%d lun=%d polling and getting command error done, but got unknow DeviceStatus=0x%x \n", + ("arcmsr%d: scsi id=%d lun=%d polling and getting command error done, but got unknown DeviceStatus=0x%x \n", pACB->adapter_index, id, lun, pCCB->arcmsr_cdb.DeviceStatus); pACB->devstate[id][lun] = ARECA_RAID_GONE; - pCCB->pcmd->result = DID_BAD_TARGET << 16; /*unknow error or crc error just for retry */ + pCCB->pcmd->result = DID_BAD_TARGET << 16; /* unknown error or crc error just for retry */ arcmsr_ccb_complete(pCCB, 1); break; } } } - return; } -/* -********************************************************************** -********************************************************************** -*/ -static void arcmsr_iop_init(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_iop_init(struct ACB *pACB) { uint32_t intmask_org, mask, outbound_doorbell, firmware_state = 0; @@ -1817,28 +1653,25 @@ static void arcmsr_iop_init(struct _ACB arcmsr_get_firmware_spec(pACB); arcmsr_start_adapter_bgrb(pACB); outbound_doorbell = readl(&pACB->pmu->outbound_doorbell); - writel(outbound_doorbell, &pACB->pmu->outbound_doorbell); /*clear interrupt */ + /* clear interrupt: */ + writel(outbound_doorbell, &pACB->pmu->outbound_doorbell); writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &pACB->pmu->inbound_doorbell); - mask = - ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | + mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE); writel(intmask_org & mask, &pACB->pmu->outbound_intmask); pACB->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; pACB->acb_flags |= ACB_F_IOP_INITED; - return; } -/* -**************************************************************************** -**************************************************************************** -*/ +/********************************************************************/ + static int arcmsr_bus_reset(struct scsi_cmnd *cmd) { - struct _ACB *pACB; + struct ACB *pACB; int retry = 0; - pACB = (struct _ACB *)cmd->device->host->hostdata; + pACB = (struct ACB *)cmd->device->host->hostdata; printk("arcmsr%d: bus reset ..... \n", pACB->adapter_index); pACB->num_resets++; pACB->acb_flags |= ACB_F_BUS_RESET; @@ -1849,29 +1682,28 @@ static int arcmsr_bus_reset(struct scsi_ } arcmsr_iop_reset(pACB); pACB->acb_flags &= ~ACB_F_BUS_RESET; - return (SUCCESS); + return SUCCESS; } -/* -***************************************************************************************** -***************************************************************************************** -*/ +/********************************************************************/ + static int arcmsr_seek_cmd2abort(struct scsi_cmnd *abortcmd) { - struct _ACB *pACB = (struct _ACB *)abortcmd->device->host->hostdata; - struct _CCB *pCCB; + struct ACB *pACB = (struct ACB *)abortcmd->device->host->hostdata; + struct CCB *pCCB; uint32_t intmask_org, mask; int i = 0, pendingcount; pACB->num_aborts++; /* - ***************************************************************************** - ** It is the upper layer do abort command this lock just prior to calling us. + ****************************************************************** + ** It is the upper layer do abort command this lock just prior to + ** calling us. ** First determine if we currently own this command. ** Start by searching the device queue. If not found - ** at all,and the system wanted us to just abort the + ** at all, and the system wanted us to just abort the ** command return success. - ***************************************************************************** + ****************************************************************** */ if (atomic_read(&pACB->ccboutstandingcount) != 0) { for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { @@ -1892,16 +1724,15 @@ static int arcmsr_seek_cmd2abort(struct /* ********************************************************** ** seek this command at our command list - ** if command found then remove,abort it and free this CCB + ** if command found then remove, abort it and free this CCB ********************************************************** */ pendingcount = atomic_read(&pACB->ccbpendingcount); if (pendingcount > 0) { do { pCCB = arcmsr_get_pendingccb(pACB); - if (pCCB == NULL) { + if (!pCCB) break; - } if (pCCB->pcmd == abortcmd) { printk ("arcmsr%d: scsi id=%d lun=%d abort ccb '0x%p' pending command \n", @@ -1910,35 +1741,32 @@ static int arcmsr_seek_cmd2abort(struct pCCB->startdone = ARCMSR_CCB_ABORTED; pCCB->pcmd->result = DID_ABORT << 16; arcmsr_ccb_complete(pCCB, 0); - return (SUCCESS); - } else { + return SUCCESS; + } else arcmsr_queue_pendingccb(pACB, pCCB); - } } while (pendingcount--); } - return (SUCCESS); - abort_outstanding_cmd: - msleep_interruptible(3000); /*wait for 3 sec for all command done */ + return SUCCESS; + +abort_outstanding_cmd: + msleep_interruptible(3000); /* wait for 3 sec for all command done */ /* disable all outbound interrupt */ intmask_org = readl(&pACB->pmu->outbound_intmask); writel(intmask_org | ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, &pACB->pmu->outbound_intmask); arcmsr_polling_ccbdone(pACB, pCCB); /* enable all outbound interrupt */ - mask = - ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | - ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE); + mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | + ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE); writel(intmask_org & mask, &pACB->pmu->outbound_intmask); - return (SUCCESS); + return SUCCESS; } -/* -***************************************************************************************** -***************************************************************************************** -*/ +/********************************************************************/ + static int arcmsr_cmd_abort(struct scsi_cmnd *cmd) { - struct _ACB *pACB = (struct _ACB *)cmd->device->host->hostdata; + struct ACB *pACB = (struct ACB *)cmd->device->host->hostdata; int error; printk("arcmsr%d: abort device command of scsi id=%d lun=%d \n", @@ -1950,121 +1778,95 @@ static int arcmsr_cmd_abort(struct scsi_ ************************************************ */ error = arcmsr_seek_cmd2abort(cmd); - if (error != SUCCESS) { + if (error != SUCCESS) printk("arcmsr%d: abort command failed scsi id=%d lun=%d \n", pACB->adapter_index, cmd->device->id, cmd->device->lun); - } - return (error); + return error; } -/* -********************************************************************* -********************************************************************* -*/ +/********************************************************************/ + static const char *arcmsr_info(struct Scsi_Host *host) { static char buf[256]; - struct _ACB *pACB; + struct ACB *pACB; uint16_t device_id; - pACB = (struct _ACB *)host->hostdata; + pACB = (struct ACB *)host->hostdata; device_id = pACB->pPCI_DEV->device; + switch (device_id) { case PCIDeviceIDARC1110: - { - sprintf(buf, - "ARECA ARC1110 PCI-X 4 PORTS SATA RAID CONTROLLER\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1110 PCI-X 4 PORTS SATA RAID CONTROLLER\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1120: - { - sprintf(buf, - "ARECA ARC1120 PCI-X 8 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1120 PCI-X 8 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1130: - { - sprintf(buf, - "ARECA ARC1130 PCI-X 12 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1130 PCI-X 12 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1160: - { - sprintf(buf, - "ARECA ARC1160 PCI-X 16 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1160 PCI-X 16 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1170: - { - sprintf(buf, - "ARECA ARC1170 PCI-X 24 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1170 PCI-X 24 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1210: - { - sprintf(buf, - "ARECA ARC1210 PCI-EXPRESS 4 PORTS SATA RAID CONTROLLER\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1210 PCI-EXPRESS 4 PORTS SATA RAID CONTROLLER\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1220: - { - sprintf(buf, - "ARECA ARC1220 PCI-EXPRESS 8 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1220 PCI-EXPRESS 8 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1230: - { - sprintf(buf, - "ARECA ARC1230 PCI-EXPRESS 12 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1230 PCI-EXPRESS 12 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1260: - { - sprintf(buf, - "ARECA ARC1260 PCI-EXPRESS 16 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1260 PCI-EXPRESS 16 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; case PCIDeviceIDARC1270: - { - sprintf(buf, - "ARECA ARC1270 PCI-EXPRESS 24 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA ARC1270 PCI-EXPRESS 24 PORTS SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; default: - { - sprintf(buf, - "ARECA SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", - ARCMSR_DRIVER_VERSION); - break; - } + sprintf(buf, + "ARECA SATA RAID CONTROLLER (RAID6-ENGINE Inside)\n %s", + ARCMSR_DRIVER_VERSION); + break; } return buf; } -/* -************************************************************************ -************************************************************************ -*/ -static int arcmsr_initialize(struct _ACB *pACB, struct pci_dev *pPCI_DEV) +/********************************************************************/ + +static int arcmsr_initialize(struct ACB *pACB, struct pci_dev *pPCI_DEV) { uint32_t intmask_org, ccb_phyaddr_hi32; dma_addr_t dma_coherent_handle, dma_addr; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; uint8_t pcicmd; void *dma_coherent; void *page_remapped; int i, j; - struct _CCB *pccb_tmp; + struct CCB *pccb_tmp; pci_read_config_byte(pPCI_DEV, PCI_COMMAND, &pcicmd); pci_write_config_byte(pPCI_DEV, PCI_COMMAND, @@ -2073,12 +1875,12 @@ static int arcmsr_initialize(struct _ACB page_remapped = ioremap(pci_resource_start(pPCI_DEV, 0), pci_resource_len(pPCI_DEV, 0)); - if (page_remapped == NULL) { + if (!page_remapped) { printk("arcmsr%d: memory mapping region fail \n", arcmsr_adapterCnt); - return (ENXIO); + return -ENXIO; } - pACB->pmu = (struct _MU *)(page_remapped); + pACB->pmu = (struct MU *)(page_remapped); pACB->acb_flags |= (ACB_F_IOCTL_WQBUFFER_CLEARED | ACB_F_IOCTL_RQBUFFER_CLEARED | ACB_F_IOCTL_WQBUFFER_READED); @@ -2088,9 +1890,9 @@ static int arcmsr_initialize(struct _ACB INIT_LIST_HEAD(&pACB->ccb_pending_list); dma_coherent = dma_alloc_coherent(&pPCI_DEV->dev, - ARCMSR_MAX_FREECCB_NUM * sizeof(struct _CCB) + + ARCMSR_MAX_FREECCB_NUM * sizeof(struct CCB) + 0x20, &dma_coherent_handle, GFP_KERNEL); - if (dma_coherent == NULL) { + if (!dma_coherent) { printk("arcmsr%d: dma_alloc_coherent got error \n", arcmsr_adapterCnt); return -ENOMEM; @@ -2098,24 +1900,23 @@ static int arcmsr_initialize(struct _ACB pACB->dma_coherent = dma_coherent; pACB->dma_coherent_handle = dma_coherent_handle; memset(dma_coherent, 0, - ARCMSR_MAX_FREECCB_NUM * sizeof(struct _CCB) + 0x20); - if (((unsigned long)dma_coherent & 0x1F) != 0) { /*ccb address must 32 (0x20) boundary */ - dma_coherent = - dma_coherent + (0x20 - + ARCMSR_MAX_FREECCB_NUM * sizeof(struct CCB) + 0x20); + if (((unsigned long)dma_coherent & 0x1F) != 0) { + /* ccb address must 32 (0x20) boundary */ + dma_coherent = dma_coherent + (0x20 - ((unsigned long)dma_coherent & 0x1F)); - dma_coherent_handle = - dma_coherent_handle + (0x20 - - ((unsigned long)dma_coherent_handle & - 0x1F)); + dma_coherent_handle = dma_coherent_handle + (0x20 - + ((unsigned long)dma_coherent_handle & + 0x1F)); } dma_addr = dma_coherent_handle; - pccb_tmp = (struct _CCB *)dma_coherent; + pccb_tmp = (struct CCB *)dma_coherent; for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { pccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5; pccb_tmp->pACB = pACB; pACB->pccb_pool[i] = pccb_tmp; list_add_tail(&pccb_tmp->list, &pACB->ccb_free_list); - dma_addr = dma_addr + sizeof(struct _CCB); + dma_addr = dma_addr + sizeof(struct CCB); pccb_tmp++; } pACB->vir2phy_offset = @@ -2150,27 +1951,23 @@ static int arcmsr_initialize(struct _ACB writel(intmask_org | ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, &pACB->pmu->outbound_intmask); arcmsr_adapterCnt++; - return (0); + return 0; } -/* -********************************************************************* -********************************************************************* -*/ +/********************************************************************/ + static int arcmsr_set_info(char *buffer, int length) { - return (0); + return 0; } -/* -********************************************************************* -********************************************************************* -*/ -static void arcmsr_pcidev_disattach(struct _ACB *pACB) +/********************************************************************/ + +static void arcmsr_pcidev_disattach(struct ACB *pACB) { struct pci_dev *pPCI_DEV; - struct _CCB *pCCB; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct CCB *pCCB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; struct Scsi_Host *host; uint32_t intmask_org; int i = 0, poll_count = 0, have_msi = 0; @@ -2206,18 +2003,17 @@ static void arcmsr_pcidev_disattach(stru } while (atomic_read(&pACB->ccbpendingcount) != 0) { pCCB = arcmsr_get_pendingccb(pACB); - if (pCCB != NULL) { + if (pCCB) { pCCB->startdone = ARCMSR_CCB_ABORTED; pCCB->pcmd->result = DID_ABORT << 16; arcmsr_ccb_complete(pCCB, 0); atomic_dec(&pACB->ccbpendingcount); - } else { + } else break; - } } - if ((pACB->acb_flags & ACB_F_HAVE_MSI) != 0) { + if ((pACB->acb_flags & ACB_F_HAVE_MSI) != 0) have_msi = 1; - } + host = pACB->host; pPCI_DEV = pACB->pPCI_DEV; iounmap(pACB->pmu); @@ -2227,36 +2023,31 @@ static void arcmsr_pcidev_disattach(stru scsi_host_put(host); free_irq(pPCI_DEV->irq, pACB); #ifdef CONFIG_PCI_MSI - if (have_msi == 1) { + if (have_msi == 1) pci_disable_msi(pPCI_DEV); - } #endif pci_release_regions(pPCI_DEV); pci_disable_device(pPCI_DEV); pci_set_drvdata(pPCI_DEV, NULL); - return; } -/* -*************************************************************** -*************************************************************** -*/ +/********************************************************************/ + static int arcmsr_halt_notify(struct notifier_block *nb, unsigned long event, void *buf) { - struct _ACB *pACB; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; int i; if ((event != SYS_RESTART) && (event != SYS_HALT) - && (event != SYS_POWER_OFF)) { + && (event != SYS_POWER_OFF)) return NOTIFY_DONE; - } + for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { pACB = pHCBARC->pACB[i]; - if (pACB == NULL) { + if (!pACB) continue; - } arcmsr_pcidev_disattach(pACB); } unregister_chrdev(pHCBARC->arcmsr_major_number, "arcmsr"); @@ -2264,10 +2055,8 @@ static int arcmsr_halt_notify(struct not return NOTIFY_OK; } -/* -********************************************************************* -********************************************************************* -*/ +/********************************************************************/ + #undef SPRINTF #define SPRINTF(args...) pos +=sprintf(pos,## args) #define YESNO(YN)\ @@ -2278,16 +2067,16 @@ static int arcmsr_proc_info(struct Scsi_ off_t offset, int length, int inout) { uint8_t i; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; char *pos = buffer; - struct _ACB *pACB; + struct ACB *pACB; + + if (inout) + return arcmsr_set_info(buffer, length); - if (inout) { - return (arcmsr_set_info(buffer, length)); - } for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { pACB = pHCBARC->pACB[i]; - if (pACB == NULL) + if (!pACB) continue; SPRINTF("ARECA SATA RAID Mass Storage Host Adadpter \n"); SPRINTF("Driver Version %s ", ARCMSR_DRIVER_VERSION); @@ -2295,47 +2084,40 @@ static int arcmsr_proc_info(struct Scsi_ SPRINTF("===========================\n"); } *start = buffer + offset; - if (pos - buffer < offset) { + if (pos - buffer < offset) return 0; - } else if (pos - buffer - offset < length) { - return (pos - buffer - offset); - } else { - return length; - } + else if (pos - buffer - offset < length) + return pos - buffer - offset; + return length; } -/* -************************************************************************ -************************************************************************ -*/ +/********************************************************************/ + static int arcmsr_release(struct Scsi_Host *host) { - struct _ACB *pACB; - struct _HCBARC *pHCBARC = &arcmsr_host_control_block; + struct ACB *pACB; + struct HCBARC *pHCBARC = &arcmsr_host_control_block; uint8_t match = 0xff, i; - if (host == NULL) { + if (!host) return -ENXIO; - } - pACB = (struct _ACB *)host->hostdata; - if (pACB == NULL) { + pACB = (struct ACB *)host->hostdata; + if (!pACB) return -ENXIO; - } + for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { - if (pHCBARC->pACB[i] == pACB) { + if (pHCBARC->pACB[i] == pACB) match = i; - } } - if (match == 0xff) { + if (match == 0xff) return -ENXIO; - } + arcmsr_pcidev_disattach(pACB); for (i = 0; i < ARCMSR_MAX_ADAPTER; i++) { - if (pHCBARC->pACB[i] != NULL) { - return (0); - } + if (pHCBARC->pACB[i]) + return 0; } unregister_chrdev(pHCBARC->arcmsr_major_number, "arcmsr"); unregister_reboot_notifier(&arcmsr_event_notifier); - return (0); + return 0; } diff -puN drivers/scsi/arcmsr/arcmsr.h~areca-raid-driver-arcmsr-cleanups drivers/scsi/arcmsr/arcmsr.h --- devel/drivers/scsi/arcmsr/arcmsr.h~areca-raid-driver-arcmsr-cleanups 2006-01-07 00:16:26.000000000 -0800 +++ devel-akpm/drivers/scsi/arcmsr/arcmsr.h 2006-01-07 00:16:26.000000000 -0800 @@ -1,11 +1,11 @@ /* -*********************************************************************************************** +*************************************************************************** ** O.S : Linux ** FILE NAME : arcmsr.h ** BY : Erich Chen ** Description: SCSI RAID Device Driver for ** ARECA RAID Host adapter -*********************************************************************************************** +*************************************************************************** ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. ** ** Web site: www.areca.com.tw @@ -19,96 +19,86 @@ ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ** GNU General Public License for more details. ************************************************************************ -** Redistribution and use in source and binary forms,with or without -** modification,are permitted provided that the following conditions +** Redistribution and use in source and binary forms, with or without +** modification, are permitted provided that the following conditions ** are met: ** 1. Redistributions of source code must retain the above copyright -** notice,this list of conditions and the following disclaimer. +** notice, this list of conditions and the following disclaimer. ** 2. Redistributions in binary form must reproduce the above copyright -** notice,this list of conditions and the following disclaimer in the +** notice, this list of conditions and the following disclaimer in the ** documentation and/or other materials provided with the distribution. ** 3. The name of the author may not be used to endorse or promote products ** derived from this software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, -** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT -** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY -** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT +** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT +** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY +** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF -** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ************************************************************************** */ -#include -#include -/* -********************************************************************************** -********************************************************************************** -*/ -#define ARCMSR_MAX_OUTSTANDING_CMD 256 -#define ARCMSR_MAX_PENDING_CMD 64 -#define ARCMSR_MAX_FREECCB_NUM 320 -#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.13" -#define ARCMSR_SCSI_INITIATOR_ID 255 -#define ARCMSR_DEV_SECTOR_SIZE 512 -#define ARCMSR_MAX_XFER_SECTORS 256 -#define ARCMSR_MAX_XFER_LEN ARCMSR_MAX_XFER_SECTORS * ARCMSR_DEV_SECTOR_SIZE /* 128k */ -#define ARCMSR_MAX_TARGETID 16 /* 16 max target id + 1 */ -#define ARCMSR_MAX_TARGETLUN 8 /* 8 */ -#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_FREECCB_NUM -#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ -#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38 */ -#define ARCMSR_MAX_ADAPTER 4 -/* -********************************************************************************** -********************************************************************************** -*/ -#define PCIVendorIDARECA 0x17D3 /* Vendor ID */ -#define PCIDeviceIDARC1110 0x1110 /* Device ID */ -#define PCIDeviceIDARC1120 0x1120 /* Device ID */ -#define PCIDeviceIDARC1130 0x1130 /* Device ID */ -#define PCIDeviceIDARC1160 0x1160 /* Device ID */ -#define PCIDeviceIDARC1170 0x1170 /* Device ID */ -#define PCIDeviceIDARC1210 0x1210 /* Device ID */ -#define PCIDeviceIDARC1220 0x1220 /* Device ID */ -#define PCIDeviceIDARC1230 0x1230 /* Device ID */ -#define PCIDeviceIDARC1260 0x1260 /* Device ID */ -#define PCIDeviceIDARC1270 0x1270 /* Device ID */ -/* -********************************************************************************** -********************************************************************************** -*/ -#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) -#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) - -#ifndef DMA_64BIT_MASK -#define DMA_64BIT_MASK 0xffffffffffffffffULL -#define DMA_32BIT_MASK 0x00000000ffffffffULL -#endif + +/********************************************************************/ + +#define ARCMSR_MAX_OUTSTANDING_CMD 256 +#define ARCMSR_MAX_PENDING_CMD 64 +#define ARCMSR_MAX_FREECCB_NUM 320 +#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.13" +#define ARCMSR_SCSI_INITIATOR_ID 255 +#define ARCMSR_DEV_SECTOR_SIZE 512 +#define ARCMSR_MAX_XFER_SECTORS 256 +#define ARCMSR_MAX_XFER_LEN ARCMSR_MAX_XFER_SECTORS * ARCMSR_DEV_SECTOR_SIZE /* 128k */ +#define ARCMSR_MAX_TARGETID 16 /* 16 max target id + 1 */ +#define ARCMSR_MAX_TARGETLUN 8 +#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_FREECCB_NUM +#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ +#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38 */ +#define ARCMSR_MAX_ADAPTER 4 + +/********************************************************************/ + +#define PCIVendorIDARECA 0x17D3 /* Vendor ID */ +#define PCIDeviceIDARC1110 0x1110 /* Device ID */ +#define PCIDeviceIDARC1120 0x1120 /* Device ID */ +#define PCIDeviceIDARC1130 0x1130 /* Device ID */ +#define PCIDeviceIDARC1160 0x1160 /* Device ID */ +#define PCIDeviceIDARC1170 0x1170 /* Device ID */ +#define PCIDeviceIDARC1210 0x1210 /* Device ID */ +#define PCIDeviceIDARC1220 0x1220 /* Device ID */ +#define PCIDeviceIDARC1230 0x1230 /* Device ID */ +#define PCIDeviceIDARC1260 0x1260 /* Device ID */ +#define PCIDeviceIDARC1270 0x1270 /* Device ID */ + +/********************************************************************/ + +#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) +#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) + /* ************************************************************************ ** IOCTL CONTROL CODE ************************************************************************ */ -typedef struct _CMD_IO_CONTROL { +struct CMD_IO_CONTROL { uint32_t HeaderLength; uint8_t Signature[8]; uint32_t Timeout; uint32_t ControlCode; uint32_t ReturnCode; uint32_t Length; -} CMD_IO_CONTROL, *PCMD_IO_CONTROL; -/* -************************************************************************************************************ -************************************************************************************************************ -*/ -typedef struct _CMD_IOCTL_FIELD { - CMD_IO_CONTROL cmdioctl; /*ioctl header */ - uint8_t ioctldatabuffer[1032]; /*areca gui program does not accept more than 1031 byte */ -} CMD_IOCTL_FIELD, *PCMD_IOCTL_FIELD; +}; + +/********************************************************************/ + +struct CMD_IOCTL_FIELD { + struct CMD_IO_CONTROL cmdioctl; /* ioctl header */ + uint8_t ioctldatabuffer[1032]; /* areca gui program does not accept more than 1031 bytes */ +}; #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 @@ -133,7 +123,7 @@ typedef struct _CMD_IOCTL_FIELD { #define FUNCTION_SAY_HELLO 0x0807 #define FUNCTION_SAY_GOODBYE 0x0808 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 -/* ARECA IO CONTROL CODE*/ +/* ARECA IO CONTROL CODE */ #define ARCMSR_IOCTL_READ_RQBUFFER ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER #define ARCMSR_IOCTL_WRITE_WQBUFFER ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER #define ARCMSR_IOCTL_CLEAR_RQBUFFER ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER @@ -152,36 +142,35 @@ typedef struct _CMD_IOCTL_FIELD { ** structure for holding DMA address data ************************************************************* */ -#define IS_SG64_ADDR 0x01000000 /* bit24 */ -typedef struct _SG32ENTRY { /* size 8 bytes *//* length bit 24 == 0 */ - uint32_t length; /* high 8 bit == flag,low 24 bit == length */ +#define IS_SG64_ADDR 0x01000000 /* bit24 */ +struct SG32ENTRY { /* size 8 bytes *//* length bit 24 == 0 */ + uint32_t length; /* high 8 bit == flag, low 24 bit == length */ uint32_t address; -} SG32ENTRY, *PSG32ENTRY; -typedef struct _SG64ENTRY { /* size 12 bytes *//* length bit 24 == 1 */ - uint32_t length; /* high 8 bit == flag,low 24 bit == length */ +}; +struct SG64ENTRY { /* size 12 bytes *//* length bit 24 == 1 */ + uint32_t length; /* high 8 bit == flag, low 24 bit == length */ uint32_t address; uint32_t addresshigh; -} SG64ENTRY, *PSG64ENTRY; -typedef struct _SGENTRY_UNION { +}; +struct SGENTRY_UNION { union { - SG32ENTRY sg32entry; /* 30h Scatter gather address */ - SG64ENTRY sg64entry; /* 30h */ + struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ + struct SG64ENTRY sg64entry; /* 30h */ } u; -} SGENTRY_UNION, PSGENTRY_UNION; -/* -********************************** -********************************** -*/ -typedef struct _QBUFFER { +}; + +/********************************************************************/ + +struct QBUFFER { uint32_t data_len; uint8_t data[124]; -} QBUFFER, *PQBUFFER; +}; /* -************************************************************************************************ +********************************************************************** ** FIRMWARE INFO -************************************************************************************************ +********************************************************************** */ -typedef struct _FIRMWARE_INFO { +struct FIRMWARE_INFO { uint32_t signature; /*0,00-03 */ uint32_t request_len; /*1,04-07 */ uint32_t numbers_queue; /*2,08-11 */ @@ -191,19 +180,19 @@ typedef struct _FIRMWARE_INFO { char model[8]; /*15,60-67 */ char firmware_ver[16]; /*17,68-83 */ char device_map[16]; /*21,84-99 */ -} FIRMWARE_INFO, *PFIRMWARE_INFO; +}; /* -************************************************************************************************ +********************************************************************** ** ARECA FIRMWARE SPEC -************************************************************************************************ +********************************************************************** ** Usage of IOP331 adapter ** (All In/Out is in IOP331's view) ** 1. Message 0 --> InitThread message and retrun code ** 2. Doorbell is used for RS-232 emulation -** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) -** bit1 -- data out has been read (DRIVER DATA READ OK) -** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) -** bit1 -- data in has been read (IOP331 DATA READ OK) +** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) +** bit1 -- data out has been read (DRIVER DATA READ OK) +** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) +** bit1 -- data in has been read (IOP331 DATA READ OK) ** 3. Index Memory Usage ** offset 0xf00 : for RS232 out (request buffer) ** offset 0xe00 : for RS232 in (scratch buffer) @@ -216,67 +205,77 @@ typedef struct _FIRMWARE_INFO { ** 5. PostQ ** All SCSI Command must be sent through postQ: ** (inbound queue port) Request frame must be 32 bytes aligned -** # bit27--bit31 => flag for post ccb -** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb -** bit31 : 0 : 256 bytes frame -** 1 : 512 bytes frame -** bit30 : 0 : normal request -** 1 : BIOS request -** bit29 : reserved -** bit28 : reserved -** bit27 : reserved +** # bit27--bit31 => flag for post ccb +** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb +** bit31 : 0 : 256 bytes frame +** 1 : 512 bytes frame +** bit30 : 0 : normal request +** 1 : BIOS request +** bit29 : reserved +** bit28 : reserved +** bit27 : reserved ** ------------------------------------------------------------------------------- -** (outbount queue port) Request reply -** # bit27--bit31 => flag for reply -** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb -** bit31 : must be 0 (for this type of reply) -** bit30 : reserved for BIOS handshake -** bit29 : reserved -** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData -** 1 : Error, error code in AdapStatus/DevStatus/SenseData -** bit27 : reserved +** (outbound queue port) Request reply +** # bit27--bit31 => flag for reply +** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb +** bit31 : must be 0 (for this type of reply) +** bit30 : reserved for BIOS handshake +** bit29 : reserved +** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData +** 1 : Error, error code in AdapStatus/DevStatus/SenseData +** bit27 : reserved ** 6. BIOS request ** All BIOS request is the same with request from PostQ -** Except : -** Request frame is sent from configuration space -** offset: 0x78 : Request Frame (bit30 == 1) -** offset: 0x18 : writeonly to generate IRQ to IOP331 -** Completion of request: -** (bit30 == 0, bit28==err flag) +** Except: +** Request frame is sent from configuration space +** offset: 0x78 : Request Frame (bit30 == 1) +** offset: 0x18 : writeonly to generate IRQ to IOP331 +** Completion of request: +** (bit30 == 0, bit28==err flag) ** 7. Definition of SGL entry (structure) ** 8. Message1 Out - Diag Status Code (????) -** 9. Message0 message code : -** 0x00 : NOP -** 0x01 : Get Config ->offset 0xa00 :for outbound message code message_rwbuffer (IOP331 send to driver) -** Signature 0x87974060(4) -** Request len 0x00000200(4) -** numbers of queue 0x00000100(4) -** SDRAM Size 0x00000100(4)-->256 MB -** IDE Channels 0x00000008(4) -** vendor 40 bytes char -** model 8 bytes char -** FirmVer 16 bytes char -** Device Map 16 bytes char -** -** FirmwareVersion DWORD <== Added for checking of new firmware capability -** 0x02 : Set Config ->offset 0xa00 :for inbound message code message_rwbuffer (driver send to IOP331) -** Signature 0x87974063(4) -** UPPER32 of Request Frame (4)-->Driver Only -** 0x03 : Reset (Abort all queued Command) -** 0x04 : Stop Background Activity -** 0x05 : Flush Cache -** 0x06 : Start Background Activity (re-start if background is halted) -** 0x07 : Check If Host Command Pending (Novell May Need This Function) -** 0x08 : Set controller time ->offset 0xa00 : for inbound message code message_rwbuffer (driver to IOP331) -** byte 0 : 0xaa <-- signature -** byte 1 : 0x55 <-- signature -** byte 2 : year (04) -** byte 3 : month (1..12) -** byte 4 : date (1..31) -** byte 5 : hour (0..23) -** byte 6 : minute (0..59) -** byte 7 : second (0..59) -************************************************************************************************ +** 9. Message0 message code: +** 0x00 : NOP +** 0x01 : Get Config ->offset 0xa00: +** for outbound message code message_rwbuffer +** (IOP331 send to driver) +** Signature 0x87974060(4) +** Request len 0x00000200(4) +** numbers of queue 0x00000100(4) +** SDRAM Size 0x00000100(4)-->256 MB +** IDE Channels 0x00000008(4) +** vendor 40 bytes char +** model 8 bytes char +** FirmVer 16 bytes char +** Device Map 16 bytes char +** +** FirmwareVersion DWORD <== Added for checking +** of new firmware capability +** +** 0x02 : Set Config ->offset 0xa00: +** for inbound message code message_rwbuffer +** (driver send to IOP331) +** Signature 0x87974063(4) +** UPPER32 of Request Frame (4)-->Driver Only +** 0x03 : Reset (Abort all queued Command) +** 0x04 : Stop Background Activity +** 0x05 : Flush Cache +** 0x06 : Start Background Activity (restart if +** background is halted) +** 0x07 : Check If Host Command Pending (Novell May +** Need This Function) +** 0x08 : Set controller time ->offset 0xa00: +** for inbound message code message_rwbuffer +** (driver to IOP331) +** byte 0 : 0xaa <-- signature +** byte 1 : 0x55 <-- signature +** byte 2 : year (04) +** byte 3 : month (1..12) +** byte 4 : date (1..31) +** byte 5 : hour (0..23) +** byte 6 : minute (0..59) +** byte 7 : second (0..59) +********************************************************************** */ /* signature of set and get firmware config */ #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 @@ -304,11 +303,11 @@ typedef struct _FIRMWARE_INFO { /* outbound firmware ok */ #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 /* -************************************************************************************************ +********************************************************************** ** size 0x1F8 (504) -************************************************************************************************ +********************************************************************** */ -typedef struct _ARCMSR_CDB { +struct ARCMSR_CDB { uint8_t Bus; /* 00h should be 0 */ uint8_t TargetID; /* 01h should be 0--15 */ uint8_t LUN; /* 02h should be 0--7 */ @@ -317,13 +316,13 @@ typedef struct _ARCMSR_CDB { uint8_t CdbLength; /* 04h not used now */ uint8_t sgcount; /* 05h */ uint8_t Flags; /* 06h */ -#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ -#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ -#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ -#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ -#define ARCMSR_CDB_FLAG_HEADQ 0x08 -#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 - uint8_t Reserved1; /* 07h */ +#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ +#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ +#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ +#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3: 00: simple Q */ +#define ARCMSR_CDB_FLAG_HEADQ 0x08 /* 01: head of Q */ +#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 /* 10: ordered Q */ + uint8_t Reserved1; /* 07h */ uint32_t Context; /* 08h Address of this request */ uint32_t DataLength; /* 0ch not used now */ @@ -346,74 +345,78 @@ typedef struct _ARCMSR_CDB { uint8_t SenseData[15]; /* 21h output */ union { - SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ - SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ + struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ + struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ } u; -} ARCMSR_CDB, *PARCMSR_CDB; +}; /* -****************************************************************************************************** -** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) -** ================================================================================================== -** The Messaging Unit (MU) transfers data between the PCI system and the 80331 -** notifies the respective system when new data arrives. -** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. -** window defined by: -** 1.Inbound ATU Base Address Register 0 (IABAR0) -** 2.Inbound ATU Limit Register 0 (IALR0) -** All of the Messaging Unit errors are reported in the same manner as ATU errors. -** Error conditions and status can be found in : -** 1.ATUSR -** 2.ATUISR -**==================================================================================================== -** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt -**---------------------------------------------------------------------------------------------------- -** Message Registers 2 Inbound Optional Optional -** 2 Outbound -**---------------------------------------------------------------------------------------------------- -** Doorbell Registers 1 Inbound Optional Optional -** 1 Outbound -**---------------------------------------------------------------------------------------------------- -** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions -**---------------------------------------------------------------------------------------------------- -** Index Registers 1004 32-bit Memory Locations No Optional -**==================================================================================================== -** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space -**==================================================================================================== -** 0000H Reserved -** 0004H Reserved -** 0008H Reserved -** 000CH Reserved +********************************************************************** +** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) +** ================================================================== +** The Messaging Unit (MU) transfers data between the PCI system and the 80331 +** notifies the respective system when new data arrives. +** The PCI window for messaging transactions is always the first 4 Kbytes of +** the inbound translation. +** Window defined by: +** 1. Inbound ATU Base Address Register 0 (IABAR0) +** 2. Inbound ATU Limit Register 0 (IALR0) +** All of the Messaging Unit errors are reported in the same manner as ATU errors. +** Error conditions and status can be found in: +** 1. ATUSR +** 2. ATUISR +**==================================================================== +** Mechanism Quantity Assert PCI Generate I/O +** Interrupt Signals Processor Interrupt +**-------------------------------------------------------------------- +** Message Registers 2 Inbound Optional Optional +** 2 Outbound +**-------------------------------------------------------------------- +** Doorbell Registers 1 Inbound Optional Optional +** 1 Outbound +**-------------------------------------------------------------------- +** Circular Queues 4 Under certain Under certain +** conditions conditions +**-------------------------------------------------------------------- +** Index Registers 1004 32-bit No Optional +** Memory Locations +**==================================================================== +** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space +**==================================================================== +** 0000H Reserved +** 0004H Reserved +** 0008H Reserved +** 000CH Reserved **------------------------------------------------------------------------ -** 0010H Inbound Message Register 0 ] -** 0014H Inbound Message Register 1 ] -** 0018H Outbound Message Register 0 ] -** 001CH Outbound Message Register 1 ] 4 Message Registers +** 0010H Inbound Message Register 0 ] +** 0014H Inbound Message Register 1 ] +** 0018H Outbound Message Register 0 ] +** 001CH Outbound Message Register 1 ] 4 Message Registers **------------------------------------------------------------------------ -** 0020H Inbound Doorbell Register ] -** 0024H Inbound Interrupt Status Register ] -** 0028H Inbound Interrupt Mask Register ] -** 002CH Outbound Doorbell Register ] -** 0030H Outbound Interrupt Status Register ] -** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers +** 0020H Inbound Doorbell Register ] +** 0024H Inbound Interrupt Status Register ] +** 0028H Inbound Interrupt Mask Register ] +** 002CH Outbound Doorbell Register ] +** 0030H Outbound Interrupt Status Register ] +** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers **------------------------------------------------------------------------ -** 0038H Reserved -** 003CH Reserved +** 0038H Reserved +** 003CH Reserved **------------------------------------------------------------------------ -** 0040H Inbound Queue Port ] -** 0044H Outbound Queue Port ] 2 Queue Ports +** 0040H Inbound Queue Port ] +** 0044H Outbound Queue Port ] 2 Queue Ports **------------------------------------------------------------------------ -** 0048H Reserved -** 004CH Reserved +** 0048H Reserved +** 004CH Reserved **------------------------------------------------------------------------ -** 0050H ] -** : ] -** : Intel Xscale Microarchitecture Local Memory ] -** : ] -** 0FFCH ] 1004 Index Registers -******************************************************************************* +** 0050H ] +** : ] +** : Intel Xscale Microarchitecture Local Memory ] +** : ] +** 0FFCH ] 1004 Index Registers +*************************************************************************** */ -typedef struct _MU { - uint32_t resrved0[4]; /*0000 000F */ +struct MU { + uint32_t resrved0[4]; /*0000 000F */ uint32_t inbound_msgaddr0; /*0010 0013 */ uint32_t inbound_msgaddr1; /*0014 0017 */ uint32_t outbound_msgaddr0; /*0018 001B */ @@ -424,34 +427,34 @@ typedef struct _MU { uint32_t outbound_doorbell; /*002C 002F */ uint32_t outbound_intstatus; /*0030 0033 */ uint32_t outbound_intmask; /*0034 0037 */ - uint32_t reserved1[2]; /*0038 003F */ + uint32_t reserved1[2]; /*0038 003F */ uint32_t inbound_queueport; /*0040 0043 */ uint32_t outbound_queueport; /*0044 0047 */ - uint32_t reserved2[2]; /*0048 004F */ + uint32_t reserved2[2]; /*0048 004F */ uint32_t reserved3[492]; /*0050 07FF ......local_buffer 492 */ uint32_t reserved4[128]; /*0800 09FF 128 */ uint32_t message_rwbuffer[256]; /*0a00 0DFF 256 */ uint32_t ioctl_wbuffer[32]; /*0E00 0E7F 32 */ - uint32_t reserved5[32]; /*0E80 0EFF 32 */ + uint32_t reserved5[32]; /*0E80 0EFF 32 */ uint32_t ioctl_rbuffer[32]; /*0F00 0F7F 32 */ - uint32_t reserved6[32]; /*0F80 0FFF 32 */ -} MU, *PMU; + uint32_t reserved6[32]; /*0F80 0FFF 32 */ +}; /* ********************************************************************* ** Adapter Control Block ********************************************************************* */ -typedef struct _ACB { +struct ACB { struct pci_dev *pPCI_DEV; struct Scsi_Host *host; unsigned long vir2phy_offset; /* Offset is used in making arc cdb physical to virtual calculations */ uint32_t outbound_int_enable; - struct _MU *pmu; /* message unit ATU inbound base address0 */ + struct MU *pmu; /* message unit ATU inbound base address0 */ - uint8_t adapter_index; /* */ + uint8_t adapter_index; uint8_t irq; - uint16_t acb_flags; /* */ + uint16_t acb_flags; #define ACB_F_SCSISTOPADAPTER 0x0001 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ @@ -463,8 +466,8 @@ typedef struct _ACB { #define ACB_F_IOP_INITED 0x0100 /* iop init */ #define ACB_F_HAVE_MSI 0x0200 /* pci message signal interrupt */ - struct _CCB *pccb_pool[ARCMSR_MAX_FREECCB_NUM]; /* used for memory free */ - struct list_head ccb_free_list; /* head of free ccb list */ + struct CCB *pccb_pool[ARCMSR_MAX_FREECCB_NUM]; /* used for memory free */ + struct list_head ccb_free_list; /* head of free ccb list */ struct list_head ccb_pending_list; /* head of pending ccb list */ atomic_t ccboutstandingcount; atomic_t ccbpendingcount; @@ -472,11 +475,11 @@ typedef struct _ACB { void *dma_coherent; /* dma_coherent used for memory free */ dma_addr_t dma_coherent_handle; /* dma_coherent_handle used for memory free */ - uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ + uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ int32_t rqbuf_firstindex; /* first of read buffer */ int32_t rqbuf_lastindex; /* last of read buffer */ - uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ + uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ int32_t wqbuf_firstindex; /* first of write buffer */ int32_t wqbuf_lastindex; /* last of write buffer */ @@ -485,7 +488,7 @@ typedef struct _ACB { spinlock_t working_list_lock; spinlock_t done_list_lock; - uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ + uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ #define ARECA_RAID_GONE 0x55 #define ARECA_RAID_GOOD 0xaa uint32_t num_resets; @@ -494,24 +497,24 @@ typedef struct _ACB { uint32_t firm_numbers_queue; /*2,08-11 */ uint32_t firm_sdram_size; /*3,12-15 */ uint32_t firm_ide_channels; /*4,16-19 */ - char firm_model[12]; /*15,60-67 */ - char firm_version[20]; /*17,68-83 */ -} ACB, *PACB; /* HW_DEVICE_EXTENSION */ + char firm_model[12]; /*15,60-67 */ + char firm_version[20]; /*17,68-83 */ +}; /* ********************************************************************* ** Command Control Block ** this CCB length must be 32 bytes boundary ********************************************************************* */ -typedef struct _CCB { - struct _ARCMSR_CDB arcmsr_cdb; /* 0-503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ +struct CCB { + struct ARCMSR_CDB arcmsr_cdb; /* 0-503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ uint32_t cdb_shifted_phyaddr; /* 504-507 */ uint32_t reserved1; /* 508-511 */ #if BITS_PER_LONG == 64 /* ======================512+64 bytes======================== */ struct list_head list; /* 512-527 16 bytes next/prev ptrs for ccb lists */ struct scsi_cmnd *pcmd; /* 528-535 8 bytes pointer of linux scsi command */ - struct _ACB *pACB; /* 536-543 8 bytes pointer of acb */ + struct ACB *pACB; /* 536-543 8 bytes pointer of acb */ uint16_t ccb_flags; /* 544-545 */ #define CCB_FLAG_READ 0x0000 @@ -529,7 +532,7 @@ typedef struct _CCB { /* ======================512+32 bytes======================== */ struct list_head list; /* 512-519 8 bytes next/prev ptrs for ccb lists */ struct scsi_cmnd *pcmd; /* 520-523 4 bytes pointer of linux scsi command */ - struct _ACB *pACB; /* 524-527 4 bytes pointer of acb */ + struct ACB *pACB; /* 524-527 4 bytes pointer of acb */ uint16_t ccb_flags; /* 528-529 */ #define CCB_FLAG_READ 0x0000 @@ -545,24 +548,22 @@ typedef struct _CCB { uint32_t reserved2[3]; /* 532-535 536-539 540-543 */ #endif /* ========================================================== */ -} CCB, *PCCB; -/* -********************************************************************* -********************************************************************* -*/ -typedef struct _HCBARC { - struct _ACB *pACB[ARCMSR_MAX_ADAPTER]; +}; + +/********************************************************************/ + +struct HCBARC { + struct ACB *pACB[ARCMSR_MAX_ADAPTER]; int32_t arcmsr_major_number; uint8_t adapterCnt; uint8_t reserved[3]; -} HCBARC, *PHCBARC; -/* -************************************************************* -************************************************************* -*/ -typedef struct _SENSE_DATA { +}; + +/********************************************************************/ + +struct SENSE_DATA { uint8_t ErrorCode:7; uint8_t Valid:1; uint8_t SegmentNumber; @@ -578,46 +579,46 @@ typedef struct _SENSE_DATA { uint8_t AdditionalSenseCodeQualifier; uint8_t FieldReplaceableUnitCode; uint8_t SenseKeySpecific[3]; -} SENSE_DATA, *PSENSE_DATA; +}; + /* ********************************** ** Peripheral Device Type definitions ********************************** */ -#define SCSI_DASD 0x00 /* Direct-access Device */ +#define SCSI_DASD 0x00 /* Direct-access Device */ #define SCSI_SEQACESS 0x01 /* Sequential-access device */ #define SCSI_PRINTER 0x02 /* Printer device */ #define SCSI_PROCESSOR 0x03 /* Processor device */ #define SCSI_WRITEONCE 0x04 /* Write-once device */ -#define SCSI_CDROM 0x05 /* CD-ROM device */ +#define SCSI_CDROM 0x05 /* CD-ROM device */ #define SCSI_SCANNER 0x06 /* Scanner device */ #define SCSI_OPTICAL 0x07 /* Optical memory device */ #define SCSI_MEDCHGR 0x08 /* Medium changer device */ -#define SCSI_COMM 0x09 /* Communications device */ -#define SCSI_NODEV 0x1F /* Unknown or no device type */ +#define SCSI_COMM 0x09 /* Communications device */ +#define SCSI_NODEV 0x1F /* Unknown or no device type */ /* -************************************************************************************************************ -** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -** 80331 PCI-to-PCI Bridge -** PCI Configuration Space -** -** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -** Programming Interface -** ======================== -** Configuration Register Address Space Groupings and Ranges -** ============================================================= -** Register Group Configuration Offset -** ------------------------------------------------------------- -** Standard PCI Configuration 00-3Fh -** ------------------------------------------------------------- -** Device Specific Registers 40-A7h -** ------------------------------------------------------------- -** Reserved A8-CBh -** ------------------------------------------------------------- -** Enhanced Capability List CC-FFh -** ========================================================================================================== -** Standard PCI [Type 1] Configuration Space Address Map -** ********************************************************************************************************** +*************************************************************************** +** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +** 80331 PCI-to-PCI Bridge +** PCI Configuration Space +** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +** Programming Interface +** ======================== +** Configuration Register Address Space Groupings and Ranges +** ============================================================= +** Register Group Configuration Offset +** ------------------------------------------------------------- +** Standard PCI Configuration 00-3Fh +** ------------------------------------------------------------- +** Device Specific Registers 40-A7h +** ------------------------------------------------------------- +** Reserved A8-CBh +** ------------------------------------------------------------- +** Enhanced Capability List CC-FFh +** ======================================================================== +** Standard PCI [Type 1] Configuration Space Address Map +** ************************************************************************ ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset ** ---------------------------------------------------------------------------------------------------------- ** | Device ID | Vendor ID | 00h @@ -651,21 +652,21 @@ typedef struct _SENSE_DATA { ** | Reserved | 38h ** ---------------------------------------------------------------------------------------------------------- ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch -**============================================================================================================= +**========================================================================= */ /* -**============================================================================================================= -** 0x03-0x00 : +**========================================================================= +** 0x03-0x00: ** Bit Default Description **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. ** ID is unique per product speed as indicated. **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. -**============================================================================================================= +**========================================================================= */ -#define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word */ -#define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word */ +#define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /* word */ +#define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /* word */ /* -**============================================================================== +**========================================================================= ** 0x05-0x04 : command register ** Bit Default Description **15:11 00h Reserved @@ -702,12 +703,12 @@ typedef struct _SENSE_DATA { ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. ** 0=The bridge target response to I/O transactions on the primary interface is disabled. ** 1=The bridge target response to I/O transactions on the primary interface is enabled. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word */ +#define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /* word */ #define PCI_DISABLE_INTERRUPT 0x0400 /* -**============================================================================== +**========================================================================= ** 0x07-0x06 : status register ** Bit Default Description ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, attribute or data parity error. @@ -731,41 +732,41 @@ typedef struct _SENSE_DATA { ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. ** The bridge does not support interrupts. ** 02:00 000 Reserved -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ +#define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /* word: 06,07 */ #define ARCMSR_ADAP_66MHZ 0x20 /* -**============================================================================== +**========================================================================= ** 0x08 : revision ID ** Bit Default Description ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte */ +#define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /* byte */ /* -**============================================================================== -** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) +**========================================================================= +** 0x0b-0x09 : 0180_00 (class code 1, native pci mode ) ** Bit Default Description ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes */ +#define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /* 3 bytes */ /* -**============================================================================== +**========================================================================= ** 0x0c : cache line size ** Bit Default Description ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. ** The contents of this register are factored into internal policy decisions associated with memory read prefetching, and the promotion of Memory Write transactions to MWI transactions. ** Valid cache line sizes are 8 and 16 dwords. ** When the cache line size is set to an invalid value, bridge behaves as though the cache line size was set to 00h. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte */ +#define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /* byte */ /* -**============================================================================== +**========================================================================= ** 0x0d : latency timer (number of pci clock 00-ff ) ** Bit Default Description ** Primary Latency Timer (PTV): @@ -781,38 +782,38 @@ typedef struct _SENSE_DATA { ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. ** (Except in the case where MLT expires within 3 data phases of an ADB.In this case bridge continues on until it reaches the next ADB before relinquishing the bus.) -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte */ +#define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /* byte */ /* -**============================================================================== -** 0x0e : (header type,single function ) +**========================================================================= +** 0x0e : (header type, single function ) ** Bit Default Description ** 07 0 Multi-function device (MVD): 80331 is a single-function device. ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. ** Returns ¡§01h¡¨ when read indicating that the register layout conforms to the standard PCI-to-PCI bridge layout. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte */ +#define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /* byte */ /* -**============================================================================== +**========================================================================= ** 0x0f : -**============================================================================== +**========================================================================= */ /* -**============================================================================== +**========================================================================= ** 0x13-0x10 : ** PCI CFG Base Address #0 (0x10) -**============================================================================== +**========================================================================= */ /* -**============================================================================== +**========================================================================= ** 0x17-0x14 : ** PCI CFG Base Address #1 (0x14) -**============================================================================== +**========================================================================= */ /* -**============================================================================== +**========================================================================= ** 0x1b-0x18 : ** PCI CFG Base Address #2 (0x18) **-----------------0x1A,0x19,0x18--Bus Number Register - BNR @@ -828,25 +829,25 @@ typedef struct _SENSE_DATA { ** Bit Default Description ** Secondary Latency Timer (STV): ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. -** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# to the expiration of the timer, +** Indicates the number of PCI clock cycles, referenced from the assertion of FRAME# to the expiration of the timer, ** when bridge may continue as master of the current transaction. All bits are writable, ** resulting in a granularity of 1 PCI clock cycle. ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus after the first data transfer when its PCI bus grant has been deasserted. ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. -** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# to the expiration of the timer, +** Indicates the number of PCI clock cycles, referenced from the assertion of FRAME# to the expiration of the timer, ** when bridge may continue as master of the current transaction. All bits are writable, ** resulting in a granularity of 1 PCI clock cycle. ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. ** (Except in the case where MLT expires within 3 data phases of an ADB. In this case bridge continues on until it reaches the next ADB before relinquishing the bus) -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18 */ -#define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte */ -#define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte */ -#define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte */ +#define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /* 3byte 0x1A,0x19,0x18 */ +#define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /* byte */ +#define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /* byte */ +#define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /* byte */ /* -**============================================================================== -** 0x1f-0x1c : +**========================================================================= +** 0x1f-0x1c: ** PCI CFG Base Address #3 (0x1C) **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL ** Bit Default Description @@ -876,14 +877,14 @@ typedef struct _SENSE_DATA { ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. ** 1 = ** 04:00 00h Reserved -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte */ -#define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte */ -#define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ +#define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /* byte */ +#define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /* byte */ +#define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /* word: 0x1F,0x1E */ /* -**============================================================================== -** 0x23-0x20 : +**========================================================================= +** 0x23-0x20: ** PCI CFG Base Address #4 (0x20) **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL ** Bit Default Description @@ -896,13 +897,13 @@ typedef struct _SENSE_DATA { ** The incoming address must be greater than or equal to this value. ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) are assumed to be 0 0000h. ** 03:00 0h Reserved. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ -#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ +#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /* word: 0x21,0x20 */ +#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /* word: 0x23,0x22 */ /* -**============================================================================== -** 0x27-0x24 : +**========================================================================= +** 0x27-0x24: ** PCI CFG Base Address #5 (0x24) **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL ** Bit Default Description @@ -915,56 +916,56 @@ typedef struct _SENSE_DATA { ** The incoming address must be greater than or equal to this value. ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) are assumed to be 0 0000h. ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ -#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ +#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /* word: 0x25,0x24 */ +#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /* word: 0x27,0x26 */ /* -**============================================================================== -** 0x2b-0x28 : +**========================================================================= +** 0x2b-0x28: ** Bit Default Description ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable ** bridge supports full 64-bit addressing. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ +#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /* dword: 0x2b,0x2a,0x29,0x28 */ /* -**============================================================================== -** 0x2f-0x2c : +**========================================================================= +** 0x2f-0x2c: ** Bit Default Description ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable ** bridge supports full 64-bit addressing. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ +#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /* dword: 0x2f,0x2e,0x2d,0x2c */ /* -**============================================================================== -** 0x33-0x30 : +**========================================================================= +** 0x33-0x30: ** Bit Default Description ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration ** space. (Power Management Capability Registers) -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte */ +#define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /* byte */ /* -**============================================================================== +**========================================================================= ** 0x3b-0x35 : reserved -**============================================================================== +**========================================================================= */ /* -**============================================================================== -** 0x3d-0x3c : +**========================================================================= +** 0x3d-0x3c: ** ** Bit Default Description ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte */ -#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte */ +#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /* byte */ +#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /* byte */ /* -**============================================================================== -** 0x3f-0x3e : +**========================================================================= +** 0x3f-0x3e: ** Bit Default Description ** 15:12 0h Reserved ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response @@ -975,7 +976,7 @@ typedef struct _SENSE_DATA { ** The delayed completion is then discarded. ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles that bridge waits for an initiator on the secondary bus to repeat a delayed transaction request. ** The counter starts when the delayed transaction completion is ready to be returned to the initiator. -** When the initiator has not repeated the transaction at least once before the counter expires,bridge discards the delayed transaction from its queues. +** When the initiator has not repeated the transaction at least once before the counter expires, bridge discards the delayed transaction from its queues. ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles that bridge waits for an initiator on the primary bus to repeat a delayed transaction request. @@ -988,15 +989,15 @@ typedef struct _SENSE_DATA { ** When cleared to 0b: The bridge deasserts S_RST#, when it had been asserted by writing this bit to a 1b. ** When set to 1b: The bridge asserts S_RST#. ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus when a master abort termination occurs in response to a delayed transaction initiated by bridge on the target bus. -** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,and returns FFFF FFFFh when a read. -** 1b=When the transaction had not yet been completed on the initiator bus (e.g.,delayed reads, or non-posted writes), +** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, and returns FFFF FFFFh when a read. +** 1b=When the transaction had not yet been completed on the initiator bus (e.g., delayed reads, or non-posted writes), ** then bridge returns a Target Abort in response to the original requester ** when it returns looking for its delayed completion on the initiator bus. ** When the transaction had completed on the initiator bus (e.g., a PMW), then bridge asserts P_SERR# (when enabled). ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort while attempting to deliver a posted memory write on the destination bus. ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit (also of this register), ** and the VGA Palette Snoop Enable bit (Command Register). -** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) the VGA Aliasing bit for the corresponding enabled functionality,: +** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) the VGA Aliasing bit for the corresponding enabled functionality: ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), then this bit has no impact on bridge behavior. @@ -1014,9 +1015,9 @@ typedef struct _SENSE_DATA { ** Also bridge does not assert P_SERR# in response to a detected address or attribute parity error. ** 1b=When a data parity error is detected bridge asserts S_PERR#. The bridge also asserts P_SERR# (when enabled globally via bit(8) of the Command register) ** in response to a detected address or attribute parity error. -**============================================================================== +**========================================================================= */ -#define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word */ +#define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /* word */ /* ************************************************************************** ** Device Specific Registers 40-A7h @@ -1044,11 +1045,11 @@ typedef struct _SENSE_DATA { ** ---------------------------------------------------------------------------------------------------------- ** | Reserved | 68h:CBh ** ---------------------------------------------------------------------------------------------------------- -************************************************************************** -**============================================================================== +*************************************************************************** +**========================================================================= ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR ** Bit Default Description -** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule (PCI=16 clocks,PCI-X=6 clocks). +** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule (PCI=16 clocks, PCI-X=6 clocks). ** Note that this field is only meaningful when: ** # Bit[11] of this register is set to 1b, indicating that a Grant Time-out violation had occurred. ** # bridge internal arbiter is enabled. @@ -1073,7 +1074,7 @@ typedef struct _SENSE_DATA { ** Bits [5:4] are unused. ** 0b=Indicates that the master belongs to the low priority group. ** 1b=Indicates that the master belongs to the high priority group -**================================================================================= +**========================================================================= ** 0x43: Bridge Control Register 0 - BCR0 ** Bit Default Description ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight and the Posted Write data is limited to 4KB. @@ -1085,7 +1086,7 @@ typedef struct _SENSE_DATA { ** Multiple is enabled when forwarding a PCI-X Memory Read Block request to an upstream bus operating in Conventional PCI mode. ** 1b=bridge treats upstream PCI Memory Read requests as though they target non-prefetchable memory and forwards upstream PCI-X Memory Read Block commands as Memory Read when the primary bus is operating in Conventional PCI mode. ** NOTE: This bit does not affect bridge ability to perform read prefetching when the received command is Memory Read Line or Memory Read Multiple. -**================================================================================= +**========================================================================= ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) ** Bit Default Description ** 15:08 0000000b Reserved @@ -1120,7 +1121,7 @@ typedef struct _SENSE_DATA { ** 0b=The primary master time-out counter is enabled and uses the value specified by the Primary Discard Timer bit (see Bridge Control Register). ** 1b=The secondary master time-out counter is disabled. The bridge waits indefinitely for a secondary bus master to repeat a delayed transaction. ** 00 0b Reserved -**================================================================================= +**========================================================================= ** 0x47-0x46: Bridge Control Register 2 - BCR2 ** Bit Default Description ** 15:07 0000b Reserved. @@ -1137,7 +1138,7 @@ typedef struct _SENSE_DATA { ** frequency of the secondary bus clock: ** ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with all four S_CLKOs enabled by default. (SCLKO[3:0])¡P ** ¡E Designs with 133 MHz Secondary PCI clock power up with the lower order 3 S_CLKOs enabled by default. (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected to downstream device clock inputs. -**================================================================================= +**========================================================================= ** 0x49-0x48: Bridge Status Register - BSR ** Bit Default Description ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# is conditionally asserted when the secondary discard timer expires. @@ -1164,7 +1165,7 @@ typedef struct _SENSE_DATA { ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream PMW transaction after receiving 2 24 target retries from the secondary bus target ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when a data parity error is detected by bridge while attempting to retire a PMW downstream. ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge detects an address parity error on the primary bus. -**================================================================================== +**========================================================================= ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR ** Bit Default Description ** 15:13 000b Reserved @@ -1185,7 +1186,7 @@ typedef struct _SENSE_DATA { ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. ** When a given bit is set to 1b, its corresponding REQ#/GNT# pair is enabled for MTT functionality as determined by bits(12:10) of this register. ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. -**================================================================================== +**========================================================================= ** 0x53-0x52: Read Prefetch Policy Register - RPPR ** Bit Default Description ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the secondary bus interface on subsequent PreFetch operations given that the read demands were not satisfied using the FirstRead parameter. @@ -1210,7 +1211,7 @@ typedef struct _SENSE_DATA { ** Memory Read Line 1 cache line ** Memory Read Multiple 2 cache lines ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands only to the next higher cache line boundary.For non-cache line aligned Memory Read Multiple commands bridge pre-fetches only to the second cache line boundary encountered. -**================================================================================== +**========================================================================= ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL ** Bit Default Description ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior in response to its discarding of a delayed transaction that was initiated from the primary bus. @@ -1261,7 +1262,7 @@ typedef struct _SENSE_DATA { ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior when it detects an address parity error on the primary bus. ** 0b=bridge asserts P_SERR#. ** 1b=bridge does not assert P_SERR# -**=============================================================================== +**========================================================================= ** 0x56: Pre-Boot Status Register - PBSR ** Bit Default Description ** 07 1 Reserved @@ -1273,7 +1274,7 @@ typedef struct _SENSE_DATA { ** 0 100 MHz ** 1 133 MH ** 00 0b Reserved -**=============================================================================== +**========================================================================= ** 0x59-0x58: Secondary Decode Enable Register - SDER ** Bit Default Description ** 15:03 FFF1h Preserved. @@ -1281,7 +1282,7 @@ typedef struct _SENSE_DATA { ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. ** This creates a private memory space on the Secondary PCI bus that allows peer-to-peer transactions. ** 01:00 10 2 Preserved. -**=============================================================================== +**========================================================================= ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR ** Bit Default Description ** 15:10 000000 2 Reserved. @@ -1337,15 +1338,15 @@ typedef struct _SENSE_DATA { ** ---------------------------------------------------------------------------------------------------------- ** | PCI-X Downstream Split Transaction Control | FCh ** ---------------------------------------------------------------------------------------------------------- -**=============================================================================== +**========================================================================= ** 0xDC: Power Management Capabilities Identifier - PM_CAPID ** Bit Default Description ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block -**=============================================================================== +**========================================================================= ** 0xDD: Next Item Pointer - PM_NXTP ** Bit Default Description ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. -**=============================================================================== +**========================================================================= ** 0xDF-0xDE: Power Management Capabilities Register - PMCR ** Bit Default Description ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. @@ -1356,38 +1357,38 @@ typedef struct _SENSE_DATA { ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. ** 04:03 00 Reserved ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. -**=============================================================================== +**========================================================================= ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR ** Bit Default Description ** 15:09 00h Reserved ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. ** 07:02 00h Reserved ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of a function and to set the Function into a new power state. -** 00 - D0 state -** 01 - D1 state -** 10 - D2 state -** 11 - D3 hot state -**=============================================================================== +** 00 - D0 state +** 01 - D1 state +** 10 - D2 state +** 11 - D3 hot state +**========================================================================= ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE ** Bit Default Description ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that is to occur as a direct result of programming the function to D3 hot. -** This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨. +** This bit is only meaningful when bit 7 (BPCC_En) is a '1'. ** 05:00 00h Reserved -**=============================================================================== +**========================================================================= ** 0xE3: Power Management Data Register - PMDR ** Bit Default Description ** 07:00 00h Reserved -**=============================================================================== +**========================================================================= ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID ** Bit Default Description ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. -**=============================================================================== +**========================================================================= ** 0xF1: Next Item Pointer - PX_NXTP ** Bit Default Description ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this ** register is 00h indicating that this is the last entry in the linked list of capabilities. -**=============================================================================== +**========================================================================= ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS ** Bit Default Description ** 15:09 00h Reserved @@ -1409,7 +1410,7 @@ typedef struct _SENSE_DATA { ** 02 0b Split Completion Discarded (SCD): This bit is set when bridge discards a split completion moving toward the secondary bus because the requester would not accept it. This bit cleared by software writing a '1'. ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. -**=============================================================================== +**========================================================================= ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS ** Bit Default Description ** 31:22 0 Reserved @@ -1428,7 +1429,7 @@ typedef struct _SENSE_DATA { ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. May be updated whenever a PCI-X ** configuration write cycle that targets bridge scores a hit. ** 02:00 0h Function Number (FNUM): The bridge Function # -**=============================================================================== +**========================================================================= ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC ** Bit Default Description ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. @@ -1441,7 +1442,7 @@ typedef struct _SENSE_DATA { ** split completions. This register controls behavior of the bridge buffers for forwarding ** Split Transactions from a primary bus requester to a secondary bus completer. ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). -**=============================================================================== +**========================================================================= ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC ** Bit Default Description ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. @@ -1458,11 +1459,11 @@ typedef struct _SENSE_DATA { */ /* -************************************************************************************************************************************* -** 80331 Address Translation Unit Register Definitions -** ATU Interface Configuration Header Format -** The ATU is programmed via a [Type 0] configuration command on the PCI interface. -************************************************************************************************************************************* +*************************************************************************** +** 80331 Address Translation Unit Register Definitions +** ATU Interface Configuration Header Format +** The ATU is programmed via a [Type 0] configuration command on the PCI interface. +*************************************************************************** ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset **=================================================================================================================================== ** | ATU Device ID | Vendor ID | 00h @@ -1497,29 +1498,29 @@ typedef struct _SENSE_DATA { ** ---------------------------------------------------------------------------------------------------------- ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH ** ---------------------------------------------------------------------------------------------------------- -********************************************************************************************************************* +*************************************************************************** */ /* -*********************************************************************************** +*************************************************************************** ** ATU Vendor ID Register - ATUVID ** ----------------------------------------------------------------- ** Bit Default Description ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. This register, combined with the DID, uniquely identify the PCI device. ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID to simulate the interface of a standard mechanism currently used by existing application software. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word */ +#define ARCMSR_ATU_VENDOR_ID_REG 0x00 /* word */ /* -*********************************************************************************** +*************************************************************************** ** ATU Device ID Register - ATUDID ** ----------------------------------------------------------------- ** Bit Default Description ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. This ID, combined with the VID, uniquely identify any PCI device. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word */ +#define ARCMSR_ATU_DEVICE_ID_REG 0x02 /* word */ /* -*********************************************************************************** +*************************************************************************** ** ATU Command Register - ATUCMD ** ----------------------------------------------------------------- ** Bit Default Description @@ -1539,11 +1540,11 @@ typedef struct _SENSE_DATA { ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless of the state of this bit. ** 01 0 2 Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses. When cleared, the ATU interface does not respond to any memory access on the PCI bus. ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. Not implemented and a reserved bit field. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_COMMAND_REG 0x04 /*word */ +#define ARCMSR_ATU_COMMAND_REG 0x04 /* word */ /* -*********************************************************************************** +*************************************************************************** ** ATU Status Register - ATUSR (Sheet 1 of 2) ** ----------------------------------------------------------------- ** Bit Default Description @@ -1585,40 +1586,40 @@ typedef struct _SENSE_DATA { ** Section 3.10.23, ¡§ATU Interrupt Pin Register - ATUIPR¡¨ on page 236 for details on the ATU ** interrupt signal. ** 02:00 00000 2 Reserved. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_STATUS_REG 0x06 /*word */ +#define ARCMSR_ATU_STATUS_REG 0x06 /* word */ /* -*********************************************************************************** +*************************************************************************** ** ATU Revision ID Register - ATURID ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 00H ATU Revision - identifies the 80331 revision number. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_REVISION_REG 0x08 /*byte */ +#define ARCMSR_ATU_REVISION_REG 0x08 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** ATU Class Code Register - ATUCCR ** ----------------------------------------------------------------- ** Bit Default Description ** 23:16 05H Base Class - Memory Controller ** 15:08 80H Sub Class - Other Memory Controller ** 07:00 00H Programming Interface - None defined -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09 */ +#define ARCMSR_ATU_CLASS_CODE_REG 0x09 /* 3 bytes: 0x0B,0x0A,0x09 */ /* -*********************************************************************************** +*************************************************************************** ** ATU Cacheline Size Register - ATUCLSR ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte */ +#define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /* byte */ /* -*********************************************************************************** +*************************************************************************** ** ATU Latency Timer Register - ATULT ** ----------------------------------------------------------------- ** Bit Default Description @@ -1627,22 +1628,22 @@ typedef struct _SENSE_DATA { ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte */ +#define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /* byte */ /* -*********************************************************************************** +*************************************************************************** ** ATU Header Type Register - ATUHTR ** ----------------------------------------------------------------- ** Bit Default Description ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface ** header conforms to PCI Local Bus Specification, Revision 2.3. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte */ +#define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /* byte */ /* -*********************************************************************************** +*************************************************************************** ** ATU BIST Register - ATUBISTR ** ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is @@ -1661,13 +1662,13 @@ typedef struct _SENSE_DATA { ** 05:04 00 2 Reserved ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): ** The Intel XScale core places the results of the software BIST in these bits. A nonzero value indicates a device-specific error. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_BIST_REG 0x0F /*byte */ +#define ARCMSR_ATU_BIST_REG 0x0F /* byte */ /* -*************************************************************************************** +*************************************************************************** ** ATU Base Registers and Associated Limit Registers -*************************************************************************************** +*************************************************************************** ** Base Address Register Limit Register Description ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound translation window 0 from the PCI bus for DACs. @@ -1679,16 +1680,16 @@ typedef struct _SENSE_DATA { ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound translation window 3 from the PCI bus for DACs. ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading from an Expansion ROM. -**-------------------------------------------------------------------------------------- +**------------------------------------------------------------------------- ** ATU Inbound Window 1 is not a translate window. ** The ATU does not claim any PCI accesses that fall within this range. ** This window is used to allocate host memory for use by Private Devices. ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. -*********************************************************************************** +*************************************************************************** */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Base Address Register 0 - IABAR0 ** ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) defines the block of memory addresses where the inbound translation window 0 begins. @@ -1721,13 +1722,13 @@ typedef struct _SENSE_DATA { ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. ** The ATU does not occupy I/O space, ** thus this bit must be zero. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10 */ -#define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 -#define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 +#define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /* dword 0x13,0x12,0x11,0x10 */ +#define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 +#define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 ** ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. @@ -1741,11 +1742,11 @@ typedef struct _SENSE_DATA { ** Bit Default Description ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14 */ +#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /* dword 0x17,0x16,0x15,0x14 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Base Address Register 1 - IABAR1 ** ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) defines the block of memory addresses where the inbound translation window 1 begins. @@ -1776,11 +1777,11 @@ typedef struct _SENSE_DATA { ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. ** The ATU does not occupy I/O space, ** thus this bit must be zero. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18 */ +#define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /* dword 0x1B,0x1A,0x19,0x18 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 ** ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. @@ -1797,11 +1798,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C */ +#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /* dword 0x1F,0x1E,0x1D,0x1C */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Base Address Register 2 - IABAR2 ** ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) defines the block of memory addresses where the inbound translation window 2 begins. @@ -1834,11 +1835,11 @@ typedef struct _SENSE_DATA { ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. ** The ATU does not occupy I/O space, ** thus this bit must be zero. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20 */ +#define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /* dword 0x23,0x22,0x21,0x20 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 ** ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. @@ -1852,50 +1853,50 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 these bits define the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24 */ +#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /* dword 0x27,0x26,0x25,0x24 */ /* -*********************************************************************************** +*************************************************************************** ** ATU Subsystem Vendor ID Register - ASVIR ** ----------------------------------------------------------------- ** Bit Default Description ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C */ +#define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /* word 0x2D,0x2C */ /* -*********************************************************************************** +*************************************************************************** ** ATU Subsystem ID Register - ASIR ** ----------------------------------------------------------------- ** Bit Default Description ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E */ +#define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /* word 0x2F,0x2E */ /* -*********************************************************************************** +*************************************************************************** ** Expansion ROM Base Address Register -ERBAR ** ----------------------------------------------------------------- ** Bit Default Description ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. ** 11:01 000H Reserved ** 00 0 2 Address Decode Enable - This bit field shows the ROM address decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30 */ -#define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 +#define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /* dword 0x33,0x32,0v31,0x30 */ +#define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 /* -*********************************************************************************** +*************************************************************************** ** ATU Capabilities Pointer Register - ATU_CAP_PTR ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 C0H Capability List Pointer - This provides an offset in this function¡¦s configuration space that points to the 80331 PCl Bus Power Management extended capability. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte */ +#define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** Determining Block Sizes for Base Address Registers ** The required address size and type can be determined by writing ones to a base address register and ** reading from the registers. By scanning the returned value from the least-significant bit of the base @@ -1945,49 +1946,49 @@ typedef struct _SENSE_DATA { ** FFFC0000H 256K ** FFF80000H 512K ** -*************************************************************************************** +*************************************************************************** */ /* -*********************************************************************************** +*************************************************************************** ** ATU Interrupt Line Register - ATUILR ** ----------------------------------------------------------------- ** Bit Default Description -** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller¡¦s interrupt -** request line connects to the device's PCI interrupt request lines (as specified in the interrupt pin register). -** A value of FFH signifies ¡§no connection¡¨ or ¡§unknown¡¨. -*********************************************************************************** +** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller's interrupt +** request line connects to the device's PCI interrupt request lines (as specified in the interrupt pin register). +** A value of FFH signifies 'no connection' or 'unknown'. +*************************************************************************** */ -#define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte */ +#define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /* byte */ /* -*********************************************************************************** +*************************************************************************** ** ATU Interrupt Pin Register - ATUIPR ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte */ +#define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /* byte */ /* -*********************************************************************************** +*************************************************************************** ** ATU Minimum Grant Register - ATUMGNT ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte */ +#define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /* byte */ /* -*********************************************************************************** +*************************************************************************** ** ATU Maximum Latency Register - ATUMLAT ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte */ +#define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /* byte */ /* -*********************************************************************************** +*************************************************************************** ** Inbound Address Translation ** ** The ATU allows external PCI bus initiators to directly access the internal bus. @@ -2070,11 +2071,11 @@ typedef struct _SENSE_DATA { ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H ** ** ANS:IB_Address=B145 012CH -*********************************************************************************** +*************************************************************************** */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Limit Register 0 - IALR0 ** ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI @@ -2095,11 +2096,11 @@ typedef struct _SENSE_DATA { ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40 */ +#define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /* dword 0x43,0x42,0x41,0x40 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Translate Value Register 0 - IATVR0 ** ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to @@ -2110,11 +2111,11 @@ typedef struct _SENSE_DATA { ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to access the internal 80331 memory-mapped registers. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44 */ +#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /* dword 0x47,0x46,0x45,0x44 */ /* -*********************************************************************************** +*************************************************************************** ** Expansion ROM Limit Register - ERLR ** ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines @@ -2128,11 +2129,11 @@ typedef struct _SENSE_DATA { ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. ** 11:00 000H Reserved. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48 */ +#define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /* dword 0x4B,0x4A,0x49,0x48 */ /* -*********************************************************************************** +*************************************************************************** ** Expansion ROM Translate Value Register - ERTVR ** ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the @@ -2143,11 +2144,11 @@ typedef struct _SENSE_DATA { ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C */ +#define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /* dword 0x4F,0x4E,0x4D,0x4C */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Limit Register 1 - IALR1 ** ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a @@ -2165,11 +2166,11 @@ typedef struct _SENSE_DATA { ** Bit Default Description ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size required for the ATUs memory window 1. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50 */ +#define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /* dword 0x53,0x52,0x51,0x50 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Limit Register 2 - IALR2 ** ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI @@ -2194,11 +2195,11 @@ typedef struct _SENSE_DATA { ** Bit Default Description ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size required for the ATUs memory window 2. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54 */ +#define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /* dword 0x57,0x56,0x55,0x54 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Translate Value Register 2 - IATVR2 ** ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to @@ -2209,11 +2210,11 @@ typedef struct _SENSE_DATA { ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to access the internal 80331 memory-mapped registers. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58 */ +#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /* dword 0x5B,0x5A,0x59,0x58 */ /* -*********************************************************************************** +*************************************************************************** ** Outbound I/O Window Translate Value Register - OIOWTVR ** ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address @@ -2225,11 +2226,11 @@ typedef struct _SENSE_DATA { ** Bit Default Description ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. ** 15:00 0000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C */ +#define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /* dword 0x5F,0x5E,0x5D,0x5C */ /* -*********************************************************************************** +*************************************************************************** ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 ** ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI @@ -2242,11 +2243,11 @@ typedef struct _SENSE_DATA { ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. ** 25:02 00 0000H Reserved ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. Only linear incrementing mode is supported. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60 */ +#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /* dword 0x63,0x62,0x61,0x60 */ /* -*********************************************************************************** +*************************************************************************** ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 ** ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines @@ -2258,11 +2259,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64 */ +#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /* dword 0x67,0x66,0x65,0x64 */ /* -*********************************************************************************** +*************************************************************************** ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 ** ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI @@ -2275,11 +2276,11 @@ typedef struct _SENSE_DATA { ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. ** 25:02 00 0000H Reserved ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. Only linear incrementing mode is supported. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68 */ +#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /* dword 0x6B,0x6A,0x69,0x68 */ /* -*********************************************************************************** +*************************************************************************** ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 ** ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines @@ -2291,11 +2292,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C */ +#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /* dword 0x6F,0x6E,0x6D,0x6C */ /* -*********************************************************************************** +*************************************************************************** ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR ** ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the @@ -2305,11 +2306,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78 */ +#define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /* dword 0x7B,0x7A,0x79,0x78 */ /* -*********************************************************************************** +*************************************************************************** ** ATU Configuration Register - ATUCR ** ** The ATU Configuration Register controls the outbound address translation for address translation @@ -2342,11 +2343,11 @@ typedef struct _SENSE_DATA { ** 02 0 2 Reserved ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. When cleared, disables the outbound ATU. ** 00 0 2 Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80 */ +#define ARCMSR_ATU_CONFIGURATION_REG 0x80 /* dword 0x83,0x82,0x81,0x80 */ /* -*********************************************************************************** +*************************************************************************** ** PCI Configuration and Status Register - PCSR ** ** The PCI Configuration and Status Register has additional bits for controlling and monitoring @@ -2490,11 +2491,11 @@ typedef struct _SENSE_DATA { ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. ** 0=Private Memory control Disabled - SDER register bit 2 default to zero ** 1=Private Memory control Enabled - SDER register bits 2 default to one -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84 */ +#define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /* dword 0x87,0x86,0x85,0x84 */ /* -*********************************************************************************** +*************************************************************************** ** ATU Interrupt Status Register - ATUISR ** ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU @@ -2551,11 +2552,11 @@ typedef struct _SENSE_DATA { ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88 */ +#define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /* dword 0x8B,0x8A,0x89,0x88 */ /* -*********************************************************************************** +*************************************************************************** ** ATU Interrupt Mask Register - ATUIMR ** ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts @@ -2631,11 +2632,11 @@ typedef struct _SENSE_DATA { ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, ** independent of the setting of this bit. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C */ +#define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /* dword 0x8F,0x8E,0x8D,0x8C */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Base Address Register 3 - IABAR3 ** ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block of memory addresses where the inbound translation window 3 begins. @@ -2671,11 +2672,11 @@ typedef struct _SENSE_DATA { ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. ** The ATU does not occupy I/O space, ** thus this bit must be zero. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90 */ +#define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /* dword 0x93,0x92,0x91,0x90 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 ** ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. @@ -2689,11 +2690,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94 */ +#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /* dword 0x97,0x96,0x95,0x94 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Limit Register 3 - IALR3 ** ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI @@ -2718,11 +2719,11 @@ typedef struct _SENSE_DATA { ** Bit Default Description ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required for the ATUs memory window 3. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98 */ +#define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /* dword 0x9B,0x9A,0x99,0x98 */ /* -*********************************************************************************** +*************************************************************************** ** Inbound ATU Translate Value Register 3 - IATVR3 ** ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to @@ -2734,11 +2735,11 @@ typedef struct _SENSE_DATA { ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to ** access the internal 80331 memory-mapped registers. ** 11:00 000H Reserved -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C */ +#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /* dword 0x9F,0x9E,0x9D,0x9C */ /* -*********************************************************************************** +*************************************************************************** ** Outbound Configuration Cycle Address Register - OCCAR ** ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration @@ -2755,11 +2756,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound configuration read or write cycle. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4 */ +#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /* dword 0xA7,0xA6,0xA5,0xA4 */ /* -*********************************************************************************** +*************************************************************************** ** Outbound Configuration Cycle Data Register - OCCDR ** ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write @@ -2774,11 +2775,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read or write cycle. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC */ +#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /* dword 0xAF,0xAE,0xAD,0xAC */ /* -*********************************************************************************** +*************************************************************************** ** VPD Capability Identifier Register - VPD_CAPID ** ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, @@ -2788,11 +2789,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 03H Cap_Id - This field with its¡¦ 03H value identifies this item in the linked list of Extended Capability Headers as being the VPD capability registers. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte */ +#define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** VPD Next Item Pointer Register - VPD_NXTP ** ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, @@ -2803,11 +2804,11 @@ typedef struct _SENSE_DATA { ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the ** next item in the function¡¦s capability list. Since the VPD capabilities are the last in the linked list of ** extended capabilities in the 80331, the register is set to 00H. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte */ +#define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** VPD Address Register - VPD_AR ** ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be @@ -2822,22 +2823,22 @@ typedef struct _SENSE_DATA { ** how the 80331 handles the data transfer. ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write ** Vital Product Data from the VPD storage component. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA */ +#define ARCMSR_VPD_ADDRESS_REG 0xBA /* word 0xBB,0xBA */ /* -*********************************************************************************** +*************************************************************************** ** VPD Data Register - VPD_DR ** ** This register is used to transfer data between the 80331 and the VPD storage component. ** ----------------------------------------------------------------- ** Bit Default Description ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC */ +#define ARCMSR_VPD_DATA_REG 0xBC /* dword 0xBF,0xBE,0xBD,0xBC */ /* -*********************************************************************************** +*************************************************************************** ** Power Management Capability Identifier Register -PM_CAPID ** ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, @@ -2848,11 +2849,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 01H Cap_Id - This field with its¡¦ 01H value identifies this item in the linked list of Extended Capability Headers as being the PCI Power Management Registers. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte */ +#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** Power Management Next Item Pointer Register - PM_NXTP ** ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, @@ -2862,11 +2863,11 @@ typedef struct _SENSE_DATA { ** Bit Default Description ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the ** next item in the function¡¦s capability list which in the 80331 is the MSI extended capabilities header. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte */ +#define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** Power Management Capabilities Register - PM_CAP ** ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management @@ -2884,11 +2885,11 @@ typedef struct _SENSE_DATA { ** 4 0 2 Reserved. ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management Interface Specification, Revision 1.1 -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2 */ +#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /* word 0xC3,0xC2 */ /* -*********************************************************************************** +*************************************************************************** ** Power Management Control/Status Register - PM_CSR ** ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power @@ -2901,17 +2902,17 @@ typedef struct _SENSE_DATA { ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# generation from any power state. ** 7:2 000000 2 Reserved ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the values is: -** 00 2 - D0 -** 01 2 - D1 -** 10 2 - D2 (Unsupported) -** 11 2 - D3 hot -** The 80331 supports only the D0 and D3 hot states. +** 00 2 - D0 +** 01 2 - D1 +** 10 2 - D2 (Unsupported) +** 11 2 - D3 hot +** The 80331 supports only the D0 and D3 hot states. ** -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4 */ +#define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /* word 0xC5,0xC4 */ /* -*********************************************************************************** +*************************************************************************** ** PCI-X Capability Identifier Register - PX_CAPID ** ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, @@ -2921,11 +2922,11 @@ typedef struct _SENSE_DATA { ** ----------------------------------------------------------------- ** Bit Default Description ** 07:00 07H Cap_Id - This field with its¡¦ 07H value identifies this item in the linked list of Extended Capability Headers as being the PCI-X capability registers. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte */ +#define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** PCI-X Next Item Pointer Register - PX_NXTP ** ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, @@ -2943,16 +2944,16 @@ typedef struct _SENSE_DATA { ** PCSR¡¨ on page 253 for more details on the 80331 initialization modes. ** ----------------------------------------------------------------- ** Bit Default Description -** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the -** next item in the function¡¦s capability list. Since the PCI-X capabilities are the last in the linked list of -** extended capabilities in the 80331, the register is set to 00H. -** However, this field may be written prior to host configuration with B8H to extend the list to include the -** VPD extended capabilities header. -*********************************************************************************** +** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function's configuration space pointing to the +** next item in the function's capability list. Since the PCI-X capabilities are the last in the linked list of +** extended capabilities in the 80331, the register is set to 00H. +** However, this field may be written prior to host configuration with B8H to extend the list to include the +** VPD extended capabilities header. +*************************************************************************** */ -#define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte */ +#define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /* byte */ /* -*********************************************************************************** +*************************************************************************** ** PCI-X Command Register - PX_CMD ** ** This register controls various modes and features of ATU and Message Unit when operating in the @@ -2984,11 +2985,11 @@ typedef struct _SENSE_DATA { ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. -*********************************************************************************** +*************************************************************************** */ -#define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2 */ +#define ARCMSR_PCIX_COMMAND_REG 0xE2 /* word 0xE3,0xE2 */ /* -*********************************************************************************** +*************************************************************************** ** PCI-X Status Register - PX_SR ** ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message @@ -3011,7 +3012,7 @@ typedef struct _SENSE_DATA { ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up to 1024 bytes. ** 20 1 2 80331 is a complex device. -** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device¡¦s +** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device's ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. ** 0=no unexpected Split Completion has been received. ** 1=an unexpected Split Completion has been received. @@ -3060,7 +3061,7 @@ typedef struct _SENSE_DATA { ** ************************************************************************** */ -#define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4 */ +#define ARCMSR_PCIX_STATUS_RE 0xE4 /* dword 0xE7,0xE6,0xE5,0xE4 */ /* ************************************************************************** ** Inbound Read Transaction @@ -3518,8 +3519,8 @@ typedef struct _SENSE_DATA { ** When written, an interrupt to the Intel XScale core may be generated. ************************************************************************** */ -#define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10 */ -#define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14 */ +#define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /* dword 0x13,0x12,0x11,0x10 */ +#define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /* dword 0x17,0x16,0x15,0x14 */ /* ************************************************************************** ** Outbound Message Register - OMRx @@ -3534,8 +3535,8 @@ typedef struct _SENSE_DATA { ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. ************************************************************************** */ -#define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18 */ -#define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C */ +#define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /* dword 0x1B,0x1A,0x19,0x18 */ +#define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /* dword 0x1F,0x1E,0x1D,0x1C */ /* ************************************************************************** ** Doorbell Registers @@ -3576,7 +3577,7 @@ typedef struct _SENSE_DATA { ** When all bits are clear, do not generate a Normal Interrupt. ************************************************************************** */ -#define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20 */ +#define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /* dword 0x23,0x22,0x21,0x20 */ /* ************************************************************************** ** Inbound Interrupt Status Register - IISR @@ -3609,14 +3610,14 @@ typedef struct _SENSE_DATA { ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. ************************************************************************** */ -#define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24 */ -#define ARCMSR_MU_INBOUND_INDEX_INT 0x40 -#define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 -#define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 -#define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 -#define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 -#define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 -#define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 +#define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /* dword 0x27,0x26,0x25,0x24 */ +#define ARCMSR_MU_INBOUND_INDEX_INT 0x40 +#define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 +#define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 +#define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 +#define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 +#define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 +#define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 /* ************************************************************************** ** Inbound Interrupt Mask Register - IIMR @@ -3637,14 +3638,14 @@ typedef struct _SENSE_DATA { ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. ************************************************************************** */ -#define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28 */ -#define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 -#define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 -#define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 -#define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 -#define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 -#define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 -#define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 +#define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /* dword 0x2B,0x2A,0x29,0x28 */ +#define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 +#define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 +#define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 +#define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 +#define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 +#define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 +#define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 /* ************************************************************************** ** Outbound Doorbell Register - ODR @@ -3670,7 +3671,7 @@ typedef struct _SENSE_DATA { ** signal is deasserted. ************************************************************************** */ -#define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C //dword 0x2F,0x2E,0x2D,0x2C// +#define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /* dword 0x2F,0x2E,0x2D,0x2C */ /* ************************************************************************** ** Outbound Interrupt Status Register - OISR @@ -3697,13 +3698,13 @@ typedef struct _SENSE_DATA { ** written. Clearing this bit clears the interrupt. ************************************************************************** */ -#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 //dword 0x33,0x32,0x31,0x30// -#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 -#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 -#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 -#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 -#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 -#define ARCMSR_MU_OUTBOUND_HANDLE_INT (ARCMSR_MU_OUTBOUND_MESSAGE0_INT|ARCMSR_MU_OUTBOUND_MESSAGE1_INT|ARCMSR_MU_OUTBOUND_DOORBELL_INT|ARCMSR_MU_OUTBOUND_POSTQUEUE_INT|ARCMSR_MU_OUTBOUND_PCI_INT) +#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /* dword 0x33,0x32,0x31,0x30 */ +#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 +#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 +#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 +#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 +#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 +#define ARCMSR_MU_OUTBOUND_HANDLE_INT (ARCMSR_MU_OUTBOUND_MESSAGE0_INT|ARCMSR_MU_OUTBOUND_MESSAGE1_INT|ARCMSR_MU_OUTBOUND_DOORBELL_INT|ARCMSR_MU_OUTBOUND_POSTQUEUE_INT|ARCMSR_MU_OUTBOUND_PCI_INT) /* ************************************************************************** ** Outbound Interrupt Mask Register - OIMR @@ -3728,20 +3729,20 @@ typedef struct _SENSE_DATA { ** generated by a write to the Outbound Message 0 Register. ************************************************************************** */ -#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 //dword 0x37,0x36,0x35,0x34// -#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 -#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 -#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 -#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 -#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 -#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F +#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /* dword 0x37,0x36,0x35,0x34 */ +#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 +#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 +#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 +#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 +#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 +#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F /* ************************************************************************** ** ************************************************************************** */ -#define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 //dword 0x43,0x42,0x41,0x40// -#define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 //dword 0x47,0x46,0x45,0x44// +#define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /* dword 0x43,0x42,0x41,0x40 */ +#define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /* dword 0x47,0x46,0x45,0x44 */ /* ************************************************************************** ** Circular Queues @@ -3762,7 +3763,7 @@ typedef struct _SENSE_DATA { ** The other inbound queue is designated the Post queue and it contains inbound posted messages. ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. ** -** ============================================================================================================= +** ======================================================================= ** Circular Queue Summary ** _____________________________________________________________________________________________________________ ** | Queue Name | Purpose | Action on PCI Interface| @@ -3793,9 +3794,9 @@ typedef struct _SENSE_DATA { ** does not cause the MU hardware to increment the queue pointers. ** This is treated as when the PCI transaction did not occur. ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. -** ====================================================================================== +** ======================================================================= ** Overview of Circular Queue Operation -** ====================================================================================== +** ======================================================================= ** . The data storage for the circular queues must be provided by the 80331 local memory. ** . The base address of the circular queues is contained in the Queue Base Address Register. ** Each entry in the queue is a 32-bit data value. @@ -3831,7 +3832,7 @@ typedef struct _SENSE_DATA { ** Inbound Post Queue QBAR + Queue Size ** Outbound Post Queue QBAR + 2 * Queue Size ** Outbound Free Queue QBAR + 3 * Queue Size -** =================================================================================== +** ======================================================================= ** Inbound Post Queue ** ------------------ ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. @@ -3853,7 +3854,7 @@ typedef struct _SENSE_DATA { ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), the hardware retries any PCI writes until a slot in the queue becomes available. ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. -** =================================================================================== +** ======================================================================= ** Inbound Free Queue ** ------------------ ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. @@ -3880,7 +3881,7 @@ typedef struct _SENSE_DATA { ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the ** local memory location pointed to by the Inbound Free Head Pointer Register. ** The processor must then increment the Inbound Free Head Pointer Register. -** ================================================================================== +** ======================================================================= ** Outbound Post Queue ** ------------------- ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale @@ -3942,7 +3943,7 @@ typedef struct _SENSE_DATA { ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, ** the hardware must retry any PCI writes until a slot in the queue becomes available. ** -** ================================================================================== +** ======================================================================= ** Circular Queue Summary ** ---------------------- ** ________________________________________________________________________________________________________________________________________________ @@ -3954,7 +3955,7 @@ typedef struct _SENSE_DATA { ** |Inbound Free | Inbound Queue | | | | | ** | Queue | Port | NO | NO | Intel XScale | MU hardware | ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| -** ================================================================================== +** ======================================================================== ** Circular Queue Status Summary ** ---------------------- ** ____________________________________________________________________________________________________ @@ -4055,13 +4056,13 @@ typedef struct _SENSE_DATA { ** disabled. When set, the Circular Queues are fully enabled. ************************************************************************** */ -#define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 -#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 -#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 -#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 -#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 -#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 -#define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable */ +#define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 +#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 +#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 +#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 +#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 +#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 +#define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /* 0:disable 1:enable */ /* ************************************************************************** ** Queue Base Address Register - QBAR @@ -4160,9 +4161,10 @@ typedef struct _SENSE_DATA { ** 01:00 00 2 Reserved ************************************************************************** */ -#define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF */ +#define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 + /* 1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF */ /* -********************************************************************************************************** +*************************************************************************** ** RS-232 Interface for Areca Raid Controller ** The low level command interface is exclusive with VT100 terminal ** -------------------------------------------------------------------- @@ -4237,7 +4239,7 @@ typedef struct _SENSE_DATA { ** GUI_STOP_CHECK_VOLUME ** }; ** -** Command description : +** Command description: ** ** GUI_SET_SERIAL : Set the controller serial# ** byte 0,1 : length @@ -4556,7 +4558,7 @@ typedef struct _SENSE_DATA { ** byte 2 : command code 0x52 ** byte 3 : raidset# ** byte 4/5/6/7 : device mask for expansion -** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) +** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate; 9:new raid level; 10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) ** byte 11/12/13 : repeat for each volume in the raidset .... ** ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set @@ -4625,7 +4627,7 @@ typedef struct _SENSE_DATA { ** --------------------------------------------------------------------- ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) -** (C) status or data : +** (C) status or data: ** <1> If length == 1 ==> 1 byte status code ** #define GUI_OK 0x41 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 diff -puN drivers/scsi/arcmsr/arcmsr.txt~areca-raid-driver-arcmsr-cleanups drivers/scsi/arcmsr/arcmsr.txt --- devel/drivers/scsi/arcmsr/arcmsr.txt~areca-raid-driver-arcmsr-cleanups 2006-01-07 00:16:26.000000000 -0800 +++ devel-akpm/drivers/scsi/arcmsr/arcmsr.txt 2006-01-07 00:16:26.000000000 -0800 @@ -27,9 +27,9 @@ README file for the arcmsr RAID controll ** 1.20.00.07 3/23/2005 Erich Chen bug fix with arcmsr_scsi_host_template_init occur segmentation fault, ** if RAID adapter does not on PCI slot and modprobe/rmmod this driver twice. ** bug fix enormous stack usage (Adrian Bunk's comment) -** 1.20.00.08 6/23/2005 Erich Chen bug fix with abort command,in case of heavy loading when sata cable +** 1.20.00.08 6/23/2005 Erich Chen bug fix with abort command, in case of heavy loading when sata cable ** working on low quality connection -** 1.20.00.09 9/12/2005 Erich Chen bug fix with abort command handling,firmware version check +** 1.20.00.09 9/12/2005 Erich Chen bug fix with abort command handling, firmware version check ** and firmware update notify for hardware bug fix ** 1.20.00.10 9/23/2005 Erich Chen enhance sysfs function for change driver's max tag Q number. ** add DMA_64BIT_MASK for backward compatible with all 2.6.x @@ -80,15 +80,15 @@ config SCSI_ARCMSR tristate "ARECA ARC11X0[PCI-X]/ARC12X0[PCI-EXPRESS] SATA-RAID support" depends on PCI && SCSI help - This driver supports all of ARECA's SATA RAID controllers cards. - This is an ARECA maintained driver by Erich Chen. + This driver supports all of ARECA's SATA RAID controller cards. + This is an ARECA-maintained driver by Erich Chen. If you have any problems, please mail to: < erich@areca.com.tw > - Areca have suport Linux RAID config tools + Areca supports Linux RAID config tools. < http://www.areca.com.tw > To compile this driver as a module, choose M here: the - module will be called arcmsr (modprobe arcmsr) . + module will be called arcmsr (modprobe arcmsr). .... ... @@ -115,25 +115,25 @@ Copyright ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ** GNU General Public License for more details. ************************************************************************ -** Redistribution and use in source and binary forms,with or without -** modification,are permitted provided that the following conditions +** Redistribution and use in source and binary forms, with or without +** modification, are permitted provided that the following conditions ** are met: ** 1. Redistributions of source code must retain the above copyright -** notice,this list of conditions and the following disclaimer. +** notice, this list of conditions and the following disclaimer. ** 2. Redistributions in binary form must reproduce the above copyright -** notice,this list of conditions and the following disclaimer in the +** notice, this list of conditions and the following disclaimer in the ** documentation and/or other materials provided with the distribution. ** 3. The name of the author may not be used to endorse or promote products ** derived from this software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, -** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT -** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY -** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT +** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT +** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY +** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF -** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ************************************************************************** diff -puN drivers/scsi/arcmsr/Makefile~areca-raid-driver-arcmsr-cleanups drivers/scsi/arcmsr/Makefile --- devel/drivers/scsi/arcmsr/Makefile~areca-raid-driver-arcmsr-cleanups 2006-01-07 00:16:26.000000000 -0800 +++ devel-akpm/drivers/scsi/arcmsr/Makefile 2006-01-07 00:16:26.000000000 -0800 @@ -2,7 +2,3 @@ # Makefile for the ARECA PCI-X PCI-EXPRESS SATA RAID controllers SCSI driver. obj-$(CONFIG_SCSI_ARCMSR) := arcmsr.o - -EXTRA_CFLAGS += -I. - - diff -puN drivers/scsi/Kconfig~areca-raid-driver-arcmsr-cleanups drivers/scsi/Kconfig --- devel/drivers/scsi/Kconfig~areca-raid-driver-arcmsr-cleanups 2006-01-07 00:16:26.000000000 -0800 +++ devel-akpm/drivers/scsi/Kconfig 2006-01-07 00:16:26.000000000 -0800 @@ -424,20 +424,6 @@ config SCSI_AIC7XXX_OLD source "drivers/scsi/aic7xxx/Kconfig.aic79xx" -config SCSI_ARCMSR - tristate "ARECA ARC11X0[PCI-X]/ARC12X0[PCI-EXPRESS] SATA-RAID support" - depends on PCI && SCSI - help - This driver supports all of ARECA's SATA RAID controllers cards. - This is an ARECA maintained driver by Erich Chen. - If you have any problems, please mail to: < erich@areca.com.tw > - Areca have suport Linux RAID config tools - - < http://www.areca.com.tw > - - To compile this driver as a module, choose M here: the - module will be called arcmsr (modprobe arcmsr) . - # All the I2O code and drivers do not seem to be 64bit safe. config SCSI_DPT_I2O tristate "Adaptec I2O RAID support " @@ -473,6 +459,20 @@ config SCSI_IN2000 To compile this driver as a module, choose M here: the module will be called in2000. +config SCSI_ARCMSR + tristate "ARECA ARC11X0[PCI-X]/ARC12X0[PCI-EXPRESS] SATA-RAID support" + depends on PCI && SCSI + help + This driver supports all of ARECA's SATA RAID controller cards. + This is an ARECA-maintained driver by Erich Chen. + If you have any problems, please mail to: < erich@areca.com.tw > + Areca supports Linux RAID config tools. + + < http://www.areca.com.tw > + + To compile this driver as a module, choose M here: the + module will be called arcmsr (modprobe arcmsr). + source "drivers/scsi/megaraid/Kconfig.megaraid" config SCSI_SATA _