From: David Vrabel <dvrabel@arcom.com>

Add support for rev.  1 Geode GXes.  Unfortunatly, I don't have access to
such hardware so it's not tested.  It's taken from AMD's original 2.4
driver so it should be fine...

Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---

 drivers/video/geode/video_gx.c |   61 ++++++++++++++++++++++++++-----
 1 files changed, 53 insertions(+), 8 deletions(-)

diff -puN drivers/video/geode/video_gx.c~fbdev-framebuffer-driver-for-geode-gx-update drivers/video/geode/video_gx.c
--- devel/drivers/video/geode/video_gx.c~fbdev-framebuffer-driver-for-geode-gx-update	2006-02-09 02:36:12.000000000 -0800
+++ devel-akpm/drivers/video/geode/video_gx.c	2006-02-09 02:36:12.000000000 -0800
@@ -34,7 +34,7 @@ struct gx_pll_entry {
 #define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
 #define PREDIV2  ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
 
-struct gx_pll_entry gx_pll_table_48MHz[] = {
+static const struct gx_pll_entry gx_pll_table_48MHz[] = {
 	{ 40123, POSTDIV3,	    0x00000BF2 },	/*  24.9230 */
 	{ 39721, 0,		    0x00000037 },	/*  25.1750 */
 	{ 35308, POSTDIV3|PREMULT2, 0x00000B1A },	/*  28.3220 */
@@ -77,24 +77,69 @@ struct gx_pll_entry gx_pll_table_48MHz[]
 	{  4357, 0,		    0x0000057D },	/* 229.5000 */
 };
 
+static const struct gx_pll_entry gx_pll_table_14MHz[] = {
+	{ 39721, 0, 0x00000037 },	/*  25.1750 */
+	{ 35308, 0, 0x00000B7B },	/*  28.3220 */
+	{ 31746, 0, 0x000004D3 },	/*  31.5000 */
+	{ 27777, 0, 0x00000BE3 },	/*  36.0000 */
+	{ 26666, 0, 0x0000074F },	/*  37.5000 */
+	{ 25000, 0, 0x0000050B },	/*  40.0000 */
+	{ 22271, 0, 0x00000063 },	/*  44.9000 */
+	{ 20202, 0, 0x0000054B },	/*  49.5000 */
+	{ 20000, 0, 0x0000026E },	/*  50.0000 */
+	{ 19860, 0, 0x000007C3 },	/*  50.3500 */
+	{ 18518, 0, 0x000007E3 },	/*  54.0000 */
+	{ 17777, 0, 0x00000577 },	/*  56.2500 */
+	{ 17733, 0, 0x000002FB },	/*  56.3916 */
+	{ 17653, 0, 0x0000057B },	/*  56.6444 */
+	{ 16949, 0, 0x0000058B },	/*  59.0000 */
+	{ 15873, 0, 0x0000095E },	/*  63.0000 */
+	{ 15384, 0, 0x0000096A },	/*  65.0000 */
+	{ 14814, 0, 0x00000BC2 },	/*  67.5000 */
+	{ 14124, 0, 0x0000098A },	/*  70.8000 */
+	{ 13888, 0, 0x00000BE2 },	/*  72.0000 */
+	{ 13333, 0, 0x00000052 },	/*  75.0000 */
+	{ 12698, 0, 0x00000056 },	/*  78.7500 */
+	{ 12500, 0, 0x0000050A },	/*  80.0000 */
+	{ 11135, 0, 0x0000078E },	/*  89.8000 */
+	{ 10582, 0, 0x000002D2 },	/*  94.5000 */
+	{ 10101, 0, 0x000011F6 },	/*  99.0000 */
+	{ 10000, 0, 0x0000054E },	/* 100.0000 */
+	{  9259, 0, 0x000007E2 },	/* 108.0000 */
+	{  8888, 0, 0x000002FA },	/* 112.5000 */
+	{  7692, 0, 0x00000BB1 },	/* 130.0000 */
+	{  7407, 0, 0x00000975 },	/* 135.0000 */
+	{  6349, 0, 0x00000055 },	/* 157.5000 */
+	{  6172, 0, 0x000009C1 },	/* 162.0000 */
+	{  5698, 0, 0x000002C1 },	/* 175.5000 */
+	{  5291, 0, 0x00000539 },	/* 189.0000 */
+	{  4938, 0, 0x00000551 },	/* 202.5000 */
+	{  4357, 0, 0x0000057D },	/* 229.5000 */
+};
+
 static void gx_set_dclk_frequency(struct fb_info *info)
 {
 	struct gx_pll_entry *pll_table;
+	int pll_table_len;
 	int i, best_i;
 	long min, diff;
 	u64 dotpll, sys_rstpll;
 	int timeout = 1000;
 
-	/* FIXME: Handle rev 1 Geode GXs with a 14 MHz reference clock */
-	pll_table = gx_pll_table_48MHz;
+	/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
+	if (cpu_data->x86_mask == 1) {
+		pll_table = gx_pll_table_14MHz;
+		pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
+	} else {
+		pll_table = gx_pll_table_48MHz;
+		pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
+	}
 
 	/* Search the table for the closest pixclock. */
 	best_i = 0;
-	min = pll_table[0].pixclock - info->var.pixclock;
-	if (min < 0) min = -min;
-	for (i = 1; i < ARRAY_SIZE(gx_pll_table_48MHz); i++) {
-		diff = pll_table[i].pixclock - info->var.pixclock;
-		if (diff < 0L) diff = -diff;
+	min = abs(pll_table[0].pixclock - info->var.pixclock);
+	for (i = 1; i < pll_table_len; i++) {
+		diff = abs(pll_table[i].pixclock - info->var.pixclock);
 		if (diff < min) {
 			min = diff;
 			best_i = i;
_