From owner-linux-pci@atrey.karlin.mff.cuni.cz Tue Oct 10 07:01:47 2006 From: Matthew Wilcox To: Greg Kroah-Hartman Cc: linux-pci@atrey.karlin.mff.cuni.cz, Matthew Wilcox Subject: PCI: Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWI Date: Tue, 10 Oct 2006 08:01:21 -0600 Message-Id: <11604888833435-git-send-email-matthew@wil.cx> From: Matthew Wilcox pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's really inappropriate for its needs. It really wants to disable MWI altogether. So here are a pair of stub implementations for pci_set_mwi and pci_clear_mwi. Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that better reflects what it does. Signed-off-by: Matthew Wilcox Cc: Paul Mackerras Acked-by: Jeff Garzik Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci.c | 31 ++++++++++++++++++------------- include/asm-powerpc/pci.h | 20 +++++++------------- 2 files changed, 25 insertions(+), 26 deletions(-) --- gregkh-2.6.orig/drivers/pci/pci.c +++ gregkh-2.6/drivers/pci/pci.c @@ -831,7 +831,17 @@ pci_set_master(struct pci_dev *dev) pcibios_set_master(dev); } -#ifndef HAVE_ARCH_PCI_MWI +#ifdef PCI_DISABLE_MWI +int pci_set_mwi(struct pci_dev *dev) +{ + return 0; +} + +void pci_clear_mwi(struct pci_dev *dev) +{ +} + +#else #ifndef PCI_CACHE_LINE_BYTES #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES @@ -842,17 +852,17 @@ pci_set_master(struct pci_dev *dev) u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; /** - * pci_generic_prep_mwi - helper function for pci_set_mwi - * @dev: the PCI device for which MWI is enabled + * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed + * @dev: the PCI device for which MWI is to be enabled * - * Helper function for generic implementation of pcibios_prep_mwi - * function. Originally copied from drivers/net/acenic.c. + * Helper function for pci_set_mwi. + * Originally copied from drivers/net/acenic.c. * Copyright 1998-2001 by Jes Sorensen, . * * RETURNS: An appropriate -ERRNO error value on error, or zero for success. */ static int -pci_generic_prep_mwi(struct pci_dev *dev) +pci_set_cacheline_size(struct pci_dev *dev) { u8 cacheline_size; @@ -878,7 +888,6 @@ pci_generic_prep_mwi(struct pci_dev *dev return -EINVAL; } -#endif /* !HAVE_ARCH_PCI_MWI */ /** * pci_set_mwi - enables memory-write-invalidate PCI transaction @@ -896,12 +905,7 @@ pci_set_mwi(struct pci_dev *dev) int rc; u16 cmd; -#ifdef HAVE_ARCH_PCI_MWI - rc = pcibios_prep_mwi(dev); -#else - rc = pci_generic_prep_mwi(dev); -#endif - + rc = pci_set_cacheline_size(dev); if (rc) return rc; @@ -932,6 +936,7 @@ pci_clear_mwi(struct pci_dev *dev) pci_write_config_word(dev, PCI_COMMAND, cmd); } } +#endif /* ! PCI_DISABLE_MWI */ /** * pci_intx - enables/disables PCI INTx for device dev --- gregkh-2.6.orig/include/asm-powerpc/pci.h +++ gregkh-2.6/include/asm-powerpc/pci.h @@ -62,19 +62,13 @@ static inline int pci_get_legacy_ide_irq } #ifdef CONFIG_PPC64 -#define HAVE_ARCH_PCI_MWI 1 -static inline int pcibios_prep_mwi(struct pci_dev *dev) -{ - /* - * We would like to avoid touching the cacheline size or MWI bit - * but we cant do that with the current pcibios_prep_mwi - * interface. pSeries firmware sets the cacheline size (which is not - * the cpu cacheline size in all cases) and hardware treats MWI - * the same as memory write. So we dont touch the cacheline size - * here and allow the generic code to set the MWI bit. - */ - return 0; -} + +/* + * We want to avoid touching the cacheline size or MWI bit. + * pSeries firmware sets the cacheline size (which is not the cpu cacheline + * size in all cases) and hardware treats MWI the same as memory write. + */ +#define PCI_DISABLE_MWI extern struct dma_mapping_ops pci_dma_ops;