GIT 71074d3a2c70aa8a213222fef5014bfd9b3daf1f git+ssh://master.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git commit Author: Paul Mundt Date: Wed Feb 14 14:49:04 2007 +0900 sh: Fixup r7780rp pata_platform for devres conversion. Tidy up the R7780RP I/O mapping routines and switch the pata_platform resources to IORESOURCE_MEM types, killing off the useless port->addr conversion. This fixes up R7780RP to boot after the recent devres conversion. Signed-off-by: Paul Mundt commit db2e1fa3f0eefbbe04e90d6e4d290ee176b28248 Author: Paul Mundt Date: Wed Feb 14 14:13:10 2007 +0900 sh: Revert TLB miss fast-path changes that broke PTEA parts. This ended up causing problems for older parts (particularly ones using PTEA). Revert this for now, it can be added back in once it's had some more testing. Signed-off-by: Paul Mundt commit 401e9093a326725780aed270a6eb53e7ddab14ff Author: Paul Mundt Date: Tue Feb 13 15:46:39 2007 +0900 sh: Compile fix for heartbeat consolidation. Signed-off-by: Paul Mundt commit 3b4d9539628502768fe7f8fd4b48f2fbf2426255 Author: Paul Mundt Date: Tue Feb 13 15:42:28 2007 +0900 sh: heartbeat consolidation for banked LEDs. This consolidates the various board heartbeat LED implementations, used for strobing the load average across a LED bank. Those boards not implementing a full bank can hook in via the LED class. We leave the compat hook in the machvec for now until those non-banked boards are able to migrate to the drivers/leds. Signed-off-by: Paul Mundt commit c7666e72cff1a2793055486340ac5f5137494c08 Author: Paul Mundt Date: Tue Feb 13 11:11:22 2007 +0900 sh: define dma noncoherent API functions. sh was missing these, too. Signed-off-by: Paul Mundt commit fe8289175059a807094ba962828318910ea08a37 Author: Paul Mundt Date: Tue Feb 13 11:09:15 2007 +0900 sh: Missing flush_dcache_all() proto in cacheflush.h. Some boards need this, so provide a definition. Signed-off-by: Paul Mundt commit ca43ecbf6e5c7216152e5a388f2ecdd87e07a293 Author: Paul Mundt Date: Wed Feb 7 21:27:50 2007 +0900 sh: Kill dead/unused ISA code from __ioremap(). Signed-off-by: Paul Mundt commit f5df54dc2e1dce80eb7fb45f3f6d5ce096d911f3 Author: Paul Mundt Date: Wed Feb 7 20:00:01 2007 +0900 sh: Add cpu-features header to asm/Kbuild. This is used by the libc for parsing CPU capability flags passed via the ELF auxvt, needed for run-time selection of atomic opcodes amongst other things. Signed-off-by: Paul Mundt commit a5ba7d545364b85c3a97f65d328be55ca933a9c7 Author: Paul Mundt Date: Wed Feb 7 19:58:07 2007 +0900 sh: Move __KERNEL__ up in asm/page.h. This was breaking the uClibc build, which triggered the bogus page size error. Signed-off-by: Paul Mundt commit b37814352d2c4b83e0636e57f997c3a79d33be05 Author: Paul Mundt Date: Wed Feb 7 19:11:35 2007 +0900 sh: Fix syscall numbering breakage. We accidentally broke the inotify syscalls, fix those up again. Signed-off-by: Paul Mundt commit 5904539b7f21ae97f16278ea4bfb81fd19749e1a Author: Paul Mundt Date: Wed Feb 7 18:35:39 2007 +0900 sh: dcache write-back for R7780RP PIO. Signed-off-by: Paul Mundt commit 0072032d7babc4347556c1863919f3c532d9cf5b Author: Paul Mundt Date: Mon Dec 25 19:37:56 2006 +0900 sh: Switch to local TLB flush variants in additional callsites. Convert some of the global flush users over to using the local variants that don't need to use the global routines. Signed-off-by: Paul Mundt commit ea9af69481730e3d712104dfd549ba6c8ddd29f1 Author: Paul Mundt Date: Mon Dec 25 19:28:54 2006 +0900 sh: Local TLB flushing variants for SMP prep. Rename the existing flush routines to local_ variants for use by the IPI-backed global flush routines on SMP. Signed-off-by: Paul Mundt commit 11c1965687b0a472add948d4240dfe65a2fcb298 Author: Paul Mundt Date: Mon Dec 25 10:19:56 2006 +0900 sh: Fixup cpu_data references for the non-boot CPUs. There are a lot of bogus cpu_data-> references that only end up working for the boot CPU, convert these to current_cpu_data to fixup SMP. Signed-off-by: Paul Mundt commit aec5e0e1c179fac4bbca4007a3f0d3107275a73c Author: Paul Mundt Date: Mon Dec 25 09:51:47 2006 +0900 sh: Use a per-cpu ASID cache. Previously this was implemented using a global cache, cache this per-CPU instead and bump up the number of context IDs to match NR_CPUS. Signed-off-by: Paul Mundt commit 506b85f4114b912d2e91fab8da9849289e43857f Author: Andrew Morton Date: Wed Feb 7 13:56:44 2007 +0900 sh: add SH_CLK_MD Kconfig default. This option needs a default - otherwise `make allmodconfig' gets stuck in an infinite loop. Signed-off-by: Andrew Morton Signed-off-by: Paul Mundt commit dbbfa2da27fbf353caa8934768afbbf8d5e73d9b Author: Nobuhiro Iwamatsu Date: Wed Feb 7 13:54:39 2007 +0900 sh: Fixup SHMIN INTC register definitions. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt commit 9f8a5e3a44d81bbf19fddeb74645dec6b0e23b23 Author: Manuel Lauss Date: Thu Jan 25 15:22:11 2007 +0900 sh: SH-DMAC compile fixes This patch does the following: - remove the make_ipr_irq stuff from dma-sh.c and replace it with a simple channel<->irq mapping table. - add DMTEx_IRQ constants for sh4 cpus - fix sh7751 DMAE irq number The SH7780 uses the same IRQs for DMA as other SH4 types, so I put the constants on top of the dma.h file. Other CPU types need to #define their own DMTEx_IRQ contants in their appropriate header. Signed-off-by: Manuel Lauss Signed-off-by: Paul Mundt commit 6dcda6f1ecef86209ac161631837bc57172ba049 Author: Manuel Lauss Date: Thu Jan 25 15:21:03 2007 +0900 sh: add SH7760 IPR IRQ data Add SH7760 IPR IRQ data; makes 2.6.20-rc bootable again. Signed-off-by: Manuel Lauss Signed-off-by: Paul Mundt commit 86b67ef7518d1fcd4489dc464d4c33a274a1c635 Author: Nobuhiro Iwamatsu Date: Mon Jan 1 09:21:43 2007 +0900 sh: Fix handle_BUG() compile error. handle_BUG() uses TRAPA_BUG_OPCODE which is only defined for CONFIG_BUG, make sure it's not built when CONFIG_BUG=n. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt commit adac9570966eb2eb137209e552b258d4d1d4825b Author: Paul Mundt Date: Thu Dec 28 10:54:01 2006 +0900 sh: Don't set reserved _PAGE_WT bit on SH-3. Only SH-4 needs to set _PAGE_WT when using write-through caching, don't attempt to set it on SH-3 where it ends up being a reserved bit. Signed-off-by: Paul Mundt commit 26b7a78c55fbc0e23a7dc19e89fd50f200efc002 Author: Paul Mundt Date: Thu Dec 28 10:31:48 2006 +0900 sh: Lazy dcache writeback optimizations. This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt commit 7a847f819063b80cc5b38d39e8aad4d60f6ca2fd Author: Paul Mundt Date: Tue Dec 26 15:29:19 2006 +0900 sh: More tidying for large base pages. There were a few more things that needed fixing up, namely THREAD_SIZE and the TLB miss handler where certain PTRS_PER_PGD == PTRS_PER_PTE assumptions were being made. Signed-off-by: Paul Mundt commit aa4a5db52a440d32eab134bfb79d2c9af71eedb4 Author: Nobuhiro Iwamatsu Date: Fri Dec 29 01:50:35 2006 +0900 sh: Solution Engine 770x IPR irq setup. Fixups for external IPR IRQs for the SE770x FPGA. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt commit 08d2e099fb19ec2edef548a2988c824c8ec0b071 Author: Nobuhiro Iwamatsu Date: Fri Dec 29 01:44:32 2006 +0900 sh: Solution Engine 7750's defconfig update. Update se7750_defconfig. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt commit f725b5ee1e392ab1299c9317236cf736af1183ab Author: Takashi YOSHII Date: Mon Dec 25 18:35:24 2006 +0900 sh: shmin updates. This fixes up shmin (and SH7706/SH7708) IPR support for some of the recent API changes. Signed-off-by: Takashi YOSHII Signed-off-by: Paul Mundt commit 2c081e71baadccb4543815ef42c5290ac2961546 Author: Paul Mundt Date: Mon Dec 25 18:28:33 2006 +0900 sh: Fixup R7780RP iVDR clock enable. The iVDR clock enable bit happens to actually reside in a rather different place than what is documented, so fix it up accordingly. This fixes up SATA boot for some of the R7780RP boards that didn't default-enable the clock in the loader. Signed-off-by: Paul Mundt commit 703404ea441fc198d03ca3e9edbac6e09b5415f4 Author: Jamie Lenehan Date: Tue Dec 19 12:16:06 2006 +0900 sh: allow earlyprintk baud rate to be set via command line This allows the baud rate for earlyprintk for sh4 without the standard BIOS to be set via the command line. This uses the same format as i386 and x86_64, which is: earlyprintk=serial,ttySC1,38400 The second parameter (ttySC1 above) is usually the console device name or the io address of the serial port. I allow that to be specified but ignore it in order to keep the format the same as i386/x86_64. Signed-off-by: Jamie Lenehan Signed-off-by: Paul Mundt commit 106dac130d6fb6670a0bbfa8c714054990b41b03 Author: SUGIOKA Toshinobu Date: Tue Dec 19 12:13:55 2006 +0900 sh: syscall 300 should be __NR_fstatat64. syscall number 300 fails while testing with latest LTP (ltp-full-20061121.tgz) on sh. sys_fstatat64 is called on syscall 300 (see arch/sh/kernel/syscalls.S), and __ARCH_WANT_STAT64 is defined in include/asm-sh/unistd.h, so following patch seems correct. Signed-off-by: SUGIOKA Toshinobu Signed-off-by: Paul Mundt commit 5c67cd05e3e9b6f08c3472dd66f0d8d03e1ee870 Author: Yoshinori Sato Date: Tue Dec 19 12:12:01 2006 +0900 sh: sh7619 / sh7206 IPR initialize update IPR initialize proceduere update. Signed-off-by: Yoshinori Sato Signed-off-by: Paul Mundt commit 4aa362bbdd801dd971acbe3db479fe871f2fed0b Author: Yoshinori Sato Date: Tue Dec 19 12:10:48 2006 +0900 sh: Update SH-2 to use the debug trap jump table. Signed-off-by: Yoshinori Sato Signed-off-by: Paul Mundt commit 702dd80375046d36f892a0f86c83f8549c623b35 Author: Paul Mundt Date: Tue Dec 19 12:05:17 2006 +0900 sh: Use proper SH-2A CFLAGS on newer compilers. -m2 doesn't end up working particularly well when we've got a constrained toolchain target. Switch to the same semantics used by SH-4A to attempt to get it right. Spotted by Alex Song . Signed-off-by: Paul Mundt commit f413d0d9fa7abcecc40e115cf4aead372d164a75 Author: Paul Mundt Date: Wed Dec 13 17:40:05 2006 +0900 sh: Use a jump call table for debug trap handlers. This rips out most of the needlessly complicated sh_bios and kgdb trap handling, and forces it all through a common fast dispatch path. As more debug traps are inserted, it's important to keep them in sync for all of the parts, not just SH-3/4. As the SH-2 parts are unable to do traps in the >= 0x40 range, we restrict the debug traps to the 0x30-0x3f range on all parts, and also bump the kgdb breakpoint trap down in to this range (from 0xff to 0x3c) so it's possible to use for nommu. Optionally, this table can be padded out to catch spurious traps for SH-3/4, but we don't do that yet.. Signed-off-by: Paul Mundt arch/sh/Kconfig | 6 + arch/sh/Makefile | 1 arch/sh/boards/mpc1211/Makefile | 2 arch/sh/boards/mpc1211/led.c | 63 --------- arch/sh/boards/mpc1211/setup.c | 31 ++++ arch/sh/boards/renesas/r7780rp/Makefile | 1 arch/sh/boards/renesas/r7780rp/io.c | 152 ++++++--------------- arch/sh/boards/renesas/r7780rp/led.c | 43 ------ arch/sh/boards/renesas/r7780rp/setup.c | 49 +++++-- arch/sh/boards/renesas/rts7751r2d/Makefile | 1 arch/sh/boards/renesas/rts7751r2d/led.c | 44 ------ arch/sh/boards/renesas/rts7751r2d/setup.c | 19 ++- arch/sh/boards/se/7206/Makefile | 2 arch/sh/boards/se/7206/led.c | 57 -------- arch/sh/boards/se/7206/setup.c | 34 ++++- arch/sh/boards/se/7300/Makefile | 2 arch/sh/boards/se/7300/led.c | 54 ------- arch/sh/boards/se/7300/setup.c | 36 ++++- arch/sh/boards/se/73180/Makefile | 2 arch/sh/boards/se/73180/led.c | 53 ------- arch/sh/boards/se/73180/setup.c | 31 ++++ arch/sh/boards/se/7343/Makefile | 2 arch/sh/boards/se/7343/led.c | 44 ------ arch/sh/boards/se/7343/setup.c | 26 +++- arch/sh/boards/se/770x/Makefile | 1 arch/sh/boards/se/770x/irq.c | 108 ++++++++++----- arch/sh/boards/se/770x/led.c | 52 ------- arch/sh/boards/se/770x/setup.c | 43 ++++-- arch/sh/boards/se/7751/Makefile | 1 arch/sh/boards/se/7751/led.c | 51 ------- arch/sh/boards/se/7751/setup.c | 36 ++++- arch/sh/boards/sh03/Makefile | 1 arch/sh/boards/sh03/led.c | 48 ------ arch/sh/boards/sh03/setup.c | 30 ++++ arch/sh/boards/shmin/setup.c | 12 +- arch/sh/configs/se7750_defconfig | 140 ++++++++++++++++--- arch/sh/drivers/Makefile | 1 arch/sh/drivers/dma/dma-sh.c | 45 ++---- arch/sh/drivers/heartbeat.c | 132 ++++++++++++++++++ arch/sh/kernel/Makefile | 3 arch/sh/kernel/cpu/init.c | 41 +++--- arch/sh/kernel/cpu/irq/ipr.c | 19 ++- arch/sh/kernel/cpu/sh2/entry.S | 12 +- arch/sh/kernel/cpu/sh2/probe.c | 32 ++-- arch/sh/kernel/cpu/sh2/setup-sh7619.c | 62 ++++---- arch/sh/kernel/cpu/sh2a/probe.c | 16 +- arch/sh/kernel/cpu/sh2a/setup-sh7206.c | 89 ++++++------ arch/sh/kernel/cpu/sh3/entry.S | 207 +++------------------------- arch/sh/kernel/cpu/sh3/probe.c | 42 +++--- arch/sh/kernel/cpu/sh3/setup-sh7709.c | 21 +++ arch/sh/kernel/cpu/sh4/probe.c | 183 +++++++++++++------------ arch/sh/kernel/cpu/sh4/setup-sh7750.c | 2 arch/sh/kernel/cpu/sh4/setup-sh7760.c | 66 +++++++-- arch/sh/kernel/debugtraps.S | 41 ++++++ arch/sh/kernel/early_printk.c | 24 +++ arch/sh/kernel/entry-common.S | 119 ++++++---------- arch/sh/kernel/kgdb_stub.c | 7 + arch/sh/kernel/process.c | 95 +++++++------ arch/sh/kernel/setup.c | 49 +++---- arch/sh/kernel/sh_ksyms.c | 1 arch/sh/kernel/signal.c | 6 - arch/sh/kernel/syscalls.S | 8 + arch/sh/kernel/traps.c | 4 - arch/sh/mm/Kconfig | 5 + arch/sh/mm/cache-debugfs.c | 4 - arch/sh/mm/cache-sh3.c | 8 + arch/sh/mm/cache-sh4.c | 77 ++++++---- arch/sh/mm/cache-sh7705.c | 29 ++-- arch/sh/mm/fault.c | 87 ++++++++++++ arch/sh/mm/init.c | 7 - arch/sh/mm/ioremap.c | 6 - arch/sh/mm/pg-sh4.c | 28 ---- arch/sh/mm/pg-sh7705.c | 37 +---- arch/sh/mm/tlb-flush.c | 101 +++++++++++--- arch/sh/mm/tlb-nommu.c | 19 +-- arch/sh/mm/tlb-sh3.c | 67 --------- arch/sh/mm/tlb-sh4.c | 70 --------- arch/sh/oprofile/op_model_sh7750.c | 2 include/asm-sh/Kbuild | 2 include/asm-sh/bugs.h | 6 - include/asm-sh/cacheflush.h | 3 include/asm-sh/cpu-sh3/cacheflush.h | 2 include/asm-sh/cpu-sh4/cacheflush.h | 13 -- include/asm-sh/cpu-sh4/dma.h | 11 + include/asm-sh/dma-mapping.h | 4 + include/asm-sh/kgdb.h | 8 + include/asm-sh/mmu.h | 20 +-- include/asm-sh/mmu_context.h | 61 +++++--- include/asm-sh/page.h | 3 include/asm-sh/pgtable.h | 11 - include/asm-sh/processor.h | 6 + include/asm-sh/thread_info.h | 16 ++ include/asm-sh/tlbflush.h | 38 ++++- include/asm-sh/ubc.h | 2 include/asm-sh/unistd.h | 20 +-- 95 files changed, 1616 insertions(+), 1762 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 4f38912..90c8c42 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -481,6 +481,7 @@ config SH_PCLK_FREQ config SH_CLK_MD int "CPU Mode Pin Setting" + default 0 depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206 help MD2 - MD0 pin setting. @@ -511,7 +512,8 @@ config HEARTBEAT bool "Heartbeat LED" depends on SH_MPC1211 || SH_SH03 || \ SH_BIGSUR || SOLUTION_ENGINE || \ - SH_RTS7751R2D || SH_SH4202_MICRODEV || SH_LANDISK + SH_RTS7751R2D || SH_SH4202_MICRODEV || SH_LANDISK || \ + SH_R7780RP help Use the power-on LED on your machine as a load meter. The exact behavior is platform-dependent, but normally the flash frequency is @@ -596,6 +598,8 @@ menu "Boot options" config ZERO_PAGE_OFFSET hex "Zero page offset" default "0x00004000" if SH_MPC1211 || SH_SH03 + default "0x00010000" if PAGE_SIZE_64KB + default "0x00002000" if PAGE_SIZE_8KB default "0x00001000" help This sets the default offset of zero page. diff --git a/arch/sh/Makefile b/arch/sh/Makefile index c1dbef2..4903c7c 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -35,6 +35,7 @@ endif endif cflags-$(CONFIG_CPU_SH2) := -m2 +cflags-$(CONFIG_CPU_SH2A) := -m2a $(call cc-option,-m2a-nofpu,) cflags-$(CONFIG_CPU_SH3) := -m3 cflags-$(CONFIG_CPU_SH4) := -m4 \ $(call cc-option,-mno-implicit-fp,-m4-nofpu) diff --git a/arch/sh/boards/mpc1211/Makefile b/arch/sh/boards/mpc1211/Makefile index 1644ebe..8cd31b5 100644 --- a/arch/sh/boards/mpc1211/Makefile +++ b/arch/sh/boards/mpc1211/Makefile @@ -2,7 +2,7 @@ # # Makefile for the Interface (CTP/PCI/MPC-SH02) specific parts of the kernel # -obj-y := setup.o rtc.o led.o +obj-y := setup.o rtc.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/sh/boards/mpc1211/led.c b/arch/sh/boards/mpc1211/led.c deleted file mode 100644 index 8df1591..0000000 --- a/arch/sh/boards/mpc1211/led.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * linux/arch/sh/boards/mpc1211/led.c - * - * Copyright (C) 2001 Saito.K & Jeanne - * - * This file contains Interface MPC-1211 specific LED code. - */ - - -static void mach_led(int position, int value) -{ - volatile unsigned char* p = (volatile unsigned char*)0xa2000000; - - if (value) { - *p |= 1; - } else { - *p &= ~1; - } -} - -#ifdef CONFIG_HEARTBEAT - -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_mpc1211(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned char* p = (volatile unsigned char*)0xa2000000; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ( (300< #include #include #include +#include #include #include #include @@ -281,6 +282,32 @@ static int put_smb_blk(unsigned char *p, return 0; } +static struct resource heartbeat_resources[] = { + [0] = { + .start = 0xa2000000, + .end = 0xa2000000 + 8 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *mpc1211_devices[] __initdata = { + &heartbeat_device, +}; + +static int __init mpc1211_devices_setup(void) +{ + return platform_add_devices(mpc1211_devices, + ARRAY_SIZE(mpc1211_devices)); +} +__initcall(mpc1211_devices_setup); + /* arch/sh/boards/mpc1211/rtc.c */ void mpc1211_time_init(void); @@ -317,9 +344,5 @@ struct sh_machine_vector mv_mpc1211 __in .mv_nr_irqs = 48, .mv_irq_demux = mpc1211_irq_demux, .mv_init_irq = init_mpc1211_IRQ, - -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_mpc1211, -#endif }; ALIAS_MV(mpc1211) diff --git a/arch/sh/boards/renesas/r7780rp/Makefile b/arch/sh/boards/renesas/r7780rp/Makefile index 574b031..3c93012 100644 --- a/arch/sh/boards/renesas/r7780rp/Makefile +++ b/arch/sh/boards/renesas/r7780rp/Makefile @@ -4,5 +4,4 @@ # obj-y := setup.o io.o irq.o -obj-$(CONFIG_HEARTBEAT) += led.o obj-$(CONFIG_PUSH_SWITCH) += psw.o diff --git a/arch/sh/boards/renesas/r7780rp/io.c b/arch/sh/boards/renesas/r7780rp/io.c index 311cccc..f74d2ff 100644 --- a/arch/sh/boards/renesas/r7780rp/io.c +++ b/arch/sh/boards/renesas/r7780rp/io.c @@ -11,22 +11,9 @@ #include #include #include +#include #include #include -#include - -static inline unsigned long port2adr(unsigned int port) -{ - if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) - if (port == 0x3f6) - return (PA_AREA5_IO + 0x80c); - else - return (PA_AREA5_IO + 0x1000 + ((port-0x1f0) << 1)); - else - maybebadio((unsigned long)port); - - return port; -} static inline unsigned long port88796l(unsigned int port, int flag) { @@ -40,18 +27,6 @@ static inline unsigned long port88796l(u return addr; } -/* The 7780 R7780RP-1 seems to have everything hooked */ -/* up pretty normally (nothing on high-bytes only...) so this */ -/* shouldn't be needed */ -static inline int shifted_port(unsigned long port) -{ - /* For IDE registers, value is not shifted */ - if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) - return 0; - else - return 1; -} - #if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE) #define CHECK_AX88796L_PORT(port) \ ((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20))) @@ -70,12 +45,10 @@ u8 r7780rp_inb(unsigned long port) { if (CHECK_AX88796L_PORT(port)) return ctrl_inw(port88796l(port, 0)) & 0xff; - else if (PXSEG(port)) - return ctrl_inb(port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + else if (is_pci_ioaddr(port)) return ctrl_inb(pci_ioaddr(port)); - return ctrl_inw(port2adr(port)) & 0xff; + return ctrl_inw(port) & 0xff; } u8 r7780rp_inb_p(unsigned long port) @@ -84,12 +57,10 @@ u8 r7780rp_inb_p(unsigned long port) if (CHECK_AX88796L_PORT(port)) v = ctrl_inw(port88796l(port, 0)) & 0xff; - else if (PXSEG(port)) - v = ctrl_inb(port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + else if (is_pci_ioaddr(port)) v = ctrl_inb(pci_ioaddr(port)); else - v = ctrl_inw(port2adr(port)) & 0xff; + v = ctrl_inw(port) & 0xff; ctrl_delay(); @@ -98,80 +69,56 @@ u8 r7780rp_inb_p(unsigned long port) u16 r7780rp_inw(unsigned long port) { - if (CHECK_AX88796L_PORT(port)) - maybebadio(port); - else if (PXSEG(port)) - return ctrl_inw(port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + if (is_pci_ioaddr(port)) return ctrl_inw(pci_ioaddr(port)); - else - maybebadio(port); - return 0; + return ctrl_inw(port); } u32 r7780rp_inl(unsigned long port) { - if (CHECK_AX88796L_PORT(port)) - maybebadio(port); - else if (PXSEG(port)) - return ctrl_inl(port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + if (is_pci_ioaddr(port)) return ctrl_inl(pci_ioaddr(port)); - else - maybebadio(port); - return 0; + return ctrl_inl(port); } void r7780rp_outb(u8 value, unsigned long port) { if (CHECK_AX88796L_PORT(port)) ctrl_outw(value, port88796l(port, 0)); - else if (PXSEG(port)) - ctrl_outb(value, port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + else if (is_pci_ioaddr(port)) ctrl_outb(value, pci_ioaddr(port)); else - ctrl_outw(value, port2adr(port)); + ctrl_outb(value, port); } void r7780rp_outb_p(u8 value, unsigned long port) { if (CHECK_AX88796L_PORT(port)) ctrl_outw(value, port88796l(port, 0)); - else if (PXSEG(port)) - ctrl_outb(value, port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + else if (is_pci_ioaddr(port)) ctrl_outb(value, pci_ioaddr(port)); else - ctrl_outw(value, port2adr(port)); + ctrl_outb(value, port); ctrl_delay(); } void r7780rp_outw(u16 value, unsigned long port) { - if (CHECK_AX88796L_PORT(port)) - maybebadio(port); - else if (PXSEG(port)) - ctrl_outw(value, port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + if (is_pci_ioaddr(port)) ctrl_outw(value, pci_ioaddr(port)); else - maybebadio(port); + ctrl_outw(value, port); } void r7780rp_outl(u32 value, unsigned long port) { - if (CHECK_AX88796L_PORT(port)) - maybebadio(port); - else if (PXSEG(port)) - ctrl_outl(value, port); - else if (is_pci_ioaddr(port) || shifted_port(port)) + if (is_pci_ioaddr(port)) ctrl_outl(value, pci_ioaddr(port)); else - maybebadio(port); + ctrl_outl(value, port); } void r7780rp_insb(unsigned long port, void *dst, unsigned long count) @@ -183,16 +130,13 @@ void r7780rp_insb(unsigned long port, vo p = (volatile u16 *)port88796l(port, 0); while (count--) *buf++ = *p & 0xff; - } else if (PXSEG(port)) { - while (count--) - *buf++ = *(volatile u8 *)port; - } else if (is_pci_ioaddr(port) || shifted_port(port)) { + } else if (is_pci_ioaddr(port)) { volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *buf++ = *bp; } else { - p = (volatile u16 *)port2adr(port); + p = (volatile u16 *)port; while (count--) *buf++ = *p & 0xff; } @@ -205,30 +149,26 @@ void r7780rp_insw(unsigned long port, vo if (CHECK_AX88796L_PORT(port)) p = (volatile u16 *)port88796l(port, 1); - else if (PXSEG(port)) - p = (volatile u16 *)port; - else if (is_pci_ioaddr(port) || shifted_port(port)) + else if (is_pci_ioaddr(port)) p = (volatile u16 *)pci_ioaddr(port); else - p = (volatile u16 *)port2adr(port); + p = (volatile u16 *)port; while (count--) *buf++ = *p; + + flush_dcache_all(); } void r7780rp_insl(unsigned long port, void *dst, unsigned long count) { - u32 *buf = dst; - - if (CHECK_AX88796L_PORT(port)) - maybebadio(port); - else if (is_pci_ioaddr(port) || shifted_port(port)) { + if (is_pci_ioaddr(port)) { volatile u32 *p = (volatile u32 *)pci_ioaddr(port); + u32 *buf = dst; while (count--) *buf++ = *p; - } else - maybebadio(port); + } } void r7780rp_outsb(unsigned long port, const void *src, unsigned long count) @@ -240,19 +180,14 @@ void r7780rp_outsb(unsigned long port, c p = (volatile u16 *)port88796l(port, 0); while (count--) *p = *buf++; - } else if (PXSEG(port)) - while (count--) - ctrl_outb(*buf++, port); - else if (is_pci_ioaddr(port) || shifted_port(port)) { + } else if (is_pci_ioaddr(port)) { volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *bp = *buf++; - } else { - p = (volatile u16 *)port2adr(port); + } else while (count--) - *p = *buf++; - } + ctrl_outb(*buf++, port); } void r7780rp_outsw(unsigned long port, const void *src, unsigned long count) @@ -262,40 +197,37 @@ void r7780rp_outsw(unsigned long port, c if (CHECK_AX88796L_PORT(port)) p = (volatile u16 *)port88796l(port, 1); - else if (PXSEG(port)) - p = (volatile u16 *)port; - else if (is_pci_ioaddr(port) || shifted_port(port)) + else if (is_pci_ioaddr(port)) p = (volatile u16 *)pci_ioaddr(port); else - p = (volatile u16 *)port2adr(port); + p = (volatile u16 *)port; while (count--) *p = *buf++; + + flush_dcache_all(); } void r7780rp_outsl(unsigned long port, const void *src, unsigned long count) { const u32 *buf = src; + u32 *p; - if (CHECK_AX88796L_PORT(port)) - maybebadio(port); - else if (is_pci_ioaddr(port) || shifted_port(port)) { - volatile u32 *p = (volatile u32 *)pci_ioaddr(port); + if (is_pci_ioaddr(port)) + p = (u32 *)pci_ioaddr(port); + else + p = (u32 *)port; - while (count--) - *p = *buf++; - } else - maybebadio(port); + while (count--) + ctrl_outl(*buf++, (unsigned long)p); } void __iomem *r7780rp_ioport_map(unsigned long port, unsigned int size) { if (CHECK_AX88796L_PORT(port)) return (void __iomem *)port88796l(port, size > 1); - else if (PXSEG(port)) - return (void __iomem *)port; - else if (is_pci_ioaddr(port) || shifted_port(port)) + else if (is_pci_ioaddr(port)) return (void __iomem *)pci_ioaddr(port); - return (void __iomem *)port2adr(port); + return (void __iomem *)port; } diff --git a/arch/sh/boards/renesas/r7780rp/led.c b/arch/sh/boards/renesas/r7780rp/led.c deleted file mode 100644 index 6a00a25..0000000 --- a/arch/sh/boards/renesas/r7780rp/led.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) Atom Create Engineering Co., Ltd. - * - * May be copied or modified under the terms of GNU General Public - * License. See linux/COPYING for more information. - * - * This file contains Renesas Solutions HIGHLANDER R7780RP-1 specific LED code. - */ -#include -#include -#include - -/* Cycle the LED's in the clasic Knightriger/Sun pattern */ -void heartbeat_r7780rp(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short *p = (volatile unsigned short *)PA_OBLED; - static unsigned bit = 0, up = 1; - unsigned bit_pos[] = {2, 1, 0, 3, 6, 5, 4, 7}; - - cnt += 1; - if (cnt < period) - return; - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35, f(int)->110 - */ - period = 110 - ((300 << FSHIFT)/((avenrun[0]/5) + (3< #include +#include #include #include #include #include -extern void heartbeat_r7780rp(void); extern void init_r7780rp_IRQ(void); static struct resource m66596_usb_host_resources[] = { @@ -46,14 +46,14 @@ static struct platform_device m66596_usb static struct resource cf_ide_resources[] = { [0] = { - .start = 0x1f0, - .end = 0x1f0 + 8, - .flags = IORESOURCE_IO, + .start = PA_AREA5_IO + 0x1000, + .end = PA_AREA5_IO + 0x1000 + 0x08 - 1, + .flags = IORESOURCE_MEM, }, [1] = { - .start = 0x1f0 + 0x206, - .end = 0x1f0 + 8 + 0x206 + 8, - .flags = IORESOURCE_IO, + .start = PA_AREA5_IO + 0x80c, + .end = PA_AREA5_IO + 0x80c + 0x16 - 1, + .flags = IORESOURCE_MEM, }, [2] = { #ifdef CONFIG_SH_R7780MP @@ -65,16 +65,44 @@ #endif }, }; +static struct pata_platform_info pata_info = { + .ioport_shift = 1, +}; + static struct platform_device cf_ide_device = { .name = "pata_platform", .id = -1, .num_resources = ARRAY_SIZE(cf_ide_resources), .resource = cf_ide_resources, + .dev = { + .platform_data = &pata_info, + }, +}; + +static unsigned char heartbeat_bit_pos[] = { 2, 1, 0, 3, 6, 5, 4, 7 }; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_OBLED, + .end = PA_OBLED + ARRAY_SIZE(heartbeat_bit_pos) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = heartbeat_bit_pos, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, }; static struct platform_device *r7780rp_devices[] __initdata = { &m66596_usb_host_device, &cf_ide_device, + &heartbeat_device, }; static int __init r7780rp_devices_setup(void) @@ -148,7 +176,7 @@ static void __init r7780rp_setup(char ** #ifndef CONFIG_SH_R7780MP ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */ #endif - ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x0100, PA_IVDRCTL); /* Si13112 */ + ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */ pm_power_off = r7780rp_power_off; } @@ -185,8 +213,5 @@ struct sh_machine_vector mv_r7780rp __in .mv_ioport_map = r7780rp_ioport_map, .mv_init_irq = init_r7780rp_IRQ, -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_r7780rp, -#endif }; ALIAS_MV(r7780rp) diff --git a/arch/sh/boards/renesas/rts7751r2d/Makefile b/arch/sh/boards/renesas/rts7751r2d/Makefile index 686fc9e..833de1e 100644 --- a/arch/sh/boards/renesas/rts7751r2d/Makefile +++ b/arch/sh/boards/renesas/rts7751r2d/Makefile @@ -3,4 +3,3 @@ # Makefile for the RTS7751R2D specific p # obj-y := setup.o io.o irq.o -obj-$(CONFIG_HEARTBEAT) += led.o diff --git a/arch/sh/boards/renesas/rts7751r2d/led.c b/arch/sh/boards/renesas/rts7751r2d/led.c deleted file mode 100644 index 509f548..0000000 --- a/arch/sh/boards/renesas/rts7751r2d/led.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * linux/arch/sh/boards/renesas/rts7751r2d/led.c - * - * Copyright (C) Atom Create Engineering Co., Ltd. - * - * May be copied or modified under the terms of GNU General Public - * License. See linux/COPYING for more information. - * - * This file contains Renesas Technology Sales RTS7751R2D specific LED code. - */ -#include -#include -#include - -/* Cycle the LED's in the clasic Knightriger/Sun pattern */ -void heartbeat_rts7751r2d(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short *p = (volatile unsigned short *)PA_OUTPORT; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) - return; - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35, f(int)->110 - */ - period = 110 - ((300 << FSHIFT)/((avenrun[0]/5) + (3< - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * This file contains Solution Engine specific LED code. - */ - -#include -#include - -#ifdef CONFIG_HEARTBEAT - -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_se(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short* p = (volatile unsigned short*)PA_LED; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ( (300< - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * This file contains Solution Engine specific LED code. - */ - -#include -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_7300se(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short *p = (volatile unsigned short *) PA_LED; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ((300 << FSHIFT) / ((avenrun[0] / 5) + (3 << FSHIFT))); - - if (up) { - if (bit == 7) { - bit--; - up = 0; - } else { - bit++; - } - } else { - if (bit == 0) { - bit++; - up = 1; - } else { - bit--; - } - } - *p = 1 << (bit + 8); - -} - diff --git a/arch/sh/boards/se/7300/setup.c b/arch/sh/boards/se/7300/setup.c index 6f082a7..f196095 100644 --- a/arch/sh/boards/se/7300/setup.c +++ b/arch/sh/boards/se/7300/setup.c @@ -6,14 +6,43 @@ * SH-Mobile SolutionEngine 7300 Support. * */ - #include +#include #include #include -void heartbeat_7300se(void); void init_7300se_IRQ(void); +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = heartbeat_bit_pos, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *se7300_devices[] __initdata = { + &heartbeat_device, +}; + +static int __init se7300_devices_setup(void) +{ + return platform_add_devices(se7300_devices, ARRAY_SIZE(se7300_devices)); +} +__initcall(se7300_devices_setup); + /* * The Machine Vector */ @@ -42,8 +71,5 @@ struct sh_machine_vector mv_7300se __ini .mv_outsl = sh7300se_outsl, .mv_init_irq = init_7300se_IRQ, -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_7300se, -#endif }; ALIAS_MV(7300se) diff --git a/arch/sh/boards/se/73180/Makefile b/arch/sh/boards/se/73180/Makefile index 8f63886..e7c0996 100644 --- a/arch/sh/boards/se/73180/Makefile +++ b/arch/sh/boards/se/73180/Makefile @@ -3,5 +3,3 @@ # Makefile for the 73180 SolutionEngine # obj-y := setup.o io.o irq.o - -obj-$(CONFIG_HEARTBEAT) += led.o diff --git a/arch/sh/boards/se/73180/led.c b/arch/sh/boards/se/73180/led.c deleted file mode 100644 index 4b72e9a..0000000 --- a/arch/sh/boards/se/73180/led.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/sh/boards/se/73180/led.c - * - * Derived from arch/sh/boards/se/770x/led.c - * - * Copyright (C) 2000 Stuart Menefy - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * This file contains Solution Engine specific LED code. - */ - -#include -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_73180se(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short *p = (volatile unsigned short *) PA_LED; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ((300 << FSHIFT) / ((avenrun[0] / 5) + (3 << FSHIFT))); - - if (up) { - if (bit == 7) { - bit--; - up = 0; - } else { - bit++; - } - } else { - if (bit == 0) { - bit++; - up = 1; - } else { - bit--; - } - } - *p = 1 << (bit + LED_SHIFT); - -} diff --git a/arch/sh/boards/se/73180/setup.c b/arch/sh/boards/se/73180/setup.c index b38ef50..911ce1c 100644 --- a/arch/sh/boards/se/73180/setup.c +++ b/arch/sh/boards/se/73180/setup.c @@ -10,13 +10,39 @@ */ #include +#include #include #include #include -void heartbeat_73180se(void); void init_73180se_IRQ(void); +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED + 8 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *se73180_devices[] __initdata = { + &heartbeat_device, +}; + +static int __init se73180_devices_setup(void) +{ + return platform_add_devices(sh7343se_platform_devices, + ARRAY_SIZE(sh7343se_platform_devices)); +} +__initcall(se73180_devices_setup); + /* * The Machine Vector */ @@ -46,8 +72,5 @@ struct sh_machine_vector mv_73180se __in .mv_init_irq = init_73180se_IRQ, .mv_irq_demux = shmse_irq_demux, -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_73180se, -#endif }; ALIAS_MV(73180se) diff --git a/arch/sh/boards/se/7343/Makefile b/arch/sh/boards/se/7343/Makefile index 4291069..3024796 100644 --- a/arch/sh/boards/se/7343/Makefile +++ b/arch/sh/boards/se/7343/Makefile @@ -3,5 +3,3 @@ # Makefile for the 7343 SolutionEngine s # obj-y := setup.o io.o irq.o - -obj-$(CONFIG_HEARTBEAT) += led.o diff --git a/arch/sh/boards/se/7343/led.c b/arch/sh/boards/se/7343/led.c deleted file mode 100644 index 6b39e19..0000000 --- a/arch/sh/boards/se/7343/led.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * arch/sh/boards/se/7343/led.c - * - */ -#include -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_7343se(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short *p = (volatile unsigned short *) PA_LED; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ((300 << FSHIFT) / ((avenrun[0] / 5) + (3 << FSHIFT))); - - if (up) { - if (bit == 7) { - bit--; - up = 0; - } else { - bit++; - } - } else { - if (bit == 0) { - bit++; - up = 1; - } else { - bit--; - } - } - *p = 1 << (bit + LED_SHIFT); - -} diff --git a/arch/sh/boards/se/7343/setup.c b/arch/sh/boards/se/7343/setup.c index c7d17fe..3fdb16f 100644 --- a/arch/sh/boards/se/7343/setup.c +++ b/arch/sh/boards/se/7343/setup.c @@ -4,7 +4,6 @@ #include #include #include -void heartbeat_7343se(void); void init_7343se_IRQ(void); static struct resource smc91x_resources[] = { @@ -31,14 +30,30 @@ static struct platform_device smc91x_dev .resource = smc91x_resources, }; -static struct platform_device *smc91x_platform_devices[] __initdata = { +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED + 8 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *sh7343se_platform_devices[] __initdata = { &smc91x_device, + &heartbeat_device, }; static int __init sh7343se_devices_setup(void) { - return platform_add_devices(smc91x_platform_devices, - ARRAY_SIZE(smc91x_platform_devices)); + return platform_add_devices(sh7343se_platform_devices, + ARRAY_SIZE(sh7343se_platform_devices)); } static void __init sh7343se_setup(char **cmdline_p) @@ -76,8 +91,5 @@ struct sh_machine_vector mv_7343se __ini .mv_init_irq = init_7343se_IRQ, .mv_irq_demux = shmse_irq_demux, -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_7343se, -#endif }; ALIAS_MV(7343se) diff --git a/arch/sh/boards/se/770x/Makefile b/arch/sh/boards/se/770x/Makefile index 9a5035f..8e624b0 100644 --- a/arch/sh/boards/se/770x/Makefile +++ b/arch/sh/boards/se/770x/Makefile @@ -3,4 +3,3 @@ # Makefile for the 770x SolutionEngine s # obj-y := setup.o io.o irq.o -obj-$(CONFIG_HEARTBEAT) += led.o diff --git a/arch/sh/boards/se/770x/irq.c b/arch/sh/boards/se/770x/irq.c index fcd7cd7..307ca5d 100644 --- a/arch/sh/boards/se/770x/irq.c +++ b/arch/sh/boards/se/770x/irq.c @@ -2,56 +2,96 @@ * linux/arch/sh/boards/se/770x/irq.c * * Copyright (C) 2000 Kazumoto Kojima + * Copyright (C) 2006 Nobuhiro Iwamatsu * * Hitachi SolutionEngine Support. * */ #include +#include #include #include #include #include +/* + * If the problem of make_ipr_irq is solved, + * this code will become unnecessary. :-) + */ +static void se770x_disable_ipr_irq(unsigned int irq) +{ + struct ipr_data *p = get_irq_chip_data(irq); + + ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr); +} + +static void se770x_enable_ipr_irq(unsigned int irq) +{ + struct ipr_data *p = get_irq_chip_data(irq); + + ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr); +} + +static struct irq_chip se770x_irq_chip = { + .name = "MS770xSE-FPGA", + .mask = se770x_disable_ipr_irq, + .unmask = se770x_enable_ipr_irq, + .mask_ack = se770x_disable_ipr_irq, +}; + +void make_se770x_irq(struct ipr_data *table, unsigned int nr_irqs) +{ + int i; + + for (i = 0; i < nr_irqs; i++) { + unsigned int irq = table[i].irq; + disable_irq_nosync(irq); + set_irq_chip_and_handler_name(irq, &se770x_irq_chip, + handle_level_irq, "level"); + set_irq_chip_data(irq, &table[i]); + se770x_enable_ipr_irq(irq); + } +} + static struct ipr_data se770x_ipr_map[] = { #if defined(CONFIG_CPU_SUBTYPE_SH7705) /* This is default value */ - { 0xf-0x2, BCR_ILCRA, 2, 0x2 }, - { 0xf-0xa, BCR_ILCRA, 1, 0xa }, - { 0xf-0x5, BCR_ILCRB, 0, 0x5 }, - { 0xf-0x8, BCR_ILCRC, 1, 0x8 }, - { 0xf-0xc, BCR_ILCRC, 0, 0xc }, - { 0xf-0xe, BCR_ILCRD, 3, 0xe }, - { 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */ - { 0xf-0xd, BCR_ILCRE, 2, 0xd }, - { 0xf-0x9, BCR_ILCRE, 1, 0x9 }, - { 0xf-0x1, BCR_ILCRE, 0, 0x1 }, - { 0xf-0xf, BCR_ILCRF, 3, 0xf }, - { 0xf-0xb, BCR_ILCRF, 1, 0xb }, - { 0xf-0x7, BCR_ILCRG, 3, 0x7 }, - { 0xf-0x6, BCR_ILCRG, 2, 0x6 }, - { 0xf-0x4, BCR_ILCRG, 1, 0x4 }, + { 0xf-0x2, 0, 8, 0x2 , BCR_ILCRA}, + { 0xf-0xa, 0, 4, 0xa , BCR_ILCRA}, + { 0xf-0x5, 0, 0, 0x5 , BCR_ILCRB}, + { 0xf-0x8, 0, 4, 0x8 , BCR_ILCRC}, + { 0xf-0xc, 0, 0, 0xc , BCR_ILCRC}, + { 0xf-0xe, 0, 12, 0xe , BCR_ILCRD}, + { 0xf-0x3, 0, 4, 0x3 , BCR_ILCRD}, /* LAN */ + { 0xf-0xd, 0, 8, 0xd , BCR_ILCRE}, + { 0xf-0x9, 0, 4, 0x9 , BCR_ILCRE}, + { 0xf-0x1, 0, 0, 0x1 , BCR_ILCRE}, + { 0xf-0xf, 0, 12, 0xf , BCR_ILCRF}, + { 0xf-0xb, 0, 4, 0xb , BCR_ILCRF}, + { 0xf-0x7, 0, 12, 0x7 , BCR_ILCRG}, + { 0xf-0x6, 0, 8, 0x6 , BCR_ILCRG}, + { 0xf-0x4, 0, 4, 0x4 , BCR_ILCRG}, #else - { 14, BCR_ILCRA, 2, 0x0f-14 }, - { 12, BCR_ILCRA, 1, 0x0f-12 }, - { 8, BCR_ILCRB, 1, 0x0f- 8 }, - { 6, BCR_ILCRC, 3, 0x0f- 6 }, - { 5, BCR_ILCRC, 2, 0x0f- 5 }, - { 4, BCR_ILCRC, 1, 0x0f- 4 }, - { 3, BCR_ILCRC, 0, 0x0f- 3 }, - { 1, BCR_ILCRD, 3, 0x0f- 1 }, - - { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */ - - { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */ - { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */ - { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */ - { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */ - + { 14, 0, 8, 0x0f-14 ,BCR_ILCRA}, + { 12, 0, 4, 0x0f-12 ,BCR_ILCRA}, + { 8, 0, 4, 0x0f- 8 ,BCR_ILCRB}, + { 6, 0, 12, 0x0f- 6 ,BCR_ILCRC}, + { 5, 0, 8, 0x0f- 5 ,BCR_ILCRC}, + { 4, 0, 4, 0x0f- 4 ,BCR_ILCRC}, + { 3, 0, 0, 0x0f- 3 ,BCR_ILCRC}, + { 1, 0, 12, 0x0f- 1 ,BCR_ILCRD}, + /* ST NIC */ + { 10, 0, 4, 0x0f-10 ,BCR_ILCRD}, /* LAN */ + /* MRSHPC IRQs setting */ + { 0, 0, 12, 0x0f- 0 ,BCR_ILCRE}, /* PCIRQ3 */ + { 11, 0, 8, 0x0f-11 ,BCR_ILCRE}, /* PCIRQ2 */ + { 9, 0, 4, 0x0f- 9 ,BCR_ILCRE}, /* PCIRQ1 */ + { 7, 0, 0, 0x0f- 7 ,BCR_ILCRE}, /* PCIRQ0 */ /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ /* NOTE: #2 and #13 are not used on PC */ - { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */ - { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */ + { 13, 0, 4, 0x0f-13 ,BCR_ILCRG}, /* SLOTIRQ2 */ + { 2, 0, 0, 0x0f- 2 ,BCR_ILCRG}, /* SLOTIRQ1 */ #endif }; @@ -81,5 +121,5 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) ctrl_outw(0, BCR_ILCRF); ctrl_outw(0, BCR_ILCRG); #endif - make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map)); + make_se770x_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map)); } diff --git a/arch/sh/boards/se/770x/led.c b/arch/sh/boards/se/770x/led.c deleted file mode 100644 index d93dd83..0000000 --- a/arch/sh/boards/se/770x/led.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * linux/arch/sh/boards/se/770x/led.c - * - * Copyright (C) 2000 Stuart Menefy - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * This file contains Solution Engine specific LED code. - */ - -#include -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_se(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short* p = (volatile unsigned short*)PA_LED; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ( (300< +#include #include #include #include #include -void heartbeat_se(void); void init_se_IRQ(void); /* @@ -36,11 +35,6 @@ static void __init smsc_setup(char **cmd smsc_config(ACTIVATE_INDEX, 0x01); smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */ - /* IDE1 */ - smsc_config(CURRENT_LDN_INDEX, LDN_IDE1); - smsc_config(ACTIVATE_INDEX, 0x01); - smsc_config(IRQ_SELECT_INDEX, 14); /* IRQ14 */ - /* AUXIO (GPIO): to use IDE1 */ smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO); smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ @@ -69,6 +63,36 @@ static void __init smsc_setup(char **cmd outb_p(CONFIG_EXIT, CONFIG_PORT); } +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = heartbeat_bit_pos, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *se_devices[] __initdata = { + &heartbeat_device, +}; + +static int __init se_devices_setup(void) +{ + return platform_add_devices(se_devices, ARRAY_SIZE(se_devices)); +} +__initcall(se_devices_setup); + /* * The Machine Vector */ @@ -107,8 +131,5 @@ #endif .mv_outsl = se_outsl, .mv_init_irq = init_se_IRQ, -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_se, -#endif }; ALIAS_MV(se) diff --git a/arch/sh/boards/se/7751/Makefile b/arch/sh/boards/se/7751/Makefile index 188900c..dbc29f3 100644 --- a/arch/sh/boards/se/7751/Makefile +++ b/arch/sh/boards/se/7751/Makefile @@ -5,4 +5,3 @@ # obj-y := setup.o io.o irq.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_HEARTBEAT) += led.o diff --git a/arch/sh/boards/se/7751/led.c b/arch/sh/boards/se/7751/led.c deleted file mode 100644 index de4194d..0000000 --- a/arch/sh/boards/se/7751/led.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * linux/arch/sh/boards/se/7751/led.c - * - * Copyright (C) 2000 Stuart Menefy - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * This file contains Solution Engine specific LED code. - */ -#include -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_7751se(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned short* p = (volatile unsigned short*)PA_LED; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ( (300< +#include #include #include #include -void heartbeat_7751se(void); void init_7751se_IRQ(void); #ifdef CONFIG_SH_KGDB @@ -161,11 +161,40 @@ static int kgdb_uart_setup(void) } #endif /* CONFIG_SH_KGDB */ +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = heartbeat_bit_pos, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *se7751_devices[] __initdata = { + &smc91x_device, + &heartbeat_device, +}; + +static int __init se7751_devices_setup(void) +{ + return platform_add_devices(se7751_devices, ARRAY_SIZE(se7751_devices)); +} +__initcall(se7751_devices_setup); /* * The Machine Vector */ - struct sh_machine_vector mv_7751se __initmv = { .mv_name = "7751 SolutionEngine", .mv_setup = sh7751se_setup, @@ -189,8 +218,5 @@ struct sh_machine_vector mv_7751se __ini .mv_outsl = sh7751se_outsl, .mv_init_irq = init_7751se_IRQ, -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_7751se, -#endif }; ALIAS_MV(7751se) diff --git a/arch/sh/boards/sh03/Makefile b/arch/sh/boards/sh03/Makefile index 321be50..400306a 100644 --- a/arch/sh/boards/sh03/Makefile +++ b/arch/sh/boards/sh03/Makefile @@ -3,4 +3,3 @@ # Makefile for the Interface (CTP/PCI-SH # obj-y := setup.o rtc.o -obj-$(CONFIG_HEARTBEAT) += led.o diff --git a/arch/sh/boards/sh03/led.c b/arch/sh/boards/sh03/led.c deleted file mode 100644 index d38562a..0000000 --- a/arch/sh/boards/sh03/led.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/sh/boards/sh03/led.c - * - * Copyright (C) 2004 Saito.K Interface Corporation. - * - * This file contains Interface CTP/PCI-SH03 specific LED code. - */ - -#include - -/* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void heartbeat_sh03(void) -{ - static unsigned int cnt = 0, period = 0; - volatile unsigned char* p = (volatile unsigned char*)0xa0800000; - static unsigned bit = 0, up = 1; - - cnt += 1; - if (cnt < period) { - return; - } - - cnt = 0; - - /* Go through the points (roughly!): - * f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110 - */ - period = 110 - ( (300< #include #include +#include #include #include #include @@ -48,15 +49,36 @@ static void __init sh03_setup(char **cmd board_time_init = sh03_time_init; } +static struct resource heartbeat_resources[] = { + [0] = { + .start = 0xa0800000, + .end = 0xa0800000 + 8 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *sh03_devices[] __initdata = { + &heartbeat_device, +}; + +static int __init sh03_devices_setup(void) +{ + return platform_add_devices(sh03_devices, ARRAY_SIZE(sh03_devices)); +} +__initcall(sh03_devices_setup); + struct sh_machine_vector mv_sh03 __initmv = { .mv_name = "Interface (CTP/PCI-SH03)", .mv_setup = sh03_setup, .mv_nr_irqs = 48, .mv_ioport_map = sh03_ioport_map, .mv_init_irq = init_sh03_IRQ, - -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_sh03, -#endif }; ALIAS_MV(sh03) diff --git a/arch/sh/boards/shmin/setup.c b/arch/sh/boards/shmin/setup.c index a31a1d1..4a9df4a 100644 --- a/arch/sh/boards/shmin/setup.c +++ b/arch/sh/boards/shmin/setup.c @@ -12,12 +12,22 @@ #include #include #include -#define PFC_PHCR 0xa400010e +#define PFC_PHCR 0xa400010eUL +#define INTC_ICR1 0xa4000010UL +#define INTC_IPRC 0xa4000016UL + +static struct ipr_data shmin_ipr_map[] = { + { .irq=32, .addr=INTC_IPRC, .shift= 0, .priority=0 }, + { .irq=33, .addr=INTC_IPRC, .shift= 4, .priority=0 }, + { .irq=34, .addr=INTC_IPRC, .shift= 8, .priority=8 }, + { .irq=35, .addr=INTC_IPRC, .shift=12, .priority=0 }, +}; static void __init init_shmin_irq(void) { ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. + make_ipr_irq(shmin_ipr_map, ARRAY_SIZE(shmin_ipr_map)); } static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size) diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig index 5d357d6..4e6e77f 100644 --- a/arch/sh/configs/se7750_defconfig +++ b/arch/sh/configs/se7750_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.18 -# Tue Oct 3 11:49:01 2006 +# Linux kernel version: 2.6.20-rc2 +# Thu Dec 28 23:15:49 2006 # CONFIG_SUPERH=y CONFIG_RWSEM_GENERIC_SPINLOCK=y @@ -10,6 +10,11 @@ CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_CALIBRATE_DELAY=y +# CONFIG_GENERIC_TIME is not set +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -35,6 +40,7 @@ # CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_SYSFS_DEPRECATED=y # CONFIG_RELAY is not set CONFIG_INITRAMFS_SOURCE="" # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -116,6 +122,8 @@ # CONFIG_SH_SH4202_MICRODEV is not set # CONFIG_SH_LANDISK is not set # CONFIG_SH_TITAN is not set # CONFIG_SH_SHMIN is not set +# CONFIG_SH_7206_SOLUTION_ENGINE is not set +# CONFIG_SH_7619_SOLUTION_ENGINE is not set # CONFIG_SH_UNKNOWN is not set # @@ -127,6 +135,12 @@ # # SH-2 Processor Support # # CONFIG_CPU_SUBTYPE_SH7604 is not set +# CONFIG_CPU_SUBTYPE_SH7619 is not set + +# +# SH-2A Processor Support +# +# CONFIG_CPU_SUBTYPE_SH7206 is not set # # SH-3 Processor Support @@ -162,12 +176,14 @@ # SH-4A Processor Support # # CONFIG_CPU_SUBTYPE_SH7770 is not set # CONFIG_CPU_SUBTYPE_SH7780 is not set +# CONFIG_CPU_SUBTYPE_SH7785 is not set # # SH4AL-DSP Processor Support # # CONFIG_CPU_SUBTYPE_SH73180 is not set # CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set # # Memory management options @@ -177,6 +193,9 @@ CONFIG_PAGE_OFFSET=0x80000000 CONFIG_MEMORY_START=0x0c000000 CONFIG_MEMORY_SIZE=0x02000000 CONFIG_VSYSCALL=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_64KB is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -202,17 +221,22 @@ # # Processor features # CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_SH_FPU=y # CONFIG_SH_DSP is not set # CONFIG_SH_STORE_QUEUES is not set CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_IPR_IRQ=y CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_PTEA=y # # Timer support # CONFIG_SH_TMU=y -CONFIG_SH_PCLK_FREQ=50000000 +CONFIG_SH_TIMER_IRQ=16 +# CONFIG_NO_IDLE_HZ is not set +CONFIG_SH_PCLK_FREQ=33333333 # # CPU Frequency scaling @@ -231,10 +255,16 @@ # CONFIG_HD6446X_SERIES is not set CONFIG_HEARTBEAT=y # +# Additional SuperH Device Drivers +# +# CONFIG_PUSH_SWITCH is not set + +# # Kernel features # # CONFIG_HZ_100 is not set CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 # CONFIG_KEXEC is not set @@ -249,8 +279,7 @@ # CONFIG_ZERO_PAGE_OFFSET=0x00001000 CONFIG_BOOT_LINK_OFFSET=0x00800000 # CONFIG_UBC_WAKEUP is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttySC1,38400 root=/dev/nfs ip=bootp" +# CONFIG_CMDLINE_BOOL is not set # # Bus options @@ -313,11 +342,13 @@ # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_INET6_XFRM_TUNNEL is not set # CONFIG_INET6_TUNNEL is not set @@ -480,16 +511,79 @@ # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # +# Misc devices +# +# CONFIG_TIFM_CORE is not set + +# # ATA/ATAPI/MFM/RLL support # -# CONFIG_IDE is not set +CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set +CONFIG_SCSI=y +# CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set # # Serial ATA (prod) and Parallel ATA (experimental) drivers @@ -633,17 +727,12 @@ CONFIG_HW_RANDOM=y # CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# # CONFIG_RAW_DRIVER is not set # # TPM devices # # CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set # # I2C support @@ -659,6 +748,7 @@ # CONFIG_SPI_MASTER is not set # # Dallas's 1-wire bus # +# CONFIG_W1 is not set # # Hardware Monitoring support @@ -667,18 +757,14 @@ CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_HWMON_DEBUG_CHIP is not set # -# Misc devices -# - -# # Multimedia devices # # CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y # # Digital Video Broadcasting Devices @@ -758,14 +844,20 @@ # DMA Devices # # +# Virtualization +# + +# # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -814,7 +906,6 @@ # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y @@ -875,6 +966,11 @@ # # CONFIG_NLS is not set # +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# # Profiling support # # CONFIG_PROFILING is not set @@ -882,14 +978,16 @@ # CONFIG_PROFILING is not set # # Kernel hacking # +CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_ENABLE_MUST_CHECK is not set # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_FS is not set # CONFIG_SH_STANDARD_BIOS is not set # CONFIG_EARLY_SCIF_CONSOLE is not set # CONFIG_KGDB is not set @@ -908,6 +1006,7 @@ # CONFIG_CRYPTO is not set # # Library routines # +CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC32=y @@ -915,3 +1014,4 @@ # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_PLIST=y +CONFIG_IOMAP_COPY=y diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile index bf18dbf..6cb9267 100644 --- a/arch/sh/drivers/Makefile +++ b/arch/sh/drivers/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PCI) += pci/ obj-$(CONFIG_SH_DMA) += dma/ obj-$(CONFIG_SUPERHYWAY) += superhyway/ obj-$(CONFIG_PUSH_SWITCH) += push-switch.o +obj-$(CONFIG_HEARTBEAT) += heartbeat.o diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index f63721e..06ed060 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c @@ -19,34 +19,26 @@ #include #include #include "dma-sh.h" - - -#ifdef CONFIG_CPU_SH4 -static struct ipr_data dmae_ipr_map[] = { - { DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, -}; +static int dmte_irq_map[] = { + DMTE0_IRQ, + DMTE1_IRQ, + DMTE2_IRQ, + DMTE3_IRQ, +#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ + defined(CONFIG_CPU_SUBTYPE_SH7760) || \ + defined(CONFIG_CPU_SUBTYPE_SH7780) + DMTE4_IRQ, + DMTE5_IRQ, + DMTE6_IRQ, + DMTE7_IRQ, #endif -static struct ipr_data dmte_ipr_map[] = { - /* - * Normally we could just do DMTE0_IRQ + chan outright, though in the - * case of the 7751R, the DMTE IRQs for channels > 4 start right above - * the SCIF - */ - { DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, - { DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, - { DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, - { DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, - { DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, - { DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, - { DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, - { DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, }; static inline unsigned int get_dmte_irq(unsigned int chan) { unsigned int irq = 0; - if (chan < ARRAY_SIZE(dmte_ipr_map)) - irq = dmte_ipr_map[chan].irq; + if (chan < ARRAY_SIZE(dmte_irq_map)) + irq = dmte_irq_map[chan]; return irq; } @@ -103,7 +95,7 @@ static void sh_dmac_free_dma(struct dma_ free_irq(get_dmte_irq(chan->chan), chan); } -static void +static int sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr) { if (!chcr) @@ -119,6 +111,7 @@ sh_dmac_configure_channel(struct dma_cha ctrl_outl(chcr, CHCR[chan->chan]); chan->flags |= DMA_CONFIGURED; + return 0; } static void sh_dmac_enable_dma(struct dma_channel *chan) @@ -262,17 +255,11 @@ static int __init sh_dmac_init(void) int i; #ifdef CONFIG_CPU_SH4 - make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map)); i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0); if (unlikely(i < 0)) return i; #endif - i = info->nr_channels; - if (i > ARRAY_SIZE(dmte_ipr_map)) - i = ARRAY_SIZE(dmte_ipr_map); - make_ipr_irq(dmte_ipr_map, i); - /* * Initialize DMAOR, and clean up any error flags that may have * been set. diff --git a/arch/sh/drivers/heartbeat.c b/arch/sh/drivers/heartbeat.c new file mode 100644 index 0000000..bc59cb6 --- /dev/null +++ b/arch/sh/drivers/heartbeat.c @@ -0,0 +1,132 @@ +/* + * Generic heartbeat driver for regular LED banks + * + * Copyright (C) 2007 Paul Mundt + * + * Most SH reference boards include a number of individual LEDs that can + * be independently controlled (either via a pre-defined hardware + * function or via the LED class, if desired -- the hardware tends to + * encapsulate some of the same "triggers" that the LED class supports, + * so there's not too much value in it). + * + * Additionally, most of these boards also have a LED bank that we've + * traditionally used for strobing the load average. This use case is + * handled by this driver, rather than giving each LED bit position its + * own struct device. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "heartbeat" +#define DRV_VERSION "0.1.0" + +struct heartbeat_data { + void __iomem *base; + unsigned char bit_pos[8]; + struct timer_list timer; +}; + +static void heartbeat_timer(unsigned long data) +{ + struct heartbeat_data *hd = (struct heartbeat_data *)data; + static unsigned bit = 0, up = 1; + + ctrl_outw(1 << hd->bit_pos[bit], (unsigned long)hd->base); + if (up) + if (bit == (ARRAY_SIZE(hd->bit_pos) - 1)) { + bit--; + up = 0; + } else + bit++; + else if (bit == 0) + up = 1; + else + bit--; + + mod_timer(&hd->timer, jiffies + (110 - ((300 << FSHIFT) / + ((avenrun[0] / 5) + (3 << FSHIFT))))); +} + +static int heartbeat_drv_probe(struct platform_device *pdev) +{ + struct resource *res; + struct heartbeat_data *hd; + + if (unlikely(pdev->num_resources != 1)) { + dev_err(&pdev->dev, "invalid number of resources\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (unlikely(res == NULL)) { + dev_err(&pdev->dev, "invalid resource\n"); + return -EINVAL; + } + + hd = kmalloc(sizeof(struct heartbeat_data), GFP_KERNEL); + if (unlikely(!hd)) + return -ENOMEM; + + if (pdev->dev.platform_data) { + memcpy(hd->bit_pos, pdev->dev.platform_data, + ARRAY_SIZE(hd->bit_pos)); + } else { + int i; + + for (i = 0; i < ARRAY_SIZE(hd->bit_pos); i++) + hd->bit_pos[i] = i; + } + + hd->base = (void __iomem *)res->start; + + setup_timer(&hd->timer, heartbeat_timer, (unsigned long)hd); + platform_set_drvdata(pdev, hd); + + return mod_timer(&hd->timer, jiffies + 1); +} + +static int heartbeat_drv_remove(struct platform_device *pdev) +{ + struct heartbeat_data *hd = platform_get_drvdata(pdev); + + del_timer_sync(&hd->timer); + + platform_set_drvdata(pdev, NULL); + + kfree(hd); + + return 0; +} + +static struct platform_driver heartbeat_driver = { + .probe = heartbeat_drv_probe, + .remove = heartbeat_drv_remove, + .driver = { + .name = DRV_NAME, + }, +}; + +static int __init heartbeat_init(void) +{ + printk(KERN_NOTICE DRV_NAME ": version %s loaded\n", DRV_VERSION); + return platform_driver_register(&heartbeat_driver); +} + +static void __exit heartbeat_exit(void) +{ + platform_driver_unregister(&heartbeat_driver); +} +module_init(heartbeat_init); +module_exit(heartbeat_exit); + +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Paul Mundt"); +MODULE_LICENSE("GPLv2"); diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index 2f6d2bc..ff30d7f 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -6,7 +6,8 @@ extra-y := head.o init_task.o vmlinux.ld obj-y := process.o signal.o traps.o irq.o \ ptrace.o setup.o time.o sys_sh.o semaphore.o \ - io.o io_generic.o sh_ksyms.o syscalls.o + io.o io_generic.o sh_ksyms.o syscalls.o \ + debugtraps.o obj-y += cpu/ timers/ obj-$(CONFIG_VSYSCALL) += vsyscall/ diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 4812176..4b339a6 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -3,7 +3,7 @@ * * CPU init code * - * Copyright (C) 2002, 2003 Paul Mundt + * Copyright (C) 2002 - 2006 Paul Mundt * Copyright (C) 2003 Richard Curnow * * This file is subject to the terms and conditions of the GNU General Public @@ -12,6 +12,8 @@ */ #include #include +#include +#include #include #include #include @@ -46,7 +48,7 @@ static void __init cache_init(void) { unsigned long ccr, flags; - if (cpu_data->type == CPU_SH_NONE) + if (current_cpu_data.type == CPU_SH_NONE) panic("Unknown CPU"); jump_to_P2(); @@ -66,7 +68,7 @@ static void __init cache_init(void) if (ccr & CCR_CACHE_ENABLE) { unsigned long ways, waysize, addrstart; - waysize = cpu_data->dcache.sets; + waysize = current_cpu_data.dcache.sets; #ifdef CCR_CACHE_ORA /* @@ -77,7 +79,7 @@ #ifdef CCR_CACHE_ORA waysize >>= 1; #endif - waysize <<= cpu_data->dcache.entry_shift; + waysize <<= current_cpu_data.dcache.entry_shift; #ifdef CCR_CACHE_EMODE /* If EMODE is not set, we only have 1 way to flush. */ @@ -85,7 +87,7 @@ #ifdef CCR_CACHE_EMODE ways = 1; else #endif - ways = cpu_data->dcache.ways; + ways = current_cpu_data.dcache.ways; addrstart = CACHE_OC_ADDRESS_ARRAY; do { @@ -93,10 +95,10 @@ #endif for (addr = addrstart; addr < addrstart + waysize; - addr += cpu_data->dcache.linesz) + addr += current_cpu_data.dcache.linesz) ctrl_outl(0, addr); - addrstart += cpu_data->dcache.way_incr; + addrstart += current_cpu_data.dcache.way_incr; } while (--ways); } @@ -108,7 +110,7 @@ #endif #ifdef CCR_CACHE_EMODE /* Force EMODE if possible */ - if (cpu_data->dcache.ways > 1) + if (current_cpu_data.dcache.ways > 1) flags |= CCR_CACHE_EMODE; else flags &= ~CCR_CACHE_EMODE; @@ -125,10 +127,10 @@ #endif #ifdef CONFIG_SH_OCRAM /* Turn on OCRAM -- halve the OC */ flags |= CCR_CACHE_ORA; - cpu_data->dcache.sets >>= 1; + current_cpu_data.dcache.sets >>= 1; - cpu_data->dcache.way_size = cpu_data->dcache.sets * - cpu_data->dcache.linesz; + current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; #endif ctrl_outl(flags, CCR); @@ -170,7 +172,7 @@ static void __init dsp_init(void) /* If the DSP bit is still set, this CPU has a DSP */ if (sr & SR_DSP) - cpu_data->flags |= CPU_HAS_DSP; + current_cpu_data.flags |= CPU_HAS_DSP; /* Now that we've determined the DSP status, clear the DSP bit. */ release_dsp(); @@ -202,22 +204,28 @@ asmlinkage void __init sh_cpu_init(void) cache_init(); shm_align_mask = max_t(unsigned long, - cpu_data->dcache.way_size - 1, + current_cpu_data.dcache.way_size - 1, PAGE_SIZE - 1); /* Disable the FPU */ if (fpu_disabled) { printk("FPU Disabled\n"); - cpu_data->flags &= ~CPU_HAS_FPU; + current_cpu_data.flags &= ~CPU_HAS_FPU; disable_fpu(); } /* FPU initialization */ - if ((cpu_data->flags & CPU_HAS_FPU)) { + if ((current_cpu_data.flags & CPU_HAS_FPU)) { clear_thread_flag(TIF_USEDFPU); clear_used_math(); } + /* + * Initialize the per-CPU ASID cache very early, since the + * TLB flushing routines depend on this being setup. + */ + current_cpu_data.asid_cache = NO_CONTEXT; + #ifdef CONFIG_SH_DSP /* Probe for DSP */ dsp_init(); @@ -225,7 +233,7 @@ #ifdef CONFIG_SH_DSP /* Disable the DSP */ if (dsp_disabled) { printk("DSP Disabled\n"); - cpu_data->flags &= ~CPU_HAS_DSP; + current_cpu_data.flags &= ~CPU_HAS_DSP; release_dsp(); } #endif @@ -240,4 +248,3 @@ #ifdef CONFIG_UBC_WAKEUP ubc_wakeup(); #endif } - diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 35eb575..210280b 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c @@ -43,16 +43,29 @@ static struct irq_chip ipr_irq_chip = { .mask_ack = disable_ipr_irq, }; +unsigned int map_ipridx_to_addr(int idx) __attribute__ ((weak)); +unsigned int map_ipridx_to_addr(int idx) +{ + return 0; +} + void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs) { int i; for (i = 0; i < nr_irqs; i++) { unsigned int irq = table[i].irq; - table[i].addr = map_ipridx_to_addr(table[i].ipr_idx); + + if (!irq) + irq = table[i].irq = i; + /* could the IPR index be mapped, if not we ignore this */ - if (table[i].addr == 0) - continue; + if (!table[i].addr) { + table[i].addr = map_ipridx_to_addr(table[i].ipr_idx); + if (!table[i].addr) + continue; + } + disable_irq_nosync(irq); set_irq_chip_and_handler_name(irq, &ipr_irq_chip, handle_level_irq, "level"); diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S index d51fa5e..7f7d292 100644 --- a/arch/sh/kernel/cpu/sh2/entry.S +++ b/arch/sh/kernel/cpu/sh2/entry.S @@ -178,12 +178,10 @@ interrupt_entry: 8: .long do_exception_error trap_entry: - /* verbose BUG trapa entry check */ - mov #0x3e,r8 - cmp/ge r8,r9 - bf/s 1f - add #-0x10,r9 - add #0x10,r9 + mov #0x30,r8 + cmp/ge r8,r9 ! vector 0x20-0x2f is systemcall + bt 1f + add #-0x10,r9 ! convert SH2 to SH3/4 ABI 1: shll2 r9 ! TRA mov #OFF_TRA,r8 @@ -206,7 +204,7 @@ #endif #if defined(CONFIG_SH_STANDARD_BIOS) /* Unwind the stack and jmp to the debug entry */ -debug_kernel_fw: +ENTRY(sh_bios_handler) mov r15,r0 add #(22-4)*4-4,r0 ldc.l @r0+,gbr diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index ba527d9..108e81b 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -18,27 +18,27 @@ #include int __init detect_cpu_and_cache_system(void) { #if defined(CONFIG_CPU_SUBTYPE_SH7604) - cpu_data->type = CPU_SH7604; - cpu_data->dcache.ways = 4; - cpu_data->dcache.way_incr = (1<<10); - cpu_data->dcache.sets = 64; - cpu_data->dcache.entry_shift = 4; - cpu_data->dcache.linesz = L1_CACHE_BYTES; - cpu_data->dcache.flags = 0; + current_cpu_data.type = CPU_SH7604; + current_cpu_data.dcache.ways = 4; + current_cpu_data.dcache.way_incr = (1<<10); + current_cpu_data.dcache.sets = 64; + current_cpu_data.dcache.entry_shift = 4; + current_cpu_data.dcache.linesz = L1_CACHE_BYTES; + current_cpu_data.dcache.flags = 0; #elif defined(CONFIG_CPU_SUBTYPE_SH7619) - cpu_data->type = CPU_SH7619; - cpu_data->dcache.ways = 4; - cpu_data->dcache.way_incr = (1<<12); - cpu_data->dcache.sets = 256; - cpu_data->dcache.entry_shift = 4; - cpu_data->dcache.linesz = L1_CACHE_BYTES; - cpu_data->dcache.flags = 0; + current_cpu_data.type = CPU_SH7619; + current_cpu_data.dcache.ways = 4; + current_cpu_data.dcache.way_incr = (1<<12); + current_cpu_data.dcache.sets = 256; + current_cpu_data.dcache.entry_shift = 4; + current_cpu_data.dcache.linesz = L1_CACHE_BYTES; + current_cpu_data.dcache.flags = 0; #endif /* * SH-2 doesn't have separate caches */ - cpu_data->dcache.flags |= SH_CACHE_COMBINED; - cpu_data->icache = cpu_data->dcache; + current_cpu_data.dcache.flags |= SH_CACHE_COMBINED; + current_cpu_data.icache = current_cpu_data.dcache; return 0; } diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 79283e6..f83ff8a 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c @@ -52,42 +52,38 @@ static int __init sh7619_devices_setup(v } __initcall(sh7619_devices_setup); -#define INTC_IPRC 0xf8080000UL -#define INTC_IPRD 0xf8080002UL - -#define CMI0_IRQ 86 - -#define SCIF0_ERI_IRQ 88 -#define SCIF0_RXI_IRQ 89 -#define SCIF0_BRI_IRQ 90 -#define SCIF0_TXI_IRQ 91 - -#define SCIF1_ERI_IRQ 92 -#define SCIF1_RXI_IRQ 93 -#define SCIF1_BRI_IRQ 94 -#define SCIF1_TXI_IRQ 95 - -#define SCIF2_BRI_IRQ 96 -#define SCIF2_ERI_IRQ 97 -#define SCIF2_RXI_IRQ 98 -#define SCIF2_TXI_IRQ 99 - static struct ipr_data sh7619_ipr_map[] = { - { CMI0_IRQ, INTC_IPRC, 1, 2 }, - { SCIF0_ERI_IRQ, INTC_IPRD, 3, 3 }, - { SCIF0_RXI_IRQ, INTC_IPRD, 3, 3 }, - { SCIF0_BRI_IRQ, INTC_IPRD, 3, 3 }, - { SCIF0_TXI_IRQ, INTC_IPRD, 3, 3 }, - { SCIF1_ERI_IRQ, INTC_IPRD, 2, 3 }, - { SCIF1_RXI_IRQ, INTC_IPRD, 2, 3 }, - { SCIF1_BRI_IRQ, INTC_IPRD, 2, 3 }, - { SCIF1_TXI_IRQ, INTC_IPRD, 2, 3 }, - { SCIF2_ERI_IRQ, INTC_IPRD, 1, 3 }, - { SCIF2_RXI_IRQ, INTC_IPRD, 1, 3 }, - { SCIF2_BRI_IRQ, INTC_IPRD, 1, 3 }, - { SCIF2_TXI_IRQ, INTC_IPRD, 1, 3 }, + { 86, 0, 4, 2 }, /* CMI0 */ + { 88, 1, 12, 3 }, /* SCIF0_ERI */ + { 89, 1, 12, 3 }, /* SCIF0_RXI */ + { 90, 1, 12, 3 }, /* SCIF0_BRI */ + { 91, 1, 12, 3 }, /* SCIF0_TXI */ + { 92, 1, 8, 3 }, /* SCIF1_ERI */ + { 93, 1, 8, 3 }, /* SCIF1_RXI */ + { 94, 1, 8, 3 }, /* SCIF1_BRI */ + { 95, 1, 8, 3 }, /* SCIF1_TXI */ + { 96, 1, 4, 3 }, /* SCIF2_ERI */ + { 97, 1, 4, 3 }, /* SCIF2_RXI */ + { 98, 1, 4, 3 }, /* SCIF2_BRI */ + { 99, 1, 4, 3 }, /* SCIF2_TXI */ }; +static unsigned int ipr_offsets[] = { + 0xf8080000, /* IPRC */ + 0xf8080002, /* IPRD */ + 0xf8080004, /* IPRE */ + 0xf8080006, /* IPRF */ + 0xf8080008, /* IPRG */ +}; + +/* given the IPR index return the address of the IPR register */ +unsigned int map_ipridx_to_addr(int idx) +{ + if (unlikely(idx >= ARRAY_SIZE(ipr_offsets))) + return 0; + return ipr_offsets[idx]; +} + void __init init_IRQ_ipr(void) { make_ipr_irq(sh7619_ipr_map, ARRAY_SIZE(sh7619_ipr_map)); diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 87c6c05..426f6db 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -17,14 +17,14 @@ #include int __init detect_cpu_and_cache_system(void) { /* Just SH7206 for now .. */ - cpu_data->type = CPU_SH7206; + current_cpu_data.type = CPU_SH7206; - cpu_data->dcache.ways = 4; - cpu_data->dcache.way_incr = (1 << 11); - cpu_data->dcache.sets = 128; - cpu_data->dcache.entry_shift = 4; - cpu_data->dcache.linesz = L1_CACHE_BYTES; - cpu_data->dcache.flags = 0; + current_cpu_data.dcache.ways = 4; + current_cpu_data.dcache.way_incr = (1 << 11); + current_cpu_data.dcache.sets = 128; + current_cpu_data.dcache.entry_shift = 4; + current_cpu_data.dcache.linesz = L1_CACHE_BYTES; + current_cpu_data.dcache.flags = 0; /* * The icache is the same as the dcache as far as this setup is @@ -32,7 +32,7 @@ int __init detect_cpu_and_cache_system(v * lacks the U bit that the dcache has, none of this has any bearing * on the cache info. */ - cpu_data->icache = cpu_data->dcache; + current_cpu_data.icache = current_cpu_data.dcache; return 0; } diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index 4b60fcc..4ed9110 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c @@ -57,55 +57,52 @@ static int __init sh7206_devices_setup(v } __initcall(sh7206_devices_setup); -#define INTC_IPR08 0xfffe0c04UL -#define INTC_IPR09 0xfffe0c06UL -#define INTC_IPR14 0xfffe0c10UL - -#define CMI0_IRQ 140 - -#define MTU1_TGI1A 164 - -#define SCIF0_BRI_IRQ 240 -#define SCIF0_ERI_IRQ 241 -#define SCIF0_RXI_IRQ 242 -#define SCIF0_TXI_IRQ 243 - -#define SCIF1_BRI_IRQ 244 -#define SCIF1_ERI_IRQ 245 -#define SCIF1_RXI_IRQ 246 -#define SCIF1_TXI_IRQ 247 - -#define SCIF2_BRI_IRQ 248 -#define SCIF2_ERI_IRQ 249 -#define SCIF2_RXI_IRQ 250 -#define SCIF2_TXI_IRQ 251 - -#define SCIF3_BRI_IRQ 252 -#define SCIF3_ERI_IRQ 253 -#define SCIF3_RXI_IRQ 254 -#define SCIF3_TXI_IRQ 255 - static struct ipr_data sh7206_ipr_map[] = { - { CMI0_IRQ, INTC_IPR08, 3, 2 }, - { MTU2_TGI1A, INTC_IPR09, 1, 2 }, - { SCIF0_ERI_IRQ, INTC_IPR14, 3, 3 }, - { SCIF0_RXI_IRQ, INTC_IPR14, 3, 3 }, - { SCIF0_BRI_IRQ, INTC_IPR14, 3, 3 }, - { SCIF0_TXI_IRQ, INTC_IPR14, 3, 3 }, - { SCIF1_ERI_IRQ, INTC_IPR14, 2, 3 }, - { SCIF1_RXI_IRQ, INTC_IPR14, 2, 3 }, - { SCIF1_BRI_IRQ, INTC_IPR14, 2, 3 }, - { SCIF1_TXI_IRQ, INTC_IPR14, 2, 3 }, - { SCIF2_ERI_IRQ, INTC_IPR14, 1, 3 }, - { SCIF2_RXI_IRQ, INTC_IPR14, 1, 3 }, - { SCIF2_BRI_IRQ, INTC_IPR14, 1, 3 }, - { SCIF2_TXI_IRQ, INTC_IPR14, 1, 3 }, - { SCIF3_ERI_IRQ, INTC_IPR14, 0, 3 }, - { SCIF3_RXI_IRQ, INTC_IPR14, 0, 3 }, - { SCIF3_BRI_IRQ, INTC_IPR14, 0, 3 }, - { SCIF3_TXI_IRQ, INTC_IPR14, 0, 3 }, + { 140, 7, 12, 2 }, /* CMI0 */ + { 164, 8, 4, 2 }, /* MTU2_TGI1A */ + { 240, 13, 12, 3 }, /* SCIF0_BRI */ + { 241, 13, 12, 3 }, /* SCIF0_ERI */ + { 242, 13, 12, 3 }, /* SCIF0_RXI */ + { 243, 13, 12, 3 }, /* SCIF0_TXI */ + { 244, 13, 8, 3 }, /* SCIF1_BRI */ + { 245, 13, 8, 3 }, /* SCIF1_ERI */ + { 246, 13, 8, 3 }, /* SCIF1_RXI */ + { 247, 13, 8, 3 }, /* SCIF1_TXI */ + { 248, 13, 4, 3 }, /* SCIF2_BRI */ + { 249, 13, 4, 3 }, /* SCIF2_ERI */ + { 250, 13, 4, 3 }, /* SCIF2_RXI */ + { 251, 13, 4, 3 }, /* SCIF2_TXI */ + { 252, 13, 0, 3 }, /* SCIF3_BRI */ + { 253, 13, 0, 3 }, /* SCIF3_ERI */ + { 254, 13, 0, 3 }, /* SCIF3_RXI */ + { 255, 13, 0, 3 }, /* SCIF3_TXI */ +}; + +static unsigned int ipr_offsets[] = { + 0xfffe0818, /* IPR01 */ + 0xfffe081a, /* IPR02 */ + 0, /* unused */ + 0, /* unused */ + 0xfffe0820, /* IPR05 */ + 0xfffe0c00, /* IPR06 */ + 0xfffe0c02, /* IPR07 */ + 0xfffe0c04, /* IPR08 */ + 0xfffe0c06, /* IPR09 */ + 0xfffe0c08, /* IPR10 */ + 0xfffe0c0a, /* IPR11 */ + 0xfffe0c0c, /* IPR12 */ + 0xfffe0c0e, /* IPR13 */ + 0xfffe0c10, /* IPR14 */ }; +/* given the IPR index return the address of the IPR register */ +unsigned int map_ipridx_to_addr(int idx) +{ + if (unlikely(idx >= ARRAY_SIZE(ipr_offsets))) + return 0; + return ipr_offsets[idx]; +} + void __init init_IRQ_ipr(void) { make_ipr_irq(sh7206_ipr_map, ARRAY_SIZE(sh7206_ipr_map)); diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S index 8c0dc27..c19205b 100644 --- a/arch/sh/kernel/cpu/sh3/entry.S +++ b/arch/sh/kernel/cpu/sh3/entry.S @@ -13,10 +13,8 @@ #include #include #include #include -#include #include -#include -#include +#include ! NOTE: ! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address @@ -138,14 +136,29 @@ ENTRY(tlb_protection_violation_store) call_dpf: mov.l 1f, r0 - mov.l @r0, r6 ! address + mov r5, r8 + mov.l @r0, r6 + mov r6, r9 + mov.l 2f, r0 + sts pr, r10 + jsr @r0 + mov r15, r4 + ! + tst r0, r0 + bf/s 0f + lds r10, pr + rts + nop +0: sti mov.l 3f, r0 - + mov r9, r6 + mov r8, r5 jmp @r0 - mov r15, r4 ! regs + mov r15, r4 .align 2 1: .long MMU_TEA +2: .long __do_page_fault 3: .long do_page_fault .align 2 @@ -173,7 +186,7 @@ #endif /* CONFIG_MMU */ #if defined(CONFIG_SH_STANDARD_BIOS) /* Unwind the stack and jmp to the debug entry */ -debug_kernel_fw: +ENTRY(sh_bios_handler) mov.l @r15+, r0 mov.l @r15+, r1 mov.l @r15+, r2 @@ -332,175 +345,9 @@ general_exception: ! ! -/* This code makes some assumptions to improve performance. - * Make sure they are stil true. */ -#if PTRS_PER_PGD != PTRS_PER_PTE -#error PGD and PTE sizes don't match -#endif - -/* gas doesn't flag impossible values for mov #immediate as an error */ -#if (_PAGE_PRESENT >> 2) > 0x7f -#error cannot load PAGE_PRESENT as an immediate -#endif -#if _PAGE_DIRTY > 0x7f -#error cannot load PAGE_DIRTY as an immediate -#endif -#if (_PAGE_PRESENT << 2) != _PAGE_ACCESSED -#error cannot derive PAGE_ACCESSED from PAGE_PRESENT -#endif - -#if defined(CONFIG_CPU_SH4) -#define ldmmupteh(r) mov.l 8f, r -#else -#define ldmmupteh(r) mov #MMU_PTEH, r -#endif - .balign 1024,0,1024 tlb_miss: -#ifdef COUNT_EXCEPTIONS - ! Increment the counts - mov.l 9f, k1 - mov.l @k1, k2 - add #1, k2 - mov.l k2, @k1 -#endif - - ! k0 scratch - ! k1 pgd and pte pointers - ! k2 faulting address - ! k3 pgd and pte index masks - ! k4 shift - - ! Load up the pgd entry (k1) - - ldmmupteh(k0) ! 9 LS (latency=2) MMU_PTEH - - mov.w 4f, k3 ! 8 LS (latency=2) (PTRS_PER_PGD-1) << 2 - mov #-(PGDIR_SHIFT-2), k4 ! 6 EX - - mov.l @(MMU_TEA-MMU_PTEH,k0), k2 ! 18 LS (latency=2) - - mov.l @(MMU_TTB-MMU_PTEH,k0), k1 ! 18 LS (latency=2) - - mov k2, k0 ! 5 MT (latency=0) - shld k4, k0 ! 99 EX - - and k3, k0 ! 78 EX - - mov.l @(k0, k1), k1 ! 21 LS (latency=2) - mov #-(PAGE_SHIFT-2), k4 ! 6 EX - - ! Load up the pte entry (k2) - - mov k2, k0 ! 5 MT (latency=0) - shld k4, k0 ! 99 EX - - tst k1, k1 ! 86 MT - - bt 20f ! 110 BR - - and k3, k0 ! 78 EX - mov.w 5f, k4 ! 8 LS (latency=2) _PAGE_PRESENT - - mov.l @(k0, k1), k2 ! 21 LS (latency=2) - add k0, k1 ! 49 EX - -#ifdef CONFIG_CPU_HAS_PTEA - ! Test the entry for present and _PAGE_ACCESSED - - mov #-28, k3 ! 6 EX - mov k2, k0 ! 5 MT (latency=0) - - tst k4, k2 ! 68 MT - shld k3, k0 ! 99 EX - - bt 20f ! 110 BR - - ! Set PTEA register - ! MMU_PTEA = ((pteval >> 28) & 0xe) | (pteval & 0x1) - ! - ! k0=pte>>28, k1=pte*, k2=pte, k3=, k4=_PAGE_PRESENT - - and #0xe, k0 ! 79 EX - - mov k0, k3 ! 5 MT (latency=0) - mov k2, k0 ! 5 MT (latency=0) - - and #1, k0 ! 79 EX - - or k0, k3 ! 82 EX - - ldmmupteh(k0) ! 9 LS (latency=2) - shll2 k4 ! 101 EX _PAGE_ACCESSED - - tst k4, k2 ! 68 MT - - mov.l k3, @(MMU_PTEA-MMU_PTEH,k0) ! 27 LS - - mov.l 7f, k3 ! 9 LS (latency=2) _PAGE_FLAGS_HARDWARE_MASK - - ! k0=MMU_PTEH, k1=pte*, k2=pte, k3=_PAGE_FLAGS_HARDWARE, k4=_PAGE_ACCESSED -#else - - ! Test the entry for present and _PAGE_ACCESSED - - mov.l 7f, k3 ! 9 LS (latency=2) _PAGE_FLAGS_HARDWARE_MASK - tst k4, k2 ! 68 MT - - shll2 k4 ! 101 EX _PAGE_ACCESSED - ldmmupteh(k0) ! 9 LS (latency=2) - - bt 20f ! 110 BR - tst k4, k2 ! 68 MT - - ! k0=MMU_PTEH, k1=pte*, k2=pte, k3=_PAGE_FLAGS_HARDWARE, k4=_PAGE_ACCESSED - -#endif - - ! Set up the entry - - and k2, k3 ! 78 EX - bt/s 10f ! 108 BR - - mov.l k3, @(MMU_PTEL-MMU_PTEH,k0) ! 27 LS - - ldtlb ! 128 CO - - ! At least one instruction between ldtlb and rte - nop ! 119 NOP - - rte ! 126 CO - - nop ! 119 NOP - - -10: or k4, k2 ! 82 EX - - ldtlb ! 128 CO - - ! At least one instruction between ldtlb and rte - mov.l k2, @k1 ! 27 LS - - rte ! 126 CO - - ! Note we cannot execute mov here, because it is executed after - ! restoring SSR, so would be executed in user space. - nop ! 119 NOP - - - .align 5 - ! Once cache line if possible... -1: .long swapper_pg_dir -4: .short (PTRS_PER_PGD-1) << 2 -5: .short _PAGE_PRESENT -7: .long _PAGE_FLAGS_HARDWARE_MASK -8: .long MMU_PTEH -#ifdef COUNT_EXCEPTIONS -9: .long exception_count_miss -#endif - - ! Either pgd or pte not present -20: mov.l 1f, k2 + mov.l 1f, k2 mov.l 4f, k3 bra handle_exception mov.l @k2, k2 @@ -651,15 +498,6 @@ #endif bf interrupt_exception shlr2 r8 shlr r8 - -#ifdef COUNT_EXCEPTIONS - mov.l 5f, r9 - add r8, r9 - mov.l @r9, r10 - add #1, r10 - mov.l r10, @r9 -#endif - mov.l 4f, r9 add r8, r9 mov.l @r9, r9 @@ -673,9 +511,6 @@ #endif 2: .long 0x000080f0 ! FD=1, IMASK=15 3: .long 0xcfffffff ! RB=0, BL=0 4: .long exception_handling_table -#ifdef COUNT_EXCEPTIONS -5: .long exception_count_table -#endif interrupt_exception: mov.l 1f, r9 diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c index e670988..821b0ab 100644 --- a/arch/sh/kernel/cpu/sh3/probe.c +++ b/arch/sh/kernel/cpu/sh3/probe.c @@ -50,41 +50,41 @@ int __init detect_cpu_and_cache_system(v back_to_P1(); - cpu_data->dcache.ways = 4; - cpu_data->dcache.entry_shift = 4; - cpu_data->dcache.linesz = L1_CACHE_BYTES; - cpu_data->dcache.flags = 0; + current_cpu_data.dcache.ways = 4; + current_cpu_data.dcache.entry_shift = 4; + current_cpu_data.dcache.linesz = L1_CACHE_BYTES; + current_cpu_data.dcache.flags = 0; /* * 7709A/7729 has 16K cache (256-entry), while 7702 has only * 2K(direct) 7702 is not supported (yet) */ if (data0 == data1 && data2 == data3) { /* Shadow */ - cpu_data->dcache.way_incr = (1 << 11); - cpu_data->dcache.entry_mask = 0x7f0; - cpu_data->dcache.sets = 128; - cpu_data->type = CPU_SH7708; + current_cpu_data.dcache.way_incr = (1 << 11); + current_cpu_data.dcache.entry_mask = 0x7f0; + current_cpu_data.dcache.sets = 128; + current_cpu_data.type = CPU_SH7708; - cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC; + current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC; } else { /* 7709A or 7729 */ - cpu_data->dcache.way_incr = (1 << 12); - cpu_data->dcache.entry_mask = 0xff0; - cpu_data->dcache.sets = 256; - cpu_data->type = CPU_SH7729; + current_cpu_data.dcache.way_incr = (1 << 12); + current_cpu_data.dcache.entry_mask = 0xff0; + current_cpu_data.dcache.sets = 256; + current_cpu_data.type = CPU_SH7729; #if defined(CONFIG_CPU_SUBTYPE_SH7706) - cpu_data->type = CPU_SH7706; + current_cpu_data.type = CPU_SH7706; #endif #if defined(CONFIG_CPU_SUBTYPE_SH7710) - cpu_data->type = CPU_SH7710; + current_cpu_data.type = CPU_SH7710; #endif #if defined(CONFIG_CPU_SUBTYPE_SH7705) - cpu_data->type = CPU_SH7705; + current_cpu_data.type = CPU_SH7705; #if defined(CONFIG_SH7705_CACHE_32KB) - cpu_data->dcache.way_incr = (1 << 13); - cpu_data->dcache.entry_mask = 0x1ff0; - cpu_data->dcache.sets = 512; + current_cpu_data.dcache.way_incr = (1 << 13); + current_cpu_data.dcache.entry_mask = 0x1ff0; + current_cpu_data.dcache.sets = 512; ctrl_outl(CCR_CACHE_32KB, CCR3); #else ctrl_outl(CCR_CACHE_16KB, CCR3); @@ -95,8 +95,8 @@ #endif /* * SH-3 doesn't have separate caches */ - cpu_data->dcache.flags |= SH_CACHE_COMBINED; - cpu_data->icache = cpu_data->dcache; + current_cpu_data.dcache.flags |= SH_CACHE_COMBINED; + current_cpu_data.icache = current_cpu_data.dcache; return 0; } diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c b/arch/sh/kernel/cpu/sh3/setup-sh7709.c index ff43ef2..dc9b211 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c @@ -51,3 +51,24 @@ static int __init sh7709_devices_setup(v ARRAY_SIZE(sh7709_devices)); } __initcall(sh7709_devices_setup); + +#define IPRx(A,N) .addr=A, .shift=0*N*-1 +#define IPRA(N) IPRx(0xfffffee2UL,N) +#define IPRB(N) IPRx(0xfffffee4UL,N) +#define IPRE(N) IPRx(0xa400001aUL,N) + +static struct ipr_data sh7709_ipr_map[] = { + [16] = { IPRA(15-12), 2 }, /* TMU TUNI0 */ + [17] = { IPRA(11-8), 4 }, /* TMU TUNI1 */ + [22] = { IPRA(3-0), 2 }, /* RTC CUI */ + [23 ... 26] = { IPRB(7-4), 3 }, /* SCI */ + [27] = { IPRB(15-12), 2 }, /* WDT ITI */ + [48 ... 51] = { IPRE(15-12), 7 }, /* DMA */ + [52 ... 55] = { IPRE(11-8), 3 }, /* IRDA */ + [56 ... 59] = { IPRE(7-4), 3 }, /* SCIF */ +}; + +void __init init_IRQ_ipr() +{ + make_ipr_irq(sh7709_ipr_map, ARRAY_SIZE(sh7709_ipr_map)); +} diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 9031a22..9d28c88 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -10,11 +10,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ - #include +#include #include #include -#include int __init detect_cpu_and_cache_system(void) { @@ -36,20 +35,20 @@ int __init detect_cpu_and_cache_system(v /* * Setup some sane SH-4 defaults for the icache */ - cpu_data->icache.way_incr = (1 << 13); - cpu_data->icache.entry_shift = 5; - cpu_data->icache.sets = 256; - cpu_data->icache.ways = 1; - cpu_data->icache.linesz = L1_CACHE_BYTES; + current_cpu_data.icache.way_incr = (1 << 13); + current_cpu_data.icache.entry_shift = 5; + current_cpu_data.icache.sets = 256; + current_cpu_data.icache.ways = 1; + current_cpu_data.icache.linesz = L1_CACHE_BYTES; /* * And again for the dcache .. */ - cpu_data->dcache.way_incr = (1 << 14); - cpu_data->dcache.entry_shift = 5; - cpu_data->dcache.sets = 512; - cpu_data->dcache.ways = 1; - cpu_data->dcache.linesz = L1_CACHE_BYTES; + current_cpu_data.dcache.way_incr = (1 << 14); + current_cpu_data.dcache.entry_shift = 5; + current_cpu_data.dcache.sets = 512; + current_cpu_data.dcache.ways = 1; + current_cpu_data.dcache.linesz = L1_CACHE_BYTES; /* * Setup some generic flags we can probe @@ -57,16 +56,16 @@ int __init detect_cpu_and_cache_system(v */ if (((pvr >> 16) & 0xff) == 0x10) { if ((cvr & 0x02000000) == 0) - cpu_data->flags |= CPU_HAS_L2_CACHE; + current_cpu_data.flags |= CPU_HAS_L2_CACHE; if ((cvr & 0x10000000) == 0) - cpu_data->flags |= CPU_HAS_DSP; + current_cpu_data.flags |= CPU_HAS_DSP; - cpu_data->flags |= CPU_HAS_LLSC; + current_cpu_data.flags |= CPU_HAS_LLSC; } /* FPU detection works for everyone */ if ((cvr & 0x20000000) == 1) - cpu_data->flags |= CPU_HAS_FPU; + current_cpu_data.flags |= CPU_HAS_FPU; /* Mask off the upper chip ID */ pvr &= 0xffff; @@ -77,151 +76,151 @@ int __init detect_cpu_and_cache_system(v */ switch (pvr) { case 0x205: - cpu_data->type = CPU_SH7750; - cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | + current_cpu_data.type = CPU_SH7750; + current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | CPU_HAS_PERF_COUNTER; break; case 0x206: - cpu_data->type = CPU_SH7750S; - cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | + current_cpu_data.type = CPU_SH7750S; + current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | CPU_HAS_PERF_COUNTER; break; case 0x1100: - cpu_data->type = CPU_SH7751; - cpu_data->flags |= CPU_HAS_FPU; + current_cpu_data.type = CPU_SH7751; + current_cpu_data.flags |= CPU_HAS_FPU; break; case 0x2000: - cpu_data->type = CPU_SH73180; - cpu_data->icache.ways = 4; - cpu_data->dcache.ways = 4; - cpu_data->flags |= CPU_HAS_LLSC; + current_cpu_data.type = CPU_SH73180; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; + current_cpu_data.flags |= CPU_HAS_LLSC; break; case 0x2001: case 0x2004: - cpu_data->type = CPU_SH7770; - cpu_data->icache.ways = 4; - cpu_data->dcache.ways = 4; + current_cpu_data.type = CPU_SH7770; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; - cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC; + current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; break; case 0x2006: case 0x200A: if (prr == 0x61) - cpu_data->type = CPU_SH7781; + current_cpu_data.type = CPU_SH7781; else - cpu_data->type = CPU_SH7780; + current_cpu_data.type = CPU_SH7780; - cpu_data->icache.ways = 4; - cpu_data->dcache.ways = 4; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; - cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | + current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | CPU_HAS_LLSC; break; case 0x3000: case 0x3003: case 0x3009: - cpu_data->type = CPU_SH7343; - cpu_data->icache.ways = 4; - cpu_data->dcache.ways = 4; - cpu_data->flags |= CPU_HAS_LLSC; + current_cpu_data.type = CPU_SH7343; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; + current_cpu_data.flags |= CPU_HAS_LLSC; break; case 0x3008: if (prr == 0xa0) { - cpu_data->type = CPU_SH7722; - cpu_data->icache.ways = 4; - cpu_data->dcache.ways = 4; - cpu_data->flags |= CPU_HAS_LLSC; + current_cpu_data.type = CPU_SH7722; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; + current_cpu_data.flags |= CPU_HAS_LLSC; } break; case 0x8000: - cpu_data->type = CPU_ST40RA; - cpu_data->flags |= CPU_HAS_FPU; + current_cpu_data.type = CPU_ST40RA; + current_cpu_data.flags |= CPU_HAS_FPU; break; case 0x8100: - cpu_data->type = CPU_ST40GX1; - cpu_data->flags |= CPU_HAS_FPU; + current_cpu_data.type = CPU_ST40GX1; + current_cpu_data.flags |= CPU_HAS_FPU; break; case 0x700: - cpu_data->type = CPU_SH4_501; - cpu_data->icache.ways = 2; - cpu_data->dcache.ways = 2; + current_cpu_data.type = CPU_SH4_501; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; break; case 0x600: - cpu_data->type = CPU_SH4_202; - cpu_data->icache.ways = 2; - cpu_data->dcache.ways = 2; - cpu_data->flags |= CPU_HAS_FPU; + current_cpu_data.type = CPU_SH4_202; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; + current_cpu_data.flags |= CPU_HAS_FPU; break; case 0x500 ... 0x501: switch (prr) { case 0x10: - cpu_data->type = CPU_SH7750R; + current_cpu_data.type = CPU_SH7750R; break; case 0x11: - cpu_data->type = CPU_SH7751R; + current_cpu_data.type = CPU_SH7751R; break; case 0x50 ... 0x5f: - cpu_data->type = CPU_SH7760; + current_cpu_data.type = CPU_SH7760; break; } - cpu_data->icache.ways = 2; - cpu_data->dcache.ways = 2; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; - cpu_data->flags |= CPU_HAS_FPU; + current_cpu_data.flags |= CPU_HAS_FPU; break; default: - cpu_data->type = CPU_SH_NONE; + current_cpu_data.type = CPU_SH_NONE; break; } #ifdef CONFIG_SH_DIRECT_MAPPED - cpu_data->icache.ways = 1; - cpu_data->dcache.ways = 1; + current_cpu_data.icache.ways = 1; + current_cpu_data.dcache.ways = 1; #endif #ifdef CONFIG_CPU_HAS_PTEA - cpu_data->flags |= CPU_HAS_PTEA; + current_cpu_data.flags |= CPU_HAS_PTEA; #endif /* * On anything that's not a direct-mapped cache, look to the CVR * for I/D-cache specifics. */ - if (cpu_data->icache.ways > 1) { + if (current_cpu_data.icache.ways > 1) { size = sizes[(cvr >> 20) & 0xf]; - cpu_data->icache.way_incr = (size >> 1); - cpu_data->icache.sets = (size >> 6); + current_cpu_data.icache.way_incr = (size >> 1); + current_cpu_data.icache.sets = (size >> 6); } /* Setup the rest of the I-cache info */ - cpu_data->icache.entry_mask = cpu_data->icache.way_incr - - cpu_data->icache.linesz; + current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - + current_cpu_data.icache.linesz; - cpu_data->icache.way_size = cpu_data->icache.sets * - cpu_data->icache.linesz; + current_cpu_data.icache.way_size = current_cpu_data.icache.sets * + current_cpu_data.icache.linesz; /* And the rest of the D-cache */ - if (cpu_data->dcache.ways > 1) { + if (current_cpu_data.dcache.ways > 1) { size = sizes[(cvr >> 16) & 0xf]; - cpu_data->dcache.way_incr = (size >> 1); - cpu_data->dcache.sets = (size >> 6); + current_cpu_data.dcache.way_incr = (size >> 1); + current_cpu_data.dcache.sets = (size >> 6); } - cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr - - cpu_data->dcache.linesz; + current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - + current_cpu_data.dcache.linesz; - cpu_data->dcache.way_size = cpu_data->dcache.sets * - cpu_data->dcache.linesz; + current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; /* * Setup the L2 cache desc * * SH-4A's have an optional PIPT L2. */ - if (cpu_data->flags & CPU_HAS_L2_CACHE) { + if (current_cpu_data.flags & CPU_HAS_L2_CACHE) { /* * Size calculation is much more sensible * than it is for the L1. @@ -232,16 +231,22 @@ #endif BUG_ON(!size); - cpu_data->scache.way_incr = (1 << 16); - cpu_data->scache.entry_shift = 5; - cpu_data->scache.ways = 4; - cpu_data->scache.linesz = L1_CACHE_BYTES; - cpu_data->scache.entry_mask = - (cpu_data->scache.way_incr - cpu_data->scache.linesz); - cpu_data->scache.sets = size / - (cpu_data->scache.linesz * cpu_data->scache.ways); - cpu_data->scache.way_size = - (cpu_data->scache.sets * cpu_data->scache.linesz); + current_cpu_data.scache.way_incr = (1 << 16); + current_cpu_data.scache.entry_shift = 5; + current_cpu_data.scache.ways = 4; + current_cpu_data.scache.linesz = L1_CACHE_BYTES; + + current_cpu_data.scache.entry_mask = + (current_cpu_data.scache.way_incr - + current_cpu_data.scache.linesz); + + current_cpu_data.scache.sets = size / + (current_cpu_data.scache.linesz * + current_cpu_data.scache.ways); + + current_cpu_data.scache.way_size = + (current_cpu_data.scache.sets * + current_cpu_data.scache.linesz); } return 0; diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index cbac276..aa26245 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c @@ -101,7 +101,7 @@ static struct ipr_data sh7750_ipr_map[] { 35, 2, 8, 7 }, /* DMAC DMTE1 */ { 36, 2, 8, 7 }, /* DMAC DMTE2 */ { 37, 2, 8, 7 }, /* DMAC DMTE3 */ - { 28, 2, 8, 7 }, /* DMAC DMAE */ + { 38, 2, 8, 7 }, /* DMAC DMAE */ }; static struct ipr_data sh7751_ipr_map[] = { diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 07e5377..b7c7028 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c @@ -52,17 +52,11 @@ static int __init sh7760_devices_setup(v } __initcall(sh7760_devices_setup); -/* - * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0 - */ static struct intc2_data intc2_irq_table[] = { - /* INTPRIO0 | INTMSK0 */ {48, 0, 28, 0, 31, 3}, /* IRQ 4 */ {49, 0, 24, 0, 30, 3}, /* IRQ 3 */ {50, 0, 20, 0, 29, 3}, /* IRQ 2 */ {51, 0, 16, 0, 28, 3}, /* IRQ 1 */ - /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */ - /* INTPRIO4 | INTMSK0 */ {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */ {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */ {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */ @@ -71,18 +65,15 @@ static struct intc2_data intc2_irq_table {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */ {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */ {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */ - /* INTPRIO8 | INTMSK0 */ {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */ {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */ {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */ {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */ {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */ {65, 8, 24, 0, 16, 3}, /* LCDC */ - /* 66, 67 unused */ {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */ {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */ {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */ - /* 71 unused */ {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */ {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */ {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */ @@ -91,26 +82,71 @@ static struct intc2_data intc2_irq_table {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */ {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */ {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */ - /* | INTMSK4 */ {80, 8, 4, 4, 23, 3}, /* SIM_ERI */ {81, 8, 4, 4, 22, 3}, /* SIM_RXI */ {82, 8, 4, 4, 21, 3}, /* SIM_TXI */ {83, 8, 4, 4, 20, 3}, /* SIM_TEI */ {84, 8, 0, 4, 19, 3}, /* HSPII */ - /* INTPRIOC | INTMSK4 */ - /* 85-87 unused/reserved */ {88, 12, 20, 4, 18, 3}, /* MMCI0 */ {89, 12, 20, 4, 17, 3}, /* MMCI1 */ {90, 12, 20, 4, 16, 3}, /* MMCI2 */ {91, 12, 20, 4, 15, 3}, /* MMCI3 */ - {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/ - /* 93-107 reserved/undocumented */ + {92, 12, 12, 4, 6, 3}, /* MFI */ {108,12, 4, 4, 1, 3}, /* ADC */ {109,12, 0, 4, 0, 3}, /* CMTI */ - /* 110-111 reserved/unused */ }; +static struct ipr_data sh7760_ipr_map[] = { + /* IRQ, IPR-idx, shift, priority */ + { 16, 0, 12, 2 }, /* TMU0 TUNI*/ + { 17, 0, 8, 2 }, /* TMU1 TUNI */ + { 18, 0, 4, 2 }, /* TMU2 TUNI */ + { 19, 0, 4, 2 }, /* TMU2 TIPCI */ + { 27, 1, 12, 2 }, /* WDT ITI */ + { 28, 1, 8, 2 }, /* REF RCMI */ + { 29, 1, 8, 2 }, /* REF ROVI */ + { 32, 2, 0, 7 }, /* HUDI */ + { 33, 2, 12, 7 }, /* GPIOI */ + { 34, 2, 8, 7 }, /* DMAC DMTE0 */ + { 35, 2, 8, 7 }, /* DMAC DMTE1 */ + { 36, 2, 8, 7 }, /* DMAC DMTE2 */ + { 37, 2, 8, 7 }, /* DMAC DMTE3 */ + { 38, 2, 8, 7 }, /* DMAC DMAE */ + { 44, 2, 8, 7 }, /* DMAC DMTE4 */ + { 45, 2, 8, 7 }, /* DMAC DMTE5 */ + { 46, 2, 8, 7 }, /* DMAC DMTE6 */ + { 47, 2, 8, 7 }, /* DMAC DMTE7 */ +/* these here are only valid if INTC_ICR bit 7 is set to 1! + * XXX: maybe CONFIG_SH_IRLMODE symbol? SH7751 could use it too */ +#if 0 + { 2, 3, 12, 3 }, /* IRL0 */ + { 5, 3, 8, 3 }, /* IRL1 */ + { 8, 3, 4, 3 }, /* IRL2 */ + { 11, 3, 0, 3 }, /* IRL3 */ +#endif +}; + +static unsigned long ipr_offsets[] = { + 0xffd00004UL, /* 0: IPRA */ + 0xffd00008UL, /* 1: IPRB */ + 0xffd0000cUL, /* 2: IPRC */ + 0xffd00010UL, /* 3: IPRD */ +}; + +/* given the IPR index return the address of the IPR register */ +unsigned int map_ipridx_to_addr(int idx) +{ + if (idx >= ARRAY_SIZE(ipr_offsets)) + return 0; + return ipr_offsets[idx]; +} + void __init init_IRQ_intc2(void) { make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table)); } + +void __init init_IRQ_ipr(void) +{ + make_ipr_irq(sh7760_ipr_map, ARRAY_SIZE(sh7760_ipr_map)); +} diff --git a/arch/sh/kernel/debugtraps.S b/arch/sh/kernel/debugtraps.S new file mode 100644 index 0000000..13b6674 --- /dev/null +++ b/arch/sh/kernel/debugtraps.S @@ -0,0 +1,41 @@ +/* + * arch/sh/kernel/debugtraps.S + * + * Debug trap jump tables for SuperH + * + * Copyright (C) 2006 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include + +#if !defined(CONFIG_SH_KGDB) +#define kgdb_handle_exception debug_trap_handler +#endif + +#if !defined(CONFIG_SH_STANDARD_BIOS) +#define sh_bios_handler debug_trap_handler +#endif + + .data + +ENTRY(debug_trap_table) + .long debug_trap_handler /* 0x30 */ + .long debug_trap_handler /* 0x31 */ + .long debug_trap_handler /* 0x32 */ + .long debug_trap_handler /* 0x33 */ + .long debug_trap_handler /* 0x34 */ + .long debug_trap_handler /* 0x35 */ + .long debug_trap_handler /* 0x36 */ + .long debug_trap_handler /* 0x37 */ + .long debug_trap_handler /* 0x38 */ + .long debug_trap_handler /* 0x39 */ + .long debug_trap_handler /* 0x3a */ + .long debug_trap_handler /* 0x3b */ + .long kgdb_handle_exception /* 0x3c */ + .long debug_trap_handler /* 0x3d */ + .long bug_trap_handler /* 0x3e */ + .long sh_bios_handler /* 0x3f */ diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c index 560b91c..9048c03 100644 --- a/arch/sh/kernel/early_printk.c +++ b/arch/sh/kernel/early_printk.c @@ -106,12 +106,32 @@ static struct console scif_console = { }; #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS) +#define DEFAULT_BAUD 115200 /* * Simple SCIF init, primarily aimed at SH7750 and other similar SH-4 * devices that aren't using sh-ipl+g. */ -static void scif_sercon_init(int baud) +static void scif_sercon_init(char *s) { + unsigned baud = DEFAULT_BAUD; + char *e; + + if (*s == ',') + ++s; + + if (*s) { + /* ignore ioport/device name */ + s += strcspn(s, ","); + if (*s == ',') + s++; + } + + if (*s) { + baud = simple_strtoul(s, &e, 0); + if (baud == 0 || s == e) + baud = DEFAULT_BAUD; + } + ctrl_outw(0, scif_port.mapbase + 8); ctrl_outw(0, scif_port.mapbase); @@ -167,7 +187,7 @@ #if defined(CONFIG_EARLY_SCIF_CONSOLE) early_console = &scif_console; #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS) - scif_sercon_init(115200); + scif_sercon_init(buf + 6); #endif } #endif diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S index fc279ae..ab4ebb8 100644 --- a/arch/sh/kernel/entry-common.S +++ b/arch/sh/kernel/entry-common.S @@ -54,79 +54,24 @@ # define preempt_stop() # define resume_kernel __restore_all #endif -#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) -! Handle kernel debug if either kgdb (SW) or gdb-stub (FW) is present. -! If both are configured, handle the debug traps (breakpoints) in SW, -! but still allow BIOS traps to FW. - - .align 2 -debug_kernel: -#if defined(CONFIG_SH_STANDARD_BIOS) && defined(CONFIG_SH_KGDB) - /* Force BIOS call to FW (debug_trap put TRA in r8) */ - mov r8,r0 - shlr2 r0 - cmp/eq #0x3f,r0 - bt debug_kernel_fw -#endif /* CONFIG_SH_STANDARD_BIOS && CONFIG_SH_KGDB */ - -debug_enter: -#if defined(CONFIG_SH_KGDB) - /* Jump to kgdb, pass stacked regs as arg */ -debug_kernel_sw: - mov.l 3f, r0 - jmp @r0 - mov r15, r4 - .align 2 -3: .long kgdb_handle_exception -#endif /* CONFIG_SH_KGDB */ -#ifdef CONFIG_SH_STANDARD_BIOS - bra debug_kernel_fw - nop -#endif -#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ - - .align 2 -debug_trap: -#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) - mov r8, r0 - shlr2 r0 - cmp/eq #0x3f, r0 ! sh_bios() trap - bf 1f -#ifdef CONFIG_SH_KGDB - cmp/eq #0xff, r0 ! XXX: KGDB trap, fix for SH-2. - bf 1f -#endif - mov #OFF_SR, r0 - mov.l @(r0,r15), r0 ! get status register - shll r0 - shll r0 ! kernel space? - bt/s debug_kernel -1: -#endif - mov.l @r15, r0 ! Restore R0 value - mov.l 1f, r8 - jmp @r8 - nop .align 2 ENTRY(exception_error) ! #ifdef CONFIG_TRACE_IRQFLAGS - mov.l 3f, r0 + mov.l 2f, r0 jsr @r0 nop #endif sti - mov.l 2f, r0 + mov.l 1f, r0 jmp @r0 nop -! .align 2 -1: .long break_point_trap_software -2: .long do_exception_error +1: .long do_exception_error #ifdef CONFIG_TRACE_IRQFLAGS -3: .long trace_hardirqs_on +2: .long trace_hardirqs_on #endif .align 2 @@ -331,16 +276,31 @@ __restore_all: 1: .long restore_all .align 2 -not_syscall_tra: - bra debug_trap - nop - - .align 2 syscall_badsys: ! Bad syscall number mov #-ENOSYS, r0 bra resume_userspace mov.l r0, @(OFF_R0,r15) ! Return value - + +/* + * The main debug trap handler. + * + * r8=TRA (not the trap number!) + * + * Note: This assumes that the trapa value is left in its original + * form (without the shlr2 shift) so the calculation for the jump + * call table offset remains a simple in place mask. + */ +debug_trap: + mov r8, r0 + and #(0xf << 2), r0 + mov.l 1f, r8 + add r0, r8 + mov.l @r8, r8 + jmp @r8 + nop + + .align 2 +1: .long debug_trap_table /* * Syscall interface: @@ -348,17 +308,19 @@ syscall_badsys: ! Bad syscall number * Syscall #: R3 * Arguments #0 to #3: R4--R7 * Arguments #4 to #6: R0, R1, R2 - * TRA: (number of arguments + 0x10) x 4 + * TRA: (number of arguments + ABI revision) x 4 * * This code also handles delegating other traps to the BIOS/gdb stub * according to: * * Trap number - * (TRA>>2) Purpose - * -------- ------- - * 0x0-0xf old syscall ABI - * 0x10-0x1f new syscall ABI - * 0x20-0xff delegated through debug_trap to BIOS/gdb stub. + * (TRA>>2) Purpose + * -------- ------- + * 0x00-0x0f original SH-3/4 syscall ABI (not in general use). + * 0x10-0x1f general SH-3/4 syscall ABI. + * 0x20-0x2f syscall ABI for SH-2 parts. + * 0x30-0x3f debug traps used by the kernel. + * 0x40-0xff Not supported by all parts, so left unhandled. * * Note: When we're first called, the TRA value must be shifted * right 2 bits in order to get the value that was used as the "trapa" @@ -375,17 +337,22 @@ ret_from_fork: nop .align 2 1: .long schedule_tail - ! + +/* + * The poorly named main trapa decode and dispatch routine, for + * system calls and debug traps through their respective jump tables. + */ ENTRY(system_call) #if !defined(CONFIG_CPU_SH2) mov.l 1f, r9 mov.l @r9, r8 ! Read from TRA (Trap Address) Register #endif - ! - ! Is the trap argument >= 0x20? (TRA will be >= 0x80) - mov #0x7f, r9 + /* + * Check the trap type + */ + mov #((0x20 << 2) - 1), r9 cmp/hi r9, r8 - bt/s not_syscall_tra + bt/s debug_trap ! it's a debug trap.. mov #OFF_TRA, r9 add r15, r9 mov.l r8, @r9 ! set TRA value to tra diff --git a/arch/sh/kernel/kgdb_stub.c b/arch/sh/kernel/kgdb_stub.c index 9c6315f..d8927d8 100644 --- a/arch/sh/kernel/kgdb_stub.c +++ b/arch/sh/kernel/kgdb_stub.c @@ -1323,8 +1323,11 @@ #endif } /* There has been an exception, most likely a breakpoint. */ -void kgdb_handle_exception(struct pt_regs *regs) +asmlinkage void kgdb_handle_exception(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs __regs) { + struct pt_regs *regs = RELOC_HIDE(&__regs, 0); int excep_code, vbr_val; int count; int trapa_value = ctrl_inl(TRA); @@ -1368,8 +1371,6 @@ void kgdb_handle_exception(struct pt_reg vbr_val = trap_registers.vbr; asm("ldc %0, vbr": :"r"(vbr_val)); - - return; } /* Trigger a breakpoint by function */ diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c index 486c06e..9d6a438 100644 --- a/arch/sh/kernel/process.c +++ b/arch/sh/kernel/process.c @@ -1,42 +1,30 @@ -/* $Id: process.c,v 1.28 2004/05/05 16:54:23 lethal Exp $ +/* + * arch/sh/kernel/process.c * - * linux/arch/sh/kernel/process.c + * This file handles the architecture-dependent parts of process handling.. * * Copyright (C) 1995 Linus Torvalds * * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC + * Copyright (C) 2002 - 2006 Paul Mundt */ - -/* - * This file handles the architecture-dependent parts of process handling.. - */ - #include -#include #include #include -#include -#include #include -#include #include #include - -#include #include #include -#include #include -static int hlt_counter=0; - +static int hlt_counter; int ubc_usercnt = 0; #define HARD_IDLE_TIMEOUT (HZ / 3) void (*pm_idle)(void); - void (*pm_power_off)(void); EXPORT_SYMBOL(pm_power_off); @@ -44,14 +32,12 @@ void disable_hlt(void) { hlt_counter++; } - EXPORT_SYMBOL(disable_hlt); void enable_hlt(void) { hlt_counter--; } - EXPORT_SYMBOL(enable_hlt); void default_idle(void) @@ -152,19 +138,21 @@ __asm__(".align 5\n" ".align 2\n\t" "1:.long do_exit"); +/* Don't use this in BL=1(cli). Or else, CPU resets! */ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) -{ /* Don't use this in BL=1(cli). Or else, CPU resets! */ +{ struct pt_regs regs; memset(®s, 0, sizeof(regs)); - regs.regs[4] = (unsigned long) arg; - regs.regs[5] = (unsigned long) fn; + regs.regs[4] = (unsigned long)arg; + regs.regs[5] = (unsigned long)fn; - regs.pc = (unsigned long) kernel_thread_helper; + regs.pc = (unsigned long)kernel_thread_helper; regs.sr = (1 << 30); /* Ok, create the new process.. */ - return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); + return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, + ®s, 0, NULL, NULL); } /* @@ -211,21 +199,20 @@ #endif return fpvalid; } -/* +/* * Capture the user space registers if the task is not running (in user space) */ int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs) { struct pt_regs ptregs; - + ptregs = *task_pt_regs(tsk); elf_core_copy_regs(regs, &ptregs); return 1; } -int -dump_task_fpu (struct task_struct *tsk, elf_fpregset_t *fpu) +int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpu) { int fpvalid = 0; @@ -263,12 +250,14 @@ #endif childregs->regs[15] = usp; ti->addr_limit = USER_DS; } else { - childregs->regs[15] = (unsigned long)task_stack_page(p) + THREAD_SIZE; + childregs->regs[15] = (unsigned long)task_stack_page(p) + + THREAD_SIZE; ti->addr_limit = KERNEL_DS; } - if (clone_flags & CLONE_SETTLS) { + + if (clone_flags & CLONE_SETTLS) childregs->gbr = childregs->regs[0]; - } + childregs->regs[0] = 0; /* Set return value for child */ p->thread.sp = (unsigned long) childregs; @@ -280,8 +269,7 @@ #endif } /* Tracing by user break controller. */ -static void -ubc_set_tracing(int asid, unsigned long pc) +static void ubc_set_tracing(int asid, unsigned long pc) { #if defined(CONFIG_CPU_SH4A) unsigned long val; @@ -297,7 +285,7 @@ #if defined(CONFIG_CPU_SH4A) val = (UBC_CRR_RES | UBC_CRR_PCB | UBC_CRR_BIE); ctrl_outl(val, UBC_CRR0); - /* Read UBC register that we writed last. For chekking UBC Register changed */ + /* Read UBC register that we wrote last, for checking update */ val = ctrl_inl(UBC_CRR0); #else /* CONFIG_CPU_SH4A */ @@ -305,13 +293,14 @@ #else /* CONFIG_CPU_SH4A */ #ifdef CONFIG_MMU /* We don't have any ASID settings for the SH-2! */ - if (cpu_data->type != CPU_SH7604) + if (current_cpu_data.type != CPU_SH7604) ctrl_outb(asid, UBC_BASRA); #endif ctrl_outl(0, UBC_BAMRA); - if (cpu_data->type == CPU_SH7729 || cpu_data->type == CPU_SH7710) { + if (current_cpu_data.type == CPU_SH7729 || + current_cpu_data.type == CPU_SH7710) { ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA); ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR); } else { @@ -325,7 +314,8 @@ #endif /* CONFIG_CPU_SH4A */ * switch_to(x,y) should switch tasks from x to y. * */ -struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next) +struct task_struct *__switch_to(struct task_struct *prev, + struct task_struct *next) { #if defined(CONFIG_SH_FPU) unlazy_fpu(prev, task_pt_regs(prev)); @@ -354,7 +344,7 @@ #endif #ifdef CONFIG_MMU /* * Restore the kernel mode register - * k7 (r7_bank1) + * k7 (r7_bank1) */ asm volatile("ldc %0, r7_bank" : /* no output */ @@ -367,7 +357,7 @@ #endif else if (next->thread.ubc_pc && next->mm) { int asid = 0; #ifdef CONFIG_MMU - asid |= next->mm->context.id & MMU_CONTEXT_ASID_MASK; + asid |= cpu_asid(smp_processor_id(), next->mm); #endif ubc_set_tracing(asid, next->thread.ubc_pc); } else { @@ -405,7 +395,8 @@ asmlinkage int sys_clone(unsigned long c if (!newsp) newsp = regs->regs[15]; return do_fork(clone_flags, newsp, regs, 0, - (int __user *)parent_tidptr, (int __user *)child_tidptr); + (int __user *)parent_tidptr, + (int __user *)child_tidptr); } /* @@ -493,9 +484,27 @@ #endif force_sig(SIGTRAP, current); } -asmlinkage void break_point_trap_software(unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7, - struct pt_regs __regs) +/* + * Generic trap handler. + */ +asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs __regs) +{ + struct pt_regs *regs = RELOC_HIDE(&__regs, 0); + + /* Rewind */ + regs->pc -= 2; + + force_sig(SIGTRAP, current); +} + +/* + * Special handler for BUG() traps. + */ +asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs __regs) { struct pt_regs *regs = RELOC_HIDE(&__regs, 0); diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index d6b817a..98802ab 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -1,14 +1,11 @@ /* - * linux/arch/sh/kernel/setup.c + * arch/sh/kernel/setup.c * - * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2002, 2003 Paul Mundt - */ - -/* * This file handles the architecture-dependent parts of initialization + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2002 - 2006 Paul Mundt */ - #include #include #include @@ -395,9 +392,9 @@ static const char *cpu_name[] = { [CPU_SH_NONE] = "Unknown" }; -const char *get_cpu_subtype(void) +const char *get_cpu_subtype(struct sh_cpuinfo *c) { - return cpu_name[boot_cpu_data.type]; + return cpu_name[c->type]; } #ifdef CONFIG_PROC_FS @@ -407,19 +404,19 @@ static const char *cpu_flags[] = { "ptea", "llsc", "l2", NULL }; -static void show_cpuflags(struct seq_file *m) +static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c) { unsigned long i; seq_printf(m, "cpu flags\t:"); - if (!cpu_data->flags) { + if (!c->flags) { seq_printf(m, " %s\n", cpu_flags[0]); return; } for (i = 0; cpu_flags[i]; i++) - if ((cpu_data->flags & (1 << i))) + if ((c->flags & (1 << i))) seq_printf(m, " %s", cpu_flags[i+1]); seq_printf(m, "\n"); @@ -441,16 +438,20 @@ static void show_cacheinfo(struct seq_fi */ static int show_cpuinfo(struct seq_file *m, void *v) { - unsigned int cpu = smp_processor_id(); + struct sh_cpuinfo *c = v; + unsigned int cpu = c - cpu_data; + + if (!cpu_online(cpu)) + return 0; - if (!cpu && cpu_online(cpu)) + if (cpu == 0) seq_printf(m, "machine\t\t: %s\n", get_system_type()); seq_printf(m, "processor\t: %d\n", cpu); seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine); - seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype()); + seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c)); - show_cpuflags(m); + show_cpuflags(m, c); seq_printf(m, "cache type\t: "); @@ -459,22 +460,22 @@ static int show_cpuinfo(struct seq_file * unified cache on the SH-2 and SH-3, as well as the harvard * style cache on the SH-4. */ - if (boot_cpu_data.icache.flags & SH_CACHE_COMBINED) { + if (c->icache.flags & SH_CACHE_COMBINED) { seq_printf(m, "unified\n"); - show_cacheinfo(m, "cache", boot_cpu_data.icache); + show_cacheinfo(m, "cache", c->icache); } else { seq_printf(m, "split (harvard)\n"); - show_cacheinfo(m, "icache", boot_cpu_data.icache); - show_cacheinfo(m, "dcache", boot_cpu_data.dcache); + show_cacheinfo(m, "icache", c->icache); + show_cacheinfo(m, "dcache", c->dcache); } /* Optional secondary cache */ - if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) - show_cacheinfo(m, "scache", boot_cpu_data.scache); + if (c->flags & CPU_HAS_L2_CACHE) + show_cacheinfo(m, "scache", c->scache); seq_printf(m, "bogomips\t: %lu.%02lu\n", - boot_cpu_data.loops_per_jiffy/(500000/HZ), - (boot_cpu_data.loops_per_jiffy/(5000/HZ)) % 100); + c->loops_per_jiffy/(500000/HZ), + (c->loops_per_jiffy/(5000/HZ)) % 100); return show_clocks(m); } diff --git a/arch/sh/kernel/sh_ksyms.c b/arch/sh/kernel/sh_ksyms.c index e610623..fe1b276 100644 --- a/arch/sh/kernel/sh_ksyms.c +++ b/arch/sh/kernel/sh_ksyms.c @@ -105,7 +105,6 @@ #if defined(CONFIG_MMU) && (defined(CONF EXPORT_SYMBOL(clear_user_page); #endif -EXPORT_SYMBOL(flush_tlb_page); EXPORT_SYMBOL(__down_trylock); #ifdef CONFIG_SMP diff --git a/arch/sh/kernel/signal.c b/arch/sh/kernel/signal.c index 379c88b..32f10a0 100644 --- a/arch/sh/kernel/signal.c +++ b/arch/sh/kernel/signal.c @@ -127,7 +127,7 @@ static inline int restore_sigcontext_fpu { struct task_struct *tsk = current; - if (!(cpu_data->flags & CPU_HAS_FPU)) + if (!(current_cpu_data.flags & CPU_HAS_FPU)) return 0; set_used_math(); @@ -140,7 +140,7 @@ static inline int save_sigcontext_fpu(st { struct task_struct *tsk = current; - if (!(cpu_data->flags & CPU_HAS_FPU)) + if (!(current_cpu_data.flags & CPU_HAS_FPU)) return 0; if (!used_math()) { @@ -181,7 +181,7 @@ #define COPY(x) err |= __get_user(regs- #undef COPY #ifdef CONFIG_SH_FPU - if (cpu_data->flags & CPU_HAS_FPU) { + if (current_cpu_data.flags & CPU_HAS_FPU) { int owned_fp; struct task_struct *tsk = current; diff --git a/arch/sh/kernel/syscalls.S b/arch/sh/kernel/syscalls.S index ca81976..38fc8cd 100644 --- a/arch/sh/kernel/syscalls.S +++ b/arch/sh/kernel/syscalls.S @@ -319,15 +319,15 @@ ENTRY(sys_call_table) .long sys_mq_getsetattr .long sys_kexec_load .long sys_waitid - .long sys_ni_syscall /* 285 */ - .long sys_add_key + .long sys_add_key /* 285 */ .long sys_request_key .long sys_keyctl .long sys_ioprio_set - .long sys_ioprio_get /* 290 */ - .long sys_inotify_init + .long sys_ioprio_get + .long sys_inotify_init /* 290 */ .long sys_inotify_add_watch .long sys_inotify_rm_watch + .long sys_ni_syscall .long sys_migrate_pages .long sys_openat /* 295 */ .long sys_mkdirat diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index ec11015..e9f168f 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c @@ -156,13 +156,13 @@ static inline void do_bug_verbose(struct { } #endif /* CONFIG_DEBUG_BUGVERBOSE */ -#endif /* CONFIG_BUG */ void handle_BUG(struct pt_regs *regs) { do_bug_verbose(regs); die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff); } +#endif /* CONFIG_BUG */ /* * handle an instruction that does an unaligned memory access by emulating the @@ -641,7 +641,7 @@ int is_dsp_inst(struct pt_regs *regs) * Safe guard if DSP mode is already enabled or we're lacking * the DSP altogether. */ - if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) + if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) return 0; get_user(inst, ((unsigned short *) regs->pc)); diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index 29f4ee3..6b0d28a 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -20,7 +20,7 @@ config CPU_SH4 bool select CPU_HAS_INTEVT select CPU_HAS_SR_RB - select CPU_HAS_PTEA if !CPU_SUBTYPE_ST40 + select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 config CPU_SH4A bool @@ -72,6 +72,7 @@ config CPU_SUBTYPE_SH7705 config CPU_SUBTYPE_SH7706 bool "Support SH7706 processor" select CPU_SH3 + select CPU_HAS_IPR_IRQ help Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. @@ -92,6 +93,7 @@ config CPU_SUBTYPE_SH7708 config CPU_SUBTYPE_SH7709 bool "Support SH7709 processor" select CPU_SH3 + select CPU_HAS_IPR_IRQ select CPU_HAS_PINT_IRQ help Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. @@ -149,6 +151,7 @@ config CPU_SUBTYPE_SH7760 bool "Support SH7760 processor" select CPU_SH4 select CPU_HAS_INTC2_IRQ + select CPU_HAS_IPR_IRQ config CPU_SUBTYPE_SH4_202 bool "Support SH4-202 processor" diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c index 909dcfa..de6d2c9 100644 --- a/arch/sh/mm/cache-debugfs.c +++ b/arch/sh/mm/cache-debugfs.c @@ -46,10 +46,10 @@ static int cache_seq_show(struct seq_fil if (cache_type == CACHE_TYPE_DCACHE) { base = CACHE_OC_ADDRESS_ARRAY; - cache = &cpu_data->dcache; + cache = ¤t_cpu_data.dcache; } else { base = CACHE_IC_ADDRESS_ARRAY; - cache = &cpu_data->icache; + cache = ¤t_cpu_data.icache; } /* diff --git a/arch/sh/mm/cache-sh3.c b/arch/sh/mm/cache-sh3.c index 838731f..6d1dbec 100644 --- a/arch/sh/mm/cache-sh3.c +++ b/arch/sh/mm/cache-sh3.c @@ -44,11 +44,11 @@ void __flush_wback_region(void *start, i for (v = begin; v < end; v+=L1_CACHE_BYTES) { unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY; - for (j = 0; j < cpu_data->dcache.ways; j++) { + for (j = 0; j < current_cpu_data.dcache.ways; j++) { unsigned long data, addr, p; p = __pa(v); - addr = addrstart | (v & cpu_data->dcache.entry_mask); + addr = addrstart | (v & current_cpu_data.dcache.entry_mask); local_irq_save(flags); data = ctrl_inl(addr); @@ -60,7 +60,7 @@ void __flush_wback_region(void *start, i break; } local_irq_restore(flags); - addrstart += cpu_data->dcache.way_incr; + addrstart += current_cpu_data.dcache.way_incr; } } } @@ -85,7 +85,7 @@ void __flush_purge_region(void *start, i data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */ addr = CACHE_OC_ADDRESS_ARRAY | - (v & cpu_data->dcache.entry_mask) | SH_CACHE_ASSOC; + (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC; ctrl_outl(data, addr); } } diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index c695515..e0cd4b7 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -54,21 +54,21 @@ static void __init emit_cache_params(voi ctrl_inl(CCN_CVR), ctrl_inl(CCN_PRR)); printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n", - cpu_data->icache.ways, - cpu_data->icache.sets, - cpu_data->icache.way_incr); + current_cpu_data.icache.ways, + current_cpu_data.icache.sets, + current_cpu_data.icache.way_incr); printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", - cpu_data->icache.entry_mask, - cpu_data->icache.alias_mask, - cpu_data->icache.n_aliases); + current_cpu_data.icache.entry_mask, + current_cpu_data.icache.alias_mask, + current_cpu_data.icache.n_aliases); printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n", - cpu_data->dcache.ways, - cpu_data->dcache.sets, - cpu_data->dcache.way_incr); + current_cpu_data.dcache.ways, + current_cpu_data.dcache.sets, + current_cpu_data.dcache.way_incr); printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", - cpu_data->dcache.entry_mask, - cpu_data->dcache.alias_mask, - cpu_data->dcache.n_aliases); + current_cpu_data.dcache.entry_mask, + current_cpu_data.dcache.alias_mask, + current_cpu_data.dcache.n_aliases); if (!__flush_dcache_segment_fn) panic("unknown number of cache ways\n"); @@ -87,10 +87,10 @@ void __init p3_cache_init(void) { int i; - compute_alias(&cpu_data->icache); - compute_alias(&cpu_data->dcache); + compute_alias(¤t_cpu_data.icache); + compute_alias(¤t_cpu_data.dcache); - switch (cpu_data->dcache.ways) { + switch (current_cpu_data.dcache.ways) { case 1: __flush_dcache_segment_fn = __flush_dcache_segment_1way; break; @@ -110,7 +110,7 @@ void __init p3_cache_init(void) if (ioremap_page_range(P3SEG, P3SEG + (PAGE_SIZE * 4), 0, PAGE_KERNEL)) panic("%s failed.", __FUNCTION__); - for (i = 0; i < cpu_data->dcache.n_aliases; i++) + for (i = 0; i < current_cpu_data.dcache.n_aliases; i++) mutex_init(&p3map_mutex[i]); } @@ -200,13 +200,14 @@ void flush_cache_sigtramp(unsigned long : /* no output */ : "m" (__m(v))); - index = CACHE_IC_ADDRESS_ARRAY | (v & cpu_data->icache.entry_mask); + index = CACHE_IC_ADDRESS_ARRAY | + (v & current_cpu_data.icache.entry_mask); local_irq_save(flags); jump_to_P2(); - for (i = 0; i < cpu_data->icache.ways; - i++, index += cpu_data->icache.way_incr) + for (i = 0; i < current_cpu_data.icache.ways; + i++, index += current_cpu_data.icache.way_incr) ctrl_outl(0, index); /* Clear out Valid-bit */ back_to_P1(); @@ -223,7 +224,7 @@ static inline void flush_cache_4096(unsi * All types of SH-4 require PC to be in P2 to operate on the I-cache. * Some types of SH-4 require PC to be in P2 to operate on the D-cache. */ - if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG) || + if ((current_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) || (start < CACHE_OC_ADDRESS_ARRAY)) exec_offset = 0x20000000; @@ -236,16 +237,26 @@ static inline void flush_cache_4096(unsi /* * Write back & invalidate the D-cache of the page. * (To avoid "alias" issues) + * + * This uses a lazy write-back on UP, which is explicitly + * disabled on SMP. */ void flush_dcache_page(struct page *page) { - if (test_bit(PG_mapped, &page->flags)) { +#ifndef CONFIG_SMP + struct address_space *mapping = page_mapping(page); + + if (mapping && !mapping_mapped(mapping)) + set_bit(PG_dcache_dirty, &page->flags); + else +#endif + { unsigned long phys = PHYSADDR(page_address(page)); unsigned long addr = CACHE_OC_ADDRESS_ARRAY; int i, n; /* Loop all the D-cache */ - n = cpu_data->dcache.n_aliases; + n = current_cpu_data.dcache.n_aliases; for (i = 0; i < n; i++, addr += 4096) flush_cache_4096(addr, phys); } @@ -277,7 +288,7 @@ static inline void flush_icache_all(void void flush_dcache_all(void) { - (*__flush_dcache_segment_fn)(0UL, cpu_data->dcache.way_size); + (*__flush_dcache_segment_fn)(0UL, current_cpu_data.dcache.way_size); wmb(); } @@ -291,8 +302,8 @@ static void __flush_cache_mm(struct mm_s unsigned long end) { unsigned long d = 0, p = start & PAGE_MASK; - unsigned long alias_mask = cpu_data->dcache.alias_mask; - unsigned long n_aliases = cpu_data->dcache.n_aliases; + unsigned long alias_mask = current_cpu_data.dcache.alias_mask; + unsigned long n_aliases = current_cpu_data.dcache.n_aliases; unsigned long select_bit; unsigned long all_aliases_mask; unsigned long addr_offset; @@ -379,7 +390,7 @@ void flush_cache_mm(struct mm_struct *mm * If cache is only 4k-per-way, there are never any 'aliases'. Since * the cache is physically tagged, the data can just be left in there. */ - if (cpu_data->dcache.n_aliases == 0) + if (current_cpu_data.dcache.n_aliases == 0) return; /* @@ -416,7 +427,7 @@ void flush_cache_page(struct vm_area_str unsigned long phys = pfn << PAGE_SHIFT; unsigned int alias_mask; - alias_mask = cpu_data->dcache.alias_mask; + alias_mask = current_cpu_data.dcache.alias_mask; /* We only need to flush D-cache when we have alias */ if ((address^phys) & alias_mask) { @@ -430,7 +441,7 @@ void flush_cache_page(struct vm_area_str phys); } - alias_mask = cpu_data->icache.alias_mask; + alias_mask = current_cpu_data.icache.alias_mask; if (vma->vm_flags & VM_EXEC) { /* * Evict entries from the portion of the cache from which code @@ -462,7 +473,7 @@ void flush_cache_range(struct vm_area_st * If cache is only 4k-per-way, there are never any 'aliases'. Since * the cache is physically tagged, the data can just be left in there. */ - if (cpu_data->dcache.n_aliases == 0) + if (current_cpu_data.dcache.n_aliases == 0) return; /* @@ -523,7 +534,7 @@ static void __flush_cache_4096(unsigned unsigned long a, ea, p; unsigned long temp_pc; - dcache = &cpu_data->dcache; + dcache = ¤t_cpu_data.dcache; /* Write this way for better assembly. */ way_count = dcache->ways; way_incr = dcache->way_incr; @@ -598,7 +609,7 @@ static void __flush_dcache_segment_1way( base_addr = ((base_addr >> 16) << 16); base_addr |= start; - dcache = &cpu_data->dcache; + dcache = ¤t_cpu_data.dcache; linesz = dcache->linesz; way_incr = dcache->way_incr; way_size = dcache->way_size; @@ -640,7 +651,7 @@ static void __flush_dcache_segment_2way( base_addr = ((base_addr >> 16) << 16); base_addr |= start; - dcache = &cpu_data->dcache; + dcache = ¤t_cpu_data.dcache; linesz = dcache->linesz; way_incr = dcache->way_incr; way_size = dcache->way_size; @@ -699,7 +710,7 @@ static void __flush_dcache_segment_4way( base_addr = ((base_addr >> 16) << 16); base_addr |= start; - dcache = &cpu_data->dcache; + dcache = ¤t_cpu_data.dcache; linesz = dcache->linesz; way_incr = dcache->way_incr; way_size = dcache->way_size; diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c index 045abdf..31f8deb 100644 --- a/arch/sh/mm/cache-sh7705.c +++ b/arch/sh/mm/cache-sh7705.c @@ -3,11 +3,11 @@ * * Copyright (C) 1999, 2000 Niibe Yutaka * Copyright (C) 2004 Alex Song + * Copyright (C) 2006 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * */ #include #include @@ -32,9 +32,9 @@ static inline void cache_wback_all(void) { unsigned long ways, waysize, addrstart; - ways = cpu_data->dcache.ways; - waysize = cpu_data->dcache.sets; - waysize <<= cpu_data->dcache.entry_shift; + ways = current_cpu_data.dcache.ways; + waysize = current_cpu_data.dcache.sets; + waysize <<= current_cpu_data.dcache.entry_shift; addrstart = CACHE_OC_ADDRESS_ARRAY; @@ -43,7 +43,7 @@ static inline void cache_wback_all(void) for (addr = addrstart; addr < addrstart + waysize; - addr += cpu_data->dcache.linesz) { + addr += current_cpu_data.dcache.linesz) { unsigned long data; int v = SH_CACHE_UPDATED | SH_CACHE_VALID; @@ -51,10 +51,9 @@ static inline void cache_wback_all(void) if ((data & v) == v) ctrl_outl(data & ~v, addr); - } - addrstart += cpu_data->dcache.way_incr; + addrstart += current_cpu_data.dcache.way_incr; } while (--ways); } @@ -94,9 +93,9 @@ static void __flush_dcache_page(unsigned local_irq_save(flags); jump_to_P2(); - ways = cpu_data->dcache.ways; - waysize = cpu_data->dcache.sets; - waysize <<= cpu_data->dcache.entry_shift; + ways = current_cpu_data.dcache.ways; + waysize = current_cpu_data.dcache.sets; + waysize <<= current_cpu_data.dcache.entry_shift; addrstart = CACHE_OC_ADDRESS_ARRAY; @@ -105,7 +104,7 @@ static void __flush_dcache_page(unsigned for (addr = addrstart; addr < addrstart + waysize; - addr += cpu_data->dcache.linesz) { + addr += current_cpu_data.dcache.linesz) { unsigned long data; data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID); @@ -115,7 +114,7 @@ static void __flush_dcache_page(unsigned } } - addrstart += cpu_data->dcache.way_incr; + addrstart += current_cpu_data.dcache.way_incr; } while (--ways); back_to_P1(); @@ -128,7 +127,11 @@ static void __flush_dcache_page(unsigned */ void flush_dcache_page(struct page *page) { - if (test_bit(PG_mapped, &page->flags)) + struct address_space *mapping = page_mapping(page); + + if (mapping && !mapping_mapped(mapping)) + set_bit(PG_dcache_dirty, &page->flags); + else __flush_dcache_page(PHYSADDR(page_address(page))); } diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c index 716ebf5..fa5d7f0 100644 --- a/arch/sh/mm/fault.c +++ b/arch/sh/mm/fault.c @@ -17,6 +17,7 @@ #include #include #include #include +#include #include extern void die(const char *,struct pt_regs *,long); @@ -224,3 +225,89 @@ do_sigbus: if (!user_mode(regs)) goto no_context; } + +#ifdef CONFIG_SH_STORE_QUEUES +/* + * This is a special case for the SH-4 store queues, as pages for this + * space still need to be faulted in before it's possible to flush the + * store queue cache for writeout to the remapped region. + */ +#define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000) +#else +#define P3_ADDR_MAX P4SEG +#endif + +/* + * Called with interrupts disabled. + */ +asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs, + unsigned long writeaccess, + unsigned long address) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + pte_t entry; + struct mm_struct *mm = current->mm; + spinlock_t *ptl; + int ret = 1; + +#ifdef CONFIG_SH_KGDB + if (kgdb_nofault && kgdb_bus_err_hook) + kgdb_bus_err_hook(); +#endif + + /* + * We don't take page faults for P1, P2, and parts of P4, these + * are always mapped, whether it be due to legacy behaviour in + * 29-bit mode, or due to PMB configuration in 32-bit mode. + */ + if (address >= P3SEG && address < P3_ADDR_MAX) { + pgd = pgd_offset_k(address); + mm = NULL; + } else { + if (unlikely(address >= TASK_SIZE || !mm)) + return 1; + + pgd = pgd_offset(mm, address); + } + + pud = pud_offset(pgd, address); + if (pud_none_or_clear_bad(pud)) + return 1; + pmd = pmd_offset(pud, address); + if (pmd_none_or_clear_bad(pmd)) + return 1; + + if (mm) + pte = pte_offset_map_lock(mm, pmd, address, &ptl); + else + pte = pte_offset_kernel(pmd, address); + + entry = *pte; + if (unlikely(pte_none(entry) || pte_not_present(entry))) + goto unlock; + if (unlikely(writeaccess && !pte_write(entry))) + goto unlock; + + if (writeaccess) + entry = pte_mkdirty(entry); + entry = pte_mkyoung(entry); + +#ifdef CONFIG_CPU_SH4 + /* + * ITLB is not affected by "ldtlb" instruction. + * So, we need to flush the entry by ourselves. + */ + local_flush_tlb_one(get_asid(), address & PAGE_MASK); +#endif + + set_pte(pte, entry); + update_mmu_cache(NULL, address, entry); + ret = 0; +unlock: + if (mm) + pte_unmap_unlock(pte, ptl); + return ret; +} diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index bf0c263..ae957a9 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -39,11 +39,6 @@ #include DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); pgd_t swapper_pg_dir[PTRS_PER_PGD]; -/* - * Cache of MMU context last used. - */ -unsigned long mmu_context_cache = NO_CONTEXT; - #ifdef CONFIG_MMU /* It'd be good if these lines were in the standard header file. */ #define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT) @@ -111,7 +106,7 @@ static void set_pte_phys(unsigned long a set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot)); - __flush_tlb_page(get_asid(), addr); + flush_tlb_one(get_asid(), addr); } /* diff --git a/arch/sh/mm/ioremap.c b/arch/sh/mm/ioremap.c index 90b494a..be03d74 100644 --- a/arch/sh/mm/ioremap.c +++ b/arch/sh/mm/ioremap.c @@ -45,12 +45,6 @@ void __iomem *__ioremap(unsigned long ph return NULL; /* - * Don't remap the low PCI/ISA area, it's always mapped.. - */ - if (phys_addr >= 0xA0000 && last_addr < 0x100000) - return (void __iomem *)phys_to_virt(phys_addr); - - /* * If we're on an SH7751 or SH7780 PCI controller, PCI memory is * mapped at the end of the address space (typically 0xfd000000) * in a non-translatable area, so mapping through page tables for diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c index 3f98d2a..969efec 100644 --- a/arch/sh/mm/pg-sh4.c +++ b/arch/sh/mm/pg-sh4.c @@ -13,7 +13,7 @@ #include extern struct mutex p3map_mutex[]; -#define CACHE_ALIAS (cpu_data->dcache.alias_mask) +#define CACHE_ALIAS (current_cpu_data.dcache.alias_mask) /* * clear_user_page @@ -23,7 +23,6 @@ #define CACHE_ALIAS (cpu_data->dcache.al */ void clear_user_page(void *to, unsigned long address, struct page *page) { - __set_bit(PG_mapped, &page->flags); if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) clear_page(to); else { @@ -40,7 +39,7 @@ void clear_user_page(void *to, unsigned mutex_lock(&p3map_mutex[(address & CACHE_ALIAS)>>12]); set_pte(pte, entry); local_irq_save(flags); - __flush_tlb_page(get_asid(), p3_addr); + flush_tlb_one(get_asid(), p3_addr); local_irq_restore(flags); update_mmu_cache(NULL, p3_addr, entry); __clear_user_page((void *)p3_addr, to); @@ -59,7 +58,6 @@ void clear_user_page(void *to, unsigned void copy_user_page(void *to, void *from, unsigned long address, struct page *page) { - __set_bit(PG_mapped, &page->flags); if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) copy_page(to, from); else { @@ -76,7 +74,7 @@ void copy_user_page(void *to, void *from mutex_lock(&p3map_mutex[(address & CACHE_ALIAS)>>12]); set_pte(pte, entry); local_irq_save(flags); - __flush_tlb_page(get_asid(), p3_addr); + flush_tlb_one(get_asid(), p3_addr); local_irq_restore(flags); update_mmu_cache(NULL, p3_addr, entry); __copy_user_page((void *)p3_addr, from, to); @@ -84,23 +82,3 @@ void copy_user_page(void *to, void *from mutex_unlock(&p3map_mutex[(address & CACHE_ALIAS)>>12]); } } - -/* - * For SH-4, we have our own implementation for ptep_get_and_clear - */ -inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) -{ - pte_t pte = *ptep; - - pte_clear(mm, addr, ptep); - if (!pte_not_present(pte)) { - unsigned long pfn = pte_pfn(pte); - if (pfn_valid(pfn)) { - struct page *page = pfn_to_page(pfn); - struct address_space *mapping = page_mapping(page); - if (!mapping || !mapping_writably_mapped(mapping)) - __clear_bit(PG_mapped, &page->flags); - } - } - return pte; -} diff --git a/arch/sh/mm/pg-sh7705.c b/arch/sh/mm/pg-sh7705.c index ff9ece9..887ab9d 100644 --- a/arch/sh/mm/pg-sh7705.c +++ b/arch/sh/mm/pg-sh7705.c @@ -7,9 +7,7 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * */ - #include #include #include @@ -45,13 +43,13 @@ static inline void __flush_purge_virtual p = __pa(p1_begin); - ways = cpu_data->dcache.ways; + ways = current_cpu_data.dcache.ways; addr = CACHE_OC_ADDRESS_ARRAY; do { unsigned long data; - addr |= (v & cpu_data->dcache.entry_mask); + addr |= (v & current_cpu_data.dcache.entry_mask); data = ctrl_inl(addr); if ((data & CACHE_PHYSADDR_MASK) == @@ -60,7 +58,7 @@ static inline void __flush_purge_virtual ctrl_outl(data, addr); } - addr += cpu_data->dcache.way_incr; + addr += current_cpu_data.dcache.way_incr; } while (--ways); p1_begin += L1_CACHE_BYTES; @@ -76,7 +74,6 @@ void clear_user_page(void *to, unsigned { struct page *page = virt_to_page(to); - __set_bit(PG_mapped, &page->flags); if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) { clear_page(to); __flush_wback_region(to, PAGE_SIZE); @@ -95,12 +92,11 @@ void clear_user_page(void *to, unsigned * @from: P1 address * @address: U0 address to be mapped */ -void copy_user_page(void *to, void *from, unsigned long address, struct page *pg) +void copy_user_page(void *to, void *from, unsigned long address, + struct page *pg) { struct page *page = virt_to_page(to); - - __set_bit(PG_mapped, &page->flags); if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) { copy_page(to, from); __flush_wback_region(to, PAGE_SIZE); @@ -112,26 +108,3 @@ void copy_user_page(void *to, void *from __flush_wback_region(to, PAGE_SIZE); } } - -/* - * For SH7705, we have our own implementation for ptep_get_and_clear - * Copied from pg-sh4.c - */ -inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) -{ - pte_t pte = *ptep; - - pte_clear(mm, addr, ptep); - if (!pte_not_present(pte)) { - unsigned long pfn = pte_pfn(pte); - if (pfn_valid(pfn)) { - struct page *page = pfn_to_page(pfn); - struct address_space *mapping = page_mapping(page); - if (!mapping || !mapping_writably_mapped(mapping)) - __clear_bit(PG_mapped, &page->flags); - } - } - - return pte; -} - diff --git a/arch/sh/mm/tlb-flush.c b/arch/sh/mm/tlb-flush.c index 73ec7f6..d2f7b4a 100644 --- a/arch/sh/mm/tlb-flush.c +++ b/arch/sh/mm/tlb-flush.c @@ -2,24 +2,28 @@ * TLB flushing operations for SH with an MMU. * * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 Paul Mundt + * Copyright (C) 2003 - 2006 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #include +#include #include #include +#include -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { - if (vma->vm_mm && vma->vm_mm->context.id != NO_CONTEXT) { + unsigned int cpu = smp_processor_id(); + + if (vma->vm_mm && cpu_context(cpu, vma->vm_mm) != NO_CONTEXT) { unsigned long flags; unsigned long asid; unsigned long saved_asid = MMU_NO_ASID; - asid = vma->vm_mm->context.id & MMU_CONTEXT_ASID_MASK; + asid = cpu_asid(cpu, vma->vm_mm); page &= PAGE_MASK; local_irq_save(flags); @@ -27,33 +31,34 @@ void flush_tlb_page(struct vm_area_struc saved_asid = get_asid(); set_asid(asid); } - __flush_tlb_page(asid, page); + local_flush_tlb_one(asid, page); if (saved_asid != MMU_NO_ASID) set_asid(saved_asid); local_irq_restore(flags); } } -void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) { struct mm_struct *mm = vma->vm_mm; + unsigned int cpu = smp_processor_id(); - if (mm->context.id != NO_CONTEXT) { + if (cpu_context(cpu, mm) != NO_CONTEXT) { unsigned long flags; int size; local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */ - mm->context.id = NO_CONTEXT; + cpu_context(cpu, mm) = NO_CONTEXT; if (mm == current->mm) - activate_context(mm); + activate_context(mm, cpu); } else { unsigned long asid; unsigned long saved_asid = MMU_NO_ASID; - asid = mm->context.id & MMU_CONTEXT_ASID_MASK; + asid = cpu_asid(cpu, mm); start &= PAGE_MASK; end += (PAGE_SIZE - 1); end &= PAGE_MASK; @@ -62,7 +67,7 @@ void flush_tlb_range(struct vm_area_stru set_asid(asid); } while (start < end) { - __flush_tlb_page(asid, start); + local_flush_tlb_one(asid, start); start += PAGE_SIZE; } if (saved_asid != MMU_NO_ASID) @@ -72,26 +77,27 @@ void flush_tlb_range(struct vm_area_stru } } -void flush_tlb_kernel_range(unsigned long start, unsigned long end) +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { + unsigned int cpu = smp_processor_id(); unsigned long flags; int size; local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */ - flush_tlb_all(); + local_flush_tlb_all(); } else { unsigned long asid; unsigned long saved_asid = get_asid(); - asid = init_mm.context.id & MMU_CONTEXT_ASID_MASK; + asid = cpu_asid(cpu, &init_mm); start &= PAGE_MASK; end += (PAGE_SIZE - 1); end &= PAGE_MASK; set_asid(asid); while (start < end) { - __flush_tlb_page(asid, start); + local_flush_tlb_one(asid, start); start += PAGE_SIZE; } set_asid(saved_asid); @@ -99,22 +105,24 @@ void flush_tlb_kernel_range(unsigned lon local_irq_restore(flags); } -void flush_tlb_mm(struct mm_struct *mm) +void local_flush_tlb_mm(struct mm_struct *mm) { + unsigned int cpu = smp_processor_id(); + /* Invalidate all TLB of this process. */ /* Instead of invalidating each TLB, we get new MMU context. */ - if (mm->context.id != NO_CONTEXT) { + if (cpu_context(cpu, mm) != NO_CONTEXT) { unsigned long flags; local_irq_save(flags); - mm->context.id = NO_CONTEXT; + cpu_context(cpu, mm) = NO_CONTEXT; if (mm == current->mm) - activate_context(mm); + activate_context(mm, cpu); local_irq_restore(flags); } } -void flush_tlb_all(void) +void local_flush_tlb_all(void) { unsigned long flags, status; @@ -132,3 +140,54 @@ void flush_tlb_all(void) ctrl_barrier(); local_irq_restore(flags); } + +void update_mmu_cache(struct vm_area_struct *vma, + unsigned long address, pte_t pte) +{ + unsigned long flags; + unsigned long pteval; + unsigned long vpn; + struct page *page; + unsigned long pfn = pte_pfn(pte); + struct address_space *mapping; + + if (!pfn_valid(pfn)) + return; + + page = pfn_to_page(pfn); + mapping = page_mapping(page); + if (mapping) { + unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; + int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); + + if (dirty) + __flush_wback_region((void *)P1SEGADDR(phys), + PAGE_SIZE); + } + + local_irq_save(flags); + + /* Set PTEH register */ + vpn = (address & MMU_VPN_MASK) | get_asid(); + ctrl_outl(vpn, MMU_PTEH); + + pteval = pte_val(pte); + +#ifdef CONFIG_CPU_HAS_PTEA + /* Set PTEA register */ + /* TODO: make this look less hacky */ + ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); +#endif + + /* Set PTEL register */ + pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ +#if defined(CONFIG_SH_WRITETHROUGH) && defined(CONFIG_CPU_SH4) + pteval |= _PAGE_WT; +#endif + /* conveniently, we want all the software flags to be 0 anyway */ + ctrl_outl(pteval, MMU_PTEL); + + /* Load the TLB */ + asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); + local_irq_restore(flags); +} diff --git a/arch/sh/mm/tlb-nommu.c b/arch/sh/mm/tlb-nommu.c index e55cfea..1ccca7c 100644 --- a/arch/sh/mm/tlb-nommu.c +++ b/arch/sh/mm/tlb-nommu.c @@ -13,39 +13,33 @@ #include /* * Nothing too terribly exciting here .. */ - -void flush_tlb(void) -{ - BUG(); -} - -void flush_tlb_all(void) +void local_flush_tlb_all(void) { BUG(); } -void flush_tlb_mm(struct mm_struct *mm) +void local_flush_tlb_mm(struct mm_struct *mm) { BUG(); } -void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { BUG(); } -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { BUG(); } -void __flush_tlb_page(unsigned long asid, unsigned long page) +void local_flush_tlb_one(unsigned long asid, unsigned long page) { BUG(); } -void flush_tlb_kernel_range(unsigned long start, unsigned long end) +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { BUG(); } @@ -55,4 +49,3 @@ void update_mmu_cache(struct vm_area_str { BUG(); } - diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c index 46b09e2..e5e76eb 100644 --- a/arch/sh/mm/tlb-sh3.c +++ b/arch/sh/mm/tlb-sh3.c @@ -8,71 +8,11 @@ * * Released under the terms of the GNU GPL v2.0. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - +#include #include -#include -#include -#include #include -#include -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - unsigned long pteval; - unsigned long vpn; - - /* Ptrace may call this routine. */ - if (vma && current->active_mm != vma->vm_mm) - return; - -#if defined(CONFIG_SH7705_CACHE_32KB) - { - struct page *page = pte_page(pte); - unsigned long pfn = pte_pfn(pte); - - if (pfn_valid(pfn) && !test_bit(PG_mapped, &page->flags)) { - unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; - - __flush_wback_region((void *)P1SEGADDR(phys), - PAGE_SIZE); - __set_bit(PG_mapped, &page->flags); - } - } -#endif - - local_irq_save(flags); - - /* Set PTEH register */ - vpn = (address & MMU_VPN_MASK) | get_asid(); - ctrl_outl(vpn, MMU_PTEH); - - pteval = pte_val(pte); - - /* Set PTEL register */ - pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ - /* conveniently, we want all the software flags to be 0 anyway */ - ctrl_outl(pteval, MMU_PTEL); - - /* Load the TLB */ - asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); - local_irq_restore(flags); -} - -void __flush_tlb_page(unsigned long asid, unsigned long page) +void local_flush_tlb_one(unsigned long asid, unsigned long page) { unsigned long addr, data; int i, ways = MMU_NTLB_WAYS; @@ -86,7 +26,7 @@ void __flush_tlb_page(unsigned long asid addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000); data = (page & 0xfffe0000) | asid; /* VALID bit is off */ - if ((cpu_data->flags & CPU_HAS_MMU_PAGE_ASSOC)) { + if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) { addr |= MMU_PAGE_ASSOC_BIT; ways = 1; /* we already know the way .. */ } @@ -94,4 +34,3 @@ void __flush_tlb_page(unsigned long asid for (i = 0; i < ways; i++) ctrl_outl(data, addr + (i << 8)); } - diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c index 812b2d5..221e709 100644 --- a/arch/sh/mm/tlb-sh4.c +++ b/arch/sh/mm/tlb-sh4.c @@ -8,76 +8,11 @@ * * Released under the terms of the GNU GPL v2.0. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - +#include #include -#include -#include -#include #include -#include -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - unsigned long pteval; - unsigned long vpn; - struct page *page; - unsigned long pfn; - - /* Ptrace may call this routine. */ - if (vma && current->active_mm != vma->vm_mm) - return; - - pfn = pte_pfn(pte); - if (pfn_valid(pfn)) { - page = pfn_to_page(pfn); - if (!test_bit(PG_mapped, &page->flags)) { - unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; - __flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE); - __set_bit(PG_mapped, &page->flags); - } - } - - local_irq_save(flags); - - /* Set PTEH register */ - vpn = (address & MMU_VPN_MASK) | get_asid(); - ctrl_outl(vpn, MMU_PTEH); - - pteval = pte_val(pte); - - /* Set PTEA register */ - if (cpu_data->flags & CPU_HAS_PTEA) - /* TODO: make this look less hacky */ - ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); - - /* Set PTEL register */ - pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ -#ifdef CONFIG_SH_WRITETHROUGH - pteval |= _PAGE_WT; -#endif - /* conveniently, we want all the software flags to be 0 anyway */ - ctrl_outl(pteval, MMU_PTEL); - - /* Load the TLB */ - asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); - local_irq_restore(flags); -} - -void __flush_tlb_page(unsigned long asid, unsigned long page) +void local_flush_tlb_one(unsigned long asid, unsigned long page) { unsigned long addr, data; @@ -93,4 +28,3 @@ void __flush_tlb_page(unsigned long asid ctrl_outl(data, addr); back_to_P1(); } - diff --git a/arch/sh/oprofile/op_model_sh7750.c b/arch/sh/oprofile/op_model_sh7750.c index 0104e44..ebee7e2 100644 --- a/arch/sh/oprofile/op_model_sh7750.c +++ b/arch/sh/oprofile/op_model_sh7750.c @@ -259,7 +259,7 @@ static struct oprofile_operations sh7750 int __init oprofile_arch_init(struct oprofile_operations **ops) { - if (!(cpu_data->flags & CPU_HAS_PERF_COUNTER)) + if (!(current_cpu_data.flags & CPU_HAS_PERF_COUNTER)) return -ENODEV; sh7750_perf_counter_ops.cpu_type = (char *)get_cpu_subtype(); diff --git a/include/asm-sh/Kbuild b/include/asm-sh/Kbuild index c68e168..76a8ccf 100644 --- a/include/asm-sh/Kbuild +++ b/include/asm-sh/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +header-y += cpu-features.h diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h index a294997..5a117ec 100644 --- a/include/asm-sh/bugs.h +++ b/include/asm-sh/bugs.h @@ -19,9 +19,9 @@ static void __init check_bugs(void) extern unsigned long loops_per_jiffy; char *p = &init_utsname()->machine[2]; /* "sh" */ - cpu_data->loops_per_jiffy = loops_per_jiffy; + current_cpu_data.loops_per_jiffy = loops_per_jiffy; - switch (cpu_data->type) { + switch (current_cpu_data.type) { case CPU_SH7604 ... CPU_SH7619: *p++ = '2'; break; @@ -54,7 +54,7 @@ static void __init check_bugs(void) break; } - printk("CPU: %s\n", get_cpu_subtype()); + printk("CPU: %s\n", get_cpu_subtype(¤t_cpu_data)); #ifndef __LITTLE_ENDIAN__ /* 'eb' means 'Endian Big' */ diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h index 07f62ec..22f1263 100644 --- a/include/asm-sh/cacheflush.h +++ b/include/asm-sh/cacheflush.h @@ -30,5 +30,8 @@ #define copy_from_user_page(vma, page, v #define HAVE_ARCH_UNMAPPED_AREA +/* Page flag for lazy dcache write-back for the aliasing UP caches */ +#define PG_dcache_dirty PG_arch_1 + #endif /* __KERNEL__ */ #endif /* __ASM_SH_CACHEFLUSH_H */ diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h index f70d8ef..6fabbba 100644 --- a/include/asm-sh/cpu-sh3/cacheflush.h +++ b/include/asm-sh/cpu-sh3/cacheflush.h @@ -36,8 +36,6 @@ #if defined(CONFIG_SH7705_CACHE_32KB) /* 32KB cache, 4kb PAGE sizes need to check bit 12 */ #define CACHE_ALIAS 0x00001000 -#define PG_mapped PG_arch_1 - void flush_cache_all(void); void flush_cache_mm(struct mm_struct *mm); #define flush_cache_dup_mm(mm) flush_cache_mm(mm) diff --git a/include/asm-sh/cpu-sh4/cacheflush.h b/include/asm-sh/cpu-sh4/cacheflush.h index b01a10f..b3746a9 100644 --- a/include/asm-sh/cpu-sh4/cacheflush.h +++ b/include/asm-sh/cpu-sh4/cacheflush.h @@ -17,6 +17,7 @@ #define __ASM_CPU_SH4_CACHEFLUSH_H * so we need them. */ void flush_cache_all(void); +void flush_dcache_all(void); void flush_cache_mm(struct mm_struct *mm); #define flush_cache_dup_mm(mm) flush_cache_mm(mm) void flush_cache_range(struct vm_area_struct *vma, unsigned long start, @@ -38,16 +39,4 @@ #define flush_icache_page(vma,pg) do { /* Initialization of P3 area for copy_user_page */ void p3_cache_init(void); -#define PG_mapped PG_arch_1 - -#ifdef CONFIG_MMU -extern int remap_area_pages(unsigned long addr, unsigned long phys_addr, - unsigned long size, unsigned long flags); -#else /* CONFIG_MMU */ -static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr, - unsigned long size, unsigned long flags) -{ - return 0; -} -#endif /* CONFIG_MMU */ #endif /* __ASM_CPU_SH4_CACHEFLUSH_H */ diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h index 3e4b3e6..c135e9c 100644 --- a/include/asm-sh/cpu-sh4/dma.h +++ b/include/asm-sh/cpu-sh4/dma.h @@ -3,6 +3,17 @@ #define __ASM_CPU_SH4_DMA_H #define DMAOR_INIT ( 0x8000 | DMAOR_DME ) +/* SH7751/7760/7780 DMA IRQ sources */ +#define DMTE0_IRQ 34 +#define DMTE1_IRQ 35 +#define DMTE2_IRQ 36 +#define DMTE3_IRQ 37 +#define DMTE4_IRQ 44 +#define DMTE5_IRQ 45 +#define DMTE6_IRQ 46 +#define DMTE7_IRQ 47 +#define DMAE_IRQ 38 + #ifdef CONFIG_CPU_SH4A #define SH_DMAC_BASE 0xfc808020 diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h index 8d0867b..d3bc781 100644 --- a/include/asm-sh/dma-mapping.h +++ b/include/asm-sh/dma-mapping.h @@ -53,6 +53,10 @@ static inline void dma_free_coherent(str consistent_free(vaddr, size); } +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +#define dma_is_consistent(d, h) (1) + static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction dir) { diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h index 7b26f53..0095c66 100644 --- a/include/asm-sh/kgdb.h +++ b/include/asm-sh/kgdb.h @@ -85,10 +85,10 @@ extern int setjmp(jmp_buf __jmpb); #define KGDB_PRINTK(...) printk("KGDB: " __VA_ARGS__) /* Forced breakpoint */ -#define BREAKPOINT() do { \ - if (kgdb_enabled) { \ - asm volatile("trapa #0xff"); \ - } \ +#define BREAKPOINT() \ +do { \ + if (kgdb_enabled) \ + __asm__ __volatile__("trapa #0x3c"); \ } while (0) /* KGDB should be able to flush all kernel text space */ diff --git a/include/asm-sh/mmu.h b/include/asm-sh/mmu.h index cf47df7..eb0358c 100644 --- a/include/asm-sh/mmu.h +++ b/include/asm-sh/mmu.h @@ -1,25 +1,19 @@ #ifndef __MMU_H #define __MMU_H -#if !defined(CONFIG_MMU) +/* Default "unsigned long" context */ +typedef unsigned long mm_context_id_t[NR_CPUS]; typedef struct { +#ifdef CONFIG_MMU + mm_context_id_t id; + void *vdso; +#else struct vm_list_struct *vmlist; unsigned long end_brk; +#endif } mm_context_t; -#else - -/* Default "unsigned long" context */ -typedef unsigned long mm_context_id_t; - -typedef struct { - mm_context_id_t id; - void *vdso; -} mm_context_t; - -#endif /* CONFIG_MMU */ - /* * Privileged Space Mapping Buffer (PMB) definitions */ diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h index 46f04e2..3420244 100644 --- a/include/asm-sh/mmu_context.h +++ b/include/asm-sh/mmu_context.h @@ -1,6 +1,6 @@ /* * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 Paul Mundt + * Copyright (C) 2003 - 2006 Paul Mundt * * ASID handling idea taken from MIPS implementation. */ @@ -19,11 +19,6 @@ #include * (b) ASID (Address Space IDentifier) */ -/* - * Cache of MMU context last used. - */ -extern unsigned long mmu_context_cache; - #define MMU_CONTEXT_ASID_MASK 0x000000ff #define MMU_CONTEXT_VERSION_MASK 0xffffff00 #define MMU_CONTEXT_FIRST_VERSION 0x00000100 @@ -32,6 +27,11 @@ #define NO_CONTEXT 0 /* ASID is 8-bit value, so it can't be 0x100 */ #define MMU_NO_ASID 0x100 +#define cpu_context(cpu, mm) ((mm)->context.id[cpu]) +#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & \ + MMU_CONTEXT_ASID_MASK) +#define asid_cache(cpu) (cpu_data[cpu].asid_cache) + /* * Virtual Page Number mask */ @@ -41,18 +41,17 @@ #ifdef CONFIG_MMU /* * Get MMU context if needed. */ -static inline void get_mmu_context(struct mm_struct *mm) +static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu) { - unsigned long mc = mmu_context_cache; + unsigned long asid = asid_cache(cpu); /* Check if we have old version of context. */ - if (((mm->context.id ^ mc) & MMU_CONTEXT_VERSION_MASK) == 0) + if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0) /* It's up to date, do nothing */ return; /* It's old, we need to get new context with new version. */ - mc = ++mmu_context_cache; - if (!(mc & MMU_CONTEXT_ASID_MASK)) { + if (!(++asid & MMU_CONTEXT_ASID_MASK)) { /* * We exhaust ASID of this version. * Flush all TLB and start new cycle. @@ -63,10 +62,11 @@ static inline void get_mmu_context(struc * Fix version; Note that we avoid version #0 * to distingush NO_CONTEXT. */ - if (!mc) - mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION; + if (!asid) + asid = MMU_CONTEXT_FIRST_VERSION; } - mm->context.id = mc; + + cpu_context(cpu, mm) = asid_cache(cpu) = asid; } /* @@ -74,9 +74,13 @@ static inline void get_mmu_context(struc * instance. */ static inline int init_new_context(struct task_struct *tsk, - struct mm_struct *mm) + struct mm_struct *mm) { - mm->context.id = NO_CONTEXT; + int i; + + for (i = 0; i < num_online_cpus(); i++) + cpu_context(i, mm) = NO_CONTEXT; + return 0; } @@ -117,10 +121,10 @@ static inline unsigned long get_asid(voi * After we have set current->mm to a new value, this activates * the context for the new mm so we see the new mappings. */ -static inline void activate_context(struct mm_struct *mm) +static inline void activate_context(struct mm_struct *mm, unsigned int cpu) { - get_mmu_context(mm); - set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK); + get_mmu_context(mm, cpu); + set_asid(cpu_asid(cpu, mm)); } /* MMU_TTB is used for optimizing the fault handling. */ @@ -138,10 +142,15 @@ static inline void switch_mm(struct mm_s struct mm_struct *next, struct task_struct *tsk) { + unsigned int cpu = smp_processor_id(); + if (likely(prev != next)) { + cpu_set(cpu, next->cpu_vm_mask); set_TTB(next->pgd); - activate_context(next); - } + activate_context(next, cpu); + } else + if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) + activate_context(next, cpu); } #define deactivate_mm(tsk,mm) do { } while (0) @@ -159,7 +168,7 @@ #define init_new_context(tsk,mm) (0) #define destroy_context(mm) do { } while (0) #define set_asid(asid) do { } while (0) #define get_asid() (0) -#define activate_context(mm) do { } while (0) +#define activate_context(mm,cpu) do { } while (0) #define switch_mm(prev,next,tsk) do { } while (0) #define deactivate_mm(tsk,mm) do { } while (0) #define activate_mm(prev,next) do { } while (0) @@ -174,14 +183,16 @@ #if defined(CONFIG_CPU_SH3) || defined(C */ static inline void enable_mmu(void) { + unsigned int cpu = smp_processor_id(); + /* Enable MMU */ ctrl_outl(MMU_CONTROL_INIT, MMUCR); ctrl_barrier(); - if (mmu_context_cache == NO_CONTEXT) - mmu_context_cache = MMU_CONTEXT_FIRST_VERSION; + if (asid_cache(cpu) == NO_CONTEXT) + asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION; - set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK); + set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK); } static inline void disable_mmu(void) diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index 380fd62..ac4b467 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h @@ -13,6 +13,8 @@ #define __ASM_SH_PAGE_H [ P4 control ] 0xE0000000 */ +#ifdef __KERNEL__ + /* PAGE_SHIFT determines the page size */ #if defined(CONFIG_PAGE_SIZE_4KB) # define PAGE_SHIFT 12 @@ -51,7 +53,6 @@ #define HPAGE_MASK (~(HPAGE_SIZE-1)) #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT-PAGE_SHIFT) #endif -#ifdef __KERNEL__ #ifndef __ASSEMBLY__ extern void (*clear_page)(void *to); diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index 036ca28..9214c01 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h @@ -43,17 +43,17 @@ #define PTE_BITS (PTE_SHIFT - PTE_MAGNIT /* PGD bits */ #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) #define PGDIR_BITS (32 - PGDIR_SHIFT) -#define PGDIR_SIZE (1 << PGDIR_SHIFT) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* Entries per level */ -#define PTRS_PER_PTE (PAGE_SIZE / 4) +#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) #define PTRS_PER_PGD (PAGE_SIZE / 4) #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0 -#define PTE_PHYS_MASK 0x1ffff000 +#define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE) /* * First 1MB map is used by fixed purpose. @@ -583,11 +583,6 @@ #ifndef CONFIG_MMU extern unsigned int kobjsize(const void *objp); #endif /* !CONFIG_MMU */ -#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); -#endif - extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init(void); diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index e29f2ab..3e46a7a 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -27,8 +27,6 @@ #define CCN_PVR 0xff000030 #define CCN_CVR 0xff000040 #define CCN_PRR 0xff000044 -const char *get_cpu_subtype(void); - /* * CPU type and hardware bug flags. Kept separately for each CPU. * @@ -66,6 +64,7 @@ enum cpu_type { struct sh_cpuinfo { unsigned int type; unsigned long loops_per_jiffy; + unsigned long asid_cache; struct cache_info icache; /* Primary I-cache */ struct cache_info dcache; /* Primary D-cache */ @@ -288,5 +287,8 @@ #else #define vsyscall_init() do { } while (0) #endif +/* arch/sh/kernel/setup.c */ +const char *get_cpu_subtype(struct sh_cpuinfo *c); + #endif /* __KERNEL__ */ #endif /* __ASM_SH_PROCESSOR_H */ diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h index 879f741..279e70a 100644 --- a/include/asm-sh/thread_info.h +++ b/include/asm-sh/thread_info.h @@ -32,12 +32,20 @@ #endif #define PREEMPT_ACTIVE 0x10000000 -#ifdef CONFIG_4KSTACKS -#define THREAD_SIZE (PAGE_SIZE) +#if defined(CONFIG_4KSTACKS) +#define THREAD_SIZE_ORDER (0) +#elif defined(CONFIG_PAGE_SIZE_4KB) +#define THREAD_SIZE_ORDER (1) +#elif defined(CONFIG_PAGE_SIZE_8KB) +#define THREAD_SIZE_ORDER (1) +#elif defined(CONFIG_PAGE_SIZE_64KB) +#define THREAD_SIZE_ORDER (0) #else -#define THREAD_SIZE (PAGE_SIZE * 2) +#error "Unknown thread size" #endif -#define STACK_WARN (THREAD_SIZE / 8) + +#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) +#define STACK_WARN (THREAD_SIZE >> 3) /* * macros/functions for gaining access to the thread information structure diff --git a/include/asm-sh/tlbflush.h b/include/asm-sh/tlbflush.h index 28c073b..455fb8d 100644 --- a/include/asm-sh/tlbflush.h +++ b/include/asm-sh/tlbflush.h @@ -4,7 +4,6 @@ #define __ASM_SH_TLBFLUSH_H /* * TLB flushing: * - * - flush_tlb() flushes the current mm struct TLBs * - flush_tlb_all() flushes all processes TLBs * - flush_tlb_mm(mm) flushes the specified mm context TLB's * - flush_tlb_page(vma, vmaddr) flushes one page @@ -12,20 +11,45 @@ #define __ASM_SH_TLBFLUSH_H * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables */ +extern void local_flush_tlb_all(void); +extern void local_flush_tlb_mm(struct mm_struct *mm); +extern void local_flush_tlb_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end); +extern void local_flush_tlb_page(struct vm_area_struct *vma, + unsigned long page); +extern void local_flush_tlb_kernel_range(unsigned long start, + unsigned long end); +extern void local_flush_tlb_one(unsigned long asid, unsigned long page); + +#ifdef CONFIG_SMP -extern void flush_tlb(void); extern void flush_tlb_all(void); extern void flush_tlb_mm(struct mm_struct *mm); extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page); -extern void __flush_tlb_page(unsigned long asid, unsigned long page); +extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); +extern void flush_tlb_one(unsigned long asid, unsigned long page); + +#else + +#define flush_tlb_all() local_flush_tlb_all() +#define flush_tlb_mm(mm) local_flush_tlb_mm(mm) +#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page) +#define flush_tlb_one(asid, page) local_flush_tlb_one(asid, page) + +#define flush_tlb_range(vma, start, end) \ + local_flush_tlb_range(vma, start, end) + +#define flush_tlb_kernel_range(start, end) \ + local_flush_tlb_kernel_range(start, end) + +#endif /* CONFIG_SMP */ static inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) -{ /* Nothing to do */ +{ + /* Nothing to do */ } - -extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); - #endif /* __ASM_SH_TLBFLUSH_H */ diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h index 694f51f..ae9bbde 100644 --- a/include/asm-sh/ubc.h +++ b/include/asm-sh/ubc.h @@ -17,7 +17,7 @@ #include /* User Break Controller */ #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ defined(CONFIG_CPU_SUBTYPE_SH7300) -#define UBC_TYPE_SH7729 (cpu_data->type == CPU_SH7729) +#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729) #else #define UBC_TYPE_SH7729 0 #endif diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h index f982073..17f527b 100644 --- a/include/asm-sh/unistd.h +++ b/include/asm-sh/unistd.h @@ -292,22 +292,22 @@ #define __NR_mq_notify (__NR_mq #define __NR_mq_getsetattr (__NR_mq_open+5) #define __NR_kexec_load 283 #define __NR_waitid 284 -/* #define __NR_sys_setaltroot 285 */ -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 +#define __NR_add_key 285 +#define __NR_request_key 286 +#define __NR_keyctl 287 +#define __NR_ioprio_set 288 +#define __NR_ioprio_get 289 +#define __NR_inotify_init 290 +#define __NR_inotify_add_watch 291 +#define __NR_inotify_rm_watch 292 +/* 293 is unused */ #define __NR_migrate_pages 294 #define __NR_openat 295 #define __NR_mkdirat 296 #define __NR_mknodat 297 #define __NR_fchownat 298 #define __NR_futimesat 299 -#define __NR_newfstatat 300 +#define __NR_fstatat64 300 #define __NR_unlinkat 301 #define __NR_renameat 302 #define __NR_linkat 303