GIT f9b4958d60202cd44ca38ede3bdb02e31512b8f9 git://www.linux-mips.org/pub/scm/upstream.git#for-akpm commit f9b4958d60202cd44ca38ede3bdb02e31512b8f9 Author: Ralf Baechle Date: Fri Sep 21 15:27:43 2007 +0100 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle commit fcc183bcf78c5e7f71ad806d5f0ebefdf082a093 Author: Ralf Baechle Date: Fri Sep 21 15:27:42 2007 +0100 [MIPS] Alchemy: remove useless prototypes. Signed-off-by: Ralf Baechle commit b0d71ce8940e2f5ea5a85989e32fbae365c126d0 Author: Ralf Baechle Date: Fri Sep 21 15:27:42 2007 +0100 [MIPS] Sibyte: cleanup static inline forward declarations. In fact there are no foward declarations at all needed when moving things into the right order. Signed-off-by: Ralf Baechle commit cc6d62426c0e825576ab589ebe013beb6a4c606c Author: Maciej W. Rozycki Date: Tue Sep 18 18:49:08 2007 +0100 [MIPS] R3000 setup for kernel_thread() Match the R4000 semantics for the initial state of interrupt/kernel status register flags for the R3000 in kernel_thread(). Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle commit ee2f9078d35a5659fde132ed09fdc66d4dafdafc Author: Ralf Baechle Date: Fri Sep 21 15:27:42 2007 +0100 [MIPS] Introduce a consistent style for vmlinux.lds. This style will be consitent with all other arch's - soon. In addition: - Moved a few labels inside brackets for the sections they specify to prevent that linker alignmnet made them point before the section start Signed-off-by: Sam Ravnborg Signed-off-by: Ralf Baechle --- commit 12aa0c83c1b85d52a89fcb5be0364f82f488503d Author: Yoichi Yuasa Date: Thu Sep 13 23:51:26 2007 +0900 [MIPS] Add GT641xx IRQ routines. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit fa6f315038c8109ab3c5760d455063c826ea1527 Author: Yoichi Yuasa Date: Wed Sep 12 23:19:45 2007 +0900 [MIPS] GT64120: Remove unused definitions Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 1a68bb4e13c6f6f5dfe042db8c8550383d6a8082 Author: Yoichi Yuasa Date: Thu Sep 13 11:04:04 2007 +0900 [MIPS] i8295 cleanups. o Move i8259 function declarations to include/asm-mips/i8259.h o Make i8259.c functions static where possible. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 366db44b192bb1bcdb79a8a9434409b4184648c9 Author: Ralf Baechle Date: Fri Sep 21 15:27:41 2007 +0100 [MIPS] Kill useless volatile keyword Signed-off-by: Ralf Baechle commit d7de4438dfa934b932f1f3fe0da831bdfd37c6b2 Author: Atsushi Nemoto Date: Sun Sep 9 02:50:42 2007 +0900 [MIPS] Kill redundant EXTRA_AFLAGS Kill redundant EXTRA_AFLAGS added after the commit d2af363cfb94f1bacb3e60327bc44a97881a38c2. Signed-off-by: Atsushi Nemoto commit 3ff13eed808752d55d58319925a2e8fd8bc7d225 Author: Thiemo Seufer Date: Wed Sep 5 17:44:50 2007 +0100 [MIPS] Define known MIPS ISA overrides for Sibyte and Excite boards. Signed-Off-By: Thiemo Seufer Signed-off-by: Ralf Baechle commit 835cbb280d26d4d5a6251f5b5b9836c80c9dc2cd Author: Ralf Baechle Date: Fri Sep 21 15:27:41 2007 +0100 [MIPS] floppy: Rewrite fd_cacheflush() to use dma_cache_sync(). Signed-off-by: Ralf Baechle commit d2e2ca808a4a8f08505f384ee62afb0e1488a40d Author: Ralf Baechle Date: Fri Sep 21 15:27:41 2007 +0100 [MIPS] PCI: Always enable CONFIG_PCI_DOMAINS The cost is just too low. Signed-off-by: Ralf Baechle commit 7a857a37b80659dd4a51a66ddb79af15a034a423 Author: Atsushi Nemoto Date: Tue Aug 28 00:28:09 2007 +0900 [MIPS] tx4927: Cleanup unused macros and non-standard IO accessors. This patch removes many unused constants, replaces non-standard IO accessors with standard ones, and kills terrible tx4927_mips.h file. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle commit ab269c5092aaec970baa1b617ae3df9afa9aef5d Author: Thomas Gleixner Date: Tue Aug 28 09:03:01 2007 +0000 [MIPS] cleanup struct irqaction initializers Signed-off-by: Thomas Gleixner CC: Ralf Baechle Signed-off-by: Ralf Baechle commit eee9f082ea1527d6ef2a75de44a5d42e4ba62d16 Author: Aurelien Jarno Date: Fri Aug 10 14:00:23 2007 -0700 [MIPS] Add support for BCM947xx CPUs. Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch Cc: Felix Fietkau Cc: Florian Schirmer Signed-off-by: Aurelien Jarno Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle commit c3c54ceee39224076ca715d812156e1ceeedaca1 Author: Thomas Bogendoerfer Date: Sat Aug 25 11:01:50 2007 +0200 [MIPS] JAZZ fixes - restructured irq handling - switched vdma to use memory allocated via get_free_pages - setup platform devices for serial, jazz_esp and jazzsonic - fixed cmos rtc access Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle commit aaf2b07e2dc4144c6a69bf04e802a067c58a620d Author: Brian Murphy Date: Tue Aug 21 22:34:16 2007 +0200 [MIPS] Add back support for LASAT platforms Signed-off-by: Brian Murphy Signed-off-by: Ralf Baechle commit 60687cfc2c4ddc02b6b683e830971b13c367adcf Author: Yoichi Yuasa Date: Thu Aug 16 23:15:42 2007 +0900 [MIPS] fix ABI check in include/asm-mips/arv/hinv.h Fix ABI check in include/asm-mips/arv/hinv.h Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 4fed7a2686c82c6f16ef54bc4ed0e9fb7984a8fa Author: Yoichi Yuasa Date: Thu Aug 16 22:56:04 2007 +0900 [MIPS] remove unused include/asm-mips/ip32/machine.h Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 15851f3e9ed3a43e79afaf7d1ae5d44484acad8a Author: Yoichi Yuasa Date: Thu Aug 16 22:54:02 2007 +0900 [MIPS] IP27: remove duplicate extern dump_tlb_all() prototype Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 153b639db41da9ef00177b69194c6ab461b93108 Author: Yoichi Yuasa Date: Thu Aug 16 22:27:05 2007 +0900 [MIPS] VR41xx: replace infinite loop with hibernate Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 7072751d9d785b6f05849f04186ed9067f2fcd6b Author: Yoichi Yuasa Date: Thu Aug 16 22:20:11 2007 +0900 [MIPS] VR41xx: Add default restart routine. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 8fac7acd3a2b324afc885b0874f339bcd0a6a4c9 Author: Franck Bui-Huu Date: Thu Feb 15 12:06:47 2007 +0100 [MIPS] Remove '-mno-explicit-relocs' option when CONFIG_BUILD_ELF64 This patch removes '-mno-explicit-relocs' usage when CONFIG_BUILD_ELF64 is set since this option was only required with the old hack to truncate addresses at the assembly level where "-mabi=64 -Wa,-mabi=32" was used. This should yield a small code size improvement for inline assembly, where the R constraint is used. The idea is coming from Maciej . Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle commit 42d876b1507cb4a05e42deda7bdc1852f2fab9b5 Author: Ralf Baechle Date: Fri Sep 21 15:27:39 2007 +0100 [MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency. Signed-off-by: Ralf Baechle commit 9cffd184c5636251423f4e43aef98b2fa2dcd6ae Author: Yoichi Yuasa Date: Tue Aug 7 00:09:17 2007 +0900 [MIPS] vr41xx: add cpu_wait Add cpu_wait for NEC VR41xx Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 56207cf9b29a91330c0a2af9e44018fbaffaf766 Author: Kevin D. Kissell Date: Fri Aug 3 19:38:03 2007 +0200 [MIPS] IRQ Affinity Support for SMTC on Malta Platform Signed-off-by: Kevin D. Kissell Signed-off-by: Ralf Baechle Signed-off-by: Andrew Morton --- arch/mips/Kconfig | 54 arch/mips/Makefile | 24 arch/mips/au1000/common/irq.c | 11 arch/mips/bcm947xx/Makefile | 6 arch/mips/bcm947xx/irq.c | 55 arch/mips/bcm947xx/prom.c | 49 arch/mips/bcm947xx/serial.c | 52 arch/mips/bcm947xx/setup.c | 79 arch/mips/bcm947xx/time.c | 56 arch/mips/cobalt/irq.c | 116 arch/mips/cobalt/rtc.c | 5 arch/mips/cobalt/serial.c | 7 arch/mips/cobalt/setup.c | 9 arch/mips/configs/lasat_defconfig | 828 + arch/mips/jazz/Makefile | 2 arch/mips/jazz/irq.c | 94 arch/mips/jazz/jazz-platform.c | 60 arch/mips/jazz/jazzdma.c | 47 arch/mips/jazz/setup.c | 115 arch/mips/jmr3927/rbhma3100/irq.c | 8 arch/mips/kernel/Makefile | 1 arch/mips/kernel/cpu-probe.c | 28 arch/mips/kernel/i8259.c | 21 arch/mips/kernel/irq-gt641xx.c | 131 arch/mips/kernel/proc.c | 2 arch/mips/kernel/process.c | 4 arch/mips/kernel/smtc.c | 65 arch/mips/kernel/traps.c | 10 arch/mips/kernel/vmlinux.lds.S | 339 arch/mips/lasat/Kconfig | 15 arch/mips/lasat/Makefile | 16 arch/mips/lasat/at93c.c | 149 arch/mips/lasat/at93c.h | 18 arch/mips/lasat/ds1603.c | 183 arch/mips/lasat/ds1603.h | 33 arch/mips/lasat/image/Makefile | 54 arch/mips/lasat/image/head.S | 31 arch/mips/lasat/image/romscript.normal | 23 arch/mips/lasat/interrupt.c | 130 arch/mips/lasat/lasat_board.c | 280 arch/mips/lasat/lasat_models.h | 67 arch/mips/lasat/picvue.c | 244 arch/mips/lasat/picvue.h | 48 arch/mips/lasat/picvue_proc.c | 191 arch/mips/lasat/prom.c | 128 arch/mips/lasat/prom.h | 7 arch/mips/lasat/reset.c | 61 arch/mips/lasat/serial.c | 94 arch/mips/lasat/setup.c | 158 arch/mips/lasat/sysctl.c | 454 + arch/mips/lasat/sysctl.h | 24 arch/mips/mips-boards/malta/malta_smtc.c | 50 arch/mips/mm/Makefile | 2 arch/mips/mm/c-r4k.c | 22 arch/mips/mm/c-sb1.c | 535 - arch/mips/mm/cache.c | 9 arch/mips/mm/pg-sb1.c | 8 arch/mips/mm/tlbex.c | 2 arch/mips/pci/Makefile | 2 arch/mips/pci/fixup-cobalt.c | 23 arch/mips/pci/ops-nile4.c | 147 arch/mips/pci/pci-lasat.c | 91 arch/mips/sgi-ip27/ip27-berr.c | 2 arch/mips/sgi-ip32/ip32-irq.c | 16 arch/mips/sibyte/bcm1480/setup.c | 78 arch/mips/sibyte/sb1250/setup.c | 74 arch/mips/tx4927/common/tx4927_dbgio.c | 1 arch/mips/tx4927/common/tx4927_prom.c | 12 arch/mips/tx4927/common/tx4927_setup.c | 11 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 31 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 32 arch/mips/vr41xx/common/pmu.c | 36 include/asm-mips/arc/hinv.h | 3 include/asm-mips/bootinfo.h | 13 include/asm-mips/cpu-features.h | 3 include/asm-mips/cpu.h | 47 include/asm-mips/floppy.h | 4 include/asm-mips/hw_irq.h | 7 include/asm-mips/i8259.h | 5 include/asm-mips/ip32/machine.h | 20 include/asm-mips/irq.h | 66 include/asm-mips/irq_gt641xx.h | 60 include/asm-mips/jazz.h | 38 include/asm-mips/jazzdma.h | 1 include/asm-mips/lasat/ds1603.h | 18 include/asm-mips/lasat/eeprom.h | 17 include/asm-mips/lasat/head.h | 22 include/asm-mips/lasat/lasat.h | 256 include/asm-mips/lasat/lasatint.h | 12 include/asm-mips/lasat/picvue.h | 15 include/asm-mips/lasat/serial.h | 13 include/asm-mips/linkage.h | 2 include/asm-mips/mach-bcm947xx/bcm947xx.h | 27 include/asm-mips/mach-cobalt/cobalt.h | 26 include/asm-mips/mach-cobalt/cpu-feature-overrides.h | 1 include/asm-mips/mach-cobalt/irq.h | 58 include/asm-mips/mach-excite/cpu-feature-overrides.h | 5 include/asm-mips/mach-jazz/mc146818rtc.h | 10 include/asm-mips/mach-lasat/mach-gt64120.h | 27 include/asm-mips/mach-mips/mach-gt64120.h | 9 include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 7 include/asm-mips/mach-wrppmc/mach-gt64120.h | 1 include/asm-mips/nile4.h | 310 include/asm-mips/pci.h | 4 include/asm-mips/smtc_ipi.h | 1 include/asm-mips/tx4927/toshiba_rbtx4927.h | 8 include/asm-mips/tx4927/tx4927.h | 439 - include/asm-mips/tx4927/tx4927_mips.h | 4177 ---------- 108 files changed, 5712 insertions(+), 5890 deletions(-) diff -puN arch/mips/Kconfig~git-mips arch/mips/Kconfig --- a/arch/mips/Kconfig~git-mips +++ a/arch/mips/Kconfig @@ -44,12 +44,27 @@ config BASLER_EXCITE_PROTOTYPE note that a kernel built with this option selected will not be able to run on normal units. +config BCM947XX + bool "BCM947xx based boards" + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SSB + select SSB_DRIVER_MIPS + select GENERIC_GPIO + help + Support for BCM947xx based boards + config MIPS_COBALT bool "Cobalt Server" select DMA_NONCOHERENT select HW_HAS_PCI select I8259 select IRQ_CPU + select IRQ_GT641XX select PCI_GT64XXX_PCI0 select SYS_HAS_CPU_NEVADA select SYS_HAS_EARLY_PRINTK @@ -93,6 +108,7 @@ config MACH_JAZZ select ARC32 select ARCH_MAY_HAVE_PC_FDC select GENERIC_ISA_DMA + select IRQ_CPU select I8259 select ISA select PCSPEAKER @@ -107,6 +123,20 @@ config MACH_JAZZ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and Olivetti M700-10 workstations. +config LASAT + bool "LASAT Networks platforms" + select DMA_NONCOHERENT + select SYS_HAS_EARLY_PRINTK + select HW_HAS_PCI + select PCI_GT64XXX_PCI0 + select MIPS_NILE4 + select R5000_CPU_SCACHE + select SYS_HAS_CPU_R5000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if BROKEN + select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + config LEMOTE_FULONG bool "Lemote Fulong mini-PC" select ARCH_SPARSEMEM_ENABLE @@ -352,7 +382,6 @@ config SGI_IP27 select SYS_HAS_EARLY_PRINTK select HW_HAS_PCI select NR_CPUS_DEFAULT_64 - select PCI_DOMAINS select SYS_HAS_CPU_R10000 select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN @@ -484,7 +513,6 @@ config SIBYTE_BIGSUR select BOOT_ELF32 select DMA_COHERENT select NR_CPUS_DEFAULT_4 - select PCI_DOMAINS select SIBYTE_BCM1x80 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -599,6 +627,7 @@ endchoice source "arch/mips/au1000/Kconfig" source "arch/mips/jazz/Kconfig" +source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" @@ -706,6 +735,9 @@ config MIPS_BONITO64 config MIPS_MSC bool +config MIPS_NILE4 + bool + config MIPS_DISABLE_OBSOLETE_IDE bool @@ -775,6 +807,9 @@ config IRQ_MSP_CIC config IRQ_TXX9 bool +config IRQ_GT641XX + bool + config MIPS_BOARDS_GEN bool @@ -1378,6 +1413,19 @@ config MIPS_MT_SMTC_IM_BACKSTOP impact on interrupt service overhead. Disable it only if you know what you are doing. +config MIPS_MT_SMTC_IRQAFF + bool "Support IRQ affinity API" + depends on MIPS_MT_SMTC + default n + help + Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.) + for SMTC Linux kernel. Requires platform support, of which + an example can be found in the MIPS kernel i8259 and Malta + platform code. It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY + be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to + interrupt dispatch, and should be used only if you know what + you are doing. + config MIPS_VPE_LOADER_TOM bool "Load VPE program into memory hidden from linux" depends on MIPS_VPE_LOADER @@ -1762,6 +1810,7 @@ config HW_HAS_PCI config PCI bool "Support for PCI controller" depends on HW_HAS_PCI + select PCI_DOMAINS help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@ -1775,7 +1824,6 @@ config PCI config PCI_DOMAINS bool - depends on PCI source "drivers/pci/Kconfig" diff -puN arch/mips/Makefile~git-mips arch/mips/Makefile --- a/arch/mips/Makefile~git-mips +++ a/arch/mips/Makefile @@ -60,9 +60,7 @@ vmlinux-32 = vmlinux.32 vmlinux-64 = vmlinux cflags-y += -mabi=64 -ifdef CONFIG_BUILD_ELF64 -cflags-y += $(call cc-option,-mno-explicit-relocs) -else +ifndef CONFIG_BUILD_ELF64 cflags-y += $(call cc-option,-msym32) endif endif @@ -367,6 +365,13 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iincl load-$(CONFIG_BASLER_EXCITE) += 0x80100000 # +# LASAT platforms +# +core-$(CONFIG_LASAT) += arch/mips/lasat/ +cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat +load-$(CONFIG_LASAT) += 0xffffffff80000000 + +# # Common VR41xx # core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ @@ -533,6 +538,13 @@ libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mip load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 # +# Broadcom BCM947XX boards +# +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ +cflags-$(CONFIG_BCM947XX) += -Iinclude/asm-mips/mach-bcm947xx +load-$(CONFIG_BCM947XX) := 0xffffffff80001000 + +# # SNI RM # core-$(CONFIG_SNI_RM) += arch/mips/sni/ @@ -615,6 +627,11 @@ core-y += arch/mips/kernel/ arch/mips/ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ +ifdef CONFIG_LASAT +rom.bin rom.sw: vmlinux + $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ +endif + # # Some machines like the Indy need 32-bit ELF binaries for booting purposes. # Other need ECOFF, so we build a 32-bit ELF binary for them which we then @@ -658,6 +675,7 @@ endif archclean: @$(MAKE) $(clean)=arch/mips/boot + @$(MAKE) $(clean)=arch/mips/lasat define archhelp echo ' vmlinux.ecoff - ECOFF boot image' diff -puN arch/mips/au1000/common/irq.c~git-mips arch/mips/au1000/common/irq.c --- a/arch/mips/au1000/common/irq.c~git-mips +++ a/arch/mips/au1000/common/irq.c @@ -65,19 +65,8 @@ #define EXT_INTC1_REQ1 5 /* IP 5 */ #define MIPS_TIMER_IP 7 /* IP 7 */ -extern void set_debug_traps(void); -extern irq_cpustat_t irq_stat [NR_CPUS]; extern void mips_timer_interrupt(void); -static void setup_local_irq(unsigned int irq, int type, int int_req); -static void end_irq(unsigned int irq_nr); -static inline void mask_and_ack_level_irq(unsigned int irq_nr); -static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); -static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr); -static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr); -inline void local_enable_irq(unsigned int irq_nr); -inline void local_disable_irq(unsigned int irq_nr); - void (*board_init_irq)(void); static DEFINE_SPINLOCK(irq_lock); diff -puN /dev/null arch/mips/bcm947xx/Makefile --- /dev/null +++ a/arch/mips/bcm947xx/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the BCM947xx specific kernel interface routines +# under Linux. +# + +obj-y := irq.o prom.o serial.o setup.o time.o diff -puN /dev/null arch/mips/bcm947xx/irq.c --- /dev/null +++ a/arch/mips/bcm947xx/irq.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +void plat_irq_dispatch(void) +{ + u32 cause; + + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP; + + clear_c0_status(cause); + + if (cause & CAUSEF_IP7) + do_IRQ(7); + if (cause & CAUSEF_IP2) + do_IRQ(2); + if (cause & CAUSEF_IP3) + do_IRQ(3); + if (cause & CAUSEF_IP4) + do_IRQ(4); + if (cause & CAUSEF_IP5) + do_IRQ(5); + if (cause & CAUSEF_IP6) + do_IRQ(6); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); +} diff -puN /dev/null arch/mips/bcm947xx/prom.c --- /dev/null +++ a/arch/mips/bcm947xx/prom.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +const char *get_system_type(void) +{ + return "Broadcom BCM947xx"; +} + +void __init prom_init(void) +{ + unsigned long mem; + + /* Figure out memory size by finding aliases */ + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) { + if (*(unsigned long *)((unsigned long)(prom_init) + mem) == + *(unsigned long *)(prom_init)) + break; + } + + add_memory_region(0, mem, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} diff -puN /dev/null arch/mips/bcm947xx/serial.c --- /dev/null +++ a/arch/mips/bcm947xx/serial.c @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno + */ + +#include +#include +#include +#include +#include +#include + +static struct plat_serial8250_port uart8250_data[5]; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + int i; + struct ssb_mipscore *mcore = &(ssb_bcm947xx.mipscore); + + memset(&uart8250_data, 0, sizeof(uart8250_data)); + + for (i = 0; i < mcore->nr_serial_ports; i++) { + struct plat_serial8250_port *p = &(uart8250_data[i]); + struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]); + + p->mapbase = (unsigned int) ssb_port->regs; + p->membase = (void *) ssb_port->regs; + p->irq = ssb_port->irq + 2; + p->uartclk = ssb_port->baud_base; + p->regshift = ssb_port->reg_shift; + p->iotype = UPIO_MEM; + p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; + } + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Aurelien Jarno "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for the BCM947xx platforms"); diff -puN /dev/null arch/mips/bcm947xx/setup.c --- /dev/null +++ a/arch/mips/bcm947xx/setup.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * Copyright (C) 2005 Waldemar Brodkorb + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2006 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +struct ssb_bus ssb_bcm947xx; +EXPORT_SYMBOL(ssb_bcm947xx); + +static void bcm947xx_machine_restart(char *command) +{ + printk(KERN_ALERT "Please stand by while rebooting the system...\n"); + local_irq_disable(); + /* Set the watchdog timer to reset immediately */ + ssb_chipco_watchdog_timer_set(&ssb_bcm947xx.chipco, 1); + while (1) + cpu_relax(); +} + +static void bcm947xx_machine_halt(void) +{ + /* Disable interrupts and watchdog and spin forever */ + local_irq_disable(); + ssb_chipco_watchdog_timer_set(&ssb_bcm947xx.chipco, 0); + while (1) + cpu_relax(); +} + +static int bcm947xx_get_invariants(struct ssb_bus *bus, + struct ssb_init_invariants *iv) +{ + /* TODO: fill ssb_init_invariants using boardtype/boardrev + * CFE environment variables. + */ + return 0; +} + +void __init plat_mem_setup(void) +{ + int err; + + err = ssb_bus_ssbbus_register(&ssb_bcm947xx, SSB_ENUM_BASE, + bcm947xx_get_invariants); + if (err) + panic("Failed to initialize SSB bus (err %d)\n", err); + + _machine_restart = bcm947xx_machine_restart; + _machine_halt = bcm947xx_machine_halt; + pm_power_off = bcm947xx_machine_halt; + board_time_init = bcm947xx_time_init; +} + diff -puN /dev/null arch/mips/bcm947xx/time.c --- /dev/null +++ a/arch/mips/bcm947xx/time.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#include +#include +#include +#include + +void __init +bcm947xx_time_init(void) +{ + unsigned long hz; + + /* + * Use deterministic values for initial counter interrupt + * so that calibrate delay avoids encountering a counter wrap. + */ + write_c0_count(0); + write_c0_compare(0xffff); + + hz = ssb_cpu_clock(&ssb_bcm947xx.mipscore) / 2; + if (!hz) + hz = 100000000; + + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */ + mips_hpt_frequency = hz; +} + +void __init +plat_timer_setup(struct irqaction *irq) +{ + /* Enable the timer interrupt */ + setup_irq(7, irq); +} diff -puN arch/mips/cobalt/irq.c~git-mips arch/mips/cobalt/irq.c --- a/arch/mips/cobalt/irq.c~git-mips +++ a/arch/mips/cobalt/irq.c @@ -15,102 +15,48 @@ #include #include +#include #include -#include - -/* - * We have two types of interrupts that we handle, ones that come in through - * the CPU interrupt lines, and ones that come in on the via chip. The CPU - * mappings are: - * - * 16 - Software interrupt 0 (unused) IE_SW0 - * 17 - Software interrupt 1 (unused) IE_SW1 - * 18 - Galileo chip (timer) IE_IRQ0 - * 19 - Tulip 0 + NCR SCSI IE_IRQ1 - * 20 - Tulip 1 IE_IRQ2 - * 21 - 16550 UART IE_IRQ3 - * 22 - VIA southbridge PIC IE_IRQ4 - * 23 - unused IE_IRQ5 - * - * The VIA chip is a master/slave 8259 setup and has the following interrupts: - * - * 8 - RTC - * 9 - PCI - * 14 - IDE0 - * 15 - IDE1 - */ - -static inline void galileo_irq(void) -{ - unsigned int mask, pending, devfn; - - mask = GT_READ(GT_INTRMASK_OFS); - pending = GT_READ(GT_INTRCAUSE_OFS) & mask; - - if (pending & GT_INTR_T0EXP_MSK) { - GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK); - do_IRQ(COBALT_GALILEO_IRQ); - } else if (pending & GT_INTR_RETRYCTR0_MSK) { - devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8; - GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK); - printk(KERN_WARNING - "Galileo: PCI retry count exceeded (%02x.%u)\n", - PCI_SLOT(devfn), PCI_FUNC(devfn)); - } else { - GT_WRITE(GT_INTRMASK_OFS, mask & ~pending); - printk(KERN_WARNING - "Galileo: masking unexpected interrupt %08x\n", pending); - } -} - -static inline void via_pic_irq(void) -{ - int irq; - - irq = i8259_irq(); - if (irq >= 0) - do_IRQ(irq); -} +#include asmlinkage void plat_irq_dispatch(void) { - unsigned pending = read_c0_status() & read_c0_cause(); + unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM; + int irq; - if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ - galileo_irq(); - else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ - via_pic_irq(); - else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ - do_IRQ(COBALT_CPU_IRQ + 3); - else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ - do_IRQ(COBALT_CPU_IRQ + 4); - else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ - do_IRQ(COBALT_CPU_IRQ + 5); - else if (pending & CAUSEF_IP7) /* IRQ 23 */ - do_IRQ(COBALT_CPU_IRQ + 7); + if (pending & CAUSEF_IP2) + gt641xx_irq_dispatch(); + else if (pending & CAUSEF_IP6) { + irq = i8259_irq(); + if (irq < 0) + spurious_interrupt(); + else + do_IRQ(irq); + } else if (pending & CAUSEF_IP3) + do_IRQ(MIPS_CPU_IRQ_BASE + 3); + else if (pending & CAUSEF_IP4) + do_IRQ(MIPS_CPU_IRQ_BASE + 4); + else if (pending & CAUSEF_IP5) + do_IRQ(MIPS_CPU_IRQ_BASE + 5); + else if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else + spurious_interrupt(); } -static struct irqaction irq_via = { - no_action, 0, { { 0, } }, "cascade", NULL, NULL +static struct irqaction cascade = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", }; void __init arch_init_irq(void) { - /* - * Mask all Galileo interrupts. The Galileo - * handler is set in cobalt_timer_setup() - */ - GT_WRITE(GT_INTRMASK_OFS, 0); - - init_i8259_irqs(); /* 0 ... 15 */ - mips_cpu_irq_init(); /* 16 ... 23 */ - - /* - * Mask all cpu interrupts - * (except IE4, we already masked those at VIA level) - */ - change_c0_status(ST0_IM, IE_IRQ4); + mips_cpu_irq_init(); + gt641xx_irq_init(); + init_i8259_irqs(); - setup_irq(COBALT_VIA_IRQ, &irq_via); + setup_irq(GT641XX_CASCADE_IRQ, &cascade); + setup_irq(I8259_CASCADE_IRQ, &cascade); } diff -puN arch/mips/cobalt/rtc.c~git-mips arch/mips/cobalt/rtc.c --- a/arch/mips/cobalt/rtc.c~git-mips +++ a/arch/mips/cobalt/rtc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include static struct resource cobalt_rtc_resource[] __initdata = { @@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resour .flags = IORESOURCE_IO, }, { - .start = 8, - .end = 8, + .start = RTC_IRQ, + .end = RTC_IRQ, .flags = IORESOURCE_IRQ, }, }; diff -puN arch/mips/cobalt/serial.c~git-mips arch/mips/cobalt/serial.c --- a/arch/mips/cobalt/serial.c~git-mips +++ a/arch/mips/cobalt/serial.c @@ -24,6 +24,7 @@ #include #include +#include static struct resource cobalt_uart_resource[] __initdata = { { @@ -32,15 +33,15 @@ static struct resource cobalt_uart_resou .flags = IORESOURCE_MEM, }, { - .start = COBALT_SERIAL_IRQ, - .end = COBALT_SERIAL_IRQ, + .start = SERIAL_IRQ, + .end = SERIAL_IRQ, .flags = IORESOURCE_IRQ, }, }; static struct plat_serial8250_port cobalt_serial8250_port[] = { { - .irq = COBALT_SERIAL_IRQ, + .irq = SERIAL_IRQ, .uartclk = 18432000, .iotype = UPIO_MEM, .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, diff -puN arch/mips/cobalt/setup.c~git-mips arch/mips/cobalt/setup.c --- a/arch/mips/cobalt/setup.c~git-mips +++ a/arch/mips/cobalt/setup.c @@ -20,6 +20,7 @@ #include #include +#include extern void cobalt_machine_restart(char *command); extern void cobalt_machine_halt(void); @@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqa /* Load timer value for HZ (TCLK is 50MHz) */ GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); - /* Enable timer */ + /* Enable timer0 */ GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); - /* Register interrupt */ - setup_irq(COBALT_GALILEO_IRQ, irq); - - /* Enable interrupt */ - GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS)); + setup_irq(GT641XX_TIMER0_IRQ, irq); } /* diff -puN /dev/null arch/mips/configs/lasat_defconfig --- /dev/null +++ a/arch/mips/configs/lasat_defconfig @@ -0,0 +1,828 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc3 +# Sat Aug 18 17:37:58 2007 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +CONFIG_LASAT=y +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_WR_PPMC is not set +CONFIG_PICVUE=y +CONFIG_PICVUE_PROC=y +CONFIG_DS1603=y +CONFIG_LASAT_SYSCTL=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +CONFIG_MIPS_NILE4=y +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_R5000_CPU_SCACHE=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_LASAT=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_IDEPCI_PCIBUS_ORDER=y +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_ONLYDISK is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +CONFIG_BLK_DEV_CMD64X=y +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_DM9000 is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +CONFIG_PCNET32=y +# CONFIG_PCNET32_NAPI is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_TC35815 is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_INFINIBAND is not set +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +CONFIG_CONFIGFS_FS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -puN arch/mips/jazz/Makefile~git-mips arch/mips/jazz/Makefile --- a/arch/mips/jazz/Makefile~git-mips +++ a/arch/mips/jazz/Makefile @@ -2,6 +2,6 @@ # Makefile for the Jazz family specific parts of the kernel # -obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o +obj-y := irq.o jazzdma.o reset.o setup.o EXTRA_CFLAGS += -Werror diff -puN arch/mips/jazz/irq.c~git-mips arch/mips/jazz/irq.c --- a/arch/mips/jazz/irq.c~git-mips +++ a/arch/mips/jazz/irq.c @@ -11,15 +11,17 @@ #include #include +#include #include #include #include +#include static DEFINE_SPINLOCK(r4030_lock); static void enable_r4030_irq(unsigned int irq) { - unsigned int mask = 1 << (irq - JAZZ_PARALLEL_IRQ); + unsigned int mask = 1 << (irq - JAZZ_IRQ_START); unsigned long flags; spin_lock_irqsave(&r4030_lock, flags); @@ -30,7 +32,7 @@ static void enable_r4030_irq(unsigned in void disable_r4030_irq(unsigned int irq) { - unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); + unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START)); unsigned long flags; spin_lock_irqsave(&r4030_lock, flags); @@ -51,7 +53,7 @@ void __init init_r4030_ints(void) { int i; - for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) + for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++) set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); @@ -66,82 +68,40 @@ void __init init_r4030_ints(void) */ void __init arch_init_irq(void) { + /* + * this is a hack to get back the still needed wired mapping + * killed by init_mm() + */ + + /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ + add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); + /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ + add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); + /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ + add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); + init_i8259_irqs(); /* Integrated i8259 */ + mips_cpu_irq_init(); init_r4030_ints(); - change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1); -} - -static void loc_call(unsigned int irq, unsigned int mask) -{ - r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, - r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask); - do_IRQ(irq); - r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, - r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask); -} - -static void ll_local_dev(void) -{ - switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) { - case 0: - panic("Unimplemented loc_no_irq handler"); - break; - case 4: - loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_PARALLEL); - break; - case 8: - loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_FLOPPY); - break; - case 12: - panic("Unimplemented loc_sound handler"); - break; - case 16: - panic("Unimplemented loc_video handler"); - break; - case 20: - loc_call(JAZZ_ETHERNET_IRQ, JAZZ_IE_ETHERNET); - break; - case 24: - loc_call(JAZZ_SCSI_IRQ, JAZZ_IE_SCSI); - break; - case 28: - loc_call(JAZZ_KEYBOARD_IRQ, JAZZ_IE_KEYBOARD); - break; - case 32: - loc_call(JAZZ_MOUSE_IRQ, JAZZ_IE_MOUSE); - break; - case 36: - loc_call(JAZZ_SERIAL1_IRQ, JAZZ_IE_SERIAL1); - break; - case 40: - loc_call(JAZZ_SERIAL2_IRQ, JAZZ_IE_SERIAL2); - break; - } + change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1); } asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_cause() & read_c0_status(); + unsigned int irq; - if (pending & IE_IRQ5) - write_c0_compare(0); - else if (pending & IE_IRQ4) { + if (pending & IE_IRQ4) { r4030_read_reg32(JAZZ_TIMER_REGISTER); do_IRQ(JAZZ_TIMER_IRQ); - } else if (pending & IE_IRQ3) - panic("Unimplemented ISA NMI handler"); - else if (pending & IE_IRQ2) + } else if (pending & IE_IRQ2) do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK)); else if (pending & IE_IRQ1) { - ll_local_dev(); - } else if (unlikely(pending & IE_IRQ0)) - panic("Unimplemented local_dma handler"); - else if (pending & IE_SW1) { - clear_c0_cause(IE_SW1); - panic("Unimplemented sw1 handler"); - } else if (pending & IE_SW0) { - clear_c0_cause(IE_SW0); - panic("Unimplemented sw0 handler"); + irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2; + if (likely(irq > 0)) + do_IRQ(irq + JAZZ_IRQ_START - 1); + else + panic("Unimplemented loc_no_irq handler"); } } diff -puN arch/mips/jazz/jazz-platform.c~git-mips /dev/null --- a/arch/mips/jazz/jazz-platform.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include - -#include - -/* - * Confusion ... It seems the original Microsoft Jazz machine used to have a - * 4.096MHz clock for its UART while the MIPS Magnum and Millenium systems - * had 8MHz. The Olivetti M700-10 and the Acer PICA have 1.8432MHz like PCs. - */ -#ifdef CONFIG_OLIVETTI_M700 -#define JAZZ_BASE_BAUD 1843200 -#else -#define JAZZ_BASE_BAUD 8000000 /* 3072000 */ -#endif - -#define JAZZ_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) - -#define JAZZ_PORT(base, int) \ -{ \ - .mapbase = base, \ - .irq = int, \ - .uartclk = JAZZ_BASE_BAUD, \ - .iotype = UPIO_MEM, \ - .flags = JAZZ_UART_FLAGS, \ - .regshift = 0, \ -} - -static struct plat_serial8250_port uart8250_data[] = { - JAZZ_PORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ), - JAZZ_PORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ), - { }, -}; - -static struct platform_device uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = uart8250_data, - }, -}; - -static int __init uart8250_init(void) -{ - return platform_device_register(&uart8250_device); -} - -module_init(uart8250_init); - -MODULE_AUTHOR("Ralf Baechle "); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for the Jazz family"); diff -puN arch/mips/jazz/jazzdma.c~git-mips arch/mips/jazz/jazzdma.c --- a/arch/mips/jazz/jazzdma.c~git-mips +++ a/arch/mips/jazz/jazzdma.c @@ -27,7 +27,7 @@ */ #define CONF_DEBUG_VDMA 0 -static unsigned long vdma_pagetable_start; +static VDMA_PGTBL_ENTRY *pgtbl; static DEFINE_SPINLOCK(vdma_lock); @@ -46,7 +46,6 @@ static int debuglvl = 3; */ static inline void vdma_pgtbl_init(void) { - VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; unsigned long paddr = 0; int i; @@ -60,31 +59,31 @@ static inline void vdma_pgtbl_init(void) /* * Initialize the Jazz R4030 dma controller */ -void __init vdma_init(void) +static int __init vdma_init(void) { /* * Allocate 32k of memory for DMA page tables. This needs to be page * aligned and should be uncached to avoid cache flushing after every * update. */ - vdma_pagetable_start = - (unsigned long) alloc_bootmem_low_pages(VDMA_PGTBL_SIZE); - if (!vdma_pagetable_start) + pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA, + get_order(VDMA_PGTBL_SIZE)); + if (!pgtbl) BUG(); - dma_cache_wback_inv(vdma_pagetable_start, VDMA_PGTBL_SIZE); - vdma_pagetable_start = KSEG1ADDR(vdma_pagetable_start); + dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE); + pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl); /* * Clear the R4030 translation table */ vdma_pgtbl_init(); - r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, - CPHYSADDR(vdma_pagetable_start)); + r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl)); r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE); r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0); - printk("VDMA: R4030 DMA pagetables initialized.\n"); + printk(KERN_INFO "VDMA: R4030 DMA pagetables initialized.\n"); + return 0; } /* @@ -92,7 +91,6 @@ void __init vdma_init(void) */ unsigned long vdma_alloc(unsigned long paddr, unsigned long size) { - VDMA_PGTBL_ENTRY *entry = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; int first, last, pages, frame, i; unsigned long laddr, flags; @@ -114,10 +112,10 @@ unsigned long vdma_alloc(unsigned long p /* * Find free chunk */ - pages = (size + 4095) >> 12; /* no. of pages to allocate */ + pages = VDMA_PAGE(paddr + size) - VDMA_PAGE(paddr) + 1; first = 0; while (1) { - while (entry[first].owner != VDMA_PAGE_EMPTY && + while (pgtbl[first].owner != VDMA_PAGE_EMPTY && first < VDMA_PGTBL_ENTRIES) first++; if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */ spin_unlock_irqrestore(&vdma_lock, flags); @@ -125,12 +123,13 @@ unsigned long vdma_alloc(unsigned long p } last = first + 1; - while (entry[last].owner == VDMA_PAGE_EMPTY + while (pgtbl[last].owner == VDMA_PAGE_EMPTY && last - first < pages) last++; if (last - first == pages) break; /* found */ + first = last + 1; } /* @@ -140,8 +139,8 @@ unsigned long vdma_alloc(unsigned long p frame = paddr & ~(VDMA_PAGESIZE - 1); for (i = first; i < last; i++) { - entry[i].frame = frame; - entry[i].owner = laddr; + pgtbl[i].frame = frame; + pgtbl[i].owner = laddr; frame += VDMA_PAGESIZE; } @@ -160,10 +159,10 @@ unsigned long vdma_alloc(unsigned long p printk("%08x ", i << 12); printk("\nPADDR: "); for (i = first; i < last; i++) - printk("%08x ", entry[i].frame); + printk("%08x ", pgtbl[i].frame); printk("\nOWNER: "); for (i = first; i < last; i++) - printk("%08x ", entry[i].owner); + printk("%08x ", pgtbl[i].owner); printk("\n"); } @@ -181,7 +180,6 @@ EXPORT_SYMBOL(vdma_alloc); */ int vdma_free(unsigned long laddr) { - VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; int i; i = laddr >> 12; @@ -213,8 +211,6 @@ EXPORT_SYMBOL(vdma_free); */ int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size) { - VDMA_PGTBL_ENTRY *pgtbl = - (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; int first, pages, npages; if (laddr > 0xffffff) { @@ -289,8 +285,6 @@ unsigned long vdma_phys2log(unsigned lon { int i; int frame; - VDMA_PGTBL_ENTRY *pgtbl = - (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; frame = paddr & ~(VDMA_PAGESIZE - 1); @@ -312,9 +306,6 @@ EXPORT_SYMBOL(vdma_phys2log); */ unsigned long vdma_log2phys(unsigned long laddr) { - VDMA_PGTBL_ENTRY *pgtbl = - (VDMA_PGTBL_ENTRY *) vdma_pagetable_start; - return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1)); } @@ -564,3 +555,5 @@ int vdma_get_enable(int channel) return enable; } + +arch_initcall(vdma_init); diff -puN arch/mips/jazz/setup.c~git-mips arch/mips/jazz/setup.c --- a/arch/mips/jazz/setup.c~git-mips +++ a/arch/mips/jazz/setup.c @@ -7,6 +7,7 @@ * * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2007 by Thomas Bogendoerfer */ #include #include @@ -20,6 +21,8 @@ #include #include #include +#include +#include #include #include @@ -30,6 +33,7 @@ #include #include #include +#include extern asmlinkage void jazz_handle_int(void); @@ -72,10 +76,8 @@ void __init plat_mem_setup(void) /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ add_wired_entry (0x02000017, 0x03c00017, 0xe0000000, PM_64K); - /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ add_wired_entry (0x02400017, 0x02440017, 0xe2000000, PM_16M); - /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ add_wired_entry (0x01800017, 0x01000017, 0xe4000000, PM_4M); @@ -94,6 +96,7 @@ void __init plat_mem_setup(void) _machine_restart = jazz_machine_restart; +#ifdef CONFIG_VT screen_info = (struct screen_info) { 0, 0, /* orig-x, orig-y */ 0, /* unused */ @@ -105,6 +108,112 @@ void __init plat_mem_setup(void) 0, /* orig_video_isVGA */ 16 /* orig_video_points */ }; +#endif - vdma_init(); + add_preferred_console("ttyS", 0, "9600"); } + +#ifdef CONFIG_OLIVETTI_M700 +#define UART_CLK 1843200 +#else +/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know + exactly which ones ... XXX */ +#define UART_CLK (8000000 / 16) /* ( 3072000 / 16) */ +#endif + +#define MEMPORT(_base, _irq) \ + { \ + .mapbase = (_base), \ + .membase = (void *)(_base), \ + .irq = (_irq), \ + .uartclk = UART_CLK, \ + .iotype = UPIO_MEM, \ + .flags = UPF_BOOT_AUTOCONF, \ + } + +static struct plat_serial8250_port jazz_serial_data[] = { + MEMPORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ), + MEMPORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ), + { }, +}; + +static struct platform_device jazz_serial8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = jazz_serial_data, + }, +}; + +static struct resource jazz_esp_rsrc[] = { + { + .start = JAZZ_SCSI_BASE, + .end = JAZZ_SCSI_BASE + 31, + .flags = IORESOURCE_MEM + }, + { + .start = JAZZ_SCSI_DMA, + .end = JAZZ_SCSI_DMA, + .flags = IORESOURCE_MEM + }, + { + .start = JAZZ_SCSI_IRQ, + .end = JAZZ_SCSI_IRQ, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device jazz_esp_pdev = { + .name = "jazz_esp", + .num_resources = ARRAY_SIZE(jazz_esp_rsrc), + .resource = jazz_esp_rsrc +}; + +static struct resource jazz_sonic_rsrc[] = { + { + .start = JAZZ_ETHERNET_BASE, + .end = JAZZ_ETHERNET_BASE + 0xff, + .flags = IORESOURCE_MEM + }, + { + .start = JAZZ_ETHERNET_IRQ, + .end = JAZZ_ETHERNET_IRQ, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device jazz_sonic_pdev = { + .name = "jazzsonic", + .num_resources = ARRAY_SIZE(jazz_sonic_rsrc), + .resource = jazz_sonic_rsrc +}; + +static struct resource jazz_cmos_rsrc[] = { + { + .start = 0x70, + .end = 0x71, + .flags = IORESOURCE_IO + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device jazz_cmos_pdev = { + .name = "rtc_cmos", + .num_resources = ARRAY_SIZE(jazz_cmos_rsrc), + .resource = jazz_cmos_rsrc +}; + +static int __init jazz_setup_devinit(void) +{ + platform_device_register(&jazz_serial8250_device); + platform_device_register(&jazz_esp_pdev); + platform_device_register(&jazz_sonic_pdev); + platform_device_register(&jazz_cmos_pdev); + return 0; +} + +device_initcall(jazz_setup_devinit); diff -puN arch/mips/jmr3927/rbhma3100/irq.c~git-mips arch/mips/jmr3927/rbhma3100/irq.c --- a/arch/mips/jmr3927/rbhma3100/irq.c~git-mips +++ a/arch/mips/jmr3927/rbhma3100/irq.c @@ -104,7 +104,9 @@ static irqreturn_t jmr3927_ioc_interrupt } static struct irqaction ioc_action = { - jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL, + .handler = jmr3927_ioc_interrupt, + .mask = CPU_MASK_NONE, + .name = "IOC", }; static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) @@ -116,7 +118,9 @@ static irqreturn_t jmr3927_pcierr_interr return IRQ_HANDLED; } static struct irqaction pcierr_action = { - jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL, + .handler = jmr3927_pcierr_interrupt, + .mask = CPU_MASK_NONE, + .name = "PCI error", }; static void __init jmr3927_irq_init(void); diff -puN arch/mips/kernel/Makefile~git-mips arch/mips/kernel/Makefile --- a/arch/mips/kernel/Makefile~git-mips +++ a/arch/mips/kernel/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000 obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o +obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o obj-$(CONFIG_32BIT) += scall32-o32.o obj-$(CONFIG_64BIT) += scall64-64.o diff -puN arch/mips/kernel/cpu-probe.c~git-mips arch/mips/kernel/cpu-probe.c --- a/arch/mips/kernel/cpu-probe.c~git-mips +++ a/arch/mips/kernel/cpu-probe.c @@ -159,6 +159,7 @@ static inline void check_wait(void) case CPU_5KC: case CPU_25KF: case CPU_PR4450: + case CPU_BCM3302: cpu_wait = r4k_wait; break; @@ -745,14 +746,6 @@ static inline void cpu_probe_sibyte(stru { decode_configs(c); - /* - * For historical reasons the SB1 comes with it's own variant of - * cache code which eventually will be folded into c-r4k.c. Until - * then we pretend it's got it's own cache architecture. - */ - c->options &= ~MIPS_CPU_4K_CACHE; - c->options |= MIPS_CPU_SB1_CACHE; - switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; @@ -793,6 +786,22 @@ static inline void cpu_probe_philips(str } +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_BCM3302: + c->cputype = CPU_BCM3302; + break; + case PRID_IMP_BCM4710: + c->cputype = CPU_BCM4710; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } +} + __init void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -815,6 +824,9 @@ __init void cpu_probe(void) case PRID_COMP_SIBYTE: cpu_probe_sibyte(c); break; + case PRID_COMP_BROADCOM: + cpu_probe_broadcom(c); + break; case PRID_COMP_SANDCRAFT: cpu_probe_sandcraft(c); break; diff -puN arch/mips/kernel/i8259.c~git-mips arch/mips/kernel/i8259.c --- a/arch/mips/kernel/i8259.c~git-mips +++ a/arch/mips/kernel/i8259.c @@ -30,8 +30,10 @@ static int i8259A_auto_eoi = -1; DEFINE_SPINLOCK(i8259A_lock); -/* some platforms call this... */ -void mask_and_ack_8259A(unsigned int); +static void disable_8259A_irq(unsigned int irq); +static void enable_8259A_irq(unsigned int irq); +static void mask_and_ack_8259A(unsigned int irq); +static void init_8259A(int auto_eoi); static struct irq_chip i8259A_chip = { .name = "XT-PIC", @@ -39,6 +41,9 @@ static struct irq_chip i8259A_chip = { .disable = disable_8259A_irq, .unmask = enable_8259A_irq, .mask_ack = mask_and_ack_8259A, +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF + .set_affinity = plat_set_irq_affinity, +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ }; /* @@ -53,7 +58,7 @@ static unsigned int cached_irq_mask = 0x #define cached_master_mask (cached_irq_mask) #define cached_slave_mask (cached_irq_mask >> 8) -void disable_8259A_irq(unsigned int irq) +static void disable_8259A_irq(unsigned int irq) { unsigned int mask; unsigned long flags; @@ -69,7 +74,7 @@ void disable_8259A_irq(unsigned int irq) spin_unlock_irqrestore(&i8259A_lock, flags); } -void enable_8259A_irq(unsigned int irq) +static void enable_8259A_irq(unsigned int irq) { unsigned int mask; unsigned long flags; @@ -139,7 +144,7 @@ static inline int i8259A_irq_real(unsign * first, _then_ send the EOI, and the order of EOI * to the two 8259s is important! */ -void mask_and_ack_8259A(unsigned int irq) +static void mask_and_ack_8259A(unsigned int irq) { unsigned int irqmask; unsigned long flags; @@ -256,7 +261,7 @@ static int __init i8259A_init_sysfs(void device_initcall(i8259A_init_sysfs); -void init_8259A(int auto_eoi) +static void init_8259A(int auto_eoi) { unsigned long flags; @@ -303,7 +308,9 @@ void init_8259A(int auto_eoi) * IRQ2 is cascade interrupt to second interrupt controller */ static struct irqaction irq2 = { - no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", }; static struct resource pic1_io_resource = { diff -puN /dev/null arch/mips/kernel/irq-gt641xx.c --- /dev/null +++ a/arch/mips/kernel/irq-gt641xx.c @@ -0,0 +1,131 @@ +/* + * GT641xx IRQ routines. + * + * Copyright (C) 2007 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#include + +#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE)) + +static DEFINE_SPINLOCK(gt641xx_irq_lock); + +static void ack_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 cause; + + spin_lock_irqsave(>641xx_irq_lock, flags); + cause = GT_READ(GT_INTRCAUSE_OFS); + cause &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRCAUSE_OFS, cause); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static void mask_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 mask; + + spin_lock_irqsave(>641xx_irq_lock, flags); + mask = GT_READ(GT_INTRMASK_OFS); + mask &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRMASK_OFS, mask); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static void mask_ack_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 cause, mask; + + spin_lock_irqsave(>641xx_irq_lock, flags); + mask = GT_READ(GT_INTRMASK_OFS); + mask &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRMASK_OFS, mask); + + cause = GT_READ(GT_INTRCAUSE_OFS); + cause &= ~GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRCAUSE_OFS, cause); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static void unmask_gt641xx_irq(unsigned int irq) +{ + unsigned long flags; + u32 mask; + + spin_lock_irqsave(>641xx_irq_lock, flags); + mask = GT_READ(GT_INTRMASK_OFS); + mask |= GT641XX_IRQ_TO_BIT(irq); + GT_WRITE(GT_INTRMASK_OFS, mask); + spin_unlock_irqrestore(>641xx_irq_lock, flags); +} + +static struct irq_chip gt641xx_irq_chip = { + .name = "GT641xx", + .ack = ack_gt641xx_irq, + .mask = mask_gt641xx_irq, + .mask_ack = mask_ack_gt641xx_irq, + .unmask = unmask_gt641xx_irq, +}; + +void gt641xx_irq_dispatch(void) +{ + u32 cause, mask; + int i; + + cause = GT_READ(GT_INTRCAUSE_OFS); + mask = GT_READ(GT_INTRMASK_OFS); + cause &= mask; + + /* + * bit0 : logical or of all the interrupt bits. + * bit30: logical or of bits[29:26,20:1]. + * bit31: logical or of bits[25:1]. + */ + for (i = 1; i < 30; i++) { + if (cause & (1U << i)) { + do_IRQ(GT641XX_IRQ_BASE + i); + return; + } + } + + atomic_inc(&irq_err_count); +} + +void __init gt641xx_irq_init(void) +{ + int i; + + GT_WRITE(GT_INTRMASK_OFS, 0); + GT_WRITE(GT_INTRCAUSE_OFS, 0); + + /* + * bit0 : logical or of all the interrupt bits. + * bit30: logical or of bits[29:26,20:1]. + * bit31: logical or of bits[25:1]. + */ + for (i = 1; i < 30; i++) + set_irq_chip_and_handler(GT641XX_IRQ_BASE + i, + >641xx_irq_chip, handle_level_irq); +} diff -puN arch/mips/kernel/proc.c~git-mips arch/mips/kernel/proc.c --- a/arch/mips/kernel/proc.c~git-mips +++ a/arch/mips/kernel/proc.c @@ -82,6 +82,8 @@ static const char *cpu_name[] = { [CPU_VR4181] = "NEC VR4181", [CPU_VR4181A] = "NEC VR4181A", [CPU_SR71000] = "Sandcraft SR71000", + [CPU_BCM3302] = "Broadcom BCM3302", + [CPU_BCM4710] = "Broadcom BCM4710", [CPU_PR4450] = "Philips PR4450", [CPU_LOONGSON2] = "ICT Loongson-2", }; diff -puN arch/mips/kernel/process.c~git-mips arch/mips/kernel/process.c --- a/arch/mips/kernel/process.c~git-mips +++ a/arch/mips/kernel/process.c @@ -231,8 +231,8 @@ long kernel_thread(int (*fn)(void *), vo regs.cp0_epc = (unsigned long) kernel_thread_helper; regs.cp0_status = read_c0_status(); #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - regs.cp0_status &= ~(ST0_KUP | ST0_IEC); - regs.cp0_status |= ST0_IEP; + regs.cp0_status = (regs.cp0_status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | + ((regs.cp0_status & (ST0_KUC | ST0_IEC)) << 2); #else regs.cp0_status |= ST0_EXL; #endif diff -puN arch/mips/kernel/smtc.c~git-mips arch/mips/kernel/smtc.c --- a/arch/mips/kernel/smtc.c~git-mips +++ a/arch/mips/kernel/smtc.c @@ -603,6 +603,60 @@ int setup_irq_smtc(unsigned int irq, str return setup_irq(irq, new); } +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * Support for IRQ affinity to TCs + */ + +void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity) +{ + /* + * If a "fast path" cache of quickly decodable affinity state + * is maintained, this is where it gets done, on a call up + * from the platform affinity code. + */ +} + +void smtc_forward_irq(unsigned int irq) +{ + int target; + + /* + * OK wise guy, now figure out how to get the IRQ + * to be serviced on an authorized "CPU". + * + * Ideally, to handle the situation where an IRQ has multiple + * eligible CPUS, we would maintain state per IRQ that would + * allow a fair distribution of service requests. Since the + * expected use model is any-or-only-one, for simplicity + * and efficiency, we just pick the easiest one to find. + */ + + target = first_cpu(irq_desc[irq].affinity); + + /* + * We depend on the platform code to have correctly processed + * IRQ affinity change requests to ensure that the IRQ affinity + * mask has been purged of bits corresponding to nonexistent and + * offline "CPUs", and to TCs bound to VPEs other than the VPE + * connected to the physical interrupt input for the interrupt + * in question. Otherwise we have a nasty problem with interrupt + * mask management. This is best handled in non-performance-critical + * platform IRQ affinity setting code, to minimize interrupt-time + * checks. + */ + + /* If no one is eligible, service locally */ + if (target >= NR_CPUS) { + do_IRQ_no_affinity(irq); + return; + } + + smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq); +} + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + /* * IPI model for SMTC is tricky, because interrupts aren't TC-specific. * Within a VPE one TC can interrupt another by different approaches. @@ -656,7 +710,7 @@ static __inline__ int atomic_postincreme " addu %1, %0, 1 \n" " sc %1, %2 \n" " beqz %1, 1b \n" - " sync \n" + __WEAK_LLSC_MB : "=&r" (result), "=&r" (temp), "=m" (*pv) : "m" (*pv) : "memory"); @@ -827,6 +881,15 @@ void ipi_decode(struct smtc_ipi *pipi) break; } break; +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF + case IRQ_AFFINITY_IPI: + /* + * Accept a "forwarded" interrupt that was initially + * taken by a TC who doesn't have affinity for the IRQ. + */ + do_IRQ_no_affinity((int)arg_copy); + break; +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ default: printk("Impossible SMTC IPI Type 0x%x\n", type_copy); break; diff -puN arch/mips/kernel/traps.c~git-mips arch/mips/kernel/traps.c --- a/arch/mips/kernel/traps.c~git-mips +++ a/arch/mips/kernel/traps.c @@ -1075,8 +1075,8 @@ void *set_except_vector(int n, void *add exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { - *(volatile u32 *)(ebase + 0x200) = 0x08000000 | - (0x03ffffff & (handler >> 2)); + *(u32 *)(ebase + 0x200) = 0x08000000 | + (0x03ffffff & (handler >> 2)); flush_icache_range(ebase + 0x200, ebase + 0x204); } return (void *)old_handler; @@ -1435,6 +1435,9 @@ void __init set_handler (unsigned long o flush_icache_range(ebase + offset, ebase + offset + size); } +static char panic_null_cerr[] __initdata = + "Trying to set NULL cache error exception handler"; + /* Install uncached CPU exception handler */ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) { @@ -1445,6 +1448,9 @@ void __init set_uncached_handler (unsign unsigned long uncached_ebase = TO_UNCAC(ebase); #endif + if (!addr) + panic(panic_null_cerr); + memcpy((void *)(uncached_ebase + offset), addr, size); } diff -puN arch/mips/kernel/vmlinux.lds.S~git-mips arch/mips/kernel/vmlinux.lds.S --- a/arch/mips/kernel/vmlinux.lds.S~git-mips +++ a/arch/mips/kernel/vmlinux.lds.S @@ -6,161 +6,202 @@ OUTPUT_ARCH(mips) ENTRY(kernel_entry) jiffies = JIFFIES; + SECTIONS { #ifdef CONFIG_BOOT_ELF64 - /* Read-only sections, merged into text segment: */ - /* . = 0xc000000000000000; */ + /* Read-only sections, merged into text segment: */ + /* . = 0xc000000000000000; */ - /* This is the value for an Origin kernel, taken from an IRIX kernel. */ - /* . = 0xc00000000001c000; */ + /* This is the value for an Origin kernel, taken from an IRIX kernel. */ + /* . = 0xc00000000001c000; */ - /* Set the vaddr for the text segment to a value - >= 0xa800 0000 0001 9000 if no symmon is going to configured - >= 0xa800 0000 0030 0000 otherwise */ - - /* . = 0xa800000000300000; */ - /* . = 0xa800000000300000; */ - . = 0xffffffff80300000; + /* Set the vaddr for the text segment to a value + * >= 0xa800 0000 0001 9000 if no symmon is going to configured + * >= 0xa800 0000 0030 0000 otherwise + */ + + /* . = 0xa800000000300000; */ + /* . = 0xa800000000300000; */ + . = 0xffffffff80300000; #endif - . = LOADADDR; - /* read-only */ - _text = .; /* Text and read-only data */ - .text : { - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT - *(.fixup) - *(.gnu.warning) - } =0 - - _etext = .; /* End of text section */ - - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - __start___dbe_table = .; /* Exception table for data bus errors */ - __dbe_table : { *(__dbe_table) } - __stop___dbe_table = .; - - RODATA - - /* writeable */ - .data : { /* Data */ - . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ - /* - * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which - * limits the maximum alignment to at most 32kB and results in the following - * warning: - * - * CC arch/mips/kernel/init_task.o - * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’ - * is greater than maximum object file alignment. Using 32768 - */ - . = ALIGN(_PAGE_SIZE); - *(.data.init_task) - - DATA_DATA - - CONSTRUCTORS - } - _gp = . + 0x8000; - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - - . = ALIGN(_PAGE_SIZE); - __nosave_begin = .; - .data_nosave : { *(.data.nosave) } - . = ALIGN(_PAGE_SIZE); - __nosave_end = .; - - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - _edata = .; /* End of data section */ - - /* will be freed after init */ - . = ALIGN(_PAGE_SIZE); /* Init code and data */ - __init_begin = .; - .init.text : { - _sinittext = .; - *(.init.text) - _einittext = .; - } - .init.data : { *(.init.data) } - . = ALIGN(16); - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; - - __initcall_start = .; - .initcall.init : { - INITCALLS - } - __initcall_end = .; - - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; - SECURITY_INIT - /* .exit.text is discarded at runtime, not link time, to deal with - references from .rodata */ - .exit.text : { *(.exit.text) } - .exit.data : { *(.exit.data) } + . = LOADADDR; + /* read-only */ + _text = .; /* Text and read-only data */ + .text : { + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + *(.fixup) + *(.gnu.warning) + } =0 + _etext = .; /* End of text section */ + + /* Exception table */ + . = ALIGN(16); + __ex_table : { + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + } + + /* Exception table for data bus errors */ + __dbe_table : { + __start___dbe_table = .; + *(__dbe_table) + __stop___dbe_table = .; + } + RODATA + + /* writeable */ + .data : { /* Data */ + . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ + /* + * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which + * limits the maximum alignment to at most 32kB and results in the following + * warning: + * + * CC arch/mips/kernel/init_task.o + * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’ + * is greater than maximum object file alignment. Using 32768 + */ + . = ALIGN(_PAGE_SIZE); + *(.data.init_task) + + DATA_DATA + CONSTRUCTORS + } + _gp = . + 0x8000; + .lit8 : { + *(.lit8) + } + .lit4 : { + *(.lit4) + } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : { + *(.sdata) + } + + . = ALIGN(_PAGE_SIZE); + .data_nosave : { + __nosave_begin = .; + *(.data.nosave) + } + . = ALIGN(_PAGE_SIZE); + __nosave_end = .; + + . = ALIGN(32); + .data.cacheline_aligned : { + *(.data.cacheline_aligned) + } + _edata = .; /* End of data section */ + + /* will be freed after init */ + . = ALIGN(_PAGE_SIZE); /* Init code and data */ + __init_begin = .; + .init.text : { + _sinittext = .; + *(.init.text) + _einittext = .; + } + .init.data : { + *(.init.data) + } + . = ALIGN(16); + .init.setup : { + __setup_start = .; + *(.init.setup) + __setup_end = .; + } + + .initcall.init : { + __initcall_start = .; + INITCALLS + __initcall_end = .; + } + + .con_initcall.init : { + __con_initcall_start = .; + *(.con_initcall.init) + __con_initcall_end = .; + } + SECURITY_INIT + + /* .exit.text is discarded at runtime, not link time, to deal with + * references from .rodata + */ + .exit.text : { + *(.exit.text) + } + .exit.data : { + *(.exit.data) + } #if defined(CONFIG_BLK_DEV_INITRD) - . = ALIGN(_PAGE_SIZE); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; + . = ALIGN(_PAGE_SIZE); + .init.ramfs : { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + } #endif - PERCPU(_PAGE_SIZE) - . = ALIGN(_PAGE_SIZE); - __init_end = .; - /* freed after init ends here */ - - __bss_start = .; /* BSS */ - .sbss : { - *(.sbss) - *(.scommon) - } - .bss : { - *(.bss) - *(COMMON) - } - __bss_stop = .; - - _end = . ; - - /* Sections to be discarded */ - /DISCARD/ : { - *(.exitcall.exit) - - /* ABI crap starts here */ - *(.MIPS.options) - *(.options) - *(.pdr) - *(.reginfo) - } - - /* These mark the ABI of the kernel for debuggers. */ - .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) } - .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) } - - /* This is the MIPS specific mdebug section. */ - .mdebug : { *(.mdebug) } - - STABS_DEBUG - - DWARF_DEBUG - - /* These must appear regardless of . */ - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - .note : { *(.note) } + PERCPU(_PAGE_SIZE) + . = ALIGN(_PAGE_SIZE); + __init_end = .; + /* freed after init ends here */ + + __bss_start = .; /* BSS */ + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + __bss_stop = .; + + _end = . ; + + /* Sections to be discarded */ + /DISCARD/ : { + *(.exitcall.exit) + + /* ABI crap starts here */ + *(.MIPS.options) + *(.options) + *(.pdr) + *(.reginfo) + } + + /* These mark the ABI of the kernel for debuggers. */ + .mdebug.abi32 : { + KEEP(*(.mdebug.abi32)) + } + .mdebug.abi64 : { + KEEP(*(.mdebug.abi64)) + } + + /* This is the MIPS specific mdebug section. */ + .mdebug : { + *(.mdebug) + } + + STABS_DEBUG + DWARF_DEBUG + + /* These must appear regardless of . */ + .gptab.sdata : { + *(.gptab.data) + *(.gptab.sdata) + } + .gptab.sbss : { + *(.gptab.bss) + *(.gptab.sbss) + } + .note : { + *(.note) + } } diff -puN /dev/null arch/mips/lasat/Kconfig --- /dev/null +++ a/arch/mips/lasat/Kconfig @@ -0,0 +1,15 @@ +config PICVUE + tristate "PICVUE LCD display driver" + depends on LASAT + +config PICVUE_PROC + tristate "PICVUE LCD display driver /proc interface" + depends on PICVUE + +config DS1603 + bool "DS1603 RTC driver" + depends on LASAT + +config LASAT_SYSCTL + bool "LASAT sysctl interface" + depends on LASAT diff -puN /dev/null arch/mips/lasat/Makefile --- /dev/null +++ a/arch/mips/lasat/Makefile @@ -0,0 +1,16 @@ +# +# Makefile for the LASAT specific kernel interface routines under Linux. +# + +obj-y += reset.o setup.o prom.o lasat_board.o \ + at93c.o interrupt.o serial.o + +obj-$(CONFIG_LASAT_SYSCTL) += sysctl.o +obj-$(CONFIG_DS1603) += ds1603.o +obj-$(CONFIG_PICVUE) += picvue.o +obj-$(CONFIG_PICVUE_PROC) += picvue_proc.o + +clean: + make -C image clean + +EXTRA_CFLAGS += -Werror diff -puN /dev/null arch/mips/lasat/at93c.c --- /dev/null +++ a/arch/mips/lasat/at93c.c @@ -0,0 +1,149 @@ +/* + * Atmel AT93C46 serial eeprom driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include + +#include "at93c.h" + +#define AT93C_ADDR_SHIFT 7 +#define AT93C_ADDR_MAX ((1 << AT93C_ADDR_SHIFT) - 1) +#define AT93C_RCMD (0x6 << AT93C_ADDR_SHIFT) +#define AT93C_WCMD (0x5 << AT93C_ADDR_SHIFT) +#define AT93C_WENCMD 0x260 +#define AT93C_WDSCMD 0x200 + +struct at93c_defs *at93c; + +static void at93c_reg_write(u32 val) +{ + *at93c->reg = val; +} + +static u32 at93c_reg_read(void) +{ + u32 tmp = *at93c->reg; + return tmp; +} + +static u32 at93c_datareg_read(void) +{ + u32 tmp = *at93c->rdata_reg; + return tmp; +} + +static void at93c_cycle_clk(u32 data) +{ + at93c_reg_write(data | at93c->clk); + lasat_ndelay(250); + at93c_reg_write(data & ~at93c->clk); + lasat_ndelay(250); +} + +static void at93c_write_databit(u8 bit) +{ + u32 data = at93c_reg_read(); + if (bit) + data |= 1 << at93c->wdata_shift; + else + data &= ~(1 << at93c->wdata_shift); + + at93c_reg_write(data); + lasat_ndelay(100); + at93c_cycle_clk(data); +} + +static unsigned int at93c_read_databit(void) +{ + u32 data; + + at93c_cycle_clk(at93c_reg_read()); + data = (at93c_datareg_read() >> at93c->rdata_shift) & 1; + return data; +} + +static u8 at93c_read_byte(void) +{ + int i; + u8 data = 0; + + for (i = 0; i <= 7; i++) { + data <<= 1; + data |= at93c_read_databit(); + } + return data; +} + +static void at93c_write_bits(u32 data, int size) +{ + int i; + int shift = size - 1; + u32 mask = (1 << shift); + + for (i = 0; i < size; i++) { + at93c_write_databit((data & mask) >> shift); + data <<= 1; + } +} + +static void at93c_init_op(void) +{ + at93c_reg_write((at93c_reg_read() | at93c->cs) & + ~at93c->clk & ~(1 << at93c->rdata_shift)); + lasat_ndelay(50); +} + +static void at93c_end_op(void) +{ + at93c_reg_write(at93c_reg_read() & ~at93c->cs); + lasat_ndelay(250); +} + +static void at93c_wait(void) +{ + at93c_init_op(); + while (!at93c_read_databit()) + ; + at93c_end_op(); +}; + +static void at93c_disable_wp(void) +{ + at93c_init_op(); + at93c_write_bits(AT93C_WENCMD, 10); + at93c_end_op(); +} + +static void at93c_enable_wp(void) +{ + at93c_init_op(); + at93c_write_bits(AT93C_WDSCMD, 10); + at93c_end_op(); +} + +u8 at93c_read(u8 addr) +{ + u8 byte; + at93c_init_op(); + at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_RCMD, 10); + byte = at93c_read_byte(); + at93c_end_op(); + return byte; +} + +void at93c_write(u8 addr, u8 data) +{ + at93c_disable_wp(); + at93c_init_op(); + at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_WCMD, 10); + at93c_write_bits(data, 8); + at93c_end_op(); + at93c_wait(); + at93c_enable_wp(); +} diff -puN /dev/null arch/mips/lasat/at93c.h --- /dev/null +++ a/arch/mips/lasat/at93c.h @@ -0,0 +1,18 @@ +/* + * Atmel AT93C46 serial eeprom driver + * + * Brian Murphy + * + */ + +extern struct at93c_defs { + volatile u32 *reg; + volatile u32 *rdata_reg; + int rdata_shift; + int wdata_shift; + u32 cs; + u32 clk; +} *at93c; + +u8 at93c_read(u8 addr); +void at93c_write(u8 addr, u8 data); diff -puN /dev/null arch/mips/lasat/ds1603.c --- /dev/null +++ a/arch/mips/lasat/ds1603.c @@ -0,0 +1,183 @@ +/* + * Dallas Semiconductors 1603 RTC driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include + +#include "ds1603.h" + +#define READ_TIME_CMD 0x81 +#define SET_TIME_CMD 0x80 +#define TRIMMER_SET_CMD 0xC0 +#define TRIMMER_VALUE_MASK 0x38 +#define TRIMMER_SHIFT 3 + +struct ds_defs *ds1603; + +/* HW specific register functions */ +static void rtc_reg_write(unsigned long val) +{ + *ds1603->reg = val; +} + +static unsigned long rtc_reg_read(void) +{ + unsigned long tmp = *ds1603->reg; + return tmp; +} + +static unsigned long rtc_datareg_read(void) +{ + unsigned long tmp = *ds1603->data_reg; + return tmp; +} + +static void rtc_nrst_high(void) +{ + rtc_reg_write(rtc_reg_read() | ds1603->rst); +} + +static void rtc_nrst_low(void) +{ + rtc_reg_write(rtc_reg_read() & ~ds1603->rst); +} + +static void rtc_cycle_clock(unsigned long data) +{ + data |= ds1603->clk; + rtc_reg_write(data); + lasat_ndelay(250); + if (ds1603->data_reversed) + data &= ~ds1603->data; + else + data |= ds1603->data; + data &= ~ds1603->clk; + rtc_reg_write(data); + lasat_ndelay(250 + ds1603->huge_delay); +} + +static void rtc_write_databit(unsigned int bit) +{ + unsigned long data = rtc_reg_read(); + if (ds1603->data_reversed) + bit = !bit; + if (bit) + data |= ds1603->data; + else + data &= ~ds1603->data; + + rtc_reg_write(data); + lasat_ndelay(50 + ds1603->huge_delay); + rtc_cycle_clock(data); +} + +static unsigned int rtc_read_databit(void) +{ + unsigned int data; + + data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) + >> ds1603->data_read_shift; + rtc_cycle_clock(rtc_reg_read()); + return data; +} + +static void rtc_write_byte(unsigned int byte) +{ + int i; + + for (i = 0; i <= 7; i++) { + rtc_write_databit(byte & 1L); + byte >>= 1; + } +} + +static void rtc_write_word(unsigned long word) +{ + int i; + + for (i = 0; i <= 31; i++) { + rtc_write_databit(word & 1L); + word >>= 1; + } +} + +static unsigned long rtc_read_word(void) +{ + int i; + unsigned long word = 0; + unsigned long shift = 0; + + for (i = 0; i <= 31; i++) { + word |= rtc_read_databit() << shift; + shift++; + } + return word; +} + +static void rtc_init_op(void) +{ + rtc_nrst_high(); + + rtc_reg_write(rtc_reg_read() & ~ds1603->clk); + + lasat_ndelay(50); +} + +static void rtc_end_op(void) +{ + rtc_nrst_low(); + lasat_ndelay(1000); +} + +/* interface */ +unsigned long ds1603_read(void) +{ + unsigned long word; + unsigned long flags; + + spin_lock_irqsave(&rtc_lock, flags); + rtc_init_op(); + rtc_write_byte(READ_TIME_CMD); + word = rtc_read_word(); + rtc_end_op(); + spin_unlock_irqrestore(&rtc_lock, flags); + return word; +} + +int ds1603_set(unsigned long time) +{ + unsigned long flags; + + spin_lock_irqsave(&rtc_lock, flags); + rtc_init_op(); + rtc_write_byte(SET_TIME_CMD); + rtc_write_word(time); + rtc_end_op(); + spin_unlock_irqrestore(&rtc_lock, flags); + + return 0; +} + +void ds1603_set_trimmer(unsigned int trimval) +{ + rtc_init_op(); + rtc_write_byte(((trimval << TRIMMER_SHIFT) & TRIMMER_VALUE_MASK) + | (TRIMMER_SET_CMD)); + rtc_end_op(); +} + +void ds1603_disable(void) +{ + ds1603_set_trimmer(TRIMMER_DISABLE_RTC); +} + +void ds1603_enable(void) +{ + ds1603_set_trimmer(TRIMMER_DEFAULT); +} diff -puN /dev/null arch/mips/lasat/ds1603.h --- /dev/null +++ a/arch/mips/lasat/ds1603.h @@ -0,0 +1,33 @@ +/* + * Dallas Semiconductors 1603 RTC driver + * + * Brian Murphy + * + */ +#ifndef __DS1603_H +#define __DS1603_H + +struct ds_defs { + volatile u32 *reg; + volatile u32 *data_reg; + u32 rst; + u32 clk; + u32 data; + u32 data_read_shift; + char data_reversed; + u32 huge_delay; +}; + +extern struct ds_defs *ds1603; + +unsigned long ds1603_read(void); +int ds1603_set(unsigned long); +void ds1603_set_trimmer(unsigned int); +void ds1603_enable(void); +void ds1603_disable(void); +void ds1603_init(struct ds_defs *); + +#define TRIMMER_DEFAULT 3 +#define TRIMMER_DISABLE_RTC 0 + +#endif diff -puN /dev/null arch/mips/lasat/image/Makefile --- /dev/null +++ a/arch/mips/lasat/image/Makefile @@ -0,0 +1,54 @@ +# +# MAKEFILE FOR THE MIPS LINUX BOOTLOADER AND ROM DEBUGGER +# +# i-data Networks +# +# Author: Thomas Horsten +# + +ifndef Version + Version = "$(USER)-test" +endif + +MKLASATIMG = mklasatimg +MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200 +KERNEL_IMAGE = $(TOPDIR)/vmlinux +KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ ) +KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ ) + +LDSCRIPT= -L$(obj) -Tromscript.normal + +HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ + -D_kernel_entry=0x$(KERNEL_ENTRY) \ + -D VERSION="\"$(Version)\"" \ + -D TIMESTAMP=$(shell date +%s) + +$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) + $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< + +OBJECTS = head.o kImage.o + +rom.sw: $(obj)/rom.sw +rom.bin: $(obj)/rom.bin + +$(obj)/rom.sw: $(obj)/rom.bin + $(MKLASATIMG) -o $@ -k $^ -m $(MKLASATIMG_ARCH) + +$(obj)/rom.bin: $(obj)/rom + $(OBJCOPY) -O binary -S $^ $@ + +# Rule to make the bootloader +$(obj)/rom: $(addprefix $(obj)/,$(OBJECTS)) + $(LD) $(LDFLAGS) $(LDSCRIPT) -o $@ $^ + +$(obj)/%.o: $(obj)/%.gz + $(LD) -r -o $@ -b binary $< + +$(obj)/%.gz: $(obj)/%.bin + gzip -cf -9 $< > $@ + +$(obj)/kImage.bin: $(KERNEL_IMAGE) + $(OBJCOPY) -O binary -S $^ $@ + +clean: + rm -f rom rom.bin rom.sw kImage.bin kImage.o diff -puN /dev/null arch/mips/lasat/image/head.S --- /dev/null +++ a/arch/mips/lasat/image/head.S @@ -0,0 +1,31 @@ +#include + + .text + .section .text.start, "ax" + .set noreorder + .set mips3 + + /* Magic words identifying a software image */ + .word LASAT_K_MAGIC0_VAL + .word LASAT_K_MAGIC1_VAL + + /* Image header version */ + .word 0x00000002 + + /* image start and size */ + .word _image_start + .word _image_size + + /* start of kernel and entrypoint in uncompressed image */ + .word _kernel_start + .word _kernel_entry + + /* Here we have room for future flags */ + + .org 0x40 +reldate: + .word TIMESTAMP + + .org 0x50 +release: + .string VERSION diff -puN /dev/null arch/mips/lasat/image/romscript.normal --- /dev/null +++ a/arch/mips/lasat/image/romscript.normal @@ -0,0 +1,23 @@ +OUTPUT_ARCH(mips) + +SECTIONS +{ + .text : + { + *(.text.start) + } + + /* Data in ROM */ + + .data ALIGN(0x10) : + { + *(.data) + } + _image_start = ADDR(.data); + _image_size = SIZEOF(.data); + + .other : + { + *(.*) + } +} diff -puN /dev/null arch/mips/lasat/interrupt.c --- /dev/null +++ a/arch/mips/lasat/interrupt.c @@ -0,0 +1,130 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the + * Lasat boards. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static volatile int *lasat_int_status; +static volatile int *lasat_int_mask; +static volatile int lasat_int_mask_shift; + +void disable_lasat_irq(unsigned int irq_nr) +{ + *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; +} + +void enable_lasat_irq(unsigned int irq_nr) +{ + *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; +} + +static struct irq_chip lasat_irq_type = { + .name = "Lasat", + .ack = disable_lasat_irq, + .mask = disable_lasat_irq, + .mask_ack = disable_lasat_irq, + .unmask = enable_lasat_irq, +}; + +static inline int ls1bit32(unsigned int x) +{ + int b = 31, s; + + s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; + s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; + s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; + s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; + s = 1; if (x << 1 == 0) s = 0; b -= s; + + return b; +} + +static unsigned long (*get_int_status)(void); + +static unsigned long get_int_status_100(void) +{ + return *lasat_int_status & *lasat_int_mask; +} + +static unsigned long get_int_status_200(void) +{ + unsigned long int_status; + + int_status = *lasat_int_status; + int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff; + return int_status; +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long int_status; + unsigned int cause = read_c0_cause(); + int irq; + + if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */ + ll_timer_interrupt(7); + return; + } + + int_status = get_int_status(); + + /* if int_status == 0, then the interrupt has already been cleared */ + if (int_status) { + irq = ls1bit32(int_status); + + do_IRQ(irq); + } +} + +void __init arch_init_irq(void) +{ + int i; + + switch (mips_machtype) { + case MACH_LASAT_100: + lasat_int_status = (void *)LASAT_INT_STATUS_REG_100; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_100; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_100; + get_int_status = get_int_status_100; + *lasat_int_mask = 0; + break; + case MACH_LASAT_200: + lasat_int_status = (void *)LASAT_INT_STATUS_REG_200; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_200; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_200; + get_int_status = get_int_status_200; + *lasat_int_mask &= 0xffff; + break; + default: + panic("arch_init_irq: mips_machtype incorrect"); + } + + for (i = 0; i <= LASATINT_END; i++) + set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); +} diff -puN /dev/null arch/mips/lasat/lasat_board.c --- /dev/null +++ a/arch/mips/lasat/lasat_board.c @@ -0,0 +1,280 @@ +/* + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines specific to the LASAT boards + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "at93c.h" +/* New model description table */ +#include "lasat_models.h" + +#define EEPROM_CRC(data, len) (~crc32(~0, data, len)) + +struct lasat_info lasat_board_info; + +void update_bcastaddr(void); + +int EEPROMRead(unsigned int pos, unsigned char *data, int len) +{ + int i; + + for (i = 0; i < len; i++) + *data++ = at93c_read(pos++); + + return 0; +} + +int EEPROMWrite(unsigned int pos, unsigned char *data, int len) +{ + int i; + + for (i = 0; i < len; i++) + at93c_write(pos++, *data++); + + return 0; +} + +static void init_flash_sizes(void) +{ + unsigned long *lb = lasat_board_info.li_flashpart_base; + unsigned long *ls = lasat_board_info.li_flashpart_size; + int i; + + ls[LASAT_MTD_BOOTLOADER] = 0x40000; + ls[LASAT_MTD_SERVICE] = 0xC0000; + ls[LASAT_MTD_NORMAL] = 0x100000; + + if (mips_machtype == MACH_LASAT_100) { + lasat_board_info.li_flash_base = 0x1e000000; + + lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; + + if (lasat_board_info.li_flash_size > 0x200000) { + ls[LASAT_MTD_CONFIG] = 0x100000; + ls[LASAT_MTD_FS] = 0x500000; + } + } else { + lasat_board_info.li_flash_base = 0x10000000; + + if (lasat_board_info.li_flash_size < 0x1000000) { + lb[LASAT_MTD_BOOTLOADER] = 0x10000000; + ls[LASAT_MTD_CONFIG] = 0x100000; + if (lasat_board_info.li_flash_size >= 0x400000) + ls[LASAT_MTD_FS] = + lasat_board_info.li_flash_size - 0x300000; + } + } + + for (i = 1; i < LASAT_MTD_LAST; i++) + lb[i] = lb[i-1] + ls[i-1]; +} + +int lasat_init_board_info(void) +{ + int c; + unsigned long crc; + unsigned long cfg0, cfg1; + const struct product_info *ppi; + int i_n_base_models = N_BASE_MODELS; + const char * const * i_txt_base_models = txt_base_models; + int i_n_prids = N_PRIDS; + + memset(&lasat_board_info, 0, sizeof(lasat_board_info)); + + /* First read the EEPROM info */ + EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + sizeof(struct lasat_eeprom_struct)); + + /* Check the CRC */ + crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info), + sizeof(struct lasat_eeprom_struct) - 4); + + if (crc != lasat_board_info.li_eeprom_info.crc32) { + printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM CRC does " + "not match calculated, attempting to soldier on...\n"); + } + + if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) { + printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM version " + "%d, wanted version %d, attempting to soldier on...\n", + (unsigned int)lasat_board_info.li_eeprom_info.version, + LASAT_EEPROM_VERSION); + } + + cfg0 = lasat_board_info.li_eeprom_info.cfg[0]; + cfg1 = lasat_board_info.li_eeprom_info.cfg[1]; + + if (LASAT_W0_DSCTYPE(cfg0) != 1) { + printk(KERN_WARNING "WARNING...\nWARNING...\n" + "Invalid configuration read from EEPROM, attempting to " + "soldier on..."); + } + /* We have a valid configuration */ + + switch (LASAT_W0_SDRAMBANKSZ(cfg0)) { + case 0: + lasat_board_info.li_memsize = 0x0800000; + break; + case 1: + lasat_board_info.li_memsize = 0x1000000; + break; + case 2: + lasat_board_info.li_memsize = 0x2000000; + break; + case 3: + lasat_board_info.li_memsize = 0x4000000; + break; + case 4: + lasat_board_info.li_memsize = 0x8000000; + break; + default: + lasat_board_info.li_memsize = 0; + } + + switch (LASAT_W0_SDRAMBANKS(cfg0)) { + case 0: + break; + case 1: + lasat_board_info.li_memsize *= 2; + break; + default: + break; + } + + switch (LASAT_W0_BUSSPEED(cfg0)) { + case 0x0: + lasat_board_info.li_bus_hz = 60000000; + break; + case 0x1: + lasat_board_info.li_bus_hz = 66000000; + break; + case 0x2: + lasat_board_info.li_bus_hz = 66666667; + break; + case 0x3: + lasat_board_info.li_bus_hz = 80000000; + break; + case 0x4: + lasat_board_info.li_bus_hz = 83333333; + break; + case 0x5: + lasat_board_info.li_bus_hz = 100000000; + break; + } + + switch (LASAT_W0_CPUCLK(cfg0)) { + case 0x0: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz; + break; + case 0x1: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + (lasat_board_info.li_bus_hz >> 1); + break; + case 0x2: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz; + break; + case 0x3: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz + + (lasat_board_info.li_bus_hz >> 1); + break; + case 0x4: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz; + break; + } + + /* Flash size */ + switch (LASAT_W1_FLASHSIZE(cfg1)) { + case 0: + lasat_board_info.li_flash_size = 0x200000; + break; + case 1: + lasat_board_info.li_flash_size = 0x400000; + break; + case 2: + lasat_board_info.li_flash_size = 0x800000; + break; + case 3: + lasat_board_info.li_flash_size = 0x1000000; + break; + case 4: + lasat_board_info.li_flash_size = 0x2000000; + break; + } + + init_flash_sizes(); + + lasat_board_info.li_bmid = LASAT_W0_BMID(cfg0); + lasat_board_info.li_prid = lasat_board_info.li_eeprom_info.prid; + if (lasat_board_info.li_prid == 0xffff || lasat_board_info.li_prid == 0) + lasat_board_info.li_prid = lasat_board_info.li_bmid; + + /* Base model stuff */ + if (lasat_board_info.li_bmid > i_n_base_models) + lasat_board_info.li_bmid = i_n_base_models; + strcpy(lasat_board_info.li_bmstr, + i_txt_base_models[lasat_board_info.li_bmid]); + + /* Product ID dependent values */ + c = lasat_board_info.li_prid; + if (c >= i_n_prids) { + strcpy(lasat_board_info.li_namestr, "Unknown Model"); + strcpy(lasat_board_info.li_typestr, "Unknown Type"); + } else { + ppi = &vendor_info_table[0].vi_product_info[c]; + strcpy(lasat_board_info.li_namestr, ppi->pi_name); + if (ppi->pi_type) + strcpy(lasat_board_info.li_typestr, ppi->pi_type); + else + sprintf(lasat_board_info.li_typestr, "%d", 10 * c); + } + +#if defined(CONFIG_INET) && defined(CONFIG_SYSCTL) + update_bcastaddr(); +#endif + + return 0; +} + +void lasat_write_eeprom_info(void) +{ + unsigned long crc; + + /* Generate the CRC */ + crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info), + sizeof(struct lasat_eeprom_struct) - 4); + lasat_board_info.li_eeprom_info.crc32 = crc; + + /* Write the EEPROM info */ + EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + sizeof(struct lasat_eeprom_struct)); +} diff -puN /dev/null arch/mips/lasat/lasat_models.h --- /dev/null +++ a/arch/mips/lasat/lasat_models.h @@ -0,0 +1,67 @@ +/* + * Model description tables + */ +#include + +struct product_info { + const char *pi_name; + const char *pi_type; +}; + +struct vendor_info { + const char *vi_name; + const struct product_info *vi_product_info; +}; + +/* + * Base models + */ +static const char * const txt_base_models[] = { + "MQ 2", "MQ Pro", "SP 25", "SP 50", "SP 100", "SP 5000", "SP 7000", + "SP 1000", "Unknown" +}; +#define N_BASE_MODELS (ARRAY_SIZE(txt_base_models) - 1) + +/* + * Eicon Networks + */ +static const char txt_en_mq[] = "Masquerade"; +static const char txt_en_sp[] = "Safepipe"; + +static const struct product_info product_info_eicon[] = { + { txt_en_mq, "II" }, /* 0 */ + { txt_en_mq, "Pro" }, /* 1 */ + { txt_en_sp, "25" }, /* 2 */ + { txt_en_sp, "50" }, /* 3 */ + { txt_en_sp, "100" }, /* 4 */ + { txt_en_sp, "5000" }, /* 5 */ + { txt_en_sp, "7000" }, /* 6 */ + { txt_en_sp, "30" }, /* 7 */ + { txt_en_sp, "5100" }, /* 8 */ + { txt_en_sp, "7100" }, /* 9 */ + { txt_en_sp, "1110" }, /* 10 */ + { txt_en_sp, "3020" }, /* 11 */ + { txt_en_sp, "3030" }, /* 12 */ + { txt_en_sp, "5020" }, /* 13 */ + { txt_en_sp, "5030" }, /* 14 */ + { txt_en_sp, "1120" }, /* 15 */ + { txt_en_sp, "1130" }, /* 16 */ + { txt_en_sp, "6010" }, /* 17 */ + { txt_en_sp, "6110" }, /* 18 */ + { txt_en_sp, "6210" }, /* 19 */ + { txt_en_sp, "1020" }, /* 20 */ + { txt_en_sp, "1040" }, /* 21 */ + { txt_en_sp, "1050" }, /* 22 */ + { txt_en_sp, "1060" }, /* 23 */ +}; + +#define N_PRIDS ARRAY_SIZE(product_info_eicon) + +/* + * The vendor table + */ +static struct vendor_info const vendor_info_table[] = { + { "Eicon Networks", product_info_eicon }, +}; + +#define N_VENDORS ARRAY_SIZE(vendor_info_table) diff -puN /dev/null arch/mips/lasat/picvue.c --- /dev/null +++ a/arch/mips/lasat/picvue.c @@ -0,0 +1,244 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "picvue.h" + +#define PVC_BUSY 0x80 +#define PVC_NLINES 2 +#define PVC_DISPMEM 80 +#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES + +struct pvc_defs *picvue; + +DECLARE_MUTEX(pvc_sem); + +static void pvc_reg_write(u32 val) +{ + *picvue->reg = val; +} + +static u32 pvc_reg_read(void) +{ + u32 tmp = *picvue->reg; + return tmp; +} + +static void pvc_write_byte(u32 data, u8 byte) +{ + data |= picvue->e; + pvc_reg_write(data); + data &= ~picvue->data_mask; + data |= byte << picvue->data_shift; + pvc_reg_write(data); + ndelay(220); + pvc_reg_write(data & ~picvue->e); + ndelay(220); +} + +static u8 pvc_read_byte(u32 data) +{ + u8 byte; + + data |= picvue->e; + pvc_reg_write(data); + ndelay(220); + byte = (pvc_reg_read() & picvue->data_mask) >> picvue->data_shift; + data &= ~picvue->e; + pvc_reg_write(data); + ndelay(220); + return byte; +} + +static u8 pvc_read_data(void) +{ + u32 data = pvc_reg_read(); + u8 byte; + data |= picvue->rw; + data &= ~picvue->rs; + pvc_reg_write(data); + ndelay(40); + byte = pvc_read_byte(data); + data |= picvue->rs; + pvc_reg_write(data); + return byte; +} + +#define TIMEOUT 1000 +static int pvc_wait(void) +{ + int i = TIMEOUT; + int err = 0; + + while ((pvc_read_data() & PVC_BUSY) && i) + i--; + if (i == 0) + err = -ETIME; + + return err; +} + +#define MODE_INST 0 +#define MODE_DATA 1 +static void pvc_write(u8 byte, int mode) +{ + u32 data = pvc_reg_read(); + data &= ~picvue->rw; + if (mode == MODE_DATA) + data |= picvue->rs; + else + data &= ~picvue->rs; + pvc_reg_write(data); + ndelay(40); + pvc_write_byte(data, byte); + if (mode == MODE_DATA) + data &= ~picvue->rs; + else + data |= picvue->rs; + pvc_reg_write(data); + pvc_wait(); +} + +void pvc_write_string(const unsigned char *str, u8 addr, int line) +{ + int i = 0; + + if (line > 0 && (PVC_NLINES > 1)) + addr += 0x40 * line; + pvc_write(0x80 | addr, MODE_INST); + + while (*str != 0 && i < PVC_LINELEN) { + pvc_write(*str++, MODE_DATA); + i++; + } +} + +void pvc_write_string_centered(const unsigned char *str, int line) +{ + int len = strlen(str); + u8 addr; + + if (len > PVC_VISIBLE_CHARS) + addr = 0; + else + addr = (PVC_VISIBLE_CHARS - strlen(str))/2; + + pvc_write_string(str, addr, line); +} + +void pvc_dump_string(const unsigned char *str) +{ + int len = strlen(str); + + pvc_write_string(str, 0, 0); + if (len > PVC_VISIBLE_CHARS) + pvc_write_string(&str[PVC_VISIBLE_CHARS], 0, 1); +} + +#define BM_SIZE 8 +#define MAX_PROGRAMMABLE_CHARS 8 +int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]) +{ + int i; + int addr; + + if (charnum > MAX_PROGRAMMABLE_CHARS) + return -ENOENT; + + addr = charnum * 8; + pvc_write(0x40 | addr, MODE_INST); + + for (i = 0; i < BM_SIZE; i++) + pvc_write(bitmap[i], MODE_DATA); + return 0; +} + +#define FUNC_SET_CMD 0x20 +#define EIGHT_BYTE (1 << 4) +#define FOUR_BYTE 0 +#define TWO_LINES (1 << 3) +#define ONE_LINE 0 +#define LARGE_FONT (1 << 2) +#define SMALL_FONT 0 + +static void pvc_funcset(u8 cmd) +{ + pvc_write(FUNC_SET_CMD | (cmd & (EIGHT_BYTE|TWO_LINES|LARGE_FONT)), + MODE_INST); +} + +#define ENTRYMODE_CMD 0x4 +#define AUTO_INC (1 << 1) +#define AUTO_DEC 0 +#define CURSOR_FOLLOWS_DISP (1 << 0) + +static void pvc_entrymode(u8 cmd) +{ + pvc_write(ENTRYMODE_CMD | (cmd & (AUTO_INC|CURSOR_FOLLOWS_DISP)), + MODE_INST); +} + +#define DISP_CNT_CMD 0x08 +#define DISP_OFF 0 +#define DISP_ON (1 << 2) +#define CUR_ON (1 << 1) +#define CUR_BLINK (1 << 0) +void pvc_dispcnt(u8 cmd) +{ + pvc_write(DISP_CNT_CMD | (cmd & (DISP_ON|CUR_ON|CUR_BLINK)), MODE_INST); +} + +#define MOVE_CMD 0x10 +#define DISPLAY (1 << 3) +#define CURSOR 0 +#define RIGHT (1 << 2) +#define LEFT 0 +void pvc_move(u8 cmd) +{ + pvc_write(MOVE_CMD | (cmd & (DISPLAY|RIGHT)), MODE_INST); +} + +#define CLEAR_CMD 0x1 +void pvc_clear(void) +{ + pvc_write(CLEAR_CMD, MODE_INST); +} + +#define HOME_CMD 0x2 +void pvc_home(void) +{ + pvc_write(HOME_CMD, MODE_INST); +} + +int pvc_init(void) +{ + u8 cmd = EIGHT_BYTE; + + if (PVC_NLINES == 2) + cmd |= (SMALL_FONT|TWO_LINES); + else + cmd |= (LARGE_FONT|ONE_LINE); + pvc_funcset(cmd); + pvc_dispcnt(DISP_ON); + pvc_entrymode(AUTO_INC); + + pvc_clear(); + pvc_write_string_centered("Display", 0); + pvc_write_string_centered("Initialized", 1); + + return 0; +} + +module_init(pvc_init); +MODULE_LICENSE("GPL"); diff -puN /dev/null arch/mips/lasat/picvue.h --- /dev/null +++ a/arch/mips/lasat/picvue.h @@ -0,0 +1,48 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include + +struct pvc_defs { + volatile u32 *reg; + u32 data_shift; + u32 data_mask; + u32 e; + u32 rw; + u32 rs; +}; + +extern struct pvc_defs *picvue; + +#define PVC_NLINES 2 +#define PVC_DISPMEM 80 +#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES +#define PVC_VISIBLE_CHARS 16 + +void pvc_write_string(const unsigned char *str, u8 addr, int line); +void pvc_write_string_centered(const unsigned char *str, int line); +void pvc_dump_string(const unsigned char *str); + +#define BM_SIZE 8 +#define MAX_PROGRAMMABLE_CHARS 8 +int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]); + +void pvc_dispcnt(u8 cmd); +#define DISP_OFF 0 +#define DISP_ON (1 << 2) +#define CUR_ON (1 << 1) +#define CUR_BLINK (1 << 0) + +void pvc_move(u8 cmd); +#define DISPLAY (1 << 3) +#define CURSOR 0 +#define RIGHT (1 << 2) +#define LEFT 0 + +void pvc_clear(void); +void pvc_home(void); + +extern struct semaphore pvc_sem; diff -puN /dev/null arch/mips/lasat/picvue_proc.c --- /dev/null +++ a/arch/mips/lasat/picvue_proc.c @@ -0,0 +1,191 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include + +#include +#include + +#include + +#include "picvue.h" + +static char pvc_lines[PVC_NLINES][PVC_LINELEN+1]; +static int pvc_linedata[PVC_NLINES]; +static struct proc_dir_entry *pvc_display_dir; +static char *pvc_linename[PVC_NLINES] = {"line1", "line2"}; +#define DISPLAY_DIR_NAME "display" +static int scroll_dir, scroll_interval; + +static struct timer_list timer; + +static void pvc_display(unsigned long data) +{ + int i; + + pvc_clear(); + for (i = 0; i < PVC_NLINES; i++) + pvc_write_string(pvc_lines[i], 0, i); +} + +static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0); + +static int pvc_proc_read_line(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + char *origpage = page; + int lineno = *(int *)data; + + if (lineno < 0 || lineno > PVC_NLINES) { + printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno); + return 0; + } + + down(&pvc_sem); + page += sprintf(page, "%s\n", pvc_lines[lineno]); + up(&pvc_sem); + + return page - origpage; +} + +static int pvc_proc_write_line(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int origcount = count; + int lineno = *(int *)data; + + if (lineno < 0 || lineno > PVC_NLINES) { + printk(KERN_WARNING "proc_write_line: invalid lineno %d\n", + lineno); + return origcount; + } + + if (count > PVC_LINELEN) + count = PVC_LINELEN; + + if (buffer[count-1] == '\n') + count--; + + down(&pvc_sem); + strncpy(pvc_lines[lineno], buffer, count); + pvc_lines[lineno][count] = '\0'; + up(&pvc_sem); + + tasklet_schedule(&pvc_display_tasklet); + + return origcount; +} + +static int pvc_proc_write_scroll(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int origcount = count; + int cmd = simple_strtol(buffer, NULL, 10); + + down(&pvc_sem); + if (scroll_interval != 0) + del_timer(&timer); + + if (cmd == 0) { + scroll_dir = 0; + scroll_interval = 0; + } else { + if (cmd < 0) { + scroll_dir = -1; + scroll_interval = -cmd; + } else { + scroll_dir = 1; + scroll_interval = cmd; + } + add_timer(&timer); + } + up(&pvc_sem); + + return origcount; +} + +static int pvc_proc_read_scroll(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + char *origpage = page; + + down(&pvc_sem); + page += sprintf(page, "%d\n", scroll_dir * scroll_interval); + up(&pvc_sem); + + return page - origpage; +} + + +void pvc_proc_timerfunc(unsigned long data) +{ + if (scroll_dir < 0) + pvc_move(DISPLAY|RIGHT); + else if (scroll_dir > 0) + pvc_move(DISPLAY|LEFT); + + timer.expires = jiffies + scroll_interval; + add_timer(&timer); +} + +static void pvc_proc_cleanup(void) +{ + int i; + for (i = 0; i < PVC_NLINES; i++) + remove_proc_entry(pvc_linename[i], pvc_display_dir); + remove_proc_entry("scroll", pvc_display_dir); + remove_proc_entry(DISPLAY_DIR_NAME, NULL); + + del_timer(&timer); +} + +static int __init pvc_proc_init(void) +{ + struct proc_dir_entry *proc_entry; + int i; + + pvc_display_dir = proc_mkdir(DISPLAY_DIR_NAME, NULL); + if (pvc_display_dir == NULL) + goto error; + + for (i = 0; i < PVC_NLINES; i++) { + strcpy(pvc_lines[i], ""); + pvc_linedata[i] = i; + } + for (i = 0; i < PVC_NLINES; i++) { + proc_entry = create_proc_entry(pvc_linename[i], 0644, + pvc_display_dir); + if (proc_entry == NULL) + goto error; + + proc_entry->read_proc = pvc_proc_read_line; + proc_entry->write_proc = pvc_proc_write_line; + proc_entry->data = &pvc_linedata[i]; + } + proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir); + if (proc_entry == NULL) + goto error; + + proc_entry->write_proc = pvc_proc_write_scroll; + proc_entry->read_proc = pvc_proc_read_scroll; + + init_timer(&timer); + timer.function = pvc_proc_timerfunc; + + return 0; +error: + pvc_proc_cleanup(); + return -ENOMEM; +} + +module_init(pvc_proc_init); +module_exit(pvc_proc_cleanup); +MODULE_LICENSE("GPL"); diff -puN /dev/null arch/mips/lasat/prom.c --- /dev/null +++ a/arch/mips/lasat/prom.c @@ -0,0 +1,128 @@ +/* + * PROM interface routines. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "at93c.h" +#include +#include "prom.h" + +#define RESET_VECTOR 0xbfc00000 +#define PROM_JUMP_TABLE_ENTRY(n) (*((u32 *)(RESET_VECTOR + 0x20) + n)) +#define PROM_DISPLAY_ADDR PROM_JUMP_TABLE_ENTRY(0) +#define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1) +#define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2) + +static void null_prom_display(const char *string, int pos, int clear) +{ +} + +static void null_prom_monitor(void) +{ +} + +static void null_prom_putc(char c) +{ +} + +/* these are functions provided by the bootloader */ +static void (*__prom_putc)(char c) = null_prom_putc; + +void prom_putchar(char c) +{ + __prom_putc(c); +} + +void (*prom_display)(const char *string, int pos, int clear) = + null_prom_display; +void (*prom_monitor)(void) = null_prom_monitor; + +unsigned int lasat_ndelay_divider; + +static void setup_prom_vectors(void) +{ + u32 version = *(u32 *)(RESET_VECTOR + 0x90); + + if (version >= 307) { + prom_display = (void *)PROM_DISPLAY_ADDR; + __prom_putc = (void *)PROM_PUTC_ADDR; + prom_monitor = (void *)PROM_MONITOR_ADDR; + } + printk(KERN_DEBUG "prom vectors set up\n"); +} + +static struct at93c_defs at93c_defs[N_MACHTYPES] = { + { + .reg = (void *)AT93C_REG_100, + .rdata_reg = (void *)AT93C_RDATA_REG_100, + .rdata_shift = AT93C_RDATA_SHIFT_100, + .wdata_shift = AT93C_WDATA_SHIFT_100, + .cs = AT93C_CS_M_100, + .clk = AT93C_CLK_M_100 + }, { + .reg = (void *)AT93C_REG_200, + .rdata_reg = (void *)AT93C_RDATA_REG_200, + .rdata_shift = AT93C_RDATA_SHIFT_200, + .wdata_shift = AT93C_WDATA_SHIFT_200, + .cs = AT93C_CS_M_200, + .clk = AT93C_CLK_M_200 + }, +}; + +void __init prom_init(void) +{ + int argc = fw_arg0; + char **argv = (char **) fw_arg1; + + setup_prom_vectors(); + + if (current_cpu_data.cputype == CPU_R5000) { + printk(KERN_INFO "LASAT 200 board\n"); + mips_machtype = MACH_LASAT_200; + lasat_ndelay_divider = LASAT_200_DIVIDER; + } else { + printk(KERN_INFO "LASAT 100 board\n"); + mips_machtype = MACH_LASAT_100; + lasat_ndelay_divider = LASAT_100_DIVIDER; + } + + at93c = &at93c_defs[mips_machtype]; + + lasat_init_board_info(); /* Read info from EEPROM */ + + mips_machgroup = MACH_GROUP_LASAT; + + /* Get the command line */ + if (argc > 0) { + strncpy(arcs_cmdline, argv[0], CL_SIZE-1); + arcs_cmdline[CL_SIZE-1] = '\0'; + } + + /* Set the I/O base address */ + set_io_port_base(KSEG1); + + /* Set memory regions */ + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; /* Wrong, fixme. */ + + add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return lasat_board_info.li_bmstr; +} diff -puN /dev/null arch/mips/lasat/prom.h --- /dev/null +++ a/arch/mips/lasat/prom.h @@ -0,0 +1,7 @@ +#ifndef __PROM_H +#define __PROM_H + +extern void (*prom_display)(const char *string, int pos, int clear); +extern void (*prom_monitor)(void); + +#endif /* __PROM_H */ diff -puN /dev/null arch/mips/lasat/reset.c --- /dev/null +++ a/arch/mips/lasat/reset.c @@ -0,0 +1,61 @@ +/* + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Reset the LASAT board. + */ +#include +#include + +#include +#include +#include + +#include "picvue.h" +#include "prom.h" + +static void lasat_machine_restart(char *command); +static void lasat_machine_halt(void); + +/* Used to set machine to boot in service mode via /proc interface */ +int lasat_boot_to_service; + +static void lasat_machine_restart(char *command) +{ + local_irq_disable(); + + if (lasat_boot_to_service) { + *(volatile unsigned int *)0xa0000024 = 0xdeadbeef; + *(volatile unsigned int *)0xa00000fc = 0xfedeabba; + } + *lasat_misc->reset_reg = 0xbedead; + for (;;) ; +} + +static void lasat_machine_halt(void) +{ + local_irq_disable(); + + prom_monitor(); + for (;;) ; +} + +void lasat_reboot_setup(void) +{ + _machine_restart = lasat_machine_restart; + _machine_halt = lasat_machine_halt; + pm_power_off = lasat_machine_halt; +} diff -puN /dev/null arch/mips/lasat/serial.c --- /dev/null +++ a/arch/mips/lasat/serial.c @@ -0,0 +1,94 @@ +/* + * Registration of Lasat UART platform device. + * + * Copyright (C) 2007 Brian Murphy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct resource lasat_serial_res[2] __initdata; + +static struct plat_serial8250_port lasat_serial8250_port[] = { + { + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | + UPF_SKIP_TEST, + }, + {}, +}; + +static __init int lasat_uart_add(void) +{ + struct platform_device *pdev; + int retval; + + pdev = platform_device_alloc("serial8250", -1); + if (!pdev) + return -ENOMEM; + + if (mips_machtype == MACH_LASAT_100) { + lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_100); + lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_100 * 8 - 1; + lasat_serial_res[0].flags = IORESOURCE_MEM; + lasat_serial_res[1].start = LASATINT_UART_100; + lasat_serial_res[1].end = LASATINT_UART_100; + lasat_serial_res[1].flags = IORESOURCE_IRQ; + + lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_100; + lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_100 * 16; + lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_100; + lasat_serial8250_port[0].irq = LASATINT_UART_100; + } else { + lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_200); + lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_200 * 8 - 1; + lasat_serial_res[0].flags = IORESOURCE_MEM; + lasat_serial_res[1].start = LASATINT_UART_200; + lasat_serial_res[1].end = LASATINT_UART_200; + lasat_serial_res[1].flags = IORESOURCE_IRQ; + + lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_200; + lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_200 * 16; + lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_200; + lasat_serial8250_port[0].irq = LASATINT_UART_200; + } + + pdev->id = PLAT8250_DEV_PLATFORM; + pdev->dev.platform_data = lasat_serial8250_port; + + retval = platform_device_add_resources(pdev, lasat_serial_res, ARRAY_SIZE(lasat_serial_res)); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} +device_initcall(lasat_uart_add); diff -puN /dev/null arch/mips/lasat/setup.c --- /dev/null +++ a/arch/mips/lasat/setup.c @@ -0,0 +1,158 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. + * + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * Brian Murphy + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Lasat specific setup. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PICVUE +#include +#endif + +#include "ds1603.h" +#include +#include +#include + +#include "prom.h" + +int lasat_command_line; +void lasatint_init(void); + +extern void lasat_reboot_setup(void); +extern void pcisetup(void); +extern void edhac_init(void *, void *, void *); +extern void addrflt_init(void); + +struct lasat_misc lasat_misc_info[N_MACHTYPES] = { + { + .reset_reg = (void *)KSEG1ADDR(0x1c840000), + .flash_wp_reg = (void *)KSEG1ADDR(0x1c800000), 2 + }, { + .reset_reg = (void *)KSEG1ADDR(0x11080000), + .flash_wp_reg = (void *)KSEG1ADDR(0x11000000), 6 + } +}; + +struct lasat_misc *lasat_misc; + +#ifdef CONFIG_DS1603 +static struct ds_defs ds_defs[N_MACHTYPES] = { + { (void *)DS1603_REG_100, (void *)DS1603_REG_100, + DS1603_RST_100, DS1603_CLK_100, DS1603_DATA_100, + DS1603_DATA_SHIFT_100, 0, 0 }, + { (void *)DS1603_REG_200, (void *)DS1603_DATA_REG_200, + DS1603_RST_200, DS1603_CLK_200, DS1603_DATA_200, + DS1603_DATA_READ_SHIFT_200, 1, 2000 } +}; +#endif + +#ifdef CONFIG_PICVUE +#include "picvue.h" +static struct pvc_defs pvc_defs[N_MACHTYPES] = { + { (void *)PVC_REG_100, PVC_DATA_SHIFT_100, PVC_DATA_M_100, + PVC_E_100, PVC_RW_100, PVC_RS_100 }, + { (void *)PVC_REG_200, PVC_DATA_SHIFT_200, PVC_DATA_M_200, + PVC_E_200, PVC_RW_200, PVC_RS_200 } +}; +#endif + +static int lasat_panic_display(struct notifier_block *this, + unsigned long event, void *ptr) +{ +#ifdef CONFIG_PICVUE + unsigned char *string = ptr; + if (string == NULL) + string = "Kernel Panic"; + pvc_dump_string(string); +#endif + return NOTIFY_DONE; +} + +static int lasat_panic_prom_monitor(struct notifier_block *this, + unsigned long event, void *ptr) +{ + prom_monitor(); + return NOTIFY_DONE; +} + +static struct notifier_block lasat_panic_block[] = +{ + { + .notifier_call = lasat_panic_display, + .priority = INT_MAX + }, { + .notifier_call = lasat_panic_prom_monitor, + .priority = INT_MIN + } +}; + +static void lasat_time_init(void) +{ + mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2; +} + +void __init plat_timer_setup(struct irqaction *irq) +{ + change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); +} + +void __init plat_mem_setup(void) +{ + int i; + lasat_misc = &lasat_misc_info[mips_machtype]; +#ifdef CONFIG_PICVUE + picvue = &pvc_defs[mips_machtype]; +#endif + + /* Set up panic notifier */ + for (i = 0; i < ARRAY_SIZE(lasat_panic_block); i++) + atomic_notifier_chain_register(&panic_notifier_list, + &lasat_panic_block[i]); + + lasat_reboot_setup(); + + board_time_init = lasat_time_init; + +#ifdef CONFIG_DS1603 + ds1603 = &ds_defs[mips_machtype]; + rtc_mips_get_time = ds1603_read; + rtc_mips_set_time = ds1603_set; +#endif + +#ifdef DYNAMIC_SERIAL_INIT + serial_init(); +#endif + + pr_info("Lasat specific initialization complete\n"); +} diff -puN /dev/null arch/mips/lasat/sysctl.c --- /dev/null +++ a/arch/mips/lasat/sysctl.c @@ -0,0 +1,454 @@ +/* + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines specific to the LASAT boards + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sysctl.h" +#include "ds1603.h" + +static DEFINE_MUTEX(lasat_info_mutex); + +/* Strategy function to write EEPROM after changing string entry */ +int sysctl_lasatstring(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = sysctl_string(table, name, + nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (newval && newlen) + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 1; +} + + +/* And the same for proc */ +int proc_dolasatstring(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = proc_dostring(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +/* proc function to write EEPROM after changing int entry */ +int proc_dolasatint(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = proc_dointvec(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +static int rtctmp; + +#ifdef CONFIG_DS1603 +/* proc function to read/write RealTime Clock */ +int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + if (!write) { + rtctmp = ds1603_read(); + /* check for time < 0 and set to 0 */ + if (rtctmp < 0) + rtctmp = 0; + } + r = proc_dointvec(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + ds1603_set(rtctmp); + mutex_unlock(&lasat_info_mutex); + + return 0; +} +#endif + +/* Sysctl for setting the IP addresses */ +int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (newval && newlen) + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 1; +} + +#ifdef CONFIG_DS1603 +/* Same for RTC */ +int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + rtctmp = ds1603_read(); + if (rtctmp < 0) + rtctmp = 0; + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (newval && newlen) + ds1603_set(rtctmp); + mutex_unlock(&lasat_info_mutex); + + return 1; +} +#endif + +#ifdef CONFIG_INET +static char lasat_bcastaddr[16]; + +void update_bcastaddr(void) +{ + unsigned int ip; + + ip = (lasat_board_info.li_eeprom_info.ipaddr & + lasat_board_info.li_eeprom_info.netmask) | + ~lasat_board_info.li_eeprom_info.netmask; + + sprintf(lasat_bcastaddr, "%d.%d.%d.%d", + (ip) & 0xff, + (ip >> 8) & 0xff, + (ip >> 16) & 0xff, + (ip >> 24) & 0xff); +} + +static char proc_lasat_ipbuf[32]; + +/* Parsing of IP address */ +int proc_lasat_ip(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + unsigned int ip; + char *p, c; + int len; + + if (!table->data || !table->maxlen || !*lenp || + (*ppos && !write)) { + *lenp = 0; + return 0; + } + + mutex_lock(&lasat_info_mutex); + if (write) { + len = 0; + p = buffer; + while (len < *lenp) { + if (get_user(c, p++)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + if (c == 0 || c == '\n') + break; + len++; + } + if (len >= sizeof(proc_lasat_ipbuf)-1) + len = sizeof(proc_lasat_ipbuf) - 1; + if (copy_from_user(proc_lasat_ipbuf, buffer, len)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + proc_lasat_ipbuf[len] = 0; + *ppos += *lenp; + /* Now see if we can convert it to a valid IP */ + ip = in_aton(proc_lasat_ipbuf); + *(unsigned int *)(table->data) = ip; + lasat_write_eeprom_info(); + } else { + ip = *(unsigned int *)(table->data); + sprintf(proc_lasat_ipbuf, "%d.%d.%d.%d", + (ip) & 0xff, + (ip >> 8) & 0xff, + (ip >> 16) & 0xff, + (ip >> 24) & 0xff); + len = strlen(proc_lasat_ipbuf); + if (len > *lenp) + len = *lenp; + if (len) + if (copy_to_user(buffer, proc_lasat_ipbuf, len)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + if (len < *lenp) { + if (put_user('\n', ((char *) buffer) + len)) { + mutex_unlock(&lasat_info_mutex); + return -EFAULT; + } + len++; + } + *lenp = len; + *ppos += len; + } + update_bcastaddr(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} +#endif /* defined(CONFIG_INET) */ + +static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); + if (r < 0) { + mutex_unlock(&lasat_info_mutex); + return r; + } + + if (newval && newlen) { + if (name && *name == LASAT_PRID) + lasat_board_info.li_eeprom_info.prid = *(int *)newval; + + lasat_write_eeprom_info(); + lasat_init_board_info(); + } + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp, loff_t *ppos) +{ + int r; + + mutex_lock(&lasat_info_mutex); + r = proc_dointvec(table, write, filp, buffer, lenp, ppos); + if ((!write) || r) { + mutex_unlock(&lasat_info_mutex); + return r; + } + if (filp && filp->f_path.dentry) { + if (!strcmp(filp->f_path.dentry->d_name.name, "prid")) + lasat_board_info.li_eeprom_info.prid = + lasat_board_info.li_prid; + if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess")) + lasat_board_info.li_eeprom_info.debugaccess = + lasat_board_info.li_debugaccess; + } + lasat_write_eeprom_info(); + mutex_unlock(&lasat_info_mutex); + + return 0; +} + +extern int lasat_boot_to_service; + +#ifdef CONFIG_SYSCTL + +static ctl_table lasat_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "cpu-hz", + .data = &lasat_board_info.li_cpu_hz, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "bus-hz", + .data = &lasat_board_info.li_bus_hz, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "bmid", + .data = &lasat_board_info.li_bmid, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "prid", + .data = &lasat_board_info.li_prid, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_lasat_eeprom_value, + .strategy = &sysctl_lasat_eeprom_value + }, +#ifdef CONFIG_INET + { + .ctl_name = CTL_UNNUMBERED, + .procname = "ipaddr", + .data = &lasat_board_info.li_eeprom_info.ipaddr, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_lasat_ip, + .strategy = &sysctl_lasat_intvec + }, + { + .ctl_name = LASAT_NETMASK, + .procname = "netmask", + .data = &lasat_board_info.li_eeprom_info.netmask, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_lasat_ip, + .strategy = &sysctl_lasat_intvec + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "bcastaddr", + .data = &lasat_bcastaddr, + .maxlen = sizeof(lasat_bcastaddr), + .mode = 0600, + .proc_handler = &proc_dostring, + .strategy = &sysctl_string + }, +#endif + { + .ctl_name = CTL_UNNUMBERED, + .procname = "passwd_hash", + .data = &lasat_board_info.li_eeprom_info.passwd_hash, + .maxlen = + sizeof(lasat_board_info.li_eeprom_info.passwd_hash), + .mode = 0600, + .proc_handler = &proc_dolasatstring, + .strategy = &sysctl_lasatstring + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "boot-service", + .data = &lasat_boot_to_service, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_dointvec, + .strategy = &sysctl_intvec + }, +#ifdef CONFIG_DS1603 + { + .ctl_name = CTL_UNNUMBERED, + .procname = "rtc", + .data = &rtctmp, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_dolasatrtc, + .strategy = &sysctl_lasat_rtc + }, +#endif + { + .ctl_name = CTL_UNNUMBERED, + .procname = "namestr", + .data = &lasat_board_info.li_namestr, + .maxlen = sizeof(lasat_board_info.li_namestr), + .mode = 0444, + .proc_handler = &proc_dostring, + .strategy = &sysctl_string + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "typestr", + .data = &lasat_board_info.li_typestr, + .maxlen = sizeof(lasat_board_info.li_typestr), + .mode = 0444, + .proc_handler = &proc_dostring, + .strategy = &sysctl_string + }, + {} +}; + +static ctl_table lasat_root_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "lasat", + .mode = 0555, + .child = lasat_table + }, + {} +}; + +static int __init lasat_register_sysctl(void) +{ + struct ctl_table_header *lasat_table_header; + + lasat_table_header = + register_sysctl_table(lasat_root_table); + + return 0; +} + +__initcall(lasat_register_sysctl); +#endif /* CONFIG_SYSCTL */ diff -puN /dev/null arch/mips/lasat/sysctl.h --- /dev/null +++ a/arch/mips/lasat/sysctl.h @@ -0,0 +1,24 @@ +/* + * LASAT sysctl values + */ + +#ifndef _LASAT_SYSCTL_H +#define _LASAT_SYSCTL_H + +/* /proc/sys/lasat */ +enum { + LASAT_CPU_HZ = 1, + LASAT_BUS_HZ, + LASAT_MODEL, + LASAT_PRID, + LASAT_IPADDR, + LASAT_NETMASK, + LASAT_BCAST, + LASAT_PASSWORD, + LASAT_SBOOT, + LASAT_RTC, + LASAT_NAMESTR, + LASAT_TYPESTR, +}; + +#endif /* _LASAT_SYSCTL_H */ diff -puN arch/mips/lemote/lm2e/Makefile~git-mips arch/mips/lemote/lm2e/Makefile diff -puN arch/mips/mips-boards/malta/malta_smtc.c~git-mips arch/mips/mips-boards/malta/malta_smtc.c --- a/arch/mips/mips-boards/malta/malta_smtc.c~git-mips +++ a/arch/mips/mips-boards/malta/malta_smtc.c @@ -88,3 +88,53 @@ void __cpuinit prom_smp_finish(void) void prom_cpus_done(void) { } + +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * IRQ affinity hook + */ + + +void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity) +{ + cpumask_t tmask = affinity; + int cpu = 0; + void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); + + /* + * On the legacy Malta development board, all I/O interrupts + * are routed through the 8259 and combined in a single signal + * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, + * that signal is brought to IP2 of both VPEs. To avoid racing + * concurrent interrupt service events, IP2 is enabled only on + * one VPE, by convention VPE0. So long as no bits are ever + * cleared in the affinity mask, there will never be any + * interrupt forwarding. But as soon as a program or operator + * sets affinity for one of the related IRQs, we need to make + * sure that we don't ever try to forward across the VPE boundry, + * at least not until we engineer a system where the interrupt + * _ack() or _end() function can somehow know that it corresponds + * to an interrupt taken on another VPE, and perform the appropriate + * restoration of Status.IM state using MFTR/MTTR instead of the + * normal local behavior. We also ensure that no attempt will + * be made to forward to an offline "CPU". + */ + + for_each_cpu_mask(cpu, affinity) { + if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) + cpu_clear(cpu, tmask); + } + irq_desc[irq].affinity = tmask; + + if (cpus_empty(tmask)) + /* + * We could restore a default mask here, but the + * runtime code can anyway deal with the null set + */ + printk(KERN_WARNING + "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); + + /* Do any generic SMTC IRQ affinity setup */ + smtc_set_irq_affinity(irq, tmask); +} +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff -puN arch/mips/mm/Makefile~git-mips arch/mips/mm/Makefile --- a/arch/mips/mm/Makefile~git-mips +++ a/arch/mips/mm/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R5432) += c-r4k.o cex- obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ +obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o pg-sb1.o \ tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o diff -puN arch/mips/mm/c-r4k.c~git-mips arch/mips/mm/c-r4k.c --- a/arch/mips/mm/c-r4k.c~git-mips +++ a/arch/mips/mm/c-r4k.c @@ -9,6 +9,7 @@ */ #include #include +#include #include #include #include @@ -948,12 +949,16 @@ static void __init probe_pcache(void) switch (c->cputype) { case CPU_20KC: case CPU_25KF: + case CPU_SB1: + case CPU_SB1A: c->dcache.flags |= MIPS_CACHE_PINDEX; + break; + case CPU_R10000: case CPU_R12000: case CPU_R14000: - case CPU_SB1: break; + case CPU_24K: case CPU_34K: case CPU_74K: @@ -1235,11 +1240,20 @@ void __init r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); - extern char except_vec2_generic; + extern char __weak except_vec2_generic; + extern char __weak except_vec2_sb1; struct cpuinfo_mips *c = ¤t_cpu_data; - /* Default cache error handler for R4000 and R5000 family */ - set_uncached_handler (0x100, &except_vec2_generic, 0x80); + switch (c->cputype) { + case CPU_SB1: + case CPU_SB1A: + set_uncached_handler(0x100, &except_vec2_sb1, 0x80); + break; + + default: + set_uncached_handler(0x100, &except_vec2_generic, 0x80); + break; + } probe_pcache(); setup_scache(); diff -puN arch/mips/mm/c-sb1.c~git-mips /dev/null --- a/arch/mips/mm/c-sb1.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -extern void sb1_dma_init(void); - -/* These are probed at ld_mmu time */ -static unsigned long icache_size; -static unsigned long dcache_size; - -static unsigned short icache_line_size; -static unsigned short dcache_line_size; - -static unsigned int icache_index_mask; -static unsigned int dcache_index_mask; - -static unsigned short icache_assoc; -static unsigned short dcache_assoc; - -static unsigned short icache_sets; -static unsigned short dcache_sets; - -static unsigned int icache_range_cutoff; -static unsigned int dcache_range_cutoff; - -static inline void sb1_on_each_cpu(void (*func) (void *info), void *info, - int retry, int wait) -{ - preempt_disable(); - smp_call_function(func, info, retry, wait); - func(info); - preempt_enable(); -} - -/* - * The dcache is fully coherent to the system, with one - * big caveat: the instruction stream. In other words, - * if we miss in the icache, and have dirty data in the - * L1 dcache, then we'll go out to memory (or the L2) and - * get the not-as-recent data. - * - * So the only time we have to flush the dcache is when - * we're flushing the icache. Since the L2 is fully - * coherent to everything, including I/O, we never have - * to flush it - */ - -#define cache_set_op(op, addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips64\n\t \n" \ - " cache %0, (0<<13)(%1) \n" \ - " cache %0, (1<<13)(%1) \n" \ - " cache %0, (2<<13)(%1) \n" \ - " cache %0, (3<<13)(%1) \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "r" (addr)) - -#define sync() \ - __asm__ __volatile( \ - " .set mips64\n\t \n" \ - " sync \n" \ - " .set mips0") - -#define mispredict() \ - __asm__ __volatile__( \ - " bnezl $0, 1f \n" /* Force mispredict */ \ - "1: \n"); - -/* - * Writeback and invalidate the entire dcache - */ -static inline void __sb1_writeback_inv_dcache_all(void) -{ - unsigned long addr = 0; - - while (addr < dcache_line_size * dcache_sets) { - cache_set_op(Index_Writeback_Inv_D, addr); - addr += dcache_line_size; - } -} - -/* - * Writeback and invalidate a range of the dcache. The addresses are - * virtual, and since we're using index ops and bit 12 is part of both - * the virtual frame and physical index, we have to clear both sets - * (bit 12 set and cleared). - */ -static inline void __sb1_writeback_inv_dcache_range(unsigned long start, - unsigned long end) -{ - unsigned long index; - - start &= ~(dcache_line_size - 1); - end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1); - - while (start != end) { - index = start & dcache_index_mask; - cache_set_op(Index_Writeback_Inv_D, index); - cache_set_op(Index_Writeback_Inv_D, index ^ (1<<12)); - start += dcache_line_size; - } - sync(); -} - -/* - * Writeback and invalidate a range of the dcache. With physical - * addresseses, we don't have to worry about possible bit 12 aliasing. - * XXXKW is it worth turning on KX and using hit ops with xkphys? - */ -static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start, - unsigned long end) -{ - start &= ~(dcache_line_size - 1); - end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1); - - while (start != end) { - cache_set_op(Index_Writeback_Inv_D, start & dcache_index_mask); - start += dcache_line_size; - } - sync(); -} - - -/* - * Invalidate the entire icache - */ -static inline void __sb1_flush_icache_all(void) -{ - unsigned long addr = 0; - - while (addr < icache_line_size * icache_sets) { - cache_set_op(Index_Invalidate_I, addr); - addr += icache_line_size; - } -} - -/* - * Invalidate a range of the icache. The addresses are virtual, and - * the cache is virtually indexed and tagged. However, we don't - * necessarily have the right ASID context, so use index ops instead - * of hit ops. - */ -static inline void __sb1_flush_icache_range(unsigned long start, - unsigned long end) -{ - start &= ~(icache_line_size - 1); - end = (end + icache_line_size - 1) & ~(icache_line_size - 1); - - while (start != end) { - cache_set_op(Index_Invalidate_I, start & icache_index_mask); - start += icache_line_size; - } - mispredict(); - sync(); -} - -/* - * Flush the icache for a given physical page. Need to writeback the - * dcache first, then invalidate the icache. If the page isn't - * executable, nothing is required. - */ -static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) -{ - int cpu = smp_processor_id(); - -#ifndef CONFIG_SMP - if (!(vma->vm_flags & VM_EXEC)) - return; -#endif - - __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); - - /* - * Bumping the ASID is probably cheaper than the flush ... - */ - if (vma->vm_mm == current->active_mm) { - if (cpu_context(cpu, vma->vm_mm) != 0) - drop_mmu_context(vma->vm_mm, cpu); - } else - __sb1_flush_icache_range(addr, addr + PAGE_SIZE); -} - -#ifdef CONFIG_SMP -struct flush_cache_page_args { - struct vm_area_struct *vma; - unsigned long addr; - unsigned long pfn; -}; - -static void sb1_flush_cache_page_ipi(void *info) -{ - struct flush_cache_page_args *args = info; - - local_sb1_flush_cache_page(args->vma, args->addr, args->pfn); -} - -/* Dirty dcache could be on another CPU, so do the IPIs */ -static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) -{ - struct flush_cache_page_args args; - - if (!(vma->vm_flags & VM_EXEC)) - return; - - addr &= PAGE_MASK; - args.vma = vma; - args.addr = addr; - args.pfn = pfn; - sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); -} -#else -void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) - __attribute__((alias("local_sb1_flush_cache_page"))); -#endif - -#ifdef CONFIG_SMP -static void sb1_flush_cache_data_page_ipi(void *info) -{ - unsigned long start = (unsigned long)info; - - __sb1_writeback_inv_dcache_range(start, start + PAGE_SIZE); -} - -static void sb1_flush_cache_data_page(unsigned long addr) -{ - if (in_atomic()) - __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); - else - on_each_cpu(sb1_flush_cache_data_page_ipi, (void *) addr, 1, 1); -} -#else - -static void local_sb1_flush_cache_data_page(unsigned long addr) -{ - __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); -} - -void sb1_flush_cache_data_page(unsigned long) - __attribute__((alias("local_sb1_flush_cache_data_page"))); -#endif - -/* - * Invalidate all caches on this CPU - */ -static void __used local_sb1___flush_cache_all(void) -{ - __sb1_writeback_inv_dcache_all(); - __sb1_flush_icache_all(); -} - -#ifdef CONFIG_SMP -void sb1___flush_cache_all_ipi(void *ignored) - __attribute__((alias("local_sb1___flush_cache_all"))); - -static void sb1___flush_cache_all(void) -{ - sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); -} -#else -void sb1___flush_cache_all(void) - __attribute__((alias("local_sb1___flush_cache_all"))); -#endif - -/* - * When flushing a range in the icache, we have to first writeback - * the dcache for the same range, so new ifetches will see any - * data that was dirty in the dcache. - * - * The start/end arguments are Kseg addresses (possibly mapped Kseg). - */ - -static void local_sb1_flush_icache_range(unsigned long start, - unsigned long end) -{ - /* Just wb-inv the whole dcache if the range is big enough */ - if ((end - start) > dcache_range_cutoff) - __sb1_writeback_inv_dcache_all(); - else - __sb1_writeback_inv_dcache_range(start, end); - - /* Just flush the whole icache if the range is big enough */ - if ((end - start) > icache_range_cutoff) - __sb1_flush_icache_all(); - else - __sb1_flush_icache_range(start, end); -} - -#ifdef CONFIG_SMP -struct flush_icache_range_args { - unsigned long start; - unsigned long end; -}; - -static void sb1_flush_icache_range_ipi(void *info) -{ - struct flush_icache_range_args *args = info; - - local_sb1_flush_icache_range(args->start, args->end); -} - -void sb1_flush_icache_range(unsigned long start, unsigned long end) -{ - struct flush_icache_range_args args; - - args.start = start; - args.end = end; - sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); -} -#else -void sb1_flush_icache_range(unsigned long start, unsigned long end) - __attribute__((alias("local_sb1_flush_icache_range"))); -#endif - -/* - * A signal trampoline must fit into a single cacheline. - */ -static void local_sb1_flush_cache_sigtramp(unsigned long addr) -{ - cache_set_op(Index_Writeback_Inv_D, addr & dcache_index_mask); - cache_set_op(Index_Writeback_Inv_D, (addr ^ (1<<12)) & dcache_index_mask); - cache_set_op(Index_Invalidate_I, addr & icache_index_mask); - mispredict(); -} - -#ifdef CONFIG_SMP -static void sb1_flush_cache_sigtramp_ipi(void *info) -{ - unsigned long iaddr = (unsigned long) info; - local_sb1_flush_cache_sigtramp(iaddr); -} - -static void sb1_flush_cache_sigtramp(unsigned long addr) -{ - sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); -} -#else -void sb1_flush_cache_sigtramp(unsigned long addr) - __attribute__((alias("local_sb1_flush_cache_sigtramp"))); -#endif - - -/* - * Anything that just flushes dcache state can be ignored, as we're always - * coherent in dcache space. This is just a dummy function that all the - * nop'ed routines point to - */ -static void sb1_nop(void) -{ -} - -/* - * Cache set values (from the mips64 spec) - * 0 - 64 - * 1 - 128 - * 2 - 256 - * 3 - 512 - * 4 - 1024 - * 5 - 2048 - * 6 - 4096 - * 7 - Reserved - */ - -static unsigned int decode_cache_sets(unsigned int config_field) -{ - if (config_field == 7) { - /* JDCXXX - Find a graceful way to abort. */ - return 0; - } - return (1<<(config_field + 6)); -} - -/* - * Cache line size values (from the mips64 spec) - * 0 - No cache present. - * 1 - 4 bytes - * 2 - 8 bytes - * 3 - 16 bytes - * 4 - 32 bytes - * 5 - 64 bytes - * 6 - 128 bytes - * 7 - Reserved - */ - -static unsigned int decode_cache_line_size(unsigned int config_field) -{ - if (config_field == 0) { - return 0; - } else if (config_field == 7) { - /* JDCXXX - Find a graceful way to abort. */ - return 0; - } - return (1<<(config_field + 1)); -} - -/* - * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs) - * - * 24:22 Icache sets per way - * 21:19 Icache line size - * 18:16 Icache Associativity - * 15:13 Dcache sets per way - * 12:10 Dcache line size - * 9:7 Dcache Associativity - */ - -static char *way_string[] = { - "direct mapped", "2-way", "3-way", "4-way", - "5-way", "6-way", "7-way", "8-way", -}; - -static __init void probe_cache_sizes(void) -{ - u32 config1; - - config1 = read_c0_config1(); - icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7); - dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7); - icache_sets = decode_cache_sets((config1 >> 22) & 0x7); - dcache_sets = decode_cache_sets((config1 >> 13) & 0x7); - icache_assoc = ((config1 >> 16) & 0x7) + 1; - dcache_assoc = ((config1 >> 7) & 0x7) + 1; - icache_size = icache_line_size * icache_sets * icache_assoc; - dcache_size = dcache_line_size * dcache_sets * dcache_assoc; - /* Need to remove non-index bits for index ops */ - icache_index_mask = (icache_sets - 1) * icache_line_size; - dcache_index_mask = (dcache_sets - 1) * dcache_line_size; - /* - * These are for choosing range (index ops) versus all. - * icache flushes all ways for each set, so drop icache_assoc. - * dcache flushes all ways and each setting of bit 12 for each - * index, so drop dcache_assoc and halve the dcache_sets. - */ - icache_range_cutoff = icache_sets * icache_line_size; - dcache_range_cutoff = (dcache_sets / 2) * icache_line_size; - - printk("Primary instruction cache %ldkB, %s, linesize %d bytes.\n", - icache_size >> 10, way_string[icache_assoc - 1], - icache_line_size); - printk("Primary data cache %ldkB, %s, linesize %d bytes.\n", - dcache_size >> 10, way_string[dcache_assoc - 1], - dcache_line_size); -} - -/* - * This is called from cache.c. We have to set up all the - * memory management function pointers, as well as initialize - * the caches and tlbs - */ -void __init sb1_cache_init(void) -{ - extern char except_vec2_sb1; - - /* Special cache error handler for SB1 */ - set_uncached_handler (0x100, &except_vec2_sb1, 0x80); - - probe_cache_sizes(); - -#ifdef CONFIG_SIBYTE_DMA_PAGEOPS - sb1_dma_init(); -#endif - - /* - * None of these are needed for the SB1 - the Dcache is - * physically indexed and tagged, so no virtual aliasing can - * occur - */ - flush_cache_range = (void *) sb1_nop; - flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop; - flush_cache_all = sb1_nop; - - /* These routines are for Icache coherence with the Dcache */ - flush_icache_range = sb1_flush_icache_range; - flush_icache_all = __sb1_flush_icache_all; /* local only */ - - /* This implies an Icache flush too, so can't be nop'ed */ - flush_cache_page = sb1_flush_cache_page; - - flush_cache_sigtramp = sb1_flush_cache_sigtramp; - local_flush_data_cache_page = (void *) sb1_nop; - flush_data_cache_page = sb1_flush_cache_data_page; - - /* Full flush */ - __flush_cache_all = sb1___flush_cache_all; - - change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); - - /* - * This is the only way to force the update of K0 to complete - * before subsequent instruction fetch. - */ - __asm__ __volatile__( - ".set push \n" - " .set noat \n" - " .set noreorder \n" - " .set mips3 \n" - " " STR(PTR_LA) " $1, 1f \n" - " " STR(MTC0) " $1, $14 \n" - " eret \n" - "1: .set pop" - : - : - : "memory"); - - local_sb1___flush_cache_all(); -} diff -puN arch/mips/mm/cache.c~git-mips arch/mips/mm/cache.c --- a/arch/mips/mm/cache.c~git-mips +++ a/arch/mips/mm/cache.c @@ -3,13 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2007 MIPS Technologies, Inc. */ #include #include #include #include +#include #include #include #include @@ -157,12 +158,6 @@ void __init cpu_cache_init(void) tx39_cache_init(); return; } - if (cpu_has_sb1_cache) { - extern void __weak sb1_cache_init(void); - - sb1_cache_init(); - return; - } panic(cache_panic); } diff -puN arch/mips/mm/pg-sb1.c~git-mips arch/mips/mm/pg-sb1.c --- a/arch/mips/mm/pg-sb1.c~git-mips +++ a/arch/mips/mm/pg-sb1.c @@ -292,3 +292,11 @@ void copy_page(void *to, void *from) EXPORT_SYMBOL(clear_page); EXPORT_SYMBOL(copy_page); + +void __init build_clear_page(void) +{ +} + +void __init build_copy_page(void) +{ +} diff -puN arch/mips/mm/tlbex.c~git-mips arch/mips/mm/tlbex.c --- a/arch/mips/mm/tlbex.c~git-mips +++ a/arch/mips/mm/tlbex.c @@ -908,6 +908,8 @@ static __init void build_tlb_write_entry case CPU_4KSC: case CPU_20KC: case CPU_25KF: + case CPU_BCM3302: + case CPU_BCM4710: case CPU_LOONGSON2: if (m4kc_tlbp_war()) i_nop(p); diff -puN arch/mips/pci/Makefile~git-mips arch/mips/pci/Makefile --- a/arch/mips/pci/Makefile~git-mips +++ a/arch/mips/pci/Makefile @@ -10,6 +10,7 @@ obj-y += pci.o obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o +obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o @@ -19,6 +20,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o # These are still pretty much in the old state, watch, go blind. # obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o +obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o diff -puN arch/mips/pci/fixup-cobalt.c~git-mips arch/mips/pci/fixup-cobalt.c --- a/arch/mips/pci/fixup-cobalt.c~git-mips +++ a/arch/mips/pci/fixup-cobalt.c @@ -18,6 +18,7 @@ #include #include +#include static void qube_raq_galileo_early_fixup(struct pci_dev *dev) { @@ -132,29 +133,29 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_V static char irq_tab_qube1[] __initdata = { [COBALT_PCICONF_CPU] = 0, - [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, - [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, + [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, [COBALT_PCICONF_VIA] = 0, - [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, + [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, [COBALT_PCICONF_ETH1] = 0 }; static char irq_tab_cobalt[] __initdata = { [COBALT_PCICONF_CPU] = 0, - [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, - [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, + [COBALT_PCICONF_ETH0] = ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, [COBALT_PCICONF_VIA] = 0, - [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, - [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ + [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, + [COBALT_PCICONF_ETH1] = ETH1_IRQ }; static char irq_tab_raq2[] __initdata = { [COBALT_PCICONF_CPU] = 0, - [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, - [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ, + [COBALT_PCICONF_ETH0] = ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ, [COBALT_PCICONF_VIA] = 0, - [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, - [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ + [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, + [COBALT_PCICONF_ETH1] = ETH1_IRQ }; int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) diff -puN /dev/null arch/mips/pci/ops-nile4.c --- /dev/null +++ a/arch/mips/pci/ops-nile4.c @@ -0,0 +1,147 @@ +#include +#include +#include +#include + +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define LO(reg) (reg / 4) +#define HI(reg) (reg / 4 + 1) + +volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; + +static DEFINE_SPINLOCK(nile4_pci_lock); + +static int nile4_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, unsigned int devfn, int where, u32 *val) +{ + unsigned char busnum = bus->number; + u32 adr, mask, err; + + if ((busnum == 0) && (PCI_SLOT(devfn) > 8)) + /* The addressing scheme chosen leaves room for just + * 8 devices on the first busnum (besides the PCI + * controller itself) */ + return PCIBIOS_DEVICE_NOT_FOUND; + + if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) { + /* Access controller registers directly */ + if (access_type == PCI_ACCESS_WRITE) { + vrc_pciregs[(0x200 + where) >> 2] = *val; + } else { + *val = vrc_pciregs[(0x200 + where) >> 2]; + } + return PCIBIOS_SUCCESSFUL; + } + + /* Temporarily map PCI Window 1 to config space */ + mask = vrc_pciregs[LO(NILE4_PCIINIT1)]; + vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0); + + /* Clear PCI Error register. This also clears the Error Type + * bits in the Control register */ + vrc_pciregs[LO(NILE4_PCIERR)] = 0; + vrc_pciregs[HI(NILE4_PCIERR)] = 0; + + /* Setup address */ + if (busnum == 0) + adr = + KSEG1ADDR(PCI_WINDOW1) + + ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8) + | (where & ~3)); + else + adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) | + (where & ~3); + + if (access_type == PCI_ACCESS_WRITE) + *(u32 *) adr = *val; + else + *val = *(u32 *) adr; + + /* Check for master or target abort */ + err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7; + + /* Restore PCI Window 1 */ + vrc_pciregs[LO(NILE4_PCIINIT1)] = mask; + + if (err) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} + +static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + unsigned long flags; + u32 data = 0; + int err; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&nile4_pci_lock, flags); + err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data); + spin_unlock_irqrestore(&nile4_pci_lock, flags); + + if (err) + return err; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + unsigned long flags; + u32 data = 0; + int err; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&nile4_pci_lock, flags); + err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data); + spin_unlock_irqrestore(&nile4_pci_lock, flags); + + if (err) + return err; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + if (nile4_pcibios_config_access + (PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops nile4_pci_ops = { + .read = nile4_pcibios_read, + .write = nile4_pcibios_write, +}; diff -puN /dev/null arch/mips/pci/pci-lasat.c --- /dev/null +++ a/arch/mips/pci/pci-lasat.c @@ -0,0 +1,91 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000, 2001, 04 Keith M Wesolowski + */ +#include +#include +#include +#include +#include + +extern struct pci_ops nile4_pci_ops; +extern struct pci_ops gt64xxx_pci0_ops; +static struct resource lasat_pci_mem_resource = { + .name = "LASAT PCI MEM", + .start = 0x18000000, + .end = 0x19ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct resource lasat_pci_io_resource = { + .name = "LASAT PCI IO", + .start = 0x1a000000, + .end = 0x1bffffff, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller lasat_pci_controller = { + .mem_resource = &lasat_pci_mem_resource, + .io_resource = &lasat_pci_io_resource, +}; + +static int __init lasat_pci_setup(void) +{ + printk(KERN_DEBUG "PCI: starting\n"); + + switch (mips_machtype) { + case MACH_LASAT_100: + lasat_pci_controller.pci_ops = >64xxx_pci0_ops; + break; + case MACH_LASAT_200: + lasat_pci_controller.pci_ops = &nile4_pci_ops; + break; + default: + panic("pcibios_init: mips_machtype incorrect"); + } + + register_pci_controller(&lasat_pci_controller); + + return 0; +} + +arch_initcall(lasat_pci_setup); + +#define LASATINT_ETH1 0 +#define LASATINT_ETH0 1 +#define LASATINT_HDC 2 +#define LASATINT_COMP 3 +#define LASATINT_HDLC 4 +#define LASATINT_PCIA 5 +#define LASATINT_PCIB 6 +#define LASATINT_PCIC 7 +#define LASATINT_PCID 8 + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + switch (slot) { + case 1: + case 2: + case 3: + return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4); + case 4: + return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ + case 5: + return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ + case 6: + return LASATINT_HDC; /* IDE controller */ + default: + return 0xff; /* Illegal */ + } + + return -1; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff -puN arch/mips/sgi-ip27/ip27-berr.c~git-mips arch/mips/sgi-ip27/ip27-berr.c --- a/arch/mips/sgi-ip27/ip27-berr.c~git-mips +++ a/arch/mips/sgi-ip27/ip27-berr.c @@ -21,8 +21,6 @@ #include #include -extern void dump_tlb_all(void); - static void dump_hub_information(unsigned long errst0, unsigned long errst1) { static char *err_type[2][8] = { diff -puN arch/mips/sgi-ip32/ip32-irq.c~git-mips arch/mips/sgi-ip32/ip32-irq.c --- a/arch/mips/sgi-ip32/ip32-irq.c~git-mips +++ a/arch/mips/sgi-ip32/ip32-irq.c @@ -117,10 +117,18 @@ static void inline flush_mace_bus(void) extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); -struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED, - CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; -struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED, - CPU_MASK_NONE, "CRIME CPU error", NULL, NULL }; +struct irqaction memerr_irq = { + .handler = crime_memerr_intr, + .flags = IRQF_DISABLED, + .mask = CPU_MASK_NONE, + .name = "CRIME memory error", +}; +struct irqaction cpuerr_irq = { + .handler = crime_cpuerr_intr, + .flags = IRQF_DISABLED, + .mask = CPU_MASK_NONE, + .name = "CRIME CPU error", +}; /* * For interrupts wired from a single device to the CPU. Only the clock diff -puN arch/mips/sibyte/bcm1480/setup.c~git-mips arch/mips/sibyte/bcm1480/setup.c --- a/arch/mips/sibyte/bcm1480/setup.c~git-mips +++ a/arch/mips/sibyte/bcm1480/setup.c @@ -43,16 +43,49 @@ static unsigned int part_type; static char *soc_str; static char *pass_str; -static inline int setup_bcm1x80_bcm1x55(void); +static int __init setup_bcm1x80_bcm1x55(void) +{ + int ret = 0; + + switch (soc_pass) { + case K_SYS_REVISION_BCM1480_S0: + periph_rev = 1; + pass_str = "S0 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A1: + periph_rev = 1; + pass_str = "A1 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A2: + periph_rev = 1; + pass_str = "A2 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_A3: + periph_rev = 1; + pass_str = "A3 (pass1)"; + break; + case K_SYS_REVISION_BCM1480_B0: + periph_rev = 1; + pass_str = "B0 (pass2)"; + break; + default: + printk("Unknown %s rev %x\n", soc_str, soc_pass); + periph_rev = 1; + pass_str = "Unknown Revision"; + break; + } + + return ret; +} /* Setup code likely to be common to all SiByte platforms */ -static inline int sys_rev_decode(void) +static int __init sys_rev_decode(void) { int ret = 0; switch (soc_type) { - case K_SYS_SOC_TYPE_BCM1x80: + case K_SYS_SOC_TYPE_BCM1x80: if (part_type == K_SYS_PART_BCM1480) soc_str = "BCM1480"; else if (part_type == K_SYS_PART_BCM1280) @@ -62,7 +95,7 @@ static inline int sys_rev_decode(void) ret = setup_bcm1x80_bcm1x55(); break; - case K_SYS_SOC_TYPE_BCM1x55: + case K_SYS_SOC_TYPE_BCM1x55: if (part_type == K_SYS_PART_BCM1455) soc_str = "BCM1455"; else if (part_type == K_SYS_PART_BCM1255) @@ -72,49 +105,16 @@ static inline int sys_rev_decode(void) ret = setup_bcm1x80_bcm1x55(); break; - default: + default: printk("Unknown part type %x\n", part_type); ret = 1; break; } - return ret; -} -static inline int setup_bcm1x80_bcm1x55(void) -{ - int ret = 0; - - switch (soc_pass) { - case K_SYS_REVISION_BCM1480_S0: - periph_rev = 1; - pass_str = "S0 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_A1: - periph_rev = 1; - pass_str = "A1 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_A2: - periph_rev = 1; - pass_str = "A2 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_A3: - periph_rev = 1; - pass_str = "A3 (pass1)"; - break; - case K_SYS_REVISION_BCM1480_B0: - periph_rev = 1; - pass_str = "B0 (pass2)"; - break; - default: - printk("Unknown %s rev %x\n", soc_str, soc_pass); - periph_rev = 1; - pass_str = "Unknown Revision"; - break; - } return ret; } -void bcm1480_setup(void) +void __init bcm1480_setup(void) { uint64_t sys_rev; int plldiv; diff -puN arch/mips/sibyte/common/Makefile~git-mips arch/mips/sibyte/common/Makefile diff -puN arch/mips/sibyte/sb1250/setup.c~git-mips arch/mips/sibyte/sb1250/setup.c --- a/arch/mips/sibyte/sb1250/setup.c~git-mips +++ a/arch/mips/sibyte/sb1250/setup.c @@ -40,43 +40,6 @@ static char *soc_str; static char *pass_str; static unsigned int war_pass; /* XXXKW don't overload PASS defines? */ -static inline int setup_bcm1250(void); -static inline int setup_bcm112x(void); - -/* Setup code likely to be common to all SiByte platforms */ - -static int __init sys_rev_decode(void) -{ - int ret = 0; - - war_pass = soc_pass; - switch (soc_type) { - case K_SYS_SOC_TYPE_BCM1250: - case K_SYS_SOC_TYPE_BCM1250_ALT: - case K_SYS_SOC_TYPE_BCM1250_ALT2: - soc_str = "BCM1250"; - ret = setup_bcm1250(); - break; - case K_SYS_SOC_TYPE_BCM1120: - soc_str = "BCM1120"; - ret = setup_bcm112x(); - break; - case K_SYS_SOC_TYPE_BCM1125: - soc_str = "BCM1125"; - ret = setup_bcm112x(); - break; - case K_SYS_SOC_TYPE_BCM1125H: - soc_str = "BCM1125H"; - ret = setup_bcm112x(); - break; - default: - printk("Unknown SOC type %x\n", soc_type); - ret = 1; - break; - } - return ret; -} - static int __init setup_bcm1250(void) { int ret = 0; @@ -120,6 +83,7 @@ static int __init setup_bcm1250(void) } break; } + return ret; } @@ -158,6 +122,42 @@ static int __init setup_bcm112x(void) printk("Unknown %s rev %x\n", soc_str, soc_pass); ret = 1; } + + return ret; +} + +/* Setup code likely to be common to all SiByte platforms */ + +static int __init sys_rev_decode(void) +{ + int ret = 0; + + war_pass = soc_pass; + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1250: + case K_SYS_SOC_TYPE_BCM1250_ALT: + case K_SYS_SOC_TYPE_BCM1250_ALT2: + soc_str = "BCM1250"; + ret = setup_bcm1250(); + break; + case K_SYS_SOC_TYPE_BCM1120: + soc_str = "BCM1120"; + ret = setup_bcm112x(); + break; + case K_SYS_SOC_TYPE_BCM1125: + soc_str = "BCM1125"; + ret = setup_bcm112x(); + break; + case K_SYS_SOC_TYPE_BCM1125H: + soc_str = "BCM1125H"; + ret = setup_bcm112x(); + break; + default: + printk("Unknown SOC type %x\n", soc_type); + ret = 1; + break; + } + return ret; } diff -puN arch/mips/tx4927/common/tx4927_dbgio.c~git-mips arch/mips/tx4927/common/tx4927_dbgio.c --- a/arch/mips/tx4927/common/tx4927_dbgio.c~git-mips +++ a/arch/mips/tx4927/common/tx4927_dbgio.c @@ -31,7 +31,6 @@ #include #include -#include u8 getDebugChar(void) { diff -puN arch/mips/tx4927/common/tx4927_prom.c~git-mips arch/mips/tx4927/common/tx4927_prom.c --- a/arch/mips/tx4927/common/tx4927_prom.c~git-mips +++ a/arch/mips/tx4927/common/tx4927_prom.c @@ -38,7 +38,7 @@ #include #include -static unsigned int __init tx4927_process_sdccr(u64 * addr) +static unsigned int __init tx4927_process_sdccr(unsigned long addr) { u64 val; unsigned int sdccr_ce; @@ -52,7 +52,7 @@ static unsigned int __init tx4927_proces unsigned int mw = 0; unsigned int msize = 0; - val = (*((vu64 *) (addr))); + val = __raw_readq((void __iomem *)addr); /* MVMCP -- need #defs for these bits masks */ sdccr_ce = ((val & (1 << 10)) >> 10); @@ -136,10 +136,10 @@ unsigned int __init tx4927_get_mem_size( unsigned int total; /* MVMCP -- need #defs for these registers */ - c0 = tx4927_process_sdccr((u64 *) 0xff1f8000); - c1 = tx4927_process_sdccr((u64 *) 0xff1f8008); - c2 = tx4927_process_sdccr((u64 *) 0xff1f8010); - c3 = tx4927_process_sdccr((u64 *) 0xff1f8018); + c0 = tx4927_process_sdccr(0xff1f8000); + c1 = tx4927_process_sdccr(0xff1f8008); + c2 = tx4927_process_sdccr(0xff1f8010); + c3 = tx4927_process_sdccr(0xff1f8018); total = c0 + c1 + c2 + c3; return (total); diff -puN arch/mips/tx4927/common/tx4927_setup.c~git-mips arch/mips/tx4927/common/tx4927_setup.c --- a/arch/mips/tx4927/common/tx4927_setup.c~git-mips +++ a/arch/mips/tx4927/common/tx4927_setup.c @@ -124,10 +124,10 @@ dump_cp0(char *key) return; } -void print_pic(char *key, u32 reg, char *name) +void print_pic(char *key, unsigned long reg, char *name) { - printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, - TX4927_RD(reg)); + printk(KERN_INFO "%s pic:0x%08lx:%s=0x%08x\n", key, reg, name, + __raw_readl((void __iomem *)reg)); return; } @@ -166,9 +166,10 @@ void dump_pic(char *key) } -void print_addr(char *hdr, char *key, u32 addr) +void print_addr(char *hdr, char *key, unsigned long addr) { - printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr)); + printk(KERN_INFO "%s %s:0x%08lx=0x%08x\n", hdr, key, addr, + __raw_readl((void __iomem *)addr)); return; } diff -puN arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c~git-mips arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c~git-mips +++ a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -204,8 +204,8 @@ static struct irq_chip toshiba_rbtx4927_ .mask_ack = toshiba_rbtx4927_irq_ioc_disable, .unmask = toshiba_rbtx4927_irq_ioc_enable, }; -#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 -#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 +#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL +#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL u32 bit2num(u32 num) @@ -224,7 +224,7 @@ int toshiba_rbtx4927_irq_nested(int sw_i { u32 level3; - level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; if (level3) { sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { @@ -243,10 +243,12 @@ int toshiba_rbtx4927_irq_nested(int sw_i return (sw_irq); } -//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } -#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL } -static struct irqaction toshiba_rbtx4927_irq_ioc_action = -TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); +static struct irqaction toshiba_rbtx4927_irq_ioc_action = { + .handler = no_action, + .flags = IRQF_SHARED, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4927_IOC_NAME +}; /**********************************************************************************/ @@ -286,9 +288,9 @@ static void toshiba_rbtx4927_irq_ioc_ena panic("\n"); } - v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); } @@ -306,9 +308,10 @@ static void toshiba_rbtx4927_irq_ioc_dis panic("\n"); } - v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); + mmiowb(); } @@ -385,12 +388,12 @@ void toshiba_rbtx4927_irq_dump_pics(char level1_m = level0_m; level1_s = level0_s & 0x87; - level2 = TX4927_RD(0xff1ff6a0); + level2 = __raw_readl((void __iomem *)0xff1ff6a0UL); level2_p = (((level2 & 0x10000)) ? 0 : 1); level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); - level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; - level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; + level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; level4_m = inb(0x21); outb(0x0A, 0x20); diff -puN arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c~git-mips arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c~git-mips +++ a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -679,25 +679,30 @@ void __init tx4927_pci_setup(void) #endif /* CONFIG_PCI */ +static void __noreturn wait_forever(void) +{ + while (1) + if (cpu_wait) + (*cpu_wait)(); +} + void toshiba_rbtx4927_restart(char *command) { printk(KERN_NOTICE "System Rebooting...\n"); /* enable the s/w reset register */ - reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET); + writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); /* wait for enable to be seen */ - while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) & + while ((readb(RBTX4927_SW_RESET_ENABLE) & RBTX4927_SW_RESET_ENABLE_SET) == 0x00); /* do a s/w reset */ - reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET); + writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); /* do something passive while waiting for reset */ local_irq_disable(); - while (1) - asm_wait(); - + wait_forever(); /* no return */ } @@ -706,9 +711,7 @@ void toshiba_rbtx4927_halt(void) { printk(KERN_NOTICE "System Halted\n"); local_irq_disable(); - while (1) { - asm_wait(); - } + wait_forever(); /* no return */ } @@ -720,7 +723,7 @@ void toshiba_rbtx4927_power_off(void) void __init toshiba_rbtx4927_setup(void) { - vu32 cp0_config; + u32 cp0_config; char *argptr; printk("CPU is %s\n", toshiba_name); @@ -747,15 +750,6 @@ void __init toshiba_rbtx4927_setup(void) } #endif - /* setup serial stuff */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Setting up tx4927 sio.\n"); - TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ - TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - "+\n"); - set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, ":mips_io_port_base=0x%08lx\n", diff -puN arch/mips/vr41xx/common/pmu.c~git-mips arch/mips/vr41xx/common/pmu.c --- a/arch/mips/vr41xx/common/pmu.c~git-mips +++ a/arch/mips/vr41xx/common/pmu.c @@ -1,7 +1,7 @@ /* * pmu.c, Power Management Unit routines for NEC VR4100 series. * - * Copyright (C) 2003-2005 Yoichi Yuasa + * Copyright (C) 2003-2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,11 +22,13 @@ #include #include #include -#include +#include #include +#include #include #include +#include #include #include @@ -44,6 +46,18 @@ static void __iomem *pmu_base; #define pmu_read(offset) readw(pmu_base + (offset)) #define pmu_write(offset, value) writew((value), pmu_base + (offset)) +static void vr41xx_cpu_wait(void) +{ + local_irq_disable(); + if (!need_resched()) + /* + * "standby" sets IE bit of the CP0_STATUS to 1. + */ + __asm__("standby;\n"); + else + local_irq_enable(); +} + static inline void software_reset(void) { uint16_t pmucnt2; @@ -57,6 +71,11 @@ static inline void software_reset(void) pmu_write(PMUCNT2REG, pmucnt2); break; default: + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__("jr %0"::"r"(0xbfc00000)); break; } } @@ -65,7 +84,6 @@ static void vr41xx_restart(char *command { local_irq_disable(); software_reset(); - printk(KERN_NOTICE "\nYou can reset your system\n"); while (1) ; } @@ -73,14 +91,7 @@ static void vr41xx_halt(void) { local_irq_disable(); printk(KERN_NOTICE "\nYou can turn off the power supply\n"); - while (1) ; -} - -static void vr41xx_power_off(void) -{ - local_irq_disable(); - printk(KERN_NOTICE "\nYou can turn off the power supply\n"); - while (1) ; + __asm__("hibernate;\n"); } static int __init vr41xx_pmu_init(void) @@ -113,9 +124,10 @@ static int __init vr41xx_pmu_init(void) return -EBUSY; } + cpu_wait = vr41xx_cpu_wait; _machine_restart = vr41xx_restart; _machine_halt = vr41xx_halt; - pm_power_off = vr41xx_power_off; + pm_power_off = vr41xx_halt; return 0; } diff -puN include/asm-mips/arc/hinv.h~git-mips include/asm-mips/arc/hinv.h --- a/include/asm-mips/arc/hinv.h~git-mips +++ a/include/asm-mips/arc/hinv.h @@ -4,6 +4,7 @@ #ifndef _ASM_ARC_HINV_H #define _ASM_ARC_HINV_H +#include #include /* configuration query defines */ @@ -110,7 +111,7 @@ union key_u { ULONG FullKey; }; -#if _MIPS_SIM == _ABI64 +#if _MIPS_SIM == _MIPS_SIM_ABI64 #define SGI_ARCS_VERS 64 /* sgi 64-bit version */ #define SGI_ARCS_REV 0 /* rev .00 */ #else diff -puN include/asm-mips/bootinfo.h~git-mips include/asm-mips/bootinfo.h --- a/include/asm-mips/bootinfo.h~git-mips +++ a/include/asm-mips/bootinfo.h @@ -175,6 +175,13 @@ #define MACH_HP_LASERJET 1 /* + * Valid machtype for group LASAT + */ +#define MACH_GROUP_LASAT 21 +#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ +#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ + +/* * Valid machtype for group TITAN */ #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ @@ -208,6 +215,12 @@ #define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ #define MACH_WRPPMC 1 +/* + * Valid machtype for group Broadcom + */ +#define MACH_GROUP_BRCM 23 /* Broadcom */ +#define MACH_BCM947XX 1 /* Broadcom BCM947xx */ + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); diff -puN include/asm-mips/cpu-features.h~git-mips include/asm-mips/cpu-features.h --- a/include/asm-mips/cpu-features.h~git-mips +++ a/include/asm-mips/cpu-features.h @@ -35,9 +35,6 @@ #ifndef cpu_has_tx39_cache #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) #endif -#ifndef cpu_has_sb1_cache -#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) -#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff -puN include/asm-mips/cpu.h~git-mips include/asm-mips/cpu.h --- a/include/asm-mips/cpu.h~git-mips +++ a/include/asm-mips/cpu.h @@ -106,6 +106,13 @@ #define PRID_IMP_SR71000 0x0400 /* + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM + */ + +#define PRID_IMP_BCM4710 0x4000 +#define PRID_IMP_BCM3302 0x9000 + +/* * Definitions for 7:0 on legacy processors */ @@ -217,8 +224,9 @@ #define CPU_R14000 64 #define CPU_LOONGSON1 65 #define CPU_LOONGSON2 66 - -#define CPU_LAST 66 +#define CPU_BCM3302 67 +#define CPU_BCM4710 68 +#define CPU_LAST 68 /* * ISA Level encodings @@ -247,24 +255,23 @@ #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ -#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ -#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ -#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ -#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ -#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ -#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ +#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ /* * CPU ASE encodings diff -puN include/asm-mips/floppy.h~git-mips include/asm-mips/floppy.h --- a/include/asm-mips/floppy.h~git-mips +++ a/include/asm-mips/floppy.h @@ -10,9 +10,11 @@ #ifndef _ASM_FLOPPY_H #define _ASM_FLOPPY_H +#include + static inline void fd_cacheflush(char * addr, long size) { - dma_cache_wback_inv((unsigned long)addr,size); + dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL); } #define MAX_BUFFER_SECTORS 24 diff -puN include/asm-mips/hw_irq.h~git-mips include/asm-mips/hw_irq.h --- a/include/asm-mips/hw_irq.h~git-mips +++ a/include/asm-mips/hw_irq.h @@ -8,15 +8,8 @@ #ifndef __ASM_HW_IRQ_H #define __ASM_HW_IRQ_H -#include #include -extern void disable_8259A_irq(unsigned int irq); -extern void enable_8259A_irq(unsigned int irq); -extern int i8259A_irq_pending(unsigned int irq); -extern void make_8259A_irq(unsigned int irq); -extern void init_8259A(int aeoi); - extern atomic_t irq_err_count; /* diff -puN include/asm-mips/i8259.h~git-mips include/asm-mips/i8259.h --- a/include/asm-mips/i8259.h~git-mips +++ a/include/asm-mips/i8259.h @@ -37,9 +37,8 @@ extern spinlock_t i8259A_lock; -extern void init_8259A(int auto_eoi); -extern void enable_8259A_irq(unsigned int irq); -extern void disable_8259A_irq(unsigned int irq); +extern int i8259A_irq_pending(unsigned int irq); +extern void make_8259A_irq(unsigned int irq); extern void init_i8259_irqs(void); diff -puN include/asm-mips/ip32/machine.h~git-mips /dev/null --- a/include/asm-mips/ip32/machine.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * machine.h -- Machine/group probing for ip32 - * - * Copyright (C) 2001 Keith M Wesolowski - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ -#ifndef _ASM_IP32_MACHINE_H -#define _ASM_IP32_MACHINE_H - - -#ifdef CONFIG_SGI_IP32 - -#define SGI_MACH_O2 0x3201 - -#endif /* CONFIG_SGI_IP32 */ - -#endif /* _ASM_SGI_MACHINE_H */ diff -puN include/asm-mips/irq.h~git-mips include/asm-mips/irq.h --- a/include/asm-mips/irq.h~git-mips +++ a/include/asm-mips/irq.h @@ -24,6 +24,36 @@ static inline int irq_canonicalize(int i #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ #endif +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +#include + +extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity); +extern void smtc_forward_irq(unsigned int irq); + +/* + * IRQ affinity hook invoked at the beginning of interrupt dispatch + * if option is enabled. + * + * Up through Linux 2.6.22 (at least) cpumask operations are very + * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity + * used a "fast path" per-IRQ-descriptor cache of affinity information + * to reduce latency. As there is a project afoot to optimize the + * cpumask implementations, this version is optimistically assuming + * that cpumask.h macro overhead is reasonable during interrupt dispatch. + */ +#define IRQ_AFFINITY_HOOK(irq) \ +do { \ + if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \ + smtc_forward_irq(irq); \ + irq_exit(); \ + return; \ + } \ +} while (0) +#else /* Not doing SMTC affinity */ +#define IRQ_AFFINITY_HOOK(irq) \ +do { } while (0) +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* * Clear interrupt mask handling "backstop" if irq_hwmask @@ -33,13 +63,26 @@ static inline int irq_canonicalize(int i */ #define __DO_IRQ_SMTC_HOOK(irq) \ do { \ + IRQ_AFFINITY_HOOK(irq); \ if (irq_hwmask[irq] & 0x0000ff00) \ write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ +} while (0) + +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ +do { \ + if (irq_hwmask[irq] & 0x0000ff00) \ + write_c0_tccontext(read_c0_tccontext() & \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ } while (0) #else -#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) -#endif +#define __DO_IRQ_SMTC_HOOK(irq) do { \ + IRQ_AFFINITY_HOOK(irq); \ +} while (0) +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { \ +} while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */ /* * do_IRQ handles all normal device IRQ's (the special @@ -57,6 +100,23 @@ do { \ irq_exit(); \ } while (0) +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * To avoid inefficient and in some cases pathological re-checking of + * IRQ affinity, we have this variant that skips the affinity check. + */ + + +#define do_IRQ_no_affinity(irq) \ +do { \ + irq_enter(); \ + __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ + generic_handle_irq(irq); \ + irq_exit(); \ +} while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + extern void arch_init_irq(void); extern void spurious_interrupt(void); diff -puN /dev/null include/asm-mips/irq_gt641xx.h --- /dev/null +++ a/include/asm-mips/irq_gt641xx.h @@ -0,0 +1,60 @@ +/* + * Galileo/Marvell GT641xx IRQ definitions. + * + * Copyright (C) 2007 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef _ASM_IRQ_GT641XX_H +#define _ASM_IRQ_GT641XX_H + +#ifndef GT641XX_IRQ_BASE +#define GT641XX_IRQ_BASE 8 +#endif + +#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) +#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) +#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) +#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) +#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) +#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) +#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) +#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) +#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) +#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) +#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) +#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) +#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) +#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) +#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) +#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) +#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) +#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) +#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) +#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) +#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) +#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) +#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) +#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) +#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) +#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) +#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) +#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) +#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) + +extern void gt641xx_irq_dispatch(void); +extern void gt641xx_irq_init(void); + +#endif /* _ASM_IRQ_GT641XX_H */ diff -puN include/asm-mips/jazz.h~git-mips include/asm-mips/jazz.h --- a/include/asm-mips/jazz.h~git-mips +++ a/include/asm-mips/jazz.h @@ -185,37 +185,25 @@ typedef struct { #define JAZZ_IO_IRQ_ENABLE 0xe0010002 /* - * JAZZ interrupt enable bits - */ -#define JAZZ_IE_PARALLEL (1 << 0) -#define JAZZ_IE_FLOPPY (1 << 1) -#define JAZZ_IE_SOUND (1 << 2) -#define JAZZ_IE_VIDEO (1 << 3) -#define JAZZ_IE_ETHERNET (1 << 4) -#define JAZZ_IE_SCSI (1 << 5) -#define JAZZ_IE_KEYBOARD (1 << 6) -#define JAZZ_IE_MOUSE (1 << 7) -#define JAZZ_IE_SERIAL1 (1 << 8) -#define JAZZ_IE_SERIAL2 (1 << 9) - -/* * JAZZ Interrupt Level definitions * * This is somewhat broken. For reasons which nobody can remember anymore * we remap the Jazz interrupts to the usual ISA style interrupt numbers. */ -#define JAZZ_PARALLEL_IRQ 16 -#define JAZZ_FLOPPY_IRQ 17 -#define JAZZ_SOUND_IRQ 18 -#define JAZZ_VIDEO_IRQ 19 -#define JAZZ_ETHERNET_IRQ 20 -#define JAZZ_SCSI_IRQ 21 -#define JAZZ_KEYBOARD_IRQ 22 -#define JAZZ_MOUSE_IRQ 23 -#define JAZZ_SERIAL1_IRQ 24 -#define JAZZ_SERIAL2_IRQ 25 +#define JAZZ_IRQ_START 24 +#define JAZZ_IRQ_END (24 + 9) +#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0) +#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1) +#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2) +#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3) +#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4) +#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5) +#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6) +#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7) +#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8) +#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9) -#define JAZZ_TIMER_IRQ 31 +#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) /* diff -puN include/asm-mips/jazzdma.h~git-mips include/asm-mips/jazzdma.h --- a/include/asm-mips/jazzdma.h~git-mips +++ a/include/asm-mips/jazzdma.h @@ -7,7 +7,6 @@ /* * Prototypes and macros */ -extern void vdma_init(void); extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); extern int vdma_free(unsigned long laddr); extern int vdma_remap(unsigned long laddr, unsigned long paddr, diff -puN /dev/null include/asm-mips/lasat/ds1603.h --- /dev/null +++ a/include/asm-mips/lasat/ds1603.h @@ -0,0 +1,18 @@ +#include + +/* Lasat 100 */ +#define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) +#define DS1603_RST_100 (1 << 2) +#define DS1603_CLK_100 (1 << 0) +#define DS1603_DATA_SHIFT_100 1 +#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) + +/* Lasat 200 */ +#define DS1603_REG_200 (KSEG1ADDR(0x11000000)) +#define DS1603_RST_200 (1 << 3) +#define DS1603_CLK_200 (1 << 4) +#define DS1603_DATA_200 (1 << 5) + +#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) +#define DS1603_DATA_READ_SHIFT_200 9 +#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) diff -puN /dev/null include/asm-mips/lasat/eeprom.h --- /dev/null +++ a/include/asm-mips/lasat/eeprom.h @@ -0,0 +1,17 @@ +#include + +/* lasat 100 */ +#define AT93C_REG_100 KSEG1ADDR(0x1c810000) +#define AT93C_RDATA_REG_100 AT93C_REG_100 +#define AT93C_RDATA_SHIFT_100 4 +#define AT93C_WDATA_SHIFT_100 4 +#define AT93C_CS_M_100 (1 << 5) +#define AT93C_CLK_M_100 (1 << 3) + +/* lasat 200 */ +#define AT93C_REG_200 KSEG1ADDR(0x11000000) +#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) +#define AT93C_RDATA_SHIFT_200 8 +#define AT93C_WDATA_SHIFT_200 2 +#define AT93C_CS_M_200 (1 << 0) +#define AT93C_CLK_M_200 (1 << 1) diff -puN /dev/null include/asm-mips/lasat/head.h --- /dev/null +++ a/include/asm-mips/lasat/head.h @@ -0,0 +1,22 @@ +/* + * Image header stuff + */ +#ifndef _HEAD_H +#define _HEAD_H + +#define LASAT_K_MAGIC0_VAL 0xfedeabba +#define LASAT_K_MAGIC1_VAL 0x00bedead + +#ifndef _LANGUAGE_ASSEMBLY +#include +struct bootloader_header { + u32 magic[2]; + u32 version; + u32 image_start; + u32 image_size; + u32 kernel_start; + u32 kernel_entry; +}; +#endif + +#endif /* _HEAD_H */ diff -puN /dev/null include/asm-mips/lasat/lasat.h --- /dev/null +++ a/include/asm-mips/lasat/lasat.h @@ -0,0 +1,256 @@ +/* + * lasat.h + * + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Configuration for LASAT boards, loads the appropriate include files. + */ +#ifndef _LASAT_H +#define _LASAT_H + +#ifndef _LANGUAGE_ASSEMBLY + +extern struct lasat_misc { + volatile u32 *reset_reg; + volatile u32 *flash_wp_reg; + u32 flash_wp_bit; +} *lasat_misc; + +enum lasat_mtdparts { + LASAT_MTD_BOOTLOADER, + LASAT_MTD_SERVICE, + LASAT_MTD_NORMAL, + LASAT_MTD_CONFIG, + LASAT_MTD_FS, + LASAT_MTD_LAST +}; + +/* + * The format of the data record in the EEPROM. + * See Documentation/LASAT/eeprom.txt for a detailed description + * of the fields in this struct, and the LASAT Hardware Configuration + * field specification for a detailed description of the config + * field. + */ +#include + +#define LASAT_EEPROM_VERSION 7 +struct lasat_eeprom_struct { + unsigned int version; + unsigned int cfg[3]; + unsigned char hwaddr[6]; + unsigned char print_partno[12]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[12]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[16]; + unsigned char pwdnull; + unsigned char vendid; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[11]; + unsigned char debugaccess; + unsigned short prid; + unsigned int serviceflag; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +struct lasat_eeprom_struct_pre7 { + unsigned int version; + unsigned int flags[3]; + unsigned char hwaddr0[6]; + unsigned char hwaddr1[6]; + unsigned char print_partno[9]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[9]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[24]; + unsigned char pwdnull; + unsigned char vendor; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[6]; + unsigned int writecount; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +/* Configuration descriptor encoding - see the doc for details */ + +#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf) +#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf) +#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf) +#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf) +#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf) +#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf) +#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf) + +#define LASAT_W1_EDHAC(v) (((v)) & 0xf) +#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1) +#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1) +#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1) +#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1) +#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1) +#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1) +#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1) +#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf) +#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf) +#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf) +#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf) + +/* Routines specific to LASAT boards */ + +#define LASAT_BMID_MASQUERADE2 0 +#define LASAT_BMID_MASQUERADEPRO 1 +#define LASAT_BMID_SAFEPIPE25 2 +#define LASAT_BMID_SAFEPIPE50 3 +#define LASAT_BMID_SAFEPIPE100 4 +#define LASAT_BMID_SAFEPIPE5000 5 +#define LASAT_BMID_SAFEPIPE7000 6 +#define LASAT_BMID_SAFEPIPE1000 7 +#if 0 +#define LASAT_BMID_SAFEPIPE30 7 +#define LASAT_BMID_SAFEPIPE5100 8 +#define LASAT_BMID_SAFEPIPE7100 9 +#endif +#define LASAT_BMID_UNKNOWN 0xf +#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */ + +#define LASAT_HAS_EDHAC (1 << 0) +#define LASAT_EDHAC_FAST (1 << 1) +#define LASAT_HAS_EADI (1 << 2) +#define LASAT_HAS_HIFN (1 << 3) +#define LASAT_HAS_ISDN (1 << 4) +#define LASAT_HAS_LEASEDLINE_IF (1 << 5) +#define LASAT_HAS_HDC (1 << 6) + +#define LASAT_PRID_MASQUERADE2 0 +#define LASAT_PRID_MASQUERADEPRO 1 +#define LASAT_PRID_SAFEPIPE25 2 +#define LASAT_PRID_SAFEPIPE50 3 +#define LASAT_PRID_SAFEPIPE100 4 +#define LASAT_PRID_SAFEPIPE5000 5 +#define LASAT_PRID_SAFEPIPE7000 6 +#define LASAT_PRID_SAFEPIPE30 7 +#define LASAT_PRID_SAFEPIPE5100 8 +#define LASAT_PRID_SAFEPIPE7100 9 + +#define LASAT_PRID_SAFEPIPE1110 10 +#define LASAT_PRID_SAFEPIPE3020 11 +#define LASAT_PRID_SAFEPIPE3030 12 +#define LASAT_PRID_SAFEPIPE5020 13 +#define LASAT_PRID_SAFEPIPE5030 14 +#define LASAT_PRID_SAFEPIPE1120 15 +#define LASAT_PRID_SAFEPIPE1130 16 +#define LASAT_PRID_SAFEPIPE6010 17 +#define LASAT_PRID_SAFEPIPE6110 18 +#define LASAT_PRID_SAFEPIPE6210 19 +#define LASAT_PRID_SAFEPIPE1020 20 +#define LASAT_PRID_SAFEPIPE1040 21 +#define LASAT_PRID_SAFEPIPE1060 22 + +struct lasat_info { + unsigned int li_cpu_hz; + unsigned int li_bus_hz; + unsigned int li_bmid; + unsigned int li_memsize; + unsigned int li_flash_size; + unsigned int li_prid; + unsigned char li_bmstr[16]; + unsigned char li_namestr[32]; + unsigned char li_typestr[16]; + /* Info on the Flash layout */ + unsigned int li_flash_base; + unsigned long li_flashpart_base[LASAT_MTD_LAST]; + unsigned long li_flashpart_size[LASAT_MTD_LAST]; + struct lasat_eeprom_struct li_eeprom_info; + unsigned int li_eeprom_upgrade_version; + unsigned int li_debugaccess; +}; + +extern struct lasat_info lasat_board_info; + +static inline unsigned long lasat_flash_partition_start(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_base[partno]; +} + +static inline unsigned long lasat_flash_partition_size(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_size[partno]; +} + +/* Called from setup() to initialize the global board_info struct */ +extern int lasat_init_board_info(void); + +/* Write the modified EEPROM info struct */ +extern void lasat_write_eeprom_info(void); + +#define N_MACHTYPES 2 +/* for calibration of delays */ + +/* the lasat_ndelay function is necessary because it is used at an + * early stage of the boot process where ndelay is not calibrated. + * It is used for the bit-banging rtc and eeprom drivers */ + +#include + +/* calculating with the slowest board with 100 MHz clock */ +#define LASAT_100_DIVIDER 20 +/* All 200's run at 250 MHz clock */ +#define LASAT_200_DIVIDER 8 + +extern unsigned int lasat_ndelay_divider; + +static inline void lasat_ndelay(unsigned int ns) +{ + __delay(ns / lasat_ndelay_divider); +} + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef +#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba + +/* Lasat 100 boards */ +#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) + +/* Lasat 200 boards */ +#define Vrc5074_PHYS_BASE 0x1fa00000 +#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) +#define PCI_WINDOW1 0x1a000000 + +#endif /* _LASAT_H */ diff -puN /dev/null include/asm-mips/lasat/lasatint.h --- /dev/null +++ a/include/asm-mips/lasat/lasatint.h @@ -0,0 +1,12 @@ +#define LASATINT_END 16 + +/* lasat 100 */ +#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) +#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) +#define LASATINT_MASK_SHIFT_100 0 + +/* lasat 200 */ +#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASATINT_MASK_SHIFT_200 16 + diff -puN /dev/null include/asm-mips/lasat/picvue.h --- /dev/null +++ a/include/asm-mips/lasat/picvue.h @@ -0,0 +1,15 @@ +/* Lasat 100 */ +#define PVC_REG_100 KSEG1ADDR(0x1c820000) +#define PVC_DATA_SHIFT_100 0 +#define PVC_DATA_M_100 0xFF +#define PVC_E_100 (1 << 8) +#define PVC_RW_100 (1 << 9) +#define PVC_RS_100 (1 << 10) + +/* Lasat 200 */ +#define PVC_REG_200 KSEG1ADDR(0x11000000) +#define PVC_DATA_SHIFT_200 24 +#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) +#define PVC_E_200 (1 << 16) +#define PVC_RW_200 (1 << 17) +#define PVC_RS_200 (1 << 18) diff -puN /dev/null include/asm-mips/lasat/serial.h --- /dev/null +++ a/include/asm-mips/lasat/serial.h @@ -0,0 +1,13 @@ +#include + +/* Lasat 100 boards serial configuration */ +#define LASAT_BASE_BAUD_100 (7372800 / 16) +#define LASAT_UART_REGS_BASE_100 0x1c8b0000 +#define LASAT_UART_REGS_SHIFT_100 2 +#define LASATINT_UART_100 8 + +/* * LASAT 200 boards serial configuration */ +#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) +#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) +#define LASAT_UART_REGS_SHIFT_200 3 +#define LASATINT_UART_200 13 diff -puN include/asm-mips/linkage.h~git-mips include/asm-mips/linkage.h --- a/include/asm-mips/linkage.h~git-mips +++ a/include/asm-mips/linkage.h @@ -5,4 +5,6 @@ #include #endif +#define __weak __attribute__((weak)) + #endif diff -puN /dev/null include/asm-mips/mach-bcm947xx/bcm947xx.h --- /dev/null +++ a/include/asm-mips/mach-bcm947xx/bcm947xx.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2007 Aurelien Jarno + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_BCM947XX_H +#define __ASM_BCM947XX_H + +/* SSB bus */ +extern struct ssb_bus ssb_bcm947xx; + +extern void bcm947xx_time_init(void); + +#endif /* __ASM_BCM947XX_H */ diff -puN include/asm-mips/mach-cobalt/cobalt.h~git-mips include/asm-mips/mach-cobalt/cobalt.h --- a/include/asm-mips/mach-cobalt/cobalt.h~git-mips +++ a/include/asm-mips/mach-cobalt/cobalt.h @@ -12,32 +12,6 @@ #ifndef __ASM_COBALT_H #define __ASM_COBALT_H -#include - -/* - * i8259 legacy interrupts used on Cobalt: - * - * 8 - RTC - * 9 - PCI - * 14 - IDE0 - * 15 - IDE1 - */ -#define COBALT_QUBE_SLOT_IRQ 9 - -/* - * CPU IRQs are 16 ... 23 - */ -#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE - -#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) -#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ - /* * PCI configuration space manifest constants. These are wired into * the board layout according to the PCI spec to enable the software diff -puN include/asm-mips/mach-cobalt/cpu-feature-overrides.h~git-mips include/asm-mips/mach-cobalt/cpu-feature-overrides.h --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h~git-mips +++ a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -14,7 +14,6 @@ #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 #define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 diff -puN /dev/null include/asm-mips/mach-cobalt/irq.h --- /dev/null +++ a/include/asm-mips/mach-cobalt/irq.h @@ -0,0 +1,58 @@ +/* + * Cobalt IRQ definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997 Cobalt Microserver + * Copyright (C) 1997, 2003 Ralf Baechle + * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) + * Copyright (C) 2007 Yoichi Yuasa + */ +#ifndef _ASM_COBALT_IRQ_H +#define _ASM_COBALT_IRQ_H + +/* + * i8259 interrupts used on Cobalt: + * + * 8 - RTC + * 9 - PCI slot + * 14 - IDE0 + * 15 - IDE1(no connector on board) + */ +#define I8259A_IRQ_BASE 0 + +#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) + +/* + * CPU interrupts used on Cobalt: + * + * 0 - Software interrupt 0 (unused) + * 1 - Software interrupt 0 (unused) + * 2 - cascade GT64111 + * 3 - ethernet or SCSI host controller + * 4 - ethernet + * 5 - 16550 UART + * 6 - cascade i8259 + * 7 - CP0 counter (unused) + */ +#define MIPS_CPU_IRQ_BASE 16 + +#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) +#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) + + +#define GT641XX_IRQ_BASE 24 + +#include + +#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) + +#endif /* _ASM_COBALT_IRQ_H */ diff -puN include/asm-mips/mach-excite/cpu-feature-overrides.h~git-mips include/asm-mips/mach-excite/cpu-feature-overrides.h --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h~git-mips +++ a/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -34,6 +34,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff -puN include/asm-mips/mach-jazz/mc146818rtc.h~git-mips include/asm-mips/mach-jazz/mc146818rtc.h --- a/include/asm-mips/mach-jazz/mc146818rtc.h~git-mips +++ a/include/asm-mips/mach-jazz/mc146818rtc.h @@ -4,12 +4,15 @@ * for more details. * * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * Copyright (C) 2007 Thomas Bogendoerfer * * RTC routines for Jazz style attached Dallas chip. */ #ifndef __ASM_MACH_JAZZ_MC146818RTC_H #define __ASM_MACH_JAZZ_MC146818RTC_H +#include + #include #include @@ -19,16 +22,17 @@ static inline unsigned char CMOS_READ(unsigned long addr) { outb_p(addr, RTC_PORT(0)); - - return *(char *)JAZZ_RTC_BASE; + return *(volatile char *)JAZZ_RTC_BASE; } static inline void CMOS_WRITE(unsigned char data, unsigned long addr) { outb_p(addr, RTC_PORT(0)); - *(char *)JAZZ_RTC_BASE = data; + *(volatile char *)JAZZ_RTC_BASE = data; } #define RTC_ALWAYS_BCD 0 +#define mc146818_decode_year(year) ((year) + 1980) + #endif /* __ASM_MACH_JAZZ_MC146818RTC_H */ diff -puN /dev/null include/asm-mips/mach-lasat/mach-gt64120.h --- /dev/null +++ a/include/asm-mips/mach-lasat/mach-gt64120.h @@ -0,0 +1,27 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H +#define _ASM_GT64120_LASAT_GT64120_DEP_H + +/* + * GT64120 config space base address on Lasat 100 + */ +#define GT64120_BASE (KSEG1ADDR(0x14000000)) + +/* + * PCI Bus allocation + * + * (Guessing ...) + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff -puN include/asm-mips/mach-mips/mach-gt64120.h~git-mips include/asm-mips/mach-mips/mach-gt64120.h --- a/include/asm-mips/mach-mips/mach-gt64120.h~git-mips +++ a/include/asm-mips/mach-mips/mach-gt64120.h @@ -16,13 +16,4 @@ extern unsigned long _pcictrl_gt64120; */ #define GT64120_BASE _pcictrl_gt64120 -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff -puN include/asm-mips/mach-sibyte/cpu-feature-overrides.h~git-mips include/asm-mips/mach-sibyte/cpu-feature-overrides.h --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h~git-mips +++ a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -9,7 +9,7 @@ #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H /* - * Sibyte are MIPS64 processors weired to a specific configuration + * Sibyte are MIPS64 processors wired to a specific configuration */ #define cpu_has_watch 1 #define cpu_has_mips16 0 @@ -33,6 +33,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff -puN include/asm-mips/mach-wrppmc/mach-gt64120.h~git-mips include/asm-mips/mach-wrppmc/mach-gt64120.h --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h~git-mips +++ a/include/asm-mips/mach-wrppmc/mach-gt64120.h @@ -43,7 +43,6 @@ #define GT_PCI_MEM_SIZE 0x02000000UL #define GT_PCI_IO_BASE 0x11000000UL #define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE /* * PCI interrupts will come in on either the INTA or INTD interrups lines, diff -puN /dev/null include/asm-mips/nile4.h --- /dev/null +++ a/include/asm-mips/nile4.h @@ -0,0 +1,310 @@ +/* + * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + * + * This file is based on the following documentation: + * + * NEC Vrc 5074 System Controller Data Sheet, June 1998 + */ + +#ifndef _ASM_NILE4_H +#define _ASM_NILE4_H + +#define NILE4_BASE 0xbfa00000 +#define NILE4_SIZE 0x00200000 /* 2 MB */ + + + /* + * Physical Device Address Registers (PDARs) + */ + +#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ +#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ +#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ +#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ +#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ +#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ +#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ +#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ +#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ +#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ +#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ +#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ + /* [R/W] */ +#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ + + + /* + * CPU Interface Registers + */ + +#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ +#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ +#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ +#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ + /* Enable [R/W] */ +#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ +#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ + + + /* + * Memory-Interface Registers + */ + +#define NILE4_MEMCTRL 0x00C0 /* Memory Control */ +#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ +#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ + + + /* + * PCI-Bus Registers + */ + +#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ +#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ +#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ +#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ +#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ + + + /* + * Local-Bus Registers + */ + +#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ +#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ +#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ +#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ +#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ +#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ +#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ +#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ +#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ + /* Enables [R/W] */ +#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ +#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ + + + /* + * DMA Registers + */ + +#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ +#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ +#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ +#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ +#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ +#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ + + + /* + * Timer Registers + */ + +#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ +#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ +#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ +#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ +#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ +#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ +#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ +#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ + + + /* + * PCI Configuration Space Registers + */ + +#define NILE4_PCI_BASE 0x0200 + +#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ +#define NILE4_DID 0x0202 /* PCI Device ID [R] */ +#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ +#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ +#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ +#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ +#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ +#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ +#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ +#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ +#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ +#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ +#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ +#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ + /* (unimplemented) */ +#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ +#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ +#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ + /* (unimplemented) */ +#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ +#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ +#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ +#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ +#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ +#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ +#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ +#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ +#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ +#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ +#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ +#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ + + + /* + * Serial-Port Registers + */ + +#define NILE4_UART_BASE 0x0300 + +#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ +#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ +#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ +#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ +#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ +#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ +#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ +#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ +#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ +#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ +#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ +#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ + +#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ + + + /* + * Interrupt Lines + */ + +#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ +#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ +#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ +#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ +#define NILE4_INT_UART 4 /* UART Interrupt */ +#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ +#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ +#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ +#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ +#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ +#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ +#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ +#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ +#define NILE4_INT_RESV 13 /* Reserved */ +#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ +#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ + + + /* + * Nile 4 Register Access + */ + +static inline void nile4_sync(void) +{ + volatile u32 *p = (volatile u32 *)0xbfc00000; + (void)(*p); +} + +static inline void nile4_out32(u32 offset, u32 val) +{ + *(volatile u32 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u32 nile4_in32(u32 offset) +{ + u32 val = *(volatile u32 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out16(u32 offset, u16 val) +{ + *(volatile u16 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u16 nile4_in16(u32 offset) +{ + u16 val = *(volatile u16 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out8(u32 offset, u8 val) +{ + *(volatile u8 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u8 nile4_in8(u32 offset) +{ + u8 val = *(volatile u8 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + + + /* + * Physical Device Address Registers + */ + +extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, + int on_memory_bus, int visible); + + + /* + * PCI Master Registers + */ + +#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ +#define NILE4_PCICMD_IO 1 /* PCI I/O Space */ +#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ +#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ + + + /* + * PCI Address Spaces + * + * Note that these are multiplexed using PCIINIT[01]! + */ + +#define NILE4_PCI_IO_BASE 0xa6000000 +#define NILE4_PCI_MEM_BASE 0xa8000000 +#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE +#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE + + +extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); + + + /* + * Interrupt Programming + */ + +#define NUM_I8259_INTERRUPTS 16 +#define NUM_NILE4_INTERRUPTS 16 + +#define IRQ_I8259_CASCADE NILE4_INT_INTE +#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) +#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) +#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) + +extern void nile4_map_irq(int nile4_irq, int cpu_irq); +extern void nile4_map_irq_all(int cpu_irq); +extern void nile4_enable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq_all(void); +extern u16 nile4_get_irq_stat(int cpu_irq); +extern void nile4_enable_irq_output(int cpu_irq); +extern void nile4_disable_irq_output(int cpu_irq); +extern void nile4_set_pci_irq_polarity(int pci_irq, int high); +extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); +extern void nile4_clear_irq(int nile4_irq); +extern void nile4_clear_irq_mask(u32 mask); +extern u8 nile4_i8259_iack(void); +extern void nile4_dump_irq_status(void); /* Debug */ + +#endif + diff -puN include/asm-mips/pci.h~git-mips include/asm-mips/pci.h --- a/include/asm-mips/pci.h~git-mips +++ a/include/asm-mips/pci.h @@ -150,8 +150,6 @@ pcibios_select_root(struct pci_dev *pdev return root; } -#ifdef CONFIG_PCI_DOMAINS - #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) @@ -160,8 +158,6 @@ static inline int pci_proc_domain(struct return hose->need_domain_info; } -#endif /* CONFIG_PCI_DOMAINS */ - #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ diff -puN include/asm-mips/smtc_ipi.h~git-mips include/asm-mips/smtc_ipi.h --- a/include/asm-mips/smtc_ipi.h~git-mips +++ a/include/asm-mips/smtc_ipi.h @@ -34,6 +34,7 @@ struct smtc_ipi { #define LINUX_SMP_IPI 1 #define SMTC_CLOCK_TICK 2 +#define IRQ_AFFINITY_IPI 3 /* * A queue of IPI messages diff -puN include/asm-mips/tx4927/toshiba_rbtx4927.h~git-mips include/asm-mips/tx4927/toshiba_rbtx4927.h --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h~git-mips +++ a/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -28,24 +28,20 @@ #define __ASM_TX4927_TOSHIBA_RBTX4927_H #include -#include #ifdef CONFIG_PCI #include #endif -#define TOSHIBA_RBTX4927_WR08(a,b) do { TX4927_WR08(a,b); wbflush(); } while ( 0 ) - - #ifdef CONFIG_PCI #define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO #else #define TBTX4927_ISA_IO_OFFSET 0 #endif -#define RBTX4927_SW_RESET_DO 0xbc00f000 +#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL #define RBTX4927_SW_RESET_DO_SET 0x01 -#define RBTX4927_SW_RESET_ENABLE 0xbc00f002 +#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 diff -puN include/asm-mips/tx4927/tx4927.h~git-mips include/asm-mips/tx4927/tx4927.h --- a/include/asm-mips/tx4927/tx4927.h~git-mips +++ a/include/asm-mips/tx4927/tx4927.h @@ -27,447 +27,8 @@ #ifndef __ASM_TX4927_TX4927_H #define __ASM_TX4927_TX4927_H -#include #include -/* - This register naming came from the integrated CPU/controller name TX4927 - followed by the device name from table 4.2.2 on page 4-3 and then followed - by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul - used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". - */ - -#define TX4927_SIO_0_BASE - -/* TX4927 controller */ -#define TX4927_BASE 0xfff1f0000 -#define TX4927_BASE 0xfff1f0000 -#define TX4927_LIMIT 0xfff1fffff - - -/* TX4927 SDRAM controller (64-bit registers) */ -#define TX4927_SDRAMC_BASE 0x8000 -#define TX4927_SDRAMC_SDCCR0 0x8000 -#define TX4927_SDRAMC_SDCCR1 0x8008 -#define TX4927_SDRAMC_SDCCR2 0x8010 -#define TX4927_SDRAMC_SDCCR3 0x8018 -#define TX4927_SDRAMC_SDCTR 0x8040 -#define TX4927_SDRAMC_SDCMD 0x8058 -#define TX4927_SDRAMC_LIMIT 0x8fff - - -/* TX4927 external bus controller (64-bit registers) */ -#define TX4927_EBUSC_BASE 0x9000 -#define TX4927_EBUSC_EBCCR0 0x9000 -#define TX4927_EBUSC_EBCCR1 0x9008 -#define TX4927_EBUSC_EBCCR2 0x9010 -#define TX4927_EBUSC_EBCCR3 0x9018 -#define TX4927_EBUSC_EBCCR4 0x9020 -#define TX4927_EBUSC_EBCCR5 0x9028 -#define TX4927_EBUSC_EBCCR6 0x9030 -#define TX4927_EBUSC_EBCCR7 0x9008 -#define TX4927_EBUSC_LIMIT 0x9fff - - -/* TX4927 SDRRAM Error Check Correction (64-bit registers) */ -#define TX4927_ECC_BASE 0xa000 -#define TX4927_ECC_ECCCR 0xa000 -#define TX4927_ECC_ECCSR 0xa008 -#define TX4927_ECC_LIMIT 0xafff - - -/* TX4927 DMA Controller (64-bit registers) */ -#define TX4927_DMAC_BASE 0xb000 -#define TX4927_DMAC_TBD 0xb000 -#define TX4927_DMAC_LIMIT 0xbfff - - -/* TX4927 PCI Controller (32-bit registers) */ -#define TX4927_PCIC_BASE 0xd000 -#define TX4927_PCIC_TBD 0xb000 -#define TX4927_PCIC_LIMIT 0xdfff - - -/* TX4927 Configuration registers (64-bit registers) */ -#define TX4927_CONFIG_BASE 0xe000 -#define TX4927_CONFIG_CCFG 0xe000 -#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 -#define TX4927_CONFIG_CCFG_WDRST BM_41_41 -#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 -#define TX4927_CONFIG_CCFG_BCFG BM_39_32 -#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27 -#define TX4927_CONFIG_CCFG_GTOT BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26 -#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25 -#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25) -#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24 -#define TX4927_CONFIG_CCFG_PCI66 BM_23_23 -#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22 -#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20 -#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19 -#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17) -#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18 -#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17) -#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17 -#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18 -#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17 -#define TX4927_CONFIG_CCFG_BEOW BM_16_16 -#define TX4927_CONFIG_CCFG_WR BM_15_15 -#define TX4927_CONFIG_CCFG_TOE BM_14_14 -#define TX4927_CONFIG_CCFG_PCIARB BM_13_13 -#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11 -#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08 -#define TX4927_CONFIG_CCFG_SYSSP BM_07_06 -#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03 -#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 -#define TX4927_CONFIG_CCFG_ARMODE BM_01_01 -#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 -#define TX4927_CONFIG_REVID 0xe008 -#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 -#define TX4927_CONFIG_REVID_PCODE BM_16_31 -#define TX4927_CONFIG_REVID_MJERREV BM_12_15 -#define TX4927_CONFIG_REVID_MINEREV BM_08_11 -#define TX4927_CONFIG_REVID_MJREV BM_04_07 -#define TX4927_CONFIG_REVID_MINREV BM_00_03 -#define TX4927_CONFIG_PCFG 0xe010 -#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 -#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 -#define TX4927_CONFIG_PCFG_DRVCB BM_55_55 -#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54 -#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53 -#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52 -#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51 -#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50 -#define TX4927_CONFIG_PCFG_DRVWE BM_49_49 -#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48 -#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47 -#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k -#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45 -#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44 -#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43 -#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42 -#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41 -#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40 -#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39 -#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32 -#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31 -#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29) -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29 -#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27 -#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26 -#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25 -#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24 -#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23 -#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22 -#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21 -#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20 -#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19 -#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18 -#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17 -#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16 -#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_PCFG_SEL2 BM_09_09 -#define TX4927_CONFIG_PCFG_SEL1 BM_08_08 -#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03) -#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01 -#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01) -#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 -#define TX4927_CONFIG_TOEA 0xe018 -#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 -#define TX4927_CONFIG_TOEA_TOEA BM_00_35 -#define TX4927_CONFIG_CLKCTR 0xe020 -#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 -#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 -#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 -#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23 -#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22 -#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21 -#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20 -#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19 -#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18 -#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17 -#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16 -#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09 -#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08 -#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07 -#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06 -#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05 -#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04 -#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03 -#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 -#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 -#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 -#define TX4927_CONFIG_GARBC 0xe030 -#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 -#define TX4927_CONFIG_GARBC_SET_09 BM_09_09 -#define TX4927_CONFIG_GARBC_ARBMD BM_08_08 -#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07 -#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05) -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03) -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01) -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 -#define TX4927_CONFIG_RAMP 0xe048 -#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 -#define TX4927_CONFIG_RAMP_RAMP BM_00_19 -#define TX4927_CONFIG_LIMIT 0xefff - - -/* TX4927 Timer 0 (32-bit registers) */ -#define TX4927_TMR0_BASE 0xf000 -#define TX4927_TMR0_TMTCR0 0xf000 -#define TX4927_TMR0_TMTISR0 0xf004 -#define TX4927_TMR0_TMCPRA0 0xf008 -#define TX4927_TMR0_TMCPRB0 0xf00c -#define TX4927_TMR0_TMITMR0 0xf010 -#define TX4927_TMR0_TMCCDR0 0xf020 -#define TX4927_TMR0_TMPGMR0 0xf030 -#define TX4927_TMR0_TMTRR0 0xf0f0 -#define TX4927_TMR0_LIMIT 0xf0ff - - -/* TX4927 Timer 1 (32-bit registers) */ -#define TX4927_TMR1_BASE 0xf100 -#define TX4927_TMR1_TMTCR1 0xf100 -#define TX4927_TMR1_TMTISR1 0xf104 -#define TX4927_TMR1_TMCPRA1 0xf108 -#define TX4927_TMR1_TMCPRB1 0xf10c -#define TX4927_TMR1_TMITMR1 0xf110 -#define TX4927_TMR1_TMCCDR1 0xf120 -#define TX4927_TMR1_TMPGMR1 0xf130 -#define TX4927_TMR1_TMTRR1 0xf1f0 -#define TX4927_TMR1_LIMIT 0xf1ff - - -/* TX4927 Timer 2 (32-bit registers) */ -#define TX4927_TMR2_BASE 0xf200 -#define TX4927_TMR2_TMTCR2 0xf200 -#define TX4927_TMR2_TMTISR2 0xf204 -#define TX4927_TMR2_TMCPRA2 0xf208 -#define TX4927_TMR2_TMITMR2 0xf210 -#define TX4927_TMR2_TMCCDR2 0xf220 -#define TX4927_TMR2_TMWTMR2 0xf240 -#define TX4927_TMR2_TMTRR2 0xf2f0 -#define TX4927_TMR2_LIMIT 0xf2ff - - -/* TX4927 serial port 0 (32-bit registers) */ -#define TX4927_SIO0_BASE 0xf300 -#define TX4927_SIO0_SILCR0 0xf300 -#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SILCR0_RWUB BM_15_15 -#define TX4927_SIO0_SILCR0_TWUB BM_14_14 -#define TX4927_SIO0_SILCR0_UODE BM_13_13 -#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12 -#define TX4927_SIO0_SILCR0_SCS BM_05_06 -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06) -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05 -#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06 -#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06 -#define TX4927_SIO0_SILCR0_UEPS BM_04_04 -#define TX4927_SIO0_SILCR0_UPEN BM_03_03 -#define TX4927_SIO0_SILCR0_USBL BM_02_02 -#define TX4927_SIO0_SILCR0_UMODE BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 -#define TX4927_SIO0_SIDICR0 0xf304 -#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDICR0_TDE BM_15_15 -#define TX4927_SIO0_SIDICR0_RDE BM_14_14 -#define TX4927_SIO0_SIDICR0_TIE BM_13_13 -#define TX4927_SIO0_SIDICR0_RIE BM_12_12 -#define TX4927_SIO0_SIDICR0_SPIE BM_11_11 -#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10 -#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10) -#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09 -#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10 -#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10 -#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08 -#define TX4927_SIO0_SIDICR0_STIE BM_00_05 -#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05) -#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05 -#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04 -#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03 -#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 -#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 -#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 -#define TX4927_SIO0_SIDISR0 0xf308 -#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDISR0_UBRK BM_15_15 -#define TX4927_SIO0_SIDISR0_UVALID BM_14_14 -#define TX4927_SIO0_SIDISR0_UFER BM_13_13 -#define TX4927_SIO0_SIDISR0_UPER BM_12_12 -#define TX4927_SIO0_SIDISR0_UOER BM_11_11 -#define TX4927_SIO0_SIDISR0_ERI BM_10_10 -#define TX4927_SIO0_SIDISR0_TOUT BM_09_09 -#define TX4927_SIO0_SIDISR0_TDIS BM_08_08 -#define TX4927_SIO0_SIDISR0_RDIS BM_07_07 -#define TX4927_SIO0_SIDISR0_STIS BM_06_06 -#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 -#define TX4927_SIO0_SIDISR0_RFDN BM_00_04 -#define TX4927_SIO0_SISCISR0 0xf30c -#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 -#define TX4927_SIO0_SISCISR0_OERS BM_05_05 -#define TX4927_SIO0_SISCISR0_CTSS BM_04_04 -#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03 -#define TX4927_SIO0_SISCISR0_TRDY BM_02_02 -#define TX4927_SIO0_SISCISR0_TXALS BM_01_01 -#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 -#define TX4927_SIO0_SIFCR0 0xf310 -#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIFCR0_SWRST BM_16_31 -#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 -#define TX4927_SIO0_SIFCR0_RDIL BM_16_31 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08) -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08 -#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFCR0_TDIL BM_03_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04) -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04 -#define TX4927_SIO0_SIFCR0_TFRST BM_02_02 -#define TX4927_SIO0_SIFCR0_RFRST BM_01_01 -#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 -#define TX4927_SIO0_SIFLCR0 0xf314 -#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 -#define TX4927_SIO0_SIFLCR0_RCS BM_12_12 -#define TX4927_SIO0_SIFLCR0_TES BM_11_11 -#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10 -#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09 -#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08 -#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07 -#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 -#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 -#define TX4927_SIO0_SIBGR0 0xf318 -#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 -#define TX4927_SIO0_SIBGR0_BCLK BM_08_09 -#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) -#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08 -#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 -#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 -#define TX4927_SIO0_SIBGR0_BRD BM_00_07 -#define TX4927_SIO0_SITFIF00 0xf31c -#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SITFIF00_TXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_LIMIT 0xf3ff - - -/* TX4927 serial port 1 (32-bit registers) */ -#define TX4927_SIO1_BASE 0xf400 -#define TX4927_SIO1_SILCR1 0xf400 -#define TX4927_SIO1_SIDICR1 0xf404 -#define TX4927_SIO1_SIDISR1 0xf408 -#define TX4927_SIO1_SISCISR1 0xf40c -#define TX4927_SIO1_SIFCR1 0xf410 -#define TX4927_SIO1_SIFLCR1 0xf414 -#define TX4927_SIO1_SIBGR1 0xf418 -#define TX4927_SIO1_SITFIF01 0xf41c -#define TX4927_SIO1_SIRFIFO1 0xf420 -#define TX4927_SIO1_LIMIT 0xf4ff - - -/* TX4927 parallel port (32-bit registers) */ -#define TX4927_PIO_BASE 0xf500 -#define TX4927_PIO_PIOD0 0xf500 -#define TX4927_PIO_PIODI 0xf504 -#define TX4927_PIO_PIODIR 0xf508 -#define TX4927_PIO_PIOOD 0xf50c -#define TX4927_PIO_LIMIT 0xf50f - - -/* TX4927 AC-link controller (32-bit registers) */ -#define TX4927_ACLC_BASE 0xf700 -#define TX4927_ACLC_ACCTLEN 0xf700 -#define TX4927_ACLC_ACCTLDIS 0xf704 -#define TX4927_ACLC_ACREGACC 0xf708 -#define TX4927_ACLC_ACINTSTS 0xf710 -#define TX4927_ACLC_ACINTMSTS 0xf714 -#define TX4927_ACLC_ACINTEN 0xf718 -#define TX4927_ACLC_ACINTDIS 0xf71c -#define TX4927_ACLC_ACSEMAPH 0xf720 -#define TX4927_ACLC_ACGPIDAT 0xf740 -#define TX4927_ACLC_ACGPODAT 0xf744 -#define TX4927_ACLC_ACSLTEN 0xf748 -#define TX4927_ACLC_ACSLTDIS 0xf74c -#define TX4927_ACLC_ACFIFOSTS 0xf750 -#define TX4927_ACLC_ACDMASTS 0xf780 -#define TX4927_ACLC_ACDMASEL 0xf784 -#define TX4927_ACLC_ACAUDODAT 0xf7a0 -#define TX4927_ACLC_ACSURRDAT 0xf7a4 -#define TX4927_ACLC_ACCENTDAT 0xf7a8 -#define TX4927_ACLC_ACLFEDAT 0xf7ac -#define TX4927_ACLC_ACAUDIDAT 0xf7b0 -#define TX4927_ACLC_ACMODODAT 0xf7b8 -#define TX4927_ACLC_ACMODIDAT 0xf7bc -#define TX4927_ACLC_ACREVID 0xf7fc -#define TX4927_ACLC_LIMIT 0xf7ff - - -#define TX4927_REG(x) ((TX4927_BASE)+(x)) - -#define TX4927_RD08( reg ) (*(vu08*)(reg)) -#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val)) - -#define TX4927_RD16( reg ) (*(vu16*)(reg)) -#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val)) - -#define TX4927_RD32( reg ) (*(vu32*)(reg)) -#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val)) - -#define TX4927_RD64( reg ) (*(vu64*)(reg)) -#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val)) - -#define TX4927_RD( reg ) TX4927_RD32( reg ) -#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) - - #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) diff -puN include/asm-mips/tx4927/tx4927_mips.h~git-mips /dev/null --- a/include/asm-mips/tx4927/tx4927_mips.h +++ /dev/null @@ -1,4177 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TX4927_MIPS_H -#define __ASM_TX4927_TX4927_MIPS_H - -#ifndef __ASSEMBLY__ - -static inline void asm_wait(void) -{ - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -#define reg_rd08(r) ((u8 )(*((vu8 *)(r)))) -#define reg_rd16(r) ((u16)(*((vu16*)(r)))) -#define reg_rd32(r) ((u32)(*((vu32*)(r)))) -#define reg_rd64(r) ((u64)(*((vu64*)(r)))) - -#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) - -typedef volatile __signed char vs8; -typedef volatile unsigned char vu8; - -typedef volatile __signed short vs16; -typedef volatile unsigned short vu16; - -typedef volatile __signed int vs32; -typedef volatile unsigned int vu32; - -typedef s8 s08; -typedef vs8 vs08; - -typedef u8 u08; -typedef vu8 vu08; - - -#if (_MIPS_SZLONG == 64) - -typedef volatile __signed__ long vs64; -typedef volatile unsigned long vu64; - -#else - -typedef volatile __signed__ long long vs64; -typedef volatile unsigned long long vu64; - -#endif - - -#define BM_00_00 0x0000000000000001 -#define BM_01_00 0x0000000000000003 -#define BM_00_01 BM_01_00 -#define BM_02_00 0x0000000000000007 -#define BM_00_02 BM_02_00 -#define BM_03_00 0x000000000000000f -#define BM_00_03 BM_03_00 -#define BM_04_00 0x000000000000001f -#define BM_00_04 BM_04_00 -#define BM_05_00 0x000000000000003f -#define BM_00_05 BM_05_00 -#define BM_06_00 0x000000000000007f -#define BM_00_06 BM_06_00 -#define BM_07_00 0x00000000000000ff -#define BM_00_07 BM_07_00 -#define BM_08_00 0x00000000000001ff -#define BM_00_08 BM_08_00 -#define BM_09_00 0x00000000000003ff -#define BM_00_09 BM_09_00 -#define BM_10_00 0x00000000000007ff -#define BM_00_10 BM_10_00 -#define BM_11_00 0x0000000000000fff -#define BM_00_11 BM_11_00 -#define BM_12_00 0x0000000000001fff -#define BM_00_12 BM_12_00 -#define BM_13_00 0x0000000000003fff -#define BM_00_13 BM_13_00 -#define BM_14_00 0x0000000000007fff -#define BM_00_14 BM_14_00 -#define BM_15_00 0x000000000000ffff -#define BM_00_15 BM_15_00 -#define BM_16_00 0x000000000001ffff -#define BM_00_16 BM_16_00 -#define BM_17_00 0x000000000003ffff -#define BM_00_17 BM_17_00 -#define BM_18_00 0x000000000007ffff -#define BM_00_18 BM_18_00 -#define BM_19_00 0x00000000000fffff -#define BM_00_19 BM_19_00 -#define BM_20_00 0x00000000001fffff -#define BM_00_20 BM_20_00 -#define BM_21_00 0x00000000003fffff -#define BM_00_21 BM_21_00 -#define BM_22_00 0x00000000007fffff -#define BM_00_22 BM_22_00 -#define BM_23_00 0x0000000000ffffff -#define BM_00_23 BM_23_00 -#define BM_24_00 0x0000000001ffffff -#define BM_00_24 BM_24_00 -#define BM_25_00 0x0000000003ffffff -#define BM_00_25 BM_25_00 -#define BM_26_00 0x0000000007ffffff -#define BM_00_26 BM_26_00 -#define BM_27_00 0x000000000fffffff -#define BM_00_27 BM_27_00 -#define BM_28_00 0x000000001fffffff -#define BM_00_28 BM_28_00 -#define BM_29_00 0x000000003fffffff -#define BM_00_29 BM_29_00 -#define BM_30_00 0x000000007fffffff -#define BM_00_30 BM_30_00 -#define BM_31_00 0x00000000ffffffff -#define BM_00_31 BM_31_00 -#define BM_32_00 0x00000001ffffffff -#define BM_00_32 BM_32_00 -#define BM_33_00 0x00000003ffffffff -#define BM_00_33 BM_33_00 -#define BM_34_00 0x00000007ffffffff -#define BM_00_34 BM_34_00 -#define BM_35_00 0x0000000fffffffff -#define BM_00_35 BM_35_00 -#define BM_36_00 0x0000001fffffffff -#define BM_00_36 BM_36_00 -#define BM_37_00 0x0000003fffffffff -#define BM_00_37 BM_37_00 -#define BM_38_00 0x0000007fffffffff -#define BM_00_38 BM_38_00 -#define BM_39_00 0x000000ffffffffff -#define BM_00_39 BM_39_00 -#define BM_40_00 0x000001ffffffffff -#define BM_00_40 BM_40_00 -#define BM_41_00 0x000003ffffffffff -#define BM_00_41 BM_41_00 -#define BM_42_00 0x000007ffffffffff -#define BM_00_42 BM_42_00 -#define BM_43_00 0x00000fffffffffff -#define BM_00_43 BM_43_00 -#define BM_44_00 0x00001fffffffffff -#define BM_00_44 BM_44_00 -#define BM_45_00 0x00003fffffffffff -#define BM_00_45 BM_45_00 -#define BM_46_00 0x00007fffffffffff -#define BM_00_46 BM_46_00 -#define BM_47_00 0x0000ffffffffffff -#define BM_00_47 BM_47_00 -#define BM_48_00 0x0001ffffffffffff -#define BM_00_48 BM_48_00 -#define BM_49_00 0x0003ffffffffffff -#define BM_00_49 BM_49_00 -#define BM_50_00 0x0007ffffffffffff -#define BM_00_50 BM_50_00 -#define BM_51_00 0x000fffffffffffff -#define BM_00_51 BM_51_00 -#define BM_52_00 0x001fffffffffffff -#define BM_00_52 BM_52_00 -#define BM_53_00 0x003fffffffffffff -#define BM_00_53 BM_53_00 -#define BM_54_00 0x007fffffffffffff -#define BM_00_54 BM_54_00 -#define BM_55_00 0x00ffffffffffffff -#define BM_00_55 BM_55_00 -#define BM_56_00 0x01ffffffffffffff -#define BM_00_56 BM_56_00 -#define BM_57_00 0x03ffffffffffffff -#define BM_00_57 BM_57_00 -#define BM_58_00 0x07ffffffffffffff -#define BM_00_58 BM_58_00 -#define BM_59_00 0x0fffffffffffffff -#define BM_00_59 BM_59_00 -#define BM_60_00 0x1fffffffffffffff -#define BM_00_60 BM_60_00 -#define BM_61_00 0x3fffffffffffffff -#define BM_00_61 BM_61_00 -#define BM_62_00 0x7fffffffffffffff -#define BM_00_62 BM_62_00 -#define BM_63_00 0xffffffffffffffff -#define BM_00_63 BM_63_00 -#define BM_01_01 0x0000000000000002 -#define BM_02_01 0x0000000000000006 -#define BM_01_02 BM_02_01 -#define BM_03_01 0x000000000000000e -#define BM_01_03 BM_03_01 -#define BM_04_01 0x000000000000001e -#define BM_01_04 BM_04_01 -#define BM_05_01 0x000000000000003e -#define BM_01_05 BM_05_01 -#define BM_06_01 0x000000000000007e -#define BM_01_06 BM_06_01 -#define BM_07_01 0x00000000000000fe -#define BM_01_07 BM_07_01 -#define BM_08_01 0x00000000000001fe -#define BM_01_08 BM_08_01 -#define BM_09_01 0x00000000000003fe -#define BM_01_09 BM_09_01 -#define BM_10_01 0x00000000000007fe -#define BM_01_10 BM_10_01 -#define BM_11_01 0x0000000000000ffe -#define BM_01_11 BM_11_01 -#define BM_12_01 0x0000000000001ffe -#define BM_01_12 BM_12_01 -#define BM_13_01 0x0000000000003ffe -#define BM_01_13 BM_13_01 -#define BM_14_01 0x0000000000007ffe -#define BM_01_14 BM_14_01 -#define BM_15_01 0x000000000000fffe -#define BM_01_15 BM_15_01 -#define BM_16_01 0x000000000001fffe -#define BM_01_16 BM_16_01 -#define BM_17_01 0x000000000003fffe -#define BM_01_17 BM_17_01 -#define BM_18_01 0x000000000007fffe -#define BM_01_18 BM_18_01 -#define BM_19_01 0x00000000000ffffe -#define BM_01_19 BM_19_01 -#define BM_20_01 0x00000000001ffffe -#define BM_01_20 BM_20_01 -#define BM_21_01 0x00000000003ffffe -#define BM_01_21 BM_21_01 -#define BM_22_01 0x00000000007ffffe -#define BM_01_22 BM_22_01 -#define BM_23_01 0x0000000000fffffe -#define BM_01_23 BM_23_01 -#define BM_24_01 0x0000000001fffffe -#define BM_01_24 BM_24_01 -#define BM_25_01 0x0000000003fffffe -#define BM_01_25 BM_25_01 -#define BM_26_01 0x0000000007fffffe -#define BM_01_26 BM_26_01 -#define BM_27_01 0x000000000ffffffe -#define BM_01_27 BM_27_01 -#define BM_28_01 0x000000001ffffffe -#define BM_01_28 BM_28_01 -#define BM_29_01 0x000000003ffffffe -#define BM_01_29 BM_29_01 -#define BM_30_01 0x000000007ffffffe -#define BM_01_30 BM_30_01 -#define BM_31_01 0x00000000fffffffe -#define BM_01_31 BM_31_01 -#define BM_32_01 0x00000001fffffffe -#define BM_01_32 BM_32_01 -#define BM_33_01 0x00000003fffffffe -#define BM_01_33 BM_33_01 -#define BM_34_01 0x00000007fffffffe -#define BM_01_34 BM_34_01 -#define BM_35_01 0x0000000ffffffffe -#define BM_01_35 BM_35_01 -#define BM_36_01 0x0000001ffffffffe -#define BM_01_36 BM_36_01 -#define BM_37_01 0x0000003ffffffffe -#define BM_01_37 BM_37_01 -#define BM_38_01 0x0000007ffffffffe -#define BM_01_38 BM_38_01 -#define BM_39_01 0x000000fffffffffe -#define BM_01_39 BM_39_01 -#define BM_40_01 0x000001fffffffffe -#define BM_01_40 BM_40_01 -#define BM_41_01 0x000003fffffffffe -#define BM_01_41 BM_41_01 -#define BM_42_01 0x000007fffffffffe -#define BM_01_42 BM_42_01 -#define BM_43_01 0x00000ffffffffffe -#define BM_01_43 BM_43_01 -#define BM_44_01 0x00001ffffffffffe -#define BM_01_44 BM_44_01 -#define BM_45_01 0x00003ffffffffffe -#define BM_01_45 BM_45_01 -#define BM_46_01 0x00007ffffffffffe -#define BM_01_46 BM_46_01 -#define BM_47_01 0x0000fffffffffffe -#define BM_01_47 BM_47_01 -#define BM_48_01 0x0001fffffffffffe -#define BM_01_48 BM_48_01 -#define BM_49_01 0x0003fffffffffffe -#define BM_01_49 BM_49_01 -#define BM_50_01 0x0007fffffffffffe -#define BM_01_50 BM_50_01 -#define BM_51_01 0x000ffffffffffffe -#define BM_01_51 BM_51_01 -#define BM_52_01 0x001ffffffffffffe -#define BM_01_52 BM_52_01 -#define BM_53_01 0x003ffffffffffffe -#define BM_01_53 BM_53_01 -#define BM_54_01 0x007ffffffffffffe -#define BM_01_54 BM_54_01 -#define BM_55_01 0x00fffffffffffffe -#define BM_01_55 BM_55_01 -#define BM_56_01 0x01fffffffffffffe -#define BM_01_56 BM_56_01 -#define BM_57_01 0x03fffffffffffffe -#define BM_01_57 BM_57_01 -#define BM_58_01 0x07fffffffffffffe -#define BM_01_58 BM_58_01 -#define BM_59_01 0x0ffffffffffffffe -#define BM_01_59 BM_59_01 -#define BM_60_01 0x1ffffffffffffffe -#define BM_01_60 BM_60_01 -#define BM_61_01 0x3ffffffffffffffe -#define BM_01_61 BM_61_01 -#define BM_62_01 0x7ffffffffffffffe -#define BM_01_62 BM_62_01 -#define BM_63_01 0xfffffffffffffffe -#define BM_01_63 BM_63_01 -#define BM_02_02 0x0000000000000004 -#define BM_03_02 0x000000000000000c -#define BM_02_03 BM_03_02 -#define BM_04_02 0x000000000000001c -#define BM_02_04 BM_04_02 -#define BM_05_02 0x000000000000003c -#define BM_02_05 BM_05_02 -#define BM_06_02 0x000000000000007c -#define BM_02_06 BM_06_02 -#define BM_07_02 0x00000000000000fc -#define BM_02_07 BM_07_02 -#define BM_08_02 0x00000000000001fc -#define BM_02_08 BM_08_02 -#define BM_09_02 0x00000000000003fc -#define BM_02_09 BM_09_02 -#define BM_10_02 0x00000000000007fc -#define BM_02_10 BM_10_02 -#define BM_11_02 0x0000000000000ffc -#define BM_02_11 BM_11_02 -#define BM_12_02 0x0000000000001ffc -#define BM_02_12 BM_12_02 -#define BM_13_02 0x0000000000003ffc -#define BM_02_13 BM_13_02 -#define BM_14_02 0x0000000000007ffc -#define BM_02_14 BM_14_02 -#define BM_15_02 0x000000000000fffc -#define BM_02_15 BM_15_02 -#define BM_16_02 0x000000000001fffc -#define BM_02_16 BM_16_02 -#define BM_17_02 0x000000000003fffc -#define BM_02_17 BM_17_02 -#define BM_18_02 0x000000000007fffc -#define BM_02_18 BM_18_02 -#define BM_19_02 0x00000000000ffffc -#define BM_02_19 BM_19_02 -#define BM_20_02 0x00000000001ffffc -#define BM_02_20 BM_20_02 -#define BM_21_02 0x00000000003ffffc -#define BM_02_21 BM_21_02 -#define BM_22_02 0x00000000007ffffc -#define BM_02_22 BM_22_02 -#define BM_23_02 0x0000000000fffffc -#define BM_02_23 BM_23_02 -#define BM_24_02 0x0000000001fffffc -#define BM_02_24 BM_24_02 -#define BM_25_02 0x0000000003fffffc -#define BM_02_25 BM_25_02 -#define BM_26_02 0x0000000007fffffc -#define BM_02_26 BM_26_02 -#define BM_27_02 0x000000000ffffffc -#define BM_02_27 BM_27_02 -#define BM_28_02 0x000000001ffffffc -#define BM_02_28 BM_28_02 -#define BM_29_02 0x000000003ffffffc -#define BM_02_29 BM_29_02 -#define BM_30_02 0x000000007ffffffc -#define BM_02_30 BM_30_02 -#define BM_31_02 0x00000000fffffffc -#define BM_02_31 BM_31_02 -#define BM_32_02 0x00000001fffffffc -#define BM_02_32 BM_32_02 -#define BM_33_02 0x00000003fffffffc -#define BM_02_33 BM_33_02 -#define BM_34_02 0x00000007fffffffc -#define BM_02_34 BM_34_02 -#define BM_35_02 0x0000000ffffffffc -#define BM_02_35 BM_35_02 -#define BM_36_02 0x0000001ffffffffc -#define BM_02_36 BM_36_02 -#define BM_37_02 0x0000003ffffffffc -#define BM_02_37 BM_37_02 -#define BM_38_02 0x0000007ffffffffc -#define BM_02_38 BM_38_02 -#define BM_39_02 0x000000fffffffffc -#define BM_02_39 BM_39_02 -#define BM_40_02 0x000001fffffffffc -#define BM_02_40 BM_40_02 -#define BM_41_02 0x000003fffffffffc -#define BM_02_41 BM_41_02 -#define BM_42_02 0x000007fffffffffc -#define BM_02_42 BM_42_02 -#define BM_43_02 0x00000ffffffffffc -#define BM_02_43 BM_43_02 -#define BM_44_02 0x00001ffffffffffc -#define BM_02_44 BM_44_02 -#define BM_45_02 0x00003ffffffffffc -#define BM_02_45 BM_45_02 -#define BM_46_02 0x00007ffffffffffc -#define BM_02_46 BM_46_02 -#define BM_47_02 0x0000fffffffffffc -#define BM_02_47 BM_47_02 -#define BM_48_02 0x0001fffffffffffc -#define BM_02_48 BM_48_02 -#define BM_49_02 0x0003fffffffffffc -#define BM_02_49 BM_49_02 -#define BM_50_02 0x0007fffffffffffc -#define BM_02_50 BM_50_02 -#define BM_51_02 0x000ffffffffffffc -#define BM_02_51 BM_51_02 -#define BM_52_02 0x001ffffffffffffc -#define BM_02_52 BM_52_02 -#define BM_53_02 0x003ffffffffffffc -#define BM_02_53 BM_53_02 -#define BM_54_02 0x007ffffffffffffc -#define BM_02_54 BM_54_02 -#define BM_55_02 0x00fffffffffffffc -#define BM_02_55 BM_55_02 -#define BM_56_02 0x01fffffffffffffc -#define BM_02_56 BM_56_02 -#define BM_57_02 0x03fffffffffffffc -#define BM_02_57 BM_57_02 -#define BM_58_02 0x07fffffffffffffc -#define BM_02_58 BM_58_02 -#define BM_59_02 0x0ffffffffffffffc -#define BM_02_59 BM_59_02 -#define BM_60_02 0x1ffffffffffffffc -#define BM_02_60 BM_60_02 -#define BM_61_02 0x3ffffffffffffffc -#define BM_02_61 BM_61_02 -#define BM_62_02 0x7ffffffffffffffc -#define BM_02_62 BM_62_02 -#define BM_63_02 0xfffffffffffffffc -#define BM_02_63 BM_63_02 -#define BM_03_03 0x0000000000000008 -#define BM_04_03 0x0000000000000018 -#define BM_03_04 BM_04_03 -#define BM_05_03 0x0000000000000038 -#define BM_03_05 BM_05_03 -#define BM_06_03 0x0000000000000078 -#define BM_03_06 BM_06_03 -#define BM_07_03 0x00000000000000f8 -#define BM_03_07 BM_07_03 -#define BM_08_03 0x00000000000001f8 -#define BM_03_08 BM_08_03 -#define BM_09_03 0x00000000000003f8 -#define BM_03_09 BM_09_03 -#define BM_10_03 0x00000000000007f8 -#define BM_03_10 BM_10_03 -#define BM_11_03 0x0000000000000ff8 -#define BM_03_11 BM_11_03 -#define BM_12_03 0x0000000000001ff8 -#define BM_03_12 BM_12_03 -#define BM_13_03 0x0000000000003ff8 -#define BM_03_13 BM_13_03 -#define BM_14_03 0x0000000000007ff8 -#define BM_03_14 BM_14_03 -#define BM_15_03 0x000000000000fff8 -#define BM_03_15 BM_15_03 -#define BM_16_03 0x000000000001fff8 -#define BM_03_16 BM_16_03 -#define BM_17_03 0x000000000003fff8 -#define BM_03_17 BM_17_03 -#define BM_18_03 0x000000000007fff8 -#define BM_03_18 BM_18_03 -#define BM_19_03 0x00000000000ffff8 -#define BM_03_19 BM_19_03 -#define BM_20_03 0x00000000001ffff8 -#define BM_03_20 BM_20_03 -#define BM_21_03 0x00000000003ffff8 -#define BM_03_21 BM_21_03 -#define BM_22_03 0x00000000007ffff8 -#define BM_03_22 BM_22_03 -#define BM_23_03 0x0000000000fffff8 -#define BM_03_23 BM_23_03 -#define BM_24_03 0x0000000001fffff8 -#define BM_03_24 BM_24_03 -#define BM_25_03 0x0000000003fffff8 -#define BM_03_25 BM_25_03 -#define BM_26_03 0x0000000007fffff8 -#define BM_03_26 BM_26_03 -#define BM_27_03 0x000000000ffffff8 -#define BM_03_27 BM_27_03 -#define BM_28_03 0x000000001ffffff8 -#define BM_03_28 BM_28_03 -#define BM_29_03 0x000000003ffffff8 -#define BM_03_29 BM_29_03 -#define BM_30_03 0x000000007ffffff8 -#define BM_03_30 BM_30_03 -#define BM_31_03 0x00000000fffffff8 -#define BM_03_31 BM_31_03 -#define BM_32_03 0x00000001fffffff8 -#define BM_03_32 BM_32_03 -#define BM_33_03 0x00000003fffffff8 -#define BM_03_33 BM_33_03 -#define BM_34_03 0x00000007fffffff8 -#define BM_03_34 BM_34_03 -#define BM_35_03 0x0000000ffffffff8 -#define BM_03_35 BM_35_03 -#define BM_36_03 0x0000001ffffffff8 -#define BM_03_36 BM_36_03 -#define BM_37_03 0x0000003ffffffff8 -#define BM_03_37 BM_37_03 -#define BM_38_03 0x0000007ffffffff8 -#define BM_03_38 BM_38_03 -#define BM_39_03 0x000000fffffffff8 -#define BM_03_39 BM_39_03 -#define BM_40_03 0x000001fffffffff8 -#define BM_03_40 BM_40_03 -#define BM_41_03 0x000003fffffffff8 -#define BM_03_41 BM_41_03 -#define BM_42_03 0x000007fffffffff8 -#define BM_03_42 BM_42_03 -#define BM_43_03 0x00000ffffffffff8 -#define BM_03_43 BM_43_03 -#define BM_44_03 0x00001ffffffffff8 -#define BM_03_44 BM_44_03 -#define BM_45_03 0x00003ffffffffff8 -#define BM_03_45 BM_45_03 -#define BM_46_03 0x00007ffffffffff8 -#define BM_03_46 BM_46_03 -#define BM_47_03 0x0000fffffffffff8 -#define BM_03_47 BM_47_03 -#define BM_48_03 0x0001fffffffffff8 -#define BM_03_48 BM_48_03 -#define BM_49_03 0x0003fffffffffff8 -#define BM_03_49 BM_49_03 -#define BM_50_03 0x0007fffffffffff8 -#define BM_03_50 BM_50_03 -#define BM_51_03 0x000ffffffffffff8 -#define BM_03_51 BM_51_03 -#define BM_52_03 0x001ffffffffffff8 -#define BM_03_52 BM_52_03 -#define BM_53_03 0x003ffffffffffff8 -#define BM_03_53 BM_53_03 -#define BM_54_03 0x007ffffffffffff8 -#define BM_03_54 BM_54_03 -#define BM_55_03 0x00fffffffffffff8 -#define BM_03_55 BM_55_03 -#define BM_56_03 0x01fffffffffffff8 -#define BM_03_56 BM_56_03 -#define BM_57_03 0x03fffffffffffff8 -#define BM_03_57 BM_57_03 -#define BM_58_03 0x07fffffffffffff8 -#define BM_03_58 BM_58_03 -#define BM_59_03 0x0ffffffffffffff8 -#define BM_03_59 BM_59_03 -#define BM_60_03 0x1ffffffffffffff8 -#define BM_03_60 BM_60_03 -#define BM_61_03 0x3ffffffffffffff8 -#define BM_03_61 BM_61_03 -#define BM_62_03 0x7ffffffffffffff8 -#define BM_03_62 BM_62_03 -#define BM_63_03 0xfffffffffffffff8 -#define BM_03_63 BM_63_03 -#define BM_04_04 0x0000000000000010 -#define BM_05_04 0x0000000000000030 -#define BM_04_05 BM_05_04 -#define BM_06_04 0x0000000000000070 -#define BM_04_06 BM_06_04 -#define BM_07_04 0x00000000000000f0 -#define BM_04_07 BM_07_04 -#define BM_08_04 0x00000000000001f0 -#define BM_04_08 BM_08_04 -#define BM_09_04 0x00000000000003f0 -#define BM_04_09 BM_09_04 -#define BM_10_04 0x00000000000007f0 -#define BM_04_10 BM_10_04 -#define BM_11_04 0x0000000000000ff0 -#define BM_04_11 BM_11_04 -#define BM_12_04 0x0000000000001ff0 -#define BM_04_12 BM_12_04 -#define BM_13_04 0x0000000000003ff0 -#define BM_04_13 BM_13_04 -#define BM_14_04 0x0000000000007ff0 -#define BM_04_14 BM_14_04 -#define BM_15_04 0x000000000000fff0 -#define BM_04_15 BM_15_04 -#define BM_16_04 0x000000000001fff0 -#define BM_04_16 BM_16_04 -#define BM_17_04 0x000000000003fff0 -#define BM_04_17 BM_17_04 -#define BM_18_04 0x000000000007fff0 -#define BM_04_18 BM_18_04 -#define BM_19_04 0x00000000000ffff0 -#define BM_04_19 BM_19_04 -#define BM_20_04 0x00000000001ffff0 -#define BM_04_20 BM_20_04 -#define BM_21_04 0x00000000003ffff0 -#define BM_04_21 BM_21_04 -#define BM_22_04 0x00000000007ffff0 -#define BM_04_22 BM_22_04 -#define BM_23_04 0x0000000000fffff0 -#define BM_04_23 BM_23_04 -#define BM_24_04 0x0000000001fffff0 -#define BM_04_24 BM_24_04 -#define BM_25_04 0x0000000003fffff0 -#define BM_04_25 BM_25_04 -#define BM_26_04 0x0000000007fffff0 -#define BM_04_26 BM_26_04 -#define BM_27_04 0x000000000ffffff0 -#define BM_04_27 BM_27_04 -#define BM_28_04 0x000000001ffffff0 -#define BM_04_28 BM_28_04 -#define BM_29_04 0x000000003ffffff0 -#define BM_04_29 BM_29_04 -#define BM_30_04 0x000000007ffffff0 -#define BM_04_30 BM_30_04 -#define BM_31_04 0x00000000fffffff0 -#define BM_04_31 BM_31_04 -#define BM_32_04 0x00000001fffffff0 -#define BM_04_32 BM_32_04 -#define BM_33_04 0x00000003fffffff0 -#define BM_04_33 BM_33_04 -#define BM_34_04 0x00000007fffffff0 -#define BM_04_34 BM_34_04 -#define BM_35_04 0x0000000ffffffff0 -#define BM_04_35 BM_35_04 -#define BM_36_04 0x0000001ffffffff0 -#define BM_04_36 BM_36_04 -#define BM_37_04 0x0000003ffffffff0 -#define BM_04_37 BM_37_04 -#define BM_38_04 0x0000007ffffffff0 -#define BM_04_38 BM_38_04 -#define BM_39_04 0x000000fffffffff0 -#define BM_04_39 BM_39_04 -#define BM_40_04 0x000001fffffffff0 -#define BM_04_40 BM_40_04 -#define BM_41_04 0x000003fffffffff0 -#define BM_04_41 BM_41_04 -#define BM_42_04 0x000007fffffffff0 -#define BM_04_42 BM_42_04 -#define BM_43_04 0x00000ffffffffff0 -#define BM_04_43 BM_43_04 -#define BM_44_04 0x00001ffffffffff0 -#define BM_04_44 BM_44_04 -#define BM_45_04 0x00003ffffffffff0 -#define BM_04_45 BM_45_04 -#define BM_46_04 0x00007ffffffffff0 -#define BM_04_46 BM_46_04 -#define BM_47_04 0x0000fffffffffff0 -#define BM_04_47 BM_47_04 -#define BM_48_04 0x0001fffffffffff0 -#define BM_04_48 BM_48_04 -#define BM_49_04 0x0003fffffffffff0 -#define BM_04_49 BM_49_04 -#define BM_50_04 0x0007fffffffffff0 -#define BM_04_50 BM_50_04 -#define BM_51_04 0x000ffffffffffff0 -#define BM_04_51 BM_51_04 -#define BM_52_04 0x001ffffffffffff0 -#define BM_04_52 BM_52_04 -#define BM_53_04 0x003ffffffffffff0 -#define BM_04_53 BM_53_04 -#define BM_54_04 0x007ffffffffffff0 -#define BM_04_54 BM_54_04 -#define BM_55_04 0x00fffffffffffff0 -#define BM_04_55 BM_55_04 -#define BM_56_04 0x01fffffffffffff0 -#define BM_04_56 BM_56_04 -#define BM_57_04 0x03fffffffffffff0 -#define BM_04_57 BM_57_04 -#define BM_58_04 0x07fffffffffffff0 -#define BM_04_58 BM_58_04 -#define BM_59_04 0x0ffffffffffffff0 -#define BM_04_59 BM_59_04 -#define BM_60_04 0x1ffffffffffffff0 -#define BM_04_60 BM_60_04 -#define BM_61_04 0x3ffffffffffffff0 -#define BM_04_61 BM_61_04 -#define BM_62_04 0x7ffffffffffffff0 -#define BM_04_62 BM_62_04 -#define BM_63_04 0xfffffffffffffff0 -#define BM_04_63 BM_63_04 -#define BM_05_05 0x0000000000000020 -#define BM_06_05 0x0000000000000060 -#define BM_05_06 BM_06_05 -#define BM_07_05 0x00000000000000e0 -#define BM_05_07 BM_07_05 -#define BM_08_05 0x00000000000001e0 -#define BM_05_08 BM_08_05 -#define BM_09_05 0x00000000000003e0 -#define BM_05_09 BM_09_05 -#define BM_10_05 0x00000000000007e0 -#define BM_05_10 BM_10_05 -#define BM_11_05 0x0000000000000fe0 -#define BM_05_11 BM_11_05 -#define BM_12_05 0x0000000000001fe0 -#define BM_05_12 BM_12_05 -#define BM_13_05 0x0000000000003fe0 -#define BM_05_13 BM_13_05 -#define BM_14_05 0x0000000000007fe0 -#define BM_05_14 BM_14_05 -#define BM_15_05 0x000000000000ffe0 -#define BM_05_15 BM_15_05 -#define BM_16_05 0x000000000001ffe0 -#define BM_05_16 BM_16_05 -#define BM_17_05 0x000000000003ffe0 -#define BM_05_17 BM_17_05 -#define BM_18_05 0x000000000007ffe0 -#define BM_05_18 BM_18_05 -#define BM_19_05 0x00000000000fffe0 -#define BM_05_19 BM_19_05 -#define BM_20_05 0x00000000001fffe0 -#define BM_05_20 BM_20_05 -#define BM_21_05 0x00000000003fffe0 -#define BM_05_21 BM_21_05 -#define BM_22_05 0x00000000007fffe0 -#define BM_05_22 BM_22_05 -#define BM_23_05 0x0000000000ffffe0 -#define BM_05_23 BM_23_05 -#define BM_24_05 0x0000000001ffffe0 -#define BM_05_24 BM_24_05 -#define BM_25_05 0x0000000003ffffe0 -#define BM_05_25 BM_25_05 -#define BM_26_05 0x0000000007ffffe0 -#define BM_05_26 BM_26_05 -#define BM_27_05 0x000000000fffffe0 -#define BM_05_27 BM_27_05 -#define BM_28_05 0x000000001fffffe0 -#define BM_05_28 BM_28_05 -#define BM_29_05 0x000000003fffffe0 -#define BM_05_29 BM_29_05 -#define BM_30_05 0x000000007fffffe0 -#define BM_05_30 BM_30_05 -#define BM_31_05 0x00000000ffffffe0 -#define BM_05_31 BM_31_05 -#define BM_32_05 0x00000001ffffffe0 -#define BM_05_32 BM_32_05 -#define BM_33_05 0x00000003ffffffe0 -#define BM_05_33 BM_33_05 -#define BM_34_05 0x00000007ffffffe0 -#define BM_05_34 BM_34_05 -#define BM_35_05 0x0000000fffffffe0 -#define BM_05_35 BM_35_05 -#define BM_36_05 0x0000001fffffffe0 -#define BM_05_36 BM_36_05 -#define BM_37_05 0x0000003fffffffe0 -#define BM_05_37 BM_37_05 -#define BM_38_05 0x0000007fffffffe0 -#define BM_05_38 BM_38_05 -#define BM_39_05 0x000000ffffffffe0 -#define BM_05_39 BM_39_05 -#define BM_40_05 0x000001ffffffffe0 -#define BM_05_40 BM_40_05 -#define BM_41_05 0x000003ffffffffe0 -#define BM_05_41 BM_41_05 -#define BM_42_05 0x000007ffffffffe0 -#define BM_05_42 BM_42_05 -#define BM_43_05 0x00000fffffffffe0 -#define BM_05_43 BM_43_05 -#define BM_44_05 0x00001fffffffffe0 -#define BM_05_44 BM_44_05 -#define BM_45_05 0x00003fffffffffe0 -#define BM_05_45 BM_45_05 -#define BM_46_05 0x00007fffffffffe0 -#define BM_05_46 BM_46_05 -#define BM_47_05 0x0000ffffffffffe0 -#define BM_05_47 BM_47_05 -#define BM_48_05 0x0001ffffffffffe0 -#define BM_05_48 BM_48_05 -#define BM_49_05 0x0003ffffffffffe0 -#define BM_05_49 BM_49_05 -#define BM_50_05 0x0007ffffffffffe0 -#define BM_05_50 BM_50_05 -#define BM_51_05 0x000fffffffffffe0 -#define BM_05_51 BM_51_05 -#define BM_52_05 0x001fffffffffffe0 -#define BM_05_52 BM_52_05 -#define BM_53_05 0x003fffffffffffe0 -#define BM_05_53 BM_53_05 -#define BM_54_05 0x007fffffffffffe0 -#define BM_05_54 BM_54_05 -#define BM_55_05 0x00ffffffffffffe0 -#define BM_05_55 BM_55_05 -#define BM_56_05 0x01ffffffffffffe0 -#define BM_05_56 BM_56_05 -#define BM_57_05 0x03ffffffffffffe0 -#define BM_05_57 BM_57_05 -#define BM_58_05 0x07ffffffffffffe0 -#define BM_05_58 BM_58_05 -#define BM_59_05 0x0fffffffffffffe0 -#define BM_05_59 BM_59_05 -#define BM_60_05 0x1fffffffffffffe0 -#define BM_05_60 BM_60_05 -#define BM_61_05 0x3fffffffffffffe0 -#define BM_05_61 BM_61_05 -#define BM_62_05 0x7fffffffffffffe0 -#define BM_05_62 BM_62_05 -#define BM_63_05 0xffffffffffffffe0 -#define BM_05_63 BM_63_05 -#define BM_06_06 0x0000000000000040 -#define BM_07_06 0x00000000000000c0 -#define BM_06_07 BM_07_06 -#define BM_08_06 0x00000000000001c0 -#define BM_06_08 BM_08_06 -#define BM_09_06 0x00000000000003c0 -#define BM_06_09 BM_09_06 -#define BM_10_06 0x00000000000007c0 -#define BM_06_10 BM_10_06 -#define BM_11_06 0x0000000000000fc0 -#define BM_06_11 BM_11_06 -#define BM_12_06 0x0000000000001fc0 -#define BM_06_12 BM_12_06 -#define BM_13_06 0x0000000000003fc0 -#define BM_06_13 BM_13_06 -#define BM_14_06 0x0000000000007fc0 -#define BM_06_14 BM_14_06 -#define BM_15_06 0x000000000000ffc0 -#define BM_06_15 BM_15_06 -#define BM_16_06 0x000000000001ffc0 -#define BM_06_16 BM_16_06 -#define BM_17_06 0x000000000003ffc0 -#define BM_06_17 BM_17_06 -#define BM_18_06 0x000000000007ffc0 -#define BM_06_18 BM_18_06 -#define BM_19_06 0x00000000000fffc0 -#define BM_06_19 BM_19_06 -#define BM_20_06 0x00000000001fffc0 -#define BM_06_20 BM_20_06 -#define BM_21_06 0x00000000003fffc0 -#define BM_06_21 BM_21_06 -#define BM_22_06 0x00000000007fffc0 -#define BM_06_22 BM_22_06 -#define BM_23_06 0x0000000000ffffc0 -#define BM_06_23 BM_23_06 -#define BM_24_06 0x0000000001ffffc0 -#define BM_06_24 BM_24_06 -#define BM_25_06 0x0000000003ffffc0 -#define BM_06_25 BM_25_06 -#define BM_26_06 0x0000000007ffffc0 -#define BM_06_26 BM_26_06 -#define BM_27_06 0x000000000fffffc0 -#define BM_06_27 BM_27_06 -#define BM_28_06 0x000000001fffffc0 -#define BM_06_28 BM_28_06 -#define BM_29_06 0x000000003fffffc0 -#define BM_06_29 BM_29_06 -#define BM_30_06 0x000000007fffffc0 -#define BM_06_30 BM_30_06 -#define BM_31_06 0x00000000ffffffc0 -#define BM_06_31 BM_31_06 -#define BM_32_06 0x00000001ffffffc0 -#define BM_06_32 BM_32_06 -#define BM_33_06 0x00000003ffffffc0 -#define BM_06_33 BM_33_06 -#define BM_34_06 0x00000007ffffffc0 -#define BM_06_34 BM_34_06 -#define BM_35_06 0x0000000fffffffc0 -#define BM_06_35 BM_35_06 -#define BM_36_06 0x0000001fffffffc0 -#define BM_06_36 BM_36_06 -#define BM_37_06 0x0000003fffffffc0 -#define BM_06_37 BM_37_06 -#define BM_38_06 0x0000007fffffffc0 -#define BM_06_38 BM_38_06 -#define BM_39_06 0x000000ffffffffc0 -#define BM_06_39 BM_39_06 -#define BM_40_06 0x000001ffffffffc0 -#define BM_06_40 BM_40_06 -#define BM_41_06 0x000003ffffffffc0 -#define BM_06_41 BM_41_06 -#define BM_42_06 0x000007ffffffffc0 -#define BM_06_42 BM_42_06 -#define BM_43_06 0x00000fffffffffc0 -#define BM_06_43 BM_43_06 -#define BM_44_06 0x00001fffffffffc0 -#define BM_06_44 BM_44_06 -#define BM_45_06 0x00003fffffffffc0 -#define BM_06_45 BM_45_06 -#define BM_46_06 0x00007fffffffffc0 -#define BM_06_46 BM_46_06 -#define BM_47_06 0x0000ffffffffffc0 -#define BM_06_47 BM_47_06 -#define BM_48_06 0x0001ffffffffffc0 -#define BM_06_48 BM_48_06 -#define BM_49_06 0x0003ffffffffffc0 -#define BM_06_49 BM_49_06 -#define BM_50_06 0x0007ffffffffffc0 -#define BM_06_50 BM_50_06 -#define BM_51_06 0x000fffffffffffc0 -#define BM_06_51 BM_51_06 -#define BM_52_06 0x001fffffffffffc0 -#define BM_06_52 BM_52_06 -#define BM_53_06 0x003fffffffffffc0 -#define BM_06_53 BM_53_06 -#define BM_54_06 0x007fffffffffffc0 -#define BM_06_54 BM_54_06 -#define BM_55_06 0x00ffffffffffffc0 -#define BM_06_55 BM_55_06 -#define BM_56_06 0x01ffffffffffffc0 -#define BM_06_56 BM_56_06 -#define BM_57_06 0x03ffffffffffffc0 -#define BM_06_57 BM_57_06 -#define BM_58_06 0x07ffffffffffffc0 -#define BM_06_58 BM_58_06 -#define BM_59_06 0x0fffffffffffffc0 -#define BM_06_59 BM_59_06 -#define BM_60_06 0x1fffffffffffffc0 -#define BM_06_60 BM_60_06 -#define BM_61_06 0x3fffffffffffffc0 -#define BM_06_61 BM_61_06 -#define BM_62_06 0x7fffffffffffffc0 -#define BM_06_62 BM_62_06 -#define BM_63_06 0xffffffffffffffc0 -#define BM_06_63 BM_63_06 -#define BM_07_07 0x0000000000000080 -#define BM_08_07 0x0000000000000180 -#define BM_07_08 BM_08_07 -#define BM_09_07 0x0000000000000380 -#define BM_07_09 BM_09_07 -#define BM_10_07 0x0000000000000780 -#define BM_07_10 BM_10_07 -#define BM_11_07 0x0000000000000f80 -#define BM_07_11 BM_11_07 -#define BM_12_07 0x0000000000001f80 -#define BM_07_12 BM_12_07 -#define BM_13_07 0x0000000000003f80 -#define BM_07_13 BM_13_07 -#define BM_14_07 0x0000000000007f80 -#define BM_07_14 BM_14_07 -#define BM_15_07 0x000000000000ff80 -#define BM_07_15 BM_15_07 -#define BM_16_07 0x000000000001ff80 -#define BM_07_16 BM_16_07 -#define BM_17_07 0x000000000003ff80 -#define BM_07_17 BM_17_07 -#define BM_18_07 0x000000000007ff80 -#define BM_07_18 BM_18_07 -#define BM_19_07 0x00000000000fff80 -#define BM_07_19 BM_19_07 -#define BM_20_07 0x00000000001fff80 -#define BM_07_20 BM_20_07 -#define BM_21_07 0x00000000003fff80 -#define BM_07_21 BM_21_07 -#define BM_22_07 0x00000000007fff80 -#define BM_07_22 BM_22_07 -#define BM_23_07 0x0000000000ffff80 -#define BM_07_23 BM_23_07 -#define BM_24_07 0x0000000001ffff80 -#define BM_07_24 BM_24_07 -#define BM_25_07 0x0000000003ffff80 -#define BM_07_25 BM_25_07 -#define BM_26_07 0x0000000007ffff80 -#define BM_07_26 BM_26_07 -#define BM_27_07 0x000000000fffff80 -#define BM_07_27 BM_27_07 -#define BM_28_07 0x000000001fffff80 -#define BM_07_28 BM_28_07 -#define BM_29_07 0x000000003fffff80 -#define BM_07_29 BM_29_07 -#define BM_30_07 0x000000007fffff80 -#define BM_07_30 BM_30_07 -#define BM_31_07 0x00000000ffffff80 -#define BM_07_31 BM_31_07 -#define BM_32_07 0x00000001ffffff80 -#define BM_07_32 BM_32_07 -#define BM_33_07 0x00000003ffffff80 -#define BM_07_33 BM_33_07 -#define BM_34_07 0x00000007ffffff80 -#define BM_07_34 BM_34_07 -#define BM_35_07 0x0000000fffffff80 -#define BM_07_35 BM_35_07 -#define BM_36_07 0x0000001fffffff80 -#define BM_07_36 BM_36_07 -#define BM_37_07 0x0000003fffffff80 -#define BM_07_37 BM_37_07 -#define BM_38_07 0x0000007fffffff80 -#define BM_07_38 BM_38_07 -#define BM_39_07 0x000000ffffffff80 -#define BM_07_39 BM_39_07 -#define BM_40_07 0x000001ffffffff80 -#define BM_07_40 BM_40_07 -#define BM_41_07 0x000003ffffffff80 -#define BM_07_41 BM_41_07 -#define BM_42_07 0x000007ffffffff80 -#define BM_07_42 BM_42_07 -#define BM_43_07 0x00000fffffffff80 -#define BM_07_43 BM_43_07 -#define BM_44_07 0x00001fffffffff80 -#define BM_07_44 BM_44_07 -#define BM_45_07 0x00003fffffffff80 -#define BM_07_45 BM_45_07 -#define BM_46_07 0x00007fffffffff80 -#define BM_07_46 BM_46_07 -#define BM_47_07 0x0000ffffffffff80 -#define BM_07_47 BM_47_07 -#define BM_48_07 0x0001ffffffffff80 -#define BM_07_48 BM_48_07 -#define BM_49_07 0x0003ffffffffff80 -#define BM_07_49 BM_49_07 -#define BM_50_07 0x0007ffffffffff80 -#define BM_07_50 BM_50_07 -#define BM_51_07 0x000fffffffffff80 -#define BM_07_51 BM_51_07 -#define BM_52_07 0x001fffffffffff80 -#define BM_07_52 BM_52_07 -#define BM_53_07 0x003fffffffffff80 -#define BM_07_53 BM_53_07 -#define BM_54_07 0x007fffffffffff80 -#define BM_07_54 BM_54_07 -#define BM_55_07 0x00ffffffffffff80 -#define BM_07_55 BM_55_07 -#define BM_56_07 0x01ffffffffffff80 -#define BM_07_56 BM_56_07 -#define BM_57_07 0x03ffffffffffff80 -#define BM_07_57 BM_57_07 -#define BM_58_07 0x07ffffffffffff80 -#define BM_07_58 BM_58_07 -#define BM_59_07 0x0fffffffffffff80 -#define BM_07_59 BM_59_07 -#define BM_60_07 0x1fffffffffffff80 -#define BM_07_60 BM_60_07 -#define BM_61_07 0x3fffffffffffff80 -#define BM_07_61 BM_61_07 -#define BM_62_07 0x7fffffffffffff80 -#define BM_07_62 BM_62_07 -#define BM_63_07 0xffffffffffffff80 -#define BM_07_63 BM_63_07 -#define BM_08_08 0x0000000000000100 -#define BM_09_08 0x0000000000000300 -#define BM_08_09 BM_09_08 -#define BM_10_08 0x0000000000000700 -#define BM_08_10 BM_10_08 -#define BM_11_08 0x0000000000000f00 -#define BM_08_11 BM_11_08 -#define BM_12_08 0x0000000000001f00 -#define BM_08_12 BM_12_08 -#define BM_13_08 0x0000000000003f00 -#define BM_08_13 BM_13_08 -#define BM_14_08 0x0000000000007f00 -#define BM_08_14 BM_14_08 -#define BM_15_08 0x000000000000ff00 -#define BM_08_15 BM_15_08 -#define BM_16_08 0x000000000001ff00 -#define BM_08_16 BM_16_08 -#define BM_17_08 0x000000000003ff00 -#define BM_08_17 BM_17_08 -#define BM_18_08 0x000000000007ff00 -#define BM_08_18 BM_18_08 -#define BM_19_08 0x00000000000fff00 -#define BM_08_19 BM_19_08 -#define BM_20_08 0x00000000001fff00 -#define BM_08_20 BM_20_08 -#define BM_21_08 0x00000000003fff00 -#define BM_08_21 BM_21_08 -#define BM_22_08 0x00000000007fff00 -#define BM_08_22 BM_22_08 -#define BM_23_08 0x0000000000ffff00 -#define BM_08_23 BM_23_08 -#define BM_24_08 0x0000000001ffff00 -#define BM_08_24 BM_24_08 -#define BM_25_08 0x0000000003ffff00 -#define BM_08_25 BM_25_08 -#define BM_26_08 0x0000000007ffff00 -#define BM_08_26 BM_26_08 -#define BM_27_08 0x000000000fffff00 -#define BM_08_27 BM_27_08 -#define BM_28_08 0x000000001fffff00 -#define BM_08_28 BM_28_08 -#define BM_29_08 0x000000003fffff00 -#define BM_08_29 BM_29_08 -#define BM_30_08 0x000000007fffff00 -#define BM_08_30 BM_30_08 -#define BM_31_08 0x00000000ffffff00 -#define BM_08_31 BM_31_08 -#define BM_32_08 0x00000001ffffff00 -#define BM_08_32 BM_32_08 -#define BM_33_08 0x00000003ffffff00 -#define BM_08_33 BM_33_08 -#define BM_34_08 0x00000007ffffff00 -#define BM_08_34 BM_34_08 -#define BM_35_08 0x0000000fffffff00 -#define BM_08_35 BM_35_08 -#define BM_36_08 0x0000001fffffff00 -#define BM_08_36 BM_36_08 -#define BM_37_08 0x0000003fffffff00 -#define BM_08_37 BM_37_08 -#define BM_38_08 0x0000007fffffff00 -#define BM_08_38 BM_38_08 -#define BM_39_08 0x000000ffffffff00 -#define BM_08_39 BM_39_08 -#define BM_40_08 0x000001ffffffff00 -#define BM_08_40 BM_40_08 -#define BM_41_08 0x000003ffffffff00 -#define BM_08_41 BM_41_08 -#define BM_42_08 0x000007ffffffff00 -#define BM_08_42 BM_42_08 -#define BM_43_08 0x00000fffffffff00 -#define BM_08_43 BM_43_08 -#define BM_44_08 0x00001fffffffff00 -#define BM_08_44 BM_44_08 -#define BM_45_08 0x00003fffffffff00 -#define BM_08_45 BM_45_08 -#define BM_46_08 0x00007fffffffff00 -#define BM_08_46 BM_46_08 -#define BM_47_08 0x0000ffffffffff00 -#define BM_08_47 BM_47_08 -#define BM_48_08 0x0001ffffffffff00 -#define BM_08_48 BM_48_08 -#define BM_49_08 0x0003ffffffffff00 -#define BM_08_49 BM_49_08 -#define BM_50_08 0x0007ffffffffff00 -#define BM_08_50 BM_50_08 -#define BM_51_08 0x000fffffffffff00 -#define BM_08_51 BM_51_08 -#define BM_52_08 0x001fffffffffff00 -#define BM_08_52 BM_52_08 -#define BM_53_08 0x003fffffffffff00 -#define BM_08_53 BM_53_08 -#define BM_54_08 0x007fffffffffff00 -#define BM_08_54 BM_54_08 -#define BM_55_08 0x00ffffffffffff00 -#define BM_08_55 BM_55_08 -#define BM_56_08 0x01ffffffffffff00 -#define BM_08_56 BM_56_08 -#define BM_57_08 0x03ffffffffffff00 -#define BM_08_57 BM_57_08 -#define BM_58_08 0x07ffffffffffff00 -#define BM_08_58 BM_58_08 -#define BM_59_08 0x0fffffffffffff00 -#define BM_08_59 BM_59_08 -#define BM_60_08 0x1fffffffffffff00 -#define BM_08_60 BM_60_08 -#define BM_61_08 0x3fffffffffffff00 -#define BM_08_61 BM_61_08 -#define BM_62_08 0x7fffffffffffff00 -#define BM_08_62 BM_62_08 -#define BM_63_08 0xffffffffffffff00 -#define BM_08_63 BM_63_08 -#define BM_09_09 0x0000000000000200 -#define BM_10_09 0x0000000000000600 -#define BM_09_10 BM_10_09 -#define BM_11_09 0x0000000000000e00 -#define BM_09_11 BM_11_09 -#define BM_12_09 0x0000000000001e00 -#define BM_09_12 BM_12_09 -#define BM_13_09 0x0000000000003e00 -#define BM_09_13 BM_13_09 -#define BM_14_09 0x0000000000007e00 -#define BM_09_14 BM_14_09 -#define BM_15_09 0x000000000000fe00 -#define BM_09_15 BM_15_09 -#define BM_16_09 0x000000000001fe00 -#define BM_09_16 BM_16_09 -#define BM_17_09 0x000000000003fe00 -#define BM_09_17 BM_17_09 -#define BM_18_09 0x000000000007fe00 -#define BM_09_18 BM_18_09 -#define BM_19_09 0x00000000000ffe00 -#define BM_09_19 BM_19_09 -#define BM_20_09 0x00000000001ffe00 -#define BM_09_20 BM_20_09 -#define BM_21_09 0x00000000003ffe00 -#define BM_09_21 BM_21_09 -#define BM_22_09 0x00000000007ffe00 -#define BM_09_22 BM_22_09 -#define BM_23_09 0x0000000000fffe00 -#define BM_09_23 BM_23_09 -#define BM_24_09 0x0000000001fffe00 -#define BM_09_24 BM_24_09 -#define BM_25_09 0x0000000003fffe00 -#define BM_09_25 BM_25_09 -#define BM_26_09 0x0000000007fffe00 -#define BM_09_26 BM_26_09 -#define BM_27_09 0x000000000ffffe00 -#define BM_09_27 BM_27_09 -#define BM_28_09 0x000000001ffffe00 -#define BM_09_28 BM_28_09 -#define BM_29_09 0x000000003ffffe00 -#define BM_09_29 BM_29_09 -#define BM_30_09 0x000000007ffffe00 -#define BM_09_30 BM_30_09 -#define BM_31_09 0x00000000fffffe00 -#define BM_09_31 BM_31_09 -#define BM_32_09 0x00000001fffffe00 -#define BM_09_32 BM_32_09 -#define BM_33_09 0x00000003fffffe00 -#define BM_09_33 BM_33_09 -#define BM_34_09 0x00000007fffffe00 -#define BM_09_34 BM_34_09 -#define BM_35_09 0x0000000ffffffe00 -#define BM_09_35 BM_35_09 -#define BM_36_09 0x0000001ffffffe00 -#define BM_09_36 BM_36_09 -#define BM_37_09 0x0000003ffffffe00 -#define BM_09_37 BM_37_09 -#define BM_38_09 0x0000007ffffffe00 -#define BM_09_38 BM_38_09 -#define BM_39_09 0x000000fffffffe00 -#define BM_09_39 BM_39_09 -#define BM_40_09 0x000001fffffffe00 -#define BM_09_40 BM_40_09 -#define BM_41_09 0x000003fffffffe00 -#define BM_09_41 BM_41_09 -#define BM_42_09 0x000007fffffffe00 -#define BM_09_42 BM_42_09 -#define BM_43_09 0x00000ffffffffe00 -#define BM_09_43 BM_43_09 -#define BM_44_09 0x00001ffffffffe00 -#define BM_09_44 BM_44_09 -#define BM_45_09 0x00003ffffffffe00 -#define BM_09_45 BM_45_09 -#define BM_46_09 0x00007ffffffffe00 -#define BM_09_46 BM_46_09 -#define BM_47_09 0x0000fffffffffe00 -#define BM_09_47 BM_47_09 -#define BM_48_09 0x0001fffffffffe00 -#define BM_09_48 BM_48_09 -#define BM_49_09 0x0003fffffffffe00 -#define BM_09_49 BM_49_09 -#define BM_50_09 0x0007fffffffffe00 -#define BM_09_50 BM_50_09 -#define BM_51_09 0x000ffffffffffe00 -#define BM_09_51 BM_51_09 -#define BM_52_09 0x001ffffffffffe00 -#define BM_09_52 BM_52_09 -#define BM_53_09 0x003ffffffffffe00 -#define BM_09_53 BM_53_09 -#define BM_54_09 0x007ffffffffffe00 -#define BM_09_54 BM_54_09 -#define BM_55_09 0x00fffffffffffe00 -#define BM_09_55 BM_55_09 -#define BM_56_09 0x01fffffffffffe00 -#define BM_09_56 BM_56_09 -#define BM_57_09 0x03fffffffffffe00 -#define BM_09_57 BM_57_09 -#define BM_58_09 0x07fffffffffffe00 -#define BM_09_58 BM_58_09 -#define BM_59_09 0x0ffffffffffffe00 -#define BM_09_59 BM_59_09 -#define BM_60_09 0x1ffffffffffffe00 -#define BM_09_60 BM_60_09 -#define BM_61_09 0x3ffffffffffffe00 -#define BM_09_61 BM_61_09 -#define BM_62_09 0x7ffffffffffffe00 -#define BM_09_62 BM_62_09 -#define BM_63_09 0xfffffffffffffe00 -#define BM_09_63 BM_63_09 -#define BM_10_10 0x0000000000000400 -#define BM_11_10 0x0000000000000c00 -#define BM_10_11 BM_11_10 -#define BM_12_10 0x0000000000001c00 -#define BM_10_12 BM_12_10 -#define BM_13_10 0x0000000000003c00 -#define BM_10_13 BM_13_10 -#define BM_14_10 0x0000000000007c00 -#define BM_10_14 BM_14_10 -#define BM_15_10 0x000000000000fc00 -#define BM_10_15 BM_15_10 -#define BM_16_10 0x000000000001fc00 -#define BM_10_16 BM_16_10 -#define BM_17_10 0x000000000003fc00 -#define BM_10_17 BM_17_10 -#define BM_18_10 0x000000000007fc00 -#define BM_10_18 BM_18_10 -#define BM_19_10 0x00000000000ffc00 -#define BM_10_19 BM_19_10 -#define BM_20_10 0x00000000001ffc00 -#define BM_10_20 BM_20_10 -#define BM_21_10 0x00000000003ffc00 -#define BM_10_21 BM_21_10 -#define BM_22_10 0x00000000007ffc00 -#define BM_10_22 BM_22_10 -#define BM_23_10 0x0000000000fffc00 -#define BM_10_23 BM_23_10 -#define BM_24_10 0x0000000001fffc00 -#define BM_10_24 BM_24_10 -#define BM_25_10 0x0000000003fffc00 -#define BM_10_25 BM_25_10 -#define BM_26_10 0x0000000007fffc00 -#define BM_10_26 BM_26_10 -#define BM_27_10 0x000000000ffffc00 -#define BM_10_27 BM_27_10 -#define BM_28_10 0x000000001ffffc00 -#define BM_10_28 BM_28_10 -#define BM_29_10 0x000000003ffffc00 -#define BM_10_29 BM_29_10 -#define BM_30_10 0x000000007ffffc00 -#define BM_10_30 BM_30_10 -#define BM_31_10 0x00000000fffffc00 -#define BM_10_31 BM_31_10 -#define BM_32_10 0x00000001fffffc00 -#define BM_10_32 BM_32_10 -#define BM_33_10 0x00000003fffffc00 -#define BM_10_33 BM_33_10 -#define BM_34_10 0x00000007fffffc00 -#define BM_10_34 BM_34_10 -#define BM_35_10 0x0000000ffffffc00 -#define BM_10_35 BM_35_10 -#define BM_36_10 0x0000001ffffffc00 -#define BM_10_36 BM_36_10 -#define BM_37_10 0x0000003ffffffc00 -#define BM_10_37 BM_37_10 -#define BM_38_10 0x0000007ffffffc00 -#define BM_10_38 BM_38_10 -#define BM_39_10 0x000000fffffffc00 -#define BM_10_39 BM_39_10 -#define BM_40_10 0x000001fffffffc00 -#define BM_10_40 BM_40_10 -#define BM_41_10 0x000003fffffffc00 -#define BM_10_41 BM_41_10 -#define BM_42_10 0x000007fffffffc00 -#define BM_10_42 BM_42_10 -#define BM_43_10 0x00000ffffffffc00 -#define BM_10_43 BM_43_10 -#define BM_44_10 0x00001ffffffffc00 -#define BM_10_44 BM_44_10 -#define BM_45_10 0x00003ffffffffc00 -#define BM_10_45 BM_45_10 -#define BM_46_10 0x00007ffffffffc00 -#define BM_10_46 BM_46_10 -#define BM_47_10 0x0000fffffffffc00 -#define BM_10_47 BM_47_10 -#define BM_48_10 0x0001fffffffffc00 -#define BM_10_48 BM_48_10 -#define BM_49_10 0x0003fffffffffc00 -#define BM_10_49 BM_49_10 -#define BM_50_10 0x0007fffffffffc00 -#define BM_10_50 BM_50_10 -#define BM_51_10 0x000ffffffffffc00 -#define BM_10_51 BM_51_10 -#define BM_52_10 0x001ffffffffffc00 -#define BM_10_52 BM_52_10 -#define BM_53_10 0x003ffffffffffc00 -#define BM_10_53 BM_53_10 -#define BM_54_10 0x007ffffffffffc00 -#define BM_10_54 BM_54_10 -#define BM_55_10 0x00fffffffffffc00 -#define BM_10_55 BM_55_10 -#define BM_56_10 0x01fffffffffffc00 -#define BM_10_56 BM_56_10 -#define BM_57_10 0x03fffffffffffc00 -#define BM_10_57 BM_57_10 -#define BM_58_10 0x07fffffffffffc00 -#define BM_10_58 BM_58_10 -#define BM_59_10 0x0ffffffffffffc00 -#define BM_10_59 BM_59_10 -#define BM_60_10 0x1ffffffffffffc00 -#define BM_10_60 BM_60_10 -#define BM_61_10 0x3ffffffffffffc00 -#define BM_10_61 BM_61_10 -#define BM_62_10 0x7ffffffffffffc00 -#define BM_10_62 BM_62_10 -#define BM_63_10 0xfffffffffffffc00 -#define BM_10_63 BM_63_10 -#define BM_11_11 0x0000000000000800 -#define BM_12_11 0x0000000000001800 -#define BM_11_12 BM_12_11 -#define BM_13_11 0x0000000000003800 -#define BM_11_13 BM_13_11 -#define BM_14_11 0x0000000000007800 -#define BM_11_14 BM_14_11 -#define BM_15_11 0x000000000000f800 -#define BM_11_15 BM_15_11 -#define BM_16_11 0x000000000001f800 -#define BM_11_16 BM_16_11 -#define BM_17_11 0x000000000003f800 -#define BM_11_17 BM_17_11 -#define BM_18_11 0x000000000007f800 -#define BM_11_18 BM_18_11 -#define BM_19_11 0x00000000000ff800 -#define BM_11_19 BM_19_11 -#define BM_20_11 0x00000000001ff800 -#define BM_11_20 BM_20_11 -#define BM_21_11 0x00000000003ff800 -#define BM_11_21 BM_21_11 -#define BM_22_11 0x00000000007ff800 -#define BM_11_22 BM_22_11 -#define BM_23_11 0x0000000000fff800 -#define BM_11_23 BM_23_11 -#define BM_24_11 0x0000000001fff800 -#define BM_11_24 BM_24_11 -#define BM_25_11 0x0000000003fff800 -#define BM_11_25 BM_25_11 -#define BM_26_11 0x0000000007fff800 -#define BM_11_26 BM_26_11 -#define BM_27_11 0x000000000ffff800 -#define BM_11_27 BM_27_11 -#define BM_28_11 0x000000001ffff800 -#define BM_11_28 BM_28_11 -#define BM_29_11 0x000000003ffff800 -#define BM_11_29 BM_29_11 -#define BM_30_11 0x000000007ffff800 -#define BM_11_30 BM_30_11 -#define BM_31_11 0x00000000fffff800 -#define BM_11_31 BM_31_11 -#define BM_32_11 0x00000001fffff800 -#define BM_11_32 BM_32_11 -#define BM_33_11 0x00000003fffff800 -#define BM_11_33 BM_33_11 -#define BM_34_11 0x00000007fffff800 -#define BM_11_34 BM_34_11 -#define BM_35_11 0x0000000ffffff800 -#define BM_11_35 BM_35_11 -#define BM_36_11 0x0000001ffffff800 -#define BM_11_36 BM_36_11 -#define BM_37_11 0x0000003ffffff800 -#define BM_11_37 BM_37_11 -#define BM_38_11 0x0000007ffffff800 -#define BM_11_38 BM_38_11 -#define BM_39_11 0x000000fffffff800 -#define BM_11_39 BM_39_11 -#define BM_40_11 0x000001fffffff800 -#define BM_11_40 BM_40_11 -#define BM_41_11 0x000003fffffff800 -#define BM_11_41 BM_41_11 -#define BM_42_11 0x000007fffffff800 -#define BM_11_42 BM_42_11 -#define BM_43_11 0x00000ffffffff800 -#define BM_11_43 BM_43_11 -#define BM_44_11 0x00001ffffffff800 -#define BM_11_44 BM_44_11 -#define BM_45_11 0x00003ffffffff800 -#define BM_11_45 BM_45_11 -#define BM_46_11 0x00007ffffffff800 -#define BM_11_46 BM_46_11 -#define BM_47_11 0x0000fffffffff800 -#define BM_11_47 BM_47_11 -#define BM_48_11 0x0001fffffffff800 -#define BM_11_48 BM_48_11 -#define BM_49_11 0x0003fffffffff800 -#define BM_11_49 BM_49_11 -#define BM_50_11 0x0007fffffffff800 -#define BM_11_50 BM_50_11 -#define BM_51_11 0x000ffffffffff800 -#define BM_11_51 BM_51_11 -#define BM_52_11 0x001ffffffffff800 -#define BM_11_52 BM_52_11 -#define BM_53_11 0x003ffffffffff800 -#define BM_11_53 BM_53_11 -#define BM_54_11 0x007ffffffffff800 -#define BM_11_54 BM_54_11 -#define BM_55_11 0x00fffffffffff800 -#define BM_11_55 BM_55_11 -#define BM_56_11 0x01fffffffffff800 -#define BM_11_56 BM_56_11 -#define BM_57_11 0x03fffffffffff800 -#define BM_11_57 BM_57_11 -#define BM_58_11 0x07fffffffffff800 -#define BM_11_58 BM_58_11 -#define BM_59_11 0x0ffffffffffff800 -#define BM_11_59 BM_59_11 -#define BM_60_11 0x1ffffffffffff800 -#define BM_11_60 BM_60_11 -#define BM_61_11 0x3ffffffffffff800 -#define BM_11_61 BM_61_11 -#define BM_62_11 0x7ffffffffffff800 -#define BM_11_62 BM_62_11 -#define BM_63_11 0xfffffffffffff800 -#define BM_11_63 BM_63_11 -#define BM_12_12 0x0000000000001000 -#define BM_13_12 0x0000000000003000 -#define BM_12_13 BM_13_12 -#define BM_14_12 0x0000000000007000 -#define BM_12_14 BM_14_12 -#define BM_15_12 0x000000000000f000 -#define BM_12_15 BM_15_12 -#define BM_16_12 0x000000000001f000 -#define BM_12_16 BM_16_12 -#define BM_17_12 0x000000000003f000 -#define BM_12_17 BM_17_12 -#define BM_18_12 0x000000000007f000 -#define BM_12_18 BM_18_12 -#define BM_19_12 0x00000000000ff000 -#define BM_12_19 BM_19_12 -#define BM_20_12 0x00000000001ff000 -#define BM_12_20 BM_20_12 -#define BM_21_12 0x00000000003ff000 -#define BM_12_21 BM_21_12 -#define BM_22_12 0x00000000007ff000 -#define BM_12_22 BM_22_12 -#define BM_23_12 0x0000000000fff000 -#define BM_12_23 BM_23_12 -#define BM_24_12 0x0000000001fff000 -#define BM_12_24 BM_24_12 -#define BM_25_12 0x0000000003fff000 -#define BM_12_25 BM_25_12 -#define BM_26_12 0x0000000007fff000 -#define BM_12_26 BM_26_12 -#define BM_27_12 0x000000000ffff000 -#define BM_12_27 BM_27_12 -#define BM_28_12 0x000000001ffff000 -#define BM_12_28 BM_28_12 -#define BM_29_12 0x000000003ffff000 -#define BM_12_29 BM_29_12 -#define BM_30_12 0x000000007ffff000 -#define BM_12_30 BM_30_12 -#define BM_31_12 0x00000000fffff000 -#define BM_12_31 BM_31_12 -#define BM_32_12 0x00000001fffff000 -#define BM_12_32 BM_32_12 -#define BM_33_12 0x00000003fffff000 -#define BM_12_33 BM_33_12 -#define BM_34_12 0x00000007fffff000 -#define BM_12_34 BM_34_12 -#define BM_35_12 0x0000000ffffff000 -#define BM_12_35 BM_35_12 -#define BM_36_12 0x0000001ffffff000 -#define BM_12_36 BM_36_12 -#define BM_37_12 0x0000003ffffff000 -#define BM_12_37 BM_37_12 -#define BM_38_12 0x0000007ffffff000 -#define BM_12_38 BM_38_12 -#define BM_39_12 0x000000fffffff000 -#define BM_12_39 BM_39_12 -#define BM_40_12 0x000001fffffff000 -#define BM_12_40 BM_40_12 -#define BM_41_12 0x000003fffffff000 -#define BM_12_41 BM_41_12 -#define BM_42_12 0x000007fffffff000 -#define BM_12_42 BM_42_12 -#define BM_43_12 0x00000ffffffff000 -#define BM_12_43 BM_43_12 -#define BM_44_12 0x00001ffffffff000 -#define BM_12_44 BM_44_12 -#define BM_45_12 0x00003ffffffff000 -#define BM_12_45 BM_45_12 -#define BM_46_12 0x00007ffffffff000 -#define BM_12_46 BM_46_12 -#define BM_47_12 0x0000fffffffff000 -#define BM_12_47 BM_47_12 -#define BM_48_12 0x0001fffffffff000 -#define BM_12_48 BM_48_12 -#define BM_49_12 0x0003fffffffff000 -#define BM_12_49 BM_49_12 -#define BM_50_12 0x0007fffffffff000 -#define BM_12_50 BM_50_12 -#define BM_51_12 0x000ffffffffff000 -#define BM_12_51 BM_51_12 -#define BM_52_12 0x001ffffffffff000 -#define BM_12_52 BM_52_12 -#define BM_53_12 0x003ffffffffff000 -#define BM_12_53 BM_53_12 -#define BM_54_12 0x007ffffffffff000 -#define BM_12_54 BM_54_12 -#define BM_55_12 0x00fffffffffff000 -#define BM_12_55 BM_55_12 -#define BM_56_12 0x01fffffffffff000 -#define BM_12_56 BM_56_12 -#define BM_57_12 0x03fffffffffff000 -#define BM_12_57 BM_57_12 -#define BM_58_12 0x07fffffffffff000 -#define BM_12_58 BM_58_12 -#define BM_59_12 0x0ffffffffffff000 -#define BM_12_59 BM_59_12 -#define BM_60_12 0x1ffffffffffff000 -#define BM_12_60 BM_60_12 -#define BM_61_12 0x3ffffffffffff000 -#define BM_12_61 BM_61_12 -#define BM_62_12 0x7ffffffffffff000 -#define BM_12_62 BM_62_12 -#define BM_63_12 0xfffffffffffff000 -#define BM_12_63 BM_63_12 -#define BM_13_13 0x0000000000002000 -#define BM_14_13 0x0000000000006000 -#define BM_13_14 BM_14_13 -#define BM_15_13 0x000000000000e000 -#define BM_13_15 BM_15_13 -#define BM_16_13 0x000000000001e000 -#define BM_13_16 BM_16_13 -#define BM_17_13 0x000000000003e000 -#define BM_13_17 BM_17_13 -#define BM_18_13 0x000000000007e000 -#define BM_13_18 BM_18_13 -#define BM_19_13 0x00000000000fe000 -#define BM_13_19 BM_19_13 -#define BM_20_13 0x00000000001fe000 -#define BM_13_20 BM_20_13 -#define BM_21_13 0x00000000003fe000 -#define BM_13_21 BM_21_13 -#define BM_22_13 0x00000000007fe000 -#define BM_13_22 BM_22_13 -#define BM_23_13 0x0000000000ffe000 -#define BM_13_23 BM_23_13 -#define BM_24_13 0x0000000001ffe000 -#define BM_13_24 BM_24_13 -#define BM_25_13 0x0000000003ffe000 -#define BM_13_25 BM_25_13 -#define BM_26_13 0x0000000007ffe000 -#define BM_13_26 BM_26_13 -#define BM_27_13 0x000000000fffe000 -#define BM_13_27 BM_27_13 -#define BM_28_13 0x000000001fffe000 -#define BM_13_28 BM_28_13 -#define BM_29_13 0x000000003fffe000 -#define BM_13_29 BM_29_13 -#define BM_30_13 0x000000007fffe000 -#define BM_13_30 BM_30_13 -#define BM_31_13 0x00000000ffffe000 -#define BM_13_31 BM_31_13 -#define BM_32_13 0x00000001ffffe000 -#define BM_13_32 BM_32_13 -#define BM_33_13 0x00000003ffffe000 -#define BM_13_33 BM_33_13 -#define BM_34_13 0x00000007ffffe000 -#define BM_13_34 BM_34_13 -#define BM_35_13 0x0000000fffffe000 -#define BM_13_35 BM_35_13 -#define BM_36_13 0x0000001fffffe000 -#define BM_13_36 BM_36_13 -#define BM_37_13 0x0000003fffffe000 -#define BM_13_37 BM_37_13 -#define BM_38_13 0x0000007fffffe000 -#define BM_13_38 BM_38_13 -#define BM_39_13 0x000000ffffffe000 -#define BM_13_39 BM_39_13 -#define BM_40_13 0x000001ffffffe000 -#define BM_13_40 BM_40_13 -#define BM_41_13 0x000003ffffffe000 -#define BM_13_41 BM_41_13 -#define BM_42_13 0x000007ffffffe000 -#define BM_13_42 BM_42_13 -#define BM_43_13 0x00000fffffffe000 -#define BM_13_43 BM_43_13 -#define BM_44_13 0x00001fffffffe000 -#define BM_13_44 BM_44_13 -#define BM_45_13 0x00003fffffffe000 -#define BM_13_45 BM_45_13 -#define BM_46_13 0x00007fffffffe000 -#define BM_13_46 BM_46_13 -#define BM_47_13 0x0000ffffffffe000 -#define BM_13_47 BM_47_13 -#define BM_48_13 0x0001ffffffffe000 -#define BM_13_48 BM_48_13 -#define BM_49_13 0x0003ffffffffe000 -#define BM_13_49 BM_49_13 -#define BM_50_13 0x0007ffffffffe000 -#define BM_13_50 BM_50_13 -#define BM_51_13 0x000fffffffffe000 -#define BM_13_51 BM_51_13 -#define BM_52_13 0x001fffffffffe000 -#define BM_13_52 BM_52_13 -#define BM_53_13 0x003fffffffffe000 -#define BM_13_53 BM_53_13 -#define BM_54_13 0x007fffffffffe000 -#define BM_13_54 BM_54_13 -#define BM_55_13 0x00ffffffffffe000 -#define BM_13_55 BM_55_13 -#define BM_56_13 0x01ffffffffffe000 -#define BM_13_56 BM_56_13 -#define BM_57_13 0x03ffffffffffe000 -#define BM_13_57 BM_57_13 -#define BM_58_13 0x07ffffffffffe000 -#define BM_13_58 BM_58_13 -#define BM_59_13 0x0fffffffffffe000 -#define BM_13_59 BM_59_13 -#define BM_60_13 0x1fffffffffffe000 -#define BM_13_60 BM_60_13 -#define BM_61_13 0x3fffffffffffe000 -#define BM_13_61 BM_61_13 -#define BM_62_13 0x7fffffffffffe000 -#define BM_13_62 BM_62_13 -#define BM_63_13 0xffffffffffffe000 -#define BM_13_63 BM_63_13 -#define BM_14_14 0x0000000000004000 -#define BM_15_14 0x000000000000c000 -#define BM_14_15 BM_15_14 -#define BM_16_14 0x000000000001c000 -#define BM_14_16 BM_16_14 -#define BM_17_14 0x000000000003c000 -#define BM_14_17 BM_17_14 -#define BM_18_14 0x000000000007c000 -#define BM_14_18 BM_18_14 -#define BM_19_14 0x00000000000fc000 -#define BM_14_19 BM_19_14 -#define BM_20_14 0x00000000001fc000 -#define BM_14_20 BM_20_14 -#define BM_21_14 0x00000000003fc000 -#define BM_14_21 BM_21_14 -#define BM_22_14 0x00000000007fc000 -#define BM_14_22 BM_22_14 -#define BM_23_14 0x0000000000ffc000 -#define BM_14_23 BM_23_14 -#define BM_24_14 0x0000000001ffc000 -#define BM_14_24 BM_24_14 -#define BM_25_14 0x0000000003ffc000 -#define BM_14_25 BM_25_14 -#define BM_26_14 0x0000000007ffc000 -#define BM_14_26 BM_26_14 -#define BM_27_14 0x000000000fffc000 -#define BM_14_27 BM_27_14 -#define BM_28_14 0x000000001fffc000 -#define BM_14_28 BM_28_14 -#define BM_29_14 0x000000003fffc000 -#define BM_14_29 BM_29_14 -#define BM_30_14 0x000000007fffc000 -#define BM_14_30 BM_30_14 -#define BM_31_14 0x00000000ffffc000 -#define BM_14_31 BM_31_14 -#define BM_32_14 0x00000001ffffc000 -#define BM_14_32 BM_32_14 -#define BM_33_14 0x00000003ffffc000 -#define BM_14_33 BM_33_14 -#define BM_34_14 0x00000007ffffc000 -#define BM_14_34 BM_34_14 -#define BM_35_14 0x0000000fffffc000 -#define BM_14_35 BM_35_14 -#define BM_36_14 0x0000001fffffc000 -#define BM_14_36 BM_36_14 -#define BM_37_14 0x0000003fffffc000 -#define BM_14_37 BM_37_14 -#define BM_38_14 0x0000007fffffc000 -#define BM_14_38 BM_38_14 -#define BM_39_14 0x000000ffffffc000 -#define BM_14_39 BM_39_14 -#define BM_40_14 0x000001ffffffc000 -#define BM_14_40 BM_40_14 -#define BM_41_14 0x000003ffffffc000 -#define BM_14_41 BM_41_14 -#define BM_42_14 0x000007ffffffc000 -#define BM_14_42 BM_42_14 -#define BM_43_14 0x00000fffffffc000 -#define BM_14_43 BM_43_14 -#define BM_44_14 0x00001fffffffc000 -#define BM_14_44 BM_44_14 -#define BM_45_14 0x00003fffffffc000 -#define BM_14_45 BM_45_14 -#define BM_46_14 0x00007fffffffc000 -#define BM_14_46 BM_46_14 -#define BM_47_14 0x0000ffffffffc000 -#define BM_14_47 BM_47_14 -#define BM_48_14 0x0001ffffffffc000 -#define BM_14_48 BM_48_14 -#define BM_49_14 0x0003ffffffffc000 -#define BM_14_49 BM_49_14 -#define BM_50_14 0x0007ffffffffc000 -#define BM_14_50 BM_50_14 -#define BM_51_14 0x000fffffffffc000 -#define BM_14_51 BM_51_14 -#define BM_52_14 0x001fffffffffc000 -#define BM_14_52 BM_52_14 -#define BM_53_14 0x003fffffffffc000 -#define BM_14_53 BM_53_14 -#define BM_54_14 0x007fffffffffc000 -#define BM_14_54 BM_54_14 -#define BM_55_14 0x00ffffffffffc000 -#define BM_14_55 BM_55_14 -#define BM_56_14 0x01ffffffffffc000 -#define BM_14_56 BM_56_14 -#define BM_57_14 0x03ffffffffffc000 -#define BM_14_57 BM_57_14 -#define BM_58_14 0x07ffffffffffc000 -#define BM_14_58 BM_58_14 -#define BM_59_14 0x0fffffffffffc000 -#define BM_14_59 BM_59_14 -#define BM_60_14 0x1fffffffffffc000 -#define BM_14_60 BM_60_14 -#define BM_61_14 0x3fffffffffffc000 -#define BM_14_61 BM_61_14 -#define BM_62_14 0x7fffffffffffc000 -#define BM_14_62 BM_62_14 -#define BM_63_14 0xffffffffffffc000 -#define BM_14_63 BM_63_14 -#define BM_15_15 0x0000000000008000 -#define BM_16_15 0x0000000000018000 -#define BM_15_16 BM_16_15 -#define BM_17_15 0x0000000000038000 -#define BM_15_17 BM_17_15 -#define BM_18_15 0x0000000000078000 -#define BM_15_18 BM_18_15 -#define BM_19_15 0x00000000000f8000 -#define BM_15_19 BM_19_15 -#define BM_20_15 0x00000000001f8000 -#define BM_15_20 BM_20_15 -#define BM_21_15 0x00000000003f8000 -#define BM_15_21 BM_21_15 -#define BM_22_15 0x00000000007f8000 -#define BM_15_22 BM_22_15 -#define BM_23_15 0x0000000000ff8000 -#define BM_15_23 BM_23_15 -#define BM_24_15 0x0000000001ff8000 -#define BM_15_24 BM_24_15 -#define BM_25_15 0x0000000003ff8000 -#define BM_15_25 BM_25_15 -#define BM_26_15 0x0000000007ff8000 -#define BM_15_26 BM_26_15 -#define BM_27_15 0x000000000fff8000 -#define BM_15_27 BM_27_15 -#define BM_28_15 0x000000001fff8000 -#define BM_15_28 BM_28_15 -#define BM_29_15 0x000000003fff8000 -#define BM_15_29 BM_29_15 -#define BM_30_15 0x000000007fff8000 -#define BM_15_30 BM_30_15 -#define BM_31_15 0x00000000ffff8000 -#define BM_15_31 BM_31_15 -#define BM_32_15 0x00000001ffff8000 -#define BM_15_32 BM_32_15 -#define BM_33_15 0x00000003ffff8000 -#define BM_15_33 BM_33_15 -#define BM_34_15 0x00000007ffff8000 -#define BM_15_34 BM_34_15 -#define BM_35_15 0x0000000fffff8000 -#define BM_15_35 BM_35_15 -#define BM_36_15 0x0000001fffff8000 -#define BM_15_36 BM_36_15 -#define BM_37_15 0x0000003fffff8000 -#define BM_15_37 BM_37_15 -#define BM_38_15 0x0000007fffff8000 -#define BM_15_38 BM_38_15 -#define BM_39_15 0x000000ffffff8000 -#define BM_15_39 BM_39_15 -#define BM_40_15 0x000001ffffff8000 -#define BM_15_40 BM_40_15 -#define BM_41_15 0x000003ffffff8000 -#define BM_15_41 BM_41_15 -#define BM_42_15 0x000007ffffff8000 -#define BM_15_42 BM_42_15 -#define BM_43_15 0x00000fffffff8000 -#define BM_15_43 BM_43_15 -#define BM_44_15 0x00001fffffff8000 -#define BM_15_44 BM_44_15 -#define BM_45_15 0x00003fffffff8000 -#define BM_15_45 BM_45_15 -#define BM_46_15 0x00007fffffff8000 -#define BM_15_46 BM_46_15 -#define BM_47_15 0x0000ffffffff8000 -#define BM_15_47 BM_47_15 -#define BM_48_15 0x0001ffffffff8000 -#define BM_15_48 BM_48_15 -#define BM_49_15 0x0003ffffffff8000 -#define BM_15_49 BM_49_15 -#define BM_50_15 0x0007ffffffff8000 -#define BM_15_50 BM_50_15 -#define BM_51_15 0x000fffffffff8000 -#define BM_15_51 BM_51_15 -#define BM_52_15 0x001fffffffff8000 -#define BM_15_52 BM_52_15 -#define BM_53_15 0x003fffffffff8000 -#define BM_15_53 BM_53_15 -#define BM_54_15 0x007fffffffff8000 -#define BM_15_54 BM_54_15 -#define BM_55_15 0x00ffffffffff8000 -#define BM_15_55 BM_55_15 -#define BM_56_15 0x01ffffffffff8000 -#define BM_15_56 BM_56_15 -#define BM_57_15 0x03ffffffffff8000 -#define BM_15_57 BM_57_15 -#define BM_58_15 0x07ffffffffff8000 -#define BM_15_58 BM_58_15 -#define BM_59_15 0x0fffffffffff8000 -#define BM_15_59 BM_59_15 -#define BM_60_15 0x1fffffffffff8000 -#define BM_15_60 BM_60_15 -#define BM_61_15 0x3fffffffffff8000 -#define BM_15_61 BM_61_15 -#define BM_62_15 0x7fffffffffff8000 -#define BM_15_62 BM_62_15 -#define BM_63_15 0xffffffffffff8000 -#define BM_15_63 BM_63_15 -#define BM_16_16 0x0000000000010000 -#define BM_17_16 0x0000000000030000 -#define BM_16_17 BM_17_16 -#define BM_18_16 0x0000000000070000 -#define BM_16_18 BM_18_16 -#define BM_19_16 0x00000000000f0000 -#define BM_16_19 BM_19_16 -#define BM_20_16 0x00000000001f0000 -#define BM_16_20 BM_20_16 -#define BM_21_16 0x00000000003f0000 -#define BM_16_21 BM_21_16 -#define BM_22_16 0x00000000007f0000 -#define BM_16_22 BM_22_16 -#define BM_23_16 0x0000000000ff0000 -#define BM_16_23 BM_23_16 -#define BM_24_16 0x0000000001ff0000 -#define BM_16_24 BM_24_16 -#define BM_25_16 0x0000000003ff0000 -#define BM_16_25 BM_25_16 -#define BM_26_16 0x0000000007ff0000 -#define BM_16_26 BM_26_16 -#define BM_27_16 0x000000000fff0000 -#define BM_16_27 BM_27_16 -#define BM_28_16 0x000000001fff0000 -#define BM_16_28 BM_28_16 -#define BM_29_16 0x000000003fff0000 -#define BM_16_29 BM_29_16 -#define BM_30_16 0x000000007fff0000 -#define BM_16_30 BM_30_16 -#define BM_31_16 0x00000000ffff0000 -#define BM_16_31 BM_31_16 -#define BM_32_16 0x00000001ffff0000 -#define BM_16_32 BM_32_16 -#define BM_33_16 0x00000003ffff0000 -#define BM_16_33 BM_33_16 -#define BM_34_16 0x00000007ffff0000 -#define BM_16_34 BM_34_16 -#define BM_35_16 0x0000000fffff0000 -#define BM_16_35 BM_35_16 -#define BM_36_16 0x0000001fffff0000 -#define BM_16_36 BM_36_16 -#define BM_37_16 0x0000003fffff0000 -#define BM_16_37 BM_37_16 -#define BM_38_16 0x0000007fffff0000 -#define BM_16_38 BM_38_16 -#define BM_39_16 0x000000ffffff0000 -#define BM_16_39 BM_39_16 -#define BM_40_16 0x000001ffffff0000 -#define BM_16_40 BM_40_16 -#define BM_41_16 0x000003ffffff0000 -#define BM_16_41 BM_41_16 -#define BM_42_16 0x000007ffffff0000 -#define BM_16_42 BM_42_16 -#define BM_43_16 0x00000fffffff0000 -#define BM_16_43 BM_43_16 -#define BM_44_16 0x00001fffffff0000 -#define BM_16_44 BM_44_16 -#define BM_45_16 0x00003fffffff0000 -#define BM_16_45 BM_45_16 -#define BM_46_16 0x00007fffffff0000 -#define BM_16_46 BM_46_16 -#define BM_47_16 0x0000ffffffff0000 -#define BM_16_47 BM_47_16 -#define BM_48_16 0x0001ffffffff0000 -#define BM_16_48 BM_48_16 -#define BM_49_16 0x0003ffffffff0000 -#define BM_16_49 BM_49_16 -#define BM_50_16 0x0007ffffffff0000 -#define BM_16_50 BM_50_16 -#define BM_51_16 0x000fffffffff0000 -#define BM_16_51 BM_51_16 -#define BM_52_16 0x001fffffffff0000 -#define BM_16_52 BM_52_16 -#define BM_53_16 0x003fffffffff0000 -#define BM_16_53 BM_53_16 -#define BM_54_16 0x007fffffffff0000 -#define BM_16_54 BM_54_16 -#define BM_55_16 0x00ffffffffff0000 -#define BM_16_55 BM_55_16 -#define BM_56_16 0x01ffffffffff0000 -#define BM_16_56 BM_56_16 -#define BM_57_16 0x03ffffffffff0000 -#define BM_16_57 BM_57_16 -#define BM_58_16 0x07ffffffffff0000 -#define BM_16_58 BM_58_16 -#define BM_59_16 0x0fffffffffff0000 -#define BM_16_59 BM_59_16 -#define BM_60_16 0x1fffffffffff0000 -#define BM_16_60 BM_60_16 -#define BM_61_16 0x3fffffffffff0000 -#define BM_16_61 BM_61_16 -#define BM_62_16 0x7fffffffffff0000 -#define BM_16_62 BM_62_16 -#define BM_63_16 0xffffffffffff0000 -#define BM_16_63 BM_63_16 -#define BM_17_17 0x0000000000020000 -#define BM_18_17 0x0000000000060000 -#define BM_17_18 BM_18_17 -#define BM_19_17 0x00000000000e0000 -#define BM_17_19 BM_19_17 -#define BM_20_17 0x00000000001e0000 -#define BM_17_20 BM_20_17 -#define BM_21_17 0x00000000003e0000 -#define BM_17_21 BM_21_17 -#define BM_22_17 0x00000000007e0000 -#define BM_17_22 BM_22_17 -#define BM_23_17 0x0000000000fe0000 -#define BM_17_23 BM_23_17 -#define BM_24_17 0x0000000001fe0000 -#define BM_17_24 BM_24_17 -#define BM_25_17 0x0000000003fe0000 -#define BM_17_25 BM_25_17 -#define BM_26_17 0x0000000007fe0000 -#define BM_17_26 BM_26_17 -#define BM_27_17 0x000000000ffe0000 -#define BM_17_27 BM_27_17 -#define BM_28_17 0x000000001ffe0000 -#define BM_17_28 BM_28_17 -#define BM_29_17 0x000000003ffe0000 -#define BM_17_29 BM_29_17 -#define BM_30_17 0x000000007ffe0000 -#define BM_17_30 BM_30_17 -#define BM_31_17 0x00000000fffe0000 -#define BM_17_31 BM_31_17 -#define BM_32_17 0x00000001fffe0000 -#define BM_17_32 BM_32_17 -#define BM_33_17 0x00000003fffe0000 -#define BM_17_33 BM_33_17 -#define BM_34_17 0x00000007fffe0000 -#define BM_17_34 BM_34_17 -#define BM_35_17 0x0000000ffffe0000 -#define BM_17_35 BM_35_17 -#define BM_36_17 0x0000001ffffe0000 -#define BM_17_36 BM_36_17 -#define BM_37_17 0x0000003ffffe0000 -#define BM_17_37 BM_37_17 -#define BM_38_17 0x0000007ffffe0000 -#define BM_17_38 BM_38_17 -#define BM_39_17 0x000000fffffe0000 -#define BM_17_39 BM_39_17 -#define BM_40_17 0x000001fffffe0000 -#define BM_17_40 BM_40_17 -#define BM_41_17 0x000003fffffe0000 -#define BM_17_41 BM_41_17 -#define BM_42_17 0x000007fffffe0000 -#define BM_17_42 BM_42_17 -#define BM_43_17 0x00000ffffffe0000 -#define BM_17_43 BM_43_17 -#define BM_44_17 0x00001ffffffe0000 -#define BM_17_44 BM_44_17 -#define BM_45_17 0x00003ffffffe0000 -#define BM_17_45 BM_45_17 -#define BM_46_17 0x00007ffffffe0000 -#define BM_17_46 BM_46_17 -#define BM_47_17 0x0000fffffffe0000 -#define BM_17_47 BM_47_17 -#define BM_48_17 0x0001fffffffe0000 -#define BM_17_48 BM_48_17 -#define BM_49_17 0x0003fffffffe0000 -#define BM_17_49 BM_49_17 -#define BM_50_17 0x0007fffffffe0000 -#define BM_17_50 BM_50_17 -#define BM_51_17 0x000ffffffffe0000 -#define BM_17_51 BM_51_17 -#define BM_52_17 0x001ffffffffe0000 -#define BM_17_52 BM_52_17 -#define BM_53_17 0x003ffffffffe0000 -#define BM_17_53 BM_53_17 -#define BM_54_17 0x007ffffffffe0000 -#define BM_17_54 BM_54_17 -#define BM_55_17 0x00fffffffffe0000 -#define BM_17_55 BM_55_17 -#define BM_56_17 0x01fffffffffe0000 -#define BM_17_56 BM_56_17 -#define BM_57_17 0x03fffffffffe0000 -#define BM_17_57 BM_57_17 -#define BM_58_17 0x07fffffffffe0000 -#define BM_17_58 BM_58_17 -#define BM_59_17 0x0ffffffffffe0000 -#define BM_17_59 BM_59_17 -#define BM_60_17 0x1ffffffffffe0000 -#define BM_17_60 BM_60_17 -#define BM_61_17 0x3ffffffffffe0000 -#define BM_17_61 BM_61_17 -#define BM_62_17 0x7ffffffffffe0000 -#define BM_17_62 BM_62_17 -#define BM_63_17 0xfffffffffffe0000 -#define BM_17_63 BM_63_17 -#define BM_18_18 0x0000000000040000 -#define BM_19_18 0x00000000000c0000 -#define BM_18_19 BM_19_18 -#define BM_20_18 0x00000000001c0000 -#define BM_18_20 BM_20_18 -#define BM_21_18 0x00000000003c0000 -#define BM_18_21 BM_21_18 -#define BM_22_18 0x00000000007c0000 -#define BM_18_22 BM_22_18 -#define BM_23_18 0x0000000000fc0000 -#define BM_18_23 BM_23_18 -#define BM_24_18 0x0000000001fc0000 -#define BM_18_24 BM_24_18 -#define BM_25_18 0x0000000003fc0000 -#define BM_18_25 BM_25_18 -#define BM_26_18 0x0000000007fc0000 -#define BM_18_26 BM_26_18 -#define BM_27_18 0x000000000ffc0000 -#define BM_18_27 BM_27_18 -#define BM_28_18 0x000000001ffc0000 -#define BM_18_28 BM_28_18 -#define BM_29_18 0x000000003ffc0000 -#define BM_18_29 BM_29_18 -#define BM_30_18 0x000000007ffc0000 -#define BM_18_30 BM_30_18 -#define BM_31_18 0x00000000fffc0000 -#define BM_18_31 BM_31_18 -#define BM_32_18 0x00000001fffc0000 -#define BM_18_32 BM_32_18 -#define BM_33_18 0x00000003fffc0000 -#define BM_18_33 BM_33_18 -#define BM_34_18 0x00000007fffc0000 -#define BM_18_34 BM_34_18 -#define BM_35_18 0x0000000ffffc0000 -#define BM_18_35 BM_35_18 -#define BM_36_18 0x0000001ffffc0000 -#define BM_18_36 BM_36_18 -#define BM_37_18 0x0000003ffffc0000 -#define BM_18_37 BM_37_18 -#define BM_38_18 0x0000007ffffc0000 -#define BM_18_38 BM_38_18 -#define BM_39_18 0x000000fffffc0000 -#define BM_18_39 BM_39_18 -#define BM_40_18 0x000001fffffc0000 -#define BM_18_40 BM_40_18 -#define BM_41_18 0x000003fffffc0000 -#define BM_18_41 BM_41_18 -#define BM_42_18 0x000007fffffc0000 -#define BM_18_42 BM_42_18 -#define BM_43_18 0x00000ffffffc0000 -#define BM_18_43 BM_43_18 -#define BM_44_18 0x00001ffffffc0000 -#define BM_18_44 BM_44_18 -#define BM_45_18 0x00003ffffffc0000 -#define BM_18_45 BM_45_18 -#define BM_46_18 0x00007ffffffc0000 -#define BM_18_46 BM_46_18 -#define BM_47_18 0x0000fffffffc0000 -#define BM_18_47 BM_47_18 -#define BM_48_18 0x0001fffffffc0000 -#define BM_18_48 BM_48_18 -#define BM_49_18 0x0003fffffffc0000 -#define BM_18_49 BM_49_18 -#define BM_50_18 0x0007fffffffc0000 -#define BM_18_50 BM_50_18 -#define BM_51_18 0x000ffffffffc0000 -#define BM_18_51 BM_51_18 -#define BM_52_18 0x001ffffffffc0000 -#define BM_18_52 BM_52_18 -#define BM_53_18 0x003ffffffffc0000 -#define BM_18_53 BM_53_18 -#define BM_54_18 0x007ffffffffc0000 -#define BM_18_54 BM_54_18 -#define BM_55_18 0x00fffffffffc0000 -#define BM_18_55 BM_55_18 -#define BM_56_18 0x01fffffffffc0000 -#define BM_18_56 BM_56_18 -#define BM_57_18 0x03fffffffffc0000 -#define BM_18_57 BM_57_18 -#define BM_58_18 0x07fffffffffc0000 -#define BM_18_58 BM_58_18 -#define BM_59_18 0x0ffffffffffc0000 -#define BM_18_59 BM_59_18 -#define BM_60_18 0x1ffffffffffc0000 -#define BM_18_60 BM_60_18 -#define BM_61_18 0x3ffffffffffc0000 -#define BM_18_61 BM_61_18 -#define BM_62_18 0x7ffffffffffc0000 -#define BM_18_62 BM_62_18 -#define BM_63_18 0xfffffffffffc0000 -#define BM_18_63 BM_63_18 -#define BM_19_19 0x0000000000080000 -#define BM_20_19 0x0000000000180000 -#define BM_19_20 BM_20_19 -#define BM_21_19 0x0000000000380000 -#define BM_19_21 BM_21_19 -#define BM_22_19 0x0000000000780000 -#define BM_19_22 BM_22_19 -#define BM_23_19 0x0000000000f80000 -#define BM_19_23 BM_23_19 -#define BM_24_19 0x0000000001f80000 -#define BM_19_24 BM_24_19 -#define BM_25_19 0x0000000003f80000 -#define BM_19_25 BM_25_19 -#define BM_26_19 0x0000000007f80000 -#define BM_19_26 BM_26_19 -#define BM_27_19 0x000000000ff80000 -#define BM_19_27 BM_27_19 -#define BM_28_19 0x000000001ff80000 -#define BM_19_28 BM_28_19 -#define BM_29_19 0x000000003ff80000 -#define BM_19_29 BM_29_19 -#define BM_30_19 0x000000007ff80000 -#define BM_19_30 BM_30_19 -#define BM_31_19 0x00000000fff80000 -#define BM_19_31 BM_31_19 -#define BM_32_19 0x00000001fff80000 -#define BM_19_32 BM_32_19 -#define BM_33_19 0x00000003fff80000 -#define BM_19_33 BM_33_19 -#define BM_34_19 0x00000007fff80000 -#define BM_19_34 BM_34_19 -#define BM_35_19 0x0000000ffff80000 -#define BM_19_35 BM_35_19 -#define BM_36_19 0x0000001ffff80000 -#define BM_19_36 BM_36_19 -#define BM_37_19 0x0000003ffff80000 -#define BM_19_37 BM_37_19 -#define BM_38_19 0x0000007ffff80000 -#define BM_19_38 BM_38_19 -#define BM_39_19 0x000000fffff80000 -#define BM_19_39 BM_39_19 -#define BM_40_19 0x000001fffff80000 -#define BM_19_40 BM_40_19 -#define BM_41_19 0x000003fffff80000 -#define BM_19_41 BM_41_19 -#define BM_42_19 0x000007fffff80000 -#define BM_19_42 BM_42_19 -#define BM_43_19 0x00000ffffff80000 -#define BM_19_43 BM_43_19 -#define BM_44_19 0x00001ffffff80000 -#define BM_19_44 BM_44_19 -#define BM_45_19 0x00003ffffff80000 -#define BM_19_45 BM_45_19 -#define BM_46_19 0x00007ffffff80000 -#define BM_19_46 BM_46_19 -#define BM_47_19 0x0000fffffff80000 -#define BM_19_47 BM_47_19 -#define BM_48_19 0x0001fffffff80000 -#define BM_19_48 BM_48_19 -#define BM_49_19 0x0003fffffff80000 -#define BM_19_49 BM_49_19 -#define BM_50_19 0x0007fffffff80000 -#define BM_19_50 BM_50_19 -#define BM_51_19 0x000ffffffff80000 -#define BM_19_51 BM_51_19 -#define BM_52_19 0x001ffffffff80000 -#define BM_19_52 BM_52_19 -#define BM_53_19 0x003ffffffff80000 -#define BM_19_53 BM_53_19 -#define BM_54_19 0x007ffffffff80000 -#define BM_19_54 BM_54_19 -#define BM_55_19 0x00fffffffff80000 -#define BM_19_55 BM_55_19 -#define BM_56_19 0x01fffffffff80000 -#define BM_19_56 BM_56_19 -#define BM_57_19 0x03fffffffff80000 -#define BM_19_57 BM_57_19 -#define BM_58_19 0x07fffffffff80000 -#define BM_19_58 BM_58_19 -#define BM_59_19 0x0ffffffffff80000 -#define BM_19_59 BM_59_19 -#define BM_60_19 0x1ffffffffff80000 -#define BM_19_60 BM_60_19 -#define BM_61_19 0x3ffffffffff80000 -#define BM_19_61 BM_61_19 -#define BM_62_19 0x7ffffffffff80000 -#define BM_19_62 BM_62_19 -#define BM_63_19 0xfffffffffff80000 -#define BM_19_63 BM_63_19 -#define BM_20_20 0x0000000000100000 -#define BM_21_20 0x0000000000300000 -#define BM_20_21 BM_21_20 -#define BM_22_20 0x0000000000700000 -#define BM_20_22 BM_22_20 -#define BM_23_20 0x0000000000f00000 -#define BM_20_23 BM_23_20 -#define BM_24_20 0x0000000001f00000 -#define BM_20_24 BM_24_20 -#define BM_25_20 0x0000000003f00000 -#define BM_20_25 BM_25_20 -#define BM_26_20 0x0000000007f00000 -#define BM_20_26 BM_26_20 -#define BM_27_20 0x000000000ff00000 -#define BM_20_27 BM_27_20 -#define BM_28_20 0x000000001ff00000 -#define BM_20_28 BM_28_20 -#define BM_29_20 0x000000003ff00000 -#define BM_20_29 BM_29_20 -#define BM_30_20 0x000000007ff00000 -#define BM_20_30 BM_30_20 -#define BM_31_20 0x00000000fff00000 -#define BM_20_31 BM_31_20 -#define BM_32_20 0x00000001fff00000 -#define BM_20_32 BM_32_20 -#define BM_33_20 0x00000003fff00000 -#define BM_20_33 BM_33_20 -#define BM_34_20 0x00000007fff00000 -#define BM_20_34 BM_34_20 -#define BM_35_20 0x0000000ffff00000 -#define BM_20_35 BM_35_20 -#define BM_36_20 0x0000001ffff00000 -#define BM_20_36 BM_36_20 -#define BM_37_20 0x0000003ffff00000 -#define BM_20_37 BM_37_20 -#define BM_38_20 0x0000007ffff00000 -#define BM_20_38 BM_38_20 -#define BM_39_20 0x000000fffff00000 -#define BM_20_39 BM_39_20 -#define BM_40_20 0x000001fffff00000 -#define BM_20_40 BM_40_20 -#define BM_41_20 0x000003fffff00000 -#define BM_20_41 BM_41_20 -#define BM_42_20 0x000007fffff00000 -#define BM_20_42 BM_42_20 -#define BM_43_20 0x00000ffffff00000 -#define BM_20_43 BM_43_20 -#define BM_44_20 0x00001ffffff00000 -#define BM_20_44 BM_44_20 -#define BM_45_20 0x00003ffffff00000 -#define BM_20_45 BM_45_20 -#define BM_46_20 0x00007ffffff00000 -#define BM_20_46 BM_46_20 -#define BM_47_20 0x0000fffffff00000 -#define BM_20_47 BM_47_20 -#define BM_48_20 0x0001fffffff00000 -#define BM_20_48 BM_48_20 -#define BM_49_20 0x0003fffffff00000 -#define BM_20_49 BM_49_20 -#define BM_50_20 0x0007fffffff00000 -#define BM_20_50 BM_50_20 -#define BM_51_20 0x000ffffffff00000 -#define BM_20_51 BM_51_20 -#define BM_52_20 0x001ffffffff00000 -#define BM_20_52 BM_52_20 -#define BM_53_20 0x003ffffffff00000 -#define BM_20_53 BM_53_20 -#define BM_54_20 0x007ffffffff00000 -#define BM_20_54 BM_54_20 -#define BM_55_20 0x00fffffffff00000 -#define BM_20_55 BM_55_20 -#define BM_56_20 0x01fffffffff00000 -#define BM_20_56 BM_56_20 -#define BM_57_20 0x03fffffffff00000 -#define BM_20_57 BM_57_20 -#define BM_58_20 0x07fffffffff00000 -#define BM_20_58 BM_58_20 -#define BM_59_20 0x0ffffffffff00000 -#define BM_20_59 BM_59_20 -#define BM_60_20 0x1ffffffffff00000 -#define BM_20_60 BM_60_20 -#define BM_61_20 0x3ffffffffff00000 -#define BM_20_61 BM_61_20 -#define BM_62_20 0x7ffffffffff00000 -#define BM_20_62 BM_62_20 -#define BM_63_20 0xfffffffffff00000 -#define BM_20_63 BM_63_20 -#define BM_21_21 0x0000000000200000 -#define BM_22_21 0x0000000000600000 -#define BM_21_22 BM_22_21 -#define BM_23_21 0x0000000000e00000 -#define BM_21_23 BM_23_21 -#define BM_24_21 0x0000000001e00000 -#define BM_21_24 BM_24_21 -#define BM_25_21 0x0000000003e00000 -#define BM_21_25 BM_25_21 -#define BM_26_21 0x0000000007e00000 -#define BM_21_26 BM_26_21 -#define BM_27_21 0x000000000fe00000 -#define BM_21_27 BM_27_21 -#define BM_28_21 0x000000001fe00000 -#define BM_21_28 BM_28_21 -#define BM_29_21 0x000000003fe00000 -#define BM_21_29 BM_29_21 -#define BM_30_21 0x000000007fe00000 -#define BM_21_30 BM_30_21 -#define BM_31_21 0x00000000ffe00000 -#define BM_21_31 BM_31_21 -#define BM_32_21 0x00000001ffe00000 -#define BM_21_32 BM_32_21 -#define BM_33_21 0x00000003ffe00000 -#define BM_21_33 BM_33_21 -#define BM_34_21 0x00000007ffe00000 -#define BM_21_34 BM_34_21 -#define BM_35_21 0x0000000fffe00000 -#define BM_21_35 BM_35_21 -#define BM_36_21 0x0000001fffe00000 -#define BM_21_36 BM_36_21 -#define BM_37_21 0x0000003fffe00000 -#define BM_21_37 BM_37_21 -#define BM_38_21 0x0000007fffe00000 -#define BM_21_38 BM_38_21 -#define BM_39_21 0x000000ffffe00000 -#define BM_21_39 BM_39_21 -#define BM_40_21 0x000001ffffe00000 -#define BM_21_40 BM_40_21 -#define BM_41_21 0x000003ffffe00000 -#define BM_21_41 BM_41_21 -#define BM_42_21 0x000007ffffe00000 -#define BM_21_42 BM_42_21 -#define BM_43_21 0x00000fffffe00000 -#define BM_21_43 BM_43_21 -#define BM_44_21 0x00001fffffe00000 -#define BM_21_44 BM_44_21 -#define BM_45_21 0x00003fffffe00000 -#define BM_21_45 BM_45_21 -#define BM_46_21 0x00007fffffe00000 -#define BM_21_46 BM_46_21 -#define BM_47_21 0x0000ffffffe00000 -#define BM_21_47 BM_47_21 -#define BM_48_21 0x0001ffffffe00000 -#define BM_21_48 BM_48_21 -#define BM_49_21 0x0003ffffffe00000 -#define BM_21_49 BM_49_21 -#define BM_50_21 0x0007ffffffe00000 -#define BM_21_50 BM_50_21 -#define BM_51_21 0x000fffffffe00000 -#define BM_21_51 BM_51_21 -#define BM_52_21 0x001fffffffe00000 -#define BM_21_52 BM_52_21 -#define BM_53_21 0x003fffffffe00000 -#define BM_21_53 BM_53_21 -#define BM_54_21 0x007fffffffe00000 -#define BM_21_54 BM_54_21 -#define BM_55_21 0x00ffffffffe00000 -#define BM_21_55 BM_55_21 -#define BM_56_21 0x01ffffffffe00000 -#define BM_21_56 BM_56_21 -#define BM_57_21 0x03ffffffffe00000 -#define BM_21_57 BM_57_21 -#define BM_58_21 0x07ffffffffe00000 -#define BM_21_58 BM_58_21 -#define BM_59_21 0x0fffffffffe00000 -#define BM_21_59 BM_59_21 -#define BM_60_21 0x1fffffffffe00000 -#define BM_21_60 BM_60_21 -#define BM_61_21 0x3fffffffffe00000 -#define BM_21_61 BM_61_21 -#define BM_62_21 0x7fffffffffe00000 -#define BM_21_62 BM_62_21 -#define BM_63_21 0xffffffffffe00000 -#define BM_21_63 BM_63_21 -#define BM_22_22 0x0000000000400000 -#define BM_23_22 0x0000000000c00000 -#define BM_22_23 BM_23_22 -#define BM_24_22 0x0000000001c00000 -#define BM_22_24 BM_24_22 -#define BM_25_22 0x0000000003c00000 -#define BM_22_25 BM_25_22 -#define BM_26_22 0x0000000007c00000 -#define BM_22_26 BM_26_22 -#define BM_27_22 0x000000000fc00000 -#define BM_22_27 BM_27_22 -#define BM_28_22 0x000000001fc00000 -#define BM_22_28 BM_28_22 -#define BM_29_22 0x000000003fc00000 -#define BM_22_29 BM_29_22 -#define BM_30_22 0x000000007fc00000 -#define BM_22_30 BM_30_22 -#define BM_31_22 0x00000000ffc00000 -#define BM_22_31 BM_31_22 -#define BM_32_22 0x00000001ffc00000 -#define BM_22_32 BM_32_22 -#define BM_33_22 0x00000003ffc00000 -#define BM_22_33 BM_33_22 -#define BM_34_22 0x00000007ffc00000 -#define BM_22_34 BM_34_22 -#define BM_35_22 0x0000000fffc00000 -#define BM_22_35 BM_35_22 -#define BM_36_22 0x0000001fffc00000 -#define BM_22_36 BM_36_22 -#define BM_37_22 0x0000003fffc00000 -#define BM_22_37 BM_37_22 -#define BM_38_22 0x0000007fffc00000 -#define BM_22_38 BM_38_22 -#define BM_39_22 0x000000ffffc00000 -#define BM_22_39 BM_39_22 -#define BM_40_22 0x000001ffffc00000 -#define BM_22_40 BM_40_22 -#define BM_41_22 0x000003ffffc00000 -#define BM_22_41 BM_41_22 -#define BM_42_22 0x000007ffffc00000 -#define BM_22_42 BM_42_22 -#define BM_43_22 0x00000fffffc00000 -#define BM_22_43 BM_43_22 -#define BM_44_22 0x00001fffffc00000 -#define BM_22_44 BM_44_22 -#define BM_45_22 0x00003fffffc00000 -#define BM_22_45 BM_45_22 -#define BM_46_22 0x00007fffffc00000 -#define BM_22_46 BM_46_22 -#define BM_47_22 0x0000ffffffc00000 -#define BM_22_47 BM_47_22 -#define BM_48_22 0x0001ffffffc00000 -#define BM_22_48 BM_48_22 -#define BM_49_22 0x0003ffffffc00000 -#define BM_22_49 BM_49_22 -#define BM_50_22 0x0007ffffffc00000 -#define BM_22_50 BM_50_22 -#define BM_51_22 0x000fffffffc00000 -#define BM_22_51 BM_51_22 -#define BM_52_22 0x001fffffffc00000 -#define BM_22_52 BM_52_22 -#define BM_53_22 0x003fffffffc00000 -#define BM_22_53 BM_53_22 -#define BM_54_22 0x007fffffffc00000 -#define BM_22_54 BM_54_22 -#define BM_55_22 0x00ffffffffc00000 -#define BM_22_55 BM_55_22 -#define BM_56_22 0x01ffffffffc00000 -#define BM_22_56 BM_56_22 -#define BM_57_22 0x03ffffffffc00000 -#define BM_22_57 BM_57_22 -#define BM_58_22 0x07ffffffffc00000 -#define BM_22_58 BM_58_22 -#define BM_59_22 0x0fffffffffc00000 -#define BM_22_59 BM_59_22 -#define BM_60_22 0x1fffffffffc00000 -#define BM_22_60 BM_60_22 -#define BM_61_22 0x3fffffffffc00000 -#define BM_22_61 BM_61_22 -#define BM_62_22 0x7fffffffffc00000 -#define BM_22_62 BM_62_22 -#define BM_63_22 0xffffffffffc00000 -#define BM_22_63 BM_63_22 -#define BM_23_23 0x0000000000800000 -#define BM_24_23 0x0000000001800000 -#define BM_23_24 BM_24_23 -#define BM_25_23 0x0000000003800000 -#define BM_23_25 BM_25_23 -#define BM_26_23 0x0000000007800000 -#define BM_23_26 BM_26_23 -#define BM_27_23 0x000000000f800000 -#define BM_23_27 BM_27_23 -#define BM_28_23 0x000000001f800000 -#define BM_23_28 BM_28_23 -#define BM_29_23 0x000000003f800000 -#define BM_23_29 BM_29_23 -#define BM_30_23 0x000000007f800000 -#define BM_23_30 BM_30_23 -#define BM_31_23 0x00000000ff800000 -#define BM_23_31 BM_31_23 -#define BM_32_23 0x00000001ff800000 -#define BM_23_32 BM_32_23 -#define BM_33_23 0x00000003ff800000 -#define BM_23_33 BM_33_23 -#define BM_34_23 0x00000007ff800000 -#define BM_23_34 BM_34_23 -#define BM_35_23 0x0000000fff800000 -#define BM_23_35 BM_35_23 -#define BM_36_23 0x0000001fff800000 -#define BM_23_36 BM_36_23 -#define BM_37_23 0x0000003fff800000 -#define BM_23_37 BM_37_23 -#define BM_38_23 0x0000007fff800000 -#define BM_23_38 BM_38_23 -#define BM_39_23 0x000000ffff800000 -#define BM_23_39 BM_39_23 -#define BM_40_23 0x000001ffff800000 -#define BM_23_40 BM_40_23 -#define BM_41_23 0x000003ffff800000 -#define BM_23_41 BM_41_23 -#define BM_42_23 0x000007ffff800000 -#define BM_23_42 BM_42_23 -#define BM_43_23 0x00000fffff800000 -#define BM_23_43 BM_43_23 -#define BM_44_23 0x00001fffff800000 -#define BM_23_44 BM_44_23 -#define BM_45_23 0x00003fffff800000 -#define BM_23_45 BM_45_23 -#define BM_46_23 0x00007fffff800000 -#define BM_23_46 BM_46_23 -#define BM_47_23 0x0000ffffff800000 -#define BM_23_47 BM_47_23 -#define BM_48_23 0x0001ffffff800000 -#define BM_23_48 BM_48_23 -#define BM_49_23 0x0003ffffff800000 -#define BM_23_49 BM_49_23 -#define BM_50_23 0x0007ffffff800000 -#define BM_23_50 BM_50_23 -#define BM_51_23 0x000fffffff800000 -#define BM_23_51 BM_51_23 -#define BM_52_23 0x001fffffff800000 -#define BM_23_52 BM_52_23 -#define BM_53_23 0x003fffffff800000 -#define BM_23_53 BM_53_23 -#define BM_54_23 0x007fffffff800000 -#define BM_23_54 BM_54_23 -#define BM_55_23 0x00ffffffff800000 -#define BM_23_55 BM_55_23 -#define BM_56_23 0x01ffffffff800000 -#define BM_23_56 BM_56_23 -#define BM_57_23 0x03ffffffff800000 -#define BM_23_57 BM_57_23 -#define BM_58_23 0x07ffffffff800000 -#define BM_23_58 BM_58_23 -#define BM_59_23 0x0fffffffff800000 -#define BM_23_59 BM_59_23 -#define BM_60_23 0x1fffffffff800000 -#define BM_23_60 BM_60_23 -#define BM_61_23 0x3fffffffff800000 -#define BM_23_61 BM_61_23 -#define BM_62_23 0x7fffffffff800000 -#define BM_23_62 BM_62_23 -#define BM_63_23 0xffffffffff800000 -#define BM_23_63 BM_63_23 -#define BM_24_24 0x0000000001000000 -#define BM_25_24 0x0000000003000000 -#define BM_24_25 BM_25_24 -#define BM_26_24 0x0000000007000000 -#define BM_24_26 BM_26_24 -#define BM_27_24 0x000000000f000000 -#define BM_24_27 BM_27_24 -#define BM_28_24 0x000000001f000000 -#define BM_24_28 BM_28_24 -#define BM_29_24 0x000000003f000000 -#define BM_24_29 BM_29_24 -#define BM_30_24 0x000000007f000000 -#define BM_24_30 BM_30_24 -#define BM_31_24 0x00000000ff000000 -#define BM_24_31 BM_31_24 -#define BM_32_24 0x00000001ff000000 -#define BM_24_32 BM_32_24 -#define BM_33_24 0x00000003ff000000 -#define BM_24_33 BM_33_24 -#define BM_34_24 0x00000007ff000000 -#define BM_24_34 BM_34_24 -#define BM_35_24 0x0000000fff000000 -#define BM_24_35 BM_35_24 -#define BM_36_24 0x0000001fff000000 -#define BM_24_36 BM_36_24 -#define BM_37_24 0x0000003fff000000 -#define BM_24_37 BM_37_24 -#define BM_38_24 0x0000007fff000000 -#define BM_24_38 BM_38_24 -#define BM_39_24 0x000000ffff000000 -#define BM_24_39 BM_39_24 -#define BM_40_24 0x000001ffff000000 -#define BM_24_40 BM_40_24 -#define BM_41_24 0x000003ffff000000 -#define BM_24_41 BM_41_24 -#define BM_42_24 0x000007ffff000000 -#define BM_24_42 BM_42_24 -#define BM_43_24 0x00000fffff000000 -#define BM_24_43 BM_43_24 -#define BM_44_24 0x00001fffff000000 -#define BM_24_44 BM_44_24 -#define BM_45_24 0x00003fffff000000 -#define BM_24_45 BM_45_24 -#define BM_46_24 0x00007fffff000000 -#define BM_24_46 BM_46_24 -#define BM_47_24 0x0000ffffff000000 -#define BM_24_47 BM_47_24 -#define BM_48_24 0x0001ffffff000000 -#define BM_24_48 BM_48_24 -#define BM_49_24 0x0003ffffff000000 -#define BM_24_49 BM_49_24 -#define BM_50_24 0x0007ffffff000000 -#define BM_24_50 BM_50_24 -#define BM_51_24 0x000fffffff000000 -#define BM_24_51 BM_51_24 -#define BM_52_24 0x001fffffff000000 -#define BM_24_52 BM_52_24 -#define BM_53_24 0x003fffffff000000 -#define BM_24_53 BM_53_24 -#define BM_54_24 0x007fffffff000000 -#define BM_24_54 BM_54_24 -#define BM_55_24 0x00ffffffff000000 -#define BM_24_55 BM_55_24 -#define BM_56_24 0x01ffffffff000000 -#define BM_24_56 BM_56_24 -#define BM_57_24 0x03ffffffff000000 -#define BM_24_57 BM_57_24 -#define BM_58_24 0x07ffffffff000000 -#define BM_24_58 BM_58_24 -#define BM_59_24 0x0fffffffff000000 -#define BM_24_59 BM_59_24 -#define BM_60_24 0x1fffffffff000000 -#define BM_24_60 BM_60_24 -#define BM_61_24 0x3fffffffff000000 -#define BM_24_61 BM_61_24 -#define BM_62_24 0x7fffffffff000000 -#define BM_24_62 BM_62_24 -#define BM_63_24 0xffffffffff000000 -#define BM_24_63 BM_63_24 -#define BM_25_25 0x0000000002000000 -#define BM_26_25 0x0000000006000000 -#define BM_25_26 BM_26_25 -#define BM_27_25 0x000000000e000000 -#define BM_25_27 BM_27_25 -#define BM_28_25 0x000000001e000000 -#define BM_25_28 BM_28_25 -#define BM_29_25 0x000000003e000000 -#define BM_25_29 BM_29_25 -#define BM_30_25 0x000000007e000000 -#define BM_25_30 BM_30_25 -#define BM_31_25 0x00000000fe000000 -#define BM_25_31 BM_31_25 -#define BM_32_25 0x00000001fe000000 -#define BM_25_32 BM_32_25 -#define BM_33_25 0x00000003fe000000 -#define BM_25_33 BM_33_25 -#define BM_34_25 0x00000007fe000000 -#define BM_25_34 BM_34_25 -#define BM_35_25 0x0000000ffe000000 -#define BM_25_35 BM_35_25 -#define BM_36_25 0x0000001ffe000000 -#define BM_25_36 BM_36_25 -#define BM_37_25 0x0000003ffe000000 -#define BM_25_37 BM_37_25 -#define BM_38_25 0x0000007ffe000000 -#define BM_25_38 BM_38_25 -#define BM_39_25 0x000000fffe000000 -#define BM_25_39 BM_39_25 -#define BM_40_25 0x000001fffe000000 -#define BM_25_40 BM_40_25 -#define BM_41_25 0x000003fffe000000 -#define BM_25_41 BM_41_25 -#define BM_42_25 0x000007fffe000000 -#define BM_25_42 BM_42_25 -#define BM_43_25 0x00000ffffe000000 -#define BM_25_43 BM_43_25 -#define BM_44_25 0x00001ffffe000000 -#define BM_25_44 BM_44_25 -#define BM_45_25 0x00003ffffe000000 -#define BM_25_45 BM_45_25 -#define BM_46_25 0x00007ffffe000000 -#define BM_25_46 BM_46_25 -#define BM_47_25 0x0000fffffe000000 -#define BM_25_47 BM_47_25 -#define BM_48_25 0x0001fffffe000000 -#define BM_25_48 BM_48_25 -#define BM_49_25 0x0003fffffe000000 -#define BM_25_49 BM_49_25 -#define BM_50_25 0x0007fffffe000000 -#define BM_25_50 BM_50_25 -#define BM_51_25 0x000ffffffe000000 -#define BM_25_51 BM_51_25 -#define BM_52_25 0x001ffffffe000000 -#define BM_25_52 BM_52_25 -#define BM_53_25 0x003ffffffe000000 -#define BM_25_53 BM_53_25 -#define BM_54_25 0x007ffffffe000000 -#define BM_25_54 BM_54_25 -#define BM_55_25 0x00fffffffe000000 -#define BM_25_55 BM_55_25 -#define BM_56_25 0x01fffffffe000000 -#define BM_25_56 BM_56_25 -#define BM_57_25 0x03fffffffe000000 -#define BM_25_57 BM_57_25 -#define BM_58_25 0x07fffffffe000000 -#define BM_25_58 BM_58_25 -#define BM_59_25 0x0ffffffffe000000 -#define BM_25_59 BM_59_25 -#define BM_60_25 0x1ffffffffe000000 -#define BM_25_60 BM_60_25 -#define BM_61_25 0x3ffffffffe000000 -#define BM_25_61 BM_61_25 -#define BM_62_25 0x7ffffffffe000000 -#define BM_25_62 BM_62_25 -#define BM_63_25 0xfffffffffe000000 -#define BM_25_63 BM_63_25 -#define BM_26_26 0x0000000004000000 -#define BM_27_26 0x000000000c000000 -#define BM_26_27 BM_27_26 -#define BM_28_26 0x000000001c000000 -#define BM_26_28 BM_28_26 -#define BM_29_26 0x000000003c000000 -#define BM_26_29 BM_29_26 -#define BM_30_26 0x000000007c000000 -#define BM_26_30 BM_30_26 -#define BM_31_26 0x00000000fc000000 -#define BM_26_31 BM_31_26 -#define BM_32_26 0x00000001fc000000 -#define BM_26_32 BM_32_26 -#define BM_33_26 0x00000003fc000000 -#define BM_26_33 BM_33_26 -#define BM_34_26 0x00000007fc000000 -#define BM_26_34 BM_34_26 -#define BM_35_26 0x0000000ffc000000 -#define BM_26_35 BM_35_26 -#define BM_36_26 0x0000001ffc000000 -#define BM_26_36 BM_36_26 -#define BM_37_26 0x0000003ffc000000 -#define BM_26_37 BM_37_26 -#define BM_38_26 0x0000007ffc000000 -#define BM_26_38 BM_38_26 -#define BM_39_26 0x000000fffc000000 -#define BM_26_39 BM_39_26 -#define BM_40_26 0x000001fffc000000 -#define BM_26_40 BM_40_26 -#define BM_41_26 0x000003fffc000000 -#define BM_26_41 BM_41_26 -#define BM_42_26 0x000007fffc000000 -#define BM_26_42 BM_42_26 -#define BM_43_26 0x00000ffffc000000 -#define BM_26_43 BM_43_26 -#define BM_44_26 0x00001ffffc000000 -#define BM_26_44 BM_44_26 -#define BM_45_26 0x00003ffffc000000 -#define BM_26_45 BM_45_26 -#define BM_46_26 0x00007ffffc000000 -#define BM_26_46 BM_46_26 -#define BM_47_26 0x0000fffffc000000 -#define BM_26_47 BM_47_26 -#define BM_48_26 0x0001fffffc000000 -#define BM_26_48 BM_48_26 -#define BM_49_26 0x0003fffffc000000 -#define BM_26_49 BM_49_26 -#define BM_50_26 0x0007fffffc000000 -#define BM_26_50 BM_50_26 -#define BM_51_26 0x000ffffffc000000 -#define BM_26_51 BM_51_26 -#define BM_52_26 0x001ffffffc000000 -#define BM_26_52 BM_52_26 -#define BM_53_26 0x003ffffffc000000 -#define BM_26_53 BM_53_26 -#define BM_54_26 0x007ffffffc000000 -#define BM_26_54 BM_54_26 -#define BM_55_26 0x00fffffffc000000 -#define BM_26_55 BM_55_26 -#define BM_56_26 0x01fffffffc000000 -#define BM_26_56 BM_56_26 -#define BM_57_26 0x03fffffffc000000 -#define BM_26_57 BM_57_26 -#define BM_58_26 0x07fffffffc000000 -#define BM_26_58 BM_58_26 -#define BM_59_26 0x0ffffffffc000000 -#define BM_26_59 BM_59_26 -#define BM_60_26 0x1ffffffffc000000 -#define BM_26_60 BM_60_26 -#define BM_61_26 0x3ffffffffc000000 -#define BM_26_61 BM_61_26 -#define BM_62_26 0x7ffffffffc000000 -#define BM_26_62 BM_62_26 -#define BM_63_26 0xfffffffffc000000 -#define BM_26_63 BM_63_26 -#define BM_27_27 0x0000000008000000 -#define BM_28_27 0x0000000018000000 -#define BM_27_28 BM_28_27 -#define BM_29_27 0x0000000038000000 -#define BM_27_29 BM_29_27 -#define BM_30_27 0x0000000078000000 -#define BM_27_30 BM_30_27 -#define BM_31_27 0x00000000f8000000 -#define BM_27_31 BM_31_27 -#define BM_32_27 0x00000001f8000000 -#define BM_27_32 BM_32_27 -#define BM_33_27 0x00000003f8000000 -#define BM_27_33 BM_33_27 -#define BM_34_27 0x00000007f8000000 -#define BM_27_34 BM_34_27 -#define BM_35_27 0x0000000ff8000000 -#define BM_27_35 BM_35_27 -#define BM_36_27 0x0000001ff8000000 -#define BM_27_36 BM_36_27 -#define BM_37_27 0x0000003ff8000000 -#define BM_27_37 BM_37_27 -#define BM_38_27 0x0000007ff8000000 -#define BM_27_38 BM_38_27 -#define BM_39_27 0x000000fff8000000 -#define BM_27_39 BM_39_27 -#define BM_40_27 0x000001fff8000000 -#define BM_27_40 BM_40_27 -#define BM_41_27 0x000003fff8000000 -#define BM_27_41 BM_41_27 -#define BM_42_27 0x000007fff8000000 -#define BM_27_42 BM_42_27 -#define BM_43_27 0x00000ffff8000000 -#define BM_27_43 BM_43_27 -#define BM_44_27 0x00001ffff8000000 -#define BM_27_44 BM_44_27 -#define BM_45_27 0x00003ffff8000000 -#define BM_27_45 BM_45_27 -#define BM_46_27 0x00007ffff8000000 -#define BM_27_46 BM_46_27 -#define BM_47_27 0x0000fffff8000000 -#define BM_27_47 BM_47_27 -#define BM_48_27 0x0001fffff8000000 -#define BM_27_48 BM_48_27 -#define BM_49_27 0x0003fffff8000000 -#define BM_27_49 BM_49_27 -#define BM_50_27 0x0007fffff8000000 -#define BM_27_50 BM_50_27 -#define BM_51_27 0x000ffffff8000000 -#define BM_27_51 BM_51_27 -#define BM_52_27 0x001ffffff8000000 -#define BM_27_52 BM_52_27 -#define BM_53_27 0x003ffffff8000000 -#define BM_27_53 BM_53_27 -#define BM_54_27 0x007ffffff8000000 -#define BM_27_54 BM_54_27 -#define BM_55_27 0x00fffffff8000000 -#define BM_27_55 BM_55_27 -#define BM_56_27 0x01fffffff8000000 -#define BM_27_56 BM_56_27 -#define BM_57_27 0x03fffffff8000000 -#define BM_27_57 BM_57_27 -#define BM_58_27 0x07fffffff8000000 -#define BM_27_58 BM_58_27 -#define BM_59_27 0x0ffffffff8000000 -#define BM_27_59 BM_59_27 -#define BM_60_27 0x1ffffffff8000000 -#define BM_27_60 BM_60_27 -#define BM_61_27 0x3ffffffff8000000 -#define BM_27_61 BM_61_27 -#define BM_62_27 0x7ffffffff8000000 -#define BM_27_62 BM_62_27 -#define BM_63_27 0xfffffffff8000000 -#define BM_27_63 BM_63_27 -#define BM_28_28 0x0000000010000000 -#define BM_29_28 0x0000000030000000 -#define BM_28_29 BM_29_28 -#define BM_30_28 0x0000000070000000 -#define BM_28_30 BM_30_28 -#define BM_31_28 0x00000000f0000000 -#define BM_28_31 BM_31_28 -#define BM_32_28 0x00000001f0000000 -#define BM_28_32 BM_32_28 -#define BM_33_28 0x00000003f0000000 -#define BM_28_33 BM_33_28 -#define BM_34_28 0x00000007f0000000 -#define BM_28_34 BM_34_28 -#define BM_35_28 0x0000000ff0000000 -#define BM_28_35 BM_35_28 -#define BM_36_28 0x0000001ff0000000 -#define BM_28_36 BM_36_28 -#define BM_37_28 0x0000003ff0000000 -#define BM_28_37 BM_37_28 -#define BM_38_28 0x0000007ff0000000 -#define BM_28_38 BM_38_28 -#define BM_39_28 0x000000fff0000000 -#define BM_28_39 BM_39_28 -#define BM_40_28 0x000001fff0000000 -#define BM_28_40 BM_40_28 -#define BM_41_28 0x000003fff0000000 -#define BM_28_41 BM_41_28 -#define BM_42_28 0x000007fff0000000 -#define BM_28_42 BM_42_28 -#define BM_43_28 0x00000ffff0000000 -#define BM_28_43 BM_43_28 -#define BM_44_28 0x00001ffff0000000 -#define BM_28_44 BM_44_28 -#define BM_45_28 0x00003ffff0000000 -#define BM_28_45 BM_45_28 -#define BM_46_28 0x00007ffff0000000 -#define BM_28_46 BM_46_28 -#define BM_47_28 0x0000fffff0000000 -#define BM_28_47 BM_47_28 -#define BM_48_28 0x0001fffff0000000 -#define BM_28_48 BM_48_28 -#define BM_49_28 0x0003fffff0000000 -#define BM_28_49 BM_49_28 -#define BM_50_28 0x0007fffff0000000 -#define BM_28_50 BM_50_28 -#define BM_51_28 0x000ffffff0000000 -#define BM_28_51 BM_51_28 -#define BM_52_28 0x001ffffff0000000 -#define BM_28_52 BM_52_28 -#define BM_53_28 0x003ffffff0000000 -#define BM_28_53 BM_53_28 -#define BM_54_28 0x007ffffff0000000 -#define BM_28_54 BM_54_28 -#define BM_55_28 0x00fffffff0000000 -#define BM_28_55 BM_55_28 -#define BM_56_28 0x01fffffff0000000 -#define BM_28_56 BM_56_28 -#define BM_57_28 0x03fffffff0000000 -#define BM_28_57 BM_57_28 -#define BM_58_28 0x07fffffff0000000 -#define BM_28_58 BM_58_28 -#define BM_59_28 0x0ffffffff0000000 -#define BM_28_59 BM_59_28 -#define BM_60_28 0x1ffffffff0000000 -#define BM_28_60 BM_60_28 -#define BM_61_28 0x3ffffffff0000000 -#define BM_28_61 BM_61_28 -#define BM_62_28 0x7ffffffff0000000 -#define BM_28_62 BM_62_28 -#define BM_63_28 0xfffffffff0000000 -#define BM_28_63 BM_63_28 -#define BM_29_29 0x0000000020000000 -#define BM_30_29 0x0000000060000000 -#define BM_29_30 BM_30_29 -#define BM_31_29 0x00000000e0000000 -#define BM_29_31 BM_31_29 -#define BM_32_29 0x00000001e0000000 -#define BM_29_32 BM_32_29 -#define BM_33_29 0x00000003e0000000 -#define BM_29_33 BM_33_29 -#define BM_34_29 0x00000007e0000000 -#define BM_29_34 BM_34_29 -#define BM_35_29 0x0000000fe0000000 -#define BM_29_35 BM_35_29 -#define BM_36_29 0x0000001fe0000000 -#define BM_29_36 BM_36_29 -#define BM_37_29 0x0000003fe0000000 -#define BM_29_37 BM_37_29 -#define BM_38_29 0x0000007fe0000000 -#define BM_29_38 BM_38_29 -#define BM_39_29 0x000000ffe0000000 -#define BM_29_39 BM_39_29 -#define BM_40_29 0x000001ffe0000000 -#define BM_29_40 BM_40_29 -#define BM_41_29 0x000003ffe0000000 -#define BM_29_41 BM_41_29 -#define BM_42_29 0x000007ffe0000000 -#define BM_29_42 BM_42_29 -#define BM_43_29 0x00000fffe0000000 -#define BM_29_43 BM_43_29 -#define BM_44_29 0x00001fffe0000000 -#define BM_29_44 BM_44_29 -#define BM_45_29 0x00003fffe0000000 -#define BM_29_45 BM_45_29 -#define BM_46_29 0x00007fffe0000000 -#define BM_29_46 BM_46_29 -#define BM_47_29 0x0000ffffe0000000 -#define BM_29_47 BM_47_29 -#define BM_48_29 0x0001ffffe0000000 -#define BM_29_48 BM_48_29 -#define BM_49_29 0x0003ffffe0000000 -#define BM_29_49 BM_49_29 -#define BM_50_29 0x0007ffffe0000000 -#define BM_29_50 BM_50_29 -#define BM_51_29 0x000fffffe0000000 -#define BM_29_51 BM_51_29 -#define BM_52_29 0x001fffffe0000000 -#define BM_29_52 BM_52_29 -#define BM_53_29 0x003fffffe0000000 -#define BM_29_53 BM_53_29 -#define BM_54_29 0x007fffffe0000000 -#define BM_29_54 BM_54_29 -#define BM_55_29 0x00ffffffe0000000 -#define BM_29_55 BM_55_29 -#define BM_56_29 0x01ffffffe0000000 -#define BM_29_56 BM_56_29 -#define BM_57_29 0x03ffffffe0000000 -#define BM_29_57 BM_57_29 -#define BM_58_29 0x07ffffffe0000000 -#define BM_29_58 BM_58_29 -#define BM_59_29 0x0fffffffe0000000 -#define BM_29_59 BM_59_29 -#define BM_60_29 0x1fffffffe0000000 -#define BM_29_60 BM_60_29 -#define BM_61_29 0x3fffffffe0000000 -#define BM_29_61 BM_61_29 -#define BM_62_29 0x7fffffffe0000000 -#define BM_29_62 BM_62_29 -#define BM_63_29 0xffffffffe0000000 -#define BM_29_63 BM_63_29 -#define BM_30_30 0x0000000040000000 -#define BM_31_30 0x00000000c0000000 -#define BM_30_31 BM_31_30 -#define BM_32_30 0x00000001c0000000 -#define BM_30_32 BM_32_30 -#define BM_33_30 0x00000003c0000000 -#define BM_30_33 BM_33_30 -#define BM_34_30 0x00000007c0000000 -#define BM_30_34 BM_34_30 -#define BM_35_30 0x0000000fc0000000 -#define BM_30_35 BM_35_30 -#define BM_36_30 0x0000001fc0000000 -#define BM_30_36 BM_36_30 -#define BM_37_30 0x0000003fc0000000 -#define BM_30_37 BM_37_30 -#define BM_38_30 0x0000007fc0000000 -#define BM_30_38 BM_38_30 -#define BM_39_30 0x000000ffc0000000 -#define BM_30_39 BM_39_30 -#define BM_40_30 0x000001ffc0000000 -#define BM_30_40 BM_40_30 -#define BM_41_30 0x000003ffc0000000 -#define BM_30_41 BM_41_30 -#define BM_42_30 0x000007ffc0000000 -#define BM_30_42 BM_42_30 -#define BM_43_30 0x00000fffc0000000 -#define BM_30_43 BM_43_30 -#define BM_44_30 0x00001fffc0000000 -#define BM_30_44 BM_44_30 -#define BM_45_30 0x00003fffc0000000 -#define BM_30_45 BM_45_30 -#define BM_46_30 0x00007fffc0000000 -#define BM_30_46 BM_46_30 -#define BM_47_30 0x0000ffffc0000000 -#define BM_30_47 BM_47_30 -#define BM_48_30 0x0001ffffc0000000 -#define BM_30_48 BM_48_30 -#define BM_49_30 0x0003ffffc0000000 -#define BM_30_49 BM_49_30 -#define BM_50_30 0x0007ffffc0000000 -#define BM_30_50 BM_50_30 -#define BM_51_30 0x000fffffc0000000 -#define BM_30_51 BM_51_30 -#define BM_52_30 0x001fffffc0000000 -#define BM_30_52 BM_52_30 -#define BM_53_30 0x003fffffc0000000 -#define BM_30_53 BM_53_30 -#define BM_54_30 0x007fffffc0000000 -#define BM_30_54 BM_54_30 -#define BM_55_30 0x00ffffffc0000000 -#define BM_30_55 BM_55_30 -#define BM_56_30 0x01ffffffc0000000 -#define BM_30_56 BM_56_30 -#define BM_57_30 0x03ffffffc0000000 -#define BM_30_57 BM_57_30 -#define BM_58_30 0x07ffffffc0000000 -#define BM_30_58 BM_58_30 -#define BM_59_30 0x0fffffffc0000000 -#define BM_30_59 BM_59_30 -#define BM_60_30 0x1fffffffc0000000 -#define BM_30_60 BM_60_30 -#define BM_61_30 0x3fffffffc0000000 -#define BM_30_61 BM_61_30 -#define BM_62_30 0x7fffffffc0000000 -#define BM_30_62 BM_62_30 -#define BM_63_30 0xffffffffc0000000 -#define BM_30_63 BM_63_30 -#define BM_31_31 0x0000000080000000 -#define BM_32_31 0x0000000180000000 -#define BM_31_32 BM_32_31 -#define BM_33_31 0x0000000380000000 -#define BM_31_33 BM_33_31 -#define BM_34_31 0x0000000780000000 -#define BM_31_34 BM_34_31 -#define BM_35_31 0x0000000f80000000 -#define BM_31_35 BM_35_31 -#define BM_36_31 0x0000001f80000000 -#define BM_31_36 BM_36_31 -#define BM_37_31 0x0000003f80000000 -#define BM_31_37 BM_37_31 -#define BM_38_31 0x0000007f80000000 -#define BM_31_38 BM_38_31 -#define BM_39_31 0x000000ff80000000 -#define BM_31_39 BM_39_31 -#define BM_40_31 0x000001ff80000000 -#define BM_31_40 BM_40_31 -#define BM_41_31 0x000003ff80000000 -#define BM_31_41 BM_41_31 -#define BM_42_31 0x000007ff80000000 -#define BM_31_42 BM_42_31 -#define BM_43_31 0x00000fff80000000 -#define BM_31_43 BM_43_31 -#define BM_44_31 0x00001fff80000000 -#define BM_31_44 BM_44_31 -#define BM_45_31 0x00003fff80000000 -#define BM_31_45 BM_45_31 -#define BM_46_31 0x00007fff80000000 -#define BM_31_46 BM_46_31 -#define BM_47_31 0x0000ffff80000000 -#define BM_31_47 BM_47_31 -#define BM_48_31 0x0001ffff80000000 -#define BM_31_48 BM_48_31 -#define BM_49_31 0x0003ffff80000000 -#define BM_31_49 BM_49_31 -#define BM_50_31 0x0007ffff80000000 -#define BM_31_50 BM_50_31 -#define BM_51_31 0x000fffff80000000 -#define BM_31_51 BM_51_31 -#define BM_52_31 0x001fffff80000000 -#define BM_31_52 BM_52_31 -#define BM_53_31 0x003fffff80000000 -#define BM_31_53 BM_53_31 -#define BM_54_31 0x007fffff80000000 -#define BM_31_54 BM_54_31 -#define BM_55_31 0x00ffffff80000000 -#define BM_31_55 BM_55_31 -#define BM_56_31 0x01ffffff80000000 -#define BM_31_56 BM_56_31 -#define BM_57_31 0x03ffffff80000000 -#define BM_31_57 BM_57_31 -#define BM_58_31 0x07ffffff80000000 -#define BM_31_58 BM_58_31 -#define BM_59_31 0x0fffffff80000000 -#define BM_31_59 BM_59_31 -#define BM_60_31 0x1fffffff80000000 -#define BM_31_60 BM_60_31 -#define BM_61_31 0x3fffffff80000000 -#define BM_31_61 BM_61_31 -#define BM_62_31 0x7fffffff80000000 -#define BM_31_62 BM_62_31 -#define BM_63_31 0xffffffff80000000 -#define BM_31_63 BM_63_31 -#define BM_32_32 0x0000000100000000 -#define BM_33_32 0x0000000300000000 -#define BM_32_33 BM_33_32 -#define BM_34_32 0x0000000700000000 -#define BM_32_34 BM_34_32 -#define BM_35_32 0x0000000f00000000 -#define BM_32_35 BM_35_32 -#define BM_36_32 0x0000001f00000000 -#define BM_32_36 BM_36_32 -#define BM_37_32 0x0000003f00000000 -#define BM_32_37 BM_37_32 -#define BM_38_32 0x0000007f00000000 -#define BM_32_38 BM_38_32 -#define BM_39_32 0x000000ff00000000 -#define BM_32_39 BM_39_32 -#define BM_40_32 0x000001ff00000000 -#define BM_32_40 BM_40_32 -#define BM_41_32 0x000003ff00000000 -#define BM_32_41 BM_41_32 -#define BM_42_32 0x000007ff00000000 -#define BM_32_42 BM_42_32 -#define BM_43_32 0x00000fff00000000 -#define BM_32_43 BM_43_32 -#define BM_44_32 0x00001fff00000000 -#define BM_32_44 BM_44_32 -#define BM_45_32 0x00003fff00000000 -#define BM_32_45 BM_45_32 -#define BM_46_32 0x00007fff00000000 -#define BM_32_46 BM_46_32 -#define BM_47_32 0x0000ffff00000000 -#define BM_32_47 BM_47_32 -#define BM_48_32 0x0001ffff00000000 -#define BM_32_48 BM_48_32 -#define BM_49_32 0x0003ffff00000000 -#define BM_32_49 BM_49_32 -#define BM_50_32 0x0007ffff00000000 -#define BM_32_50 BM_50_32 -#define BM_51_32 0x000fffff00000000 -#define BM_32_51 BM_51_32 -#define BM_52_32 0x001fffff00000000 -#define BM_32_52 BM_52_32 -#define BM_53_32 0x003fffff00000000 -#define BM_32_53 BM_53_32 -#define BM_54_32 0x007fffff00000000 -#define BM_32_54 BM_54_32 -#define BM_55_32 0x00ffffff00000000 -#define BM_32_55 BM_55_32 -#define BM_56_32 0x01ffffff00000000 -#define BM_32_56 BM_56_32 -#define BM_57_32 0x03ffffff00000000 -#define BM_32_57 BM_57_32 -#define BM_58_32 0x07ffffff00000000 -#define BM_32_58 BM_58_32 -#define BM_59_32 0x0fffffff00000000 -#define BM_32_59 BM_59_32 -#define BM_60_32 0x1fffffff00000000 -#define BM_32_60 BM_60_32 -#define BM_61_32 0x3fffffff00000000 -#define BM_32_61 BM_61_32 -#define BM_62_32 0x7fffffff00000000 -#define BM_32_62 BM_62_32 -#define BM_63_32 0xffffffff00000000 -#define BM_32_63 BM_63_32 -#define BM_33_33 0x0000000200000000 -#define BM_34_33 0x0000000600000000 -#define BM_33_34 BM_34_33 -#define BM_35_33 0x0000000e00000000 -#define BM_33_35 BM_35_33 -#define BM_36_33 0x0000001e00000000 -#define BM_33_36 BM_36_33 -#define BM_37_33 0x0000003e00000000 -#define BM_33_37 BM_37_33 -#define BM_38_33 0x0000007e00000000 -#define BM_33_38 BM_38_33 -#define BM_39_33 0x000000fe00000000 -#define BM_33_39 BM_39_33 -#define BM_40_33 0x000001fe00000000 -#define BM_33_40 BM_40_33 -#define BM_41_33 0x000003fe00000000 -#define BM_33_41 BM_41_33 -#define BM_42_33 0x000007fe00000000 -#define BM_33_42 BM_42_33 -#define BM_43_33 0x00000ffe00000000 -#define BM_33_43 BM_43_33 -#define BM_44_33 0x00001ffe00000000 -#define BM_33_44 BM_44_33 -#define BM_45_33 0x00003ffe00000000 -#define BM_33_45 BM_45_33 -#define BM_46_33 0x00007ffe00000000 -#define BM_33_46 BM_46_33 -#define BM_47_33 0x0000fffe00000000 -#define BM_33_47 BM_47_33 -#define BM_48_33 0x0001fffe00000000 -#define BM_33_48 BM_48_33 -#define BM_49_33 0x0003fffe00000000 -#define BM_33_49 BM_49_33 -#define BM_50_33 0x0007fffe00000000 -#define BM_33_50 BM_50_33 -#define BM_51_33 0x000ffffe00000000 -#define BM_33_51 BM_51_33 -#define BM_52_33 0x001ffffe00000000 -#define BM_33_52 BM_52_33 -#define BM_53_33 0x003ffffe00000000 -#define BM_33_53 BM_53_33 -#define BM_54_33 0x007ffffe00000000 -#define BM_33_54 BM_54_33 -#define BM_55_33 0x00fffffe00000000 -#define BM_33_55 BM_55_33 -#define BM_56_33 0x01fffffe00000000 -#define BM_33_56 BM_56_33 -#define BM_57_33 0x03fffffe00000000 -#define BM_33_57 BM_57_33 -#define BM_58_33 0x07fffffe00000000 -#define BM_33_58 BM_58_33 -#define BM_59_33 0x0ffffffe00000000 -#define BM_33_59 BM_59_33 -#define BM_60_33 0x1ffffffe00000000 -#define BM_33_60 BM_60_33 -#define BM_61_33 0x3ffffffe00000000 -#define BM_33_61 BM_61_33 -#define BM_62_33 0x7ffffffe00000000 -#define BM_33_62 BM_62_33 -#define BM_63_33 0xfffffffe00000000 -#define BM_33_63 BM_63_33 -#define BM_34_34 0x0000000400000000 -#define BM_35_34 0x0000000c00000000 -#define BM_34_35 BM_35_34 -#define BM_36_34 0x0000001c00000000 -#define BM_34_36 BM_36_34 -#define BM_37_34 0x0000003c00000000 -#define BM_34_37 BM_37_34 -#define BM_38_34 0x0000007c00000000 -#define BM_34_38 BM_38_34 -#define BM_39_34 0x000000fc00000000 -#define BM_34_39 BM_39_34 -#define BM_40_34 0x000001fc00000000 -#define BM_34_40 BM_40_34 -#define BM_41_34 0x000003fc00000000 -#define BM_34_41 BM_41_34 -#define BM_42_34 0x000007fc00000000 -#define BM_34_42 BM_42_34 -#define BM_43_34 0x00000ffc00000000 -#define BM_34_43 BM_43_34 -#define BM_44_34 0x00001ffc00000000 -#define BM_34_44 BM_44_34 -#define BM_45_34 0x00003ffc00000000 -#define BM_34_45 BM_45_34 -#define BM_46_34 0x00007ffc00000000 -#define BM_34_46 BM_46_34 -#define BM_47_34 0x0000fffc00000000 -#define BM_34_47 BM_47_34 -#define BM_48_34 0x0001fffc00000000 -#define BM_34_48 BM_48_34 -#define BM_49_34 0x0003fffc00000000 -#define BM_34_49 BM_49_34 -#define BM_50_34 0x0007fffc00000000 -#define BM_34_50 BM_50_34 -#define BM_51_34 0x000ffffc00000000 -#define BM_34_51 BM_51_34 -#define BM_52_34 0x001ffffc00000000 -#define BM_34_52 BM_52_34 -#define BM_53_34 0x003ffffc00000000 -#define BM_34_53 BM_53_34 -#define BM_54_34 0x007ffffc00000000 -#define BM_34_54 BM_54_34 -#define BM_55_34 0x00fffffc00000000 -#define BM_34_55 BM_55_34 -#define BM_56_34 0x01fffffc00000000 -#define BM_34_56 BM_56_34 -#define BM_57_34 0x03fffffc00000000 -#define BM_34_57 BM_57_34 -#define BM_58_34 0x07fffffc00000000 -#define BM_34_58 BM_58_34 -#define BM_59_34 0x0ffffffc00000000 -#define BM_34_59 BM_59_34 -#define BM_60_34 0x1ffffffc00000000 -#define BM_34_60 BM_60_34 -#define BM_61_34 0x3ffffffc00000000 -#define BM_34_61 BM_61_34 -#define BM_62_34 0x7ffffffc00000000 -#define BM_34_62 BM_62_34 -#define BM_63_34 0xfffffffc00000000 -#define BM_34_63 BM_63_34 -#define BM_35_35 0x0000000800000000 -#define BM_36_35 0x0000001800000000 -#define BM_35_36 BM_36_35 -#define BM_37_35 0x0000003800000000 -#define BM_35_37 BM_37_35 -#define BM_38_35 0x0000007800000000 -#define BM_35_38 BM_38_35 -#define BM_39_35 0x000000f800000000 -#define BM_35_39 BM_39_35 -#define BM_40_35 0x000001f800000000 -#define BM_35_40 BM_40_35 -#define BM_41_35 0x000003f800000000 -#define BM_35_41 BM_41_35 -#define BM_42_35 0x000007f800000000 -#define BM_35_42 BM_42_35 -#define BM_43_35 0x00000ff800000000 -#define BM_35_43 BM_43_35 -#define BM_44_35 0x00001ff800000000 -#define BM_35_44 BM_44_35 -#define BM_45_35 0x00003ff800000000 -#define BM_35_45 BM_45_35 -#define BM_46_35 0x00007ff800000000 -#define BM_35_46 BM_46_35 -#define BM_47_35 0x0000fff800000000 -#define BM_35_47 BM_47_35 -#define BM_48_35 0x0001fff800000000 -#define BM_35_48 BM_48_35 -#define BM_49_35 0x0003fff800000000 -#define BM_35_49 BM_49_35 -#define BM_50_35 0x0007fff800000000 -#define BM_35_50 BM_50_35 -#define BM_51_35 0x000ffff800000000 -#define BM_35_51 BM_51_35 -#define BM_52_35 0x001ffff800000000 -#define BM_35_52 BM_52_35 -#define BM_53_35 0x003ffff800000000 -#define BM_35_53 BM_53_35 -#define BM_54_35 0x007ffff800000000 -#define BM_35_54 BM_54_35 -#define BM_55_35 0x00fffff800000000 -#define BM_35_55 BM_55_35 -#define BM_56_35 0x01fffff800000000 -#define BM_35_56 BM_56_35 -#define BM_57_35 0x03fffff800000000 -#define BM_35_57 BM_57_35 -#define BM_58_35 0x07fffff800000000 -#define BM_35_58 BM_58_35 -#define BM_59_35 0x0ffffff800000000 -#define BM_35_59 BM_59_35 -#define BM_60_35 0x1ffffff800000000 -#define BM_35_60 BM_60_35 -#define BM_61_35 0x3ffffff800000000 -#define BM_35_61 BM_61_35 -#define BM_62_35 0x7ffffff800000000 -#define BM_35_62 BM_62_35 -#define BM_63_35 0xfffffff800000000 -#define BM_35_63 BM_63_35 -#define BM_36_36 0x0000001000000000 -#define BM_37_36 0x0000003000000000 -#define BM_36_37 BM_37_36 -#define BM_38_36 0x0000007000000000 -#define BM_36_38 BM_38_36 -#define BM_39_36 0x000000f000000000 -#define BM_36_39 BM_39_36 -#define BM_40_36 0x000001f000000000 -#define BM_36_40 BM_40_36 -#define BM_41_36 0x000003f000000000 -#define BM_36_41 BM_41_36 -#define BM_42_36 0x000007f000000000 -#define BM_36_42 BM_42_36 -#define BM_43_36 0x00000ff000000000 -#define BM_36_43 BM_43_36 -#define BM_44_36 0x00001ff000000000 -#define BM_36_44 BM_44_36 -#define BM_45_36 0x00003ff000000000 -#define BM_36_45 BM_45_36 -#define BM_46_36 0x00007ff000000000 -#define BM_36_46 BM_46_36 -#define BM_47_36 0x0000fff000000000 -#define BM_36_47 BM_47_36 -#define BM_48_36 0x0001fff000000000 -#define BM_36_48 BM_48_36 -#define BM_49_36 0x0003fff000000000 -#define BM_36_49 BM_49_36 -#define BM_50_36 0x0007fff000000000 -#define BM_36_50 BM_50_36 -#define BM_51_36 0x000ffff000000000 -#define BM_36_51 BM_51_36 -#define BM_52_36 0x001ffff000000000 -#define BM_36_52 BM_52_36 -#define BM_53_36 0x003ffff000000000 -#define BM_36_53 BM_53_36 -#define BM_54_36 0x007ffff000000000 -#define BM_36_54 BM_54_36 -#define BM_55_36 0x00fffff000000000 -#define BM_36_55 BM_55_36 -#define BM_56_36 0x01fffff000000000 -#define BM_36_56 BM_56_36 -#define BM_57_36 0x03fffff000000000 -#define BM_36_57 BM_57_36 -#define BM_58_36 0x07fffff000000000 -#define BM_36_58 BM_58_36 -#define BM_59_36 0x0ffffff000000000 -#define BM_36_59 BM_59_36 -#define BM_60_36 0x1ffffff000000000 -#define BM_36_60 BM_60_36 -#define BM_61_36 0x3ffffff000000000 -#define BM_36_61 BM_61_36 -#define BM_62_36 0x7ffffff000000000 -#define BM_36_62 BM_62_36 -#define BM_63_36 0xfffffff000000000 -#define BM_36_63 BM_63_36 -#define BM_37_37 0x0000002000000000 -#define BM_38_37 0x0000006000000000 -#define BM_37_38 BM_38_37 -#define BM_39_37 0x000000e000000000 -#define BM_37_39 BM_39_37 -#define BM_40_37 0x000001e000000000 -#define BM_37_40 BM_40_37 -#define BM_41_37 0x000003e000000000 -#define BM_37_41 BM_41_37 -#define BM_42_37 0x000007e000000000 -#define BM_37_42 BM_42_37 -#define BM_43_37 0x00000fe000000000 -#define BM_37_43 BM_43_37 -#define BM_44_37 0x00001fe000000000 -#define BM_37_44 BM_44_37 -#define BM_45_37 0x00003fe000000000 -#define BM_37_45 BM_45_37 -#define BM_46_37 0x00007fe000000000 -#define BM_37_46 BM_46_37 -#define BM_47_37 0x0000ffe000000000 -#define BM_37_47 BM_47_37 -#define BM_48_37 0x0001ffe000000000 -#define BM_37_48 BM_48_37 -#define BM_49_37 0x0003ffe000000000 -#define BM_37_49 BM_49_37 -#define BM_50_37 0x0007ffe000000000 -#define BM_37_50 BM_50_37 -#define BM_51_37 0x000fffe000000000 -#define BM_37_51 BM_51_37 -#define BM_52_37 0x001fffe000000000 -#define BM_37_52 BM_52_37 -#define BM_53_37 0x003fffe000000000 -#define BM_37_53 BM_53_37 -#define BM_54_37 0x007fffe000000000 -#define BM_37_54 BM_54_37 -#define BM_55_37 0x00ffffe000000000 -#define BM_37_55 BM_55_37 -#define BM_56_37 0x01ffffe000000000 -#define BM_37_56 BM_56_37 -#define BM_57_37 0x03ffffe000000000 -#define BM_37_57 BM_57_37 -#define BM_58_37 0x07ffffe000000000 -#define BM_37_58 BM_58_37 -#define BM_59_37 0x0fffffe000000000 -#define BM_37_59 BM_59_37 -#define BM_60_37 0x1fffffe000000000 -#define BM_37_60 BM_60_37 -#define BM_61_37 0x3fffffe000000000 -#define BM_37_61 BM_61_37 -#define BM_62_37 0x7fffffe000000000 -#define BM_37_62 BM_62_37 -#define BM_63_37 0xffffffe000000000 -#define BM_37_63 BM_63_37 -#define BM_38_38 0x0000004000000000 -#define BM_39_38 0x000000c000000000 -#define BM_38_39 BM_39_38 -#define BM_40_38 0x000001c000000000 -#define BM_38_40 BM_40_38 -#define BM_41_38 0x000003c000000000 -#define BM_38_41 BM_41_38 -#define BM_42_38 0x000007c000000000 -#define BM_38_42 BM_42_38 -#define BM_43_38 0x00000fc000000000 -#define BM_38_43 BM_43_38 -#define BM_44_38 0x00001fc000000000 -#define BM_38_44 BM_44_38 -#define BM_45_38 0x00003fc000000000 -#define BM_38_45 BM_45_38 -#define BM_46_38 0x00007fc000000000 -#define BM_38_46 BM_46_38 -#define BM_47_38 0x0000ffc000000000 -#define BM_38_47 BM_47_38 -#define BM_48_38 0x0001ffc000000000 -#define BM_38_48 BM_48_38 -#define BM_49_38 0x0003ffc000000000 -#define BM_38_49 BM_49_38 -#define BM_50_38 0x0007ffc000000000 -#define BM_38_50 BM_50_38 -#define BM_51_38 0x000fffc000000000 -#define BM_38_51 BM_51_38 -#define BM_52_38 0x001fffc000000000 -#define BM_38_52 BM_52_38 -#define BM_53_38 0x003fffc000000000 -#define BM_38_53 BM_53_38 -#define BM_54_38 0x007fffc000000000 -#define BM_38_54 BM_54_38 -#define BM_55_38 0x00ffffc000000000 -#define BM_38_55 BM_55_38 -#define BM_56_38 0x01ffffc000000000 -#define BM_38_56 BM_56_38 -#define BM_57_38 0x03ffffc000000000 -#define BM_38_57 BM_57_38 -#define BM_58_38 0x07ffffc000000000 -#define BM_38_58 BM_58_38 -#define BM_59_38 0x0fffffc000000000 -#define BM_38_59 BM_59_38 -#define BM_60_38 0x1fffffc000000000 -#define BM_38_60 BM_60_38 -#define BM_61_38 0x3fffffc000000000 -#define BM_38_61 BM_61_38 -#define BM_62_38 0x7fffffc000000000 -#define BM_38_62 BM_62_38 -#define BM_63_38 0xffffffc000000000 -#define BM_38_63 BM_63_38 -#define BM_39_39 0x0000008000000000 -#define BM_40_39 0x0000018000000000 -#define BM_39_40 BM_40_39 -#define BM_41_39 0x0000038000000000 -#define BM_39_41 BM_41_39 -#define BM_42_39 0x0000078000000000 -#define BM_39_42 BM_42_39 -#define BM_43_39 0x00000f8000000000 -#define BM_39_43 BM_43_39 -#define BM_44_39 0x00001f8000000000 -#define BM_39_44 BM_44_39 -#define BM_45_39 0x00003f8000000000 -#define BM_39_45 BM_45_39 -#define BM_46_39 0x00007f8000000000 -#define BM_39_46 BM_46_39 -#define BM_47_39 0x0000ff8000000000 -#define BM_39_47 BM_47_39 -#define BM_48_39 0x0001ff8000000000 -#define BM_39_48 BM_48_39 -#define BM_49_39 0x0003ff8000000000 -#define BM_39_49 BM_49_39 -#define BM_50_39 0x0007ff8000000000 -#define BM_39_50 BM_50_39 -#define BM_51_39 0x000fff8000000000 -#define BM_39_51 BM_51_39 -#define BM_52_39 0x001fff8000000000 -#define BM_39_52 BM_52_39 -#define BM_53_39 0x003fff8000000000 -#define BM_39_53 BM_53_39 -#define BM_54_39 0x007fff8000000000 -#define BM_39_54 BM_54_39 -#define BM_55_39 0x00ffff8000000000 -#define BM_39_55 BM_55_39 -#define BM_56_39 0x01ffff8000000000 -#define BM_39_56 BM_56_39 -#define BM_57_39 0x03ffff8000000000 -#define BM_39_57 BM_57_39 -#define BM_58_39 0x07ffff8000000000 -#define BM_39_58 BM_58_39 -#define BM_59_39 0x0fffff8000000000 -#define BM_39_59 BM_59_39 -#define BM_60_39 0x1fffff8000000000 -#define BM_39_60 BM_60_39 -#define BM_61_39 0x3fffff8000000000 -#define BM_39_61 BM_61_39 -#define BM_62_39 0x7fffff8000000000 -#define BM_39_62 BM_62_39 -#define BM_63_39 0xffffff8000000000 -#define BM_39_63 BM_63_39 -#define BM_40_40 0x0000010000000000 -#define BM_41_40 0x0000030000000000 -#define BM_40_41 BM_41_40 -#define BM_42_40 0x0000070000000000 -#define BM_40_42 BM_42_40 -#define BM_43_40 0x00000f0000000000 -#define BM_40_43 BM_43_40 -#define BM_44_40 0x00001f0000000000 -#define BM_40_44 BM_44_40 -#define BM_45_40 0x00003f0000000000 -#define BM_40_45 BM_45_40 -#define BM_46_40 0x00007f0000000000 -#define BM_40_46 BM_46_40 -#define BM_47_40 0x0000ff0000000000 -#define BM_40_47 BM_47_40 -#define BM_48_40 0x0001ff0000000000 -#define BM_40_48 BM_48_40 -#define BM_49_40 0x0003ff0000000000 -#define BM_40_49 BM_49_40 -#define BM_50_40 0x0007ff0000000000 -#define BM_40_50 BM_50_40 -#define BM_51_40 0x000fff0000000000 -#define BM_40_51 BM_51_40 -#define BM_52_40 0x001fff0000000000 -#define BM_40_52 BM_52_40 -#define BM_53_40 0x003fff0000000000 -#define BM_40_53 BM_53_40 -#define BM_54_40 0x007fff0000000000 -#define BM_40_54 BM_54_40 -#define BM_55_40 0x00ffff0000000000 -#define BM_40_55 BM_55_40 -#define BM_56_40 0x01ffff0000000000 -#define BM_40_56 BM_56_40 -#define BM_57_40 0x03ffff0000000000 -#define BM_40_57 BM_57_40 -#define BM_58_40 0x07ffff0000000000 -#define BM_40_58 BM_58_40 -#define BM_59_40 0x0fffff0000000000 -#define BM_40_59 BM_59_40 -#define BM_60_40 0x1fffff0000000000 -#define BM_40_60 BM_60_40 -#define BM_61_40 0x3fffff0000000000 -#define BM_40_61 BM_61_40 -#define BM_62_40 0x7fffff0000000000 -#define BM_40_62 BM_62_40 -#define BM_63_40 0xffffff0000000000 -#define BM_40_63 BM_63_40 -#define BM_41_41 0x0000020000000000 -#define BM_42_41 0x0000060000000000 -#define BM_41_42 BM_42_41 -#define BM_43_41 0x00000e0000000000 -#define BM_41_43 BM_43_41 -#define BM_44_41 0x00001e0000000000 -#define BM_41_44 BM_44_41 -#define BM_45_41 0x00003e0000000000 -#define BM_41_45 BM_45_41 -#define BM_46_41 0x00007e0000000000 -#define BM_41_46 BM_46_41 -#define BM_47_41 0x0000fe0000000000 -#define BM_41_47 BM_47_41 -#define BM_48_41 0x0001fe0000000000 -#define BM_41_48 BM_48_41 -#define BM_49_41 0x0003fe0000000000 -#define BM_41_49 BM_49_41 -#define BM_50_41 0x0007fe0000000000 -#define BM_41_50 BM_50_41 -#define BM_51_41 0x000ffe0000000000 -#define BM_41_51 BM_51_41 -#define BM_52_41 0x001ffe0000000000 -#define BM_41_52 BM_52_41 -#define BM_53_41 0x003ffe0000000000 -#define BM_41_53 BM_53_41 -#define BM_54_41 0x007ffe0000000000 -#define BM_41_54 BM_54_41 -#define BM_55_41 0x00fffe0000000000 -#define BM_41_55 BM_55_41 -#define BM_56_41 0x01fffe0000000000 -#define BM_41_56 BM_56_41 -#define BM_57_41 0x03fffe0000000000 -#define BM_41_57 BM_57_41 -#define BM_58_41 0x07fffe0000000000 -#define BM_41_58 BM_58_41 -#define BM_59_41 0x0ffffe0000000000 -#define BM_41_59 BM_59_41 -#define BM_60_41 0x1ffffe0000000000 -#define BM_41_60 BM_60_41 -#define BM_61_41 0x3ffffe0000000000 -#define BM_41_61 BM_61_41 -#define BM_62_41 0x7ffffe0000000000 -#define BM_41_62 BM_62_41 -#define BM_63_41 0xfffffe0000000000 -#define BM_41_63 BM_63_41 -#define BM_42_42 0x0000040000000000 -#define BM_43_42 0x00000c0000000000 -#define BM_42_43 BM_43_42 -#define BM_44_42 0x00001c0000000000 -#define BM_42_44 BM_44_42 -#define BM_45_42 0x00003c0000000000 -#define BM_42_45 BM_45_42 -#define BM_46_42 0x00007c0000000000 -#define BM_42_46 BM_46_42 -#define BM_47_42 0x0000fc0000000000 -#define BM_42_47 BM_47_42 -#define BM_48_42 0x0001fc0000000000 -#define BM_42_48 BM_48_42 -#define BM_49_42 0x0003fc0000000000 -#define BM_42_49 BM_49_42 -#define BM_50_42 0x0007fc0000000000 -#define BM_42_50 BM_50_42 -#define BM_51_42 0x000ffc0000000000 -#define BM_42_51 BM_51_42 -#define BM_52_42 0x001ffc0000000000 -#define BM_42_52 BM_52_42 -#define BM_53_42 0x003ffc0000000000 -#define BM_42_53 BM_53_42 -#define BM_54_42 0x007ffc0000000000 -#define BM_42_54 BM_54_42 -#define BM_55_42 0x00fffc0000000000 -#define BM_42_55 BM_55_42 -#define BM_56_42 0x01fffc0000000000 -#define BM_42_56 BM_56_42 -#define BM_57_42 0x03fffc0000000000 -#define BM_42_57 BM_57_42 -#define BM_58_42 0x07fffc0000000000 -#define BM_42_58 BM_58_42 -#define BM_59_42 0x0ffffc0000000000 -#define BM_42_59 BM_59_42 -#define BM_60_42 0x1ffffc0000000000 -#define BM_42_60 BM_60_42 -#define BM_61_42 0x3ffffc0000000000 -#define BM_42_61 BM_61_42 -#define BM_62_42 0x7ffffc0000000000 -#define BM_42_62 BM_62_42 -#define BM_63_42 0xfffffc0000000000 -#define BM_42_63 BM_63_42 -#define BM_43_43 0x0000080000000000 -#define BM_44_43 0x0000180000000000 -#define BM_43_44 BM_44_43 -#define BM_45_43 0x0000380000000000 -#define BM_43_45 BM_45_43 -#define BM_46_43 0x0000780000000000 -#define BM_43_46 BM_46_43 -#define BM_47_43 0x0000f80000000000 -#define BM_43_47 BM_47_43 -#define BM_48_43 0x0001f80000000000 -#define BM_43_48 BM_48_43 -#define BM_49_43 0x0003f80000000000 -#define BM_43_49 BM_49_43 -#define BM_50_43 0x0007f80000000000 -#define BM_43_50 BM_50_43 -#define BM_51_43 0x000ff80000000000 -#define BM_43_51 BM_51_43 -#define BM_52_43 0x001ff80000000000 -#define BM_43_52 BM_52_43 -#define BM_53_43 0x003ff80000000000 -#define BM_43_53 BM_53_43 -#define BM_54_43 0x007ff80000000000 -#define BM_43_54 BM_54_43 -#define BM_55_43 0x00fff80000000000 -#define BM_43_55 BM_55_43 -#define BM_56_43 0x01fff80000000000 -#define BM_43_56 BM_56_43 -#define BM_57_43 0x03fff80000000000 -#define BM_43_57 BM_57_43 -#define BM_58_43 0x07fff80000000000 -#define BM_43_58 BM_58_43 -#define BM_59_43 0x0ffff80000000000 -#define BM_43_59 BM_59_43 -#define BM_60_43 0x1ffff80000000000 -#define BM_43_60 BM_60_43 -#define BM_61_43 0x3ffff80000000000 -#define BM_43_61 BM_61_43 -#define BM_62_43 0x7ffff80000000000 -#define BM_43_62 BM_62_43 -#define BM_63_43 0xfffff80000000000 -#define BM_43_63 BM_63_43 -#define BM_44_44 0x0000100000000000 -#define BM_45_44 0x0000300000000000 -#define BM_44_45 BM_45_44 -#define BM_46_44 0x0000700000000000 -#define BM_44_46 BM_46_44 -#define BM_47_44 0x0000f00000000000 -#define BM_44_47 BM_47_44 -#define BM_48_44 0x0001f00000000000 -#define BM_44_48 BM_48_44 -#define BM_49_44 0x0003f00000000000 -#define BM_44_49 BM_49_44 -#define BM_50_44 0x0007f00000000000 -#define BM_44_50 BM_50_44 -#define BM_51_44 0x000ff00000000000 -#define BM_44_51 BM_51_44 -#define BM_52_44 0x001ff00000000000 -#define BM_44_52 BM_52_44 -#define BM_53_44 0x003ff00000000000 -#define BM_44_53 BM_53_44 -#define BM_54_44 0x007ff00000000000 -#define BM_44_54 BM_54_44 -#define BM_55_44 0x00fff00000000000 -#define BM_44_55 BM_55_44 -#define BM_56_44 0x01fff00000000000 -#define BM_44_56 BM_56_44 -#define BM_57_44 0x03fff00000000000 -#define BM_44_57 BM_57_44 -#define BM_58_44 0x07fff00000000000 -#define BM_44_58 BM_58_44 -#define BM_59_44 0x0ffff00000000000 -#define BM_44_59 BM_59_44 -#define BM_60_44 0x1ffff00000000000 -#define BM_44_60 BM_60_44 -#define BM_61_44 0x3ffff00000000000 -#define BM_44_61 BM_61_44 -#define BM_62_44 0x7ffff00000000000 -#define BM_44_62 BM_62_44 -#define BM_63_44 0xfffff00000000000 -#define BM_44_63 BM_63_44 -#define BM_45_45 0x0000200000000000 -#define BM_46_45 0x0000600000000000 -#define BM_45_46 BM_46_45 -#define BM_47_45 0x0000e00000000000 -#define BM_45_47 BM_47_45 -#define BM_48_45 0x0001e00000000000 -#define BM_45_48 BM_48_45 -#define BM_49_45 0x0003e00000000000 -#define BM_45_49 BM_49_45 -#define BM_50_45 0x0007e00000000000 -#define BM_45_50 BM_50_45 -#define BM_51_45 0x000fe00000000000 -#define BM_45_51 BM_51_45 -#define BM_52_45 0x001fe00000000000 -#define BM_45_52 BM_52_45 -#define BM_53_45 0x003fe00000000000 -#define BM_45_53 BM_53_45 -#define BM_54_45 0x007fe00000000000 -#define BM_45_54 BM_54_45 -#define BM_55_45 0x00ffe00000000000 -#define BM_45_55 BM_55_45 -#define BM_56_45 0x01ffe00000000000 -#define BM_45_56 BM_56_45 -#define BM_57_45 0x03ffe00000000000 -#define BM_45_57 BM_57_45 -#define BM_58_45 0x07ffe00000000000 -#define BM_45_58 BM_58_45 -#define BM_59_45 0x0fffe00000000000 -#define BM_45_59 BM_59_45 -#define BM_60_45 0x1fffe00000000000 -#define BM_45_60 BM_60_45 -#define BM_61_45 0x3fffe00000000000 -#define BM_45_61 BM_61_45 -#define BM_62_45 0x7fffe00000000000 -#define BM_45_62 BM_62_45 -#define BM_63_45 0xffffe00000000000 -#define BM_45_63 BM_63_45 -#define BM_46_46 0x0000400000000000 -#define BM_47_46 0x0000c00000000000 -#define BM_46_47 BM_47_46 -#define BM_48_46 0x0001c00000000000 -#define BM_46_48 BM_48_46 -#define BM_49_46 0x0003c00000000000 -#define BM_46_49 BM_49_46 -#define BM_50_46 0x0007c00000000000 -#define BM_46_50 BM_50_46 -#define BM_51_46 0x000fc00000000000 -#define BM_46_51 BM_51_46 -#define BM_52_46 0x001fc00000000000 -#define BM_46_52 BM_52_46 -#define BM_53_46 0x003fc00000000000 -#define BM_46_53 BM_53_46 -#define BM_54_46 0x007fc00000000000 -#define BM_46_54 BM_54_46 -#define BM_55_46 0x00ffc00000000000 -#define BM_46_55 BM_55_46 -#define BM_56_46 0x01ffc00000000000 -#define BM_46_56 BM_56_46 -#define BM_57_46 0x03ffc00000000000 -#define BM_46_57 BM_57_46 -#define BM_58_46 0x07ffc00000000000 -#define BM_46_58 BM_58_46 -#define BM_59_46 0x0fffc00000000000 -#define BM_46_59 BM_59_46 -#define BM_60_46 0x1fffc00000000000 -#define BM_46_60 BM_60_46 -#define BM_61_46 0x3fffc00000000000 -#define BM_46_61 BM_61_46 -#define BM_62_46 0x7fffc00000000000 -#define BM_46_62 BM_62_46 -#define BM_63_46 0xffffc00000000000 -#define BM_46_63 BM_63_46 -#define BM_47_47 0x0000800000000000 -#define BM_48_47 0x0001800000000000 -#define BM_47_48 BM_48_47 -#define BM_49_47 0x0003800000000000 -#define BM_47_49 BM_49_47 -#define BM_50_47 0x0007800000000000 -#define BM_47_50 BM_50_47 -#define BM_51_47 0x000f800000000000 -#define BM_47_51 BM_51_47 -#define BM_52_47 0x001f800000000000 -#define BM_47_52 BM_52_47 -#define BM_53_47 0x003f800000000000 -#define BM_47_53 BM_53_47 -#define BM_54_47 0x007f800000000000 -#define BM_47_54 BM_54_47 -#define BM_55_47 0x00ff800000000000 -#define BM_47_55 BM_55_47 -#define BM_56_47 0x01ff800000000000 -#define BM_47_56 BM_56_47 -#define BM_57_47 0x03ff800000000000 -#define BM_47_57 BM_57_47 -#define BM_58_47 0x07ff800000000000 -#define BM_47_58 BM_58_47 -#define BM_59_47 0x0fff800000000000 -#define BM_47_59 BM_59_47 -#define BM_60_47 0x1fff800000000000 -#define BM_47_60 BM_60_47 -#define BM_61_47 0x3fff800000000000 -#define BM_47_61 BM_61_47 -#define BM_62_47 0x7fff800000000000 -#define BM_47_62 BM_62_47 -#define BM_63_47 0xffff800000000000 -#define BM_47_63 BM_63_47 -#define BM_48_48 0x0001000000000000 -#define BM_49_48 0x0003000000000000 -#define BM_48_49 BM_49_48 -#define BM_50_48 0x0007000000000000 -#define BM_48_50 BM_50_48 -#define BM_51_48 0x000f000000000000 -#define BM_48_51 BM_51_48 -#define BM_52_48 0x001f000000000000 -#define BM_48_52 BM_52_48 -#define BM_53_48 0x003f000000000000 -#define BM_48_53 BM_53_48 -#define BM_54_48 0x007f000000000000 -#define BM_48_54 BM_54_48 -#define BM_55_48 0x00ff000000000000 -#define BM_48_55 BM_55_48 -#define BM_56_48 0x01ff000000000000 -#define BM_48_56 BM_56_48 -#define BM_57_48 0x03ff000000000000 -#define BM_48_57 BM_57_48 -#define BM_58_48 0x07ff000000000000 -#define BM_48_58 BM_58_48 -#define BM_59_48 0x0fff000000000000 -#define BM_48_59 BM_59_48 -#define BM_60_48 0x1fff000000000000 -#define BM_48_60 BM_60_48 -#define BM_61_48 0x3fff000000000000 -#define BM_48_61 BM_61_48 -#define BM_62_48 0x7fff000000000000 -#define BM_48_62 BM_62_48 -#define BM_63_48 0xffff000000000000 -#define BM_48_63 BM_63_48 -#define BM_49_49 0x0002000000000000 -#define BM_50_49 0x0006000000000000 -#define BM_49_50 BM_50_49 -#define BM_51_49 0x000e000000000000 -#define BM_49_51 BM_51_49 -#define BM_52_49 0x001e000000000000 -#define BM_49_52 BM_52_49 -#define BM_53_49 0x003e000000000000 -#define BM_49_53 BM_53_49 -#define BM_54_49 0x007e000000000000 -#define BM_49_54 BM_54_49 -#define BM_55_49 0x00fe000000000000 -#define BM_49_55 BM_55_49 -#define BM_56_49 0x01fe000000000000 -#define BM_49_56 BM_56_49 -#define BM_57_49 0x03fe000000000000 -#define BM_49_57 BM_57_49 -#define BM_58_49 0x07fe000000000000 -#define BM_49_58 BM_58_49 -#define BM_59_49 0x0ffe000000000000 -#define BM_49_59 BM_59_49 -#define BM_60_49 0x1ffe000000000000 -#define BM_49_60 BM_60_49 -#define BM_61_49 0x3ffe000000000000 -#define BM_49_61 BM_61_49 -#define BM_62_49 0x7ffe000000000000 -#define BM_49_62 BM_62_49 -#define BM_63_49 0xfffe000000000000 -#define BM_49_63 BM_63_49 -#define BM_50_50 0x0004000000000000 -#define BM_51_50 0x000c000000000000 -#define BM_50_51 BM_51_50 -#define BM_52_50 0x001c000000000000 -#define BM_50_52 BM_52_50 -#define BM_53_50 0x003c000000000000 -#define BM_50_53 BM_53_50 -#define BM_54_50 0x007c000000000000 -#define BM_50_54 BM_54_50 -#define BM_55_50 0x00fc000000000000 -#define BM_50_55 BM_55_50 -#define BM_56_50 0x01fc000000000000 -#define BM_50_56 BM_56_50 -#define BM_57_50 0x03fc000000000000 -#define BM_50_57 BM_57_50 -#define BM_58_50 0x07fc000000000000 -#define BM_50_58 BM_58_50 -#define BM_59_50 0x0ffc000000000000 -#define BM_50_59 BM_59_50 -#define BM_60_50 0x1ffc000000000000 -#define BM_50_60 BM_60_50 -#define BM_61_50 0x3ffc000000000000 -#define BM_50_61 BM_61_50 -#define BM_62_50 0x7ffc000000000000 -#define BM_50_62 BM_62_50 -#define BM_63_50 0xfffc000000000000 -#define BM_50_63 BM_63_50 -#define BM_51_51 0x0008000000000000 -#define BM_52_51 0x0018000000000000 -#define BM_51_52 BM_52_51 -#define BM_53_51 0x0038000000000000 -#define BM_51_53 BM_53_51 -#define BM_54_51 0x0078000000000000 -#define BM_51_54 BM_54_51 -#define BM_55_51 0x00f8000000000000 -#define BM_51_55 BM_55_51 -#define BM_56_51 0x01f8000000000000 -#define BM_51_56 BM_56_51 -#define BM_57_51 0x03f8000000000000 -#define BM_51_57 BM_57_51 -#define BM_58_51 0x07f8000000000000 -#define BM_51_58 BM_58_51 -#define BM_59_51 0x0ff8000000000000 -#define BM_51_59 BM_59_51 -#define BM_60_51 0x1ff8000000000000 -#define BM_51_60 BM_60_51 -#define BM_61_51 0x3ff8000000000000 -#define BM_51_61 BM_61_51 -#define BM_62_51 0x7ff8000000000000 -#define BM_51_62 BM_62_51 -#define BM_63_51 0xfff8000000000000 -#define BM_51_63 BM_63_51 -#define BM_52_52 0x0010000000000000 -#define BM_53_52 0x0030000000000000 -#define BM_52_53 BM_53_52 -#define BM_54_52 0x0070000000000000 -#define BM_52_54 BM_54_52 -#define BM_55_52 0x00f0000000000000 -#define BM_52_55 BM_55_52 -#define BM_56_52 0x01f0000000000000 -#define BM_52_56 BM_56_52 -#define BM_57_52 0x03f0000000000000 -#define BM_52_57 BM_57_52 -#define BM_58_52 0x07f0000000000000 -#define BM_52_58 BM_58_52 -#define BM_59_52 0x0ff0000000000000 -#define BM_52_59 BM_59_52 -#define BM_60_52 0x1ff0000000000000 -#define BM_52_60 BM_60_52 -#define BM_61_52 0x3ff0000000000000 -#define BM_52_61 BM_61_52 -#define BM_62_52 0x7ff0000000000000 -#define BM_52_62 BM_62_52 -#define BM_63_52 0xfff0000000000000 -#define BM_52_63 BM_63_52 -#define BM_53_53 0x0020000000000000 -#define BM_54_53 0x0060000000000000 -#define BM_53_54 BM_54_53 -#define BM_55_53 0x00e0000000000000 -#define BM_53_55 BM_55_53 -#define BM_56_53 0x01e0000000000000 -#define BM_53_56 BM_56_53 -#define BM_57_53 0x03e0000000000000 -#define BM_53_57 BM_57_53 -#define BM_58_53 0x07e0000000000000 -#define BM_53_58 BM_58_53 -#define BM_59_53 0x0fe0000000000000 -#define BM_53_59 BM_59_53 -#define BM_60_53 0x1fe0000000000000 -#define BM_53_60 BM_60_53 -#define BM_61_53 0x3fe0000000000000 -#define BM_53_61 BM_61_53 -#define BM_62_53 0x7fe0000000000000 -#define BM_53_62 BM_62_53 -#define BM_63_53 0xffe0000000000000 -#define BM_53_63 BM_63_53 -#define BM_54_54 0x0040000000000000 -#define BM_55_54 0x00c0000000000000 -#define BM_54_55 BM_55_54 -#define BM_56_54 0x01c0000000000000 -#define BM_54_56 BM_56_54 -#define BM_57_54 0x03c0000000000000 -#define BM_54_57 BM_57_54 -#define BM_58_54 0x07c0000000000000 -#define BM_54_58 BM_58_54 -#define BM_59_54 0x0fc0000000000000 -#define BM_54_59 BM_59_54 -#define BM_60_54 0x1fc0000000000000 -#define BM_54_60 BM_60_54 -#define BM_61_54 0x3fc0000000000000 -#define BM_54_61 BM_61_54 -#define BM_62_54 0x7fc0000000000000 -#define BM_54_62 BM_62_54 -#define BM_63_54 0xffc0000000000000 -#define BM_54_63 BM_63_54 -#define BM_55_55 0x0080000000000000 -#define BM_56_55 0x0180000000000000 -#define BM_55_56 BM_56_55 -#define BM_57_55 0x0380000000000000 -#define BM_55_57 BM_57_55 -#define BM_58_55 0x0780000000000000 -#define BM_55_58 BM_58_55 -#define BM_59_55 0x0f80000000000000 -#define BM_55_59 BM_59_55 -#define BM_60_55 0x1f80000000000000 -#define BM_55_60 BM_60_55 -#define BM_61_55 0x3f80000000000000 -#define BM_55_61 BM_61_55 -#define BM_62_55 0x7f80000000000000 -#define BM_55_62 BM_62_55 -#define BM_63_55 0xff80000000000000 -#define BM_55_63 BM_63_55 -#define BM_56_56 0x0100000000000000 -#define BM_57_56 0x0300000000000000 -#define BM_56_57 BM_57_56 -#define BM_58_56 0x0700000000000000 -#define BM_56_58 BM_58_56 -#define BM_59_56 0x0f00000000000000 -#define BM_56_59 BM_59_56 -#define BM_60_56 0x1f00000000000000 -#define BM_56_60 BM_60_56 -#define BM_61_56 0x3f00000000000000 -#define BM_56_61 BM_61_56 -#define BM_62_56 0x7f00000000000000 -#define BM_56_62 BM_62_56 -#define BM_63_56 0xff00000000000000 -#define BM_56_63 BM_63_56 -#define BM_57_57 0x0200000000000000 -#define BM_58_57 0x0600000000000000 -#define BM_57_58 BM_58_57 -#define BM_59_57 0x0e00000000000000 -#define BM_57_59 BM_59_57 -#define BM_60_57 0x1e00000000000000 -#define BM_57_60 BM_60_57 -#define BM_61_57 0x3e00000000000000 -#define BM_57_61 BM_61_57 -#define BM_62_57 0x7e00000000000000 -#define BM_57_62 BM_62_57 -#define BM_63_57 0xfe00000000000000 -#define BM_57_63 BM_63_57 -#define BM_58_58 0x0400000000000000 -#define BM_59_58 0x0c00000000000000 -#define BM_58_59 BM_59_58 -#define BM_60_58 0x1c00000000000000 -#define BM_58_60 BM_60_58 -#define BM_61_58 0x3c00000000000000 -#define BM_58_61 BM_61_58 -#define BM_62_58 0x7c00000000000000 -#define BM_58_62 BM_62_58 -#define BM_63_58 0xfc00000000000000 -#define BM_58_63 BM_63_58 -#define BM_59_59 0x0800000000000000 -#define BM_60_59 0x1800000000000000 -#define BM_59_60 BM_60_59 -#define BM_61_59 0x3800000000000000 -#define BM_59_61 BM_61_59 -#define BM_62_59 0x7800000000000000 -#define BM_59_62 BM_62_59 -#define BM_63_59 0xf800000000000000 -#define BM_59_63 BM_63_59 -#define BM_60_60 0x1000000000000000 -#define BM_61_60 0x3000000000000000 -#define BM_60_61 BM_61_60 -#define BM_62_60 0x7000000000000000 -#define BM_60_62 BM_62_60 -#define BM_63_60 0xf000000000000000 -#define BM_60_63 BM_63_60 -#define BM_61_61 0x2000000000000000 -#define BM_62_61 0x6000000000000000 -#define BM_61_62 BM_62_61 -#define BM_63_61 0xe000000000000000 -#define BM_61_63 BM_63_61 -#define BM_62_62 0x4000000000000000 -#define BM_63_62 0xc000000000000000 -#define BM_62_63 BM_63_62 -#define BM_63_63 0x8000000000000000 - -#endif - -#endif /* __ASM_TX4927_TX4927_MIPS_H */ _