GIT c4d5e375470862fd741f93bf0686d7ac2f7fdce4 git+ssh://master.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git commit c4d5e375470862fd741f93bf0686d7ac2f7fdce4 Author: David Gibson Date: Thu Sep 20 11:22:25 2007 +1000 [POWERPC] Cleanups for physmap_of.c (v2) This patch includes a whole batch of smallish cleanups for drivers/mtd/physmap_of.c. - A bunch of uneeded #includes are removed - We switch to the modern linux/of.h etc. in place of asm/prom.h - Use some helper macros to avoid some ugly inline #ifdefs - A few lines of unreachable code are removed - A number of indentation / line-wrapping fixes - More consistent use of kernel idioms such as if (!p) instead of if (p == NULL) - Clarify some printk()s and other informative strings. - parse_obsolete_partitions() now returns 0 if no partition information is found, instead of returning -ENOENT which the caller had to handle specially. - (the big one) Despite the name, this driver really has nothing to do with drivers/mtd/physmap.c. The fact that the flash chips must be physically direct mapped is a constrant, but doesn't really say anything about the actual purpose of this driver, which is to instantiate MTD devices based on information from the device tree. Therefore the physmap name is replaced everywhere within the file with "of_flash". The file itself and the Kconfig option is not renamed for now (so that the diff is actually a diff). That can come later. Signed-off-by: David Gibson Signed-off-by: Josh Boyer commit bd0076cc330f303905018a17d9dcfbabde497572 Author: Valentine Barshak Date: Wed Sep 19 03:29:13 2007 +1000 [POWERPC] 4xx: Fix Sequoia MAL0 and EMAC dts entries. According to PowerPC 440EPx documentation, MAL0 is comprised of four channels (two transmit and two receive). Each channel is dedicated to one of two EMAC cores. This patch fixes Sequoia DTS MAL0 entry and EMAC entries, assigning correct channel numbers to EMACs. Signed-off-by: Valentine Barshak Signed-off-by: Josh Boyer commit e52f5677bf6954dbd128a2d659d77a85ced55d30 Author: Valentine Barshak Date: Wed Sep 19 03:27:52 2007 +1000 [POWERPC] 4xx: Fix Bamboo MAL0 dts entry. According to PowerPC 440EP documentation, MAL0 consists of 6 channels (4 transmit channels and 2 receive channels) This patch fixes Bamboo DTS MAL0 "num-rx-chans" entry. Signed-off-by: Valentine Barshak Signed-off-by: Josh Boyer commit 472b5b43bec45e7e79f86094ca9091bd9eb474ed Author: Valentine Barshak Date: Thu Sep 6 03:30:16 2007 +1000 [POWERPC] Add 64-bit resources support to pci_iomap The patch adds support for the 64-bit resources to the PCI iomap code. Signed-off-by: Valentine Barshak Acked-by: David Gibson Signed-off-by: Josh Boyer commit 9a474fff4f6a5fc14ac493c48f56a14e65912cc7 Author: Josh Boyer Date: Wed Sep 19 21:19:07 2007 -0500 [POWERPC] Update PowerPC 4xx entry in MAINTAINERS Add myself as PowerPC 4xx maintainer and list the git tree Signed-off-by: Josh Boyer commit 70dea47da12932cc512e09124a836ddd3499ab39 Author: Hollis Blanchard Date: Mon Sep 17 05:56:47 2007 -0500 [POWERPC] 4xx: Implement udbg_getc() for 440 Implement udbg_getc() for 440, which fixes xmon input. Signed-off-by: Hollis Blanchard Acked-by: David Gibson Signed-off-by: Josh Boyer commit 504ca43e5e681b8ed3837f11ea458eb145a82e4e Author: Josh Boyer Date: Sat Sep 15 04:54:14 2007 +1000 [POWERPC] 4xx: Convert Seqouia flash mappings to new binding A new binding for flash devices was recently introduced. This updates the Sequoia DTS to use the new binding and enabled MTD in the defconfig. Signed-off-by: Josh Boyer Acked-by: David Gibson Acked-by: Stefan Roese commit bf07f32d4332be50f5d4ef06307fb328257fcd1b Author: Josh Boyer Date: Sat Sep 15 04:54:13 2007 +1000 [POWERPC] 4xx: Convert Walnut flash mappings to new binding A new binding for flash devices was recently introduced. This updates the Walnut DTS to use the new binding. Signed-off-by: Josh Boyer Acked-by: David Gibson commit 8d9ae994d8fce807fc90fb8e3b6ac8df1cc7dce6 Author: Josh Boyer Date: Sat Sep 15 04:54:12 2007 +1000 [POWERPC] Make partitions optional in physmap_of The latest physmap_of driver has a small error where it will fail the probe with: physmap-flash: probe of fff00000.small-flas failed with error -2 if there are no partition subnodes in the device tree and the old style binding is not used. Since partition definitions are optional, the probe should still succeed. Signed-off-by: Josh Boyer Acked-by: David Gibson commit 658e81701970a82d33f46241f20be416ebd5e930 Author: Josh Boyer Date: Sat Sep 15 04:54:11 2007 +1000 [POWERPC] cuimage for Bamboo board Add a cuboot wrapper for the Bamboo board. Additionally, we enable MAC address fixups for both cuboot and treeboot. This also removes some obsoleted linker declarations that have been moved into ops.h Signed-off-by: Josh Boyer Acked-by: David Gibson commit 9e4859ef5462193643fd2b3c8ffb298e5a4a4319 Author: Stephen Rothwell Date: Tue Sep 18 17:25:12 2007 +1000 [POWERPC] FWNMI is only used on pSeries This saves 4k on non pSeries builds (except for iSeries where it saves almost 4k). Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit ee7a76da1ef5e3e5e0e54e84319e435ea25c267c Author: Stephen Rothwell Date: Tue Sep 18 17:22:59 2007 +1000 [POWERPC] Size swapper_pg_dir correctly David Gibson pointed out that swapper_pg_dir actually need to be PGD_TABLE_SIZE bytes long not PAGE_SIZE. This actually saves 64k in the bss for a kernel ppc64_defconfig built with CONFIG_PPC_64K_PAGES. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 19a8d97d89442e2bda6245b8a3de2c1fec69a7ad Author: Stephen Rothwell Date: Mon Sep 17 14:41:38 2007 +1000 [POWERPC] Remove cmd_line from head*.S It is just a C char array, so declare it thusly. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 7b2c3c5b1d6dd77d7bb5a7d57ab7280e051c59bc Author: Stephen Rothwell Date: Mon Sep 17 14:08:06 2007 +1000 [POWERPC] Fix section mismatch in PCI code Create a helper function (alloc_maybe_bootmem) that is marked __init_refok to limit the chances of mistakenly referring to other __init routines. WARNING: vmlinux.o(.text+0x2a9c4): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.update_dn_pci_info' and '.pci_dn_reconfig_notifier') WARNING: vmlinux.o(.text+0x36430): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.mpic_msi_init_allocator' and '.find_ht_magic_addr') WARNING: vmlinux.o(.text+0x5e804): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') WARNING: vmlinux.o(.text+0x5e8e8): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') WARNING: vmlinux.o(.text+0x5e968): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit ee983079ce04641523b23b8ed02cc3503632351e Author: Domen Puncer Date: Wed Jul 18 06:32:31 2007 +1000 [POWERPC] MPC5200 low power mode Low-power mode implementation for Lite5200b. Some I/O registers are also saved here. A recent U-Boot that supports this (lite5200b_PM_config) is needed. Signed-off-by: Domen Puncer Signed-off-by: Sylvain Munaut Signed-off-by: Paul Mackerras commit 104f0cc2dcf7ce0ca7da041177233747d6aa0136 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Add DEFINE_SPUFS_ATTRIBUTE() This patch adds DEFINE_SPUFS_ATTRIBUTE(), a wrapper around DEFINE_SIMPLE_ATTRIBUTE which does the specified locking for the get routine for us. Unfortunately we need two get routines (a locked and unlocked version) to support the coredump code. This hides one of those (the locked version) inside the macro foo. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 9e25ae6d91e7fb058c8957c2a64dc3ca0377dd5b Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Respect RLIMIT_CORE in spu coredump code Currently the spu coredump code doesn't respect the ulimit, it should. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 7af1443a9d319132087e1e9a3984b94c6998835c Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Handle errors in SPU coredump code, and support coredump to a pipe Rework spufs_coredump_extra_notes_write() to check for and return errors. If we're coredumping to a pipe we can't trust file->f_pos, we need to maintain the foffset value passed to us. The cleanest way to do this is to have the low level write routine increment foffset when we've successfully written. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit e55014923e65e4ee8e477a1212381cca0125f3aa Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Cleanup ELF coredump extra notes logic To start with, arch_notes_size() etc. is a little too ambiguous a name for my liking, so change the function names to be more explicit. Calling through macros is ugly, especially with hidden parameters, so don't do that, call the routines directly. Use ARCH_HAVE_EXTRA_ELF_NOTES as the only flag, and based on it decide whether we want the extern declarations or the empty versions. Since we have empty routines, actually use them in the coredump code to save a few #ifdefs. We want to change the handling of foffset so that the write routine updates foffset as it goes, instead of using file->f_pos (so that writing to a pipe works). So pass foffset to the write routine, and for now just set it to file->f_pos at the end of writing. It should also be possible for the write routine to fail, so change it to return int and treat a non-zero return as failure. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 48cad41f7ee7b8a9a8317a4abbdaf09bc68b4773 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Combine spufs_coredump_calls with spufs_calls Because spufs might be built as a module, we can't have other parts of the kernel calling directly into it, we need stub routines that check first if the module is loaded. Currently we have two structures which hold callbacks for these stubs, the syscalls are in spufs_calls and the coredump calls are in spufs_coredump_calls. In both cases the logic for registering/unregistering is essentially the same, so we can simplify things by combining the two. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Acked-by: Arnd Bergmann Signed-off-by: Paul Mackerras commit 78810ff6723f20015373b1ba8dd981f24c62f680 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Add contents of npc file to SPU coredumps Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Acked-by: Arnd Bergmann Signed-off-by: Paul Mackerras commit 74de08bc10dd4d67870cf5b6c5aaf6875cd869c5 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Internal __spufs_get_foo() routines should take a spu_context * The SPUFS attribute get routines take a void * because the generic attribute code doesn't know what sort of data it's passing around. However our internal __spufs_get_foo() routines can take a spu_context * directly, which saves plonking it in and out of a void * again. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Acked-by: Arnd Bergmann Signed-off-by: Paul Mackerras commit 936d5bf1d7dc69c56bf79ad68819e597307a1884 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Get rid of spufs_coredump_num_notes, it's not needed if we NULL terminate The spufs_coredump_read array is NULL terminated, and we also store the size. We only need one or the other, and the other arrays in file.c are NULL terminated, so do that. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit c1a72173ab156306666cb531f891f32e4e21d592 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Don't return -ENOSYS as extra notes size if spufs is not loaded Because the SPU coredump code might be built as part of a module (spufs), we have a stub which is called by the coredump code, this routine then calls into spufs if it's loaded. Unfortunately the stub returns -ENOSYS if spufs is not loaded, which is interpreted by the coredump code as an extra note size of -38 bytes. This leads to a corrupt core dump. If spufs is not loaded there will be no SPU ELF notes to write, and so the extra notes size will be == 0. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Acked-by: Arnd Bergmann Signed-off-by: Paul Mackerras commit 59000b53c7ea07531018b6cf1f5fcd21e881867a Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Correctly calculate the size of the local-store to dump The routine to dump the local store, __spufs_mem_read(), does not take the spu_lslr_RW value into account - so we shouldn't check it when we're calculating the size either. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Acked-by: Arnd Bergmann Signed-off-by: Paul Mackerras commit d464fb441071a3d65bde2264c5f97f9ca47ce5c3 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Write some SPU coredump values as ASCII Unfortunately GDB expects some of the SPU coredump values to be identical in format to what is found in spufs. This means we need to dump some of the values as ASCII strings, not the actual values. Because we don't know what the values will be, we always print the values with the format "0x%.16lx", that way we know the result will be 19 bytes. do_coredump_read() doesn't take a __user buffer, so remove the annotation, and because we know that it's safe to just snprintf() directly to it. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 4fca9c425009c01d41db6c6ebf0189843ee90f0b Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Use computed sizes/#defines rather than literals in SPU coredump code The spufs_coredump_reader array contains the size of the data that will be returned by the read routine. Currently these are specified as literals, and though some are obvious, sizeof(u32) == 4, others are not, 69 * 8 == ??? Instead, use sizeof() whatever type is returned by each routine, or in the case of spufs_mem_read() the #define LS_SIZE. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 9a5080f11d67972d7972d824f1b1827fafbce126 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Call spu_acquire_saved() before calculating the SPU note sizes It makes sense to stop the SPU processes as soon as possible. Also if we dont acquire_saved() I think there's a possibility that the value in csa.priv2.spu_lslr_RW won't be accurate. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit f9b7bbe7a803c6f10e7b3a354c5d97f632060320 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Remove ctx_info and ctx_info_list Remove the ctx_info struct entirely, and also the ctx_info_list. This fixes a race where two processes can clobber each other's ctx_info structs. Instead of using the list, we just repeat the search through the file descriptor table. Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit a595ed662c96dcd920415bea3135ff1af60e9a00 Author: Michael Ellerman Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Extract the file descriptor search logic in SPU coredump code Extract the logic for searching through the file descriptors for spu contexts into a separate routine, coredump_next_context(), so we can use it elsewhere in future. In the process we flatten the for loop, and move the NOSCHED test into coredump_next_context(). Signed-off-by: Michael Ellerman Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit c70d4ca52b1390dd2603535600c948cbdb0b9ec9 Author: Jeremy Kerr Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] cell: Remove DEBUG for SPU callbacks We don't want SPE programs to be able to flood the kernel log by invoking the SPE callback handler, so don't enable DEBUG for spu_callbacks.c by default. Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 05a059f3296c07a7455290dd8188b23ecb380fc7 Author: Jeremy Kerr Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Fix restore_decr_wrapped() to match CBE Handbook Based on an original patch from Masato Noguchi . We're currently not restoring the SPE decrementer as specified by the CBE handbook. This change fixes our implementation to match, and makes the function read more like the docs. Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 4ec3c3d08d4de744b7a1d885529d1e040ec747a4 Author: Jeremy Kerr Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Remove asmlinkage from spufs_calls spu_create and spu_run are wrapped by the cell syscall layer, so we don't need the asmlinkage. Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 98f06978ffebbec16abdea58489f217229580859 Author: Jeremy Kerr Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] cell: Unify spufs syscall path At present, a built-in spufs will not use the spufs_calls callbacks, but directly call sys_spu_create. This saves us an indirect branch, but means we have duplicated functions - one for CONFIG_SPU_FS=y and one for =m. This change unifies the spufs syscall path, and provides access to the spufs_calls structure through a get/put pair. At present, the only user of the spufs_calls structure is spu_syscalls.c, but this will facilitate adding the coredump calls later. Everyone likes numbers, right? Here's a before/after comparison with CONFIG_SPU_FS=y, doing spu_create(); close(); 64k times. Before: [jk@cell ~]$ time ./spu_create performing 65536 spu_create calls real 0m24.075s user 0m0.146s sys 0m23.925s After: [jk@cell ~]$ time ./spu_create performing 65536 spu_create calls real 0m24.777s user 0m0.141s sys 0m24.631s So, we're adding around 11us per syscall, at the benefit of having only one syscall path. Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 36ddbb1380f282b4280c57efdb646dd8647a789f Author: Andre Detsch Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Fix race condition on gang->aff_ref_spu Affinity reference point location (gang->aff_ref_spu) is reset when the whole gang is descheduled. However, the last member of a gang can be descheduled while we are trying to schedule another member of the gang. This was leading to a race condition, and the code was using gang->aff_ref_spu in an unsafe manner. By holding the gang->aff_mutex a little bit longer, and increment gang->aff_sched_count (which controls when gang->aff_ref_spu should be reset) a little bit earlier, the problem is fixed. Signed-off-by: Andre Detsch Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 8b0d3121a0b2cf91768ecef635e241b6abc3f1da Author: Sebastian Siewior Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Make isolated loader properly aligned According to the comment in spufs_init_isolated_loader(), the isolated loader should be aligned on a 16 byte boundary. ARCH_{KMALLOC,SLAB}_MINALIGN is not defined so only 8 byte alignment is guaranteed. This enforces alignment via __get_free_pages. Signed-off-by: Sebastian Siewior Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 6232a74f25f45a98d8cf64c5d4208f4795eb693d Author: Jeremy Kerr Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Remove spu_harvest Based on an initial patch from Sebastian Siewior spu_harvest isn't used, remove it. Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 1e8b0f6d1b4dd5fafe732a24dfcb9ac9fd27cf08 Author: Jeremy Kerr Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Remove asmlinkage from do_spu_create do_spu_create doesn't need the asmlinkage qualifier; remove it. Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit 1238819a41b6e38e1560afe8f33bbc815671b4f7 Author: Sebastian Siewior Date: Wed Sep 19 14:38:12 2007 +1000 [POWERPC] spufs: Make file-internal functions & variables static There are a few symbols used only in one file within spufs; this change makes them static where suitable. Signed-off-by: Sebastian Siewior Signed-off-by: Jeremy Kerr Signed-off-by: Paul Mackerras commit aa0154290fc05948560ac43afcccf8259e10bcd0 Author: Olaf Hering Date: Sun Aug 26 19:10:59 2007 +1000 [POWERPC] Fix pmac_zilog debug arg drivers/serial/pmac_zilog.c:1590: warning: format '%d' expects type 'int', but argument 3 has type 'pm_message_t' Signed-off-by: Olaf Hering Signed-off-by: Paul Mackerras commit 00efee7d5d0d7888aafbf0d2de76943ee8aca47a Author: Michael Neuling Date: Fri Aug 24 16:58:37 2007 +1000 [POWERPC] Remove barriers from the SLB shadow buffer update After talking to an IBM POWER hypervisor (PHYP) design and development guy, there seems to be no need for memory barriers when updating the SLB shadow buffer provided we only update it from the current CPU, which we do. Also, these guys see no need in the future for these barriers. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras commit 61a564fd2e7ab13ab11a6ce8305433baacf344ef Author: Jesper Juhl Date: Fri Aug 24 09:45:08 2007 +1000 [POWERPC] Don't cast kmalloc return value in ibmebus.c kmalloc() returns a void pointer so there is absolutely no need to cast it in ibmebus_chomp(). Signed-off-by: Jesper Juhl Signed-off-by: Paul Mackerras commit e6b6e3ffb9ee8926f9f2f7dc9147df73e27d5828 Author: Adrian Bunk Date: Mon Aug 27 23:29:53 2007 +0200 [POWERPC] Remove APUS support from arch/ppc Current status of APUS: - arch/powerpc/: removed in 2.6.23 - arch/ppc/: marked BROKEN since 2 years This therefore removes the remaining parts of APUS support from arch/ppc, include/asm-ppc, arch/powerpc and include/asm-powerpc. Signed-off-by: Adrian Bunk Signed-off-by: Paul Mackerras commit 8237bf080e9ef6adc3f2adce26060722685bbb15 Author: Anton Vorontsov Date: Thu Aug 23 15:36:00 2007 +0400 [POWERPC] MPC832x_RDB: Update dts to use SPI1 in QE, register mmc_spi stub Enabled using SPI controller on the MPC832x RDB board. We currently use a modalias of "spidev" as a place holder (replace with "mmc_spie") until the mmc_spi driver support is merged in. This gets us the ability to test SPI until then. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala commit 26f6cb999366a71b8e318bceaf8fafc1ffecae40 Author: Anton Vorontsov Date: Thu Aug 23 15:35:56 2007 +0400 [POWERPC] fsl_soc: add support for fsl_spi Add helper function to setup SPI bus/device information Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala commit af6a9aabc106b70ab03d6665c713bca3dd3cb195 Author: John Rigby Date: Wed May 23 11:30:55 2007 -0600 [POWERPC] 52xx: Fix mpc52xx_uart_of_assign to use correct index Use idx as index into mpc52xx_uart_nodes instead of i Signed-off-by: John Rigby Signed-off-by: Kumar Gala commit 82925e76db19112cad62066828c1db0bbb3f77e3 Author: Timur Tabi Date: Wed Jul 25 12:30:33 2007 -0500 [POWERPC] 86xx: Fix definition of global-utilites structure The current definition of struct ccsr_guts in immap_86xx.h was for 85xx. This patch fixes that and replaces the vague integer types with sized types of the correct endianness. The unused struct ccsr_pci is also deleted. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala commit dc967d7f5e5d2c9d01c8ea172a1e231908dba9de Author: Timur Tabi Date: Wed Aug 22 20:07:28 2007 -0500 [POWERPC] add clrsetbits macros This patch adds the clrsetbits_xxx() macros, which are used to set and clear multiple bits in a single read-modify-write operation. Specify the bits to clear in the 'clear' parameter and the bits to set in the 'set' parameter. These macros can also be used to set a multiple-bit bit pattern using a mask, by specifying the mask in the 'clear' parameter and the new bit pattern in the 'set' parameter. There are big-endian and little-endian versions for 8, 16, 32, and 64 bits. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala commit 364f8ffc182ac5431b156ca1915dd81ddd4a592b Author: Anton Vorontsov Date: Thu Aug 23 15:35:53 2007 +0400 [POWERPC] QE: extern par_io_config_pin and par_io_data_set funcs This is needed to configure and control QE pario pins from the kernel. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala commit 5a24e1a1773f284d19859d27f2ba7e50a533aaaf Author: Scott Wood Date: Tue Aug 28 15:16:49 2007 -0500 [PPC] Add clrbits8 and setbits8. These I/O accessors will be used in code under drivers/, which is expected to still work in arch/ppc. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala commit 748a768384e05c021ea6be221b80c62a83d7b520 Author: Kumar Gala Date: Thu Sep 13 15:42:35 2007 -0500 [POWERPC] Fix modpost warnings from head*.S on ppc32 We get warnings like the following from the various ppc32 head*.S files: WARNING: vmlinux.o(.text+0x358): Section mismatch: reference to .init.text:early_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x380): Section mismatch: reference to .init.text:machine_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x384): Section mismatch: reference to .init.text:MMU_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x3aa): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x3ae): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base') Added a .text.head section simliar to what other architectures do since modpost already excludes this from its warnings. Signed-off-by: Kumar Gala commit 5e14d21e3f28a4181dacff0336040e30942f4921 Author: Kumar Gala Date: Thu Sep 13 01:44:20 2007 -0500 [POWERPC] Add cpu feature for SPE handling Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE. Signed-off-by: Kumar Gala commit d8f1324a5063c833862328ceafabc53ac3cc4f71 Author: Kumar Gala Date: Wed Sep 12 22:14:10 2007 -0500 [POWERPC] 83xx: Removed PCI exclude of PHB Now that the generic code doesn't assign resources for Freescale PHBs we dont have to explicitly exclude it. Signed-off-by: Kumar Gala commit 1b3c5cdab49a605f0e048e1ccbf4cc61a2626485 Author: Kumar Gala Date: Wed Sep 12 18:23:46 2007 -0500 [POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala commit f0c8ac8083cbd9347b398bfddcca20f1e2786016 Author: Kumar Gala Date: Wed Sep 12 11:52:31 2007 -0500 [POWERPC] DTS cleanup Removed the following cruft from .dts files: * 32-bit in cpu node -- doesn't exist in any spec and not used by kernel * removed built-in (chrp legacy) * Removed #interrupt-cells in places they don't need to be set * Fixed ranges on lite5200* * Removed clock-frequency from i8259 pic node, not sure where this came from * Removed big-endian from i8259 pic nodes, this was just bogus Signed-off-by: Kumar Gala commit 5d54ddcbcf931bf07cd1ce262bda4674ebd1427f Author: Kumar Gala Date: Tue Sep 11 01:25:43 2007 -0500 [POWERPC] 85xx: Add basic Uniprocessor MPC8572 DS port Added basic board port for MPC8572 DS reference platform that is similiar to the MPC8544/33 DS reference platform in uniprocessor mode. Signed-off-by: Kumar Gala commit 26caeb2ee1924d564e8d8190aa783a569532f81a Author: Kumar Gala Date: Fri Aug 24 16:42:53 2007 -0500 [POWERPC] Handle alignment faults on SPE load/store instructions This adds code to handle alignment traps generated by the following SPE (signal processing engine) load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): evldd[x] Vector Load Double Word into Double Word [Indexed] evldw[x] Vector Load Double into Two Words [Indexed] evldh[x] Vector Load Double into Four Half Words [Indexed] evlhhesplat[x] Vector Load Half Word into Half Words Even and Splat [Indexed] evlhhousplat[x] Vector Load Half Word into Half Word Odd Unsigned and Splat [Indexed] evlhhossplat[x] Vector Load Half Word into Half Word Odd Signed and Splat [Indexed] evlwhe[x] Vector Load Word into Two Half Words Even [Indexed] evlwhou[x] Vector Load Word into Two Half Words Odd Unsigned (zero-extended) [Indexed] evlwhos[x] Vector Load Word into Two Half Words Odd Signed (with sign extension) [Indexed] evlwwsplat[x] Vector Load Word into Word and Splat [Indexed] evlwhsplat[x] Vector Load Word into Two Half Words and Splat [Indexed] evstdd[x] Vector Store Double of Double [Indexed] evstdw[x] Vector Store Double of Two Words [Indexed] evstdh[x] Vector Store Double of Four Half Words [Indexed] evstwhe[x] Vector Store Word of Two Half Words from Even [Indexed] evstwho[x] Vector Store Word of Two Half Words from Odd [Indexed] evstwwe[x] Vector Store Word of Word from Even [Indexed] evstwwo[x] Vector Store Word of Word from Odd [Indexed] Signed-off-by: Kumar Gala commit f9234736112bf193e5ab451abbfbdf279cc53137 Author: Scott Wood Date: Mon Aug 20 11:38:12 2007 -0500 [POWERPC] fsl_soc.c cleanup 1. Update the way get_brgfreq() finds things in the device tree. It now uses names that are less namespace polluting. The old names are supported until all boards are converted. 2. "size" is changed from unsigned int to int, to match what of_get_property() expects. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala commit 683d00b03eb09a140e25d7f1457d347277bc2619 Author: Jon Loeliger Date: Fri Jul 27 13:24:45 2007 -0500 [POWERPC] 85xx: Remove unnecessary loops_per_jiffy initialization code. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala commit d347b3291b284e42c90b3f675a8332daf890b85a Author: Jon Loeliger Date: Fri Jul 27 13:24:36 2007 -0500 [POWERPC] 86xx: Remove unnecessary loops_per_jiffy initialization code. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala commit 7f2862c34521ee6006f9c2678d68a02dc57b5444 Author: Guennadi Liakhovetski Date: Sun Aug 26 00:08:11 2007 +0200 [POWERPC] linkstation updates 1. Fix RTC type - it is a rs5c372a, not rs5c372b 2. Configure both UART interrupts edge-triggered 3. Add a license header to ls_uart.c 4. Check for running on linkstation in a late_initcall() function. Needed for multiplatform builds, even though linkstation doesn't support them yet 5. Remove unneeded #include from linkstation.c Signed-off-by: Guennadi Liakhovetski Signed-off-by: Kumar Gala commit 7f50382dc87988d618f2d47364b22ad5973a968d Author: Kumar Gala Date: Fri Aug 17 09:26:40 2007 -0500 [POWERPC] 85xx: Clean up from 85xx_ds rename Renamed functions in 85xx_ds from 8544 to 85xx. Kept an unique machine def/probe for the MPC8544 DS board to handle some subtle differences between the future board based on the DS platform. Also fixed building w/o CONFIG_PCI and minor whitespace fixes. Signed-off-by: Kumar Gala commit 16d24060d1df9e38dd11ffb0a8afcb5e69a08e3c Author: Kumar Gala Date: Fri Aug 17 09:22:09 2007 -0500 [POWERPC] 85xx: Renamed mpc8544_ds.c to mpc85xx_ds.c Renamed the mpc8544_ds.c board code to mpc85xx_ds.c to make it more generic in prep for other boards based on the same platform. Signed-off-by: Kumar Gala commit 89a300e85b646dd08343264f025f4f412d552bfd Author: Kumar Gala Date: Wed Aug 22 21:49:01 2007 -0500 ucc_geth: kill unused include The ucc_geth_mii code is based on the gianfar_mii code that use to include ocp.h. ucc never need this and it causes issues when we want to kill arch/ppc includes from arch/powerpc. Signed-off-by: Kumar Gala commit 75cdff9242c4e048cb830d359920719d29b9ee7c Author: Geoff Levand Date: Wed Sep 12 18:43:17 2007 +1000 [POWERPC] PS3: Enhance storage probe debug output Add some more info to the PS3 storage probe debug output. Signed-off-by: Geoff Levand Signed-off-by: Paul Mackerras commit 06462d9263e168da3ecdff5a3d95ed470a91bbdc Author: Geert Uytterhoeven Date: Wed Sep 12 18:43:16 2007 +1000 [POWERPC] PS3: Add new LV1 error codes Add new error codes that may be returned by the LV1 hypervisor Signed-off-by: Geert Uytterhoeven Signed-off-by: Geoff Levand Signed-off-by: Paul Mackerras commit 85d02924a38789be35e83adba32eb6690535cfb0 Author: Jeremy Kerr Date: Wed Sep 12 18:43:15 2007 +1000 [POWERPC] PS3: Fix CONFIG_SMP=n, CONFIG_KEXEC=y build Currently, the ps3 kernel fails to build without smp but with kexec, as ps3_kexec_cpu_down needs ps3_smp_cleanup_cpu, which isn't defined on UP kernels. This change adds an empty ps3_smp_cleanup_cpu for UP kernels. Booted on ps3. Signed-off-by: Jeremy Kerr Signed-off-by: Geoff Levand Signed-off-by: Paul Mackerras commit 0d72ba930cbc9140a584af7e4e65041b6c7a7d18 Author: Olof Johansson Date: Sat Sep 8 05:13:19 2007 +1000 [POWERPC] Add workaround for MPICs with broken register reads Some versions of PWRficient 1682M have an interrupt controller in which the first register in each pair for interrupt sources doesn't always read with the right polarity/sense values. To work around this, keep a software copy of the register instead. Since it's not modified from the mpic itself, it's a feasible solution. Still, keep it under a config option to avoid wasting memory on other platforms. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit 2099172d61abda1b793b499bb8edcaac4de2cdae Author: David Gibson Date: Fri Sep 7 13:23:53 2007 +1000 [POWERPC] Document and implement an improved flash device binding for powerpc This replaces the binding for flash chips in booting-without-of.txt with an clarified and improved version. It also makes drivers/mtd/maps/physmap_of.c recognize this new binding. Finally it revises the Ebony device tree source to use the new binding as an example. Signed-off-by: David Gibson Acked-by: Segher Boessenkool Signed-off-by: Paul Mackerras commit 3c607ce2a3213f33b8b6b854b5f7db876021e466 Author: Linas Vepstas Date: Fri Sep 7 03:47:29 2007 +1000 [POWERPC] setup_64.c and prom.c comment cleanup Grammatical corrections to comments. Signed-off-by: Linas Vepstas Signed-off-by: Paul Mackerras commit 70c6cc37db342d9f970884e12744ab5ee290d4ad Author: Linas Vepstas Date: Fri Sep 7 03:46:15 2007 +1000 [POWERPC] prom.c whitespace cleanup Whitespace cleanup: badly indented lines. Signed-off-by: Linas Vepstas Signed-off-by: Paul Mackerras commit e788ff13be03c2cc4055d5569b7b218dc3f2cb7b Author: Linas Vepstas Date: Fri Sep 7 03:45:21 2007 +1000 [POWERPC] prom_init whitespace cleanup, typo fix Whitespace cleanup: badly indented lines. Typo in comment. Signed-off-by: Linas Vepstas Signed-off-by: Paul Mackerras commit bde6c6e16aa489ea76c762fb7ffb0abb48660dd8 Author: Scott Wood Date: Thu Sep 6 08:04:38 2007 +1000 [POWERPC] Check _PAGE_RW and _PAGE_PRESENT on kernel addresses Previously, the TLB miss handlers assumed that pages above KERNELBASE are always present and read/write. This assumption is false in the case of CONFIG_DEBUG_PAGEALLOC. Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras commit 96ebc3bfb6ddedd5a400d5653b50551d5a3de439 Author: Scott Wood Date: Thu Sep 6 05:21:18 2007 +1000 [POWERPC] bootwrapper: Only print MAC addresses when the node is actually present Some firmwares (such as PlanetCore) only provide a base MAC address, and expect the kernel to set certain bits to generate the addresses for the other ports. As such, MAC addresses are generated that may not correspond to actual hardware. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 21f3fe2f7ab57832ea1fc7f719ec7e167b7ad80e Author: Scott Wood Date: Thu Sep 6 05:21:12 2007 +1000 [POWERPC] bootwrapper: Add get_path() This will be used by the PlanetCore firmware support to construct a linux,stdout-path from the serial node that it finds. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 9de782770b84768e1aa2e6454223ef30768de84e Author: Scott Wood Date: Thu Sep 6 05:21:10 2007 +1000 [POWERPC] bootwrapper: Add strtoull() This will be needed by PlanetCore firmware support. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 4674f2f33948432469e52d5bcaeda9904e34fe46 Author: Scott Wood Date: Thu Sep 6 05:21:04 2007 +1000 [POWERPC] bootwrapper: flatdevtree fixes 1. ft_create_node was returning the internal pointer rather than a phandle. 2. ft_find_device_rel was treating a "top" phandle of NULL as an error, rather than as the root of the tree. The old, absolute ft_find_device is removed, and the relative version is renamed to ft_find_device(). Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 6bcc4c01755fd2066bc374193cf3b0849cbabe47 Author: Olof Johansson Date: Wed Sep 5 12:43:17 2007 +1000 [POWERPC] Remove warning in arch/powerpc/kernel/sysfs.c Fixes: arch/powerpc/kernel/sysfs.c: In function 'cpu_add_sysdev_attr_group': arch/powerpc/kernel/sysfs.c:388: warning: ignoring return value of 'sysfs_create_group', declared with attribute warn_unused_result Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit a416561bf790d55db68b2980c2a6951981018041 Author: Olof Johansson Date: Wed Sep 5 12:42:30 2007 +1000 [POWERPC] Move lowlevel runlatch calls under cpu feature control There's no need to call the runlatch on functions on processors that don't implement them (CPU_FTR_CTRL). Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit 01f1c735f57548e6b862e815cc845e452405643d Author: Olof Johansson Date: Wed Sep 5 12:41:09 2007 +1000 [POWERPC] Remove unused platform_machine_check() Remove leftover cruft from ARCH=ppc. There are no users of platform_machine_check() in ARCH=powerpc, and none should be added (they should use ppc_md.machine_check_handler instead). Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit 3850169dbddcc9e53fd550eb093af7da5dfcefa9 Author: Olof Johansson Date: Wed Sep 5 12:09:45 2007 +1000 [POWERPC] pasemi: Move pasemi_idle_init() to late_initcall() Move pasemi_idle_init() to be a late_initcall instead of being called from setup_arch(). This way the cpufreq driver has a chance to initialize and save away the boot time astate before we go to idle for the first time. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit cd7834167ffb66b470e4d9edb10efb5c1a2dfe7f Author: Olof Johansson Date: Wed Sep 5 12:09:23 2007 +1000 [POWERPC] pasemi: Print more information at machine check Add printout of some SoC error status registers, and dump the SLB contents for those machine check events where it makes sense. Since we can't go about and ioremap registers at machine check time, and we generally want to do as little as possible to print out the information, pre-build a table of the registers to dump and their address in the common PCI config space range. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit 2e1957fd47b9d4b7bf35be2ec3d4b5e3eefe5cc0 Author: Olof Johansson Date: Wed Sep 5 12:09:06 2007 +1000 [POWERPC] pasemi: Export more SPRs to sysfs when CONFIG_DEBUG_KERNEL=y Export some of the implementation-specific registers via sysfs. Useful when debugging, etc. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit 4d442331e57b7bbc28b5a20f7d069bc12e9c503e Author: Olof Johansson Date: Wed Sep 5 12:08:50 2007 +1000 [POWERPC] pasemi: Add workaround for erratum 5945 Erratum 5945 causes some of the registers on the PCIe root ports to not read correctly. Do a small dance to avoid this: Write an unused register, read the value and write it back. Thankfully this is not in a hot code path. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit 68c8404c742fdda2151b4bf6bd98419bf8118481 Author: Olof Johansson Date: Wed Sep 5 12:08:30 2007 +1000 [POWERPC] pasemi: Add pasemi_pci_getcfgaddr() Add pasemi_pci_getcfgaddr(), to get the remapped address of a specific config register for a PCI device. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit a302cb9d95978505b18c12be0cd1e41556564f68 Author: Olof Johansson Date: Fri Aug 31 13:58:51 2007 +1000 [POWERPC] Export new __io{re,un}map_at() symbols Export new __io{re,un}map_at() symbols so modules can use them. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit 60b332e755da7dbf32f1660973ce4f97ebf05d05 Author: Michael Ellerman Date: Tue Aug 28 18:47:57 2007 +1000 [POWERPC] Export virq mapping via debugfs This adds a debugfs file "powerpc/virq_mapping", which shows the virtual to real mapping of irq numbers. Enable it with CONFIG_VIRQ_DEBUG. Signed-off-by: Zhang Wei Signed-off-by: Chen Gong Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras commit 7866291d4cabf5491d4ecb62787308f8b8958f59 Author: Michael Ellerman Date: Tue Aug 28 18:47:56 2007 +1000 [POWERPC] Initialise hwirq for legacy irqs Although no one uses the hwirq value for legacy irqs at the moment, we should really setup the correct value in the irq_map. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras commit 6815800601d3e46b976c868e4e85fb6de32b9133 Author: Michael Ellerman Date: Tue Aug 28 18:47:55 2007 +1000 [POWERPC] Provide a default irq_host match, which matches on an exact of_node The most common match semantic is an exact match based on the device node. So provide a default implementation that does this, and hook it up if no match routine is specified. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras commit 8528ab84ebe7a1eeed9b0acc808df86663d506c0 Author: Michael Ellerman Date: Tue Aug 28 18:47:55 2007 +1000 [POWERPC] Invert null match behaviour for irq_hosts Currently if you don't specify a match callback for your irq_host it's assumed you match everything. This is a kind of opt-out approach, and turns out to be the exception rather than the rule. So change the semantics to be opt-in, ie. you don't match anything unless you provide a match callback. This in itself isn't very useful, but will allow us to provide a default match implementation in a subsequent patch. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras commit 52964f87c64e6c6ea671b5bf3030fb1494090a48 Author: Michael Ellerman Date: Tue Aug 28 18:47:54 2007 +1000 [POWERPC] Add an optional device_node pointer to the irq_host The majority of irq_host implementations (3 out of 4) are associated with a device_node, and need to stash it somewhere. Rather than having it somewhere different for each host, add an optional device_node pointer to the irq_host structure. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras commit 0ae0b54565a8dcc2b98de694b998e765de15b713 Author: David Gibson Date: Tue Aug 28 14:52:57 2007 +1000 [POWERPC] Move bootwrapper's strchr() and strncmp() from .h to string.S Currently the bootwrapper has implementations of strchr() and strncmp(), but they're inlines in flatdevtree_env.h, rather than in string.S with all the rest of the string functions. This moves them to string.S. Signed-off-by: David Gibson Signed-off-by: Paul Mackerras commit 768cc2d3b2768ca34f254e8190f1f9e297b09ad4 Author: Linas Vepstas Date: Wed Jul 18 02:09:35 2007 +1000 [POWERPC] IOMMU virtual merge is no longer experimental Per conversations with BenH, IOMMU virtual merging should no longer be considered to be an "experimental" feature. In particular, CONFIG_VMERGE has been set to "y" in the defconfigs for quite a while. Signed-off-by: Linas Vepstas Acked-by: Benjamin Herrenschmidt ---- arch/powerpc/Kconfig | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) Signed-off-by: Paul Mackerras commit 5326152fa182b0a16e4abf913ce403e3c7ab53b7 Author: Josh Boyer Date: Fri Sep 7 07:51:44 2007 -0500 [POWERPC] Walnut zImage wrapper Add zImage wrapper for walnut board Signed-off-by: Josh Boyer Acked-by: David Gibson commit 545c069ccd76a0f1f3ceacd8ba5bc8f5208eb727 Author: Josh Boyer Date: Fri Sep 7 07:51:24 2007 -0500 [POWERPC] Walnut board support Board support for the PPC405 Walnut evaluation board Signed-off-by: Josh Boyer Acked-by: David Gibson commit 7f2814d229905c35d7c38798891adf00286fdca4 Author: Josh Boyer Date: Fri Sep 7 07:51:08 2007 -0500 [POWERPC] Walnut defconfig Walnut board defconfig Signed-off-by: Josh Boyer commit 8852ab7afc2397779f9ea926187dbc4e0452ab47 Author: Josh Boyer Date: Fri Sep 7 07:50:50 2007 -0500 [POWERPC] Walnut DTS Device tree source file for the PPC405 Walnut evaluation board. Signed-off-by: Josh Boyer Acked-by: David Gibson commit 1f6e57952180cd54e245241b74f4b9cb10c24f98 Author: Josh Boyer Date: Fri Sep 7 07:50:26 2007 -0500 [POWERPC] Fix bus probe on Bamboo board Commit 804ace8881d21 changed the behavior of how compatible nodes are found. This highlighted a bug on the Bamboo board where it wasn't probing the bus specified in the DTS file. We fix it by being explicit about which bus to probe. Signed-off-by: Josh Boyer Acked-by: David Gibson commit c9c6b744d8a2a95ef6d5c8389964df5148e3102a Author: Josh Boyer Date: Fri Sep 7 07:49:59 2007 -0500 [POWERPC] Remove dtc build cruft from DTS files The patch below removes the dtc incantation instructions from the in-kernel DTS files. It's not needed, and is prone to being out-of-date most of the time. Signed-off-by: Josh Boyer Acked-by: David Gibson commit 606d08bcd674073e0e505cb1eb4ff1516c3b498a Author: Valentine Barshak Date: Wed Aug 29 17:38:30 2007 +0400 [POWERPC] PowerPC 440EPx: Sequoia bootwrapper Bootwrapper code for AMCC PPC440EPx Sequoia. Signed-off-by: Valentine Barshak Acked-by: David Gibson Signed-off-by: Josh Boyer commit 15fc993e31293f9b179eb5f08b18a4a4f2ca648a Author: Valentine Barshak Date: Wed Aug 29 17:40:30 2007 +0400 [POWERPC] PowerPC 440EPx: Sequoia board support AMCC PPC440EPx Sequoia board support. Signed-off-by: Valentine Barshak Acked-by: David Gibson Signed-off-by: Josh Boyer commit 38a5d6c9e79c2dbf3b23fb6fe8c2b51551bc9ee3 Author: Valentine Barshak Date: Wed Aug 29 17:41:28 2007 +0400 [POWERPC] PowerPC 440EPx: Sequoia defconfig AMCC PPC440EPx Sequoia default config. Signed-off-by: Valentine Barshak Acked-by: David Gibson Signed-off-by: Josh Boyer commit d60ff953652f0a2f74ad17ab2d9a0e928c1902d3 Author: Valentine Barshak Date: Wed Aug 29 17:39:42 2007 +0400 [POWERPC] PowerPC 440EPx: Sequoia device tree AMCC PPC440EPx Sequoia device tree. Signed-off-by: Valentine Barshak Acked-by: David Gibson Signed-off-by: Josh Boyer commit 2f6c9d961081dc7b109eb19166244bcb2a5dfc28 Author: Kumar Gala Date: Fri Aug 17 01:52:39 2007 -0500 [POWERPC] Stop include asm-ppc when building ARCH=powerpc for ppc32 We no longer have any dependancies on include/asm-ppc so we can get ride of the makefile hacks to include it in the build process. Signed-off-by: Kumar Gala commit 33d71d26ba982f99b8cb76b86b2e1e0a0964a8ac Author: Kumar Gala Date: Mon Aug 20 08:50:28 2007 -0500 [POWERPC] Copy over headers from arch/ppc to arch/powerpc that we need To build arch/powerpc without including asm-ppc/ we need these files in asm-powerpc/ Moved some headers under arch/powerpc/platforms if they were only used by platform or driver files and fixed up the source file includes to match the new locations Signed-off-by: Kumar Gala commit ed16c20da6f500bc2dfad933078d2987636a7b60 Author: Kumar Gala Date: Fri Aug 17 01:47:39 2007 -0500 [POWERPC] Remove old includes from arch/ppc Remove includes of files that existed in arch/ppc that we dont need in arch/powerpc anymore. The following includes were removed: This also caused platforms/embedded6xx/mpc7448_hpc2.h to no longer be needed and thus removed. Signed-off-by: Kumar Gala commit 5b072ba453078293b8f6de8cdd79d9c26f015238 Author: Stephen Rothwell Date: Wed Aug 22 13:49:41 2007 +1000 [POWERPC] Exception numbers are not relevant to iSeries so remove them from the macros. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 7180e3e636deff82f8810291878a184f21142fa9 Author: Stephen Rothwell Date: Wed Aug 22 13:48:37 2007 +1000 [POWERPC] Split out iSeries specific exception macros Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit dc8f571a26689102f6abe2565a84226edeaacc61 Author: Stephen Rothwell Date: Wed Aug 22 13:47:24 2007 +1000 [POWERPC] Move the iSeries exception vectors out of head_64.S and into platforms/iseries/exception.S Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit f9ff0f304833be9a6a605c84e24d630d5aef2230 Author: Stephen Rothwell Date: Wed Aug 22 13:46:44 2007 +1000 [POWERPC] Move the exception macros into a header file It makes head_64.S a bit more readable and will allow us to move the iSeries exceptions elsewhere. This also removes the last line of the comment: * The following macros define the code that appears as * the prologue to each of the exception handlers. They * are split into two parts to allow a single kernel binary * to be used for pSeries and iSeries. * LOL. One day... - paulus Anything is possible. :-) Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit fc68e8699f1f987060ef817cff6a13a7cd7d4c8a Author: Stephen Rothwell Date: Wed Aug 22 13:44:58 2007 +1000 [POWERPC] Move iSeries startup code out of head_64.S Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit dc559f7cd5d6d11a99b6c29402b31fbb3f3a1db0 Author: Olof Johansson Date: Wed Aug 22 12:26:43 2007 +1000 [POWERPC] Rework SMP timebase handoff for pasemi Rework timebase handoff to play nice with configurations with more than 2 cores, as well as with CPU hotplug. Previous scheme just pushed out the current timebase from the giving core to all cores without caring if they wanted it or not, nor checking if they'd taken it. The taking side didn't make sure the giving side had provided a value yet either. In other words, it was completely broken. Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras commit e5d8d54db25790524da34b0143f4e0176fb7677b Author: Scott Wood Date: Tue Aug 21 03:40:02 2007 +1000 [POWERPC] bootwrapper: Add PowerQUICC II (82xx with CPM) cuboot support This allows booting on legacy, non-device-tree aware versions of U-boot. It also fixes up the hardware to match the PCI and chipselect information in the device tree, as u-boot is inconsistent in setting these up correctly (or at all). Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 0b195812dfbccc2ac33e17b35b899dd4fea7611f Author: Scott Wood Date: Tue Aug 21 03:40:01 2007 +1000 [POWERPC] bootwrapper: Add 8xx cuboot support This allows booting on legacy, non-device-tree aware versions of U-boot. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 2f1d4899321be87bc5f0c4ee0e62c9d9ced05f80 Author: Scott Wood Date: Tue Aug 21 03:39:58 2007 +1000 [POWERPC] bootwrapper: Move linker symbols into ops.h Most of these were previously used by numerous C files and redeclared in each one. Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras commit d0f53fafc016b3f4f20f63ecf52f6df8774bcb3c Author: Scott Wood Date: Tue Aug 21 03:39:57 2007 +1000 [POWERPC] bootwrapper: Add CPM serial driver This serial port is used on all 8xx, many 82xx, and some 85xx chips. The driver requires that the port has already been set up by the firmware and/or platform code. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 3ee9b7abafc36a9377af6f036f50c3450954884c Author: Scott Wood Date: Tue Aug 21 03:39:55 2007 +1000 [POWERPC] bootwrapper: Declare udelay() in ops.h Declarations in various users are removed. Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras commit dc4f397d6e385c4ea0fe9732df911a86f1a78c9a Author: Scott Wood Date: Tue Aug 21 03:39:54 2007 +1000 [POWERPC] bootwrapper: serial_console_init() fixes 1. Search the entire compatible list for serial devices. The serial code previously did a simple strcmp on the compatible node; this fails when the match string is not the first compatible listed. Use dt_is_compatible() instead. 2. Don't call serial_edit_cmdline if getc isn't defined. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 61d3b949b70802c4f32d540b11a93128c31c67ea Author: Scott Wood Date: Tue Aug 21 03:39:52 2007 +1000 [POWERPC] bootwrapper: Add TARGET_HAS_ETHn tests to ppcboot.h U-boots more recent than when ppcboot.h was forked allow the board config file to enable additional ethernet ports explicitly, rather than using a hardcoded list of targets. This allows bootwrapper platform files to do the same. Fortunately, nothing after the ethernet addresses is of interest to cuboot platforms, so the inevitable mismatches won't be too catastrophic. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 6e913c67b3eb93e2b8bc1dc0ff854f00a760f41b Author: Scott Wood Date: Tue Aug 21 03:39:51 2007 +1000 [POWERPC] bootwrapper: Add 16-bit I/O, sync(), eieio(), and barrier() Also, include types.h from io.h, so callers don't have to. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit a73ac50c4787b1b28d5c94bb18c60352f5dd7d6f Author: Scott Wood Date: Tue Aug 21 03:39:48 2007 +1000 [POWERPC] bootwrapper: Add dt_is_compatible() This can be used rather than doing a simple strcmp, which will fail to handle multiple compatible entries. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 0602801c22ea1767cd0298b11da140bd5cb764d2 Author: Scott Wood Date: Tue Aug 21 03:39:46 2007 +1000 [POWERPC] bootwrapper: dt_xlate_range() bugfixes 1. The check whether ranges fits in the buffer was using elements rather than bytes. 2. Empty ranges were not properly treated as transparent, and missing ranges were treated as transparent. 3. The loop terminated when translating from the root rather than to. Once bug #2 was fixed, it failed due to a missing ranges in the root node. 4. In decoding the ranges property, the #size-cells used was that of the parent, not the child. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 643d3c139b0a5289d7f0ba19fdcb24be6d7e768f Author: Scott Wood Date: Tue Aug 21 03:39:45 2007 +1000 [POWERPC] bootwrapper: Set timebase_period_ns from dt_fixup_cpu_clocks This lets udelay() work properly on platforms which use dt_fixup_cpu_clocks. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 44d06ba72990893eb5506516b25ccaf3a757ffc0 Author: Scott Wood Date: Tue Aug 21 03:39:20 2007 +1000 [POWERPC] bootwrapper: Update .gitignore All cuImage types are ignored, as well as preprocessed .lds files, and the forthcoming zImage.bin files and embedded planet board images. Signed-off-by: Scott Wood Acked-by: David Gibson Signed-off-by: Paul Mackerras commit 804ace8881d211ac448082e871dd312132393049 Author: Scott Wood Date: Tue Aug 21 02:36:59 2007 +1000 [POWERPC] Use strcasecmp() rather than strncasecmp() when determining device node compatibility The current code assumes "foo-bar" must always be compatible with a node compatible with "foo", which breaks device trees where this is not so. The "case" part is also wrong according to Open Firmware, but it's more likely to have drivers and/or device trees depending on it, and thus needs to be handled more carefully. Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras commit 12cdac34c6e90d887de23ab9747185731cba254a Author: Scott Wood Date: Tue Aug 21 02:36:58 2007 +1000 [POWERPC] Add clrbits8 and setbits8 Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras commit 4b218e9bb2fbbc57b5a05de41d77c056a134528c Author: Scott Wood Date: Tue Aug 21 02:36:19 2007 +1000 [POWERPC] Whitespace cleanup in arch/powerpc Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras commit 16a15a30f8a09af6ce2dc4fd6eec9b454c1fe488 Author: Stephen Rothwell Date: Mon Aug 20 14:58:36 2007 +1000 [POWERPC] iSeries: Clean up lparmap mess We need to have xLparMap in head_64.S so that it is at a fixed address (because the linker will not resolve (address & 0xffffffff) for us). But the assembler miscalculates the KERNEL_VSID() expressions. So put the confusing expressions into asm-offsets.c. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 556ecf9be66f4d493e19bc71a7ce84366d512b71 Author: Olaf Hering Date: Sat Aug 18 04:27:17 2007 +1000 [POWERPC] Advertise correct IDE mode on Pegasos2 The built-in IDE controller is configured in legacy mode, but the PCI registers advertise native mode. Force the PCI class into legacy mode. This allows pata_via to access two drives. The Pegasos specific irq enforcement in the via82cxxx driver must stay because there is apparently no generic way to setup irq per channel. Tested on Pegasos2 with firmware version 20040810, and two IDE disks. Signed-off-by: Olaf Hering Signed-off-by: Paul Mackerras commit 2ba4573cdaf98b0f3acb8795a66f412c1c41284a Author: Josh Boyer Date: Mon Aug 20 07:30:32 2007 -0500 [POWERPC] Bamboo zImage wrapper Add a bootwrapper for the AMCC 440EP Bamboo Eval board. This also adds a common fixup_clock function for all 440EP(x) chips. Signed-off-by: Josh Boyer Acked-by: David Gibson commit 8c1449bdb4c7e9c4492ba18ded70fd8669eeffae Author: Josh Boyer Date: Mon Aug 20 07:30:14 2007 -0500 [POWERPC] Bamboo board support Add support for the AMCC Bamboo board Signed-off-by: Josh Boyer Acked-by: David Gibson commit 142b58ee5600e592e83ff7d2e4672e6cb0b39c27 Author: Josh Boyer Date: Mon Aug 20 07:29:55 2007 -0500 [POWERPC] Bamboo DTS AMCC Bamboo board DTS Signed-off-by: Josh Boyer commit 1daa194a87b3ea77760b4b5361eb47900dfc00a9 Author: Josh Boyer Date: Mon Aug 20 07:29:36 2007 -0500 [POWERPC] Fix 40x build Remove inclusion of __res on 40x. We don't need it in arch/powerpc Signed-off-by: Josh Boyer Acked-by: David Gibson commit aab69292e4efd38181cd300d9b83b12592643d6c Author: Josh Boyer Date: Mon Aug 20 07:29:11 2007 -0500 [POWERPC] 40x decrementer fixes Allow generic_calibrate_decr to work for 40x platforms. Given that the hardware behavior is identical, this also changes the set_dec function to reload the PIT on 40x to match the behavior 44x currently has. Signed-off-by: Josh Boyer commit 4d922c8dc332f4c7bc156fa832187661d4899cee Author: Josh Boyer Date: Mon Aug 20 07:28:48 2007 -0500 [POWERPC] 40x MMU Add MMU definitions for 40x platforms. Also fixes two warnings in 40x_mmu.c. Signed-off-by: Josh Boyer Acked-by: David Gibson commit e90f3b74d884d0f2826e06dbab4f615ca346eaa4 Author: Josh Boyer Date: Mon Aug 20 07:28:30 2007 -0500 [POWERPC] 4xx bootwrapper reworks Make the fixup_memsize function common for all of 4xx as several chips share the same SDRAM controller. Also add functions to reset 40x chips and quiesce the ethernet. Signed-off-by: Josh Boyer commit 869680c16fb028ac4ad9a449283e0514789c654a Author: Josh Boyer Date: Mon Aug 20 07:28:05 2007 -0500 [POWERPC] Rename 44x bootwrapper Rename the 44x.c wrapper file to 4xx.c. This will allow us to add common functions in a single file that can be shared across all of 4xx. Signed-off-by: Josh Boyer Acked-by: David Gibson commit 3cc248ae6eaac4175047d1fdc4fadd8a94651f83 Author: Josh Boyer Date: Mon Aug 20 07:27:42 2007 -0500 [POWERPC] 4xx Kconfig cleanup Remove some leftover cruft in the 40x Kconfig file. Also make sure we select WANT_DEVICE_TREE for 40x. Signed-off-by: Josh Boyer Acked-by: David Gibson commit 15f6527e8e63e793f8ab1ddce4ed3c487ebd0d42 Author: Josh Boyer Date: Mon Aug 20 07:27:07 2007 -0500 [POWERPC] Rename 4xx paths to 40x 4xx is a bit of a misnomer for certain things, as they really apply to PowerPC 40x only. Rename some of the files to clean this up. Signed-off-by: Josh Boyer Acked-by: David Gibson commit a65517f857bf6657839957617af942a4b631fba5 Author: Stephen Rothwell Date: Thu Aug 16 11:19:19 2007 +1000 [POWERPC] Remove some duplicate declarations from pmac.h Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit e78bb5dc2e0515dce2ac2c590d66405028b7ccd6 Author: Guennadi Liakhovetski Date: Thu Aug 16 05:15:03 2007 +1000 [POWERPC] Fix i2c device string format Use strlcpy() to guarantee strings in i2c device type and driver_name fields are 0-terminated. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mackerras commit 750d1d1ca1d2e94e15393927fd3c30222d1c5203 Author: Stephen Rothwell Date: Wed Aug 15 20:58:23 2007 +1000 [POWERPC] Fix section mismatch in pasemi/iommu.c These functions are only called by __init functions. WARNING: vmlinux.o(.text+0x56aa0): Section mismatch: reference to .init.text:.lmb_alloc (between '.iob_init' and '.iommu_init_early_pasemi') Signed-off-by: Stephen Rothwell Acked-by: Olof Johansson Signed-off-by: Paul Mackerras commit 124d795d16b018b054956c9be561f889acf95ac4 Author: Stephen Rothwell Date: Wed Aug 15 20:55:57 2007 +1000 [POWERPC] Fix section mismatches in udbg_adb.c The functions are only called from __init functions. WARNING: vmlinux.o(.text+0x45ed0): Section mismatch: reference to .init.text:.btext_find_display (between '.udbg_adb_init_early' and '.udbg_adb_init') WARNING: vmlinux.o(.text+0x45f9c): Section mismatch: reference to .init.text:.btext_find_display (between '.udbg_adb_init' and '.udbg_adb_getc_poll') WARNING: vmlinux.o(.text+0x46000): Section mismatch: reference to .init.text:.find_via_pmu (between '.udbg_adb_init' and '.udbg_adb_getc_poll') Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 109b60f0bc1306192c765875badcaa5f3850a0a1 Author: Stephen Rothwell Date: Wed Aug 15 20:54:32 2007 +1000 [POWERPC] Fix section mismatch in dart_iommu.c These functions are only called from __init functions. WARNING: vmlinux.o(.text+0x398f4): Section mismatch: reference to .init.text:.lmb_alloc (between '.iommu_init_early_dart' and '.pci_dma_bus_setup_dart') Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit d56c3aaa9f660e5f5f295da74f5d3db510de0ede Author: Stephen Rothwell Date: Wed Aug 15 20:53:26 2007 +1000 [POWERPC] Fix section mismatch in crash_dump.c WARNING: vmlinux.o(.text+0x23258): Section mismatch: reference to .init.text:.lmb_reserve (between '.reserve_kdump_trampoline' and '.restore_processor_state') Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 553fdff633b1cb8cfccf554768444c5580a8d7f7 Author: David Gibson Date: Tue Aug 14 13:52:42 2007 +1000 [POWERPC] Improve robustness of the UIC cascade handler At present the cascade interrupt handler for the UIC (interrupt controller on 4xx embedded chips) will misbehave badly if it is called spuriously - that is if the handler is invoked when no interrupts are asserted in the child UIC. Although spurious interrupts shouldn't happen, it's good to behave robustly if they do. This patch does so by checking for and ignoring spurious interrupts. Signed-off-by: Valentine Barshak Signed-off-by: David Gibson Acked-by: Josh Boyer Signed-off-by: Paul Mackerras commit 868afce21fdadcecc7bde9263321065948508c56 Author: David Gibson Date: Tue Aug 14 13:52:42 2007 +1000 [POWERPC] Fix irq flow handler for 4xx UIC At present the driver for the UIC (the embedded interrupt controller in 4xx chips) uses the handle_level_irq() flow handler. It turns out this does not correctly handle level triggered interrupts on the UIC. Specifically, acknowledging an irq on the UIC (i.e. clearing the relevant bit in UIC_SR) will have no effect for a level interrupt which is still asserted by the external device, even if the irq is already masked. Therefore, unlike handle_level_irq() we must ack the interrupt after invoking the ISR (which should cause the device to stop asserting the irq) instead of acking it when we mask it, before the ISR. This patch implements this change, in a new handle_uic_irq(), a customised irq flow handler for the UIC. For edge triggered interrupts, handle_uic_irq() still uses the old flow - we must ack edge triggered interrupt before the ISR not after, or we could miss a second event which occurred between invoking the ISR and acking the irq. Signed-off-by: David Gibson Acked-by: Josh Boyer Signed-off-by: Paul Mackerras commit 4dc7b4b0405fd7320940849b6e31ea8ea68fd0df Author: David Gibson Date: Tue Aug 14 13:52:42 2007 +1000 [POWERPC] Fix setting of irq trigger type in UIC driver The UIC (interrupt controller in 4xx embedded CPUs) driver currently missets the IRQ_lEVEL flag in desc->status, due to a thinko. This patch fixes the bug. Currently this is only a cosmetic problem (affects the output in /proc/interrupts), however subsequent patches will use the IRQ_LEVEL flag to affect flow handling. Signed-off-by: Valentine Barshak Signed-off-by: David Gibson Acked-by: Josh Boyer Signed-off-by: Paul Mackerras commit a05afe9146f7611d40a58be34ee8442727a6af1f Author: Stephen Rothwell Date: Wed Aug 15 16:54:04 2007 +1000 [POWERPC] Comment out a currently unused function Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit e8ff0646e5df850ff084be9c97a2e69fff5697b4 Author: Stephen Rothwell Date: Wed Aug 15 16:51:18 2007 +1000 [POWERPC] Tidy up CONFIG_PPC_MM_SLICES code This removes some of the #ifdefs from .c files. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 0b8188a44def37f4f8ef01653da199ca3a3e0a2a Author: Stephen Rothwell Date: Wed Aug 15 16:45:15 2007 +1000 [POWERPC] Remove get_property and device_is_compatible They were only needed for backwards compatibility and all in tree uses have now been changed. Signed-off-by: Stephen Rothwell Acked-by: David S. Miller Signed-off-by: Paul Mackerras commit 9c25099db74b384e16345622071552f9f10dd045 Author: Stephen Rothwell Date: Wed Aug 15 16:42:12 2007 +1000 [POWERPC] Use of_get_property in ipmi code get_property has been renamed to of_get_property. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 9dfe5c53d0fcc08e9efc1e13bb6702fac74f4a12 Author: Stephen Rothwell Date: Wed Aug 15 16:33:55 2007 +1000 [POWERPC] Fix non HUGETLB_PAGE build warning arch/powerpc/mm/mmu_context_64.c: In function 'init_new_context': arch/powerpc/mm/mmu_context_64.c:31: warning: unused variable 'new_context' Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras commit 1ac9f1f71dea5944085b7b4954516794a9dab35a Author: Becky Bruce Date: Wed Aug 15 04:45:44 2007 +1000 [POWERPC] Update lmb.h include protection to ASM_POWERPC This file was protected by _PPC64_LMB_H, which is confusing, as the 32-bit code also uses the lmb these days. Changed to _ASM_POWERPC_LMB_H. Signed-off-by: Becky Bruce Signed-off-by: Paul Mackerras commit 7b52b440d37d669ec93297cf589984a110518d43 Author: Michael Buesch Date: Mon Aug 13 06:38:34 2007 +1000 [POWERPC] via-pmu: Fix typo in printk This fixes a typo in a printk message. Signed-off-by: Michael Buesch Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras commit 9f0cbea0d8cc47801b853d3c61d0e17475b0cc89 Author: Segher Boessenkool Date: Sat Aug 11 10:15:30 2007 +1000 [POWERPC] Implement atomic{, 64}_{read, write}() without volatile Instead, use asm() like all other atomic operations already do. Also use inline functions instead of macros; this actually improves code generation (some code becomes a little smaller, probably because of improved alias information -- just a few hundred bytes total on a default kernel build, nothing shocking). Signed-off-by: Segher Boessenkool Signed-off-by: Paul Mackerras commit c6d4267eced79775399f256fbb4adb671e9b597e Author: Paul Mackerras Date: Fri Aug 10 14:07:38 2007 +1000 [POWERPC] Handle alignment faults on new FP load/store instructions This adds code to handle alignment traps generated by the following new floating-point load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): lfiwax load floating-point as integer word algebraic indexed stfiwx store floating-point as integer word indexed lfdp load floating-point double pair lfdpx load floating-point double pair indexed stfdp store floating-point double pair stfdpx store floating-point double pair indexed All these except stfiwx are new in POWER6. lfdp/lfdpx/stfdp/stfdpx load and store 16 bytes of memory into an even/odd FP register pair. In little-endian mode each 8-byte value is byte-reversed separately (i.e. not as a 16-byte unit). lfiwax/stfiwx load or store the lower 4 bytes of a floating-point register from/to memory; lfiwax sets the upper 4 bytes of the FP register to the sign extension of the value loaded. Signed-off-by: Paul Mackerras commit 09a54101e15f43607722dee55f33d1962653c6cb Author: Linas Vepstas Date: Fri Aug 10 09:28:11 2007 +1000 [POWERPC] pseries: Remove dead EEH video code Remove dead code, and a misleading comment about EEH checking for video devices. The removed code is a left-over from the olden days where there was concern over how video devices worked in Linux. We are never going to go that way again, so kill this. Signed-off-by: Linas Vepstas ---- arch/powerpc/platforms/pseries/eeh.c | 17 ----------------- 1 file changed, 17 deletions(-) Signed-off-by: Paul Mackerras commit 0f7f2fb85a67953acd6bf379681f22f5c83d4f60 Author: Nathan Lynch Date: Fri Aug 10 07:43:28 2007 +1000 [POWERPC] Remove gratuitous reads from powermac pci config space methods The powermac pci configuration space write methods read the written location immediately after the write is performed, presumably in order to flush the write. However, configuration space writes are not allowed to be posted, making these reads gratuitous. Furthermore, this behavior potentially causes us to violate the PCI PM spec when changing between e.g. D0 and D3 states, because a delay of up to 10ms may be required before the OS accesses configuration space after the write which initiates the transition. Remove the unnecessary reads from macrisc_write_config, u3_ht_write_config, and u4_pcie_write_config. Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit b139f1fb0f1e4bfe06f2c88ba8c9a55d9513d871 Author: Nathan Lynch Date: Fri Aug 10 07:37:27 2007 +1000 [POWERPC] Remove gratuitous reads from pasemi pci config space methods The pasemi pci configuration space write method reads the written location immediately after the write is performed, presumably in order to flush the write. However, configuration space writes are not allowed to be posted, making these reads gratuitous. Furthermore, this behavior potentially causes us to violate the PCI PM spec when changing between e.g. D0 and D3 states, because a delay of up to 10ms may be required before the OS accesses configuration space after the write which initiates the transition. Remove the unnecessary reads from pa_pxp_write_config. Signed-off-by: Nathan Lynch Acked-by: Olof Johansson Signed-off-by: Paul Mackerras commit 8935fa0fe6f87c4df806f605de04aed4353c7600 Author: Nathan Lynch Date: Fri Aug 10 05:18:46 2007 +1000 [POWERPC] tsi108_direct_pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit c78d453b6f95ff38a2226f6f77a4b08a6e27fc42 Author: Nathan Lynch Date: Fri Aug 10 05:18:45 2007 +1000 [POWERPC] indirect_pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit f1d645f42849ce3c12781514e6ced97748ada6b1 Author: Nathan Lynch Date: Fri Aug 10 05:18:44 2007 +1000 [POWERPC] chrp pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit 21d8f6c728a0eb852b521626a41b2bba6a6216d9 Author: Nathan Lynch Date: Fri Aug 10 05:18:43 2007 +1000 [POWERPC] efika rtas_pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit 6127d1c0b097b2e9acc83dede1c1cb64ce76e7d5 Author: Nathan Lynch Date: Fri Aug 10 05:18:42 2007 +1000 [POWERPC] null_pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit 3fac10e7f5a6dfa4a08938d24af2775cd9b9e267 Author: Nathan Lynch Date: Fri Aug 10 05:18:41 2007 +1000 [POWERPC] powermac pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit 1bb8c6216f08519c16ce20b82e6f6a59fe0ce717 Author: Nathan Lynch Date: Fri Aug 10 05:18:40 2007 +1000 [POWERPC] pa_pxp_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Acked-by: Olof Johansson Signed-off-by: Paul Mackerras commit 2e67d40762215bcd7c9b81e828ef6de453a09bc4 Author: Nathan Lynch Date: Fri Aug 10 05:18:39 2007 +1000 [POWERPC] maple pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit 3e02aebbca47174d4263cac5ff5b68ea29a7bcff Author: Nathan Lynch Date: Fri Aug 10 05:18:38 2007 +1000 [POWERPC] celleb_epci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit aec249bc1944c5359c6d3aa2f674be6a9fb3d076 Author: Nathan Lynch Date: Fri Aug 10 05:18:37 2007 +1000 [POWERPC] celleb_fake_pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit 8674e0c9e570fcce948518e8fe518f4b61ac91fe Author: Nathan Lynch Date: Fri Aug 10 05:18:36 2007 +1000 [POWERPC] rtas_pci_ops: Use named structure member initializers Signed-off-by: Nathan Lynch Signed-off-by: Paul Mackerras commit 1bdb2867e5f0bca7c94f7df92f23fdd20524a488 Author: Nathan Lynch Date: Thu Aug 9 10:50:44 2007 +1000 [POWERPC] Remove gratuitous reads from maple PCI config space methods The maple PCI configuration space write methods read the written location immediately after the write is performed, presumably in order to flush the write. However, configuration space writes are not allowed to be posted, making these reads gratuitous. Furthermore, this behavior potentially causes us to violate the PCI PM spec when changing between e.g. D0 and D3 states, because a delay of up to 10ms may be required before the OS accesses configuration space after the write which initiates the transition. It definitely causes a system hang for me with a Broadcom 5721 PCIE network adapter, which is fixed by this change. Therefore this removes the gratuitous reads from u3_agp_write_config, u3_ht_write_config, and u4_pcie_write_config. Signed-off-by: Nathan Lynch Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras commit 96b952dd4b8aaa752b6086ad8bcaf2af23729b5f Author: Murali Iyer Date: Thu Aug 9 07:46:49 2007 +1000 [POWERPC] Export DCR symbols for modules In order to compile drivers as modules that uses some of the DCR functions, we need to export the symbols. Example, EMAC driver and other drivers that are under development use these functions. Signed-off-by: Murali Iyer Acked-by: Arnd Bergmann Signed-off-by: Paul Mackerras commit 0f2342c85df4248bc1cd72421b13969a0782ed6a Author: Linas Vepstas Date: Fri Aug 10 06:56:41 2007 +1000 [POWERPC] pseries: Eliminate global error_log_cnt variable Eliminate the use of error_log_cnt as a global var shared across different directories. Pass it as a parameter instead. Signed-off-by: Linas Vepstas ---- Respin of earlier patch, with the CONFIG_PSERIES junk removed from the header file. arch/powerpc/kernel/nvram_64.c | 10 +++++----- arch/powerpc/platforms/pseries/rtasd.c | 7 ++++--- include/asm-powerpc/nvram.h | 6 ++++-- 3 files changed, 13 insertions(+), 10 deletions(-) Signed-off-by: Paul Mackerras commit 79c0108d1b9db4864ab77b2a95dfa04f2dcf264c Author: Linas Vepstas Date: Thu Aug 9 06:06:15 2007 +1000 [POWERPC] pseries: Fix jumbled no_logging flag Get rid of the jumbled usage of the no_logging flag. Its use spans several directories, and is incorrectly/misleadingly documented. Instead, two changes: 1) nvram will accept error log as soon as its ready. 2) logging to nvram stops on the first fatal error reported. Signed-off-by: Linas Vepstas ---- arch/powerpc/kernel/nvram_64.c | 8 -------- arch/powerpc/platforms/pseries/rtasd.c | 14 ++++++-------- 2 files changed, 6 insertions(+), 16 deletions(-) Signed-off-by: Paul Mackerras commit 72755f44075d34cdb9bc467c6cd9a229292b5aff Author: Linas Vepstas Date: Thu Aug 9 06:04:48 2007 +1000 [POWERPC] Remove nvram forward declarations Forward declarations serve no purpose in this file. Signed-off-by: Linas Vepstas ---- arch/powerpc/kernel/nvram_64.c | 5 ----- 1 file changed, 5 deletions(-) Signed-off-by: Paul Mackerras commit 4511dad42a8da41fc2f5a58066c519c2228896ac Author: Linas Vepstas Date: Thu Aug 9 06:03:37 2007 +1000 [POWERPC] pseries: Simplify rtasd initialization Simplify rtasd initialization code; this also fixes a buglet, where the /proc entries weren't being cleaned up in case of failure. Signed-off-by: Linas Vepstas ---- arch/powerpc/platforms/pseries/rtasd.c | 53 +++++++++++---------------------- 1 file changed, 19 insertions(+), 34 deletions(-) Signed-off-by: Paul Mackerras commit ba28cc09316510aacb17f8421fdaae37969a4d5b Author: Linas Vepstas Date: Thu Aug 9 06:02:10 2007 +1000 [POWERPC] pseries: Use rtas_token instead of hand-rolled code The rtas_token() call does the same thing as this hand-rolled code. This makes the code easier to read. Signed-off-by: Linas Vepstas ---- arch/powerpc/platforms/pseries/rtasd.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) Signed-off-by: Paul Mackerras commit a4fc3a3cead7f9e00dc0f6e00238b11c030f94cc Author: Linas Vepstas Date: Fri Aug 10 07:01:50 2007 +1000 [POWERPC] pseries: Avoid excess rtas_token calls We don't need to look up the rtas event token once per cpu per second. This avoids some misc device-tree lookups and string ops and so provides some minor performance improvement. Signed-off-by: Linas Vepstas ---- Revised commit-log message. arch/powerpc/platforms/pseries/rtasd.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) Signed-off-by: Paul Mackerras commit f774216d465959a4777ac3de67f33bf75ecd4a76 Author: Segher Boessenkool Date: Thu Aug 2 01:41:15 2007 +1000 [POWERPC] Replace a few #defines with empty inline functions ...so that GCC doesn't complain about unused variables in the callers of these. Signed-off-by: Segher Boessenkool Signed-off-by: Paul Mackerras commit c05129bd8190fd702426f93f9fe0a00fa6cacb31 Author: Grant Likely Date: Wed Aug 1 23:53:28 2007 +1000 [POWERPC] Only ignore arch/ppc/include, not arch/ppc/boot/include arch/ppc/.gitignore shouldn't exclude arch/ppc/boot/include, so this makes arch/ppc/.gitignore more specific. Signed-off-by: Paul Mackerras commit 33567a023e734b640c27fc9cc4e7c6b45987b083 Author: Gabriel C Date: Wed Aug 1 19:41:09 2007 +1000 [POWERPC] Typo fixes interrrupt -> interrupt This fixes some interrrupt -> interrupt typos. Signed-off-by: Gabriel Craciunescu Signed-off-by: Paul Mackerras commit cc61f957f486871536cc5531e83337fff4fe48f3 Author: Mariusz Kozlowski Date: Wed Aug 1 08:10:03 2007 +1000 [POWERPC] drivers/macintosh/therm_adt746x.c: kmalloc + memset conversion to kzalloc Signed-off-by: Mariusz Kozlowski Signed-off-by: Paul Mackerras commit 0d279d47612d1b63155a1d9637a6fc5143dad594 Author: David Gibson Date: Mon Jul 30 15:55:02 2007 +1000 [POWERPC] Fixes to allow use of Ebony's flash chips through physmap_of This patch contains a handful of small fixes to allow the Ebony's flash to be exposed as MTD devices via the physmap_of driver. Specifically it: - Makes a small addition to the device tree and zImage wrapper to record the correct address for the flash in the device tree based on the board switches as reported via an FPGA register. - Prohibits building the old hard-coded "Ebony" flash map on arch/powerpc kernels, in favour of using physmap_of's device tree based approach. - Enables MTD and physmap_of in the Ebony defconfig. Signed-off-by: David Gibson Signed-off-by: Paul Mackerras commit 9420dc65ff9e6b67c032286efde823aeb8684670 Author: Jesper Juhl Date: Mon Jul 30 08:18:25 2007 +1000 [POWERPC] Clean out a bunch of duplicate includes This removes several duplicate includes from arch/powerpc/. Signed-off-by: Jesper Juhl Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras commit 2a4a9fbf26b109a748a336560ae3155c54f89de8 Author: Jon Loeliger Date: Sat Jul 28 04:25:09 2007 +1000 [POWERPC] embedded6xx: Remove unnecessary loops_per_jiffy initialization code Signed-off-by: Jon Loeliger Acked-by: Mark A. Greer Signed-off-by: Paul Mackerras commit c3ca32fdb820d59e63c95115ec5caf2862c85040 Author: Jon Loeliger Date: Sat Jul 28 04:24:59 2007 +1000 [POWERPC] 8xx: Remove unnecessary loops_per_jiffy initialization code Signed-off-by: Jon Loeliger Acked-by: Vitaly Bordug Signed-off-by: Paul Mackerras commit 7888fbf7bbf8840e83078eae3a537fd1cde46e6e Author: Jon Loeliger Date: Sat Jul 28 04:24:52 2007 +1000 [POWERPC] 52xx: Remove unnecessary loops_per_jiffy initialization code Signed-off-by: Jon Loeliger Signed-off-by: Paul Mackerras commit 0b9369f4934eb9933a1fbe991c5e8a4f9725da37 Author: Linas Vepstas Date: Fri Jul 27 08:35:40 2007 +1000 [POWERPC] EEH: Dump PCI bridge status on event Gather bridge-specific data on EEH events. Signed-off-by: Linas Vepstas ---- arch/powerpc/platforms/pseries/eeh.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) Signed-off-by: Paul Mackerras commit 093eda3ce5dc3758c9a5e806ea6573bfffed3ff7 Author: Linas Vepstas Date: Fri Jul 27 08:33:58 2007 +1000 [POWERPC] EEH: Fix PCI bridge handling bug The EEH code needs to ignore PCI bridges; sort-of. It was ignoring them in the wrong place, and thus failing to set up the PCI_DN(dn)->pcidev pointer. Imprudent dereferencing of this pointer would lead to a crash on cards with bridges. Signed-off-by: Linas Vepstas ---- arch/powerpc/platforms/pseries/eeh_cache.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) Signed-off-by: Paul Mackerras commit 12588da7cb57edc25355c8ae2a245f66d0d067d1 Author: Linas Vepstas Date: Fri Jul 27 08:30:26 2007 +1000 [POWERPC] EEH: Tweak printk message Print return code to print message. Also fix whitespace. Signed-off-by: Linas Vepstas ---- arch/powerpc/platforms/pseries/eeh.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) Signed-off-by: Paul Mackerras commit 301d9cb80b4f64ba24d4b141ad3ca58165a29afb Author: Ishizaki Kou Date: Thu Jul 26 20:06:08 2007 +1000 [POWERPC] Init markings for hvc_beat Fix warnings about section mismatch. Signed-off-by: Kou Ishizaki Signed-off-by: Paul Mackerras commit a4ebd0174724193cbabf989352702ff37b1eb060 Author: Ishizaki Kou Date: Thu Jul 26 20:02:27 2007 +1000 [POWERPC] Init markings for celleb There are some variables and functions that we should place in init section. And this patch changes some '__devinit' to '__init', because the device is platform device and not hot-pluggable. Signed-off-by: Kou Ishizaki Signed-off-by: Paul Mackerras commit b090b3388b6ea5d1003260daa0a997f4a1c4acc5 Author: Ishizaki Kou Date: Thu Jul 26 20:00:56 2007 +1000 [POWERPC] Fix celleb sio section warning Fix following warning: WARNING: vmlinux.o(.text+0x45fd4): Section mismatch: reference to .init.text:.early_serial_txx9_setup (between '.txx9_serial_init' and '.txx9_serial_config') Signed-off-by: Kou Ishizaki Signed-off-by: Paul Mackerras commit e5b9187b16993e4bb6799185e266f68e26663bee Author: Ishizaki Kou Date: Thu Jul 26 19:59:17 2007 +1000 [POWERPC] Fix celleb pci section warnings Fix following warnings: WARNING: vmlinux.o(.text+0x44ad0): Section mismatch: reference to .init.text:.__alloc_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') WARNING: vmlinux.o(.text+0x44dd8): Section mismatch: reference to .init.text:.free_bootmem (between '.celleb_setup_phb' and '.celleb_fake_pci_write_config') Signed-off-by: Kou Ishizaki Signed-off-by: Paul Mackerras Signed-off-by: Andrew Morton --- Documentation/powerpc/booting-without-of.txt | 92 MAINTAINERS | 3 arch/powerpc/Kconfig | 11 arch/powerpc/Kconfig.debug | 10 arch/powerpc/Makefile | 19 arch/powerpc/boot/.gitignore | 8 arch/powerpc/boot/44x.c | 85 arch/powerpc/boot/44x.h | 5 arch/powerpc/boot/4xx.c | 300 ++ arch/powerpc/boot/4xx.h | 22 arch/powerpc/boot/Makefile | 13 arch/powerpc/boot/bamboo.c | 47 arch/powerpc/boot/cpm-serial.c | 249 + arch/powerpc/boot/cuboot-83xx.c | 1 arch/powerpc/boot/cuboot-85xx.c | 1 arch/powerpc/boot/cuboot-8xx.c | 45 arch/powerpc/boot/cuboot-bamboo.c | 30 arch/powerpc/boot/cuboot-pq2.c | 283 ++ arch/powerpc/boot/cuboot-sequoia.c | 56 arch/powerpc/boot/cuboot.c | 3 arch/powerpc/boot/dcr.h | 18 arch/powerpc/boot/devtree.c | 80 arch/powerpc/boot/dts/bamboo.dts | 244 + arch/powerpc/boot/dts/ebony.dts | 35 arch/powerpc/boot/dts/holly.dts | 5 arch/powerpc/boot/dts/kuroboxHD.dts | 9 arch/powerpc/boot/dts/kuroboxHG.dts | 9 arch/powerpc/boot/dts/lite5200.dts | 49 arch/powerpc/boot/dts/lite5200b.dts | 59 arch/powerpc/boot/dts/mpc7448hpc2.dts | 4 arch/powerpc/boot/dts/mpc8272ads.dts | 369 +- arch/powerpc/boot/dts/mpc8313erdb.dts | 63 arch/powerpc/boot/dts/mpc832x_mds.dts | 122 arch/powerpc/boot/dts/mpc832x_rdb.dts | 72 arch/powerpc/boot/dts/mpc8349emitx.dts | 98 arch/powerpc/boot/dts/mpc8349emitxgp.dts | 47 arch/powerpc/boot/dts/mpc834x_mds.dts | 243 - arch/powerpc/boot/dts/mpc836x_mds.dts | 123 arch/powerpc/boot/dts/mpc8540ads.dts | 181 - arch/powerpc/boot/dts/mpc8541cds.dts | 196 - arch/powerpc/boot/dts/mpc8544ds.dts | 379 +-- arch/powerpc/boot/dts/mpc8548cds.dts | 406 +-- arch/powerpc/boot/dts/mpc8555cds.dts | 196 - arch/powerpc/boot/dts/mpc8560ads.dts | 185 - arch/powerpc/boot/dts/mpc8568mds.dts | 4 arch/powerpc/boot/dts/mpc8572ds.dts | 404 +++ arch/powerpc/boot/dts/mpc8641_hpcn.dts | 287 +- arch/powerpc/boot/dts/mpc866ads.dts | 5 arch/powerpc/boot/dts/mpc885ads.dts | 5 arch/powerpc/boot/dts/prpmc2800.dts | 5 arch/powerpc/boot/dts/sequoia.dts | 302 ++ arch/powerpc/boot/dts/walnut.dts | 190 + arch/powerpc/boot/ebony.c | 45 arch/powerpc/boot/flatdevtree.c | 100 arch/powerpc/boot/flatdevtree.h | 8 arch/powerpc/boot/flatdevtree_env.h | 20 arch/powerpc/boot/flatdevtree_misc.c | 8 arch/powerpc/boot/holly.c | 5 arch/powerpc/boot/io.h | 49 arch/powerpc/boot/main.c | 10 arch/powerpc/boot/mpsc.c | 1 arch/powerpc/boot/mv64x60_i2c.c | 2 arch/powerpc/boot/of.c | 2 arch/powerpc/boot/ops.h | 33 arch/powerpc/boot/ppcboot.h | 7 arch/powerpc/boot/prpmc2800.c | 6 arch/powerpc/boot/ps3.c | 4 arch/powerpc/boot/serial.c | 19 arch/powerpc/boot/stdlib.c | 45 arch/powerpc/boot/stdlib.h | 6 arch/powerpc/boot/string.S | 24 arch/powerpc/boot/string.h | 2 arch/powerpc/boot/treeboot-bamboo.c | 43 arch/powerpc/boot/treeboot-ebony.c | 2 arch/powerpc/boot/treeboot-walnut.c | 131 + arch/powerpc/configs/bamboo_defconfig | 775 ++++++ arch/powerpc/configs/ebony_defconfig | 85 arch/powerpc/configs/mpc8544_ds_defconfig | 2 arch/powerpc/configs/mpc8572_ds_defconfig | 1496 ++++++++++++ arch/powerpc/configs/sequoia_defconfig | 861 ++++++ arch/powerpc/configs/walnut_defconfig | 773 ++++++ arch/powerpc/kernel/Makefile | 9 arch/powerpc/kernel/align.c | 307 ++ arch/powerpc/kernel/asm-offsets.c | 12 arch/powerpc/kernel/btext.c | 1 arch/powerpc/kernel/cputable.c | 41 arch/powerpc/kernel/crash.c | 1 arch/powerpc/kernel/crash_dump.c | 4 arch/powerpc/kernel/entry_32.S | 4 arch/powerpc/kernel/entry_64.S | 8 arch/powerpc/kernel/head_32.S | 37 arch/powerpc/kernel/head_40x.S | 1013 ++++++++ arch/powerpc/kernel/head_44x.S | 16 arch/powerpc/kernel/head_4xx.S | 1021 -------- arch/powerpc/kernel/head_64.S | 602 ---- arch/powerpc/kernel/head_8xx.S | 17 arch/powerpc/kernel/head_fsl_booke.S | 14 arch/powerpc/kernel/ibmebus.c | 3 arch/powerpc/kernel/iomap.c | 4 arch/powerpc/kernel/iommu.c | 1 arch/powerpc/kernel/irq.c | 89 arch/powerpc/kernel/lparmap.c | 32 arch/powerpc/kernel/nvram_64.c | 23 arch/powerpc/kernel/pci_32.c | 4 arch/powerpc/kernel/pci_dn.c | 7 arch/powerpc/kernel/ppc_ksyms.c | 2 arch/powerpc/kernel/process.c | 15 arch/powerpc/kernel/prom.c | 23 arch/powerpc/kernel/prom_init.c | 23 arch/powerpc/kernel/ptrace.c | 6 arch/powerpc/kernel/rtas_pci.c | 4 arch/powerpc/kernel/setup-common.c | 2 arch/powerpc/kernel/setup_32.c | 2 arch/powerpc/kernel/setup_64.c | 6 arch/powerpc/kernel/sysfs.c | 64 arch/powerpc/kernel/time.c | 3 arch/powerpc/kernel/traps.c | 15 arch/powerpc/kernel/udbg_16550.c | 11 arch/powerpc/kernel/vmlinux.lds.S | 2 arch/powerpc/lib/Makefile | 2 arch/powerpc/lib/alloc.c | 14 arch/powerpc/mm/40x_mmu.c | 135 + arch/powerpc/mm/4xx_mmu.c | 135 - arch/powerpc/mm/Makefile | 2 arch/powerpc/mm/hash_utils_64.c | 7 arch/powerpc/mm/hugetlbpage.c | 3 arch/powerpc/mm/init_32.c | 1 arch/powerpc/mm/mem.c | 1 arch/powerpc/mm/mmu_context_64.c | 11 arch/powerpc/mm/pgtable_64.c | 2 arch/powerpc/mm/slb.c | 6 arch/powerpc/mm/slice.c | 1 arch/powerpc/platforms/40x/Kconfig | 131 + arch/powerpc/platforms/40x/Makefile | 1 arch/powerpc/platforms/40x/walnut.c | 68 arch/powerpc/platforms/44x/Kconfig | 32 arch/powerpc/platforms/44x/Makefile | 2 arch/powerpc/platforms/44x/bamboo.c | 66 arch/powerpc/platforms/44x/sequoia.c | 66 arch/powerpc/platforms/4xx/Kconfig | 208 - arch/powerpc/platforms/4xx/Makefile | 1 arch/powerpc/platforms/52xx/Makefile | 3 arch/powerpc/platforms/52xx/efika.c | 4 arch/powerpc/platforms/52xx/lite5200.c | 28 arch/powerpc/platforms/52xx/lite5200_pm.c | 213 + arch/powerpc/platforms/52xx/lite5200_sleep.S | 412 +++ arch/powerpc/platforms/52xx/mpc52xx_pic.c | 11 arch/powerpc/platforms/82xx/m82xx_pci.h | 2 arch/powerpc/platforms/82xx/mpc82xx.c | 1 arch/powerpc/platforms/82xx/mpc82xx_ads.c | 12 arch/powerpc/platforms/82xx/pq2ads.h | 1 arch/powerpc/platforms/83xx/mpc8313_rdb.c | 2 arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 arch/powerpc/platforms/83xx/mpc832x_rdb.c | 48 arch/powerpc/platforms/83xx/mpc834x_itx.c | 3 arch/powerpc/platforms/83xx/mpc834x_mds.c | 3 arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 arch/powerpc/platforms/83xx/mpc83xx.h | 2 arch/powerpc/platforms/83xx/pci.c | 7 arch/powerpc/platforms/85xx/Kconfig | 8 arch/powerpc/platforms/85xx/Makefile | 2 arch/powerpc/platforms/85xx/mpc8544_ds.c | 188 - arch/powerpc/platforms/85xx/mpc85xx_ads.c | 13 arch/powerpc/platforms/85xx/mpc85xx_cds.c | 14 arch/powerpc/platforms/85xx/mpc85xx_ds.c | 227 + arch/powerpc/platforms/85xx/mpc85xx_mds.c | 12 arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 14 arch/powerpc/platforms/8xx/m8xx_setup.c | 78 arch/powerpc/platforms/8xx/mpc86xads.h | 1 arch/powerpc/platforms/8xx/mpc86xads_setup.c | 15 arch/powerpc/platforms/8xx/mpc885ads.h | 1 arch/powerpc/platforms/8xx/mpc885ads_setup.c | 15 arch/powerpc/platforms/Kconfig | 13 arch/powerpc/platforms/Kconfig.cputype | 2 arch/powerpc/platforms/Makefile | 2 arch/powerpc/platforms/cell/Makefile | 4 arch/powerpc/platforms/cell/axon_msi.c | 18 arch/powerpc/platforms/cell/interrupt.c | 2 arch/powerpc/platforms/cell/spider-pic.c | 22 arch/powerpc/platforms/cell/spu_base.c | 2 arch/powerpc/platforms/cell/spu_callbacks.c | 4 arch/powerpc/platforms/cell/spu_coredump.c | 79 arch/powerpc/platforms/cell/spu_syscalls.c | 144 - arch/powerpc/platforms/cell/spufs/coredump.c | 236 - arch/powerpc/platforms/cell/spufs/file.c | 251 -- arch/powerpc/platforms/cell/spufs/inode.c | 15 arch/powerpc/platforms/cell/spufs/run.c | 4 arch/powerpc/platforms/cell/spufs/sched.c | 49 arch/powerpc/platforms/cell/spufs/spufs.h | 7 arch/powerpc/platforms/cell/spufs/switch.c | 29 arch/powerpc/platforms/cell/spufs/syscalls.c | 48 arch/powerpc/platforms/celleb/interrupt.c | 9 arch/powerpc/platforms/celleb/pci.c | 35 arch/powerpc/platforms/celleb/scc_epci.c | 8 arch/powerpc/platforms/celleb/scc_sio.c | 8 arch/powerpc/platforms/celleb/setup.c | 4 arch/powerpc/platforms/chrp/gg2.h | 61 arch/powerpc/platforms/chrp/pci.c | 39 arch/powerpc/platforms/chrp/setup.c | 3 arch/powerpc/platforms/chrp/smp.c | 2 arch/powerpc/platforms/embedded6xx/holly.c | 14 arch/powerpc/platforms/embedded6xx/linkstation.c | 6 arch/powerpc/platforms/embedded6xx/ls_uart.c | 18 arch/powerpc/platforms/embedded6xx/mpc10x.h | 180 + arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | 3 arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.h | 21 arch/powerpc/platforms/embedded6xx/prpmc2800.c | 7 arch/powerpc/platforms/iseries/Makefile | 1 arch/powerpc/platforms/iseries/exception.S | 251 ++ arch/powerpc/platforms/iseries/exception.h | 58 arch/powerpc/platforms/iseries/irq.c | 10 arch/powerpc/platforms/iseries/it_lp_naca.h | 2 arch/powerpc/platforms/iseries/setup.c | 1 arch/powerpc/platforms/maple/pci.c | 21 arch/powerpc/platforms/pasemi/Kconfig | 1 arch/powerpc/platforms/pasemi/idle.c | 8 arch/powerpc/platforms/pasemi/iommu.c | 4 arch/powerpc/platforms/pasemi/pasemi.h | 4 arch/powerpc/platforms/pasemi/pci.c | 74 arch/powerpc/platforms/pasemi/setup.c | 134 - arch/powerpc/platforms/powermac/bootx_init.c | 1 arch/powerpc/platforms/powermac/low_i2c.c | 1 arch/powerpc/platforms/powermac/pci.c | 25 arch/powerpc/platforms/powermac/pic.c | 2 arch/powerpc/platforms/powermac/pmac.h | 4 arch/powerpc/platforms/powermac/udbg_adb.c | 5 arch/powerpc/platforms/ps3/device-init.c | 24 arch/powerpc/platforms/ps3/interrupt.c | 9 arch/powerpc/platforms/ps3/platform.h | 4 arch/powerpc/platforms/pseries/eeh.c | 52 arch/powerpc/platforms/pseries/eeh_cache.c | 9 arch/powerpc/platforms/pseries/lpar.c | 1 arch/powerpc/platforms/pseries/rtasd.c | 96 arch/powerpc/platforms/pseries/xics.c | 2 arch/powerpc/sysdev/commproc.c | 32 arch/powerpc/sysdev/cpm2_common.c | 2 arch/powerpc/sysdev/cpm2_pic.c | 11 arch/powerpc/sysdev/dart_iommu.c | 4 arch/powerpc/sysdev/dcr.c | 4 arch/powerpc/sysdev/fsl_pci.c | 2 arch/powerpc/sysdev/fsl_soc.c | 127 - arch/powerpc/sysdev/fsl_soc.h | 7 arch/powerpc/sysdev/i8259.c | 8 arch/powerpc/sysdev/indirect_pci.c | 4 arch/powerpc/sysdev/ipic.c | 7 arch/powerpc/sysdev/ipic.h | 3 arch/powerpc/sysdev/mpc8xx_pic.c | 23 arch/powerpc/sysdev/mpic.c | 25 arch/powerpc/sysdev/mpic_msi.c | 13 arch/powerpc/sysdev/mv64x60_pic.c | 12 arch/powerpc/sysdev/qe_lib/qe_ic.c | 7 arch/powerpc/sysdev/qe_lib/qe_ic.h | 3 arch/powerpc/sysdev/tsi108_pci.c | 16 arch/powerpc/sysdev/uic.c | 77 arch/ppc/.gitignore | 2 arch/ppc/Kconfig | 148 - arch/ppc/Makefile | 1 arch/ppc/amiga/Makefile | 8 arch/ppc/amiga/amiga_ksyms.c | 1 arch/ppc/amiga/amiints.c | 322 -- arch/ppc/amiga/amisound.c | 1 arch/ppc/amiga/bootinfo.c | 78 arch/ppc/amiga/chipram.c | 1 arch/ppc/amiga/cia.c | 176 - arch/ppc/amiga/config.c | 953 ------- arch/ppc/amiga/ints.c | 158 - arch/ppc/amiga/pcmcia.c | 1 arch/ppc/amiga/time.c | 57 arch/ppc/configs/apus_defconfig | 920 ------- arch/ppc/kernel/head.S | 117 arch/ppc/kernel/ppc_ksyms.c | 3 arch/ppc/kernel/setup.c | 1 arch/ppc/mm/pgtable.c | 38 arch/ppc/platforms/Makefile | 4 arch/ppc/platforms/apus_pci.c | 207 - arch/ppc/platforms/apus_pci.h | 34 arch/ppc/platforms/apus_setup.c | 798 ------ drivers/char/hvc_beat.c | 4 drivers/char/ipmi/ipmi_si_intf.c | 6 drivers/macintosh/adb-iop.c | 1 drivers/macintosh/ans-lcd.c | 3 drivers/macintosh/ans-lcd.h | 11 drivers/macintosh/therm_adt746x.c | 5 drivers/macintosh/via-pmu.c | 2 drivers/macintosh/windfarm_smu_sat.c | 2 drivers/mtd/maps/Kconfig | 2 drivers/mtd/maps/physmap_of.c | 345 +- drivers/net/ucc_geth_mii.c | 1 drivers/serial/mpc52xx_uart.c | 2 drivers/serial/pmac_zilog.c | 2 fs/binfmt_elf.c | 14 include/asm-powerpc/8xx_immap.h | 564 ++++ include/asm-powerpc/atomic.h | 34 include/asm-powerpc/commproc.h | 692 +++++ include/asm-powerpc/cpm2.h | 1248 ++++++++++ include/asm-powerpc/cputable.h | 26 include/asm-powerpc/dma-mapping.h | 24 include/asm-powerpc/elf.h | 9 include/asm-powerpc/exception.h | 311 ++ include/asm-powerpc/highmem.h | 135 + include/asm-powerpc/hydra.h | 102 include/asm-powerpc/ide.h | 2 include/asm-powerpc/immap_86xx.h | 151 - include/asm-powerpc/immap_cpm2.h | 648 +++++ include/asm-powerpc/io.h | 26 include/asm-powerpc/irq.h | 8 include/asm-powerpc/iseries/lpar_map.h | 3 include/asm-powerpc/kgdb.h | 57 include/asm-powerpc/lmb.h | 6 include/asm-powerpc/mmu-40x.h | 65 include/asm-powerpc/mmu.h | 3 include/asm-powerpc/mpc52xx.h | 10 include/asm-powerpc/mpc52xx_psc.h | 191 + include/asm-powerpc/mpic.h | 7 include/asm-powerpc/nvram.h | 6 include/asm-powerpc/page_64.h | 9 include/asm-powerpc/pgtable-4k.h | 2 include/asm-powerpc/pgtable-64k.h | 2 include/asm-powerpc/ppc_asm.h | 18 include/asm-powerpc/prom.h | 3 include/asm-powerpc/ps3.h | 9 include/asm-powerpc/qe.h | 3 include/asm-powerpc/reg.h | 52 include/asm-powerpc/spu.h | 28 include/asm-powerpc/system.h | 2 include/asm-powerpc/time.h | 2 include/asm-ppc/amigahw.h | 16 include/asm-ppc/amigaints.h | 133 - include/asm-ppc/amigappc.h | 85 include/asm-ppc/ans-lcd.h | 11 include/asm-ppc/bootinfo.h | 5 include/asm-ppc/io.h | 51 include/asm-ppc/machdep.h | 4 include/asm-ppc/page.h | 44 include/asm-ppc/pgtable.h | 8 include/asm-ppc/prom.h | 1 include/linux/elf.h | 14 include/linux/of.h | 1 include/linux/pci_ids.h | 2 339 files changed, 17627 insertions(+), 10103 deletions(-) diff -puN Documentation/powerpc/booting-without-of.txt~git-powerpc Documentation/powerpc/booting-without-of.txt --- a/Documentation/powerpc/booting-without-of.txt~git-powerpc +++ a/Documentation/powerpc/booting-without-of.txt @@ -50,7 +50,7 @@ Table of Contents g) Freescale SOC SEC Security Engines h) Board Control and Status (BCSR) i) Freescale QUICC Engine module (QE) - j) Flash chip nodes + j) CFI or JEDEC memory-mapped NOR flash k) Global Utilities Block VII - Specifying interrupt information for devices @@ -1757,45 +1757,69 @@ platforms are moved over to use the flat }; }; - j) Flash chip nodes + j) CFI or JEDEC memory-mapped NOR flash Flash chips (Memory Technology Devices) are often used for solid state file systems on embedded devices. - Required properties: + - compatible : should contain the specific model of flash chip(s) + used, if known, followed by either "cfi-flash" or "jedec-flash" + - reg : Address range of the flash chip + - bank-width : Width (in bytes) of the flash bank. Equal to the + device width times the number of interleaved chips. + - device-width : (optional) Width of a single flash chip. If + omitted, assumed to be equal to 'bank-width'. + - #address-cells, #size-cells : Must be present if the flash has + sub-nodes representing partitions (see below). In this case + both #address-cells and #size-cells must be equal to 1. + + For JEDEC compatible devices, the following additional properties + are defined: + + - vendor-id : Contains the flash chip's vendor id (1 byte). + - device-id : Contains the flash chip's device id (1 byte). + + In addition to the information on the flash bank itself, the + device tree may optionally contain additional information + describing partitions of the flash address space. This can be + used on platforms which have strong conventions about which + portions of the flash are used for what purposes, but which don't + use an on-flash partition table such as RedBoot. + + Each partition is represented as a sub-node of the flash device. + Each node's name represents the name of the corresponding + partition of the flash device. + + Flash partitions + - reg : The partition's offset and size within the flash bank. + - label : (optional) The label / name for this flash partition. + If omitted, the label is taken from the node name (excluding + the unit address). + - read-only : (optional) This parameter, if present, is a hint to + Linux that this flash partition should only be mounted + read-only. This is usually used for flash partitions + containing early-boot firmware images or data which should not + be clobbered. - - device_type : has to be "rom" - - compatible : Should specify what this flash device is compatible with. - Currently, this is most likely to be "direct-mapped" (which - corresponds to the MTD physmap mapping driver). - - reg : Offset and length of the register set (or memory mapping) for - the device. - - bank-width : Width of the flash data bus in bytes. Required - for the NOR flashes (compatible == "direct-mapped" and others) ONLY. - - Recommended properties : - - - partitions : Several pairs of 32-bit values where the first value is - partition's offset from the start of the device and the second one is - partition size in bytes with LSB used to signify a read only - partition (so, the partition size should always be an even number). - - partition-names : The list of concatenated zero terminated strings - representing the partition names. - - probe-type : The type of probe which should be done for the chip - (JEDEC vs CFI actually). Valid ONLY for NOR flashes. - - Example: + Example: - flash@ff000000 { - device_type = "rom"; - compatible = "direct-mapped"; - probe-type = "CFI"; - reg = ; - bank-width = <4>; - partitions = <00000000 00f80000 - 00f80000 00080001>; - partition-names = "fs\0firmware"; - }; + flash@ff000000 { + compatible = "amd,am29lv128ml", "cfi-flash"; + reg = ; + bank-width = <4>; + device-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + fs@0 { + label = "fs"; + reg = <0 f80000>; + }; + firmware@f80000 { + label ="firmware"; + reg = ; + read-only; + }; + }; k) Global Utilities Block diff -puN MAINTAINERS~git-powerpc MAINTAINERS --- a/MAINTAINERS~git-powerpc +++ a/MAINTAINERS @@ -2295,10 +2295,13 @@ L: linuxppc-embedded@ozlabs.org S: Maintained LINUX FOR POWERPC EMBEDDED PPC4XX +P: Josh Boyer +M: jwboyer@linux.vnet.ibm.com P: Matt Porter M: mporter@kernel.crashing.org W: http://www.penguinppc.org/ L: linuxppc-embedded@ozlabs.org +T: git kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc.git S: Maintained LINUX FOR POWERPC BOOT CODE diff -puN arch/powerpc/Kconfig~git-powerpc arch/powerpc/Kconfig --- a/arch/powerpc/Kconfig~git-powerpc +++ a/arch/powerpc/Kconfig @@ -181,16 +181,17 @@ config MATH_EMULATION instructions to run. config IOMMU_VMERGE - bool "Enable IOMMU virtual merging (EXPERIMENTAL)" - depends on EXPERIMENTAL && PPC64 - default n + bool "Enable IOMMU virtual merging" + depends on PPC64 + default y help Cause IO segments sent to a device for DMA to be merged virtually by the IOMMU when they happen to have been allocated contiguously. This doesn't add pressure to the IOMMU allocator. However, some drivers don't support getting large merged segments coming back - from *_map_sg(). Say Y if you know the drivers you are using are - properly handling this case. + from *_map_sg(). + + Most drivers don't have this problem; it is safe to say Y here. config HOTPLUG_CPU bool "Support for enabling/disabling CPUs" diff -puN arch/powerpc/Kconfig.debug~git-powerpc arch/powerpc/Kconfig.debug --- a/arch/powerpc/Kconfig.debug~git-powerpc +++ a/arch/powerpc/Kconfig.debug @@ -124,6 +124,16 @@ config IRQSTACKS for handling hard and soft interrupts. This can help avoid overflowing the process kernel stacks. +config VIRQ_DEBUG + bool "Expose hardware/virtual IRQ mapping via debugfs" + depends on DEBUG_FS && PPC_MERGE + help + This option will show the mapping relationship between hardware irq + numbers and virtual irq numbers. The mapping is exposed via debugfs + in the file powerpc/virq_mapping. + + If you don't know what this means you don't need it. + config BDI_SWITCH bool "Include BDI-2000 user context switcher" depends on DEBUG_KERNEL && PPC32 diff -puN arch/powerpc/Makefile~git-powerpc arch/powerpc/Makefile --- a/arch/powerpc/Makefile~git-powerpc +++ a/arch/powerpc/Makefile @@ -63,8 +63,7 @@ endif LDFLAGS_vmlinux := -Bstatic -# The -Iarch/$(ARCH)/include is temporary while we are merging -CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -Iarch/$(ARCH)/include +CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) AFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc CFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -ffixed-r2 -mmultiple @@ -72,9 +71,6 @@ CPPFLAGS += $(CPPFLAGS-y) AFLAGS += $(AFLAGS-y) CFLAGS += -msoft-float -pipe $(CFLAGS-y) CPP = $(CC) -E $(CFLAGS) -# Temporary hack until we have migrated to asm-powerpc -LINUXINCLUDE-$(CONFIG_PPC32) := -Iarch/$(ARCH)/include -LINUXINCLUDE += $(LINUXINCLUDE-y) CHECKFLAGS += -m$(SZ) -D__powerpc__ -D__powerpc$(SZ)__ @@ -123,7 +119,7 @@ CFLAGS += $(cpu-as-y) head-y := arch/powerpc/kernel/head_32.o head-$(CONFIG_PPC64) := arch/powerpc/kernel/head_64.o head-$(CONFIG_8xx) := arch/powerpc/kernel/head_8xx.o -head-$(CONFIG_4xx) := arch/powerpc/kernel/head_4xx.o +head-$(CONFIG_40x) := arch/powerpc/kernel/head_40x.o head-$(CONFIG_44x) := arch/powerpc/kernel/head_44x.o head-$(CONFIG_FSL_BOOKE) := arch/powerpc/kernel/head_fsl_booke.o @@ -172,19 +168,8 @@ install: archclean: $(Q)$(MAKE) $(clean)=$(boot) -archmrproper: - $(Q)rm -rf arch/$(ARCH)/include - archprepare: checkbin -ifeq ($(CONFIG_PPC32),y) -# Temporary hack until we have migrated to asm-powerpc -include/asm: arch/$(ARCH)/include/asm -arch/$(ARCH)/include/asm: FORCE - $(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi - $(Q)ln -fsn $(srctree)/include/asm-$(OLDARCH) arch/$(ARCH)/include/asm -endif - # Use the file '.tmp_gas_check' for binutils tests, as gas won't output # to stdout and these checks are run even on install targets. TOUT := .tmp_gas_check diff -puN arch/powerpc/boot/.gitignore~git-powerpc arch/powerpc/boot/.gitignore --- a/arch/powerpc/boot/.gitignore~git-powerpc +++ a/arch/powerpc/boot/.gitignore @@ -18,14 +18,14 @@ kernel-vmlinux.strip.c kernel-vmlinux.strip.gz mktree uImage -cuImage -cuImage.bin.gz -cuImage.elf +cuImage.* zImage +zImage.bin.* zImage.chrp zImage.coff zImage.coff.lds -zImage.lds +zImage.ep* +zImage.*lds zImage.miboot zImage.pmac zImage.pseries diff -puN arch/powerpc/boot/44x.c~git-powerpc /dev/null --- a/arch/powerpc/boot/44x.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2007 David Gibson, IBM Corporation. - * - * Based on earlier code: - * Matt Porter - * Copyright 2002-2005 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include "types.h" -#include "string.h" -#include "stdio.h" -#include "ops.h" -#include "reg.h" -#include "dcr.h" - -/* Read the 44x memory controller to get size of system memory. */ -void ibm44x_fixup_memsize(void) -{ - int i; - unsigned long memsize, bank_config; - - memsize = 0; - for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { - mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]); - bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); - - if (bank_config & SDRAM_CONFIG_BANK_ENABLE) - memsize += SDRAM_CONFIG_BANK_SIZE(bank_config); - } - - dt_fixup_memory(0, memsize); -} - -#define SPRN_DBCR0 0x134 -#define DBCR0_RST_SYSTEM 0x30000000 - -void ibm44x_dbcr_reset(void) -{ - unsigned long tmp; - - asm volatile ( - "mfspr %0,%1\n" - "oris %0,%0,%2@h\n" - "mtspr %1,%0" - : "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM) - ); - -} - -/* Read 4xx EBC bus bridge registers to get mappings of the peripheral - * banks into the OPB address space */ -void ibm4xx_fixup_ebc_ranges(const char *ebc) -{ - void *devp; - u32 bxcr; - u32 ranges[EBC_NUM_BANKS*4]; - u32 *p = ranges; - int i; - - for (i = 0; i < EBC_NUM_BANKS; i++) { - mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); - bxcr = mfdcr(DCRN_EBC0_CFGDATA); - - if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) { - *p++ = i; - *p++ = 0; - *p++ = bxcr & EBC_BXCR_BAS; - *p++ = EBC_BXCR_BANK_SIZE(bxcr); - } - } - - devp = finddevice(ebc); - if (! devp) - fatal("Couldn't locate EBC node %s\n\r", ebc); - - setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32)); -} diff -puN arch/powerpc/boot/44x.h~git-powerpc arch/powerpc/boot/44x.h --- a/arch/powerpc/boot/44x.h~git-powerpc +++ a/arch/powerpc/boot/44x.h @@ -10,10 +10,7 @@ #ifndef _PPC_BOOT_44X_H_ #define _PPC_BOOT_44X_H_ -void ibm44x_fixup_memsize(void); -void ibm4xx_fixup_ebc_ranges(const char *ebc); - -void ibm44x_dbcr_reset(void); void ebony_init(void *mac0, void *mac1); +void bamboo_init(void *mac0, void *mac1); #endif /* _PPC_BOOT_44X_H_ */ diff -puN /dev/null arch/powerpc/boot/4xx.c --- /dev/null +++ a/arch/powerpc/boot/4xx.c @@ -0,0 +1,300 @@ +/* + * Copyright 2007 David Gibson, IBM Corporation. + * + * Based on earlier code: + * Matt Porter + * Copyright 2002-2005 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003, 2004 Zultys Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include "types.h" +#include "string.h" +#include "stdio.h" +#include "ops.h" +#include "reg.h" +#include "dcr.h" + +/* Read the 4xx SDRAM controller to get size of system memory. */ +void ibm4xx_fixup_memsize(void) +{ + int i; + unsigned long memsize, bank_config; + + memsize = 0; + for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { + mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]); + bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); + + if (bank_config & SDRAM_CONFIG_BANK_ENABLE) + memsize += SDRAM_CONFIG_BANK_SIZE(bank_config); + } + + dt_fixup_memory(0, memsize); +} + +/* 4xx DDR1/2 Denali memory controller support */ +/* DDR0 registers */ +#define DDR0_02 2 +#define DDR0_08 8 +#define DDR0_10 10 +#define DDR0_14 14 +#define DDR0_42 42 +#define DDR0_43 43 + +/* DDR0_02 */ +#define DDR_START 0x1 +#define DDR_START_SHIFT 0 +#define DDR_MAX_CS_REG 0x3 +#define DDR_MAX_CS_REG_SHIFT 24 +#define DDR_MAX_COL_REG 0xf +#define DDR_MAX_COL_REG_SHIFT 16 +#define DDR_MAX_ROW_REG 0xf +#define DDR_MAX_ROW_REG_SHIFT 8 +/* DDR0_08 */ +#define DDR_DDR2_MODE 0x1 +#define DDR_DDR2_MODE_SHIFT 0 +/* DDR0_10 */ +#define DDR_CS_MAP 0x3 +#define DDR_CS_MAP_SHIFT 8 +/* DDR0_14 */ +#define DDR_REDUC 0x1 +#define DDR_REDUC_SHIFT 16 +/* DDR0_42 */ +#define DDR_APIN 0x7 +#define DDR_APIN_SHIFT 24 +/* DDR0_43 */ +#define DDR_COL_SZ 0x7 +#define DDR_COL_SZ_SHIFT 8 +#define DDR_BANK8 0x1 +#define DDR_BANK8_SHIFT 0 + +#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) + +static inline u32 mfdcr_sdram0(u32 reg) +{ + mtdcr(DCRN_SDRAM0_CFGADDR, reg); + return mfdcr(DCRN_SDRAM0_CFGDATA); +} + +void ibm4xx_denali_fixup_memsize(void) +{ + u32 val, max_cs, max_col, max_row; + u32 cs, col, row, bank, dpath; + unsigned long memsize; + + val = mfdcr_sdram0(DDR0_02); + if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) + fatal("DDR controller is not initialized\n"); + + /* get maximum cs col and row values */ + max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); + max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); + max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); + + /* get CS value */ + val = mfdcr_sdram0(DDR0_10); + + val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); + cs = 0; + while (val) { + if (val && 0x1) + cs++; + val = val >> 1; + } + + if (!cs) + fatal("No memory installed\n"); + if (cs > max_cs) + fatal("DDR wrong CS configuration\n"); + + /* get data path bytes */ + val = mfdcr_sdram0(DDR0_14); + + if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) + dpath = 8; /* 64 bits */ + else + dpath = 4; /* 32 bits */ + + /* get adress pins (rows) */ + val = mfdcr_sdram0(DDR0_42); + + row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT); + if (row > max_row) + fatal("DDR wrong APIN configuration\n"); + row = max_row - row; + + /* get collomn size and banks */ + val = mfdcr_sdram0(DDR0_43); + + col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT); + if (col > max_col) + fatal("DDR wrong COL configuration\n"); + col = max_col - col; + + if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT)) + bank = 8; /* 8 banks */ + else + bank = 4; /* 4 banks */ + + memsize = cs * (1 << (col+row)) * bank * dpath; + dt_fixup_memory(0, memsize); +} + +#define SPRN_DBCR0_40X 0x3F2 +#define SPRN_DBCR0_44X 0x134 +#define DBCR0_RST_SYSTEM 0x30000000 + +void ibm44x_dbcr_reset(void) +{ + unsigned long tmp; + + asm volatile ( + "mfspr %0,%1\n" + "oris %0,%0,%2@h\n" + "mtspr %1,%0" + : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM) + ); + +} + +void ibm40x_dbcr_reset(void) +{ + unsigned long tmp; + + asm volatile ( + "mfspr %0,%1\n" + "oris %0,%0,%2@h\n" + "mtspr %1,%0" + : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM) + ); +} + +#define EMAC_RESET 0x20000000 +void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) +{ + /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */ + if (emac0) + *emac0 = EMAC_RESET; + if (emac1) + *emac1 = EMAC_RESET; + + mtdcr(DCRN_MAL0_CFG, MAL_RESET); +} + +/* Read 4xx EBC bus bridge registers to get mappings of the peripheral + * banks into the OPB address space */ +void ibm4xx_fixup_ebc_ranges(const char *ebc) +{ + void *devp; + u32 bxcr; + u32 ranges[EBC_NUM_BANKS*4]; + u32 *p = ranges; + int i; + + for (i = 0; i < EBC_NUM_BANKS; i++) { + mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); + bxcr = mfdcr(DCRN_EBC0_CFGDATA); + + if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) { + *p++ = i; + *p++ = 0; + *p++ = bxcr & EBC_BXCR_BAS; + *p++ = EBC_BXCR_BANK_SIZE(bxcr); + } + } + + devp = finddevice(ebc); + if (! devp) + fatal("Couldn't locate EBC node %s\n\r", ebc); + + setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32)); +} + +#define SPRN_CCR1 0x378 +void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) +{ + u32 cpu, plb, opb, ebc, tb, uart0, m, vco; + u32 reg; + u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp; + + mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0); + reg = mfdcr(DCRN_CPR0_DATA); + tmp = (reg & 0x000F0000) >> 16; + fwdva = tmp ? tmp : 16; + tmp = (reg & 0x00000700) >> 8; + fwdvb = tmp ? tmp : 8; + tmp = (reg & 0x1F000000) >> 24; + fbdv = tmp ? tmp : 32; + lfbdv = (reg & 0x0000007F); + + mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0); + reg = mfdcr(DCRN_CPR0_DATA); + tmp = (reg & 0x03000000) >> 24; + opbdv0 = tmp ? tmp : 4; + + mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0); + reg = mfdcr(DCRN_CPR0_DATA); + tmp = (reg & 0x07000000) >> 24; + perdv0 = tmp ? tmp : 8; + + mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0); + reg = mfdcr(DCRN_CPR0_DATA); + tmp = (reg & 0x07000000) >> 24; + prbdv0 = tmp ? tmp : 8; + + mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID); + reg = mfdcr(DCRN_CPR0_DATA); + tmp = (reg & 0x03000000) >> 24; + spcid0 = tmp ? tmp : 4; + + /* Calculate M */ + mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0); + reg = mfdcr(DCRN_CPR0_DATA); + tmp = (reg & 0x03000000) >> 24; + if (tmp == 0) { /* PLL output */ + tmp = (reg & 0x20000000) >> 29; + if (!tmp) /* PLLOUTA */ + m = fbdv * lfbdv * fwdva; + else + m = fbdv * lfbdv * fwdvb; + } + else if (tmp == 1) /* CPU output */ + m = fbdv * fwdva; + else + m = perdv0 * opbdv0 * fwdvb; + + vco = (m * sysclk) + (m >> 1); + cpu = vco / fwdva; + plb = vco / fwdvb / prbdv0; + opb = plb / opbdv0; + ebc = plb / perdv0; + + /* FIXME */ + uart0 = ser_clk; + + /* Figure out timebase. Either CPU or default TmrClk */ + asm volatile ( + "mfspr %0,%1\n" + : + "=&r"(reg) : "i"(SPRN_CCR1)); + if (reg & 0x0080) + tb = 25000000; /* TmrClk is 25MHz */ + else + tb = cpu; + + dt_fixup_cpu_clocks(cpu, tb, 0); + dt_fixup_clock("/plb", plb); + dt_fixup_clock("/plb/opb", opb); + dt_fixup_clock("/plb/opb/ebc", ebc); + dt_fixup_clock("/plb/opb/serial@ef600300", uart0); + dt_fixup_clock("/plb/opb/serial@ef600400", uart0); + dt_fixup_clock("/plb/opb/serial@ef600500", uart0); + dt_fixup_clock("/plb/opb/serial@ef600600", uart0); +} diff -puN /dev/null arch/powerpc/boot/4xx.h --- /dev/null +++ a/arch/powerpc/boot/4xx.h @@ -0,0 +1,22 @@ +/* + * PowerPC 4xx related functions + * + * Copyright 2007 IBM Corporation. + * Josh Boyer + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#ifndef _POWERPC_BOOT_4XX_H_ +#define _POWERPC_BOOT_4XX_H_ + +void ibm4xx_fixup_memsize(void); +void ibm4xx_denali_fixup_memsize(void); +void ibm44x_dbcr_reset(void); +void ibm40x_dbcr_reset(void); +void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1); +void ibm4xx_fixup_ebc_ranges(const char *ebc); +void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk); + +#endif /* _POWERPC_BOOT_4XX_H_ */ diff -puN arch/powerpc/boot/Makefile~git-powerpc arch/powerpc/boot/Makefile --- a/arch/powerpc/boot/Makefile~git-powerpc +++ a/arch/powerpc/boot/Makefile @@ -31,7 +31,7 @@ endif BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -$(obj)/44x.o: BOOTCFLAGS += -mcpu=440 +$(obj)/4xx.o: BOOTCFLAGS += -mcpu=440 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=440 zlib := inffast.c inflate.c inftrees.c @@ -44,10 +44,12 @@ $(addprefix $(obj)/,$(zlib) gunzip_util. src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \ ns16550.c serial.c simple_alloc.c div64.S util.S \ gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \ - 44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c + 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \ + cpm-serial.c stdlib.c src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \ cuboot-ebony.c treeboot-ebony.c prpmc2800.c \ - ps3-head.S ps3-hvcall.S ps3.c + ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ + cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -139,9 +141,14 @@ image-$(CONFIG_PPC_ISERIES) += zImage.i image-$(CONFIG_DEFAULT_UIMAGE) += uImage ifneq ($(CONFIG_DEVICE_TREE),"") +image-$(CONFIG_PPC_8xx) += cuImage.8xx +image-$(CONFIG_8260) += cuImage.pq2 image-$(CONFIG_PPC_83xx) += cuImage.83xx image-$(CONFIG_PPC_85xx) += cuImage.85xx image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony +image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo +image-$(CONFIG_SEQUOIA) += cuImage.sequoia +image-$(CONFIG_WALNUT) += treeImage.walnut endif # For 32-bit powermacs, build the COFF and miboot images diff -puN /dev/null arch/powerpc/boot/bamboo.c --- /dev/null +++ a/arch/powerpc/boot/bamboo.c @@ -0,0 +1,47 @@ +/* + * Copyright IBM Corporation, 2007 + * Josh Boyer + * + * Based on ebony wrapper: + * Copyright 2007 David Gibson, IBM Corporation. + * + * Clocking code based on code by: + * Stefan Roese + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 of the License + */ +#include +#include +#include "types.h" +#include "elf.h" +#include "string.h" +#include "stdio.h" +#include "page.h" +#include "ops.h" +#include "dcr.h" +#include "4xx.h" +#include "44x.h" + +static u8 *bamboo_mac0, *bamboo_mac1; + +static void bamboo_fixups(void) +{ + unsigned long sysclk = 33333333; + + ibm440ep_fixup_clocks(sysclk, 11059200); + ibm4xx_fixup_memsize(); + ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00); + dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1); +} + +void bamboo_init(void *mac0, void *mac1) +{ + platform_ops.fixups = bamboo_fixups; + platform_ops.exit = ibm44x_dbcr_reset; + bamboo_mac0 = mac0; + bamboo_mac1 = mac1; + ft_init(_dtb_start, 0, 32); + serial_console_init(); +} diff -puN /dev/null arch/powerpc/boot/cpm-serial.c --- /dev/null +++ a/arch/powerpc/boot/cpm-serial.c @@ -0,0 +1,249 @@ +/* + * CPM serial console support. + * + * Copyright 2007 Freescale Semiconductor, Inc. + * Author: Scott Wood + * + * It is assumed that the firmware (or the platform file) has already set + * up the port. + */ + +#include "types.h" +#include "io.h" +#include "ops.h" + +struct cpm_scc { + u32 gsmrl; + u32 gsmrh; + u16 psmr; + u8 res1[2]; + u16 todr; + u16 dsr; + u16 scce; + u8 res2[2]; + u16 sccm; + u8 res3; + u8 sccs; + u8 res4[8]; +}; + +struct cpm_smc { + u8 res1[2]; + u16 smcmr; + u8 res2[2]; + u8 smce; + u8 res3[3]; + u8 smcm; + u8 res4[5]; +}; + +struct cpm_param { + u16 rbase; + u16 tbase; + u8 rfcr; + u8 tfcr; +}; + +struct cpm_bd { + u16 sc; /* Status and Control */ + u16 len; /* Data length in buffer */ + u8 *addr; /* Buffer address in host memory */ +}; + +static void *cpcr; +static struct cpm_param *param; +static struct cpm_smc *smc; +static struct cpm_scc *scc; +struct cpm_bd *tbdf, *rbdf; +static u32 cpm_cmd; +static u8 *dpram_start; + +static void (*do_cmd)(int op); +static void (*enable_port)(void); +static void (*disable_port)(void); + +#define CPM_CMD_STOP_TX 4 +#define CPM_CMD_RESTART_TX 6 +#define CPM_CMD_INIT_RX_TX 0 + +static void cpm1_cmd(int op) +{ + while (in_be16(cpcr) & 1) + ; + + out_be16(cpcr, (op << 8) | cpm_cmd | 1); + + while (in_be16(cpcr) & 1) + ; +} + +static void cpm2_cmd(int op) +{ + while (in_be32(cpcr) & 0x10000) + ; + + out_be32(cpcr, op | cpm_cmd | 0x10000); + + while (in_be32(cpcr) & 0x10000) + ; +} + +static void smc_disable_port(void) +{ + do_cmd(CPM_CMD_STOP_TX); + out_be16(&smc->smcmr, in_be16(&smc->smcmr) & ~3); +} + +static void scc_disable_port(void) +{ + do_cmd(CPM_CMD_STOP_TX); + out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30); +} + +static void smc_enable_port(void) +{ + out_be16(&smc->smcmr, in_be16(&smc->smcmr) | 3); + do_cmd(CPM_CMD_RESTART_TX); +} + +static void scc_enable_port(void) +{ + out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30); + do_cmd(CPM_CMD_RESTART_TX); +} + +static int cpm_serial_open(void) +{ + int dpaddr = 0x800; + disable_port(); + + out_8(¶m->rfcr, 0x10); + out_8(¶m->tfcr, 0x10); + + rbdf = (struct cpm_bd *)(dpram_start + dpaddr); + rbdf->addr = (u8 *)(rbdf + 2); + rbdf->sc = 0xa000; + rbdf->len = 1; + + tbdf = rbdf + 1; + tbdf->addr = (u8 *)(rbdf + 2) + 1; + tbdf->sc = 0x2000; + tbdf->len = 1; + + sync(); + out_be16(¶m->rbase, dpaddr); + out_be16(¶m->tbase, dpaddr + sizeof(struct cpm_bd)); + + do_cmd(CPM_CMD_INIT_RX_TX); + + enable_port(); + return 0; +} + +static void cpm_serial_putc(unsigned char c) +{ + while (tbdf->sc & 0x8000) + barrier(); + + sync(); + + tbdf->addr[0] = c; + eieio(); + tbdf->sc |= 0x8000; +} + +static unsigned char cpm_serial_tstc(void) +{ + barrier(); + return !(rbdf->sc & 0x8000); +} + +static unsigned char cpm_serial_getc(void) +{ + unsigned char c; + + while (!cpm_serial_tstc()) + ; + + sync(); + c = rbdf->addr[0]; + eieio(); + rbdf->sc |= 0x8000; + + return c; +} + +int cpm_console_init(void *devp, struct serial_console_data *scdp) +{ + void *reg_virt[2]; + int is_smc = 0, is_cpm2 = 0, n; + unsigned long reg_phys; + void *parent; + + if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) { + is_smc = 1; + } else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) { + is_cpm2 = 1; + } else if (dt_is_compatible(devp, "fsl,cpm2-smc-uart")) { + is_cpm2 = 1; + is_smc = 1; + } + + if (is_smc) { + enable_port = smc_enable_port; + disable_port = smc_disable_port; + } else { + enable_port = scc_enable_port; + disable_port = scc_disable_port; + } + + if (is_cpm2) + do_cmd = cpm2_cmd; + else + do_cmd = cpm1_cmd; + + n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4); + if (n < 4) + return -1; + + n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt)); + if (n < (int)sizeof(reg_virt)) { + for (n = 0; n < 2; n++) { + if (!dt_xlate_reg(devp, n, ®_phys, NULL)) + return -1; + + reg_virt[n] = (void *)reg_phys; + } + } + + if (is_smc) + smc = reg_virt[0]; + else + scc = reg_virt[0]; + + param = reg_virt[1]; + + parent = get_parent(devp); + if (!parent) + return -1; + + n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt)); + if (n < (int)sizeof(reg_virt)) { + for (n = 0; n < 2; n++) { + if (!dt_xlate_reg(parent, n, ®_phys, NULL)) + return -1; + + reg_virt[n] = (void *)reg_phys; + } + } + + cpcr = reg_virt[0]; + dpram_start = reg_virt[1]; + + scdp->open = cpm_serial_open; + scdp->putc = cpm_serial_putc; + scdp->getc = cpm_serial_getc; + scdp->tstc = cpm_serial_tstc; + + return 0; +} diff -puN arch/powerpc/boot/cuboot-83xx.c~git-powerpc arch/powerpc/boot/cuboot-83xx.c --- a/arch/powerpc/boot/cuboot-83xx.c~git-powerpc +++ a/arch/powerpc/boot/cuboot-83xx.c @@ -18,7 +18,6 @@ #include "ppcboot.h" static bd_t bd; -extern char _dtb_start[], _dtb_end[]; static void platform_fixups(void) { diff -puN arch/powerpc/boot/cuboot-85xx.c~git-powerpc arch/powerpc/boot/cuboot-85xx.c --- a/arch/powerpc/boot/cuboot-85xx.c~git-powerpc +++ a/arch/powerpc/boot/cuboot-85xx.c @@ -18,7 +18,6 @@ #include "ppcboot.h" static bd_t bd; -extern char _dtb_start[], _dtb_end[]; static void platform_fixups(void) { diff -puN /dev/null arch/powerpc/boot/cuboot-8xx.c --- /dev/null +++ a/arch/powerpc/boot/cuboot-8xx.c @@ -0,0 +1,45 @@ +/* + * Old U-boot compatibility for 8xx + * + * Author: Scott Wood + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "cuboot.h" + +#define TARGET_8xx +#define TARGET_HAS_ETH1 +#include "ppcboot.h" + +static bd_t bd; + +static void platform_fixups(void) +{ + void *node; + + dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); + dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr); + dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq); + + node = finddevice("/soc/cpm"); + if (node) { + setprop(node, "clock-frequency", &bd.bi_busfreq, 4); + setprop(node, "fsl,brg-frequency", &bd.bi_busfreq, 4); + } +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + ft_init(_dtb_start, _dtb_end - _dtb_start, 32); + serial_console_init(); + platform_ops.fixups = platform_fixups; +} diff -puN /dev/null arch/powerpc/boot/cuboot-bamboo.c --- /dev/null +++ a/arch/powerpc/boot/cuboot-bamboo.c @@ -0,0 +1,30 @@ +/* + * Old U-boot compatibility for Bamboo + * + * Author: Josh Boyer + * + * Copyright 2007 IBM Corporation + * + * Based on cuboot-ebony.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "44x.h" +#include "cuboot.h" + +#define TARGET_44x +#include "ppcboot.h" + +static bd_t bd; + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + bamboo_init(&bd.bi_enetaddr, &bd.bi_enet1addr); +} diff -puN /dev/null arch/powerpc/boot/cuboot-pq2.c --- /dev/null +++ a/arch/powerpc/boot/cuboot-pq2.c @@ -0,0 +1,283 @@ +/* + * Old U-boot compatibility for PowerQUICC II + * (a.k.a. 82xx with CPM, not the 8240 family of chips) + * + * Author: Scott Wood + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "cuboot.h" +#include "io.h" + +#define TARGET_CPM2 +#define TARGET_HAS_ETH1 +#include "ppcboot.h" + +static bd_t bd; + +struct cs_range { + u32 csnum; + u32 base; /* must be zero */ + u32 addr; + u32 size; +}; + +struct pci_range { + u32 flags; + u32 pci_addr[2]; + u32 phys_addr; + u32 size[2]; +}; + +struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)]; +struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)]; + +/* Different versions of u-boot put the BCSR in different places, and + * some don't set up the PCI PIC at all, so we assume the device tree is + * sane and update the BRx registers appropriately. + * + * For any node defined as compatible with fsl,pq2-chipselect, + * #address/#size must be 2/1 for chipselect bus, 1/1 for parent bus, + * and ranges must be for whole chip selects. + */ +static void update_cs_ranges(void) +{ + u32 ctrl_ph; + void *ctrl_node, *bus_node, *parent_node; + u32 *ctrl_addr; + unsigned long ctrl_size; + u32 naddr, nsize; + int len; + int i; + + bus_node = finddevice("/chipselect"); + if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-chipselect")) + return; + + dt_get_reg_format(bus_node, &naddr, &nsize); + if (naddr != 2 || nsize != 1) + goto err; + + parent_node = get_parent(bus_node); + if (!parent_node) + goto err; + + dt_get_reg_format(parent_node, &naddr, &nsize); + if (naddr != 1 || nsize != 1) + goto err; + + len = getprop(bus_node, "fsl,ctrl", &ctrl_ph, 4); + if (len != 4) + goto err; + + ctrl_node = find_node_by_prop_value(NULL, "linux,phandle", + (char *)&ctrl_ph, 4); + if (!ctrl_node) + goto err; + + if (!dt_is_compatible(ctrl_node, "fsl,pq2-chipselect-ctrl")) + goto err; + + if (!dt_xlate_reg(ctrl_node, 0, (unsigned long *)&ctrl_addr, + &ctrl_size)) + goto err; + + len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf)); + + for (i = 0; i < len / sizeof(struct cs_range); i++) { + u32 base, option; + int cs = cs_ranges_buf[i].csnum; + if (cs >= ctrl_size / 8) + goto err; + + if (cs_ranges_buf[i].base != 0) + goto err; + + base = in_be32(&ctrl_addr[cs * 2]); + + /* If CS is already valid, use the existing flags. + * Otherwise, guess a sane default. + */ + if (base & 1) { + base &= 0x7fff; + option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; + } else { + base = 0x1801; + option = 0x10; + } + + out_be32(&ctrl_addr[cs * 2], 0); + out_be32(&ctrl_addr[cs * 2 + 1], + option | ~(cs_ranges_buf[i].size - 1)); + out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); + } + + return; + +err: + printf("Bad /chipselect or fsl,pq2-chipselect-ctrl node\r\n"); +} + +/* Older u-boots don't set PCI up properly. Update the hardware to match + * the device tree. The prefetch mem region and non-prefetch mem region + * must be contiguous in the host bus. As required by the PCI binding, + * PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only + * 32-bit PCI is supported. All three region types (prefetchable mem, + * non-prefetchable mem, and I/O) must be present. + */ +static void fixup_pci(void) +{ + struct pci_range *mem = NULL, *mmio = NULL, + *io = NULL, *mem_base = NULL; + u32 *pci_regs[3]; + u8 *soc_regs; + int i, len; + void *ctrl_node, *bus_node, *parent_node, *soc_node; + u32 naddr, nsize, bus_ph, mem_log2; + + ctrl_node = finddevice("/soc/pci"); + if (!ctrl_node || !dt_is_compatible(ctrl_node, "fsl,pq2-pci")) + return; + + soc_node = finddevice("/soc"); + if (!soc_node || !dt_is_compatible(soc_node, "fsl,pq2-soc")) + goto err; + + for (i = 0; i < 3; i++) + if (!dt_xlate_reg(ctrl_node, i, + (unsigned long *)&pci_regs[i], NULL)) + goto err; + + if (!dt_xlate_reg(soc_node, 0, (unsigned long *)&soc_regs, NULL)) + goto err; + + len = getprop(ctrl_node, "fsl,bus", &bus_ph, 4); + if (len != 4) + goto err; + + bus_node = find_node_by_prop_value(NULL, "linux,phandle", + (char *)&bus_ph, 4); + if (!bus_node) + goto err; + + dt_get_reg_format(bus_node, &naddr, &nsize); + if (naddr != 3 || nsize != 2) + goto err; + + parent_node = get_parent(bus_node); + if (!parent_node) + goto err; + + dt_get_reg_format(parent_node, &naddr, &nsize); + if (naddr != 1 || nsize != 1) + goto err; + + len = getprop(bus_node, "ranges", pci_ranges_buf, + sizeof(pci_ranges_buf)); + + for (i = 0; i < len / sizeof(struct pci_range); i++) { + u32 flags = pci_ranges_buf[i].flags & 0x43000000; + + if (flags == 0x42000000) + mem = &pci_ranges_buf[i]; + else if (flags == 0x02000000) + mmio = &pci_ranges_buf[i]; + else if (flags == 0x01000000) + io = &pci_ranges_buf[i]; + } + + if (!mem || !mmio || !io) + goto err; + + if (mem->phys_addr + mem->size[1] == mmio->phys_addr) + mem_base = mem; + else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr) + mem_base = mmio; + else + goto err; + + out_be32(&pci_regs[1][0], mem_base->phys_addr | 1); + out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1)); + + out_be32(&pci_regs[1][1], io->phys_addr | 1); + out_be32(&pci_regs[2][1], ~(io->size[1] - 1)); + + out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12); + out_le32(&pci_regs[0][2], mem->phys_addr >> 12); + out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000); + + out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12); + out_le32(&pci_regs[0][8], mmio->phys_addr >> 12); + out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000); + + out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12); + out_le32(&pci_regs[0][14], io->phys_addr >> 12); + out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000); + + /* Inbound translation */ + out_le32(&pci_regs[0][58], 0); + out_le32(&pci_regs[0][60], 0); + + mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1); + out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1)); + + /* If PCI is disabled, drive RST high to enable. */ + if (!(in_le32(&pci_regs[0][32]) & 1)) { + /* Tpvrh (Power valid to RST# high) 100 ms */ + udelay(100000); + + out_le32(&pci_regs[0][32], 1); + + /* Trhfa (RST# high to first cfg access) 2^25 clocks */ + udelay(1020000); + } + + /* Enable bus master and memory access */ + out_le32(&pci_regs[0][64], 0x80000004); + out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6); + + /* Park the bus on PCI, and elevate PCI's arbitration priority, + * as required by section 9.6 of the user's manual. + */ + out_8(&soc_regs[0x10028], 3); + out_be32((u32 *)&soc_regs[0x1002c], 0x01236745); + + return; + +err: + printf("Bad PCI node\r\n"); +} + +static void pq2_platform_fixups(void) +{ + void *node; + + dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); + dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr); + dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq); + + node = finddevice("/soc/cpm"); + if (node) { + setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4); + setprop(node, "fsl,brg-frequency", &bd.bi_brgfreq, 4); + } + + update_cs_ranges(); + fixup_pci(); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + ft_init(_dtb_start, _dtb_end - _dtb_start, 32); + serial_console_init(); + platform_ops.fixups = pq2_platform_fixups; +} diff -puN /dev/null arch/powerpc/boot/cuboot-sequoia.c --- /dev/null +++ a/arch/powerpc/boot/cuboot-sequoia.c @@ -0,0 +1,56 @@ +/* + * Old U-boot compatibility for Sequoia + * + * Valentine Barshak + * Copyright 2007 MontaVista Software, Inc + * + * Based on Ebony code by David Gibson + * Copyright IBM Corporation, 2007 + * + * Based on Bamboo code by Josh Boyer + * Copyright IBM Corporation, 2007 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 of the License + */ + +#include +#include +#include "types.h" +#include "elf.h" +#include "string.h" +#include "stdio.h" +#include "page.h" +#include "ops.h" +#include "dcr.h" +#include "4xx.h" +#include "44x.h" +#include "cuboot.h" + +#define TARGET_4xx +#define TARGET_44x +#include "ppcboot.h" + +static bd_t bd; + + +static void sequoia_fixups(void) +{ + unsigned long sysclk = 33333333; + + ibm440ep_fixup_clocks(sysclk, 11059200); + ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); + ibm4xx_denali_fixup_memsize(); + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + platform_ops.fixups = sequoia_fixups; + platform_ops.exit = ibm44x_dbcr_reset; + ft_init(_dtb_start, 0, 32); + serial_console_init(); +} diff -puN arch/powerpc/boot/cuboot.c~git-powerpc arch/powerpc/boot/cuboot.c --- a/arch/powerpc/boot/cuboot.c~git-powerpc +++ a/arch/powerpc/boot/cuboot.c @@ -17,9 +17,6 @@ #include "ppcboot.h" -extern char _end[]; -extern char _dtb_start[], _dtb_end[]; - void cuboot_init(unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7, unsigned long end_of_ram) diff -puN arch/powerpc/boot/dcr.h~git-powerpc arch/powerpc/boot/dcr.h --- a/arch/powerpc/boot/dcr.h~git-powerpc +++ a/arch/powerpc/boot/dcr.h @@ -121,4 +121,22 @@ static const unsigned long sdram_bxcr[] #define DCRN_CPC0_MIRQ1 0x0ed #define DCRN_CPC0_JTAGID 0x0ef +#define DCRN_MAL0_CFG 0x180 +#define MAL_RESET 0x80000000 + +/* 440EP Clock/Power-on Reset regs */ +#define DCRN_CPR0_ADDR 0xc +#define DCRN_CPR0_DATA 0xd +#define CPR0_PLLD0 0x60 +#define CPR0_OPBD0 0xc0 +#define CPR0_PERD0 0xe0 +#define CPR0_PRIMBD0 0xa0 +#define CPR0_SCPID 0x120 +#define CPR0_PLLC0 0x40 + +/* 405GP Clocking/Power Management/Chip Control regs */ +#define DCRN_CPC0_PLLMR 0xb0 +#define DCRN_405_CPC0_CR0 0xb1 +#define DCRN_405_CPC0_CR1 0xb2 + #endif /* _PPC_BOOT_DCR_H_ */ diff -puN arch/powerpc/boot/devtree.c~git-powerpc arch/powerpc/boot/devtree.c --- a/arch/powerpc/boot/devtree.c~git-powerpc +++ a/arch/powerpc/boot/devtree.c @@ -74,6 +74,8 @@ void dt_fixup_cpu_clocks(u32 cpu, u32 tb if (bus > 0) setprop_val(devp, "bus-frequency", bus); } + + timebase_period_ns = 1000000000 / tb; } void dt_fixup_clock(const char *path, u32 freq) @@ -98,12 +100,14 @@ void __dt_fixup_mac_addresses(u32 starti devp = find_node_by_prop_value(NULL, "linux,network-index", (void*)&index, sizeof(index)); - printf("ENET%d: local-mac-address <-" - " %02x:%02x:%02x:%02x:%02x:%02x\n\r", index, - addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); + if (devp) { + printf("ENET%d: local-mac-address <-" + " %02x:%02x:%02x:%02x:%02x:%02x\n\r", index, + addr[0], addr[1], addr[2], + addr[3], addr[4], addr[5]); - if (devp) setprop(devp, "local-mac-address", addr, 6); + } index++; } @@ -111,9 +115,8 @@ void __dt_fixup_mac_addresses(u32 starti } #define MAX_ADDR_CELLS 4 -#define MAX_RANGES 8 -static void get_reg_format(void *node, u32 *naddr, u32 *nsize) +void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize) { if (getprop(node, "#address-cells", naddr, 4) != 4) *naddr = 2; @@ -207,7 +210,7 @@ static int find_range(u32 *reg, u32 *ran * In particular, PCI is not supported. Also, only the beginning of the * reg block is tracked; size is ignored except in ranges. */ -static u32 dt_xlate_buf[MAX_ADDR_CELLS * MAX_RANGES * 3]; +static u32 prop_buf[MAX_PROP_LEN / 4]; static int dt_xlate(void *node, int res, int reglen, unsigned long *addr, unsigned long *size) @@ -216,14 +219,14 @@ static int dt_xlate(void *node, int res, u32 this_addr[MAX_ADDR_CELLS]; void *parent; u64 ret_addr, ret_size; - u32 naddr, nsize, prev_naddr; + u32 naddr, nsize, prev_naddr, prev_nsize; int buflen, offset; parent = get_parent(node); if (!parent) return 0; - get_reg_format(parent, &naddr, &nsize); + dt_get_reg_format(parent, &naddr, &nsize); if (nsize > 2) return 0; @@ -231,41 +234,47 @@ static int dt_xlate(void *node, int res, offset = (naddr + nsize) * res; if (reglen < offset + naddr + nsize || - sizeof(dt_xlate_buf) < offset + naddr + nsize) + MAX_PROP_LEN < (offset + naddr + nsize) * 4) return 0; - copy_val(last_addr, dt_xlate_buf + offset, naddr); + copy_val(last_addr, prop_buf + offset, naddr); - ret_size = dt_xlate_buf[offset + naddr]; + ret_size = prop_buf[offset + naddr]; if (nsize == 2) { ret_size <<= 32; - ret_size |= dt_xlate_buf[offset + naddr + 1]; + ret_size |= prop_buf[offset + naddr + 1]; } - while ((node = get_parent(node))) { + for (;;) { prev_naddr = naddr; + prev_nsize = nsize; + node = parent; + + parent = get_parent(node); + if (!parent) + break; - get_reg_format(node, &naddr, &nsize); + dt_get_reg_format(parent, &naddr, &nsize); - buflen = getprop(node, "ranges", dt_xlate_buf, - sizeof(dt_xlate_buf)); - if (buflen < 0) + buflen = getprop(node, "ranges", prop_buf, + sizeof(prop_buf)); + if (buflen == 0) continue; - if (buflen > sizeof(dt_xlate_buf)) + if (buflen < 0 || buflen > sizeof(prop_buf)) return 0; - offset = find_range(last_addr, dt_xlate_buf, prev_naddr, - naddr, nsize, buflen / 4); + offset = find_range(last_addr, prop_buf, prev_naddr, + naddr, prev_nsize, buflen / 4); if (offset < 0) return 0; - copy_val(this_addr, dt_xlate_buf + offset, prev_naddr); + copy_val(this_addr, prop_buf + offset, prev_naddr); if (!sub_reg(last_addr, this_addr)) return 0; - copy_val(this_addr, dt_xlate_buf + offset + prev_naddr, naddr); + copy_val(this_addr, prop_buf + offset + prev_naddr, naddr); if (!add_reg(last_addr, this_addr, naddr)) return 0; @@ -292,16 +301,35 @@ int dt_xlate_reg(void *node, int res, un { int reglen; - reglen = getprop(node, "reg", dt_xlate_buf, sizeof(dt_xlate_buf)) / 4; + reglen = getprop(node, "reg", prop_buf, sizeof(prop_buf)) / 4; return dt_xlate(node, res, reglen, addr, size); } int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr) { - if (buflen > sizeof(dt_xlate_buf)) + if (buflen > sizeof(prop_buf)) return 0; - memcpy(dt_xlate_buf, buf, buflen); + memcpy(prop_buf, buf, buflen); return dt_xlate(node, 0, buflen / 4, xlated_addr, NULL); } + +int dt_is_compatible(void *node, const char *compat) +{ + char *buf = (char *)prop_buf; + int len, pos; + + len = getprop(node, "compatible", buf, MAX_PROP_LEN); + if (len < 0) + return 0; + + for (pos = 0; pos < len; pos++) { + if (!strcmp(buf + pos, compat)) + return 1; + + pos += strnlen(&buf[pos], len - pos); + } + + return 0; +} diff -puN /dev/null arch/powerpc/boot/dts/bamboo.dts --- /dev/null +++ a/arch/powerpc/boot/dts/bamboo.dts @@ -0,0 +1,244 @@ +/* + * Device Tree Source for AMCC Bamboo + * + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer + * + * FIXME: Draft only! + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,bamboo"; + compatible = "amcc,bamboo"; + dcr-parent = <&/cpus/PowerPC,440EP@0>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,440EP@0 { + device_type = "cpu"; + reg = <0>; + clock-frequency = <0>; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <8000>; + d-cache-size = <8000>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440ep","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440ep","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1e 4 1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-440ep"; + dcr-reg = <00e 002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-440ep"; + dcr-reg = <00c 002>; + }; + + plb { + compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: sdram { + compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; + dcr-reg = <010 2>; + }; + + DMA0: dma { + compatible = "ibm,dma-440ep", "ibm,dma-440gp"; + dcr-reg = <100 027>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; + dcr-reg = <180 62>; + num-tx-chans = <4>; + num-rx-chans = <2>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + interrupt-map = ; + }; + + POB0: opb { + compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Bamboo is oddball in the 44x world and doesn't use the ERPN + * bits. + */ + ranges = <00000000 0 00000000 80000000 + 80000000 0 80000000 80000000>; + interrupt-parent = <&UIC1>; + interrupts = <7 4>; + clock-frequency = <0>; /* Filled in by zImage */ + + EBC0: ebc { + compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by zImage */ + ranges; + interrupts = <5 1>; + interrupt-parent = <&UIC1>; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <1c200>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + UART2: serial@ef600500 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <3 4>; + }; + + UART3: serial@ef600600 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <4 4>; + }; + + IIC0: i2c@ef600700 { + device_type = "i2c"; + compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; + reg = ; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + + IIC1: i2c@ef600800 { + device_type = "i2c"; + compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; + reg = ; + interrupt-parent = <&UIC0>; + interrupts = <7 4>; + }; + + ZMII0: emac-zmii@ef600d00 { + device_type = "zmii-interface"; + compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; + reg = ; + }; + + EMAC0: ethernet@ef600e00 { + device_type = "network"; + compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <1c 4 1d 4>; + reg = ; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <0 1>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000001>; + zmii-device = <&ZMII0>; + zmii-channel = <0>; + }; + + EMAC1: ethernet@ef600f00 { + device_type = "network"; + compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <1e 4 1f 4>; + reg = ; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <2 3>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000001>; + zmii-device = <&ZMII0>; + zmii-channel = <1>; + }; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@ef600300"; + bootargs = "console=ttyS0,115200"; + }; +}; diff -puN arch/powerpc/boot/dts/ebony.dts~git-powerpc arch/powerpc/boot/dts/ebony.dts --- a/arch/powerpc/boot/dts/ebony.dts~git-powerpc +++ a/arch/powerpc/boot/dts/ebony.dts @@ -9,10 +9,6 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without * any warranty of any kind, whether express or implied. - * - * To build: - * dtc -I dts -O asm -o ebony.S -b 0 ebony.dts - * dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts */ / { @@ -142,13 +138,16 @@ interrupt-parent = <&UIC1>; small-flash@0,80000 { - device_type = "rom"; - compatible = "direct-mapped"; - probe-type = "JEDEC"; + compatible = "jedec-flash"; bank-width = <1>; - partitions = <0 80000>; - partition-names = "OpenBIOS"; reg = <0 80000 80000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "OpenBIOS"; + reg = <0 80000>; + read-only; + }; }; ds1743@1,0 { @@ -158,14 +157,19 @@ }; large-flash@2,0 { - device_type = "rom"; - compatible = "direct-mapped"; - probe-type = "JEDEC"; + compatible = "jedec-flash"; bank-width = <1>; - partitions = <0 380000 - 380000 80000>; - partition-names = "fs", "firmware"; reg = <2 0 400000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "fs"; + reg = <0 380000>; + }; + partition@380000 { + label = "firmware"; + reg = <380000 80000>; + }; }; ir@3,0 { @@ -175,6 +179,7 @@ fpga@7,0 { compatible = "Ebony-FPGA"; reg = <7 0 10>; + virtual-reg = ; }; }; diff -puN arch/powerpc/boot/dts/holly.dts~git-powerpc arch/powerpc/boot/dts/holly.dts --- a/arch/powerpc/boot/dts/holly.dts~git-powerpc +++ a/arch/powerpc/boot/dts/holly.dts @@ -8,10 +8,6 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without * any warranty of any kind, whether express or implied. - * - * To build: - * dtc -I dts -O asm -o holly.S -b 0 holly.dts - * dtc -I dts -O dtb -o holly.dtb -b 0 holly.dts */ / { @@ -35,7 +31,6 @@ timebase-frequency = <2faf080>; clock-frequency = <23c34600>; bus-frequency = ; - 32-bit; }; }; diff -puN arch/powerpc/boot/dts/kuroboxHD.dts~git-powerpc arch/powerpc/boot/dts/kuroboxHD.dts --- a/arch/powerpc/boot/dts/kuroboxHD.dts~git-powerpc +++ a/arch/powerpc/boot/dts/kuroboxHD.dts @@ -15,9 +15,6 @@ XXXX add flash parts, rtc, ?? -build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts" - - */ / { @@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kur soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; compatible = "mpc10x"; store-gathering = <0>; /* 0 == off, !0 == on */ @@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kur rtc@32 { device_type = "rtc"; - compatible = "ricoh,rs5c372b"; + compatible = "ricoh,rs5c372a"; reg = <32>; }; }; @@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kur reg = <80004500 8>; clock-frequency = <5d08d88>; current-speed = <2580>; - interrupts = <9 2>; + interrupts = <9 0>; interrupt-parent = <&mpic>; }; @@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kur compatible = "chrp,open-pic"; interrupt-controller; reg = <80040000 40000>; - built-in; }; pci@fec00000 { diff -puN arch/powerpc/boot/dts/kuroboxHG.dts~git-powerpc arch/powerpc/boot/dts/kuroboxHG.dts --- a/arch/powerpc/boot/dts/kuroboxHG.dts~git-powerpc +++ a/arch/powerpc/boot/dts/kuroboxHG.dts @@ -15,9 +15,6 @@ XXXX add flash parts, rtc, ?? -build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts" - - */ / { @@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kur soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; compatible = "mpc10x"; store-gathering = <0>; /* 0 == off, !0 == on */ @@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kur rtc@32 { device_type = "rtc"; - compatible = "ricoh,rs5c372b"; + compatible = "ricoh,rs5c372a"; reg = <32>; }; }; @@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kur reg = <80004500 8>; clock-frequency = <7c044a8>; current-speed = <2580>; - interrupts = <9 2>; + interrupts = <9 0>; interrupt-parent = <&mpic>; }; @@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kur compatible = "chrp,open-pic"; interrupt-controller; reg = <80040000 40000>; - built-in; }; pci@fec00000 { diff -puN arch/powerpc/boot/dts/lite5200.dts~git-powerpc arch/powerpc/boot/dts/lite5200.dts --- a/arch/powerpc/boot/dts/lite5200.dts~git-powerpc +++ a/arch/powerpc/boot/dts/lite5200.dts @@ -37,7 +37,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; }; @@ -50,10 +49,9 @@ model = "fsl,mpc5200"; compatible = "mpc5200"; revision = ""; // from bootloader - #interrupt-cells = <3>; device_type = "soc"; - ranges = <0 f0000000 f0010000>; - reg = ; + ranges = <0 f0000000 0000c000>; + reg = ; bus-frequency = <0>; // from bootloader system-frequency = <0>; // from bootloader @@ -69,7 +67,6 @@ device_type = "interrupt-controller"; compatible = "mpc5200-pic"; reg = <500 80>; - built-in; }; gpt@600 { // General Purpose Timer @@ -185,27 +182,6 @@ interrupt-parent = <&mpc5200_pic>; }; - pci@0d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "mpc5200-pci"; - reg = ; - interrupt-map-mask = ; - interrupt-map = ; - clock-frequency = <0>; // From boot loader - interrupts = <2 8 0 2 9 0 2 a 0>; - interrupt-parent = <&mpc5200_pic>; - bus-range = <0 0>; - ranges = <42000000 0 80000000 80000000 0 20000000 - 02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 b0000000 0 01000000>; - }; - spi@f00 { device_type = "spi"; compatible = "mpc5200-spi"; @@ -340,4 +316,25 @@ reg = <8000 4000>; }; }; + + pci@f0000d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "mpc5200-pci"; + reg = ; + interrupt-map-mask = ; + interrupt-map = ; + clock-frequency = <0>; // From boot loader + interrupts = <2 8 0 2 9 0 2 a 0>; + interrupt-parent = <&mpc5200_pic>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 20000000 + 02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 b0000000 0 01000000>; + }; }; diff -puN arch/powerpc/boot/dts/lite5200b.dts~git-powerpc arch/powerpc/boot/dts/lite5200b.dts --- a/arch/powerpc/boot/dts/lite5200b.dts~git-powerpc +++ a/arch/powerpc/boot/dts/lite5200b.dts @@ -37,7 +37,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; }; @@ -50,10 +49,9 @@ model = "fsl,mpc5200b"; compatible = "mpc5200"; revision = ""; // from bootloader - #interrupt-cells = <3>; device_type = "soc"; - ranges = <0 f0000000 f0010000>; - reg = ; + ranges = <0 f0000000 0000c000>; + reg = ; bus-frequency = <0>; // from bootloader system-frequency = <0>; // from bootloader @@ -69,7 +67,6 @@ device_type = "interrupt-controller"; compatible = "mpc5200b-pic\0mpc5200-pic"; reg = <500 80>; - built-in; }; gpt@600 { // General Purpose Timer @@ -185,32 +182,6 @@ interrupt-parent = <&mpc5200_pic>; }; - pci@0d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "mpc5200b-pci\0mpc5200-pci"; - reg = ; - interrupt-map-mask = ; - interrupt-map = ; - clock-frequency = <0>; // From boot loader - interrupts = <2 8 0 2 9 0 2 a 0>; - interrupt-parent = <&mpc5200_pic>; - bus-range = <0 0>; - ranges = <42000000 0 80000000 80000000 0 20000000 - 02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 b0000000 0 01000000>; - }; - spi@f00 { device_type = "spi"; compatible = "mpc5200b-spi\0mpc5200-spi"; @@ -345,4 +316,30 @@ reg = <8000 4000>; }; }; + + pci@f0000d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "mpc5200b-pci\0mpc5200-pci"; + reg = ; + interrupt-map-mask = ; + interrupt-map = ; + clock-frequency = <0>; // From boot loader + interrupts = <2 8 0 2 9 0 2 a 0>; + interrupt-parent = <&mpc5200_pic>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 20000000 + 02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 b0000000 0 01000000>; + }; }; diff -puN arch/powerpc/boot/dts/mpc7448hpc2.dts~git-powerpc arch/powerpc/boot/dts/mpc7448hpc2.dts --- a/arch/powerpc/boot/dts/mpc7448hpc2.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc7448hpc2.dts @@ -31,7 +31,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot clock-frequency = <0>; // From U-Boot bus-frequency = <0>; // From U-Boot - 32-bit; }; }; @@ -44,7 +43,6 @@ tsi108@c0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "tsi-bridge"; ranges = <00000000 c0000000 00010000>; reg = ; @@ -128,7 +126,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <7400 400>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -180,7 +177,6 @@ device_type = "pic-router"; #address-cells = <0>; #interrupt-cells = <2>; - built-in; big-endian; interrupts = <17 2>; interrupt-parent = <&mpic>; diff -puN arch/powerpc/boot/dts/mpc8272ads.dts~git-powerpc arch/powerpc/boot/dts/mpc8272ads.dts --- a/arch/powerpc/boot/dts/mpc8272ads.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8272ads.dts @@ -10,207 +10,204 @@ */ / { - model = "MPC8272ADS"; - compatible = "MPC8260ADS"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,8272@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <4000>; // L1, 16K - i-cache-size = <4000>; // L1, 16K - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - 32-bit; - }; - }; - - pci_pic: interrupt-controller@f8200000 { - #address-cells = <0>; - #interrupt-cells = <2>; - interrupt-controller; - reg = ; - built-in; - device_type = "pci-pic"; - }; - memory { - device_type = "memory"; - reg = <00000000 4000000 f4500000 00000020>; - }; - - chosen { - name = "chosen"; - linux,platform = <0>; + model = "MPC8272ADS"; + compatible = "MPC8260ADS"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8272@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <4000>; // L1, 16K + i-cache-size = <4000>; // L1, 16K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + pci_pic: interrupt-controller@f8200000 { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + reg = ; + device_type = "pci-pic"; + }; + + memory { + device_type = "memory"; + reg = <00000000 4000000 f4500000 00000020>; + }; + + chosen { + name = "chosen"; + linux,platform = <0>; interrupt-controller = <&Cpm_pic>; - }; + }; + + soc8272@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <00000000 f0000000 00053000>; + reg = ; + + mdio@0 { + device_type = "mdio"; + compatible = "fs_enet"; + reg = <0 0>; + #address-cells = <1>; + #size-cells = <0>; - soc8272@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - device_type = "soc"; - ranges = <00000000 f0000000 00053000>; - reg = ; - - mdio@0 { - device_type = "mdio"; - compatible = "fs_enet"; - reg = <0 0>; - #address-cells = <1>; - #size-cells = <0>; phy0:ethernet-phy@0 { interrupt-parent = <&Cpm_pic>; - interrupts = <17 4>; - reg = <0>; - bitbang = [ 12 12 13 02 02 01 ]; - device_type = "ethernet-phy"; - }; + interrupts = <17 4>; + reg = <0>; + bitbang = [ 12 12 13 02 02 01 ]; + device_type = "ethernet-phy"; + }; + phy1:ethernet-phy@1 { interrupt-parent = <&Cpm_pic>; - interrupts = <17 4>; - bitbang = [ 12 12 13 02 02 01 ]; - reg = <3>; - device_type = "ethernet-phy"; - }; - }; - - ethernet@24000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - device-id = <1>; - compatible = "fs_enet"; - model = "FCC"; - reg = <11300 20 8400 100 11380 30>; - mac-address = [ 00 11 2F 99 43 54 ]; - interrupts = <20 2>; + interrupts = <17 4>; + bitbang = [ 12 12 13 02 02 01 ]; + reg = <3>; + device_type = "ethernet-phy"; + }; + }; + + ethernet@24000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + device-id = <1>; + compatible = "fs_enet"; + model = "FCC"; + reg = <11300 20 8400 100 11380 30>; + mac-address = [ 00 11 2F 99 43 54 ]; + interrupts = <20 2>; interrupt-parent = <&Cpm_pic>; phy-handle = <&Phy0>; - rx-clock = <13>; - tx-clock = <12>; - }; - - ethernet@25000 { - device_type = "network"; - device-id = <2>; - compatible = "fs_enet"; - model = "FCC"; - reg = <11320 20 8500 100 113b0 30>; - mac-address = [ 00 11 2F 99 44 54 ]; - interrupts = <21 2>; + rx-clock = <13>; + tx-clock = <12>; + }; + + ethernet@25000 { + device_type = "network"; + device-id = <2>; + compatible = "fs_enet"; + model = "FCC"; + reg = <11320 20 8500 100 113b0 30>; + mac-address = [ 00 11 2F 99 44 54 ]; + interrupts = <21 2>; interrupt-parent = <&Cpm_pic>; phy-handle = <&Phy1>; - rx-clock = <17>; - tx-clock = <18>; - }; - - cpm@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - device_type = "cpm"; - model = "CPM2"; - ranges = <00000000 00000000 20000>; - reg = <0 20000>; - command-proc = <119c0>; - brg-frequency = <17D7840>; - cpm_clk = ; - - scc@11a00 { - device_type = "serial"; - compatible = "cpm_uart"; - model = "SCC"; - device-id = <1>; - reg = <11a00 20 8000 100>; - current-speed = <1c200>; - interrupts = <28 2>; + rx-clock = <17>; + tx-clock = <18>; + }; + + cpm@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "cpm"; + model = "CPM2"; + ranges = <00000000 00000000 20000>; + reg = <0 20000>; + command-proc = <119c0>; + brg-frequency = <17D7840>; + cpm_clk = ; + + scc@11a00 { + device_type = "serial"; + compatible = "cpm_uart"; + model = "SCC"; + device-id = <1>; + reg = <11a00 20 8000 100>; + current-speed = <1c200>; + interrupts = <28 2>; interrupt-parent = <&Cpm_pic>; - clock-setup = <0 00ffffff>; - rx-clock = <1>; - tx-clock = <1>; - }; - - scc@11a60 { - device_type = "serial"; - compatible = "cpm_uart"; - model = "SCC"; - device-id = <4>; - reg = <11a60 20 8300 100>; - current-speed = <1c200>; - interrupts = <2b 2>; + clock-setup = <0 00ffffff>; + rx-clock = <1>; + tx-clock = <1>; + }; + + scc@11a60 { + device_type = "serial"; + compatible = "cpm_uart"; + model = "SCC"; + device-id = <4>; + reg = <11a60 20 8300 100>; + current-speed = <1c200>; + interrupts = <2b 2>; interrupt-parent = <&Cpm_pic>; - clock-setup = <1b ffffff00>; - rx-clock = <4>; - tx-clock = <4>; - }; - - }; - cpm_pic:interrupt-controller@10c00 { - #address-cells = <0>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <10c00 80>; - built-in; - device_type = "cpm-pic"; - compatible = "CPM2"; - }; - pci@0500 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - compatible = "8272"; - device_type = "pci"; - reg = <10430 4dc>; - clock-frequency = <3f940aa>; - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x16 */ - b000 0 0 1 f8200000 40 8 - b000 0 0 2 f8200000 41 8 - b000 0 0 3 f8200000 42 8 - b000 0 0 4 f8200000 43 8 - - /* IDSEL 0x17 */ - b800 0 0 1 f8200000 43 8 - b800 0 0 2 f8200000 40 8 - b800 0 0 3 f8200000 41 8 - b800 0 0 4 f8200000 42 8 - - /* IDSEL 0x18 */ - c000 0 0 1 f8200000 42 8 - c000 0 0 2 f8200000 43 8 - c000 0 0 3 f8200000 40 8 - c000 0 0 4 f8200000 41 8>; + clock-setup = <1b ffffff00>; + rx-clock = <4>; + tx-clock = <4>; + }; + }; + + cpm_pic:interrupt-controller@10c00 { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <10c00 80>; + device_type = "cpm-pic"; + compatible = "CPM2"; + }; + + pci@0500 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "8272"; + device_type = "pci"; + reg = <10430 4dc>; + clock-frequency = <3f940aa>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x16 */ + b000 0 0 1 f8200000 40 8 + b000 0 0 2 f8200000 41 8 + b000 0 0 3 f8200000 42 8 + b000 0 0 4 f8200000 43 8 + + /* IDSEL 0x17 */ + b800 0 0 1 f8200000 43 8 + b800 0 0 2 f8200000 40 8 + b800 0 0 3 f8200000 41 8 + b800 0 0 4 f8200000 42 8 + + /* IDSEL 0x18 */ + c000 0 0 1 f8200000 42 8 + c000 0 0 2 f8200000 43 8 + c000 0 0 3 f8200000 40 8 + c000 0 0 4 f8200000 41 8>; interrupt-parent = <&Cpm_pic>; - interrupts = <14 8>; - bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 40000000 - 01000000 0 00000000 f6000000 0 02000000>; - }; + interrupts = <14 8>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 40000000 + 01000000 0 00000000 f6000000 0 02000000>; + }; /* May need to remove if on a part without crypto engine */ - crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; - reg = <30000 10000>; - interrupts = ; + crypto@30000 { + device_type = "crypto"; + model = "SEC2"; + compatible = "talitos"; + reg = <30000 10000>; + interrupts = ; interrupt-parent = <&Cpm_pic>; - num-channels = <4>; - channel-fifo-len = <18>; - exec-units-mask = <0000007e>; + num-channels = <4>; + channel-fifo-len = <18>; + exec-units-mask = <0000007e>; /* desc mask is for rev1.x, we need runtime fixup for >=2.x */ - descriptor-types-mask = <01010ebf>; - }; - - }; + descriptor-types-mask = <01010ebf>; + }; + }; }; diff -puN arch/powerpc/boot/dts/mpc8313erdb.dts~git-powerpc arch/powerpc/boot/dts/mpc8313erdb.dts --- a/arch/powerpc/boot/dts/mpc8313erdb.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -29,7 +29,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; }; @@ -41,7 +40,6 @@ soc8313@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -152,36 +150,6 @@ interrupt-parent = < &ipic >; }; - pci@8500 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x0E -mini PCI */ - 7000 0 0 1 &ipic 12 8 - 7000 0 0 2 &ipic 12 8 - 7000 0 0 3 &ipic 12 8 - 7000 0 0 4 &ipic 12 8 - - /* IDSEL 0x0F - PCI slot */ - 7800 0 0 1 &ipic 11 8 - 7800 0 0 2 &ipic 12 8 - 7800 0 0 3 &ipic 11 8 - 7800 0 0 4 &ipic 12 8>; - interrupt-parent = < &ipic >; - interrupts = <42 8>; - bus-range = <0 0>; - ranges = <02000000 0 90000000 90000000 0 10000000 - 42000000 0 80000000 80000000 0 10000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8500 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - crypto@30000 { device_type = "crypto"; model = "SEC2"; @@ -207,8 +175,37 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; }; + + pci@e0008500 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x0E -mini PCI */ + 7000 0 0 1 &ipic 12 8 + 7000 0 0 2 &ipic 12 8 + 7000 0 0 3 &ipic 12 8 + 7000 0 0 4 &ipic 12 8 + + /* IDSEL 0x0F - PCI slot */ + 7800 0 0 1 &ipic 11 8 + 7800 0 0 2 &ipic 12 8 + 7800 0 0 3 &ipic 11 8 + 7800 0 0 4 &ipic 12 8>; + interrupt-parent = < &ipic >; + interrupts = <42 8>; + bus-range = <0 0>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 42000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc832x_mds.dts~git-powerpc arch/powerpc/boot/dts/mpc832x_mds.dts --- a/arch/powerpc/boot/dts/mpc832x_mds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -29,7 +29,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; }; @@ -46,7 +45,6 @@ soc8323@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -99,71 +97,11 @@ descriptor-types-mask = <0122003f>; }; - pci@8500 { - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x11 AD17 */ - 8800 0 0 1 &ipic 14 8 - 8800 0 0 2 &ipic 15 8 - 8800 0 0 3 &ipic 16 8 - 8800 0 0 4 &ipic 17 8 - - /* IDSEL 0x12 AD18 */ - 9000 0 0 1 &ipic 16 8 - 9000 0 0 2 &ipic 17 8 - 9000 0 0 3 &ipic 14 8 - 9000 0 0 4 &ipic 15 8 - - /* IDSEL 0x13 AD19 */ - 9800 0 0 1 &ipic 17 8 - 9800 0 0 2 &ipic 14 8 - 9800 0 0 3 &ipic 15 8 - 9800 0 0 4 &ipic 16 8 - - /* IDSEL 0x15 AD21*/ - a800 0 0 1 &ipic 14 8 - a800 0 0 2 &ipic 15 8 - a800 0 0 3 &ipic 16 8 - a800 0 0 4 &ipic 17 8 - - /* IDSEL 0x16 AD22*/ - b000 0 0 1 &ipic 17 8 - b000 0 0 2 &ipic 14 8 - b000 0 0 3 &ipic 15 8 - b000 0 0 4 &ipic 16 8 - - /* IDSEL 0x17 AD23*/ - b800 0 0 1 &ipic 16 8 - b800 0 0 2 &ipic 17 8 - b800 0 0 3 &ipic 14 8 - b800 0 0 4 &ipic 15 8 - - /* IDSEL 0x18 AD24*/ - c000 0 0 1 &ipic 15 8 - c000 0 0 2 &ipic 16 8 - c000 0 0 3 &ipic 17 8 - c000 0 0 4 &ipic 14 8>; - interrupt-parent = < &ipic >; - interrupts = <42 8>; - bus-range = <0 0>; - ranges = <02000000 0 90000000 90000000 0 10000000 - 42000000 0 80000000 80000000 0 10000000 - 01000000 0 00000000 d0000000 0 00100000>; - clock-frequency = <0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8500 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - ipic: pic@700 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; @@ -333,10 +271,68 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <20 8 21 8>; //high:32 low:33 interrupt-parent = < &ipic >; }; }; + + pci@e0008500 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x11 AD17 */ + 8800 0 0 1 &ipic 14 8 + 8800 0 0 2 &ipic 15 8 + 8800 0 0 3 &ipic 16 8 + 8800 0 0 4 &ipic 17 8 + + /* IDSEL 0x12 AD18 */ + 9000 0 0 1 &ipic 16 8 + 9000 0 0 2 &ipic 17 8 + 9000 0 0 3 &ipic 14 8 + 9000 0 0 4 &ipic 15 8 + + /* IDSEL 0x13 AD19 */ + 9800 0 0 1 &ipic 17 8 + 9800 0 0 2 &ipic 14 8 + 9800 0 0 3 &ipic 15 8 + 9800 0 0 4 &ipic 16 8 + + /* IDSEL 0x15 AD21*/ + a800 0 0 1 &ipic 14 8 + a800 0 0 2 &ipic 15 8 + a800 0 0 3 &ipic 16 8 + a800 0 0 4 &ipic 17 8 + + /* IDSEL 0x16 AD22*/ + b000 0 0 1 &ipic 17 8 + b000 0 0 2 &ipic 14 8 + b000 0 0 3 &ipic 15 8 + b000 0 0 4 &ipic 16 8 + + /* IDSEL 0x17 AD23*/ + b800 0 0 1 &ipic 16 8 + b800 0 0 2 &ipic 17 8 + b800 0 0 3 &ipic 14 8 + b800 0 0 4 &ipic 15 8 + + /* IDSEL 0x18 AD24*/ + c000 0 0 1 &ipic 15 8 + c000 0 0 2 &ipic 16 8 + c000 0 0 3 &ipic 17 8 + c000 0 0 4 &ipic 14 8>; + interrupt-parent = < &ipic >; + interrupts = <42 8>; + bus-range = <0 0>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 42000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 d0000000 0 00100000>; + clock-frequency = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc832x_rdb.dts~git-powerpc arch/powerpc/boot/dts/mpc832x_rdb.dts --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -29,7 +29,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; }; @@ -41,7 +40,6 @@ soc8323@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -94,45 +92,11 @@ descriptor-types-mask = <0122003f>; }; - pci@8500 { - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x10 AD16 (USB) */ - 8000 0 0 1 &pic 11 8 - - /* IDSEL 0x11 AD17 (Mini1)*/ - 8800 0 0 1 &pic 12 8 - 8800 0 0 2 &pic 13 8 - 8800 0 0 3 &pic 14 8 - 8800 0 0 4 &pic 30 8 - - /* IDSEL 0x12 AD18 (PCI/Mini2) */ - 9000 0 0 1 &pic 13 8 - 9000 0 0 2 &pic 14 8 - 9000 0 0 3 &pic 30 8 - 9000 0 0 4 &pic 11 8>; - - interrupt-parent = <&pic>; - interrupts = <42 8>; - bus-range = <0 0>; - ranges = <42000000 0 80000000 80000000 0 10000000 - 02000000 0 90000000 90000000 0 10000000 - 01000000 0 d0000000 d0000000 0 04000000>; - clock-frequency = <0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8500 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - pic:pic@700 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; @@ -211,7 +175,7 @@ reg = <4c0 40>; interrupts = <2>; interrupt-parent = <&qeic>; - mode = "cpu"; + mode = "cpu-qe"; }; spi@500 { @@ -292,10 +256,42 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <20 8 21 8>; //high:32 low:33 interrupt-parent = <&pic>; }; }; + + pci@e0008500 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x10 AD16 (USB) */ + 8000 0 0 1 &pic 11 8 + + /* IDSEL 0x11 AD17 (Mini1)*/ + 8800 0 0 1 &pic 12 8 + 8800 0 0 2 &pic 13 8 + 8800 0 0 3 &pic 14 8 + 8800 0 0 4 &pic 30 8 + + /* IDSEL 0x12 AD18 (PCI/Mini2) */ + 9000 0 0 1 &pic 13 8 + 9000 0 0 2 &pic 14 8 + 9000 0 0 3 &pic 30 8 + 9000 0 0 4 &pic 11 8>; + + interrupt-parent = <&pic>; + interrupts = <42 8>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 10000000 + 02000000 0 90000000 90000000 0 10000000 + 01000000 0 d0000000 d0000000 0 04000000>; + clock-frequency = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc8349emitx.dts~git-powerpc arch/powerpc/boot/dts/mpc8349emitx.dts --- a/arch/powerpc/boot/dts/mpc8349emitx.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -28,7 +28,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; }; @@ -40,7 +39,6 @@ soc8349@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -180,52 +178,6 @@ interrupt-parent = < &ipic >; }; - pci@8500 { - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x10 - SATA */ - 8000 0 0 1 &ipic 16 8 /* SATA_INTA */ - >; - interrupt-parent = < &ipic >; - interrupts = <42 8>; - bus-range = <0 0>; - ranges = <42000000 0 80000000 80000000 0 10000000 - 02000000 0 90000000 90000000 0 10000000 - 01000000 0 00000000 e2000000 0 01000000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8500 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - - pci@8600 { - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x0E - MiniPCI Slot */ - 7000 0 0 1 &ipic 15 8 /* PCI_INTA */ - - /* IDSEL 0x0F - PCI Slot */ - 7800 0 0 1 &ipic 14 8 /* PCI_INTA */ - 7800 0 0 2 &ipic 15 8 /* PCI_INTB */ - >; - interrupt-parent = < &ipic >; - interrupts = <43 8>; - bus-range = <1 1>; - ranges = <42000000 0 a0000000 a0000000 0 10000000 - 02000000 0 b0000000 b0000000 0 10000000 - 01000000 0 00000000 e3000000 0 01000000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8600 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - crypto@30000 { device_type = "crypto"; model = "SEC2"; @@ -244,8 +196,56 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; }; + + pci@e0008500 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x10 - SATA */ + 8000 0 0 1 &ipic 16 8 /* SATA_INTA */ + >; + interrupt-parent = < &ipic >; + interrupts = <42 8>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 10000000 + 02000000 0 90000000 90000000 0 10000000 + 01000000 0 00000000 e2000000 0 01000000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; + + pci@e0008600 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0E - MiniPCI Slot */ + 7000 0 0 1 &ipic 15 8 /* PCI_INTA */ + + /* IDSEL 0x0F - PCI Slot */ + 7800 0 0 1 &ipic 14 8 /* PCI_INTA */ + 7800 0 0 2 &ipic 15 8 /* PCI_INTB */ + >; + interrupt-parent = < &ipic >; + interrupts = <43 8>; + bus-range = <0 0>; + ranges = <42000000 0 a0000000 a0000000 0 10000000 + 02000000 0 b0000000 b0000000 0 10000000 + 01000000 0 00000000 e3000000 0 01000000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; + + + }; diff -puN arch/powerpc/boot/dts/mpc8349emitxgp.dts~git-powerpc arch/powerpc/boot/dts/mpc8349emitxgp.dts --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -28,7 +28,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; }; @@ -40,7 +39,6 @@ soc8349@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -136,28 +134,6 @@ interrupt-parent = < &ipic >; }; - pci@8600 { - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x0F - PCI Slot */ - 7800 0 0 1 &ipic 14 8 /* PCI_INTA */ - 7800 0 0 2 &ipic 15 8 /* PCI_INTB */ - >; - interrupt-parent = < &ipic >; - interrupts = <43 8>; - bus-range = <1 1>; - ranges = <42000000 0 a0000000 a0000000 0 10000000 - 02000000 0 b0000000 b0000000 0 10000000 - 01000000 0 00000000 e3000000 0 01000000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8600 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - crypto@30000 { device_type = "crypto"; model = "SEC2"; @@ -176,8 +152,29 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; }; + + pci@e0008600 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0F - PCI Slot */ + 7800 0 0 1 &ipic 14 8 /* PCI_INTA */ + 7800 0 0 2 &ipic 15 8 /* PCI_INTB */ + >; + interrupt-parent = < &ipic >; + interrupts = <43 8>; + bus-range = <1 1>; + ranges = <42000000 0 a0000000 a0000000 0 10000000 + 02000000 0 b0000000 b0000000 0 10000000 + 01000000 0 00000000 e3000000 0 01000000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc834x_mds.dts~git-powerpc arch/powerpc/boot/dts/mpc834x_mds.dts --- a/arch/powerpc/boot/dts/mpc834x_mds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -29,7 +29,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; }; @@ -46,7 +45,6 @@ soc8349@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -185,126 +183,6 @@ interrupt-parent = < &ipic >; }; - pci@8500 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x11 */ - 8800 0 0 1 &ipic 14 8 - 8800 0 0 2 &ipic 15 8 - 8800 0 0 3 &ipic 16 8 - 8800 0 0 4 &ipic 17 8 - - /* IDSEL 0x12 */ - 9000 0 0 1 &ipic 16 8 - 9000 0 0 2 &ipic 17 8 - 9000 0 0 3 &ipic 14 8 - 9000 0 0 4 &ipic 15 8 - - /* IDSEL 0x13 */ - 9800 0 0 1 &ipic 17 8 - 9800 0 0 2 &ipic 14 8 - 9800 0 0 3 &ipic 15 8 - 9800 0 0 4 &ipic 16 8 - - /* IDSEL 0x15 */ - a800 0 0 1 &ipic 14 8 - a800 0 0 2 &ipic 15 8 - a800 0 0 3 &ipic 16 8 - a800 0 0 4 &ipic 17 8 - - /* IDSEL 0x16 */ - b000 0 0 1 &ipic 17 8 - b000 0 0 2 &ipic 14 8 - b000 0 0 3 &ipic 15 8 - b000 0 0 4 &ipic 16 8 - - /* IDSEL 0x17 */ - b800 0 0 1 &ipic 16 8 - b800 0 0 2 &ipic 17 8 - b800 0 0 3 &ipic 14 8 - b800 0 0 4 &ipic 15 8 - - /* IDSEL 0x18 */ - c000 0 0 1 &ipic 15 8 - c000 0 0 2 &ipic 16 8 - c000 0 0 3 &ipic 17 8 - c000 0 0 4 &ipic 14 8>; - interrupt-parent = < &ipic >; - interrupts = <42 8>; - bus-range = <0 0>; - ranges = <02000000 0 90000000 90000000 0 10000000 - 42000000 0 80000000 80000000 0 10000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8500 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - - pci@8600 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x11 */ - 8800 0 0 1 &ipic 14 8 - 8800 0 0 2 &ipic 15 8 - 8800 0 0 3 &ipic 16 8 - 8800 0 0 4 &ipic 17 8 - - /* IDSEL 0x12 */ - 9000 0 0 1 &ipic 16 8 - 9000 0 0 2 &ipic 17 8 - 9000 0 0 3 &ipic 14 8 - 9000 0 0 4 &ipic 15 8 - - /* IDSEL 0x13 */ - 9800 0 0 1 &ipic 17 8 - 9800 0 0 2 &ipic 14 8 - 9800 0 0 3 &ipic 15 8 - 9800 0 0 4 &ipic 16 8 - - /* IDSEL 0x15 */ - a800 0 0 1 &ipic 14 8 - a800 0 0 2 &ipic 15 8 - a800 0 0 3 &ipic 16 8 - a800 0 0 4 &ipic 17 8 - - /* IDSEL 0x16 */ - b000 0 0 1 &ipic 17 8 - b000 0 0 2 &ipic 14 8 - b000 0 0 3 &ipic 15 8 - b000 0 0 4 &ipic 16 8 - - /* IDSEL 0x17 */ - b800 0 0 1 &ipic 16 8 - b800 0 0 2 &ipic 17 8 - b800 0 0 3 &ipic 14 8 - b800 0 0 4 &ipic 15 8 - - /* IDSEL 0x18 */ - c000 0 0 1 &ipic 15 8 - c000 0 0 2 &ipic 16 8 - c000 0 0 3 &ipic 17 8 - c000 0 0 4 &ipic 14 8>; - interrupt-parent = < &ipic >; - interrupts = <42 8>; - bus-range = <0 0>; - ranges = <02000000 0 b0000000 b0000000 0 10000000 - 42000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 e2100000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8600 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - /* May need to remove if on a part without crypto engine */ crypto@30000 { device_type = "crypto"; @@ -332,8 +210,127 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; }; + + pci@e0008500 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x11 */ + 8800 0 0 1 &ipic 14 8 + 8800 0 0 2 &ipic 15 8 + 8800 0 0 3 &ipic 16 8 + 8800 0 0 4 &ipic 17 8 + + /* IDSEL 0x12 */ + 9000 0 0 1 &ipic 16 8 + 9000 0 0 2 &ipic 17 8 + 9000 0 0 3 &ipic 14 8 + 9000 0 0 4 &ipic 15 8 + + /* IDSEL 0x13 */ + 9800 0 0 1 &ipic 17 8 + 9800 0 0 2 &ipic 14 8 + 9800 0 0 3 &ipic 15 8 + 9800 0 0 4 &ipic 16 8 + + /* IDSEL 0x15 */ + a800 0 0 1 &ipic 14 8 + a800 0 0 2 &ipic 15 8 + a800 0 0 3 &ipic 16 8 + a800 0 0 4 &ipic 17 8 + + /* IDSEL 0x16 */ + b000 0 0 1 &ipic 17 8 + b000 0 0 2 &ipic 14 8 + b000 0 0 3 &ipic 15 8 + b000 0 0 4 &ipic 16 8 + + /* IDSEL 0x17 */ + b800 0 0 1 &ipic 16 8 + b800 0 0 2 &ipic 17 8 + b800 0 0 3 &ipic 14 8 + b800 0 0 4 &ipic 15 8 + + /* IDSEL 0x18 */ + c000 0 0 1 &ipic 15 8 + c000 0 0 2 &ipic 16 8 + c000 0 0 3 &ipic 17 8 + c000 0 0 4 &ipic 14 8>; + interrupt-parent = < &ipic >; + interrupts = <42 8>; + bus-range = <0 0>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 42000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; + + pci@e0008600 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x11 */ + 8800 0 0 1 &ipic 14 8 + 8800 0 0 2 &ipic 15 8 + 8800 0 0 3 &ipic 16 8 + 8800 0 0 4 &ipic 17 8 + + /* IDSEL 0x12 */ + 9000 0 0 1 &ipic 16 8 + 9000 0 0 2 &ipic 17 8 + 9000 0 0 3 &ipic 14 8 + 9000 0 0 4 &ipic 15 8 + + /* IDSEL 0x13 */ + 9800 0 0 1 &ipic 17 8 + 9800 0 0 2 &ipic 14 8 + 9800 0 0 3 &ipic 15 8 + 9800 0 0 4 &ipic 16 8 + + /* IDSEL 0x15 */ + a800 0 0 1 &ipic 14 8 + a800 0 0 2 &ipic 15 8 + a800 0 0 3 &ipic 16 8 + a800 0 0 4 &ipic 17 8 + + /* IDSEL 0x16 */ + b000 0 0 1 &ipic 17 8 + b000 0 0 2 &ipic 14 8 + b000 0 0 3 &ipic 15 8 + b000 0 0 4 &ipic 16 8 + + /* IDSEL 0x17 */ + b800 0 0 1 &ipic 16 8 + b800 0 0 2 &ipic 17 8 + b800 0 0 3 &ipic 14 8 + b800 0 0 4 &ipic 15 8 + + /* IDSEL 0x18 */ + c000 0 0 1 &ipic 15 8 + c000 0 0 2 &ipic 16 8 + c000 0 0 3 &ipic 17 8 + c000 0 0 4 &ipic 14 8>; + interrupt-parent = < &ipic >; + interrupts = <42 8>; + bus-range = <0 0>; + ranges = <02000000 0 b0000000 b0000000 0 10000000 + 42000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 e2100000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc836x_mds.dts~git-powerpc arch/powerpc/boot/dts/mpc836x_mds.dts --- a/arch/powerpc/boot/dts/mpc836x_mds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -34,7 +34,6 @@ timebase-frequency = <3EF1480>; bus-frequency = ; clock-frequency = <1F78A400>; - 32-bit; }; }; @@ -51,7 +50,6 @@ soc8360@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -113,72 +111,11 @@ descriptor-types-mask = <01010ebf>; }; - pci@8500 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x11 AD17 */ - 8800 0 0 1 &ipic 14 8 - 8800 0 0 2 &ipic 15 8 - 8800 0 0 3 &ipic 16 8 - 8800 0 0 4 &ipic 17 8 - - /* IDSEL 0x12 AD18 */ - 9000 0 0 1 &ipic 16 8 - 9000 0 0 2 &ipic 17 8 - 9000 0 0 3 &ipic 14 8 - 9000 0 0 4 &ipic 15 8 - - /* IDSEL 0x13 AD19 */ - 9800 0 0 1 &ipic 17 8 - 9800 0 0 2 &ipic 14 8 - 9800 0 0 3 &ipic 15 8 - 9800 0 0 4 &ipic 16 8 - - /* IDSEL 0x15 AD21*/ - a800 0 0 1 &ipic 14 8 - a800 0 0 2 &ipic 15 8 - a800 0 0 3 &ipic 16 8 - a800 0 0 4 &ipic 17 8 - - /* IDSEL 0x16 AD22*/ - b000 0 0 1 &ipic 17 8 - b000 0 0 2 &ipic 14 8 - b000 0 0 3 &ipic 15 8 - b000 0 0 4 &ipic 16 8 - - /* IDSEL 0x17 AD23*/ - b800 0 0 1 &ipic 16 8 - b800 0 0 2 &ipic 17 8 - b800 0 0 3 &ipic 14 8 - b800 0 0 4 &ipic 15 8 - - /* IDSEL 0x18 AD24*/ - c000 0 0 1 &ipic 15 8 - c000 0 0 2 &ipic 16 8 - c000 0 0 3 &ipic 17 8 - c000 0 0 4 &ipic 14 8>; - interrupt-parent = < &ipic >; - interrupts = <42 8>; - bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 10000000 - 42000000 0 80000000 80000000 0 10000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8500 100>; - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; - ipic: pic@700 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; @@ -364,11 +301,69 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <20 8 21 8>; //high:32 low:33 interrupt-parent = < &ipic >; }; + }; + pci@e0008500 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x11 AD17 */ + 8800 0 0 1 &ipic 14 8 + 8800 0 0 2 &ipic 15 8 + 8800 0 0 3 &ipic 16 8 + 8800 0 0 4 &ipic 17 8 + + /* IDSEL 0x12 AD18 */ + 9000 0 0 1 &ipic 16 8 + 9000 0 0 2 &ipic 17 8 + 9000 0 0 3 &ipic 14 8 + 9000 0 0 4 &ipic 15 8 + + /* IDSEL 0x13 AD19 */ + 9800 0 0 1 &ipic 17 8 + 9800 0 0 2 &ipic 14 8 + 9800 0 0 3 &ipic 15 8 + 9800 0 0 4 &ipic 16 8 + + /* IDSEL 0x15 AD21*/ + a800 0 0 1 &ipic 14 8 + a800 0 0 2 &ipic 15 8 + a800 0 0 3 &ipic 16 8 + a800 0 0 4 &ipic 17 8 + + /* IDSEL 0x16 AD22*/ + b000 0 0 1 &ipic 17 8 + b000 0 0 2 &ipic 14 8 + b000 0 0 3 &ipic 15 8 + b000 0 0 4 &ipic 16 8 + + /* IDSEL 0x17 AD23*/ + b800 0 0 1 &ipic 16 8 + b800 0 0 2 &ipic 17 8 + b800 0 0 3 &ipic 14 8 + b800 0 0 4 &ipic 15 8 + + /* IDSEL 0x18 AD24*/ + c000 0 0 1 &ipic 15 8 + c000 0 0 2 &ipic 16 8 + c000 0 0 3 &ipic 17 8 + c000 0 0 4 &ipic 14 8>; + interrupt-parent = < &ipic >; + interrupts = <42 8>; + bus-range = <0 0>; + ranges = <02000000 0 a0000000 a0000000 0 10000000 + 42000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; }; }; diff -puN arch/powerpc/boot/dts/mpc8540ads.dts~git-powerpc arch/powerpc/boot/dts/mpc8540ads.dts --- a/arch/powerpc/boot/dts/mpc8540ads.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8540ads.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; }; @@ -42,7 +41,6 @@ soc8540@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; // CCSRBAR 1M @@ -173,105 +171,104 @@ interrupts = <2a 2>; interrupt-parent = <&mpic>; }; - pci@8000 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x02 */ - 1000 0 0 1 &mpic 1 1 - 1000 0 0 2 &mpic 2 1 - 1000 0 0 3 &mpic 3 1 - 1000 0 0 4 &mpic 4 1 - - /* IDSEL 0x03 */ - 1800 0 0 1 &mpic 4 1 - 1800 0 0 2 &mpic 1 1 - 1800 0 0 3 &mpic 2 1 - 1800 0 0 4 &mpic 3 1 - - /* IDSEL 0x04 */ - 2000 0 0 1 &mpic 3 1 - 2000 0 0 2 &mpic 4 1 - 2000 0 0 3 &mpic 1 1 - 2000 0 0 4 &mpic 2 1 - - /* IDSEL 0x05 */ - 2800 0 0 1 &mpic 2 1 - 2800 0 0 2 &mpic 3 1 - 2800 0 0 3 &mpic 4 1 - 2800 0 0 4 &mpic 1 1 - - /* IDSEL 0x0c */ - 6000 0 0 1 &mpic 1 1 - 6000 0 0 2 &mpic 2 1 - 6000 0 0 3 &mpic 3 1 - 6000 0 0 4 &mpic 4 1 - - /* IDSEL 0x0d */ - 6800 0 0 1 &mpic 4 1 - 6800 0 0 2 &mpic 1 1 - 6800 0 0 3 &mpic 2 1 - 6800 0 0 4 &mpic 3 1 - - /* IDSEL 0x0e */ - 7000 0 0 1 &mpic 3 1 - 7000 0 0 2 &mpic 4 1 - 7000 0 0 3 &mpic 1 1 - 7000 0 0 4 &mpic 2 1 - - /* IDSEL 0x0f */ - 7800 0 0 1 &mpic 2 1 - 7800 0 0 2 &mpic 3 1 - 7800 0 0 3 &mpic 4 1 - 7800 0 0 4 &mpic 1 1 - - /* IDSEL 0x12 */ - 9000 0 0 1 &mpic 1 1 - 9000 0 0 2 &mpic 2 1 - 9000 0 0 3 &mpic 3 1 - 9000 0 0 4 &mpic 4 1 - - /* IDSEL 0x13 */ - 9800 0 0 1 &mpic 4 1 - 9800 0 0 2 &mpic 1 1 - 9800 0 0 3 &mpic 2 1 - 9800 0 0 4 &mpic 3 1 - - /* IDSEL 0x14 */ - a000 0 0 1 &mpic 3 1 - a000 0 0 2 &mpic 4 1 - a000 0 0 3 &mpic 1 1 - a000 0 0 4 &mpic 2 1 - - /* IDSEL 0x15 */ - a800 0 0 1 &mpic 2 1 - a800 0 0 2 &mpic 3 1 - a800 0 0 3 &mpic 4 1 - a800 0 0 4 &mpic 1 1>; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; - compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; - device_type = "pci"; - }; - mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; }; }; + + pci@e0008000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x02 */ + 1000 0 0 1 &mpic 1 1 + 1000 0 0 2 &mpic 2 1 + 1000 0 0 3 &mpic 3 1 + 1000 0 0 4 &mpic 4 1 + + /* IDSEL 0x03 */ + 1800 0 0 1 &mpic 4 1 + 1800 0 0 2 &mpic 1 1 + 1800 0 0 3 &mpic 2 1 + 1800 0 0 4 &mpic 3 1 + + /* IDSEL 0x04 */ + 2000 0 0 1 &mpic 3 1 + 2000 0 0 2 &mpic 4 1 + 2000 0 0 3 &mpic 1 1 + 2000 0 0 4 &mpic 2 1 + + /* IDSEL 0x05 */ + 2800 0 0 1 &mpic 2 1 + 2800 0 0 2 &mpic 3 1 + 2800 0 0 3 &mpic 4 1 + 2800 0 0 4 &mpic 1 1 + + /* IDSEL 0x0c */ + 6000 0 0 1 &mpic 1 1 + 6000 0 0 2 &mpic 2 1 + 6000 0 0 3 &mpic 3 1 + 6000 0 0 4 &mpic 4 1 + + /* IDSEL 0x0d */ + 6800 0 0 1 &mpic 4 1 + 6800 0 0 2 &mpic 1 1 + 6800 0 0 3 &mpic 2 1 + 6800 0 0 4 &mpic 3 1 + + /* IDSEL 0x0e */ + 7000 0 0 1 &mpic 3 1 + 7000 0 0 2 &mpic 4 1 + 7000 0 0 3 &mpic 1 1 + 7000 0 0 4 &mpic 2 1 + + /* IDSEL 0x0f */ + 7800 0 0 1 &mpic 2 1 + 7800 0 0 2 &mpic 3 1 + 7800 0 0 3 &mpic 4 1 + 7800 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 */ + 9000 0 0 1 &mpic 1 1 + 9000 0 0 2 &mpic 2 1 + 9000 0 0 3 &mpic 3 1 + 9000 0 0 4 &mpic 4 1 + + /* IDSEL 0x13 */ + 9800 0 0 1 &mpic 4 1 + 9800 0 0 2 &mpic 1 1 + 9800 0 0 3 &mpic 2 1 + 9800 0 0 4 &mpic 3 1 + + /* IDSEL 0x14 */ + a000 0 0 1 &mpic 3 1 + a000 0 0 2 &mpic 4 1 + a000 0 0 3 &mpic 1 1 + a000 0 0 4 &mpic 2 1 + + /* IDSEL 0x15 */ + a800 0 0 1 &mpic 2 1 + a800 0 0 2 &mpic 3 1 + a800 0 0 3 &mpic 4 1 + a800 0 0 4 &mpic 1 1>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc8541cds.dts~git-powerpc arch/powerpc/boot/dts/mpc8541cds.dts --- a/arch/powerpc/boot/dts/mpc8541cds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8541cds.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; }; @@ -42,10 +41,9 @@ soc8541@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; - reg = ; // CCSRBAR 1M + reg = ; // CCSRBAR 1M bus-frequency = <0>; memory-controller@2000 { @@ -137,113 +135,109 @@ interrupt-parent = <&mpic>; }; - pci1: pci@8000 { - interrupt-map-mask = <1f800 0 0 7>; - interrupt-map = < - - /* IDSEL 0x10 */ - 08000 0 0 1 &mpic 0 1 - 08000 0 0 2 &mpic 1 1 - 08000 0 0 3 &mpic 2 1 - 08000 0 0 4 &mpic 3 1 - - /* IDSEL 0x11 */ - 08800 0 0 1 &mpic 0 1 - 08800 0 0 2 &mpic 1 1 - 08800 0 0 3 &mpic 2 1 - 08800 0 0 4 &mpic 3 1 - - /* IDSEL 0x12 (Slot 1) */ - 09000 0 0 1 &mpic 0 1 - 09000 0 0 2 &mpic 1 1 - 09000 0 0 3 &mpic 2 1 - 09000 0 0 4 &mpic 3 1 - - /* IDSEL 0x13 (Slot 2) */ - 09800 0 0 1 &mpic 1 1 - 09800 0 0 2 &mpic 2 1 - 09800 0 0 3 &mpic 3 1 - 09800 0 0 4 &mpic 0 1 - - /* IDSEL 0x14 (Slot 3) */ - 0a000 0 0 1 &mpic 2 1 - 0a000 0 0 2 &mpic 3 1 - 0a000 0 0 3 &mpic 0 1 - 0a000 0 0 4 &mpic 1 1 - - /* IDSEL 0x15 (Slot 4) */ - 0a800 0 0 1 &mpic 3 1 - 0a800 0 0 2 &mpic 0 1 - 0a800 0 0 3 &mpic 1 1 - 0a800 0 0 4 &mpic 2 1 - - /* Bus 1 (Tundra Bridge) */ - /* IDSEL 0x12 (ISA bridge) */ - 19000 0 0 1 &mpic 0 1 - 19000 0 0 2 &mpic 1 1 - 19000 0 0 3 &mpic 2 1 - 19000 0 0 4 &mpic 3 1>; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; - compatible = "fsl,mpc8540-pci"; - device_type = "pci"; - - i8259@19000 { - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - reg = <19000 0 0 0 1>; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <1>; - interrupt-parent = <&pci1>; - }; - }; - - pci@9000 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x15 */ - a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic b 1 - a800 0 0 3 &mpic b 1 - a800 0 0 4 &mpic b 1>; - interrupt-parent = <&mpic>; - interrupts = <19 2>; - bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <9000 1000>; - compatible = "fsl,mpc8540-pci"; - device_type = "pci"; - }; - mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; }; }; + + pci1: pci@e0008000 { + interrupt-map-mask = <1f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x10 */ + 08000 0 0 1 &mpic 0 1 + 08000 0 0 2 &mpic 1 1 + 08000 0 0 3 &mpic 2 1 + 08000 0 0 4 &mpic 3 1 + + /* IDSEL 0x11 */ + 08800 0 0 1 &mpic 0 1 + 08800 0 0 2 &mpic 1 1 + 08800 0 0 3 &mpic 2 1 + 08800 0 0 4 &mpic 3 1 + + /* IDSEL 0x12 (Slot 1) */ + 09000 0 0 1 &mpic 0 1 + 09000 0 0 2 &mpic 1 1 + 09000 0 0 3 &mpic 2 1 + 09000 0 0 4 &mpic 3 1 + + /* IDSEL 0x13 (Slot 2) */ + 09800 0 0 1 &mpic 1 1 + 09800 0 0 2 &mpic 2 1 + 09800 0 0 3 &mpic 3 1 + 09800 0 0 4 &mpic 0 1 + + /* IDSEL 0x14 (Slot 3) */ + 0a000 0 0 1 &mpic 2 1 + 0a000 0 0 2 &mpic 3 1 + 0a000 0 0 3 &mpic 0 1 + 0a000 0 0 4 &mpic 1 1 + + /* IDSEL 0x15 (Slot 4) */ + 0a800 0 0 1 &mpic 3 1 + 0a800 0 0 2 &mpic 0 1 + 0a800 0 0 3 &mpic 1 1 + 0a800 0 0 4 &mpic 2 1 + + /* Bus 1 (Tundra Bridge) */ + /* IDSEL 0x12 (ISA bridge) */ + 19000 0 0 1 &mpic 0 1 + 19000 0 0 2 &mpic 1 1 + 19000 0 0 3 &mpic 2 1 + 19000 0 0 4 &mpic 3 1>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + + i8259@19000 { + interrupt-controller; + device_type = "interrupt-controller"; + reg = <19000 0 0 0 1>; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + interrupts = <1>; + interrupt-parent = <&pci1>; + }; + }; + + pci@e0009000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x15 */ + a800 0 0 1 &mpic b 1 + a800 0 0 2 &mpic b 1 + a800 0 0 3 &mpic b 1 + a800 0 0 4 &mpic b 1>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + bus-range = <0 0>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc8544ds.dts~git-powerpc arch/powerpc/boot/dts/mpc8544ds.dts --- a/arch/powerpc/boot/dts/mpc8544ds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8544ds.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; }; @@ -42,19 +41,9 @@ soc8544@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; - - ranges = <00001000 e0001000 000ff000 - 80000000 80000000 20000000 - a0000000 a0000000 10000000 - b0000000 b0000000 00100000 - c0000000 c0000000 20000000 - b0100000 b0100000 00100000 - e1000000 e1000000 00010000 - e1010000 e1010000 00010000 - e1020000 e1020000 00010000>; + ranges = <00000000 e0000000 00100000>; reg = ; // CCSRBAR 1M bus-frequency = <0>; // Filled out by uboot. @@ -149,115 +138,173 @@ interrupt-parent = <&mpic>; }; - pci@8000 { - compatible = "fsl,mpc8540-pci"; - device_type = "pci"; - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x11 J17 Slot 1 */ - 8800 0 0 1 &mpic 2 1 - 8800 0 0 2 &mpic 3 1 - 8800 0 0 3 &mpic 4 1 - 8800 0 0 4 &mpic 1 1 - - /* IDSEL 0x12 J16 Slot 2 */ - - 9000 0 0 1 &mpic 3 1 - 9000 0 0 2 &mpic 4 1 - 9000 0 0 3 &mpic 2 1 - 9000 0 0 4 &mpic 1 1>; + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8548-guts"; + reg = ; + fsl,has-rstcr; + }; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 ff>; - ranges = <02000000 0 c0000000 c0000000 0 20000000 - 01000000 0 00000000 e1000000 0 00010000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; }; + }; - pcie@9000 { - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; + pci@e0008000 { + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x11 J17 Slot 1 */ + 8800 0 0 1 &mpic 2 1 + 8800 0 0 2 &mpic 3 1 + 8800 0 0 3 &mpic 4 1 + 8800 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 J16 Slot 2 */ + + 9000 0 0 1 &mpic 3 1 + 9000 0 0 2 &mpic 4 1 + 9000 0 0 3 &mpic 2 1 + 9000 0 0 4 &mpic 1 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 ff>; + ranges = <02000000 0 c0000000 c0000000 0 20000000 + 01000000 0 00000000 e1000000 0 00010000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + }; + + pcie@e0009000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e1010000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; - reg = <9000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e1010000 0 00010000>; - clock-frequency = <1fca055>; - interrupt-parent = <&mpic>; - interrupts = <1a 2>; - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 4 1 - 0000 0 0 2 &mpic 5 1 - 0000 0 0 3 &mpic 6 1 - 0000 0 0 4 &mpic 7 1 - >; + device_type = "pci"; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00010000>; }; + }; - pcie@a000 { - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; + pcie@e000a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 e1020000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; - reg = ; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 e1020000 0 00010000>; - clock-frequency = <1fca055>; - interrupt-parent = <&mpic>; - interrupts = <19 2>; - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 0 1 - 0000 0 0 2 &mpic 1 1 - 0000 0 0 3 &mpic 2 1 - 0000 0 0 4 &mpic 3 1 - >; + device_type = "pci"; + ranges = <02000000 0 a0000000 + 02000000 0 a0000000 + 0 10000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00010000>; }; + }; - pcie@b000 { - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; + pcie@e000b000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 b0000000 b0000000 0 00100000 + 01000000 0 00000000 b0100000 0 00100000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1b 2>; + interrupt-map-mask = ; + interrupt-map = < + // IDSEL 0x1c USB + e000 0 0 0 &i8259 c 2 + e100 0 0 0 &i8259 9 2 + e200 0 0 0 &i8259 a 2 + e300 0 0 0 &i8259 b 2 + + // IDSEL 0x1d Audio + e800 0 0 0 &i8259 6 2 + + // IDSEL 0x1e Legacy + f000 0 0 0 &i8259 7 2 + f100 0 0 0 &i8259 7 2 + + // IDSEL 0x1f IDE/SATA + f800 0 0 0 &i8259 e 2 + f900 0 0 0 &i8259 5 2 + >; + + pcie@0 { + reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; - reg = ; - bus-range = <0 ff>; - ranges = <02000000 0 b0000000 b0000000 0 00100000 - 01000000 0 00000000 b0100000 0 00100000>; - clock-frequency = <1fca055>; - interrupt-parent = <&mpic>; - interrupts = <1b 2>; - interrupt-map-mask = ; - interrupt-map = < - // IDSEL 0x1c USB - e000 0 0 0 &i8259 c 2 - e100 0 0 0 &i8259 9 2 - e200 0 0 0 &i8259 a 2 - e300 0 0 0 &i8259 b 2 - - // IDSEL 0x1d Audio - e800 0 0 0 &i8259 6 2 - - // IDSEL 0x1e Legacy - f000 0 0 0 &i8259 7 2 - f100 0 0 0 &i8259 7 2 - - // IDSEL 0x1f IDE/SATA - f800 0 0 0 &i8259 e 2 - f900 0 0 0 &i8259 5 2 - >; + device_type = "pci"; + ranges = <02000000 0 b0000000 + 02000000 0 b0000000 + 0 00100000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + uli1575@0 { reg = <0 0 0 0 0>; #size-cells = <2>; @@ -265,95 +312,63 @@ ranges = <02000000 0 b0000000 02000000 0 b0000000 0 00100000 + 01000000 0 00000000 01000000 0 00000000 0 00100000>; - - pci_bridge@0 { - reg = <0 0 0 0 0>; - #size-cells = <2>; - #address-cells = <3>; - ranges = <02000000 0 b0000000 - 02000000 0 b0000000 - 0 00100000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; - - isa@1e { - device_type = "isa"; + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = ; + ranges = <1 0 + 01000000 0 0 + 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; #interrupt-cells = <2>; - #size-cells = <1>; - #address-cells = <2>; - reg = ; - ranges = <1 0 - 01000000 0 0 - 00001000>; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 60 1 1 64 1>; + interrupts = <1 3 c 3>; interrupt-parent = <&i8259>; - i8259: interrupt-controller@20 { - reg = <1 20 2 - 1 a0 2 - 1 4d0 2>; - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - interrupts = <9 2>; - interrupt-parent = <&mpic>; + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; }; - i8042@60 { - #size-cells = <0>; - #address-cells = <1>; - reg = <1 60 1 1 64 1>; - interrupts = <1 3 c 3>; - interrupt-parent = <&i8259>; - - keyboard@0 { - reg = <0>; - compatible = "pnpPNP,303"; - }; - - mouse@1 { - reg = <1>; - compatible = "pnpPNP,f03"; - }; + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; }; + }; - rtc@70 { - compatible = "pnpPNP,b00"; - reg = <1 70 2>; - }; + rtc@70 { + compatible = "pnpPNP,b00"; + reg = <1 70 2>; + }; - gpio@400 { - reg = <1 400 80>; - }; + gpio@400 { + reg = <1 400 80>; }; }; }; - }; - global-utilities@e0000 { //global utilities block - compatible = "fsl,mpc8548-guts"; - reg = ; - fsl,has-rstcr; - }; - - mpic: pic@40000 { - clock-frequency = <0>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <40000 40000>; - built-in; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - big-endian; - }; }; }; diff -puN arch/powerpc/boot/dts/mpc8548cds.dts~git-powerpc arch/powerpc/boot/dts/mpc8548cds.dts --- a/arch/powerpc/boot/dts/mpc8548cds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8548cds.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; }; @@ -42,15 +41,8 @@ soc8548@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; - ranges = <00001000 e0001000 000ff000 - 80000000 80000000 10000000 - e2000000 e2000000 00800000 - 90000000 90000000 10000000 - e2800000 e2800000 00800000 - a0000000 a0000000 20000000 - e3000000 e3000000 01000000>; + ranges = <00000000 e0000000 00100000>; reg = ; // CCSRBAR bus-frequency = <0>; @@ -189,215 +181,225 @@ fsl,has-rstcr; }; - pci@8000 { + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + }; + + pci@e0008000 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x4 (PCIX Slot 2) */ + 02000 0 0 1 &mpic 0 1 + 02000 0 0 2 &mpic 1 1 + 02000 0 0 3 &mpic 2 1 + 02000 0 0 4 &mpic 3 1 + + /* IDSEL 0x5 (PCIX Slot 3) */ + 02800 0 0 1 &mpic 1 1 + 02800 0 0 2 &mpic 2 1 + 02800 0 0 3 &mpic 3 1 + 02800 0 0 4 &mpic 0 1 + + /* IDSEL 0x6 (PCIX Slot 4) */ + 03000 0 0 1 &mpic 2 1 + 03000 0 0 2 &mpic 3 1 + 03000 0 0 3 &mpic 0 1 + 03000 0 0 4 &mpic 1 1 + + /* IDSEL 0x8 (PCIX Slot 5) */ + 04000 0 0 1 &mpic 0 1 + 04000 0 0 2 &mpic 1 1 + 04000 0 0 3 &mpic 2 1 + 04000 0 0 4 &mpic 3 1 + + /* IDSEL 0xC (Tsi310 bridge) */ + 06000 0 0 1 &mpic 0 1 + 06000 0 0 2 &mpic 1 1 + 06000 0 0 3 &mpic 2 1 + 06000 0 0 4 &mpic 3 1 + + /* IDSEL 0x14 (Slot 2) */ + 0a000 0 0 1 &mpic 0 1 + 0a000 0 0 2 &mpic 1 1 + 0a000 0 0 3 &mpic 2 1 + 0a000 0 0 4 &mpic 3 1 + + /* IDSEL 0x15 (Slot 3) */ + 0a800 0 0 1 &mpic 1 1 + 0a800 0 0 2 &mpic 2 1 + 0a800 0 0 3 &mpic 3 1 + 0a800 0 0 4 &mpic 0 1 + + /* IDSEL 0x16 (Slot 4) */ + 0b000 0 0 1 &mpic 2 1 + 0b000 0 0 2 &mpic 3 1 + 0b000 0 0 3 &mpic 0 1 + 0b000 0 0 4 &mpic 1 1 + + /* IDSEL 0x18 (Slot 5) */ + 0c000 0 0 1 &mpic 0 1 + 0c000 0 0 2 &mpic 1 1 + 0c000 0 0 3 &mpic 2 1 + 0c000 0 0 4 &mpic 3 1 + + /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ + 0E000 0 0 1 &mpic 0 1 + 0E000 0 0 2 &mpic 1 1 + 0E000 0 0 3 &mpic 2 1 + 0E000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00800000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + + pci_bridge@1c { interrupt-map-mask = ; interrupt-map = < - /* IDSEL 0x4 (PCIX Slot 2) */ - 02000 0 0 1 &mpic 0 1 - 02000 0 0 2 &mpic 1 1 - 02000 0 0 3 &mpic 2 1 - 02000 0 0 4 &mpic 3 1 - - /* IDSEL 0x5 (PCIX Slot 3) */ - 02800 0 0 1 &mpic 1 1 - 02800 0 0 2 &mpic 2 1 - 02800 0 0 3 &mpic 3 1 - 02800 0 0 4 &mpic 0 1 - - /* IDSEL 0x6 (PCIX Slot 4) */ - 03000 0 0 1 &mpic 2 1 - 03000 0 0 2 &mpic 3 1 - 03000 0 0 3 &mpic 0 1 - 03000 0 0 4 &mpic 1 1 - - /* IDSEL 0x8 (PCIX Slot 5) */ - 04000 0 0 1 &mpic 0 1 - 04000 0 0 2 &mpic 1 1 - 04000 0 0 3 &mpic 2 1 - 04000 0 0 4 &mpic 3 1 - - /* IDSEL 0xC (Tsi310 bridge) */ - 06000 0 0 1 &mpic 0 1 - 06000 0 0 2 &mpic 1 1 - 06000 0 0 3 &mpic 2 1 - 06000 0 0 4 &mpic 3 1 - - /* IDSEL 0x14 (Slot 2) */ - 0a000 0 0 1 &mpic 0 1 - 0a000 0 0 2 &mpic 1 1 - 0a000 0 0 3 &mpic 2 1 - 0a000 0 0 4 &mpic 3 1 - - /* IDSEL 0x15 (Slot 3) */ - 0a800 0 0 1 &mpic 1 1 - 0a800 0 0 2 &mpic 2 1 - 0a800 0 0 3 &mpic 3 1 - 0a800 0 0 4 &mpic 0 1 - - /* IDSEL 0x16 (Slot 4) */ - 0b000 0 0 1 &mpic 2 1 - 0b000 0 0 2 &mpic 3 1 - 0b000 0 0 3 &mpic 0 1 - 0b000 0 0 4 &mpic 1 1 - - /* IDSEL 0x18 (Slot 5) */ - 0c000 0 0 1 &mpic 0 1 - 0c000 0 0 2 &mpic 1 1 - 0c000 0 0 3 &mpic 2 1 - 0c000 0 0 4 &mpic 3 1 - - /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ - 0E000 0 0 1 &mpic 0 1 - 0E000 0 0 2 &mpic 1 1 - 0E000 0 0 3 &mpic 2 1 - 0E000 0 0 4 &mpic 3 1>; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 10000000 - 01000000 0 00000000 e2000000 0 00800000>; - clock-frequency = <3f940aa>; + /* IDSEL 0x00 (PrPMC Site) */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + + /* IDSEL 0x04 (VIA chip) */ + 2000 0 0 1 &mpic 0 1 + 2000 0 0 2 &mpic 1 1 + 2000 0 0 3 &mpic 2 1 + 2000 0 0 4 &mpic 3 1 + + /* IDSEL 0x05 (8139) */ + 2800 0 0 1 &mpic 1 1 + + /* IDSEL 0x06 (Slot 6) */ + 3000 0 0 1 &mpic 2 1 + 3000 0 0 2 &mpic 3 1 + 3000 0 0 3 &mpic 0 1 + 3000 0 0 4 &mpic 1 1 + + /* IDESL 0x07 (Slot 7) */ + 3800 0 0 1 &mpic 3 1 + 3800 0 0 2 &mpic 0 1 + 3800 0 0 3 &mpic 1 1 + 3800 0 0 4 &mpic 2 1>; + + reg = ; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <8000 1000>; - compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; - device_type = "pci"; - - pci_bridge@1c { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x00 (PrPMC Site) */ - 0000 0 0 1 &mpic 0 1 - 0000 0 0 2 &mpic 1 1 - 0000 0 0 3 &mpic 2 1 - 0000 0 0 4 &mpic 3 1 - - /* IDSEL 0x04 (VIA chip) */ - 2000 0 0 1 &mpic 0 1 - 2000 0 0 2 &mpic 1 1 - 2000 0 0 3 &mpic 2 1 - 2000 0 0 4 &mpic 3 1 - - /* IDSEL 0x05 (8139) */ - 2800 0 0 1 &mpic 1 1 - - /* IDSEL 0x06 (Slot 6) */ - 3000 0 0 1 &mpic 2 1 - 3000 0 0 2 &mpic 3 1 - 3000 0 0 3 &mpic 0 1 - 3000 0 0 4 &mpic 1 1 - - /* IDESL 0x07 (Slot 7) */ - 3800 0 0 1 &mpic 3 1 - 3800 0 0 2 &mpic 0 1 - 3800 0 0 3 &mpic 1 1 - 3800 0 0 4 &mpic 2 1>; - - reg = ; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - ranges = <02000000 0 80000000 - 02000000 0 80000000 - 0 20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00080000>; - clock-frequency = <1fca055>; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00080000>; + clock-frequency = <1fca055>; - isa@4 { - device_type = "isa"; + isa@4 { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <2000 0 0 0 0>; + ranges = <1 0 01000000 0 0 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + interrupt-controller; + device_type = "interrupt-controller"; + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + #address-cells = <0>; #interrupt-cells = <2>; - #size-cells = <1>; - #address-cells = <2>; - reg = <2000 0 0 0 0>; - ranges = <1 0 01000000 0 0 00001000>; - interrupt-parent = <&i8259>; - - i8259: interrupt-controller@20 { - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - reg = <1 20 2 - 1 a0 2 - 1 4d0 2>; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - interrupts = <0 1>; - interrupt-parent = <&mpic>; - }; - - rtc@70 { - compatible = "pnpPNP,b00"; - reg = <1 70 2>; - }; + compatible = "chrp,iic"; + interrupts = <0 1>; + interrupt-parent = <&mpic>; }; - }; - }; - - pci@9000 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x15 */ - a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic 1 1 - a800 0 0 3 &mpic 2 1 - a800 0 0 4 &mpic 3 1>; - interrupt-parent = <&mpic>; - interrupts = <19 2>; - bus-range = <0 0>; - ranges = <02000000 0 90000000 90000000 0 10000000 - 01000000 0 00000000 e2800000 0 00800000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <9000 1000>; - compatible = "fsl,mpc8540-pci"; - device_type = "pci"; + rtc@70 { + compatible = "pnpPNP,b00"; + reg = <1 70 2>; + }; + }; }; - /* PCI Express */ - pcie@a000 { - interrupt-map-mask = ; - interrupt-map = < + }; - /* IDSEL 0x0 (PEX) */ - 00000 0 0 1 &mpic 0 1 - 00000 0 0 2 &mpic 1 1 - 00000 0 0 3 &mpic 2 1 - 00000 0 0 4 &mpic 3 1>; + pci@e0009000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x15 */ + a800 0 0 1 &mpic b 1 + a800 0 0 2 &mpic 1 1 + a800 0 0 3 &mpic 2 1 + a800 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <19 2>; + bus-range = <0 0>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 01000000 0 00000000 e2800000 0 00800000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; - interrupt-parent = <&mpic>; - interrupts = <1a 2>; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 08000000>; - clock-frequency = <1fca055>; - #interrupt-cells = <1>; + pcie@e000a000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x0 (PEX) */ + 00000 0 0 1 &mpic 0 1 + 00000 0 0 2 &mpic 1 1 + 00000 0 0 3 &mpic 2 1 + 00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 08000000>; + clock-frequency = <1fca055>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + pcie@0 { + reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; - reg = ; - compatible = "fsl,mpc8548-pcie"; device_type = "pci"; - }; - - mpic: pic@40000 { - clock-frequency = <0>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <40000 40000>; - built-in; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - big-endian; + ranges = <02000000 0 a0000000 + 02000000 0 a0000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 08000000>; }; }; }; diff -puN arch/powerpc/boot/dts/mpc8555cds.dts~git-powerpc arch/powerpc/boot/dts/mpc8555cds.dts --- a/arch/powerpc/boot/dts/mpc8555cds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8555cds.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; }; @@ -42,10 +41,9 @@ soc8555@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; - reg = ; // CCSRBAR 1M + reg = ; // CCSRBAR 1M bus-frequency = <0>; memory-controller@2000 { @@ -137,113 +135,109 @@ interrupt-parent = <&mpic>; }; - pci1: pci@8000 { - interrupt-map-mask = <1f800 0 0 7>; - interrupt-map = < - - /* IDSEL 0x10 */ - 08000 0 0 1 &mpic 0 1 - 08000 0 0 2 &mpic 1 1 - 08000 0 0 3 &mpic 2 1 - 08000 0 0 4 &mpic 3 1 - - /* IDSEL 0x11 */ - 08800 0 0 1 &mpic 0 1 - 08800 0 0 2 &mpic 1 1 - 08800 0 0 3 &mpic 2 1 - 08800 0 0 4 &mpic 3 1 - - /* IDSEL 0x12 (Slot 1) */ - 09000 0 0 1 &mpic 0 1 - 09000 0 0 2 &mpic 1 1 - 09000 0 0 3 &mpic 2 1 - 09000 0 0 4 &mpic 3 1 - - /* IDSEL 0x13 (Slot 2) */ - 09800 0 0 1 &mpic 1 1 - 09800 0 0 2 &mpic 2 1 - 09800 0 0 3 &mpic 3 1 - 09800 0 0 4 &mpic 0 1 - - /* IDSEL 0x14 (Slot 3) */ - 0a000 0 0 1 &mpic 2 1 - 0a000 0 0 2 &mpic 3 1 - 0a000 0 0 3 &mpic 0 1 - 0a000 0 0 4 &mpic 1 1 - - /* IDSEL 0x15 (Slot 4) */ - 0a800 0 0 1 &mpic 3 1 - 0a800 0 0 2 &mpic 0 1 - 0a800 0 0 3 &mpic 1 1 - 0a800 0 0 4 &mpic 2 1 - - /* Bus 1 (Tundra Bridge) */ - /* IDSEL 0x12 (ISA bridge) */ - 19000 0 0 1 &mpic 0 1 - 19000 0 0 2 &mpic 1 1 - 19000 0 0 3 &mpic 2 1 - 19000 0 0 4 &mpic 3 1>; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; - compatible = "fsl,mpc8540-pci"; - device_type = "pci"; - - i8259@19000 { - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - reg = <19000 0 0 0 1>; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <1>; - interrupt-parent = <&pci1>; - }; - }; - - pci@9000 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x15 */ - a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic b 1 - a800 0 0 3 &mpic b 1 - a800 0 0 4 &mpic b 1>; - interrupt-parent = <&mpic>; - interrupts = <19 2>; - bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <9000 1000>; - compatible = "fsl,mpc8540-pci"; - device_type = "pci"; - }; - mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; }; }; + + pci1: pci@e0008000 { + interrupt-map-mask = <1f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x10 */ + 08000 0 0 1 &mpic 0 1 + 08000 0 0 2 &mpic 1 1 + 08000 0 0 3 &mpic 2 1 + 08000 0 0 4 &mpic 3 1 + + /* IDSEL 0x11 */ + 08800 0 0 1 &mpic 0 1 + 08800 0 0 2 &mpic 1 1 + 08800 0 0 3 &mpic 2 1 + 08800 0 0 4 &mpic 3 1 + + /* IDSEL 0x12 (Slot 1) */ + 09000 0 0 1 &mpic 0 1 + 09000 0 0 2 &mpic 1 1 + 09000 0 0 3 &mpic 2 1 + 09000 0 0 4 &mpic 3 1 + + /* IDSEL 0x13 (Slot 2) */ + 09800 0 0 1 &mpic 1 1 + 09800 0 0 2 &mpic 2 1 + 09800 0 0 3 &mpic 3 1 + 09800 0 0 4 &mpic 0 1 + + /* IDSEL 0x14 (Slot 3) */ + 0a000 0 0 1 &mpic 2 1 + 0a000 0 0 2 &mpic 3 1 + 0a000 0 0 3 &mpic 0 1 + 0a000 0 0 4 &mpic 1 1 + + /* IDSEL 0x15 (Slot 4) */ + 0a800 0 0 1 &mpic 3 1 + 0a800 0 0 2 &mpic 0 1 + 0a800 0 0 3 &mpic 1 1 + 0a800 0 0 4 &mpic 2 1 + + /* Bus 1 (Tundra Bridge) */ + /* IDSEL 0x12 (ISA bridge) */ + 19000 0 0 1 &mpic 0 1 + 19000 0 0 2 &mpic 1 1 + 19000 0 0 3 &mpic 2 1 + 19000 0 0 4 &mpic 3 1>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + + i8259@19000 { + interrupt-controller; + device_type = "interrupt-controller"; + reg = <19000 0 0 0 1>; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + interrupts = <1>; + interrupt-parent = <&pci1>; + }; + }; + + pci@e0009000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x15 */ + a800 0 0 1 &mpic b 1 + a800 0 0 2 &mpic b 1 + a800 0 0 3 &mpic b 1 + a800 0 0 4 &mpic b 1>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + bus-range = <0 0>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; }; diff -puN arch/powerpc/boot/dts/mpc8560ads.dts~git-powerpc arch/powerpc/boot/dts/mpc8560ads.dts --- a/arch/powerpc/boot/dts/mpc8560ads.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8560ads.dts @@ -30,7 +30,6 @@ timebase-frequency = <04ead9a0>; bus-frequency = <13ab6680>; clock-frequency = <312c8040>; - 32-bit; }; }; @@ -42,7 +41,6 @@ soc8560@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -132,109 +130,17 @@ phy-handle = <&phy1>; }; - pci@8000 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; - device_type = "pci"; - reg = <8000 1000>; - clock-frequency = <3f940aa>; - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x2 */ - 1000 0 0 1 &mpic 1 1 - 1000 0 0 2 &mpic 2 1 - 1000 0 0 3 &mpic 3 1 - 1000 0 0 4 &mpic 4 1 - - /* IDSEL 0x3 */ - 1800 0 0 1 &mpic 4 1 - 1800 0 0 2 &mpic 1 1 - 1800 0 0 3 &mpic 2 1 - 1800 0 0 4 &mpic 3 1 - - /* IDSEL 0x4 */ - 2000 0 0 1 &mpic 3 1 - 2000 0 0 2 &mpic 4 1 - 2000 0 0 3 &mpic 1 1 - 2000 0 0 4 &mpic 2 1 - - /* IDSEL 0x5 */ - 2800 0 0 1 &mpic 2 1 - 2800 0 0 2 &mpic 3 1 - 2800 0 0 3 &mpic 4 1 - 2800 0 0 4 &mpic 1 1 - - /* IDSEL 12 */ - 6000 0 0 1 &mpic 1 1 - 6000 0 0 2 &mpic 2 1 - 6000 0 0 3 &mpic 3 1 - 6000 0 0 4 &mpic 4 1 - - /* IDSEL 13 */ - 6800 0 0 1 &mpic 4 1 - 6800 0 0 2 &mpic 1 1 - 6800 0 0 3 &mpic 2 1 - 6800 0 0 4 &mpic 3 1 - - /* IDSEL 14*/ - 7000 0 0 1 &mpic 3 1 - 7000 0 0 2 &mpic 4 1 - 7000 0 0 3 &mpic 1 1 - 7000 0 0 4 &mpic 2 1 - - /* IDSEL 15 */ - 7800 0 0 1 &mpic 2 1 - 7800 0 0 2 &mpic 3 1 - 7800 0 0 3 &mpic 4 1 - 7800 0 0 4 &mpic 1 1 - - /* IDSEL 18 */ - 9000 0 0 1 &mpic 1 1 - 9000 0 0 2 &mpic 2 1 - 9000 0 0 3 &mpic 3 1 - 9000 0 0 4 &mpic 4 1 - - /* IDSEL 19 */ - 9800 0 0 1 &mpic 4 1 - 9800 0 0 2 &mpic 1 1 - 9800 0 0 3 &mpic 2 1 - 9800 0 0 4 &mpic 3 1 - - /* IDSEL 20 */ - a000 0 0 1 &mpic 3 1 - a000 0 0 2 &mpic 4 1 - a000 0 0 3 &mpic 1 1 - a000 0 0 4 &mpic 2 1 - - /* IDSEL 21 */ - a800 0 0 1 &mpic 2 1 - a800 0 0 2 &mpic 3 1 - a800 0 0 3 &mpic 4 1 - a800 0 0 4 &mpic 1 1>; - - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 01000000>; - }; - mpic: pic@40000 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; device_type = "open-pic"; }; cpm@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "cpm"; model = "CPM2"; ranges = <0 0 c0000>; @@ -249,7 +155,6 @@ interrupts = <2e 2>; interrupt-parent = <&mpic>; reg = <90c00 80>; - built-in; device_type = "cpm-pic"; }; @@ -324,4 +229,94 @@ }; }; }; + + pci@e0008000 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + reg = ; + clock-frequency = <3f940aa>; + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x2 */ + 1000 0 0 1 &mpic 1 1 + 1000 0 0 2 &mpic 2 1 + 1000 0 0 3 &mpic 3 1 + 1000 0 0 4 &mpic 4 1 + + /* IDSEL 0x3 */ + 1800 0 0 1 &mpic 4 1 + 1800 0 0 2 &mpic 1 1 + 1800 0 0 3 &mpic 2 1 + 1800 0 0 4 &mpic 3 1 + + /* IDSEL 0x4 */ + 2000 0 0 1 &mpic 3 1 + 2000 0 0 2 &mpic 4 1 + 2000 0 0 3 &mpic 1 1 + 2000 0 0 4 &mpic 2 1 + + /* IDSEL 0x5 */ + 2800 0 0 1 &mpic 2 1 + 2800 0 0 2 &mpic 3 1 + 2800 0 0 3 &mpic 4 1 + 2800 0 0 4 &mpic 1 1 + + /* IDSEL 12 */ + 6000 0 0 1 &mpic 1 1 + 6000 0 0 2 &mpic 2 1 + 6000 0 0 3 &mpic 3 1 + 6000 0 0 4 &mpic 4 1 + + /* IDSEL 13 */ + 6800 0 0 1 &mpic 4 1 + 6800 0 0 2 &mpic 1 1 + 6800 0 0 3 &mpic 2 1 + 6800 0 0 4 &mpic 3 1 + + /* IDSEL 14*/ + 7000 0 0 1 &mpic 3 1 + 7000 0 0 2 &mpic 4 1 + 7000 0 0 3 &mpic 1 1 + 7000 0 0 4 &mpic 2 1 + + /* IDSEL 15 */ + 7800 0 0 1 &mpic 2 1 + 7800 0 0 2 &mpic 3 1 + 7800 0 0 3 &mpic 4 1 + 7800 0 0 4 &mpic 1 1 + + /* IDSEL 18 */ + 9000 0 0 1 &mpic 1 1 + 9000 0 0 2 &mpic 2 1 + 9000 0 0 3 &mpic 3 1 + 9000 0 0 4 &mpic 4 1 + + /* IDSEL 19 */ + 9800 0 0 1 &mpic 4 1 + 9800 0 0 2 &mpic 1 1 + 9800 0 0 3 &mpic 2 1 + 9800 0 0 4 &mpic 3 1 + + /* IDSEL 20 */ + a000 0 0 1 &mpic 3 1 + a000 0 0 2 &mpic 4 1 + a000 0 0 3 &mpic 1 1 + a000 0 0 4 &mpic 2 1 + + /* IDSEL 21 */ + a800 0 0 1 &mpic 2 1 + a800 0 0 2 &mpic 3 1 + a800 0 0 3 &mpic 4 1 + a800 0 0 4 &mpic 1 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 01000000>; + }; }; diff -puN arch/powerpc/boot/dts/mpc8568mds.dts~git-powerpc arch/powerpc/boot/dts/mpc8568mds.dts --- a/arch/powerpc/boot/dts/mpc8568mds.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8568mds.dts @@ -34,7 +34,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; }; @@ -51,7 +50,6 @@ soc8568@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = ; @@ -258,7 +256,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -449,7 +446,6 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <2e 2 2e 2>; //high:30 low:30 interrupt-parent = <&mpic>; diff -puN /dev/null arch/powerpc/boot/dts/mpc8572ds.dts --- /dev/null +++ a/arch/powerpc/boot/dts/mpc8572ds.dts @@ -0,0 +1,404 @@ +/* + * MPC8572 DS Device Tree Source + * + * Copyright 2007 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/ { + model = "fsl,MPC8572DS"; + compatible = "fsl,MPC8572DS"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8572@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 00000000>; // Filled by U-Boot + }; + + soc8572@ffe00000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <00000000 ffe00000 00100000>; + reg = ; // CCSRBAR & soc regs, remove once parse code for immrbase fixed + bus-frequency = <0>; // Filled out by uboot. + + memory-controller@2000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <12 2>; + }; + + memory-controller@6000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <6000 1000>; + interrupt-parent = <&mpic>; + interrupts = <12 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,mpc8572-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <10 2>; + }; + + i2c@3000 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3000 100>; + interrupts = <2b 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3100 100>; + interrupts = <2b 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "mdio"; + compatible = "gianfar"; + reg = <24520 20>; + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = ; + reg = <0>; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = ; + reg = <1>; + }; + phy2: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = ; + reg = <2>; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = ; + reg = <3>; + }; + }; + + ethernet@24000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <24000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <1d 2 1e 2 22 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + ethernet@25000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <25000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <23 2 24 2 28 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; + + ethernet@26000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <26000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <1f 2 20 2 21 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-id"; + }; + + ethernet@27000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <27000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <25 2 26 2 27 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy3>; + phy-connection-type = "rgmii-id"; + }; + + serial@4500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4500 100>; + clock-frequency = <0>; + interrupts = <2a 2>; + interrupt-parent = <&mpic>; + }; + + serial@4600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4600 100>; + clock-frequency = <0>; + interrupts = <2a 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8572-guts"; + reg = ; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + }; + + pcie@ffe08000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 ffc00000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x11 - PCI slot 1 */ + 8800 0 0 1 &mpic 2 1 + 8800 0 0 2 &mpic 3 1 + 8800 0 0 3 &mpic 4 1 + 8800 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 - PCI slot 2 */ + 9000 0 0 1 &mpic 3 1 + 9000 0 0 2 &mpic 4 1 + 9000 0 0 3 &mpic 1 1 + 9000 0 0 4 &mpic 2 1 + + // IDSEL 0x1c USB + e000 0 0 0 &i8259 c 2 + e100 0 0 0 &i8259 9 2 + e200 0 0 0 &i8259 a 2 + e300 0 0 0 &i8259 b 2 + + // IDSEL 0x1d Audio + e800 0 0 0 &i8259 6 2 + + // IDSEL 0x1e Legacy + f000 0 0 0 &i8259 7 2 + f100 0 0 0 &i8259 7 2 + + // IDSEL 0x1f IDE/SATA + f800 0 0 0 &i8259 e 2 + f900 0 0 0 &i8259 5 2 + + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + uli1575@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = ; + ranges = <1 0 01000000 0 0 + 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 60 1 1 64 1>; + interrupts = <1 3 c 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = "pnpPNP,b00"; + reg = <1 70 2>; + }; + + gpio@400 { + reg = <1 400 80>; + }; + }; + }; + }; + + }; + + pcie@ffe09000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 ffc10000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <02000000 0 a0000000 + 02000000 0 a0000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + }; + }; + + pcie@ffe0a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 c0000000 c0000000 0 20000000 + 01000000 0 00000000 ffc20000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1b 2>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <02000000 0 c0000000 + 02000000 0 c0000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + }; + }; +}; diff -puN arch/powerpc/boot/dts/mpc8641_hpcn.dts~git-powerpc arch/powerpc/boot/dts/mpc8641_hpcn.dts --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot - 32-bit; }; PowerPC,8641@1 { device_type = "cpu"; @@ -42,7 +41,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot - 32-bit; }; }; @@ -54,13 +52,8 @@ soc8641@f8000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; - ranges = <00001000 f8001000 000ff000 - 80000000 80000000 20000000 - e2000000 e2000000 00100000 - a0000000 a0000000 20000000 - e3000000 e3000000 00100000>; + ranges = <00000000 f8000000 00100000>; reg = ; // CCSRBAR bus-frequency = <0>; @@ -211,50 +204,75 @@ interrupt-parent = <&mpic>; }; - pcie@8000 { - compatible = "fsl,mpc8641-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + }; + + pcie@f8008000 { + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x11 */ + 8800 0 0 1 &i8259 9 2 + 8800 0 0 2 &i8259 a 2 + 8800 0 0 3 &i8259 b 2 + 8800 0 0 4 &i8259 c 2 + + /* IDSEL 0x12 */ + 9000 0 0 1 &i8259 a 2 + 9000 0 0 2 &i8259 b 2 + 9000 0 0 3 &i8259 c 2 + 9000 0 0 4 &i8259 9 2 + + // IDSEL 0x1c USB + e000 0 0 0 &i8259 c 2 + e100 0 0 0 &i8259 9 2 + e200 0 0 0 &i8259 a 2 + e300 0 0 0 &i8259 b 2 + + // IDSEL 0x1d Audio + e800 0 0 0 &i8259 6 2 + + // IDSEL 0x1e Legacy + f000 0 0 0 &i8259 7 2 + f100 0 0 0 &i8259 7 2 + + // IDSEL 0x1f IDE/SATA + f800 0 0 0 &i8259 e 2 + f900 0 0 0 &i8259 5 2 + >; + + pcie@0 { + reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; - reg = <8000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <1fca055>; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x11 */ - 8800 0 0 1 &i8259 9 2 - 8800 0 0 2 &i8259 a 2 - 8800 0 0 3 &i8259 b 2 - 8800 0 0 4 &i8259 c 2 - - /* IDSEL 0x12 */ - 9000 0 0 1 &i8259 a 2 - 9000 0 0 2 &i8259 b 2 - 9000 0 0 3 &i8259 c 2 - 9000 0 0 4 &i8259 9 2 - - // IDSEL 0x1c USB - e000 0 0 0 &i8259 c 2 - e100 0 0 0 &i8259 9 2 - e200 0 0 0 &i8259 a 2 - e300 0 0 0 &i8259 b 2 - - // IDSEL 0x1d Audio - e800 0 0 0 &i8259 6 2 - - // IDSEL 0x1e Legacy - f000 0 0 0 &i8259 7 2 - f100 0 0 0 &i8259 7 2 - - // IDSEL 0x1f IDE/SATA - f800 0 0 0 &i8259 e 2 - f900 0 0 0 &i8259 5 2 - >; + device_type = "pci"; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; uli1575@0 { reg = <0 0 0 0 0>; #size-cells = <2>; @@ -265,111 +283,96 @@ 01000000 0 00000000 01000000 0 00000000 0 00100000>; - - pci_bridge@0 { - reg = <0 0 0 0 0>; - #size-cells = <2>; - #address-cells = <3>; - ranges = <02000000 0 80000000 - 02000000 0 80000000 - 0 20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; - - isa@1e { - device_type = "isa"; + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = ; + ranges = <1 0 01000000 0 0 + 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; #interrupt-cells = <2>; - #size-cells = <1>; - #address-cells = <2>; - reg = ; - ranges = <1 0 01000000 0 0 - 00001000>; - interrupt-parent = <&i8259>; - - i8259: interrupt-controller@20 { - reg = <1 20 2 - 1 a0 2 - 1 4d0 2>; - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - interrupts = <9 2>; - interrupt-parent = - <&mpic>; - }; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = <&mpic>; + }; - i8042@60 { - #size-cells = <0>; - #address-cells = <1>; - reg = <1 60 1 1 64 1>; - interrupts = <1 3 c 3>; - interrupt-parent = - <&i8259>; - - keyboard@0 { - reg = <0>; - compatible = "pnpPNP,303"; - }; - - mouse@1 { - reg = <1>; - compatible = "pnpPNP,f03"; - }; + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 60 1 1 64 1>; + interrupts = <1 3 c 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; }; - rtc@70 { - compatible = - "pnpPNP,b00"; - reg = <1 70 2>; + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; }; + }; - gpio@400 { - reg = <1 400 80>; - }; + rtc@70 { + compatible = + "pnpPNP,b00"; + reg = <1 70 2>; + }; + + gpio@400 { + reg = <1 400 80>; }; }; }; - }; - pcie@9000 { - compatible = "fsl,mpc8641-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; + }; + + pcie@f8009000 { + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 00100000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; - reg = <9000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; - clock-frequency = <1fca055>; - interrupt-parent = <&mpic>; - interrupts = <19 2>; - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 4 1 - 0000 0 0 2 &mpic 5 1 - 0000 0 0 3 &mpic 6 1 - 0000 0 0 4 &mpic 7 1 - >; - }; - - mpic: pic@40000 { - clock-frequency = <0>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <40000 40000>; - built-in; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - big-endian; + device_type = "pci"; + ranges = <02000000 0 a0000000 + 02000000 0 a0000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; }; }; }; diff -puN arch/powerpc/boot/dts/mpc866ads.dts~git-powerpc arch/powerpc/boot/dts/mpc866ads.dts --- a/arch/powerpc/boot/dts/mpc866ads.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc866ads.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; interrupts = ; // decrementer interrupt interrupt-parent = <&Mpc8xx_pic>; }; @@ -44,7 +43,6 @@ soc866@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 ff000000 00100000>; reg = ; @@ -78,7 +76,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0 24>; - built-in; device_type = "mpc8xx-pic"; compatible = "CPM"; }; @@ -86,7 +83,6 @@ cpm@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "cpm"; model = "CPM"; ranges = <0 0 4000>; @@ -103,7 +99,6 @@ interrupts = <5 2 0 2>; interrupt-parent = <&Mpc8xx_pic>; reg = <930 20>; - built-in; device_type = "cpm-pic"; compatible = "CPM"; }; diff -puN arch/powerpc/boot/dts/mpc885ads.dts~git-powerpc arch/powerpc/boot/dts/mpc885ads.dts --- a/arch/powerpc/boot/dts/mpc885ads.dts~git-powerpc +++ a/arch/powerpc/boot/dts/mpc885ads.dts @@ -30,7 +30,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; interrupts = ; // decrementer interrupt interrupt-parent = <&Mpc8xx_pic>; }; @@ -44,7 +43,6 @@ soc885@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 ff000000 00100000>; reg = ; @@ -98,7 +96,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0 24>; - built-in; device_type = "mpc8xx-pic"; compatible = "CPM"; }; @@ -117,7 +114,6 @@ cpm@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "cpm"; model = "CPM"; ranges = <0 0 4000>; @@ -134,7 +130,6 @@ interrupts = <5 2 0 2>; interrupt-parent = <&Mpc8xx_pic>; reg = <930 20>; - built-in; device_type = "cpm-pic"; compatible = "CPM"; }; diff -puN arch/powerpc/boot/dts/prpmc2800.dts~git-powerpc arch/powerpc/boot/dts/prpmc2800.dts --- a/arch/powerpc/boot/dts/prpmc2800.dts~git-powerpc +++ a/arch/powerpc/boot/dts/prpmc2800.dts @@ -9,10 +9,6 @@ * * Property values that are labeled as "Default" will be updated by bootwrapper * if it can determine the exact PrPMC type. - * - * To build: - * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts - * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts */ / { @@ -47,7 +43,6 @@ mv64x60@f1000000 { /* Marvell Discovery */ #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <1>; model = "mv64360"; /* Default */ compatible = "marvell,mv64x60"; clock-frequency = <7f28155>; /* 133.333333 MHz */ diff -puN /dev/null arch/powerpc/boot/dts/sequoia.dts --- /dev/null +++ a/arch/powerpc/boot/dts/sequoia.dts @@ -0,0 +1,302 @@ +/* + * Device Tree Source for AMCC Sequoia + * + * Based on Bamboo code by Josh Boyer + * Copyright (c) 2006, 2007 IBM Corp. + * + * FIXME: Draft only! + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,sequoia"; + compatible = "amcc,sequoia"; + dcr-parent = <&/cpus/PowerPC,440EPx@0>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,440EPx@0 { + device_type = "cpu"; + reg = <0>; + clock-frequency = <0>; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <8000>; + d-cache-size = <8000>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440epx","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440epx","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1e 4 1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-440epx","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0e0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1c 4 1d 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-440epx", "ibm,sdr-440ep"; + dcr-reg = <00e 002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-440epx", "ibm,cpr-440ep"; + dcr-reg = <00c 002>; + }; + + plb { + compatible = "ibm,plb-440epx", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: sdram { + device_type = "memory-controller"; + compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali"; + dcr-reg = <010 2>; + }; + + DMA0: dma { + compatible = "ibm,dma-440epx", "ibm,dma-4xx"; + dcr-reg = <100 027>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440epx", "ibm,mcmal2"; + dcr-reg = <180 62>; + num-tx-chans = <2>; + num-rx-chans = <2>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = ; + interrupt-map-mask = ; + }; + + POB0: opb { + compatible = "ibm,opb-440epx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <00000000 1 00000000 80000000 + 80000000 1 80000000 80000000>; + interrupt-parent = <&UIC1>; + interrupts = <7 4>; + clock-frequency = <0>; /* Filled in by zImage */ + + EBC0: ebc { + compatible = "ibm,ebc-440epx", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by zImage */ + interrupts = <5 1>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl256n", "cfi-flash"; + bank-width = <2>; + reg = <0 000000 4000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Kernel"; + reg = <0 180000>; + }; + partition@180000 { + label = "ramdisk"; + reg = <180000 200000>; + }; + partition@380000 { + label = "file system"; + reg = <380000 3aa0000>; + }; + partition@3e20000 { + label = "kozio"; + reg = <3e20000 140000>; + }; + partition@3f60000 { + label = "env"; + reg = <3f60000 40000>; + }; + partition@3fa0000 { + label = "u-boot"; + reg = <3fa0000 60000>; + }; + }; + + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <1c200>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + UART2: serial@ef600500 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC1>; + interrupts = <3 4>; + }; + + UART3: serial@ef600600 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC1>; + interrupts = <4 4>; + }; + + IIC0: i2c@ef600700 { + device_type = "i2c"; + compatible = "ibm,iic-440epx", "ibm,iic"; + reg = ; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + + IIC1: i2c@ef600800 { + device_type = "i2c"; + compatible = "ibm,iic-440epx", "ibm,iic"; + reg = ; + interrupt-parent = <&UIC0>; + interrupts = <7 4>; + }; + + ZMII0: emac-zmii@ef600d00 { + device_type = "zmii-interface"; + compatible = "ibm,zmii-440epx", "ibm,zmii"; + reg = ; + }; + + EMAC0: ethernet@ef600e00 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-440epx", "ibm,emac4"; + interrupt-parent = <&EMAC0>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = ; + reg = ; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <0>; + }; + + EMAC1: ethernet@ef600f00 { + linux,network-index = <1>; + device_type = "network"; + compatible = "ibm,emac-440epx", "ibm,emac4"; + interrupt-parent = <&EMAC1>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = ; + reg = ; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <1>; + }; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@ef600300"; + bootargs = "console=ttyS0,115200"; + }; +}; diff -puN /dev/null arch/powerpc/boot/dts/walnut.dts --- /dev/null +++ a/arch/powerpc/boot/dts/walnut.dts @@ -0,0 +1,190 @@ +/* + * Device Tree Source for IBM Walnut + * + * Copyright 2007 IBM Corp. + * Josh Boyer + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "ibm,walnut"; + compatible = "ibm,walnut"; + dcr-parent = <&/cpus/PowerPC,405GP@0>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,405GP@0 { + device_type = "cpu"; + reg = <0>; + clock-frequency = ; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <4000>; + d-cache-size = <4000>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller { + compatible = "ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 9>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + plb { + compatible = "ibm,plb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: memory-controller { + compatible = "ibm,sdram-405gp"; + dcr-reg = <010 2>; + }; + + MAL: mcmal { + compatible = "ibm,mcmal-405gp", "ibm,mcmal"; + dcr-reg = <180 62>; + num-tx-chans = <2>; + num-rx-chans = <1>; + interrupt-parent = <&UIC0>; + interrupts = ; + }; + + POB0: opb { + compatible = "ibm,opb-405gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = ; + dcr-reg = <0a0 5>; + clock-frequency = <0>; /* Filled in by zImage */ + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <2580>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <2580>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + IIC: i2c@ef600500 { + compatible = "ibm,iic-405gp", "ibm,iic"; + reg = ; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + + GPIO: gpio@ef600700 { + compatible = "ibm,gpio-405gp"; + reg = ; + }; + + EMAC: ethernet@ef600800 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-405gp", "ibm,emac"; + interrupt-parent = <&UIC0>; + interrupts = <9 4 f 4>; + reg = ; + mal-device = <&MAL>; + mal-tx-channel = <0 1>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000001>; + }; + + }; + + EBC0: ebc { + compatible = "ibm,ebc-405gp", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + /* The ranges property is supplied by the bootwrapper + * and is based on the firmware's configuration of the + * EBC bridge + */ + clock-frequency = <0>; /* Filled in by zImage */ + + sram@0,0 { + reg = <0 0 80000>; + }; + + flash@0,80000 { + compatible = "jedec-flash"; + bank-width = <1>; + reg = <0 80000 80000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "OpenBIOS"; + reg = <0 80000>; + read-only; + }; + }; + + ds1743@1,0 { + /* NVRAM and RTC */ + compatible = "ds1743"; + reg = <1 0 2000>; + }; + + keyboard@2,0 { + compatible = "intel,82C42PC"; + reg = <2 0 2>; + }; + + ir@3,0 { + compatible = "ti,TIR2000PAG"; + reg = <3 0 10>; + }; + + fpga@7,0 { + compatible = "Walnut-FPGA"; + reg = <7 0 10>; + virtual-reg = ; + }; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@ef600300"; + }; +}; diff -puN arch/powerpc/boot/ebony.c~git-powerpc arch/powerpc/boot/ebony.c --- a/arch/powerpc/boot/ebony.c~git-powerpc +++ a/arch/powerpc/boot/ebony.c @@ -24,12 +24,11 @@ #include "page.h" #include "ops.h" #include "reg.h" +#include "io.h" #include "dcr.h" +#include "4xx.h" #include "44x.h" -extern char _dtb_start[]; -extern char _dtb_end[]; - static u8 *ebony_mac0, *ebony_mac1; /* Calculate 440GP clocks */ @@ -92,15 +91,53 @@ void ibm440gp_fixup_clocks(unsigned int dt_fixup_clock("/plb/opb/serial@40000300", uart1); } +#define EBONY_FPGA_PATH "/plb/opb/ebc/fpga" +#define EBONY_FPGA_FLASH_SEL 0x01 +#define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash" + +static void ebony_flashsel_fixup(void) +{ + void *devp; + u32 reg[3] = {0x0, 0x0, 0x80000}; + u8 *fpga; + u8 fpga_reg0 = 0x0; + + devp = finddevice(EBONY_FPGA_PATH); + if (!devp) + fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); + + if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) + fatal("%s has missing or invalid virtual-reg property\n\r", + EBONY_FPGA_PATH); + + fpga_reg0 = in_8(fpga); + + devp = finddevice(EBONY_SMALL_FLASH_PATH); + if (!devp) + fatal("Couldn't locate small flash node %s\n\r", + EBONY_SMALL_FLASH_PATH); + + if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg)) + fatal("%s has reg property of unexpected size\n\r", + EBONY_SMALL_FLASH_PATH); + + /* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */ + if (fpga_reg0 & EBONY_FPGA_FLASH_SEL) + reg[1] ^= 0x80000; + + setprop(devp, "reg", reg, sizeof(reg)); +} + static void ebony_fixups(void) { // FIXME: sysclk should be derived by reading the FPGA registers unsigned long sysclk = 33000000; ibm440gp_fixup_clocks(sysclk, 6 * 1843200); - ibm44x_fixup_memsize(); + ibm4xx_fixup_memsize(); dt_fixup_mac_addresses(ebony_mac0, ebony_mac1); ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); + ebony_flashsel_fixup(); } void ebony_init(void *mac0, void *mac1) diff -puN arch/powerpc/boot/flatdevtree.c~git-powerpc arch/powerpc/boot/flatdevtree.c --- a/arch/powerpc/boot/flatdevtree.c~git-powerpc +++ a/arch/powerpc/boot/flatdevtree.c @@ -354,16 +354,21 @@ static void ft_put_bin(struct ft_cxt *cx cxt->p += sza; } -int ft_begin_node(struct ft_cxt *cxt, const char *name) +char *ft_begin_node(struct ft_cxt *cxt, const char *name) { unsigned long nlen = strlen(name) + 1; unsigned long len = 8 + _ALIGN(nlen, 4); + char *ret; if (!ft_make_space(cxt, &cxt->p, FT_STRUCT, len)) - return -1; + return NULL; + + ret = cxt->p; + ft_put_word(cxt, OF_DT_BEGIN_NODE); ft_put_bin(cxt, name, strlen(name) + 1); - return 0; + + return ret; } void ft_end_node(struct ft_cxt *cxt) @@ -625,25 +630,17 @@ void ft_end_tree(struct ft_cxt *cxt) bph->dt_strings_size = cpu_to_be32(ssize); } -void *ft_find_device(struct ft_cxt *cxt, const char *srch_path) -{ - char *node; - - /* require absolute path */ - if (srch_path[0] != '/') - return NULL; - node = ft_find_descendent(cxt, ft_root_node(cxt), srch_path); - return ft_get_phandle(cxt, node); -} - -void *ft_find_device_rel(struct ft_cxt *cxt, const void *top, - const char *srch_path) +void *ft_find_device(struct ft_cxt *cxt, const void *top, const char *srch_path) { char *node; - node = ft_node_ph2node(cxt, top); - if (node == NULL) - return NULL; + if (top) { + node = ft_node_ph2node(cxt, top); + if (node == NULL) + return NULL; + } else { + node = ft_root_node(cxt); + } node = ft_find_descendent(cxt, node, srch_path); return ft_get_phandle(cxt, node); @@ -945,7 +942,7 @@ int ft_del_prop(struct ft_cxt *cxt, cons void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name) { struct ft_atom atom; - char *p, *next; + char *p, *next, *ret; int depth = 0; if (parent) { @@ -970,11 +967,70 @@ void *ft_create_node(struct ft_cxt *cxt, break; /* end of node, insert here */ cxt->p = p; - ft_begin_node(cxt, name); + ret = ft_begin_node(cxt, name); ft_end_node(cxt); - return p; + return ft_get_phandle(cxt, ret); } p = next; } return NULL; } + +/* Returns the start of the path within the provided buffer, or NULL on + * error. + */ +char *ft_get_path(struct ft_cxt *cxt, const void *phandle, + char *buf, int len) +{ + const char *path_comp[FT_MAX_DEPTH]; + struct ft_atom atom; + char *p, *next, *pos; + int depth = 0, i; + void *node; + + node = ft_node_ph2node(cxt, phandle); + if (node == NULL) + return NULL; + + p = ft_root_node(cxt); + + while ((next = ft_next(cxt, p, &atom)) != NULL) { + switch (atom.tag) { + case OF_DT_BEGIN_NODE: + path_comp[depth++] = atom.name; + if (p == node) + goto found; + + break; + + case OF_DT_END_NODE: + if (--depth == 0) + return NULL; + } + + p = next; + } + +found: + pos = buf; + for (i = 1; i < depth; i++) { + int this_len; + + if (len <= 1) + return NULL; + + *pos++ = '/'; + len--; + + strncpy(pos, path_comp[i], len); + + if (pos[len - 1] != 0) + return NULL; + + this_len = strlen(pos); + len -= this_len; + pos += this_len; + } + + return buf; +} diff -puN arch/powerpc/boot/flatdevtree.h~git-powerpc arch/powerpc/boot/flatdevtree.h --- a/arch/powerpc/boot/flatdevtree.h~git-powerpc +++ a/arch/powerpc/boot/flatdevtree.h @@ -76,7 +76,7 @@ struct ft_cxt { unsigned int nodes_used; }; -int ft_begin_node(struct ft_cxt *cxt, const char *name); +char *ft_begin_node(struct ft_cxt *cxt, const char *name); void ft_end_node(struct ft_cxt *cxt); void ft_begin_tree(struct ft_cxt *cxt); @@ -96,9 +96,8 @@ int ft_add_rsvmap(struct ft_cxt *cxt, u6 void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); -void *ft_find_device(struct ft_cxt *cxt, const char *srch_path); -void *ft_find_device_rel(struct ft_cxt *cxt, const void *top, - const char *srch_path); +void *ft_find_device(struct ft_cxt *cxt, const void *top, + const char *srch_path); void *ft_find_descendent(struct ft_cxt *cxt, void *top, const char *srch_path); int ft_get_prop(struct ft_cxt *cxt, const void *phandle, const char *propname, void *buf, const unsigned int buflen); @@ -109,5 +108,6 @@ void *ft_find_node_by_prop_value(struct const char *propname, const char *propval, int proplen); void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name); +char *ft_get_path(struct ft_cxt *cxt, const void *phandle, char *buf, int len); #endif /* FLATDEVTREE_H */ diff -puN arch/powerpc/boot/flatdevtree_env.h~git-powerpc arch/powerpc/boot/flatdevtree_env.h --- a/arch/powerpc/boot/flatdevtree_env.h~git-powerpc +++ a/arch/powerpc/boot/flatdevtree_env.h @@ -24,24 +24,4 @@ #define be64_to_cpu(x) (x) #define cpu_to_be64(x) (x) -static inline int strncmp(const char *cs, const char *ct, size_t count) -{ - signed char __res = 0; - - while (count) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - count--; - } - return __res; -} - -static inline char *strchr(const char *s, int c) -{ - for (; *s != (char)c; ++s) - if (*s == '\0') - return NULL; - return (char *)s; -} - #endif /* _PPC_BOOT_FLATDEVTREE_ENV_H_ */ diff -puN arch/powerpc/boot/flatdevtree_misc.c~git-powerpc arch/powerpc/boot/flatdevtree_misc.c --- a/arch/powerpc/boot/flatdevtree_misc.c~git-powerpc +++ a/arch/powerpc/boot/flatdevtree_misc.c @@ -18,7 +18,7 @@ static struct ft_cxt cxt; static void *fdtm_finddevice(const char *name) { - return ft_find_device(&cxt, name); + return ft_find_device(&cxt, NULL, name); } static int fdtm_getprop(const void *phandle, const char *propname, @@ -58,6 +58,11 @@ static unsigned long fdtm_finalize(void) return (unsigned long)cxt.bph; } +static char *fdtm_get_path(const void *phandle, char *buf, int len) +{ + return ft_get_path(&cxt, phandle, buf, len); +} + int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device) { dt_ops.finddevice = fdtm_finddevice; @@ -67,6 +72,7 @@ int ft_init(void *dt_blob, unsigned int dt_ops.create_node = fdtm_create_node; dt_ops.find_node_by_prop_value = fdtm_find_node_by_prop_value; dt_ops.finalize = fdtm_finalize; + dt_ops.get_path = fdtm_get_path; return ft_open(&cxt, dt_blob, max_size, max_find_device, platform_ops.realloc); diff -puN arch/powerpc/boot/holly.c~git-powerpc arch/powerpc/boot/holly.c --- a/arch/powerpc/boot/holly.c~git-powerpc +++ a/arch/powerpc/boot/holly.c @@ -21,11 +21,6 @@ #include "ops.h" #include "io.h" -extern char _start[]; -extern char _end[]; -extern char _dtb_start[]; -extern char _dtb_end[]; - BSS_STACK(4096); void platform_init(unsigned long r3, unsigned long r4, unsigned long r5) diff -puN arch/powerpc/boot/io.h~git-powerpc arch/powerpc/boot/io.h --- a/arch/powerpc/boot/io.h~git-powerpc +++ a/arch/powerpc/boot/io.h @@ -1,5 +1,8 @@ #ifndef _IO_H #define __IO_H + +#include "types.h" + /* * Low-level I/O routines. * @@ -20,6 +23,37 @@ static inline void out_8(volatile unsign : "=m" (*addr) : "r" (val)); } +static inline unsigned in_le16(const volatile u16 *addr) +{ + unsigned ret; + + __asm__ __volatile__("lhbrx %0,0,%1; twi 0,%0,0; isync" + : "=r" (ret) : "r" (addr), "m" (*addr)); + + return ret; +} + +static inline unsigned in_be16(const volatile u16 *addr) +{ + unsigned ret; + + __asm__ __volatile__("lhz%U1%X1 %0,%1; twi 0,%0,0; isync" + : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_le16(volatile u16 *addr, int val) +{ + __asm__ __volatile__("sthbrx %1,0,%2; sync" : "=m" (*addr) + : "r" (val), "r" (addr)); +} + +static inline void out_be16(volatile u16 *addr, int val) +{ + __asm__ __volatile__("sth%U0%X0 %1,%0; sync" + : "=m" (*addr) : "r" (val)); +} + static inline unsigned in_le32(const volatile unsigned *addr) { unsigned ret; @@ -50,4 +84,19 @@ static inline void out_be32(volatile uns : "=m" (*addr) : "r" (val)); } +static inline void sync(void) +{ + asm volatile("sync" : : : "memory"); +} + +static inline void eieio(void) +{ + asm volatile("eieio" : : : "memory"); +} + +static inline void barrier(void) +{ + asm volatile("" : : : "memory"); +} + #endif /* _IO_H */ diff -puN arch/powerpc/boot/main.c~git-powerpc arch/powerpc/boot/main.c --- a/arch/powerpc/boot/main.c~git-powerpc +++ a/arch/powerpc/boot/main.c @@ -19,16 +19,6 @@ #include "flatdevtree.h" #include "reg.h" -extern char _start[]; -extern char __bss_start[]; -extern char _end[]; -extern char _vmlinux_start[]; -extern char _vmlinux_end[]; -extern char _initrd_start[]; -extern char _initrd_end[]; -extern char _dtb_start[]; -extern char _dtb_end[]; - static struct gunzip_state gzstate; struct addr_range { diff -puN arch/powerpc/boot/mpsc.c~git-powerpc arch/powerpc/boot/mpsc.c --- a/arch/powerpc/boot/mpsc.c~git-powerpc +++ a/arch/powerpc/boot/mpsc.c @@ -17,7 +17,6 @@ #include "io.h" #include "ops.h" -extern void udelay(long delay); #define MPSC_CHR_1 0x000c diff -puN arch/powerpc/boot/mv64x60_i2c.c~git-powerpc arch/powerpc/boot/mv64x60_i2c.c --- a/arch/powerpc/boot/mv64x60_i2c.c~git-powerpc +++ a/arch/powerpc/boot/mv64x60_i2c.c @@ -21,8 +21,6 @@ #include "ops.h" #include "mv64x60.h" -extern void udelay(long); - /* Register defines */ #define MV64x60_I2C_REG_SLAVE_ADDR 0x00 #define MV64x60_I2C_REG_DATA 0x04 diff -puN arch/powerpc/boot/of.c~git-powerpc arch/powerpc/boot/of.c --- a/arch/powerpc/boot/of.c~git-powerpc +++ a/arch/powerpc/boot/of.c @@ -17,8 +17,6 @@ #include "of.h" -extern char _end[]; - /* Value picked to match that used by yaboot */ #define PROG_START 0x01400000 /* only used on 64-bit systems */ #define RAM_END (512<<20) /* Fixme: use OF */ diff -puN arch/powerpc/boot/ops.h~git-powerpc arch/powerpc/boot/ops.h --- a/arch/powerpc/boot/ops.h~git-powerpc +++ a/arch/powerpc/boot/ops.h @@ -47,6 +47,7 @@ struct dt_ops { const char *propname, const char *propval, int proplen); unsigned long (*finalize)(void); + char *(*get_path)(const void *phandle, char *buf, int len); }; extern struct dt_ops dt_ops; @@ -82,11 +83,14 @@ int ft_init(void *dt_blob, unsigned int int serial_console_init(void); int ns16550_console_init(void *devp, struct serial_console_data *scdp); int mpsc_console_init(void *devp, struct serial_console_data *scdp); +int cpm_console_init(void *devp, struct serial_console_data *scdp); void *simple_alloc_init(char *base, unsigned long heap_size, unsigned long granularity, unsigned long max_allocs); extern void flush_cache(void *, unsigned long); int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size); int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr); +int dt_is_compatible(void *node, const char *compat); +void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize); static inline void *finddevice(const char *name) { @@ -167,6 +171,14 @@ static inline void *find_node_by_linuxph (char *)&linuxphandle, sizeof(u32)); } +static inline char *get_path(const void *phandle, char *buf, int len) +{ + if (dt_ops.get_path) + return dt_ops.get_path(phandle, buf, len); + + return NULL; +} + static inline void *malloc(unsigned long size) { return (platform_ops.malloc) ? platform_ops.malloc(size) : NULL; @@ -191,4 +203,25 @@ static inline void exit(void) static char _bss_stack[size]; \ void *_platform_stack_top = _bss_stack + sizeof(_bss_stack); +extern unsigned long timebase_period_ns; +void udelay(long delay); + +extern char _start[]; +extern char __bss_start[]; +extern char _end[]; +extern char _vmlinux_start[]; +extern char _vmlinux_end[]; +extern char _initrd_start[]; +extern char _initrd_end[]; +extern char _dtb_start[]; +extern char _dtb_end[]; + +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + int bit; + asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n)); + return 31 - bit; +} + #endif /* _PPC_BOOT_OPS_H_ */ diff -puN arch/powerpc/boot/ppcboot.h~git-powerpc arch/powerpc/boot/ppcboot.h --- a/arch/powerpc/boot/ppcboot.h~git-powerpc +++ a/arch/powerpc/boot/ppcboot.h @@ -78,17 +78,18 @@ typedef struct bd_info { hymod_conf_t bi_hymod_conf; /* hymod configuration information */ #endif #if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \ - defined(TARGET_85xx) || defined(TARGET_83xx) + defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1) /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; #define HAVE_ENET1ADDR #endif -#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || defined(TARGET_85xx) +#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \ + defined(TARGET_85xx) || defined(TARGET_HAS_ETH2) /* third onboard ethernet ports */ unsigned char bi_enet2addr[6]; #define HAVE_ENET2ADDR #endif -#if defined(TARGET_440GX) +#if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3) /* fourth onboard ethernet ports */ unsigned char bi_enet3addr[6]; #define HAVE_ENET3ADDR diff -puN arch/powerpc/boot/prpmc2800.c~git-powerpc arch/powerpc/boot/prpmc2800.c --- a/arch/powerpc/boot/prpmc2800.c~git-powerpc +++ a/arch/powerpc/boot/prpmc2800.c @@ -21,12 +21,6 @@ #include "gunzip_util.h" #include "mv64x60.h" -extern char _end[]; -extern char _vmlinux_start[], _vmlinux_end[]; -extern char _dtb_start[], _dtb_end[]; - -extern void udelay(long delay); - #define KB 1024U #define MB (KB*KB) #define GB (KB*MB) diff -puN arch/powerpc/boot/ps3.c~git-powerpc arch/powerpc/boot/ps3.c --- a/arch/powerpc/boot/ps3.c~git-powerpc +++ a/arch/powerpc/boot/ps3.c @@ -120,10 +120,6 @@ void ps3_copy_vectors(void) void platform_init(void) { - extern char _end[]; - extern char _dtb_start[]; - extern char _initrd_start[]; - extern char _initrd_end[]; const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */ void *chosen; unsigned long ft_addr; diff -puN arch/powerpc/boot/serial.c~git-powerpc arch/powerpc/boot/serial.c --- a/arch/powerpc/boot/serial.c~git-powerpc +++ a/arch/powerpc/boot/serial.c @@ -19,8 +19,6 @@ #include "io.h" #include "ops.h" -extern void udelay(long delay); - static int serial_open(void) { struct serial_console_data *scdp = console_ops.data; @@ -114,29 +112,32 @@ int serial_console_init(void) { void *devp; int rc = -1; - char compat[MAX_PROP_LEN]; devp = serial_get_stdout_devp(); if (devp == NULL) goto err_out; - if (getprop(devp, "compatible", compat, sizeof(compat)) < 0) - goto err_out; - - if (!strcmp(compat, "ns16550")) + if (dt_is_compatible(devp, "ns16550")) rc = ns16550_console_init(devp, &serial_cd); - else if (!strcmp(compat, "marvell,mpsc")) + else if (dt_is_compatible(devp, "marvell,mpsc")) rc = mpsc_console_init(devp, &serial_cd); + else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") || + dt_is_compatible(devp, "fsl,cpm1-smc-uart") || + dt_is_compatible(devp, "fsl,cpm2-scc-uart") || + dt_is_compatible(devp, "fsl,cpm2-smc-uart")) + rc = cpm_console_init(devp, &serial_cd); /* Add other serial console driver calls here */ if (!rc) { console_ops.open = serial_open; console_ops.write = serial_write; - console_ops.edit_cmdline = serial_edit_cmdline; console_ops.close = serial_close; console_ops.data = &serial_cd; + if (serial_cd.getc) + console_ops.edit_cmdline = serial_edit_cmdline; + return 0; } err_out: diff -puN /dev/null arch/powerpc/boot/stdlib.c --- /dev/null +++ a/arch/powerpc/boot/stdlib.c @@ -0,0 +1,45 @@ +/* + * stdlib functions + * + * Author: Scott Wood + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "stdlib.h" + +/* Not currently supported: leading whitespace, sign, 0x prefix, zero base */ +unsigned long long int strtoull(const char *ptr, char **end, int base) +{ + unsigned long long ret = 0; + + if (base > 36) + goto out; + + while (*ptr) { + int digit; + + if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base) + digit = *ptr - '0'; + else if (*ptr >= 'A' && *ptr < 'A' + base - 10) + digit = *ptr - 'A' + 10; + else if (*ptr >= 'a' && *ptr < 'a' + base - 10) + digit = *ptr - 'a' + 10; + else + break; + + ret *= base; + ret += digit; + ptr++; + } + +out: + if (end) + *end = (char *)ptr; + + return ret; +} diff -puN /dev/null arch/powerpc/boot/stdlib.h --- /dev/null +++ a/arch/powerpc/boot/stdlib.h @@ -0,0 +1,6 @@ +#ifndef _PPC_BOOT_STDLIB_H_ +#define _PPC_BOOT_STDLIB_H_ + +unsigned long long int strtoull(const char *ptr, char **end, int base); + +#endif diff -puN arch/powerpc/boot/string.S~git-powerpc arch/powerpc/boot/string.S --- a/arch/powerpc/boot/string.S~git-powerpc +++ a/arch/powerpc/boot/string.S @@ -49,6 +49,17 @@ strcat: bne 1b blr + .globl strchr +strchr: + addi r3,r3,-1 +1: lbzu r0,1(r3) + cmpw 0,r0,r4 + beqlr + cmpwi 0,r0,0 + bne 1b + li r3,0 + blr + .globl strcmp strcmp: addi r5,r3,-1 @@ -61,6 +72,19 @@ strcmp: beq 1b blr + .globl strncmp +strncmp: + mtctr r5 + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r3,1(r5) + cmpwi 1,r3,0 + lbzu r0,1(r4) + subf. r3,r0,r3 + beqlr 1 + bdnzt eq,1b + blr + .globl strlen strlen: addi r4,r3,-1 diff -puN arch/powerpc/boot/string.h~git-powerpc arch/powerpc/boot/string.h --- a/arch/powerpc/boot/string.h~git-powerpc +++ a/arch/powerpc/boot/string.h @@ -5,7 +5,9 @@ extern char *strcpy(char *dest, const char *src); extern char *strncpy(char *dest, const char *src, size_t n); extern char *strcat(char *dest, const char *src); +extern char *strchr(const char *s, int c); extern int strcmp(const char *s1, const char *s2); +extern int strncmp(const char *s1, const char *s2, size_t n); extern size_t strlen(const char *s); extern size_t strnlen(const char *s, size_t count); diff -puN /dev/null arch/powerpc/boot/treeboot-bamboo.c --- /dev/null +++ a/arch/powerpc/boot/treeboot-bamboo.c @@ -0,0 +1,43 @@ +/* + * Copyright IBM Corporation, 2007 + * Josh Boyer + * + * Based on ebony wrapper: + * Copyright 2007 David Gibson, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 of the License + */ +#include "ops.h" +#include "stdio.h" +#include "44x.h" +#include "stdlib.h" + +BSS_STACK(4096); + +#define PIBS_MAC0 0xfffc0400 +#define PIBS_MAC1 0xfffc0500 +char pibs_mac0[6]; +char pibs_mac1[6]; + +static void read_pibs_mac(void) +{ + unsigned long long mac64; + + mac64 = strtoull((char *)PIBS_MAC0, 0, 16); + memcpy(&pibs_mac0, (char *)&mac64+2, 6); + + mac64 = strtoull((char *)PIBS_MAC1, 0, 16); + memcpy(&pibs_mac1, (char *)&mac64+2, 6); +} + +void platform_init(void) +{ + unsigned long end_of_ram = 0x8000000; + unsigned long avail_ram = end_of_ram - (unsigned long)_end; + + simple_alloc_init(_end, avail_ram, 32, 64); + read_pibs_mac(); + bamboo_init((u8 *)&pibs_mac0, (u8 *)&pibs_mac1); +} diff -puN arch/powerpc/boot/treeboot-ebony.c~git-powerpc arch/powerpc/boot/treeboot-ebony.c --- a/arch/powerpc/boot/treeboot-ebony.c~git-powerpc +++ a/arch/powerpc/boot/treeboot-ebony.c @@ -16,8 +16,6 @@ #include "stdio.h" #include "44x.h" -extern char _end[]; - BSS_STACK(4096); #define OPENBIOS_MAC_BASE 0xfffffe0c diff -puN /dev/null arch/powerpc/boot/treeboot-walnut.c --- /dev/null +++ a/arch/powerpc/boot/treeboot-walnut.c @@ -0,0 +1,131 @@ +/* + * Old U-boot compatibility for Walnut + * + * Author: Josh Boyer + * + * Copyright 2007 IBM Corporation + * Based on cuboot-83xx.c, which is: + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "dcr.h" +#include "4xx.h" +#include "io.h" + +BSS_STACK(4096); + +void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) +{ + u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); + u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); + u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); + u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; + u32 fwdv, fbdv, cbdv, opdv, epdv, udiv; + + fwdv = (8 - ((pllmr & 0xe0000000) >> 29)); + fbdv = (pllmr & 0x1e000000) >> 25; + cbdv = ((pllmr & 0x00060000) >> 17) + 1; + opdv = ((pllmr & 0x00018000) >> 15) + 1; + epdv = ((pllmr & 0x00001800) >> 13) + 2; + udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1; + + m = fwdv * fbdv * cbdv; + + cpu = sysclk * m / fwdv; + plb = cpu / cbdv; + opb = plb / opdv; + ebc = plb / epdv; + + if (cpc0_cr0 & 0x80) { + /* uart0 uses the external clock */ + uart0 = ser_clk; + } else { + uart0 = cpu / udiv; + } + + if (cpc0_cr0 & 0x40) { + /* uart1 uses the external clock */ + uart1 = ser_clk; + } else { + uart1 = cpu / udiv; + } + + /* setup the timebase clock to tick at the cpu frequency */ + cpc0_cr1 = cpc0_cr1 & ~ 0x00800000; + mtdcr(DCRN_CPC0_CR1, cpc0_cr1); + tb = cpu; + + dt_fixup_cpu_clocks(cpu, tb, 0); + dt_fixup_clock("/plb", plb); + dt_fixup_clock("/plb/opb", opb); + dt_fixup_clock("/plb/ebc", ebc); + dt_fixup_clock("/plb/opb/serial@ef600300", uart0); + dt_fixup_clock("/plb/opb/serial@ef600400", uart1); +} + +static void walnut_flashsel_fixup(void) +{ + void *devp, *sram; + u32 reg_flash[3] = {0x0, 0x0, 0x80000}; + u32 reg_sram[3] = {0x0, 0x0, 0x80000}; + u8 *fpga; + u8 fpga_brds1 = 0x0; + + devp = finddevice("/plb/ebc/fpga"); + if (!devp) + fatal("Couldn't locate FPGA node\n\r"); + + if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) + fatal("no virtual-reg property\n\r"); + + fpga_brds1 = in_8(fpga); + + devp = finddevice("/plb/ebc/flash"); + if (!devp) + fatal("Couldn't locate flash node\n\r"); + + if (getprop(devp, "reg", reg_flash, sizeof(reg_flash)) != sizeof(reg_flash)) + fatal("flash reg property has unexpected size\n\r"); + + sram = finddevice("/plb/ebc/sram"); + if (!sram) + fatal("Couldn't locate sram node\n\r"); + + if (getprop(sram, "reg", reg_sram, sizeof(reg_sram)) != sizeof(reg_sram)) + fatal("sram reg property has unexpected size\n\r"); + + if (fpga_brds1 & 0x1) { + reg_flash[1] ^= 0x80000; + reg_sram[1] ^= 0x80000; + } + + setprop(devp, "reg", reg_flash, sizeof(reg_flash)); + setprop(sram, "reg", reg_sram, sizeof(reg_sram)); +} + +static void walnut_fixups(void) +{ + ibm4xx_fixup_memsize(); + ibm405gp_fixup_clocks(33330000, 0xa8c000); + ibm4xx_quiesce_eth((u32 *)0xef600800, NULL); + ibm4xx_fixup_ebc_ranges("/plb/ebc"); + walnut_flashsel_fixup(); +} + +void platform_init(void) +{ + unsigned long end_of_ram = 0x2000000; + unsigned long avail_ram = end_of_ram - (unsigned long) _end; + + simple_alloc_init(_end, avail_ram, 32, 32); + platform_ops.fixups = walnut_fixups; + platform_ops.exit = ibm40x_dbcr_reset; + ft_init(_dtb_start, _dtb_end - _dtb_start, 32); + serial_console_init(); +} diff -puN /dev/null arch/powerpc/configs/bamboo_defconfig --- /dev/null +++ a/arch/powerpc/configs/bamboo_defconfig @@ -0,0 +1,775 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc1 +# Fri Aug 3 10:46:53 2007 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_PPC_MERGE=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_IRQ_PER_CPU=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Platform support +# +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_MPC5200 is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_BAMBOO=y +# CONFIG_EBONY is not set +CONFIG_440EP=y +CONFIG_IBM440EP_ERR42=y +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPM2 is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_RESOURCES_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_PROC_DEVICETREE=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="" +CONFIG_SECCOMP=y +CONFIG_WANT_DEVICE_TREE=y +CONFIG_DEVICE_TREE="bamboo.dts" +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_DEBUG is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_HIGHMEM_START=0xfe000000 +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_TASK_SIZE=0x80000000 +CONFIG_CONSISTENT_START=0xff100000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_BOOT_LOAD=0x01000000 + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_MACINTOSH_DRIVERS=y +# CONFIG_MAC_EMUMOUSEBTN is not set +# CONFIG_WINDFARM is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +# CONFIG_FB_IBM_GXT4500 is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set +# CONFIG_UCC_SLOW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y + +# +# Instrumentation Support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_DEBUGGER=y +# CONFIG_KGDB is not set +# CONFIG_XMON is not set +# CONFIG_BDI_SWITCH is not set +CONFIG_PPC_EARLY_DEBUG=y +# CONFIG_PPC_EARLY_DEBUG_LPAR is not set +# CONFIG_PPC_EARLY_DEBUG_G5 is not set +# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set +# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set +# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set +# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set +# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set +# CONFIG_PPC_EARLY_DEBUG_BEAT is not set +CONFIG_PPC_EARLY_DEBUG_44x=y +CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0xef600300 +CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x0 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_HW=y diff -puN arch/powerpc/configs/ebony_defconfig~git-powerpc arch/powerpc/configs/ebony_defconfig --- a/arch/powerpc/configs/ebony_defconfig~git-powerpc +++ a/arch/powerpc/configs/ebony_defconfig @@ -313,7 +313,80 @@ CONFIG_FW_LOADER=y # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set CONFIG_OF_DEVICE=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y @@ -607,6 +680,15 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -665,6 +747,7 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y diff -puN arch/powerpc/configs/mpc8544_ds_defconfig~git-powerpc arch/powerpc/configs/mpc8544_ds_defconfig --- a/arch/powerpc/configs/mpc8544_ds_defconfig~git-powerpc +++ a/arch/powerpc/configs/mpc8544_ds_defconfig @@ -136,7 +136,7 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_MPC8560_ADS is not set # CONFIG_MPC85xx_CDS is not set # CONFIG_MPC85xx_MDS is not set -CONFIG_MPC8544_DS=y +CONFIG_MPC85xx_DS=y CONFIG_MPC85xx=y CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set diff -puN /dev/null arch/powerpc/configs/mpc8572_ds_defconfig --- /dev/null +++ a/arch/powerpc/configs/mpc8572_ds_defconfig @@ -0,0 +1,1496 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc4 +# Tue Sep 11 01:19:35 2007 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +CONFIG_PPC_85xx=y +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_85xx=y +CONFIG_E500=y +CONFIG_BOOKE=y +CONFIG_FSL_BOOKE=y +# CONFIG_PHYS_64BIT is not set +CONFIG_SPE=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_PPC32=y +CONFIG_PPC_MERGE=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_IRQ_PER_CPU=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# Platform support +# +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_MPC5200 is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_MPC8540_ADS is not set +# CONFIG_MPC8560_ADS is not set +# CONFIG_MPC85xx_CDS is not set +# CONFIG_MPC85xx_MDS is not set +CONFIG_MPC85xx_DS=y +CONFIG_MPC85xx=y +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +CONFIG_PPC_I8259=y +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPM2 is not set +CONFIG_FSL_ULI1575=y + +# +# Kernel options +# +CONFIG_HIGHMEM=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_MISC=m +CONFIG_MATH_EMULATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_PROC_DEVICETREE=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_PM is not set +CONFIG_SECCOMP=y +CONFIG_WANT_DEVICE_TREE=y +CONFIG_DEVICE_TREE="" +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_FSL_SOC=y +CONFIG_FSL_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_DEBUG is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_HIGHMEM_START=0xfe000000 +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_TASK_SIZE=0x80000000 +CONFIG_BOOT_LOAD=0x00800000 + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE=y +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_AHCI=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +CONFIG_PATA_ALI=y +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +CONFIG_GIANFAR=y +CONFIG_GFAR_NAPI=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +CONFIG_GEN_RTC=y +CONFIG_GEN_RTC_X=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +CONFIG_I2C_MPC=y +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +CONFIG_SENSORS_EEPROM=y +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_M41T00 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +CONFIG_DVB_CORE=m +# CONFIG_DVB_CORE_ATTACH is not set +CONFIG_DVB_CAPTURE_DRIVERS=y + +# +# Supported SAA7146 based PCI Adapters +# + +# +# Supported USB Adapters +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_DVB_CINERGYT2 is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported BT878 Adapters +# + +# +# Supported Pluto2 Adapters +# +# CONFIG_DVB_PLUTO2 is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_TDA10086 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set + +# +# Tuners/PLL support +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TDA827X is not set +# CONFIG_DVB_TUNER_QT1010 is not set +# CONFIG_DVB_TUNER_MT2060 is not set + +# +# Miscellaneous devices +# +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_TUA6100 is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +# CONFIG_FB is not set +# CONFIG_FB_IBM_GXT4500 is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALS4000 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5530 is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +CONFIG_SND_INTEL8X0=y +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_AC97_POWER_SAVE is not set + +# +# ALSA PowerMac devices +# + +# +# ALSA PowerPC devices +# + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_USX2Y is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# SoC Audio support for SuperH +# + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PPC_OF=y +CONFIG_USB_OHCI_HCD_PPC_OF_BE=y +CONFIG_USB_OHCI_HCD_PPC_OF_LE=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_CRAMFS=y +CONFIG_VXFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +CONFIG_NFSD_TCP=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set +# CONFIG_UCC_SLOW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y + +# +# Instrumentation Support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUGGER is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_ECB is not set +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_HW=y diff -puN /dev/null arch/powerpc/configs/sequoia_defconfig --- /dev/null +++ a/arch/powerpc/configs/sequoia_defconfig @@ -0,0 +1,861 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc6 +# Fri Sep 14 13:20:06 2007 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_PPC_MERGE=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_IRQ_PER_CPU=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Platform support +# +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_MPC5200 is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +CONFIG_SEQUOIA=y +CONFIG_440EPX=y +CONFIG_440A=y +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPM2 is not set +# CONFIG_FSL_ULI1575 is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_RESOURCES_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_PROC_DEVICETREE=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="" +CONFIG_SECCOMP=y +CONFIG_WANT_DEVICE_TREE=y +CONFIG_DEVICE_TREE="sequoia.dts" +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_DEBUG is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_HIGHMEM_START=0xfe000000 +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_TASK_SIZE=0x80000000 +CONFIG_CONSISTENT_START=0xff100000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_BOOT_LOAD=0x01000000 + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_MACINTOSH_DRIVERS=y +# CONFIG_MAC_EMUMOUSEBTN is not set +# CONFIG_WINDFARM is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +# CONFIG_FB_IBM_GXT4500 is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set +# CONFIG_UCC_SLOW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y + +# +# Instrumentation Support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_DEBUGGER=y +# CONFIG_KGDB is not set +# CONFIG_XMON is not set +# CONFIG_BDI_SWITCH is not set +CONFIG_PPC_EARLY_DEBUG=y +# CONFIG_PPC_EARLY_DEBUG_LPAR is not set +# CONFIG_PPC_EARLY_DEBUG_G5 is not set +# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set +# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set +# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set +# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set +# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set +# CONFIG_PPC_EARLY_DEBUG_BEAT is not set +CONFIG_PPC_EARLY_DEBUG_44x=y +CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0xef600300 +CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x1 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_HW=y diff -puN /dev/null arch/powerpc/configs/walnut_defconfig --- /dev/null +++ a/arch/powerpc/configs/walnut_defconfig @@ -0,0 +1,773 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc4 +# Wed Sep 5 12:06:37 2007 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +CONFIG_40x=y +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_4xx=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_PPC_MERGE=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_IRQ_PER_CPU=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +# CONFIG_PPC_UDBG_16550 is not set +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Platform support +# +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_MPC5200 is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_WALNUT=y +CONFIG_405GP=y +CONFIG_IBM405_ERR77=y +CONFIG_IBM405_ERR51=y +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPM2 is not set +# CONFIG_FSL_ULI1575 is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_RESOURCES_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_PROC_DEVICETREE=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_PM is not set +CONFIG_SECCOMP=y +CONFIG_WANT_DEVICE_TREE=y +CONFIG_DEVICE_TREE="walnut.dts" +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_HIGHMEM_START=0xfe000000 +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_TASK_SIZE=0x80000000 +CONFIG_CONSISTENT_START=0xff100000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_BOOT_LOAD=0x00400000 + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_WALNUT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +# CONFIG_FB_IBM_GXT4500 is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set +# CONFIG_UCC_SLOW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y + +# +# Instrumentation Support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUGGER is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_HW=y diff -puN arch/powerpc/kernel/Makefile~git-powerpc arch/powerpc/kernel/Makefile --- a/arch/powerpc/kernel/Makefile~git-powerpc +++ a/arch/powerpc/kernel/Makefile @@ -46,7 +46,7 @@ ifeq ($(CONFIG_PPC_MERGE),y) extra-$(CONFIG_PPC_STD_MMU) := head_32.o extra-$(CONFIG_PPC64) := head_64.o -extra-$(CONFIG_40x) := head_4xx.o +extra-$(CONFIG_40x) := head_40x.o extra-$(CONFIG_44x) := head_44x.o extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o extra-$(CONFIG_8xx) := head_8xx.o @@ -80,13 +80,6 @@ ifneq ($(CONFIG_PPC_INDIRECT_IO),y) obj-y += iomap.o endif -ifeq ($(CONFIG_PPC_ISERIES),y) -CFLAGS_lparmap.s += -g0 -extra-y += lparmap.s -$(obj)/head_64.o: $(obj)/lparmap.s -AFLAGS_head_64.o += -I$(obj) -endif - else # stuff used from here for ARCH=ppc smpobj-$(CONFIG_SMP) += smp.o diff -puN arch/powerpc/kernel/align.c~git-powerpc arch/powerpc/kernel/align.c --- a/arch/powerpc/kernel/align.c~git-powerpc +++ a/arch/powerpc/kernel/align.c @@ -38,7 +38,7 @@ struct aligninfo { /* Bits in the flags field */ #define LD 0 /* load */ #define ST 1 /* store */ -#define SE 2 /* sign-extend value */ +#define SE 2 /* sign-extend value, or FP ld/st as word */ #define F 4 /* to/from fp regs */ #define U 8 /* update index register */ #define M 0x10 /* multiple load/store */ @@ -46,6 +46,8 @@ struct aligninfo { #define S 0x40 /* single-precision fp or... */ #define SX 0x40 /* ... byte count in XER */ #define HARD 0x80 /* string, stwcx. */ +#define E4 0x40 /* SPE endianness is word */ +#define E8 0x80 /* SPE endianness is double word */ /* DSISR bits reported for a DCBZ instruction: */ #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */ @@ -87,9 +89,9 @@ static struct aligninfo aligninfo[128] = { 8, LD+F+U }, /* 00 1 1001: lfdu */ { 4, ST+F+S+U }, /* 00 1 1010: stfsu */ { 8, ST+F+U }, /* 00 1 1011: stfdu */ - INVALID, /* 00 1 1100 */ + { 16, LD+F }, /* 00 1 1100: lfdp */ INVALID, /* 00 1 1101 */ - INVALID, /* 00 1 1110 */ + { 16, ST+F }, /* 00 1 1110: stfdp */ INVALID, /* 00 1 1111 */ { 8, LD }, /* 01 0 0000: ldx */ INVALID, /* 01 0 0001 */ @@ -167,10 +169,10 @@ static struct aligninfo aligninfo[128] = { 8, LD+F }, /* 11 0 1001: lfdx */ { 4, ST+F+S }, /* 11 0 1010: stfsx */ { 8, ST+F }, /* 11 0 1011: stfdx */ - INVALID, /* 11 0 1100 */ - { 8, LD+M }, /* 11 0 1101: lmd */ - INVALID, /* 11 0 1110 */ - { 8, ST+M }, /* 11 0 1111: stmd */ + { 16, LD+F }, /* 11 0 1100: lfdpx */ + { 4, LD+F+SE }, /* 11 0 1101: lfiwax */ + { 16, ST+F }, /* 11 0 1110: stfdpx */ + { 4, ST+F }, /* 11 0 1111: stfiwx */ { 4, LD+U }, /* 11 1 0000: lwzux */ INVALID, /* 11 1 0001 */ { 4, ST+U }, /* 11 1 0010: stwux */ @@ -356,6 +358,284 @@ static int emulate_multiple(struct pt_re return 1; } +/* + * Emulate floating-point pair loads and stores. + * Only POWER6 has these instructions, and it does true little-endian, + * so we don't need the address swizzling. + */ +static int emulate_fp_pair(struct pt_regs *regs, unsigned char __user *addr, + unsigned int reg, unsigned int flags) +{ + char *ptr = (char *) ¤t->thread.fpr[reg]; + int i, ret; + + if (!(flags & F)) + return 0; + if (reg & 1) + return 0; /* invalid form: FRS/FRT must be even */ + if (!(flags & SW)) { + /* not byte-swapped - easy */ + if (!(flags & ST)) + ret = __copy_from_user(ptr, addr, 16); + else + ret = __copy_to_user(addr, ptr, 16); + } else { + /* each FPR value is byte-swapped separately */ + ret = 0; + for (i = 0; i < 16; ++i) { + if (!(flags & ST)) + ret |= __get_user(ptr[i^7], addr + i); + else + ret |= __put_user(ptr[i^7], addr + i); + } + } + if (ret) + return -EFAULT; + return 1; /* exception handled and fixed up */ +} + +#ifdef CONFIG_SPE + +static struct aligninfo spe_aligninfo[32] = { + { 8, LD+E8 }, /* 0 00 00: evldd[x] */ + { 8, LD+E4 }, /* 0 00 01: evldw[x] */ + { 8, LD }, /* 0 00 10: evldh[x] */ + INVALID, /* 0 00 11 */ + { 2, LD }, /* 0 01 00: evlhhesplat[x] */ + INVALID, /* 0 01 01 */ + { 2, LD }, /* 0 01 10: evlhhousplat[x] */ + { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */ + { 4, LD }, /* 0 10 00: evlwhe[x] */ + INVALID, /* 0 10 01 */ + { 4, LD }, /* 0 10 10: evlwhou[x] */ + { 4, LD+SE }, /* 0 10 11: evlwhos[x] */ + { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */ + INVALID, /* 0 11 01 */ + { 4, LD }, /* 0 11 10: evlwhsplat[x] */ + INVALID, /* 0 11 11 */ + + { 8, ST+E8 }, /* 1 00 00: evstdd[x] */ + { 8, ST+E4 }, /* 1 00 01: evstdw[x] */ + { 8, ST }, /* 1 00 10: evstdh[x] */ + INVALID, /* 1 00 11 */ + INVALID, /* 1 01 00 */ + INVALID, /* 1 01 01 */ + INVALID, /* 1 01 10 */ + INVALID, /* 1 01 11 */ + { 4, ST }, /* 1 10 00: evstwhe[x] */ + INVALID, /* 1 10 01 */ + { 4, ST }, /* 1 10 10: evstwho[x] */ + INVALID, /* 1 10 11 */ + { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */ + INVALID, /* 1 11 01 */ + { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */ + INVALID, /* 1 11 11 */ +}; + +#define EVLDD 0x00 +#define EVLDW 0x01 +#define EVLDH 0x02 +#define EVLHHESPLAT 0x04 +#define EVLHHOUSPLAT 0x06 +#define EVLHHOSSPLAT 0x07 +#define EVLWHE 0x08 +#define EVLWHOU 0x0A +#define EVLWHOS 0x0B +#define EVLWWSPLAT 0x0C +#define EVLWHSPLAT 0x0E +#define EVSTDD 0x10 +#define EVSTDW 0x11 +#define EVSTDH 0x12 +#define EVSTWHE 0x18 +#define EVSTWHO 0x1A +#define EVSTWWE 0x1C +#define EVSTWWO 0x1E + +/* + * Emulate SPE loads and stores. + * Only Book-E has these instructions, and it does true little-endian, + * so we don't need the address swizzling. + */ +static int emulate_spe(struct pt_regs *regs, unsigned int reg, + unsigned int instr) +{ + int t, ret; + union { + u64 ll; + u32 w[2]; + u16 h[4]; + u8 v[8]; + } data, temp; + unsigned char __user *p, *addr; + unsigned long *evr = ¤t->thread.evr[reg]; + unsigned int nb, flags; + + instr = (instr >> 1) & 0x1f; + + /* DAR has the operand effective address */ + addr = (unsigned char __user *)regs->dar; + + nb = spe_aligninfo[instr].len; + flags = spe_aligninfo[instr].flags; + + /* Verify the address of the operand */ + if (unlikely(user_mode(regs) && + !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ), + addr, nb))) + return -EFAULT; + + /* userland only */ + if (unlikely(!user_mode(regs))) + return 0; + + flush_spe_to_thread(current); + + /* If we are loading, get the data from user space, else + * get it from register values + */ + if (flags & ST) { + data.ll = 0; + switch (instr) { + case EVSTDD: + case EVSTDW: + case EVSTDH: + data.w[0] = *evr; + data.w[1] = regs->gpr[reg]; + break; + case EVSTWHE: + data.h[2] = *evr >> 16; + data.h[3] = regs->gpr[reg] >> 16; + break; + case EVSTWHO: + data.h[2] = *evr & 0xffff; + data.h[3] = regs->gpr[reg] & 0xffff; + break; + case EVSTWWE: + data.w[1] = *evr; + break; + case EVSTWWO: + data.w[1] = regs->gpr[reg]; + break; + default: + return -EINVAL; + } + } else { + temp.ll = data.ll = 0; + ret = 0; + p = addr; + + switch (nb) { + case 8: + ret |= __get_user_inatomic(temp.v[0], p++); + ret |= __get_user_inatomic(temp.v[1], p++); + ret |= __get_user_inatomic(temp.v[2], p++); + ret |= __get_user_inatomic(temp.v[3], p++); + case 4: + ret |= __get_user_inatomic(temp.v[4], p++); + ret |= __get_user_inatomic(temp.v[5], p++); + case 2: + ret |= __get_user_inatomic(temp.v[6], p++); + ret |= __get_user_inatomic(temp.v[7], p++); + if (unlikely(ret)) + return -EFAULT; + } + + switch (instr) { + case EVLDD: + case EVLDW: + case EVLDH: + data.ll = temp.ll; + break; + case EVLHHESPLAT: + data.h[0] = temp.h[3]; + data.h[2] = temp.h[3]; + break; + case EVLHHOUSPLAT: + case EVLHHOSSPLAT: + data.h[1] = temp.h[3]; + data.h[3] = temp.h[3]; + break; + case EVLWHE: + data.h[0] = temp.h[2]; + data.h[2] = temp.h[3]; + break; + case EVLWHOU: + case EVLWHOS: + data.h[1] = temp.h[2]; + data.h[3] = temp.h[3]; + break; + case EVLWWSPLAT: + data.w[0] = temp.w[1]; + data.w[1] = temp.w[1]; + break; + case EVLWHSPLAT: + data.h[0] = temp.h[2]; + data.h[1] = temp.h[2]; + data.h[2] = temp.h[3]; + data.h[3] = temp.h[3]; + break; + default: + return -EINVAL; + } + } + + if (flags & SW) { + switch (flags & 0xf0) { + case E8: + SWAP(data.v[0], data.v[7]); + SWAP(data.v[1], data.v[6]); + SWAP(data.v[2], data.v[5]); + SWAP(data.v[3], data.v[4]); + break; + case E4: + + SWAP(data.v[0], data.v[3]); + SWAP(data.v[1], data.v[2]); + SWAP(data.v[4], data.v[7]); + SWAP(data.v[5], data.v[6]); + break; + /* Its half word endian */ + default: + SWAP(data.v[0], data.v[1]); + SWAP(data.v[2], data.v[3]); + SWAP(data.v[4], data.v[5]); + SWAP(data.v[6], data.v[7]); + break; + } + } + + if (flags & SE) { + data.w[0] = (s16)data.h[1]; + data.w[1] = (s16)data.h[3]; + } + + /* Store result to memory or update registers */ + if (flags & ST) { + ret = 0; + p = addr; + switch (nb) { + case 8: + ret |= __put_user_inatomic(data.v[0], p++); + ret |= __put_user_inatomic(data.v[1], p++); + ret |= __put_user_inatomic(data.v[2], p++); + ret |= __put_user_inatomic(data.v[3], p++); + case 4: + ret |= __put_user_inatomic(data.v[4], p++); + ret |= __put_user_inatomic(data.v[5], p++); + case 2: + ret |= __put_user_inatomic(data.v[6], p++); + ret |= __put_user_inatomic(data.v[7], p++); + } + if (unlikely(ret)) + return -EFAULT; + } else { + *evr = data.w[0]; + regs->gpr[reg] = data.w[1]; + } + + return 1; +} +#endif /* CONFIG_SPE */ /* * Called on alignment exception. Attempts to fixup @@ -414,6 +694,12 @@ int fix_alignment(struct pt_regs *regs) /* extract the operation and registers from the dsisr */ reg = (dsisr >> 5) & 0x1f; /* source/dest register */ areg = dsisr & 0x1f; /* register to update */ + +#ifdef CONFIG_SPE + if ((instr >> 26) == 0x4) + return emulate_spe(regs, reg, instr); +#endif + instr = (dsisr >> 10) & 0x7f; instr |= (dsisr >> 13) & 0x60; @@ -471,6 +757,10 @@ int fix_alignment(struct pt_regs *regs) flush_fp_to_thread(current); } + /* Special case for 16-byte FP loads and stores */ + if (nb == 16) + return emulate_fp_pair(regs, addr, reg, flags); + /* If we are loading, get the data from user space, else * get it from register values */ @@ -531,7 +821,8 @@ int fix_alignment(struct pt_regs *regs) * or floating point single precision conversion */ switch (flags & ~(U|SW)) { - case LD+SE: /* sign extend */ + case LD+SE: /* sign extending integer loads */ + case LD+F+SE: /* sign extend for lfiwax */ if ( nb == 2 ) data.ll = data.x16.low16; else /* nb must be 4 */ diff -puN arch/powerpc/kernel/asm-offsets.c~git-powerpc arch/powerpc/kernel/asm-offsets.c --- a/arch/powerpc/kernel/asm-offsets.c~git-powerpc +++ a/arch/powerpc/kernel/asm-offsets.c @@ -312,5 +312,17 @@ int main(void) #ifdef CONFIG_BUG DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry)); #endif + +#ifdef CONFIG_PPC_ISERIES + /* the assembler miscalculates the VSID values */ + DEFINE(PAGE_OFFSET_ESID, GET_ESID(PAGE_OFFSET)); + DEFINE(PAGE_OFFSET_VSID, KERNEL_VSID(PAGE_OFFSET)); + DEFINE(VMALLOC_START_ESID, GET_ESID(VMALLOC_START)); + DEFINE(VMALLOC_START_VSID, KERNEL_VSID(VMALLOC_START)); +#endif + +#ifdef CONFIG_PPC64 + DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE); +#endif return 0; } diff -puN arch/powerpc/kernel/btext.c~git-powerpc arch/powerpc/kernel/btext.c --- a/arch/powerpc/kernel/btext.c~git-powerpc +++ a/arch/powerpc/kernel/btext.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff -puN arch/powerpc/kernel/cputable.c~git-powerpc arch/powerpc/kernel/cputable.c --- a/arch/powerpc/kernel/cputable.c~git-powerpc +++ a/arch/powerpc/kernel/cputable.c @@ -68,15 +68,6 @@ extern void __restore_cpu_ppc970(void); #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ PPC_FEATURE_BOOKE) -/* We only set the spe features if the kernel was compiled with - * spe support - */ -#ifdef CONFIG_SPE -#define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE -#else -#define PPC_FEATURE_SPE_COMP 0 -#endif - static struct cpu_spec cpu_specs[] = { #ifdef CONFIG_PPC64 { /* Power3 */ @@ -1132,6 +1123,24 @@ static struct cpu_spec cpu_specs[] = { .dcache_bsize = 32, .platform = "ppc440", }, + { /* 440EPX */ + .pvr_mask = 0xf0000ffb, + .pvr_value = 0x200008D0, + .cpu_name = "440EPX", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, + .icache_bsize = 32, + .dcache_bsize = 32, + }, + { /* 440GRX */ + .pvr_mask = 0xf0000ffb, + .pvr_value = 0x200008D8, + .cpu_name = "440GRX", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE, + .icache_bsize = 32, + .dcache_bsize = 32, + }, { /* 440GP Rev. B */ .pvr_mask = 0xf0000fff, .pvr_value = 0x40000440, @@ -1243,8 +1252,8 @@ static struct cpu_spec cpu_specs[] = { /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E200, .cpu_user_features = COMMON_USER_BOOKE | - PPC_FEATURE_SPE_COMP | - PPC_FEATURE_HAS_EFP_SINGLE | + PPC_FEATURE_HAS_SPE_COMP | + PPC_FEATURE_HAS_EFP_SINGLE_COMP | PPC_FEATURE_UNIFIED_CACHE, .dcache_bsize = 32, .platform = "ppc5554", @@ -1256,8 +1265,8 @@ static struct cpu_spec cpu_specs[] = { /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E500, .cpu_user_features = COMMON_USER_BOOKE | - PPC_FEATURE_SPE_COMP | - PPC_FEATURE_HAS_EFP_SINGLE, + PPC_FEATURE_HAS_SPE_COMP | + PPC_FEATURE_HAS_EFP_SINGLE_COMP, .icache_bsize = 32, .dcache_bsize = 32, .num_pmcs = 4, @@ -1272,9 +1281,9 @@ static struct cpu_spec cpu_specs[] = { /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E500_2, .cpu_user_features = COMMON_USER_BOOKE | - PPC_FEATURE_SPE_COMP | - PPC_FEATURE_HAS_EFP_SINGLE | - PPC_FEATURE_HAS_EFP_DOUBLE, + PPC_FEATURE_HAS_SPE_COMP | + PPC_FEATURE_HAS_EFP_SINGLE_COMP | + PPC_FEATURE_HAS_EFP_DOUBLE_COMP, .icache_bsize = 32, .dcache_bsize = 32, .num_pmcs = 4, diff -puN arch/powerpc/kernel/crash.c~git-powerpc arch/powerpc/kernel/crash.c --- a/arch/powerpc/kernel/crash.c~git-powerpc +++ a/arch/powerpc/kernel/crash.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff -puN arch/powerpc/kernel/crash_dump.c~git-powerpc arch/powerpc/kernel/crash_dump.c --- a/arch/powerpc/kernel/crash_dump.c~git-powerpc +++ a/arch/powerpc/kernel/crash_dump.c @@ -25,7 +25,7 @@ #define DBG(fmt...) #endif -void reserve_kdump_trampoline(void) +void __init reserve_kdump_trampoline(void) { lmb_reserve(0, KDUMP_RESERVE_LIMIT); } @@ -54,8 +54,10 @@ void __init setup_kdump_trampoline(void) create_trampoline(i); } +#ifdef CONFIG_PPC_PSERIES create_trampoline(__pa(system_reset_fwnmi) - PHYSICAL_START); create_trampoline(__pa(machine_check_fwnmi) - PHYSICAL_START); +#endif /* CONFIG_PPC_PSERIES */ DBG(" <- setup_kdump_trampoline()\n"); } diff -puN arch/powerpc/kernel/entry_32.S~git-powerpc arch/powerpc/kernel/entry_32.S --- a/arch/powerpc/kernel/entry_32.S~git-powerpc +++ a/arch/powerpc/kernel/entry_32.S @@ -504,9 +504,11 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) #endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_SPE +BEGIN_FTR_SECTION oris r0,r0,MSR_SPE@h /* Disable SPE */ mfspr r12,SPRN_SPEFSCR /* save spefscr register value */ stw r12,THREAD+THREAD_SPEFSCR(r2) +END_FTR_SECTION_IFSET(CPU_FTR_SPE) #endif /* CONFIG_SPE */ and. r0,r0,r11 /* FP or altivec or SPE enabled? */ beq+ 1f @@ -542,8 +544,10 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) #endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_SPE +BEGIN_FTR_SECTION lwz r0,THREAD+THREAD_SPEFSCR(r2) mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */ +END_FTR_SECTION_IFSET(CPU_FTR_SPE) #endif /* CONFIG_SPE */ lwz r0,_CCR(r1) diff -puN arch/powerpc/kernel/entry_64.S~git-powerpc arch/powerpc/kernel/entry_64.S --- a/arch/powerpc/kernel/entry_64.S~git-powerpc +++ a/arch/powerpc/kernel/entry_64.S @@ -385,15 +385,15 @@ BEGIN_FTR_SECTION oris r0,r6,(SLB_ESID_V)@h ori r0,r0,(SLB_NUM_BOLTED-1)@l - /* Update the last bolted SLB */ + /* Update the last bolted SLB. No write barriers are needed + * here, provided we only update the current CPU's SLB shadow + * buffer. + */ ld r9,PACA_SLBSHADOWPTR(r13) li r12,0 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ - eieio std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */ - eieio std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */ - eieio slbie r6 slbie r6 /* Workaround POWER5 < DD2.1 issue */ diff -puN arch/powerpc/kernel/head_32.S~git-powerpc arch/powerpc/kernel/head_32.S --- a/arch/powerpc/kernel/head_32.S~git-powerpc +++ a/arch/powerpc/kernel/head_32.S @@ -48,20 +48,17 @@ mtspr SPRN_DBAT##n##L,RB; \ 1: - .text + .section .text.head, "ax" .stabs "arch/powerpc/kernel/",N_SO,0,0,0f .stabs "head_32.S",N_SO,0,0,0f 0: - .globl _stext -_stext: +_ENTRY(_stext); /* * _start is defined this way because the XCOFF loader in the OpenFirmware * on the powermac expects the entry point to be a procedure descriptor. */ - .text - .globl _start -_start: +_ENTRY(_start); /* * These are here for legacy reasons, the kernel used to * need to look like a coff function entry for the pmac @@ -475,10 +472,10 @@ InstructionTLBMiss: li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ lwz r2,PGDIR(r2) blt+ 112f + mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ + rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ lis r2,swapper_pg_dir@ha /* if kernel address, use */ addi r2,r2,swapper_pg_dir@l /* kernel page table */ - mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ - rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ 112: tophys(r2,r2) rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ lwz r2,0(r2) /* get pmd entry */ @@ -549,10 +546,10 @@ DataLoadTLBMiss: li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ lwz r2,PGDIR(r2) blt+ 112f + mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ + rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ lis r2,swapper_pg_dir@ha /* if kernel address, use */ addi r2,r2,swapper_pg_dir@l /* kernel page table */ - mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ - rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ 112: tophys(r2,r2) rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ lwz r2,0(r2) /* get pmd entry */ @@ -621,10 +618,10 @@ DataStoreTLBMiss: li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ lwz r2,PGDIR(r2) blt+ 112f + mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ + rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ lis r2,swapper_pg_dir@ha /* if kernel address, use */ addi r2,r2,swapper_pg_dir@l /* kernel page table */ - mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ - rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ 112: tophys(r2,r2) rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ lwz r2,0(r2) /* get pmd entry */ @@ -841,7 +838,7 @@ relocate_kernel: * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. */ -_GLOBAL(copy_and_flush) +_ENTRY(copy_and_flush) addi r5,r5,-4 addi r6,r6,-4 4: li r0,L1_CACHE_BYTES/4 @@ -954,9 +951,9 @@ __secondary_start: * included in CONFIG_6xx */ #if !defined(CONFIG_6xx) -_GLOBAL(__save_cpu_setup) +_ENTRY(__save_cpu_setup) blr -_GLOBAL(__restore_cpu_setup) +_ENTRY(__restore_cpu_setup) blr #endif /* !defined(CONFIG_6xx) */ @@ -1080,7 +1077,7 @@ start_here: /* * Set up the segment registers for a new context. */ -_GLOBAL(set_context) +_ENTRY(set_context) mulli r3,r3,897 /* multiply context by skew factor */ rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ addis r3,r3,0x6000 /* Set Ks, Ku bits */ @@ -1300,14 +1297,6 @@ empty_zero_page: swapper_pg_dir: .space 4096 -/* - * This space gets a copy of optional info passed to us by the bootstrap - * Used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - .globl intercept_table intercept_table: .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700 diff -puN /dev/null arch/powerpc/kernel/head_40x.S --- /dev/null +++ a/arch/powerpc/kernel/head_40x.S @@ -0,0 +1,1013 @@ +/* + * Copyright (c) 1995-1996 Gary Thomas + * Initial PowerPC version. + * Copyright (c) 1996 Cort Dougan + * Rewritten for PReP + * Copyright (c) 1996 Paul Mackerras + * Low-level exception handers, MMU support, and rewrite. + * Copyright (c) 1997 Dan Malek + * PowerPC 8xx modifications. + * Copyright (c) 1998-1999 TiVo, Inc. + * PowerPC 403GCX modifications. + * Copyright (c) 1999 Grant Erickson + * PowerPC 403GCX/405GP modifications. + * Copyright 2000 MontaVista Software Inc. + * PPC405 modifications + * PowerPC 403GCX/405GP modifications. + * Author: MontaVista Software, Inc. + * frank_rowand@mvista.com or source@mvista.com + * debbie_chu@mvista.com + * + * + * Module name: head_4xx.S + * + * Description: + * Kernel execution entry point code. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* As with the other PowerPC ports, it is expected that when code + * execution begins here, the following registers contain valid, yet + * optional, information: + * + * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) + * r4 - Starting address of the init RAM disk + * r5 - Ending address of the init RAM disk + * r6 - Start of kernel command line string (e.g. "mem=96m") + * r7 - End of kernel command line string + * + * This is all going to change RSN when we add bi_recs....... -- Dan + */ + .section .text.head, "ax" +_ENTRY(_stext); +_ENTRY(_start); + + /* Save parameters we are passed. + */ + mr r31,r3 + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + + /* We have to turn on the MMU right away so we get cache modes + * set correctly. + */ + bl initial_mmu + +/* We now have the lower 16 Meg mapped into TLB entries, and the caches + * ready to work. + */ +turn_on_mmu: + lis r0,MSR_KERNEL@h + ori r0,r0,MSR_KERNEL@l + mtspr SPRN_SRR1,r0 + lis r0,start_here@h + ori r0,r0,start_here@l + mtspr SPRN_SRR0,r0 + SYNC + rfi /* enables MMU */ + b . /* prevent prefetch past rfi */ + +/* + * This area is used for temporarily saving registers during the + * critical exception prolog. + */ + . = 0xc0 +crit_save: +_ENTRY(crit_r10) + .space 4 +_ENTRY(crit_r11) + .space 4 + +/* + * Exception vector entry code. This code runs with address translation + * turned off (i.e. using physical addresses). We assume SPRG3 has the + * physical address of the current task thread_struct. + * Note that we have to have decremented r1 before we write to any fields + * of the exception frame, since a critical interrupt could occur at any + * time, and it will write to the area immediately below the current r1. + */ +#define NORMAL_EXCEPTION_PROLOG \ + mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ + mtspr SPRN_SPRG1,r11; \ + mtspr SPRN_SPRG2,r1; \ + mfcr r10; /* save CR in r10 for now */\ + mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ + andi. r11,r11,MSR_PR; \ + beq 1f; \ + mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ + lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ + addi r1,r1,THREAD_SIZE; \ +1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ + tophys(r11,r1); \ + stw r10,_CCR(r11); /* save various registers */\ + stw r12,GPR12(r11); \ + stw r9,GPR9(r11); \ + mfspr r10,SPRN_SPRG0; \ + stw r10,GPR10(r11); \ + mfspr r12,SPRN_SPRG1; \ + stw r12,GPR11(r11); \ + mflr r10; \ + stw r10,_LINK(r11); \ + mfspr r10,SPRN_SPRG2; \ + mfspr r12,SPRN_SRR0; \ + stw r10,GPR1(r11); \ + mfspr r9,SPRN_SRR1; \ + stw r10,0(r11); \ + rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ + stw r0,GPR0(r11); \ + SAVE_4GPRS(3, r11); \ + SAVE_2GPRS(7, r11) + +/* + * Exception prolog for critical exceptions. This is a little different + * from the normal exception prolog above since a critical exception + * can potentially occur at any point during normal exception processing. + * Thus we cannot use the same SPRG registers as the normal prolog above. + * Instead we use a couple of words of memory at low physical addresses. + * This is OK since we don't support SMP on these processors. + */ +#define CRITICAL_EXCEPTION_PROLOG \ + stw r10,crit_r10@l(0); /* save two registers to work with */\ + stw r11,crit_r11@l(0); \ + mfcr r10; /* save CR in r10 for now */\ + mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ + andi. r11,r11,MSR_PR; \ + lis r11,critical_stack_top@h; \ + ori r11,r11,critical_stack_top@l; \ + beq 1f; \ + /* COMING FROM USER MODE */ \ + mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ + lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ + addi r11,r11,THREAD_SIZE; \ +1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ + tophys(r11,r11); \ + stw r10,_CCR(r11); /* save various registers */\ + stw r12,GPR12(r11); \ + stw r9,GPR9(r11); \ + mflr r10; \ + stw r10,_LINK(r11); \ + mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ + stw r12,_DEAR(r11); /* since they may have had stuff */\ + mfspr r9,SPRN_ESR; /* in them at the point where the */\ + stw r9,_ESR(r11); /* exception was taken */\ + mfspr r12,SPRN_SRR2; \ + stw r1,GPR1(r11); \ + mfspr r9,SPRN_SRR3; \ + stw r1,0(r11); \ + tovirt(r1,r11); \ + rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ + stw r0,GPR0(r11); \ + SAVE_4GPRS(3, r11); \ + SAVE_2GPRS(7, r11) + + /* + * State at this point: + * r9 saved in stack frame, now saved SRR3 & ~MSR_WE + * r10 saved in crit_r10 and in stack frame, trashed + * r11 saved in crit_r11 and in stack frame, + * now phys stack/exception frame pointer + * r12 saved in stack frame, now saved SRR2 + * CR saved in stack frame, CR0.EQ = !SRR3.PR + * LR, DEAR, ESR in stack frame + * r1 saved in stack frame, now virt stack/excframe pointer + * r0, r3-r8 saved in stack frame + */ + +/* + * Exception vectors. + */ +#define START_EXCEPTION(n, label) \ + . = n; \ +label: + +#define EXCEPTION(n, label, hdlr, xfer) \ + START_EXCEPTION(n, label); \ + NORMAL_EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + xfer(n, hdlr) + +#define CRITICAL_EXCEPTION(n, label, hdlr) \ + START_EXCEPTION(n, label); \ + CRITICAL_EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ + NOCOPY, crit_transfer_to_handler, \ + ret_from_crit_exc) + +#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ + li r10,trap; \ + stw r10,_TRAP(r11); \ + lis r10,msr@h; \ + ori r10,r10,msr@l; \ + copyee(r10, r9); \ + bl tfer; \ + .long hdlr; \ + .long ret + +#define COPY_EE(d, s) rlwimi d,s,0,16,16 +#define NOCOPY(d, s) + +#define EXC_XFER_STD(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ + ret_from_except) + +#define EXC_XFER_EE(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_EE_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ + ret_from_except) + + +/* + * 0x0100 - Critical Interrupt Exception + */ + CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) + +/* + * 0x0200 - Machine Check Exception + */ + CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) + +/* + * 0x0300 - Data Storage Exception + * This happens for just a few reasons. U0 set (but we don't do that), + * or zone protection fault (user violation, write to protected page). + * If this is just an update of modified status, we do that quickly + * and exit. Otherwise, we call heavywight functions to do the work. + */ + START_EXCEPTION(0x0300, DataStorage) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 +#ifdef CONFIG_403GCX + stw r12, 0(r0) + stw r9, 4(r0) + mfcr r11 + mfspr r12, SPRN_PID + stw r11, 8(r0) + stw r12, 12(r0) +#else + mtspr SPRN_SPRG4, r12 + mtspr SPRN_SPRG5, r9 + mfcr r11 + mfspr r12, SPRN_PID + mtspr SPRN_SPRG7, r11 + mtspr SPRN_SPRG6, r12 +#endif + + /* First, check if it was a zone fault (which means a user + * tried to access a kernel or read-protected page - always + * a SEGV). All other faults here must be stores, so no + * need to check ESR_DST as well. */ + mfspr r10, SPRN_ESR + andis. r10, r10, ESR_DIZ@h + bne 2f + + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + li r9, 0 + mtspr SPRN_PID, r9 /* TLB will have 0 TID */ + b 4f + + /* Get the PGD for the current thread. + */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) +4: + tophys(r11, r11) + rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ + lwz r11, 0(r11) /* Get L1 entry */ + rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ + lwz r11, 0(r12) /* Get Linux PTE */ + + andi. r9, r11, _PAGE_RW /* Is it writeable? */ + beq 2f /* Bail if not */ + + /* Update 'changed'. + */ + ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE + stw r11, 0(r12) /* Update Linux page table */ + + /* Most of the Linux PTE is ready to load into the TLB LO. + * We set ZSEL, where only the LS-bit determines user access. + * We set execute, because we don't have the granularity to + * properly set this at the page level (Linux problem). + * If shared is set, we cause a zero PID->TID load. + * Many of these bits are software only. Bits we don't set + * here we (properly should) assume have the appropriate value. + */ + li r12, 0x0ce2 + andc r11, r11, r12 /* Make sure 20, 21 are zero */ + + /* find the TLB index that caused the fault. It has to be here. + */ + tlbsx r9, 0, r10 + + tlbwe r11, r9, TLB_DATA /* Load TLB LO */ + + /* Done...restore registers and get out of here. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + PPC405_ERR77_SYNC + rfi /* Should sync shadow TLBs */ + b . /* prevent prefetch past rfi */ + +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b DataAccess + +/* + * 0x0400 - Instruction Storage Exception + * This is caused by a fetch from non-execute or guarded pages. + */ + START_EXCEPTION(0x0400, InstructionAccess) + NORMAL_EXCEPTION_PROLOG + mr r4,r12 /* Pass SRR0 as arg2 */ + li r5,0 /* Pass zero as arg3 */ + EXC_XFER_EE_LITE(0x400, handle_page_fault) + +/* 0x0500 - External Interrupt Exception */ + EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) + +/* 0x0600 - Alignment Exception */ + START_EXCEPTION(0x0600, Alignment) + NORMAL_EXCEPTION_PROLOG + mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ + stw r4,_DEAR(r11) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE(0x600, alignment_exception) + +/* 0x0700 - Program Exception */ + START_EXCEPTION(0x0700, ProgramCheck) + NORMAL_EXCEPTION_PROLOG + mfspr r4,SPRN_ESR /* Grab the ESR and save it */ + stw r4,_ESR(r11) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_STD(0x700, program_check_exception) + + EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) + +/* 0x0C00 - System Call Exception */ + START_EXCEPTION(0x0C00, SystemCall) + NORMAL_EXCEPTION_PROLOG + EXC_XFER_EE_LITE(0xc00, DoSyscall) + + EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) + +/* 0x1000 - Programmable Interval Timer (PIT) Exception */ + START_EXCEPTION(0x1000, Decrementer) + NORMAL_EXCEPTION_PROLOG + lis r0,TSR_PIS@h + mtspr SPRN_TSR,r0 /* Clear the PIT exception */ + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_LITE(0x1000, timer_interrupt) + +#if 0 +/* NOTE: + * FIT and WDT handlers are not implemented yet. + */ + +/* 0x1010 - Fixed Interval Timer (FIT) Exception +*/ + STND_EXCEPTION(0x1010, FITException, unknown_exception) + +/* 0x1020 - Watchdog Timer (WDT) Exception +*/ +#ifdef CONFIG_BOOKE_WDT + CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException) +#else + CRITICAL_EXCEPTION(0x1020, WDTException, unknown_exception) +#endif +#endif + +/* 0x1100 - Data TLB Miss Exception + * As the name implies, translation is not in the MMU, so search the + * page tables and fix it. The only purpose of this function is to + * load TLB entries from the page table if they exist. + */ + START_EXCEPTION(0x1100, DTLBMiss) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 +#ifdef CONFIG_403GCX + stw r12, 0(r0) + stw r9, 4(r0) + mfcr r11 + mfspr r12, SPRN_PID + stw r11, 8(r0) + stw r12, 12(r0) +#else + mtspr SPRN_SPRG4, r12 + mtspr SPRN_SPRG5, r9 + mfcr r11 + mfspr r12, SPRN_PID + mtspr SPRN_SPRG7, r11 + mtspr SPRN_SPRG6, r12 +#endif + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + li r9, 0 + mtspr SPRN_PID, r9 /* TLB will have 0 TID */ + b 4f + + /* Get the PGD for the current thread. + */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) +4: + tophys(r11, r11) + rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ + lwz r12, 0(r11) /* Get L1 entry */ + andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ + lwz r11, 0(r12) /* Get Linux PTE */ + andi. r9, r11, _PAGE_PRESENT + beq 5f + + ori r11, r11, _PAGE_ACCESSED + stw r11, 0(r12) + + /* Create TLB tag. This is the faulting address plus a static + * set of bits. These are size, valid, E, U0. + */ + li r12, 0x00c0 + rlwimi r10, r12, 0, 20, 31 + + b finish_tlb_load + +2: /* Check for possible large-page pmd entry */ + rlwinm. r9, r12, 2, 22, 24 + beq 5f + + /* Create TLB tag. This is the faulting address, plus a static + * set of bits (valid, E, U0) plus the size from the PMD. + */ + ori r9, r9, 0x40 + rlwimi r10, r9, 0, 20, 31 + mr r11, r12 + + b finish_tlb_load + +5: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b DataAccess + +/* 0x1200 - Instruction TLB Miss Exception + * Nearly the same as above, except we get our information from different + * registers and bailout to a different point. + */ + START_EXCEPTION(0x1200, ITLBMiss) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 +#ifdef CONFIG_403GCX + stw r12, 0(r0) + stw r9, 4(r0) + mfcr r11 + mfspr r12, SPRN_PID + stw r11, 8(r0) + stw r12, 12(r0) +#else + mtspr SPRN_SPRG4, r12 + mtspr SPRN_SPRG5, r9 + mfcr r11 + mfspr r12, SPRN_PID + mtspr SPRN_SPRG7, r11 + mtspr SPRN_SPRG6, r12 +#endif + mfspr r10, SPRN_SRR0 /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + li r9, 0 + mtspr SPRN_PID, r9 /* TLB will have 0 TID */ + b 4f + + /* Get the PGD for the current thread. + */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) +4: + tophys(r11, r11) + rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ + lwz r12, 0(r11) /* Get L1 entry */ + andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ + lwz r11, 0(r12) /* Get Linux PTE */ + andi. r9, r11, _PAGE_PRESENT + beq 5f + + ori r11, r11, _PAGE_ACCESSED + stw r11, 0(r12) + + /* Create TLB tag. This is the faulting address plus a static + * set of bits. These are size, valid, E, U0. + */ + li r12, 0x00c0 + rlwimi r10, r12, 0, 20, 31 + + b finish_tlb_load + +2: /* Check for possible large-page pmd entry */ + rlwinm. r9, r12, 2, 22, 24 + beq 5f + + /* Create TLB tag. This is the faulting address, plus a static + * set of bits (valid, E, U0) plus the size from the PMD. + */ + ori r9, r9, 0x40 + rlwimi r10, r9, 0, 20, 31 + mr r11, r12 + + b finish_tlb_load + +5: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b InstructionAccess + + EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) +#ifdef CONFIG_IBM405_ERR51 + /* 405GP errata 51 */ + START_EXCEPTION(0x1700, Trap_17) + b DTLBMiss +#else + EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) +#endif + EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE) + +/* Check for a single step debug exception while in an exception + * handler before state has been saved. This is to catch the case + * where an instruction that we are trying to single step causes + * an exception (eg ITLB/DTLB miss) and thus the first instruction of + * the exception handler generates a single step debug exception. + * + * If we get a debug trap on the first instruction of an exception handler, + * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is + * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). + * The exception handler was handling a non-critical interrupt, so it will + * save (and later restore) the MSR via SPRN_SRR1, which will still have + * the MSR_DE bit set. + */ + /* 0x2000 - Debug Exception */ + START_EXCEPTION(0x2000, DebugTrap) + CRITICAL_EXCEPTION_PROLOG + + /* + * If this is a single step or branch-taken exception in an + * exception entry sequence, it was probably meant to apply to + * the code where the exception occurred (since exception entry + * doesn't turn off DE automatically). We simulate the effect + * of turning off DE on entry to an exception handler by turning + * off DE in the SRR3 value and clearing the debug status. + */ + mfspr r10,SPRN_DBSR /* check single-step/branch taken */ + andis. r10,r10,DBSR_IC@h + beq+ 2f + + andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ + beq 1f /* branch and fix it up */ + + mfspr r10,SPRN_SRR2 /* Faulting instruction address */ + cmplwi r10,0x2100 + bgt+ 2f /* address above exception vectors */ + + /* here it looks like we got an inappropriate debug exception. */ +1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ + lis r10,DBSR_IC@h /* clear the IC event */ + mtspr SPRN_DBSR,r10 + /* restore state and get out */ + lwz r10,_CCR(r11) + lwz r0,GPR0(r11) + lwz r1,GPR1(r11) + mtcrf 0x80,r10 + mtspr SPRN_SRR2,r12 + mtspr SPRN_SRR3,r9 + lwz r9,GPR9(r11) + lwz r12,GPR12(r11) + lwz r10,crit_r10@l(0) + lwz r11,crit_r11@l(0) + PPC405_ERR77_SYNC + rfci + b . + + /* continue normal handling for a critical exception... */ +2: mfspr r4,SPRN_DBSR + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(DebugException, 0x2002, \ + (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ + NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) + +/* + * The other Data TLB exceptions bail out to this point + * if they can't resolve the lightweight TLB fault. + */ +DataAccess: + NORMAL_EXCEPTION_PROLOG + mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ + stw r5,_ESR(r11) + mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ + EXC_XFER_EE_LITE(0x300, handle_page_fault) + +/* Other PowerPC processors, namely those derived from the 6xx-series + * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. + * However, for the 4xx-series processors these are neither defined nor + * reserved. + */ + + /* Damn, I came up one instruction too many to fit into the + * exception space :-). Both the instruction and data TLB + * miss get to this point to load the TLB. + * r10 - TLB_TAG value + * r11 - Linux PTE + * r12, r9 - avilable to use + * PID - loaded with proper value when we get here + * Upon exit, we reload everything and RFI. + * Actually, it will fit now, but oh well.....a common place + * to load the TLB. + */ +tlb_4xx_index: + .long 0 +finish_tlb_load: + /* load the next available TLB index. + */ + lwz r9, tlb_4xx_index@l(0) + addi r9, r9, 1 + andi. r9, r9, (PPC40X_TLB_SIZE-1) + stw r9, tlb_4xx_index@l(0) + +6: + /* + * Clear out the software-only bits in the PTE to generate the + * TLB_DATA value. These are the bottom 2 bits of the RPM, the + * top 3 bits of the zone field, and M. + */ + li r12, 0x0ce2 + andc r11, r11, r12 + + tlbwe r11, r9, TLB_DATA /* Load TLB LO */ + tlbwe r10, r9, TLB_TAG /* Load TLB HI */ + + /* Done...restore registers and get out of here. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + PPC405_ERR77_SYNC + rfi /* Should sync shadow TLBs */ + b . /* prevent prefetch past rfi */ + +/* extern void giveup_fpu(struct task_struct *prev) + * + * The PowerPC 4xx family of processors do not have an FPU, so this just + * returns. + */ +_ENTRY(giveup_fpu) + blr + +/* This is where the main kernel code starts. + */ +start_here: + + /* ptr to current */ + lis r2,init_task@h + ori r2,r2,init_task@l + + /* ptr to phys current thread */ + tophys(r4,r2) + addi r4,r4,THREAD /* init task's THREAD */ + mtspr SPRN_SPRG3,r4 + + /* stack */ + lis r1,init_thread_union@ha + addi r1,r1,init_thread_union@l + li r0,0 + stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) + + bl early_init /* We have to do this with MMU on */ + +/* + * Decide what sort of machine this is and initialize the MMU. + */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + bl machine_init + bl MMU_init + +/* Go back to running unmapped so we can load up new values + * and change to using our exception vectors. + * On the 4xx, all we have to do is invalidate the TLB to clear + * the old 16M byte TLB mappings. + */ + lis r4,2f@h + ori r4,r4,2f@l + tophys(r4,r4) + lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h + ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + rfi + b . /* prevent prefetch past rfi */ + +/* Load up the kernel context */ +2: + sync /* Flush to memory before changing TLB */ + tlbia + isync /* Flush shadow TLBs */ + + /* set up the PTE pointers for the Abatron bdiGDB. + */ + lis r6, swapper_pg_dir@h + ori r6, r6, swapper_pg_dir@l + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + stw r5, 0xf0(r0) /* Must match your Abatron config file */ + tophys(r5,r5) + stw r6, 0(r5) + +/* Now turn on the MMU for real! */ + lis r4,MSR_KERNEL@h + ori r4,r4,MSR_KERNEL@l + lis r3,start_kernel@h + ori r3,r3,start_kernel@l + mtspr SPRN_SRR0,r3 + mtspr SPRN_SRR1,r4 + rfi /* enable MMU and jump to start_kernel */ + b . /* prevent prefetch past rfi */ + +/* Set up the initial MMU state so we can do the first level of + * kernel initialization. This maps the first 16 MBytes of memory 1:1 + * virtual to physical and more importantly sets the cache mode. + */ +initial_mmu: + tlbia /* Invalidate all TLB entries */ + isync + + /* We should still be executing code at physical address 0x0000xxxx + * at this point. However, start_here is at virtual address + * 0xC000xxxx. So, set up a TLB mapping to cover this once + * translation is enabled. + */ + + lis r3,KERNELBASE@h /* Load the kernel virtual address */ + ori r3,r3,KERNELBASE@l + tophys(r4,r3) /* Load the kernel physical address */ + + iccci r0,r3 /* Invalidate the i-cache before use */ + + /* Load the kernel PID. + */ + li r0,0 + mtspr SPRN_PID,r0 + sync + + /* Configure and load two entries into TLB slots 62 and 63. + * In case we are pinning TLBs, these are reserved in by the + * other TLB functions. If not reserving, then it doesn't + * matter where they are loaded. + */ + clrrwi r4,r4,10 /* Mask off the real page number */ + ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ + + clrrwi r3,r3,10 /* Mask off the effective page number */ + ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) + + li r0,63 /* TLB slot 63 */ + + tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ + tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE) + + /* Load a TLB entry for the UART, so that ppc4xx_progress() can use + * the UARTs nice and early. We use a 4k real==virtual mapping. */ + + lis r3,SERIAL_DEBUG_IO_BASE@h + ori r3,r3,SERIAL_DEBUG_IO_BASE@l + mr r4,r3 + clrrwi r4,r4,12 + ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G) + + clrrwi r3,r3,12 + ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) + + li r0,0 /* TLB slot 0 */ + tlbwe r4,r0,TLB_DATA + tlbwe r3,r0,TLB_TAG +#endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */ + + isync + + /* Establish the exception vector base + */ + lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ + tophys(r0,r4) /* Use the physical address */ + mtspr SPRN_EVPR,r0 + + blr + +_GLOBAL(abort) + mfspr r13,SPRN_DBCR0 + oris r13,r13,DBCR0_RST_SYSTEM@h + mtspr SPRN_DBCR0,r13 + +_GLOBAL(set_context) + +#ifdef CONFIG_BDI_SWITCH + /* Context switch the PTE pointer for the Abatron BDI2000. + * The PGDIR is the second parameter. + */ + lis r5, KERNELBASE@h + lwz r5, 0xf0(r5) + stw r4, 0x4(r5) +#endif + sync + mtspr SPRN_PID,r3 + isync /* Need an isync to flush shadow */ + /* TLBs after changing PID */ + blr + +/* We put a few things here that have to be page-aligned. This stuff + * goes at the beginning of the data segment, which is page-aligned. + */ + .data + .align 12 + .globl sdata +sdata: + .globl empty_zero_page +empty_zero_page: + .space 4096 + .globl swapper_pg_dir +swapper_pg_dir: + .space 4096 + + +/* Stack for handling critical exceptions from kernel mode */ + .section .bss + .align 12 +exception_stack_bottom: + .space 4096 +critical_stack_top: + .globl exception_stack_top +exception_stack_top: + +/* Room for two PTE pointers, usually the kernel and current user pointers + * to their respective root page table. + */ +abatron_pteptrs: + .space 8 diff -puN arch/powerpc/kernel/head_44x.S~git-powerpc arch/powerpc/kernel/head_44x.S --- a/arch/powerpc/kernel/head_44x.S~git-powerpc +++ a/arch/powerpc/kernel/head_44x.S @@ -50,9 +50,9 @@ * r7 - End of kernel command line string * */ - .text -_GLOBAL(_stext) -_GLOBAL(_start) + .section .text.head, "ax" +_ENTRY(_stext); +_ENTRY(_start); /* * Reserve a word at a fixed location to store the address * of abatron_pteptrs @@ -217,7 +217,7 @@ skpinv: addi r4,r4,1 /* Increment */ lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ mtspr SPRN_IVPR,r4 -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */ mfspr r2,SPRN_CCR0 lis r3,0xffef @@ -744,14 +744,6 @@ exception_stack_bottom: exception_stack_top: /* - * This space gets a copy of optional info passed to us by the bootstrap - * which is used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - -/* * Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table. */ diff -puN arch/powerpc/kernel/head_4xx.S~git-powerpc /dev/null --- a/arch/powerpc/kernel/head_4xx.S +++ /dev/null @@ -1,1021 +0,0 @@ -/* - * Copyright (c) 1995-1996 Gary Thomas - * Initial PowerPC version. - * Copyright (c) 1996 Cort Dougan - * Rewritten for PReP - * Copyright (c) 1996 Paul Mackerras - * Low-level exception handers, MMU support, and rewrite. - * Copyright (c) 1997 Dan Malek - * PowerPC 8xx modifications. - * Copyright (c) 1998-1999 TiVo, Inc. - * PowerPC 403GCX modifications. - * Copyright (c) 1999 Grant Erickson - * PowerPC 403GCX/405GP modifications. - * Copyright 2000 MontaVista Software Inc. - * PPC405 modifications - * PowerPC 403GCX/405GP modifications. - * Author: MontaVista Software, Inc. - * frank_rowand@mvista.com or source@mvista.com - * debbie_chu@mvista.com - * - * - * Module name: head_4xx.S - * - * Description: - * Kernel execution entry point code. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* As with the other PowerPC ports, it is expected that when code - * execution begins here, the following registers contain valid, yet - * optional, information: - * - * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) - * r4 - Starting address of the init RAM disk - * r5 - Ending address of the init RAM disk - * r6 - Start of kernel command line string (e.g. "mem=96m") - * r7 - End of kernel command line string - * - * This is all going to change RSN when we add bi_recs....... -- Dan - */ - .text -_GLOBAL(_stext) -_GLOBAL(_start) - - /* Save parameters we are passed. - */ - mr r31,r3 - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - - /* We have to turn on the MMU right away so we get cache modes - * set correctly. - */ - bl initial_mmu - -/* We now have the lower 16 Meg mapped into TLB entries, and the caches - * ready to work. - */ -turn_on_mmu: - lis r0,MSR_KERNEL@h - ori r0,r0,MSR_KERNEL@l - mtspr SPRN_SRR1,r0 - lis r0,start_here@h - ori r0,r0,start_here@l - mtspr SPRN_SRR0,r0 - SYNC - rfi /* enables MMU */ - b . /* prevent prefetch past rfi */ - -/* - * This area is used for temporarily saving registers during the - * critical exception prolog. - */ - . = 0xc0 -crit_save: -_GLOBAL(crit_r10) - .space 4 -_GLOBAL(crit_r11) - .space 4 - -/* - * Exception vector entry code. This code runs with address translation - * turned off (i.e. using physical addresses). We assume SPRG3 has the - * physical address of the current task thread_struct. - * Note that we have to have decremented r1 before we write to any fields - * of the exception frame, since a critical interrupt could occur at any - * time, and it will write to the area immediately below the current r1. - */ -#define NORMAL_EXCEPTION_PROLOG \ - mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ - mtspr SPRN_SPRG1,r11; \ - mtspr SPRN_SPRG2,r1; \ - mfcr r10; /* save CR in r10 for now */\ - mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ - andi. r11,r11,MSR_PR; \ - beq 1f; \ - mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ - lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ - addi r1,r1,THREAD_SIZE; \ -1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ - tophys(r11,r1); \ - stw r10,_CCR(r11); /* save various registers */\ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mfspr r10,SPRN_SPRG0; \ - stw r10,GPR10(r11); \ - mfspr r12,SPRN_SPRG1; \ - stw r12,GPR11(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r10,SPRN_SPRG2; \ - mfspr r12,SPRN_SRR0; \ - stw r10,GPR1(r11); \ - mfspr r9,SPRN_SRR1; \ - stw r10,0(r11); \ - rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - -/* - * Exception prolog for critical exceptions. This is a little different - * from the normal exception prolog above since a critical exception - * can potentially occur at any point during normal exception processing. - * Thus we cannot use the same SPRG registers as the normal prolog above. - * Instead we use a couple of words of memory at low physical addresses. - * This is OK since we don't support SMP on these processors. - */ -#define CRITICAL_EXCEPTION_PROLOG \ - stw r10,crit_r10@l(0); /* save two registers to work with */\ - stw r11,crit_r11@l(0); \ - mfcr r10; /* save CR in r10 for now */\ - mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ - andi. r11,r11,MSR_PR; \ - lis r11,critical_stack_top@h; \ - ori r11,r11,critical_stack_top@l; \ - beq 1f; \ - /* COMING FROM USER MODE */ \ - mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ - lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ - addi r11,r11,THREAD_SIZE; \ -1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ - tophys(r11,r11); \ - stw r10,_CCR(r11); /* save various registers */\ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ - stw r12,_DEAR(r11); /* since they may have had stuff */\ - mfspr r9,SPRN_ESR; /* in them at the point where the */\ - stw r9,_ESR(r11); /* exception was taken */\ - mfspr r12,SPRN_SRR2; \ - stw r1,GPR1(r11); \ - mfspr r9,SPRN_SRR3; \ - stw r1,0(r11); \ - tovirt(r1,r11); \ - rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - - /* - * State at this point: - * r9 saved in stack frame, now saved SRR3 & ~MSR_WE - * r10 saved in crit_r10 and in stack frame, trashed - * r11 saved in crit_r11 and in stack frame, - * now phys stack/exception frame pointer - * r12 saved in stack frame, now saved SRR2 - * CR saved in stack frame, CR0.EQ = !SRR3.PR - * LR, DEAR, ESR in stack frame - * r1 saved in stack frame, now virt stack/excframe pointer - * r0, r3-r8 saved in stack frame - */ - -/* - * Exception vectors. - */ -#define START_EXCEPTION(n, label) \ - . = n; \ -label: - -#define EXCEPTION(n, label, hdlr, xfer) \ - START_EXCEPTION(n, label); \ - NORMAL_EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - xfer(n, hdlr) - -#define CRITICAL_EXCEPTION(n, label, hdlr) \ - START_EXCEPTION(n, label); \ - CRITICAL_EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ - NOCOPY, crit_transfer_to_handler, \ - ret_from_crit_exc) - -#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ - li r10,trap; \ - stw r10,_TRAP(r11); \ - lis r10,msr@h; \ - ori r10,r10,msr@l; \ - copyee(r10, r9); \ - bl tfer; \ - .long hdlr; \ - .long ret - -#define COPY_EE(d, s) rlwimi d,s,0,16,16 -#define NOCOPY(d, s) - -#define EXC_XFER_STD(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ - ret_from_except) - -#define EXC_XFER_EE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_EE_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ - ret_from_except) - - -/* - * 0x0100 - Critical Interrupt Exception - */ - CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) - -/* - * 0x0200 - Machine Check Exception - */ - CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) - -/* - * 0x0300 - Data Storage Exception - * This happens for just a few reasons. U0 set (but we don't do that), - * or zone protection fault (user violation, write to protected page). - * If this is just an update of modified status, we do that quickly - * and exit. Otherwise, we call heavywight functions to do the work. - */ - START_EXCEPTION(0x0300, DataStorage) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 -#ifdef CONFIG_403GCX - stw r12, 0(r0) - stw r9, 4(r0) - mfcr r11 - mfspr r12, SPRN_PID - stw r11, 8(r0) - stw r12, 12(r0) -#else - mtspr SPRN_SPRG4, r12 - mtspr SPRN_SPRG5, r9 - mfcr r11 - mfspr r12, SPRN_PID - mtspr SPRN_SPRG7, r11 - mtspr SPRN_SPRG6, r12 -#endif - - /* First, check if it was a zone fault (which means a user - * tried to access a kernel or read-protected page - always - * a SEGV). All other faults here must be stores, so no - * need to check ESR_DST as well. */ - mfspr r10, SPRN_ESR - andis. r10, r10, ESR_DIZ@h - bne 2f - - mfspr r10, SPRN_DEAR /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - li r9, 0 - mtspr SPRN_PID, r9 /* TLB will have 0 TID */ - b 4f - - /* Get the PGD for the current thread. - */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) -4: - tophys(r11, r11) - rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ - lwz r11, 0(r11) /* Get L1 entry */ - rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ - lwz r11, 0(r12) /* Get Linux PTE */ - - andi. r9, r11, _PAGE_RW /* Is it writeable? */ - beq 2f /* Bail if not */ - - /* Update 'changed'. - */ - ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE - stw r11, 0(r12) /* Update Linux page table */ - - /* Most of the Linux PTE is ready to load into the TLB LO. - * We set ZSEL, where only the LS-bit determines user access. - * We set execute, because we don't have the granularity to - * properly set this at the page level (Linux problem). - * If shared is set, we cause a zero PID->TID load. - * Many of these bits are software only. Bits we don't set - * here we (properly should) assume have the appropriate value. - */ - li r12, 0x0ce2 - andc r11, r11, r12 /* Make sure 20, 21 are zero */ - - /* find the TLB index that caused the fault. It has to be here. - */ - tlbsx r9, 0, r10 - - tlbwe r11, r9, TLB_DATA /* Load TLB LO */ - - /* Done...restore registers and get out of here. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - PPC405_ERR77_SYNC - rfi /* Should sync shadow TLBs */ - b . /* prevent prefetch past rfi */ - -2: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b DataAccess - -/* - * 0x0400 - Instruction Storage Exception - * This is caused by a fetch from non-execute or guarded pages. - */ - START_EXCEPTION(0x0400, InstructionAccess) - NORMAL_EXCEPTION_PROLOG - mr r4,r12 /* Pass SRR0 as arg2 */ - li r5,0 /* Pass zero as arg3 */ - EXC_XFER_EE_LITE(0x400, handle_page_fault) - -/* 0x0500 - External Interrupt Exception */ - EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) - -/* 0x0600 - Alignment Exception */ - START_EXCEPTION(0x0600, Alignment) - NORMAL_EXCEPTION_PROLOG - mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ - stw r4,_DEAR(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_EE(0x600, alignment_exception) - -/* 0x0700 - Program Exception */ - START_EXCEPTION(0x0700, ProgramCheck) - NORMAL_EXCEPTION_PROLOG - mfspr r4,SPRN_ESR /* Grab the ESR and save it */ - stw r4,_ESR(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_STD(0x700, program_check_exception) - - EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) - -/* 0x0C00 - System Call Exception */ - START_EXCEPTION(0x0C00, SystemCall) - NORMAL_EXCEPTION_PROLOG - EXC_XFER_EE_LITE(0xc00, DoSyscall) - - EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) - -/* 0x1000 - Programmable Interval Timer (PIT) Exception */ - START_EXCEPTION(0x1000, Decrementer) - NORMAL_EXCEPTION_PROLOG - lis r0,TSR_PIS@h - mtspr SPRN_TSR,r0 /* Clear the PIT exception */ - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_LITE(0x1000, timer_interrupt) - -#if 0 -/* NOTE: - * FIT and WDT handlers are not implemented yet. - */ - -/* 0x1010 - Fixed Interval Timer (FIT) Exception -*/ - STND_EXCEPTION(0x1010, FITException, unknown_exception) - -/* 0x1020 - Watchdog Timer (WDT) Exception -*/ -#ifdef CONFIG_BOOKE_WDT - CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException) -#else - CRITICAL_EXCEPTION(0x1020, WDTException, unknown_exception) -#endif -#endif - -/* 0x1100 - Data TLB Miss Exception - * As the name implies, translation is not in the MMU, so search the - * page tables and fix it. The only purpose of this function is to - * load TLB entries from the page table if they exist. - */ - START_EXCEPTION(0x1100, DTLBMiss) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 -#ifdef CONFIG_403GCX - stw r12, 0(r0) - stw r9, 4(r0) - mfcr r11 - mfspr r12, SPRN_PID - stw r11, 8(r0) - stw r12, 12(r0) -#else - mtspr SPRN_SPRG4, r12 - mtspr SPRN_SPRG5, r9 - mfcr r11 - mfspr r12, SPRN_PID - mtspr SPRN_SPRG7, r11 - mtspr SPRN_SPRG6, r12 -#endif - mfspr r10, SPRN_DEAR /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - li r9, 0 - mtspr SPRN_PID, r9 /* TLB will have 0 TID */ - b 4f - - /* Get the PGD for the current thread. - */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) -4: - tophys(r11, r11) - rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ - lwz r12, 0(r11) /* Get L1 entry */ - andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ - lwz r11, 0(r12) /* Get Linux PTE */ - andi. r9, r11, _PAGE_PRESENT - beq 5f - - ori r11, r11, _PAGE_ACCESSED - stw r11, 0(r12) - - /* Create TLB tag. This is the faulting address plus a static - * set of bits. These are size, valid, E, U0. - */ - li r12, 0x00c0 - rlwimi r10, r12, 0, 20, 31 - - b finish_tlb_load - -2: /* Check for possible large-page pmd entry */ - rlwinm. r9, r12, 2, 22, 24 - beq 5f - - /* Create TLB tag. This is the faulting address, plus a static - * set of bits (valid, E, U0) plus the size from the PMD. - */ - ori r9, r9, 0x40 - rlwimi r10, r9, 0, 20, 31 - mr r11, r12 - - b finish_tlb_load - -5: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b DataAccess - -/* 0x1200 - Instruction TLB Miss Exception - * Nearly the same as above, except we get our information from different - * registers and bailout to a different point. - */ - START_EXCEPTION(0x1200, ITLBMiss) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 -#ifdef CONFIG_403GCX - stw r12, 0(r0) - stw r9, 4(r0) - mfcr r11 - mfspr r12, SPRN_PID - stw r11, 8(r0) - stw r12, 12(r0) -#else - mtspr SPRN_SPRG4, r12 - mtspr SPRN_SPRG5, r9 - mfcr r11 - mfspr r12, SPRN_PID - mtspr SPRN_SPRG7, r11 - mtspr SPRN_SPRG6, r12 -#endif - mfspr r10, SPRN_SRR0 /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - li r9, 0 - mtspr SPRN_PID, r9 /* TLB will have 0 TID */ - b 4f - - /* Get the PGD for the current thread. - */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) -4: - tophys(r11, r11) - rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ - lwz r12, 0(r11) /* Get L1 entry */ - andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ - lwz r11, 0(r12) /* Get Linux PTE */ - andi. r9, r11, _PAGE_PRESENT - beq 5f - - ori r11, r11, _PAGE_ACCESSED - stw r11, 0(r12) - - /* Create TLB tag. This is the faulting address plus a static - * set of bits. These are size, valid, E, U0. - */ - li r12, 0x00c0 - rlwimi r10, r12, 0, 20, 31 - - b finish_tlb_load - -2: /* Check for possible large-page pmd entry */ - rlwinm. r9, r12, 2, 22, 24 - beq 5f - - /* Create TLB tag. This is the faulting address, plus a static - * set of bits (valid, E, U0) plus the size from the PMD. - */ - ori r9, r9, 0x40 - rlwimi r10, r9, 0, 20, 31 - mr r11, r12 - - b finish_tlb_load - -5: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b InstructionAccess - - EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) -#ifdef CONFIG_IBM405_ERR51 - /* 405GP errata 51 */ - START_EXCEPTION(0x1700, Trap_17) - b DTLBMiss -#else - EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) -#endif - EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE) - -/* Check for a single step debug exception while in an exception - * handler before state has been saved. This is to catch the case - * where an instruction that we are trying to single step causes - * an exception (eg ITLB/DTLB miss) and thus the first instruction of - * the exception handler generates a single step debug exception. - * - * If we get a debug trap on the first instruction of an exception handler, - * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is - * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). - * The exception handler was handling a non-critical interrupt, so it will - * save (and later restore) the MSR via SPRN_SRR1, which will still have - * the MSR_DE bit set. - */ - /* 0x2000 - Debug Exception */ - START_EXCEPTION(0x2000, DebugTrap) - CRITICAL_EXCEPTION_PROLOG - - /* - * If this is a single step or branch-taken exception in an - * exception entry sequence, it was probably meant to apply to - * the code where the exception occurred (since exception entry - * doesn't turn off DE automatically). We simulate the effect - * of turning off DE on entry to an exception handler by turning - * off DE in the SRR3 value and clearing the debug status. - */ - mfspr r10,SPRN_DBSR /* check single-step/branch taken */ - andis. r10,r10,DBSR_IC@h - beq+ 2f - - andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ - beq 1f /* branch and fix it up */ - - mfspr r10,SPRN_SRR2 /* Faulting instruction address */ - cmplwi r10,0x2100 - bgt+ 2f /* address above exception vectors */ - - /* here it looks like we got an inappropriate debug exception. */ -1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ - lis r10,DBSR_IC@h /* clear the IC event */ - mtspr SPRN_DBSR,r10 - /* restore state and get out */ - lwz r10,_CCR(r11) - lwz r0,GPR0(r11) - lwz r1,GPR1(r11) - mtcrf 0x80,r10 - mtspr SPRN_SRR2,r12 - mtspr SPRN_SRR3,r9 - lwz r9,GPR9(r11) - lwz r12,GPR12(r11) - lwz r10,crit_r10@l(0) - lwz r11,crit_r11@l(0) - PPC405_ERR77_SYNC - rfci - b . - - /* continue normal handling for a critical exception... */ -2: mfspr r4,SPRN_DBSR - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(DebugException, 0x2002, \ - (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ - NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) - -/* - * The other Data TLB exceptions bail out to this point - * if they can't resolve the lightweight TLB fault. - */ -DataAccess: - NORMAL_EXCEPTION_PROLOG - mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ - stw r5,_ESR(r11) - mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ - EXC_XFER_EE_LITE(0x300, handle_page_fault) - -/* Other PowerPC processors, namely those derived from the 6xx-series - * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. - * However, for the 4xx-series processors these are neither defined nor - * reserved. - */ - - /* Damn, I came up one instruction too many to fit into the - * exception space :-). Both the instruction and data TLB - * miss get to this point to load the TLB. - * r10 - TLB_TAG value - * r11 - Linux PTE - * r12, r9 - avilable to use - * PID - loaded with proper value when we get here - * Upon exit, we reload everything and RFI. - * Actually, it will fit now, but oh well.....a common place - * to load the TLB. - */ -tlb_4xx_index: - .long 0 -finish_tlb_load: - /* load the next available TLB index. - */ - lwz r9, tlb_4xx_index@l(0) - addi r9, r9, 1 - andi. r9, r9, (PPC4XX_TLB_SIZE-1) - stw r9, tlb_4xx_index@l(0) - -6: - /* - * Clear out the software-only bits in the PTE to generate the - * TLB_DATA value. These are the bottom 2 bits of the RPM, the - * top 3 bits of the zone field, and M. - */ - li r12, 0x0ce2 - andc r11, r11, r12 - - tlbwe r11, r9, TLB_DATA /* Load TLB LO */ - tlbwe r10, r9, TLB_TAG /* Load TLB HI */ - - /* Done...restore registers and get out of here. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - PPC405_ERR77_SYNC - rfi /* Should sync shadow TLBs */ - b . /* prevent prefetch past rfi */ - -/* extern void giveup_fpu(struct task_struct *prev) - * - * The PowerPC 4xx family of processors do not have an FPU, so this just - * returns. - */ -_GLOBAL(giveup_fpu) - blr - -/* This is where the main kernel code starts. - */ -start_here: - - /* ptr to current */ - lis r2,init_task@h - ori r2,r2,init_task@l - - /* ptr to phys current thread */ - tophys(r4,r2) - addi r4,r4,THREAD /* init task's THREAD */ - mtspr SPRN_SPRG3,r4 - - /* stack */ - lis r1,init_thread_union@ha - addi r1,r1,init_thread_union@l - li r0,0 - stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) - - bl early_init /* We have to do this with MMU on */ - -/* - * Decide what sort of machine this is and initialize the MMU. - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl machine_init - bl MMU_init - -/* Go back to running unmapped so we can load up new values - * and change to using our exception vectors. - * On the 4xx, all we have to do is invalidate the TLB to clear - * the old 16M byte TLB mappings. - */ - lis r4,2f@h - ori r4,r4,2f@l - tophys(r4,r4) - lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h - ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r3 - rfi - b . /* prevent prefetch past rfi */ - -/* Load up the kernel context */ -2: - sync /* Flush to memory before changing TLB */ - tlbia - isync /* Flush shadow TLBs */ - - /* set up the PTE pointers for the Abatron bdiGDB. - */ - lis r6, swapper_pg_dir@h - ori r6, r6, swapper_pg_dir@l - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r5, 0xf0(r0) /* Must match your Abatron config file */ - tophys(r5,r5) - stw r6, 0(r5) - -/* Now turn on the MMU for real! */ - lis r4,MSR_KERNEL@h - ori r4,r4,MSR_KERNEL@l - lis r3,start_kernel@h - ori r3,r3,start_kernel@l - mtspr SPRN_SRR0,r3 - mtspr SPRN_SRR1,r4 - rfi /* enable MMU and jump to start_kernel */ - b . /* prevent prefetch past rfi */ - -/* Set up the initial MMU state so we can do the first level of - * kernel initialization. This maps the first 16 MBytes of memory 1:1 - * virtual to physical and more importantly sets the cache mode. - */ -initial_mmu: - tlbia /* Invalidate all TLB entries */ - isync - - /* We should still be executing code at physical address 0x0000xxxx - * at this point. However, start_here is at virtual address - * 0xC000xxxx. So, set up a TLB mapping to cover this once - * translation is enabled. - */ - - lis r3,KERNELBASE@h /* Load the kernel virtual address */ - ori r3,r3,KERNELBASE@l - tophys(r4,r3) /* Load the kernel physical address */ - - iccci r0,r3 /* Invalidate the i-cache before use */ - - /* Load the kernel PID. - */ - li r0,0 - mtspr SPRN_PID,r0 - sync - - /* Configure and load two entries into TLB slots 62 and 63. - * In case we are pinning TLBs, these are reserved in by the - * other TLB functions. If not reserving, then it doesn't - * matter where they are loaded. - */ - clrrwi r4,r4,10 /* Mask off the real page number */ - ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ - - clrrwi r3,r3,10 /* Mask off the effective page number */ - ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) - - li r0,63 /* TLB slot 63 */ - - tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ - tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE) - - /* Load a TLB entry for the UART, so that ppc4xx_progress() can use - * the UARTs nice and early. We use a 4k real==virtual mapping. */ - - lis r3,SERIAL_DEBUG_IO_BASE@h - ori r3,r3,SERIAL_DEBUG_IO_BASE@l - mr r4,r3 - clrrwi r4,r4,12 - ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G) - - clrrwi r3,r3,12 - ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) - - li r0,0 /* TLB slot 0 */ - tlbwe r4,r0,TLB_DATA - tlbwe r3,r0,TLB_TAG -#endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */ - - isync - - /* Establish the exception vector base - */ - lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ - tophys(r0,r4) /* Use the physical address */ - mtspr SPRN_EVPR,r0 - - blr - -_GLOBAL(abort) - mfspr r13,SPRN_DBCR0 - oris r13,r13,DBCR0_RST_SYSTEM@h - mtspr SPRN_DBCR0,r13 - -_GLOBAL(set_context) - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is the second parameter. - */ - lis r5, KERNELBASE@h - lwz r5, 0xf0(r5) - stw r4, 0x4(r5) -#endif - sync - mtspr SPRN_PID,r3 - isync /* Need an isync to flush shadow */ - /* TLBs after changing PID */ - blr - -/* We put a few things here that have to be page-aligned. This stuff - * goes at the beginning of the data segment, which is page-aligned. - */ - .data - .align 12 - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 - .globl swapper_pg_dir -swapper_pg_dir: - .space 4096 - - -/* Stack for handling critical exceptions from kernel mode */ - .section .bss - .align 12 -exception_stack_bottom: - .space 4096 -critical_stack_top: - .globl exception_stack_top -exception_stack_top: - -/* This space gets a copy of optional info passed to us by the bootstrap - * which is used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - -/* Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 diff -puN arch/powerpc/kernel/head_64.S~git-powerpc arch/powerpc/kernel/head_64.S --- a/arch/powerpc/kernel/head_64.S~git-powerpc +++ a/arch/powerpc/kernel/head_64.S @@ -34,6 +34,8 @@ #include #include #include +#include +#include #define DO_SOFT_DISABLE @@ -144,344 +146,9 @@ exception_marker: .text /* - * The following macros define the code that appears as - * the prologue to each of the exception handlers. They - * are split into two parts to allow a single kernel binary - * to be used for pSeries and iSeries. - * LOL. One day... - paulus - */ - -/* - * We make as much of the exception code common between native - * exception handlers (including pSeries LPAR) and iSeries LPAR - * implementations as possible. - */ - -/* * This is the start of the interrupt handlers for pSeries * This code runs with relocation off. */ -#define EX_R9 0 -#define EX_R10 8 -#define EX_R11 16 -#define EX_R12 24 -#define EX_R13 32 -#define EX_SRR0 40 -#define EX_DAR 48 -#define EX_DSISR 56 -#define EX_CCR 60 -#define EX_R3 64 -#define EX_LR 72 - -/* - * We're short on space and time in the exception prolog, so we can't - * use the normal SET_REG_IMMEDIATE macro. Normally we just need the - * low halfword of the address, but for Kdump we need the whole low - * word. - */ -#ifdef CONFIG_CRASH_DUMP -#define LOAD_HANDLER(reg, label) \ - oris reg,reg,(label)@h; /* virt addr of handler ... */ \ - ori reg,reg,(label)@l; /* .. and the rest */ -#else -#define LOAD_HANDLER(reg, label) \ - ori reg,reg,(label)@l; /* virt addr of handler ... */ -#endif - -/* - * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. - * The firmware calls the registered system_reset_fwnmi and - * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run - * a 32bit application at the time of the event. - * This firmware bug is present on POWER4 and JS20. - */ -#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ - mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ - std r9,area+EX_R9(r13); /* save r9 - r12 */ \ - std r10,area+EX_R10(r13); \ - std r11,area+EX_R11(r13); \ - std r12,area+EX_R12(r13); \ - mfspr r9,SPRN_SPRG1; \ - std r9,area+EX_R13(r13); \ - mfcr r9; \ - clrrdi r12,r13,32; /* get high part of &label */ \ - mfmsr r10; \ - /* force 64bit mode */ \ - li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ - rldimi r10,r11,61,0; /* insert into top 3 bits */ \ - /* done 64bit mode */ \ - mfspr r11,SPRN_SRR0; /* save SRR0 */ \ - LOAD_HANDLER(r12,label) \ - ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ - mtspr SPRN_SRR0,r12; \ - mfspr r12,SPRN_SRR1; /* and SRR1 */ \ - mtspr SPRN_SRR1,r10; \ - rfid; \ - b . /* prevent speculative execution */ - -#define EXCEPTION_PROLOG_PSERIES(area, label) \ - mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ - std r9,area+EX_R9(r13); /* save r9 - r12 */ \ - std r10,area+EX_R10(r13); \ - std r11,area+EX_R11(r13); \ - std r12,area+EX_R12(r13); \ - mfspr r9,SPRN_SPRG1; \ - std r9,area+EX_R13(r13); \ - mfcr r9; \ - clrrdi r12,r13,32; /* get high part of &label */ \ - mfmsr r10; \ - mfspr r11,SPRN_SRR0; /* save SRR0 */ \ - LOAD_HANDLER(r12,label) \ - ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ - mtspr SPRN_SRR0,r12; \ - mfspr r12,SPRN_SRR1; /* and SRR1 */ \ - mtspr SPRN_SRR1,r10; \ - rfid; \ - b . /* prevent speculative execution */ - -/* - * This is the start of the interrupt handlers for iSeries - * This code runs with relocation on. - */ -#define EXCEPTION_PROLOG_ISERIES_1(area) \ - mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ - std r9,area+EX_R9(r13); /* save r9 - r12 */ \ - std r10,area+EX_R10(r13); \ - std r11,area+EX_R11(r13); \ - std r12,area+EX_R12(r13); \ - mfspr r9,SPRN_SPRG1; \ - std r9,area+EX_R13(r13); \ - mfcr r9 - -#define EXCEPTION_PROLOG_ISERIES_2 \ - mfmsr r10; \ - ld r12,PACALPPACAPTR(r13); \ - ld r11,LPPACASRR0(r12); \ - ld r12,LPPACASRR1(r12); \ - ori r10,r10,MSR_RI; \ - mtmsrd r10,1 - -/* - * The common exception prolog is used for all except a few exceptions - * such as a segment miss on a kernel address. We have to be prepared - * to take another exception from the point where we first touch the - * kernel stack onwards. - * - * On entry r13 points to the paca, r9-r13 are saved in the paca, - * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and - * SRR1, and relocation is on. - */ -#define EXCEPTION_PROLOG_COMMON(n, area) \ - andi. r10,r12,MSR_PR; /* See if coming from user */ \ - mr r10,r1; /* Save r1 */ \ - subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ - beq- 1f; \ - ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ -1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ - bge- cr1,2f; /* abort if it is */ \ - b 3f; \ -2: li r1,(n); /* will be reloaded later */ \ - sth r1,PACA_TRAP_SAVE(r13); \ - b bad_stack; \ -3: std r9,_CCR(r1); /* save CR in stackframe */ \ - std r11,_NIP(r1); /* save SRR0 in stackframe */ \ - std r12,_MSR(r1); /* save SRR1 in stackframe */ \ - std r10,0(r1); /* make stack chain pointer */ \ - std r0,GPR0(r1); /* save r0 in stackframe */ \ - std r10,GPR1(r1); /* save r1 in stackframe */ \ - ACCOUNT_CPU_USER_ENTRY(r9, r10); \ - std r2,GPR2(r1); /* save r2 in stackframe */ \ - SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ - SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ - ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ - ld r10,area+EX_R10(r13); \ - std r9,GPR9(r1); \ - std r10,GPR10(r1); \ - ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ - ld r10,area+EX_R12(r13); \ - ld r11,area+EX_R13(r13); \ - std r9,GPR11(r1); \ - std r10,GPR12(r1); \ - std r11,GPR13(r1); \ - ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ - mflr r9; /* save LR in stackframe */ \ - std r9,_LINK(r1); \ - mfctr r10; /* save CTR in stackframe */ \ - std r10,_CTR(r1); \ - lbz r10,PACASOFTIRQEN(r13); \ - mfspr r11,SPRN_XER; /* save XER in stackframe */ \ - std r10,SOFTE(r1); \ - std r11,_XER(r1); \ - li r9,(n)+1; \ - std r9,_TRAP(r1); /* set trap number */ \ - li r10,0; \ - ld r11,exception_marker@toc(r2); \ - std r10,RESULT(r1); /* clear regs->result */ \ - std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ - -/* - * Exception vectors. - */ -#define STD_EXCEPTION_PSERIES(n, label) \ - . = n; \ - .globl label##_pSeries; \ -label##_pSeries: \ - HMT_MEDIUM; \ - mtspr SPRN_SPRG1,r13; /* save r13 */ \ - EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) - -#define HSTD_EXCEPTION_PSERIES(n, label) \ - . = n; \ - .globl label##_pSeries; \ -label##_pSeries: \ - HMT_MEDIUM; \ - mtspr SPRN_SPRG1,r20; /* save r20 */ \ - mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ - mtspr SPRN_SRR0,r20; \ - mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ - mtspr SPRN_SRR1,r20; \ - mfspr r20,SPRN_SPRG1; /* restore r20 */ \ - mtspr SPRN_SPRG1,r13; /* save r13 */ \ - EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) - - -#define MASKABLE_EXCEPTION_PSERIES(n, label) \ - . = n; \ - .globl label##_pSeries; \ -label##_pSeries: \ - HMT_MEDIUM; \ - mtspr SPRN_SPRG1,r13; /* save r13 */ \ - mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ - std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ - std r10,PACA_EXGEN+EX_R10(r13); \ - lbz r10,PACASOFTIRQEN(r13); \ - mfcr r9; \ - cmpwi r10,0; \ - beq masked_interrupt; \ - mfspr r10,SPRN_SPRG1; \ - std r10,PACA_EXGEN+EX_R13(r13); \ - std r11,PACA_EXGEN+EX_R11(r13); \ - std r12,PACA_EXGEN+EX_R12(r13); \ - clrrdi r12,r13,32; /* get high part of &label */ \ - mfmsr r10; \ - mfspr r11,SPRN_SRR0; /* save SRR0 */ \ - LOAD_HANDLER(r12,label##_common) \ - ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ - mtspr SPRN_SRR0,r12; \ - mfspr r12,SPRN_SRR1; /* and SRR1 */ \ - mtspr SPRN_SRR1,r10; \ - rfid; \ - b . /* prevent speculative execution */ - -#define STD_EXCEPTION_ISERIES(n, label, area) \ - .globl label##_iSeries; \ -label##_iSeries: \ - HMT_MEDIUM; \ - mtspr SPRN_SPRG1,r13; /* save r13 */ \ - EXCEPTION_PROLOG_ISERIES_1(area); \ - EXCEPTION_PROLOG_ISERIES_2; \ - b label##_common - -#define MASKABLE_EXCEPTION_ISERIES(n, label) \ - .globl label##_iSeries; \ -label##_iSeries: \ - HMT_MEDIUM; \ - mtspr SPRN_SPRG1,r13; /* save r13 */ \ - EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ - lbz r10,PACASOFTIRQEN(r13); \ - cmpwi 0,r10,0; \ - beq- label##_iSeries_masked; \ - EXCEPTION_PROLOG_ISERIES_2; \ - b label##_common; \ - -#ifdef CONFIG_PPC_ISERIES -#define DISABLE_INTS \ - li r11,0; \ - stb r11,PACASOFTIRQEN(r13); \ -BEGIN_FW_FTR_SECTION; \ - stb r11,PACAHARDIRQEN(r13); \ -END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ -BEGIN_FW_FTR_SECTION; \ - mfmsr r10; \ - ori r10,r10,MSR_EE; \ - mtmsrd r10,1; \ -END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) - -#else -#define DISABLE_INTS \ - li r11,0; \ - stb r11,PACASOFTIRQEN(r13); \ - stb r11,PACAHARDIRQEN(r13) - -#endif /* CONFIG_PPC_ISERIES */ - -#define ENABLE_INTS \ - ld r12,_MSR(r1); \ - mfmsr r11; \ - rlwimi r11,r12,0,MSR_EE; \ - mtmsrd r11,1 - -#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ - .align 7; \ - .globl label##_common; \ -label##_common: \ - EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ - DISABLE_INTS; \ - bl .save_nvgprs; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - bl hdlr; \ - b .ret_from_except - -/* - * Like STD_EXCEPTION_COMMON, but for exceptions that can occur - * in the idle task and therefore need the special idle handling. - */ -#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ - .align 7; \ - .globl label##_common; \ -label##_common: \ - EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ - FINISH_NAP; \ - DISABLE_INTS; \ - bl .save_nvgprs; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - bl hdlr; \ - b .ret_from_except - -#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ - .align 7; \ - .globl label##_common; \ -label##_common: \ - EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ - FINISH_NAP; \ - DISABLE_INTS; \ - bl .ppc64_runlatch_on; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - bl hdlr; \ - b .ret_from_except_lite - -/* - * When the idle code in power4_idle puts the CPU into NAP mode, - * it has to do so in a loop, and relies on the external interrupt - * and decrementer interrupt entry code to get it out of the loop. - * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags - * to signal that it is in the loop and needs help to get out. - */ -#ifdef CONFIG_PPC_970_NAP -#define FINISH_NAP \ -BEGIN_FTR_SECTION \ - clrrdi r11,r1,THREAD_SHIFT; \ - ld r9,TI_LOCAL_FLAGS(r11); \ - andi. r10,r9,_TLF_NAPPING; \ - bnel power4_fixup_nap; \ -END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) -#else -#define FINISH_NAP -#endif - -/* - * Start of pSeries system interrupt routines - */ . = 0x100 .globl __start_interrupts __start_interrupts: @@ -674,6 +341,7 @@ slb_miss_user_pseries: b . /* prevent spec. execution */ #endif /* __DISABLED__ */ +#ifdef CONFIG_PPC_PSERIES /* * Vectors for the FWNMI option. Share common code. */ @@ -691,191 +359,7 @@ machine_check_fwnmi: mtspr SPRN_SPRG1,r13 /* save r13 */ EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common) -#ifdef CONFIG_PPC_ISERIES -/*** ISeries-LPAR interrupt handlers ***/ - - STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) - - .globl data_access_iSeries -data_access_iSeries: - mtspr SPRN_SPRG1,r13 -BEGIN_FTR_SECTION - mtspr SPRN_SPRG2,r12 - mfspr r13,SPRN_DAR - mfspr r12,SPRN_DSISR - srdi r13,r13,60 - rlwimi r13,r12,16,0x20 - mfcr r12 - cmpwi r13,0x2c - beq .do_stab_bolted_iSeries - mtcrf 0x80,r12 - mfspr r12,SPRN_SPRG2 -END_FTR_SECTION_IFCLR(CPU_FTR_SLB) - EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) - EXCEPTION_PROLOG_ISERIES_2 - b data_access_common - -.do_stab_bolted_iSeries: - mtcrf 0x80,r12 - mfspr r12,SPRN_SPRG2 - EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) - EXCEPTION_PROLOG_ISERIES_2 - b .do_stab_bolted - - .globl data_access_slb_iSeries -data_access_slb_iSeries: - mtspr SPRN_SPRG1,r13 /* save r13 */ - mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ - std r3,PACA_EXSLB+EX_R3(r13) - mfspr r3,SPRN_DAR - std r9,PACA_EXSLB+EX_R9(r13) - mfcr r9 -#ifdef __DISABLED__ - cmpdi r3,0 - bge slb_miss_user_iseries -#endif - std r10,PACA_EXSLB+EX_R10(r13) - std r11,PACA_EXSLB+EX_R11(r13) - std r12,PACA_EXSLB+EX_R12(r13) - mfspr r10,SPRN_SPRG1 - std r10,PACA_EXSLB+EX_R13(r13) - ld r12,PACALPPACAPTR(r13) - ld r12,LPPACASRR1(r12) - b .slb_miss_realmode - - STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) - - .globl instruction_access_slb_iSeries -instruction_access_slb_iSeries: - mtspr SPRN_SPRG1,r13 /* save r13 */ - mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ - std r3,PACA_EXSLB+EX_R3(r13) - ld r3,PACALPPACAPTR(r13) - ld r3,LPPACASRR0(r3) /* get SRR0 value */ - std r9,PACA_EXSLB+EX_R9(r13) - mfcr r9 -#ifdef __DISABLED__ - cmpdi r3,0 - bge .slb_miss_user_iseries -#endif - std r10,PACA_EXSLB+EX_R10(r13) - std r11,PACA_EXSLB+EX_R11(r13) - std r12,PACA_EXSLB+EX_R12(r13) - mfspr r10,SPRN_SPRG1 - std r10,PACA_EXSLB+EX_R13(r13) - ld r12,PACALPPACAPTR(r13) - ld r12,LPPACASRR1(r12) - b .slb_miss_realmode - -#ifdef __DISABLED__ -slb_miss_user_iseries: - std r10,PACA_EXGEN+EX_R10(r13) - std r11,PACA_EXGEN+EX_R11(r13) - std r12,PACA_EXGEN+EX_R12(r13) - mfspr r10,SPRG1 - ld r11,PACA_EXSLB+EX_R9(r13) - ld r12,PACA_EXSLB+EX_R3(r13) - std r10,PACA_EXGEN+EX_R13(r13) - std r11,PACA_EXGEN+EX_R9(r13) - std r12,PACA_EXGEN+EX_R3(r13) - EXCEPTION_PROLOG_ISERIES_2 - b slb_miss_user_common -#endif - - MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) - STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) - STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) - STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) - MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) - STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) - STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) - - .globl system_call_iSeries -system_call_iSeries: - mr r9,r13 - mfspr r13,SPRN_SPRG3 - EXCEPTION_PROLOG_ISERIES_2 - b system_call_common - - STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) - STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) - STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) - - .globl system_reset_iSeries -system_reset_iSeries: - mfspr r13,SPRN_SPRG3 /* Get paca address */ - mfmsr r24 - ori r24,r24,MSR_RI - mtmsrd r24 /* RI on */ - lhz r24,PACAPACAINDEX(r13) /* Get processor # */ - cmpwi 0,r24,0 /* Are we processor 0? */ - bne 1f - b .__start_initialization_iSeries /* Start up the first processor */ -1: mfspr r4,SPRN_CTRLF - li r5,CTRL_RUNLATCH /* Turn off the run light */ - andc r4,r4,r5 - mtspr SPRN_CTRLT,r4 - -1: - HMT_LOW -#ifdef CONFIG_SMP - lbz r23,PACAPROCSTART(r13) /* Test if this processor - * should start */ - sync - LOAD_REG_IMMEDIATE(r3,current_set) - sldi r28,r24,3 /* get current_set[cpu#] */ - ldx r3,r3,r28 - addi r1,r3,THREAD_SIZE - subi r1,r1,STACK_FRAME_OVERHEAD - - cmpwi 0,r23,0 - beq iSeries_secondary_smp_loop /* Loop until told to go */ - bne __secondary_start /* Loop until told to go */ -iSeries_secondary_smp_loop: - /* Let the Hypervisor know we are alive */ - /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ - lis r3,0x8002 - rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ -#else /* CONFIG_SMP */ - /* Yield the processor. This is required for non-SMP kernels - which are running on multi-threaded machines. */ - lis r3,0x8000 - rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ - addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ - li r4,0 /* "yield timed" */ - li r5,-1 /* "yield forever" */ -#endif /* CONFIG_SMP */ - li r0,-1 /* r0=-1 indicates a Hypervisor call */ - sc /* Invoke the hypervisor via a system call */ - mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ - b 1b /* If SMP not configured, secondaries - * loop forever */ - -decrementer_iSeries_masked: - /* We may not have a valid TOC pointer in here. */ - li r11,1 - ld r12,PACALPPACAPTR(r13) - stb r11,LPPACADECRINT(r12) - LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy) - lwz r12,0(r12) - mtspr SPRN_DEC,r12 - /* fall through */ - -hardware_interrupt_iSeries_masked: - mtcrf 0x80,r9 /* Restore regs */ - ld r12,PACALPPACAPTR(r13) - ld r11,LPPACASRR0(r12) - ld r12,LPPACASRR1(r12) - mtspr SPRN_SRR0,r11 - mtspr SPRN_SRR1,r12 - ld r9,PACA_EXGEN+EX_R9(r13) - ld r10,PACA_EXGEN+EX_R10(r13) - ld r11,PACA_EXGEN+EX_R11(r13) - ld r12,PACA_EXGEN+EX_R12(r13) - ld r13,PACA_EXGEN+EX_R13(r13) - rfid - b . /* prevent speculative execution */ -#endif /* CONFIG_PPC_ISERIES */ +#endif /* CONFIG_PPC_PSERIES */ /*** Common interrupt handlers ***/ @@ -1175,7 +659,9 @@ hardware_interrupt_common: FINISH_NAP hardware_interrupt_entry: DISABLE_INTS +BEGIN_FTR_SECTION bl .ppc64_runlatch_on +END_FTR_SECTION_IFSET(CPU_FTR_CTRL) addi r3,r1,STACK_FRAME_OVERHEAD bl .do_IRQ b .ret_from_except_lite @@ -1519,8 +1005,8 @@ _GLOBAL(do_stab_bolted) * Space for CPU0's segment table. * * On iSeries, the hypervisor must fill in at least one entry before - * we get control (with relocate on). The address is give to the hv - * as a page number (see xLparMap in lpardata.c), so this must be at a + * we get control (with relocate on). The address is given to the hv + * as a page number (see xLparMap below), so this must be at a * fixed address (the linker can't compute (u64)&initial_stab >> * PAGE_SHIFT). */ @@ -1529,6 +1015,7 @@ _GLOBAL(do_stab_bolted) initial_stab: .space 4096 +#ifdef CONFIG_PPC_PSERIES /* * Data area reserved for FWNMI option. * This address (0x7000) is fixed by the RPA. @@ -1536,21 +1023,34 @@ initial_stab: .= 0x7000 .globl fwnmi_data_area fwnmi_data_area: +#endif /* CONFIG_PPC_PSERIES */ /* iSeries does not use the FWNMI stuff, so it is safe to put * this here, even if we later allow kernels that will boot on * both pSeries and iSeries */ #ifdef CONFIG_PPC_ISERIES . = LPARMAP_PHYS -#include "lparmap.s" -/* - * This ".text" is here for old compilers that generate a trailing - * .note section when compiling .c files to .s - */ - .text + .globl xLparMap +xLparMap: + .quad HvEsidsToMap /* xNumberEsids */ + .quad HvRangesToMap /* xNumberRanges */ + .quad STAB0_PAGE /* xSegmentTableOffs */ + .zero 40 /* xRsvd */ + /* xEsids (HvEsidsToMap entries of 2 quads) */ + .quad PAGE_OFFSET_ESID /* xKernelEsid */ + .quad PAGE_OFFSET_VSID /* xKernelVsid */ + .quad VMALLOC_START_ESID /* xKernelEsid */ + .quad VMALLOC_START_VSID /* xKernelVsid */ + /* xRanges (HvRangesToMap entries of 3 quads) */ + .quad HvPagesToMap /* xPages */ + .quad 0 /* xOffset */ + .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ + #endif /* CONFIG_PPC_ISERIES */ +#ifdef CONFIG_PPC_PSERIES . = 0x8000 +#endif /* CONFIG_PPC_PSERIES */ /* * On pSeries and most other platforms, secondary processors spin @@ -1611,39 +1111,6 @@ _GLOBAL(generic_secondary_smp_init) b __secondary_start #endif -#ifdef CONFIG_PPC_ISERIES -_INIT_STATIC(__start_initialization_iSeries) - /* Clear out the BSS */ - LOAD_REG_IMMEDIATE(r11,__bss_stop) - LOAD_REG_IMMEDIATE(r8,__bss_start) - sub r11,r11,r8 /* bss size */ - addi r11,r11,7 /* round up to an even double word */ - rldicl. r11,r11,61,3 /* shift right by 3 */ - beq 4f - addi r8,r8,-8 - li r0,0 - mtctr r11 /* zero this many doublewords */ -3: stdu r0,8(r8) - bdnz 3b -4: - LOAD_REG_IMMEDIATE(r1,init_thread_union) - addi r1,r1,THREAD_SIZE - li r0,0 - stdu r0,-STACK_FRAME_OVERHEAD(r1) - - LOAD_REG_IMMEDIATE(r2,__toc_start) - addi r2,r2,0x4000 - addi r2,r2,0x4000 - - bl .iSeries_early_setup - bl .early_setup - - /* relocation is on at this point */ - - b .start_here_common -#endif /* CONFIG_PPC_ISERIES */ - - _STATIC(__mmu_off) mfmsr r3 andi. r0,r3,MSR_IR|MSR_DR @@ -1891,6 +1358,7 @@ _GLOBAL(pmac_secondary_start) * r13 = paca virtual address * SPRG3 = paca virtual address */ + .globl __secondary_start __secondary_start: /* Set thread priority to MEDIUM */ HMT_MEDIUM @@ -2021,7 +1489,7 @@ _INIT_STATIC(start_here_multiplatform) b . /* prevent speculative execution */ /* This is where all platforms converge execution */ -_INIT_STATIC(start_here_common) +_INIT_GLOBAL(start_here_common) /* relocation is on at this point */ /* The following code sets up the SP and TOC now that we are */ @@ -2078,12 +1546,4 @@ empty_zero_page: .globl swapper_pg_dir swapper_pg_dir: - .space PAGE_SIZE - -/* - * This space gets a copy of optional info passed to us by the bootstrap - * Used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space COMMAND_LINE_SIZE + .space PGD_TABLE_SIZE diff -puN arch/powerpc/kernel/head_8xx.S~git-powerpc arch/powerpc/kernel/head_8xx.S --- a/arch/powerpc/kernel/head_8xx.S~git-powerpc +++ a/arch/powerpc/kernel/head_8xx.S @@ -38,12 +38,9 @@ #else #define DO_8xx_CPU6(val, reg) #endif - .text - .globl _stext -_stext: - .text - .globl _start -_start: + .section .text.head, "ax" +_ENTRY(_stext); +_ENTRY(_start); /* MPC8xx * This port was done on an MBX board with an 860. Right now I only @@ -835,14 +832,6 @@ empty_zero_page: swapper_pg_dir: .space 4096 -/* - * This space gets a copy of optional info passed to us by the bootstrap - * Used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - /* Room for two PTE table poiners, usually the kernel and current user * pointer to their respective root page table (pgdir). */ diff -puN arch/powerpc/kernel/head_fsl_booke.S~git-powerpc arch/powerpc/kernel/head_fsl_booke.S --- a/arch/powerpc/kernel/head_fsl_booke.S~git-powerpc +++ a/arch/powerpc/kernel/head_fsl_booke.S @@ -52,9 +52,9 @@ * r7 - End of kernel command line string * */ - .text -_GLOBAL(_stext) -_GLOBAL(_start) + .section .text.head, "ax" +_ENTRY(_stext); +_ENTRY(_start); /* * Reserve a word at a fixed location to store the address * of abatron_pteptrs @@ -1050,14 +1050,6 @@ exception_stack_bottom: exception_stack_top: /* - * This space gets a copy of optional info passed to us by the bootstrap - * which is used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - -/* * Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table. */ diff -puN arch/powerpc/kernel/ibmebus.c~git-powerpc arch/powerpc/kernel/ibmebus.c --- a/arch/powerpc/kernel/ibmebus.c~git-powerpc +++ a/arch/powerpc/kernel/ibmebus.c @@ -371,7 +371,8 @@ static int ibmebus_match_path(struct dev static char *ibmebus_chomp(const char *in, size_t count) { - char *out = (char*)kmalloc(count + 1, GFP_KERNEL); + char *out = kmalloc(count + 1, GFP_KERNEL); + if (!out) return NULL; diff -puN arch/powerpc/kernel/iomap.c~git-powerpc arch/powerpc/kernel/iomap.c --- a/arch/powerpc/kernel/iomap.c~git-powerpc +++ a/arch/powerpc/kernel/iomap.c @@ -119,8 +119,8 @@ EXPORT_SYMBOL(ioport_unmap); void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) { - unsigned long start = pci_resource_start(dev, bar); - unsigned long len = pci_resource_len(dev, bar); + resource_size_t start = pci_resource_start(dev, bar); + resource_size_t len = pci_resource_len(dev, bar); unsigned long flags = pci_resource_flags(dev, bar); if (!len) diff -puN arch/powerpc/kernel/iommu.c~git-powerpc arch/powerpc/kernel/iommu.c --- a/arch/powerpc/kernel/iommu.c~git-powerpc +++ a/arch/powerpc/kernel/iommu.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include diff -puN arch/powerpc/kernel/irq.c~git-powerpc arch/powerpc/kernel/irq.c --- a/arch/powerpc/kernel/irq.c~git-powerpc +++ a/arch/powerpc/kernel/irq.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -272,7 +273,7 @@ void do_IRQ(struct pt_regs *regs) struct thread_info *curtp, *irqtp; #endif - irq_enter(); + irq_enter(); #ifdef CONFIG_DEBUG_STACKOVERFLOW /* Debugging check for stack overflow: is there less than 2KB free? */ @@ -321,7 +322,7 @@ void do_IRQ(struct pt_regs *regs) /* That's not SMP safe ... but who cares ? */ ppc_spurious_interrupts++; - irq_exit(); + irq_exit(); set_irq_regs(old_regs); #ifdef CONFIG_PPC_ISERIES @@ -418,10 +419,16 @@ irq_hw_number_t virq_to_hw(unsigned int } EXPORT_SYMBOL_GPL(virq_to_hw); -__init_refok struct irq_host *irq_alloc_host(unsigned int revmap_type, - unsigned int revmap_arg, - struct irq_host_ops *ops, - irq_hw_number_t inval_irq) +static int default_irq_host_match(struct irq_host *h, struct device_node *np) +{ + return h->of_node != NULL && h->of_node == np; +} + +__init_refok struct irq_host *irq_alloc_host(struct device_node *of_node, + unsigned int revmap_type, + unsigned int revmap_arg, + struct irq_host_ops *ops, + irq_hw_number_t inval_irq) { struct irq_host *host; unsigned int size = sizeof(struct irq_host); @@ -446,6 +453,10 @@ __init_refok struct irq_host *irq_alloc_ host->revmap_type = revmap_type; host->inval_irq = inval_irq; host->ops = ops; + host->of_node = of_node; + + if (host->ops->match == NULL) + host->ops->match = default_irq_host_match; spin_lock_irqsave(&irq_big_lock, flags); @@ -477,7 +488,7 @@ __init_refok struct irq_host *irq_alloc_ host->inval_irq = 0; /* setup us as the host for all legacy interrupts */ for (i = 1; i < NUM_ISA_INTERRUPTS; i++) { - irq_map[i].hwirq = 0; + irq_map[i].hwirq = i; smp_wmb(); irq_map[i].host = host; smp_wmb(); @@ -521,7 +532,7 @@ struct irq_host *irq_find_host(struct de */ spin_lock_irqsave(&irq_big_lock, flags); list_for_each_entry(h, &irq_hosts, link) - if (h->ops->match == NULL || h->ops->match(h, node)) { + if (h->ops->match(h, node)) { found = h; break; } @@ -996,6 +1007,68 @@ static int irq_late_init(void) } arch_initcall(irq_late_init); +#ifdef CONFIG_VIRQ_DEBUG +static int virq_debug_show(struct seq_file *m, void *private) +{ + unsigned long flags; + irq_desc_t *desc; + const char *p; + char none[] = "none"; + int i; + + seq_printf(m, "%-5s %-7s %-15s %s\n", "virq", "hwirq", + "chip name", "host name"); + + for (i = 1; i < NR_IRQS; i++) { + desc = get_irq_desc(i); + spin_lock_irqsave(&desc->lock, flags); + + if (desc->action && desc->action->handler) { + seq_printf(m, "%5d ", i); + seq_printf(m, "0x%05lx ", virq_to_hw(i)); + + if (desc->chip && desc->chip->typename) + p = desc->chip->typename; + else + p = none; + seq_printf(m, "%-15s ", p); + + if (irq_map[i].host && irq_map[i].host->of_node) + p = irq_map[i].host->of_node->full_name; + else + p = none; + seq_printf(m, "%s\n", p); + } + + spin_unlock_irqrestore(&desc->lock, flags); + } + + return 0; +} + +static int virq_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, virq_debug_show, inode->i_private); +} + +static const struct file_operations virq_debug_fops = { + .open = virq_debug_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init irq_debugfs_init(void) +{ + if (debugfs_create_file("virq_mapping", S_IRUGO, powerpc_debugfs_root, + NULL, &virq_debug_fops)) + return -ENOMEM; + + return 0; +} +__initcall(irq_debugfs_init); +#endif /* CONFIG_VIRQ_DEBUG */ + #endif /* CONFIG_PPC_MERGE */ #ifdef CONFIG_PPC64 diff -puN arch/powerpc/kernel/lparmap.c~git-powerpc /dev/null --- a/arch/powerpc/kernel/lparmap.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2005 Stephen Rothwell IBM Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include -#include - -/* The # is to stop gcc trying to make .text nonexecutable */ -const struct LparMap __attribute__((__section__(".text #"))) xLparMap = { - .xNumberEsids = HvEsidsToMap, - .xNumberRanges = HvRangesToMap, - .xSegmentTableOffs = STAB0_PAGE, - - .xEsids = { - { .xKernelEsid = GET_ESID(PAGE_OFFSET), - .xKernelVsid = KERNEL_VSID(PAGE_OFFSET), }, - { .xKernelEsid = GET_ESID(VMALLOC_START), - .xKernelVsid = KERNEL_VSID(VMALLOC_START), }, - }, - - .xRanges = { - { .xPages = HvPagesToMap, - .xOffset = 0, - .xVPN = KERNEL_VSID(PAGE_OFFSET) << (SID_SHIFT - HW_PAGE_SHIFT), - }, - }, -}; diff -puN arch/powerpc/kernel/nvram_64.c~git-powerpc arch/powerpc/kernel/nvram_64.c --- a/arch/powerpc/kernel/nvram_64.c~git-powerpc +++ a/arch/powerpc/kernel/nvram_64.c @@ -34,21 +34,10 @@ #undef DEBUG_NVRAM -static int nvram_scan_partitions(void); -static int nvram_setup_partition(void); -static int nvram_create_os_partition(void); -static int nvram_remove_os_partition(void); - static struct nvram_partition * nvram_part; static long nvram_error_log_index = -1; static long nvram_error_log_size = 0; -int no_logging = 1; /* Until we initialize everything, - * make sure we don't try logging - * anything */ - -extern volatile int error_log_cnt; - struct err_log_info { int error_type; unsigned int seq_num; @@ -636,16 +625,13 @@ void __exit nvram_cleanup(void) * sequence #: The unique sequence # for each event. (until it wraps) * error log: The error log from event_scan */ -int nvram_write_error_log(char * buff, int length, unsigned int err_type) +int nvram_write_error_log(char * buff, int length, + unsigned int err_type, unsigned int error_log_cnt) { int rc; loff_t tmp_index; struct err_log_info info; - if (no_logging) { - return -EPERM; - } - if (nvram_error_log_index == -1) { return -ESPIPE; } @@ -678,7 +664,8 @@ int nvram_write_error_log(char * buff, i * * Reads nvram for error log for at most 'length' */ -int nvram_read_error_log(char * buff, int length, unsigned int * err_type) +int nvram_read_error_log(char * buff, int length, + unsigned int * err_type, unsigned int * error_log_cnt) { int rc; loff_t tmp_index; @@ -704,7 +691,7 @@ int nvram_read_error_log(char * buff, in return rc; } - error_log_cnt = info.seq_num; + *error_log_cnt = info.seq_num; *err_type = info.error_type; return 0; diff -puN arch/powerpc/kernel/pci_32.c~git-powerpc arch/powerpc/kernel/pci_32.c --- a/arch/powerpc/kernel/pci_32.c~git-powerpc +++ a/arch/powerpc/kernel/pci_32.c @@ -1457,8 +1457,8 @@ null_write_config(struct pci_bus *bus, u static struct pci_ops null_pci_ops = { - null_read_config, - null_write_config + .read = null_read_config, + .write = null_write_config, }; /* diff -puN arch/powerpc/kernel/pci_dn.c~git-powerpc arch/powerpc/kernel/pci_dn.c --- a/arch/powerpc/kernel/pci_dn.c~git-powerpc +++ a/arch/powerpc/kernel/pci_dn.c @@ -23,8 +23,6 @@ #include #include #include -#include -#include #include #include @@ -45,10 +43,7 @@ static void * __devinit update_dn_pci_in const u32 *regs; struct pci_dn *pdn; - if (mem_init_done) - pdn = kmalloc(sizeof(*pdn), GFP_KERNEL); - else - pdn = alloc_bootmem(sizeof(*pdn)); + pdn = alloc_maybe_bootmem(sizeof(*pdn), GFP_KERNEL); if (pdn == NULL) return NULL; memset(pdn, 0, sizeof(*pdn)); diff -puN arch/powerpc/kernel/ppc_ksyms.c~git-powerpc arch/powerpc/kernel/ppc_ksyms.c --- a/arch/powerpc/kernel/ppc_ksyms.c~git-powerpc +++ a/arch/powerpc/kernel/ppc_ksyms.c @@ -180,7 +180,7 @@ EXPORT_SYMBOL(cacheable_memcpy); EXPORT_SYMBOL(cpm_install_handler); EXPORT_SYMBOL(cpm_free_handler); #endif /* CONFIG_8xx */ -#if defined(CONFIG_8xx) || defined(CONFIG_40x) +#if defined(CONFIG_8xx) EXPORT_SYMBOL(__res); #endif diff -puN arch/powerpc/kernel/process.c~git-powerpc arch/powerpc/kernel/process.c --- a/arch/powerpc/kernel/process.c~git-powerpc +++ a/arch/powerpc/kernel/process.c @@ -676,9 +676,13 @@ int set_fpexc_mode(struct task_struct *t * mode (asyn, precise, disabled) for 'Classic' FP. */ if (val & PR_FP_EXC_SW_ENABLE) { #ifdef CONFIG_SPE - tsk->thread.fpexc_mode = val & - (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); - return 0; + if (cpu_has_feature(CPU_FTR_SPE)) { + tsk->thread.fpexc_mode = val & + (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); + return 0; + } else { + return -EINVAL; + } #else return -EINVAL; #endif @@ -704,7 +708,10 @@ int get_fpexc_mode(struct task_struct *t if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) #ifdef CONFIG_SPE - val = tsk->thread.fpexc_mode; + if (cpu_has_feature(CPU_FTR_SPE)) + val = tsk->thread.fpexc_mode; + else + return -EINVAL; #else return -EINVAL; #endif diff -puN arch/powerpc/kernel/prom.c~git-powerpc arch/powerpc/kernel/prom.c --- a/arch/powerpc/kernel/prom.c~git-powerpc +++ a/arch/powerpc/kernel/prom.c @@ -52,7 +52,6 @@ #include #include #include -#include #ifdef DEBUG #define DBG(fmt...) printk(KERN_ERR fmt) @@ -431,9 +430,11 @@ static int __init early_parse_mem(char * } early_param("mem", early_parse_mem); -/* - * The device tree may be allocated below our memory limit, or inside the - * crash kernel region for kdump. If so, move it out now. +/** + * move_device_tree - move tree to an unused area, if needed. + * + * The device tree may be allocated beyond our memory limit, or inside the + * crash kernel region for kdump. If so, move it out of the way. */ static void move_device_tree(void) { @@ -780,13 +781,13 @@ static int __init early_init_dt_scan_cho #endif #ifdef CONFIG_KEXEC - lprop = (u64*)of_get_flat_dt_prop(node, "linux,crashkernel-base", NULL); - if (lprop) - crashk_res.start = *lprop; - - lprop = (u64*)of_get_flat_dt_prop(node, "linux,crashkernel-size", NULL); - if (lprop) - crashk_res.end = crashk_res.start + *lprop - 1; + lprop = (u64*)of_get_flat_dt_prop(node, "linux,crashkernel-base", NULL); + if (lprop) + crashk_res.start = *lprop; + + lprop = (u64*)of_get_flat_dt_prop(node, "linux,crashkernel-size", NULL); + if (lprop) + crashk_res.end = crashk_res.start + *lprop - 1; #endif early_init_dt_check_for_initrd(node); diff -puN arch/powerpc/kernel/prom_init.c~git-powerpc arch/powerpc/kernel/prom_init.c --- a/arch/powerpc/kernel/prom_init.c~git-powerpc +++ a/arch/powerpc/kernel/prom_init.c @@ -1199,7 +1199,7 @@ static void __init prom_initialize_tce_t if ((type[0] == 0) || (strstr(type, RELOC("pci")) == NULL)) continue; - /* Keep the old logic in tack to avoid regression. */ + /* Keep the old logic intact to avoid regression. */ if (compatible[0] != 0) { if ((strstr(compatible, RELOC("python")) == NULL) && (strstr(compatible, RELOC("Speedwagon")) == NULL) && @@ -2046,6 +2046,7 @@ static void __init fixup_device_tree_map /* * Pegasos and BriQ lacks the "ranges" property in the isa node * Pegasos needs decimal IRQ 14/15, not hexadecimal + * Pegasos has the IDE configured in legacy mode, but advertised as native */ static void __init fixup_device_tree_chrp(void) { @@ -2083,9 +2084,13 @@ static void __init fixup_device_tree_chr prom_printf("Fixing up IDE interrupt on Pegasos...\n"); prop[0] = 14; prop[1] = 0x0; - prop[2] = 15; - prop[3] = 0x0; - prom_setprop(ph, name, "interrupts", prop, 4*sizeof(u32)); + prom_setprop(ph, name, "interrupts", prop, 2*sizeof(u32)); + prom_printf("Fixing up IDE class-code on Pegasos...\n"); + rc = prom_getprop(ph, "class-code", prop, sizeof(u32)); + if (rc == sizeof(u32)) { + prop[0] &= ~0x5; + prom_setprop(ph, name, "class-code", prop, sizeof(u32)); + } } } #else @@ -2226,7 +2231,7 @@ static void __init fixup_device_tree(voi static void __init prom_find_boot_cpu(void) { - struct prom_t *_prom = &RELOC(prom); + struct prom_t *_prom = &RELOC(prom); u32 getprop_rval; ihandle prom_cpu; phandle cpu_pkg; @@ -2246,7 +2251,7 @@ static void __init prom_find_boot_cpu(vo static void __init prom_check_initrd(unsigned long r3, unsigned long r4) { #ifdef CONFIG_BLK_DEV_INITRD - struct prom_t *_prom = &RELOC(prom); + struct prom_t *_prom = &RELOC(prom); if (r3 && r4 && r4 != 0xdeadbeef) { unsigned long val; @@ -2279,7 +2284,7 @@ unsigned long __init prom_init(unsigned unsigned long pp, unsigned long r6, unsigned long r7) { - struct prom_t *_prom; + struct prom_t *_prom; unsigned long hdr; unsigned long offset = reloc_offset(); @@ -2338,8 +2343,8 @@ unsigned long __init prom_init(unsigned /* * Copy the CPU hold code */ - if (RELOC(of_platform) != PLATFORM_POWERMAC) - copy_and_flush(0, KERNELBASE + offset, 0x100, 0); + if (RELOC(of_platform) != PLATFORM_POWERMAC) + copy_and_flush(0, KERNELBASE + offset, 0x100, 0); /* * Do early parsing of command line diff -puN arch/powerpc/kernel/ptrace.c~git-powerpc arch/powerpc/kernel/ptrace.c --- a/arch/powerpc/kernel/ptrace.c~git-powerpc +++ a/arch/powerpc/kernel/ptrace.c @@ -572,8 +572,7 @@ long arch_ptrace(struct task_struct *chi #ifdef CONFIG_SPE case PTRACE_GETEVRREGS: /* Get the child spe register state. */ - if (child->thread.regs->msr & MSR_SPE) - giveup_spe(child); + flush_spe_to_thread(child); ret = get_evrregs((unsigned long __user *)data, child); break; @@ -581,8 +580,7 @@ long arch_ptrace(struct task_struct *chi /* Set the child spe register state. */ /* this is to clear the MSR_SPE bit to force a reload * of register state from memory */ - if (child->thread.regs->msr & MSR_SPE) - giveup_spe(child); + flush_spe_to_thread(child); ret = set_evrregs(child, (unsigned long __user *)data); break; #endif diff -puN arch/powerpc/kernel/rtas_pci.c~git-powerpc arch/powerpc/kernel/rtas_pci.c --- a/arch/powerpc/kernel/rtas_pci.c~git-powerpc +++ a/arch/powerpc/kernel/rtas_pci.c @@ -171,8 +171,8 @@ static int rtas_pci_write_config(struct } struct pci_ops rtas_pci_ops = { - rtas_pci_read_config, - rtas_pci_write_config + .read = rtas_pci_read_config, + .write = rtas_pci_write_config, }; int is_python(struct device_node *dev) diff -puN arch/powerpc/kernel/setup-common.c~git-powerpc arch/powerpc/kernel/setup-common.c --- a/arch/powerpc/kernel/setup-common.c~git-powerpc +++ a/arch/powerpc/kernel/setup-common.c @@ -76,6 +76,8 @@ EXPORT_SYMBOL(machine_id); unsigned long klimit = (unsigned long) _end; +char cmd_line[COMMAND_LINE_SIZE]; + /* * This still seems to be needed... -- paulus */ diff -puN arch/powerpc/kernel/setup_32.c~git-powerpc arch/powerpc/kernel/setup_32.c --- a/arch/powerpc/kernel/setup_32.c~git-powerpc +++ a/arch/powerpc/kernel/setup_32.c @@ -18,13 +18,11 @@ #include #include -#include #include #include #include #include #include -#include #include #include #include diff -puN arch/powerpc/kernel/setup_64.c~git-powerpc arch/powerpc/kernel/setup_64.c --- a/arch/powerpc/kernel/setup_64.c~git-powerpc +++ a/arch/powerpc/kernel/setup_64.c @@ -181,9 +181,9 @@ void __init early_setup(unsigned long dt DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); /* - * Do early initializations using the flattened device - * tree, like retreiving the physical memory map or - * calculating/retreiving the hash table size + * Do early initialization using the flattened device + * tree, such as retrieving the physical memory map or + * calculating/retrieving the hash table size. */ early_init_devtree(__va(dt_ptr)); diff -puN arch/powerpc/kernel/sysfs.c~git-powerpc arch/powerpc/kernel/sysfs.c --- a/arch/powerpc/kernel/sysfs.c~git-powerpc +++ a/arch/powerpc/kernel/sysfs.c @@ -197,6 +197,36 @@ SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4); SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5); +#ifdef CONFIG_DEBUG_KERNEL +SYSFS_PMCSETUP(hid0, SPRN_HID0); +SYSFS_PMCSETUP(hid1, SPRN_HID1); +SYSFS_PMCSETUP(hid4, SPRN_HID4); +SYSFS_PMCSETUP(hid5, SPRN_HID5); +SYSFS_PMCSETUP(ima0, SPRN_PA6T_IMA0); +SYSFS_PMCSETUP(ima1, SPRN_PA6T_IMA1); +SYSFS_PMCSETUP(ima2, SPRN_PA6T_IMA2); +SYSFS_PMCSETUP(ima3, SPRN_PA6T_IMA3); +SYSFS_PMCSETUP(ima4, SPRN_PA6T_IMA4); +SYSFS_PMCSETUP(ima5, SPRN_PA6T_IMA5); +SYSFS_PMCSETUP(ima6, SPRN_PA6T_IMA6); +SYSFS_PMCSETUP(ima7, SPRN_PA6T_IMA7); +SYSFS_PMCSETUP(ima8, SPRN_PA6T_IMA8); +SYSFS_PMCSETUP(ima9, SPRN_PA6T_IMA9); +SYSFS_PMCSETUP(imaat, SPRN_PA6T_IMAAT); +SYSFS_PMCSETUP(btcr, SPRN_PA6T_BTCR); +SYSFS_PMCSETUP(pccr, SPRN_PA6T_PCCR); +SYSFS_PMCSETUP(rpccr, SPRN_PA6T_RPCCR); +SYSFS_PMCSETUP(der, SPRN_PA6T_DER); +SYSFS_PMCSETUP(mer, SPRN_PA6T_MER); +SYSFS_PMCSETUP(ber, SPRN_PA6T_BER); +SYSFS_PMCSETUP(ier, SPRN_PA6T_IER); +SYSFS_PMCSETUP(sier, SPRN_PA6T_SIER); +SYSFS_PMCSETUP(siar, SPRN_PA6T_SIAR); +SYSFS_PMCSETUP(tsr0, SPRN_PA6T_TSR0); +SYSFS_PMCSETUP(tsr1, SPRN_PA6T_TSR1); +SYSFS_PMCSETUP(tsr2, SPRN_PA6T_TSR2); +SYSFS_PMCSETUP(tsr3, SPRN_PA6T_TSR3); +#endif /* CONFIG_DEBUG_KERNEL */ static SYSDEV_ATTR(mmcra, 0600, show_mmcra, store_mmcra); static SYSDEV_ATTR(spurr, 0600, show_spurr, NULL); @@ -228,6 +258,36 @@ static struct sysdev_attribute pa6t_attr _SYSDEV_ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3), _SYSDEV_ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4), _SYSDEV_ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5), +#ifdef CONFIG_DEBUG_KERNEL + _SYSDEV_ATTR(hid0, 0600, show_hid0, store_hid0), + _SYSDEV_ATTR(hid1, 0600, show_hid1, store_hid1), + _SYSDEV_ATTR(hid4, 0600, show_hid4, store_hid4), + _SYSDEV_ATTR(hid5, 0600, show_hid5, store_hid5), + _SYSDEV_ATTR(ima0, 0600, show_ima0, store_ima0), + _SYSDEV_ATTR(ima1, 0600, show_ima1, store_ima1), + _SYSDEV_ATTR(ima2, 0600, show_ima2, store_ima2), + _SYSDEV_ATTR(ima3, 0600, show_ima3, store_ima3), + _SYSDEV_ATTR(ima4, 0600, show_ima4, store_ima4), + _SYSDEV_ATTR(ima5, 0600, show_ima5, store_ima5), + _SYSDEV_ATTR(ima6, 0600, show_ima6, store_ima6), + _SYSDEV_ATTR(ima7, 0600, show_ima7, store_ima7), + _SYSDEV_ATTR(ima8, 0600, show_ima8, store_ima8), + _SYSDEV_ATTR(ima9, 0600, show_ima9, store_ima9), + _SYSDEV_ATTR(imaat, 0600, show_imaat, store_imaat), + _SYSDEV_ATTR(btcr, 0600, show_btcr, store_btcr), + _SYSDEV_ATTR(pccr, 0600, show_pccr, store_pccr), + _SYSDEV_ATTR(rpccr, 0600, show_rpccr, store_rpccr), + _SYSDEV_ATTR(der, 0600, show_der, store_der), + _SYSDEV_ATTR(mer, 0600, show_mer, store_mer), + _SYSDEV_ATTR(ber, 0600, show_ber, store_ber), + _SYSDEV_ATTR(ier, 0600, show_ier, store_ier), + _SYSDEV_ATTR(sier, 0600, show_sier, store_sier), + _SYSDEV_ATTR(siar, 0600, show_siar, store_siar), + _SYSDEV_ATTR(tsr0, 0600, show_tsr0, store_tsr0), + _SYSDEV_ATTR(tsr1, 0600, show_tsr1, store_tsr1), + _SYSDEV_ATTR(tsr2, 0600, show_tsr2, store_tsr2), + _SYSDEV_ATTR(tsr3, 0600, show_tsr3, store_tsr3), +#endif /* CONFIG_DEBUG_KERNEL */ }; @@ -380,12 +440,14 @@ int cpu_add_sysdev_attr_group(struct att { int cpu; struct sys_device *sysdev; + int ret; mutex_lock(&cpu_mutex); for_each_possible_cpu(cpu) { sysdev = get_cpu_sysdev(cpu); - sysfs_create_group(&sysdev->kobj, attrs); + ret = sysfs_create_group(&sysdev->kobj, attrs); + WARN_ON(ret != 0); } mutex_unlock(&cpu_mutex); diff -puN arch/powerpc/kernel/time.c~git-powerpc arch/powerpc/kernel/time.c --- a/arch/powerpc/kernel/time.c~git-powerpc +++ a/arch/powerpc/kernel/time.c @@ -72,7 +72,6 @@ #include #include #endif -#include /* keep track of when we need to update the rtc */ time_t last_rtc_update; @@ -869,7 +868,7 @@ void __init generic_calibrate_decr(void) "(not found)\n"); } -#ifdef CONFIG_BOOKE +#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) /* Set the time base to zero */ mtspr(SPRN_TBWL, 0); mtspr(SPRN_TBWU, 0); diff -puN arch/powerpc/kernel/traps.c~git-powerpc arch/powerpc/kernel/traps.c --- a/arch/powerpc/kernel/traps.c~git-powerpc +++ a/arch/powerpc/kernel/traps.c @@ -324,15 +324,6 @@ static inline int check_io_access(struct #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) #endif -/* - * This is "fall-back" implementation for configurations - * which don't provide platform-specific machine check info - */ -void __attribute__ ((weak)) -platform_machine_check(struct pt_regs *regs) -{ -} - void machine_check_exception(struct pt_regs *regs) { int recover = 0; @@ -480,12 +471,6 @@ void machine_check_exception(struct pt_r } #endif /* CONFIG_4xx */ - /* - * Optional platform-provided routine to print out - * additional info, e.g. bus error registers. - */ - platform_machine_check(regs); - if (debugger_fault_handler(regs)) return; die("Machine check", regs, SIGBUS); diff -puN arch/powerpc/kernel/udbg_16550.c~git-powerpc arch/powerpc/kernel/udbg_16550.c --- a/arch/powerpc/kernel/udbg_16550.c~git-powerpc +++ a/arch/powerpc/kernel/udbg_16550.c @@ -206,11 +206,22 @@ static void udbg_44x_as1_putc(char c) } } +static int udbg_44x_as1_getc(void) +{ + if (udbg_comport) { + while ((as1_readb(&udbg_comport->lsr) & LSR_DR) == 0) + ; /* wait for char */ + return as1_readb(&udbg_comport->rbr); + } + return -1; +} + void __init udbg_init_44x_as1(void) { udbg_comport = (volatile struct NS16550 __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR; udbg_putc = udbg_44x_as1_putc; + udbg_getc = udbg_44x_as1_getc; } #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ diff -puN arch/powerpc/kernel/vmlinux.lds.S~git-powerpc arch/powerpc/kernel/vmlinux.lds.S --- a/arch/powerpc/kernel/vmlinux.lds.S~git-powerpc +++ a/arch/powerpc/kernel/vmlinux.lds.S @@ -34,6 +34,8 @@ SECTIONS /* Text and gots */ .text : { + ALIGN_FUNCTION(); + *(.text.head) _text = .; TEXT_TEXT SCHED_TEXT diff -puN arch/powerpc/lib/Makefile~git-powerpc arch/powerpc/lib/Makefile --- a/arch/powerpc/lib/Makefile~git-powerpc +++ a/arch/powerpc/lib/Makefile @@ -7,7 +7,7 @@ EXTRA_CFLAGS += -mno-minimal-toc endif ifeq ($(CONFIG_PPC_MERGE),y) -obj-y := string.o +obj-y := string.o alloc.o obj-$(CONFIG_PPC32) += div64.o copy_32.o checksum_32.o endif diff -puN /dev/null arch/powerpc/lib/alloc.c --- /dev/null +++ a/arch/powerpc/lib/alloc.c @@ -0,0 +1,14 @@ +#include +#include +#include +#include + +#include + +void * __init_refok alloc_maybe_bootmem(size_t size, gfp_t mask) +{ + if (mem_init_done) + return kmalloc(size, mask); + else + return alloc_bootmem(size); +} diff -puN /dev/null arch/powerpc/mm/40x_mmu.c --- /dev/null +++ a/arch/powerpc/mm/40x_mmu.c @@ -0,0 +1,135 @@ +/* + * This file contains the routines for initializing the MMU + * on the 4xx series of chips. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mmu_decl.h" + +extern int __map_without_ltlbs; +/* + * MMU_init_hw does the chip-specific initialization of the MMU hardware. + */ +void __init MMU_init_hw(void) +{ + /* + * The Zone Protection Register (ZPR) defines how protection will + * be applied to every page which is a member of a given zone. At + * present, we utilize only two of the 4xx's zones. + * The zone index bits (of ZSEL) in the PTE are used for software + * indicators, except the LSB. For user access, zone 1 is used, + * for kernel access, zone 0 is used. We set all but zone 1 + * to zero, allowing only kernel access as indicated in the PTE. + * For zone 1, we set a 01 binary (a value of 10 will not work) + * to allow user access as indicated in the PTE. This also allows + * kernel access as indicated in the PTE. + */ + + mtspr(SPRN_ZPR, 0x10000000); + + flush_instruction_cache(); + + /* + * Set up the real-mode cache parameters for the exception vector + * handlers (which are run in real-mode). + */ + + mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */ + + /* + * Cache instruction and data space where the exception + * vectors and the kernel live in real-mode. + */ + + mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */ + mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */ +} + +#define LARGE_PAGE_SIZE_16M (1<<24) +#define LARGE_PAGE_SIZE_4M (1<<22) + +unsigned long __init mmu_mapin_ram(void) +{ + unsigned long v, s; + phys_addr_t p; + + v = KERNELBASE; + p = PPC_MEMSTART; + s = 0; + + if (__map_without_ltlbs) { + return s; + } + + while (s <= (total_lowmem - LARGE_PAGE_SIZE_16M)) { + pmd_t *pmdp; + unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE; + + pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v); + pmd_val(*pmdp++) = val; + pmd_val(*pmdp++) = val; + pmd_val(*pmdp++) = val; + pmd_val(*pmdp++) = val; + + v += LARGE_PAGE_SIZE_16M; + p += LARGE_PAGE_SIZE_16M; + s += LARGE_PAGE_SIZE_16M; + } + + while (s <= (total_lowmem - LARGE_PAGE_SIZE_4M)) { + pmd_t *pmdp; + unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE; + + pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v); + pmd_val(*pmdp) = val; + + v += LARGE_PAGE_SIZE_4M; + p += LARGE_PAGE_SIZE_4M; + s += LARGE_PAGE_SIZE_4M; + } + + return s; +} diff -puN arch/powerpc/mm/4xx_mmu.c~git-powerpc /dev/null --- a/arch/powerpc/mm/4xx_mmu.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file contains the routines for initializing the MMU - * on the 4xx series of chips. - * -- paulus - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mmu_decl.h" - -extern int __map_without_ltlbs; -/* - * MMU_init_hw does the chip-specific initialization of the MMU hardware. - */ -void __init MMU_init_hw(void) -{ - /* - * The Zone Protection Register (ZPR) defines how protection will - * be applied to every page which is a member of a given zone. At - * present, we utilize only two of the 4xx's zones. - * The zone index bits (of ZSEL) in the PTE are used for software - * indicators, except the LSB. For user access, zone 1 is used, - * for kernel access, zone 0 is used. We set all but zone 1 - * to zero, allowing only kernel access as indicated in the PTE. - * For zone 1, we set a 01 binary (a value of 10 will not work) - * to allow user access as indicated in the PTE. This also allows - * kernel access as indicated in the PTE. - */ - - mtspr(SPRN_ZPR, 0x10000000); - - flush_instruction_cache(); - - /* - * Set up the real-mode cache parameters for the exception vector - * handlers (which are run in real-mode). - */ - - mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */ - - /* - * Cache instruction and data space where the exception - * vectors and the kernel live in real-mode. - */ - - mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */ - mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */ -} - -#define LARGE_PAGE_SIZE_16M (1<<24) -#define LARGE_PAGE_SIZE_4M (1<<22) - -unsigned long __init mmu_mapin_ram(void) -{ - unsigned long v, s; - phys_addr_t p; - - v = KERNELBASE; - p = PPC_MEMSTART; - s = 0; - - if (__map_without_ltlbs) { - return s; - } - - while (s <= (total_lowmem - LARGE_PAGE_SIZE_16M)) { - pmd_t *pmdp; - unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE; - - pmdp = pmd_offset(pgd_offset_k(v), v); - pmd_val(*pmdp++) = val; - pmd_val(*pmdp++) = val; - pmd_val(*pmdp++) = val; - pmd_val(*pmdp++) = val; - - v += LARGE_PAGE_SIZE_16M; - p += LARGE_PAGE_SIZE_16M; - s += LARGE_PAGE_SIZE_16M; - } - - while (s <= (total_lowmem - LARGE_PAGE_SIZE_4M)) { - pmd_t *pmdp; - unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE; - - pmdp = pmd_offset(pgd_offset_k(v), v); - pmd_val(*pmdp) = val; - - v += LARGE_PAGE_SIZE_4M; - p += LARGE_PAGE_SIZE_4M; - s += LARGE_PAGE_SIZE_4M; - } - - return s; -} diff -puN arch/powerpc/mm/Makefile~git-powerpc arch/powerpc/mm/Makefile --- a/arch/powerpc/mm/Makefile~git-powerpc +++ a/arch/powerpc/mm/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_PPC64) += init_64.o pgtabl hash_utils_64.o hash_low_64.o tlb_64.o \ slb_low.o slb.o stab.o mmap.o $(hash-y) obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o hash_low_32.o tlb_32.o -obj-$(CONFIG_40x) += 4xx_mmu.o +obj-$(CONFIG_40x) += 40x_mmu.o obj-$(CONFIG_44x) += 44x_mmu.o obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o diff -puN arch/powerpc/mm/hash_utils_64.c~git-powerpc arch/powerpc/mm/hash_utils_64.c --- a/arch/powerpc/mm/hash_utils_64.c~git-powerpc +++ a/arch/powerpc/mm/hash_utils_64.c @@ -49,7 +49,6 @@ #include #include #include -#include #include #include @@ -602,13 +601,7 @@ static void demote_segment_4k(struct mm_ { if (mm->context.user_psize == MMU_PAGE_4K) return; -#ifdef CONFIG_PPC_MM_SLICES slice_set_user_psize(mm, MMU_PAGE_4K); -#else /* CONFIG_PPC_MM_SLICES */ - mm->context.user_psize = MMU_PAGE_4K; - mm->context.sllp = SLB_VSID_USER | mmu_psize_defs[MMU_PAGE_4K].sllp; -#endif /* CONFIG_PPC_MM_SLICES */ - #ifdef CONFIG_SPU_BASE spu_flush_all_slbs(mm); #endif diff -puN arch/powerpc/mm/hugetlbpage.c~git-powerpc arch/powerpc/mm/hugetlbpage.c --- a/arch/powerpc/mm/hugetlbpage.c~git-powerpc +++ a/arch/powerpc/mm/hugetlbpage.c @@ -22,11 +22,8 @@ #include #include #include -#include #include -#include - #define NUM_LOW_AREAS (0x100000000UL >> SID_SHIFT) #define NUM_HIGH_AREAS (PGTABLE_RANGE >> HTLB_AREA_SHIFT) diff -puN arch/powerpc/mm/init_32.c~git-powerpc arch/powerpc/mm/init_32.c --- a/arch/powerpc/mm/init_32.c~git-powerpc +++ a/arch/powerpc/mm/init_32.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include diff -puN arch/powerpc/mm/mem.c~git-powerpc arch/powerpc/mm/mem.c --- a/arch/powerpc/mm/mem.c~git-powerpc +++ a/arch/powerpc/mm/mem.c @@ -42,7 +42,6 @@ #include #include #include -#include #include #include #include diff -puN arch/powerpc/mm/mmu_context_64.c~git-powerpc arch/powerpc/mm/mmu_context_64.c --- a/arch/powerpc/mm/mmu_context_64.c~git-powerpc +++ a/arch/powerpc/mm/mmu_context_64.c @@ -28,7 +28,6 @@ int init_new_context(struct task_struct { int index; int err; - int new_context = (mm->context.id == 0); again: if (!idr_pre_get(&mmu_context_idr, GFP_KERNEL)) @@ -50,19 +49,13 @@ again: return -ENOMEM; } - mm->context.id = index; -#ifdef CONFIG_PPC_MM_SLICES /* The old code would re-promote on fork, we don't do that * when using slices as it could cause problem promoting slices * that have been forced down to 4K */ - if (new_context) + if (slice_mm_new_context(mm)) slice_set_user_psize(mm, mmu_virtual_psize); -#else - mm->context.user_psize = mmu_virtual_psize; - mm->context.sllp = SLB_VSID_USER | - mmu_psize_defs[mmu_virtual_psize].sllp; -#endif + mm->context.id = index; return 0; } diff -puN arch/powerpc/mm/pgtable_64.c~git-powerpc arch/powerpc/mm/pgtable_64.c --- a/arch/powerpc/mm/pgtable_64.c~git-powerpc +++ a/arch/powerpc/mm/pgtable_64.c @@ -228,5 +228,7 @@ void iounmap(volatile void __iomem *toke EXPORT_SYMBOL(ioremap); EXPORT_SYMBOL(ioremap_flags); EXPORT_SYMBOL(__ioremap); +EXPORT_SYMBOL(__ioremap_at); EXPORT_SYMBOL(iounmap); EXPORT_SYMBOL(__iounmap); +EXPORT_SYMBOL(__iounmap_at); diff -puN arch/powerpc/mm/slb.c~git-powerpc arch/powerpc/mm/slb.c --- a/arch/powerpc/mm/slb.c~git-powerpc +++ a/arch/powerpc/mm/slb.c @@ -59,14 +59,12 @@ static inline void slb_shadow_update(uns { /* * Clear the ESID first so the entry is not valid while we are - * updating it. + * updating it. No write barriers are needed here, provided + * we only update the current CPU's SLB shadow buffer. */ get_slb_shadow()->save_area[entry].esid = 0; - smp_wmb(); get_slb_shadow()->save_area[entry].vsid = mk_vsid_data(ea, flags); - smp_wmb(); get_slb_shadow()->save_area[entry].esid = mk_esid_data(ea, entry); - smp_wmb(); } static inline void slb_shadow_clear(unsigned long entry) diff -puN arch/powerpc/mm/slice.c~git-powerpc arch/powerpc/mm/slice.c --- a/arch/powerpc/mm/slice.c~git-powerpc +++ a/arch/powerpc/mm/slice.c @@ -551,6 +551,7 @@ EXPORT_SYMBOL_GPL(get_slice_psize); * * This is also called in init_new_context() to change back the user * psize from whatever the parent context had it set to + * N.B. This may be called before mm->context.id has been set. * * This function will only change the content of the {low,high)_slice_psize * masks, it will not flush SLBs as this shall be handled lazily by the diff -puN /dev/null arch/powerpc/platforms/40x/Kconfig --- /dev/null +++ a/arch/powerpc/platforms/40x/Kconfig @@ -0,0 +1,131 @@ +#config BUBINGA +# bool "Bubinga" +# depends on 40x +# default n +# select 405EP +# help +# This option enables support for the IBM 405EP evaluation board. + +#config CPCI405 +# bool "CPCI405" +# depends on 40x +# default n +# select 405GP +# help +# This option enables support for the CPCI405 board. + +#config EP405 +# bool "EP405/EP405PC" +# depends on 40x +# default n +# select 405GP +# help +# This option enables support for the EP405/EP405PC boards. + +#config EP405PC +# bool "EP405PC Support" +# depends on EP405 +# default y +# help +# This option enables support for the extra features of the EP405PC board. + +#config REDWOOD_5 +# bool "Redwood-5" +# depends on 40x +# default n +# select STB03xxx +# help +# This option enables support for the IBM STB04 evaluation board. + +#config REDWOOD_6 +# bool "Redwood-6" +# depends on 40x +# default n +# select STB03xxx +# help +# This option enables support for the IBM STBx25xx evaluation board. + +#config SYCAMORE +# bool "Sycamore" +# depends on 40x +# default n +# select 405GPR +# help +# This option enables support for the IBM PPC405GPr evaluation board. + +config WALNUT + bool "Walnut" + depends on 40x + default y + select 405GP + help + This option enables support for the IBM PPC405GP evaluation board. + +#config XILINX_ML300 +# bool "Xilinx-ML300" +# depends on 40x +# default y +# select VIRTEX_II_PRO +# help +# This option enables support for the Xilinx ML300 evaluation board. + +# 40x specific CPU modules, selected based on the board above. +config NP405H + bool + #depends on ASH + +# OAK doesn't exist but wanted to keep this around for any future 403GCX boards +config 403GCX + bool + #depends on OAK + select IBM405_ERR51 + +config 405GP + bool + select IBM405_ERR77 + select IBM405_ERR51 + +config 405EP + bool + +config 405GPR + bool + +config VIRTEX_II_PRO + bool + select IBM405_ERR77 + select IBM405_ERR51 + +config STB03xxx + bool + select IBM405_ERR77 + select IBM405_ERR51 + +# 40x errata/workaround config symbols, selected by the CPU models above + +# All 405-based cores up until the 405GPR and 405EP have this errata. +config IBM405_ERR77 + bool + +# All 40x-based cores, up until the 405GPR and 405EP have this errata. +config IBM405_ERR51 + bool + +#config XILINX_OCP +# bool +# depends on XILINX_ML300 +# default y + +#config BIOS_FIXUP +# bool +# depends on BUBINGA || EP405 || SYCAMORE || WALNUT +# default y + +#config PPC4xx_DMA +# bool "PPC4xx DMA controller support" +# depends on 4xx + +#config PPC4xx_EDMA +# bool +# depends on !STB03xxx && PPC4xx_DMA +# default y diff -puN /dev/null arch/powerpc/platforms/40x/Makefile --- /dev/null +++ a/arch/powerpc/platforms/40x/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_WALNUT) += walnut.o diff -puN /dev/null arch/powerpc/platforms/40x/walnut.c --- /dev/null +++ a/arch/powerpc/platforms/40x/walnut.c @@ -0,0 +1,68 @@ +/* + * Architecture- / platform-specific boot-time initialization code for + * IBM PowerPC 4xx based boards. Adapted from original + * code by Gary Thomas, Cort Dougan , and Dan Malek + * . + * + * Copyright(c) 1999-2000 Grant Erickson + * + * Rewritten and ported to the merged powerpc tree: + * Copyright 2007 IBM Corporation + * Josh Boyer + * + * 2002 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct of_device_id walnut_of_bus[] = { + { .compatible = "ibm,plb3", }, + { .compatible = "ibm,opb", }, + { .compatible = "ibm,ebc", }, + {}, +}; + +static int __init walnut_device_probe(void) +{ + if (!machine_is(walnut)) + return 0; + + /* FIXME: do bus probe here */ + of_platform_bus_probe(NULL, walnut_of_bus, NULL); + + return 0; +} +device_initcall(walnut_device_probe); + +static int __init walnut_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (!of_flat_dt_is_compatible(root, "ibm,walnut")) + return 0; + + return 1; +} + +static void __init walnut_setup_arch(void) +{ +} + +define_machine(walnut) { + .name = "Walnut", + .probe = walnut_probe, + .setup_arch = walnut_setup_arch, + .progress = udbg_progress, + .init_IRQ = uic_init_tree, + .get_irq = uic_get_irq, + .calibrate_decr = generic_calibrate_decr, +}; diff -puN arch/powerpc/platforms/44x/Kconfig~git-powerpc arch/powerpc/platforms/44x/Kconfig --- a/arch/powerpc/platforms/44x/Kconfig~git-powerpc +++ a/arch/powerpc/platforms/44x/Kconfig @@ -1,10 +1,10 @@ -#config BAMBOO -# bool "Bamboo" -# depends on 44x -# default n -# select 440EP -# help -# This option enables support for the IBM PPC440EP evaluation board. +config BAMBOO + bool "Bamboo" + depends on 44x + default n + select 440EP + help + This option enables support for the IBM PPC440EP evaluation board. config EBONY bool "Ebony" @@ -14,6 +14,14 @@ config EBONY help This option enables support for the IBM PPC440GP evaluation board. +config SEQUOIA + bool "Sequoia" + depends on 44x + default n + select 440EPX + help + This option enables support for the AMCC PPC440EPX evaluation board. + #config LUAN # bool "Luan" # depends on 44x @@ -35,6 +43,14 @@ config 440EP bool select PPC_FPU select IBM440EP_ERR42 +# select IBM_NEW_EMAC_ZMII + +config 440EPX + bool + select PPC_FPU +# Disabled until the new EMAC Driver is merged. +# select IBM_NEW_EMAC_EMAC4 +# select IBM_NEW_EMAC_ZMII config 440GP bool @@ -49,7 +65,7 @@ config 440SP config 440A bool - depends on 440GX + depends on 440GX || 440EPX default y # 44x errata/workaround config symbols, selected by the CPU models above diff -puN arch/powerpc/platforms/44x/Makefile~git-powerpc arch/powerpc/platforms/44x/Makefile --- a/arch/powerpc/platforms/44x/Makefile~git-powerpc +++ a/arch/powerpc/platforms/44x/Makefile @@ -1,2 +1,4 @@ obj-$(CONFIG_44x) := misc_44x.o obj-$(CONFIG_EBONY) += ebony.o +obj-$(CONFIG_BAMBOO) += bamboo.o +obj-$(CONFIG_SEQUOIA) += sequoia.o diff -puN /dev/null arch/powerpc/platforms/44x/bamboo.c --- /dev/null +++ a/arch/powerpc/platforms/44x/bamboo.c @@ -0,0 +1,66 @@ +/* + * Bamboo board specific routines + * + * Wade Farnsworth + * Copyright 2004 MontaVista Software Inc. + * + * Rewritten and ported to the merged powerpc tree: + * Josh Boyer + * Copyright 2007 IBM Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include "44x.h" + +static struct of_device_id bamboo_of_bus[] = { + { .compatible = "ibm,plb4", }, + { .compatible = "ibm,opb", }, + { .compatible = "ibm,ebc", }, + {}, +}; + +static int __init bamboo_device_probe(void) +{ + if (!machine_is(bamboo)) + return 0; + + of_platform_bus_probe(NULL, bamboo_of_bus, NULL); + + return 0; +} +device_initcall(bamboo_device_probe); + +static int __init bamboo_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (!of_flat_dt_is_compatible(root, "amcc,bamboo")) + return 0; + + return 1; +} + +static void __init bamboo_setup_arch(void) +{ +} + +define_machine(bamboo) { + .name = "Bamboo", + .probe = bamboo_probe, + .setup_arch = bamboo_setup_arch, + .progress = udbg_progress, + .init_IRQ = uic_init_tree, + .get_irq = uic_get_irq, + .restart = ppc44x_reset_system, + .calibrate_decr = generic_calibrate_decr, +}; diff -puN /dev/null arch/powerpc/platforms/44x/sequoia.c --- /dev/null +++ a/arch/powerpc/platforms/44x/sequoia.c @@ -0,0 +1,66 @@ +/* + * Sequoia board specific routines + * + * Valentine Barshak + * Copyright 2007 MontaVista Software Inc. + * + * Based on the Bamboo code by + * Josh Boyer + * Copyright 2007 IBM Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include "44x.h" + +static struct of_device_id sequoia_of_bus[] = { + { .compatible = "ibm,plb4", }, + { .compatible = "ibm,opb", }, + { .compatible = "ibm,ebc", }, + {}, +}; + +static int __init sequoia_device_probe(void) +{ + if (!machine_is(sequoia)) + return 0; + + of_platform_bus_probe(NULL, sequoia_of_bus, NULL); + + return 0; +} +device_initcall(sequoia_device_probe); + +static int __init sequoia_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (!of_flat_dt_is_compatible(root, "amcc,sequoia")) + return 0; + + return 1; +} + +static void __init sequoia_setup_arch(void) +{ +} + +define_machine(sequoia) { + .name = "Sequoia", + .probe = sequoia_probe, + .setup_arch = sequoia_setup_arch, + .progress = udbg_progress, + .init_IRQ = uic_init_tree, + .get_irq = uic_get_irq, + .restart = ppc44x_reset_system, + .calibrate_decr = generic_calibrate_decr, +}; diff -puN arch/powerpc/platforms/4xx/Kconfig~git-powerpc /dev/null --- a/arch/powerpc/platforms/4xx/Kconfig +++ /dev/null @@ -1,208 +0,0 @@ -config 4xx - bool - depends on 40x || 44x - default y - -config BOOKE - bool - depends on 44x - default y - -menu "AMCC 40x options" - depends on 40x - -#config BUBINGA -# bool "Bubinga" -# depends on 40x -# default n -# select 405EP -# help -# This option enables support for the IBM 405EP evaluation board. - -#config CPCI405 -# bool "CPCI405" -# depends on 40x -# default n -# select 405GP -# help -# This option enables support for the CPCI405 board. - -#config EP405 -# bool "EP405/EP405PC" -# depends on 40x -# default n -# select 405GP -# help -# This option enables support for the EP405/EP405PC boards. - -#config EP405PC -# bool "EP405PC Support" -# depends on EP405 -# default y -# help -# This option enables support for the extra features of the EP405PC board. - -#config REDWOOD_5 -# bool "Redwood-5" -# depends on 40x -# default n -# select STB03xxx -# help -# This option enables support for the IBM STB04 evaluation board. - -#config REDWOOD_6 -# bool "Redwood-6" -# depends on 40x -# default n -# select STB03xxx -# help -# This option enables support for the IBM STBx25xx evaluation board. - -#config SYCAMORE -# bool "Sycamore" -# depends on 40x -# default n -# select 405GPR -# help -# This option enables support for the IBM PPC405GPr evaluation board. - -#config WALNUT -# bool "Walnut" -# depends on 40x -# default y -# select 405GP -# help -# This option enables support for the IBM PPC405GP evaluation board. - -#config XILINX_ML300 -# bool "Xilinx-ML300" -# depends on 40x -# default y -# select VIRTEX_II_PRO -# help -# This option enables support for the Xilinx ML300 evaluation board. - -endmenu - -# 40x specific CPU modules, selected based on the board above. -config NP405H - bool - #depends on ASH - -# OAK doesn't exist but wanted to keep this around for any future 403GCX boards -config 403GCX - bool - #depends on OAK - select IBM405_ERR51 - -config 405GP - bool - select IBM405_ERR77 - select IBM405_ERR51 - -config 405EP - bool - -config 405GPR - bool - -config VIRTEX_II_PRO - bool - select IBM405_ERR77 - select IBM405_ERR51 - -config STB03xxx - bool - select IBM405_ERR77 - select IBM405_ERR51 - -# 40x errata/workaround config symbols, selected by the CPU models above - -# All 405-based cores up until the 405GPR and 405EP have this errata. -config IBM405_ERR77 - bool - -# All 40x-based cores, up until the 405GPR and 405EP have this errata. -config IBM405_ERR51 - bool - -menu "AMCC 44x options" - depends on 44x - -#config BAMBOO -# bool "Bamboo" -# depends on 44x -# default n -# select 440EP -# help -# This option enables support for the IBM PPC440EP evaluation board. - -config EBONY - bool "Ebony" - depends on 44x - default y - select 440GP - help - This option enables support for the IBM PPC440GP evaluation board. - -#config LUAN -# bool "Luan" -# depends on 44x -# default n -# select 440SP -# help -# This option enables support for the IBM PPC440SP evaluation board. - -#config OCOTEA -# bool "Ocotea" -# depends on 44x -# default n -# select 440GX -# help -# This option enables support for the IBM PPC440GX evaluation board. - -endmenu - -# 44x specific CPU modules, selected based on the board above. -config 440EP - bool - select PPC_FPU - select IBM440EP_ERR42 - -config 440GP - bool - select IBM_NEW_EMAC_ZMII - -config 440GX - bool - -config 440SP - bool - -config 440A - bool - depends on 440GX - default y - -# 44x errata/workaround config symbols, selected by the CPU models above -config IBM440EP_ERR42 - bool - -#config XILINX_OCP -# bool -# depends on XILINX_ML300 -# default y - -#config BIOS_FIXUP -# bool -# depends on BUBINGA || EP405 || SYCAMORE || WALNUT -# default y - -#config PPC4xx_DMA -# bool "PPC4xx DMA controller support" -# depends on 4xx - -#config PPC4xx_EDMA -# bool -# depends on !STB03xxx && PPC4xx_DMA -# default y diff -puN arch/powerpc/platforms/4xx/Makefile~git-powerpc /dev/null --- a/arch/powerpc/platforms/4xx/Makefile +++ /dev/null @@ -1 +0,0 @@ -# empty makefile so make clean works \ No newline at end of file diff -puN arch/powerpc/platforms/52xx/Makefile~git-powerpc arch/powerpc/platforms/52xx/Makefile --- a/arch/powerpc/platforms/52xx/Makefile~git-powerpc +++ a/arch/powerpc/platforms/52xx/Makefile @@ -10,3 +10,6 @@ obj-$(CONFIG_PPC_EFIKA) += efika.o obj-$(CONFIG_PPC_LITE5200) += lite5200.o obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o +ifeq ($(CONFIG_PPC_LITE5200),y) + obj-$(CONFIG_PM) += lite5200_sleep.o lite5200_pm.o +endif diff -puN arch/powerpc/platforms/52xx/efika.c~git-powerpc arch/powerpc/platforms/52xx/efika.c --- a/arch/powerpc/platforms/52xx/efika.c~git-powerpc +++ a/arch/powerpc/platforms/52xx/efika.c @@ -78,8 +78,8 @@ static int rtas_write_config(struct pci_ } static struct pci_ops rtas_pci_ops = { - rtas_read_config, - rtas_write_config + .read = rtas_read_config, + .write = rtas_write_config, }; diff -puN arch/powerpc/platforms/52xx/lite5200.c~git-powerpc arch/powerpc/platforms/52xx/lite5200.c --- a/arch/powerpc/platforms/52xx/lite5200.c~git-powerpc +++ a/arch/powerpc/platforms/52xx/lite5200.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -86,7 +85,6 @@ error: } #ifdef CONFIG_PM -static u32 descr_a; static void lite5200_suspend_prepare(void __iomem *mbar) { u8 pin = 1; /* GPIO_WKUP_1 (GPIO_PSC2_4) */ @@ -97,34 +95,30 @@ static void lite5200_suspend_prepare(voi * power down usb port * this needs to be called before of-ohci suspend code */ - descr_a = in_be32(mbar + 0x1048); - out_be32(mbar + 0x1048, (descr_a & ~0x200) | 0x100); + + /* set ports to "power switched" and "powered at the same time" + * USB Rh descriptor A: NPS = 0, PSM = 0 */ + out_be32(mbar + 0x1048, in_be32(mbar + 0x1048) & ~0x300); + /* USB Rh status: LPS = 1 - turn off power */ + out_be32(mbar + 0x1050, 0x00000001); } static void lite5200_resume_finish(void __iomem *mbar) { - out_be32(mbar + 0x1048, descr_a); + /* USB Rh status: LPSC = 1 - turn on power */ + out_be32(mbar + 0x1050, 0x00010000); } #endif static void __init lite5200_setup_arch(void) { +#ifdef CONFIG_PCI struct device_node *np; +#endif if (ppc_md.progress) ppc_md.progress("lite5200_setup_arch()", 0); - np = of_find_node_by_type(NULL, "cpu"); - if (np) { - const unsigned int *fp = - of_get_property(np, "clock-frequency", NULL); - if (fp != 0) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 50000000 / HZ; - of_node_put(np); - } - /* CPU & Port mux setup */ mpc52xx_setup_cpu(); /* Generic */ lite5200_setup_cpu(); /* Platorm specific */ @@ -132,7 +126,7 @@ static void __init lite5200_setup_arch(v #ifdef CONFIG_PM mpc52xx_suspend.board_suspend_prepare = lite5200_suspend_prepare; mpc52xx_suspend.board_resume_finish = lite5200_resume_finish; - mpc52xx_pm_init(); + lite5200_pm_init(); #endif #ifdef CONFIG_PCI diff -puN /dev/null arch/powerpc/platforms/52xx/lite5200_pm.c --- /dev/null +++ a/arch/powerpc/platforms/52xx/lite5200_pm.c @@ -0,0 +1,213 @@ +#include +#include +#include +#include +#include +#include "mpc52xx_pic.h" + +/* defined in lite5200_sleep.S and only used here */ +extern void lite5200_low_power(void __iomem *sram, void __iomem *mbar); + +static struct mpc52xx_cdm __iomem *cdm; +static struct mpc52xx_intr __iomem *pic; +static struct mpc52xx_sdma __iomem *bes; +static struct mpc52xx_xlb __iomem *xlb; +static struct mpc52xx_gpio __iomem *gps; +static struct mpc52xx_gpio_wkup __iomem *gpw; +static void __iomem *sram; +static const int sram_size = 0x4000; /* 16 kBytes */ +static void __iomem *mbar; + +static int lite5200_pm_valid(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + return 1; + default: + return 0; + } +} + +static int lite5200_pm_prepare(suspend_state_t state) +{ + /* deep sleep? let mpc52xx code handle that */ + if (state == PM_SUSPEND_STANDBY) + return mpc52xx_pm_prepare(state); + + if (state != PM_SUSPEND_MEM) + return -EINVAL; + + /* map registers */ + mbar = mpc52xx_find_and_map("mpc5200"); + if (!mbar) { + printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__); + return -ENOSYS; + } + + cdm = mbar + 0x200; + pic = mbar + 0x500; + gps = mbar + 0xb00; + gpw = mbar + 0xc00; + bes = mbar + 0x1200; + xlb = mbar + 0x1f00; + sram = mbar + 0x8000; + + return 0; +} + +/* save and restore registers not bound to any real devices */ +static struct mpc52xx_cdm scdm; +static struct mpc52xx_intr spic; +static struct mpc52xx_sdma sbes; +static struct mpc52xx_xlb sxlb; +static struct mpc52xx_gpio sgps; +static struct mpc52xx_gpio_wkup sgpw; + +static void lite5200_save_regs(void) +{ + _memcpy_fromio(&spic, pic, sizeof(*pic)); + _memcpy_fromio(&sbes, bes, sizeof(*bes)); + _memcpy_fromio(&scdm, cdm, sizeof(*cdm)); + _memcpy_fromio(&sxlb, xlb, sizeof(*xlb)); + _memcpy_fromio(&sgps, gps, sizeof(*gps)); + _memcpy_fromio(&sgpw, gpw, sizeof(*gpw)); + + _memcpy_fromio(saved_sram, sram, sram_size); +} + +static void lite5200_restore_regs(void) +{ + int i; + _memcpy_toio(sram, saved_sram, sram_size); + + + /* + * GPIOs. Interrupt Master Enable has higher address then other + * registers, so just memcpy is ok. + */ + _memcpy_toio(gpw, &sgpw, sizeof(*gpw)); + _memcpy_toio(gps, &sgps, sizeof(*gps)); + + + /* XLB Arbitrer */ + out_be32(&xlb->snoop_window, sxlb.snoop_window); + out_be32(&xlb->master_priority, sxlb.master_priority); + out_be32(&xlb->master_pri_enable, sxlb.master_pri_enable); + + /* enable */ + out_be32(&xlb->int_enable, sxlb.int_enable); + out_be32(&xlb->config, sxlb.config); + + + /* CDM - Clock Distribution Module */ + out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel); + out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel); + + out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en); + out_8(&cdm->fd_enable, scdm.fd_enable); + out_be16(&cdm->fd_counters, scdm.fd_counters); + + out_be32(&cdm->clk_enables, scdm.clk_enables); + + out_8(&cdm->osc_disable, scdm.osc_disable); + + out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1); + out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2); + out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3); + out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6); + + + /* BESTCOMM */ + out_be32(&bes->taskBar, sbes.taskBar); + out_be32(&bes->currentPointer, sbes.currentPointer); + out_be32(&bes->endPointer, sbes.endPointer); + out_be32(&bes->variablePointer, sbes.variablePointer); + + out_8(&bes->IntVect1, sbes.IntVect1); + out_8(&bes->IntVect2, sbes.IntVect2); + out_be16(&bes->PtdCntrl, sbes.PtdCntrl); + + for (i=0; i<32; i++) + out_8(&bes->ipr[i], sbes.ipr[i]); + + out_be32(&bes->cReqSelect, sbes.cReqSelect); + out_be32(&bes->task_size0, sbes.task_size0); + out_be32(&bes->task_size1, sbes.task_size1); + out_be32(&bes->MDEDebug, sbes.MDEDebug); + out_be32(&bes->ADSDebug, sbes.ADSDebug); + out_be32(&bes->Value1, sbes.Value1); + out_be32(&bes->Value2, sbes.Value2); + out_be32(&bes->Control, sbes.Control); + out_be32(&bes->Status, sbes.Status); + out_be32(&bes->PTDDebug, sbes.PTDDebug); + + /* restore tasks */ + for (i=0; i<16; i++) + out_be16(&bes->tcr[i], sbes.tcr[i]); + + /* enable interrupts */ + out_be32(&bes->IntPend, sbes.IntPend); + out_be32(&bes->IntMask, sbes.IntMask); + + + /* PIC */ + out_be32(&pic->per_pri1, spic.per_pri1); + out_be32(&pic->per_pri2, spic.per_pri2); + out_be32(&pic->per_pri3, spic.per_pri3); + + out_be32(&pic->main_pri1, spic.main_pri1); + out_be32(&pic->main_pri2, spic.main_pri2); + + out_be32(&pic->enc_status, spic.enc_status); + + /* unmask and enable interrupts */ + out_be32(&pic->per_mask, spic.per_mask); + out_be32(&pic->main_mask, spic.main_mask); + out_be32(&pic->ctrl, spic.ctrl); +} + +static int lite5200_pm_enter(suspend_state_t state) +{ + /* deep sleep? let mpc52xx code handle that */ + if (state == PM_SUSPEND_STANDBY) { + return mpc52xx_pm_enter(state); + } + + lite5200_save_regs(); + + /* effectively save FP regs */ + enable_kernel_fp(); + + lite5200_low_power(sram, mbar); + + lite5200_restore_regs(); + + /* restart jiffies */ + wakeup_decrementer(); + + iounmap(mbar); + return 0; +} + +static int lite5200_pm_finish(suspend_state_t state) +{ + /* deep sleep? let mpc52xx code handle that */ + if (state == PM_SUSPEND_STANDBY) { + return mpc52xx_pm_finish(state); + } + return 0; +} + +static struct pm_ops lite5200_pm_ops = { + .valid = lite5200_pm_valid, + .prepare = lite5200_pm_prepare, + .enter = lite5200_pm_enter, + .finish = lite5200_pm_finish, +}; + +int __init lite5200_pm_init(void) +{ + pm_set_ops(&lite5200_pm_ops); + return 0; +} diff -puN /dev/null arch/powerpc/platforms/52xx/lite5200_sleep.S --- /dev/null +++ a/arch/powerpc/platforms/52xx/lite5200_sleep.S @@ -0,0 +1,412 @@ +#include +#include +#include +#include + + +#define SDRAM_CTRL 0x104 +#define SC_MODE_EN (1<<31) +#define SC_CKE (1<<30) +#define SC_REF_EN (1<<28) +#define SC_SOFT_PRE (1<<1) + +#define GPIOW_GPIOE 0xc00 +#define GPIOW_DDR 0xc08 +#define GPIOW_DVO 0xc0c + +#define CDM_CE 0x214 +#define CDM_SDRAM (1<<3) + + +/* helpers... beware: r10 and r4 are overwritten */ +#define SAVE_SPRN(reg, addr) \ + mfspr r10, SPRN_##reg; \ + stw r10, ((addr)*4)(r4); + +#define LOAD_SPRN(reg, addr) \ + lwz r10, ((addr)*4)(r4); \ + mtspr SPRN_##reg, r10; \ + sync; \ + isync; + + + .data +registers: + .space 0x5c*4 + .text + +/* ---------------------------------------------------------------------- */ +/* low-power mode with help of M68HLC908QT1 */ + + .globl lite5200_low_power +lite5200_low_power: + + mr r7, r3 /* save SRAM va */ + mr r8, r4 /* save MBAR va */ + + /* setup wakeup address for u-boot at physical location 0x0 */ + lis r3, CONFIG_KERNEL_START@h + lis r4, lite5200_wakeup@h + ori r4, r4, lite5200_wakeup@l + sub r4, r4, r3 + stw r4, 0(r3) + + + /* + * save stuff BDI overwrites + * 0xf0 (0xe0->0x100 gets overwritten when BDI connected; + * even when CONFIG_BDI* is disabled and MMU XLAT commented; heisenbug?)) + * WARNING: self-refresh doesn't seem to work when BDI2000 is connected, + * possibly because BDI sets SDRAM registers before wakeup code does + */ + lis r4, registers@h + ori r4, r4, registers@l + lwz r10, 0xf0(r3) + stw r10, (0x1d*4)(r4) + + /* save registers to r4 [destroys r10] */ + SAVE_SPRN(LR, 0x1c) + bl save_regs + + /* flush caches [destroys r3, r4] */ + bl flush_data_cache + + + /* copy code to sram */ + mr r4, r7 + li r3, (sram_code_end - sram_code)/4 + mtctr r3 + lis r3, sram_code@h + ori r3, r3, sram_code@l +1: + lwz r5, 0(r3) + stw r5, 0(r4) + addi r3, r3, 4 + addi r4, r4, 4 + bdnz 1b + + /* get tb_ticks_per_usec */ + lis r3, tb_ticks_per_usec@h + lwz r11, tb_ticks_per_usec@l(r3) + + /* disable I and D caches */ + mfspr r3, SPRN_HID0 + ori r3, r3, HID0_ICE | HID0_DCE + xori r3, r3, HID0_ICE | HID0_DCE + sync; isync; + mtspr SPRN_HID0, r3 + sync; isync; + + /* jump to sram */ + mtlr r7 + blrl + /* doesn't return */ + + +sram_code: + /* self refresh */ + lwz r4, SDRAM_CTRL(r8) + + /* send NOP (precharge) */ + oris r4, r4, SC_MODE_EN@h /* mode_en */ + stw r4, SDRAM_CTRL(r8) + sync + + ori r4, r4, SC_SOFT_PRE /* soft_pre */ + stw r4, SDRAM_CTRL(r8) + sync + xori r4, r4, SC_SOFT_PRE + + xoris r4, r4, SC_MODE_EN@h /* !mode_en */ + stw r4, SDRAM_CTRL(r8) + sync + + /* delay (for NOP to finish) */ + li r12, 1 + bl udelay + + /* + * mode_en must not be set when enabling self-refresh + * send AR with CKE low (self-refresh) + */ + oris r4, r4, (SC_REF_EN | SC_CKE)@h + xoris r4, r4, (SC_CKE)@h /* ref_en !cke */ + stw r4, SDRAM_CTRL(r8) + sync + + /* delay (after !CKE there should be two cycles) */ + li r12, 1 + bl udelay + + /* disable clock */ + lwz r4, CDM_CE(r8) + ori r4, r4, CDM_SDRAM + xori r4, r4, CDM_SDRAM + stw r4, CDM_CE(r8) + sync + + /* delay a bit */ + li r12, 1 + bl udelay + + + /* turn off with QT chip */ + li r4, 0x02 + stb r4, GPIOW_GPIOE(r8) /* enable gpio_wkup1 */ + sync + + stb r4, GPIOW_DVO(r8) /* "output" high */ + sync + stb r4, GPIOW_DDR(r8) /* output */ + sync + stb r4, GPIOW_DVO(r8) /* output high */ + sync + + /* 10uS delay */ + li r12, 10 + bl udelay + + /* turn off */ + li r4, 0 + stb r4, GPIOW_DVO(r8) /* output low */ + sync + + /* wait until we're offline */ + 1: + b 1b + + + /* local udelay in sram is needed */ + udelay: /* r11 - tb_ticks_per_usec, r12 - usecs, overwrites r13 */ + mullw r12, r12, r11 + mftb r13 /* start */ + addi r12, r13, r12 /* end */ + 1: + mftb r13 /* current */ + cmp cr0, r13, r12 + blt 1b + blr + +sram_code_end: + + + +/* uboot jumps here on resume */ +lite5200_wakeup: + bl restore_regs + + + /* HIDs, MSR */ + LOAD_SPRN(HID1, 0x19) + LOAD_SPRN(HID2, 0x1a) + + + /* address translation is tricky (see turn_on_mmu) */ + mfmsr r10 + ori r10, r10, MSR_DR | MSR_IR + + + mtspr SPRN_SRR1, r10 + lis r10, mmu_on@h + ori r10, r10, mmu_on@l + mtspr SPRN_SRR0, r10 + sync + rfi +mmu_on: + /* kernel offset (r4 is still set from restore_registers) */ + addis r4, r4, CONFIG_KERNEL_START@h + + + /* restore MSR */ + lwz r10, (4*0x1b)(r4) + mtmsr r10 + sync; isync; + + /* invalidate caches */ + mfspr r10, SPRN_HID0 + ori r5, r10, HID0_ICFI | HID0_DCI + mtspr SPRN_HID0, r5 /* invalidate caches */ + sync; isync; + mtspr SPRN_HID0, r10 + sync; isync; + + /* enable caches */ + lwz r10, (4*0x18)(r4) + mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */ + /* ^ this has to be after address translation set in MSR */ + sync + isync + + + /* restore 0xf0 (BDI2000) */ + lis r3, CONFIG_KERNEL_START@h + lwz r10, (0x1d*4)(r4) + stw r10, 0xf0(r3) + + LOAD_SPRN(LR, 0x1c) + + + blr + + +/* ---------------------------------------------------------------------- */ +/* boring code: helpers */ + +/* save registers */ +#define SAVE_BAT(n, addr) \ + SAVE_SPRN(DBAT##n##L, addr); \ + SAVE_SPRN(DBAT##n##U, addr+1); \ + SAVE_SPRN(IBAT##n##L, addr+2); \ + SAVE_SPRN(IBAT##n##U, addr+3); + +#define SAVE_SR(n, addr) \ + mfsr r10, n; \ + stw r10, ((addr)*4)(r4); + +#define SAVE_4SR(n, addr) \ + SAVE_SR(n, addr); \ + SAVE_SR(n+1, addr+1); \ + SAVE_SR(n+2, addr+2); \ + SAVE_SR(n+3, addr+3); + +save_regs: + stw r0, 0(r4) + stw r1, 0x4(r4) + stw r2, 0x8(r4) + stmw r11, 0xc(r4) /* 0xc -> 0x5f, (0x18*4-1) */ + + SAVE_SPRN(HID0, 0x18) + SAVE_SPRN(HID1, 0x19) + SAVE_SPRN(HID2, 0x1a) + mfmsr r10 + stw r10, (4*0x1b)(r4) + /*SAVE_SPRN(LR, 0x1c) have to save it before the call */ + /* 0x1d reserved by 0xf0 */ + SAVE_SPRN(RPA, 0x1e) + SAVE_SPRN(SDR1, 0x1f) + + /* save MMU regs */ + SAVE_BAT(0, 0x20) + SAVE_BAT(1, 0x24) + SAVE_BAT(2, 0x28) + SAVE_BAT(3, 0x2c) + SAVE_BAT(4, 0x30) + SAVE_BAT(5, 0x34) + SAVE_BAT(6, 0x38) + SAVE_BAT(7, 0x3c) + + SAVE_4SR(0, 0x40) + SAVE_4SR(4, 0x44) + SAVE_4SR(8, 0x48) + SAVE_4SR(12, 0x4c) + + SAVE_SPRN(SPRG0, 0x50) + SAVE_SPRN(SPRG1, 0x51) + SAVE_SPRN(SPRG2, 0x52) + SAVE_SPRN(SPRG3, 0x53) + SAVE_SPRN(SPRG4, 0x54) + SAVE_SPRN(SPRG5, 0x55) + SAVE_SPRN(SPRG6, 0x56) + SAVE_SPRN(SPRG7, 0x57) + + SAVE_SPRN(IABR, 0x58) + SAVE_SPRN(DABR, 0x59) + SAVE_SPRN(TBRL, 0x5a) + SAVE_SPRN(TBRU, 0x5b) + + blr + + +/* restore registers */ +#define LOAD_BAT(n, addr) \ + LOAD_SPRN(DBAT##n##L, addr); \ + LOAD_SPRN(DBAT##n##U, addr+1); \ + LOAD_SPRN(IBAT##n##L, addr+2); \ + LOAD_SPRN(IBAT##n##U, addr+3); + +#define LOAD_SR(n, addr) \ + lwz r10, ((addr)*4)(r4); \ + mtsr n, r10; + +#define LOAD_4SR(n, addr) \ + LOAD_SR(n, addr); \ + LOAD_SR(n+1, addr+1); \ + LOAD_SR(n+2, addr+2); \ + LOAD_SR(n+3, addr+3); + +restore_regs: + lis r4, registers@h + ori r4, r4, registers@l + + /* MMU is not up yet */ + subis r4, r4, CONFIG_KERNEL_START@h + + lwz r0, 0(r4) + lwz r1, 0x4(r4) + lwz r2, 0x8(r4) + lmw r11, 0xc(r4) + + /* + * these are a bit tricky + * + * 0x18 - HID0 + * 0x19 - HID1 + * 0x1a - HID2 + * 0x1b - MSR + * 0x1c - LR + * 0x1d - reserved by 0xf0 (BDI2000) + */ + LOAD_SPRN(RPA, 0x1e); + LOAD_SPRN(SDR1, 0x1f); + + /* restore MMU regs */ + LOAD_BAT(0, 0x20) + LOAD_BAT(1, 0x24) + LOAD_BAT(2, 0x28) + LOAD_BAT(3, 0x2c) + LOAD_BAT(4, 0x30) + LOAD_BAT(5, 0x34) + LOAD_BAT(6, 0x38) + LOAD_BAT(7, 0x3c) + + LOAD_4SR(0, 0x40) + LOAD_4SR(4, 0x44) + LOAD_4SR(8, 0x48) + LOAD_4SR(12, 0x4c) + + /* rest of regs */ + LOAD_SPRN(SPRG0, 0x50); + LOAD_SPRN(SPRG1, 0x51); + LOAD_SPRN(SPRG2, 0x52); + LOAD_SPRN(SPRG3, 0x53); + LOAD_SPRN(SPRG4, 0x54); + LOAD_SPRN(SPRG5, 0x55); + LOAD_SPRN(SPRG6, 0x56); + LOAD_SPRN(SPRG7, 0x57); + + LOAD_SPRN(IABR, 0x58); + LOAD_SPRN(DABR, 0x59); + LOAD_SPRN(TBWL, 0x5a); /* these two have separate R/W regs */ + LOAD_SPRN(TBWU, 0x5b); + + blr + + + +/* cache flushing code. copied from arch/ppc/boot/util.S */ +#define NUM_CACHE_LINES (128*8) + +/* + * Flush data cache + * Do this by just reading lots of stuff into the cache. + */ +flush_data_cache: + lis r3,CONFIG_KERNEL_START@h + ori r3,r3,CONFIG_KERNEL_START@l + li r4,NUM_CACHE_LINES + mtctr r4 +1: + lwz r4,0(r3) + addi r3,r3,L1_CACHE_BYTES /* Next line, please */ + bdnz 1b + blr diff -puN arch/powerpc/platforms/52xx/mpc52xx_pic.c~git-powerpc arch/powerpc/platforms/52xx/mpc52xx_pic.c --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c~git-powerpc +++ a/arch/powerpc/platforms/52xx/mpc52xx_pic.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -242,12 +241,6 @@ static struct irq_chip mpc52xx_sdma_irqc * irq_host */ -static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node) -{ - pr_debug("%s: node=%p\n", __func__, node); - return mpc52xx_irqhost->host_data == node; -} - static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, u32 * intspec, unsigned int intsize, irq_hw_number_t * out_hwirq, @@ -368,7 +361,6 @@ static int mpc52xx_irqhost_map(struct ir } static struct irq_host_ops mpc52xx_irqhost_ops = { - .match = mpc52xx_irqhost_match, .xlate = mpc52xx_irqhost_xlate, .map = mpc52xx_irqhost_map, }; @@ -420,14 +412,13 @@ void __init mpc52xx_init_irq(void) * hw irq information provided by the ofw to linux virq */ - mpc52xx_irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, + mpc52xx_irqhost = irq_alloc_host(picnode, IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTHWIRQ, &mpc52xx_irqhost_ops, -1); if (!mpc52xx_irqhost) panic(__FILE__ ": Cannot allocate the IRQ host\n"); - mpc52xx_irqhost->host_data = picnode; printk(KERN_INFO "MPC52xx PIC is up and running!\n"); } diff -puN arch/powerpc/platforms/82xx/m82xx_pci.h~git-powerpc arch/powerpc/platforms/82xx/m82xx_pci.h --- a/arch/powerpc/platforms/82xx/m82xx_pci.h~git-powerpc +++ a/arch/powerpc/platforms/82xx/m82xx_pci.h @@ -8,8 +8,6 @@ * 2 of the License, or (at your option) any later version. */ -#include - #define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET) #ifndef _IO_BASE diff -puN arch/powerpc/platforms/82xx/mpc82xx.c~git-powerpc arch/powerpc/platforms/82xx/mpc82xx.c --- a/arch/powerpc/platforms/82xx/mpc82xx.c~git-powerpc +++ a/arch/powerpc/platforms/82xx/mpc82xx.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include diff -puN arch/powerpc/platforms/82xx/mpc82xx_ads.c~git-powerpc arch/powerpc/platforms/82xx/mpc82xx_ads.c --- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c~git-powerpc +++ a/arch/powerpc/platforms/82xx/mpc82xx_ads.c @@ -37,7 +37,6 @@ #include #include #include -#include #include #include #include @@ -62,7 +61,6 @@ static struct { static unsigned long pci_int_base; static struct irq_host *pci_pic_host; -static struct device_node *pci_pic_node; #endif static void __init mpc82xx_ads_pic_init(void) @@ -400,11 +398,6 @@ m82xx_pci_irq_demux(unsigned int irq, st } } -static int pci_pic_host_match(struct irq_host *h, struct device_node *node) -{ - return node == pci_pic_node; -} - static int pci_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { @@ -420,7 +413,6 @@ static void pci_host_unmap(struct irq_ho } static struct irq_host_ops pci_pic_host_ops = { - .match = pci_pic_host_match, .map = pci_pic_host_map, .unmap = pci_host_unmap, }; @@ -479,7 +471,6 @@ void m82xx_pci_init_irq(void) iounmap(immap); return; } - pci_pic_node = of_node_get(np); /* PCI interrupt controller registers: status and mask */ regs = of_get_property(np, "reg", &size); if ((!regs) || (size <= 2)) { @@ -491,7 +482,6 @@ void m82xx_pci_init_irq(void) ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg)); pci_regs.pci_int_mask_reg = ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg)); - of_node_put(np); /* configure chip select for PCI interrupt controller */ immap->im_memctl.memc_br3 = regs[0] | 0x00001801; immap->im_memctl.memc_or3 = 0xffff8010; @@ -502,7 +492,7 @@ void m82xx_pci_init_irq(void) *pci_regs.pci_int_mask_reg |= 0xfff00000; iounmap(immap); pci_pic_host = - irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1, + irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1, &pci_pic_host_ops, irq_max + 1); return; } diff -puN arch/powerpc/platforms/82xx/pq2ads.h~git-powerpc arch/powerpc/platforms/82xx/pq2ads.h --- a/arch/powerpc/platforms/82xx/pq2ads.h~git-powerpc +++ a/arch/powerpc/platforms/82xx/pq2ads.h @@ -23,7 +23,6 @@ #define __MACH_ADS8260_DEFS #include -#include /* For our show_cpuinfo hooks. */ #define CPUINFO_VENDOR "Freescale Semiconductor" diff -puN arch/powerpc/platforms/83xx/mpc8313_rdb.c~git-powerpc arch/powerpc/platforms/83xx/mpc8313_rdb.c --- a/arch/powerpc/platforms/83xx/mpc8313_rdb.c~git-powerpc +++ a/arch/powerpc/platforms/83xx/mpc8313_rdb.c @@ -45,8 +45,6 @@ static void __init mpc8313_rdb_setup_arc #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif mpc831x_usb_cfg(); } diff -puN arch/powerpc/platforms/83xx/mpc832x_mds.c~git-powerpc arch/powerpc/platforms/83xx/mpc832x_mds.c --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c~git-powerpc +++ a/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -76,7 +75,6 @@ static void __init mpc832x_sys_setup_arc #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); - ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif #ifdef CONFIG_QUICC_ENGINE diff -puN arch/powerpc/platforms/83xx/mpc832x_rdb.c~git-powerpc arch/powerpc/platforms/83xx/mpc832x_rdb.c --- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c~git-powerpc +++ a/arch/powerpc/platforms/83xx/mpc832x_rdb.c @@ -15,6 +15,7 @@ */ #include +#include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include "mpc83xx.h" @@ -32,6 +34,50 @@ #define DBG(fmt...) #endif +static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity) +{ + pr_debug("%s %d %d\n", __func__, cs, polarity); + par_io_data_set(3, 13, polarity); +} + +static void mpc83xx_spi_deactivate_cs(u8 cs, u8 polarity) +{ + pr_debug("%s %d %d\n", __func__, cs, polarity); + par_io_data_set(3, 13, !polarity); +} + +static struct spi_board_info mpc832x_spi_boardinfo = { + .bus_num = 0x4c0, + .chip_select = 0, + .max_speed_hz = 50000000, + /* + * XXX: This is spidev (spi in userspace) stub, should + * be replaced by "mmc_spi" when mmc_spi will hit mainline. + */ + .modalias = "spidev", +}; + +static int __init mpc832x_spi_init(void) +{ + if (!machine_is(mpc832x_rdb)) + return 0; + + par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */ + par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */ + par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */ + par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */ + + par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */ + par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */ + par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */ + + return fsl_spi_init(&mpc832x_spi_boardinfo, 1, + mpc83xx_spi_activate_cs, + mpc83xx_spi_deactivate_cs); +} + +device_initcall(mpc832x_spi_init); + /* ************************************************************************ * * Setup the architecture @@ -49,8 +95,6 @@ static void __init mpc832x_rdb_setup_arc #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif #ifdef CONFIG_QUICC_ENGINE diff -puN arch/powerpc/platforms/83xx/mpc834x_itx.c~git-powerpc arch/powerpc/platforms/83xx/mpc834x_itx.c --- a/arch/powerpc/platforms/83xx/mpc834x_itx.c~git-powerpc +++ a/arch/powerpc/platforms/83xx/mpc834x_itx.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -55,8 +54,6 @@ static void __init mpc834x_itx_setup_arc #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif mpc834x_usb_cfg(); diff -puN arch/powerpc/platforms/83xx/mpc834x_mds.c~git-powerpc arch/powerpc/platforms/83xx/mpc834x_mds.c --- a/arch/powerpc/platforms/83xx/mpc834x_mds.c~git-powerpc +++ a/arch/powerpc/platforms/83xx/mpc834x_mds.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -86,8 +85,6 @@ static void __init mpc834x_mds_setup_arc #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif mpc834xemds_usb_cfg(); diff -puN arch/powerpc/platforms/83xx/mpc836x_mds.c~git-powerpc arch/powerpc/platforms/83xx/mpc836x_mds.c --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c~git-powerpc +++ a/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include #include @@ -82,7 +81,6 @@ static void __init mpc836x_mds_setup_arc #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); - ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif #ifdef CONFIG_QUICC_ENGINE diff -puN arch/powerpc/platforms/83xx/mpc83xx.h~git-powerpc arch/powerpc/platforms/83xx/mpc83xx.h --- a/arch/powerpc/platforms/83xx/mpc83xx.h~git-powerpc +++ a/arch/powerpc/platforms/83xx/mpc83xx.h @@ -49,8 +49,6 @@ */ extern int mpc83xx_add_bridge(struct device_node *dev); -extern int mpc83xx_exclude_device(struct pci_controller *hose, - u_char bus, u_char devfn); extern void mpc83xx_restart(char *cmd); extern long mpc83xx_time_init(void); extern int mpc834x_usb_cfg(void); diff -puN arch/powerpc/platforms/83xx/pci.c~git-powerpc arch/powerpc/platforms/83xx/pci.c --- a/arch/powerpc/platforms/83xx/pci.c~git-powerpc +++ a/arch/powerpc/platforms/83xx/pci.c @@ -33,13 +33,6 @@ #define DBG(x...) #endif -int mpc83xx_exclude_device(struct pci_controller *hose, u_char bus, u_char devfn) -{ - if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; - return PCIBIOS_SUCCESSFUL; -} - int __init mpc83xx_add_bridge(struct device_node *dev) { int len; diff -puN arch/powerpc/platforms/85xx/Kconfig~git-powerpc arch/powerpc/platforms/85xx/Kconfig --- a/arch/powerpc/platforms/85xx/Kconfig~git-powerpc +++ a/arch/powerpc/platforms/85xx/Kconfig @@ -29,13 +29,13 @@ config MPC85xx_MDS help This option enables support for the MPC85xx MDS board -config MPC8544_DS - bool "Freescale MPC8544 DS" +config MPC85xx_DS + bool "Freescale MPC85xx DS" select PPC_I8259 select DEFAULT_UIMAGE select FSL_ULI1575 help - This option enables support for the MPC8544 DS board + This option enables support for the MPC85xx DS (MPC8544 DS) board endchoice @@ -58,4 +58,4 @@ config MPC85xx select FSL_PCI if PCI select SERIAL_8250_SHARE_IRQ if SERIAL_8250 default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \ - || MPC85xx_MDS || MPC8544_DS + || MPC85xx_MDS || MPC85xx_DS diff -puN arch/powerpc/platforms/85xx/Makefile~git-powerpc arch/powerpc/platforms/85xx/Makefile --- a/arch/powerpc/platforms/85xx/Makefile~git-powerpc +++ a/arch/powerpc/platforms/85xx/Makefile @@ -5,5 +5,5 @@ obj-$(CONFIG_PPC_85xx) += misc.o obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o -obj-$(CONFIG_MPC8544_DS) += mpc8544_ds.o +obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o diff -puN arch/powerpc/platforms/85xx/mpc8544_ds.c~git-powerpc /dev/null --- a/arch/powerpc/platforms/85xx/mpc8544_ds.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * MPC8544 DS Board Setup - * - * Author Xianghua Xiao (x.xiao@freescale.com) - * Roy Zang - * - Add PCI/PCI Exprees support - * Copyright 2007 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "mpc85xx.h" - -#undef DEBUG - -#ifdef DEBUG -#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) -#else -#define DBG(fmt, args...) -#endif - -#ifdef CONFIG_PPC_I8259 -static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc) -{ - unsigned int cascade_irq = i8259_irq(); - - if (cascade_irq != NO_IRQ) { - generic_handle_irq(cascade_irq); - } - desc->chip->eoi(irq); -} -#endif /* CONFIG_PPC_I8259 */ - -void __init mpc8544_ds_pic_init(void) -{ - struct mpic *mpic; - struct resource r; - struct device_node *np = NULL; -#ifdef CONFIG_PPC_I8259 - struct device_node *cascade_node = NULL; - int cascade_irq; -#endif - - np = of_find_node_by_type(np, "open-pic"); - - if (np == NULL) { - printk(KERN_ERR "Could not find open-pic node\n"); - return; - } - - if (of_address_to_resource(np, 0, &r)) { - printk(KERN_ERR "Failed to map mpic register space\n"); - of_node_put(np); - return; - } - - mpic = mpic_alloc(np, r.start, - MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, - 0, 256, " OpenPIC "); - BUG_ON(mpic == NULL); - - mpic_init(mpic); - -#ifdef CONFIG_PPC_I8259 - /* Initialize the i8259 controller */ - for_each_node_by_type(np, "interrupt-controller") - if (of_device_is_compatible(np, "chrp,iic")) { - cascade_node = np; - break; - } - - if (cascade_node == NULL) { - printk(KERN_DEBUG "Could not find i8259 PIC\n"); - return; - } - - cascade_irq = irq_of_parse_and_map(cascade_node, 0); - if (cascade_irq == NO_IRQ) { - printk(KERN_ERR "Failed to map cascade interrupt\n"); - return; - } - - DBG("mpc8544ds: cascade mapped to irq %d\n", cascade_irq); - - i8259_init(cascade_node, 0); - of_node_put(cascade_node); - - set_irq_chained_handler(cascade_irq, mpc8544_8259_cascade); -#endif /* CONFIG_PPC_I8259 */ -} - -#ifdef CONFIG_PCI -extern int uses_fsl_uli_m1575; -extern int uli_exclude_device(struct pci_controller *hose, - u_char bus, u_char devfn); - -static int mpc85xx_exclude_device(struct pci_controller *hose, - u_char bus, u_char devfn) -{ - struct device_node* node; - struct resource rsrc; - - node = (struct device_node *)hose->arch_data; - of_address_to_resource(node, 0, &rsrc); - - if ((rsrc.start & 0xfffff) == 0xb000) { - return uli_exclude_device(hose, bus, devfn); - } - - return PCIBIOS_SUCCESSFUL; -} -#endif /* CONFIG_PCI */ - -/* - * Setup the architecture - */ -static void __init mpc8544_ds_setup_arch(void) -{ -#ifdef CONFIG_PCI - struct device_node *np; -#endif - - if (ppc_md.progress) - ppc_md.progress("mpc8544_ds_setup_arch()", 0); - -#ifdef CONFIG_PCI - for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { - struct resource rsrc; - of_address_to_resource(np, 0, &rsrc); - if ((rsrc.start & 0xfffff) == 0xb000) - fsl_add_bridge(np, 1); - else - fsl_add_bridge(np, 0); - } - uses_fsl_uli_m1575 = 1; - ppc_md.pci_exclude_device = mpc85xx_exclude_device; -#endif - - printk("MPC8544 DS board from Freescale Semiconductor\n"); -} - -/* - * Called very early, device-tree isn't unflattened - */ -static int __init mpc8544_ds_probe(void) -{ - unsigned long root = of_get_flat_dt_root(); - - return of_flat_dt_is_compatible(root, "MPC8544DS"); -} - -define_machine(mpc8544_ds) { - .name = "MPC8544 DS", - .probe = mpc8544_ds_probe, - .setup_arch = mpc8544_ds_setup_arch, - .init_IRQ = mpc8544_ds_pic_init, -#ifdef CONFIG_PCI - .pcibios_fixup_bus = fsl_pcibios_fixup_bus, -#endif - .get_irq = mpic_get_irq, - .restart = mpc85xx_restart, - .calibrate_decr = generic_calibrate_decr, - .progress = udbg_progress, -}; diff -puN arch/powerpc/platforms/85xx/mpc85xx_ads.c~git-powerpc arch/powerpc/platforms/85xx/mpc85xx_ads.c --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c~git-powerpc +++ a/arch/powerpc/platforms/85xx/mpc85xx_ads.c @@ -192,7 +192,6 @@ void init_fcc_ioports(struct fs_platform static void __init mpc85xx_ads_setup_arch(void) { - struct device_node *cpu; #ifdef CONFIG_PCI struct device_node *np; #endif @@ -200,18 +199,6 @@ static void __init mpc85xx_ads_setup_arc if (ppc_md.progress) ppc_md.progress("mpc85xx_ads_setup_arch()", 0); - cpu = of_find_node_by_type(NULL, "cpu"); - if (cpu != 0) { - const unsigned int *fp; - - fp = of_get_property(cpu, "clock-frequency", NULL); - if (fp != 0) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 50000000 / HZ; - of_node_put(cpu); - } - #ifdef CONFIG_CPM2 cpm2_reset(); #endif diff -puN arch/powerpc/platforms/85xx/mpc85xx_cds.c~git-powerpc arch/powerpc/platforms/85xx/mpc85xx_cds.c --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c~git-powerpc +++ a/arch/powerpc/platforms/85xx/mpc85xx_cds.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -266,7 +265,6 @@ device_initcall(mpc85xx_cds_8259_attach) */ static void __init mpc85xx_cds_setup_arch(void) { - struct device_node *cpu; #ifdef CONFIG_PCI struct device_node *np; #endif @@ -274,18 +272,6 @@ static void __init mpc85xx_cds_setup_arc if (ppc_md.progress) ppc_md.progress("mpc85xx_cds_setup_arch()", 0); - cpu = of_find_node_by_type(NULL, "cpu"); - if (cpu != 0) { - const unsigned int *fp; - - fp = of_get_property(cpu, "clock-frequency", NULL); - if (fp != 0) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 500000000 / HZ; - of_node_put(cpu); - } - cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE); cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1; diff -puN /dev/null arch/powerpc/platforms/85xx/mpc85xx_ds.c --- /dev/null +++ a/arch/powerpc/platforms/85xx/mpc85xx_ds.c @@ -0,0 +1,227 @@ +/* + * MPC85xx DS Board Setup + * + * Author Xianghua Xiao (x.xiao@freescale.com) + * Roy Zang + * - Add PCI/PCI Exprees support + * Copyright 2007 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "mpc85xx.h" + +#undef DEBUG + +#ifdef DEBUG +#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) +#else +#define DBG(fmt, args...) +#endif + +#ifdef CONFIG_PPC_I8259 +static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) +{ + unsigned int cascade_irq = i8259_irq(); + + if (cascade_irq != NO_IRQ) { + generic_handle_irq(cascade_irq); + } + desc->chip->eoi(irq); +} +#endif /* CONFIG_PPC_I8259 */ + +void __init mpc85xx_ds_pic_init(void) +{ + struct mpic *mpic; + struct resource r; + struct device_node *np = NULL; +#ifdef CONFIG_PPC_I8259 + struct device_node *cascade_node = NULL; + int cascade_irq; +#endif + + np = of_find_node_by_type(np, "open-pic"); + + if (np == NULL) { + printk(KERN_ERR "Could not find open-pic node\n"); + return; + } + + if (of_address_to_resource(np, 0, &r)) { + printk(KERN_ERR "Failed to map mpic register space\n"); + of_node_put(np); + return; + } + + mpic = mpic_alloc(np, r.start, + MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, + 0, 256, " OpenPIC "); + BUG_ON(mpic == NULL); + + mpic_init(mpic); + +#ifdef CONFIG_PPC_I8259 + /* Initialize the i8259 controller */ + for_each_node_by_type(np, "interrupt-controller") + if (of_device_is_compatible(np, "chrp,iic")) { + cascade_node = np; + break; + } + + if (cascade_node == NULL) { + printk(KERN_DEBUG "Could not find i8259 PIC\n"); + return; + } + + cascade_irq = irq_of_parse_and_map(cascade_node, 0); + if (cascade_irq == NO_IRQ) { + printk(KERN_ERR "Failed to map cascade interrupt\n"); + return; + } + + DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq); + + i8259_init(cascade_node, 0); + of_node_put(cascade_node); + + set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); +#endif /* CONFIG_PPC_I8259 */ +} + +#ifdef CONFIG_PCI +static int primary_phb_addr; +extern int uses_fsl_uli_m1575; +extern int uli_exclude_device(struct pci_controller *hose, + u_char bus, u_char devfn); + +static int mpc85xx_exclude_device(struct pci_controller *hose, + u_char bus, u_char devfn) +{ + struct device_node* node; + struct resource rsrc; + + node = (struct device_node *)hose->arch_data; + of_address_to_resource(node, 0, &rsrc); + + if ((rsrc.start & 0xfffff) == primary_phb_addr) { + return uli_exclude_device(hose, bus, devfn); + } + + return PCIBIOS_SUCCESSFUL; +} +#endif /* CONFIG_PCI */ + +/* + * Setup the architecture + */ +static void __init mpc85xx_ds_setup_arch(void) +{ +#ifdef CONFIG_PCI + struct device_node *np; +#endif + + if (ppc_md.progress) + ppc_md.progress("mpc85xx_ds_setup_arch()", 0); + +#ifdef CONFIG_PCI + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { + struct resource rsrc; + of_address_to_resource(np, 0, &rsrc); + if ((rsrc.start & 0xfffff) == primary_phb_addr) + fsl_add_bridge(np, 1); + else + fsl_add_bridge(np, 0); + } + uses_fsl_uli_m1575 = 1; + ppc_md.pci_exclude_device = mpc85xx_exclude_device; +#endif + + printk("MPC85xx DS board from Freescale Semiconductor\n"); +} + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init mpc8544_ds_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "MPC8544DS")) { +#ifdef CONFIG_PCI + primary_phb_addr = 0xb000; +#endif + return 1; + } else { + return 0; + } +} + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init mpc8572_ds_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) { +#ifdef CONFIG_PCI + primary_phb_addr = 0x8000; +#endif + return 1; + } else { + return 0; + } +} + +define_machine(mpc8544_ds) { + .name = "MPC8544 DS", + .probe = mpc8544_ds_probe, + .setup_arch = mpc85xx_ds_setup_arch, + .init_IRQ = mpc85xx_ds_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = mpc85xx_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; + +define_machine(mpc8572_ds) { + .name = "MPC8572 DS", + .probe = mpc8572_ds_probe, + .setup_arch = mpc85xx_ds_setup_arch, + .init_IRQ = mpc85xx_ds_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = mpc85xx_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; diff -puN arch/powerpc/platforms/85xx/mpc85xx_mds.c~git-powerpc arch/powerpc/platforms/85xx/mpc85xx_mds.c --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c~git-powerpc +++ a/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include #include @@ -73,17 +72,6 @@ static void __init mpc85xx_mds_setup_arc if (ppc_md.progress) ppc_md.progress("mpc85xx_mds_setup_arch()", 0); - np = of_find_node_by_type(NULL, "cpu"); - if (np != NULL) { - const unsigned int *fp = - of_get_property(np, "clock-frequency", NULL); - if (fp != NULL) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 50000000 / HZ; - of_node_put(np); - } - /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np != NULL) { diff -puN arch/powerpc/platforms/86xx/mpc86xx_hpcn.c~git-powerpc arch/powerpc/platforms/86xx/mpc86xx_hpcn.c --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c~git-powerpc +++ a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c @@ -132,23 +132,13 @@ static int mpc86xx_exclude_device(struct static void __init mpc86xx_hpcn_setup_arch(void) { +#ifdef CONFIG_PCI struct device_node *np; +#endif if (ppc_md.progress) ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0); - np = of_find_node_by_type(NULL, "cpu"); - if (np != 0) { - const unsigned int *fp; - - fp = of_get_property(np, "clock-frequency", NULL); - if (fp != 0) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 50000000 / HZ; - of_node_put(np); - } - #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { struct resource rsrc; diff -puN arch/powerpc/platforms/8xx/m8xx_setup.c~git-powerpc arch/powerpc/platforms/8xx/m8xx_setup.c --- a/arch/powerpc/platforms/8xx/m8xx_setup.c~git-powerpc +++ a/arch/powerpc/platforms/8xx/m8xx_setup.c @@ -36,13 +36,11 @@ #include #include -#include #include #include #include #include #include -#include #include #include #include @@ -55,7 +53,9 @@ struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops #endif void m8xx_calibrate_decr(void); +#ifdef CONFIG_8xx_WDT extern void m8xx_wdt_handler_install(bd_t *bp); +#endif extern int cpm_pic_init(void); extern int cpm_get_irq(void); @@ -89,24 +89,24 @@ init_internal_rtc(void) static int __init get_freq(char *name, unsigned long *val) { - struct device_node *cpu; - const unsigned int *fp; - int found = 0; - - /* The cpu node should have timebase and clock frequency properties */ - cpu = of_find_node_by_type(NULL, "cpu"); - - if (cpu) { - fp = of_get_property(cpu, name, NULL); - if (fp) { - found = 1; - *val = *fp; - } + struct device_node *cpu; + const unsigned int *fp; + int found = 0; + + /* The cpu node should have timebase and clock frequency properties */ + cpu = of_find_node_by_type(NULL, "cpu"); - of_node_put(cpu); - } + if (cpu) { + fp = of_get_property(cpu, name, NULL); + if (fp) { + found = 1; + *val = *fp; + } - return found; + of_node_put(cpu); + } + + return found; } /* The decrementer counts at the system (internal) clock frequency divided by @@ -122,7 +122,7 @@ void __init mpc8xx_calibrate_decr(void) sit8xx_t *sys_tmr2; int irq, virq; - clk_r1 = (cark8xx_t *) immr_map(im_clkrstk); + clk_r1 = (cark8xx_t *) immr_map(im_clkrstk); /* Unlock the SCCR. */ out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY); @@ -130,24 +130,24 @@ void __init mpc8xx_calibrate_decr(void) immr_unmap(clk_r1); /* Force all 8xx processors to use divide by 16 processor clock. */ - clk_r2 = (car8xx_t *) immr_map(im_clkrst); + clk_r2 = (car8xx_t *) immr_map(im_clkrst); setbits32(&clk_r2->car_sccr, 0x02000000); immr_unmap(clk_r2); /* Processor frequency is MHz. */ - ppc_tb_freq = 50000000; - if (!get_freq("bus-frequency", &ppc_tb_freq)) { - printk(KERN_ERR "WARNING: Estimating decrementer frequency " - "(not found)\n"); - } - ppc_tb_freq /= 16; - ppc_proc_freq = 50000000; - if (!get_freq("clock-frequency", &ppc_proc_freq)) - printk(KERN_ERR "WARNING: Estimating processor frequency" - "(not found)\n"); + ppc_tb_freq = 50000000; + if (!get_freq("bus-frequency", &ppc_tb_freq)) { + printk(KERN_ERR "WARNING: Estimating decrementer frequency " + "(not found)\n"); + } + ppc_tb_freq /= 16; + ppc_proc_freq = 50000000; + if (!get_freq("clock-frequency", &ppc_proc_freq)) + printk(KERN_ERR "WARNING: Estimating processor frequency" + "(not found)\n"); - printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); + printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); /* Perform some more timer/timebase initialization. This used * to be done elsewhere, but other changes caused it to get @@ -164,7 +164,7 @@ void __init mpc8xx_calibrate_decr(void) * we guarantee the registers are locked, then we unlock them * for our use. */ - sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); + sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY); out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY); out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY); @@ -180,8 +180,8 @@ void __init mpc8xx_calibrate_decr(void) * we have to enable the timebase). The decrementer interrupt * is wired into the vector table, nothing to do here for that. */ - cpu = of_find_node_by_type(NULL, "cpu"); - virq= irq_of_parse_and_map(cpu, 0); + cpu = of_find_node_by_type(NULL, "cpu"); + virq= irq_of_parse_and_map(cpu, 0); irq = irq_map[virq].hwirq; sys_tmr2 = (sit8xx_t *) immr_map(im_sit); @@ -211,10 +211,10 @@ int mpc8xx_set_rtc_time(struct rtc_time sit8xx_t *sys_tmr2; int time; - sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); + sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); sys_tmr2 = (sit8xx_t *) immr_map(im_sit); time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday, - tm->tm_hour, tm->tm_min, tm->tm_sec); + tm->tm_hour, tm->tm_min, tm->tm_sec); out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY); out_be32(&sys_tmr2->sit_rtc, time); @@ -233,8 +233,8 @@ void mpc8xx_get_rtc_time(struct rtc_time /* Get time from the RTC. */ data = in_be32(&sys_tmr->sit_rtc); to_tm(data, tm); - tm->tm_year -= 1900; - tm->tm_mon -= 1; + tm->tm_year -= 1900; + tm->tm_mon -= 1; immr_unmap(sys_tmr); return; } @@ -298,7 +298,7 @@ void __init m8xx_pic_init(void) int irq; if (mpc8xx_pic_init()) { - printk(KERN_ERR "Failed interrupt 8xx controller initialization\n"); + printk(KERN_ERR "Failed interrupt 8xx controller initialization\n"); return; } diff -puN arch/powerpc/platforms/8xx/mpc86xads.h~git-powerpc arch/powerpc/platforms/8xx/mpc86xads.h --- a/arch/powerpc/platforms/8xx/mpc86xads.h~git-powerpc +++ a/arch/powerpc/platforms/8xx/mpc86xads.h @@ -15,7 +15,6 @@ #ifndef __ASM_MPC86XADS_H__ #define __ASM_MPC86XADS_H__ -#include #include /* U-Boot maps BCSR to 0xff080000 */ diff -puN arch/powerpc/platforms/8xx/mpc86xads_setup.c~git-powerpc arch/powerpc/platforms/8xx/mpc86xads_setup.c --- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c~git-powerpc +++ a/arch/powerpc/platforms/8xx/mpc86xads_setup.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -254,20 +253,6 @@ int platform_device_skip(const char *mod static void __init mpc86xads_setup_arch(void) { - struct device_node *cpu; - - cpu = of_find_node_by_type(NULL, "cpu"); - if (cpu != 0) { - const unsigned int *fp; - - fp = of_get_property(cpu, "clock-frequency", NULL); - if (fp != 0) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 50000000 / HZ; - of_node_put(cpu); - } - cpm_reset(); mpc86xads_board_setup(); diff -puN arch/powerpc/platforms/8xx/mpc885ads.h~git-powerpc arch/powerpc/platforms/8xx/mpc885ads.h --- a/arch/powerpc/platforms/8xx/mpc885ads.h~git-powerpc +++ a/arch/powerpc/platforms/8xx/mpc885ads.h @@ -15,7 +15,6 @@ #ifndef __ASM_MPC885ADS_H__ #define __ASM_MPC885ADS_H__ -#include #include /* U-Boot maps BCSR to 0xff080000 */ diff -puN arch/powerpc/platforms/8xx/mpc885ads_setup.c~git-powerpc arch/powerpc/platforms/8xx/mpc885ads_setup.c --- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c~git-powerpc +++ a/arch/powerpc/platforms/8xx/mpc885ads_setup.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -406,20 +405,6 @@ int platform_device_skip(const char *mod static void __init mpc885ads_setup_arch(void) { - struct device_node *cpu; - - cpu = of_find_node_by_type(NULL, "cpu"); - if (cpu != 0) { - const unsigned int *fp; - - fp = of_get_property(cpu, "clock-frequency", NULL); - if (fp != 0) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 50000000 / HZ; - of_node_put(cpu); - } - cpm_reset(); mpc885ads_board_setup(); diff -puN arch/powerpc/platforms/Kconfig~git-powerpc arch/powerpc/platforms/Kconfig --- a/arch/powerpc/platforms/Kconfig~git-powerpc +++ a/arch/powerpc/platforms/Kconfig @@ -19,6 +19,7 @@ config EMBEDDED6xx config PPC_82xx bool "Freescale 82xx" depends on 6xx + select WANT_DEVICE_TREE config PPC_83xx bool "Freescale 83xx" @@ -58,7 +59,7 @@ source "arch/powerpc/platforms/85xx/Kcon source "arch/powerpc/platforms/86xx/Kconfig" source "arch/powerpc/platforms/embedded6xx/Kconfig" source "arch/powerpc/platforms/44x/Kconfig" -#source "arch/powerpc/platforms/4xx/Kconfig +source "arch/powerpc/platforms/40x/Kconfig" config PPC_NATIVE bool @@ -136,6 +137,16 @@ config MPIC_U3_HT_IRQS depends on PPC_MAPLE default y +config MPIC_BROKEN_REGREAD + bool + depends on MPIC + help + This option enables a MPIC driver workaround for some chips + that have a bug that causes some interrupt source information + to not read back properly. It is safe to use on other chips as + well, but enabling it uses about 8KB of memory to keep copies + of the register contents in software. + config IBMVIO depends on PPC_PSERIES || PPC_ISERIES bool diff -puN arch/powerpc/platforms/Kconfig.cputype~git-powerpc arch/powerpc/platforms/Kconfig.cputype --- a/arch/powerpc/platforms/Kconfig.cputype~git-powerpc +++ a/arch/powerpc/platforms/Kconfig.cputype @@ -36,10 +36,12 @@ config PPC_8xx bool "Freescale 8xx" select FSL_SOC select 8xx + select WANT_DEVICE_TREE config 40x bool "AMCC 40x" select PPC_DCR_NATIVE + select WANT_DEVICE_TREE config 44x bool "AMCC 44x" diff -puN arch/powerpc/platforms/Makefile~git-powerpc arch/powerpc/platforms/Makefile --- a/arch/powerpc/platforms/Makefile~git-powerpc +++ a/arch/powerpc/platforms/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_PPC_PMAC) += powermac/ endif endif obj-$(CONFIG_PPC_CHRP) += chrp/ -#obj-$(CONFIG_4xx) += 4xx/ +obj-$(CONFIG_40x) += 40x/ obj-$(CONFIG_44x) += 44x/ obj-$(CONFIG_PPC_MPC52xx) += 52xx/ obj-$(CONFIG_PPC_8xx) += 8xx/ diff -puN arch/powerpc/platforms/cell/Makefile~git-powerpc arch/powerpc/platforms/cell/Makefile --- a/arch/powerpc/platforms/cell/Makefile~git-powerpc +++ a/arch/powerpc/platforms/cell/Makefile @@ -13,15 +13,13 @@ obj-$(CONFIG_PPC_CELL_NATIVE) += smp.o endif # needed only when building loadable spufs.ko -spufs-modular-$(CONFIG_SPU_FS) += spu_syscalls.o spu-priv1-$(CONFIG_PPC_CELL_NATIVE) += spu_priv1_mmio.o spu-manage-$(CONFIG_PPC_CELLEB) += spu_manage.o spu-manage-$(CONFIG_PPC_CELL_NATIVE) += spu_manage.o obj-$(CONFIG_SPU_BASE) += spu_callbacks.o spu_base.o \ - spu_coredump.o \ - $(spufs-modular-m) \ + spu_syscalls.o \ $(spu-priv1-y) \ $(spu-manage-y) \ spufs/ diff -puN arch/powerpc/platforms/cell/axon_msi.c~git-powerpc arch/powerpc/platforms/cell/axon_msi.c --- a/arch/powerpc/platforms/cell/axon_msi.c~git-powerpc +++ a/arch/powerpc/platforms/cell/axon_msi.c @@ -64,7 +64,6 @@ struct axon_msic { - struct device_node *dn; struct irq_host *irq_host; __le32 *fifo; dcr_host_t dcr_host; @@ -295,15 +294,7 @@ static int msic_host_map(struct irq_host return 0; } -static int msic_host_match(struct irq_host *host, struct device_node *dn) -{ - struct axon_msic *msic = host->host_data; - - return msic->dn == dn; -} - static struct irq_host_ops msic_host_ops = { - .match = msic_host_match, .map = msic_host_map, }; @@ -314,7 +305,8 @@ static int axon_msi_notify_reboot(struct u32 tmp; list_for_each_entry(msic, &axon_msic_list, list) { - pr_debug("axon_msi: disabling %s\n", msic->dn->full_name); + pr_debug("axon_msi: disabling %s\n", + msic->irq_host->of_node->full_name); tmp = msic_dcr_read(msic, MSIC_CTRL_REG); tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; msic_dcr_write(msic, MSIC_CTRL_REG, tmp); @@ -370,8 +362,8 @@ static int axon_msi_setup_one(struct dev msic->fifo = page_address(page); - msic->irq_host = irq_alloc_host(IRQ_HOST_MAP_NOMAP, NR_IRQS, - &msic_host_ops, 0); + msic->irq_host = irq_alloc_host(of_node_get(dn), IRQ_HOST_MAP_NOMAP, + NR_IRQS, &msic_host_ops, 0); if (!msic->irq_host) { printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n", dn->full_name); @@ -387,8 +379,6 @@ static int axon_msi_setup_one(struct dev goto out_free_host; } - msic->dn = of_node_get(dn); - set_irq_data(virq, msic); set_irq_chained_handler(virq, axon_msi_cascade); pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq); diff -puN arch/powerpc/platforms/cell/interrupt.c~git-powerpc arch/powerpc/platforms/cell/interrupt.c --- a/arch/powerpc/platforms/cell/interrupt.c~git-powerpc +++ a/arch/powerpc/platforms/cell/interrupt.c @@ -381,7 +381,7 @@ static int __init setup_iic(void) void __init iic_init_IRQ(void) { /* Setup an irq host data structure */ - iic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT, + iic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT, &iic_host_ops, IIC_IRQ_INVALID); BUG_ON(iic_host == NULL); irq_set_default_host(iic_host); diff -puN arch/powerpc/platforms/cell/spider-pic.c~git-powerpc arch/powerpc/platforms/cell/spider-pic.c --- a/arch/powerpc/platforms/cell/spider-pic.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spider-pic.c @@ -63,7 +63,6 @@ enum { struct spider_pic { struct irq_host *host; - struct device_node *of_node; void __iomem *regs; unsigned int node_id; }; @@ -176,12 +175,6 @@ static struct irq_chip spider_pic = { .set_type = spider_set_irq_type, }; -static int spider_host_match(struct irq_host *h, struct device_node *node) -{ - struct spider_pic *pic = h->host_data; - return node == pic->of_node; -} - static int spider_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { @@ -208,7 +201,6 @@ static int spider_host_xlate(struct irq_ } static struct irq_host_ops spider_host_ops = { - .match = spider_host_match, .map = spider_host_map, .xlate = spider_host_xlate, }; @@ -247,18 +239,18 @@ static unsigned int __init spider_find_c * tree in case the device-tree is ever fixed */ struct of_irq oirq; - if (of_irq_map_one(pic->of_node, 0, &oirq) == 0) { + if (of_irq_map_one(pic->host->of_node, 0, &oirq) == 0) { virq = irq_create_of_mapping(oirq.controller, oirq.specifier, oirq.size); return virq; } /* Now do the horrible hacks */ - tmp = of_get_property(pic->of_node, "#interrupt-cells", NULL); + tmp = of_get_property(pic->host->of_node, "#interrupt-cells", NULL); if (tmp == NULL) return NO_IRQ; intsize = *tmp; - imap = of_get_property(pic->of_node, "interrupt-map", &imaplen); + imap = of_get_property(pic->host->of_node, "interrupt-map", &imaplen); if (imap == NULL || imaplen < (intsize + 1)) return NO_IRQ; iic = of_find_node_by_phandle(imap[intsize]); @@ -308,15 +300,13 @@ static void __init spider_init_one(struc panic("spider_pic: can't map registers !"); /* Allocate a host */ - pic->host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, SPIDER_SRC_COUNT, - &spider_host_ops, SPIDER_IRQ_INVALID); + pic->host = irq_alloc_host(of_node_get(of_node), IRQ_HOST_MAP_LINEAR, + SPIDER_SRC_COUNT, &spider_host_ops, + SPIDER_IRQ_INVALID); if (pic->host == NULL) panic("spider_pic: can't allocate irq host !"); pic->host->host_data = pic; - /* Fill out other bits */ - pic->of_node = of_node_get(of_node); - /* Go through all sources and disable them */ for (i = 0; i < SPIDER_SRC_COUNT; i++) { void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i; diff -puN arch/powerpc/platforms/cell/spu_base.c~git-powerpc arch/powerpc/platforms/cell/spu_base.c --- a/arch/powerpc/platforms/cell/spu_base.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spu_base.c @@ -458,7 +458,7 @@ static int spu_shutdown(struct sys_devic return 0; } -struct sysdev_class spu_sysdev_class = { +static struct sysdev_class spu_sysdev_class = { set_kset_name("spu"), .shutdown = spu_shutdown, }; diff -puN arch/powerpc/platforms/cell/spu_callbacks.c~git-powerpc arch/powerpc/platforms/cell/spu_callbacks.c --- a/arch/powerpc/platforms/cell/spu_callbacks.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spu_callbacks.c @@ -2,7 +2,7 @@ * System call callback functions for SPUs */ -#define DEBUG +#undef DEBUG #include #include @@ -33,7 +33,7 @@ * mbind, mq_open, ipc, ... */ -void *spu_syscall_table[] = { +static void *spu_syscall_table[] = { #define SYSCALL(func) sys_ni_syscall, #define COMPAT_SYS(func) sys_ni_syscall, #define PPC_SYS(func) sys_ni_syscall, diff -puN arch/powerpc/platforms/cell/spu_coredump.c~git-powerpc /dev/null --- a/arch/powerpc/platforms/cell/spu_coredump.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * SPU core dump code - * - * (C) Copyright 2006 IBM Corp. - * - * Author: Dwayne Grant McConnell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include - -#include - -static struct spu_coredump_calls *spu_coredump_calls; -static DEFINE_MUTEX(spu_coredump_mutex); - -int arch_notes_size(void) -{ - long ret; - - ret = -ENOSYS; - mutex_lock(&spu_coredump_mutex); - if (spu_coredump_calls && try_module_get(spu_coredump_calls->owner)) { - ret = spu_coredump_calls->arch_notes_size(); - module_put(spu_coredump_calls->owner); - } - mutex_unlock(&spu_coredump_mutex); - return ret; -} - -void arch_write_notes(struct file *file) -{ - mutex_lock(&spu_coredump_mutex); - if (spu_coredump_calls && try_module_get(spu_coredump_calls->owner)) { - spu_coredump_calls->arch_write_notes(file); - module_put(spu_coredump_calls->owner); - } - mutex_unlock(&spu_coredump_mutex); -} - -int register_arch_coredump_calls(struct spu_coredump_calls *calls) -{ - int ret = 0; - - - mutex_lock(&spu_coredump_mutex); - if (spu_coredump_calls) - ret = -EBUSY; - else - spu_coredump_calls = calls; - mutex_unlock(&spu_coredump_mutex); - return ret; -} -EXPORT_SYMBOL_GPL(register_arch_coredump_calls); - -void unregister_arch_coredump_calls(struct spu_coredump_calls *calls) -{ - BUG_ON(spu_coredump_calls != calls); - - mutex_lock(&spu_coredump_mutex); - spu_coredump_calls = NULL; - mutex_unlock(&spu_coredump_mutex); -} -EXPORT_SYMBOL_GPL(unregister_arch_coredump_calls); diff -puN arch/powerpc/platforms/cell/spu_syscalls.c~git-powerpc arch/powerpc/platforms/cell/spu_syscalls.c --- a/arch/powerpc/platforms/cell/spu_syscalls.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spu_syscalls.c @@ -2,6 +2,7 @@ * SPU file system -- system call stubs * * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 + * (C) Copyright 2006-2007, IBM Corporation * * Author: Arnd Bergmann * @@ -20,44 +21,73 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include +#include #include #include +#include #include -struct spufs_calls spufs_calls = { - .owner = NULL, -}; - -/* These stub syscalls are needed to have the actual implementation - * within a loadable module. When spufs is built into the kernel, - * this file is not used and the syscalls directly enter the fs code */ +/* protected by rcu */ +static struct spufs_calls *spufs_calls; + +#ifdef CONFIG_SPU_FS_MODULE + +static inline struct spufs_calls *spufs_calls_get(void) +{ + struct spufs_calls *calls = NULL; + + rcu_read_lock(); + calls = rcu_dereference(spufs_calls); + if (calls && !try_module_get(calls->owner)) + calls = NULL; + rcu_read_unlock(); + + return calls; +} + +static inline void spufs_calls_put(struct spufs_calls *calls) +{ + BUG_ON(calls != spufs_calls); + + /* we don't need to rcu this, as we hold a reference to the module */ + module_put(spufs_calls->owner); +} + +#else /* !defined CONFIG_SPU_FS_MODULE */ + +static inline struct spufs_calls *spufs_calls_get(void) +{ + return spufs_calls; +} + +static inline void spufs_calls_put(struct spufs_calls *calls) { } + +#endif /* CONFIG_SPU_FS_MODULE */ asmlinkage long sys_spu_create(const char __user *name, unsigned int flags, mode_t mode, int neighbor_fd) { long ret; - struct module *owner = spufs_calls.owner; struct file *neighbor; int fput_needed; + struct spufs_calls *calls; - ret = -ENOSYS; - if (owner && try_module_get(owner)) { - if (flags & SPU_CREATE_AFFINITY_SPU) { - neighbor = fget_light(neighbor_fd, &fput_needed); - ret = -EBADF; - if (neighbor) { - ret = spufs_calls.create_thread(name, flags, - mode, neighbor); - fput_light(neighbor, fput_needed); - } - } - else { - ret = spufs_calls.create_thread(name, flags, - mode, NULL); + calls = spufs_calls_get(); + if (!calls) + return -ENOSYS; + + if (flags & SPU_CREATE_AFFINITY_SPU) { + ret = -EBADF; + neighbor = fget_light(neighbor_fd, &fput_needed); + if (neighbor) { + ret = calls->create_thread(name, flags, mode, neighbor); + fput_light(neighbor, fput_needed); } - module_put(owner); - } + } else + ret = calls->create_thread(name, flags, mode, NULL); + + spufs_calls_put(calls); return ret; } @@ -66,37 +96,69 @@ asmlinkage long sys_spu_run(int fd, __u3 long ret; struct file *filp; int fput_needed; - struct module *owner = spufs_calls.owner; + struct spufs_calls *calls; - ret = -ENOSYS; - if (owner && try_module_get(owner)) { - ret = -EBADF; - filp = fget_light(fd, &fput_needed); - if (filp) { - ret = spufs_calls.spu_run(filp, unpc, ustatus); - fput_light(filp, fput_needed); - } - module_put(owner); + calls = spufs_calls_get(); + if (!calls) + return -ENOSYS; + + ret = -EBADF; + filp = fget_light(fd, &fput_needed); + if (filp) { + ret = calls->spu_run(filp, unpc, ustatus); + fput_light(filp, fput_needed); } + + spufs_calls_put(calls); + return ret; +} + +int elf_coredump_extra_notes_size(void) +{ + struct spufs_calls *calls; + int ret; + + calls = spufs_calls_get(); + if (!calls) + return 0; + + ret = calls->coredump_extra_notes_size(); + + spufs_calls_put(calls); + + return ret; +} + +int elf_coredump_extra_notes_write(struct file *file, loff_t *foffset) +{ + struct spufs_calls *calls; + int ret; + + calls = spufs_calls_get(); + if (!calls) + return 0; + + ret = calls->coredump_extra_notes_write(file, foffset); + + spufs_calls_put(calls); + return ret; } int register_spu_syscalls(struct spufs_calls *calls) { - if (spufs_calls.owner) + if (spufs_calls) return -EBUSY; - spufs_calls.create_thread = calls->create_thread; - spufs_calls.spu_run = calls->spu_run; - smp_mb(); - spufs_calls.owner = calls->owner; + rcu_assign_pointer(spufs_calls, calls); return 0; } EXPORT_SYMBOL_GPL(register_spu_syscalls); void unregister_spu_syscalls(struct spufs_calls *calls) { - BUG_ON(spufs_calls.owner != calls->owner); - spufs_calls.owner = NULL; + BUG_ON(spufs_calls->owner != calls->owner); + rcu_assign_pointer(spufs_calls, NULL); + synchronize_rcu(); } EXPORT_SYMBOL_GPL(unregister_spu_syscalls); diff -puN arch/powerpc/platforms/cell/spufs/coredump.c~git-powerpc arch/powerpc/platforms/cell/spufs/coredump.c --- a/arch/powerpc/platforms/cell/spufs/coredump.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/coredump.c @@ -31,16 +31,7 @@ #include "spufs.h" -struct spufs_ctx_info { - struct list_head list; - int dfd; - int memsize; /* in bytes */ - struct spu_context *ctx; -}; - -static LIST_HEAD(ctx_info_list); - -static ssize_t do_coredump_read(int num, struct spu_context *ctx, void __user *buffer, +static ssize_t do_coredump_read(int num, struct spu_context *ctx, void *buffer, size_t size, loff_t *off) { u64 data; @@ -50,49 +41,57 @@ static ssize_t do_coredump_read(int num, return spufs_coredump_read[num].read(ctx, buffer, size, off); data = spufs_coredump_read[num].get(ctx); - ret = copy_to_user(buffer, &data, 8); - return ret ? -EFAULT : 8; + ret = snprintf(buffer, size, "0x%.16lx", data); + if (ret >= size) + return size; + return ++ret; /* count trailing NULL */ } /* * These are the only things you should do on a core-file: use only these * functions to write out all the necessary info. */ -static int spufs_dump_write(struct file *file, const void *addr, int nr) +static int spufs_dump_write(struct file *file, const void *addr, int nr, loff_t *foffset) { - return file->f_op->write(file, addr, nr, &file->f_pos) == nr; -} + unsigned long limit = current->signal->rlim[RLIMIT_CORE].rlim_cur; + ssize_t written; -static int spufs_dump_seek(struct file *file, loff_t off) -{ - if (file->f_op->llseek) { - if (file->f_op->llseek(file, off, 0) != off) - return 0; - } else - file->f_pos = off; - return 1; + if (*foffset + nr > limit) + return -EIO; + + written = file->f_op->write(file, addr, nr, &file->f_pos); + *foffset += written; + + if (written != nr) + return -EIO; + + return 0; } -static void spufs_fill_memsize(struct spufs_ctx_info *ctx_info) +static int spufs_dump_align(struct file *file, char *buf, loff_t new_off, + loff_t *foffset) { - struct spu_context *ctx; - unsigned long long lslr; + int rc, size; - ctx = ctx_info->ctx; - lslr = ctx->csa.priv2.spu_lslr_RW; - ctx_info->memsize = lslr + 1; + size = min((loff_t)PAGE_SIZE, new_off - *foffset); + memset(buf, 0, size); + + rc = 0; + while (rc == 0 && new_off > *foffset) { + size = min((loff_t)PAGE_SIZE, new_off - *foffset); + rc = spufs_dump_write(file, buf, size, foffset); + } + + return rc; } -static int spufs_ctx_note_size(struct spufs_ctx_info *ctx_info) +static int spufs_ctx_note_size(struct spu_context *ctx, int dfd) { - int dfd, memsize, i, sz, total = 0; + int i, sz, total = 0; char *name; char fullname[80]; - dfd = ctx_info->dfd; - memsize = ctx_info->memsize; - - for (i = 0; spufs_coredump_read[i].name; i++) { + for (i = 0; spufs_coredump_read[i].name != NULL; i++) { name = spufs_coredump_read[i].name; sz = spufs_coredump_read[i].size; @@ -100,39 +99,12 @@ static int spufs_ctx_note_size(struct sp total += sizeof(struct elf_note); total += roundup(strlen(fullname) + 1, 4); - if (!strcmp(name, "mem")) - total += roundup(memsize, 4); - else - total += roundup(sz, 4); + total += roundup(sz, 4); } return total; } -static int spufs_add_one_context(struct file *file, int dfd) -{ - struct spu_context *ctx; - struct spufs_ctx_info *ctx_info; - int size; - - ctx = SPUFS_I(file->f_dentry->d_inode)->i_ctx; - if (ctx->flags & SPU_CREATE_NOSCHED) - return 0; - - ctx_info = kzalloc(sizeof(*ctx_info), GFP_KERNEL); - if (unlikely(!ctx_info)) - return -ENOMEM; - - ctx_info->dfd = dfd; - ctx_info->ctx = ctx; - - spufs_fill_memsize(ctx_info); - - size = spufs_ctx_note_size(ctx_info); - list_add(&ctx_info->list, &ctx_info_list); - return size; -} - /* * The additional architecture-specific notes for Cell are various * context files in the spu context. @@ -142,33 +114,57 @@ static int spufs_add_one_context(struct * internal functionality to dump them without needing to actually * open the files. */ -static int spufs_arch_notes_size(void) +static struct spu_context *coredump_next_context(int *fd) { struct fdtable *fdt = files_fdtable(current->files); - int size = 0, fd; + struct file *file; + struct spu_context *ctx = NULL; - for (fd = 0; fd < fdt->max_fds; fd++) { - if (FD_ISSET(fd, fdt->open_fds)) { - struct file *file = fcheck(fd); - - if (file && file->f_op == &spufs_context_fops) { - int rval = spufs_add_one_context(file, fd); - if (rval < 0) - break; - size += rval; - } - } + for (; *fd < fdt->max_fds; (*fd)++) { + if (!FD_ISSET(*fd, fdt->open_fds)) + continue; + + file = fcheck(*fd); + + if (!file || file->f_op != &spufs_context_fops) + continue; + + ctx = SPUFS_I(file->f_dentry->d_inode)->i_ctx; + if (ctx->flags & SPU_CREATE_NOSCHED) + continue; + + /* start searching the next fd next time we're called */ + (*fd)++; + break; } - return size; + return ctx; } -static void spufs_arch_write_note(struct spufs_ctx_info *ctx_info, int i, - struct file *file) +int spufs_coredump_extra_notes_size(void) { struct spu_context *ctx; + int size = 0, rc, fd; + + fd = 0; + while ((ctx = coredump_next_context(&fd)) != NULL) { + spu_acquire_saved(ctx); + rc = spufs_ctx_note_size(ctx, fd); + spu_release_saved(ctx); + if (rc < 0) + break; + + size += rc; + } + + return size; +} + +static int spufs_arch_write_note(struct spu_context *ctx, int i, + struct file *file, int dfd, loff_t *foffset) +{ loff_t pos = 0; - int sz, dfd, rc, total = 0; + int sz, rc, nread, total = 0; const int bufsz = PAGE_SIZE; char *name; char fullname[80], *buf; @@ -176,64 +172,70 @@ static void spufs_arch_write_note(struct buf = (void *)get_zeroed_page(GFP_KERNEL); if (!buf) - return; + return -ENOMEM; - dfd = ctx_info->dfd; name = spufs_coredump_read[i].name; - - if (!strcmp(name, "mem")) - sz = ctx_info->memsize; - else - sz = spufs_coredump_read[i].size; - - ctx = ctx_info->ctx; - if (!ctx) - goto out; + sz = spufs_coredump_read[i].size; sprintf(fullname, "SPU/%d/%s", dfd, name); en.n_namesz = strlen(fullname) + 1; en.n_descsz = sz; en.n_type = NT_SPU; - if (!spufs_dump_write(file, &en, sizeof(en))) + rc = spufs_dump_write(file, &en, sizeof(en), foffset); + if (rc) goto out; - if (!spufs_dump_write(file, fullname, en.n_namesz)) + + rc = spufs_dump_write(file, fullname, en.n_namesz, foffset); + if (rc) goto out; - if (!spufs_dump_seek(file, roundup((unsigned long)file->f_pos, 4))) + + rc = spufs_dump_align(file, buf, roundup(*foffset, 4), foffset); + if (rc) goto out; do { - rc = do_coredump_read(i, ctx, buf, bufsz, &pos); - if (rc > 0) { - if (!spufs_dump_write(file, buf, rc)) + nread = do_coredump_read(i, ctx, buf, bufsz, &pos); + if (nread > 0) { + rc = spufs_dump_write(file, buf, nread, foffset); + if (rc) goto out; - total += rc; + total += nread; } - } while (rc == bufsz && total < sz); + } while (nread == bufsz && total < sz); + + if (nread < 0) { + rc = nread; + goto out; + } + + rc = spufs_dump_align(file, buf, roundup(*foffset - total + sz, 4), + foffset); - spufs_dump_seek(file, roundup((unsigned long)file->f_pos - - total + sz, 4)); out: free_page((unsigned long)buf); + return rc; } -static void spufs_arch_write_notes(struct file *file) +int spufs_coredump_extra_notes_write(struct file *file, loff_t *foffset) { - int j; - struct spufs_ctx_info *ctx_info, *next; + struct spu_context *ctx; + int fd, j, rc; - list_for_each_entry_safe(ctx_info, next, &ctx_info_list, list) { - spu_acquire_saved(ctx_info->ctx); - for (j = 0; j < spufs_coredump_num_notes; j++) - spufs_arch_write_note(ctx_info, j, file); - spu_release_saved(ctx_info->ctx); - list_del(&ctx_info->list); - kfree(ctx_info); + fd = 0; + while ((ctx = coredump_next_context(&fd)) != NULL) { + spu_acquire_saved(ctx); + + for (j = 0; spufs_coredump_read[j].name != NULL; j++) { + rc = spufs_arch_write_note(ctx, j, file, fd, foffset); + if (rc) { + spu_release_saved(ctx); + return rc; + } + } + + spu_release_saved(ctx); } -} -struct spu_coredump_calls spufs_coredump_calls = { - .arch_notes_size = spufs_arch_notes_size, - .arch_write_notes = spufs_arch_write_notes, - .owner = THIS_MODULE, -}; + return 0; +} diff -puN arch/powerpc/platforms/cell/spufs/file.c~git-powerpc arch/powerpc/platforms/cell/spufs/file.c --- a/arch/powerpc/platforms/cell/spufs/file.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/file.c @@ -199,9 +199,9 @@ static int spufs_mem_mmap(struct file *f } #ifdef CONFIG_SPU_FS_64K_LS -unsigned long spufs_get_unmapped_area(struct file *file, unsigned long addr, - unsigned long len, unsigned long pgoff, - unsigned long flags) +static unsigned long spufs_get_unmapped_area(struct file *file, + unsigned long addr, unsigned long len, unsigned long pgoff, + unsigned long flags) { struct spu_context *ctx = file->private_data; struct spu_state *csa = &ctx->csa; @@ -1076,6 +1076,36 @@ static const struct file_operations spuf .mmap = spufs_signal2_mmap, }; +/* + * This is a wrapper around DEFINE_SIMPLE_ATTRIBUTE which does the + * work of acquiring (or not) the SPU context before calling through + * to the actual get routine. The set routine is called directly. + */ +#define SPU_ATTR_NOACQUIRE 0 +#define SPU_ATTR_ACQUIRE 1 +#define SPU_ATTR_ACQUIRE_SAVED 2 + +#define DEFINE_SPUFS_ATTRIBUTE(__name, __get, __set, __fmt, __acquire) \ +static u64 __##__get(void *data) \ +{ \ + struct spu_context *ctx = data; \ + u64 ret; \ + \ + if (__acquire == SPU_ATTR_ACQUIRE) { \ + spu_acquire(ctx); \ + ret = __get(ctx); \ + spu_release(ctx); \ + } else if (__acquire == SPU_ATTR_ACQUIRE_SAVED) { \ + spu_acquire_saved(ctx); \ + ret = __get(ctx); \ + spu_release_saved(ctx); \ + } else \ + ret = __get(ctx); \ + \ + return ret; \ +} \ +DEFINE_SIMPLE_ATTRIBUTE(__name, __##__get, __set, __fmt); + static void spufs_signal1_type_set(void *data, u64 val) { struct spu_context *ctx = data; @@ -1085,25 +1115,13 @@ static void spufs_signal1_type_set(void spu_release(ctx); } -static u64 __spufs_signal1_type_get(void *data) +static u64 spufs_signal1_type_get(struct spu_context *ctx) { - struct spu_context *ctx = data; return ctx->ops->signal1_type_get(ctx); } +DEFINE_SPUFS_ATTRIBUTE(spufs_signal1_type, spufs_signal1_type_get, + spufs_signal1_type_set, "%llu", SPU_ATTR_ACQUIRE); -static u64 spufs_signal1_type_get(void *data) -{ - struct spu_context *ctx = data; - u64 ret; - - spu_acquire(ctx); - ret = __spufs_signal1_type_get(data); - spu_release(ctx); - - return ret; -} -DEFINE_SIMPLE_ATTRIBUTE(spufs_signal1_type, spufs_signal1_type_get, - spufs_signal1_type_set, "%llu"); static void spufs_signal2_type_set(void *data, u64 val) { @@ -1114,25 +1132,12 @@ static void spufs_signal2_type_set(void spu_release(ctx); } -static u64 __spufs_signal2_type_get(void *data) +static u64 spufs_signal2_type_get(struct spu_context *ctx) { - struct spu_context *ctx = data; return ctx->ops->signal2_type_get(ctx); } - -static u64 spufs_signal2_type_get(void *data) -{ - struct spu_context *ctx = data; - u64 ret; - - spu_acquire(ctx); - ret = __spufs_signal2_type_get(data); - spu_release(ctx); - - return ret; -} -DEFINE_SIMPLE_ATTRIBUTE(spufs_signal2_type, spufs_signal2_type_get, - spufs_signal2_type_set, "%llu"); +DEFINE_SPUFS_ATTRIBUTE(spufs_signal2_type, spufs_signal2_type_get, + spufs_signal2_type_set, "%llu", SPU_ATTR_ACQUIRE); #if SPUFS_MMAP_4K static unsigned long spufs_mss_mmap_nopfn(struct vm_area_struct *vma, @@ -1608,17 +1613,12 @@ static void spufs_npc_set(void *data, u6 spu_release(ctx); } -static u64 spufs_npc_get(void *data) +static u64 spufs_npc_get(struct spu_context *ctx) { - struct spu_context *ctx = data; - u64 ret; - spu_acquire(ctx); - ret = ctx->ops->npc_read(ctx); - spu_release(ctx); - return ret; + return ctx->ops->npc_read(ctx); } -DEFINE_SIMPLE_ATTRIBUTE(spufs_npc_ops, spufs_npc_get, spufs_npc_set, - "0x%llx\n") +DEFINE_SPUFS_ATTRIBUTE(spufs_npc_ops, spufs_npc_get, spufs_npc_set, + "0x%llx\n", SPU_ATTR_ACQUIRE); static void spufs_decr_set(void *data, u64 val) { @@ -1629,24 +1629,13 @@ static void spufs_decr_set(void *data, u spu_release_saved(ctx); } -static u64 __spufs_decr_get(void *data) +static u64 spufs_decr_get(struct spu_context *ctx) { - struct spu_context *ctx = data; struct spu_lscsa *lscsa = ctx->csa.lscsa; return lscsa->decr.slot[0]; } - -static u64 spufs_decr_get(void *data) -{ - struct spu_context *ctx = data; - u64 ret; - spu_acquire_saved(ctx); - ret = __spufs_decr_get(data); - spu_release_saved(ctx); - return ret; -} -DEFINE_SIMPLE_ATTRIBUTE(spufs_decr_ops, spufs_decr_get, spufs_decr_set, - "0x%llx\n") +DEFINE_SPUFS_ATTRIBUTE(spufs_decr_ops, spufs_decr_get, spufs_decr_set, + "0x%llx\n", SPU_ATTR_ACQUIRE_SAVED); static void spufs_decr_status_set(void *data, u64 val) { @@ -1659,26 +1648,16 @@ static void spufs_decr_status_set(void * spu_release_saved(ctx); } -static u64 __spufs_decr_status_get(void *data) +static u64 spufs_decr_status_get(struct spu_context *ctx) { - struct spu_context *ctx = data; if (ctx->csa.priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) return SPU_DECR_STATUS_RUNNING; else return 0; } - -static u64 spufs_decr_status_get(void *data) -{ - struct spu_context *ctx = data; - u64 ret; - spu_acquire_saved(ctx); - ret = __spufs_decr_status_get(data); - spu_release_saved(ctx); - return ret; -} -DEFINE_SIMPLE_ATTRIBUTE(spufs_decr_status_ops, spufs_decr_status_get, - spufs_decr_status_set, "0x%llx\n") +DEFINE_SPUFS_ATTRIBUTE(spufs_decr_status_ops, spufs_decr_status_get, + spufs_decr_status_set, "0x%llx\n", + SPU_ATTR_ACQUIRE_SAVED); static void spufs_event_mask_set(void *data, u64 val) { @@ -1689,28 +1668,18 @@ static void spufs_event_mask_set(void *d spu_release_saved(ctx); } -static u64 __spufs_event_mask_get(void *data) +static u64 spufs_event_mask_get(struct spu_context *ctx) { - struct spu_context *ctx = data; struct spu_lscsa *lscsa = ctx->csa.lscsa; return lscsa->event_mask.slot[0]; } -static u64 spufs_event_mask_get(void *data) -{ - struct spu_context *ctx = data; - u64 ret; - spu_acquire_saved(ctx); - ret = __spufs_event_mask_get(data); - spu_release_saved(ctx); - return ret; -} -DEFINE_SIMPLE_ATTRIBUTE(spufs_event_mask_ops, spufs_event_mask_get, - spufs_event_mask_set, "0x%llx\n") +DEFINE_SPUFS_ATTRIBUTE(spufs_event_mask_ops, spufs_event_mask_get, + spufs_event_mask_set, "0x%llx\n", + SPU_ATTR_ACQUIRE_SAVED); -static u64 __spufs_event_status_get(void *data) +static u64 spufs_event_status_get(struct spu_context *ctx) { - struct spu_context *ctx = data; struct spu_state *state = &ctx->csa; u64 stat; stat = state->spu_chnlcnt_RW[0]; @@ -1718,19 +1687,8 @@ static u64 __spufs_event_status_get(void return state->spu_chnldata_RW[0]; return 0; } - -static u64 spufs_event_status_get(void *data) -{ - struct spu_context *ctx = data; - u64 ret = 0; - - spu_acquire_saved(ctx); - ret = __spufs_event_status_get(data); - spu_release_saved(ctx); - return ret; -} -DEFINE_SIMPLE_ATTRIBUTE(spufs_event_status_ops, spufs_event_status_get, - NULL, "0x%llx\n") +DEFINE_SPUFS_ATTRIBUTE(spufs_event_status_ops, spufs_event_status_get, + NULL, "0x%llx\n", SPU_ATTR_ACQUIRE_SAVED) static void spufs_srr0_set(void *data, u64 val) { @@ -1741,45 +1699,32 @@ static void spufs_srr0_set(void *data, u spu_release_saved(ctx); } -static u64 spufs_srr0_get(void *data) +static u64 spufs_srr0_get(struct spu_context *ctx) { - struct spu_context *ctx = data; struct spu_lscsa *lscsa = ctx->csa.lscsa; - u64 ret; - spu_acquire_saved(ctx); - ret = lscsa->srr0.slot[0]; - spu_release_saved(ctx); - return ret; + return lscsa->srr0.slot[0]; } -DEFINE_SIMPLE_ATTRIBUTE(spufs_srr0_ops, spufs_srr0_get, spufs_srr0_set, - "0x%llx\n") +DEFINE_SPUFS_ATTRIBUTE(spufs_srr0_ops, spufs_srr0_get, spufs_srr0_set, + "0x%llx\n", SPU_ATTR_ACQUIRE_SAVED) -static u64 spufs_id_get(void *data) +static u64 spufs_id_get(struct spu_context *ctx) { - struct spu_context *ctx = data; u64 num; - spu_acquire(ctx); if (ctx->state == SPU_STATE_RUNNABLE) num = ctx->spu->number; else num = (unsigned int)-1; - spu_release(ctx); return num; } -DEFINE_SIMPLE_ATTRIBUTE(spufs_id_ops, spufs_id_get, NULL, "0x%llx\n") - -static u64 __spufs_object_id_get(void *data) -{ - struct spu_context *ctx = data; - return ctx->object_id; -} +DEFINE_SPUFS_ATTRIBUTE(spufs_id_ops, spufs_id_get, NULL, "0x%llx\n", + SPU_ATTR_ACQUIRE) -static u64 spufs_object_id_get(void *data) +static u64 spufs_object_id_get(struct spu_context *ctx) { /* FIXME: Should there really be no locking here? */ - return __spufs_object_id_get(data); + return ctx->object_id; } static void spufs_object_id_set(void *data, u64 id) @@ -1788,27 +1733,15 @@ static void spufs_object_id_set(void *da ctx->object_id = id; } -DEFINE_SIMPLE_ATTRIBUTE(spufs_object_id_ops, spufs_object_id_get, - spufs_object_id_set, "0x%llx\n"); +DEFINE_SPUFS_ATTRIBUTE(spufs_object_id_ops, spufs_object_id_get, + spufs_object_id_set, "0x%llx\n", SPU_ATTR_NOACQUIRE); -static u64 __spufs_lslr_get(void *data) +static u64 spufs_lslr_get(struct spu_context *ctx) { - struct spu_context *ctx = data; return ctx->csa.priv2.spu_lslr_RW; } - -static u64 spufs_lslr_get(void *data) -{ - struct spu_context *ctx = data; - u64 ret; - - spu_acquire_saved(ctx); - ret = __spufs_lslr_get(data); - spu_release_saved(ctx); - - return ret; -} -DEFINE_SIMPLE_ATTRIBUTE(spufs_lslr_ops, spufs_lslr_get, NULL, "0x%llx\n") +DEFINE_SPUFS_ATTRIBUTE(spufs_lslr_ops, spufs_lslr_get, NULL, "0x%llx\n", + SPU_ATTR_ACQUIRE_SAVED); static int spufs_info_open(struct inode *inode, struct file *file) { @@ -2231,25 +2164,25 @@ struct tree_descr spufs_dir_nosched_cont }; struct spufs_coredump_reader spufs_coredump_read[] = { - { "regs", __spufs_regs_read, NULL, 128 * 16 }, - { "fpcr", __spufs_fpcr_read, NULL, 16 }, - { "lslr", NULL, __spufs_lslr_get, 11 }, - { "decr", NULL, __spufs_decr_get, 11 }, - { "decr_status", NULL, __spufs_decr_status_get, 11 }, - { "mem", __spufs_mem_read, NULL, 256 * 1024, }, - { "signal1", __spufs_signal1_read, NULL, 4 }, - { "signal1_type", NULL, __spufs_signal1_type_get, 2 }, - { "signal2", __spufs_signal2_read, NULL, 4 }, - { "signal2_type", NULL, __spufs_signal2_type_get, 2 }, - { "event_mask", NULL, __spufs_event_mask_get, 8 }, - { "event_status", NULL, __spufs_event_status_get, 8 }, - { "mbox_info", __spufs_mbox_info_read, NULL, 4 }, - { "ibox_info", __spufs_ibox_info_read, NULL, 4 }, - { "wbox_info", __spufs_wbox_info_read, NULL, 16 }, - { "dma_info", __spufs_dma_info_read, NULL, 69 * 8 }, - { "proxydma_info", __spufs_proxydma_info_read, NULL, 35 * 8 }, - { "object-id", NULL, __spufs_object_id_get, 19 }, - { }, + { "regs", __spufs_regs_read, NULL, sizeof(struct spu_reg128[128])}, + { "fpcr", __spufs_fpcr_read, NULL, sizeof(struct spu_reg128) }, + { "lslr", NULL, spufs_lslr_get, 19 }, + { "decr", NULL, spufs_decr_get, 19 }, + { "decr_status", NULL, spufs_decr_status_get, 19 }, + { "mem", __spufs_mem_read, NULL, LS_SIZE, }, + { "signal1", __spufs_signal1_read, NULL, sizeof(u32) }, + { "signal1_type", NULL, spufs_signal1_type_get, 19 }, + { "signal2", __spufs_signal2_read, NULL, sizeof(u32) }, + { "signal2_type", NULL, spufs_signal2_type_get, 19 }, + { "event_mask", NULL, spufs_event_mask_get, 19 }, + { "event_status", NULL, spufs_event_status_get, 19 }, + { "mbox_info", __spufs_mbox_info_read, NULL, sizeof(u32) }, + { "ibox_info", __spufs_ibox_info_read, NULL, sizeof(u32) }, + { "wbox_info", __spufs_wbox_info_read, NULL, 4 * sizeof(u32)}, + { "dma_info", __spufs_dma_info_read, NULL, sizeof(struct spu_dma_info)}, + { "proxydma_info", __spufs_proxydma_info_read, + NULL, sizeof(struct spu_proxydma_info)}, + { "object-id", NULL, spufs_object_id_get, 19 }, + { "npc", NULL, spufs_npc_get, 19 }, + { NULL }, }; -int spufs_coredump_num_notes = ARRAY_SIZE(spufs_coredump_read) - 1; - diff -puN arch/powerpc/platforms/cell/spufs/inode.c~git-powerpc arch/powerpc/platforms/cell/spufs/inode.c --- a/arch/powerpc/platforms/cell/spufs/inode.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/inode.c @@ -43,6 +43,7 @@ static struct kmem_cache *spufs_inode_cache; char *isolated_loader; +static int isolated_loader_size; static struct inode * spufs_alloc_inode(struct super_block *sb) @@ -667,7 +668,8 @@ spufs_parse_options(char *options, struc static void spufs_exit_isolated_loader(void) { - kfree(isolated_loader); + free_pages((unsigned long) isolated_loader, + get_order(isolated_loader_size)); } static void @@ -685,11 +687,12 @@ spufs_init_isolated_loader(void) if (!loader) return; - /* kmalloc should align on a 16 byte boundary..* */ - isolated_loader = kmalloc(size, GFP_KERNEL); + /* the loader must be align on a 16 byte boundary */ + isolated_loader = (char *)__get_free_pages(GFP_KERNEL, get_order(size)); if (!isolated_loader) return; + isolated_loader_size = size; memcpy(isolated_loader, loader, size); printk(KERN_INFO "spufs: SPU isolation mode enabled\n"); } @@ -787,16 +790,11 @@ static int __init spufs_init(void) ret = register_spu_syscalls(&spufs_calls); if (ret) goto out_fs; - ret = register_arch_coredump_calls(&spufs_coredump_calls); - if (ret) - goto out_syscalls; spufs_init_isolated_loader(); return 0; -out_syscalls: - unregister_spu_syscalls(&spufs_calls); out_fs: unregister_filesystem(&spufs_type); out_sched: @@ -812,7 +810,6 @@ static void __exit spufs_exit(void) { spu_sched_exit(); spufs_exit_isolated_loader(); - unregister_arch_coredump_calls(&spufs_coredump_calls); unregister_spu_syscalls(&spufs_calls); unregister_filesystem(&spufs_type); kmem_cache_destroy(spufs_inode_cache); diff -puN arch/powerpc/platforms/cell/spufs/run.c~git-powerpc arch/powerpc/platforms/cell/spufs/run.c --- a/arch/powerpc/platforms/cell/spufs/run.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/run.c @@ -205,7 +205,7 @@ static int spu_reacquire_runnable(struct * This means we can only do a very rough approximation of POSIX * signal semantics. */ -int spu_handle_restartsys(struct spu_context *ctx, long *spu_ret, +static int spu_handle_restartsys(struct spu_context *ctx, long *spu_ret, unsigned int *npc) { int ret; @@ -241,7 +241,7 @@ int spu_handle_restartsys(struct spu_con return ret; } -int spu_process_callback(struct spu_context *ctx) +static int spu_process_callback(struct spu_context *ctx) { struct spu_syscall_block s; u32 ls_pointer, npc; diff -puN arch/powerpc/platforms/cell/spufs/sched.c~git-powerpc arch/powerpc/platforms/cell/spufs/sched.c --- a/arch/powerpc/platforms/cell/spufs/sched.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/sched.c @@ -230,8 +230,6 @@ static void spu_bind_context(struct spu if (ctx->flags & SPU_CREATE_NOSCHED) atomic_inc(&cbe_spu_info[spu->node].reserved_spus); - if (!list_empty(&ctx->aff_list)) - atomic_inc(&ctx->gang->aff_sched_count); ctx->stats.slb_flt_base = spu->stats.slb_flt; ctx->stats.class2_intr_base = spu->stats.class2_intr; @@ -392,7 +390,6 @@ static int has_affinity(struct spu_conte if (list_empty(&ctx->aff_list)) return 0; - mutex_lock(&gang->aff_mutex); if (!gang->aff_ref_spu) { if (!(gang->aff_flags & AFF_MERGED)) aff_merge_remaining_ctxs(gang); @@ -400,7 +397,6 @@ static int has_affinity(struct spu_conte aff_set_offsets(gang); aff_set_ref_point_location(gang); } - mutex_unlock(&gang->aff_mutex); return gang->aff_ref_spu != NULL; } @@ -418,9 +414,16 @@ static void spu_unbind_context(struct sp if (spu->ctx->flags & SPU_CREATE_NOSCHED) atomic_dec(&cbe_spu_info[spu->node].reserved_spus); - if (!list_empty(&ctx->aff_list)) - if (atomic_dec_and_test(&ctx->gang->aff_sched_count)) - ctx->gang->aff_ref_spu = NULL; + + if (ctx->gang){ + mutex_lock(&ctx->gang->aff_mutex); + if (has_affinity(ctx)) { + if (atomic_dec_and_test(&ctx->gang->aff_sched_count)) + ctx->gang->aff_ref_spu = NULL; + } + mutex_unlock(&ctx->gang->aff_mutex); + } + spu_switch_notify(spu, NULL); spu_unmap_mappings(ctx); spu_save(&ctx->csa, spu); @@ -511,20 +514,32 @@ static void spu_prio_wait(struct spu_con static struct spu *spu_get_idle(struct spu_context *ctx) { - struct spu *spu; + struct spu *spu, *aff_ref_spu; int node, n; - if (has_affinity(ctx)) { - node = ctx->gang->aff_ref_spu->node; + if (ctx->gang) { + mutex_lock(&ctx->gang->aff_mutex); + if (has_affinity(ctx)) { + aff_ref_spu = ctx->gang->aff_ref_spu; + atomic_inc(&ctx->gang->aff_sched_count); + mutex_unlock(&ctx->gang->aff_mutex); + node = aff_ref_spu->node; - mutex_lock(&cbe_spu_info[node].list_mutex); - spu = ctx_location(ctx->gang->aff_ref_spu, ctx->aff_offset, node); - if (spu && spu->alloc_state == SPU_FREE) - goto found; - mutex_unlock(&cbe_spu_info[node].list_mutex); - return NULL; - } + mutex_lock(&cbe_spu_info[node].list_mutex); + spu = ctx_location(aff_ref_spu, ctx->aff_offset, node); + if (spu && spu->alloc_state == SPU_FREE) + goto found; + mutex_unlock(&cbe_spu_info[node].list_mutex); + mutex_lock(&ctx->gang->aff_mutex); + if (atomic_dec_and_test(&ctx->gang->aff_sched_count)) + ctx->gang->aff_ref_spu = NULL; + mutex_unlock(&ctx->gang->aff_mutex); + + return NULL; + } + mutex_unlock(&ctx->gang->aff_mutex); + } node = cpu_to_node(raw_smp_processor_id()); for (n = 0; n < MAX_NUMNODES; n++, node++) { node = (node < MAX_NUMNODES) ? node : 0; diff -puN arch/powerpc/platforms/cell/spufs/spufs.h~git-powerpc arch/powerpc/platforms/cell/spufs/spufs.h --- a/arch/powerpc/platforms/cell/spufs/spufs.h~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/spufs.h @@ -200,9 +200,14 @@ extern struct tree_descr spufs_dir_conte extern struct tree_descr spufs_dir_nosched_contents[]; /* system call implementation */ +extern struct spufs_calls spufs_calls; long spufs_run_spu(struct spu_context *ctx, u32 *npc, u32 *status); long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode, struct file *filp); +/* ELF coredump callbacks for writing SPU ELF notes */ +extern int spufs_coredump_extra_notes_size(void); +extern int spufs_coredump_extra_notes_write(struct file *file, loff_t *foffset); + extern const struct file_operations spufs_context_fops; /* gang management */ @@ -295,7 +300,7 @@ struct spufs_coredump_reader { char *name; ssize_t (*read)(struct spu_context *ctx, char __user *buffer, size_t size, loff_t *pos); - u64 (*get)(void *data); + u64 (*get)(struct spu_context *ctx); size_t size; }; extern struct spufs_coredump_reader spufs_coredump_read[]; diff -puN arch/powerpc/platforms/cell/spufs/switch.c~git-powerpc arch/powerpc/platforms/cell/spufs/switch.c --- a/arch/powerpc/platforms/cell/spufs/switch.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/switch.c @@ -1559,15 +1559,15 @@ static inline void restore_decr_wrapped( * "wrapped" flag is set, OR in a '1' to * CSA.SPU_Event_Status[Tm]. */ - if (csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED) { - csa->spu_chnldata_RW[0] |= 0x20; - } - if ((csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED) && - (csa->spu_chnlcnt_RW[0] == 0 && - ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) && - ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) { + if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED)) + return; + + if ((csa->spu_chnlcnt_RW[0] == 0) && + (csa->spu_chnldata_RW[1] & 0x20) && + !(csa->spu_chnldata_RW[0] & 0x20)) csa->spu_chnlcnt_RW[0] = 1; - } + + csa->spu_chnldata_RW[0] |= 0x20; } static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu) @@ -2146,19 +2146,6 @@ int spu_restore(struct spu_state *new, s } EXPORT_SYMBOL_GPL(spu_restore); -/** - * spu_harvest - SPU harvest (reset) operation - * @spu: pointer to SPU iomem structure. - * - * Perform SPU harvest (reset) operation. - */ -void spu_harvest(struct spu *spu) -{ - acquire_spu_lock(spu); - harvest(NULL, spu); - release_spu_lock(spu); -} - static void init_prob(struct spu_state *csa) { csa->spu_chnlcnt_RW[9] = 1; diff -puN arch/powerpc/platforms/cell/spufs/syscalls.c~git-powerpc arch/powerpc/platforms/cell/spufs/syscalls.c --- a/arch/powerpc/platforms/cell/spufs/syscalls.c~git-powerpc +++ a/arch/powerpc/platforms/cell/spufs/syscalls.c @@ -58,26 +58,8 @@ out: return ret; } -#ifndef MODULE -asmlinkage long sys_spu_run(int fd, __u32 __user *unpc, __u32 __user *ustatus) -{ - int fput_needed; - struct file *filp; - long ret; - - ret = -EBADF; - filp = fget_light(fd, &fput_needed); - if (filp) { - ret = do_spu_run(filp, unpc, ustatus); - fput_light(filp, fput_needed); - } - - return ret; -} -#endif - -asmlinkage long do_spu_create(const char __user *pathname, unsigned int flags, - mode_t mode, struct file *neighbor) +static long do_spu_create(const char __user *pathname, unsigned int flags, + mode_t mode, struct file *neighbor) { char *tmp; int ret; @@ -99,32 +81,10 @@ asmlinkage long do_spu_create(const char return ret; } -#ifndef MODULE -asmlinkage long sys_spu_create(const char __user *pathname, unsigned int flags, - mode_t mode, int neighbor_fd) -{ - int fput_needed; - struct file *neighbor; - long ret; - - if (flags & SPU_CREATE_AFFINITY_SPU) { - ret = -EBADF; - neighbor = fget_light(neighbor_fd, &fput_needed); - if (neighbor) { - ret = do_spu_create(pathname, flags, mode, neighbor); - fput_light(neighbor, fput_needed); - } - } - else { - ret = do_spu_create(pathname, flags, mode, NULL); - } - - return ret; -} -#endif - struct spufs_calls spufs_calls = { .create_thread = do_spu_create, .spu_run = do_spu_run, + .coredump_extra_notes_size = spufs_coredump_extra_notes_size, + .coredump_extra_notes_write = spufs_coredump_extra_notes_write, .owner = THIS_MODULE, }; diff -puN arch/powerpc/platforms/celleb/interrupt.c~git-powerpc arch/powerpc/platforms/celleb/interrupt.c --- a/arch/powerpc/platforms/celleb/interrupt.c~git-powerpc +++ a/arch/powerpc/platforms/celleb/interrupt.c @@ -175,11 +175,18 @@ static int beatic_pic_host_xlate(struct return 0; } +static int beatic_pic_host_match(struct irq_host *h, struct device_node *np) +{ + /* Match all */ + return 1; +} + static struct irq_host_ops beatic_pic_host_ops = { .map = beatic_pic_host_map, .remap = beatic_pic_host_remap, .unmap = beatic_pic_host_unmap, .xlate = beatic_pic_host_xlate, + .match = beatic_pic_host_match, }; /* @@ -242,7 +249,7 @@ void __init beatic_init_IRQ(void) ppc_md.get_irq = beatic_get_irq; /* Allocate an irq host */ - beatic_host = irq_alloc_host(IRQ_HOST_MAP_NOMAP, 0, + beatic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_NOMAP, 0, &beatic_pic_host_ops, 0); BUG_ON(beatic_host == NULL); diff -puN arch/powerpc/platforms/celleb/pci.c~git-powerpc arch/powerpc/platforms/celleb/pci.c --- a/arch/powerpc/platforms/celleb/pci.c~git-powerpc +++ a/arch/powerpc/platforms/celleb/pci.c @@ -242,8 +242,8 @@ static int celleb_fake_pci_write_config( } static struct pci_ops celleb_fake_pci_ops = { - celleb_fake_pci_read_config, - celleb_fake_pci_write_config + .read = celleb_fake_pci_read_config, + .write = celleb_fake_pci_write_config, }; static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose, @@ -288,8 +288,8 @@ static inline void celleb_setup_pci_base celleb_config_write_fake(config, PCI_COMMAND, 2, val); } -static int __devinit celleb_setup_fake_pci_device(struct device_node *node, - struct pci_controller *hose) +static int __init celleb_setup_fake_pci_device(struct device_node *node, + struct pci_controller *hose) { unsigned int rlen; int num_base_addr = 0; @@ -327,10 +327,7 @@ static int __devinit celleb_setup_fake_p size = 256; config = &private->fake_config[devno][fn]; - if (mem_init_done) - *config = kzalloc(size, GFP_KERNEL); - else - *config = alloc_bootmem(size); + *config = alloc_maybe_bootmem(size, GFP_KERNEL); if (*config == NULL) { printk(KERN_ERR "PCI: " "not enough memory for fake configuration space\n"); @@ -341,10 +338,7 @@ static int __devinit celleb_setup_fake_p size = sizeof(struct celleb_pci_resource); res = &private->res[devno][fn]; - if (mem_init_done) - *res = kzalloc(size, GFP_KERNEL); - else - *res = alloc_bootmem(size); + *res = alloc_maybe_bootmem(size, GFP_KERNEL); if (*res == NULL) { printk(KERN_ERR "PCI: not enough memory for resource data space\n"); @@ -418,8 +412,8 @@ error: return 1; } -static int __devinit phb_set_bus_ranges(struct device_node *dev, - struct pci_controller *phb) +static int __init phb_set_bus_ranges(struct device_node *dev, + struct pci_controller *phb) { const int *bus_range; unsigned int len; @@ -434,17 +428,14 @@ static int __devinit phb_set_bus_ranges( return 0; } -static void __devinit celleb_alloc_private_mem(struct pci_controller *hose) +static void __init celleb_alloc_private_mem(struct pci_controller *hose) { - if (mem_init_done) - hose->private_data = - kzalloc(sizeof(struct celleb_pci_private), GFP_KERNEL); - else - hose->private_data = - alloc_bootmem(sizeof(struct celleb_pci_private)); + hose->private_data = + alloc_maybe_bootmem(sizeof(struct celleb_pci_private), + GFP_KERNEL); } -int __devinit celleb_setup_phb(struct pci_controller *phb) +int __init celleb_setup_phb(struct pci_controller *phb) { const char *name; struct device_node *dev = phb->arch_data; diff -puN arch/powerpc/platforms/celleb/scc_epci.c~git-powerpc arch/powerpc/platforms/celleb/scc_epci.c --- a/arch/powerpc/platforms/celleb/scc_epci.c~git-powerpc +++ a/arch/powerpc/platforms/celleb/scc_epci.c @@ -278,12 +278,12 @@ static int celleb_epci_write_config(stru } struct pci_ops celleb_epci_ops = { - celleb_epci_read_config, - celleb_epci_write_config, + .read = celleb_epci_read_config, + .write = celleb_epci_write_config, }; /* to be moved in FW */ -static int __devinit celleb_epci_init(struct pci_controller *hose) +static int __init celleb_epci_init(struct pci_controller *hose) { u32 val; volatile void __iomem *reg, *epci_base; @@ -403,7 +403,7 @@ static int __devinit celleb_epci_init(st return 0; } -int __devinit celleb_setup_epci(struct device_node *node, +int __init celleb_setup_epci(struct device_node *node, struct pci_controller *hose) { struct resource r; diff -puN arch/powerpc/platforms/celleb/scc_sio.c~git-powerpc arch/powerpc/platforms/celleb/scc_sio.c --- a/arch/powerpc/platforms/celleb/scc_sio.c~git-powerpc +++ a/arch/powerpc/platforms/celleb/scc_sio.c @@ -28,18 +28,18 @@ /* sio irq0=0xb00010022 irq0=0xb00010023 irq2=0xb00010024 mmio=0xfff000-0x1000,0xff2000-0x1000 */ -static int txx9_serial_bitmap = 0; +static int txx9_serial_bitmap __initdata = 0; static struct { uint32_t offset; uint32_t index; -} txx9_scc_tab[3] = { +} txx9_scc_tab[3] __initdata = { { 0x300, 0 }, /* 0xFFF300 */ { 0x400, 0 }, /* 0xFFF400 */ { 0x800, 1 } /* 0xFF2800 */ }; -static int txx9_serial_init(void) +static int __init txx9_serial_init(void) { extern int early_serial_txx9_setup(struct uart_port *port); struct device_node *node; @@ -79,7 +79,7 @@ static int txx9_serial_init(void) return 0; } -static int txx9_serial_config(char *ptr) +static int __init txx9_serial_config(char *ptr) { int i; diff -puN arch/powerpc/platforms/celleb/setup.c~git-powerpc arch/powerpc/platforms/celleb/setup.c --- a/arch/powerpc/platforms/celleb/setup.c~git-powerpc +++ a/arch/powerpc/platforms/celleb/setup.c @@ -73,7 +73,7 @@ static void celleb_show_cpuinfo(struct s of_node_put(root); } -static int celleb_machine_type_hack(char *ptr) +static int __init celleb_machine_type_hack(char *ptr) { strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type)); celleb_machine_type[sizeof(celleb_machine_type)-1] = 0; @@ -135,7 +135,7 @@ static void celleb_kexec_cpu_down(int cr } #endif -static struct of_device_id celleb_bus_ids[] = { +static struct of_device_id celleb_bus_ids[] __initdata = { { .type = "scc", }, { .type = "ioif", }, /* old style */ {}, diff -puN /dev/null arch/powerpc/platforms/chrp/gg2.h --- /dev/null +++ a/arch/powerpc/platforms/chrp/gg2.h @@ -0,0 +1,61 @@ +/* + * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is based on the following documentation: + * + * The VAS96011/12 Chipset, Data Book, Edition 1.0 + * VLSI Technology, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _ASMPPC_GG2_H +#define _ASMPPC_GG2_H + + /* + * Memory Map (CHRP mode) + */ + +#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ +#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ +#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ +#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ +#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ + /* special PCI cycles */ +#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ +#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ + + + /* + * GG2 specific PCI Registers + */ + +extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ + +#define GG2_PCI_BUSNO 0x40 /* Bus number */ +#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ +#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ +#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ +#define GG2_PCI_ADDR_MAP 0x5c /* Address map */ +#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ +#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ +#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ +#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ +#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ +#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ +#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ +#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ +#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ +#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ +#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ +#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ +#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ +#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ +#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ + /* Cleared when read */ + +#endif /* _ASMPPC_GG2_H */ diff -puN arch/powerpc/platforms/chrp/pci.c~git-powerpc arch/powerpc/platforms/chrp/pci.c --- a/arch/powerpc/platforms/chrp/pci.c~git-powerpc +++ a/arch/powerpc/platforms/chrp/pci.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -21,6 +20,7 @@ #include #include "chrp.h" +#include "gg2.h" /* LongTrail */ void __iomem *gg2_pci_config_base; @@ -86,8 +86,8 @@ int gg2_write_config(struct pci_bus *bus static struct pci_ops gg2_pci_ops = { - gg2_read_config, - gg2_write_config + .read = gg2_read_config, + .write = gg2_write_config, }; /* @@ -124,8 +124,8 @@ int rtas_write_config(struct pci_bus *bu static struct pci_ops rtas_pci_ops = { - rtas_read_config, - rtas_write_config + .read = rtas_read_config, + .write = rtas_write_config, }; volatile struct Hydra __iomem *Hydra = NULL; @@ -338,3 +338,32 @@ void chrp_pci_fixup_winbond_ata(struct p } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, chrp_pci_fixup_winbond_ata); + +/* Pegasos2 firmware version 20040810 configures the built-in IDE controller + * in legacy mode, but sets the PCI registers to PCI native mode. + * The chip can only operate in legacy mode, so force the PCI class into legacy + * mode as well. The same fixup must be done to the class-code property in + * the IDE node /pci@80000000/ide@C,1 + */ +static void chrp_pci_fixup_vt8231_ata(struct pci_dev *viaide) +{ + u8 progif; + struct pci_dev *viaisa; + + if (!machine_is(chrp) || _chrp_type != _CHRP_Pegasos) + return; + if (viaide->irq != 14) + return; + + viaisa = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); + if (!viaisa) + return; + printk("Fixing VIA IDE, force legacy mode on '%s'\n", viaide->dev.bus_id); + + pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif); + pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5); + viaide->class &= ~0x5; + + pci_dev_put(viaisa); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, chrp_pci_fixup_vt8231_ata); diff -puN arch/powerpc/platforms/chrp/setup.c~git-powerpc arch/powerpc/platforms/chrp/setup.c --- a/arch/powerpc/platforms/chrp/setup.c~git-powerpc +++ a/arch/powerpc/platforms/chrp/setup.c @@ -32,13 +32,11 @@ #include #include #include -#include #include #include #include #include -#include #include #include #include @@ -52,6 +50,7 @@ #include #include "chrp.h" +#include "gg2.h" void rtas_indicator_progress(char *, unsigned short); diff -puN arch/powerpc/platforms/chrp/smp.c~git-powerpc arch/powerpc/platforms/chrp/smp.c --- a/arch/powerpc/platforms/chrp/smp.c~git-powerpc +++ a/arch/powerpc/platforms/chrp/smp.c @@ -26,10 +26,8 @@ #include #include #include -#include #include #include -#include #include #include diff -puN arch/powerpc/platforms/embedded6xx/holly.c~git-powerpc arch/powerpc/platforms/embedded6xx/holly.c --- a/arch/powerpc/platforms/embedded6xx/holly.c~git-powerpc +++ a/arch/powerpc/platforms/embedded6xx/holly.c @@ -113,23 +113,11 @@ static void holly_remap_bridge(void) static void __init holly_setup_arch(void) { - struct device_node *cpu; struct device_node *np; if (ppc_md.progress) ppc_md.progress("holly_setup_arch():set_bridge", 0); - cpu = of_find_node_by_type(NULL, "cpu"); - if (cpu) { - const unsigned int *fp; - - fp = of_get_property(cpu, "clock-frequency", NULL); - if (fp) - loops_per_jiffy = *fp / HZ; - else - loops_per_jiffy = 50000000 / HZ; - of_node_put(cpu); - } tsi108_csr_vir_base = get_vir_csrbase(); /* setup PCI host bridge */ @@ -147,7 +135,7 @@ static void __init holly_setup_arch(void } /* - * Interrupt setup and service. Interrrupts on the holly come + * Interrupt setup and service. Interrupts on the holly come * from the four external INT pins, PCI interrupts are routed via * PCI interrupt control registers, it generates internal IRQ23 * diff -puN arch/powerpc/platforms/embedded6xx/linkstation.c~git-powerpc arch/powerpc/platforms/embedded6xx/linkstation.c --- a/arch/powerpc/platforms/embedded6xx/linkstation.c~git-powerpc +++ a/arch/powerpc/platforms/embedded6xx/linkstation.c @@ -11,16 +11,16 @@ */ #include -#include #include #include #include #include #include -#include #include +#include "mpc10x.h" + static struct mtd_partition linkstation_physmap_partitions[] = { { .name = "mtd_firmimg", @@ -99,7 +99,7 @@ static void __init linkstation_setup_arc } /* - * Interrupt setup and service. Interrrupts on the linkstation come + * Interrupt setup and service. Interrupts on the linkstation come * from the four PCI slots plus onboard 8241 devices: I2C, DUART. */ static void __init linkstation_init_IRQ(void) diff -puN arch/powerpc/platforms/embedded6xx/ls_uart.c~git-powerpc arch/powerpc/platforms/embedded6xx/ls_uart.c --- a/arch/powerpc/platforms/embedded6xx/ls_uart.c~git-powerpc +++ a/arch/powerpc/platforms/embedded6xx/ls_uart.c @@ -1,14 +1,25 @@ +/* + * AVR power-management chip interface for the Buffalo Linkstation / + * Kurobox Platform. + * + * Author: 2006 (c) G. Liakhovetski + * g.liakhovetski@gmx.de + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ #include #include #include #include #include #include -#include -#include #include #include +#include "mpc10x.h" + static void __iomem *avr_addr; static unsigned long avr_clock; @@ -106,6 +117,9 @@ static int __init ls_uarts_init(void) phys_addr_t phys_addr; int len; + if (!machine_is(linkstation)) + return 0; + avr = of_find_node_by_path("/soc10x/serial@80004500"); if (!avr) return -EINVAL; diff -puN /dev/null arch/powerpc/platforms/embedded6xx/mpc10x.h --- /dev/null +++ a/arch/powerpc/platforms/embedded6xx/mpc10x.h @@ -0,0 +1,180 @@ +/* + * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem + * ctlr/EPIC/etc. + * + * Author: Mark A. Greer + * mgreer@mvista.com + * + * 2001 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __PPC_KERNEL_MPC10X_H +#define __PPC_KERNEL_MPC10X_H + +#include +#include + +/* + * The values here don't completely map everything but should work in most + * cases. + * + * MAP A (PReP Map) + * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff + * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff + * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 + * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) + * + * MAP B (CHRP Map) + * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff + * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff + * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 + * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) + */ + +/* + * Define the vendor/device IDs for the various bridges--should be added to + * + */ +#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ + PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) + +/* Define the type of map to use */ +#define MPC10X_MEM_MAP_A 1 +#define MPC10X_MEM_MAP_B 2 + +/* Map A (PReP Map) Defines */ +#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 +#define MPC10X_MAPA_CNFG_DATA 0x80000cfc + +#define MPC10X_MAPA_ISA_IO_BASE 0x80000000 +#define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 +#define MPC10X_MAPA_DRAM_OFFSET 0x80000000 + +#define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 +#define MPC10X_MAPA_PCI_IO_START 0x00000000 +#define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) +#define MPC10X_MAPA_PCI_MEM_START 0x00000000 +#define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) + +#define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ + MPC10X_MAPA_PCI_MEM_START) + +/* Map B (CHRP Map) Defines */ +#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 +#define MPC10X_MAPB_CNFG_DATA 0xfee00000 + +#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 +#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 +#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 + +#define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 +#define MPC10X_MAPB_PCI_IO_START 0x00000000 +#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) +#define MPC10X_MAPB_PCI_MEM_START 0x80000000 +#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) + +#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ + MPC10X_MAPB_PCI_MEM_START) + +/* Set hose members to values appropriate for the mem map used */ +#define MPC10X_SETUP_HOSE(hose, map) { \ + (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \ + (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \ + (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \ + (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \ + (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \ + (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \ +} + + +/* Miscellaneous Configuration register offsets */ +#define MPC10X_CFG_PIR_REG 0x09 +#define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 +#define MPC10X_CFG_PIR_AGENT 0x01 + +#define MPC10X_CFG_EUMBBAR 0x78 + +#define MPC10X_CFG_PICR1_REG 0xa8 +#define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 +#define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 +#define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 +#define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 +#define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 + +#define MPC10X_CFG_PICR2_REG 0xac +#define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 + +#define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 +#define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ +#define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ +#define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ +#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ +#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ + +/* Define offsets for the memory controller registers in the config space */ +#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ +#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ +#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ +#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ + +#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ +#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ +#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ +#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ + +#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 + +/* Define some offset in the EUMB */ +#define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ + +#define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ +#define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ +#define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ +#define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ +#define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ +#define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ +#define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ +#define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ +#define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ +#define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ +#define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ +#define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ +#define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ +#define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ +#define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ +#define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ + +/* + * Define some recommended places to put the EUMB regs. + * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff. + */ +extern unsigned long ioremap_base; +#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) +#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE + +enum ppc_sys_devices { + MPC10X_IIC1, + MPC10X_DMA0, + MPC10X_DMA1, + MPC10X_UART0, + MPC10X_UART1, + NUM_PPC_SYS_DEVS, +}; + +int mpc10x_bridge_init(struct pci_controller *hose, + uint current_map, + uint new_map, + uint phys_eumb_base); +unsigned long mpc10x_get_mem_size(uint mem_map); +int mpc10x_enable_store_gathering(struct pci_controller *hose); +int mpc10x_disable_store_gathering(struct pci_controller *hose); + +/* For MPC107 boards that use the built-in openpic */ +void mpc10x_set_openpic(void); + +#endif /* __PPC_KERNEL_MPC10X_H */ diff -puN arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c~git-powerpc arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c --- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c~git-powerpc +++ a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c @@ -40,7 +40,6 @@ #include #include #include -#include "mpc7448_hpc2.h" #include #include #include @@ -91,7 +90,7 @@ static void __init mpc7448_hpc2_setup_ar } /* - * Interrupt setup and service. Interrrupts on the mpc7448_hpc2 come + * Interrupt setup and service. Interrupts on the mpc7448_hpc2 come * from the four external INT pins, PCI interrupts are routed via * PCI interrupt control registers, it generates internal IRQ23 * diff -puN arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.h~git-powerpc /dev/null --- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * mpc7448_hpc2.h - * - * Definitions for Freescale MPC7448_HPC2 platform - * - * Author: Jacob Pan - * jacob.pan@freescale.com - * Maintainer: Roy Zang - * - * 2006 (c) Freescale Semiconductor, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __PPC_PLATFORMS_MPC7448_HPC2_H -#define __PPC_PLATFORMS_MPC7448_HPC2_H - -#include - -#endif /* __PPC_PLATFORMS_MPC7448_HPC2_H */ diff -puN arch/powerpc/platforms/embedded6xx/prpmc2800.c~git-powerpc arch/powerpc/platforms/embedded6xx/prpmc2800.c --- a/arch/powerpc/platforms/embedded6xx/prpmc2800.c~git-powerpc +++ a/arch/powerpc/platforms/embedded6xx/prpmc2800.c @@ -44,7 +44,6 @@ static void __init prpmc2800_setup_arch( struct device_node *np; phys_addr_t paddr; const unsigned int *reg; - const unsigned int *prop; /* * ioremap mpp and gpp registers in case they are later @@ -62,12 +61,6 @@ static void __init prpmc2800_setup_arch( of_node_put(np); mv64x60_gpp_reg_base = ioremap(paddr, reg[1]); - np = of_find_node_by_type(NULL, "cpu"); - prop = of_get_property(np, "clock-frequency", NULL); - if (prop) - loops_per_jiffy = *prop / HZ; - of_node_put(np); - #ifdef CONFIG_PCI mv64x60_pci_init(); #endif diff -puN arch/powerpc/platforms/iseries/Makefile~git-powerpc arch/powerpc/platforms/iseries/Makefile --- a/arch/powerpc/platforms/iseries/Makefile~git-powerpc +++ a/arch/powerpc/platforms/iseries/Makefile @@ -2,6 +2,7 @@ EXTRA_CFLAGS += -mno-minimal-toc extra-y += dt.o +obj-y += exception.o obj-y += hvlog.o hvlpconfig.o lpardata.o setup.o dt_mod.o mf.o lpevents.o \ hvcall.o proc.o htab.o iommu.o misc.o irq.o obj-$(CONFIG_PCI) += pci.o vpdinfo.o diff -puN /dev/null arch/powerpc/platforms/iseries/exception.S --- /dev/null +++ a/arch/powerpc/platforms/iseries/exception.S @@ -0,0 +1,251 @@ +/* + * Low level routines for legacy iSeries support. + * + * Extracted from head_64.S + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * + * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and + * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com + * + * This file contains the low-level support and setup for the + * PowerPC-64 platform, including trap and interrupt dispatch. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include + +#include "exception.h" + + .text + + .globl system_reset_iSeries +system_reset_iSeries: + mfspr r13,SPRN_SPRG3 /* Get paca address */ + mfmsr r24 + ori r24,r24,MSR_RI + mtmsrd r24 /* RI on */ + lhz r24,PACAPACAINDEX(r13) /* Get processor # */ + cmpwi 0,r24,0 /* Are we processor 0? */ + bne 1f + b .__start_initialization_iSeries /* Start up the first processor */ +1: mfspr r4,SPRN_CTRLF + li r5,CTRL_RUNLATCH /* Turn off the run light */ + andc r4,r4,r5 + mtspr SPRN_CTRLT,r4 + +1: + HMT_LOW +#ifdef CONFIG_SMP + lbz r23,PACAPROCSTART(r13) /* Test if this processor + * should start */ + sync + LOAD_REG_IMMEDIATE(r3,current_set) + sldi r28,r24,3 /* get current_set[cpu#] */ + ldx r3,r3,r28 + addi r1,r3,THREAD_SIZE + subi r1,r1,STACK_FRAME_OVERHEAD + + cmpwi 0,r23,0 + beq iSeries_secondary_smp_loop /* Loop until told to go */ + b __secondary_start /* Loop until told to go */ +iSeries_secondary_smp_loop: + /* Let the Hypervisor know we are alive */ + /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ + lis r3,0x8002 + rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ +#else /* CONFIG_SMP */ + /* Yield the processor. This is required for non-SMP kernels + which are running on multi-threaded machines. */ + lis r3,0x8000 + rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ + addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ + li r4,0 /* "yield timed" */ + li r5,-1 /* "yield forever" */ +#endif /* CONFIG_SMP */ + li r0,-1 /* r0=-1 indicates a Hypervisor call */ + sc /* Invoke the hypervisor via a system call */ + mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ + b 1b /* If SMP not configured, secondaries + * loop forever */ + +/*** ISeries-LPAR interrupt handlers ***/ + + STD_EXCEPTION_ISERIES(machine_check, PACA_EXMC) + + .globl data_access_iSeries +data_access_iSeries: + mtspr SPRN_SPRG1,r13 +BEGIN_FTR_SECTION + mtspr SPRN_SPRG2,r12 + mfspr r13,SPRN_DAR + mfspr r12,SPRN_DSISR + srdi r13,r13,60 + rlwimi r13,r12,16,0x20 + mfcr r12 + cmpwi r13,0x2c + beq .do_stab_bolted_iSeries + mtcrf 0x80,r12 + mfspr r12,SPRN_SPRG2 +END_FTR_SECTION_IFCLR(CPU_FTR_SLB) + EXCEPTION_PROLOG_1(PACA_EXGEN) + EXCEPTION_PROLOG_ISERIES_1 + b data_access_common + +.do_stab_bolted_iSeries: + mtcrf 0x80,r12 + mfspr r12,SPRN_SPRG2 + EXCEPTION_PROLOG_1(PACA_EXSLB) + EXCEPTION_PROLOG_ISERIES_1 + b .do_stab_bolted + + .globl data_access_slb_iSeries +data_access_slb_iSeries: + mtspr SPRN_SPRG1,r13 /* save r13 */ + mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ + std r3,PACA_EXSLB+EX_R3(r13) + mfspr r3,SPRN_DAR + std r9,PACA_EXSLB+EX_R9(r13) + mfcr r9 +#ifdef __DISABLED__ + cmpdi r3,0 + bge slb_miss_user_iseries +#endif + std r10,PACA_EXSLB+EX_R10(r13) + std r11,PACA_EXSLB+EX_R11(r13) + std r12,PACA_EXSLB+EX_R12(r13) + mfspr r10,SPRN_SPRG1 + std r10,PACA_EXSLB+EX_R13(r13) + ld r12,PACALPPACAPTR(r13) + ld r12,LPPACASRR1(r12) + b .slb_miss_realmode + + STD_EXCEPTION_ISERIES(instruction_access, PACA_EXGEN) + + .globl instruction_access_slb_iSeries +instruction_access_slb_iSeries: + mtspr SPRN_SPRG1,r13 /* save r13 */ + mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ + std r3,PACA_EXSLB+EX_R3(r13) + ld r3,PACALPPACAPTR(r13) + ld r3,LPPACASRR0(r3) /* get SRR0 value */ + std r9,PACA_EXSLB+EX_R9(r13) + mfcr r9 +#ifdef __DISABLED__ + cmpdi r3,0 + bge slb_miss_user_iseries +#endif + std r10,PACA_EXSLB+EX_R10(r13) + std r11,PACA_EXSLB+EX_R11(r13) + std r12,PACA_EXSLB+EX_R12(r13) + mfspr r10,SPRN_SPRG1 + std r10,PACA_EXSLB+EX_R13(r13) + ld r12,PACALPPACAPTR(r13) + ld r12,LPPACASRR1(r12) + b .slb_miss_realmode + +#ifdef __DISABLED__ +slb_miss_user_iseries: + std r10,PACA_EXGEN+EX_R10(r13) + std r11,PACA_EXGEN+EX_R11(r13) + std r12,PACA_EXGEN+EX_R12(r13) + mfspr r10,SPRG1 + ld r11,PACA_EXSLB+EX_R9(r13) + ld r12,PACA_EXSLB+EX_R3(r13) + std r10,PACA_EXGEN+EX_R13(r13) + std r11,PACA_EXGEN+EX_R9(r13) + std r12,PACA_EXGEN+EX_R3(r13) + EXCEPTION_PROLOG_ISERIES_1 + b slb_miss_user_common +#endif + + MASKABLE_EXCEPTION_ISERIES(hardware_interrupt) + STD_EXCEPTION_ISERIES(alignment, PACA_EXGEN) + STD_EXCEPTION_ISERIES(program_check, PACA_EXGEN) + STD_EXCEPTION_ISERIES(fp_unavailable, PACA_EXGEN) + MASKABLE_EXCEPTION_ISERIES(decrementer) + STD_EXCEPTION_ISERIES(trap_0a, PACA_EXGEN) + STD_EXCEPTION_ISERIES(trap_0b, PACA_EXGEN) + + .globl system_call_iSeries +system_call_iSeries: + mr r9,r13 + mfspr r13,SPRN_SPRG3 + EXCEPTION_PROLOG_ISERIES_1 + b system_call_common + + STD_EXCEPTION_ISERIES(single_step, PACA_EXGEN) + STD_EXCEPTION_ISERIES(trap_0e, PACA_EXGEN) + STD_EXCEPTION_ISERIES(performance_monitor, PACA_EXGEN) + +decrementer_iSeries_masked: + /* We may not have a valid TOC pointer in here. */ + li r11,1 + ld r12,PACALPPACAPTR(r13) + stb r11,LPPACADECRINT(r12) + LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy) + lwz r12,0(r12) + mtspr SPRN_DEC,r12 + /* fall through */ + +hardware_interrupt_iSeries_masked: + mtcrf 0x80,r9 /* Restore regs */ + ld r12,PACALPPACAPTR(r13) + ld r11,LPPACASRR0(r12) + ld r12,LPPACASRR1(r12) + mtspr SPRN_SRR0,r11 + mtspr SPRN_SRR1,r12 + ld r9,PACA_EXGEN+EX_R9(r13) + ld r10,PACA_EXGEN+EX_R10(r13) + ld r11,PACA_EXGEN+EX_R11(r13) + ld r12,PACA_EXGEN+EX_R12(r13) + ld r13,PACA_EXGEN+EX_R13(r13) + rfid + b . /* prevent speculative execution */ + +_INIT_STATIC(__start_initialization_iSeries) + /* Clear out the BSS */ + LOAD_REG_IMMEDIATE(r11,__bss_stop) + LOAD_REG_IMMEDIATE(r8,__bss_start) + sub r11,r11,r8 /* bss size */ + addi r11,r11,7 /* round up to an even double word */ + rldicl. r11,r11,61,3 /* shift right by 3 */ + beq 4f + addi r8,r8,-8 + li r0,0 + mtctr r11 /* zero this many doublewords */ +3: stdu r0,8(r8) + bdnz 3b +4: + LOAD_REG_IMMEDIATE(r1,init_thread_union) + addi r1,r1,THREAD_SIZE + li r0,0 + stdu r0,-STACK_FRAME_OVERHEAD(r1) + + LOAD_REG_IMMEDIATE(r2,__toc_start) + addi r2,r2,0x4000 + addi r2,r2,0x4000 + + bl .iSeries_early_setup + bl .early_setup + + /* relocation is on at this point */ + + b .start_here_common diff -puN /dev/null arch/powerpc/platforms/iseries/exception.h --- /dev/null +++ a/arch/powerpc/platforms/iseries/exception.h @@ -0,0 +1,58 @@ +#ifndef _ASM_POWERPC_ISERIES_EXCEPTION_H +#define _ASM_POWERPC_ISERIES_EXCEPTION_H +/* + * Extracted from head_64.S + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * + * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and + * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com + * + * This file contains the low-level support and setup for the + * PowerPC-64 platform, including trap and interrupt dispatch. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include + +#define EXCEPTION_PROLOG_ISERIES_1 \ + mfmsr r10; \ + ld r12,PACALPPACAPTR(r13); \ + ld r11,LPPACASRR0(r12); \ + ld r12,LPPACASRR1(r12); \ + ori r10,r10,MSR_RI; \ + mtmsrd r10,1 + +#define STD_EXCEPTION_ISERIES(label, area) \ + .globl label##_iSeries; \ +label##_iSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + EXCEPTION_PROLOG_1(area); \ + EXCEPTION_PROLOG_ISERIES_1; \ + b label##_common + +#define MASKABLE_EXCEPTION_ISERIES(label) \ + .globl label##_iSeries; \ +label##_iSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + EXCEPTION_PROLOG_1(PACA_EXGEN); \ + lbz r10,PACASOFTIRQEN(r13); \ + cmpwi 0,r10,0; \ + beq- label##_iSeries_masked; \ + EXCEPTION_PROLOG_ISERIES_1; \ + b label##_common; \ + +#endif /* _ASM_POWERPC_ISERIES_EXCEPTION_H */ diff -puN arch/powerpc/platforms/iseries/irq.c~git-powerpc arch/powerpc/platforms/iseries/irq.c --- a/arch/powerpc/platforms/iseries/irq.c~git-powerpc +++ a/arch/powerpc/platforms/iseries/irq.c @@ -346,8 +346,15 @@ static int iseries_irq_host_map(struct i return 0; } +static int iseries_irq_host_match(struct irq_host *h, struct device_node *np) +{ + /* Match all */ + return 1; +} + static struct irq_host_ops iseries_irq_host_ops = { .map = iseries_irq_host_map, + .match = iseries_irq_host_match, }; /* @@ -369,7 +376,8 @@ void __init iSeries_init_IRQ(void) /* Create irq host. No need for a revmap since HV will give us * back our virtual irq number */ - host = irq_alloc_host(IRQ_HOST_MAP_NOMAP, 0, &iseries_irq_host_ops, 0); + host = irq_alloc_host(NULL, IRQ_HOST_MAP_NOMAP, 0, + &iseries_irq_host_ops, 0); BUG_ON(host == NULL); irq_set_default_host(host); diff -puN arch/powerpc/platforms/iseries/it_lp_naca.h~git-powerpc arch/powerpc/platforms/iseries/it_lp_naca.h --- a/arch/powerpc/platforms/iseries/it_lp_naca.h~git-powerpc +++ a/arch/powerpc/platforms/iseries/it_lp_naca.h @@ -60,7 +60,7 @@ struct ItLpNaca { u8 xRsvd2_0[128]; // Reserved x00-x7F // CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators -// NB: Padding required to keep xInterrruptHdlr at x300 which is required +// NB: Padding required to keep xInterruptHdlr at x300 which is required // for v4r4 PLIC. u8 xOldLpQueue[128]; // LP Queue needed for v4r4 100-17F u8 xRsvd3_0[384]; // Reserved 180-2FF diff -puN arch/powerpc/platforms/iseries/setup.c~git-powerpc arch/powerpc/platforms/iseries/setup.c --- a/arch/powerpc/platforms/iseries/setup.c~git-powerpc +++ a/arch/powerpc/platforms/iseries/setup.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include #include diff -puN arch/powerpc/platforms/maple/pci.c~git-powerpc arch/powerpc/platforms/maple/pci.c --- a/arch/powerpc/platforms/maple/pci.c~git-powerpc +++ a/arch/powerpc/platforms/maple/pci.c @@ -169,15 +169,12 @@ static int u3_agp_write_config(struct pc switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -185,8 +182,8 @@ static int u3_agp_write_config(struct pc static struct pci_ops u3_agp_pci_ops = { - u3_agp_read_config, - u3_agp_write_config + .read = u3_agp_read_config, + .write = u3_agp_write_config, }; static unsigned long u3_ht_cfa0(u8 devfn, u8 off) @@ -268,15 +265,12 @@ static int u3_ht_write_config(struct pci switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -284,8 +278,8 @@ static int u3_ht_write_config(struct pci static struct pci_ops u3_ht_pci_ops = { - u3_ht_read_config, - u3_ht_write_config + .read = u3_ht_read_config, + .write = u3_ht_write_config, }; static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off) @@ -376,15 +370,12 @@ static int u4_pcie_write_config(struct p switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -392,8 +383,8 @@ static int u4_pcie_write_config(struct p static struct pci_ops u4_pcie_pci_ops = { - u4_pcie_read_config, - u4_pcie_write_config + .read = u4_pcie_read_config, + .write = u4_pcie_write_config, }; static void __init setup_u3_agp(struct pci_controller* hose) diff -puN arch/powerpc/platforms/pasemi/Kconfig~git-powerpc arch/powerpc/platforms/pasemi/Kconfig --- a/arch/powerpc/platforms/pasemi/Kconfig~git-powerpc +++ a/arch/powerpc/platforms/pasemi/Kconfig @@ -5,6 +5,7 @@ config PPC_PASEMI select MPIC select PPC_UDBG_16550 select PPC_NATIVE + select MPIC_BROKEN_REGREAD help This option enables support for PA Semi's PWRficient line of SoC processors, including PA6T-1682M diff -puN arch/powerpc/platforms/pasemi/idle.c~git-powerpc arch/powerpc/platforms/pasemi/idle.c --- a/arch/powerpc/platforms/pasemi/idle.c~git-powerpc +++ a/arch/powerpc/platforms/pasemi/idle.c @@ -72,8 +72,11 @@ static int pasemi_system_reset_exception return 1; } -void __init pasemi_idle_init(void) +static int __init pasemi_idle_init(void) { + if (!machine_is(pasemi)) + return -ENODEV; + #ifndef CONFIG_PPC_PASEMI_CPUFREQ printk(KERN_WARNING "No cpufreq driver, powersavings modes disabled\n"); current_mode = 0; @@ -82,7 +85,10 @@ void __init pasemi_idle_init(void) ppc_md.system_reset_exception = pasemi_system_reset_exception; ppc_md.power_save = modes[current_mode].entry; printk(KERN_INFO "Using PA6T idle loop (%s)\n", modes[current_mode].name); + + return 0; } +late_initcall(pasemi_idle_init); static int __init idle_param(char *p) { diff -puN arch/powerpc/platforms/pasemi/iommu.c~git-powerpc arch/powerpc/platforms/pasemi/iommu.c --- a/arch/powerpc/platforms/pasemi/iommu.c~git-powerpc +++ a/arch/powerpc/platforms/pasemi/iommu.c @@ -187,7 +187,7 @@ static void pci_dma_dev_setup_pasemi(str static void pci_dma_bus_setup_null(struct pci_bus *b) { } static void pci_dma_dev_setup_null(struct pci_dev *d) { } -int iob_init(struct device_node *dn) +int __init iob_init(struct device_node *dn) { unsigned long tmp; u32 regword; @@ -233,7 +233,7 @@ int iob_init(struct device_node *dn) /* These are called very early. */ -void iommu_init_early_pasemi(void) +void __init iommu_init_early_pasemi(void) { int iommu_off; diff -puN arch/powerpc/platforms/pasemi/pasemi.h~git-powerpc arch/powerpc/platforms/pasemi/pasemi.h --- a/arch/powerpc/platforms/pasemi/pasemi.h~git-powerpc +++ a/arch/powerpc/platforms/pasemi/pasemi.h @@ -6,9 +6,9 @@ extern void pas_pci_init(void); extern void __devinit pas_pci_irq_fixup(struct pci_dev *dev); extern void __devinit pas_pci_dma_dev_setup(struct pci_dev *dev); -extern void __init alloc_iobmap_l2(void); +extern void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset); -extern void __init pasemi_idle_init(void); +extern void __init alloc_iobmap_l2(void); /* Power savings modes, implemented in asm */ extern void idle_spin(void); diff -puN arch/powerpc/platforms/pasemi/pci.c~git-powerpc arch/powerpc/platforms/pasemi/pci.c --- a/arch/powerpc/platforms/pasemi/pci.c~git-powerpc +++ a/arch/powerpc/platforms/pasemi/pci.c @@ -51,6 +51,61 @@ static void volatile __iomem *pa_pxp_cfg return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset); } +static inline int is_root_port(int busno, int devfn) +{ + return ((busno == 0) && (PCI_FUNC(devfn) < 4) && + ((PCI_SLOT(devfn) == 16) || (PCI_SLOT(devfn) == 17))); +} + +static inline int is_5945_reg(int reg) +{ + return (((reg >= 0x18) && (reg < 0x34)) || + ((reg >= 0x158) && (reg < 0x178))); +} + +static int workaround_5945(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose; + void volatile __iomem *addr, *dummy; + int byte; + u32 tmp; + + if (!is_root_port(bus->number, devfn) || !is_5945_reg(offset)) + return 0; + + hose = pci_bus_to_host(bus); + + addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset & ~0x3); + byte = offset & 0x3; + + /* Workaround bug 5945: write 0 to a dummy register before reading, + * and write back what we read. We must read/write the full 32-bit + * contents so we need to shift and mask by hand. + */ + dummy = pa_pxp_cfg_addr(hose, bus->number, devfn, 0x10); + out_le32(dummy, 0); + tmp = in_le32(addr); + out_le32(addr, tmp); + + switch (len) { + case 1: + *val = (tmp >> (8*byte)) & 0xff; + break; + case 2: + if (byte == 0) + *val = tmp & 0xffff; + else + *val = (tmp >> 16) & 0xffff; + break; + default: + *val = tmp; + break; + } + + return 1; +} + static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { @@ -64,6 +119,9 @@ static int pa_pxp_read_config(struct pci if (!pa_pxp_offset_valid(bus->number, devfn, offset)) return PCIBIOS_BAD_REGISTER_NUMBER; + if (workaround_5945(bus, devfn, offset, len, val)) + return PCIBIOS_SUCCESSFUL; + addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset); /* @@ -107,23 +165,20 @@ static int pa_pxp_write_config(struct pc switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; } static struct pci_ops pa_pxp_ops = { - pa_pxp_read_config, - pa_pxp_write_config, + .read = pa_pxp_read_config, + .write = pa_pxp_write_config, }; static void __init setup_pa_pxp(struct pci_controller *hose) @@ -178,3 +233,12 @@ void __init pas_pci_init(void) /* Use the common resource allocation mechanism */ pci_probe_only = 1; } + +void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset) +{ + struct pci_controller *hose; + + hose = pci_bus_to_host(dev->bus); + + return (void __iomem *)pa_pxp_cfg_addr(hose, dev->bus->number, dev->devfn, offset); +} diff -puN arch/powerpc/platforms/pasemi/setup.c~git-powerpc arch/powerpc/platforms/pasemi/setup.c --- a/arch/powerpc/platforms/pasemi/setup.c~git-powerpc +++ a/arch/powerpc/platforms/pasemi/setup.c @@ -39,8 +39,21 @@ #include "pasemi.h" +/* SDC reset register, must be pre-mapped at reset time */ static void __iomem *reset_reg; +/* Various error status registers, must be pre-mapped at MCE time */ + +#define MAX_MCE_REGS 32 +struct mce_regs { + char *name; + void __iomem *addr; +}; + +static struct mce_regs mce_regs[MAX_MCE_REGS]; +static int num_mce_regs; + + static void pas_restart(char *cmd) { printk("Restarting...\n"); @@ -50,26 +63,30 @@ static void pas_restart(char *cmd) #ifdef CONFIG_SMP static DEFINE_SPINLOCK(timebase_lock); +static unsigned long timebase; static void __devinit pas_give_timebase(void) { - unsigned long tb; - spin_lock(&timebase_lock); mtspr(SPRN_TBCTL, TBCTL_FREEZE); - tb = mftb(); - mtspr(SPRN_TBCTL, TBCTL_UPDATE_LOWER | (tb & 0xffffffff)); - mtspr(SPRN_TBCTL, TBCTL_UPDATE_UPPER | (tb >> 32)); - mtspr(SPRN_TBCTL, TBCTL_RESTART); + isync(); + timebase = get_tb(); spin_unlock(&timebase_lock); - pr_debug("pas_give_timebase: cpu %d gave tb %lx\n", - smp_processor_id(), tb); + + while (timebase) + barrier(); + mtspr(SPRN_TBCTL, TBCTL_RESTART); } static void __devinit pas_take_timebase(void) { - pr_debug("pas_take_timebase: cpu %d has tb %lx\n", - smp_processor_id(), mftb()); + while (!timebase) + smp_rmb(); + + spin_lock(&timebase_lock); + set_tb(timebase >> 32, timebase & 0xffffffff); + timebase = 0; + spin_unlock(&timebase_lock); } struct smp_ops_t pas_smp_ops = { @@ -98,9 +115,60 @@ void __init pas_setup_arch(void) /* Remap SDC register for doing reset */ /* XXXOJN This should maybe come out of the device tree */ reset_reg = ioremap(0xfc101100, 4); +} + +static int __init pas_setup_mce_regs(void) +{ + struct pci_dev *dev; + int reg; + + if (!machine_is(pasemi)) + return -ENODEV; + + /* Remap various SoC status registers for use by the MCE handler */ + + reg = 0; - pasemi_idle_init(); + dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL); + while (dev && reg < MAX_MCE_REGS) { + mce_regs[reg].name = kasprintf(GFP_KERNEL, + "mc%d_mcdebug_errsta", reg); + mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); + dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev); + reg++; + } + + dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); + if (dev && reg+4 < MAX_MCE_REGS) { + mce_regs[reg].name = "iobdbg_IntStatus1"; + mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); + reg++; + mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; + mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); + reg++; + mce_regs[reg].name = "iobiom_IntStatus"; + mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); + reg++; + mce_regs[reg].name = "iobiom_IntDbgReg"; + mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); + reg++; + } + + dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL); + if (dev && reg+2 < MAX_MCE_REGS) { + mce_regs[reg].name = "l2csts_IntStatus"; + mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); + reg++; + mce_regs[reg].name = "l2csts_Cnt"; + mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); + reg++; + } + + num_mce_regs = reg; + + return 0; } +device_initcall(pas_setup_mce_regs); static __init void pas_init_IRQ(void) { @@ -162,25 +230,34 @@ static int pas_machine_check_handler(str { int cpu = smp_processor_id(); unsigned long srr0, srr1, dsisr; + int dump_slb = 0; + int i; srr0 = regs->nip; srr1 = regs->msr; dsisr = mfspr(SPRN_DSISR); printk(KERN_ERR "Machine Check on CPU %d\n", cpu); - printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); - printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); + printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); + printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); + printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER), + mfspr(SPRN_PA6T_MER)); + printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER), + mfspr(SPRN_PA6T_DER)); printk(KERN_ERR "Cause:\n"); if (srr1 & 0x200000) printk(KERN_ERR "Signalled by SDC\n"); + if (srr1 & 0x100000) { printk(KERN_ERR "Load/Store detected error:\n"); if (dsisr & 0x8000) printk(KERN_ERR "D-cache ECC double-bit error or bus error\n"); if (dsisr & 0x4000) printk(KERN_ERR "LSU snoop response error\n"); - if (dsisr & 0x2000) + if (dsisr & 0x2000) { printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n"); + dump_slb = 1; + } if (dsisr & 0x1000) printk(KERN_ERR "Recoverable Duptags\n"); if (dsisr & 0x800) @@ -188,13 +265,40 @@ static int pas_machine_check_handler(str if (dsisr & 0x400) printk(KERN_ERR "TLB parity error count overflow\n"); } + if (srr1 & 0x80000) printk(KERN_ERR "Bus Error\n"); - if (srr1 & 0x40000) + + if (srr1 & 0x40000) { printk(KERN_ERR "I-side SLB multiple hit\n"); + dump_slb = 1; + } + if (srr1 & 0x20000) printk(KERN_ERR "I-cache parity error hit\n"); + if (num_mce_regs == 0) + printk(KERN_ERR "No MCE registers mapped yet, can't dump\n"); + else + printk(KERN_ERR "SoC debug registers:\n"); + + for (i = 0; i < num_mce_regs; i++) + printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name, + in_le32(mce_regs[i].addr)); + + if (dump_slb) { + unsigned long e, v; + int i; + + printk(KERN_ERR "slb contents:\n"); + for (i = 0; i < SLB_NUM_ENTRIES; i++) { + asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i)); + asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i)); + printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v); + } + } + + /* SRR1[62] is from MSR[62] if recoverable, so pass that back */ return !!(srr1 & 0x2); } diff -puN arch/powerpc/platforms/powermac/bootx_init.c~git-powerpc arch/powerpc/platforms/powermac/bootx_init.c --- a/arch/powerpc/platforms/powermac/bootx_init.c~git-powerpc +++ a/arch/powerpc/platforms/powermac/bootx_init.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff -puN arch/powerpc/platforms/powermac/low_i2c.c~git-powerpc arch/powerpc/platforms/powermac/low_i2c.c --- a/arch/powerpc/platforms/powermac/low_i2c.c~git-powerpc +++ a/arch/powerpc/platforms/powermac/low_i2c.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include #include diff -puN arch/powerpc/platforms/powermac/pci.c~git-powerpc arch/powerpc/platforms/powermac/pci.c --- a/arch/powerpc/platforms/powermac/pci.c~git-powerpc +++ a/arch/powerpc/platforms/powermac/pci.c @@ -209,15 +209,12 @@ static int macrisc_write_config(struct p switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -225,8 +222,8 @@ static int macrisc_write_config(struct p static struct pci_ops macrisc_pci_ops = { - macrisc_read_config, - macrisc_write_config + .read = macrisc_read_config, + .write = macrisc_write_config, }; #ifdef CONFIG_PPC32 @@ -280,8 +277,8 @@ chaos_write_config(struct pci_bus *bus, static struct pci_ops chaos_pci_ops = { - chaos_read_config, - chaos_write_config + .read = chaos_read_config, + .write = chaos_write_config, }; static void __init setup_chaos(struct pci_controller *hose, @@ -440,15 +437,12 @@ static int u3_ht_write_config(struct pci switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32((u32 __iomem *)addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -456,8 +450,8 @@ static int u3_ht_write_config(struct pci static struct pci_ops u3_ht_pci_ops = { - u3_ht_read_config, - u3_ht_write_config + .read = u3_ht_read_config, + .write = u3_ht_write_config, }; #define U4_PCIE_CFA0(devfn, off) \ @@ -545,15 +539,12 @@ static int u4_pcie_write_config(struct p switch (len) { case 1: out_8(addr, val); - (void) in_8(addr); break; case 2: out_le16(addr, val); - (void) in_le16(addr); break; default: out_le32(addr, val); - (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; @@ -561,8 +552,8 @@ static int u4_pcie_write_config(struct p static struct pci_ops u4_pcie_pci_ops = { - u4_pcie_read_config, - u4_pcie_write_config + .read = u4_pcie_read_config, + .write = u4_pcie_write_config, }; #endif /* CONFIG_PPC64 */ diff -puN arch/powerpc/platforms/powermac/pic.c~git-powerpc arch/powerpc/platforms/powermac/pic.c --- a/arch/powerpc/platforms/powermac/pic.c~git-powerpc +++ a/arch/powerpc/platforms/powermac/pic.c @@ -384,7 +384,7 @@ static void __init pmac_pic_probe_oldsty /* * Allocate an irq host */ - pmac_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, max_irqs, + pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs, &pmac_pic_host_ops, max_irqs); BUG_ON(pmac_pic_host == NULL); diff -puN arch/powerpc/platforms/powermac/pmac.h~git-powerpc arch/powerpc/platforms/powermac/pmac.h --- a/arch/powerpc/platforms/powermac/pmac.h~git-powerpc +++ a/arch/powerpc/platforms/powermac/pmac.h @@ -22,9 +22,6 @@ extern void pmac_read_rtc_time(void); extern void pmac_calibrate_decr(void); extern void pmac_pci_irq_fixup(struct pci_dev *); extern void pmac_pci_init(void); -extern unsigned long pmac_ide_get_base(int index); -extern void pmac_ide_init_hwif_ports(hw_regs_t *hw, - unsigned long data_port, unsigned long ctrl_port, int *irq); extern void pmac_nvram_update(void); extern unsigned char pmac_nvram_read_byte(int addr); @@ -33,7 +30,6 @@ extern int pmac_pci_enable_device_hook(s extern void pmac_pcibios_after_init(void); extern int of_show_percpuinfo(struct seq_file *m, int i); -extern void pmac_pci_init(void); extern void pmac_setup_pci_dma(void); extern void pmac_check_ht_link(void); diff -puN arch/powerpc/platforms/powermac/udbg_adb.c~git-powerpc arch/powerpc/platforms/powermac/udbg_adb.c --- a/arch/powerpc/platforms/powermac/udbg_adb.c~git-powerpc +++ a/arch/powerpc/platforms/powermac/udbg_adb.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -150,7 +149,7 @@ static void udbg_adb_putc(char c) return udbg_adb_old_putc(c); } -void udbg_adb_init_early(void) +void __init udbg_adb_init_early(void) { #ifdef CONFIG_BOOTX_TEXT if (btext_find_display(1) == 0) { @@ -160,7 +159,7 @@ void udbg_adb_init_early(void) #endif } -int udbg_adb_init(int force_btext) +int __init udbg_adb_init(int force_btext) { struct device_node *np; diff -puN arch/powerpc/platforms/ps3/device-init.c~git-powerpc arch/powerpc/platforms/ps3/device-init.c --- a/arch/powerpc/platforms/ps3/device-init.c~git-powerpc +++ a/arch/powerpc/platforms/ps3/device-init.c @@ -297,8 +297,8 @@ static int ps3_storage_wait_for_device(c u64 dev_port; } *notify_event; - pr_debug(" -> %s:%u: bus_id %u, dev_id %u, dev_type %u\n", __func__, - __LINE__, repo->bus_id, repo->dev_id, repo->dev_type); + pr_debug(" -> %s:%u: (%u:%u:%u)\n", __func__, __LINE__, repo->bus_id, + repo->dev_id, repo->dev_type); buf = kzalloc(512, GFP_KERNEL); if (!buf) @@ -359,6 +359,11 @@ static int ps3_storage_wait_for_device(c break; } + pr_debug("%s:%d: notify event (%u:%u:%u): event_type 0x%lx, " + "port %lu\n", __func__, __LINE__, repo->bus_index, + repo->dev_index, repo->dev_type, + notify_event->event_type, notify_event->dev_port); + if (notify_event->event_type != notify_region_probe || notify_event->bus_id != repo->bus_id) { pr_debug("%s:%u: bad notify_event: event %lu, " @@ -370,8 +375,9 @@ static int ps3_storage_wait_for_device(c if (notify_event->dev_id == repo->dev_id && notify_event->dev_type == repo->dev_type) { - pr_debug("%s:%u: device ready: dev_id %u\n", __func__, - __LINE__, repo->dev_id); + pr_debug("%s:%u: device ready (%u:%u:%u)\n", __func__, + __LINE__, repo->bus_index, repo->dev_index, + repo->dev_type); error = 0; break; } @@ -412,9 +418,10 @@ static int ps3_setup_storage_dev(const s return -ENODEV; } - pr_debug("%s:%u: index %u:%u: port %lu blk_size %lu num_blocks %lu " + pr_debug("%s:%u: (%u:%u:%u): port %lu blk_size %lu num_blocks %lu " "num_regions %u\n", __func__, __LINE__, repo->bus_index, - repo->dev_index, port, blk_size, num_blocks, num_regions); + repo->dev_index, repo->dev_type, port, blk_size, num_blocks, + num_regions); p = kzalloc(sizeof(struct ps3_storage_device) + num_regions * sizeof(struct ps3_storage_region), @@ -681,8 +688,9 @@ static int ps3_probe_thread(void *data) pr_debug("%s:%u: find device error.\n", __func__, __LINE__); else { - pr_debug("%s:%u: found device\n", __func__, - __LINE__); + pr_debug("%s:%u: found device (%u:%u:%u)\n", + __func__, __LINE__, repo->bus_index, + repo->dev_index, repo->dev_type); ps3_register_repository_device(repo); ps3_repository_bump_device(repo); ms = 250; diff -puN arch/powerpc/platforms/ps3/interrupt.c~git-powerpc arch/powerpc/platforms/ps3/interrupt.c --- a/arch/powerpc/platforms/ps3/interrupt.c~git-powerpc +++ a/arch/powerpc/platforms/ps3/interrupt.c @@ -673,9 +673,16 @@ static int ps3_host_map(struct irq_host return 0; } +static int ps3_host_match(struct irq_host *h, struct device_node *np) +{ + /* Match all */ + return 1; +} + static struct irq_host_ops ps3_host_ops = { .map = ps3_host_map, .unmap = ps3_host_unmap, + .match = ps3_host_match, }; void __init ps3_register_ipi_debug_brk(unsigned int cpu, unsigned int virq) @@ -726,7 +733,7 @@ void __init ps3_init_IRQ(void) unsigned cpu; struct irq_host *host; - host = irq_alloc_host(IRQ_HOST_MAP_NOMAP, 0, &ps3_host_ops, + host = irq_alloc_host(NULL, IRQ_HOST_MAP_NOMAP, 0, &ps3_host_ops, PS3_INVALID_OUTLET); irq_set_default_host(host); irq_set_virq_count(PS3_PLUG_MAX + 1); diff -puN arch/powerpc/platforms/ps3/platform.h~git-powerpc arch/powerpc/platforms/ps3/platform.h --- a/arch/powerpc/platforms/ps3/platform.h~git-powerpc +++ a/arch/powerpc/platforms/ps3/platform.h @@ -47,7 +47,11 @@ void __init ps3_register_ipi_debug_brk(u /* smp */ void smp_init_ps3(void); +#ifdef CONFIG_SMP void ps3_smp_cleanup_cpu(int cpu); +#else +static inline void ps3_smp_cleanup_cpu(int cpu) { } +#endif /* time */ diff -puN arch/powerpc/platforms/pseries/eeh.c~git-powerpc arch/powerpc/platforms/pseries/eeh.c --- a/arch/powerpc/platforms/pseries/eeh.c~git-powerpc +++ a/arch/powerpc/platforms/pseries/eeh.c @@ -169,6 +169,8 @@ static void rtas_slot_error_detail(struc */ static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len) { + struct device_node *dn; + struct pci_dev *dev = pdn->pcidev; u32 cfg; int cap, i; int n = 0; @@ -184,6 +186,17 @@ static size_t gather_pci_data(struct pci n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); + /* Gather bridge-specific registers */ + if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { + rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg); + n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); + printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); + + rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg); + n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); + printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); + } + /* Dump out the PCI-X command and status regs */ cap = pci_find_capability(pdn->pcidev, PCI_CAP_ID_PCIX); if (cap) { @@ -209,7 +222,7 @@ static size_t gather_pci_data(struct pci printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); } - cap = pci_find_ext_capability(pdn->pcidev,PCI_EXT_CAP_ID_ERR); + cap = pci_find_ext_capability(pdn->pcidev, PCI_EXT_CAP_ID_ERR); if (cap) { n += scnprintf(buf+n, len-n, "pci-e AER:\n"); printk(KERN_WARNING @@ -222,6 +235,18 @@ static size_t gather_pci_data(struct pci } } } + + /* Gather status on devices under the bridge */ + if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { + dn = pdn->node->child; + while (dn) { + pdn = PCI_DN(dn); + if (pdn) + n += gather_pci_data(pdn, buf+n, len-n); + dn = dn->sibling; + } + } + return n; } @@ -750,12 +775,12 @@ int rtas_set_slot_reset(struct pci_dn *p return 0; if (rc < 0) { - printk (KERN_ERR "EEH: unrecoverable slot failure %s\n", - pdn->node->full_name); + printk(KERN_ERR "EEH: unrecoverable slot failure %s\n", + pdn->node->full_name); return -1; } - printk (KERN_ERR "EEH: bus reset %d failed on slot %s\n", - i+1, pdn->node->full_name); + printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n", + i+1, pdn->node->full_name, rc); } return -1; @@ -944,23 +969,6 @@ static void *early_enable_eeh(struct dev } pdn->class_code = *class_code; - /* - * Now decide if we are going to "Disable" EEH checking - * for this device. We still run with the EEH hardware active, - * but we won't be checking for ff's. This means a driver - * could return bad data (very bad!), an interrupt handler could - * hang waiting on status bits that won't change, etc. - * But there are a few cases like display devices that make sense. - */ - enable = 1; /* i.e. we will do checking */ -#if 0 - if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY) - enable = 0; -#endif - - if (!enable) - pdn->eeh_mode |= EEH_MODE_NOCHECK; - /* Ok... see if this device supports EEH. Some do, some don't, * and the only way to find out is to check each and every one. */ regs = of_get_property(dn, "reg", NULL); diff -puN arch/powerpc/platforms/pseries/eeh_cache.c~git-powerpc arch/powerpc/platforms/pseries/eeh_cache.c --- a/arch/powerpc/platforms/pseries/eeh_cache.c~git-powerpc +++ a/arch/powerpc/platforms/pseries/eeh_cache.c @@ -225,6 +225,10 @@ void pci_addr_cache_insert_device(struct { unsigned long flags; + /* Ignore PCI bridges */ + if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) + return; + spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); __pci_addr_cache_insert_device(dev); spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); @@ -285,16 +289,13 @@ void __init pci_addr_cache_build(void) spin_lock_init(&pci_io_addr_cache_root.piar_lock); while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - /* Ignore PCI bridges */ - if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) - continue; pci_addr_cache_insert_device(dev); dn = pci_device_to_OF_node(dev); if (!dn) continue; - pci_dev_get (dev); /* matching put is in eeh_remove_device() */ + pci_dev_get(dev); /* matching put is in eeh_remove_device() */ PCI_DN(dn)->pcidev = dev; eeh_sysfs_add_device(dev); diff -puN arch/powerpc/platforms/pseries/lpar.c~git-powerpc arch/powerpc/platforms/pseries/lpar.c --- a/arch/powerpc/platforms/pseries/lpar.c~git-powerpc +++ a/arch/powerpc/platforms/pseries/lpar.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include diff -puN arch/powerpc/platforms/pseries/rtasd.c~git-powerpc arch/powerpc/platforms/pseries/rtasd.c --- a/arch/powerpc/platforms/pseries/rtasd.c~git-powerpc +++ a/arch/powerpc/platforms/pseries/rtasd.c @@ -44,15 +44,19 @@ static unsigned long rtas_log_start; static unsigned long rtas_log_size; static int surveillance_timeout = -1; -static unsigned int rtas_event_scan_rate; static unsigned int rtas_error_log_max; static unsigned int rtas_error_log_buffer_max; +/* RTAS service tokens */ +static unsigned int event_scan; +static unsigned int rtas_event_scan_rate; + static int full_rtas_msgs = 0; -extern int no_logging; +/* Stop logging to nvram after first fatal error */ +static int no_more_logging; -volatile int error_log_cnt = 0; +static int error_log_cnt; /* * Since we use 32 bit RTAS, the physical address of this must be below @@ -61,8 +65,6 @@ volatile int error_log_cnt = 0; */ static unsigned char logdata[RTAS_ERROR_LOG_MAX]; -static int get_eventscan_parms(void); - static char *rtas_type[] = { "Unknown", "Retry", "TCE Error", "Internal Device Failure", "Timeout", "Data Parity", "Address Parity", "Cache Parity", @@ -166,9 +168,9 @@ static int log_rtas_len(char * buf) len += err->extended_log_length; } - if (rtas_error_log_max == 0) { - get_eventscan_parms(); - } + if (rtas_error_log_max == 0) + rtas_error_log_max = rtas_get_error_log_max(); + if (len > rtas_error_log_max) len = rtas_error_log_max; @@ -215,8 +217,8 @@ void pSeries_log_error(char *buf, unsign } /* Write error to NVRAM */ - if (!no_logging && !(err_type & ERR_FLAG_BOOT)) - nvram_write_error_log(buf, len, err_type); + if (!no_more_logging && !(err_type & ERR_FLAG_BOOT)) + nvram_write_error_log(buf, len, err_type, error_log_cnt); /* * rtas errors can occur during boot, and we do want to capture @@ -227,8 +229,8 @@ void pSeries_log_error(char *buf, unsign printk_log_rtas(buf, len); /* Check to see if we need to or have stopped logging */ - if (fatal || no_logging) { - no_logging = 1; + if (fatal || no_more_logging) { + no_more_logging = 1; spin_unlock_irqrestore(&rtasd_log_lock, s); return; } @@ -300,7 +302,7 @@ static ssize_t rtas_log_read(struct file spin_lock_irqsave(&rtasd_log_lock, s); /* if it's 0, then we know we got the last one (the one in NVRAM) */ - if (rtas_log_size == 0 && !no_logging) + if (rtas_log_size == 0 && !no_more_logging) nvram_clear_error_log(); spin_unlock_irqrestore(&rtasd_log_lock, s); @@ -356,32 +358,7 @@ static int enable_surveillance(int timeo return -1; } -static int get_eventscan_parms(void) -{ - struct device_node *node; - const int *ip; - - node = of_find_node_by_path("/rtas"); - - ip = of_get_property(node, "rtas-event-scan-rate", NULL); - if (ip == NULL) { - printk(KERN_ERR "rtasd: no rtas-event-scan-rate\n"); - of_node_put(node); - return -1; - } - rtas_event_scan_rate = *ip; - DEBUG("rtas-event-scan-rate %d\n", rtas_event_scan_rate); - - /* Make room for the sequence number */ - rtas_error_log_max = rtas_get_error_log_max(); - rtas_error_log_buffer_max = rtas_error_log_max + sizeof(int); - - of_node_put(node); - - return 0; -} - -static void do_event_scan(int event_scan) +static void do_event_scan(void) { int error; do { @@ -408,7 +385,7 @@ static void do_event_scan_all_cpus(long cpu = first_cpu(cpu_online_map); for (;;) { set_cpus_allowed(current, cpumask_of_cpu(cpu)); - do_event_scan(rtas_token("event-scan")); + do_event_scan(); set_cpus_allowed(current, CPU_MASK_ALL); /* Drop hotplug lock, and sleep for the specified delay */ @@ -426,31 +403,17 @@ static void do_event_scan_all_cpus(long static int rtasd(void *unused) { unsigned int err_type; - int event_scan = rtas_token("event-scan"); int rc; daemonize("rtasd"); - if (event_scan == RTAS_UNKNOWN_SERVICE || get_eventscan_parms() == -1) - goto error; - - rtas_log_buf = vmalloc(rtas_error_log_buffer_max*LOG_NUMBER); - if (!rtas_log_buf) { - printk(KERN_ERR "rtasd: no memory\n"); - goto error; - } - printk(KERN_DEBUG "RTAS daemon started\n"); - DEBUG("will sleep for %d milliseconds\n", (30000/rtas_event_scan_rate)); /* See if we have any error stored in NVRAM */ memset(logdata, 0, rtas_error_log_max); - - rc = nvram_read_error_log(logdata, rtas_error_log_max, &err_type); - - /* We can use rtas_log_buf now */ - no_logging = 0; + rc = nvram_read_error_log(logdata, rtas_error_log_max, + &err_type, &error_log_cnt); if (!rc) { if (err_type != ERR_FLAG_ALREADY_LOGGED) { @@ -473,8 +436,6 @@ static int rtasd(void *unused) for (;;) do_event_scan_all_cpus(30000/rtas_event_scan_rate); -error: - /* Should delete proc entries */ return -EINVAL; } @@ -486,11 +447,28 @@ static int __init rtas_init(void) return 0; /* No RTAS */ - if (rtas_token("event-scan") == RTAS_UNKNOWN_SERVICE) { + event_scan = rtas_token("event-scan"); + if (event_scan == RTAS_UNKNOWN_SERVICE) { printk(KERN_DEBUG "rtasd: no event-scan on system\n"); return -ENODEV; } + rtas_event_scan_rate = rtas_token("rtas-event-scan-rate"); + if (rtas_event_scan_rate == RTAS_UNKNOWN_SERVICE) { + printk(KERN_ERR "rtasd: no rtas-event-scan-rate on system\n"); + return -ENODEV; + } + + /* Make room for the sequence number */ + rtas_error_log_max = rtas_get_error_log_max(); + rtas_error_log_buffer_max = rtas_error_log_max + sizeof(int); + + rtas_log_buf = vmalloc(rtas_error_log_buffer_max*LOG_NUMBER); + if (!rtas_log_buf) { + printk(KERN_ERR "rtasd: no memory\n"); + return -ENOMEM; + } + entry = create_proc_entry("ppc64/rtas/error_log", S_IRUSR, NULL); if (entry) entry->proc_fops = &proc_rtas_log_operations; diff -puN arch/powerpc/platforms/pseries/xics.c~git-powerpc arch/powerpc/platforms/pseries/xics.c --- a/arch/powerpc/platforms/pseries/xics.c~git-powerpc +++ a/arch/powerpc/platforms/pseries/xics.c @@ -540,7 +540,7 @@ static void __init xics_init_host(void) ops = &xics_host_lpar_ops; else ops = &xics_host_direct_ops; - xics_host = irq_alloc_host(IRQ_HOST_MAP_TREE, 0, ops, + xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, ops, XICS_IRQ_SPURIOUS); BUG_ON(xics_host == NULL); irq_set_default_host(xics_host); diff -puN arch/powerpc/sysdev/commproc.c~git-powerpc arch/powerpc/sysdev/commproc.c --- a/arch/powerpc/sysdev/commproc.c~git-powerpc +++ a/arch/powerpc/sysdev/commproc.c @@ -45,12 +45,11 @@ #define CPM_MAP_SIZE (0x4000) static void m8xx_cpm_dpinit(void); -static uint host_buffer; /* One page of host buffer */ -static uint host_end; /* end + 1 */ -cpm8xx_t *cpmp; /* Pointer to comm processor space */ -cpic8xx_t *cpic_reg; +static uint host_buffer; /* One page of host buffer */ +static uint host_end; /* end + 1 */ +cpm8xx_t *cpmp; /* Pointer to comm processor space */ +cpic8xx_t *cpic_reg; -static struct device_node *cpm_pic_node; static struct irq_host *cpm_pic_host; static void cpm_mask_irq(unsigned int irq) @@ -95,11 +94,6 @@ int cpm_get_irq(void) return irq_linear_revmap(cpm_pic_host, cpm_vec); } -static int cpm_pic_host_match(struct irq_host *h, struct device_node *node) -{ - return cpm_pic_node == node; -} - static int cpm_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { @@ -115,7 +109,7 @@ static int cpm_pic_host_map(struct irq_h * and return. This is a no-op function so we don't need any special * tests in the interrupt handler. */ -static irqreturn_t cpm_error_interrupt(int irq, void *dev) +static irqreturn_t cpm_error_interrupt(int irq, void *dev) { return IRQ_HANDLED; } @@ -127,7 +121,6 @@ static struct irqaction cpm_error_irqact }; static struct irq_host_ops cpm_pic_host_ops = { - .match = cpm_pic_host_match, .map = cpm_pic_host_map, }; @@ -165,9 +158,8 @@ unsigned int cpm_pic_init(void) out_be32(&cpic_reg->cpic_cimr, 0); - cpm_pic_node = of_node_get(np); - - cpm_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm_pic_host_ops, 64); + cpm_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR, + 64, &cpm_pic_host_ops, 64); if (cpm_pic_host == NULL) { printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); sirq = NO_IRQ; @@ -181,7 +173,7 @@ unsigned int cpm_pic_init(void) printk(KERN_ERR "CPM PIC init: can not find cpm node\n"); goto end; } - eirq= irq_of_parse_and_map(np, 0); + eirq = irq_of_parse_and_map(np, 0); if (eirq == NO_IRQ) goto end; @@ -197,15 +189,15 @@ end: void cpm_reset(void) { - cpm8xx_t *commproc; - sysconf8xx_t *siu_conf; + cpm8xx_t *commproc; + sysconf8xx_t *siu_conf; commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); #ifdef CONFIG_UCODE_PATCH /* Perform a reset. */ - out_be16(&commproc->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); + out_be16(&commproc->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); /* Wait for it. */ @@ -307,7 +299,7 @@ static rh_block_t cpm_boot_dpmem_rh_bloc static rh_info_t cpm_dpmem_info; #define CPM_DPMEM_ALIGNMENT 8 -static u8* dpram_vbase; +static u8 *dpram_vbase; static uint dpram_pbase; void m8xx_cpm_dpinit(void) diff -puN arch/powerpc/sysdev/cpm2_common.c~git-powerpc arch/powerpc/sysdev/cpm2_common.c --- a/arch/powerpc/sysdev/cpm2_common.c~git-powerpc +++ a/arch/powerpc/sysdev/cpm2_common.c @@ -201,7 +201,7 @@ int cpm2_clk_setup(enum cpm_clk_target t } if (mode == CPM_CLK_RX) - shift +=3; + shift += 3; for (i=0; i<24; i++) { if (clk_map[i][0] == target && clk_map[i][1] == clock) { diff -puN arch/powerpc/sysdev/cpm2_pic.c~git-powerpc arch/powerpc/sysdev/cpm2_pic.c --- a/arch/powerpc/sysdev/cpm2_pic.c~git-powerpc +++ a/arch/powerpc/sysdev/cpm2_pic.c @@ -50,7 +50,6 @@ static intctl_cpm2_t *cpm2_intctl; -static struct device_node *cpm2_pic_node; static struct irq_host *cpm2_pic_host; #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; @@ -206,11 +205,6 @@ unsigned int cpm2_get_irq(void) return irq_linear_revmap(cpm2_pic_host, irq); } -static int cpm2_pic_host_match(struct irq_host *h, struct device_node *node) -{ - return cpm2_pic_node == node; -} - static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { @@ -234,7 +228,6 @@ static int cpm2_pic_host_xlate(struct ir } static struct irq_host_ops cpm2_pic_host_ops = { - .match = cpm2_pic_host_match, .map = cpm2_pic_host_map, .xlate = cpm2_pic_host_xlate, }; @@ -273,8 +266,8 @@ void cpm2_pic_init(struct device_node *n out_be32(&cpm2_intctl->ic_scprrl, 0x05309770); /* create a legacy host */ - cpm2_pic_node = of_node_get(node); - cpm2_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm2_pic_host_ops, 64); + cpm2_pic_host = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, + 64, &cpm2_pic_host_ops, 64); if (cpm2_pic_host == NULL) { printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); return; diff -puN arch/powerpc/sysdev/dart_iommu.c~git-powerpc arch/powerpc/sysdev/dart_iommu.c --- a/arch/powerpc/sysdev/dart_iommu.c~git-powerpc +++ a/arch/powerpc/sysdev/dart_iommu.c @@ -204,7 +204,7 @@ static void dart_free(struct iommu_table } -static int dart_init(struct device_node *dart_node) +static int __init dart_init(struct device_node *dart_node) { unsigned int i; unsigned long tmp, base, size; @@ -313,7 +313,7 @@ static void pci_dma_bus_setup_dart(struc PCI_DN(dn)->iommu_table = &iommu_table_dart; } -void iommu_init_early_dart(void) +void __init iommu_init_early_dart(void) { struct device_node *dn; diff -puN arch/powerpc/sysdev/dcr.c~git-powerpc arch/powerpc/sysdev/dcr.c --- a/arch/powerpc/sysdev/dcr.c~git-powerpc +++ a/arch/powerpc/sysdev/dcr.c @@ -33,6 +33,7 @@ unsigned int dcr_resource_start(struct d return dr[index * 2]; } +EXPORT_SYMBOL_GPL(dcr_resource_start); unsigned int dcr_resource_len(struct device_node *np, unsigned int index) { @@ -44,6 +45,7 @@ unsigned int dcr_resource_len(struct dev return dr[index * 2 + 1]; } +EXPORT_SYMBOL_GPL(dcr_resource_len); #ifndef CONFIG_PPC_DCR_NATIVE @@ -122,6 +124,7 @@ dcr_host_t dcr_map(struct device_node *d ret.token -= dcr_n * ret.stride; return ret; } +EXPORT_SYMBOL_GPL(dcr_map); void dcr_unmap(dcr_host_t host, unsigned int dcr_n, unsigned int dcr_c) { @@ -133,5 +136,6 @@ void dcr_unmap(dcr_host_t host, unsigned iounmap(h.token); h.token = NULL; } +EXPORT_SYMBOL_GPL(dcr_unmap); #endif /* !defined(CONFIG_PPC_DCR_NATIVE) */ diff -puN arch/powerpc/sysdev/fsl_pci.c~git-powerpc arch/powerpc/sysdev/fsl_pci.c --- a/arch/powerpc/sysdev/fsl_pci.c~git-powerpc +++ a/arch/powerpc/sysdev/fsl_pci.c @@ -255,5 +255,7 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVI DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transparent) +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); diff -puN arch/powerpc/sysdev/fsl_soc.c~git-powerpc arch/powerpc/sysdev/fsl_soc.c --- a/arch/powerpc/sysdev/fsl_soc.c~git-powerpc +++ a/arch/powerpc/sysdev/fsl_soc.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -52,13 +53,13 @@ phys_addr_t get_immrbase(void) soc = of_find_node_by_type(NULL, "soc"); if (soc) { - unsigned int size; + int size; const void *prop = of_get_property(soc, "reg", &size); if (prop) immrbase = of_translate_address(soc, prop); of_node_put(soc); - }; + } return immrbase; } @@ -76,16 +77,23 @@ u32 get_brgfreq(void) if (brgfreq != -1) return brgfreq; - node = of_find_node_by_type(NULL, "cpm"); + node = of_find_compatible_node(NULL, NULL, "fsl,cpm1"); + if (!node) + node = of_find_compatible_node(NULL, NULL, "fsl,cpm2"); + if (!node) + node = of_find_node_by_type(NULL, "cpm"); if (node) { - unsigned int size; - const unsigned int *prop = of_get_property(node, - "brg-frequency", &size); + int size; + const unsigned int *prop; - if (prop) + prop = of_get_property(node, "fsl,brg-frequency", &size); + if (!prop) + prop = of_get_property(node, "brg-frequency", &size); + if (prop && size == 4) brgfreq = *prop; + of_node_put(node); - }; + } return brgfreq; } @@ -103,14 +111,14 @@ u32 get_baudrate(void) node = of_find_node_by_type(NULL, "serial"); if (node) { - unsigned int size; + int size; const unsigned int *prop = of_get_property(node, "current-speed", &size); if (prop) fs_baudrate = *prop; of_node_put(node); - }; + } return fs_baudrate; } @@ -321,21 +329,26 @@ static struct i2c_driver_device i2c_devi {"ricoh,rv5c387a", "rtc-rs5c372", "rv5c387a",}, }; -static int __init of_find_i2c_driver(struct device_node *node, struct i2c_board_info *info) +static int __init of_find_i2c_driver(struct device_node *node, + struct i2c_board_info *info) { int i; for (i = 0; i < ARRAY_SIZE(i2c_devices); i++) { if (!of_device_is_compatible(node, i2c_devices[i].of_device)) continue; - strncpy(info->driver_name, i2c_devices[i].i2c_driver, KOBJ_NAME_LEN); - strncpy(info->type, i2c_devices[i].i2c_type, I2C_NAME_SIZE); + if (strlcpy(info->driver_name, i2c_devices[i].i2c_driver, + KOBJ_NAME_LEN) >= KOBJ_NAME_LEN || + strlcpy(info->type, i2c_devices[i].i2c_type, + I2C_NAME_SIZE) >= I2C_NAME_SIZE) + return -ENOMEM; return 0; } return -ENODEV; } -static void __init of_register_i2c_devices(struct device_node *adap_node, int bus_num) +static void __init of_register_i2c_devices(struct device_node *adap_node, + int bus_num) { struct device_node *node = NULL; @@ -1187,3 +1200,89 @@ err: arch_initcall(cpm_smc_uart_of_init); #endif /* CONFIG_8xx */ + +int __init fsl_spi_init(struct spi_board_info *board_infos, + unsigned int num_board_infos, + void (*activate_cs)(u8 cs, u8 polarity), + void (*deactivate_cs)(u8 cs, u8 polarity)) +{ + struct device_node *np; + unsigned int i; + const u32 *sysclk; + + np = of_find_node_by_type(NULL, "qe"); + if (!np) + return -ENODEV; + + sysclk = of_get_property(np, "bus-frequency", NULL); + if (!sysclk) + return -ENODEV; + + for (np = NULL, i = 1; + (np = of_find_compatible_node(np, "spi", "fsl_spi")) != NULL; + i++) { + int ret = 0; + unsigned int j; + const void *prop; + struct resource res[2]; + struct platform_device *pdev; + struct fsl_spi_platform_data pdata = { + .activate_cs = activate_cs, + .deactivate_cs = deactivate_cs, + }; + + memset(res, 0, sizeof(res)); + + pdata.sysclk = *sysclk; + + prop = of_get_property(np, "reg", NULL); + if (!prop) + goto err; + pdata.bus_num = *(u32 *)prop; + + prop = of_get_property(np, "mode", NULL); + if (prop && !strcmp(prop, "cpu-qe")) + pdata.qe_mode = 1; + + for (j = 0; j < num_board_infos; j++) { + if (board_infos[j].bus_num == pdata.bus_num) + pdata.max_chipselect++; + } + + if (!pdata.max_chipselect) + goto err; + + ret = of_address_to_resource(np, 0, &res[0]); + if (ret) + goto err; + + ret = of_irq_to_resource(np, 0, &res[1]); + if (ret == NO_IRQ) + goto err; + + pdev = platform_device_alloc("mpc83xx_spi", i); + if (!pdev) + goto err; + + ret = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (ret) + goto unreg; + + ret = platform_device_add_resources(pdev, res, + ARRAY_SIZE(res)); + if (ret) + goto unreg; + + ret = platform_device_register(pdev); + if (ret) + goto unreg; + + continue; +unreg: + platform_device_del(pdev); +err: + continue; + } + + return spi_register_board_info(board_infos, num_board_infos); +} diff -puN arch/powerpc/sysdev/fsl_soc.h~git-powerpc arch/powerpc/sysdev/fsl_soc.h --- a/arch/powerpc/sysdev/fsl_soc.h~git-powerpc +++ a/arch/powerpc/sysdev/fsl_soc.h @@ -8,5 +8,12 @@ extern phys_addr_t get_immrbase(void); extern u32 get_brgfreq(void); extern u32 get_baudrate(void); +struct spi_board_info; + +extern int fsl_spi_init(struct spi_board_info *board_infos, + unsigned int num_board_infos, + void (*activate_cs)(u8 cs, u8 polarity), + void (*deactivate_cs)(u8 cs, u8 polarity)); + #endif #endif diff -puN arch/powerpc/sysdev/i8259.c~git-powerpc arch/powerpc/sysdev/i8259.c --- a/arch/powerpc/sysdev/i8259.c~git-powerpc +++ a/arch/powerpc/sysdev/i8259.c @@ -25,7 +25,6 @@ static unsigned char cached_8259[2] = { static DEFINE_SPINLOCK(i8259_lock); -static struct device_node *i8259_node; static struct irq_host *i8259_host; /* @@ -165,7 +164,7 @@ static struct resource pic_edgectrl_iore static int i8259_host_match(struct irq_host *h, struct device_node *node) { - return i8259_node == NULL || i8259_node == node; + return h->of_node == NULL || h->of_node == node; } static int i8259_host_map(struct irq_host *h, unsigned int virq, @@ -276,9 +275,8 @@ void i8259_init(struct device_node *node spin_unlock_irqrestore(&i8259_lock, flags); /* create a legacy host */ - if (node) - i8259_node = of_node_get(node); - i8259_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &i8259_host_ops, 0); + i8259_host = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LEGACY, + 0, &i8259_host_ops, 0); if (i8259_host == NULL) { printk(KERN_ERR "i8259: failed to allocate irq host !\n"); return; diff -puN arch/powerpc/sysdev/indirect_pci.c~git-powerpc arch/powerpc/sysdev/indirect_pci.c --- a/arch/powerpc/sysdev/indirect_pci.c~git-powerpc +++ a/arch/powerpc/sysdev/indirect_pci.c @@ -144,8 +144,8 @@ indirect_write_config(struct pci_bus *bu static struct pci_ops indirect_pci_ops = { - indirect_read_config, - indirect_write_config + .read = indirect_read_config, + .write = indirect_write_config, }; void __init diff -puN arch/powerpc/sysdev/ipic.c~git-powerpc arch/powerpc/sysdev/ipic.c --- a/arch/powerpc/sysdev/ipic.c~git-powerpc +++ a/arch/powerpc/sysdev/ipic.c @@ -511,10 +511,8 @@ static struct irq_chip ipic_irq_chip = { static int ipic_host_match(struct irq_host *h, struct device_node *node) { - struct ipic *ipic = h->host_data; - /* Exact match, unless ipic node is NULL */ - return ipic->of_node == NULL || ipic->of_node == node; + return h->of_node == NULL || h->of_node == node; } static int ipic_host_map(struct irq_host *h, unsigned int virq, @@ -568,9 +566,8 @@ struct ipic * __init ipic_init(struct de return NULL; memset(ipic, 0, sizeof(struct ipic)); - ipic->of_node = of_node_get(node); - ipic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, + ipic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, NR_IPIC_INTS, &ipic_host_ops, 0); if (ipic->irqhost == NULL) { diff -puN arch/powerpc/sysdev/ipic.h~git-powerpc arch/powerpc/sysdev/ipic.h --- a/arch/powerpc/sysdev/ipic.h~git-powerpc +++ a/arch/powerpc/sysdev/ipic.h @@ -48,9 +48,6 @@ struct ipic { /* The "linux" controller struct */ struct irq_chip hc_irq; - - /* The device node of the interrupt controller */ - struct device_node *of_node; }; struct ipic_info { diff -puN arch/powerpc/sysdev/mpc8xx_pic.c~git-powerpc arch/powerpc/sysdev/mpc8xx_pic.c --- a/arch/powerpc/sysdev/mpc8xx_pic.c~git-powerpc +++ a/arch/powerpc/sysdev/mpc8xx_pic.c @@ -19,7 +19,6 @@ extern int cpm_get_irq(struct pt_regs *regs); -static struct device_node *mpc8xx_pic_node; static struct irq_host *mpc8xx_pic_host; #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; @@ -120,11 +119,6 @@ unsigned int mpc8xx_get_irq(void) } -static int mpc8xx_pic_host_match(struct irq_host *h, struct device_node *node) -{ - return mpc8xx_pic_node == node; -} - static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { @@ -158,7 +152,6 @@ static int mpc8xx_pic_host_xlate(struct static struct irq_host_ops mpc8xx_pic_host_ops = { - .match = mpc8xx_pic_host_match, .map = mpc8xx_pic_host_map, .xlate = mpc8xx_pic_host_xlate, }; @@ -176,22 +169,24 @@ int mpc8xx_pic_init(void) return -ENOMEM; } - mpc8xx_pic_node = of_node_get(np); - ret = of_address_to_resource(np, 0, &res); - of_node_put(np); if (ret) - return ret; + goto out; siu_reg = (void *)ioremap(res.start, res.end - res.start + 1); - if (siu_reg == NULL) - return -EINVAL; + if (siu_reg == NULL) { + ret = -EINVAL; + goto out; + } - mpc8xx_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &mpc8xx_pic_host_ops, 64); + mpc8xx_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR, + 64, &mpc8xx_pic_host_ops, 64); if (mpc8xx_pic_host == NULL) { printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n"); ret = -ENOMEM; } +out: + of_node_put(np); return ret; } diff -puN arch/powerpc/sysdev/mpic.c~git-powerpc arch/powerpc/sysdev/mpic.c --- a/arch/powerpc/sysdev/mpic.c~git-powerpc +++ a/arch/powerpc/sysdev/mpic.c @@ -228,8 +228,13 @@ static inline u32 _mpic_irq_read(struct unsigned int isu = src_no >> mpic->isu_shift; unsigned int idx = src_no & mpic->isu_mask; - return _mpic_read(mpic->reg_type, &mpic->isus[isu], - reg + (idx * MPIC_INFO(IRQ_STRIDE))); +#ifdef CONFIG_MPIC_BROKEN_REGREAD + if (reg == 0) + return mpic->isu_reg0_shadow[idx]; + else +#endif + return _mpic_read(mpic->reg_type, &mpic->isus[isu], + reg + (idx * MPIC_INFO(IRQ_STRIDE))); } static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, @@ -240,6 +245,11 @@ static inline void _mpic_irq_write(struc _mpic_write(mpic->reg_type, &mpic->isus[isu], reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); + +#ifdef CONFIG_MPIC_BROKEN_REGREAD + if (reg == 0) + mpic->isu_reg0_shadow[idx] = value; +#endif } #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) @@ -271,7 +281,7 @@ static void _mpic_map_dcr(struct mpic *m { rb->dbase = mpic->dcr_base; rb->doff = offset; - rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size); + rb->dhost = dcr_map(mpic->irqhost->of_node, rb->dbase + rb->doff, size); BUG_ON(!DCR_MAP_OK(rb->dhost)); } @@ -861,10 +871,8 @@ static struct irq_chip mpic_irq_ht_chip static int mpic_host_match(struct irq_host *h, struct device_node *node) { - struct mpic *mpic = h->host_data; - /* Exact match, unless mpic node is NULL */ - return mpic->of_node == NULL || mpic->of_node == node; + return h->of_node == NULL || h->of_node == node; } static int mpic_host_map(struct irq_host *h, unsigned int virq, @@ -985,10 +993,9 @@ struct mpic * __init mpic_alloc(struct d memset(mpic, 0, sizeof(struct mpic)); mpic->name = name; - mpic->of_node = of_node_get(node); - mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, isu_size, - &mpic_host_ops, + mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, + isu_size, &mpic_host_ops, flags & MPIC_LARGE_VECTORS ? 2048 : 256); if (mpic->irqhost == NULL) { of_node_put(node); diff -puN arch/powerpc/sysdev/mpic_msi.c~git-powerpc arch/powerpc/sysdev/mpic_msi.c --- a/arch/powerpc/sysdev/mpic_msi.c~git-powerpc +++ a/arch/powerpc/sysdev/mpic_msi.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include @@ -117,16 +116,17 @@ static int mpic_msi_reserve_dt_hwirqs(st int i, len; const u32 *p; - p = of_get_property(mpic->of_node, "msi-available-ranges", &len); + p = of_get_property(mpic->irqhost->of_node, + "msi-available-ranges", &len); if (!p) { pr_debug("mpic: no msi-available-ranges property found on %s\n", - mpic->of_node->full_name); + mpic->irqhost->of_node->full_name); return -ENODEV; } if (len % 8 != 0) { printk(KERN_WARNING "mpic: Malformed msi-available-ranges " - "property on %s\n", mpic->of_node->full_name); + "property on %s\n", mpic->irqhost->of_node->full_name); return -EINVAL; } @@ -151,10 +151,7 @@ int mpic_msi_init_allocator(struct mpic size = BITS_TO_LONGS(mpic->irq_count) * sizeof(long); pr_debug("mpic: allocator bitmap size is 0x%x bytes\n", size); - if (mem_init_done) - mpic->hwirq_bitmap = kmalloc(size, GFP_KERNEL); - else - mpic->hwirq_bitmap = alloc_bootmem(size); + mpic->hwirq_bitmap = alloc_maybe_bootmem(size, GFP_KERNEL); if (!mpic->hwirq_bitmap) { pr_debug("mpic: ENOMEM allocating allocator bitmap!\n"); diff -puN arch/powerpc/sysdev/mv64x60_pic.c~git-powerpc arch/powerpc/sysdev/mv64x60_pic.c --- a/arch/powerpc/sysdev/mv64x60_pic.c~git-powerpc +++ a/arch/powerpc/sysdev/mv64x60_pic.c @@ -202,11 +202,6 @@ static struct irq_chip mv64x60_chip_gpp * mv64x60_host_ops functions */ -static int mv64x60_host_match(struct irq_host *h, struct device_node *np) -{ - return mv64x60_irq_host->host_data == np; -} - static struct irq_chip *mv64x60_chips[] = { [MV64x60_LEVEL1_LOW] = &mv64x60_chip_low, [MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high, @@ -228,7 +223,6 @@ static int mv64x60_host_map(struct irq_h } static struct irq_host_ops mv64x60_host_ops = { - .match = mv64x60_host_match, .map = mv64x60_host_map, }; @@ -253,14 +247,12 @@ void __init mv64x60_init_irq(void) np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-pic"); reg = of_get_property(np, "reg", &size); paddr = of_translate_address(np, reg); - of_node_put(np); mv64x60_irq_reg_base = ioremap(paddr, reg[1]); - mv64x60_irq_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, MV64x60_NUM_IRQS, + mv64x60_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, + MV64x60_NUM_IRQS, &mv64x60_host_ops, MV64x60_NUM_IRQS); - mv64x60_irq_host->host_data = np; - spin_lock_irqsave(&mv64x60_lock, flags); out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, mv64x60_cached_gpp_mask); diff -puN arch/powerpc/sysdev/qe_lib/qe_ic.c~git-powerpc arch/powerpc/sysdev/qe_lib/qe_ic.c --- a/arch/powerpc/sysdev/qe_lib/qe_ic.c~git-powerpc +++ a/arch/powerpc/sysdev/qe_lib/qe_ic.c @@ -245,10 +245,8 @@ static struct irq_chip qe_ic_irq_chip = static int qe_ic_host_match(struct irq_host *h, struct device_node *node) { - struct qe_ic *qe_ic = h->host_data; - /* Exact match, unless qe_ic node is NULL */ - return qe_ic->of_node == NULL || qe_ic->of_node == node; + return h->of_node == NULL || h->of_node == node; } static int qe_ic_host_map(struct irq_host *h, unsigned int virq, @@ -352,9 +350,8 @@ void __init qe_ic_init(struct device_nod return; memset(qe_ic, 0, sizeof(struct qe_ic)); - qe_ic->of_node = of_node_get(node); - qe_ic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, + qe_ic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, NR_QE_IC_INTS, &qe_ic_host_ops, 0); if (qe_ic->irqhost == NULL) { of_node_put(node); diff -puN arch/powerpc/sysdev/qe_lib/qe_ic.h~git-powerpc arch/powerpc/sysdev/qe_lib/qe_ic.h --- a/arch/powerpc/sysdev/qe_lib/qe_ic.h~git-powerpc +++ a/arch/powerpc/sysdev/qe_lib/qe_ic.h @@ -84,9 +84,6 @@ struct qe_ic { /* The "linux" controller struct */ struct irq_chip hc_irq; - /* The device node of the interrupt controller */ - struct device_node *of_node; - /* VIRQ numbers of QE high/low irqs */ unsigned int virq_high; unsigned int virq_low; diff -puN arch/powerpc/sysdev/tsi108_pci.c~git-powerpc arch/powerpc/sysdev/tsi108_pci.c --- a/arch/powerpc/sysdev/tsi108_pci.c~git-powerpc +++ a/arch/powerpc/sysdev/tsi108_pci.c @@ -52,7 +52,6 @@ u32 tsi108_pci_cfg_base; static u32 tsi108_pci_cfg_phys; u32 tsi108_csr_vir_base; -static struct device_node *pci_irq_node; static struct irq_host *pci_irq_host; extern u32 get_vir_csrbase(void); @@ -193,8 +192,8 @@ void tsi108_clear_pci_cfg_error(void) } static struct pci_ops tsi108_direct_pci_ops = { - tsi108_direct_read_config, - tsi108_direct_write_config + .read = tsi108_direct_read_config, + .write = tsi108_direct_write_config, }; int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary) @@ -405,13 +404,7 @@ static int pci_irq_host_map(struct irq_h return 0; } -static int pci_irq_host_match(struct irq_host *h, struct device_node *node) -{ - return pci_irq_node == node; -} - static struct irq_host_ops pci_irq_host_ops = { - .match = pci_irq_host_match, .map = pci_irq_host_map, .xlate = pci_irq_host_xlate, }; @@ -433,10 +426,11 @@ void __init tsi108_pci_int_init(struct d { DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); - pci_irq_node = of_node_get(node); - pci_irq_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &pci_irq_host_ops, 0); + pci_irq_host = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LEGACY, + 0, &pci_irq_host_ops, 0); if (pci_irq_host == NULL) { printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n"); + of_node_put(node); return; } diff -puN arch/powerpc/sysdev/uic.c~git-powerpc arch/powerpc/sysdev/uic.c --- a/arch/powerpc/sysdev/uic.c~git-powerpc +++ a/arch/powerpc/sysdev/uic.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -55,9 +56,6 @@ struct uic { /* For secondary UICs, the cascade interrupt's irqaction */ struct irqaction cascade; - - /* The device node of the interrupt controller */ - struct device_node *of_node; }; static void uic_unmask_irq(unsigned int virq) @@ -142,7 +140,7 @@ static int uic_set_irq_type(unsigned int desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; - if (trigger) + if (!trigger) desc->status |= IRQ_LEVEL; spin_unlock_irqrestore(&uic->lock, flags); @@ -159,10 +157,62 @@ static struct irq_chip uic_irq_chip = { .set_type = uic_set_irq_type, }; -static int uic_host_match(struct irq_host *h, struct device_node *node) -{ - struct uic *uic = h->host_data; - return uic->of_node == node; +/** + * handle_uic_irq - irq flow handler for UIC + * @irq: the interrupt number + * @desc: the interrupt description structure for this irq + * + * This is modified version of the generic handle_level_irq() suitable + * for the UIC. On the UIC, acking (i.e. clearing the SR bit) a level + * irq will have no effect if the interrupt is still asserted by the + * device, even if the interrupt is already masked. Therefore, unlike + * the standard handle_level_irq(), we must ack the interrupt *after* + * invoking the ISR (which should have de-asserted the interrupt in + * the external source). For edge interrupts we ack at the beginning + * instead of the end, to keep the window in which we can miss an + * interrupt as small as possible. + */ +void fastcall handle_uic_irq(unsigned int irq, struct irq_desc *desc) +{ + unsigned int cpu = smp_processor_id(); + struct irqaction *action; + irqreturn_t action_ret; + + spin_lock(&desc->lock); + if (desc->status & IRQ_LEVEL) + desc->chip->mask(irq); + else + desc->chip->mask_ack(irq); + + if (unlikely(desc->status & IRQ_INPROGRESS)) + goto out_unlock; + desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); + kstat_cpu(cpu).irqs[irq]++; + + /* + * If its disabled or no action available + * keep it masked and get out of here + */ + action = desc->action; + if (unlikely(!action || (desc->status & IRQ_DISABLED))) { + desc->status |= IRQ_PENDING; + goto out_unlock; + } + + desc->status |= IRQ_INPROGRESS; + desc->status &= ~IRQ_PENDING; + spin_unlock(&desc->lock); + + action_ret = handle_IRQ_event(irq, action); + + spin_lock(&desc->lock); + desc->status &= ~IRQ_INPROGRESS; + if (desc->status & IRQ_LEVEL) + desc->chip->ack(irq); + if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) + desc->chip->unmask(irq); +out_unlock: + spin_unlock(&desc->lock); } static int uic_host_map(struct irq_host *h, unsigned int virq, @@ -173,7 +223,7 @@ static int uic_host_map(struct irq_host set_irq_chip_data(virq, uic); /* Despite the name, handle_level_irq() works for both level * and edge irqs on UIC. FIXME: check this is correct */ - set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); + set_irq_chip_and_handler(virq, &uic_irq_chip, handle_uic_irq); /* Set default irq type */ set_irq_type(virq, IRQ_TYPE_NONE); @@ -194,7 +244,6 @@ static int uic_host_xlate(struct irq_hos } static struct irq_host_ops uic_host_ops = { - .match = uic_host_match, .map = uic_host_map, .xlate = uic_host_xlate, }; @@ -207,6 +256,9 @@ irqreturn_t uic_cascade(int virq, void * int subvirq; msr = mfdcr(uic->dcrbase + UIC_MSR); + if (!msr) /* spurious interrupt */ + return IRQ_HANDLED; + src = 32 - ffs(msr); subvirq = irq_linear_revmap(uic->irqhost, src); @@ -229,7 +281,6 @@ static struct uic * __init uic_init_one( memset(uic, 0, sizeof(*uic)); spin_lock_init(&uic->lock); - uic->of_node = of_node_get(node); indexp = of_get_property(node, "cell-index", &len); if (!indexp || (len != sizeof(u32))) { printk(KERN_ERR "uic: Device node %s has missing or invalid " @@ -246,8 +297,8 @@ static struct uic * __init uic_init_one( } uic->dcrbase = *dcrreg; - uic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_UIC_INTS, - &uic_host_ops, -1); + uic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, + NR_UIC_INTS, &uic_host_ops, -1); if (! uic->irqhost) { of_node_put(node); return NULL; /* FIXME: panic? */ diff -puN arch/ppc/.gitignore~git-powerpc arch/ppc/.gitignore --- a/arch/ppc/.gitignore~git-powerpc +++ a/arch/ppc/.gitignore @@ -1 +1 @@ -include +/include diff -puN arch/ppc/Kconfig~git-powerpc arch/ppc/Kconfig --- a/arch/ppc/Kconfig~git-powerpc +++ a/arch/ppc/Kconfig @@ -573,24 +573,9 @@ choice Select PReP if configuring for a PReP machine. - Select Gemini if configuring for a Synergy Microsystems' Gemini - series Single Board Computer. More information is available at: - . - - Select APUS if configuring for a PowerUP Amiga. More information is - available at: . - config PPC_PREP bool "PReP" -config APUS - bool "Amiga-APUS" - depends on BROKEN - help - Select APUS if configuring for a PowerUP Amiga. - More information is available at: - . - config KATANA bool "Artesyn-Katana" help @@ -1027,132 +1012,6 @@ config CMDLINE some command-line options at build time by entering them here. In most cases you will need to specify the root device here. -config AMIGA - bool - depends on APUS - default y - help - This option enables support for the Amiga series of computers. - -config ZORRO - bool - depends on APUS - default y - help - This enables support for the Zorro bus in the Amiga. If you have - expansion cards in your Amiga that conform to the Amiga - AutoConfig(tm) specification, say Y, otherwise N. Note that even - expansion cards that do not fit in the Zorro slots but fit in e.g. - the CPU slot may fall in this category, so you have to say Y to let - Linux use these. - -config ABSTRACT_CONSOLE - bool - depends on APUS - default y - -config APUS_FAST_EXCEPT - bool - depends on APUS - default y - -config AMIGA_PCMCIA - bool "Amiga 1200/600 PCMCIA support" - depends on APUS && EXPERIMENTAL - help - Include support in the kernel for pcmcia on Amiga 1200 and Amiga - 600. If you intend to use pcmcia cards say Y; otherwise say N. - -config AMIGA_BUILTIN_SERIAL - tristate "Amiga builtin serial support" - depends on APUS - help - If you want to use your Amiga's built-in serial port in Linux, - answer Y. - - To compile this driver as a module, choose M here. - -config GVPIOEXT - tristate "GVP IO-Extender support" - depends on APUS - help - If you want to use a GVP IO-Extender serial card in Linux, say Y. - Otherwise, say N. - -config GVPIOEXT_LP - tristate "GVP IO-Extender parallel printer support" - depends on GVPIOEXT - help - Say Y to enable driving a printer from the parallel port on your - GVP IO-Extender card, N otherwise. - -config GVPIOEXT_PLIP - tristate "GVP IO-Extender PLIP support" - depends on GVPIOEXT - help - Say Y to enable doing IP over the parallel port on your GVP - IO-Extender card, N otherwise. - -config MULTIFACE_III_TTY - tristate "Multiface Card III serial support" - depends on APUS - help - If you want to use a Multiface III card's serial port in Linux, - answer Y. - - To compile this driver as a module, choose M here. - -config A2232 - tristate "Commodore A2232 serial support (EXPERIMENTAL)" - depends on EXPERIMENTAL && APUS - ---help--- - This option supports the 2232 7-port serial card shipped with the - Amiga 2000 and other Zorro-bus machines, dating from 1989. At - a max of 19,200 bps, the ports are served by a 6551 ACIA UART chip - each, plus a 8520 CIA, and a master 6502 CPU and buffer as well. The - ports were connected with 8 pin DIN connectors on the card bracket, - for which 8 pin to DB25 adapters were supplied. The card also had - jumpers internally to toggle various pinning configurations. - - This driver can be built as a module; but then "generic_serial" - will also be built as a module. This has to be loaded before - "ser_a2232". If you want to do this, answer M here. - -config WHIPPET_SERIAL - tristate "Hisoft Whippet PCMCIA serial support" - depends on AMIGA_PCMCIA - help - HiSoft has a web page at , but there - is no listing for the Whippet in their Amiga section. - -config APNE - tristate "PCMCIA NE2000 support" - depends on AMIGA_PCMCIA - help - If you have a PCMCIA NE2000 compatible adapter, say Y. Otherwise, - say N. - - To compile this driver as a module, choose M here: the - module will be called apne. - -config SERIAL_CONSOLE - bool "Support for serial port console" - depends on APUS && (AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y) - -config HEARTBEAT - bool "Use power LED as a heartbeat" - depends on APUS - help - Use the power-on LED on your machine as a load meter. The exact - behavior is platform-dependent, but normally the flash frequency is - a hyperbolic function of the 5-minute load average. - -config PROC_HARDWARE - bool "/proc/hardware support" - depends on APUS - -source "drivers/zorro/Kconfig" - if !44x || BROKEN source kernel/power/Kconfig endif @@ -1227,8 +1086,7 @@ config MCA config PCI bool "PCI support" if 40x || CPM2 || 83xx || 85xx || PPC_MPC52xx - default y if !40x && !CPM2 && !8xx && !APUS && !83xx && !85xx - default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS + default y if !40x && !CPM2 && !8xx && !83xx && !85xx default PCI_QSPAN if !4xx && !CPM2 && 8xx help Find out whether your system includes a PCI bus. PCI is the name of @@ -1284,10 +1142,6 @@ config 8260_PCI9_IDMA4 endchoice -config PCI_PERMEDIA - bool "PCI for Permedia2" - depends on !4xx && !8xx && APUS - source "drivers/pci/Kconfig" source "drivers/pcmcia/Kconfig" diff -puN arch/ppc/Makefile~git-powerpc arch/ppc/Makefile --- a/arch/ppc/Makefile~git-powerpc +++ a/arch/ppc/Makefile @@ -69,7 +69,6 @@ core-$(CONFIG_83xx) += arch/ppc/platfor core-$(CONFIG_85xx) += arch/ppc/platforms/85xx/ core-$(CONFIG_MATH_EMULATION) += arch/powerpc/math-emu/ core-$(CONFIG_XMON) += arch/ppc/xmon/ -core-$(CONFIG_APUS) += arch/ppc/amiga/ drivers-$(CONFIG_8xx) += arch/ppc/8xx_io/ drivers-$(CONFIG_4xx) += arch/ppc/4xx_io/ drivers-$(CONFIG_CPM2) += arch/ppc/8260_io/ diff -puN arch/ppc/amiga/Makefile~git-powerpc /dev/null --- a/arch/ppc/amiga/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for Linux arch/m68k/amiga source directory -# - -obj-y := config.o amiints.o cia.o time.o bootinfo.o amisound.o \ - chipram.o amiga_ksyms.o - -obj-$(CONFIG_AMIGA_PCMCIA) += pcmcia.o diff -puN arch/ppc/amiga/amiga_ksyms.c~git-powerpc /dev/null --- a/arch/ppc/amiga/amiga_ksyms.c +++ /dev/null @@ -1 +0,0 @@ -#include "../../m68k/amiga/amiga_ksyms.c" diff -puN arch/ppc/amiga/amiints.c~git-powerpc /dev/null --- a/arch/ppc/amiga/amiints.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Amiga Linux interrupt handling code - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * 11/07/96: rewritten interrupt handling, irq lists are exists now only for - * this sources where it makes sense (VERTB/PORTS/EXTER) and you must - * be careful that dev_id for this sources is unique since this the - * only possibility to distinguish between different handlers for - * free_irq. irq lists also have different irq flags: - * - IRQ_FLG_FAST: handler is inserted at top of list (after other - * fast handlers) - * - IRQ_FLG_SLOW: handler is inserted at bottom of list and before - * they're executed irq level is set to the previous - * one, but handlers don't need to be reentrant, if - * reentrance occurred, slow handlers will be just - * called again. - * The whole interrupt handling for CIAs is moved to cia.c - * /Roman Zippel - * - * 07/08/99: rewamp of the interrupt handling - we now have two types of - * interrupts, normal and fast handlers, fast handlers being - * marked with SA_INTERRUPT and runs with all other interrupts - * disabled. Normal interrupts disable their own source but - * run with all other interrupt sources enabled. - * PORTS and EXTER interrupts are always shared even if the - * drivers do not explicitly mark this when calling - * request_irq which they really should do. - * This is similar to the way interrupts are handled on all - * other architectures and makes a ton of sense besides - * having the advantage of making it easier to share - * drivers. - * /Jes - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_APUS -#include -#endif - -extern void cia_init_IRQ(struct ciabase *base); - -unsigned short ami_intena_vals[AMI_STD_IRQS] = { - IF_VERTB, IF_COPER, IF_AUD0, IF_AUD1, IF_AUD2, IF_AUD3, IF_BLIT, - IF_DSKSYN, IF_DSKBLK, IF_RBF, IF_TBE, IF_SOFT, IF_PORTS, IF_EXTER -}; -static const unsigned char ami_servers[AMI_STD_IRQS] = { - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 -}; - -static short ami_ablecount[AMI_IRQS]; - -static void ami_badint(int irq, void *dev_id, struct pt_regs *fp) -{ -/* num_spurious += 1;*/ -} - -/* - * void amiga_init_IRQ(void) - * - * Parameters: None - * - * Returns: Nothing - * - * This function should be called during kernel startup to initialize - * the amiga IRQ handling routines. - */ - -__init -void amiga_init_IRQ(void) -{ - int i; - - for (i = 0; i < AMI_IRQS; i++) - ami_ablecount[i] = 0; - - /* turn off PCMCIA interrupts */ - if (AMIGAHW_PRESENT(PCMCIA)) - gayle.inten = GAYLE_IRQ_IDE; - - /* turn off all interrupts... */ - amiga_custom.intena = 0x7fff; - amiga_custom.intreq = 0x7fff; - -#ifdef CONFIG_APUS - /* Clear any inter-CPU interrupt requests. Circumvents bug in - Blizzard IPL emulation HW (or so it appears). */ - APUS_WRITE(APUS_INT_LVL, INTLVL_SETRESET | INTLVL_MASK); - - /* Init IPL emulation. */ - APUS_WRITE(APUS_REG_INT, REGINT_INTMASTER | REGINT_ENABLEIPL); - APUS_WRITE(APUS_IPL_EMU, IPLEMU_DISABLEINT); - APUS_WRITE(APUS_IPL_EMU, IPLEMU_SETRESET | IPLEMU_IPLMASK); -#endif - /* ... and enable the master interrupt bit */ - amiga_custom.intena = IF_SETCLR | IF_INTEN; - - cia_init_IRQ(&ciaa_base); - cia_init_IRQ(&ciab_base); -} - -/* - * Enable/disable a particular machine specific interrupt source. - * Note that this may affect other interrupts in case of a shared interrupt. - * This function should only be called for a _very_ short time to change some - * internal data, that may not be changed by the interrupt at the same time. - * ami_(enable|disable)_irq calls may also be nested. - */ - -void amiga_enable_irq(unsigned int irq) -{ - if (irq >= AMI_IRQS) { - printk("%s: Unknown IRQ %d\n", __FUNCTION__, irq); - return; - } - - ami_ablecount[irq]--; - if (ami_ablecount[irq]<0) - ami_ablecount[irq]=0; - else if (ami_ablecount[irq]) - return; - - /* No action for auto-vector interrupts */ - if (irq >= IRQ_AMIGA_AUTO){ - printk("%s: Trying to enable auto-vector IRQ %i\n", - __FUNCTION__, irq - IRQ_AMIGA_AUTO); - return; - } - - if (irq >= IRQ_AMIGA_CIAA) { - cia_set_irq(irq, 0); - cia_able_irq(irq, 1); - return; - } - - /* enable the interrupt */ - amiga_custom.intena = IF_SETCLR | ami_intena_vals[irq]; -} - -void amiga_disable_irq(unsigned int irq) -{ - if (irq >= AMI_IRQS) { - printk("%s: Unknown IRQ %d\n", __FUNCTION__, irq); - return; - } - - if (ami_ablecount[irq]++) - return; - - /* No action for auto-vector interrupts */ - if (irq >= IRQ_AMIGA_AUTO) { - printk("%s: Trying to disable auto-vector IRQ %i\n", - __FUNCTION__, irq - IRQ_AMIGA_AUTO); - return; - } - - if (irq >= IRQ_AMIGA_CIAA) { - cia_able_irq(irq, 0); - return; - } - - /* disable the interrupt */ - amiga_custom.intena = ami_intena_vals[irq]; -} - -inline void amiga_do_irq(int irq, struct pt_regs *fp) -{ - irq_desc_t *desc = irq_desc + irq; - struct irqaction *action = desc->action; - - kstat_cpu(0).irqs[irq]++; - action->handler(irq, action->dev_id, fp); -} - -void amiga_do_irq_list(int irq, struct pt_regs *fp) -{ - irq_desc_t *desc = irq_desc + irq; - struct irqaction *action; - - kstat_cpu(0).irqs[irq]++; - - amiga_custom.intreq = ami_intena_vals[irq]; - - for (action = desc->action; action; action = action->next) - action->handler(irq, action->dev_id, fp); -} - -/* - * The builtin Amiga hardware interrupt handlers. - */ - -static void ami_int1(int irq, void *dev_id, struct pt_regs *fp) -{ - unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; - - /* if serial transmit buffer empty, interrupt */ - if (ints & IF_TBE) { - amiga_custom.intreq = IF_TBE; - amiga_do_irq(IRQ_AMIGA_TBE, fp); - } - - /* if floppy disk transfer complete, interrupt */ - if (ints & IF_DSKBLK) { - amiga_custom.intreq = IF_DSKBLK; - amiga_do_irq(IRQ_AMIGA_DSKBLK, fp); - } - - /* if software interrupt set, interrupt */ - if (ints & IF_SOFT) { - amiga_custom.intreq = IF_SOFT; - amiga_do_irq(IRQ_AMIGA_SOFT, fp); - } -} - -static void ami_int3(int irq, void *dev_id, struct pt_regs *fp) -{ - unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; - - /* if a blitter interrupt */ - if (ints & IF_BLIT) { - amiga_custom.intreq = IF_BLIT; - amiga_do_irq(IRQ_AMIGA_BLIT, fp); - } - - /* if a copper interrupt */ - if (ints & IF_COPER) { - amiga_custom.intreq = IF_COPER; - amiga_do_irq(IRQ_AMIGA_COPPER, fp); - } - - /* if a vertical blank interrupt */ - if (ints & IF_VERTB) - amiga_do_irq_list(IRQ_AMIGA_VERTB, fp); -} - -static void ami_int4(int irq, void *dev_id, struct pt_regs *fp) -{ - unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; - - /* if audio 0 interrupt */ - if (ints & IF_AUD0) { - amiga_custom.intreq = IF_AUD0; - amiga_do_irq(IRQ_AMIGA_AUD0, fp); - } - - /* if audio 1 interrupt */ - if (ints & IF_AUD1) { - amiga_custom.intreq = IF_AUD1; - amiga_do_irq(IRQ_AMIGA_AUD1, fp); - } - - /* if audio 2 interrupt */ - if (ints & IF_AUD2) { - amiga_custom.intreq = IF_AUD2; - amiga_do_irq(IRQ_AMIGA_AUD2, fp); - } - - /* if audio 3 interrupt */ - if (ints & IF_AUD3) { - amiga_custom.intreq = IF_AUD3; - amiga_do_irq(IRQ_AMIGA_AUD3, fp); - } -} - -static void ami_int5(int irq, void *dev_id, struct pt_regs *fp) -{ - unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; - - /* if serial receive buffer full interrupt */ - if (ints & IF_RBF) { - /* acknowledge of IF_RBF must be done by the serial interrupt */ - amiga_do_irq(IRQ_AMIGA_RBF, fp); - } - - /* if a disk sync interrupt */ - if (ints & IF_DSKSYN) { - amiga_custom.intreq = IF_DSKSYN; - amiga_do_irq(IRQ_AMIGA_DSKSYN, fp); - } -} - -static void ami_int7(int irq, void *dev_id, struct pt_regs *fp) -{ - panic ("level 7 interrupt received\n"); -} - -#ifdef CONFIG_APUS -/* The PPC irq handling links all handlers requested on the same vector - and executes them in a loop. Having ami_badint at the end of the chain - is a bad idea. */ -struct irqaction amiga_sys_irqaction[AUTO_IRQS] = { - { .handler = ami_badint, .name = "spurious int" }, - { .handler = ami_int1, .name = "int1 handler" }, - { 0, /* CIAA */ }, - { .handler = ami_int3, .name = "int3 handler" }, - { .handler = ami_int4, .name = "int4 handler" }, - { .handler = ami_int5, .name = "int5 handler" }, - { 0, /* CIAB */ }, - { .handler = ami_int7, .name = "int7 handler" }, -}; -#else -void (*amiga_default_handler[SYS_IRQS])(int, void *, struct pt_regs *) = { - ami_badint, ami_int1, ami_badint, ami_int3, - ami_int4, ami_int5, ami_badint, ami_int7 -}; -#endif diff -puN arch/ppc/amiga/amisound.c~git-powerpc /dev/null --- a/arch/ppc/amiga/amisound.c +++ /dev/null @@ -1 +0,0 @@ -#include "../../m68k/amiga/amisound.c" diff -puN arch/ppc/amiga/bootinfo.c~git-powerpc /dev/null --- a/arch/ppc/amiga/bootinfo.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Extracted from arch/m68k/kernel/setup.c. - * Should be properly generalized and put somewhere else. - * Jesper - */ - -#include -#include -#include -#include - -#include -#include - -extern char cmd_line[CL_SIZE]; - -extern int num_memory; -extern int m68k_realnum_memory; -extern struct mem_info memory[NUM_MEMINFO]; -extern struct mem_info m68k_memory[NUM_MEMINFO]; -extern struct mem_info ramdisk; - -extern int amiga_parse_bootinfo(const struct bi_record *); -extern int atari_parse_bootinfo(const struct bi_record *); -extern int mac_parse_bootinfo(const struct bi_record *); - -void __init parse_bootinfo(const struct bi_record *record) -{ - while (record->tag != BI_LAST) { - int unknown = 0; - const u_long *data = record->data; - switch (record->tag) { - case BI_MACHTYPE: - case BI_CPUTYPE: - case BI_FPUTYPE: - case BI_MMUTYPE: - /* Already set up by head.S */ - break; - - case BI_MEMCHUNK: - if (num_memory < NUM_MEMINFO) { - memory[num_memory].addr = data[0]; - memory[num_memory].size = data[1]; - num_memory++; - - /* FIXME: duplicate for m68k drivers. */ - m68k_memory[m68k_realnum_memory].addr = data[0]; - m68k_memory[m68k_realnum_memory].size = data[1]; - m68k_realnum_memory++; - } else - printk("parse_bootinfo: too many memory chunks\n"); - break; - - case BI_RAMDISK: - ramdisk.addr = data[0]; - ramdisk.size = data[1]; - break; - - case BI_COMMAND_LINE: - strlcpy(cmd_line, (const char *)data, sizeof(cmd_line)); - break; - - default: - if (MACH_IS_AMIGA) - unknown = amiga_parse_bootinfo(record); - else if (MACH_IS_ATARI) - unknown = atari_parse_bootinfo(record); - else if (MACH_IS_MAC) - unknown = mac_parse_bootinfo(record); - else - unknown = 1; - } - if (unknown) - printk("parse_bootinfo: unknown tag 0x%04x ignored\n", - record->tag); - record = (struct bi_record *)((u_long)record+record->size); - } -} diff -puN arch/ppc/amiga/chipram.c~git-powerpc /dev/null --- a/arch/ppc/amiga/chipram.c +++ /dev/null @@ -1 +0,0 @@ -#include "../../m68k/amiga/chipram.c" diff -puN arch/ppc/amiga/cia.c~git-powerpc /dev/null --- a/arch/ppc/amiga/cia.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 1996 Roman Zippel - * - * The concept of some functions bases on the original Amiga OS function - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -struct ciabase { - volatile struct CIA *cia; - u_char icr_mask, icr_data; - u_short int_mask; - int handler_irq, cia_irq, server_irq; - char *name; -} ciaa_base = { - &ciaa, 0, 0, IF_PORTS, - IRQ_AMIGA_AUTO_2, IRQ_AMIGA_CIAA, - IRQ_AMIGA_PORTS, - "CIAA handler" -}, ciab_base = { - &ciab, 0, 0, IF_EXTER, - IRQ_AMIGA_AUTO_6, IRQ_AMIGA_CIAB, - IRQ_AMIGA_EXTER, - "CIAB handler" -}; - -#define CIA_SET_BASE_ADJUST_IRQ(base, irq) \ -do { \ - if (irq >= IRQ_AMIGA_CIAB) { \ - base = &ciab_base; \ - irq -= IRQ_AMIGA_CIAB; \ - } else { \ - base = &ciaa_base; \ - irq -= IRQ_AMIGA_CIAA; \ - } \ -} while (0) - -/* - * Cause or clear CIA interrupts, return old interrupt status. - */ - -static unsigned char cia_set_irq_private(struct ciabase *base, - unsigned char mask) -{ - u_char old; - - old = (base->icr_data |= base->cia->icr); - if (mask & CIA_ICR_SETCLR) - base->icr_data |= mask; - else - base->icr_data &= ~mask; - if (base->icr_data & base->icr_mask) - amiga_custom.intreq = IF_SETCLR | base->int_mask; - return old & base->icr_mask; -} - -unsigned char cia_set_irq(unsigned int irq, int set) -{ - struct ciabase *base; - unsigned char mask; - - if (irq >= IRQ_AMIGA_CIAB) - mask = (1 << (irq - IRQ_AMIGA_CIAB)); - else - mask = (1 << (irq - IRQ_AMIGA_CIAA)); - mask |= (set) ? CIA_ICR_SETCLR : 0; - - CIA_SET_BASE_ADJUST_IRQ(base, irq); - - return cia_set_irq_private(base, mask); -} - -unsigned char cia_get_irq_mask(unsigned int irq) -{ - struct ciabase *base; - - CIA_SET_BASE_ADJUST_IRQ(base, irq); - - return base->cia->icr; -} - -/* - * Enable or disable CIA interrupts, return old interrupt mask. - */ - -static unsigned char cia_able_irq_private(struct ciabase *base, - unsigned char mask) -{ - u_char old; - - old = base->icr_mask; - base->icr_data |= base->cia->icr; - base->cia->icr = mask; - if (mask & CIA_ICR_SETCLR) - base->icr_mask |= mask; - else - base->icr_mask &= ~mask; - base->icr_mask &= CIA_ICR_ALL; - - if (base->icr_data & base->icr_mask) - amiga_custom.intreq = IF_SETCLR | base->int_mask; - return old; -} - -unsigned char cia_able_irq(unsigned int irq, int enable) -{ - struct ciabase *base; - unsigned char mask; - - if (irq >= IRQ_AMIGA_CIAB) - mask = (1 << (irq - IRQ_AMIGA_CIAB)); - else - mask = (1 << (irq - IRQ_AMIGA_CIAA)); - mask |= (enable) ? CIA_ICR_SETCLR : 0; - - CIA_SET_BASE_ADJUST_IRQ(base, irq); - - return cia_able_irq_private(base, mask); -} - -static void cia_handler(int irq, void *dev_id, struct pt_regs *fp) -{ - struct ciabase *base = (struct ciabase *)dev_id; - irq_desc_t *desc; - struct irqaction *action; - int i; - unsigned char ints; - - irq = base->cia_irq; - desc = irq_desc + irq; - ints = cia_set_irq_private(base, CIA_ICR_ALL); - amiga_custom.intreq = base->int_mask; - for (i = 0; i < CIA_IRQS; i++, irq++) { - if (ints & 1) { - kstat_cpu(0).irqs[irq]++; - action = desc->action; - action->handler(irq, action->dev_id, fp); - } - ints >>= 1; - desc++; - } - amiga_do_irq_list(base->server_irq, fp); -} - -void __init cia_init_IRQ(struct ciabase *base) -{ - extern struct irqaction amiga_sys_irqaction[AUTO_IRQS]; - struct irqaction *action; - - /* clear any pending interrupt and turn off all interrupts */ - cia_set_irq_private(base, CIA_ICR_ALL); - cia_able_irq_private(base, CIA_ICR_ALL); - - /* install CIA handler */ - action = &amiga_sys_irqaction[base->handler_irq-IRQ_AMIGA_AUTO]; - action->handler = cia_handler; - action->dev_id = base; - action->name = base->name; - setup_irq(base->handler_irq, &amiga_sys_irqaction[base->handler_irq-IRQ_AMIGA_AUTO]); - - amiga_custom.intena = IF_SETCLR | base->int_mask; -} diff -puN arch/ppc/amiga/config.c~git-powerpc /dev/null --- a/arch/ppc/amiga/config.c +++ /dev/null @@ -1,953 +0,0 @@ -#define m68k_debug_device debug_device - -/* - * Copyright (C) 1993 Hamish Macdonald - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * Miscellaneous Amiga stuff - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_ZORRO -#include -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -unsigned long powerup_PCI_present; -unsigned long powerup_BPPCPLUS_present; -unsigned long amiga_model; -unsigned long amiga_eclock; -unsigned long amiga_masterclock; -unsigned long amiga_colorclock; -unsigned long amiga_chipset; -unsigned char amiga_vblank; -unsigned char amiga_psfreq; -struct amiga_hw_present amiga_hw_present; - -static char s_a500[] __initdata = "A500"; -static char s_a500p[] __initdata = "A500+"; -static char s_a600[] __initdata = "A600"; -static char s_a1000[] __initdata = "A1000"; -static char s_a1200[] __initdata = "A1200"; -static char s_a2000[] __initdata = "A2000"; -static char s_a2500[] __initdata = "A2500"; -static char s_a3000[] __initdata = "A3000"; -static char s_a3000t[] __initdata = "A3000T"; -static char s_a3000p[] __initdata = "A3000+"; -static char s_a4000[] __initdata = "A4000"; -static char s_a4000t[] __initdata = "A4000T"; -static char s_cdtv[] __initdata = "CDTV"; -static char s_cd32[] __initdata = "CD32"; -static char s_draco[] __initdata = "Draco"; -static char *amiga_models[] __initdata = { - s_a500, s_a500p, s_a600, s_a1000, s_a1200, s_a2000, s_a2500, s_a3000, - s_a3000t, s_a3000p, s_a4000, s_a4000t, s_cdtv, s_cd32, s_draco, -}; - -static char amiga_model_name[13] = "Amiga "; - -extern char m68k_debug_device[]; - -static void amiga_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)); -/* amiga specific irq functions */ -extern void amiga_init_IRQ (void); -extern void (*amiga_default_handler[]) (int, void *, struct pt_regs *); -extern int amiga_request_irq (unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long flags, const char *devname, - void *dev_id); -extern void amiga_free_irq (unsigned int irq, void *dev_id); -extern void amiga_enable_irq (unsigned int); -extern void amiga_disable_irq (unsigned int); -static void amiga_get_model(char *model); -static int amiga_get_hardware_list(char *buffer); -/* amiga specific timer functions */ -static unsigned long amiga_gettimeoffset (void); -static void a3000_gettod (int *, int *, int *, int *, int *, int *); -static void a2000_gettod (int *, int *, int *, int *, int *, int *); -static int amiga_hwclk (int, struct hwclk_time *); -static int amiga_set_clock_mmss (unsigned long); -static void amiga_reset (void); -extern void amiga_init_sound(void); -static void amiga_savekmsg_init(void); -static void amiga_mem_console_write(struct console *co, const char *b, - unsigned int count); -void amiga_serial_console_write(struct console *co, const char *s, - unsigned int count); -static void amiga_debug_init(void); -#ifdef CONFIG_HEARTBEAT -static void amiga_heartbeat(int on); -#endif - -static struct console amiga_console_driver = { - .name = "debug", - .flags = CON_PRINTBUFFER, - .index = -1, -}; - - - /* - * Motherboard Resources present in all Amiga models - */ - -static struct { - struct resource _ciab, _ciaa, _custom, _kickstart; -} mb_resources = { -// { "Ranger Memory", 0x00c00000, 0x00c7ffff }, - ._ciab = { "CIA B", 0x00bfd000, 0x00bfdfff }, - ._ciaa = { "CIA A", 0x00bfe000, 0x00bfefff }, - ._custom = { "Custom I/O", 0x00dff000, 0x00dfffff }, - ._kickstart = { "Kickstart ROM", 0x00f80000, 0x00ffffff } -}; - -static struct resource rtc_resource = { - NULL, 0x00dc0000, 0x00dcffff -}; - -static struct resource ram_resource[NUM_MEMINFO]; - - - /* - * Parse an Amiga-specific record in the bootinfo - */ - -int amiga_parse_bootinfo(const struct bi_record *record) -{ - int unknown = 0; - const unsigned long *data = record->data; - - switch (record->tag) { - case BI_AMIGA_MODEL: - { - unsigned long d = *data; - - powerup_PCI_present = d & 0x100; - amiga_model = d & 0xff; - } - break; - - case BI_AMIGA_ECLOCK: - amiga_eclock = *data; - break; - - case BI_AMIGA_CHIPSET: - amiga_chipset = *data; - break; - - case BI_AMIGA_CHIP_SIZE: - amiga_chip_size = *(const int *)data; - break; - - case BI_AMIGA_VBLANK: - amiga_vblank = *(const unsigned char *)data; - break; - - case BI_AMIGA_PSFREQ: - amiga_psfreq = *(const unsigned char *)data; - break; - - case BI_AMIGA_AUTOCON: -#ifdef CONFIG_ZORRO - if (zorro_num_autocon < ZORRO_NUM_AUTO) { - const struct ConfigDev *cd = (struct ConfigDev *)data; - struct zorro_dev *dev = &zorro_autocon[zorro_num_autocon++]; - dev->rom = cd->cd_Rom; - dev->slotaddr = cd->cd_SlotAddr; - dev->slotsize = cd->cd_SlotSize; - dev->resource.start = (unsigned long)cd->cd_BoardAddr; - dev->resource.end = dev->resource.start+cd->cd_BoardSize-1; - } else - printk("amiga_parse_bootinfo: too many AutoConfig devices\n"); -#endif /* CONFIG_ZORRO */ - break; - - case BI_AMIGA_SERPER: - /* serial port period: ignored here */ - break; - - case BI_AMIGA_PUP_BRIDGE: - powerup_PCI_present = *(const unsigned short *)data; - break; - - case BI_AMIGA_BPPC_SCSI: - powerup_BPPCPLUS_present = *(const unsigned short *)data; - break; - - default: - unknown = 1; - } - return(unknown); -} - - /* - * Identify builtin hardware - */ - -static void __init amiga_identify(void) -{ - /* Fill in some default values, if necessary */ - if (amiga_eclock == 0) - amiga_eclock = 709379; - - memset(&amiga_hw_present, 0, sizeof(amiga_hw_present)); - - printk("Amiga hardware found: "); - if (amiga_model >= AMI_500 && amiga_model <= AMI_DRACO) { - printk("[%s] ", amiga_models[amiga_model-AMI_500]); - strcat(amiga_model_name, amiga_models[amiga_model-AMI_500]); - } - - switch(amiga_model) { - case AMI_UNKNOWN: - goto Generic; - - case AMI_600: - case AMI_1200: - AMIGAHW_SET(A1200_IDE); - AMIGAHW_SET(PCMCIA); - case AMI_500: - case AMI_500PLUS: - case AMI_1000: - case AMI_2000: - case AMI_2500: - AMIGAHW_SET(A2000_CLK); /* Is this correct for all models? */ - goto Generic; - - case AMI_3000: - case AMI_3000T: - AMIGAHW_SET(AMBER_FF); - AMIGAHW_SET(MAGIC_REKICK); - /* fall through */ - case AMI_3000PLUS: - AMIGAHW_SET(A3000_SCSI); - AMIGAHW_SET(A3000_CLK); - AMIGAHW_SET(ZORRO3); - goto Generic; - - case AMI_4000T: - AMIGAHW_SET(A4000_SCSI); - /* fall through */ - case AMI_4000: - AMIGAHW_SET(A4000_IDE); - AMIGAHW_SET(A3000_CLK); - AMIGAHW_SET(ZORRO3); - goto Generic; - - case AMI_CDTV: - case AMI_CD32: - AMIGAHW_SET(CD_ROM); - AMIGAHW_SET(A2000_CLK); /* Is this correct? */ - goto Generic; - - Generic: - AMIGAHW_SET(AMI_VIDEO); - AMIGAHW_SET(AMI_BLITTER); - AMIGAHW_SET(AMI_AUDIO); - AMIGAHW_SET(AMI_FLOPPY); - AMIGAHW_SET(AMI_KEYBOARD); - AMIGAHW_SET(AMI_MOUSE); - AMIGAHW_SET(AMI_SERIAL); - AMIGAHW_SET(AMI_PARALLEL); - AMIGAHW_SET(CHIP_RAM); - AMIGAHW_SET(PAULA); - - switch(amiga_chipset) { - case CS_OCS: - case CS_ECS: - case CS_AGA: - switch (amiga_custom.deniseid & 0xf) { - case 0x0c: - AMIGAHW_SET(DENISE_HR); - break; - case 0x08: - AMIGAHW_SET(LISA); - break; - } - break; - default: - AMIGAHW_SET(DENISE); - break; - } - switch ((amiga_custom.vposr>>8) & 0x7f) { - case 0x00: - AMIGAHW_SET(AGNUS_PAL); - break; - case 0x10: - AMIGAHW_SET(AGNUS_NTSC); - break; - case 0x20: - case 0x21: - AMIGAHW_SET(AGNUS_HR_PAL); - break; - case 0x30: - case 0x31: - AMIGAHW_SET(AGNUS_HR_NTSC); - break; - case 0x22: - case 0x23: - AMIGAHW_SET(ALICE_PAL); - break; - case 0x32: - case 0x33: - AMIGAHW_SET(ALICE_NTSC); - break; - } - AMIGAHW_SET(ZORRO); - break; - - case AMI_DRACO: - panic("No support for Draco yet"); - - default: - panic("Unknown Amiga Model"); - } - -#define AMIGAHW_ANNOUNCE(name, str) \ - if (AMIGAHW_PRESENT(name)) \ - printk(str) - - AMIGAHW_ANNOUNCE(AMI_VIDEO, "VIDEO "); - AMIGAHW_ANNOUNCE(AMI_BLITTER, "BLITTER "); - AMIGAHW_ANNOUNCE(AMBER_FF, "AMBER_FF "); - AMIGAHW_ANNOUNCE(AMI_AUDIO, "AUDIO "); - AMIGAHW_ANNOUNCE(AMI_FLOPPY, "FLOPPY "); - AMIGAHW_ANNOUNCE(A3000_SCSI, "A3000_SCSI "); - AMIGAHW_ANNOUNCE(A4000_SCSI, "A4000_SCSI "); - AMIGAHW_ANNOUNCE(A1200_IDE, "A1200_IDE "); - AMIGAHW_ANNOUNCE(A4000_IDE, "A4000_IDE "); - AMIGAHW_ANNOUNCE(CD_ROM, "CD_ROM "); - AMIGAHW_ANNOUNCE(AMI_KEYBOARD, "KEYBOARD "); - AMIGAHW_ANNOUNCE(AMI_MOUSE, "MOUSE "); - AMIGAHW_ANNOUNCE(AMI_SERIAL, "SERIAL "); - AMIGAHW_ANNOUNCE(AMI_PARALLEL, "PARALLEL "); - AMIGAHW_ANNOUNCE(A2000_CLK, "A2000_CLK "); - AMIGAHW_ANNOUNCE(A3000_CLK, "A3000_CLK "); - AMIGAHW_ANNOUNCE(CHIP_RAM, "CHIP_RAM "); - AMIGAHW_ANNOUNCE(PAULA, "PAULA "); - AMIGAHW_ANNOUNCE(DENISE, "DENISE "); - AMIGAHW_ANNOUNCE(DENISE_HR, "DENISE_HR "); - AMIGAHW_ANNOUNCE(LISA, "LISA "); - AMIGAHW_ANNOUNCE(AGNUS_PAL, "AGNUS_PAL "); - AMIGAHW_ANNOUNCE(AGNUS_NTSC, "AGNUS_NTSC "); - AMIGAHW_ANNOUNCE(AGNUS_HR_PAL, "AGNUS_HR_PAL "); - AMIGAHW_ANNOUNCE(AGNUS_HR_NTSC, "AGNUS_HR_NTSC "); - AMIGAHW_ANNOUNCE(ALICE_PAL, "ALICE_PAL "); - AMIGAHW_ANNOUNCE(ALICE_NTSC, "ALICE_NTSC "); - AMIGAHW_ANNOUNCE(MAGIC_REKICK, "MAGIC_REKICK "); - AMIGAHW_ANNOUNCE(PCMCIA, "PCMCIA "); - if (AMIGAHW_PRESENT(ZORRO)) - printk("ZORRO%s ", AMIGAHW_PRESENT(ZORRO3) ? "3" : ""); - printk("\n"); - -#undef AMIGAHW_ANNOUNCE -} - - /* - * Setup the Amiga configuration info - */ - -void __init config_amiga(void) -{ - int i; - - amiga_debug_init(); - amiga_identify(); - - /* Some APUS boxes may have PCI memory, but ... */ - iomem_resource.name = "Memory"; - for (i = 0; i < 4; i++) - request_resource(&iomem_resource, &((struct resource *)&mb_resources)[i]); - - mach_sched_init = amiga_sched_init; - mach_init_IRQ = amiga_init_IRQ; -#ifndef CONFIG_APUS - mach_default_handler = &amiga_default_handler; - mach_request_irq = amiga_request_irq; - mach_free_irq = amiga_free_irq; - enable_irq = amiga_enable_irq; - disable_irq = amiga_disable_irq; -#endif - mach_get_model = amiga_get_model; - mach_get_hardware_list = amiga_get_hardware_list; - mach_gettimeoffset = amiga_gettimeoffset; - if (AMIGAHW_PRESENT(A3000_CLK)){ - mach_gettod = a3000_gettod; - rtc_resource.name = "A3000 RTC"; - request_resource(&iomem_resource, &rtc_resource); - } - else{ /* if (AMIGAHW_PRESENT(A2000_CLK)) */ - mach_gettod = a2000_gettod; - rtc_resource.name = "A2000 RTC"; - request_resource(&iomem_resource, &rtc_resource); - } - - mach_max_dma_address = 0xffffffff; /* - * default MAX_DMA=0xffffffff - * on all machines. If we don't - * do so, the SCSI code will not - * be able to allocate any mem - * for transfers, unless we are - * dealing with a Z2 mem only - * system. /Jes - */ - - mach_hwclk = amiga_hwclk; - mach_set_clock_mmss = amiga_set_clock_mmss; - mach_reset = amiga_reset; -#ifdef CONFIG_HEARTBEAT - mach_heartbeat = amiga_heartbeat; -#endif - - /* Fill in the clock values (based on the 700 kHz E-Clock) */ - amiga_masterclock = 40*amiga_eclock; /* 28 MHz */ - amiga_colorclock = 5*amiga_eclock; /* 3.5 MHz */ - - /* clear all DMA bits */ - amiga_custom.dmacon = DMAF_ALL; - /* ensure that the DMA master bit is set */ - amiga_custom.dmacon = DMAF_SETCLR | DMAF_MASTER; - - /* request all RAM */ - for (i = 0; i < m68k_num_memory; i++) { - ram_resource[i].name = - (m68k_memory[i].addr >= 0x01000000) ? "32-bit Fast RAM" : - (m68k_memory[i].addr < 0x00c00000) ? "16-bit Fast RAM" : - "16-bit Slow RAM"; - ram_resource[i].start = m68k_memory[i].addr; - ram_resource[i].end = m68k_memory[i].addr+m68k_memory[i].size-1; - request_resource(&iomem_resource, &ram_resource[i]); - } - - /* initialize chipram allocator */ - amiga_chip_init (); - - /* debugging using chipram */ - if (!strcmp( m68k_debug_device, "mem" )){ - if (!AMIGAHW_PRESENT(CHIP_RAM)) - printk("Warning: no chipram present for debugging\n"); - else { - amiga_savekmsg_init(); - amiga_console_driver.write = amiga_mem_console_write; - register_console(&amiga_console_driver); - } - } - - /* our beloved beeper */ - if (AMIGAHW_PRESENT(AMI_AUDIO)) - amiga_init_sound(); - - /* - * if it is an A3000, set the magic bit that forces - * a hard rekick - */ - if (AMIGAHW_PRESENT(MAGIC_REKICK)) - *(unsigned char *)ZTWO_VADDR(0xde0002) |= 0x80; -} - -static unsigned short jiffy_ticks; - -static void __init amiga_sched_init(irqreturn_t (*timer_routine)(int, void *, - struct pt_regs *)) -{ - static struct resource sched_res = { - "timer", 0x00bfd400, 0x00bfd5ff, - }; - jiffy_ticks = (amiga_eclock+HZ/2)/HZ; - - if (request_resource(&mb_resources._ciab, &sched_res)) - printk("Cannot allocate ciab.ta{lo,hi}\n"); - ciab.cra &= 0xC0; /* turn off timer A, continuous mode, from Eclk */ - ciab.talo = jiffy_ticks % 256; - ciab.tahi = jiffy_ticks / 256; - - /* install interrupt service routine for CIAB Timer A - * - * Please don't change this to use ciaa, as it interferes with the - * SCSI code. We'll have to take a look at this later - */ - request_irq(IRQ_AMIGA_CIAB_TA, timer_routine, 0, "timer", NULL); - /* start timer */ - ciab.cra |= 0x11; -} - -#define TICK_SIZE 10000 - -extern unsigned char cia_get_irq_mask(unsigned int irq); - -/* This is always executed with interrupts disabled. */ -static unsigned long amiga_gettimeoffset (void) -{ - unsigned short hi, lo, hi2; - unsigned long ticks, offset = 0; - - /* read CIA B timer A current value */ - hi = ciab.tahi; - lo = ciab.talo; - hi2 = ciab.tahi; - - if (hi != hi2) { - lo = ciab.talo; - hi = hi2; - } - - ticks = hi << 8 | lo; - - if (ticks > jiffy_ticks / 2) - /* check for pending interrupt */ - if (cia_get_irq_mask(IRQ_AMIGA_CIAB) & CIA_ICR_TA) - offset = 10000; - - ticks = jiffy_ticks - ticks; - ticks = (10000 * ticks) / jiffy_ticks; - - return ticks + offset; -} - -static void a3000_gettod (int *yearp, int *monp, int *dayp, - int *hourp, int *minp, int *secp) -{ - volatile struct tod3000 *tod = TOD_3000; - - tod->cntrl1 = TOD3000_CNTRL1_HOLD; - - *secp = tod->second1 * 10 + tod->second2; - *minp = tod->minute1 * 10 + tod->minute2; - *hourp = tod->hour1 * 10 + tod->hour2; - *dayp = tod->day1 * 10 + tod->day2; - *monp = tod->month1 * 10 + tod->month2; - *yearp = tod->year1 * 10 + tod->year2; - - tod->cntrl1 = TOD3000_CNTRL1_FREE; -} - -static void a2000_gettod (int *yearp, int *monp, int *dayp, - int *hourp, int *minp, int *secp) -{ - volatile struct tod2000 *tod = TOD_2000; - - tod->cntrl1 = TOD2000_CNTRL1_HOLD; - - while (tod->cntrl1 & TOD2000_CNTRL1_BUSY) - ; - - *secp = tod->second1 * 10 + tod->second2; - *minp = tod->minute1 * 10 + tod->minute2; - *hourp = (tod->hour1 & 3) * 10 + tod->hour2; - *dayp = tod->day1 * 10 + tod->day2; - *monp = tod->month1 * 10 + tod->month2; - *yearp = tod->year1 * 10 + tod->year2; - - if (!(tod->cntrl3 & TOD2000_CNTRL3_24HMODE)){ - if (!(tod->hour1 & TOD2000_HOUR1_PM) && *hourp == 12) - *hourp = 0; - else if ((tod->hour1 & TOD2000_HOUR1_PM) && *hourp != 12) - *hourp += 12; - } - - tod->cntrl1 &= ~TOD2000_CNTRL1_HOLD; -} - -static int amiga_hwclk(int op, struct hwclk_time *t) -{ - if (AMIGAHW_PRESENT(A3000_CLK)) { - volatile struct tod3000 *tod = TOD_3000; - - tod->cntrl1 = TOD3000_CNTRL1_HOLD; - - if (!op) { /* read */ - t->sec = tod->second1 * 10 + tod->second2; - t->min = tod->minute1 * 10 + tod->minute2; - t->hour = tod->hour1 * 10 + tod->hour2; - t->day = tod->day1 * 10 + tod->day2; - t->wday = tod->weekday; - t->mon = tod->month1 * 10 + tod->month2 - 1; - t->year = tod->year1 * 10 + tod->year2; - if (t->year <= 69) - t->year += 100; - } else { - tod->second1 = t->sec / 10; - tod->second2 = t->sec % 10; - tod->minute1 = t->min / 10; - tod->minute2 = t->min % 10; - tod->hour1 = t->hour / 10; - tod->hour2 = t->hour % 10; - tod->day1 = t->day / 10; - tod->day2 = t->day % 10; - if (t->wday != -1) - tod->weekday = t->wday; - tod->month1 = (t->mon + 1) / 10; - tod->month2 = (t->mon + 1) % 10; - if (t->year >= 100) - t->year -= 100; - tod->year1 = t->year / 10; - tod->year2 = t->year % 10; - } - - tod->cntrl1 = TOD3000_CNTRL1_FREE; - } else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ { - volatile struct tod2000 *tod = TOD_2000; - - tod->cntrl1 = TOD2000_CNTRL1_HOLD; - - while (tod->cntrl1 & TOD2000_CNTRL1_BUSY) - ; - - if (!op) { /* read */ - t->sec = tod->second1 * 10 + tod->second2; - t->min = tod->minute1 * 10 + tod->minute2; - t->hour = (tod->hour1 & 3) * 10 + tod->hour2; - t->day = tod->day1 * 10 + tod->day2; - t->wday = tod->weekday; - t->mon = tod->month1 * 10 + tod->month2 - 1; - t->year = tod->year1 * 10 + tod->year2; - if (t->year <= 69) - t->year += 100; - - if (!(tod->cntrl3 & TOD2000_CNTRL3_24HMODE)){ - if (!(tod->hour1 & TOD2000_HOUR1_PM) && t->hour == 12) - t->hour = 0; - else if ((tod->hour1 & TOD2000_HOUR1_PM) && t->hour != 12) - t->hour += 12; - } - } else { - tod->second1 = t->sec / 10; - tod->second2 = t->sec % 10; - tod->minute1 = t->min / 10; - tod->minute2 = t->min % 10; - if (tod->cntrl3 & TOD2000_CNTRL3_24HMODE) - tod->hour1 = t->hour / 10; - else if (t->hour >= 12) - tod->hour1 = TOD2000_HOUR1_PM + - (t->hour - 12) / 10; - else - tod->hour1 = t->hour / 10; - tod->hour2 = t->hour % 10; - tod->day1 = t->day / 10; - tod->day2 = t->day % 10; - if (t->wday != -1) - tod->weekday = t->wday; - tod->month1 = (t->mon + 1) / 10; - tod->month2 = (t->mon + 1) % 10; - if (t->year >= 100) - t->year -= 100; - tod->year1 = t->year / 10; - tod->year2 = t->year % 10; - } - - tod->cntrl1 &= ~TOD2000_CNTRL1_HOLD; - } - - return 0; -} - -static int amiga_set_clock_mmss (unsigned long nowtime) -{ - short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60; - - if (AMIGAHW_PRESENT(A3000_CLK)) { - volatile struct tod3000 *tod = TOD_3000; - - tod->cntrl1 = TOD3000_CNTRL1_HOLD; - - tod->second1 = real_seconds / 10; - tod->second2 = real_seconds % 10; - tod->minute1 = real_minutes / 10; - tod->minute2 = real_minutes % 10; - - tod->cntrl1 = TOD3000_CNTRL1_FREE; - } else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ { - volatile struct tod2000 *tod = TOD_2000; - - tod->cntrl1 = TOD2000_CNTRL1_HOLD; - - while (tod->cntrl1 & TOD2000_CNTRL1_BUSY) - ; - - tod->second1 = real_seconds / 10; - tod->second2 = real_seconds % 10; - tod->minute1 = real_minutes / 10; - tod->minute2 = real_minutes % 10; - - tod->cntrl1 &= ~TOD2000_CNTRL1_HOLD; - } - - return 0; -} - -static NORET_TYPE void amiga_reset( void ) - ATTRIB_NORET; - -static void amiga_reset (void) -{ - for (;;); -} - - - /* - * Debugging - */ - -#define SAVEKMSG_MAXMEM 128*1024 - -#define SAVEKMSG_MAGIC1 0x53415645 /* 'SAVE' */ -#define SAVEKMSG_MAGIC2 0x4B4D5347 /* 'KMSG' */ - -struct savekmsg { - unsigned long magic1; /* SAVEKMSG_MAGIC1 */ - unsigned long magic2; /* SAVEKMSG_MAGIC2 */ - unsigned long magicptr; /* address of magic1 */ - unsigned long size; - char data[0]; -}; - -static struct savekmsg *savekmsg = NULL; - -static void amiga_mem_console_write(struct console *co, const char *s, - unsigned int count) -{ - if (savekmsg->size+count <= SAVEKMSG_MAXMEM-sizeof(struct savekmsg)) { - memcpy(savekmsg->data+savekmsg->size, s, count); - savekmsg->size += count; - } -} - -static void amiga_savekmsg_init(void) -{ - static struct resource debug_res = { "Debug" }; - - savekmsg = amiga_chip_alloc_res(SAVEKMSG_MAXMEM, &debug_res); - savekmsg->magic1 = SAVEKMSG_MAGIC1; - savekmsg->magic2 = SAVEKMSG_MAGIC2; - savekmsg->magicptr = virt_to_phys(savekmsg); - savekmsg->size = 0; -} - -static void amiga_serial_putc(char c) -{ - amiga_custom.serdat = (unsigned char)c | 0x100; - mb(); - while (!(amiga_custom.serdatr & 0x2000)) - ; -} - -void amiga_serial_console_write(struct console *co, const char *s, - unsigned int count) -{ -#if 0 /* def CONFIG_KGDB */ - /* FIXME:APUS GDB doesn't seem to like O-packages before it is - properly connected with the target. */ - __gdb_output_string (s, count); -#else - while (count--) { - if (*s == '\n') - amiga_serial_putc('\r'); - amiga_serial_putc(*s++); - } -#endif -} - -#ifdef CONFIG_SERIAL_CONSOLE -void amiga_serial_puts(const char *s) -{ - amiga_serial_console_write(NULL, s, strlen(s)); -} - -int amiga_serial_console_wait_key(struct console *co) -{ - int ch; - - while (!(amiga_custom.intreqr & IF_RBF)) - barrier(); - ch = amiga_custom.serdatr & 0xff; - /* clear the interrupt, so that another character can be read */ - amiga_custom.intreq = IF_RBF; - return ch; -} - -void amiga_serial_gets(struct console *co, char *s, int len) -{ - int ch, cnt = 0; - - while (1) { - ch = amiga_serial_console_wait_key(co); - - /* Check for backspace. */ - if (ch == 8 || ch == 127) { - if (cnt == 0) { - amiga_serial_putc('\007'); - continue; - } - cnt--; - amiga_serial_puts("\010 \010"); - continue; - } - - /* Check for enter. */ - if (ch == 10 || ch == 13) - break; - - /* See if line is too long. */ - if (cnt >= len + 1) { - amiga_serial_putc(7); - cnt--; - continue; - } - - /* Store and echo character. */ - s[cnt++] = ch; - amiga_serial_putc(ch); - } - /* Print enter. */ - amiga_serial_puts("\r\n"); - s[cnt] = 0; -} -#endif - -static void __init amiga_debug_init(void) -{ - if (!strcmp( m68k_debug_device, "ser" )) { - /* no initialization required (?) */ - amiga_console_driver.write = amiga_serial_console_write; - register_console(&amiga_console_driver); - } -} - -#ifdef CONFIG_HEARTBEAT -static void amiga_heartbeat(int on) -{ - if (on) - ciaa.pra &= ~2; - else - ciaa.pra |= 2; -} -#endif - - /* - * Amiga specific parts of /proc - */ - -static void amiga_get_model(char *model) -{ - strcpy(model, amiga_model_name); -} - - -static int amiga_get_hardware_list(char *buffer) -{ - int len = 0; - - if (AMIGAHW_PRESENT(CHIP_RAM)) - len += sprintf(buffer+len, "Chip RAM:\t%ldK\n", amiga_chip_size>>10); - len += sprintf(buffer+len, "PS Freq:\t%dHz\nEClock Freq:\t%ldHz\n", - amiga_psfreq, amiga_eclock); - if (AMIGAHW_PRESENT(AMI_VIDEO)) { - char *type; - switch(amiga_chipset) { - case CS_OCS: - type = "OCS"; - break; - case CS_ECS: - type = "ECS"; - break; - case CS_AGA: - type = "AGA"; - break; - default: - type = "Old or Unknown"; - break; - } - len += sprintf(buffer+len, "Graphics:\t%s\n", type); - } - -#define AMIGAHW_ANNOUNCE(name, str) \ - if (AMIGAHW_PRESENT(name)) \ - len += sprintf (buffer+len, "\t%s\n", str) - - len += sprintf (buffer + len, "Detected hardware:\n"); - - AMIGAHW_ANNOUNCE(AMI_VIDEO, "Amiga Video"); - AMIGAHW_ANNOUNCE(AMI_BLITTER, "Blitter"); - AMIGAHW_ANNOUNCE(AMBER_FF, "Amber Flicker Fixer"); - AMIGAHW_ANNOUNCE(AMI_AUDIO, "Amiga Audio"); - AMIGAHW_ANNOUNCE(AMI_FLOPPY, "Floppy Controller"); - AMIGAHW_ANNOUNCE(A3000_SCSI, "SCSI Controller WD33C93 (A3000 style)"); - AMIGAHW_ANNOUNCE(A4000_SCSI, "SCSI Controller NCR53C710 (A4000T style)"); - AMIGAHW_ANNOUNCE(A1200_IDE, "IDE Interface (A1200 style)"); - AMIGAHW_ANNOUNCE(A4000_IDE, "IDE Interface (A4000 style)"); - AMIGAHW_ANNOUNCE(CD_ROM, "Internal CD ROM drive"); - AMIGAHW_ANNOUNCE(AMI_KEYBOARD, "Keyboard"); - AMIGAHW_ANNOUNCE(AMI_MOUSE, "Mouse Port"); - AMIGAHW_ANNOUNCE(AMI_SERIAL, "Serial Port"); - AMIGAHW_ANNOUNCE(AMI_PARALLEL, "Parallel Port"); - AMIGAHW_ANNOUNCE(A2000_CLK, "Hardware Clock (A2000 style)"); - AMIGAHW_ANNOUNCE(A3000_CLK, "Hardware Clock (A3000 style)"); - AMIGAHW_ANNOUNCE(CHIP_RAM, "Chip RAM"); - AMIGAHW_ANNOUNCE(PAULA, "Paula 8364"); - AMIGAHW_ANNOUNCE(DENISE, "Denise 8362"); - AMIGAHW_ANNOUNCE(DENISE_HR, "Denise 8373"); - AMIGAHW_ANNOUNCE(LISA, "Lisa 8375"); - AMIGAHW_ANNOUNCE(AGNUS_PAL, "Normal/Fat PAL Agnus 8367/8371"); - AMIGAHW_ANNOUNCE(AGNUS_NTSC, "Normal/Fat NTSC Agnus 8361/8370"); - AMIGAHW_ANNOUNCE(AGNUS_HR_PAL, "Fat Hires PAL Agnus 8372"); - AMIGAHW_ANNOUNCE(AGNUS_HR_NTSC, "Fat Hires NTSC Agnus 8372"); - AMIGAHW_ANNOUNCE(ALICE_PAL, "PAL Alice 8374"); - AMIGAHW_ANNOUNCE(ALICE_NTSC, "NTSC Alice 8374"); - AMIGAHW_ANNOUNCE(MAGIC_REKICK, "Magic Hard Rekick"); - AMIGAHW_ANNOUNCE(PCMCIA, "PCMCIA Slot"); - if (AMIGAHW_PRESENT(ZORRO)) - len += sprintf(buffer+len, "\tZorro II%s AutoConfig: %d Expansion " - "Device%s\n", - AMIGAHW_PRESENT(ZORRO3) ? "I" : "", - zorro_num_autocon, zorro_num_autocon == 1 ? "" : "s"); - -#undef AMIGAHW_ANNOUNCE - - return(len); -} - -#ifdef CONFIG_APUS -int get_hardware_list(char *buffer) -{ - extern int get_cpuinfo(char *buffer); - int len = 0; - char model[80]; - u_long mem; - int i; - - if (mach_get_model) - mach_get_model(model); - else - strcpy(model, "Unknown PowerPC"); - - len += sprintf(buffer+len, "Model:\t\t%s\n", model); - len += get_cpuinfo(buffer+len); - for (mem = 0, i = 0; i < m68k_realnum_memory; i++) - mem += m68k_memory[i].size; - len += sprintf(buffer+len, "System Memory:\t%ldK\n", mem>>10); - - if (mach_get_hardware_list) - len += mach_get_hardware_list(buffer+len); - - return(len); -} -#endif diff -puN arch/ppc/amiga/ints.c~git-powerpc /dev/null --- a/arch/ppc/amiga/ints.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Linux/m68k general interrupt handling code from arch/m68k/kernel/ints.c - * Needed to drive the m68k emulating IRQ hardware on the PowerUp boards. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* table for system interrupt handlers */ -static irq_handler_t irq_list[SYS_IRQS]; - -static const char *default_names[SYS_IRQS] = { - "spurious int", "int1 handler", "int2 handler", "int3 handler", - "int4 handler", "int5 handler", "int6 handler", "int7 handler" -}; - -/* The number of spurious interrupts */ -volatile unsigned int num_spurious; - -#define NUM_IRQ_NODES 100 -static irq_node_t nodes[NUM_IRQ_NODES]; - - -/* - * void init_IRQ(void) - * - * Parameters: None - * - * Returns: Nothing - * - * This function should be called during kernel startup to initialize - * the IRQ handling routines. - */ - -__init -void m68k_init_IRQ(void) -{ - int i; - - for (i = 0; i < SYS_IRQS; i++) { - if (mach_default_handler) - irq_list[i].handler = (*mach_default_handler)[i]; - irq_list[i].flags = 0; - irq_list[i].dev_id = NULL; - irq_list[i].devname = default_names[i]; - } - - for (i = 0; i < NUM_IRQ_NODES; i++) - nodes[i].handler = NULL; - - mach_init_IRQ (); -} - -irq_node_t *new_irq_node(void) -{ - irq_node_t *node; - short i; - - for (node = nodes, i = NUM_IRQ_NODES-1; i >= 0; node++, i--) - if (!node->handler) - return node; - - printk ("new_irq_node: out of nodes\n"); - return NULL; -} - -int sys_request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long flags, const char *devname, void *dev_id) -{ - if (irq < IRQ1 || irq > IRQ7) { - printk("%s: Incorrect IRQ %d from %s\n", - __FUNCTION__, irq, devname); - return -ENXIO; - } - -#if 0 - if (!(irq_list[irq].flags & IRQ_FLG_STD)) { - if (irq_list[irq].flags & IRQ_FLG_LOCK) { - printk("%s: IRQ %d from %s is not replaceable\n", - __FUNCTION__, irq, irq_list[irq].devname); - return -EBUSY; - } - if (!(flags & IRQ_FLG_REPLACE)) { - printk("%s: %s can't replace IRQ %d from %s\n", - __FUNCTION__, devname, irq, irq_list[irq].devname); - return -EBUSY; - } - } -#endif - - irq_list[irq].handler = handler; - irq_list[irq].flags = flags; - irq_list[irq].dev_id = dev_id; - irq_list[irq].devname = devname; - return 0; -} - -void sys_free_irq(unsigned int irq, void *dev_id) -{ - if (irq < IRQ1 || irq > IRQ7) { - printk("%s: Incorrect IRQ %d\n", __FUNCTION__, irq); - return; - } - - if (irq_list[irq].dev_id != dev_id) - printk("%s: Removing probably wrong IRQ %d from %s\n", - __FUNCTION__, irq, irq_list[irq].devname); - - irq_list[irq].handler = (*mach_default_handler)[irq]; - irq_list[irq].flags = 0; - irq_list[irq].dev_id = NULL; - irq_list[irq].devname = default_names[irq]; -} - -asmlinkage void process_int(unsigned long vec, struct pt_regs *fp) -{ - if (vec >= VEC_INT1 && vec <= VEC_INT7 && !MACH_IS_BVME6000) { - vec -= VEC_SPUR; - kstat_cpu(0).irqs[vec]++; - irq_list[vec].handler(vec, irq_list[vec].dev_id, fp); - } else { - if (mach_process_int) - mach_process_int(vec, fp); - else - panic("Can't process interrupt vector %ld\n", vec); - return; - } -} - -int m68k_get_irq_list(struct seq_file *p, void *v) -{ - int i; - - /* autovector interrupts */ - if (mach_default_handler) { - for (i = 0; i < SYS_IRQS; i++) { - seq_printf(p, "auto %2d: %10u ", i, - i ? kstat_cpu(0).irqs[i] : num_spurious); - seq_puts(p, " "); - seq_printf(p, "%s\n", irq_list[i].devname); - } - } - - mach_get_irq_list(p, v); - return 0; -} diff -puN arch/ppc/amiga/pcmcia.c~git-powerpc /dev/null --- a/arch/ppc/amiga/pcmcia.c +++ /dev/null @@ -1 +0,0 @@ -#include "../../m68k/amiga/pcmcia.c" diff -puN arch/ppc/amiga/time.c~git-powerpc /dev/null --- a/arch/ppc/amiga/time.c +++ /dev/null @@ -1,57 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -unsigned long m68k_get_rtc_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - - extern void arch_gettod(int *year, int *mon, int *day, int *hour, - int *min, int *sec); - - arch_gettod (&year, &mon, &day, &hour, &min, &sec); - - if ((year += 1900) < 1970) - year += 100; - - return mktime(year, mon, day, hour, min, sec); -} - -int m68k_set_rtc_time(unsigned long nowtime) -{ - if (mach_set_clock_mmss) - return mach_set_clock_mmss (nowtime); - return -1; -} - -void apus_heartbeat (void) -{ -#ifdef CONFIG_HEARTBEAT - static unsigned cnt = 0, period = 0, dist = 0; - - if (cnt == 0 || cnt == dist) - mach_heartbeat( 1 ); - else if (cnt == 7 || cnt == dist+7) - mach_heartbeat( 0 ); - - if (++cnt > period) { - cnt = 0; - /* The hyperbolic function below modifies the heartbeat period - * length in dependency of the current (5min) load. It goes - * through the points f(0)=126, f(1)=86, f(5)=51, - * f(inf)->30. */ - period = ((672< #include -#ifdef CONFIG_APUS -#include -#endif - /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ #define LOAD_BAT(n, reg, RA, RB) \ /* see the comment for clear_bats() -- Cort */ \ @@ -128,14 +124,6 @@ __start: */ bl early_init -#ifdef CONFIG_APUS -/* On APUS the __va/__pa constants need to be set to the correct - * values before continuing. - */ - mr r4,r30 - bl fix_mem_constants -#endif /* CONFIG_APUS */ - /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains * the physical address we are running at, returned by early_init() */ @@ -145,7 +133,7 @@ __after_mmu_off: bl flush_tlbs bl initial_bats -#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) +#ifdef CONFIG_BOOTX_TEXT bl setup_disp_bat #endif @@ -161,7 +149,6 @@ __after_mmu_off: #endif /* CONFIG_6xx */ -#ifndef CONFIG_APUS /* * We need to run with _start at physical address 0. * If the MMU is already turned on, we copy stuff to KERNELBASE, @@ -172,7 +159,7 @@ __after_mmu_off: addis r4,r3,KERNELBASE@h /* current address of _start */ cmpwi 0,r4,0 /* are we already running at 0? */ bne relocate_kernel -#endif /* CONFIG_APUS */ + /* * we now have the 1st 16M of ram mapped with the bats. * prep needs the mmu to be turned on here, but pmac already has it on. @@ -812,85 +799,6 @@ copy_and_flush: addi r6,r6,4 blr -#ifdef CONFIG_APUS -/* - * On APUS the physical base address of the kernel is not known at compile - * time, which means the __pa/__va constants used are incorrect. In the - * __init section is recorded the virtual addresses of instructions using - * these constants, so all that has to be done is fix these before - * continuing the kernel boot. - * - * r4 = The physical address of the kernel base. - */ -fix_mem_constants: - mr r10,r4 - addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */ - neg r11,r10 /* phys_to_virt constant */ - - lis r12,__vtop_table_begin@h - ori r12,r12,__vtop_table_begin@l - add r12,r12,r10 /* table begin phys address */ - lis r13,__vtop_table_end@h - ori r13,r13,__vtop_table_end@l - add r13,r13,r10 /* table end phys address */ - subi r12,r12,4 - subi r13,r13,4 -1: lwzu r14,4(r12) /* virt address of instruction */ - add r14,r14,r10 /* phys address of instruction */ - lwz r15,0(r14) /* instruction, now insert top */ - rlwimi r15,r10,16,16,31 /* half of vp const in low half */ - stw r15,0(r14) /* of instruction and restore. */ - dcbst r0,r14 /* write it to memory */ - sync - icbi r0,r14 /* flush the icache line */ - cmpw r12,r13 - bne 1b - sync /* additional sync needed on g4 */ - isync - -/* - * Map the memory where the exception handlers will - * be copied to when hash constants have been patched. - */ -#ifdef CONFIG_APUS_FAST_EXCEPT - lis r8,0xfff0 -#else - lis r8,0 -#endif - ori r8,r8,0x2 /* 128KB, supervisor */ - mtspr SPRN_DBAT3U,r8 - mtspr SPRN_DBAT3L,r8 - - lis r12,__ptov_table_begin@h - ori r12,r12,__ptov_table_begin@l - add r12,r12,r10 /* table begin phys address */ - lis r13,__ptov_table_end@h - ori r13,r13,__ptov_table_end@l - add r13,r13,r10 /* table end phys address */ - subi r12,r12,4 - subi r13,r13,4 -1: lwzu r14,4(r12) /* virt address of instruction */ - add r14,r14,r10 /* phys address of instruction */ - lwz r15,0(r14) /* instruction, now insert top */ - rlwimi r15,r11,16,16,31 /* half of pv const in low half*/ - stw r15,0(r14) /* of instruction and restore. */ - dcbst r0,r14 /* write it to memory */ - sync - icbi r0,r14 /* flush the icache line */ - cmpw r12,r13 - bne 1b - - sync /* additional sync needed on g4 */ - isync /* No speculative loading until now */ - blr - -/*********************************************************************** - * Please note that on APUS the exception handlers are located at the - * physical address 0xfff0000. For this reason, the exception handlers - * cannot use relative branches to access the code below. - ***********************************************************************/ -#endif /* CONFIG_APUS */ - #ifdef CONFIG_SMP .globl __secondary_start_pmac_0 __secondary_start_pmac_0: @@ -1043,19 +951,6 @@ start_here: bl machine_init bl MMU_init -#ifdef CONFIG_APUS - /* Copy exception code to exception vector base on APUS. */ - lis r4,KERNELBASE@h -#ifdef CONFIG_APUS_FAST_EXCEPT - lis r3,0xfff0 /* Copy to 0xfff00000 */ -#else - lis r3,0 /* Copy to 0x00000000 */ -#endif - li r5,0x4000 /* # bytes of memory to copy */ - li r6,0 - bl copy_and_flush /* copy the first 0x4000 bytes */ -#endif /* CONFIG_APUS */ - /* * Go back to running unmapped so we can load up new values * for SDR1 (hash table pointer) and the segment registers @@ -1232,11 +1127,7 @@ initial_bats: #else ori r8,r8,2 /* R/W access */ #endif /* CONFIG_SMP */ -#ifdef CONFIG_APUS - ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */ -#else ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */ -#endif /* CONFIG_APUS */ mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ @@ -1245,7 +1136,7 @@ initial_bats: isync blr -#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) +#ifdef CONFIG_BOOTX_TEXT setup_disp_bat: /* * setup the display bat prepared for us in prom.c @@ -1268,7 +1159,7 @@ setup_disp_bat: mtspr SPRN_IBAT3U,r11 blr -#endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */ +#endif /* defined(CONFIG_BOOTX_TEXT) */ #ifdef CONFIG_8260 /* Jump into the system reset for the rom. diff -puN arch/ppc/kernel/ppc_ksyms.c~git-powerpc arch/ppc/kernel/ppc_ksyms.c --- a/arch/ppc/kernel/ppc_ksyms.c~git-powerpc +++ a/arch/ppc/kernel/ppc_ksyms.c @@ -60,8 +60,6 @@ long long __ashrdi3(long long, int); long long __ashldi3(long long, int); long long __lshrdi3(long long, int); -extern unsigned long mm_ptov (unsigned long paddr); - EXPORT_SYMBOL(clear_pages); EXPORT_SYMBOL(clear_user_page); EXPORT_SYMBOL(transfer_to_handler); @@ -118,7 +116,6 @@ EXPORT_SYMBOL(_outsw_ns); EXPORT_SYMBOL(_insl_ns); EXPORT_SYMBOL(_outsl_ns); EXPORT_SYMBOL(iopa); -EXPORT_SYMBOL(mm_ptov); EXPORT_SYMBOL(ioremap); #ifdef CONFIG_44x EXPORT_SYMBOL(ioremap64); diff -puN arch/ppc/kernel/setup.c~git-powerpc arch/ppc/kernel/setup.c --- a/arch/ppc/kernel/setup.c~git-powerpc +++ a/arch/ppc/kernel/setup.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include diff -puN arch/ppc/mm/pgtable.c~git-powerpc arch/ppc/mm/pgtable.c --- a/arch/ppc/mm/pgtable.c~git-powerpc +++ a/arch/ppc/mm/pgtable.c @@ -426,41 +426,3 @@ unsigned long iopa(unsigned long addr) return(pa); } -/* This is will find the virtual address for a physical one.... - * Swiped from APUS, could be dangerous :-). - * This is only a placeholder until I really find a way to make this - * work. -- Dan - */ -unsigned long -mm_ptov (unsigned long paddr) -{ - unsigned long ret; -#if 0 - if (paddr < 16*1024*1024) - ret = ZTWO_VADDR(paddr); - else { - int i; - - for (i = 0; i < kmap_chunk_count;){ - unsigned long phys = kmap_chunks[i++]; - unsigned long size = kmap_chunks[i++]; - unsigned long virt = kmap_chunks[i++]; - if (paddr >= phys - && paddr < (phys + size)){ - ret = virt + paddr - phys; - goto exit; - } - } - - ret = (unsigned long) __va(paddr); - } -exit: -#ifdef DEBUGPV - printk ("PTOV(%lx)=%lx\n", paddr, ret); -#endif -#else - ret = (unsigned long)paddr + KERNELBASE; -#endif - return ret; -} - diff -puN arch/ppc/platforms/Makefile~git-powerpc arch/ppc/platforms/Makefile --- a/arch/ppc/platforms/Makefile~git-powerpc +++ a/arch/ppc/platforms/Makefile @@ -2,10 +2,6 @@ # Makefile for the linux kernel. # -obj-$(CONFIG_APUS) += apus_setup.o -ifeq ($(CONFIG_APUS),y) -obj-$(CONFIG_PCI) += apus_pci.o -endif obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o obj-$(CONFIG_PREP_RESIDUAL) += residual.o obj-$(CONFIG_PQ2ADS) += pq2ads.o diff -puN arch/ppc/platforms/apus_pci.c~git-powerpc /dev/null --- a/arch/ppc/platforms/apus_pci.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (C) Michel Dänzer - * - * APUS PCI routines. - * - * Currently, only B/CVisionPPC cards (Permedia2) are supported. - * - * Thanks to Geert Uytterhoeven for the idea: - * Read values from given config space(s) for the first devices, -1 otherwise - * - */ - -#ifdef CONFIG_AMIGA - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "apus_pci.h" - - -/* These definitions are mostly adapted from pm2fb.c */ - -#undef APUS_PCI_MASTER_DEBUG -#ifdef APUS_PCI_MASTER_DEBUG -#define DPRINTK(a,b...) printk(KERN_DEBUG "apus_pci: %s: " a, __FUNCTION__ , ## b) -#else -#define DPRINTK(a,b...) -#endif - -/* - * The _DEFINITIVE_ memory mapping/unmapping functions. - * This is due to the fact that they're changing soooo often... - */ -#define DEFW() wmb() -#define DEFR() rmb() -#define DEFRW() mb() - -#define DEVNO(d) ((d)>>3) -#define FNNO(d) ((d)&7) - - -extern unsigned long powerup_PCI_present; - -static struct pci_controller *apus_hose; - - -void *pci_io_base(unsigned int bus) -{ - return 0; -} - - -int -apus_pcibios_read_config(struct pci_bus *bus, int devfn, int offset, - int len, u32 *val) -{ - int fnno = FNNO(devfn); - int devno = DEVNO(devfn); - volatile unsigned char *cfg_data; - - if (bus->number > 0 || devno != 1) { - *val = ~0; - return PCIBIOS_DEVICE_NOT_FOUND; - } - /* base address + function offset + offset ^ endianness conversion */ - /* XXX the fnno<<5 bit seems wacky -- paulus */ - cfg_data = apus_hose->cfg_data + (fnno<<5) + (offset ^ (len - 1)); - switch (len) { - case 1: - *val = readb(cfg_data); - break; - case 2: - *val = readw(cfg_data); - break; - default: - *val = readl(cfg_data); - break; - } - - DPRINTK("read b: 0x%x, d: 0x%x, f: 0x%x, o: 0x%x, l: %d, v: 0x%x\n", - bus->number, devfn>>3, devfn&7, offset, len, *val); - return PCIBIOS_SUCCESSFUL; -} - -int -apus_pcibios_write_config(struct pci_bus *bus, int devfn, int offset, - int len, u32 *val) -{ - int fnno = FNNO(devfn); - int devno = DEVNO(devfn); - volatile unsigned char *cfg_data; - - if (bus->number > 0 || devno != 1) { - return PCIBIOS_DEVICE_NOT_FOUND; - } - /* base address + function offset + offset ^ endianness conversion */ - /* XXX the fnno<<5 bit seems wacky -- paulus */ - cfg_data = apus_hose->cfg_data + (fnno<<5) + (offset ^ (len - 1)); - switch (len) { - case 1: - writeb(val, cfg_data); DEFW(); - break; - case 2: - writew(val, cfg_data); DEFW(); - break; - default: - writel(val, cfg_data); DEFW(); - break; - } - - DPRINTK("write b: 0x%x, d: 0x%x, f: 0x%x, o: 0x%x, l: %d, v: 0x%x\n", - bus->number, devfn>>3, devfn&7, offset, len, val); - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops apus_pci_ops = { - apus_pcibios_read_config, - apus_pcibios_write_config -}; - -static struct resource pci_mem = { "B/CVisionPPC PCI mem", CVPPC_FB_APERTURE_ONE, CVPPC_PCI_CONFIG, IORESOURCE_MEM }; - -void __init -apus_pcibios_fixup(void) -{ -/* struct pci_dev *dev = pci_find_slot(0, 1<<3); - unsigned int reg, val, offset;*/ - - /* FIXME: interrupt? */ - /*dev->interrupt = xxx;*/ - - request_resource(&iomem_resource, &pci_mem); - printk("%s: PCI mem resource requested\n", __FUNCTION__); -} - -static void __init apus_pcibios_fixup_bus(struct pci_bus *bus) -{ - bus->resource[1] = &pci_mem; -} - - -/* - * This is from pm2fb.c again - * - * Check if PCI (B/CVisionPPC) is available, initialize it and set up - * the pcibios_* pointers - */ - - -void __init -apus_setup_pci_ptrs(void) -{ - if (!powerup_PCI_present) { - DPRINTK("no PCI bridge detected\n"); - return; - } - DPRINTK("Phase5 B/CVisionPPC PCI bridge detected.\n"); - - apus_hose = pcibios_alloc_controller(); - if (!apus_hose) { - printk("apus_pci: Can't allocate PCI controller structure\n"); - return; - } - - if (!(apus_hose->cfg_data = ioremap(CVPPC_PCI_CONFIG, 256))) { - printk("apus_pci: unable to map PCI config region\n"); - return; - } - - if (!(apus_hose->cfg_addr = ioremap(CSPPC_PCI_BRIDGE, 256))) { - printk("apus_pci: unable to map PCI bridge\n"); - return; - } - - writel(CSPPCF_BRIDGE_BIG_ENDIAN, apus_hose->cfg_addr + CSPPC_BRIDGE_ENDIAN); - DEFW(); - - writel(CVPPC_REGS_REGION, apus_hose->cfg_data+ PCI_BASE_ADDRESS_0); - DEFW(); - writel(CVPPC_FB_APERTURE_ONE, apus_hose->cfg_data + PCI_BASE_ADDRESS_1); - DEFW(); - writel(CVPPC_FB_APERTURE_TWO, apus_hose->cfg_data + PCI_BASE_ADDRESS_2); - DEFW(); - writel(CVPPC_ROM_ADDRESS, apus_hose->cfg_data + PCI_ROM_ADDRESS); - DEFW(); - - writel(0xef000000 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER, apus_hose->cfg_data + PCI_COMMAND); - DEFW(); - - apus_hose->first_busno = 0; - apus_hose->last_busno = 0; - apus_hose->ops = &apus_pci_ops; - ppc_md.pcibios_fixup = apus_pcibios_fixup; - ppc_md.pcibios_fixup_bus = apus_pcibios_fixup_bus; - - return; -} - -#endif /* CONFIG_AMIGA */ diff -puN arch/ppc/platforms/apus_pci.h~git-powerpc /dev/null --- a/arch/ppc/platforms/apus_pci.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer - * driver. - * - * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) - * -------------------------------------------------------------------------- - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file README.legal in the main directory of this archive - * for more details. - */ - -#ifndef APUS_PCI_H -#define APUS_PCI_H - - -#define CSPPC_PCI_BRIDGE 0xfffe0000 -#define CSPPC_BRIDGE_ENDIAN 0x0000 -#define CSPPC_BRIDGE_INT 0x0010 - -#define CVPPC_PCI_CONFIG 0xfffc0000 -#define CVPPC_ROM_ADDRESS 0xe2000001 -#define CVPPC_REGS_REGION 0xef000000 -#define CVPPC_FB_APERTURE_ONE 0xe0000000 -#define CVPPC_FB_APERTURE_TWO 0xe1000000 -#define CVPPC_FB_SIZE 0x00800000 - -/* CVPPC_BRIDGE_ENDIAN */ -#define CSPPCF_BRIDGE_BIG_ENDIAN 0x02 - -/* CVPPC_BRIDGE_INT */ -#define CSPPCF_BRIDGE_ACTIVE_INT2 0x01 - - -#endif /* APUS_PCI_H */ diff -puN arch/ppc/platforms/apus_setup.c~git-powerpc /dev/null --- a/arch/ppc/platforms/apus_setup.c +++ /dev/null @@ -1,798 +0,0 @@ -/* - * Copyright (C) 1998, 1999 Jesper Skov - * - * Basically what is needed to replace functionality found in - * arch/m68k allowing Amiga drivers to work under APUS. - * Bits of code and/or ideas from arch/m68k and arch/ppc files. - * - * TODO: - * This file needs a *really* good cleanup. Restructure and optimize. - * Make sure it can be compiled for non-APUS configs. Begin to move - * Amiga specific stuff into mach/amiga. - */ - -#include -#include -#include -#include -#include - -/* Needs INITSERIAL call in head.S! */ -#undef APUS_DEBUG - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -unsigned long m68k_machtype; -char debug_device[6] = ""; - -extern void amiga_init_IRQ(void); - -extern void apus_setup_pci_ptrs(void); - -void (*mach_sched_init) (void (*handler)(int, void *, struct pt_regs *)) __initdata = NULL; -/* machine dependent irq functions */ -void (*mach_init_IRQ) (void) __initdata = NULL; -void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *) = NULL; -void (*mach_get_model) (char *model) = NULL; -int (*mach_get_hardware_list) (char *buffer) = NULL; -int (*mach_get_irq_list) (struct seq_file *, void *) = NULL; -void (*mach_process_int) (int, struct pt_regs *) = NULL; -/* machine dependent timer functions */ -unsigned long (*mach_gettimeoffset) (void); -void (*mach_gettod) (int*, int*, int*, int*, int*, int*); -int (*mach_hwclk) (int, struct hwclk_time*) = NULL; -int (*mach_set_clock_mmss) (unsigned long) = NULL; -void (*mach_reset)( void ); -long mach_max_dma_address = 0x00ffffff; /* default set to the lower 16MB */ -#ifdef CONFIG_HEARTBEAT -void (*mach_heartbeat) (int) = NULL; -extern void apus_heartbeat (void); -#endif - -extern unsigned long amiga_model; -extern unsigned decrementer_count;/* count value for 1e6/HZ microseconds */ -extern unsigned count_period_num; /* 1 decrementer count equals */ -extern unsigned count_period_den; /* count_period_num / count_period_den us */ - -int num_memory = 0; -struct mem_info memory[NUM_MEMINFO];/* memory description */ -/* FIXME: Duplicate memory data to avoid conflicts with m68k shared code. */ -int m68k_realnum_memory = 0; -struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ - -struct mem_info ramdisk; - -extern void config_amiga(void); - -static int __60nsram = 0; - -/* for cpuinfo */ -static int __bus_speed = 0; -static int __speed_test_failed = 0; - -/********************************************** COMPILE PROTECTION */ -/* Provide some stubs that links to Amiga specific functions. - * This allows CONFIG_APUS to be removed from generic PPC files while - * preventing link errors for other PPC targets. - */ -unsigned long apus_get_rtc_time(void) -{ -#ifdef CONFIG_APUS - extern unsigned long m68k_get_rtc_time(void); - - return m68k_get_rtc_time (); -#else - return 0; -#endif -} - -int apus_set_rtc_time(unsigned long nowtime) -{ -#ifdef CONFIG_APUS - extern int m68k_set_rtc_time(unsigned long nowtime); - - return m68k_set_rtc_time (nowtime); -#else - return 0; -#endif -} - -/*********************************************************** SETUP */ -/* From arch/m68k/kernel/setup.c. */ -void __init apus_setup_arch(void) -{ -#ifdef CONFIG_APUS - extern char cmd_line[]; - int i; - char *p, *q; - - /* Let m68k-shared code know it should do the Amiga thing. */ - m68k_machtype = MACH_AMIGA; - - /* Parse the command line for arch-specific options. - * For the m68k, this is currently only "debug=xxx" to enable printing - * certain kernel messages to some machine-specific device. */ - for( p = cmd_line; p && *p; ) { - i = 0; - if (!strncmp( p, "debug=", 6 )) { - strlcpy( debug_device, p+6, sizeof(debug_device) ); - if ((q = strchr( debug_device, ' ' ))) *q = 0; - i = 1; - } else if (!strncmp( p, "60nsram", 7 )) { - APUS_WRITE (APUS_REG_WAITSTATE, - REGWAITSTATE_SETRESET - |REGWAITSTATE_PPCR - |REGWAITSTATE_PPCW); - __60nsram = 1; - i = 1; - } - - if (i) { - /* option processed, delete it */ - if ((q = strchr( p, ' ' ))) - strcpy( p, q+1 ); - else - *p = 0; - } else { - if ((p = strchr( p, ' ' ))) ++p; - } - } - - config_amiga(); - -#if 0 /* Enable for logging - also include logging.o in Makefile rule */ - { -#define LOG_SIZE 4096 - void* base; - - /* Throw away some memory - the P5 firmare stomps on top - * of CHIP memory during bootup. - */ - amiga_chip_alloc(0x1000); - - base = amiga_chip_alloc(LOG_SIZE+sizeof(klog_data_t)); - LOG_INIT(base, base+sizeof(klog_data_t), LOG_SIZE); - } -#endif -#endif -} - -int -apus_show_cpuinfo(struct seq_file *m) -{ - extern int __map_without_bats; - extern unsigned long powerup_PCI_present; - - seq_printf(m, "machine\t\t: Amiga\n"); - seq_printf(m, "bus speed\t: %d%s", __bus_speed, - (__speed_test_failed) ? " [failed]\n" : "\n"); - seq_printf(m, "using BATs\t: %s\n", - (__map_without_bats) ? "No" : "Yes"); - seq_printf(m, "ram speed\t: %dns\n", (__60nsram) ? 60 : 70); - seq_printf(m, "PCI bridge\t: %s\n", - (powerup_PCI_present) ? "Yes" : "No"); - return 0; -} - -static void get_current_tb(unsigned long long *time) -{ - __asm __volatile ("1:mftbu 4 \n\t" - " mftb 5 \n\t" - " mftbu 6 \n\t" - " cmpw 4,6 \n\t" - " bne 1b \n\t" - " stw 4,0(%0)\n\t" - " stw 5,4(%0)\n\t" - : - : "r" (time) - : "r4", "r5", "r6"); -} - - -void apus_calibrate_decr(void) -{ -#ifdef CONFIG_APUS - unsigned long freq; - - /* This algorithm for determining the bus speed was - contributed by Ralph Schmidt. */ - unsigned long long start, stop; - int bus_speed; - int speed_test_failed = 0; - - { - unsigned long loop = amiga_eclock / 10; - - get_current_tb (&start); - while (loop--) { - unsigned char tmp; - - tmp = ciaa.pra; - } - get_current_tb (&stop); - } - - bus_speed = (((unsigned long)(stop-start))*10*4) / 1000000; - if (AMI_1200 == amiga_model) - bus_speed /= 2; - - if ((bus_speed >= 47) && (bus_speed < 53)) { - bus_speed = 50; - freq = 12500000; - } else if ((bus_speed >= 57) && (bus_speed < 63)) { - bus_speed = 60; - freq = 15000000; - } else if ((bus_speed >= 63) && (bus_speed < 69)) { - bus_speed = 67; - freq = 16666667; - } else { - printk ("APUS: Unable to determine bus speed (%d). " - "Defaulting to 50MHz", bus_speed); - bus_speed = 50; - freq = 12500000; - speed_test_failed = 1; - } - - /* Ease diagnostics... */ - { - extern int __map_without_bats; - extern unsigned long powerup_PCI_present; - - printk ("APUS: BATs=%d, BUS=%dMHz", - (__map_without_bats) ? 0 : 1, - bus_speed); - if (speed_test_failed) - printk ("[FAILED - please report]"); - - printk (", RAM=%dns, PCI bridge=%d\n", - (__60nsram) ? 60 : 70, - (powerup_PCI_present) ? 1 : 0); - - /* print a bit more if asked politely... */ - if (!(ciaa.pra & 0x40)){ - extern unsigned int bat_addrs[4][3]; - int b; - for (b = 0; b < 4; ++b) { - printk ("APUS: BAT%d ", b); - printk ("%08x-%08x -> %08x\n", - bat_addrs[b][0], - bat_addrs[b][1], - bat_addrs[b][2]); - } - } - - } - - printk("time_init: decrementer frequency = %lu.%.6lu MHz\n", - freq/1000000, freq%1000000); - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); - - __bus_speed = bus_speed; - __speed_test_failed = speed_test_failed; -#endif -} - -void arch_gettod(int *year, int *mon, int *day, int *hour, - int *min, int *sec) -{ -#ifdef CONFIG_APUS - if (mach_gettod) - mach_gettod(year, mon, day, hour, min, sec); - else - *year = *mon = *day = *hour = *min = *sec = 0; -#endif -} - -/* for "kbd-reset" cmdline param */ -__init -void kbd_reset_setup(char *str, int *ints) -{ -} - -/*********************************************************** MEMORY */ -#define KMAP_MAX 32 -unsigned long kmap_chunks[KMAP_MAX*3]; -int kmap_chunk_count = 0; - -/* From pgtable.h */ -static __inline__ pte_t *my_find_pte(struct mm_struct *mm,unsigned long va) -{ - pgd_t *dir = 0; - pmd_t *pmd = 0; - pte_t *pte = 0; - - va &= PAGE_MASK; - - dir = pgd_offset( mm, va ); - if (dir) - { - pmd = pmd_offset(dir, va & PAGE_MASK); - if (pmd && pmd_present(*pmd)) - { - pte = pte_offset(pmd, va); - } - } - return pte; -} - - -/* Again simulating an m68k/mm/kmap.c function. */ -void kernel_set_cachemode( unsigned long address, unsigned long size, - unsigned int cmode ) -{ - unsigned long mask, flags; - - switch (cmode) - { - case IOMAP_FULL_CACHING: - mask = ~(_PAGE_NO_CACHE | _PAGE_GUARDED); - flags = 0; - break; - case IOMAP_NOCACHE_SER: - mask = ~0; - flags = (_PAGE_NO_CACHE | _PAGE_GUARDED); - break; - default: - panic ("kernel_set_cachemode() doesn't support mode %d\n", - cmode); - break; - } - - size /= PAGE_SIZE; - address &= PAGE_MASK; - while (size--) - { - pte_t *pte; - - pte = my_find_pte(&init_mm, address); - if ( !pte ) - { - printk("pte NULL in kernel_set_cachemode()\n"); - return; - } - - pte_val (*pte) &= mask; - pte_val (*pte) |= flags; - flush_tlb_page(find_vma(&init_mm,address),address); - - address += PAGE_SIZE; - } -} - -unsigned long mm_ptov (unsigned long paddr) -{ - unsigned long ret; - if (paddr < 16*1024*1024) - ret = ZTWO_VADDR(paddr); - else { - int i; - - for (i = 0; i < kmap_chunk_count;){ - unsigned long phys = kmap_chunks[i++]; - unsigned long size = kmap_chunks[i++]; - unsigned long virt = kmap_chunks[i++]; - if (paddr >= phys - && paddr < (phys + size)){ - ret = virt + paddr - phys; - goto exit; - } - } - - ret = (unsigned long) __va(paddr); - } -exit: -#ifdef DEBUGPV - printk ("PTOV(%lx)=%lx\n", paddr, ret); -#endif - return ret; -} - -int mm_end_of_chunk (unsigned long addr, int len) -{ - if (memory[0].addr + memory[0].size == addr + len) - return 1; - return 0; -} - -/*********************************************************** CACHE */ - -#define L1_CACHE_BYTES 32 -#define MAX_CACHE_SIZE 8192 -void cache_push(__u32 addr, int length) -{ - addr = mm_ptov(addr); - - if (MAX_CACHE_SIZE < length) - length = MAX_CACHE_SIZE; - - while(length > 0){ - __asm ("dcbf 0,%0\n\t" - : : "r" (addr)); - addr += L1_CACHE_BYTES; - length -= L1_CACHE_BYTES; - } - /* Also flush trailing block */ - __asm ("dcbf 0,%0\n\t" - "sync \n\t" - : : "r" (addr)); -} - -void cache_clear(__u32 addr, int length) -{ - if (MAX_CACHE_SIZE < length) - length = MAX_CACHE_SIZE; - - addr = mm_ptov(addr); - - __asm ("dcbf 0,%0\n\t" - "sync \n\t" - "icbi 0,%0 \n\t" - "isync \n\t" - : : "r" (addr)); - - addr += L1_CACHE_BYTES; - length -= L1_CACHE_BYTES; - - while(length > 0){ - __asm ("dcbf 0,%0\n\t" - "sync \n\t" - "icbi 0,%0 \n\t" - "isync \n\t" - : : "r" (addr)); - addr += L1_CACHE_BYTES; - length -= L1_CACHE_BYTES; - } - - __asm ("dcbf 0,%0\n\t" - "sync \n\t" - "icbi 0,%0 \n\t" - "isync \n\t" - : : "r" (addr)); -} - -/****************************************************** from setup.c */ -void -apus_restart(char *cmd) -{ - local_irq_disable(); - - APUS_WRITE(APUS_REG_LOCK, - REGLOCK_BLACKMAGICK1|REGLOCK_BLACKMAGICK2); - APUS_WRITE(APUS_REG_LOCK, - REGLOCK_BLACKMAGICK1|REGLOCK_BLACKMAGICK3); - APUS_WRITE(APUS_REG_LOCK, - REGLOCK_BLACKMAGICK2|REGLOCK_BLACKMAGICK3); - APUS_WRITE(APUS_REG_SHADOW, REGSHADOW_SELFRESET); - APUS_WRITE(APUS_REG_RESET, REGRESET_AMIGARESET); - for(;;); -} - -void -apus_power_off(void) -{ - for (;;); -} - -void -apus_halt(void) -{ - apus_restart(NULL); -} - -/****************************************************** IRQ stuff */ - -static unsigned char last_ipl[8]; - -int apus_get_irq(void) -{ - unsigned char ipl_emu, mask; - unsigned int level; - - APUS_READ(APUS_IPL_EMU, ipl_emu); - level = (ipl_emu >> 3) & IPLEMU_IPLMASK; - mask = IPLEMU_SETRESET|IPLEMU_DISABLEINT|level; - level ^= 7; - - /* Save previous IPL value */ - if (last_ipl[level]) - return -2; - last_ipl[level] = ipl_emu; - - /* Set to current IPL value */ - APUS_WRITE(APUS_IPL_EMU, mask); - APUS_WRITE(APUS_IPL_EMU, IPLEMU_DISABLEINT|level); - - -#ifdef __INTERRUPT_DEBUG - printk("<%d:%d>", level, ~ipl_emu & IPLEMU_IPLMASK); -#endif - return level + IRQ_AMIGA_AUTO; -} - -void apus_end_irq(unsigned int irq) -{ - unsigned char ipl_emu; - unsigned int level = irq - IRQ_AMIGA_AUTO; -#ifdef __INTERRUPT_DEBUG - printk("{%d}", ~last_ipl[level] & IPLEMU_IPLMASK); -#endif - /* Restore IPL to the previous value */ - ipl_emu = last_ipl[level] & IPLEMU_IPLMASK; - APUS_WRITE(APUS_IPL_EMU, IPLEMU_SETRESET|IPLEMU_DISABLEINT|ipl_emu); - last_ipl[level] = 0; - ipl_emu ^= 7; - APUS_WRITE(APUS_IPL_EMU, IPLEMU_DISABLEINT|ipl_emu); -} - -/****************************************************** debugging */ - -/* some serial hardware definitions */ -#define SDR_OVRUN (1<<15) -#define SDR_RBF (1<<14) -#define SDR_TBE (1<<13) -#define SDR_TSRE (1<<12) - -#define AC_SETCLR (1<<15) -#define AC_UARTBRK (1<<11) - -#define SER_DTR (1<<7) -#define SER_RTS (1<<6) -#define SER_DCD (1<<5) -#define SER_CTS (1<<4) -#define SER_DSR (1<<3) - -static __inline__ void ser_RTSon(void) -{ - ciab.pra &= ~SER_RTS; /* active low */ -} - -int __debug_ser_out( unsigned char c ) -{ - amiga_custom.serdat = c | 0x100; - mb(); - while (!(amiga_custom.serdatr & 0x2000)) - barrier(); - return 1; -} - -unsigned char __debug_ser_in( void ) -{ - unsigned char c; - - /* XXX: is that ok?? derived from amiga_ser.c... */ - while( !(amiga_custom.intreqr & IF_RBF) ) - barrier(); - c = amiga_custom.serdatr; - /* clear the interrupt, so that another character can be read */ - amiga_custom.intreq = IF_RBF; - return c; -} - -int __debug_serinit( void ) -{ - unsigned long flags; - - local_irq_save(flags); - - /* turn off Rx and Tx interrupts */ - amiga_custom.intena = IF_RBF | IF_TBE; - - /* clear any pending interrupt */ - amiga_custom.intreq = IF_RBF | IF_TBE; - - local_irq_restore(flags); - - /* - * set the appropriate directions for the modem control flags, - * and clear RTS and DTR - */ - ciab.ddra |= (SER_DTR | SER_RTS); /* outputs */ - ciab.ddra &= ~(SER_DCD | SER_CTS | SER_DSR); /* inputs */ - -#ifdef CONFIG_KGDB - /* turn Rx interrupts on for GDB */ - amiga_custom.intena = IF_SETCLR | IF_RBF; - ser_RTSon(); -#endif - - return 0; -} - -void __debug_print_hex(unsigned long x) -{ - int i; - char hexchars[] = "0123456789ABCDEF"; - - for (i = 0; i < 8; i++) { - __debug_ser_out(hexchars[(x >> 28) & 15]); - x <<= 4; - } - __debug_ser_out('\n'); - __debug_ser_out('\r'); -} - -void __debug_print_string(char* s) -{ - unsigned char c; - while((c = *s++)) - __debug_ser_out(c); - __debug_ser_out('\n'); - __debug_ser_out('\r'); -} - -static void apus_progress(char *s, unsigned short value) -{ - __debug_print_string(s); -} - -/****************************************************** init */ - -/* The number of spurious interrupts */ -volatile unsigned int num_spurious; - -extern struct irqaction amiga_sys_irqaction[AUTO_IRQS]; - - -extern void amiga_enable_irq(unsigned int irq); -extern void amiga_disable_irq(unsigned int irq); - -struct hw_interrupt_type amiga_sys_irqctrl = { - .typename = "Amiga IPL", - .end = apus_end_irq, -}; - -struct hw_interrupt_type amiga_irqctrl = { - .typename = "Amiga ", - .enable = amiga_enable_irq, - .disable = amiga_disable_irq, -}; - -#define HARDWARE_MAPPED_SIZE (512*1024) -unsigned long __init apus_find_end_of_memory(void) -{ - int shadow = 0; - unsigned long total; - - /* The memory size reported by ADOS excludes the 512KB - reserved for PPC exception registers and possibly 512KB - containing a shadow of the ADOS ROM. */ - { - unsigned long size = memory[0].size; - - /* If 2MB aligned, size was probably user - specified. We can't tell anything about shadowing - in this case so skip shadow assignment. */ - if (0 != (size & 0x1fffff)){ - /* Align to 512KB to ensure correct handling - of both memfile and system specified - sizes. */ - size = ((size+0x0007ffff) & 0xfff80000); - /* If memory is 1MB aligned, assume - shadowing. */ - shadow = !(size & 0x80000); - } - - /* Add the chunk that ADOS does not see. by aligning - the size to the nearest 2MB limit upwards. */ - memory[0].size = ((size+0x001fffff) & 0xffe00000); - } - - ppc_memstart = memory[0].addr; - ppc_memoffset = PAGE_OFFSET - PPC_MEMSTART; - total = memory[0].size; - - /* Remove the memory chunks that are controlled by special - Phase5 hardware. */ - - /* Remove the upper 512KB if it contains a shadow of - the ADOS ROM. FIXME: It might be possible to - disable this shadow HW. Check the booter - (ppc_boot.c) */ - if (shadow) - total -= HARDWARE_MAPPED_SIZE; - - /* Remove the upper 512KB where the PPC exception - vectors are mapped. */ - total -= HARDWARE_MAPPED_SIZE; - - /* Linux/APUS only handles one block of memory -- the one on - the PowerUP board. Other system memory is horrible slow in - comparison. The user can use other memory for swapping - using the z2ram device. */ - return total; -} - -static void __init -apus_map_io(void) -{ - /* Map PPC exception vectors. */ - io_block_mapping(0xfff00000, 0xfff00000, 0x00020000, _PAGE_KERNEL); - /* Map chip and ZorroII memory */ - io_block_mapping(zTwoBase, 0x00000000, 0x01000000, _PAGE_IO); -} - -__init -void apus_init_IRQ(void) -{ - struct irqaction *action; - int i; - -#ifdef CONFIG_PCI - apus_setup_pci_ptrs(); -#endif - - for ( i = 0 ; i < AMI_IRQS; i++ ) { - irq_desc[i].status = IRQ_LEVEL; - if (i < IRQ_AMIGA_AUTO) { - irq_desc[i].chip = &amiga_irqctrl; - } else { - irq_desc[i].chip = &amiga_sys_irqctrl; - action = &amiga_sys_irqaction[i-IRQ_AMIGA_AUTO]; - if (action->name) - setup_irq(i, action); - } - } - - amiga_init_IRQ(); - -} - -__init -void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - extern int parse_bootinfo(const struct bi_record *); - extern char _end[]; - - /* Parse bootinfo. The bootinfo is located right after - the kernel bss */ - parse_bootinfo((const struct bi_record *)&_end); -#ifdef CONFIG_BLK_DEV_INITRD - /* Take care of initrd if we have one. Use data from - bootinfo to avoid the need to initialize PPC - registers when kernel is booted via a PPC reset. */ - if ( ramdisk.addr ) { - initrd_start = (unsigned long) __va(ramdisk.addr); - initrd_end = (unsigned long) - __va(ramdisk.size + ramdisk.addr); - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - ISA_DMA_THRESHOLD = 0x00ffffff; - - ppc_md.setup_arch = apus_setup_arch; - ppc_md.show_cpuinfo = apus_show_cpuinfo; - ppc_md.init_IRQ = apus_init_IRQ; - ppc_md.get_irq = apus_get_irq; - -#ifdef CONFIG_HEARTBEAT - ppc_md.heartbeat = apus_heartbeat; - ppc_md.heartbeat_count = 1; -#endif -#ifdef APUS_DEBUG - __debug_serinit(); - ppc_md.progress = apus_progress; -#endif - ppc_md.init = NULL; - - ppc_md.restart = apus_restart; - ppc_md.power_off = apus_power_off; - ppc_md.halt = apus_halt; - - ppc_md.time_init = NULL; - ppc_md.set_rtc_time = apus_set_rtc_time; - ppc_md.get_rtc_time = apus_get_rtc_time; - ppc_md.calibrate_decr = apus_calibrate_decr; - - ppc_md.find_end_of_memory = apus_find_end_of_memory; - ppc_md.setup_io_mappings = apus_map_io; -} diff -puN drivers/char/hvc_beat.c~git-powerpc drivers/char/hvc_beat.c --- a/drivers/char/hvc_beat.c~git-powerpc +++ a/drivers/char/hvc_beat.c @@ -97,7 +97,7 @@ static int hvc_beat_config(char *p) return 0; } -static int hvc_beat_console_init(void) +static int __init hvc_beat_console_init(void) { if (hvc_beat_useit && machine_is_compatible("Beat")) { hvc_instantiate(0, 0, &hvc_beat_get_put_ops); @@ -106,7 +106,7 @@ static int hvc_beat_console_init(void) } /* temp */ -static int hvc_beat_init(void) +static int __init hvc_beat_init(void) { struct hvc_struct *hp; diff -puN drivers/char/ipmi/ipmi_si_intf.c~git-powerpc drivers/char/ipmi/ipmi_si_intf.c --- a/drivers/char/ipmi/ipmi_si_intf.c~git-powerpc +++ a/drivers/char/ipmi/ipmi_si_intf.c @@ -2252,19 +2252,19 @@ static int __devinit ipmi_of_probe(struc return ret; } - regsize = get_property(np, "reg-size", &proplen); + regsize = of_get_property(np, "reg-size", &proplen); if (regsize && proplen != 4) { dev_warn(&dev->dev, PFX "invalid regsize from OF\n"); return -EINVAL; } - regspacing = get_property(np, "reg-spacing", &proplen); + regspacing = of_get_property(np, "reg-spacing", &proplen); if (regspacing && proplen != 4) { dev_warn(&dev->dev, PFX "invalid regspacing from OF\n"); return -EINVAL; } - regshift = get_property(np, "reg-shift", &proplen); + regshift = of_get_property(np, "reg-shift", &proplen); if (regshift && proplen != 4) { dev_warn(&dev->dev, PFX "invalid regshift from OF\n"); return -EINVAL; diff -puN drivers/macintosh/adb-iop.c~git-powerpc drivers/macintosh/adb-iop.c --- a/drivers/macintosh/adb-iop.c~git-powerpc +++ a/drivers/macintosh/adb-iop.c @@ -19,7 +19,6 @@ #include #include -#include #include #include #include diff -puN drivers/macintosh/ans-lcd.c~git-powerpc drivers/macintosh/ans-lcd.c --- a/drivers/macintosh/ans-lcd.c~git-powerpc +++ a/drivers/macintosh/ans-lcd.c @@ -14,9 +14,10 @@ #include #include #include -#include #include +#include "ans-lcd.h" + #define ANSLCD_ADDR 0xf301c000 #define ANSLCD_CTRL_IX 0x00 #define ANSLCD_DATA_IX 0x10 diff -puN /dev/null drivers/macintosh/ans-lcd.h --- /dev/null +++ a/drivers/macintosh/ans-lcd.h @@ -0,0 +1,11 @@ +#ifndef _PPC_ANS_LCD_H +#define _PPC_ANS_LCD_H + +#define ANSLCD_MINOR 156 + +#define ANSLCD_CLEAR 0x01 +#define ANSLCD_SENDCTRL 0x02 +#define ANSLCD_SETSHORTDELAY 0x03 +#define ANSLCD_SETLONGDELAY 0x04 + +#endif diff -puN drivers/macintosh/therm_adt746x.c~git-powerpc drivers/macintosh/therm_adt746x.c --- a/drivers/macintosh/therm_adt746x.c~git-powerpc +++ a/drivers/macintosh/therm_adt746x.c @@ -379,13 +379,10 @@ static int attach_one_thermostat(struct if (thermostat) return 0; - th = (struct thermostat *) - kmalloc(sizeof(struct thermostat), GFP_KERNEL); - + th = kzalloc(sizeof(struct thermostat), GFP_KERNEL); if (!th) return -ENOMEM; - memset(th, 0, sizeof(*th)); th->clt.addr = addr; th->clt.adapter = adapter; th->clt.driver = &thermostat_driver; diff -puN drivers/macintosh/via-pmu.c~git-powerpc drivers/macintosh/via-pmu.c --- a/drivers/macintosh/via-pmu.c~git-powerpc +++ a/drivers/macintosh/via-pmu.c @@ -410,7 +410,7 @@ static int __init via_pmu_start(void) irq = irq_of_parse_and_map(vias, 0); if (irq == NO_IRQ) { - printk(KERN_ERR "via-pmu: can't map interruptn"); + printk(KERN_ERR "via-pmu: can't map interrupt\n"); return -ENODEV; } if (request_irq(irq, via_pmu_interrupt, 0, "VIA-PMU", (void *)0)) { diff -puN drivers/macintosh/windfarm_smu_sat.c~git-powerpc drivers/macintosh/windfarm_smu_sat.c --- a/drivers/macintosh/windfarm_smu_sat.c~git-powerpc +++ a/drivers/macintosh/windfarm_smu_sat.c @@ -380,10 +380,12 @@ static int __init sat_sensors_init(void) return i2c_add_driver(&wf_sat_driver); } +#if 0 /* uncomment when module_exit() below is uncommented */ static void __exit sat_sensors_exit(void) { i2c_del_driver(&wf_sat_driver); } +#endif module_init(sat_sensors_init); /*module_exit(sat_sensors_exit); Uncomment when cleanup is implemented */ diff -puN drivers/mtd/maps/Kconfig~git-powerpc drivers/mtd/maps/Kconfig --- a/drivers/mtd/maps/Kconfig~git-powerpc +++ a/drivers/mtd/maps/Kconfig @@ -362,7 +362,7 @@ config MTD_WALNUT config MTD_EBONY tristate "Flash devices mapped on IBM 440GP Ebony" - depends on MTD_JEDECPROBE && EBONY + depends on MTD_JEDECPROBE && EBONY && !PPC_MERGE help This enables access routines for the flash chips on the IBM 440GP Ebony board. If you have one of these boards and would like to diff -puN drivers/mtd/maps/physmap_of.c~git-powerpc drivers/mtd/maps/physmap_of.c --- a/drivers/mtd/maps/physmap_of.c~git-powerpc +++ a/drivers/mtd/maps/physmap_of.c @@ -1,9 +1,12 @@ /* - * Normal mappings of chips in physical memory for OF devices + * Flash mappings described by the OF (or flattened) device tree * * Copyright (C) 2006 MontaVista Software Inc. * Author: Vitaly Wool * + * Revised to handle newer style flash binding by: + * Copyright (C) 2007 David Gibson, IBM Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -12,102 +15,157 @@ #include #include -#include #include -#include #include #include #include #include -#include -#include -#include -#include -#include +#include +#include -struct physmap_flash_info { +struct of_flash { struct mtd_info *mtd; struct map_info map; struct resource *res; #ifdef CONFIG_MTD_PARTITIONS - int nr_parts; struct mtd_partition *parts; #endif }; -static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", "map_rom", NULL }; #ifdef CONFIG_MTD_PARTITIONS -static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; -#endif +#define OF_FLASH_PARTS(info) ((info)->parts) -#ifdef CONFIG_MTD_PARTITIONS -static int parse_flash_partitions(struct device_node *node, - struct mtd_partition **parts) +static int parse_obsolete_partitions(struct of_device *dev, + struct of_flash *info, + struct device_node *dp) { - int i, plen, retval = -ENOMEM; - const u32 *part; - const char *name; + int i, plen, nr_parts; + const struct { + u32 offset, len; + } *part; + const char *names; - part = of_get_property(node, "partitions", &plen); - if (part == NULL) - goto err; + part = of_get_property(dp, "partitions", &plen); + if (!part) + return 0; /* No partitions found */ - retval = plen / (2 * sizeof(u32)); - *parts = kzalloc(retval * sizeof(struct mtd_partition), GFP_KERNEL); - if (*parts == NULL) { - printk(KERN_ERR "Can't allocate the flash partition data!\n"); - goto err; - } + dev_warn(&dev->dev, "Device tree uses obsolete partition map binding\n"); - name = of_get_property(node, "partition-names", &plen); + nr_parts = plen / sizeof(part[0]); - for (i = 0; i < retval; i++) { - (*parts)[i].offset = *part++; - (*parts)[i].size = *part & ~1; - if (*part++ & 1) /* bit 0 set signifies read only partition */ - (*parts)[i].mask_flags = MTD_WRITEABLE; + info->parts = kzalloc(nr_parts * sizeof(*info->parts), GFP_KERNEL); + if (!info->parts) + return -ENOMEM; - if (name != NULL && plen > 0) { - int len = strlen(name) + 1; + names = of_get_property(dp, "partition-names", &plen); - (*parts)[i].name = (char *)name; + for (i = 0; i < nr_parts; i++) { + info->parts[i].offset = part->offset; + info->parts[i].size = part->len & ~1; + if (part->len & 1) /* bit 0 set signifies read only partition */ + info->parts[i].mask_flags = MTD_WRITEABLE; + + if (names && (plen > 0)) { + int len = strlen(names) + 1; + + info->parts[i].name = (char *)names; plen -= len; - name += len; - } else - (*parts)[i].name = "unnamed"; + names += len; + } else { + info->parts[i].name = "unnamed"; + } + + part++; } -err: - return retval; + + return nr_parts; } -#endif -static int of_physmap_remove(struct of_device *dev) +static int __devinit parse_partitions(struct of_flash *info, + struct of_device *dev) +{ + const char *partname; + static const char *part_probe_types[] + = { "cmdlinepart", "RedBoot", NULL }; + struct device_node *dp = dev->node, *pp; + int nr_parts, i; + + /* First look for RedBoot table or partitions on the command + * line, these take precedence over device tree information */ + nr_parts = parse_mtd_partitions(info->mtd, part_probe_types, + &info->parts, 0); + if (nr_parts > 0) { + add_mtd_partitions(info->mtd, info->parts, nr_parts); + return 0; + } + + /* First count the subnodes */ + nr_parts = 0; + for (pp = dp->child; pp; pp = pp->sibling) + nr_parts++; + + if (nr_parts == 0) + return parse_obsolete_partitions(dev, info, dp); + + info->parts = kzalloc(nr_parts * sizeof(*info->parts), + GFP_KERNEL); + if (!info->parts) + return -ENOMEM; + + for (pp = dp->child, i = 0; pp; pp = pp->sibling, i++) { + const u32 *reg; + int len; + + reg = of_get_property(pp, "reg", &len); + if (!reg || (len != 2*sizeof(u32))) { + dev_err(&dev->dev, "Invalid 'reg' on %s\n", + dp->full_name); + kfree(info->parts); + info->parts = NULL; + return -EINVAL; + } + info->parts[i].offset = reg[0]; + info->parts[i].size = reg[1]; + + partname = of_get_property(pp, "label", &len); + if (!partname) + partname = of_get_property(pp, "name", &len); + info->parts[i].name = (char *)partname; + + if (of_get_property(pp, "read-only", &len)) + info->parts[i].mask_flags = MTD_WRITEABLE; + } + + return nr_parts; +} +#else /* MTD_PARTITIONS */ +#define OF_FLASH_PARTS(info) (0) +#define parse_partitions(info, dev) (0) +#endif /* MTD_PARTITIONS */ + +static int of_flash_remove(struct of_device *dev) { - struct physmap_flash_info *info; + struct of_flash *info; info = dev_get_drvdata(&dev->dev); - if (info == NULL) + if (!info) return 0; dev_set_drvdata(&dev->dev, NULL); - if (info->mtd != NULL) { -#ifdef CONFIG_MTD_PARTITIONS - if (info->nr_parts) { + if (info->mtd) { + if (OF_FLASH_PARTS(info)) { del_mtd_partitions(info->mtd); - kfree(info->parts); + kfree(OF_FLASH_PARTS(info)); } else { del_mtd_device(info->mtd); } -#else - del_mtd_device(info->mtd); -#endif map_destroy(info->mtd); } - if (info->map.virt != NULL) + if (info->map.virt) iounmap(info->map.virt); - if (info->res != NULL) { + if (info->res) { release_resource(info->res); kfree(info->res); } @@ -115,48 +173,79 @@ static int of_physmap_remove(struct of_d return 0; } -static int __devinit of_physmap_probe(struct of_device *dev, const struct of_device_id *match) +/* Helper function to handle probing of the obsolete "direct-mapped" + * compatible binding, which has an extra "probe-type" property + * describing the type of flash probe necessary. */ +static struct mtd_info * __devinit obsolete_probe(struct of_device *dev, + struct map_info *map) { struct device_node *dp = dev->node; - struct resource res; - struct physmap_flash_info *info; - const char **probe_type; const char *of_probe; + struct mtd_info *mtd; + static const char *rom_probe_types[] + = { "cfi_probe", "jedec_probe", "map_rom"}; + int i; + + dev_warn(&dev->dev, "Device tree uses obsolete \"direct-mapped\" " + "flash binding\n"); + + of_probe = of_get_property(dp, "probe-type", NULL); + if (!of_probe) { + for (i = 0; i < ARRAY_SIZE(rom_probe_types); i++) { + mtd = do_map_probe(rom_probe_types[i], map); + if (mtd) + return mtd; + } + return NULL; + } else if (strcmp(of_probe, "CFI") == 0) { + return do_map_probe("cfi_probe", map); + } else if (strcmp(of_probe, "JEDEC") == 0) { + return do_map_probe("jedec_probe", map); + } else { + if (strcmp(of_probe, "ROM") != 0) + dev_warn(&dev->dev, "obsolete_probe: don't know probe " + "type '%s', mapping as rom\n", of_probe); + return do_map_probe("mtd_rom", map); + } +} + +static int __devinit of_flash_probe(struct of_device *dev, + const struct of_device_id *match) +{ + struct device_node *dp = dev->node; + struct resource res; + struct of_flash *info; + const char *probe_type = match->data; const u32 *width; int err; - + err = -ENXIO; if (of_address_to_resource(dp, 0, &res)) { - dev_err(&dev->dev, "Can't get the flash mapping!\n"); - err = -EINVAL; + dev_err(&dev->dev, "Can't get IO address from device tree\n"); goto err_out; } - dev_dbg(&dev->dev, "physmap flash device: %.8llx at %.8llx\n", - (unsigned long long)res.end - res.start + 1, - (unsigned long long)res.start); + dev_dbg(&dev->dev, "of_flash device: %.8llx-%.8llx\n", + (unsigned long long)res.start, (unsigned long long)res.end); - info = kzalloc(sizeof(struct physmap_flash_info), GFP_KERNEL); - if (info == NULL) { - err = -ENOMEM; + err = -ENOMEM; + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) goto err_out; - } memset(info, 0, sizeof(*info)); dev_set_drvdata(&dev->dev, info); + err = -EBUSY; info->res = request_mem_region(res.start, res.end - res.start + 1, - dev->dev.bus_id); - if (info->res == NULL) { - dev_err(&dev->dev, "Could not reserve memory region\n"); - err = -ENOMEM; + dev->dev.bus_id); + if (!info->res) goto err_out; - } + err = -ENXIO; width = of_get_property(dp, "bank-width", NULL); - if (width == NULL) { - dev_err(&dev->dev, "Can't get the flash bank width!\n"); - err = -EINVAL; + if (!width) { + dev_err(&dev->dev, "Can't get bank width from device tree\n"); goto err_out; } @@ -165,91 +254,87 @@ static int __devinit of_physmap_probe(st info->map.size = res.end - res.start + 1; info->map.bankwidth = *width; + err = -ENOMEM; info->map.virt = ioremap(info->map.phys, info->map.size); - if (info->map.virt == NULL) { - dev_err(&dev->dev, "Failed to ioremap flash region\n"); - err = EIO; + if (!info->map.virt) { + dev_err(&dev->dev, "Failed to ioremap() flash region\n"); goto err_out; } simple_map_init(&info->map); - of_probe = of_get_property(dp, "probe-type", NULL); - if (of_probe == NULL) { - probe_type = rom_probe_types; - for (; info->mtd == NULL && *probe_type != NULL; probe_type++) - info->mtd = do_map_probe(*probe_type, &info->map); - } else if (!strcmp(of_probe, "CFI")) - info->mtd = do_map_probe("cfi_probe", &info->map); - else if (!strcmp(of_probe, "JEDEC")) - info->mtd = do_map_probe("jedec_probe", &info->map); - else { - if (strcmp(of_probe, "ROM")) - dev_dbg(&dev->dev, "map_probe: don't know probe type " - "'%s', mapping as rom\n", of_probe); - info->mtd = do_map_probe("mtd_rom", &info->map); - } - if (info->mtd == NULL) { - dev_err(&dev->dev, "map_probe failed\n"); - err = -ENXIO; + if (probe_type) + info->mtd = do_map_probe(probe_type, &info->map); + else + info->mtd = obsolete_probe(dev, &info->map); + + err = -ENXIO; + if (!info->mtd) { + dev_err(&dev->dev, "do_map_probe() failed\n"); goto err_out; } info->mtd->owner = THIS_MODULE; -#ifdef CONFIG_MTD_PARTITIONS - err = parse_mtd_partitions(info->mtd, part_probe_types, &info->parts, 0); - if (err > 0) { - add_mtd_partitions(info->mtd, info->parts, err); - } else if ((err = parse_flash_partitions(dp, &info->parts)) > 0) { - dev_info(&dev->dev, "Using OF partition information\n"); - add_mtd_partitions(info->mtd, info->parts, err); - info->nr_parts = err; - } else -#endif + err = parse_partitions(info, dev); + if (err < 0) + goto err_out; + + if (err > 0) + add_mtd_partitions(info->mtd, OF_FLASH_PARTS(info), err); + else + add_mtd_device(info->mtd); - add_mtd_device(info->mtd); return 0; err_out: - of_physmap_remove(dev); + of_flash_remove(dev); return err; - - return 0; - - } -static struct of_device_id of_physmap_match[] = { +static struct of_device_id of_flash_match[] = { + { + .compatible = "cfi-flash", + .data = (void *)"cfi_probe", + }, + { + /* FIXME: JEDEC chips can't be safely and reliably + * probed, although the mtd code gets it right in + * practice most of the time. We should use the + * vendor and device ids specified by the binding to + * bypass the heuristic probe code, but the mtd layer + * provides, at present, no interface for doing so + * :(. */ + .compatible = "jedec-flash", + .data = (void *)"jedec_probe", + }, { .type = "rom", .compatible = "direct-mapped" }, { }, }; +MODULE_DEVICE_TABLE(of, of_flash_match); -MODULE_DEVICE_TABLE(of, of_physmap_match); - - -static struct of_platform_driver of_physmap_flash_driver = { - .name = "physmap-flash", - .match_table = of_physmap_match, - .probe = of_physmap_probe, - .remove = of_physmap_remove, +static struct of_platform_driver of_flash_driver = { + .name = "of-flash", + .match_table = of_flash_match, + .probe = of_flash_probe, + .remove = of_flash_remove, }; -static int __init of_physmap_init(void) +static int __init of_flash_init(void) { - return of_register_platform_driver(&of_physmap_flash_driver); + return of_register_platform_driver(&of_flash_driver); } -static void __exit of_physmap_exit(void) +static void __exit of_flash_exit(void) { - of_unregister_platform_driver(&of_physmap_flash_driver); + of_unregister_platform_driver(&of_flash_driver); } -module_init(of_physmap_init); -module_exit(of_physmap_exit); +module_init(of_flash_init); +module_exit(of_flash_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Vitaly Wool "); -MODULE_DESCRIPTION("Configurable MTD map driver for OF"); +MODULE_DESCRIPTION("Device tree based MTD map driver"); diff -puN drivers/net/ucc_geth_mii.c~git-powerpc drivers/net/ucc_geth_mii.c --- a/drivers/net/ucc_geth_mii.c~git-powerpc +++ a/drivers/net/ucc_geth_mii.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff -puN drivers/serial/mpc52xx_uart.c~git-powerpc drivers/serial/mpc52xx_uart.c --- a/drivers/serial/mpc52xx_uart.c~git-powerpc +++ a/drivers/serial/mpc52xx_uart.c @@ -1051,7 +1051,7 @@ mpc52xx_uart_of_assign(struct device_nod /* If the slot is already occupied, then swap slots */ if (mpc52xx_uart_nodes[idx] && (free_idx != -1)) mpc52xx_uart_nodes[free_idx] = mpc52xx_uart_nodes[idx]; - mpc52xx_uart_nodes[i] = np; + mpc52xx_uart_nodes[idx] = np; } static void diff -puN drivers/serial/pmac_zilog.c~git-powerpc drivers/serial/pmac_zilog.c --- a/drivers/serial/pmac_zilog.c~git-powerpc +++ a/drivers/serial/pmac_zilog.c @@ -1587,7 +1587,7 @@ static int pmz_suspend(struct macio_dev if (pm_state.event == mdev->ofdev.dev.power.power_state.event) return 0; - pmz_debug("suspend, switching to state %d\n", pm_state); + pmz_debug("suspend, switching to state %d\n", pm_state.event); state = pmz_uart_reg.state + uap->port.line; diff -puN fs/binfmt_elf.c~git-powerpc fs/binfmt_elf.c --- a/fs/binfmt_elf.c~git-powerpc +++ a/fs/binfmt_elf.c @@ -1514,9 +1514,6 @@ static int elf_core_dump(long signr, str int thread_status_size = 0; elf_addr_t *auxv; unsigned long mm_flags; -#ifdef ELF_CORE_WRITE_EXTRA_NOTES - int extra_notes_size; -#endif /* * We no longer stop all VM operations. @@ -1645,10 +1642,7 @@ static int elf_core_dump(long signr, str sz += thread_status_size; -#ifdef ELF_CORE_WRITE_EXTRA_NOTES - extra_notes_size = ELF_CORE_EXTRA_NOTES_SIZE; - sz += extra_notes_size; -#endif + sz += elf_coredump_extra_notes_size(); fill_elf_note_phdr(&phdr, sz, offset); offset += sz; @@ -1698,10 +1692,8 @@ static int elf_core_dump(long signr, str if (!writenote(notes + i, file, &foffset)) goto end_coredump; -#ifdef ELF_CORE_WRITE_EXTRA_NOTES - ELF_CORE_WRITE_EXTRA_NOTES; - foffset += extra_notes_size; -#endif + if (elf_coredump_extra_notes_write(file, &foffset)) + goto end_coredump; /* write out the thread status notes section */ list_for_each(t, &thread_list) { diff -puN /dev/null include/asm-powerpc/8xx_immap.h --- /dev/null +++ a/include/asm-powerpc/8xx_immap.h @@ -0,0 +1,564 @@ +/* + * MPC8xx Internal Memory Map + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * The I/O on the MPC860 is comprised of blocks of special registers + * and the dual port ram for the Communication Processor Module. + * Within this space are functional units such as the SIU, memory + * controller, system timers, and other control functions. It is + * a combination that I found difficult to separate into logical + * functional files.....but anyone else is welcome to try. -- Dan + */ +#ifdef __KERNEL__ +#ifndef __IMMAP_8XX__ +#define __IMMAP_8XX__ + +/* System configuration registers. +*/ +typedef struct sys_conf { + uint sc_siumcr; + uint sc_sypcr; + uint sc_swt; + char res1[2]; + ushort sc_swsr; + uint sc_sipend; + uint sc_simask; + uint sc_siel; + uint sc_sivec; + uint sc_tesr; + char res2[0xc]; + uint sc_sdcr; + char res3[0x4c]; +} sysconf8xx_t; + +/* PCMCIA configuration registers. +*/ +typedef struct pcmcia_conf { + uint pcmc_pbr0; + uint pcmc_por0; + uint pcmc_pbr1; + uint pcmc_por1; + uint pcmc_pbr2; + uint pcmc_por2; + uint pcmc_pbr3; + uint pcmc_por3; + uint pcmc_pbr4; + uint pcmc_por4; + uint pcmc_pbr5; + uint pcmc_por5; + uint pcmc_pbr6; + uint pcmc_por6; + uint pcmc_pbr7; + uint pcmc_por7; + char res1[0x20]; + uint pcmc_pgcra; + uint pcmc_pgcrb; + uint pcmc_pscr; + char res2[4]; + uint pcmc_pipr; + char res3[4]; + uint pcmc_per; + char res4[4]; +} pcmconf8xx_t; + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + uint memc_br0; + uint memc_or0; + uint memc_br1; + uint memc_or1; + uint memc_br2; + uint memc_or2; + uint memc_br3; + uint memc_or3; + uint memc_br4; + uint memc_or4; + uint memc_br5; + uint memc_or5; + uint memc_br6; + uint memc_or6; + uint memc_br7; + uint memc_or7; + char res1[0x24]; + uint memc_mar; + uint memc_mcr; + char res2[4]; + uint memc_mamr; + uint memc_mbmr; + ushort memc_mstat; + ushort memc_mptpr; + uint memc_mdr; + char res3[0x80]; +} memctl8xx_t; + +/*----------------------------------------------------------------------- + * BR - Memory Controler: Base Register 16-9 + */ +#define BR_BA_MSK 0xffff8000 /* Base Address Mask */ +#define BR_AT_MSK 0x00007000 /* Address Type Mask */ +#define BR_PS_MSK 0x00000c00 /* Port Size Mask */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PARE 0x00000200 /* Parity Enable */ +#define BR_WP 0x00000100 /* Write Protect */ +#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */ +#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ +#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ +#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */ +#define BR_V 0x00000001 /* Bank Valid */ + +/*----------------------------------------------------------------------- + * OR - Memory Controler: Option Register 16-11 + */ +#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */ +#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ +#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ + /* Address Multiplex */ +#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ +#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ +#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ +#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ +#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ +#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ +#define OR_BI 0x00000100 /* Burst inhibit */ +#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ +#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ +#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ +#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ +#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ +#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ +#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ +#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ +#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ +#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ +#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ +#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ +#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ +#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ +#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ +#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ +#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ +#define OR_SETA 0x00000008 /* External Transfer Acknowledge */ +#define OR_TRLX 0x00000004 /* Timing Relaxed */ +#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + ushort sit_tbscr; + char res0[0x02]; + uint sit_tbreff0; + uint sit_tbreff1; + char res1[0x14]; + ushort sit_rtcsc; + char res2[0x02]; + uint sit_rtc; + uint sit_rtsec; + uint sit_rtcal; + char res3[0x10]; + ushort sit_piscr; + char res4[2]; + uint sit_pitc; + uint sit_pitr; + char res5[0x34]; +} sit8xx_t; + +#define TBSCR_TBIRQ_MASK ((ushort)0xff00) +#define TBSCR_REFA ((ushort)0x0080) +#define TBSCR_REFB ((ushort)0x0040) +#define TBSCR_REFAE ((ushort)0x0008) +#define TBSCR_REFBE ((ushort)0x0004) +#define TBSCR_TBF ((ushort)0x0002) +#define TBSCR_TBE ((ushort)0x0001) + +#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) +#define RTCSC_SEC ((ushort)0x0080) +#define RTCSC_ALR ((ushort)0x0040) +#define RTCSC_38K ((ushort)0x0010) +#define RTCSC_SIE ((ushort)0x0008) +#define RTCSC_ALE ((ushort)0x0004) +#define RTCSC_RTF ((ushort)0x0002) +#define RTCSC_RTE ((ushort)0x0001) + +#define PISCR_PIRQ_MASK ((ushort)0xff00) +#define PISCR_PS ((ushort)0x0080) +#define PISCR_PIE ((ushort)0x0004) +#define PISCR_PTF ((ushort)0x0002) +#define PISCR_PTE ((ushort)0x0001) + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + uint car_sccr; + uint car_plprcr; + uint car_rsr; + char res[0x74]; /* Reserved area */ +} car8xx_t; + +/* System Integration Timers keys. +*/ +typedef struct sitk { + uint sitk_tbscrk; + uint sitk_tbreff0k; + uint sitk_tbreff1k; + uint sitk_tbk; + char res1[0x10]; + uint sitk_rtcsck; + uint sitk_rtck; + uint sitk_rtseck; + uint sitk_rtcalk; + char res2[0x10]; + uint sitk_piscrk; + uint sitk_pitck; + char res3[0x38]; +} sitk8xx_t; + +/* Clocks and reset keys. +*/ +typedef struct cark { + uint cark_sccrk; + uint cark_plprcrk; + uint cark_rsrk; + char res[0x474]; +} cark8xx_t; + +/* The key to unlock registers maintained by keep-alive power. +*/ +#define KAPWR_KEY ((unsigned int)0x55ccaa33) + +/* Video interface. MPC823 Only. +*/ +typedef struct vid823 { + ushort vid_vccr; + ushort res1; + u_char vid_vsr; + u_char res2; + u_char vid_vcmr; + u_char res3; + uint vid_vbcb; + uint res4; + uint vid_vfcr0; + uint vid_vfaa0; + uint vid_vfba0; + uint vid_vfcr1; + uint vid_vfaa1; + uint vid_vfba1; + u_char res5[0x18]; +} vid823_t; + +/* LCD interface. 823 Only. +*/ +typedef struct lcd { + uint lcd_lccr; + uint lcd_lchcr; + uint lcd_lcvcr; + char res1[4]; + uint lcd_lcfaa; + uint lcd_lcfba; + char lcd_lcsr; + char res2[0x7]; +} lcd823_t; + +/* I2C +*/ +typedef struct i2c { + u_char i2c_i2mod; + char res1[3]; + u_char i2c_i2add; + char res2[3]; + u_char i2c_i2brg; + char res3[3]; + u_char i2c_i2com; + char res4[3]; + u_char i2c_i2cer; + char res5[3]; + u_char i2c_i2cmr; + char res6[0x8b]; +} i2c8xx_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + char res1[4]; + uint sdma_sdar; + u_char sdma_sdsr; + char res3[3]; + u_char sdma_sdmr; + char res4[3]; + u_char sdma_idsr1; + char res5[3]; + u_char sdma_idmr1; + char res6[3]; + u_char sdma_idsr2; + char res7[3]; + u_char sdma_idmr2; + char res8[0x13]; +} sdma8xx_t; + +/* Communication Processor Module Interrupt Controller. +*/ +typedef struct cpm_ic { + ushort cpic_civr; + char res[0xe]; + uint cpic_cicr; + uint cpic_cipr; + uint cpic_cimr; + uint cpic_cisr; +} cpic8xx_t; + +/* Input/Output Port control/status registers. +*/ +typedef struct io_port { + ushort iop_padir; + ushort iop_papar; + ushort iop_paodr; + ushort iop_padat; + char res1[8]; + ushort iop_pcdir; + ushort iop_pcpar; + ushort iop_pcso; + ushort iop_pcdat; + ushort iop_pcint; + char res2[6]; + ushort iop_pddir; + ushort iop_pdpar; + char res3[2]; + ushort iop_pddat; + uint utmode; + char res4[4]; +} iop8xx_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + ushort cpmt_tgcr; + char res1[0xe]; + ushort cpmt_tmr1; + ushort cpmt_tmr2; + ushort cpmt_trr1; + ushort cpmt_trr2; + ushort cpmt_tcr1; + ushort cpmt_tcr2; + ushort cpmt_tcn1; + ushort cpmt_tcn2; + ushort cpmt_tmr3; + ushort cpmt_tmr4; + ushort cpmt_trr3; + ushort cpmt_trr4; + ushort cpmt_tcr3; + ushort cpmt_tcr4; + ushort cpmt_tcn3; + ushort cpmt_tcn4; + ushort cpmt_ter1; + ushort cpmt_ter2; + ushort cpmt_ter3; + ushort cpmt_ter4; + char res2[8]; +} cpmtimer8xx_t; + +/* Finally, the Communication Processor stuff..... +*/ +typedef struct scc { /* Serial communication channels */ + uint scc_gsmrl; + uint scc_gsmrh; + ushort scc_psmr; + char res1[2]; + ushort scc_todr; + ushort scc_dsr; + ushort scc_scce; + char res2[2]; + ushort scc_sccm; + char res3; + u_char scc_sccs; + char res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + char res1[2]; + ushort smc_smcmr; + char res2[2]; + u_char smc_smce; + char res3[3]; + u_char smc_smcm; + char res4[5]; +} smc_t; + +/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but + * it fits within the address space. + */ + +typedef struct fec { + uint fec_addr_low; /* lower 32 bits of station address */ + ushort fec_addr_high; /* upper 16 bits of station address */ + ushort res1; /* reserved */ + uint fec_hash_table_high; /* upper 32-bits of hash table */ + uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_r_des_start; /* beginning of Rx descriptor ring */ + uint fec_x_des_start; /* beginning of Tx descriptor ring */ + uint fec_r_buff_size; /* Rx buffer size */ + uint res2[9]; /* reserved */ + uint fec_ecntrl; /* ethernet control register */ + uint fec_ievent; /* interrupt event register */ + uint fec_imask; /* interrupt mask register */ + uint fec_ivec; /* interrupt level and vector status */ + uint fec_r_des_active; /* Rx ring updated flag */ + uint fec_x_des_active; /* Tx ring updated flag */ + uint res3[10]; /* reserved */ + uint fec_mii_data; /* MII data register */ + uint fec_mii_speed; /* MII speed control register */ + uint res4[17]; /* reserved */ + uint fec_r_bound; /* end of RAM (read-only) */ + uint fec_r_fstart; /* Rx FIFO start address */ + uint res5[6]; /* reserved */ + uint fec_x_fstart; /* Tx FIFO start address */ + uint res6[17]; /* reserved */ + uint fec_fun_code; /* fec SDMA function code */ + uint res7[3]; /* reserved */ + uint fec_r_cntrl; /* Rx control register */ + uint fec_r_hash; /* Rx hash register */ + uint res8[14]; /* reserved */ + uint fec_x_cntrl; /* Tx control register */ + uint res9[0x1e]; /* reserved */ +} fec_t; + +/* The FEC and LCD color map share the same address space.... + * I guess we will never see an 823T :-). + */ +union fec_lcd { + fec_t fl_un_fec; + u_char fl_un_cmap[0x200]; +}; + +typedef struct comm_proc { + /* General control and status registers. + */ + ushort cp_cpcr; + u_char res1[2]; + ushort cp_rccr; + u_char res2; + u_char cp_rmds; + u_char res3[4]; + ushort cp_cpmcr1; + ushort cp_cpmcr2; + ushort cp_cpmcr3; + ushort cp_cpmcr4; + u_char res4[2]; + ushort cp_rter; + u_char res5[2]; + ushort cp_rtmr; + u_char res6[0x14]; + + /* Baud rate generators. + */ + uint cp_brgc1; + uint cp_brgc2; + uint cp_brgc3; + uint cp_brgc4; + + /* Serial Communication Channels. + */ + scc_t cp_scc[4]; + + /* Serial Management Channels. + */ + smc_t cp_smc[2]; + + /* Serial Peripheral Interface. + */ + ushort cp_spmode; + u_char res7[4]; + u_char cp_spie; + u_char res8[3]; + u_char cp_spim; + u_char res9[2]; + u_char cp_spcom; + u_char res10[2]; + + /* Parallel Interface Port. + */ + u_char res11[2]; + ushort cp_pipc; + u_char res12[2]; + ushort cp_ptpr; + uint cp_pbdir; + uint cp_pbpar; + u_char res13[2]; + ushort cp_pbodr; + uint cp_pbdat; + + /* Port E - MPC87x/88x only. + */ + uint cp_pedir; + uint cp_pepar; + uint cp_peso; + uint cp_peodr; + uint cp_pedat; + + /* Communications Processor Timing Register - + Contains RMII Timing for the FECs on MPC87x/88x only. + */ + uint cp_cptr; + + /* Serial Interface and Time Slot Assignment. + */ + uint cp_simode; + u_char cp_sigmr; + u_char res15; + u_char cp_sistr; + u_char cp_sicmr; + u_char res16[4]; + uint cp_sicr; + uint cp_sirp; + u_char res17[0xc]; + + /* 256 bytes of MPC823 video controller RAM array. + */ + u_char cp_vcram[0x100]; + u_char cp_siram[0x200]; + + /* The fast ethernet controller is not really part of the CPM, + * but it resides in the address space. + * The LCD color map is also here. + */ + union fec_lcd fl_un; +#define cp_fec fl_un.fl_un_fec +#define lcd_cmap fl_un.fl_un_cmap + char res18[0xE00]; + + /* The DUET family has a second FEC here */ + fec_t cp_fec2; +#define cp_fec1 cp_fec /* consistency macro */ + + /* Dual Ported RAM follows. + * There are many different formats for this memory area + * depending upon the devices used and options chosen. + * Some processors don't have all of it populated. + */ + u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ + u_char cp_dparam[0x400]; /* Parameter RAM */ +} cpm8xx_t; + +/* Internal memory map. +*/ +typedef struct immap { + sysconf8xx_t im_siu_conf; /* SIU Configuration */ + pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ + memctl8xx_t im_memctl; /* Memory Controller */ + sit8xx_t im_sit; /* System integration timers */ + car8xx_t im_clkrst; /* Clocks and reset */ + sitk8xx_t im_sitk; /* Sys int timer keys */ + cark8xx_t im_clkrstk; /* Clocks and reset keys */ + vid823_t im_vid; /* Video (823 only) */ + lcd823_t im_lcd; /* LCD (823 only) */ + i2c8xx_t im_i2c; /* I2C control/status */ + sdma8xx_t im_sdma; /* SDMA control/status */ + cpic8xx_t im_cpic; /* CPM Interrupt Controller */ + iop8xx_t im_ioport; /* IO Port control/status */ + cpmtimer8xx_t im_cpmtimer; /* CPM timers */ + cpm8xx_t im_cpm; /* Communication processor */ +} immap_t; + +#endif /* __IMMAP_8XX__ */ +#endif /* __KERNEL__ */ diff -puN include/asm-powerpc/atomic.h~git-powerpc include/asm-powerpc/atomic.h --- a/include/asm-powerpc/atomic.h~git-powerpc +++ a/include/asm-powerpc/atomic.h @@ -5,7 +5,7 @@ * PowerPC atomic operations */ -typedef struct { volatile int counter; } atomic_t; +typedef struct { int counter; } atomic_t; #ifdef __KERNEL__ #include @@ -15,8 +15,19 @@ typedef struct { volatile int counter; } #define ATOMIC_INIT(i) { (i) } -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) +static __inline__ int atomic_read(const atomic_t *v) +{ + int t; + + __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter)); + + return t; +} + +static __inline__ void atomic_set(atomic_t *v, int i) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i)); +} static __inline__ void atomic_add(int a, atomic_t *v) { @@ -240,12 +251,23 @@ static __inline__ int atomic_dec_if_posi #ifdef __powerpc64__ -typedef struct { volatile long counter; } atomic64_t; +typedef struct { long counter; } atomic64_t; #define ATOMIC64_INIT(i) { (i) } -#define atomic64_read(v) ((v)->counter) -#define atomic64_set(v,i) (((v)->counter) = (i)) +static __inline__ long atomic64_read(const atomic64_t *v) +{ + long t; + + __asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter)); + + return t; +} + +static __inline__ void atomic64_set(atomic64_t *v, long i) +{ + __asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i)); +} static __inline__ void atomic64_add(long a, atomic64_t *v) { diff -puN /dev/null include/asm-powerpc/commproc.h --- /dev/null +++ a/include/asm-powerpc/commproc.h @@ -0,0 +1,692 @@ +/* + * MPC8xx Communication Processor Module. + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * This file contains structures and information for the communication + * processor channels. Some CPM control and status is available + * throught the MPC8xx internal memory map. See immap.h for details. + * This file only contains what I need for the moment, not the total + * CPM capabilities. I (or someone else) will add definitions as they + * are needed. -- Dan + * + * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 + * bytes of the DP RAM and relocates the I2C parameter area to the + * IDMA1 space. The remaining DP RAM is available for buffer descriptors + * or other use. + */ +#ifndef __CPM_8XX__ +#define __CPM_8XX__ + +#include +#include + +/* CPM Command register. +*/ +#define CPM_CR_RST ((ushort)0x8000) +#define CPM_CR_OPCODE ((ushort)0x0f00) +#define CPM_CR_CHAN ((ushort)0x00f0) +#define CPM_CR_FLG ((ushort)0x0001) + +/* Some commands (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) +#define CPM_CR_SET_GADDR ((ushort)0x0008) +#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR + +/* Channel numbers. +*/ +#define CPM_CR_CH_SCC1 ((ushort)0x0000) +#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ +#define CPM_CR_CH_SCC2 ((ushort)0x0004) +#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ +#define CPM_CR_CH_TIMER CPM_CR_CH_SPI +#define CPM_CR_CH_SCC3 ((ushort)0x0008) +#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ +#define CPM_CR_CH_SCC4 ((ushort)0x000c) +#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ + +#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) + +/* The dual ported RAM is multi-functional. Some areas can be (and are + * being) used for microcode. There is an area that can only be used + * as data ram for buffer descriptors, which is all we use right now. + * Currently the first 512 and last 256 bytes are used for microcode. + */ +#define CPM_DATAONLY_BASE ((uint)0x0800) +#define CPM_DATAONLY_SIZE ((uint)0x0700) +#define CPM_DP_NOSPACE ((uint)0x7fffffff) + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +extern cpm8xx_t *cpmp; /* Pointer to comm processor */ +extern unsigned long cpm_dpalloc(uint size, uint align); +extern int cpm_dpfree(unsigned long offset); +extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); +extern void cpm_dpdump(void); +extern void *cpm_dpram_addr(unsigned long offset); +extern uint cpm_dpram_phys(u8* addr); +extern void cpm_setbrg(uint brg, uint rate); + +extern uint m8xx_cpm_hostalloc(uint size); +extern int m8xx_cpm_hostfree(uint start); +extern void m8xx_cpm_hostdump(void); + +extern void cpm_load_patch(volatile immap_t *immr); + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_UN ((ushort)0x0002) /* Underrun */ +#define BD_SC_CD ((ushort)0x0001) /* ?? */ +#define BD_SC_CL ((ushort)0x0001) /* Collision */ + +/* Parameter RAM offsets. +*/ +#define PROFF_SCC1 ((uint)0x0000) +#define PROFF_IIC ((uint)0x0080) +#define PROFF_SCC2 ((uint)0x0100) +#define PROFF_SPI ((uint)0x0180) +#define PROFF_SCC3 ((uint)0x0200) +#define PROFF_SMC1 ((uint)0x0280) +#define PROFF_SCC4 ((uint)0x0300) +#define PROFF_SMC2 ((uint)0x0380) + +/* Define enough so I can at least use the serial port as a UART. + * The MBX uses SMC1 as the host serial port. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ + char res1[8]; /* Reserved */ + ushort smc_rpbase; /* Relocation pointer */ +} smc_uart_t; + +/* Function code bits. +*/ +#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* SMC uart mode register. +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC2 as Centronics parallel printer. It is half duplex, in that + * it can only receive or transmit. The parameter ram values for + * each direction are either unique or properly overlap, so we can + * include them in one structure. + */ +typedef struct smc_centronics { + ushort scent_rbase; + ushort scent_tbase; + u_char scent_cfcr; + u_char scent_smask; + ushort scent_mrblr; + uint scent_rstate; + uint scent_r_ptr; + ushort scent_rbptr; + ushort scent_r_cnt; + uint scent_rtemp; + uint scent_tstate; + uint scent_t_ptr; + ushort scent_tbptr; + ushort scent_t_cnt; + uint scent_ttemp; + ushort scent_max_sl; + ushort scent_sl_cnt; + ushort scent_character1; + ushort scent_character2; + ushort scent_character3; + ushort scent_character4; + ushort scent_character5; + ushort scent_character6; + ushort scent_character7; + ushort scent_character8; + ushort scent_rccm; + ushort scent_rccr; +} smc_cent_t; + +/* Centronics Status Mask Register. +*/ +#define SMC_CENT_F ((u_char)0x08) +#define SMC_CENT_PE ((u_char)0x04) +#define SMC_CENT_S ((u_char)0x02) + +/* SMC Event and Mask register. +*/ +#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ +#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ +#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SI Clock Route Register +*/ +#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) +#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) +#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) +#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) +#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) +#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* Function code bits. +*/ +#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* CPM Ethernet through SCCx. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PMSR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ +#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ +#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + char res1[8]; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PMSR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0002) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ + char res1[4]; /* Reserved */ + ushort iic_rpbase; /* Relocation pointer */ + char res2[2]; /* Reserved */ +} iic_t; + +#define BD_IIC_START ((ushort)0x0400) + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; + ushort spi_rpbase; /* Relocation pointer */ + ushort spi_res2; +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ +#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ +#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +/* SPIE fields */ +#define SPIE_MME 0x20 +#define SPIE_TXE 0x10 +#define SPIE_BSY 0x04 +#define SPIE_TXB 0x02 +#define SPIE_RXB 0x01 + +/* + * RISC Controller Configuration Register definitons + */ +#define RCCR_TIME 0x8000 /* RISC Timer Enable */ +#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ +#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ + +/* RISC Timer Parameter RAM offset */ +#define PROFF_RTMR ((uint)0x01B0) + +typedef struct risc_timer_pram { + unsigned short tm_base; /* RISC Timer Table Base Address */ + unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ + unsigned short r_tmr; /* RISC Timer Mode Register */ + unsigned short r_tmv; /* RISC Timer Valid Register */ + unsigned long tm_cmd; /* RISC Timer Command Register */ + unsigned long tm_cnt; /* RISC Timer Internal Count */ +} rt_pram_t; + +/* Bits in RISC Timer Command Register */ +#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ +#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ +#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ +#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ +#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ + +/* CPM interrupts. There are nearly 32 interrupts generated by CPM + * channels or devices. All of these are presented to the PPC core + * as a single interrupt. The CPM interrupt handler dispatches its + * own handlers, in a similar fashion to the PPC core handler. We + * use the table as defined in the manuals (i.e. no special high + * priority and SCC1 == SCCa, etc...). + */ +#define CPMVEC_NR 32 +#define CPMVEC_PIO_PC15 ((ushort)0x1f) +#define CPMVEC_SCC1 ((ushort)0x1e) +#define CPMVEC_SCC2 ((ushort)0x1d) +#define CPMVEC_SCC3 ((ushort)0x1c) +#define CPMVEC_SCC4 ((ushort)0x1b) +#define CPMVEC_PIO_PC14 ((ushort)0x1a) +#define CPMVEC_TIMER1 ((ushort)0x19) +#define CPMVEC_PIO_PC13 ((ushort)0x18) +#define CPMVEC_PIO_PC12 ((ushort)0x17) +#define CPMVEC_SDMA_CB_ERR ((ushort)0x16) +#define CPMVEC_IDMA1 ((ushort)0x15) +#define CPMVEC_IDMA2 ((ushort)0x14) +#define CPMVEC_TIMER2 ((ushort)0x12) +#define CPMVEC_RISCTIMER ((ushort)0x11) +#define CPMVEC_I2C ((ushort)0x10) +#define CPMVEC_PIO_PC11 ((ushort)0x0f) +#define CPMVEC_PIO_PC10 ((ushort)0x0e) +#define CPMVEC_TIMER3 ((ushort)0x0c) +#define CPMVEC_PIO_PC9 ((ushort)0x0b) +#define CPMVEC_PIO_PC8 ((ushort)0x0a) +#define CPMVEC_PIO_PC7 ((ushort)0x09) +#define CPMVEC_TIMER4 ((ushort)0x07) +#define CPMVEC_PIO_PC6 ((ushort)0x06) +#define CPMVEC_SPI ((ushort)0x05) +#define CPMVEC_SMC1 ((ushort)0x04) +#define CPMVEC_SMC2 ((ushort)0x03) +#define CPMVEC_PIO_PC5 ((ushort)0x02) +#define CPMVEC_PIO_PC4 ((ushort)0x01) +#define CPMVEC_ERROR ((ushort)0x00) + +/* CPM interrupt configuration vector. +*/ +#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ +#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ +#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ +#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ +#define CICR_IEN ((uint)0x00000080) /* Int. enable */ +#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ + +extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); +extern void cpm_free_handler(int vec); + +#endif /* __CPM_8XX__ */ diff -puN /dev/null include/asm-powerpc/cpm2.h --- /dev/null +++ a/include/asm-powerpc/cpm2.h @@ -0,0 +1,1248 @@ +/* + * Communication Processor Module v2. + * + * This file contains structures and information for the communication + * processor channels found in the dual port RAM or parameter RAM. + * All CPM control and status is available through the CPM2 internal + * memory map. See immap_cpm2.h for details. + */ +#ifdef __KERNEL__ +#ifndef __CPM2__ +#define __CPM2__ + +#include + +/* CPM Command register. +*/ +#define CPM_CR_RST ((uint)0x80000000) +#define CPM_CR_PAGE ((uint)0x7c000000) +#define CPM_CR_SBLOCK ((uint)0x03e00000) +#define CPM_CR_FLG ((uint)0x00010000) +#define CPM_CR_MCN ((uint)0x00003fc0) +#define CPM_CR_OPCODE ((uint)0x0000000f) + +/* Device sub-block and page codes. +*/ +#define CPM_CR_SCC1_SBLOCK (0x04) +#define CPM_CR_SCC2_SBLOCK (0x05) +#define CPM_CR_SCC3_SBLOCK (0x06) +#define CPM_CR_SCC4_SBLOCK (0x07) +#define CPM_CR_SMC1_SBLOCK (0x08) +#define CPM_CR_SMC2_SBLOCK (0x09) +#define CPM_CR_SPI_SBLOCK (0x0a) +#define CPM_CR_I2C_SBLOCK (0x0b) +#define CPM_CR_TIMER_SBLOCK (0x0f) +#define CPM_CR_RAND_SBLOCK (0x0e) +#define CPM_CR_FCC1_SBLOCK (0x10) +#define CPM_CR_FCC2_SBLOCK (0x11) +#define CPM_CR_FCC3_SBLOCK (0x12) +#define CPM_CR_IDMA1_SBLOCK (0x14) +#define CPM_CR_IDMA2_SBLOCK (0x15) +#define CPM_CR_IDMA3_SBLOCK (0x16) +#define CPM_CR_IDMA4_SBLOCK (0x17) +#define CPM_CR_MCC1_SBLOCK (0x1c) + +#define CPM_CR_FCC_SBLOCK(x) (x + 0x10) + +#define CPM_CR_SCC1_PAGE (0x00) +#define CPM_CR_SCC2_PAGE (0x01) +#define CPM_CR_SCC3_PAGE (0x02) +#define CPM_CR_SCC4_PAGE (0x03) +#define CPM_CR_SMC1_PAGE (0x07) +#define CPM_CR_SMC2_PAGE (0x08) +#define CPM_CR_SPI_PAGE (0x09) +#define CPM_CR_I2C_PAGE (0x0a) +#define CPM_CR_TIMER_PAGE (0x0a) +#define CPM_CR_RAND_PAGE (0x0a) +#define CPM_CR_FCC1_PAGE (0x04) +#define CPM_CR_FCC2_PAGE (0x05) +#define CPM_CR_FCC3_PAGE (0x06) +#define CPM_CR_IDMA1_PAGE (0x07) +#define CPM_CR_IDMA2_PAGE (0x08) +#define CPM_CR_IDMA3_PAGE (0x09) +#define CPM_CR_IDMA4_PAGE (0x0a) +#define CPM_CR_MCC1_PAGE (0x07) +#define CPM_CR_MCC2_PAGE (0x08) + +#define CPM_CR_FCC_PAGE(x) (x + 0x04) + +/* Some opcodes (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_SET_GADDR ((ushort)0x0008) +#define CPM_CR_START_IDMA ((ushort)0x0009) +#define CPM_CR_STOP_IDMA ((ushort)0x000b) + +#define mk_cr_cmd(PG, SBC, MCN, OP) \ + ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) + +/* Dual Port RAM addresses. The first 16K is available for almost + * any CPM use, so we put the BDs there. The first 128 bytes are + * used for SMC1 and SMC2 parameter RAM, so we start allocating + * BDs above that. All of this must change when we start + * downloading RAM microcode. + */ +#define CPM_DATAONLY_BASE ((uint)128) +#define CPM_DP_NOSPACE ((uint)0x7fffffff) +#if defined(CONFIG_8272) || defined(CONFIG_MPC8555) +#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) +#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) +#else +#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) +#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) +#endif + +/* The number of pages of host memory we allocate for CPM. This is + * done early in kernel initialization to get physically contiguous + * pages. + */ +#define NUM_CPM_HOST_PAGES 2 + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ + +extern unsigned long cpm_dpalloc(uint size, uint align); +extern int cpm_dpfree(unsigned long offset); +extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); +extern void cpm_dpdump(void); +extern void *cpm_dpram_addr(unsigned long offset); +extern void cpm_setbrg(uint brg, uint rate); +extern void cpm2_fastbrg(uint brg, uint rate, int div16); +extern void cpm2_reset(void); + + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* ?? */ + +/* Function code bits, usually generic to devices. +*/ +#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ +#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ +#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ +#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ +#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ + +/* Parameter RAM offsets from the base. +*/ +#define PROFF_SCC1 ((uint)0x8000) +#define PROFF_SCC2 ((uint)0x8100) +#define PROFF_SCC3 ((uint)0x8200) +#define PROFF_SCC4 ((uint)0x8300) +#define PROFF_FCC1 ((uint)0x8400) +#define PROFF_FCC2 ((uint)0x8500) +#define PROFF_FCC3 ((uint)0x8600) +#define PROFF_MCC1 ((uint)0x8700) +#define PROFF_SMC1_BASE ((uint)0x87fc) +#define PROFF_IDMA1_BASE ((uint)0x87fe) +#define PROFF_MCC2 ((uint)0x8800) +#define PROFF_SMC2_BASE ((uint)0x88fc) +#define PROFF_IDMA2_BASE ((uint)0x88fe) +#define PROFF_SPI_BASE ((uint)0x89fc) +#define PROFF_IDMA3_BASE ((uint)0x89fe) +#define PROFF_TIMERS ((uint)0x8ae0) +#define PROFF_REVNUM ((uint)0x8af0) +#define PROFF_RAND ((uint)0x8af8) +#define PROFF_I2C_BASE ((uint)0x8afc) +#define PROFF_IDMA4_BASE ((uint)0x8afe) + +#define PROFF_SCC_SIZE ((uint)0x100) +#define PROFF_FCC_SIZE ((uint)0x100) +#define PROFF_SMC_SIZE ((uint)64) + +/* The SMCs are relocated to any of the first eight DPRAM pages. + * We will fix these at the first locations of DPRAM, until we + * get some microcode patches :-). + * The parameter ram space for the SMCs is fifty-some bytes, and + * they are required to start on a 64 byte boundary. + */ +#define PROFF_SMC1 (0) +#define PROFF_SMC2 (64) + + +/* Define enough so I can at least use the serial port as a UART. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ + uint smc_stmp; /* SDMA Temp */ +} smc_uart_t; + +/* SMC uart mode register (Internal memory map). +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC Event and Mask register. +*/ +#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ +#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ +#define SMCM_TXE ((unsigned char)0x10) +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* CPM Ethernet through SCC1. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PSMR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. + * Common to SCC and FCC. + */ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ +#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. + * Common to SCC and FCC. + */ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + uint scc_res1; /* Reserved */ + uint scc_res2; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PSMR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0002) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* How about some FCCs..... +*/ +#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) +#define FCC_GFMR_DIAG_LE ((uint)0x40000000) +#define FCC_GFMR_DIAG_AE ((uint)0x80000000) +#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) +#define FCC_GFMR_TCI ((uint)0x20000000) +#define FCC_GFMR_TRX ((uint)0x10000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_CDP ((uint)0x04000000) +#define FCC_GFMR_CTSP ((uint)0x02000000) +#define FCC_GFMR_CDS ((uint)0x01000000) +#define FCC_GFMR_CTSS ((uint)0x00800000) +#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) +#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) +#define FCC_GFMR_SYNL_8 ((uint)0x00008000) +#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) +#define FCC_GFMR_RTSM ((uint)0x00002000) +#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) +#define FCC_GFMR_REVD ((uint)0x00000400) +#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) +#define FCC_GFMR_TCRC_16 ((uint)0x00000000) +#define FCC_GFMR_TCRC_32 ((uint)0x00000080) +#define FCC_GFMR_ENR ((uint)0x00000020) +#define FCC_GFMR_ENT ((uint)0x00000010) +#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) +#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) +#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) + +/* Generic FCC parameter ram. +*/ +typedef struct fcc_param { + ushort fcc_riptr; /* Rx Internal temp pointer */ + ushort fcc_tiptr; /* Tx Internal temp pointer */ + ushort fcc_res1; + ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ + uint fcc_rstate; /* Upper byte is Func code, must be set */ + uint fcc_rbase; /* Receive BD base */ + ushort fcc_rbdstat; /* RxBD status */ + ushort fcc_rbdlen; /* RxBD down counter */ + uint fcc_rdptr; /* RxBD internal data pointer */ + uint fcc_tstate; /* Upper byte is Func code, must be set */ + uint fcc_tbase; /* Transmit BD base */ + ushort fcc_tbdstat; /* TxBD status */ + ushort fcc_tbdlen; /* TxBD down counter */ + uint fcc_tdptr; /* TxBD internal data pointer */ + uint fcc_rbptr; /* Rx BD Internal buf pointer */ + uint fcc_tbptr; /* Tx BD Internal buf pointer */ + uint fcc_rcrc; /* Rx temp CRC */ + uint fcc_res2; + uint fcc_tcrc; /* Tx temp CRC */ +} fccp_t; + + +/* Ethernet controller through FCC. +*/ +typedef struct fcc_enet { + fccp_t fen_genfcc; + uint fen_statbuf; /* Internal status buffer */ + uint fen_camptr; /* CAM address */ + uint fen_cmask; /* Constant mask for CRC */ + uint fen_cpres; /* Preset CRC */ + uint fen_crcec; /* CRC Error counter */ + uint fen_alec; /* alignment error counter */ + uint fen_disfc; /* discard frame counter */ + ushort fen_retlim; /* Retry limit */ + ushort fen_retcnt; /* Retry counter */ + ushort fen_pper; /* Persistence */ + ushort fen_boffcnt; /* backoff counter */ + uint fen_gaddrh; /* Group address filter, high 32-bits */ + uint fen_gaddrl; /* Group address filter, low 32-bits */ + ushort fen_tfcstat; /* out of sequence TxBD */ + ushort fen_tfclen; + uint fen_tfcptr; + ushort fen_mflr; /* Maximum frame length (1518) */ + ushort fen_paddrh; /* MAC address */ + ushort fen_paddrm; + ushort fen_paddrl; + ushort fen_ibdcount; /* Internal BD counter */ + ushort fen_ibdstart; /* Internal BD start pointer */ + ushort fen_ibdend; /* Internal BD end pointer */ + ushort fen_txlen; /* Internal Tx frame length counter */ + uint fen_ibdbase[8]; /* Internal use */ + uint fen_iaddrh; /* Individual address filter */ + uint fen_iaddrl; + ushort fen_minflr; /* Minimum frame length (64) */ + ushort fen_taddrh; /* Filter transfer MAC address */ + ushort fen_taddrm; + ushort fen_taddrl; + ushort fen_padptr; /* Pointer to pad byte buffer */ + ushort fen_cftype; /* control frame type */ + ushort fen_cfrange; /* control frame range */ + ushort fen_maxb; /* maximum BD count */ + ushort fen_maxd1; /* Max DMA1 length (1520) */ + ushort fen_maxd2; /* Max DMA2 length (1520) */ + ushort fen_maxd; /* internal max DMA count */ + ushort fen_dmacnt; /* internal DMA counter */ + uint fen_octc; /* Total octect counter */ + uint fen_colc; /* Total collision counter */ + uint fen_broc; /* Total broadcast packet counter */ + uint fen_mulc; /* Total multicast packet count */ + uint fen_uspc; /* Total packets < 64 bytes */ + uint fen_frgc; /* Total packets < 64 bytes with errors */ + uint fen_ospc; /* Total packets > 1518 */ + uint fen_jbrc; /* Total packets > 1518 with errors */ + uint fen_p64c; /* Total packets == 64 bytes */ + uint fen_p65c; /* Total packets 64 < bytes <= 127 */ + uint fen_p128c; /* Total packets 127 < bytes <= 255 */ + uint fen_p256c; /* Total packets 256 < bytes <= 511 */ + uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ + uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ + uint fen_cambuf; /* Internal CAM buffer poiner */ + ushort fen_rfthr; /* Received frames threshold */ + ushort fen_rfcnt; /* Received frames count */ +} fcc_enet_t; + +/* FCC Event/Mask register as used by Ethernet. +*/ +#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ +#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ +#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ +#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* FCC Mode Register (FPSMR) as used by Ethernet. +*/ +#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ +#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ +#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ +#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ +#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ +#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ +#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ +#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ +#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ +#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ +#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ +#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ +#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ +} iic_t; + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; /* Tx temp. */ + uint spi_res1[4]; /* SDMA temp. */ +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) +#define SPMODE_PM(x) ((x) &0xF) + +#define SPI_EB ((u_char)0x10) /* big endian byte order */ + +#define BD_IIC_START ((ushort)0x0400) + +/* IDMA parameter RAM +*/ +typedef struct idma { + ushort ibase; /* IDMA buffer descriptor table base address */ + ushort dcm; /* DMA channel mode */ + ushort ibdptr; /* IDMA current buffer descriptor pointer */ + ushort dpr_buf; /* IDMA transfer buffer base address */ + ushort buf_inv; /* internal buffer inventory */ + ushort ss_max; /* steady-state maximum transfer size */ + ushort dpr_in_ptr; /* write pointer inside the internal buffer */ + ushort sts; /* source transfer size */ + ushort dpr_out_ptr; /* read pointer inside the internal buffer */ + ushort seob; /* source end of burst */ + ushort deob; /* destination end of burst */ + ushort dts; /* destination transfer size */ + ushort ret_add; /* return address when working in ERM=1 mode */ + ushort res0; /* reserved */ + uint bd_cnt; /* internal byte count */ + uint s_ptr; /* source internal data pointer */ + uint d_ptr; /* destination internal data pointer */ + uint istate; /* internal state */ + u_char res1[20]; /* pad to 64-byte length */ +} idma_t; + +/* DMA channel mode bit fields +*/ +#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ +#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ +#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ +#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ +#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ +#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ +#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ +#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ +#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ +#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ +#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ +#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ +#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ + +/* IDMA Buffer Descriptors +*/ +typedef struct idma_bd { + uint flags; + uint len; /* data length */ + uint src; /* source data buffer pointer */ + uint dst; /* destination data buffer pointer */ +} idma_bd_t; + +/* IDMA buffer descriptor flag bit fields +*/ +#define IDMA_BD_V ((uint)0x80000000) /* valid */ +#define IDMA_BD_W ((uint)0x20000000) /* wrap */ +#define IDMA_BD_I ((uint)0x10000000) /* interrupt */ +#define IDMA_BD_L ((uint)0x08000000) /* last */ +#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ +#define IDMA_BD_SDN ((uint)0x00400000) /* source done */ +#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ +#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ +#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ +#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ +#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ +#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ +#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ +#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ +#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ + +/* per-channel IDMA registers +*/ +typedef struct im_idma { + u_char idsr; /* IDMAn event status register */ + u_char res0[3]; + u_char idmr; /* IDMAn event mask register */ + u_char res1[3]; +} im_idma_t; + +/* IDMA event register bit fields +*/ +#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ +#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ +#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ +#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ + +/* RISC Controller Configuration Register (RCCR) bit fields +*/ +#define RCCR_TIME ((uint)0x80000000) /* timer enable */ +#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ +#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ +#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ +#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ +#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ +#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ +#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ +#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ +#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ +#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ +#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ +#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ +#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ +#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ +#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ +#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ +#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ +#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ +#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ +#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ +#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ +#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ +#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ +#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ +#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ +#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ +#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ +#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ +#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ +#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ +#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ +#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ +#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ +#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ +#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ +#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ +#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ + +/*----------------------------------------------------------------------- + * CMXFCR - CMX FCC Clock Route Register + */ +#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ +#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ +#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ +#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ +#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ +#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ +#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ +#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ +#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ + +#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ +#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ +#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ +#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ +#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ +#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ +#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ +#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ + +#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ +#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ +#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ +#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ +#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ +#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ +#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ +#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ + +#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ +#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ +#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ +#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ +#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ +#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ +#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ +#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ + +#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ +#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ +#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ +#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ +#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ +#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ +#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ +#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ + +#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ +#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ +#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ +#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ +#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ +#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ +#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ +#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ + +#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ +#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ +#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ +#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ +#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ +#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ +#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ +#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ + +/*----------------------------------------------------------------------- + * CMXSCR - CMX SCC Clock Route Register + */ +#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ +#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ +#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ +#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ +#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ +#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ +#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ +#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ +#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ +#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ +#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ +#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ +#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ +#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ +#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ +#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ + +#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ +#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ +#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ +#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ +#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ +#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ +#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ +#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ +#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ +#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ +#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ +#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ +#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ +#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ +#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ +#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ +#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ +#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ +#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ +#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ +#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ +#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ +#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ +#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ +#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ +#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ +#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ +#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ +#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ +#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ +#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ +#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ +#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ +#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ +#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ +#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ +#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ +#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ +#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ +#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ +#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ +#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ +#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ + +#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ +#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ +#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ +#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ +#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ +#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ +#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ +#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ +#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ +#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ +#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ +#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ +#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ +#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ +#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration Register 4-31 + */ +#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ +#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ +#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ +#define SIUMCR_CDIS 0x10000000 /* Core Disable */ +#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ +#define SIUMCR_DPPC01 0x04000000 /* - " - */ +#define SIUMCR_DPPC10 0x08000000 /* - " - */ +#define SIUMCR_DPPC11 0x0c000000 /* - " - */ +#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ +#define SIUMCR_L2CPC01 0x01000000 /* - " - */ +#define SIUMCR_L2CPC10 0x02000000 /* - " - */ +#define SIUMCR_L2CPC11 0x03000000 /* - " - */ +#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ +#define SIUMCR_LBPC01 0x00400000 /* - " - */ +#define SIUMCR_LBPC10 0x00800000 /* - " - */ +#define SIUMCR_LBPC11 0x00c00000 /* - " - */ +#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ +#define SIUMCR_APPC01 0x00100000 /* - " - */ +#define SIUMCR_APPC10 0x00200000 /* - " - */ +#define SIUMCR_APPC11 0x00300000 /* - " - */ +#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ +#define SIUMCR_CS10PC01 0x00040000 /* - " - */ +#define SIUMCR_CS10PC10 0x00080000 /* - " - */ +#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ +#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ +#define SIUMCR_BCTLC01 0x00010000 /* - " - */ +#define SIUMCR_BCTLC10 0x00020000 /* - " - */ +#define SIUMCR_BCTLC11 0x00030000 /* - " - */ +#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ +#define SIUMCR_MMR01 0x00004000 /* - " - */ +#define SIUMCR_MMR10 0x00008000 /* - " - */ +#define SIUMCR_MMR11 0x0000c000 /* - " - */ +#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control Register 9-8 +*/ +#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ +#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ +#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ +#define SCCR_PCIDF_SHIFT 3 + +#ifndef CPM_IMMR_OFFSET +#define CPM_IMMR_OFFSET 0x101a8 +#endif + +#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ + +/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK + * in order to use clock-computing stuff below for the FCC x + */ + +/* Automatically generates register configurations */ +#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ + +#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ +#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ +#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ +#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ +#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ +#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ + +#define PC_F1RXCLK PC_CLK(F1_RXCLK) +#define PC_F1TXCLK PC_CLK(F1_TXCLK) +#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) +#define CMX1_CLK_MASK ((uint)0xff000000) + +#define PC_F2RXCLK PC_CLK(F2_RXCLK) +#define PC_F2TXCLK PC_CLK(F2_TXCLK) +#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) +#define CMX2_CLK_MASK ((uint)0x00ff0000) + +#define PC_F3RXCLK PC_CLK(F3_RXCLK) +#define PC_F3TXCLK PC_CLK(F3_TXCLK) +#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) +#define CMX3_CLK_MASK ((uint)0x0000ff00) + +#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) +#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) + +#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) + +/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PA1_COL 0x00000001U +#define PA1_CRS 0x00000002U +#define PA1_TXER 0x00000004U +#define PA1_TXEN 0x00000008U +#define PA1_RXDV 0x00000010U +#define PA1_RXER 0x00000020U +#define PA1_TXDAT 0x00003c00U +#define PA1_RXDAT 0x0003c000U +#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) +#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ + PA1_RXDV | PA1_RXER) +#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) +#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) + + +/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB2_TXER 0x00000001U +#define PB2_RXDV 0x00000002U +#define PB2_TXEN 0x00000004U +#define PB2_RXER 0x00000008U +#define PB2_COL 0x00000010U +#define PB2_CRS 0x00000020U +#define PB2_TXDAT 0x000003c0U +#define PB2_RXDAT 0x00003c00U +#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ + PB2_RXER | PB2_RXDV | PB2_TXER) +#define PB2_PSORB1 (PB2_TXEN) +#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) +#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) + + +/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB3_RXDV 0x00004000U +#define PB3_RXER 0x00008000U +#define PB3_TXER 0x00010000U +#define PB3_TXEN 0x00020000U +#define PB3_COL 0x00040000U +#define PB3_CRS 0x00080000U +#define PB3_TXDAT 0x0f000000U +#define PC3_TXDAT 0x00000010U +#define PB3_RXDAT 0x00f00000U +#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ + PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) +#define PB3_PSORB1 0 +#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) +#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) +#define PC3_DIRC1 (PC3_TXDAT) + +/* Handy macro to specify mem for FCCs*/ +#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) +#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) +#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) +#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) + +/* Clocks and GRG's */ + +enum cpm_clk_dir { + CPM_CLK_RX, + CPM_CLK_TX, + CPM_CLK_RTX +}; + +enum cpm_clk_target { + CPM_CLK_SCC1, + CPM_CLK_SCC2, + CPM_CLK_SCC3, + CPM_CLK_SCC4, + CPM_CLK_FCC1, + CPM_CLK_FCC2, + CPM_CLK_FCC3 +}; + +enum cpm_clk { + CPM_CLK_NONE = 0, + CPM_BRG1, /* Baud Rate Generator 1 */ + CPM_BRG2, /* Baud Rate Generator 2 */ + CPM_BRG3, /* Baud Rate Generator 3 */ + CPM_BRG4, /* Baud Rate Generator 4 */ + CPM_BRG5, /* Baud Rate Generator 5 */ + CPM_BRG6, /* Baud Rate Generator 6 */ + CPM_BRG7, /* Baud Rate Generator 7 */ + CPM_BRG8, /* Baud Rate Generator 8 */ + CPM_CLK1, /* Clock 1 */ + CPM_CLK2, /* Clock 2 */ + CPM_CLK3, /* Clock 3 */ + CPM_CLK4, /* Clock 4 */ + CPM_CLK5, /* Clock 5 */ + CPM_CLK6, /* Clock 6 */ + CPM_CLK7, /* Clock 7 */ + CPM_CLK8, /* Clock 8 */ + CPM_CLK9, /* Clock 9 */ + CPM_CLK10, /* Clock 10 */ + CPM_CLK11, /* Clock 11 */ + CPM_CLK12, /* Clock 12 */ + CPM_CLK13, /* Clock 13 */ + CPM_CLK14, /* Clock 14 */ + CPM_CLK15, /* Clock 15 */ + CPM_CLK16, /* Clock 16 */ + CPM_CLK17, /* Clock 17 */ + CPM_CLK18, /* Clock 18 */ + CPM_CLK19, /* Clock 19 */ + CPM_CLK20, /* Clock 20 */ + CPM_CLK_DUMMY +}; + +extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); + +#endif /* __CPM2__ */ +#endif /* __KERNEL__ */ diff -puN include/asm-powerpc/cputable.h~git-powerpc include/asm-powerpc/cputable.h --- a/include/asm-powerpc/cputable.h~git-powerpc +++ a/include/asm-powerpc/cputable.h @@ -136,6 +136,7 @@ extern void do_feature_fixups(unsigned l #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) +#define CPU_FTR_SPE ASM_CONST(0x0000000002000000) /* * Add the 64-bit processor unique features in the top half of the word; @@ -180,6 +181,21 @@ extern void do_feature_fixups(unsigned l #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 #endif +/* We only set the spe features if the kernel was compiled with spe + * support + */ +#ifdef CONFIG_SPE +#define CPU_FTR_SPE_COMP CPU_FTR_SPE +#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE +#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE +#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE +#else +#define CPU_FTR_SPE_COMP 0 +#define PPC_FEATURE_HAS_SPE_COMP 0 +#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 +#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 +#endif + /* We need to mark all pages as being coherent if we're SMP or we * have a 74[45]x and an MPC107 host bridge. Also 83xx requires * it for PCI "streaming/prefetch" to work properly. @@ -310,10 +326,12 @@ extern void do_feature_fixups(unsigned l #define CPU_FTRS_8XX (CPU_FTR_USE_TB) #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ - CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) -#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ + CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ + CPU_FTR_UNIFIED_ID_CACHE) +#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ + CPU_FTR_NODSISRALIGN) +#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) diff -puN include/asm-powerpc/dma-mapping.h~git-powerpc include/asm-powerpc/dma-mapping.h --- a/include/asm-powerpc/dma-mapping.h~git-powerpc +++ a/include/asm-powerpc/dma-mapping.h @@ -249,8 +249,12 @@ dma_map_single(struct device *dev, void return virt_to_bus(ptr); } -/* We do nothing. */ -#define dma_unmap_single(dev, addr, size, dir) ((void)0) +static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, + size_t size, + enum dma_data_direction direction) +{ + /* We do nothing. */ +} static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, @@ -264,8 +268,12 @@ dma_map_page(struct device *dev, struct return page_to_bus(page) + offset; } -/* We do nothing. */ -#define dma_unmap_page(dev, handle, size, dir) ((void)0) +static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, + size_t size, + enum dma_data_direction direction) +{ + /* We do nothing. */ +} static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, @@ -284,8 +292,12 @@ dma_map_sg(struct device *dev, struct sc return nents; } -/* We don't do anything here. */ -#define dma_unmap_sg(dev, sg, nents, dir) ((void)0) +static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, + enum dma_data_direction direction) +{ + /* We don't do anything here. */ +} #endif /* CONFIG_PPC64 */ diff -puN include/asm-powerpc/elf.h~git-powerpc include/asm-powerpc/elf.h --- a/include/asm-powerpc/elf.h~git-powerpc +++ a/include/asm-powerpc/elf.h @@ -413,13 +413,8 @@ do { \ /* Notes used in ET_CORE. Note name is "SPU//". */ #define NT_SPU 1 -extern int arch_notes_size(void); -extern void arch_write_notes(struct file *file); - -#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size() -#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file) - #define ARCH_HAVE_EXTRA_ELF_NOTES -#endif /* CONFIG_PPC_CELL */ + +#endif /* CONFIG_SPU_BASE */ #endif /* _ASM_POWERPC_ELF_H */ diff -puN /dev/null include/asm-powerpc/exception.h --- /dev/null +++ a/include/asm-powerpc/exception.h @@ -0,0 +1,311 @@ +#ifndef _ASM_POWERPC_EXCEPTION_H +#define _ASM_POWERPC_EXCEPTION_H +/* + * Extracted from head_64.S + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * + * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and + * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com + * + * This file contains the low-level support and setup for the + * PowerPC-64 platform, including trap and interrupt dispatch. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +/* + * The following macros define the code that appears as + * the prologue to each of the exception handlers. They + * are split into two parts to allow a single kernel binary + * to be used for pSeries and iSeries. + * + * We make as much of the exception code common between native + * exception handlers (including pSeries LPAR) and iSeries LPAR + * implementations as possible. + */ + +#define EX_R9 0 +#define EX_R10 8 +#define EX_R11 16 +#define EX_R12 24 +#define EX_R13 32 +#define EX_SRR0 40 +#define EX_DAR 48 +#define EX_DSISR 56 +#define EX_CCR 60 +#define EX_R3 64 +#define EX_LR 72 + +/* + * We're short on space and time in the exception prolog, so we can't + * use the normal SET_REG_IMMEDIATE macro. Normally we just need the + * low halfword of the address, but for Kdump we need the whole low + * word. + */ +#ifdef CONFIG_CRASH_DUMP +#define LOAD_HANDLER(reg, label) \ + oris reg,reg,(label)@h; /* virt addr of handler ... */ \ + ori reg,reg,(label)@l; /* .. and the rest */ +#else +#define LOAD_HANDLER(reg, label) \ + ori reg,reg,(label)@l; /* virt addr of handler ... */ +#endif + +#define EXCEPTION_PROLOG_1(area) \ + mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ + std r9,area+EX_R9(r13); /* save r9 - r12 */ \ + std r10,area+EX_R10(r13); \ + std r11,area+EX_R11(r13); \ + std r12,area+EX_R12(r13); \ + mfspr r9,SPRN_SPRG1; \ + std r9,area+EX_R13(r13); \ + mfcr r9 + +/* + * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. + * The firmware calls the registered system_reset_fwnmi and + * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run + * a 32bit application at the time of the event. + * This firmware bug is present on POWER4 and JS20. + */ +#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ + EXCEPTION_PROLOG_1(area); \ + clrrdi r12,r13,32; /* get high part of &label */ \ + mfmsr r10; \ + /* force 64bit mode */ \ + li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ + rldimi r10,r11,61,0; /* insert into top 3 bits */ \ + /* done 64bit mode */ \ + mfspr r11,SPRN_SRR0; /* save SRR0 */ \ + LOAD_HANDLER(r12,label) \ + ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ + mtspr SPRN_SRR0,r12; \ + mfspr r12,SPRN_SRR1; /* and SRR1 */ \ + mtspr SPRN_SRR1,r10; \ + rfid; \ + b . /* prevent speculative execution */ + +#define EXCEPTION_PROLOG_PSERIES(area, label) \ + EXCEPTION_PROLOG_1(area); \ + clrrdi r12,r13,32; /* get high part of &label */ \ + mfmsr r10; \ + mfspr r11,SPRN_SRR0; /* save SRR0 */ \ + LOAD_HANDLER(r12,label) \ + ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ + mtspr SPRN_SRR0,r12; \ + mfspr r12,SPRN_SRR1; /* and SRR1 */ \ + mtspr SPRN_SRR1,r10; \ + rfid; \ + b . /* prevent speculative execution */ + +/* + * The common exception prolog is used for all except a few exceptions + * such as a segment miss on a kernel address. We have to be prepared + * to take another exception from the point where we first touch the + * kernel stack onwards. + * + * On entry r13 points to the paca, r9-r13 are saved in the paca, + * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and + * SRR1, and relocation is on. + */ +#define EXCEPTION_PROLOG_COMMON(n, area) \ + andi. r10,r12,MSR_PR; /* See if coming from user */ \ + mr r10,r1; /* Save r1 */ \ + subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ + beq- 1f; \ + ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ +1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ + bge- cr1,2f; /* abort if it is */ \ + b 3f; \ +2: li r1,(n); /* will be reloaded later */ \ + sth r1,PACA_TRAP_SAVE(r13); \ + b bad_stack; \ +3: std r9,_CCR(r1); /* save CR in stackframe */ \ + std r11,_NIP(r1); /* save SRR0 in stackframe */ \ + std r12,_MSR(r1); /* save SRR1 in stackframe */ \ + std r10,0(r1); /* make stack chain pointer */ \ + std r0,GPR0(r1); /* save r0 in stackframe */ \ + std r10,GPR1(r1); /* save r1 in stackframe */ \ + ACCOUNT_CPU_USER_ENTRY(r9, r10); \ + std r2,GPR2(r1); /* save r2 in stackframe */ \ + SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ + SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ + ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ + ld r10,area+EX_R10(r13); \ + std r9,GPR9(r1); \ + std r10,GPR10(r1); \ + ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ + ld r10,area+EX_R12(r13); \ + ld r11,area+EX_R13(r13); \ + std r9,GPR11(r1); \ + std r10,GPR12(r1); \ + std r11,GPR13(r1); \ + ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ + mflr r9; /* save LR in stackframe */ \ + std r9,_LINK(r1); \ + mfctr r10; /* save CTR in stackframe */ \ + std r10,_CTR(r1); \ + lbz r10,PACASOFTIRQEN(r13); \ + mfspr r11,SPRN_XER; /* save XER in stackframe */ \ + std r10,SOFTE(r1); \ + std r11,_XER(r1); \ + li r9,(n)+1; \ + std r9,_TRAP(r1); /* set trap number */ \ + li r10,0; \ + ld r11,exception_marker@toc(r2); \ + std r10,RESULT(r1); /* clear regs->result */ \ + std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ + +/* + * Exception vectors. + */ +#define STD_EXCEPTION_PSERIES(n, label) \ + . = n; \ + .globl label##_pSeries; \ +label##_pSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) + +#define HSTD_EXCEPTION_PSERIES(n, label) \ + . = n; \ + .globl label##_pSeries; \ +label##_pSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r20; /* save r20 */ \ + mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ + mtspr SPRN_SRR0,r20; \ + mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ + mtspr SPRN_SRR1,r20; \ + mfspr r20,SPRN_SPRG1; /* restore r20 */ \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) + + +#define MASKABLE_EXCEPTION_PSERIES(n, label) \ + . = n; \ + .globl label##_pSeries; \ +label##_pSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ + std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ + std r10,PACA_EXGEN+EX_R10(r13); \ + lbz r10,PACASOFTIRQEN(r13); \ + mfcr r9; \ + cmpwi r10,0; \ + beq masked_interrupt; \ + mfspr r10,SPRN_SPRG1; \ + std r10,PACA_EXGEN+EX_R13(r13); \ + std r11,PACA_EXGEN+EX_R11(r13); \ + std r12,PACA_EXGEN+EX_R12(r13); \ + clrrdi r12,r13,32; /* get high part of &label */ \ + mfmsr r10; \ + mfspr r11,SPRN_SRR0; /* save SRR0 */ \ + LOAD_HANDLER(r12,label##_common) \ + ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ + mtspr SPRN_SRR0,r12; \ + mfspr r12,SPRN_SRR1; /* and SRR1 */ \ + mtspr SPRN_SRR1,r10; \ + rfid; \ + b . /* prevent speculative execution */ + +#ifdef CONFIG_PPC_ISERIES +#define DISABLE_INTS \ + li r11,0; \ + stb r11,PACASOFTIRQEN(r13); \ +BEGIN_FW_FTR_SECTION; \ + stb r11,PACAHARDIRQEN(r13); \ +END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ +BEGIN_FW_FTR_SECTION; \ + mfmsr r10; \ + ori r10,r10,MSR_EE; \ + mtmsrd r10,1; \ +END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) + +#else +#define DISABLE_INTS \ + li r11,0; \ + stb r11,PACASOFTIRQEN(r13); \ + stb r11,PACAHARDIRQEN(r13) + +#endif /* CONFIG_PPC_ISERIES */ + +#define ENABLE_INTS \ + ld r12,_MSR(r1); \ + mfmsr r11; \ + rlwimi r11,r12,0,MSR_EE; \ + mtmsrd r11,1 + +#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + DISABLE_INTS; \ + bl .save_nvgprs; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except + +/* + * Like STD_EXCEPTION_COMMON, but for exceptions that can occur + * in the idle task and therefore need the special idle handling. + */ +#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + FINISH_NAP; \ + DISABLE_INTS; \ + bl .save_nvgprs; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except + +#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + FINISH_NAP; \ + DISABLE_INTS; \ +BEGIN_FTR_SECTION \ + bl .ppc64_runlatch_on; \ +END_FTR_SECTION_IFSET(CPU_FTR_CTRL) \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except_lite + +/* + * When the idle code in power4_idle puts the CPU into NAP mode, + * it has to do so in a loop, and relies on the external interrupt + * and decrementer interrupt entry code to get it out of the loop. + * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags + * to signal that it is in the loop and needs help to get out. + */ +#ifdef CONFIG_PPC_970_NAP +#define FINISH_NAP \ +BEGIN_FTR_SECTION \ + clrrdi r11,r1,THREAD_SHIFT; \ + ld r9,TI_LOCAL_FLAGS(r11); \ + andi. r10,r9,_TLF_NAPPING; \ + bnel power4_fixup_nap; \ +END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) +#else +#define FINISH_NAP +#endif + +#endif /* _ASM_POWERPC_EXCEPTION_H */ diff -puN /dev/null include/asm-powerpc/highmem.h --- /dev/null +++ a/include/asm-powerpc/highmem.h @@ -0,0 +1,135 @@ +/* + * highmem.h: virtual kernel memory mappings for high memory + * + * PowerPC version, stolen from the i386 version. + * + * Used in CONFIG_HIGHMEM systems for memory pages which + * are not addressable by direct kernel virtual addresses. + * + * Copyright (C) 1999 Gerhard Wichert, Siemens AG + * Gerhard.Wichert@pdb.siemens.de + * + * + * Redesigned the x86 32-bit VM architecture to deal with + * up to 16 Terrabyte physical memory. With current x86 CPUs + * we now support up to 64 Gigabytes physical RAM. + * + * Copyright (C) 1999 Ingo Molnar + */ + +#ifndef _ASM_HIGHMEM_H +#define _ASM_HIGHMEM_H + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include + +/* undef for production */ +#define HIGHMEM_DEBUG 1 + +extern pte_t *kmap_pte; +extern pgprot_t kmap_prot; +extern pte_t *pkmap_page_table; + +/* + * Right now we initialize only a single pte table. It can be extended + * easily, subsequent pte tables have to be allocated in one physical + * chunk of RAM. + */ +#define PKMAP_BASE CONFIG_HIGHMEM_START +#define LAST_PKMAP (1 << PTE_SHIFT) +#define LAST_PKMAP_MASK (LAST_PKMAP-1) +#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) +#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) + +#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL) + +extern void *kmap_high(struct page *page); +extern void kunmap_high(struct page *page); + +static inline void *kmap(struct page *page) +{ + might_sleep(); + if (!PageHighMem(page)) + return page_address(page); + return kmap_high(page); +} + +static inline void kunmap(struct page *page) +{ + BUG_ON(in_interrupt()); + if (!PageHighMem(page)) + return; + kunmap_high(page); +} + +/* + * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap + * gives a more generic (and caching) interface. But kmap_atomic can + * be used in IRQ contexts, so in some (very limited) cases we need + * it. + */ +static inline void *kmap_atomic(struct page *page, enum km_type type) +{ + unsigned int idx; + unsigned long vaddr; + + /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ + pagefault_disable(); + if (!PageHighMem(page)) + return page_address(page); + + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE; +#ifdef HIGHMEM_DEBUG + BUG_ON(!pte_none(*(kmap_pte+idx))); +#endif + set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot)); + flush_tlb_page(NULL, vaddr); + + return (void*) vaddr; +} + +static inline void kunmap_atomic(void *kvaddr, enum km_type type) +{ +#ifdef HIGHMEM_DEBUG + unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; + unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); + + if (vaddr < KMAP_FIX_BEGIN) { // FIXME + pagefault_enable(); + return; + } + + BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE); + + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(&init_mm, vaddr, kmap_pte+idx); + flush_tlb_page(NULL, vaddr); +#endif + pagefault_enable(); +} + +static inline struct page *kmap_atomic_to_page(void *ptr) +{ + unsigned long idx, vaddr = (unsigned long) ptr; + + if (vaddr < KMAP_FIX_BEGIN) + return virt_to_page(ptr); + + idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT; + return pte_page(kmap_pte[idx]); +} + +#define flush_cache_kmaps() flush_cache_all() + +#endif /* __KERNEL__ */ + +#endif /* _ASM_HIGHMEM_H */ diff -puN /dev/null include/asm-powerpc/hydra.h --- /dev/null +++ a/include/asm-powerpc/hydra.h @@ -0,0 +1,102 @@ +/* + * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is based on the following documentation: + * + * Macintosh Technology in the Common Hardware Reference Platform + * Apple Computer, Inc. + * + * © Copyright 1995 Apple Computer, Inc. All rights reserved. + * + * It's available online from http://chrp.apple.com/MacTech.pdf. + * You can obtain paper copies of this book from computer bookstores or by + * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San + * Francisco, CA 94104. Reference ISBN 1-55860-393-X. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _ASMPPC_HYDRA_H +#define _ASMPPC_HYDRA_H + +#ifdef __KERNEL__ + +struct Hydra { + /* DBDMA Controller Register Space */ + char Pad1[0x30]; + u_int CachePD; + u_int IDs; + u_int Feature_Control; + char Pad2[0x7fc4]; + /* DBDMA Channel Register Space */ + char SCSI_DMA[0x100]; + char Pad3[0x300]; + char SCCA_Tx_DMA[0x100]; + char SCCA_Rx_DMA[0x100]; + char SCCB_Tx_DMA[0x100]; + char SCCB_Rx_DMA[0x100]; + char Pad4[0x7800]; + /* Device Register Space */ + char SCSI[0x1000]; + char ADB[0x1000]; + char SCC_Legacy[0x1000]; + char SCC[0x1000]; + char Pad9[0x2000]; + char VIA[0x2000]; + char Pad10[0x28000]; + char OpenPIC[0x40000]; +}; + +extern volatile struct Hydra __iomem *Hydra; + + + /* + * Feature Control Register + */ + +#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ +#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ +#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ +#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ +#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ +#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ +#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ +#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ +#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ + + + /* + * OpenPIC Interrupt Sources + */ + +#define HYDRA_INT_SIO 0 +#define HYDRA_INT_SCSI_DMA 1 +#define HYDRA_INT_SCCA_TX_DMA 2 +#define HYDRA_INT_SCCA_RX_DMA 3 +#define HYDRA_INT_SCCB_TX_DMA 4 +#define HYDRA_INT_SCCB_RX_DMA 5 +#define HYDRA_INT_SCSI 6 +#define HYDRA_INT_SCCA 7 +#define HYDRA_INT_SCCB 8 +#define HYDRA_INT_VIA 9 +#define HYDRA_INT_ADB 10 +#define HYDRA_INT_ADB_NMI 11 +#define HYDRA_INT_EXT1 12 /* PCI IRQW */ +#define HYDRA_INT_EXT2 13 /* PCI IRQX */ +#define HYDRA_INT_EXT3 14 /* PCI IRQY */ +#define HYDRA_INT_EXT4 15 /* PCI IRQZ */ +#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */ +#define HYDRA_INT_EXT6 17 /* IDE Secondary */ +#define HYDRA_INT_EXT7 18 /* Power Off Request */ +#define HYDRA_INT_SPARE 19 + +extern int hydra_init(void); +extern void macio_adb_init(void); + +#endif /* __KERNEL__ */ + +#endif /* _ASMPPC_HYDRA_H */ diff -puN include/asm-powerpc/ide.h~git-powerpc include/asm-powerpc/ide.h --- a/include/asm-powerpc/ide.h~git-powerpc +++ a/include/asm-powerpc/ide.h @@ -67,7 +67,7 @@ static __inline__ unsigned long ide_defa #define ide_init_default_irq(base) ide_default_irq(base) #endif -#if (defined CONFIG_APUS || defined CONFIG_BLK_DEV_MPC8xx_IDE ) +#ifdef CONFIG_BLK_DEV_MPC8xx_IDE #define IDE_ARCH_ACK_INTR 1 #define ide_ack_intr(hwif) (hwif->hw.ack_intr ? hwif->hw.ack_intr(hwif) : 1) #endif diff -puN include/asm-powerpc/immap_86xx.h~git-powerpc include/asm-powerpc/immap_86xx.h --- a/include/asm-powerpc/immap_86xx.h~git-powerpc +++ a/include/asm-powerpc/immap_86xx.h @@ -1,124 +1,65 @@ -/* +/** * MPC86xx Internal Memory Map * - * Author: Jeff Brown + * Authors: Jeff Brown + * Timur Tabi * - * Copyright 2004 Freescale Semiconductor, Inc + * Copyright 2004,2007 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * + * This header file defines structures for various 86xx SOC devices that are + * used by multiple source files. */ #ifndef __ASM_POWERPC_IMMAP_86XX_H__ #define __ASM_POWERPC_IMMAP_86XX_H__ #ifdef __KERNEL__ -/* Eventually this should define all the IO block registers in 86xx */ - -/* PCI Registers */ -typedef struct ccsr_pci { - uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ - uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ - uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ - char res1[3060]; - uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ - uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ - uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ - char res2[4]; - uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ - char res3[12]; - uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ - uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ - uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ - char res4[4]; - uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ - char res5[12]; - uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ - uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ - uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ - char res6[4]; - uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ - char res7[12]; - uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ - uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ - uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ - char res8[4]; - uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ - char res9[12]; - uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ - uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ - uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ - char res10[4]; - uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ - char res11[268]; - uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ - char res12[4]; - uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ - uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ - uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ - char res13[12]; - uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ - char res14[4]; - uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ - uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ - uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ - char res15[12]; - uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ - char res16[4]; - uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ - char res17[4]; - uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ - char res18[12]; - uint err_dr; /* 0x.e00 - PCI Error Detect Register */ - uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ - uint err_en; /* 0x.e08 - PCI Error Enable Register */ - uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ - uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ - uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ - uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ - uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ - uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ - uint pci_timr; /* 0x.e24 - PCI Timer Register */ - char res19[472]; -} ccsr_pci_t; - /* Global Utility Registers */ -typedef struct ccsr_guts { - uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ - uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ - uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ - uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ - uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ - char res1[12]; - uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ - char res2[12]; - uint gpiocr; /* 0x.0030 - GPIO Control Register */ - char res3[12]; - uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ - char res4[12]; - uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ - char res5[12]; - uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ - char res6[12]; - uint devdisr; /* 0x.0070 - Device Disable Control */ - char res7[12]; - uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ - char res8[12]; - uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ - char res9[12]; - uint pvr; /* 0x.00a0 - Processor Version Register */ - uint svr; /* 0x.00a4 - System Version Register */ - char res10[3416]; - uint clkocr; /* 0x.0e00 - Clock Out Select Register */ - char res11[12]; - uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ - char res12[12]; - uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ - char res13[61916]; -} ccsr_guts_t; +struct ccsr_guts { + __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ + __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ + __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ + __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ + __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ + u8 res1[0x20 - 0x14]; + __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ + u8 res2[0x30 - 0x24]; + __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ + u8 res3[0x40 - 0x34]; + __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ + u8 res4[0x50 - 0x44]; + __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ + u8 res5[0x60 - 0x54]; + __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ + u8 res6[0x70 - 0x64]; + __be32 devdisr; /* 0x.0070 - Device Disable Control */ + u8 res7[0x80 - 0x74]; + __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ + u8 res8[0x90 - 0x84]; + __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ + __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ + u8 res9[0xA0 - 0x98]; + __be32 pvr; /* 0x.00a0 - Processor Version Register */ + __be32 svr; /* 0x.00a4 - System Version Register */ + u8 res10[0xB0 - 0xA8]; + __be32 rstcr; /* 0x.00b0 - Reset Control Register */ + u8 res11[0xB20 - 0xB4]; + __be32 ddr1clkdr; /* 0x.0b20 - DDRC1 Clock Disable Register */ + __be32 ddr2clkdr; /* 0x.0b24 - DDRC2 Clock Disable Register */ + u8 res12[0xE00 - 0xB28]; + __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ + u8 res13[0xF04 - 0xE04]; + __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ + __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ + u8 res14[0xF40 - 0xF0C]; + __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */ + __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */ +}; #endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ #endif /* __KERNEL__ */ diff -puN /dev/null include/asm-powerpc/immap_cpm2.h --- /dev/null +++ a/include/asm-powerpc/immap_cpm2.h @@ -0,0 +1,648 @@ +/* + * CPM2 Internal Memory Map + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * + * The Internal Memory Map for devices with CPM2 on them. This + * is the superset of all CPM2 devices (8260, 8266, 8280, 8272, + * 8560). + */ +#ifdef __KERNEL__ +#ifndef __IMMAP_CPM2__ +#define __IMMAP_CPM2__ + +/* System configuration registers. +*/ +typedef struct sys_82xx_conf { + u32 sc_siumcr; + u32 sc_sypcr; + u8 res1[6]; + u16 sc_swsr; + u8 res2[20]; + u32 sc_bcr; + u8 sc_ppc_acr; + u8 res3[3]; + u32 sc_ppc_alrh; + u32 sc_ppc_alrl; + u8 sc_lcl_acr; + u8 res4[3]; + u32 sc_lcl_alrh; + u32 sc_lcl_alrl; + u32 sc_tescr1; + u32 sc_tescr2; + u32 sc_ltescr1; + u32 sc_ltescr2; + u32 sc_pdtea; + u8 sc_pdtem; + u8 res5[3]; + u32 sc_ldtea; + u8 sc_ldtem; + u8 res6[163]; +} sysconf_82xx_cpm2_t; + +typedef struct sys_85xx_conf { + u32 sc_cear; + u16 sc_ceer; + u16 sc_cemr; + u8 res1[70]; + u32 sc_smaer; + u8 res2[4]; + u32 sc_smevr; + u32 sc_smctr; + u32 sc_lmaer; + u8 res3[4]; + u32 sc_lmevr; + u32 sc_lmctr; + u8 res4[144]; +} sysconf_85xx_cpm2_t; + +typedef union sys_conf { + sysconf_82xx_cpm2_t siu_82xx; + sysconf_85xx_cpm2_t siu_85xx; +} sysconf_cpm2_t; + + + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + u32 memc_br0; + u32 memc_or0; + u32 memc_br1; + u32 memc_or1; + u32 memc_br2; + u32 memc_or2; + u32 memc_br3; + u32 memc_or3; + u32 memc_br4; + u32 memc_or4; + u32 memc_br5; + u32 memc_or5; + u32 memc_br6; + u32 memc_or6; + u32 memc_br7; + u32 memc_or7; + u32 memc_br8; + u32 memc_or8; + u32 memc_br9; + u32 memc_or9; + u32 memc_br10; + u32 memc_or10; + u32 memc_br11; + u32 memc_or11; + u8 res1[8]; + u32 memc_mar; + u8 res2[4]; + u32 memc_mamr; + u32 memc_mbmr; + u32 memc_mcmr; + u8 res3[8]; + u16 memc_mptpr; + u8 res4[2]; + u32 memc_mdr; + u8 res5[4]; + u32 memc_psdmr; + u32 memc_lsdmr; + u8 memc_purt; + u8 res6[3]; + u8 memc_psrt; + u8 res7[3]; + u8 memc_lurt; + u8 res8[3]; + u8 memc_lsrt; + u8 res9[3]; + u32 memc_immr; + u32 memc_pcibr0; + u32 memc_pcibr1; + u8 res10[16]; + u32 memc_pcimsk0; + u32 memc_pcimsk1; + u8 res11[52]; +} memctl_cpm2_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + u8 res1[32]; + u16 sit_tmcntsc; + u8 res2[2]; + u32 sit_tmcnt; + u8 res3[4]; + u32 sit_tmcntal; + u8 res4[16]; + u16 sit_piscr; + u8 res5[2]; + u32 sit_pitc; + u32 sit_pitr; + u8 res6[94]; + u8 res7[390]; +} sit_cpm2_t; + +#define PISCR_PIRQ_MASK ((u16)0xff00) +#define PISCR_PS ((u16)0x0080) +#define PISCR_PIE ((u16)0x0004) +#define PISCR_PTF ((u16)0x0002) +#define PISCR_PTE ((u16)0x0001) + +/* PCI Controller. +*/ +typedef struct pci_ctlr { + u32 pci_omisr; + u32 pci_omimr; + u8 res1[8]; + u32 pci_ifqpr; + u32 pci_ofqpr; + u8 res2[8]; + u32 pci_imr0; + u32 pci_imr1; + u32 pci_omr0; + u32 pci_omr1; + u32 pci_odr; + u8 res3[4]; + u32 pci_idr; + u8 res4[20]; + u32 pci_imisr; + u32 pci_imimr; + u8 res5[24]; + u32 pci_ifhpr; + u8 res6[4]; + u32 pci_iftpr; + u8 res7[4]; + u32 pci_iphpr; + u8 res8[4]; + u32 pci_iptpr; + u8 res9[4]; + u32 pci_ofhpr; + u8 res10[4]; + u32 pci_oftpr; + u8 res11[4]; + u32 pci_ophpr; + u8 res12[4]; + u32 pci_optpr; + u8 res13[8]; + u32 pci_mucr; + u8 res14[8]; + u32 pci_qbar; + u8 res15[12]; + u32 pci_dmamr0; + u32 pci_dmasr0; + u32 pci_dmacdar0; + u8 res16[4]; + u32 pci_dmasar0; + u8 res17[4]; + u32 pci_dmadar0; + u8 res18[4]; + u32 pci_dmabcr0; + u32 pci_dmandar0; + u8 res19[86]; + u32 pci_dmamr1; + u32 pci_dmasr1; + u32 pci_dmacdar1; + u8 res20[4]; + u32 pci_dmasar1; + u8 res21[4]; + u32 pci_dmadar1; + u8 res22[4]; + u32 pci_dmabcr1; + u32 pci_dmandar1; + u8 res23[88]; + u32 pci_dmamr2; + u32 pci_dmasr2; + u32 pci_dmacdar2; + u8 res24[4]; + u32 pci_dmasar2; + u8 res25[4]; + u32 pci_dmadar2; + u8 res26[4]; + u32 pci_dmabcr2; + u32 pci_dmandar2; + u8 res27[88]; + u32 pci_dmamr3; + u32 pci_dmasr3; + u32 pci_dmacdar3; + u8 res28[4]; + u32 pci_dmasar3; + u8 res29[4]; + u32 pci_dmadar3; + u8 res30[4]; + u32 pci_dmabcr3; + u32 pci_dmandar3; + u8 res31[344]; + u32 pci_potar0; + u8 res32[4]; + u32 pci_pobar0; + u8 res33[4]; + u32 pci_pocmr0; + u8 res34[4]; + u32 pci_potar1; + u8 res35[4]; + u32 pci_pobar1; + u8 res36[4]; + u32 pci_pocmr1; + u8 res37[4]; + u32 pci_potar2; + u8 res38[4]; + u32 pci_pobar2; + u8 res39[4]; + u32 pci_pocmr2; + u8 res40[50]; + u32 pci_ptcr; + u32 pci_gpcr; + u32 pci_gcr; + u32 pci_esr; + u32 pci_emr; + u32 pci_ecr; + u32 pci_eacr; + u8 res41[4]; + u32 pci_edcr; + u8 res42[4]; + u32 pci_eccr; + u8 res43[44]; + u32 pci_pitar1; + u8 res44[4]; + u32 pci_pibar1; + u8 res45[4]; + u32 pci_picmr1; + u8 res46[4]; + u32 pci_pitar0; + u8 res47[4]; + u32 pci_pibar0; + u8 res48[4]; + u32 pci_picmr0; + u8 res49[4]; + u32 pci_cfg_addr; + u32 pci_cfg_data; + u32 pci_int_ack; + u8 res50[756]; +} pci_cpm2_t; + +/* Interrupt Controller. +*/ +typedef struct interrupt_controller { + u16 ic_sicr; + u8 res1[2]; + u32 ic_sivec; + u32 ic_sipnrh; + u32 ic_sipnrl; + u32 ic_siprr; + u32 ic_scprrh; + u32 ic_scprrl; + u32 ic_simrh; + u32 ic_simrl; + u32 ic_siexr; + u8 res2[88]; +} intctl_cpm2_t; + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + u32 car_sccr; + u8 res1[4]; + u32 car_scmr; + u8 res2[4]; + u32 car_rsr; + u32 car_rmr; + u8 res[104]; +} car_cpm2_t; + +/* Input/Output Port control/status registers. + * Names consistent with processor manual, although they are different + * from the original 8xx names....... + */ +typedef struct io_port { + u32 iop_pdira; + u32 iop_ppara; + u32 iop_psora; + u32 iop_podra; + u32 iop_pdata; + u8 res1[12]; + u32 iop_pdirb; + u32 iop_pparb; + u32 iop_psorb; + u32 iop_podrb; + u32 iop_pdatb; + u8 res2[12]; + u32 iop_pdirc; + u32 iop_pparc; + u32 iop_psorc; + u32 iop_podrc; + u32 iop_pdatc; + u8 res3[12]; + u32 iop_pdird; + u32 iop_ppard; + u32 iop_psord; + u32 iop_podrd; + u32 iop_pdatd; + u8 res4[12]; +} iop_cpm2_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + u8 cpmt_tgcr1; + u8 res1[3]; + u8 cpmt_tgcr2; + u8 res2[11]; + u16 cpmt_tmr1; + u16 cpmt_tmr2; + u16 cpmt_trr1; + u16 cpmt_trr2; + u16 cpmt_tcr1; + u16 cpmt_tcr2; + u16 cpmt_tcn1; + u16 cpmt_tcn2; + u16 cpmt_tmr3; + u16 cpmt_tmr4; + u16 cpmt_trr3; + u16 cpmt_trr4; + u16 cpmt_tcr3; + u16 cpmt_tcr4; + u16 cpmt_tcn3; + u16 cpmt_tcn4; + u16 cpmt_ter1; + u16 cpmt_ter2; + u16 cpmt_ter3; + u16 cpmt_ter4; + u8 res3[584]; +} cpmtimer_cpm2_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + u8 res0[24]; + u8 sdma_sdsr; + u8 res1[3]; + u8 sdma_sdmr; + u8 res2[3]; + u8 sdma_idsr1; + u8 res3[3]; + u8 sdma_idmr1; + u8 res4[3]; + u8 sdma_idsr2; + u8 res5[3]; + u8 sdma_idmr2; + u8 res6[3]; + u8 sdma_idsr3; + u8 res7[3]; + u8 sdma_idmr3; + u8 res8[3]; + u8 sdma_idsr4; + u8 res9[3]; + u8 sdma_idmr4; + u8 res10[707]; +} sdma_cpm2_t; + +/* Fast controllers +*/ +typedef struct fcc { + u32 fcc_gfmr; + u32 fcc_fpsmr; + u16 fcc_ftodr; + u8 res1[2]; + u16 fcc_fdsr; + u8 res2[2]; + u16 fcc_fcce; + u8 res3[2]; + u16 fcc_fccm; + u8 res4[2]; + u8 fcc_fccs; + u8 res5[3]; + u8 fcc_ftirr_phy[4]; +} fcc_t; + +/* Fast controllers continued + */ +typedef struct fcc_c { + u32 fcc_firper; + u32 fcc_firer; + u32 fcc_firsr_hi; + u32 fcc_firsr_lo; + u8 fcc_gfemr; + u8 res1[15]; +} fcc_c_t; + +/* TC Layer + */ +typedef struct tclayer { + u16 tc_tcmode; + u16 tc_cdsmr; + u16 tc_tcer; + u16 tc_rcc; + u16 tc_tcmr; + u16 tc_fcc; + u16 tc_ccc; + u16 tc_icc; + u16 tc_tcc; + u16 tc_ecc; + u8 res1[12]; +} tclayer_t; + + +/* I2C +*/ +typedef struct i2c { + u8 i2c_i2mod; + u8 res1[3]; + u8 i2c_i2add; + u8 res2[3]; + u8 i2c_i2brg; + u8 res3[3]; + u8 i2c_i2com; + u8 res4[3]; + u8 i2c_i2cer; + u8 res5[3]; + u8 i2c_i2cmr; + u8 res6[331]; +} i2c_cpm2_t; + +typedef struct scc { /* Serial communication channels */ + u32 scc_gsmrl; + u32 scc_gsmrh; + u16 scc_psmr; + u8 res1[2]; + u16 scc_todr; + u16 scc_dsr; + u16 scc_scce; + u8 res2[2]; + u16 scc_sccm; + u8 res3; + u8 scc_sccs; + u8 res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + u8 res1[2]; + u16 smc_smcmr; + u8 res2[2]; + u8 smc_smce; + u8 res3[3]; + u8 smc_smcm; + u8 res4[5]; +} smc_t; + +/* Serial Peripheral Interface. +*/ +typedef struct spi_ctrl { + u16 spi_spmode; + u8 res1[4]; + u8 spi_spie; + u8 res2[3]; + u8 spi_spim; + u8 res3[2]; + u8 spi_spcom; + u8 res4[82]; +} spictl_cpm2_t; + +/* CPM Mux. +*/ +typedef struct cpmux { + u8 cmx_si1cr; + u8 res1; + u8 cmx_si2cr; + u8 res2; + u32 cmx_fcr; + u32 cmx_scr; + u8 cmx_smr; + u8 res3; + u16 cmx_uar; + u8 res4[16]; +} cpmux_t; + +/* SIRAM control +*/ +typedef struct siram { + u16 si_amr; + u16 si_bmr; + u16 si_cmr; + u16 si_dmr; + u8 si_gmr; + u8 res1; + u8 si_cmdr; + u8 res2; + u8 si_str; + u8 res3; + u16 si_rsr; +} siramctl_t; + +typedef struct mcc { + u16 mcc_mcce; + u8 res1[2]; + u16 mcc_mccm; + u8 res2[2]; + u8 mcc_mccf; + u8 res3[7]; +} mcc_t; + +typedef struct comm_proc { + u32 cp_cpcr; + u32 cp_rccr; + u8 res1[14]; + u16 cp_rter; + u8 res2[2]; + u16 cp_rtmr; + u16 cp_rtscr; + u8 res3[2]; + u32 cp_rtsr; + u8 res4[12]; +} cpm_cpm2_t; + +/* USB Controller. +*/ +typedef struct usb_ctlr { + u8 usb_usmod; + u8 usb_usadr; + u8 usb_uscom; + u8 res1[1]; + u16 usb_usep1; + u16 usb_usep2; + u16 usb_usep3; + u16 usb_usep4; + u8 res2[4]; + u16 usb_usber; + u8 res3[2]; + u16 usb_usbmr; + u8 usb_usbs; + u8 res4[7]; +} usb_cpm2_t; + +/* ...and the whole thing wrapped up.... +*/ + +typedef struct immap { + /* Some references are into the unique and known dpram spaces, + * others are from the generic base. + */ +#define im_dprambase im_dpram1 + u8 im_dpram1[16*1024]; + u8 res1[16*1024]; + u8 im_dpram2[4*1024]; + u8 res2[8*1024]; + u8 im_dpram3[4*1024]; + u8 res3[16*1024]; + + sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ + memctl_cpm2_t im_memctl; /* Memory Controller */ + sit_cpm2_t im_sit; /* System Integration Timers */ + pci_cpm2_t im_pci; /* PCI Controller */ + intctl_cpm2_t im_intctl; /* Interrupt Controller */ + car_cpm2_t im_clkrst; /* Clocks and reset */ + iop_cpm2_t im_ioport; /* IO Port control/status */ + cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ + sdma_cpm2_t im_sdma; /* SDMA control/status */ + + fcc_t im_fcc[3]; /* Three FCCs */ + u8 res4z[32]; + fcc_c_t im_fcc_c[3]; /* Continued FCCs */ + + u8 res4[32]; + + tclayer_t im_tclayer[8]; /* Eight TCLayers */ + u16 tc_tcgsr; + u16 tc_tcger; + + /* First set of baud rate generators. + */ + u8 res[236]; + u32 im_brgc5; + u32 im_brgc6; + u32 im_brgc7; + u32 im_brgc8; + + u8 res5[608]; + + i2c_cpm2_t im_i2c; /* I2C control/status */ + cpm_cpm2_t im_cpm; /* Communication processor */ + + /* Second set of baud rate generators. + */ + u32 im_brgc1; + u32 im_brgc2; + u32 im_brgc3; + u32 im_brgc4; + + scc_t im_scc[4]; /* Four SCCs */ + smc_t im_smc[2]; /* Couple of SMCs */ + spictl_cpm2_t im_spi; /* A SPI */ + cpmux_t im_cpmux; /* CPM clock route mux */ + siramctl_t im_siramctl1; /* First SI RAM Control */ + mcc_t im_mcc1; /* First MCC */ + siramctl_t im_siramctl2; /* Second SI RAM Control */ + mcc_t im_mcc2; /* Second MCC */ + usb_cpm2_t im_usb; /* USB Controller */ + + u8 res6[1153]; + + u16 im_si1txram[256]; + u8 res7[512]; + u16 im_si1rxram[256]; + u8 res8[512]; + u16 im_si2txram[256]; + u8 res9[512]; + u16 im_si2rxram[256]; + u8 res10[512]; + u8 res11[4096]; +} cpm2_map_t; + +extern cpm2_map_t *cpm2_immr; + +#endif /* __IMMAP_CPM2__ */ +#endif /* __KERNEL__ */ diff -puN include/asm-powerpc/io.h~git-powerpc include/asm-powerpc/io.h --- a/include/asm-powerpc/io.h~git-powerpc +++ a/include/asm-powerpc/io.h @@ -734,6 +734,32 @@ static inline void * bus_to_virt(unsigne #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) +#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) +#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) + +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single read-modify-write. These + * macros can also be used to set a multiple-bit bit pattern using a mask, + * by specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#ifdef __powerpc64__ +#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) +#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) +#endif + +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_IO_H */ diff -puN include/asm-powerpc/irq.h~git-powerpc include/asm-powerpc/irq.h --- a/include/asm-powerpc/irq.h~git-powerpc +++ a/include/asm-powerpc/irq.h @@ -124,6 +124,9 @@ struct irq_host { struct irq_host_ops *ops; void *host_data; irq_hw_number_t inval_irq; + + /* Optional device node pointer */ + struct device_node *of_node; }; /* The main irq map itself is an array of NR_IRQ entries containing the @@ -142,7 +145,7 @@ extern irq_hw_number_t virq_to_hw(unsign /** * irq_alloc_host - Allocate a new irq_host data structure - * @node: device-tree node of the interrupt controller + * @of_node: optional device-tree node of the interrupt controller * @revmap_type: type of reverse mapping to use * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map * @ops: map/unmap host callbacks @@ -156,7 +159,8 @@ extern irq_hw_number_t virq_to_hw(unsign * later during boot automatically (the reverse mapping will use the slow path * until that happens). */ -extern struct irq_host *irq_alloc_host(unsigned int revmap_type, +extern struct irq_host *irq_alloc_host(struct device_node *of_node, + unsigned int revmap_type, unsigned int revmap_arg, struct irq_host_ops *ops, irq_hw_number_t inval_irq); diff -puN include/asm-powerpc/iseries/lpar_map.h~git-powerpc include/asm-powerpc/iseries/lpar_map.h --- a/include/asm-powerpc/iseries/lpar_map.h~git-powerpc +++ a/include/asm-powerpc/iseries/lpar_map.h @@ -22,6 +22,8 @@ #include +#endif + /* * The iSeries hypervisor will set up mapping for one or more * ESID/VSID pairs (in SLB/segment registers) and will set up @@ -56,6 +58,7 @@ /* Hypervisor initially maps 32MB of the load area */ #define HvPagesToMap 8192 +#ifndef __ASSEMBLY__ struct LparMap { u64 xNumberEsids; // Number of ESID/VSID pairs u64 xNumberRanges; // Number of VA ranges to map diff -puN /dev/null include/asm-powerpc/kgdb.h --- /dev/null +++ a/include/asm-powerpc/kgdb.h @@ -0,0 +1,57 @@ +/* + * kgdb.h: Defines and declarations for serial line source level + * remote debugging of the Linux kernel using gdb. + * + * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu) + * + * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + */ +#ifdef __KERNEL__ +#ifndef _PPC_KGDB_H +#define _PPC_KGDB_H + +#ifndef __ASSEMBLY__ + +/* Things specific to the gen550 backend. */ +struct uart_port; + +extern void gen550_progress(char *, unsigned short); +extern void gen550_kgdb_map_scc(void); +extern void gen550_init(int, struct uart_port *); + +/* Things specific to the pmac backend. */ +extern void zs_kgdb_hook(int tty_num); + +/* To init the kgdb engine. (called by serial hook)*/ +extern void set_debug_traps(void); + +/* To enter the debugger explicitly. */ +extern void breakpoint(void); + +/* For taking exceptions + * these are defined in traps.c + */ +extern int (*debugger)(struct pt_regs *regs); +extern int (*debugger_bpt)(struct pt_regs *regs); +extern int (*debugger_sstep)(struct pt_regs *regs); +extern int (*debugger_iabr_match)(struct pt_regs *regs); +extern int (*debugger_dabr_match)(struct pt_regs *regs); +extern void (*debugger_fault_handler)(struct pt_regs *regs); + +/* What we bring to the party */ +int kgdb_bpt(struct pt_regs *regs); +int kgdb_sstep(struct pt_regs *regs); +void kgdb(struct pt_regs *regs); +int kgdb_iabr_match(struct pt_regs *regs); +int kgdb_dabr_match(struct pt_regs *regs); + +/* + * external low-level support routines (ie macserial.c) + */ +extern void kgdb_interruptible(int); /* control interrupts from serial */ +extern void putDebugChar(char); /* write a single character */ +extern char getDebugChar(void); /* read and return a single char */ + +#endif /* !(__ASSEMBLY__) */ +#endif /* !(_PPC_KGDB_H) */ +#endif /* __KERNEL__ */ diff -puN include/asm-powerpc/lmb.h~git-powerpc include/asm-powerpc/lmb.h --- a/include/asm-powerpc/lmb.h~git-powerpc +++ a/include/asm-powerpc/lmb.h @@ -1,5 +1,5 @@ -#ifndef _PPC64_LMB_H -#define _PPC64_LMB_H +#ifndef _ASM_POWERPC_LMB_H +#define _ASM_POWERPC_LMB_H #ifdef __KERNEL__ /* @@ -77,4 +77,4 @@ lmb_end_pfn(struct lmb_region *type, uns } #endif /* __KERNEL__ */ -#endif /* _PPC64_LMB_H */ +#endif /* _ASM_POWERPC_LMB_H */ diff -puN /dev/null include/asm-powerpc/mmu-40x.h --- /dev/null +++ a/include/asm-powerpc/mmu-40x.h @@ -0,0 +1,65 @@ +#ifndef _ASM_POWERPC_MMU_40X_H_ +#define _ASM_POWERPC_MMU_40X_H_ + +/* + * PPC40x support + */ + +#define PPC40X_TLB_SIZE 64 + +/* + * TLB entries are defined by a "high" tag portion and a "low" data + * portion. On all architectures, the data portion is 32-bits. + * + * TLB entries are managed entirely under software control by reading, + * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx + * instructions. + */ + +#define TLB_LO 1 +#define TLB_HI 0 + +#define TLB_DATA TLB_LO +#define TLB_TAG TLB_HI + +/* Tag portion */ + +#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ +#define TLB_PAGESZ_MASK 0x00000380 +#define TLB_PAGESZ(x) (((x) & 0x7) << 7) +#define PAGESZ_1K 0 +#define PAGESZ_4K 1 +#define PAGESZ_16K 2 +#define PAGESZ_64K 3 +#define PAGESZ_256K 4 +#define PAGESZ_1M 5 +#define PAGESZ_4M 6 +#define PAGESZ_16M 7 +#define TLB_VALID 0x00000040 /* Entry is valid */ + +/* Data portion */ + +#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ +#define TLB_PERM_MASK 0x00000300 +#define TLB_EX 0x00000200 /* Instruction execution allowed */ +#define TLB_WR 0x00000100 /* Writes permitted */ +#define TLB_ZSEL_MASK 0x000000F0 +#define TLB_ZSEL(x) (((x) & 0xF) << 4) +#define TLB_ATTR_MASK 0x0000000F +#define TLB_W 0x00000008 /* Caching is write-through */ +#define TLB_I 0x00000004 /* Caching is inhibited */ +#define TLB_M 0x00000002 /* Memory is coherent */ +#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ + +#ifndef __ASSEMBLY__ + +typedef unsigned long phys_addr_t; + +typedef struct { + unsigned long id; + unsigned long vdso_base; +} mm_context_t; + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_POWERPC_MMU_40X_H_ */ diff -puN include/asm-powerpc/mmu.h~git-powerpc include/asm-powerpc/mmu.h --- a/include/asm-powerpc/mmu.h~git-powerpc +++ a/include/asm-powerpc/mmu.h @@ -8,6 +8,9 @@ #elif defined(CONFIG_PPC_STD_MMU) /* 32-bit classic hash table MMU */ # include +#elif defined(CONFIG_40x) +/* 40x-style software loaded TLB */ +# include #elif defined(CONFIG_44x) /* 44x-style software loaded TLB */ # include diff -puN include/asm-powerpc/mpc52xx.h~git-powerpc include/asm-powerpc/mpc52xx.h --- a/include/asm-powerpc/mpc52xx.h~git-powerpc +++ a/include/asm-powerpc/mpc52xx.h @@ -262,6 +262,16 @@ struct mpc52xx_suspend { extern struct mpc52xx_suspend mpc52xx_suspend; extern int __init mpc52xx_pm_init(void); extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level); + +#ifdef CONFIG_PPC_LITE5200 +extern int __init lite5200_pm_init(void); + +/* lite5200 calls mpc5200 suspend functions, so here they are */ +extern int mpc52xx_pm_prepare(suspend_state_t); +extern int mpc52xx_pm_enter(suspend_state_t); +extern int mpc52xx_pm_finish(suspend_state_t); +extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */ +#endif #endif /* CONFIG_PM */ #endif /* __ASM_POWERPC_MPC52xx_H__ */ diff -puN /dev/null include/asm-powerpc/mpc52xx_psc.h --- /dev/null +++ a/include/asm-powerpc/mpc52xx_psc.h @@ -0,0 +1,191 @@ +/* + * include/asm-ppc/mpc52xx_psc.h + * + * Definitions of consts/structs to drive the Freescale MPC52xx OnChip + * PSCs. Theses are shared between multiple drivers since a PSC can be + * UART, AC97, IR, I2S, ... So this header is in asm-ppc. + * + * + * Maintainer : Sylvain Munaut + * + * Based/Extracted from some header of the 2.4 originally written by + * Dale Farnsworth + * + * Copyright (C) 2004 Sylvain Munaut + * Copyright (C) 2003 MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __ASM_MPC52xx_PSC_H__ +#define __ASM_MPC52xx_PSC_H__ + +#include + +/* Max number of PSCs */ +#define MPC52xx_PSC_MAXNUM 6 + +/* Programmable Serial Controller (PSC) status register bits */ +#define MPC52xx_PSC_SR_CDE 0x0080 +#define MPC52xx_PSC_SR_RXRDY 0x0100 +#define MPC52xx_PSC_SR_RXFULL 0x0200 +#define MPC52xx_PSC_SR_TXRDY 0x0400 +#define MPC52xx_PSC_SR_TXEMP 0x0800 +#define MPC52xx_PSC_SR_OE 0x1000 +#define MPC52xx_PSC_SR_PE 0x2000 +#define MPC52xx_PSC_SR_FE 0x4000 +#define MPC52xx_PSC_SR_RB 0x8000 + +/* PSC Command values */ +#define MPC52xx_PSC_RX_ENABLE 0x0001 +#define MPC52xx_PSC_RX_DISABLE 0x0002 +#define MPC52xx_PSC_TX_ENABLE 0x0004 +#define MPC52xx_PSC_TX_DISABLE 0x0008 +#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010 +#define MPC52xx_PSC_RST_RX 0x0020 +#define MPC52xx_PSC_RST_TX 0x0030 +#define MPC52xx_PSC_RST_ERR_STAT 0x0040 +#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050 +#define MPC52xx_PSC_START_BRK 0x0060 +#define MPC52xx_PSC_STOP_BRK 0x0070 + +/* PSC TxRx FIFO status bits */ +#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040 +#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020 +#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010 +#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008 +#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004 +#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002 +#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 + +/* PSC interrupt mask bits */ +#define MPC52xx_PSC_IMR_TXRDY 0x0100 +#define MPC52xx_PSC_IMR_RXRDY 0x0200 +#define MPC52xx_PSC_IMR_DB 0x0400 +#define MPC52xx_PSC_IMR_IPC 0x8000 + +/* PSC input port change bit */ +#define MPC52xx_PSC_CTS 0x01 +#define MPC52xx_PSC_DCD 0x02 +#define MPC52xx_PSC_D_CTS 0x10 +#define MPC52xx_PSC_D_DCD 0x20 + +/* PSC mode fields */ +#define MPC52xx_PSC_MODE_5_BITS 0x00 +#define MPC52xx_PSC_MODE_6_BITS 0x01 +#define MPC52xx_PSC_MODE_7_BITS 0x02 +#define MPC52xx_PSC_MODE_8_BITS 0x03 +#define MPC52xx_PSC_MODE_BITS_MASK 0x03 +#define MPC52xx_PSC_MODE_PAREVEN 0x00 +#define MPC52xx_PSC_MODE_PARODD 0x04 +#define MPC52xx_PSC_MODE_PARFORCE 0x08 +#define MPC52xx_PSC_MODE_PARNONE 0x10 +#define MPC52xx_PSC_MODE_ERR 0x20 +#define MPC52xx_PSC_MODE_FFULL 0x40 +#define MPC52xx_PSC_MODE_RXRTS 0x80 + +#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 +#define MPC52xx_PSC_MODE_ONE_STOP 0x07 +#define MPC52xx_PSC_MODE_TWO_STOP 0x0f + +#define MPC52xx_PSC_RFNUM_MASK 0x01ff + + +/* Structure of the hardware registers */ +struct mpc52xx_psc { + u8 mode; /* PSC + 0x00 */ + u8 reserved0[3]; + union { /* PSC + 0x04 */ + u16 status; + u16 clock_select; + } sr_csr; +#define mpc52xx_psc_status sr_csr.status +#define mpc52xx_psc_clock_select sr_csr.clock_select + u16 reserved1; + u8 command; /* PSC + 0x08 */ + u8 reserved2[3]; + union { /* PSC + 0x0c */ + u8 buffer_8; + u16 buffer_16; + u32 buffer_32; + } buffer; +#define mpc52xx_psc_buffer_8 buffer.buffer_8 +#define mpc52xx_psc_buffer_16 buffer.buffer_16 +#define mpc52xx_psc_buffer_32 buffer.buffer_32 + union { /* PSC + 0x10 */ + u8 ipcr; + u8 acr; + } ipcr_acr; +#define mpc52xx_psc_ipcr ipcr_acr.ipcr +#define mpc52xx_psc_acr ipcr_acr.acr + u8 reserved3[3]; + union { /* PSC + 0x14 */ + u16 isr; + u16 imr; + } isr_imr; +#define mpc52xx_psc_isr isr_imr.isr +#define mpc52xx_psc_imr isr_imr.imr + u16 reserved4; + u8 ctur; /* PSC + 0x18 */ + u8 reserved5[3]; + u8 ctlr; /* PSC + 0x1c */ + u8 reserved6[3]; + u16 ccr; /* PSC + 0x20 */ + u8 reserved7[14]; + u8 ivr; /* PSC + 0x30 */ + u8 reserved8[3]; + u8 ip; /* PSC + 0x34 */ + u8 reserved9[3]; + u8 op1; /* PSC + 0x38 */ + u8 reserved10[3]; + u8 op0; /* PSC + 0x3c */ + u8 reserved11[3]; + u32 sicr; /* PSC + 0x40 */ + u8 ircr1; /* PSC + 0x44 */ + u8 reserved13[3]; + u8 ircr2; /* PSC + 0x44 */ + u8 reserved14[3]; + u8 irsdr; /* PSC + 0x4c */ + u8 reserved15[3]; + u8 irmdr; /* PSC + 0x50 */ + u8 reserved16[3]; + u8 irfdr; /* PSC + 0x54 */ + u8 reserved17[3]; + u16 rfnum; /* PSC + 0x58 */ + u16 reserved18; + u16 tfnum; /* PSC + 0x5c */ + u16 reserved19; + u32 rfdata; /* PSC + 0x60 */ + u16 rfstat; /* PSC + 0x64 */ + u16 reserved20; + u8 rfcntl; /* PSC + 0x68 */ + u8 reserved21[5]; + u16 rfalarm; /* PSC + 0x6e */ + u16 reserved22; + u16 rfrptr; /* PSC + 0x72 */ + u16 reserved23; + u16 rfwptr; /* PSC + 0x76 */ + u16 reserved24; + u16 rflrfptr; /* PSC + 0x7a */ + u16 reserved25; + u16 rflwfptr; /* PSC + 0x7e */ + u32 tfdata; /* PSC + 0x80 */ + u16 tfstat; /* PSC + 0x84 */ + u16 reserved26; + u8 tfcntl; /* PSC + 0x88 */ + u8 reserved27[5]; + u16 tfalarm; /* PSC + 0x8e */ + u16 reserved28; + u16 tfrptr; /* PSC + 0x92 */ + u16 reserved29; + u16 tfwptr; /* PSC + 0x96 */ + u16 reserved30; + u16 tflrfptr; /* PSC + 0x9a */ + u16 reserved31; + u16 tflwfptr; /* PSC + 0x9e */ +}; + + +#endif /* __ASM_MPC52xx_PSC_H__ */ diff -puN include/asm-powerpc/mpic.h~git-powerpc include/asm-powerpc/mpic.h --- a/include/asm-powerpc/mpic.h~git-powerpc +++ a/include/asm-powerpc/mpic.h @@ -240,9 +240,6 @@ struct mpic_irq_save { /* The instance data of a given MPIC */ struct mpic { - /* The device node of the interrupt controller */ - struct device_node *of_node; - /* The remapper for this MPIC */ struct irq_host *irqhost; @@ -309,6 +306,10 @@ struct mpic unsigned long *hwirq_bitmap; #endif +#ifdef CONFIG_MPIC_BROKEN_REGREAD + u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES]; +#endif + /* link */ struct mpic *next; diff -puN include/asm-powerpc/nvram.h~git-powerpc include/asm-powerpc/nvram.h --- a/include/asm-powerpc/nvram.h~git-powerpc +++ a/include/asm-powerpc/nvram.h @@ -63,8 +63,10 @@ struct nvram_partition { }; -extern int nvram_write_error_log(char * buff, int length, unsigned int err_type); -extern int nvram_read_error_log(char * buff, int length, unsigned int * err_type); +extern int nvram_write_error_log(char * buff, int length, + unsigned int err_type, unsigned int err_seq); +extern int nvram_read_error_log(char * buff, int length, + unsigned int * err_type, unsigned int *err_seq); extern int nvram_clear_error_log(void); extern struct nvram_partition *nvram_find_partition(int sig, const char *name); diff -puN include/asm-powerpc/page_64.h~git-powerpc include/asm-powerpc/page_64.h --- a/include/asm-powerpc/page_64.h~git-powerpc +++ a/include/asm-powerpc/page_64.h @@ -28,7 +28,7 @@ /* Segment size */ #define SID_SHIFT 28 -#define SID_MASK 0xfffffffffUL +#define SID_MASK ASM_CONST(0xfffffffff) #define ESID_MASK 0xfffffffff0000000UL #define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK) @@ -121,6 +121,7 @@ extern unsigned int get_slice_psize(stru extern void slice_init_context(struct mm_struct *mm, unsigned int psize); extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize); +#define slice_mm_new_context(mm) ((mm)->context.id == 0) #define ARCH_HAS_HUGEPAGE_ONLY_RANGE extern int is_hugepage_only_range(struct mm_struct *m, @@ -130,6 +131,12 @@ extern int is_hugepage_only_range(struct #endif /* __ASSEMBLY__ */ #else #define slice_init() +#define slice_set_user_psize(mm, psize) \ +do { \ + (mm)->context.user_psize = (psize); \ + (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \ +} while (0) +#define slice_mm_new_context(mm) 1 #endif /* CONFIG_PPC_MM_SLICES */ #ifdef CONFIG_HUGETLB_PAGE diff -puN include/asm-powerpc/pgtable-4k.h~git-powerpc include/asm-powerpc/pgtable-4k.h --- a/include/asm-powerpc/pgtable-4k.h~git-powerpc +++ a/include/asm-powerpc/pgtable-4k.h @@ -10,10 +10,12 @@ #define PUD_INDEX_SIZE 7 #define PGD_INDEX_SIZE 9 +#ifndef __ASSEMBLY__ #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) #define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) +#endif /* __ASSEMBLY__ */ #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) diff -puN include/asm-powerpc/pgtable-64k.h~git-powerpc include/asm-powerpc/pgtable-64k.h --- a/include/asm-powerpc/pgtable-64k.h~git-powerpc +++ a/include/asm-powerpc/pgtable-64k.h @@ -9,9 +9,11 @@ #define PUD_INDEX_SIZE 0 #define PGD_INDEX_SIZE 4 +#ifndef __ASSEMBLY__ #define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE) #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) +#endif /* __ASSEMBLY__ */ #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) diff -puN include/asm-powerpc/ppc_asm.h~git-powerpc include/asm-powerpc/ppc_asm.h --- a/include/asm-powerpc/ppc_asm.h~git-powerpc +++ a/include/asm-powerpc/ppc_asm.h @@ -155,6 +155,20 @@ name: \ .type GLUE(.,name),@function; \ GLUE(.,name): +#define _INIT_GLOBAL(name) \ + .section ".text.init.refok"; \ + .align 2 ; \ + .globl name; \ + .globl GLUE(.,name); \ + .section ".opd","aw"; \ +name: \ + .quad GLUE(.,name); \ + .quad .TOC.@tocbase; \ + .quad 0; \ + .previous; \ + .type GLUE(.,name),@function; \ +GLUE(.,name): + #define _KPROBE(name) \ .section ".kprobes.text","a"; \ .align 2 ; \ @@ -195,6 +209,10 @@ GLUE(.,name): #else /* 32-bit */ +#define _ENTRY(n) \ + .globl n; \ +n: + #define _GLOBAL(n) \ .text; \ .stabs __stringify(n:F-1),N_FUN,0,0,n;\ diff -puN include/asm-powerpc/prom.h~git-powerpc include/asm-powerpc/prom.h --- a/include/asm-powerpc/prom.h~git-powerpc +++ a/include/asm-powerpc/prom.h @@ -24,7 +24,7 @@ #define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1 #define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1 -#define of_compat_cmp(s1, s2, l) strncasecmp((s1), (s2), (l)) +#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2)) #define of_prop_cmp(s1, s2) strcmp((s1), (s2)) #define of_node_cmp(s1, s2) strcasecmp((s1), (s2)) @@ -145,7 +145,6 @@ extern void of_detach_node(struct device extern void finish_device_tree(void); extern void unflatten_device_tree(void); extern void early_init_devtree(void *); -#define device_is_compatible(d, c) of_device_is_compatible((d), (c)) extern int machine_is_compatible(const char *compat); extern void print_properties(struct device_node *node); extern int prom_n_intr_cells(struct device_node* np); diff -puN include/asm-powerpc/ps3.h~git-powerpc include/asm-powerpc/ps3.h --- a/include/asm-powerpc/ps3.h~git-powerpc +++ a/include/asm-powerpc/ps3.h @@ -229,6 +229,9 @@ enum lv1_result { LV1_INVALID_CLASS_ID = -21, LV1_CONSTRAINT_NOT_SATISFIED = -22, LV1_ALIGNMENT_ERROR = -23, + LV1_HARDWARE_ERROR = -24, + LV1_INVALID_DATA_FORMAT = -25, + LV1_INVALID_OPERATION = -26, LV1_INTERNAL_ERROR = -32768, }; @@ -284,6 +287,12 @@ static inline const char* ps3_result(int return "LV1_CONSTRAINT_NOT_SATISFIED (-22)"; case LV1_ALIGNMENT_ERROR: return "LV1_ALIGNMENT_ERROR (-23)"; + case LV1_HARDWARE_ERROR: + return "LV1_HARDWARE_ERROR (-24)"; + case LV1_INVALID_DATA_FORMAT: + return "LV1_INVALID_DATA_FORMAT (-25)"; + case LV1_INVALID_OPERATION: + return "LV1_INVALID_OPERATION (-26)"; case LV1_INTERNAL_ERROR: return "LV1_INTERNAL_ERROR (-32768)"; default: diff -puN include/asm-powerpc/qe.h~git-powerpc include/asm-powerpc/qe.h --- a/include/asm-powerpc/qe.h~git-powerpc +++ a/include/asm-powerpc/qe.h @@ -32,6 +32,9 @@ extern void qe_reset(void); extern int par_io_init(struct device_node *np); extern int par_io_of_config(struct device_node *np); +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, + int assignment, int has_irq); +extern int par_io_data_set(u8 port, u8 pin, u8 val); /* QE internal API */ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); diff -puN include/asm-powerpc/reg.h~git-powerpc include/asm-powerpc/reg.h --- a/include/asm-powerpc/reg.h~git-powerpc +++ a/include/asm-powerpc/reg.h @@ -102,12 +102,8 @@ #else /* 32-bit */ /* Default MSR for kernel mode. */ #ifndef MSR_KERNEL /* reg_booke.h also defines this */ -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR) -#else #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) #endif -#endif #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) #endif @@ -518,21 +514,47 @@ #define PA6T_MMCR1_ES4 0x0000000000ff0000UL #define PA6T_MMCR1_ES5 0x00000000ff000000UL -#define SPRN_PA6T_SIAR 780 -#define SPRN_PA6T_UPMC0 771 -#define SPRN_PA6T_UPMC1 772 +#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ +#define SPRN_PA6T_UPMC1 772 /* ... */ #define SPRN_PA6T_UPMC2 773 #define SPRN_PA6T_UPMC3 774 #define SPRN_PA6T_UPMC4 775 #define SPRN_PA6T_UPMC5 776 -#define SPRN_PA6T_UMMCR0 779 -#define SPRN_PA6T_UMMCR1 782 -#define SPRN_PA6T_PMC0 787 -#define SPRN_PA6T_PMC1 788 -#define SPRN_PA6T_PMC2 789 -#define SPRN_PA6T_PMC3 790 -#define SPRN_PA6T_PMC4 791 -#define SPRN_PA6T_PMC5 792 +#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ +#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ +#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ +#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ +#define SPRN_PA6T_PMC0 787 +#define SPRN_PA6T_PMC1 788 +#define SPRN_PA6T_PMC2 789 +#define SPRN_PA6T_PMC3 790 +#define SPRN_PA6T_PMC4 791 +#define SPRN_PA6T_PMC5 792 +#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ +#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ +#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ +#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ + +#define SPRN_PA6T_IER 981 /* Icache Error Register */ +#define SPRN_PA6T_DER 982 /* Dcache Error Register */ +#define SPRN_PA6T_BER 862 /* BIU Error Address Register */ +#define SPRN_PA6T_MER 849 /* MMU Error Register */ + +#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ +#define SPRN_PA6T_IMA1 881 /* ... */ +#define SPRN_PA6T_IMA2 882 +#define SPRN_PA6T_IMA3 883 +#define SPRN_PA6T_IMA4 884 +#define SPRN_PA6T_IMA5 885 +#define SPRN_PA6T_IMA6 886 +#define SPRN_PA6T_IMA7 887 +#define SPRN_PA6T_IMA8 888 +#define SPRN_PA6T_IMA9 889 +#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ +#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ +#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ +#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ + #else /* 32-bit */ #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ diff -puN include/asm-powerpc/spu.h~git-powerpc include/asm-powerpc/spu.h --- a/include/asm-powerpc/spu.h~git-powerpc +++ a/include/asm-powerpc/spu.h @@ -238,19 +238,14 @@ extern long spu_sys_callback(struct spu_ /* syscalls implemented in spufs */ struct file; -extern struct spufs_calls { - asmlinkage long (*create_thread)(const char __user *name, +struct spufs_calls { + long (*create_thread)(const char __user *name, unsigned int flags, mode_t mode, struct file *neighbor); - asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc, + long (*spu_run)(struct file *filp, __u32 __user *unpc, __u32 __user *ustatus); - struct module *owner; -} spufs_calls; - -/* coredump calls implemented in spufs */ -struct spu_coredump_calls { - asmlinkage int (*arch_notes_size)(void); - asmlinkage void (*arch_write_notes)(struct file *file); + int (*coredump_extra_notes_size)(void); + int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset); struct module *owner; }; @@ -274,21 +269,8 @@ struct spu_coredump_calls { #define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */ -#ifdef CONFIG_SPU_FS_MODULE int register_spu_syscalls(struct spufs_calls *calls); void unregister_spu_syscalls(struct spufs_calls *calls); -#else -static inline int register_spu_syscalls(struct spufs_calls *calls) -{ - return 0; -} -static inline void unregister_spu_syscalls(struct spufs_calls *calls) -{ -} -#endif /* MODULE */ - -int register_arch_coredump_calls(struct spu_coredump_calls *calls); -void unregister_arch_coredump_calls(struct spu_coredump_calls *calls); int spu_add_sysdev_attr(struct sysdev_attribute *attr); void spu_remove_sysdev_attr(struct sysdev_attribute *attr); diff -puN include/asm-powerpc/system.h~git-powerpc include/asm-powerpc/system.h --- a/include/asm-powerpc/system.h~git-powerpc +++ a/include/asm-powerpc/system.h @@ -189,6 +189,8 @@ extern int mem_init_done; /* set on boot extern unsigned long memory_limit; extern unsigned long klimit; +extern void *alloc_maybe_bootmem(size_t size, gfp_t mask); + extern int powersave_nap; /* set if nap mode can be used in idle loop */ /* diff -puN include/asm-powerpc/time.h~git-powerpc include/asm-powerpc/time.h --- a/include/asm-powerpc/time.h~git-powerpc +++ a/include/asm-powerpc/time.h @@ -179,7 +179,7 @@ static inline unsigned int get_dec(void) static inline void set_dec(int val) { #if defined(CONFIG_40x) - return; /* Have to let it auto-reload */ + mtspr(SPRN_PIT, val); #elif defined(CONFIG_8xx_CPU6) set_dec_cpu6(val); #else diff -puN include/asm-ppc/amigahw.h~git-powerpc /dev/null --- a/include/asm-ppc/amigahw.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifdef __KERNEL__ -#ifndef __ASMPPC_AMIGAHW_H -#define __ASMPPC_AMIGAHW_H - -#include - -#undef CHIP_PHYSADDR -#ifdef CONFIG_APUS_FAST_EXCEPT -#define CHIP_PHYSADDR (0x000000) -#else -#define CHIP_PHYSADDR (0x004000) -#endif - - -#endif /* __ASMPPC_AMIGAHW_H */ -#endif /* __KERNEL__ */ diff -puN include/asm-ppc/amigaints.h~git-powerpc /dev/null --- a/include/asm-ppc/amigaints.h +++ /dev/null @@ -1,133 +0,0 @@ -/* -** amigaints.h -- Amiga Linux interrupt handling structs and prototypes -** -** Copyright 1992 by Greg Harp -** -** This file is subject to the terms and conditions of the GNU General Public -** License. See the file COPYING in the main directory of this archive -** for more details. -** -** Created 10/2/92 by Greg Harp -*/ - -#ifdef __KERNEL__ -#ifndef _ASMm68k_AMIGAINTS_H_ -#define _ASMm68k_AMIGAINTS_H_ - -/* -** Amiga Interrupt sources. -** -*/ - -#define AUTO_IRQS (8) -#define AMI_STD_IRQS (14) -#define CIA_IRQS (5) -#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */ - -/* vertical blanking interrupt */ -#define IRQ_AMIGA_VERTB 0 - -/* copper interrupt */ -#define IRQ_AMIGA_COPPER 1 - -/* Audio interrupts */ -#define IRQ_AMIGA_AUD0 2 -#define IRQ_AMIGA_AUD1 3 -#define IRQ_AMIGA_AUD2 4 -#define IRQ_AMIGA_AUD3 5 - -/* Blitter done interrupt */ -#define IRQ_AMIGA_BLIT 6 - -/* floppy disk interrupts */ -#define IRQ_AMIGA_DSKSYN 7 -#define IRQ_AMIGA_DSKBLK 8 - -/* builtin serial port interrupts */ -#define IRQ_AMIGA_RBF 9 -#define IRQ_AMIGA_TBE 10 - -/* software interrupts */ -#define IRQ_AMIGA_SOFT 11 - -/* interrupts from external hardware */ -#define IRQ_AMIGA_PORTS 12 -#define IRQ_AMIGA_EXTER 13 - -/* CIA interrupt sources */ -#define IRQ_AMIGA_CIAA 14 -#define IRQ_AMIGA_CIAA_TA 14 -#define IRQ_AMIGA_CIAA_TB 15 -#define IRQ_AMIGA_CIAA_ALRM 16 -#define IRQ_AMIGA_CIAA_SP 17 -#define IRQ_AMIGA_CIAA_FLG 18 -#define IRQ_AMIGA_CIAB 19 -#define IRQ_AMIGA_CIAB_TA 19 -#define IRQ_AMIGA_CIAB_TB 20 -#define IRQ_AMIGA_CIAB_ALRM 21 -#define IRQ_AMIGA_CIAB_SP 22 -#define IRQ_AMIGA_CIAB_FLG 23 - -/* auto-vector interrupts */ -#define IRQ_AMIGA_AUTO 24 -#define IRQ_AMIGA_AUTO_0 24 /* This is just a dummy */ -#define IRQ_AMIGA_AUTO_1 25 -#define IRQ_AMIGA_AUTO_2 26 -#define IRQ_AMIGA_AUTO_3 27 -#define IRQ_AMIGA_AUTO_4 28 -#define IRQ_AMIGA_AUTO_5 29 -#define IRQ_AMIGA_AUTO_6 30 -#define IRQ_AMIGA_AUTO_7 31 - -#define IRQ_FLOPPY IRQ_AMIGA_DSKBLK - -/* INTREQR masks */ -#define IRQ1_MASK 0x0007 /* INTREQR mask for IRQ 1 */ -#define IRQ2_MASK 0x0008 /* INTREQR mask for IRQ 2 */ -#define IRQ3_MASK 0x0070 /* INTREQR mask for IRQ 3 */ -#define IRQ4_MASK 0x0780 /* INTREQR mask for IRQ 4 */ -#define IRQ5_MASK 0x1800 /* INTREQR mask for IRQ 5 */ -#define IRQ6_MASK 0x2000 /* INTREQR mask for IRQ 6 */ -#define IRQ7_MASK 0x4000 /* INTREQR mask for IRQ 7 */ - -#define IF_SETCLR 0x8000 /* set/clr bit */ -#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */ -#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */ -#define IF_DSKSYN 0x1000 /* disk sync interrupt */ -#define IF_RBF 0x0800 /* serial receive buffer full interrupt */ -#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */ -#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */ -#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */ -#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */ -#define IF_BLIT 0x0040 /* blitter done interrupt */ -#define IF_VERTB 0x0020 /* vertical blanking interrupt */ -#define IF_COPER 0x0010 /* copper interrupt */ -#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */ -#define IF_SOFT 0x0004 /* software initiated interrupt */ -#define IF_DSKBLK 0x0002 /* diskblock DMA finished */ -#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */ - -extern void amiga_do_irq(int irq, struct pt_regs *fp); -extern void amiga_do_irq_list(int irq, struct pt_regs *fp); - -/* CIA interrupt control register bits */ - -#define CIA_ICR_TA 0x01 -#define CIA_ICR_TB 0x02 -#define CIA_ICR_ALRM 0x04 -#define CIA_ICR_SP 0x08 -#define CIA_ICR_FLG 0x10 -#define CIA_ICR_ALL 0x1f -#define CIA_ICR_SETCLR 0x80 - -/* to access the interrupt control registers of CIA's use only -** these functions, they behave exactly like the amiga os routines -*/ - -extern struct ciabase ciaa_base, ciab_base; - -extern unsigned char cia_set_irq(unsigned int irq, int set); -extern unsigned char cia_able_irq(unsigned int irq, int enable); - -#endif /* asm-m68k/amigaints.h */ -#endif /* __KERNEL__ */ diff -puN include/asm-ppc/amigappc.h~git-powerpc /dev/null --- a/include/asm-ppc/amigappc.h +++ /dev/null @@ -1,85 +0,0 @@ -/* -** asm-ppc/amigappc.h -- This header defines some values and pointers for -** the Phase 5 PowerUp card. -** -** Copyright 1997, 1998 by Phase5, Germany. -** -** This file is subject to the terms and conditions of the GNU General Public -** License. See the file COPYING in the main directory of this archive -** for more details. -** -** Created: 7/22/97 by Jesper Skov -*/ - -#ifdef __KERNEL__ -#ifndef _M68K_AMIGAPPC_H -#define _M68K_AMIGAPPC_H - -#ifndef __ASSEMBLY__ - -/* #include */ -#define mb() __asm__ __volatile__ ("sync" : : : "memory") - -#define APUS_WRITE(_a_, _v_) \ -do { \ - (*((volatile unsigned char *)(_a_)) = (_v_)); \ - mb(); \ -} while (0) - -#define APUS_READ(_a_, _v_) \ -do { \ - (_v_) = (*((volatile unsigned char *)(_a_))); \ - mb(); \ -} while (0) -#endif /* ndef __ASSEMBLY__ */ - -/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */ -#define zTwoBase (0x80000000) - -#define APUS_IPL_BASE (zTwoBase + 0x00f60000) -#define APUS_REG_RESET (APUS_IPL_BASE + 0x00) -#define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10) -#define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18) -#define APUS_REG_LOCK (APUS_IPL_BASE + 0x20) -#define APUS_REG_INT (APUS_IPL_BASE + 0x28) -#define APUS_IPL_EMU (APUS_IPL_BASE + 0x30) -#define APUS_INT_LVL (APUS_IPL_BASE + 0x38) - -#define REGSHADOW_SETRESET (0x80) -#define REGSHADOW_SELFRESET (0x40) - -#define REGLOCK_SETRESET (0x80) -#define REGLOCK_BLACKMAGICK1 (0x40) -#define REGLOCK_BLACKMAGICK2 (0x20) -#define REGLOCK_BLACKMAGICK3 (0x10) - -#define REGWAITSTATE_SETRESET (0x80) -#define REGWAITSTATE_PPCW (0x08) -#define REGWAITSTATE_PPCR (0x04) - -#define REGRESET_SETRESET (0x80) -#define REGRESET_PPCRESET (0x10) -#define REGRESET_M68KRESET (0x08) -#define REGRESET_AMIGARESET (0x04) -#define REGRESET_AUXRESET (0x02) -#define REGRESET_SCSIRESET (0x01) - -#define REGINT_SETRESET (0x80) -#define REGINT_ENABLEIPL (0x02) -#define REGINT_INTMASTER (0x01) - -#define IPLEMU_SETRESET (0x80) -#define IPLEMU_DISABLEINT (0x40) -#define IPLEMU_IPL2 (0x20) -#define IPLEMU_IPL1 (0x10) -#define IPLEMU_IPL0 (0x08) -#define IPLEMU_PPCIPL2 (0x04) -#define IPLEMU_PPCIPL1 (0x02) -#define IPLEMU_PPCIPL0 (0x01) -#define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0) - -#define INTLVL_SETRESET (0x80) -#define INTLVL_MASK (0x7f) - -#endif /* _M68k_AMIGAPPC_H */ -#endif /* __KERNEL__ */ diff -puN include/asm-ppc/ans-lcd.h~git-powerpc /dev/null --- a/include/asm-ppc/ans-lcd.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _PPC_ANS_LCD_H -#define _PPC_ANS_LCD_H - -#define ANSLCD_MINOR 156 - -#define ANSLCD_CLEAR 0x01 -#define ANSLCD_SENDCTRL 0x02 -#define ANSLCD_SETSHORTDELAY 0x03 -#define ANSLCD_SETLONGDELAY 0x04 - -#endif diff -puN include/asm-ppc/bootinfo.h~git-powerpc include/asm-ppc/bootinfo.h --- a/include/asm-ppc/bootinfo.h~git-powerpc +++ a/include/asm-ppc/bootinfo.h @@ -11,10 +11,6 @@ #include -#if defined(CONFIG_APUS) && !defined(__BOOTER__) -#include -#else - struct bi_record { unsigned long tag; /* tag ID */ unsigned long size; /* size of record (in bytes) */ @@ -44,7 +40,6 @@ bootinfo_addr(unsigned long offset) return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1, (1 << 20)); } -#endif /* CONFIG_APUS */ #endif /* _PPC_BOOTINFO_H */ diff -puN include/asm-ppc/io.h~git-powerpc include/asm-ppc/io.h --- a/include/asm-ppc/io.h~git-powerpc +++ a/include/asm-ppc/io.h @@ -30,7 +30,7 @@ #include #elif defined(CONFIG_8260) #include -#elif defined(CONFIG_APUS) || !defined(CONFIG_PCI) +#elif !defined(CONFIG_PCI) #define _IO_BASE 0 #define _ISA_MEM_BASE 0 #define PCI_DRAM_OFFSET 0 @@ -145,24 +145,7 @@ static inline void writeb(__u8 b, volati } #endif -#if defined(CONFIG_APUS) -static inline __u16 readw(const volatile void __iomem *addr) -{ - return *(__force volatile __u16 *)(addr); -} -static inline __u32 readl(const volatile void __iomem *addr) -{ - return *(__force volatile __u32 *)(addr); -} -static inline void writew(__u16 b, volatile void __iomem *addr) -{ - *(__force volatile __u16 *)(addr) = b; -} -static inline void writel(__u32 b, volatile void __iomem *addr) -{ - *(__force volatile __u32 *)(addr) = b; -} -#elif defined (CONFIG_8260_PCI9) +#if defined (CONFIG_8260_PCI9) /* Use macros if PCI9 workaround enabled */ #define readw(addr) in_le16((volatile u16 *)(addr)) #define readl(addr) in_le32((volatile u32 *)(addr)) @@ -185,7 +168,7 @@ static inline void writel(__u32 b, volat { out_le32(addr, b); } -#endif /* CONFIG_APUS */ +#endif /* CONFIG_8260_PCI9 */ #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) @@ -300,13 +283,7 @@ extern __inline__ void name(unsigned int } __do_out_asm(outb, "stbx") -#ifdef CONFIG_APUS -__do_in_asm(inb, "lbzx") -__do_in_asm(inw, "lhz%U1%X1") -__do_in_asm(inl, "lwz%U1%X1") -__do_out_asm(outl,"stw%U0%X0") -__do_out_asm(outw, "sth%U0%X0") -#elif defined (CONFIG_8260_PCI9) +#if defined (CONFIG_8260_PCI9) /* in asm cannot be defined if PCI9 workaround is used */ #define inb(port) in_8((port)+___IO_BASE) #define inw(port) in_le16((port)+___IO_BASE) @@ -371,7 +348,6 @@ extern void __iomem *ioremap64(unsigned #define ioremap_nocache(addr, size) ioremap((addr), (size)) extern void iounmap(volatile void __iomem *addr); extern unsigned long iopa(unsigned long addr); -extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; extern void io_block_mapping(unsigned long virt, phys_addr_t phys, unsigned int size, int flags); @@ -384,24 +360,16 @@ extern void io_block_mapping(unsigned lo */ extern inline unsigned long virt_to_bus(volatile void * address) { -#ifndef CONFIG_APUS if (address == (void *)0) return 0; return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET; -#else - return iopa ((unsigned long) address); -#endif } extern inline void * bus_to_virt(unsigned long address) { -#ifndef CONFIG_APUS if (address == 0) return NULL; return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE); -#else - return (void*) mm_ptov (address); -#endif } /* @@ -410,20 +378,12 @@ extern inline void * bus_to_virt(unsigne */ extern inline unsigned long virt_to_phys(volatile void * address) { -#ifndef CONFIG_APUS return (unsigned long) address - KERNELBASE; -#else - return iopa ((unsigned long) address); -#endif } extern inline void * phys_to_virt(unsigned long address) { -#ifndef CONFIG_APUS return (void *) (address + KERNELBASE); -#else - return (void*) mm_ptov (address); -#endif } /* @@ -553,4 +513,7 @@ extern void pci_iounmap(struct pci_dev * #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) +#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) +#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) + #endif /* __KERNEL__ */ diff -puN include/asm-ppc/machdep.h~git-powerpc include/asm-ppc/machdep.h --- a/include/asm-ppc/machdep.h~git-powerpc +++ a/include/asm-ppc/machdep.h @@ -8,10 +8,6 @@ #include #include -#ifdef CONFIG_APUS -#include -#endif - struct pt_regs; struct pci_bus; struct pci_dev; diff -puN include/asm-ppc/page.h~git-powerpc include/asm-ppc/page.h --- a/include/asm-ppc/page.h~git-powerpc +++ a/include/asm-ppc/page.h @@ -97,62 +97,22 @@ extern void clear_user_page(void *page, extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *pg); -#ifndef CONFIG_APUS #define PPC_MEMSTART 0 -#define PPC_PGSTART 0 #define PPC_MEMOFFSET PAGE_OFFSET -#else -extern unsigned long ppc_memstart; -extern unsigned long ppc_pgstart; -extern unsigned long ppc_memoffset; -#define PPC_MEMSTART ppc_memstart -#define PPC_PGSTART ppc_pgstart -#define PPC_MEMOFFSET ppc_memoffset -#endif - -#if defined(CONFIG_APUS) && !defined(MODULE) -/* map phys->virtual and virtual->phys for RAM pages */ -static inline unsigned long ___pa(unsigned long v) -{ - unsigned long p; - asm volatile ("1: addis %0, %1, %2;" - ".section \".vtop_fixup\",\"aw\";" - ".align 1;" - ".long 1b;" - ".previous;" - : "=r" (p) - : "b" (v), "K" (((-PAGE_OFFSET) >> 16) & 0xffff)); - return p; -} -static inline void* ___va(unsigned long p) -{ - unsigned long v; - asm volatile ("1: addis %0, %1, %2;" - ".section \".ptov_fixup\",\"aw\";" - ".align 1;" - ".long 1b;" - ".previous;" - : "=r" (v) - : "b" (p), "K" (((PAGE_OFFSET) >> 16) & 0xffff)); - - return (void*) v; -} -#else #define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) #define ___va(paddr) ((paddr)+PPC_MEMOFFSET) -#endif extern int page_is_ram(unsigned long pfn); #define __pa(x) ___pa((unsigned long)(x)) #define __va(x) ((void *)(___va((unsigned long)(x)))) -#define ARCH_PFN_OFFSET (PPC_PGSTART) +#define ARCH_PFN_OFFSET 0 #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT) -#define pfn_valid(pfn) (((pfn) - PPC_PGSTART) < max_mapnr) +#define pfn_valid(pfn) ((pfn) < max_mapnr) #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) /* Pure 2^n version of get_order */ diff -puN include/asm-ppc/pgtable.h~git-powerpc include/asm-ppc/pgtable.h --- a/include/asm-ppc/pgtable.h~git-powerpc +++ a/include/asm-ppc/pgtable.h @@ -765,14 +765,6 @@ extern void paging_init(void); #define pte_to_pgoff(pte) (pte_val(pte) >> 3) #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) -/* CONFIG_APUS */ -/* For virtual address to physical address conversion */ -extern void cache_clear(__u32 addr, int length); -extern void cache_push(__u32 addr, int length); -extern int mm_end_of_chunk (unsigned long addr, int len); -extern unsigned long iopa(unsigned long addr); -extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; - /* Values for nocacheflag and cmode */ /* These are not used by the APUS kernel_map, but prevents compilation errors. */ diff -puN include/asm-ppc/prom.h~git-powerpc include/asm-ppc/prom.h --- a/include/asm-ppc/prom.h~git-powerpc +++ a/include/asm-ppc/prom.h @@ -35,7 +35,6 @@ extern unsigned long sub_reloc_offset(un #define machine_is_compatible(x) 0 #define of_find_compatible_node(f, t, c) NULL #define of_get_property(p, n, l) NULL -#define get_property(a, b, c) of_get_property((a), (b), (c)) #endif /* _PPC_PROM_H */ #endif /* __KERNEL__ */ diff -puN include/linux/elf.h~git-powerpc include/linux/elf.h --- a/include/linux/elf.h~git-powerpc +++ a/include/linux/elf.h @@ -389,12 +389,14 @@ extern Elf64_Dyn _DYNAMIC []; #endif +/* Optional callbacks to write extra ELF notes. */ #ifndef ARCH_HAVE_EXTRA_ELF_NOTES -static inline int arch_notes_size(void) { return 0; } -static inline void arch_write_notes(struct file *file) { } - -#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size() -#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file) -#endif /* ARCH_HAVE_EXTRA_ELF_NOTES */ +static inline int elf_coredump_extra_notes_size(void) { return 0; } +static inline int elf_coredump_extra_notes_write(struct file *file, + loff_t *foffset) { return 0; } +#else +extern int elf_coredump_extra_notes_size(void); +extern int elf_coredump_extra_notes_write(struct file *file, loff_t *foffset); +#endif #endif /* _LINUX_ELF_H */ diff -puN include/linux/of.h~git-powerpc include/linux/of.h --- a/include/linux/of.h~git-powerpc +++ a/include/linux/of.h @@ -54,7 +54,6 @@ extern int of_device_is_compatible(const extern const void *of_get_property(const struct device_node *node, const char *name, int *lenp); -#define get_property(a, b, c) of_get_property((a), (b), (c)) extern int of_n_addr_cells(struct device_node *np); extern int of_n_size_cells(struct device_node *np); diff -puN include/linux/pci_ids.h~git-powerpc include/linux/pci_ids.h --- a/include/linux/pci_ids.h~git-powerpc +++ a/include/linux/pci_ids.h @@ -2101,6 +2101,8 @@ #define PCI_DEVICE_ID_MPC8533 0x0031 #define PCI_DEVICE_ID_MPC8544E 0x0032 #define PCI_DEVICE_ID_MPC8544 0x0033 +#define PCI_DEVICE_ID_MPC8572E 0x0040 +#define PCI_DEVICE_ID_MPC8572 0x0041 #define PCI_DEVICE_ID_MPC8641 0x7010 #define PCI_DEVICE_ID_MPC8641D 0x7011 _