GIT b4348bb08dfc34acda8c50603abce43ce0c80129 git+ssh://master.kernel.org/home/rmk/linux-2.6-arm.git#devel commit 128df8ee51ea3dad3019db67243b8cff14b7d15f Author: Russell King Date: Mon Jan 14 22:30:10 2008 +0000 [NET] smc91x: Make smc91x use IRQ resource trigger flags smc91x is shared between many different platforms. Each platform needs to specify the interrupt type, and in some cases the irq type depends on more than just the build configuration - it depends on runtime checks. Rather than throwing this code into the SMC_IRQ_FLAGS definition, provide a way for these flags to be passed via the IRQ resource itself. Note that IRQF_TRIGGER_* constants are intentionally defined to correspond with the IORESOURCE_IRQ_* interrupt type flags, in much the same way that the low bits of PCI iomem resources correspond with the BAR flag bits. Also provide a way to configure smc91x to read the IRQ flags from the resource. Once all platforms have been converted over (signified by all definitions of SMC_IRQ_FLAGS being -1) SMC_IRQ_FLAGS should be removed. Signed-off-by: Russell King Acked-by: Nicolas Pitre Acked-by: Jeff Garzik commit e1debe84103586ef1a4a747447a474d4e739c827 Author: eric miao Date: Fri Dec 21 11:18:48 2007 +0800 [ARM] pxa: add default config for littleton default to - PXA300/PXA310 support only (there isn't any littleton board with PXA320 processor for now) - smc91x ethernet support with NFS rootfs - LCD framebuffer support with graphics console Signed-off-by: eric miao Signed-off-by: Russell King commit 9c12378d3094df38880be99fcdb0f5f4f47b2b01 Author: eric miao Date: Thu Dec 13 10:41:43 2007 +0800 [ARM] pxa: add basic support for Littleton (PXA3xx Form Factor Platform) Signed-off-by: eric miao Signed-off-by: Russell King commit 4bea4af2c4605c9034edfead76ff10113e02fb04 Author: Philipp Zabel Date: Thu Nov 22 17:59:11 2007 +0100 [ARM] 4664/1: Add basic support for HTC Magician PDA phones This includes irda, gpio keys, pxafb, backlight, ohci and flash (read-only). Signed-off-by: Philipp Zabel Signed-off-by: Russell King commit 857608d2aaeccc5215d83ce14e2642b1401ef87b Author: Ian Molton Date: Mon Nov 19 13:16:56 2007 +0100 [ARM] 4649/1: Base support for pxa-based Toshiba e-series PDAs. This patch contains the base code to boot the Toshiba e330, e740, e750, e400, and e800 PDAs. Signed-off-by: Ian Molton Signed-off-by: Russell King commit a74a443ce2beef13823b306bee851c9dc5a05109 Author: Russell King Date: Mon Jan 7 22:18:30 2008 +0000 [ARM] pxa: Add PXA3 standby code hooked into the IRQ wake scheme Wakeup sources on PXA3 are enabled at two levels. First, the MFP configuration has to be set to enable which edges a specific pin will trigger a wakeup. The pin also has to be routed to a functional unit. Lastly, the functional unit must be enabled as a wakeup source in the appropriate AD*ER registers (AD2D0ER for standby resume.) This doesn't fit well with the IRQ wake scheme - we currently do a best effort conversion from IRQ numbers to functional unit wake enable bits. For instance, there's several USB client related enable bits but there's no corresponding IRQs to determine which you'd want. Conversely, there's a single enable bit covering several functional units. Signed-off-by: Russell King commit 7b76f3815d8b919630dddffcd769c601e51283dc Author: Russell King Date: Tue Jan 8 15:25:01 2008 +0000 [ARM] pxa: Add zylonite MFP wakeup configurations Signed-off-by: Russell King commit 32e275d2109b7ae994036e41312058d4c64ce10c Author: Russell King Date: Tue Jan 8 15:12:22 2008 +0000 [ARM] pxa: program MFPs for low power mode when suspending Hook the MFP code into the power management code so that the MFPs can be reconfigured when suspending and resuming. However, note the FIXME - low power mode MFP configuration may depend on the system state being entered. Also note that we have to clear any detected edge events prior to entering a low power mode - otherwise we immediately wake up. Signed-off-by: Russell King commit de4986ad292b88fd628a0cc53b9622d3d6db653e Author: eric miao Date: Thu Jan 3 11:25:56 2008 +0800 [ARM] pxa: make MFP configuration processor independent There are two reasons for making the MFP configuration to be processor independent, i.e. removing the relationship of configuration bits with actual MFPR register settings: 1. power management sometimes requires the MFP to be configured differently when in run mode or in low power mode 2. for future integration of pxa{25x,27x} GPIO configurations The modifications include: 1. introducing of processor independent MFP configuration bits, as defined in [include/asm-arm/arch-pxa/mfp.h]: bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) bit 10..12 - Alternate Function Selection bit 13..15 - Drive Strength bit 16..18 - Low Power Mode State bit 19..20 - Low Power Mode Edge Detection bit 21..22 - Run Mode Pull State and so on, 2. moving the processor dependent code from mfp.h into mfp-pxa3xx.h 3. cleaning up of the MFPR bit definitions 4. mapping of processor independent MFP configuration into processor specific MFPR register settings is now totally encapsulated within pxa3xx_mfp_config() 5. using of "unsigned long" instead of invented type of "mfp_cfg_t" according to Documentation/CodingStyle Chapter 5, usage of this in platform code will be slowly removed in later patches Signed-off-by: eric miao Signed-off-by: Russell King commit ffc52aa647db7884f566492da9ad1926f81c23b1 Author: eric miao Date: Wed Jan 2 17:34:27 2008 +0800 [ARM] pxa: remove un-used pxa3xx_mfp_set_xxx() functions pxa3xx_mfp_set_xxx() functions are originally provided for overwriting MFP configurations performed by pxa3xx_mfp_config(), the usage of such a dirtry trick is not recommended, since there is currently no user of these functions, they are safely removed Signed-off-by: eric miao Signed-off-by: Russell King commit 102fb54f43070f31e7e302338a5ca8757ae4540a Author: eric miao Date: Wed Jan 2 16:45:06 2008 +0800 [ARM] pxa: introduce a new file mfp-pxa3xx.h for common pin configurations Signed-off-by: eric miao Signed-off-by: Russell King commit 124f39b2aef4bc58136ffb53e1e118fc1c213bc2 Author: Russell King Date: Fri Jan 4 22:43:36 2008 +0000 [ARM] pxa: omit PXA25x or PXA27x standby/sleep code as appropriate There's no point building standby/sleep code for processors which aren't configured. Signed-off-by: Russell King commit 5b689d0c0248eaba07a3d0cd1d0a360aeee43f5f Author: eric miao Date: Wed Jan 2 08:24:49 2008 +0800 [ARM] pxa: clean up pxa{27x,25x}_init_pm() to empty if CONFIG_PM not defined Signed-off-by: eric miao Signed-off-by: Russell King commit 57abc0e0c66ce49acd200dd0a1a0379a6d1cbc1f Author: Russell King Date: Mon Jan 14 17:02:33 2008 +0000 [ARM] pxa: move memory controller registers into pxa2xx-regs.h PXA3 has a different memory controller from PXA2 platforms. Avoid clashing definitions by moving the PXA2 definitions to pxa2xx-regs.h Signed-off-by: Russell King commit 44344ee6f9d4f04ba82cb21e956960c5f5f042f0 Author: Catalin Marinas Date: Wed Dec 12 15:41:36 2007 +0100 [ARM] 4705/1: RealView: Change the REALVIEW_MPCORE configuration option This patch changes the REALVIEW_MPCORE configuration option to REALVIEW_EB_ARM11MP since this is only specific to RealView/EB. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 21389e4ff4156acd31ba0f1b09abab8510199bfd Author: Catalin Marinas Date: Wed Dec 12 15:41:30 2007 +0100 [ARM] 4704/1: RealView: Remove the platform dependencies from localtimer.c This patch removes the TWD_BASE macro used to set up and configure the local timers on ARM11MPCore. The twd_base_addr and twd_size variables are defined in localtimer.c and set from the realview_eb_init function. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit f3e2e913c8fe79b8daf7cf47edbe16ad0cc869cf Author: Catalin Marinas Date: Wed Dec 12 15:41:24 2007 +0100 [ARM] 4703/1: RealView: Select the timer IRQ at run-time This patch sets the timer IRQ at run-time by moving the sys_timer structure and the timer_init function to the realview_eb.c file. This allows multiple RealView platforms to be compiled in the same kernel image. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 6c604d336d8c6858995aa578626632dd6101733c Author: Catalin Marinas Date: Wed Dec 12 15:41:18 2007 +0100 [ARM] 4702/1: RealView: Fix entry-macro.S to work with multiple platforms This patch modifies the get_irqnr_preamble macro to work with multiple platforms at run-time by reading the address of the GIC controller from the gic_cpu_base_addr variable. This variable is defined in core.c and intialised in realview_eb.c (gic_init_irq). Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 8bf6cde003e2cc449673d0b346a46a65a4270036 Author: Catalin Marinas Date: Wed Dec 12 15:41:12 2007 +0100 [ARM] 4701/1: RealView: Add core-tile detection This patch adds the core-tile detection and only enables devices if the corresponding tile is present. It currently detects the ARM11MPCore via the core_tile_eb11mp() macro. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 20d29f73a749e7333769d0f1bf2a74a9b99edc0e Author: Catalin Marinas Date: Wed Dec 12 15:41:06 2007 +0100 [ARM] 4699/1: RealView: Move the AMBA resource definitions to realview_eb.c This patch moves the IRQ and DMA definitions from core.h into realview_eb.c since they are platform-specific. It adds a realview_eb11mp_fixup function to adjust the IRQ numbers if the ARM11MPCore tile is fitted. The realview_smc91x_device is also moved from core.c into realview_eb.c. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 00dd83ec1fcfe86f46b65586a830bc74246e4c69 Author: Catalin Marinas Date: Wed Dec 12 15:41:00 2007 +0100 [ARM] 4700/1: RealView: Move the platform-specific definitions into board-eb.h This patch moves the platform specific definitions from platform.h into the board-eb.h file. It drops the INT_* definitions as they are no longer used in irqs.h (moved to board-eb.h). It renames REALVIEW_* macros to REALVIEW_EB_* or REALVIEW_EB11MP_* to distinguish between standard EB and EB + the ARM11MPCore tile. The platform.h file contains common definitions to the RealView platforms and it is only directly included in board-*.h files. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 4bb136f8fea8efc1974b35fbd99c61ef0afe91ae Author: Catalin Marinas Date: Wed Dec 12 15:40:54 2007 +0100 [ARM] 4698/1: RealView: Add clockevents suport for the local timers This patch registers the local timers on ARM11MPCore as clock event devices. The clock device can be set up as periodic or oneshot. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 470a255c79f083527919508c808d50c485f00f14 Author: Catalin Marinas Date: Wed Dec 12 15:40:48 2007 +0100 [ARM] 4696/1: RealView: Add broadcasting clockevents support for ARM11MPCore This patch adds dummy local timers for each CPU so that the board clock device is used to broadcast events to the other CPUs. The patch also adds the declaration for the dummy_timer_setup function (the equivalent of local_timer_setup when CONFIG_LOCAL_TIMERS is not set). Due to the way clockevents work, the dummy timer on the first CPU has to be registered before the board timer. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 6a3ab675fead0e31067f3a51d724b58b2bdcf8f7 Author: Catalin Marinas Date: Wed Dec 12 15:40:42 2007 +0100 [ARM] 4707/1: Add SMP helper functions for clockevents support This patch adds the smp_call_function_single and smp_timer_broadcast functions and modifies ipi_timer to call the platform-specific function local_timer_interrupt. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit fc121ea3ba78d4d5dab27271411ff3a22737f35d Author: Catalin Marinas Date: Wed Dec 12 15:40:36 2007 +0100 [ARM] 4695/1: RealView: clockevents support for the RealView platforms The patch updates the RealView code to the clockevents infrastructure. The SMP support is implemented in subsequent patches. Based on the Versatile implementation by Kevin Hilman. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit ba7bab2e45bd5afb730b993fa0965b50b19ebbc7 Author: Catalin Marinas Date: Wed Dec 12 15:40:30 2007 +0100 [ARM] 4697/1: RealView: clocksource support for the RealView platforms The patch updates the RealView platform code to use the generic clocksource infrastructure for basic time keeping. Based on the Versatile implementation by Kevin Hilman. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit d8cd32cfb80c0c0e912ddab2d9ac8ee23cd10f48 Author: Martin Michlmayr Date: Thu Dec 27 14:09:07 2007 +0100 [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device Use the new i2c framework to load rtc-rs5c372 for the GLAN Tank. Tested-by: Gordon Farquharson Signed-off-by: Martin Michlmayr Acked-by: Lennert Buytenhek Signed-off-by: Russell King commit b6070c2695ac357b149d27716d3aa23358a57626 Author: Krzysztof Halasa Date: Sun Dec 16 02:33:24 2007 +0100 [ARM] 4715/1: Ethernet support for IXDP425 boards Adds IXDP425 platform support for two built-in 10/100 Ethernet ports. This patch will do nothing until the actual Ethernet driver is also included. Depends on patch #4714 (platform struct definitions). Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King commit 6fce134a9a2e2dc1712346afc7fbf42c0ff93531 Author: Krzysztof Halasa Date: Sun Dec 16 02:22:26 2007 +0100 [ARM] 4714/1: Headers for IXP4xx built-in Ethernet and WAN drivers Adds platform structs and #defines required by drivers for IXP4xx built-in Ethernet and WAN (sync serial) ports. The actual drivers will reside in drivers/net/arm and drivers/net/wan and will be submitted separately. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King commit 2f2aaf50d4ba5ad286d7493a228e8aece4afd68b Author: Krzysztof Halasa Date: Tue Jan 1 21:55:23 2008 +0100 [ARM] 4713/3: Adds drivers for IXP4xx QMgr and NPE features This patch adds drivers for IXP4xx hardware Queue Manager and for Network Processor Engines. Requires patch #4712 (reading/writing CPU feature (aka fuse) bits). Posted to linux-arm-kernel on 2 Dec 2007 and revised. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King commit 7ca452333ddcdc966e8d5756fb568a5f6ab7fb89 Author: Krzysztof Halasa Date: Tue Dec 18 03:53:27 2007 +0100 [ARM] 4712/2: Adds functions to read and write IXP4xx "feature" bits Adds functions to read and write IXP4xx "feature" (aka "fuse") bits, containing information about available/enabled CPU features. The uncompress.h included by boot/compressed/misc.c resides in a different space than rest of the kernel and thus can't use asm/hardware.h (including asm/arch/cpu.h - which, in turn, may use EXPORTed symbol "processor_id"). Posted to linux-arm-kernel on 2 Dec 2007 and revised. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King commit b25964cbfbb5e030f48bbc215aa8ceb73f0f9a32 Author: Russell King Date: Fri Jan 4 22:41:09 2008 +0000 [ARM] pxa: increase size of memory mapping The mapping for physical address 0x48000000 is not sufficient to allow access to the dynamic memory controller configuration registers on PXA3. These registers need to be accessed to reconfigure the SDRAM when waking from a low power mode. Signed-off-by: Russell King commit dcd7436c9beb7a615a0047f2878eb573a60fea08 Author: eric miao Date: Wed Dec 12 09:29:33 2007 +0800 [ARM] pxa: move pxa27x_device_ohci out of pxa27x.c for use with pxa3xx Signed-off-by: eric miao Signed-off-by: Russell King commit cad7e736268ed8c8d65791397cf2481f0ce35ece Author: eric miao Date: Wed Dec 12 09:07:47 2007 +0800 [ARM] USB: update to allow pxa27x ohci driver to support pxa3xx Signed-off-by: eric miao Signed-off-by: Russell King commit 65f056c9c188935f689d3e1c11079ace9cca2295 Author: eric miao Date: Wed Dec 12 08:53:25 2007 +0800 [ARM] USB: update pxa27x ohci driver to use clk support Signed-off-by: eric miao Signed-off-by: Russell King commit fe56a20cff2276c81e976b8e047378002d2702f5 Author: eric miao Date: Tue Dec 25 10:34:33 2007 +0800 [ARM] pxa: make OHCI register definitions available to both pxa27x and pxa3xx Signed-off-by: eric miao Signed-off-by: Russell King commit 5e15c515499204bc07a36efa48ba38c655acf500 Author: eric miao Date: Wed Dec 12 09:32:01 2007 +0800 [ARM] pxa: add clk of CKEN_USBHOST for pxa3xx Signed-off-by: eric miao Signed-off-by: Russell King commit a6368599b3005b609c9ec01a56a3be44fe6f0732 Author: Sascha Hauer Date: Tue Jul 24 18:37:01 2007 +0200 [ARM] CONFIG_DEBUG_STACK_USAGE In early 2.6 days stack utilization instrumentation was made configurable. Seems that arm misses the DEBUG_STACK_USAGE option. Signed-off-by: Sascha Hauer Signed-off-by: Russell King commit 5e912f074d79e39a817499d2b9531e78512bebeb Author: Herbert Valerio Riedel Date: Sun Dec 16 17:42:31 2007 +0100 [ARM] Orion: implement power-off method for QNAP TS-109/209 Since the PIC is attached to UART1, it doesn't need a kernel device driver of its own; but powering off is something that the kernel should do, so this patch forcefully configures the UART1 for 19200 baud and sends the character that tells the PIC to cut the power. Signed-off-by: Herbert Valerio Riedel Cc: Byron Bradley Acked-by: Nicolas Pitre commit 00b6409bdc4fa3615dfa8e2de0f5d9ac3617e041 Author: Byron Bradley Date: Sat Dec 15 20:05:49 2007 +0000 [ARM] Orion: add support for QNAP TS-109/TS-209 This patch adds support for the Orion/MV88F5182 based QNAP TS-109/TS-209 NAS device. The driver for the S-35390A RTC chip on this board has been submitted to LKML separately. Signed-off-by: Byron Bradley Tested-by: Oyvind Repvik Tested-by: Tim Ellis Tested-by: Herbert Valerio Riedel Acked-by: Tzachi Perelstein commit 59a3002dd3df4de5a8bd744ca0ca3783098796a6 Author: Herbert Valerio Riedel Date: Mon Nov 12 09:51:36 2007 +0200 [ARM] Orion: I2C support The Orion I2C controller is the same one used in the Discovery family (MV643XX). This patch include the common platform_device stuff according to the existing i2c_mv64xxx.c conventions. Signed-off-by: Herbert Valerio Riedel Signed-off-by: Tzachi Perelstein commit 98dc38d395ef6dd7e6b4fa577f868efba7992365 Author: Jean Delvare Date: Thu Nov 22 16:58:08 2007 +0100 [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries I2C adapter drivers are supposed to handle retries on nack by themselves if they do, so there's no point in setting .retries if they don't. As this retry mechanism is going away (at least in its current form), clean this up now so that we don't get build failures later. Signed-off-by: Jean Delvare Acked-by: Mark A. Greer commit 87686f91749c779e06be4cb76eeac92cf834e125 Author: Tzachi Perelstein Date: Mon Nov 12 19:38:51 2007 +0200 [I2C] Split mv643xx I2C platform support The motivation for this change is to allow other chips, like the Marvell Orion ARM SoC family, to use the existing i2c-mv64xxx driver. Signed-off-by: Tzachi Perelstein Acked-by: Nicolas Pitre Acked-by: Dale Farnsworth Acked-by: Mark A. Greer Acked-by: Jean Delvare commit 7e25adf8571091984f8137dca41845763a277202 Author: Martin Michlmayr Date: Wed Nov 14 08:58:30 2007 +0100 [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323 The D-Link DNS-323 uses a M41T80 RTC chip, so enable this driver in the Orion defconfig. Signed-off-by: Martin Michlmayr Cc: Herbert Valerio Riedel Acked-by: Nicolas Pitre Acked-by: Russell King commit 6e0f695b06b0bf8cbf53f5b3d8d6e811a1e392d3 Author: Tzachi Perelstein Date: Tue Nov 6 11:18:46 2007 +0200 [ARM] Orion defconfig Basic selections for Orion machines Signed-off-by: Tzachi Perelstein Signed-off-by: Nicolas Pitre Acked-by: Russell King commit 2a282ea5b3ac0129b20f784f5f9e6cd94a7cf816 Author: Herbert Valerio Riedel Date: Mon Nov 12 09:05:55 2007 +0100 [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323 With this patch USB, SATA (via sata_mv), Ethernet, RTC, LEDs and NOR Flash work. Signed-off-by: Herbert Valerio Riedel Acked-by: Tzachi Perelstein Acked-by: Russell King commit cc4c82301b85a808a753fb90122da64a083a115a Author: Herbert Valerio Riedel Date: Sun Nov 11 12:05:11 2007 +0100 [ARM] Orion: MV88F5181 support bits add MV88F5181 support bits required by D-link DNS-323 patch Signed-off-by: Herbert Valerio Riedel Acked-by: Tzachi Perelstein Acked-by: Russell King commit 2ad2974f9fd01dde59bd6f570cac45e59a66987c Author: Ronen Shitrit Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: Buffalo/Revogear Kurobox Pro support Only serial, NOR, NAND, PCI and Ethernet is activated at the moment. Signed-off-by: Ronen Shitrit Reviewed-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 5e5e04e6e71a68d24a1a1b9c058197c81d3fa329 Author: Ronen Shitrit Date: Wed Oct 17 14:51:34 2007 -0400 [ARM] OrionNAS RD board support serial, NOR, PCI and Ethernet is activated at the moment. Signed-off-by: Ronen Shitrit Reviewed-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 0deff33fece888c940eb31c0064f74751554493a Author: Tzachi Perelstein Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board Signed-off-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 4190f5038585bc0e5dcc30110b9161a4c2d614c7 Author: Tzachi Perelstein Date: Wed Oct 31 12:42:41 2007 +0200 [ARM] Orion: common platform setup for Gigabit Ethernet port The Orion Ethernet port is the same port used in the Discovery family (MV643XX). This patch include the common platform_device stuff according to the existing mv643xx_eth conventions. Signed-off-by: Tzachi Perelstein Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 19d9c4e0e4e6381a7ebbdeb2db2c296d62214c10 Author: Tzachi Perelstein Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: platform device registration for UART, USB and NAND Signed-off-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit c040b3dc7f85cbb88394eef45f34c2a10b439bd4 Author: Tzachi Perelstein Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: system timer support Signed-off-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 605c7452641b6c198fb3cf71e9f68782c21ed3d0 Author: Tzachi Perelstein Date: Thu Nov 15 10:57:48 2007 +0200 [ARM] Orion edge GPIO IRQ support This patch adds support for Orion edge sensitive GPIO IRQs. Signed-off-by: Tzachi Perelstein Signed-off-by: Nicolas Pitre CC: Thomas Gleixner commit a79722a0b3962f7445068dbd78bd8d8936bff681 Author: Tzachi Perelstein Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: IRQ support Signed-off-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 64b481a98f763fa8ff82c37f36b88c45a7cfe24a Author: Herbert Valerio Riedel Date: Thu Nov 29 15:19:56 2007 +0100 [ARM] Orion: provide GPIO method for enabling hardware assisted blinking This is a pre-requisite for implementing proper hardware accelerated GPIO LED flashing, and since we want proper locking, it's sensible to provide the orion specific orion_gpio_set_blink() implementation within mach-orion/gpio.c. The functions orion_gpio_set_blink() and gpio_set_value() implicitly turn off each others state. Signed-off-by: Herbert Valerio Riedel Acked-by: Tzachi Perelstein Acked-by: Nicolas Pitre Acked-by: Russell King commit c0d747e760842d4367046f3de6ce3d9ee7908ead Author: Tzachi Perelstein Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: GPIO support Signed-off-by: Tzachi Perelstein Signed-off-by: Nicolas Pitre Acked-by: David Brownell commit 51c67ed4f693cab1ba0497d3ae228a9d026fd175 Author: Tzachi Perelstein Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: programable address map support The Orion has fully programable address map. There's a separate address map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, Gigabit Ethernet, DMA/XOR engines, etc. Signed-off-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek commit df33949259de7cad7f5a3078e7a8c03e98876954 Author: Tzachi Perelstein Date: Tue Oct 23 15:14:42 2007 -0400 [ARM] Orion: PCI support This patch adds support for PCI and PCI-E controllers in the Orion, Orion-NAS and Orion2. Signed-off-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit aee44abf5a472d1fa7849d1eaa85097aa6e93938 Author: Tzachi Perelstein Date: Tue Oct 23 15:14:41 2007 -0400 [ARM] basic support for the Marvell Orion SoC family The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces, and, depending on the specific model, PCI-E interface, PCI-X interface, SATA controllers, crypto unit, SPI interface, SDIO interface, device bus, NAND controller, DMA engine and/or XOR engine. This contains the basic structure and architecture register definitions. Signed-off-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 70f98aaece086a6a7ac4fe9c6edd603ea7760b71 Author: Tzachi Perelstein Date: Tue Nov 6 10:35:40 2007 +0200 [ARM] Feroceon: support old cores with ARM926 ID This enables the usage of some old Feroceon cores for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and old Feroceon-2850. Signed-off-by: Tzachi Perelstein Signed-off-by: Nicolas Pitre Acked-by: Russell King commit 1c84d494f958ec8e9c9bd270c5740f2bccd1ddb8 Author: Nicolas Pitre Date: Wed Oct 31 15:31:48 2007 -0400 [ARM] add Feroceon support to compressed/head.S The cache replacement policy on the Feroceon core doesn't guarantee that reading through a linear chunk of memory flushes the entire cache. This is however what the default method for ARMv5TE cores does. Although the Feroceon is an ARMv5TE core, it implements the same cache handling instructions as the ARMv5TEJ cores, and must use it for proper cache flush. Signed-off-by: Nicolas Pitre Acked-by: Russell King commit 0148d3567bdda72c58e3bf12fab7dfffa29d6773 Author: Nicolas Pitre Date: Wed Oct 31 15:15:29 2007 -0400 [ARM] add ARMv5TEJ aware cache flush method to compressed/head.S The default ARMv4 method consisting of reading through some memory area isn't compatible with the cache replacement policy of some ARMv5TEJ compatible cache implementations. It is also a bit wasteful when a dedicated instruction can do the needed work optimally. It is hard to tell if all ARMv5TEJ cores will support the used CP15 instruction, but at least all those implementations Linux currently knows about (ARM926 and ARM1026) do support it. Tested on an OMAP1610 H2 target. Signed-off-by: Nicolas Pitre Tested-by: George G. Davis Acked-by: Russell King commit 75e7b65d7e509b0b5b6ae9e2002646e9bd741cb9 Author: Assaf Hoffman Date: Tue Oct 23 15:14:41 2007 -0400 [ARM] Marvell Feroceon CPU core support The Feroceon is a family of independent ARMv5TE compliant CPU core implementations, supporting a variable depth pipeline and out-of-order execution. The Feroceon is configurable with VFP support, and the later models in the series are superscalar with up to two instructions per clock cycle. This patch adds the initial low-level cache/TLB handling for this core. Signed-off-by: Assaf Hoffman Reviewed-by: Tzachi Perelstein Reviewed-by: Nicolas Pitre Reviewed-by: Lennert Buytenhek Acked-by: Russell King commit 4a727c7d9aa1f84867a18feeccfe8c45b64b4cf0 Author: Nicolas Pitre Date: Tue Dec 4 14:33:33 2007 +0100 [ARM] 4689/1: small comment wrap fix Signed-off-by: Nicolas Pitre Signed-off-by: Russell King commit 946ae4771fa445144e886dbbe72a3c725b0429ff Author: George G. Davis Date: Sat Dec 1 05:49:41 2007 +0100 [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix Make the comment match the code Signed-off-by: George G. Davis Signed-off-by: Russell King commit e37ca3b8223044e4786e0403246ac44bbf8b96bd Author: Pavel Roskin Date: Sun Nov 25 02:12:39 2007 +0100 [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h Don't lose __iomem in casts. Use __force to cast __iomem addresses to integers. Use __force to cast u32 to __le32 and vice versa. Signed-off-by: Pavel Roskin Signed-off-by: Russell King commit 9fe72e85411d6cefe30ab561fd407bd490fc3918 Author: Lucas Woods Date: Wed Nov 21 14:51:51 2007 -0800 [ARM] remove duplicate includes Signed-off-by: Lucas Woods Acked-by: Lennert Buytenhek Signed-off-by: Andrew Morton Signed-off-by: Russell King commit 34ca28d19246f174230a32b6c73ac8670fddd609 Author: Robert P. J. Day Date: Wed Nov 21 14:51:49 2007 -0800 [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS The CONFIG variable MTD_OBSOLETE_CHIPS was deleted in commit ba7cc09c9c9e29a57045dc5bbf843ac1cfad3283. Signed-off-by: Robert P. J. Day Signed-off-by: Andrew Morton Signed-off-by: Russell King commit 73f6c34551edec5d8ea735bc99e5ce8599973c44 Author: Andre Haupt Date: Wed Nov 21 14:51:47 2007 -0800 [ARM] ixp4xx: remove double include Remove double include. Signed-off-by: Andre Haupt Signed-off-by: Alessandro Zummo Signed-off-by: Andrew Morton Signed-off-by: Russell King commit 2c98c0c3066edcbdf31b2cfb11367bad20aca175 Author: Alan Cox Date: Mon Nov 19 15:12:22 2007 +0000 [SERIAL] 21285: Report baud rate back via termios Currently reports back the requested rate not the result of the divides but thats an easy fix for someone with h/w Signed-off-by: Alan Cox Signed-off-by: Russell King commit 452590b3f149bdd2ff4c81f89201b0eb8859d956 Author: Jeff Garzik Date: Fri Oct 26 05:40:22 2007 -0400 [ARM] Remove pointless casts from void pointers, mostly in and around irq handlers. Signed-off-by: Jeff Garzik Signed-off-by: Russell King commit dab5902541a94a8281517eb7584e0057f6300fe0 Author: Jeff Garzik Date: Fri Oct 26 05:40:25 2007 -0400 [ARM] Misc minor interrupt handler cleanups mach-integrator/pci_v3.c: no need to reference 'irq' arg, its constant mach-omap1/pm.c: remove extra whitespace arch/arm/mach-sa1100/ssp.c: remove braces around single C stmt arch/arm/plat-omap/mcbsp.c: - remove pointless casts from void* - make longer lines more readable Signed-off-by: Jeff Garzik Acked-by: Lennert Buytenhek Signed-off-by: Russell King commit 2235350e97f110a7bcfb012c00e911ac8d490f76 Author: Jan Altenberg Date: Tue Oct 2 13:26:43 2007 -0700 [ARM] Remove at91_lcdc.h include/asm-arm/arch-at91/at91_lcdc.h (which is still present in latest git) has been superseeded by include/video/atmel_lcdc.h, so let's remove it. Signed-off-by: Jan Altenberg Cc: Andrew Victor Cc: Nicolas Ferre Signed-off-by: Andrew Morton Signed-off-by: Russell King commit 11e6ae5a29eb9b10e1ddbdf65917110f634b7acb Author: Alejandro Martinez Ruiz Date: Wed Oct 17 12:14:25 2007 +0200 [ARM] ARRAY_SIZE() cleanup Signed-off-by: Alejandro Martinez Ruiz Signed-off-by: Russell King commit 2d7ed47ae6e3f699396d2590c41842440d2b400e Author: Russell King Date: Tue Jan 1 10:59:26 2008 +0000 [ARM] Update mach-types Signed-off-by: Russell King commit 1f58ef2a448fa4788acbaaa09997421f9fa4a395 Author: Arve Hjønnevåg Date: Mon Nov 26 04:12:29 2007 -0800 [ARM] msm: dma support for MSM7X00A Signed-off-by: Brian Swetland commit c8dbc14c33540d670fac96d9155b639a3c99ab35 Author: Brian Swetland Date: Mon Nov 26 04:12:13 2007 -0800 [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A) Add support for the Qualcomm MSM7200A eval board. Common devices are defined in common.c, to avoid excessive cut'n'pasting them into other board files. Signed-off-by: Brian Swetland commit bdd859c12c10d9ff7092b40b607628815da5cc19 Author: Arve Hjønnevåg Date: Mon Nov 26 04:11:58 2007 -0800 [ARM] msm: irq and timer support for ARCH_MSM7X00A - Vectored Interrupt Controller support - Timer support using the GPT and DGT timers Signed-off-by: Brian Swetland commit 6e2852134d12db6d13f849c35457791e9cada377 Author: Brian Swetland Date: Mon Nov 26 04:11:43 2007 -0800 [ARM] msm: core platform support for ARCH_MSM7X00A - core header files for arch-msm - Kconfig and Makefiles to enable ARCH_MSM7X00A builds - MSM7X00A specific arch_idle - peripheral iomap and irq number definitions Signed-off-by: Brian Swetland commit 70a2e6e89136a32fec089ca3de07b58211fb2a29 Author: Catalin Marinas Date: Tue Sep 25 15:22:24 2007 +0100 [ARM] 4583/1: ARMv7: Add VFPv3 support This patch adds the support for VFPv3 (the kernel currently supports VFPv2). The main difference is 32 double registers (compared to 16). Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 650a4e492c5a850f9110ded8de55ec20af2fe441 Author: Catalin Marinas Date: Thu Nov 22 18:32:01 2007 +0100 [ARM] 4582/2: Add support for the common VFP subarchitecture This patch allows the VFP support code to run correctly on CPUs compatible with the common VFP subarchitecture specification (Appendix B in the ARM ARM v7-A and v7-R edition). It implements support for VFP subarchitecture 2 while being backwards compatible with subarchitecture 1. On VFP subarchitecture 1, the arithmetic exceptions are asynchronous (or imprecise as described in the old ARM ARM) unless the FPSCR.IXE bit is 1. The exceptional instructions can be read from FPINST and FPINST2 registers. With VFP subarchitecture 2, the arithmetic exceptions can also be synchronous and marked by the FPEXC.DEX bit (the FPEXC.EX bit is cleared). CPUs implementing the synchronous arithmetic exceptions don't have the FPINST and FPINST2 registers and accessing them would trigger and undefined exception. Note that FPEXC.EX bit has an additional meaning on subarchitecture 1 - if it isn't set, there is no additional information in FPINST and FPINST2 that needs to be saved at context switch or when lazy-loading the VFP state of a different thread. The patch also removes the clearing of the cumulative exception flags in FPSCR when additional exceptions were raised. It is up to the user application to clear these bits. Signed-off-by: Catalin Marinas Signed-off-by: Russell King commit 6a7930103b88947092797aee36e20b4e290ca3b5 Author: eric miao Date: Fri Nov 23 14:55:59 2007 +0800 [ARM] pxa: ensure SSP TX FIFO is empty instead of not full for pxa3xx Signed-off-by: eric miao Signed-off-by: Russell King commit 7abc906a9ab1cba25c7d6416f8649b1b1355722e Author: Bridge Wu Date: Fri Dec 21 19:27:08 2007 +0800 [ARM] pxa: mmc: add 3rd host controller support for pxa310 This patch is to add the third mmc controller support _only_ for pxa310. On zylonite, the third controller support one slot. Signed-off-by: Bridge Wu Signed-off-by: Russell King commit a03c065abaac920b0d31027a1f14ed03e07d6801 Author: Bridge Wu Date: Fri Dec 21 19:15:36 2007 +0800 [ARM] pxa: mmc: add 2nd host controller support for pxa3xx This patch is to add the second mmc controller support for pxa3xx. It's valid for pxa3[0|1|2]0. On zylonite, the second controller has no slot. Signed-off-by: Bridge Wu Signed-off-by: Russell King commit 0d39317a3cf7710134d890ede305c7f8d3206ebf Author: Bridge Wu Date: Fri Dec 21 19:00:13 2007 +0800 [ARM] pxa: mmc: add 1st host controller support for pxa3xx This patchis to add the first mmc controller support for pxa3xx. It's valid for pxa3[0|1|2]0. On zylonite, the first controller supports two slots, this patch only support the first one right now. Signed-off-by: Bridge Wu Signed-off-by: Russell King commit 35470960e2258446cf8de0cba69d9437c009a5dc Author: eric miao Date: Wed Dec 19 17:14:02 2007 +0800 [ARM] pxa: create arch/arm/mach-pxa/device.c for all on-chip devices Considering that generic.c is getting more and more bloated by device information, moving that part out side will be much cleaner. Signed-off-by: eric miao Signed-off-by: Russell King commit 845884bec2748ebd0355bdc3b9e10d12b710f94c Author: Philipp Zabel Date: Fri Dec 21 09:31:25 2007 +0100 [ARM] 4718/1: Fix redefinition warnings in PXA uncompressor code FFUART and friends are already defined as __REG(x) in pxa-regs.h. Instead of redefining them here, we can just provide the __REG macro. Including asm/arch/hardware.h is not an option because this physical addresses are needed here. This is a fix for the compiler warnings generated by 4663/1. Signed-off-by: Philipp Zabel Acked-by: Nicolas Pitre Signed-off-by: Russell King commit 34c67b535fde0eb5dcc7244584ffc8c9a8b0695f Author: Bridge Wu Date: Fri Dec 14 10:40:25 2007 +0100 [ARM] 4711/1: pxa: mmc: move DMA specific code to platform layer This patch is to move pxamci DMA specific code to corresponding platform layer because using DRCMRRXMMC/DRCMRTXMMC in pxamci.c makes the driver code dedicated to platform which is not extensible. It is applicable to all pxa platforms. Signed-off-by: Bridge Wu Signed-off-by: Russell King commit e9ae9af93ec70489617530474a15c2ba06d91c6a Author: Bridge Wu Date: Thu Dec 13 07:24:30 2007 +0100 [ARM] 4709/1: pxa: mmc: add 26MHz support for pxa3[0|1]0 mmc controller pxa3[0|1]0 mmc controller can support 26MHz clock mode, they support SD spec 1.1 and MMC spec 4.0 which specify high speed mode. So host caps will include MMC_CAP_MMC_HIGHSPEED and MMC_CAP_SD_HIGHSPEED for pxa3[0|1]0. This patch is to add 26MHz support for them. pxa host clock will be set to 26MHz mode when the card supported max clock rate is higher than or equal to 26MHz. Signed-off-by: Bridge Wu Acked-by: Pierre Ossman Signed-off-by: Russell King commit d6426ba0e19c73310c242371ca1f373a9282d1ff Author: Russell King Date: Fri Dec 14 13:30:14 2007 +0000 [ARM] pxa: add cpufreq support There have been patches hanging around for ages to add support for cpufreq to PXA255 processors. It's about time we applied one. Signed-off-by: Russell King commit 9b9fe6dd0ed6271ae56d84ab91344bef441052c5 Author: Russell King Date: Mon Dec 10 15:35:54 2007 +0000 [ARM] pxa: initialise SSP earlier Initialise the SSP driver at arch_initcall() time, so it's available for other drivers to use it. Signed-off-by: Russell King commit 43471eab6f17993ed91eacc6efce4a854006fbf5 Author: Russell King Date: Mon Dec 10 13:33:06 2007 +0000 [ARM] pxa: only register "cpld_irq" for the correct platform Only register the "cpld_irq" sysclass for mainstone/lubbock if we're running on one of those platforms. Signed-off-by: Russell King commit 8573d81532427cc3c04c12a378736028009ae94a Author: eric miao Date: Wed Nov 21 18:50:53 2007 +0800 [ARM] pxa: make pxa2xx_spi driver use ssp_request()/ssp_free() 1. make pxa2xx_spi.c use ssp_request() and ssp_free() to get the common information of the designated SSP port. 2. remove those IRQ/memory request code, ssp_request() has done that for the driver 3. the SPI platform device is thus made psuedo, no resource (memory/IRQ) has to be defined, all will be retreived by ssp_request() 4. introduce ssp_get_clk_div() to handle controller difference in clock divisor setting 5. use clk_xxx() API for clock enable/disable, and clk_get_rate() to handle the different SSP clock frequency between different processors Signed-off-by: eric miao Signed-off-by: Russell King commit c2d8534853078e24e8d922dbe34879df790836a0 Author: eric miao Date: Fri Nov 30 18:26:56 2007 +0800 [ARM] pxa: use __raw_writel()/__raw_readl() for ssp_xxxx() 1. change SSP register definitions from absolute virtual addresses to offsets 2. use __raw_writel()/__raw_readl() for functions of ssp_xxxx() Signed-off-by: eric miao Signed-off-by: Russell King commit 96101d36386ba6bb793ff844c57894bf7230f440 Author: eric miao Date: Wed Nov 21 16:57:12 2007 +0800 [ARM] pxa: move SSP register definitions from pxa-regs.h to regs-ssp.h Signed-off-by: eric miao Signed-off-by: Russell King commit a2f7070f1cf2a6ed19c8182146c7bc19b6fd86d6 Author: eric miao Date: Thu Dec 6 17:56:42 2007 +0800 [ARM] pxa: define "struct ssp_device" and add ssp_request()/ssp_free() 1. define "struct ssp_device" for SSP information, which is requested and released by function ssp_request()/ssp_free() 2. modify the ssp_init() and ssp_exit() to use the interface Signed-off-by: eric miao Signed-off-by: Russell King commit 487e975ee22d9bb42c63350581ac3917031b2074 Author: eric miao Date: Mon Dec 10 17:54:36 2007 +0800 [ARM] pxa: add ssp devices and clk support for pxa25x/pxa27x/pxa3xx Signed-off-by: eric miao Signed-off-by: Russell King commit 9d636eb319ac1c373686ff076b10e60e9473554c Author: eric miao Date: Mon Dec 10 17:51:29 2007 +0800 [ARM] pxa: define SSP platform devices for pxa2xx/pxa3xx Signed-off-by: eric miao Signed-off-by: Russell King commit 418311617d463bcebadca382e39bc70345a8b522 Author: Philipp Zabel Date: Thu Nov 22 17:57:30 2007 +0100 [ARM] 4663/1: Only putc uncompressor output into FFUART if it was enabled by the bootloader Also, use existing register and bit definitions instead of numbers. Signed-off-by: Philipp Zabel Acked-by: Nicolas Pitre Signed-off-by: Russell King commit e2dfc2e75e86540b7a618ef6594435dc5a813ac5 Author: Russell King Date: Mon Nov 12 22:49:58 2007 +0000 [ARM] pxa/sa1100: replace wakeup support Replace wakeup support using the alarm via the SA1100 RTC driver on SA1100 and PXA platforms. This allows RTC alarm wakeup to be enabled via sysfs using the conventional attributes. Acked-by: Alessandro Zummo Signed-off-by: Russell King commit 0304d45fcfbd19e08d5c95f7c9f111aaaac2eaf7 Author: Russell King Date: Mon Nov 12 22:48:12 2007 +0000 [ARM] pxa: Don't wind OSCR backwards over suspend/resume OSCR is supposed to monotonically increment; however restoring it to a time prior to OSMR0 may result in it being wound backwards. Instead, if OSMR0 is within the minimum expiry time, wind OSMR0 forwards. Signed-off-by: Russell King commit be7b516901080e7cdb2841ad899a4ddcaf1483bc Author: Russell King Date: Mon Nov 12 22:45:16 2007 +0000 [ARM] pxa: remove periodic mode emulation support Apparantly, the generic time subsystem can accurately emulate periodic mode via the one-shot support code, so we don't need our own periodic emulation code anymore. Just ensure that we build support for one shot into the generic time subsystem. Signed-off-by: Russell King commit b2109d8affeb73f10b1d1bdcc74d6edb3628ac1e Author: Russell King Date: Thu Nov 8 11:22:48 2007 +0000 [ARM] pxa: mainstone: update backlight to use the backlight infrastructure Linux has framebuffer backlight support infrastructure which should be used to expose backlight attributes. Mainstone should use it. Signed-off-by: Russell King commit 8b25f2b34dfb4c68fb79acfc53c7393965a3e3c5 Author: Russell King Date: Thu Nov 8 11:17:19 2007 +0000 [ARM] pxa: avoid always registering MMC, I2C, IrDA and framebuffer devices Only register the MMC, framebuffer, I2C and FICP devices when the platform supplies the necessary platform data structures for the devices. Signed-off-by: Russell King commit 8327911ee7e7926dde7cdab1553a7c9aae20734e Author: Russell King Date: Mon Nov 12 21:55:12 2007 +0000 [ARM] sa1100: add clock source support Add generic clock source support for SA11x0 platforms. Signed-off-by: Russell King commit 9fc2962481957019d5659d9a60df6d90a565190c Author: Andrew Victor Date: Mon Oct 15 14:27:41 2007 +0100 [ARM] 4603/1: KS8695: debugfs interface to view pin state This patch adds a debug interface (if CONFIG_DEBUG_FS is selected) to display the basic configuration and current state of the GPIO pins on the Kendin/Micrel KS8695 processor. Signed-off-by: Andrew Victor Signed-off-by: Russell King commit 1c9d9010dbcfb9895db89a3fe81dbec6dd8a267c Author: Andrew Victor Date: Mon Oct 15 13:09:19 2007 +0100 [ARM] 4601/1: KS8695: PCI support This patch adds support for the PCI Host controller integrated in the Kendin/Micrel KS8695 processor. Signed-off-by: Andrew Victor Signed-off-by: Russell King commit 369fd85165f8b88b5fc8375b1499c2e833fcf307 Author: Dan Williams Date: Thu Dec 13 00:20:05 2007 +0100 [ARM] 4708/1: iop: update defconfigs for 2.6.24 * iop13xx, iop33x, iop32x: re-enable the IOP_ADMA driver by default * iop32x: enable RS5C372 and RTC_CLASS support Signed-off-by: Dan Williams Signed-off-by: Russell King commit 2a12a0f8648c5b3ee3b52761591e65747f5a8c7a Author: Herbert Valerio Riedel Date: Mon Nov 26 18:50:42 2007 +0100 [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations With the new GPIO methods in place the old gpio_line_* methods are redundant, so this patch finally removes the old legacy gpio_line_* wrappers. Signed-off-by: Herbert Valerio Riedel Acked-by: Lennert Buytenhek Signed-off-by: Russell King commit 9d352cc6c65c141c7b6b38dd0a1e4a13541173cc Author: Herbert Valerio Riedel Date: Mon Nov 26 18:49:08 2007 +0100 [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type Having a both-edge sensitive irq trigger type is required for the generic gpio-keys input driver; alas the ep93xx does not support both-edge gpio triggers in hardware, so this patch implements them by switching edge polarity on each triggered interrupt. This is the same approach as taken by the Orion SoC both-edge gpio irq support implementation. Signed-off-by: Herbert Valerio Riedel Acked-by: Lennert Buytenhek Signed-off-by: Russell King commit df6af1a4d1c216d0fe1af816695a4f0e9758870c Author: Herbert Valerio Riedel Date: Mon Nov 26 18:45:59 2007 +0100 [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups This patch renumbers the (virtual) GPIO line numbering to have all irq-capable gpio lines <= EP93XX_GPIO_LINE_MAX_IRQ by swapping the port f range with the port c range; This simplifies code such as #define IRQ_EP93XX_GPIO(x) (64 + (((x) + (((x) >> 2) & 8)) & 0x1f)) or if (line >= 0 && line < 16) { /* Port A/B */ } else if (line >= 40 && line < 48) { /* Port F */ } considerably; in addition to the renumbering this patch also introduces macro constants EP93XX_GPIO_LINE_MAX_IRQ and EP93XX_GPIO_LINE_MAX, and replaces most magic numbers by those and invocations of gpio_to_irq()/irq_to_gpio(). Signed-off-by: Herbert Valerio Riedel Acked-by: Lennert Buytenhek Signed-off-by: Russell King commit cff9488d53e36d7876bf7bfa24e88b8fbe08b0a3 Author: Herbert Valerio Riedel Date: Mon Nov 26 18:41:02 2007 +0100 [ARM] 4668/1: ep93xx: implement new GPIO API Implement new GPIO API for ep93xx platform as defined in Documentation/gpio.txt and provide transitional __deprecated wrappers for the previous gpio_line_* functions. Signed-off-by: Herbert Valerio Riedel Acked-by: Lennert Buytenhek Signed-off-by: Russell King Documentation/cpu-freq/user-guide.txt | 1 + arch/arm/Kconfig | 56 +- arch/arm/Kconfig.debug | 6 + arch/arm/Makefile | 2 + arch/arm/boot/compressed/head.S | 15 +- arch/arm/common/rtctime.c | 1 - arch/arm/configs/collie_defconfig | 1 - arch/arm/configs/eseries_pxa_defconfig | 1499 +++++++++++++++++++++++++++ arch/arm/configs/iop13xx_defconfig | 156 ++-- arch/arm/configs/iop32x_defconfig | 207 +++-- arch/arm/configs/iop33x_defconfig | 154 ++-- arch/arm/configs/littleton_defconfig | 783 ++++++++++++++ arch/arm/configs/msm_defconfig | 895 ++++++++++++++++ arch/arm/configs/orion_defconfig | 1384 +++++++++++++++++++++++++ arch/arm/kernel/dma-isa.c | 2 +- arch/arm/kernel/entry-armv.S | 4 +- arch/arm/kernel/entry-common.S | 2 +- arch/arm/kernel/setup.c | 1 + arch/arm/kernel/smp.c | 34 +- arch/arm/mach-ep93xx/core.c | 258 +++-- arch/arm/mach-integrator/pci_v3.c | 8 +- arch/arm/mach-iop32x/glantank.c | 13 +- arch/arm/mach-ixp23xx/core.c | 1 - arch/arm/mach-ixp23xx/espresso.c | 2 - arch/arm/mach-ixp23xx/ixdp2351.c | 2 - arch/arm/mach-ixp23xx/roadrunner.c | 2 - arch/arm/mach-ixp4xx/Kconfig | 14 + arch/arm/mach-ixp4xx/Makefile | 2 + arch/arm/mach-ixp4xx/ixdp425-setup.c | 29 +- arch/arm/mach-ixp4xx/ixp4xx_npe.c | 741 +++++++++++++ arch/arm/mach-ixp4xx/ixp4xx_qmgr.c | 274 +++++ arch/arm/mach-ixp4xx/nslu2-power.c | 2 - arch/arm/mach-ks8695/Makefile | 2 +- arch/arm/mach-ks8695/board-micrel.c | 2 +- arch/arm/mach-ks8695/gpio.c | 83 ++ arch/arm/mach-ks8695/pci.c | 326 ++++++ arch/arm/mach-msm/Kconfig | 18 + arch/arm/mach-msm/Makefile | 7 + arch/arm/mach-msm/Makefile.boot | 3 + arch/arm/mach-msm/board-halibut.c | 114 ++ arch/arm/mach-msm/common.c | 116 ++ arch/arm/mach-msm/dma.c | 214 ++++ arch/arm/mach-msm/idle.S | 36 + arch/arm/mach-msm/io.c | 85 ++ arch/arm/mach-msm/irq.c | 154 +++ arch/arm/mach-msm/timer.c | 205 ++++ arch/arm/mach-omap1/board-fsample.c | 2 +- arch/arm/mach-omap1/board-h2.c | 2 +- arch/arm/mach-omap1/board-h3.c | 2 +- arch/arm/mach-omap1/board-innovator.c | 4 +- arch/arm/mach-omap1/board-nokia770.c | 1 - arch/arm/mach-omap1/board-osk.c | 3 +- arch/arm/mach-omap1/board-palmtt.c | 1 - arch/arm/mach-omap1/board-palmz71.c | 1 - arch/arm/mach-omap1/board-perseus2.c | 2 +- arch/arm/mach-omap1/board-voiceblue.c | 2 +- arch/arm/mach-omap1/pm.c | 2 +- arch/arm/mach-omap2/board-2430sdp.c | 2 +- arch/arm/mach-omap2/board-apollon.c | 3 +- arch/arm/mach-orion/Kconfig | 41 + arch/arm/mach-orion/Makefile | 6 + arch/arm/mach-orion/Makefile.boot | 3 + arch/arm/mach-orion/addr-map.c | 484 +++++++++ arch/arm/mach-orion/common.c | 315 ++++++ arch/arm/mach-orion/common.h | 78 ++ arch/arm/mach-orion/db88f5281-setup.c | 364 +++++++ arch/arm/mach-orion/dns323-setup.c | 322 ++++++ arch/arm/mach-orion/gpio.c | 225 ++++ arch/arm/mach-orion/irq.c | 241 +++++ arch/arm/mach-orion/kurobox_pro-setup.c | 234 +++++ arch/arm/mach-orion/pci.c | 557 ++++++++++ arch/arm/mach-orion/rd88f5182-setup.c | 306 ++++++ arch/arm/mach-orion/time.c | 181 ++++ arch/arm/mach-orion/ts209-setup.c | 335 ++++++ arch/arm/mach-pxa/Kconfig | 55 + arch/arm/mach-pxa/Makefile | 12 +- arch/arm/mach-pxa/corgi_ssp.c | 1 + arch/arm/mach-pxa/cpu-pxa.c | 294 ++++++ arch/arm/mach-pxa/devices.c | 662 ++++++++++++ arch/arm/mach-pxa/devices.h | 12 + arch/arm/mach-pxa/eseries.c | 101 ++ arch/arm/mach-pxa/generic.c | 251 +----- arch/arm/mach-pxa/idp.c | 2 +- arch/arm/mach-pxa/littleton.c | 325 ++++++ arch/arm/mach-pxa/lpd270.c | 1 + arch/arm/mach-pxa/lubbock.c | 30 +- arch/arm/mach-pxa/magician.c | 218 ++++ arch/arm/mach-pxa/mainstone.c | 73 ++- arch/arm/mach-pxa/mfp.c | 261 +++--- arch/arm/mach-pxa/pxa25x.c | 20 +- arch/arm/mach-pxa/pxa27x.c | 53 +- arch/arm/mach-pxa/pxa3xx.c | 241 +++++- arch/arm/mach-pxa/sleep.S | 9 +- arch/arm/mach-pxa/ssp.c | 386 ++++++-- arch/arm/mach-pxa/standby.S | 83 ++ arch/arm/mach-pxa/time.c | 82 +-- arch/arm/mach-pxa/zylonite.c | 96 ++- arch/arm/mach-pxa/zylonite_pxa300.c | 65 +- arch/arm/mach-pxa/zylonite_pxa320.c | 45 +- arch/arm/mach-realview/Kconfig | 21 +- arch/arm/mach-realview/Makefile | 3 +- arch/arm/mach-realview/core.c | 179 ++-- arch/arm/mach-realview/core.h | 71 +-- arch/arm/mach-realview/localtimer.c | 141 ++- arch/arm/mach-realview/platsmp.c | 13 +- arch/arm/mach-realview/realview_eb.c | 234 ++++- arch/arm/mach-s3c2410/usb-simtec.c | 2 +- arch/arm/mach-sa1100/ssp.c | 3 +- arch/arm/mach-sa1100/time.c | 38 +- arch/arm/mm/Kconfig | 28 +- arch/arm/mm/Makefile | 1 + arch/arm/mm/proc-feroceon.S | 506 +++++++++ arch/arm/plat-omap/debug-devices.c | 2 +- arch/arm/plat-omap/mailbox.c | 2 +- arch/arm/plat-omap/mcbsp.c | 20 +- arch/arm/tools/mach-types | 239 +++++- arch/arm/vfp/vfp.h | 4 + arch/arm/vfp/vfphw.S | 60 +- arch/arm/vfp/vfpinstr.h | 6 +- arch/arm/vfp/vfpmodule.c | 98 +- arch/powerpc/sysdev/mv64x60_dev.c | 6 - arch/ppc/syslib/mv64x60.c | 1 - drivers/i2c/busses/Kconfig | 2 +- drivers/i2c/busses/i2c-mv64xxx.c | 32 +- drivers/mmc/host/pxamci.c | 61 +- drivers/mmc/host/pxamci.h | 2 +- drivers/net/smc91x.c | 19 +- drivers/net/smc91x.h | 21 +- drivers/pcmcia/pxa2xx_base.c | 1 + drivers/rtc/rtc-sa1100.c | 31 + drivers/serial/21285.c | 2 + drivers/spi/Kconfig | 1 + drivers/spi/pxa2xx_spi.c | 139 +-- drivers/usb/Kconfig | 1 + drivers/usb/host/ohci-hcd.c | 2 +- drivers/usb/host/ohci-pxa27x.c | 13 +- include/asm-arm/arch-at91/at91_lcdc.h | 148 --- include/asm-arm/arch-ep93xx/gpio.h | 58 +- include/asm-arm/arch-ep93xx/irqs.h | 6 - include/asm-arm/arch-ixp4xx/cpu.h | 15 + include/asm-arm/arch-ixp4xx/hardware.h | 6 +- include/asm-arm/arch-ixp4xx/io.h | 16 +- include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 36 +- include/asm-arm/arch-ixp4xx/npe.h | 39 + include/asm-arm/arch-ixp4xx/platform.h | 24 +- include/asm-arm/arch-ixp4xx/qmgr.h | 126 +++ include/asm-arm/arch-ixp4xx/uncompress.h | 2 +- include/asm-arm/arch-ks8695/regs-gpio.h | 2 + include/asm-arm/arch-msm/board.h | 37 + include/asm-arm/arch-msm/debug-macro.S | 40 + include/asm-arm/arch-msm/dma.h | 151 +++ include/asm-arm/arch-msm/entry-macro.S | 38 + include/asm-arm/arch-msm/hardware.h | 18 + include/asm-arm/arch-msm/io.h | 33 + include/asm-arm/arch-msm/irqs.h | 89 ++ include/asm-arm/arch-msm/memory.h | 27 + include/asm-arm/arch-msm/msm_iomap.h | 104 ++ include/asm-arm/arch-msm/system.h | 23 + include/asm-arm/arch-msm/timex.h | 20 + include/asm-arm/arch-msm/uncompress.h | 36 + include/asm-arm/arch-msm/vmalloc.h | 22 + include/asm-arm/arch-orion/debug-macro.S | 17 + include/asm-arm/arch-orion/dma.h | 1 + include/asm-arm/arch-orion/entry-macro.S | 31 + include/asm-arm/arch-orion/gpio.h | 28 + include/asm-arm/arch-orion/hardware.h | 24 + include/asm-arm/arch-orion/io.h | 27 + include/asm-arm/arch-orion/irqs.h | 61 ++ include/asm-arm/arch-orion/memory.h | 15 + include/asm-arm/arch-orion/orion.h | 143 +++ include/asm-arm/arch-orion/platform.h | 25 + include/asm-arm/arch-orion/system.h | 31 + include/asm-arm/arch-orion/timex.h | 12 + include/asm-arm/arch-orion/uncompress.h | 44 + include/asm-arm/arch-orion/vmalloc.h | 5 + include/asm-arm/arch-pxa/littleton.h | 6 + include/asm-arm/arch-pxa/magician.h | 111 ++ include/asm-arm/arch-pxa/mfp-pxa300.h | 1 + include/asm-arm/arch-pxa/mfp-pxa320.h | 1 + include/asm-arm/arch-pxa/mfp-pxa3xx.h | 252 +++++ include/asm-arm/arch-pxa/mfp.h | 409 ++------ include/asm-arm/arch-pxa/mmc.h | 2 + include/asm-arm/arch-pxa/pxa-regs.h | 370 ++------ include/asm-arm/arch-pxa/pxa2xx-regs.h | 84 ++ include/asm-arm/arch-pxa/pxa2xx_spi.h | 24 - include/asm-arm/arch-pxa/pxa3xx-regs.h | 86 ++ include/asm-arm/arch-pxa/regs-ssp.h | 112 ++ include/asm-arm/arch-pxa/ssp.h | 36 +- include/asm-arm/arch-pxa/uncompress.h | 14 +- include/asm-arm/arch-pxa/zylonite.h | 9 + include/asm-arm/arch-realview/board-eb.h | 171 +++ include/asm-arm/arch-realview/entry-macro.S | 4 +- include/asm-arm/arch-realview/hardware.h | 1 - include/asm-arm/arch-realview/irqs.h | 105 +-- include/asm-arm/arch-realview/platform.h | 170 +--- include/asm-arm/arch-realview/scu.h | 4 +- include/asm-arm/arch-realview/uncompress.h | 2 + include/asm-arm/cacheflush.h | 8 + include/asm-arm/fpstate.h | 9 +- include/asm-arm/hardware/arm_twd.h | 7 +- include/asm-arm/proc-fns.h | 8 + include/asm-arm/smp.h | 16 + include/asm-arm/vfp.h | 34 +- include/asm-arm/vfpmacros.h | 18 +- include/linux/mv643xx.h | 10 +- include/linux/mv643xx_i2c.h | 22 + sound/oss/waveartist.c | 2 +- 207 files changed, 18027 insertions(+), 2679 deletions(-) diff --git a/Documentation/cpu-freq/user-guide.txt b/Documentation/cpu-freq/user-guide.txt index 555c8cf..af3b925 100644 --- a/Documentation/cpu-freq/user-guide.txt +++ b/Documentation/cpu-freq/user-guide.txt @@ -45,6 +45,7 @@ The following ARM processors are supported by cpufreq: ARM Integrator ARM-SA1100 ARM-SA1110 +Intel PXA 1.2 x86 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3a75a0b..c4f0a85 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -33,6 +33,11 @@ config GENERIC_CLOCKEVENTS bool default n +config GENERIC_CLOCKEVENTS_BROADCAST + bool + depends on GENERIC_CLOCKEVENTS + default y if SMP && !LOCAL_TIMERS + config MMU bool default y @@ -163,6 +168,8 @@ config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA select ICST307 + select GENERIC_TIME + select GENERIC_CLOCKEVENTS help This enables support for ARM Ltd RealView boards. @@ -217,6 +224,7 @@ config ARCH_EP93XX bool "EP93xx-based" select ARM_AMBA select ARM_VIC + select GENERIC_GPIO help This enables support for the Cirrus EP93xx series of CPUs. @@ -333,6 +341,16 @@ config ARCH_MXC help Support for Freescale MXC/iMX-based family of processors +config ARCH_ORION + bool "Marvell Orion" + depends on MMU + select PCI + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for Marvell Orion System on Chip family. + config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" help @@ -345,6 +363,7 @@ config ARCH_PXA select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS + select TICK_ONESHOT help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. @@ -366,6 +385,7 @@ config ARCH_SA1100 select ARCH_DISCONTIGMEM_ENABLE select ARCH_MTD_XIP select GENERIC_GPIO + select GENERIC_TIME help Support for StrongARM 11x0 based boards. @@ -409,6 +429,17 @@ config ARCH_OMAP help Support for TI's OMAP platform (OMAP1 and OMAP2). +config ARCH_MSM7X00A + bool "Qualcomm MSM7X00A" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for Qualcomm MSM7X00A based systems. This runs on the ARM11 + apps processor of the MSM7X00A and depends on a shared memory + interface to the ARM9 modem processor which runs the baseband stack + and controls some vital subsystems (clock and power control, etc). + + endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -441,6 +472,8 @@ source "arch/arm/mach-omap1/Kconfig" source "arch/arm/mach-omap2/Kconfig" +source "arch/arm/mach-orion/Kconfig" + source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" @@ -477,6 +510,8 @@ source "arch/arm/mach-davinci/Kconfig" source "arch/arm/mach-ks8695/Kconfig" +source "arch/arm/mach-msm/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool @@ -576,7 +611,7 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL && REALVIEW_MPCORE + depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -610,7 +645,7 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" - depends on SMP && REALVIEW_MPCORE + depends on SMP && REALVIEW_EB_ARM11MP default y help Enable support for local timers on SMP platforms, rather then the @@ -716,7 +751,7 @@ config LEDS ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \ - ARCH_KS8695 + ARCH_KS8695 || MACH_RD88F5182 help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. @@ -867,7 +902,7 @@ config KEXEC endmenu -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX ) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) menu "CPU Frequency scaling" @@ -903,6 +938,12 @@ config CPU_FREQ_IMX If in doubt, say N. +config CPU_FREQ_PXA + bool + depends on CPU_FREQ && ARCH_PXA && PXA25x + default y + select CPU_FREQ_DEFAULT_GOV_USERSPACE + endmenu endif @@ -951,7 +992,7 @@ config FPE_FASTFPE config VFP bool "VFP-format floating point maths" - depends on CPU_V6 || CPU_ARM926T + depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON help Say Y to include VFP support code in the kernel. This is needed if your hardware includes a VFP unit. @@ -961,6 +1002,11 @@ config VFP Say N if your target does not have VFP hardware. +config VFPv3 + bool + depends on VFP + default y if CPU_V7 + endmenu menu "Userspace binary formats" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 18101f5..192ee01 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -43,6 +43,12 @@ config DEBUG_ERRORS you are concerned with the code size or don't want to see these messages. +config DEBUG_STACK_USAGE + bool "Enable stack utilization instrumentation" + depends on DEBUG_KERNEL + help + Enables the display of the minimum amount of free stack which each + task has ever had available in the sysrq-T output. # These options are only for real kernel hackers who want to get their hands dirty. config DEBUG_LL diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 35e56c9..7b8ff66 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -139,6 +139,8 @@ endif machine-$(CONFIG_ARCH_KS8695) := ks8695 incdir-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX3) := mx3 + machine-$(CONFIG_ARCH_ORION) := orion + machine-$(CONFIG_ARCH_MSM7X00A) := msm ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 5cac46a..3c2c8f2 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -623,6 +623,12 @@ proc_types: b __armv4_mmu_cache_off b __armv4_mmu_cache_flush + .word 0x56055310 @ Feroceon + .word 0xfffffff0 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush + @ These match on the architecture ID .word 0x00020000 @ ARMv4T @@ -641,7 +647,7 @@ proc_types: .word 0x000f0000 b __armv4_mmu_cache_on b __armv4_mmu_cache_off - b __armv4_mmu_cache_flush + b __armv5tej_mmu_cache_flush .word 0x0007b000 @ ARMv6 .word 0x000ff000 @@ -821,6 +827,13 @@ iflush: mcr p15, 0, r10, c7, c10, 4 @ drain WB mov pc, lr +__armv5tej_mmu_cache_flush: +1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache + bne 1b + mcr p15, 0, r0, c7, c5, 0 @ flush I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + __armv4_mmu_cache_flush: mov r2, #64*1024 @ default: 32K dcache size (*2) mov r11, #32 @ default: 32 byte line size diff --git a/arch/arm/common/rtctime.c b/arch/arm/common/rtctime.c index bf1075e..f53bca4 100644 --- a/arch/arm/common/rtctime.c +++ b/arch/arm/common/rtctime.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig index 970c8c7..4264e27 100644 --- a/arch/arm/configs/collie_defconfig +++ b/arch/arm/configs/collie_defconfig @@ -367,7 +367,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -CONFIG_MTD_OBSOLETE_CHIPS=y CONFIG_MTD_SHARP=y # CONFIG_MTD_XIP is not set diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig new file mode 100644 index 0000000..ed487b9 --- /dev/null +++ b/arch/arm/configs/eseries_pxa_defconfig @@ -0,0 +1,1499 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.21-hh17 +# Fri Nov 9 20:23:03 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_BOARD_IRQ_MAP_SMALL is not set +CONFIG_BOARD_IRQ_MAP_BIG=y +CONFIG_DMABOUNCE=y + +# +# Intel PXA2xx Implementations +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_IDP is not set +CONFIG_TOSHIBA_TMIO_OHCI=y +CONFIG_ARCH_ESERIES=y +CONFIG_MACH_E330=y +CONFIG_MACH_E740=y +CONFIG_MACH_E750=y +CONFIG_MACH_E400=y +CONFIG_MACH_E800=y +CONFIG_E330_LCD=y +CONFIG_E740_LCD=y +CONFIG_E750_LCD=y +CONFIG_E400_LCD=y +CONFIG_E800_LCD=y +CONFIG_ESERIES_UDC=y +CONFIG_E330_TC6387XB=y +CONFIG_E740_T7L66XB=y +CONFIG_E400_T7L66XB=y +CONFIG_E750_E800_TC6393XB=y +CONFIG_E740_PCMCIA=m +CONFIG_E750_PCMCIA=m +CONFIG_E800_PCMCIA=m +# CONFIG_MACH_A620 is not set +# CONFIG_MACH_A716 is not set +# CONFIG_MACH_A730 is not set +# CONFIG_ARCH_H1900 is not set +# CONFIG_ARCH_H2200 is not set +# CONFIG_MACH_H3900 is not set +# CONFIG_MACH_H4000 is not set +# CONFIG_MACH_H4700 is not set +# CONFIG_MACH_HX2750 is not set +# CONFIG_ARCH_H5400 is not set +# CONFIG_MACH_HIMALAYA is not set +# CONFIG_MACH_HTCUNIVERSAL is not set +# CONFIG_MACH_HTCALPINE is not set +# CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_HTCAPACHE is not set +# CONFIG_MACH_BLUEANGEL is not set + +# +# HTC_HW6X00 +# +# CONFIG_MACH_HTCBEETLES is not set +# CONFIG_MACH_HW6900 is not set +# CONFIG_MACH_HTCATHENA is not set +# CONFIG_ARCH_AXIMX3 is not set +# CONFIG_ARCH_AXIMX5 is not set +# CONFIG_MACH_X50 is not set +# CONFIG_ARCH_ROVERP1 is not set +# CONFIG_ARCH_ROVERP5P is not set +# CONFIG_MACH_XSCALE_PALMLD is not set +# CONFIG_MACH_T3XSCALE is not set +# CONFIG_MACH_RECON is not set +# CONFIG_MACH_GHI270HG is not set +# CONFIG_MACH_GHI270 is not set +# CONFIG_MACH_LOOXC550 is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_MACH_TRIZEPS4 is not set +CONFIG_PXA25x=y + +# +# Linux As Bootloader +# +# CONFIG_LAB is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_IWMMXT=y +CONFIG_XSCALE_PMU=y + +# +# Bus support +# + +# +# PCCARD (PCMCIA/CardBus) support +# +CONFIG_PCCARD=m +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y + +# +# PC-card bridges +# +CONFIG_PCMCIA_PXA2XX=m + +# +# Kernel Features +# +# CONFIG_PREEMPT is not set +# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +# CONFIG_TXTOFFSET_DELTA is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_LEGACY=y +# CONFIG_PM_DEBUG is not set +# CONFIG_DPM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set +# CONFIG_APM_EMULATION is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +# CONFIG_IEEE80211_CRYPT_CCMP is not set +# CONFIG_IEEE80211_CRYPT_TKIP is not set +# CONFIG_IEEE80211_SOFTMAC is not set +CONFIG_WIRELESS_EXT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_SHARP_SL is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +CONFIG_MTD_NAND=m +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_H1900 is not set +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_NANDSIM is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=6144 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=m +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set + +# +# PCMCIA SCSI adapter support +# +# CONFIG_PCMCIA_AHA152X is not set +# CONFIG_PCMCIA_FDOMAIN is not set +# CONFIG_PCMCIA_NINJA_SCSI is not set +# CONFIG_PCMCIA_QLOGIC is not set +# CONFIG_PCMCIA_SYM53C500 is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# PHY device support +# + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +CONFIG_NET_RADIO=y +# CONFIG_NET_WIRELESS_RTNETLINK is not set + +# +# Obsolete Wireless cards support (pre-802.11) +# +# CONFIG_STRIP is not set +# CONFIG_PCMCIA_WAVELAN is not set +# CONFIG_PCMCIA_NETWAVE is not set + +# +# Wireless 802.11 Frequency Hopping cards support +# +# CONFIG_PCMCIA_RAYCS is not set + +# +# Wireless 802.11b ISA/PCI cards support +# +# CONFIG_HERMES is not set +# CONFIG_ATMEL is not set + +# +# Wireless 802.11b Pcmcia/Cardbus cards support +# +# CONFIG_AIRO_CS is not set +# CONFIG_PCMCIA_WL3501 is not set +# CONFIG_USB_ZD1201 is not set +CONFIG_HOSTAP=m +# CONFIG_HOSTAP_FIRMWARE is not set +# CONFIG_HOSTAP_CS is not set +# CONFIG_ACX is not set +CONFIG_NET_WIRELESS=y + +# +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_TSDEV=m +CONFIG_INPUT_TSDEV_SCREEN_X=240 +CONFIG_INPUT_TSDEV_SCREEN_Y=320 +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_LED_TRIGGER is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_PXA is not set +# CONFIG_RS232_SERIAL is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_SA1100_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_TIHTC is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set +# CONFIG_POWER_SUPPLY is not set + +# +# L3 serial bus support +# +# CONFIG_L3 is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_ADC is not set + +# +# Compaq/iPAQ Drivers +# + +# +# Compaq/HP iPAQ Drivers +# +# CONFIG_IPAQ_SLEEVE is not set +# CONFIG_SLEEVE_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_ASIC2 is not set +# CONFIG_HTC_ASIC3 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_BBKEYS is not set +# CONFIG_HTC_ASIC3_DS1WM is not set +# CONFIG_SOC_SAMCOP is not set +# CONFIG_SOC_HAMCOP is not set +# CONFIG_SOC_MQ11XX is not set +CONFIG_SOC_T7L66XB=y +# CONFIG_SOC_TC6387XB is not set +CONFIG_SOC_TC6393XB=y +# CONFIG_SOC_TSC2101 is not set +# CONFIG_SOC_TSC2200 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CORGI=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_IMAGEON is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_PARAMETERS is not set +# CONFIG_FB_MBX is not set +CONFIG_FB_W100=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VSFB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +CONFIG_FONT_ACORN_8x8=y +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set + +# +# Logo configuration +# +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA ARM devices +# +# CONFIG_SND_PXA2XX_AC97 is not set +# CONFIG_SND_RECON is not set + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set + +# +# PCMCIA devices +# +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_PDAUDIOCF is not set + +# +# SoC audio support +# +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC=m + +# +# SoC Platforms +# + +# +# SoC Audio for the Atmel AT91 +# + +# +# SoC Audio for the Intel PXA2xx +# +CONFIG_SND_PXA2XX_SOC=m +CONFIG_SND_PXA2XX_SOC_AC97=m +CONFIG_SND_PXA2XX_SOC_E740_WM9705=m +CONFIG_SND_PXA2XX_SOC_E750_WM9705=m +CONFIG_SND_PXA2XX_SOC_E800_WM9712=m +# CONFIG_SND_PXA2XX_SOC_MAGICIAN is not set +# CONFIG_SND_PXA2XX_SOC_BLUEANGEL is not set +# CONFIG_SND_PXA2XX_SOC_H5000 is not set + +# +# SoC Audio for the Freescale i.MX +# + +# +# SoC Audio for the Samsung S3C24XX +# +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8772 is not set +# CONFIG_SND_SOC_WM8971 is not set +# CONFIG_SND_SOC_WM8956 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8976 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8980 is not set +CONFIG_SND_SOC_WM9705=m +# CONFIG_SND_SOC_WM9713 is not set +CONFIG_SND_SOC_WM9712=m +# CONFIG_SND_SOC_UDA1380 is not set +# CONFIG_SND_SOC_AK4535 is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=m +CONFIG_USB_DEBUG=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_TOUCHSCREEN is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_ATI_REMOTE2 is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set +# CONFIG_USB_GTCO is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_NET2280 is not set +CONFIG_USB_GADGET_PXA2XX=y +CONFIG_USB_PXA2XX=y +# CONFIG_USB_PXA2XX_SMALL is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_MQ11XX is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +# CONFIG_USB_ZERO is not set +CONFIG_USB_ETH=y +# CONFIG_USB_ETH_RNDIS is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_CHAR is not set +# CONFIG_USB_PXA2XX_GPIO is not set + +# +# MMC/SD Card support +# +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_PXA is not set +CONFIG_MMC_TMIO=y +# CONFIG_MMC_SAMCOP is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig index add03c9..988b4d1 100644 --- a/arch/arm/configs/iop13xx_defconfig +++ b/arch/arm/configs/iop13xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22 -# Thu Jul 19 15:57:52 2007 +# Linux kernel version: 2.6.24-rc5 +# Wed Dec 12 16:11:03 2007 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -26,15 +26,11 @@ CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SWAP=y @@ -45,10 +41,15 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set # CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y # CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y @@ -69,7 +70,6 @@ CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y @@ -130,6 +130,7 @@ CONFIG_ARCH_IOP13XX=y # CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -151,9 +152,12 @@ CONFIG_MACH_IQ81340SC=y CONFIG_MACH_IQ81340MC=y # -# IOP13XX IMU Support +# Boot options +# + +# +# Power management # -# CONFIG_IOP_IMU is not set CONFIG_PLAT_IOP=y # @@ -185,10 +189,7 @@ CONFIG_PCI=y CONFIG_PCI_SYSCALL=y CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set - -# -# PCCARD (PCMCIA/CardBus) support -# +CONFIG_PCI_LEGACY=y # CONFIG_PCCARD is not set # @@ -207,6 +208,7 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 @@ -246,6 +248,7 @@ CONFIG_BINFMT_AOUT=y # Power management options # # CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y # # Networking @@ -285,6 +288,7 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set @@ -324,10 +328,6 @@ CONFIG_IPV6=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -356,6 +356,7 @@ CONFIG_IPV6=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set @@ -383,6 +384,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -423,6 +425,7 @@ CONFIG_MTD_PHYSMAP_START=0xfa000000 CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -463,6 +466,11 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set # # SCSI device support @@ -499,12 +507,9 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=y -CONFIG_SCSI_SAS_ATTRS=y # CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set @@ -515,6 +520,7 @@ CONFIG_SCSI_SAS_ATTRS=y # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set @@ -555,14 +561,8 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_ZERO is not set # CONFIG_DM_MULTIPATH is not set # CONFIG_DM_DELAY is not set - -# -# Fusion MPT device support -# +# CONFIG_DM_UEVENT is not set # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set # # IEEE 1394 (FireWire) support @@ -577,6 +577,8 @@ CONFIG_NETDEVICES=y # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_IP1000 is not set # CONFIG_ARCNET is not set # CONFIG_NET_ETHERNET is not set CONFIG_NETDEV_1000=y @@ -585,6 +587,7 @@ CONFIG_NETDEV_1000=y CONFIG_E1000=y CONFIG_E1000_NAPI=y # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -592,6 +595,7 @@ CONFIG_E1000_NAPI=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set @@ -600,11 +604,14 @@ CONFIG_E1000_NAPI=y CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set # CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set # CONFIG_TR is not set # @@ -639,7 +646,6 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -688,12 +694,10 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y @@ -758,9 +762,9 @@ CONFIG_I2C_IOP3XX=y # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -768,12 +772,13 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -787,14 +792,17 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set @@ -806,29 +814,18 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -CONFIG_MISC_DEVICES=y -# CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set +# CONFIG_WATCHDOG is not set # -# LED drivers +# Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# LED Triggers +# Multifunction device drivers # +# CONFIG_MFD_SM501 is not set # # Multimedia devices @@ -840,14 +837,16 @@ CONFIG_DAB=y # # Graphics support # +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -# CONFIG_FB is not set # # Console display driver support @@ -862,6 +861,7 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -877,16 +877,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set - -# -# Real Time Clock -# +# CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set +CONFIG_DMADEVICES=y # -# DMA Engine support +# DMA Devices # +CONFIG_INTEL_IOP_ADMA=y CONFIG_DMA_ENGINE=y # @@ -895,12 +894,6 @@ CONFIG_DMA_ENGINE=y # CONFIG_NET_DMA is not set # -# DMA Devices -# -# CONFIG_INTEL_IOATDMA is not set -CONFIG_INTEL_IOP_ADMA=y - -# # File systems # CONFIG_EXT2_FS=y @@ -912,7 +905,6 @@ CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_SECURITY is not set # CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set @@ -952,7 +944,6 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -969,10 +960,12 @@ CONFIG_ECRYPT_FS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set CONFIG_CRAMFS=y @@ -981,10 +974,7 @@ CONFIG_CRAMFS=y # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set @@ -1037,10 +1027,6 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set @@ -1081,21 +1067,16 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set - -# -# Distributed Lock Manager -# # CONFIG_DLM is not set - -# -# Profiling support -# +CONFIG_INSTRUMENTATION=y # CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set @@ -1104,6 +1085,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_FRAME_POINTER=y +# CONFIG_SAMPLES is not set CONFIG_DEBUG_USER=y # @@ -1112,6 +1094,7 @@ CONFIG_DEBUG_USER=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y CONFIG_ASYNC_MEMCPY=y @@ -1136,6 +1119,7 @@ CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set @@ -1150,11 +1134,13 @@ CONFIG_CRYPTO_TEA=y CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_KHAZAD=y CONFIG_CRYPTO_ANUBIS=y +# CONFIG_CRYPTO_SEED is not set CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set CONFIG_CRYPTO_HW=y # diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig index 027aef2..83f40d4 100644 --- a/arch/arm/configs/iop32x_defconfig +++ b/arch/arm/configs/iop32x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22 -# Thu Jul 19 16:00:36 2007 +# Linux kernel version: 2.6.24-rc5 +# Wed Dec 12 15:49:08 2007 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -26,15 +26,11 @@ CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y @@ -45,9 +41,14 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set # CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y # CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y @@ -69,7 +70,6 @@ CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y @@ -130,6 +130,7 @@ CONFIG_ARCH_IOP32X=y # CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -153,6 +154,15 @@ CONFIG_ARCH_IQ80321=y CONFIG_ARCH_IQ31244=y CONFIG_MACH_N2100=y CONFIG_IOP3XX_ATU=y +# CONFIG_MACH_EM7210 is not set + +# +# Boot options +# + +# +# Power management +# CONFIG_PLAT_IOP=y # @@ -182,11 +192,8 @@ CONFIG_XSCALE_PMU=y CONFIG_PCI=y CONFIG_PCI_SYSCALL=y # CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set # @@ -205,6 +212,7 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 @@ -244,6 +252,7 @@ CONFIG_BINFMT_AOUT=y # Power management options # # CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y # # Networking @@ -282,6 +291,7 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set @@ -321,10 +331,6 @@ CONFIG_IPV6=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -353,6 +359,7 @@ CONFIG_IPV6=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set @@ -382,6 +389,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -417,6 +425,7 @@ CONFIG_MTD_PHYSMAP_START=0x0 CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -459,6 +468,11 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set # CONFIG_IDE is not set # @@ -496,12 +510,9 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set @@ -512,6 +523,7 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set @@ -576,6 +588,7 @@ CONFIG_SATA_VITESSE=y # CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_NETCELL is not set # CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set # CONFIG_PATA_PDC_OLD is not set @@ -606,14 +619,8 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_ZERO is not set # CONFIG_DM_MULTIPATH is not set # CONFIG_DM_DELAY is not set - -# -# Fusion MPT device support -# +# CONFIG_DM_UEVENT is not set # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set # # IEEE 1394 (FireWire) support @@ -628,6 +635,8 @@ CONFIG_NETDEVICES=y # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_IP1000 is not set # CONFIG_ARCNET is not set # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y @@ -641,13 +650,16 @@ CONFIG_MII=y # CONFIG_DM9000 is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set # CONFIG_EEPRO100 is not set CONFIG_E100=y # CONFIG_FEALNX is not set @@ -667,6 +679,7 @@ CONFIG_NETDEV_1000=y CONFIG_E1000=y CONFIG_E1000_NAPI=y # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -675,6 +688,7 @@ CONFIG_R8169=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set @@ -683,11 +697,14 @@ CONFIG_R8169=y CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set # CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set # CONFIG_TR is not set # @@ -703,7 +720,6 @@ CONFIG_NETDEV_10000=y # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET_MII is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set @@ -732,7 +748,6 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -781,12 +796,10 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y @@ -852,9 +865,9 @@ CONFIG_I2C_IOP3XX=y # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -862,12 +875,13 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -881,14 +895,17 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set @@ -900,29 +917,18 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -CONFIG_MISC_DEVICES=y -# CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set +# CONFIG_WATCHDOG is not set # -# LED drivers +# Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# LED Triggers +# Multifunction device drivers # +# CONFIG_MFD_SM501 is not set # # Multimedia devices @@ -935,14 +941,16 @@ CONFIG_DAB=y # # Graphics support # +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -# CONFIG_FB is not set # # Console display driver support @@ -957,6 +965,7 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set # # USB Input Devices @@ -1013,6 +1022,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set @@ -1070,28 +1080,66 @@ CONFIG_USB_MON=y # # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # -# Real Time Clock +# RTC interfaces # -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set # -# DMA Engine support +# I2C RTC drivers # -CONFIG_DMA_ENGINE=y +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_RS5C372=y +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set # -# DMA Clients +# SPI RTC drivers # -CONFIG_NET_DMA=y + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_DMADEVICES=y # # DMA Devices # -# CONFIG_INTEL_IOATDMA is not set CONFIG_INTEL_IOP_ADMA=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y # # File systems @@ -1105,7 +1153,6 @@ CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_SECURITY is not set # CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set @@ -1145,7 +1192,6 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -1162,10 +1208,12 @@ CONFIG_ECRYPT_FS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set CONFIG_CRAMFS=y @@ -1174,10 +1222,7 @@ CONFIG_CRAMFS=y # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set @@ -1224,26 +1269,17 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# # CONFIG_NLS is not set - -# -# Distributed Lock Manager -# # CONFIG_DLM is not set - -# -# Profiling support -# +CONFIG_INSTRUMENTATION=y # CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set @@ -1270,10 +1306,13 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y # CONFIG_FORCED_INLINING is not set +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set CONFIG_DEBUG_USER=y # CONFIG_DEBUG_ERRORS is not set CONFIG_DEBUG_LL=y @@ -1285,6 +1324,7 @@ CONFIG_DEBUG_LL=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y CONFIG_ASYNC_MEMCPY=y @@ -1309,6 +1349,7 @@ CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set @@ -1323,11 +1364,13 @@ CONFIG_CRYPTO_TEA=y CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_KHAZAD=y CONFIG_CRYPTO_ANUBIS=y +# CONFIG_CRYPTO_SEED is not set CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set CONFIG_CRYPTO_HW=y # diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig index 721ee64..917afb5 100644 --- a/arch/arm/configs/iop33x_defconfig +++ b/arch/arm/configs/iop33x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22 -# Thu Jul 19 16:05:59 2007 +# Linux kernel version: 2.6.24-rc5 +# Wed Dec 12 16:11:27 2007 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -26,15 +26,11 @@ CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y @@ -45,9 +41,14 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set # CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y # CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y @@ -69,7 +70,6 @@ CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y @@ -130,6 +130,7 @@ CONFIG_ARCH_IOP33X=y # CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -150,6 +151,14 @@ CONFIG_IOP3XX_ATU=y # CONFIG_ARCH_IQ80331=y CONFIG_MACH_IQ80332=y + +# +# Boot options +# + +# +# Power management +# CONFIG_PLAT_IOP=y # @@ -179,11 +188,8 @@ CONFIG_XSCALE_PMU=y CONFIG_PCI=y CONFIG_PCI_SYSCALL=y # CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set # @@ -202,6 +208,7 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 @@ -241,6 +248,7 @@ CONFIG_BINFMT_AOUT=y # Power management options # # CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y # # Networking @@ -279,6 +287,7 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set @@ -318,10 +327,6 @@ CONFIG_IPV6=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -350,6 +355,7 @@ CONFIG_IPV6=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set @@ -379,6 +385,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -419,6 +426,7 @@ CONFIG_MTD_PHYSMAP_START=0x0 CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -459,6 +467,11 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set # CONFIG_IDE is not set # @@ -496,12 +509,9 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set @@ -512,6 +522,7 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set @@ -552,14 +563,8 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_ZERO is not set # CONFIG_DM_MULTIPATH is not set # CONFIG_DM_DELAY is not set - -# -# Fusion MPT device support -# +# CONFIG_DM_UEVENT is not set # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set # # IEEE 1394 (FireWire) support @@ -574,6 +579,8 @@ CONFIG_NETDEVICES=y # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_IP1000 is not set # CONFIG_ARCNET is not set # CONFIG_NET_ETHERNET is not set CONFIG_NETDEV_1000=y @@ -582,6 +589,7 @@ CONFIG_NETDEV_1000=y CONFIG_E1000=y CONFIG_E1000_NAPI=y # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -589,6 +597,7 @@ CONFIG_E1000_NAPI=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set @@ -597,11 +606,14 @@ CONFIG_E1000_NAPI=y CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set # CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set # CONFIG_TR is not set # @@ -636,7 +648,6 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -685,12 +696,10 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y @@ -755,9 +764,9 @@ CONFIG_I2C_IOP3XX=y # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -765,12 +774,13 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -784,14 +794,17 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set @@ -803,29 +816,18 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -CONFIG_MISC_DEVICES=y -# CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set +# CONFIG_WATCHDOG is not set # -# LED drivers +# Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# LED Triggers +# Multifunction device drivers # +# CONFIG_MFD_SM501 is not set # # Multimedia devices @@ -837,14 +839,16 @@ CONFIG_DAB=y # # Graphics support # +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -# CONFIG_FB is not set # # Console display driver support @@ -859,6 +863,7 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -874,16 +879,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set - -# -# Real Time Clock -# +# CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set +CONFIG_DMADEVICES=y # -# DMA Engine support +# DMA Devices # +CONFIG_INTEL_IOP_ADMA=y CONFIG_DMA_ENGINE=y # @@ -892,12 +896,6 @@ CONFIG_DMA_ENGINE=y CONFIG_NET_DMA=y # -# DMA Devices -# -# CONFIG_INTEL_IOATDMA is not set -CONFIG_INTEL_IOP_ADMA=y - -# # File systems # CONFIG_EXT2_FS=y @@ -909,7 +907,6 @@ CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_SECURITY is not set # CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set @@ -949,7 +946,6 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -969,10 +965,7 @@ CONFIG_CRAMFS=y # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set @@ -1019,26 +1012,17 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# # CONFIG_NLS is not set - -# -# Distributed Lock Manager -# # CONFIG_DLM is not set - -# -# Profiling support -# +CONFIG_INSTRUMENTATION=y # CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set @@ -1065,10 +1049,13 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y # CONFIG_FORCED_INLINING is not set +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set CONFIG_DEBUG_USER=y # CONFIG_DEBUG_ERRORS is not set CONFIG_DEBUG_LL=y @@ -1079,6 +1066,7 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y CONFIG_ASYNC_MEMCPY=y diff --git a/arch/arm/configs/littleton_defconfig b/arch/arm/configs/littleton_defconfig new file mode 100644 index 0000000..1db4969 --- /dev/null +++ b/arch/arm/configs/littleton_defconfig @@ -0,0 +1,783 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24-rc5 +# Fri Dec 21 11:06:19 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Intel PXA2xx/PXA3xx Implementations +# + +# +# Supported PXA3xx Processor Variants +# +CONFIG_CPU_PXA300=y +CONFIG_CPU_PXA310=y +# CONFIG_CPU_PXA320 is not set +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_MACH_TRIZEPS4 is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_ZYLONITE is not set +CONFIG_MACH_LITTLETON=y +# CONFIG_MACH_ARMCORE is not set +CONFIG_PXA3xx=y +CONFIG_PXA_SSP=y + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSC3=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_IO_36=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_IWMMXT=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=64M" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +# CONFIG_SMC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_PARAMETERS is not set +# CONFIG_FB_MBX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_DIRECTIO=y +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set +# CONFIG_INSTRUMENTATION is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_ECB is not set +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig new file mode 100644 index 0000000..ae4c5e6 --- /dev/null +++ b/arch/arm/configs/msm_defconfig @@ -0,0 +1,895 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23 +# Wed Nov 7 01:36:45 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_GPIOS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_GOLDFISH is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_ARCH_MSM7X00A=y + +# +# Boot options +# + +# +# Power management +# + +# +# MSM7200 Board Type +# +CONFIG_MACH_HALIBUT=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +# CONFIG_SERIAL_MSM_NOINIT is not set +CONFIG_MSM_SMD=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_RESOURCES_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=64M console=ttyMSM,115200n8" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +CONFIG_SUSPEND_UP_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set +CONFIG_MTD_MSM_NAND=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_GOLDFISH_NAND is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +CONFIG_MSM_RMNET=y +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_MEP is not set +CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI=y +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_UINPUT is not set +CONFIG_INPUT_GPIO=y + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DCC_TTY=y +# CONFIG_GOLDFISH_TTY is not set +CONFIG_BINDER=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +CONFIG_I2C_MSM=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +CONFIG_SENSORS_PCA9633=y +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +CONFIG_SENSORS_AKM8976=y +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_HWMON is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +CONFIG_LOW_MEMORY_KILLER=y + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_MSM=y +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# USB Function Support +# +CONFIG_USB_FUNCTION=y +CONFIG_USB_FUNCTION_MSM_HSUSB=y +# CONFIG_USB_FUNCTION_NULL is not set +# CONFIG_USB_FUNCTION_ZERO is not set +# CONFIG_USB_FUNCTION_LOOPBACK is not set +CONFIG_USB_FUNCTION_ADB=y +# CONFIG_MMC is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Android +# +# CONFIG_ANDROID_GADGET is not set +# CONFIG_ANDROID_RAM_CONSOLE is not set +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_VIBRATOR=y + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FRAME_POINTER=y +# CONFIG_FORCED_INLINING is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion_defconfig new file mode 100644 index 0000000..17a55de --- /dev/null +++ b/arch/arm/configs/orion_defconfig @@ -0,0 +1,1384 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24-rc3 +# Wed Nov 28 15:13:57 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +CONFIG_ARCH_ORION=y +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Orion Implementations +# +CONFIG_MACH_DB88F5281=y +CONFIG_MACH_RD88F5182=y +CONFIG_MACH_KUROBOX_PRO=y +CONFIG_MACH_DNS323=y +CONFIG_MACH_TS209=y + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +CONFIG_CPU_FEROCEON_OLD_ID=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +CONFIG_NFTL=y +# CONFIG_NFTL_RW is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_ORION=y +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +# CONFIG_MV_SATA_SUPPORT_ATAPI is not set +# CONFIG_MV_SATA_ENABLE_1MB_IOS is not set +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_IP1000 is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=y +CONFIG_SKY2=y +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_TIGON3=y +# CONFIG_BNX2 is not set +CONFIG_MV643XX_ETH=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +CONFIG_I2C_MV64XXX=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_SL811_HCD=y +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_GPIO is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_RS5C372=y +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +CONFIG_RTC_DRV_M41T80=y +# CONFIG_RTC_DRV_M41T80_WDT is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_FRAME_POINTER=y +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/kernel/dma-isa.c b/arch/arm/kernel/dma-isa.c index 0a3e9ad..2f080a3 100644 --- a/arch/arm/kernel/dma-isa.c +++ b/arch/arm/kernel/dma-isa.c @@ -216,7 +216,7 @@ void __init isa_init_dma(dma_t *dma) request_dma(DMA_ISA_CASCADE, "cascade"); - for (i = 0; i < sizeof(dma_resources) / sizeof(dma_resources[0]); i++) + for (i = 0; i < ARRAY_SIZE(dma_resources); i++) request_resource(&ioport_resource, dma_resources + i); } } diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 29dec08..d65b072 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -11,8 +11,8 @@ * * Low-level vector interface routines * - * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes - * it to save wrong values... Be aware! + * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction + * that causes it to save wrong values... Be aware! */ #include diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 33e6cc2..6c90c50 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -72,7 +72,7 @@ no_work_pending: ldr r1, [sp, #S_PSR] @ get calling cpsr ldr lr, [sp, #S_PC]! @ get pc msr spsr_cxsf, r1 @ save in spsr_svc - ldmdb sp, {r0 - lr}^ @ get calling r1 - lr + ldmdb sp, {r0 - lr}^ @ get calling r0 - lr mov r0, r0 add sp, sp, #S_FRAME_SIZE - S_PC movs pc, lr @ return & move spsr_svc into cpsr diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index bf56eb3..dd37901 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -62,6 +62,7 @@ extern int root_mountflags; extern void _stext, _text, _etext, __data_start, _edata, _end; unsigned int processor_id; +EXPORT_SYMBOL(processor_id); unsigned int __machine_arch_type; EXPORT_SYMBOL(__machine_arch_type); diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index eafbb2b..ec80a23 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -300,6 +300,11 @@ asmlinkage void __cpuinit secondary_start_kernel(void) cpu_set(cpu, cpu_online_map); /* + * Setup a dummy timer for this CPU if CONFIG_LOCAL_TIMERS is not set. + */ + dummy_timer_setup(cpu); + + /* * Setup local timer for this CPU. */ local_timer_setup(cpu); @@ -454,6 +459,27 @@ int smp_call_function(void (*func)(void *info), void *info, int retry, } EXPORT_SYMBOL_GPL(smp_call_function); +int smp_call_function_single(int cpu, void (*func)(void *info), void *info, + int retry, int wait) +{ + /* prevent preemption and reschedule on another processor */ + int current_cpu = get_cpu(); + int ret = 0; + + if (cpu == current_cpu) { + local_irq_disable(); + func(info); + local_irq_enable(); + } else + ret = smp_call_function_on_cpu(func, info, retry, wait, + cpumask_of_cpu(cpu)); + + put_cpu(); + + return ret; +} +EXPORT_SYMBOL_GPL(smp_call_function_single); + void show_ipi_list(struct seq_file *p) { unsigned int cpu; @@ -481,8 +507,7 @@ void show_local_irqs(struct seq_file *p) static void ipi_timer(void) { irq_enter(); - profile_tick(CPU_PROFILING); - update_process_times(user_mode(get_irq_regs())); + local_timer_interrupt(); irq_exit(); } @@ -621,6 +646,11 @@ void smp_send_timer(void) send_ipi_message(mask, IPI_TIMER); } +void smp_timer_broadcast(cpumask_t mask) +{ + send_ipi_message(mask, IPI_TIMER); +} + void smp_send_stop(void) { cpumask_t mask = cpu_online_map; diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 70b2c78..ea5eade 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -3,6 +3,7 @@ * Core routines for Cirrus EP93xx chips. * * Copyright (C) 2006 Lennert Buytenhek + * Copyright (C) 2007 Herbert Valerio Riedel * * Thanks go to Michael Burian and Ray Lehtiniemi for their key * role in the ep93xx linux community. @@ -21,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -157,38 +157,41 @@ static unsigned char gpio_int_enabled[3]; static unsigned char gpio_int_type1[3]; static unsigned char gpio_int_type2[3]; -static void update_gpio_int_params(int abf) +/* Port ordering is: A B F */ +static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; +static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; +static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; +static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c }; + +static void update_gpio_int_params(unsigned port) { - if (abf == 0) { - __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE); - __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2); - __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1); - __raw_writeb(gpio_int_unmasked[0] & gpio_int_enabled[0], EP93XX_GPIO_A_INT_ENABLE); - } else if (abf == 1) { - __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE); - __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2); - __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1); - __raw_writeb(gpio_int_unmasked[1] & gpio_int_enabled[1], EP93XX_GPIO_B_INT_ENABLE); - } else if (abf == 2) { - __raw_writeb(0, EP93XX_GPIO_F_INT_ENABLE); - __raw_writeb(gpio_int_type2[2], EP93XX_GPIO_F_INT_TYPE2); - __raw_writeb(gpio_int_type1[2], EP93XX_GPIO_F_INT_TYPE1); - __raw_writeb(gpio_int_unmasked[2] & gpio_int_enabled[2], EP93XX_GPIO_F_INT_ENABLE); - } else { - BUG(); - } -} + BUG_ON(port > 2); + + __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port])); + __raw_writeb(gpio_int_type2[port], + EP93XX_GPIO_REG(int_type2_register_offset[port])); -static unsigned char data_register_offset[8] = { - 0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40, + __raw_writeb(gpio_int_type1[port], + EP93XX_GPIO_REG(int_type1_register_offset[port])); + + __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], + EP93XX_GPIO_REG(int_en_register_offset[port])); +} + +/* Port ordering is: A B F D E C G H */ +static const u8 data_register_offset[8] = { + 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40, }; -static unsigned char data_direction_register_offset[8] = { - 0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44, +static const u8 data_direction_register_offset[8] = { + 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44, }; -void gpio_line_config(int line, int direction) +#define GPIO_IN 0 +#define GPIO_OUT 1 + +static void ep93xx_gpio_set_direction(unsigned line, int direction) { unsigned int data_direction_register; unsigned long flags; @@ -199,14 +202,10 @@ void gpio_line_config(int line, int direction) local_irq_save(flags); if (direction == GPIO_OUT) { - if (line >= 0 && line < 16) { - /* Port A/B. */ + if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) { + /* Port A/B/F */ gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); update_gpio_int_params(line >> 3); - } else if (line >= 40 && line < 48) { - /* Port F. */ - gpio_int_unmasked[2] &= ~(1 << (line & 7)); - update_gpio_int_params(2); } v = __raw_readb(data_direction_register); @@ -219,39 +218,58 @@ void gpio_line_config(int line, int direction) } local_irq_restore(flags); } -EXPORT_SYMBOL(gpio_line_config); -int gpio_line_get(int line) +int gpio_direction_input(unsigned gpio) +{ + if (gpio > EP93XX_GPIO_LINE_MAX) + return -EINVAL; + + ep93xx_gpio_set_direction(gpio, GPIO_IN); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned gpio, int value) +{ + if (gpio > EP93XX_GPIO_LINE_MAX) + return -EINVAL; + + gpio_set_value(gpio, value); + ep93xx_gpio_set_direction(gpio, GPIO_OUT); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + +int gpio_get_value(unsigned gpio) { unsigned int data_register; - data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]); + data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]); - return !!(__raw_readb(data_register) & (1 << (line & 7))); + return !!(__raw_readb(data_register) & (1 << (gpio & 7))); } -EXPORT_SYMBOL(gpio_line_get); +EXPORT_SYMBOL(gpio_get_value); -void gpio_line_set(int line, int value) +void gpio_set_value(unsigned gpio, int value) { unsigned int data_register; unsigned long flags; unsigned char v; - data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]); + data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]); local_irq_save(flags); - if (value == EP93XX_GPIO_HIGH) { - v = __raw_readb(data_register); - v |= 1 << (line & 7); - __raw_writeb(v, data_register); - } else if (value == EP93XX_GPIO_LOW) { - v = __raw_readb(data_register); - v &= ~(1 << (line & 7)); - __raw_writeb(v, data_register); - } + v = __raw_readb(data_register); + if (value) + v |= 1 << (gpio & 7); + else + v &= ~(1 << (gpio & 7)); + __raw_writeb(v, data_register); local_irq_restore(flags); } -EXPORT_SYMBOL(gpio_line_set); +EXPORT_SYMBOL(gpio_set_value); /************************************************************************* @@ -265,47 +283,67 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) status = __raw_readb(EP93XX_GPIO_A_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { - desc = irq_desc + IRQ_EP93XX_GPIO(0) + i; - desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc); + int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; + desc = irq_desc + gpio_irq; + desc_handle_irq(gpio_irq, desc); } } status = __raw_readb(EP93XX_GPIO_B_INT_STATUS); for (i = 0; i < 8; i++) { if (status & (1 << i)) { - desc = irq_desc + IRQ_EP93XX_GPIO(8) + i; - desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc); + int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; + desc = irq_desc + gpio_irq; + desc_handle_irq(gpio_irq, desc); } } } static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) { - int gpio_irq = IRQ_EP93XX_GPIO(16) + (((irq + 1) & 7) ^ 4); + /* + * map discontiguous hw irq range to continous sw irq range: + * + * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) + */ + int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ + int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; desc_handle_irq(gpio_irq, irq_desc + gpio_irq); } +static void ep93xx_gpio_irq_ack(unsigned int irq) +{ + int line = irq_to_gpio(irq); + int port = line >> 3; + int port_mask = 1 << (line & 7); + + if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { + gpio_int_type2[port] ^= port_mask; /* switch edge direction */ + update_gpio_int_params(port); + } + + __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); +} + static void ep93xx_gpio_irq_mask_ack(unsigned int irq) { - int line = irq - IRQ_EP93XX_GPIO(0); + int line = irq_to_gpio(irq); int port = line >> 3; + int port_mask = 1 << (line & 7); - gpio_int_unmasked[port] &= ~(1 << (line & 7)); + if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) + gpio_int_type2[port] ^= port_mask; /* switch edge direction */ + + gpio_int_unmasked[port] &= ~port_mask; update_gpio_int_params(port); - if (port == 0) { - __raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK); - } else if (port == 1) { - __raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK); - } else if (port == 2) { - __raw_writel(1 << (line & 7), EP93XX_GPIO_F_INT_ACK); - } + __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); } static void ep93xx_gpio_irq_mask(unsigned int irq) { - int line = irq - IRQ_EP93XX_GPIO(0); + int line = irq_to_gpio(irq); int port = line >> 3; gpio_int_unmasked[port] &= ~(1 << (line & 7)); @@ -314,7 +352,7 @@ static void ep93xx_gpio_irq_mask(unsigned int irq) static void ep93xx_gpio_irq_unmask(unsigned int irq) { - int line = irq - IRQ_EP93XX_GPIO(0); + int line = irq_to_gpio(irq); int port = line >> 3; gpio_int_unmasked[port] |= 1 << (line & 7); @@ -329,38 +367,54 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq) */ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) { - int port; - int line; - - line = irq - IRQ_EP93XX_GPIO(0); - if (line >= 0 && line < 16) { - gpio_line_config(line, GPIO_IN); - } else { - gpio_line_config(EP93XX_GPIO_LINE_F(line-16), GPIO_IN); + struct irq_desc *desc = irq_desc + irq; + const int gpio = irq_to_gpio(irq); + const int port = gpio >> 3; + const int port_mask = 1 << (gpio & 7); + + ep93xx_gpio_set_direction(gpio, GPIO_IN); + + switch (type) { + case IRQT_RISING: + gpio_int_type1[port] |= port_mask; + gpio_int_type2[port] |= port_mask; + desc->handle_irq = handle_edge_irq; + break; + case IRQT_FALLING: + gpio_int_type1[port] |= port_mask; + gpio_int_type2[port] &= ~port_mask; + desc->handle_irq = handle_edge_irq; + break; + case IRQT_HIGH: + gpio_int_type1[port] &= ~port_mask; + gpio_int_type2[port] |= port_mask; + desc->handle_irq = handle_level_irq; + break; + case IRQT_LOW: + gpio_int_type1[port] &= ~port_mask; + gpio_int_type2[port] &= ~port_mask; + desc->handle_irq = handle_level_irq; + break; + case IRQT_BOTHEDGE: + gpio_int_type1[port] |= port_mask; + /* set initial polarity based on current input level */ + if (gpio_get_value(gpio)) + gpio_int_type2[port] &= ~port_mask; /* falling */ + else + gpio_int_type2[port] |= port_mask; /* rising */ + desc->handle_irq = handle_edge_irq; + break; + default: + pr_err("ep93xx: failed to set irq type %d for gpio %d\n", + type, gpio); + return -EINVAL; } - port = line >> 3; - line &= 7; - - if (type & IRQT_RISING) { - gpio_int_enabled[port] |= 1 << line; - gpio_int_type1[port] |= 1 << line; - gpio_int_type2[port] |= 1 << line; - } else if (type & IRQT_FALLING) { - gpio_int_enabled[port] |= 1 << line; - gpio_int_type1[port] |= 1 << line; - gpio_int_type2[port] &= ~(1 << line); - } else if (type & IRQT_HIGH) { - gpio_int_enabled[port] |= 1 << line; - gpio_int_type1[port] &= ~(1 << line); - gpio_int_type2[port] |= 1 << line; - } else if (type & IRQT_LOW) { - gpio_int_enabled[port] |= 1 << line; - gpio_int_type1[port] &= ~(1 << line); - gpio_int_type2[port] &= ~(1 << line); - } else { - gpio_int_enabled[port] &= ~(1 << line); - } + gpio_int_enabled[port] |= port_mask; + + desc->status &= ~IRQ_TYPE_SENSE_MASK; + desc->status |= type & IRQ_TYPE_SENSE_MASK; + update_gpio_int_params(port); return 0; @@ -368,7 +422,8 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) static struct irq_chip ep93xx_gpio_irq_chip = { .name = "GPIO", - .ack = ep93xx_gpio_irq_mask_ack, + .ack = ep93xx_gpio_irq_ack, + .mask_ack = ep93xx_gpio_irq_mask_ack, .mask = ep93xx_gpio_irq_mask, .unmask = ep93xx_gpio_irq_unmask, .set_type = ep93xx_gpio_irq_type, @@ -377,15 +432,16 @@ static struct irq_chip ep93xx_gpio_irq_chip = { void __init ep93xx_init_irq(void) { - int irq; + int gpio_irq; vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); - for (irq = IRQ_EP93XX_GPIO(0); irq <= IRQ_EP93XX_GPIO(23); irq++) { - set_irq_chip(irq, &ep93xx_gpio_irq_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); + for (gpio_irq = gpio_to_irq(0); + gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { + set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); + set_irq_handler(gpio_irq, handle_level_irq); + set_irq_flags(gpio_irq, IRQF_VALID); } set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index d4d8134..d55fa4e 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -440,7 +440,7 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) return 1; } -static irqreturn_t v3_irq(int irq, void *devid) +static irqreturn_t v3_irq(int dummy, void *devid) { #ifdef CONFIG_DEBUG_LL struct pt_regs *regs = get_irq_regs(); @@ -448,8 +448,10 @@ static irqreturn_t v3_irq(int irq, void *devid) unsigned long instr = *(unsigned long *)pc; char buf[128]; - sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", irq, - pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255, + sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " + "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr, + __raw_readl(SC_LBFADDR), + __raw_readl(SC_LBFCODE) & 255, v3_readb(V3_LB_ISTAT)); printascii(buf); #endif diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 2b086ab..6309f9a 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -3,7 +3,7 @@ * * Board support code for the GLAN Tank. * - * Copyright (C) 2006 Martin Michlmayr + * Copyright (C) 2006, 2007 Martin Michlmayr * Copyright (C) 2006 Lennert Buytenhek * * This program is free software; you can redistribute it and/or modify it @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -166,6 +167,13 @@ static struct platform_device glantank_serial_device = { .resource = &glantank_uart_resource, }; +static struct i2c_board_info __initdata glantank_i2c_devices[] = { + { + I2C_BOARD_INFO("rtc-rs5c372", 0x32), + .type = "rs5c372a", + }, +}; + static void glantank_power_off(void) { __raw_writeb(0x01, 0xfe8d0004); @@ -183,6 +191,9 @@ static void __init glantank_init_machine(void) platform_device_register(&iop3xx_dma_0_channel); platform_device_register(&iop3xx_dma_1_channel); + i2c_register_board_info(0, glantank_i2c_devices, + ARRAY_SIZE(glantank_i2c_devices)); + pm_power_off = glantank_power_off; } diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index 16356ff..5fea5a1 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c index 7a85ced..d3a779a 100644 --- a/arch/arm/mach-ixp23xx/espresso.c +++ b/arch/arm/mach-ixp23xx/espresso.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -40,7 +39,6 @@ #include #include #include -#include #include static int __init espresso_pci_init(void) diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index c41a6b5..5c5d4d6 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -44,7 +43,6 @@ #include #include #include -#include #include /* diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index e356449..f0f70ba 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -44,7 +43,6 @@ #include #include #include -#include #include /* diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 61b2dfc..e774447 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -189,6 +189,20 @@ config IXP4XX_INDIRECT_PCI need to use the indirect method instead. If you don't know what you need, leave this option unselected. +config IXP4XX_QMGR + tristate "IXP4xx Queue Manager support" + help + This driver supports IXP4xx built-in hardware queue manager + and is automatically selected by Ethernet and HSS drivers. + +config IXP4XX_NPE + tristate "IXP4xx Network Processor Engine support" + select HOTPLUG + select FW_LOADER + help + This driver supports IXP4xx built-in network coprocessors + and is automatically selected by Ethernet and HSS drivers. + endmenu endif diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index 77e00ad..4bb97e1 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -30,3 +30,5 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index d5008d8..10b41c6 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -177,6 +177,31 @@ static struct platform_device ixdp425_uart = { .resource = ixdp425_uart_resources }; +/* Built-in 10/100 Ethernet MAC interfaces */ +static struct eth_plat_info ixdp425_plat_eth[] = { + { + .phy = 0, + .rxq = 3, + .txreadyq = 20, + }, { + .phy = 1, + .rxq = 4, + .txreadyq = 21, + } +}; + +static struct platform_device ixdp425_eth[] = { + { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = ixdp425_plat_eth, + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = ixdp425_plat_eth + 1, + } +}; + static struct platform_device *ixdp425_devices[] __initdata = { &ixdp425_i2c_controller, &ixdp425_flash, @@ -184,7 +209,9 @@ static struct platform_device *ixdp425_devices[] __initdata = { defined(CONFIG_MTD_NAND_PLATFORM_MODULE) &ixdp425_flash_nand, #endif - &ixdp425_uart + &ixdp425_uart, + &ixdp425_eth[0], + &ixdp425_eth[1], }; static void __init ixdp425_init(void) diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c new file mode 100644 index 0000000..83c137e --- /dev/null +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c @@ -0,0 +1,741 @@ +/* + * Intel IXP4xx Network Processor Engine driver for Linux + * + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * The code is based on publicly available information: + * - Intel IXP4xx Developer's Manual and other e-papers + * - Intel IXP400 Access Library Software (BSD license) + * - previous works by Christian Hohnstaedt + * Thanks, Christian. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEBUG_MSG 0 +#define DEBUG_FW 0 + +#define NPE_COUNT 3 +#define MAX_RETRIES 1000 /* microseconds */ +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */ +#define NPE_46X_DATA_SIZE 0x1000 +#define NPE_A_42X_INSTR_SIZE 0x1000 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800 +#define NPE_46X_INSTR_SIZE 0x1000 +#define REGS_SIZE 0x1000 + +#define NPE_PHYS_REG 32 + +#define FW_MAGIC 0xFEEDF00D +#define FW_BLOCK_TYPE_INSTR 0x0 +#define FW_BLOCK_TYPE_DATA 0x1 +#define FW_BLOCK_TYPE_EOF 0xF + +/* NPE exec status (read) and command (write) */ +#define CMD_NPE_STEP 0x01 +#define CMD_NPE_START 0x02 +#define CMD_NPE_STOP 0x03 +#define CMD_NPE_CLR_PIPE 0x04 +#define CMD_CLR_PROFILE_CNT 0x0C +#define CMD_RD_INS_MEM 0x10 /* instruction memory */ +#define CMD_WR_INS_MEM 0x11 +#define CMD_RD_DATA_MEM 0x12 /* data memory */ +#define CMD_WR_DATA_MEM 0x13 +#define CMD_RD_ECS_REG 0x14 /* exec access register */ +#define CMD_WR_ECS_REG 0x15 + +#define STAT_RUN 0x80000000 +#define STAT_STOP 0x40000000 +#define STAT_CLEAR 0x20000000 +#define STAT_ECS_K 0x00800000 /* pipeline clean */ + +#define NPE_STEVT 0x1B +#define NPE_STARTPC 0x1C +#define NPE_REGMAP 0x1E +#define NPE_CINDEX 0x1F + +#define INSTR_WR_REG_SHORT 0x0000C000 +#define INSTR_WR_REG_BYTE 0x00004000 +#define INSTR_RD_FIFO 0x0F888220 +#define INSTR_RESET_MBOX 0x0FAC8210 + +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */ +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */ +#define ECS_BG_CTXT_REG_2 0x02 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */ +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */ +#define ECS_PRI_1_CTXT_REG_2 0x06 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */ +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */ +#define ECS_PRI_2_CTXT_REG_2 0x0A +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */ +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */ +#define ECS_DBG_CTXT_REG_2 0x0E +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */ + +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */ +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */ +#define ECS_REG_0_LDUR_BITS 8 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */ +#define ECS_REG_1_CCTXT_BITS 16 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */ +#define ECS_REG_1_SELCTXT_BITS 0 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */ +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */ +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */ + +/* NPE watchpoint_fifo register bit */ +#define WFIFO_VALID 0x80000000 + +/* NPE messaging_status register bit definitions */ +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */ +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */ +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */ +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */ +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */ +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */ +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */ +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */ + +/* NPE messaging_control register bit definitions */ +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */ +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */ +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */ +#define MSGCTL_IN_FIFO_WRITE 0x02000000 + +/* NPE mailbox_status value for reset */ +#define RESET_MBOX_STAT 0x0000F0F0 + +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" }; + +#define print_npe(pri, npe, fmt, ...) \ + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) + +#if DEBUG_MSG +#define debug_msg(npe, fmt, ...) \ + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__) +#else +#define debug_msg(npe, fmt, ...) +#endif + +static struct { + u32 reg, val; +} ecs_reset[] = { + { ECS_BG_CTXT_REG_0, 0xA0000000 }, + { ECS_BG_CTXT_REG_1, 0x01000000 }, + { ECS_BG_CTXT_REG_2, 0x00008000 }, + { ECS_PRI_1_CTXT_REG_0, 0x20000080 }, + { ECS_PRI_1_CTXT_REG_1, 0x01000000 }, + { ECS_PRI_1_CTXT_REG_2, 0x00008000 }, + { ECS_PRI_2_CTXT_REG_0, 0x20000080 }, + { ECS_PRI_2_CTXT_REG_1, 0x01000000 }, + { ECS_PRI_2_CTXT_REG_2, 0x00008000 }, + { ECS_DBG_CTXT_REG_0, 0x20000000 }, + { ECS_DBG_CTXT_REG_1, 0x00000000 }, + { ECS_DBG_CTXT_REG_2, 0x001E0000 }, + { ECS_INSTRUCT_REG, 0x1003C00F }, +}; + +static struct npe npe_tab[NPE_COUNT] = { + { + .id = 0, + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT, + .regs_phys = IXP4XX_NPEA_BASE_PHYS, + }, { + .id = 1, + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT, + .regs_phys = IXP4XX_NPEB_BASE_PHYS, + }, { + .id = 2, + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT, + .regs_phys = IXP4XX_NPEC_BASE_PHYS, + } +}; + +int npe_running(struct npe *npe) +{ + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; +} + +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data) +{ + __raw_writel(data, &npe->regs->exec_data); + __raw_writel(addr, &npe->regs->exec_addr); + __raw_writel(cmd, &npe->regs->exec_status_cmd); +} + +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd) +{ + __raw_writel(addr, &npe->regs->exec_addr); + __raw_writel(cmd, &npe->regs->exec_status_cmd); + /* Iintroduce extra read cycles after issuing read command to NPE + so that we read the register after the NPE has updated it. + This is to overcome race condition between XScale and NPE */ + __raw_readl(&npe->regs->exec_data); + __raw_readl(&npe->regs->exec_data); + return __raw_readl(&npe->regs->exec_data); +} + +static void npe_clear_active(struct npe *npe, u32 reg) +{ + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); +} + +static void npe_start(struct npe *npe) +{ + /* ensure only Background Context Stack Level is active */ + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0); + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0); + npe_clear_active(npe, ECS_DBG_CTXT_REG_0); + + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); +} + +static void npe_stop(struct npe *npe) +{ + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ +} + +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, + u32 ldur) +{ + u32 wc; + int i; + + /* set the Active bit, and the LDUR, in the debug level */ + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS)); + + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute + the instruction, and set SELCTXT at ECS DEBUG Level to specify + which context store to access. + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number + */ + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG, + (ctx << ECS_REG_1_CCTXT_BITS) | + (ctx << ECS_REG_1_SELCTXT_BITS)); + + /* clear the pipeline */ + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); + + /* load NPE instruction into the instruction register */ + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr); + + /* we need this value later to wait for completion of NPE execution + step */ + wc = __raw_readl(&npe->regs->watch_count); + + /* issue a Step One command via the Execution Control register */ + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd); + + /* Watch Count register increments when NPE completes an instruction */ + for (i = 0; i < MAX_RETRIES; i++) { + if (wc != __raw_readl(&npe->regs->watch_count)) + return 0; + udelay(1); + } + + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n"); + return -ETIMEDOUT; +} + +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr, + u8 val, u32 ctx) +{ + /* here we build the NPE assembler instruction: mov8 d0, #0 */ + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */ + addr << 9 | /* base Operand */ + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ +} + +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr, + u16 val, u32 ctx) +{ + /* here we build the NPE assembler instruction: mov16 d0, #0 */ + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */ + addr << 9 | /* base Operand */ + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ +} + +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, + u32 val, u32 ctx) +{ + /* write in 16 bit steps first the high and then the low value */ + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) + return -ETIMEDOUT; + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); +} + +static int npe_reset(struct npe *npe) +{ + u32 val, ctl, exec_count, ctx_reg2; + int i; + + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & + 0x3F3FFFFF; + + /* disable parity interrupt */ + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control); + + /* pre exec - debug instruction */ + /* turn off the halt bit by clearing Execution Count register. */ + exec_count = __raw_readl(&npe->regs->exec_count); + __raw_writel(0, &npe->regs->exec_count); + /* ensure that IF and IE are on (temporarily), so that we don't end up + stepping forever */ + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG); + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 | + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE); + + /* clear the FIFOs */ + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) + ; + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) + /* read from the outFIFO until empty */ + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n", + __raw_readl(&npe->regs->in_out_fifo)); + + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) + /* step execution of the NPE intruction to read inFIFO using + the Debug Executing Context stack */ + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0)) + return -ETIMEDOUT; + + /* reset the mailbox reg from the XScale side */ + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status); + /* from NPE side */ + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0)) + return -ETIMEDOUT; + + /* Reset the physical registers in the NPE register file */ + for (val = 0; val < NPE_PHYS_REG; val++) { + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) + return -ETIMEDOUT; + /* address is either 0 or 4 */ + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) + return -ETIMEDOUT; + } + + /* Reset the context store = each context's Context Store registers */ + + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC + for Background ECS, to set where NPE starts executing code */ + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); + val &= ~ECS_REG_0_NEXTPC_MASK; + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); + + for (i = 0; i < 16; i++) { + if (i) { /* Context 0 has no STEVT nor STARTPC */ + /* STEVT = off, 0x80 */ + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i)) + return -ETIMEDOUT; + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i)) + return -ETIMEDOUT; + } + /* REGMAP = d0->p0, d8->p2, d16->p4 */ + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i)) + return -ETIMEDOUT; + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i)) + return -ETIMEDOUT; + } + + /* post exec */ + /* clear active bit in debug level */ + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0); + /* clear the pipeline */ + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); + /* restore previous values */ + __raw_writel(exec_count, &npe->regs->exec_count); + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2); + + /* write reset values to Execution Context Stack registers */ + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, + ecs_reset[val].val); + + /* clear the profile counter */ + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd); + + __raw_writel(0, &npe->regs->exec_count); + __raw_writel(0, &npe->regs->action_points[0]); + __raw_writel(0, &npe->regs->action_points[1]); + __raw_writel(0, &npe->regs->action_points[2]); + __raw_writel(0, &npe->regs->action_points[3]); + __raw_writel(0, &npe->regs->watch_count); + + val = ixp4xx_read_feature_bits(); + /* reset the NPE */ + ixp4xx_write_feature_bits(val & + ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); + for (i = 0; i < MAX_RETRIES; i++) { + if (!(ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_RESET_NPEA << npe->id))) + break; /* reset completed */ + udelay(1); + } + if (i == MAX_RETRIES) + return -ETIMEDOUT; + + /* deassert reset */ + ixp4xx_write_feature_bits(val | + (IXP4XX_FEATURE_RESET_NPEA << npe->id)); + for (i = 0; i < MAX_RETRIES; i++) { + if (ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_RESET_NPEA << npe->id)) + break; /* NPE is back alive */ + udelay(1); + } + if (i == MAX_RETRIES) + return -ETIMEDOUT; + + npe_stop(npe); + + /* restore NPE configuration bus Control Register - parity settings */ + __raw_writel(ctl, &npe->regs->messaging_control); + return 0; +} + + +int npe_send_message(struct npe *npe, const void *msg, const char *what) +{ + const u32 *send = msg; + int cycles = 0; + + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n", + what, send[0], send[1]); + + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { + debug_msg(npe, "NPE input FIFO not empty\n"); + return -EIO; + } + + __raw_writel(send[0], &npe->regs->in_out_fifo); + + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { + debug_msg(npe, "NPE input FIFO full\n"); + return -EIO; + } + + __raw_writel(send[1], &npe->regs->in_out_fifo); + + while ((cycles < MAX_RETRIES) && + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { + udelay(1); + cycles++; + } + + if (cycles == MAX_RETRIES) { + debug_msg(npe, "Timeout sending message\n"); + return -ETIMEDOUT; + } + + debug_msg(npe, "Sending a message took %i cycles\n", cycles); + return 0; +} + +int npe_recv_message(struct npe *npe, void *msg, const char *what) +{ + u32 *recv = msg; + int cycles = 0, cnt = 0; + + debug_msg(npe, "Trying to receive message %s\n", what); + + while (cycles < MAX_RETRIES) { + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); + if (cnt == 2) + break; + } else { + udelay(1); + cycles++; + } + } + + switch(cnt) { + case 1: + debug_msg(npe, "Received [%08X]\n", recv[0]); + break; + case 2: + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]); + break; + } + + if (cycles == MAX_RETRIES) { + debug_msg(npe, "Timeout waiting for message\n"); + return -ETIMEDOUT; + } + + debug_msg(npe, "Receiving a message took %i cycles\n", cycles); + return 0; +} + +int npe_send_recv_message(struct npe *npe, void *msg, const char *what) +{ + int result; + u32 *send = msg, recv[2]; + + if ((result = npe_send_message(npe, msg, what)) != 0) + return result; + if ((result = npe_recv_message(npe, recv, what)) != 0) + return result; + + if ((recv[0] != send[0]) || (recv[1] != send[1])) { + debug_msg(npe, "Message %s: unexpected message received\n", + what); + return -EIO; + } + return 0; +} + + +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) +{ + const struct firmware *fw_entry; + + struct dl_block { + u32 type; + u32 offset; + } *blk; + + struct dl_image { + u32 magic; + u32 id; + u32 size; + union { + u32 data[0]; + struct dl_block blocks[0]; + }; + } *image; + + struct dl_codeblock { + u32 npe_addr; + u32 size; + u32 data[0]; + } *cb; + + int i, j, err, data_size, instr_size, blocks, table_end; + u32 cmd; + + if ((err = request_firmware(&fw_entry, name, dev)) != 0) + return err; + + err = -EINVAL; + if (fw_entry->size < sizeof(struct dl_image)) { + print_npe(KERN_ERR, npe, "incomplete firmware file\n"); + goto err; + } + image = (struct dl_image*)fw_entry->data; + +#if DEBUG_FW + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n", + image->magic, image->id, image->size, image->size * 4); +#endif + + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */ + image->id = swab32(image->id); + image->size = swab32(image->size); + } else if (image->magic != FW_MAGIC) { + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n", + image->magic); + goto err; + } + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) { + print_npe(KERN_ERR, npe, + "inconsistent size of firmware file\n"); + goto err; + } + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) { + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n"); + goto err; + } + if (image->magic == swab32(FW_MAGIC)) + for (i = 0; i < image->size; i++) + image->data[i] = swab32(image->data[i]); + + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) { + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on " + "IXP42x\n"); + goto err; + } + + if (npe_running(npe)) { + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is " + "already running\n"); + err = -EBUSY; + goto err; + } +#if 0 + npe_stop(npe); + npe_reset(npe); +#endif + + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, + (image->id >> 8) & 0xFF, image->id & 0xFF); + + if (!cpu_is_ixp46x()) { + if (!npe->id) + instr_size = NPE_A_42X_INSTR_SIZE; + else + instr_size = NPE_B_AND_C_42X_INSTR_SIZE; + data_size = NPE_42X_DATA_SIZE; + } else { + instr_size = NPE_46X_INSTR_SIZE; + data_size = NPE_46X_DATA_SIZE; + } + + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size; + blocks++) + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF) + break; + if (blocks * sizeof(struct dl_block) / 4 >= image->size) { + print_npe(KERN_INFO, npe, "firmware EOF block marker not " + "found\n"); + goto err; + } + +#if DEBUG_FW + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks); +#endif + + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */; + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4 + || blk->offset < table_end) { + print_npe(KERN_INFO, npe, "invalid offset 0x%X of " + "firmware block #%i\n", blk->offset, i); + goto err; + } + + cb = (struct dl_codeblock*)&image->data[blk->offset]; + if (blk->type == FW_BLOCK_TYPE_INSTR) { + if (cb->npe_addr + cb->size > instr_size) + goto too_big; + cmd = CMD_WR_INS_MEM; + } else if (blk->type == FW_BLOCK_TYPE_DATA) { + if (cb->npe_addr + cb->size > data_size) + goto too_big; + cmd = CMD_WR_DATA_MEM; + } else { + print_npe(KERN_INFO, npe, "invalid firmware block #%i " + "type 0x%X\n", i, blk->type); + goto err; + } + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { + print_npe(KERN_INFO, npe, "firmware block #%i doesn't " + "fit in firmware image: type %c, start 0x%X," + " length 0x%X\n", i, + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', + cb->npe_addr, cb->size); + goto err; + } + + for (j = 0; j < cb->size; j++) + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]); + } + + npe_start(npe); + if (!npe_running(npe)) + print_npe(KERN_ERR, npe, "unable to start\n"); + release_firmware(fw_entry); + return 0; + +too_big: + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE " + "memory: type %c, start 0x%X, length 0x%X\n", i, + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', + cb->npe_addr, cb->size); +err: + release_firmware(fw_entry); + return err; +} + + +struct npe *npe_request(int id) +{ + if (id < NPE_COUNT) + if (npe_tab[id].valid) + if (try_module_get(THIS_MODULE)) + return &npe_tab[id]; + return NULL; +} + +void npe_release(struct npe *npe) +{ + module_put(THIS_MODULE); +} + + +static int __init npe_init_module(void) +{ + + int i, found = 0; + + for (i = 0; i < NPE_COUNT; i++) { + struct npe *npe = &npe_tab[i]; + if (!(ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_RESET_NPEA << i))) + continue; /* NPE already disabled or not present */ + if (!(npe->mem_res = request_mem_region(npe->regs_phys, + REGS_SIZE, + npe_name(npe)))) { + print_npe(KERN_ERR, npe, + "failed to request memory region\n"); + continue; + } + + if (npe_reset(npe)) + continue; + npe->valid = 1; + found++; + } + + if (!found) + return -ENOSYS; + return 0; +} + +static void __exit npe_cleanup_module(void) +{ + int i; + + for (i = 0; i < NPE_COUNT; i++) + if (npe_tab[i].mem_res) { + npe_reset(&npe_tab[i]); + release_resource(npe_tab[i].mem_res); + } +} + +module_init(npe_init_module); +module_exit(npe_cleanup_module); + +MODULE_AUTHOR("Krzysztof Halasa"); +MODULE_LICENSE("GPL v2"); + +EXPORT_SYMBOL(npe_names); +EXPORT_SYMBOL(npe_running); +EXPORT_SYMBOL(npe_request); +EXPORT_SYMBOL(npe_release); +EXPORT_SYMBOL(npe_load_firmware); +EXPORT_SYMBOL(npe_send_message); +EXPORT_SYMBOL(npe_recv_message); +EXPORT_SYMBOL(npe_send_recv_message); diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c new file mode 100644 index 0000000..e833013 --- /dev/null +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c @@ -0,0 +1,274 @@ +/* + * Intel IXP4xx Queue Manager driver for Linux + * + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#define DEBUG 0 + +struct qmgr_regs __iomem *qmgr_regs; +static struct resource *mem_res; +static spinlock_t qmgr_lock; +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ +static void (*irq_handlers[HALF_QUEUES])(void *pdev); +static void *irq_pdevs[HALF_QUEUES]; + +void qmgr_set_irq(unsigned int queue, int src, + void (*handler)(void *pdev), void *pdev) +{ + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */ + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ + unsigned long flags; + + src &= 7; + spin_lock_irqsave(&qmgr_lock, flags); + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg); + irq_handlers[queue] = handler; + irq_pdevs[queue] = pdev; + spin_unlock_irqrestore(&qmgr_lock, flags); +} + + +static irqreturn_t qmgr_irq1(int irq, void *pdev) +{ + int i; + u32 val = __raw_readl(&qmgr_regs->irqstat[0]); + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */ + + for (i = 0; i < HALF_QUEUES; i++) + if (val & (1 << i)) + irq_handlers[i](irq_pdevs[i]); + + return val ? IRQ_HANDLED : 0; +} + + +void qmgr_enable_irq(unsigned int queue) +{ + unsigned long flags; + + spin_lock_irqsave(&qmgr_lock, flags); + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue), + &qmgr_regs->irqen[0]); + spin_unlock_irqrestore(&qmgr_lock, flags); +} + +void qmgr_disable_irq(unsigned int queue) +{ + unsigned long flags; + + spin_lock_irqsave(&qmgr_lock, flags); + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), + &qmgr_regs->irqen[0]); + spin_unlock_irqrestore(&qmgr_lock, flags); +} + +static inline void shift_mask(u32 *mask) +{ + mask[3] = mask[3] << 1 | mask[2] >> 31; + mask[2] = mask[2] << 1 | mask[1] >> 31; + mask[1] = mask[1] << 1 | mask[0] >> 31; + mask[0] <<= 1; +} + +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, + unsigned int nearly_empty_watermark, + unsigned int nearly_full_watermark) +{ + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ + int err; + + if (queue >= HALF_QUEUES) + return -ERANGE; + + if ((nearly_empty_watermark | nearly_full_watermark) & ~7) + return -EINVAL; + + switch (len) { + case 16: + cfg = 0 << 24; + mask[0] = 0x1; + break; + case 32: + cfg = 1 << 24; + mask[0] = 0x3; + break; + case 64: + cfg = 2 << 24; + mask[0] = 0xF; + break; + case 128: + cfg = 3 << 24; + mask[0] = 0xFF; + break; + default: + return -EINVAL; + } + + cfg |= nearly_empty_watermark << 26; + cfg |= nearly_full_watermark << 29; + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */ + mask[1] = mask[2] = mask[3] = 0; + + if (!try_module_get(THIS_MODULE)) + return -ENODEV; + + spin_lock_irq(&qmgr_lock); + if (__raw_readl(&qmgr_regs->sram[queue])) { + err = -EBUSY; + goto err; + } + + while (1) { + if (!(used_sram_bitmap[0] & mask[0]) && + !(used_sram_bitmap[1] & mask[1]) && + !(used_sram_bitmap[2] & mask[2]) && + !(used_sram_bitmap[3] & mask[3])) + break; /* found free space */ + + addr++; + shift_mask(mask); + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) { + printk(KERN_ERR "qmgr: no free SRAM space for" + " queue %i\n", queue); + err = -ENOMEM; + goto err; + } + } + + used_sram_bitmap[0] |= mask[0]; + used_sram_bitmap[1] |= mask[1]; + used_sram_bitmap[2] |= mask[2]; + used_sram_bitmap[3] |= mask[3]; + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); + spin_unlock_irq(&qmgr_lock); + +#if DEBUG + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n", + queue, addr); +#endif + return 0; + +err: + spin_unlock_irq(&qmgr_lock); + module_put(THIS_MODULE); + return err; +} + +void qmgr_release_queue(unsigned int queue) +{ + u32 cfg, addr, mask[4]; + + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */ + + spin_lock_irq(&qmgr_lock); + cfg = __raw_readl(&qmgr_regs->sram[queue]); + addr = (cfg >> 14) & 0xFF; + + BUG_ON(!addr); /* not requested */ + + switch ((cfg >> 24) & 3) { + case 0: mask[0] = 0x1; break; + case 1: mask[0] = 0x3; break; + case 2: mask[0] = 0xF; break; + case 3: mask[0] = 0xFF; break; + } + + while (addr--) + shift_mask(mask); + + __raw_writel(0, &qmgr_regs->sram[queue]); + + used_sram_bitmap[0] &= ~mask[0]; + used_sram_bitmap[1] &= ~mask[1]; + used_sram_bitmap[2] &= ~mask[2]; + used_sram_bitmap[3] &= ~mask[3]; + irq_handlers[queue] = NULL; /* catch IRQ bugs */ + spin_unlock_irq(&qmgr_lock); + + module_put(THIS_MODULE); +#if DEBUG + printk(KERN_DEBUG "qmgr: released queue %i\n", queue); +#endif +} + +static int qmgr_init(void) +{ + int i, err; + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS, + IXP4XX_QMGR_REGION_SIZE, + "IXP4xx Queue Manager"); + if (mem_res == NULL) + return -EBUSY; + + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); + if (qmgr_regs == NULL) { + err = -ENOMEM; + goto error_map; + } + + /* reset qmgr registers */ + for (i = 0; i < 4; i++) { + __raw_writel(0x33333333, &qmgr_regs->stat1[i]); + __raw_writel(0, &qmgr_regs->irqsrc[i]); + } + for (i = 0; i < 2; i++) { + __raw_writel(0, &qmgr_regs->stat2[i]); + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */ + __raw_writel(0, &qmgr_regs->irqen[i]); + } + + for (i = 0; i < QUEUES; i++) + __raw_writel(0, &qmgr_regs->sram[i]); + + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0, + "IXP4xx Queue Manager", NULL); + if (err) { + printk(KERN_ERR "qmgr: failed to request IRQ%i\n", + IRQ_IXP4XX_QM1); + goto error_irq; + } + + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */ + spin_lock_init(&qmgr_lock); + + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n"); + return 0; + +error_irq: + iounmap(qmgr_regs); +error_map: + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); + return err; +} + +static void qmgr_remove(void) +{ + free_irq(IRQ_IXP4XX_QM1, NULL); + synchronize_irq(IRQ_IXP4XX_QM1); + iounmap(qmgr_regs); + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); +} + +module_init(qmgr_init); +module_exit(qmgr_remove); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Krzysztof Halasa"); + +EXPORT_SYMBOL(qmgr_regs); +EXPORT_SYMBOL(qmgr_set_irq); +EXPORT_SYMBOL(qmgr_enable_irq); +EXPORT_SYMBOL(qmgr_disable_irq); +EXPORT_SYMBOL(qmgr_request_queue); +EXPORT_SYMBOL(qmgr_release_queue); diff --git a/arch/arm/mach-ixp4xx/nslu2-power.c b/arch/arm/mach-ixp4xx/nslu2-power.c index acd71e9..d138e49 100644 --- a/arch/arm/mach-ixp4xx/nslu2-power.c +++ b/arch/arm/mach-ixp4xx/nslu2-power.c @@ -18,10 +18,8 @@ */ #include -#include #include #include -#include #include diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile index 2a07a28..730a3af 100644 --- a/arch/arm/mach-ks8695/Makefile +++ b/arch/arm/mach-ks8695/Makefile @@ -9,7 +9,7 @@ obj-n := obj- := # PCI support is optional -#obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_PCI) += pci.o # Board-specific support obj-$(CONFIG_MACH_KS8695) += board-micrel.o diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c index 2feeef8..05ac2bd 100644 --- a/arch/arm/mach-ks8695/board-micrel.c +++ b/arch/arm/mach-ks8695/board-micrel.c @@ -40,7 +40,7 @@ static void __init micrel_init(void) printk(KERN_INFO "Micrel KS8695 Development Board initializing\n"); #ifdef CONFIG_PCI -// ks8695_init_pci(&micrel_pci); + ks8695_init_pci(&micrel_pci); #endif /* Add devices */ diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c index b1aa3cb..5e46191 100644 --- a/arch/arm/mach-ks8695/gpio.c +++ b/arch/arm/mach-ks8695/gpio.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include @@ -216,3 +218,84 @@ int irq_to_gpio(unsigned int irq) return (irq - KS8695_IRQ_EXTERN0); } EXPORT_SYMBOL(irq_to_gpio); + + +/* .... Debug interface ..................................................... */ + +#ifdef CONFIG_DEBUG_FS + +static int ks8695_gpio_show(struct seq_file *s, void *unused) +{ + unsigned int enable[] = { IOPC_IOEINT0EN, IOPC_IOEINT1EN, IOPC_IOEINT2EN, IOPC_IOEINT3EN, IOPC_IOTIM0EN, IOPC_IOTIM1EN }; + unsigned int intmask[] = { IOPC_IOEINT0TM, IOPC_IOEINT1TM, IOPC_IOEINT2TM, IOPC_IOEINT3TM }; + unsigned long mode, ctrl, data; + int i; + + mode = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); + ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); + data = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); + + seq_printf(s, "Pin\tI/O\tFunction\tState\n\n"); + + for (i = KS8695_GPIO_0; i <= KS8695_GPIO_15 ; i++) { + seq_printf(s, "%i:\t", i); + + seq_printf(s, "%s\t", (mode & IOPM_(i)) ? "Output" : "Input"); + + if (i <= KS8695_GPIO_3) { + if (ctrl & enable[i]) { + seq_printf(s, "EXT%i ", i); + + switch ((ctrl & intmask[i]) >> (4 * i)) { + case IOPC_TM_LOW: + seq_printf(s, "(Low)"); break; + case IOPC_TM_HIGH: + seq_printf(s, "(High)"); break; + case IOPC_TM_RISING: + seq_printf(s, "(Rising)"); break; + case IOPC_TM_FALLING: + seq_printf(s, "(Falling)"); break; + case IOPC_TM_EDGE: + seq_printf(s, "(Edges)"); break; + } + } + else + seq_printf(s, "GPIO\t"); + } + else if (i <= KS8695_GPIO_5) { + if (ctrl & enable[i]) + seq_printf(s, "TOUT%i\t", i - KS8695_GPIO_4); + else + seq_printf(s, "GPIO\t"); + } + else + seq_printf(s, "GPIO\t"); + + seq_printf(s, "\t"); + + seq_printf(s, "%i\n", (data & IOPD_(i)) ? 1 : 0); + } + return 0; +} + +static int ks8695_gpio_open(struct inode *inode, struct file *file) +{ + return single_open(file, ks8695_gpio_show, NULL); +} + +static const struct file_operations ks8695_gpio_operations = { + .open = ks8695_gpio_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init ks8695_gpio_debugfs_init(void) +{ + /* /sys/kernel/debug/ks8695_gpio */ + (void) debugfs_create_file("ks8695_gpio", S_IFREG | S_IRUGO, NULL, NULL, &ks8695_gpio_operations); + return 0; +} +postcore_initcall(ks8695_gpio_debugfs_init); + +#endif diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c new file mode 100644 index 0000000..3f4e033 --- /dev/null +++ b/arch/arm/mach-ks8695/pci.c @@ -0,0 +1,326 @@ +/* + * arch/arm/mach-ks8695/pci.c + * + * Copyright (C) 2003, Micrel Semiconductors + * Copyright (C) 2006, Greg Ungerer + * Copyright (C) 2006, Ben Dooks + * Copyright (C) 2007, Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + + +static int pci_dbg; +static int pci_cfg_dbg; + + +static void ks8695_pci_setupconfig(unsigned int bus_nr, unsigned int devfn, unsigned int where) +{ + unsigned long pbca; + + pbca = PBCA_ENABLE | (where & ~3); + pbca |= PCI_SLOT(devfn) << 11 ; + pbca |= PCI_FUNC(devfn) << 8; + pbca |= bus_nr << 16; + + if (bus_nr == 0) { + /* use Type-0 transaction */ + __raw_writel(pbca, KS8695_PCI_VA + KS8695_PBCA); + } else { + /* use Type-1 transaction */ + __raw_writel(pbca | PBCA_TYPE1, KS8695_PCI_VA + KS8695_PBCA); + } +} + + +/* + * The KS8695 datasheet prohibits anything other than 32bit accesses + * to the IO registers, so all our configuration must be done with + * 32bit operations, and the correct bit masking and shifting. + */ + +static int ks8695_pci_readconfig(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *value) +{ + ks8695_pci_setupconfig(bus->number, devfn, where); + + *value = __raw_readl(KS8695_PCI_VA + KS8695_PBCD); + + switch (size) { + case 4: + break; + case 2: + *value = *value >> ((where & 2) * 8); + *value &= 0xffff; + break; + case 1: + *value = *value >> ((where & 3) * 8); + *value &= 0xff; + break; + } + + if (pci_cfg_dbg) { + printk("read: %d,%08x,%02x,%d: %08x (%08x)\n", + bus->number, devfn, where, size, *value, + __raw_readl(KS8695_PCI_VA + KS8695_PBCD)); + } + + return PCIBIOS_SUCCESSFUL; +} + +static int ks8695_pci_writeconfig(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 value) +{ + unsigned long tmp; + + if (pci_cfg_dbg) { + printk("write: %d,%08x,%02x,%d: %08x\n", + bus->number, devfn, where, size, value); + } + + ks8695_pci_setupconfig(bus->number, devfn, where); + + switch (size) { + case 4: + __raw_writel(value, KS8695_PCI_VA + KS8695_PBCD); + break; + case 2: + tmp = __raw_readl(KS8695_PCI_VA + KS8695_PBCD); + tmp &= ~(0xffff << ((where & 2) * 8)); + tmp |= value << ((where & 2) * 8); + + __raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD); + break; + case 1: + tmp = __raw_readl(KS8695_PCI_VA + KS8695_PBCD); + tmp &= ~(0xff << ((where & 3) * 8)); + tmp |= value << ((where & 3) * 8); + + __raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD); + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static void ks8695_local_writeconfig(int where, u32 value) +{ + ks8695_pci_setupconfig(0, 0, where); + __raw_writel(value, KS8695_PCI_VA + KS8695_PBCD); +} + +static struct pci_ops ks8695_pci_ops = { + .read = ks8695_pci_readconfig, + .write = ks8695_pci_writeconfig, +}; + +static struct pci_bus *ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys); +} + +static struct resource pci_mem = { + .name = "PCI Memory space", + .start = KS8695_PCIMEM_PA, + .end = KS8695_PCIMEM_PA + (KS8695_PCIMEM_SIZE - 1), + .flags = IORESOURCE_MEM, +}; + +static struct resource pci_io = { + .name = "PCI IO space", + .start = KS8695_PCIIO_PA, + .end = KS8695_PCIIO_PA + (KS8695_PCIIO_SIZE - 1), + .flags = IORESOURCE_IO, +}; + +static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys) +{ + if (nr > 0) + return 0; + + request_resource(&iomem_resource, &pci_mem); + request_resource(&ioport_resource, &pci_io); + + sys->resource[0] = &pci_io; + sys->resource[1] = &pci_mem; + sys->resource[2] = NULL; + + /* Assign and enable processor bridge */ + ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA); + + /* Enable bus-master & Memory Space access */ + ks8695_local_writeconfig(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Set cache-line size & latency. */ + ks8695_local_writeconfig(PCI_CACHE_LINE_SIZE, (32 << 8) | (L1_CACHE_BYTES / sizeof(u32))); + + /* Reserve PCI memory space for PCI-AHB resources */ + if (!request_mem_region(KS8695_PCIMEM_PA, SZ_64M, "PCI-AHB Bridge")) { + printk(KERN_ERR "Cannot allocate PCI-AHB Bridge memory.\n"); + return -EBUSY; + } + + return 1; +} + +static inline unsigned int size_mask(unsigned long size) +{ + return (~size) + 1; +} + +static int ks8695_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + unsigned long pc = instruction_pointer(regs); + unsigned long instr = *(unsigned long *)pc; + unsigned long cmdstat; + + cmdstat = __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS); + + printk(KERN_ERR "PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx [%s%s%s%s%s]\n", + addr, fsr, regs->ARM_pc, regs->ARM_lr, + cmdstat & (PCI_STATUS_SIG_TARGET_ABORT << 16) ? "GenTarget" : " ", + cmdstat & (PCI_STATUS_REC_TARGET_ABORT << 16) ? "RecvTarget" : " ", + cmdstat & (PCI_STATUS_REC_MASTER_ABORT << 16) ? "MasterAbort" : " ", + cmdstat & (PCI_STATUS_SIG_SYSTEM_ERROR << 16) ? "SysError" : " ", + cmdstat & (PCI_STATUS_DETECTED_PARITY << 16) ? "Parity" : " " + ); + + __raw_writel(cmdstat, KS8695_PCI_VA + KS8695_CRCFCS); + + /* + * If the instruction being executed was a read, + * make it look like it read all-ones. + */ + if ((instr & 0x0c100000) == 0x04100000) { + int reg = (instr >> 12) & 15; + unsigned long val; + + if (instr & 0x00400000) + val = 255; + else + val = -1; + + regs->uregs[reg] = val; + regs->ARM_pc += 4; + return 0; + } + + if ((instr & 0x0e100090) == 0x00100090) { + int reg = (instr >> 12) & 15; + + regs->uregs[reg] = -1; + regs->ARM_pc += 4; + return 0; + } + + return 1; +} + +static void __init ks8695_pci_preinit(void) +{ + /* stage 1 initialization, subid, subdevice = 0x0001 */ + __raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID); + + /* stage 2 initialization */ + /* prefetch limits with 16 words, retry enable */ + __raw_writel(0x40000000, KS8695_PCI_VA + KS8695_PBCS); + + /* configure memory mapping */ + __raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBA); + __raw_writel(size_mask(KS8695_PCIMEM_SIZE), KS8695_PCI_VA + KS8695_PMBAM); + __raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBAT); + __raw_writel(0, KS8695_PCI_VA + KS8695_PMBAC); + + /* configure IO mapping */ + __raw_writel(KS8695_PCIIO_PA, KS8695_PCI_VA + KS8695_PIOBA); + __raw_writel(size_mask(KS8695_PCIIO_SIZE), KS8695_PCI_VA + KS8695_PIOBAM); + __raw_writel(KS8695_PCIIO_PA, KS8695_PCI_VA + KS8695_PIOBAT); + __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC); + + /* hook in fault handlers */ + hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); + hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); +} + +static void ks8695_show_pciregs(void) +{ + if (!pci_dbg) + return; + + printk(KERN_INFO "PCI: CRCFID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFID)); + printk(KERN_INFO "PCI: CRCFCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS)); + printk(KERN_INFO "PCI: CRCFRV = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFRV)); + printk(KERN_INFO "PCI: CRCFLT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFLT)); + printk(KERN_INFO "PCI: CRCBMA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCBMA)); + printk(KERN_INFO "PCI: CRCSID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCSID)); + printk(KERN_INFO "PCI: CRCFIT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFIT)); + + printk(KERN_INFO "PCI: PBM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBM)); + printk(KERN_INFO "PCI: PBCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBCS)); + + printk(KERN_INFO "PCI: PMBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBA)); + printk(KERN_INFO "PCI: PMBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAC)); + printk(KERN_INFO "PCI: PMBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAM)); + printk(KERN_INFO "PCI: PMBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAT)); + + printk(KERN_INFO "PCI: PIOBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBA)); + printk(KERN_INFO "PCI: PIOBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAC)); + printk(KERN_INFO "PCI: PIOBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAM)); + printk(KERN_INFO "PCI: PIOBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAT)); +} + + +static struct hw_pci ks8695_pci __initdata = { + .nr_controllers = 1, + .preinit = ks8695_pci_preinit, + .setup = ks8695_pci_setup, + .scan = ks8695_pci_scan_bus, + .postinit = NULL, + .swizzle = pci_std_swizzle, + .map_irq = NULL, +}; + +void __init ks8695_init_pci(struct ks8695_pci_cfg *cfg) +{ + if (__raw_readl(KS8695_PCI_VA + KS8695_CRCFRV) & CFRV_GUEST) { + printk("PCI: KS8695 in guest mode, not initialising\n"); + return; + } + + printk(KERN_INFO "PCI: Initialising\n"); + ks8695_show_pciregs(); + + /* set Mode */ + __raw_writel(cfg->mode << 29, KS8695_PCI_VA + KS8695_PBM); + + ks8695_pci.map_irq = cfg->map_irq; /* board-specific map_irq method */ + + pci_common_init(&ks8695_pci); +} diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig new file mode 100644 index 0000000..3553bab --- /dev/null +++ b/arch/arm/mach-msm/Kconfig @@ -0,0 +1,18 @@ +if ARCH_MSM7X00A + +comment "MSM7X00A Board Type" + depends on ARCH_MSM7X00A + +config MACH_HALIBUT + depends on ARCH_MSM7X00A + default y + bool "Halibut Board (QCT SURF7200A)" + help + Support for the Qualcomm SURF7200A eval board. + +config MSM7X00A_IDLE + depends on ARCH_MSM7X00A + default y + bool "Idle Support for MSM7X00A" + +endif diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile new file mode 100644 index 0000000..d12f236 --- /dev/null +++ b/arch/arm/mach-msm/Makefile @@ -0,0 +1,7 @@ +obj-y += io.o idle.o irq.o timer.o dma.o + +# Common code for board init +obj-y += common.o + +obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o + diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot new file mode 100644 index 0000000..24dfbf8 --- /dev/null +++ b/arch/arm/mach-msm/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x10008000 +params_phys-y := 0x10000100 +initrd_phys-y := 0x10800000 diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c new file mode 100644 index 0000000..86dfb2b --- /dev/null +++ b/arch/arm/mach-msm/board-halibut.c @@ -0,0 +1,114 @@ +/* linux/arch/arm/mach-msm/board-halibut.c + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +static struct resource smc91x_resources[] = { + [0] = { + .start = 0x9C004300, + .end = 0x9C004400, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSM_GPIO_TO_INT(49), + .end = MSM_GPIO_TO_INT(49), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static void mddi0_panel_power(int on) +{ +} + +static struct msm_mddi_platform_data msm_mddi0_pdata = { + .panel_power = mddi0_panel_power, + .has_vsync_irq = 0, +}; + +static struct platform_device msm_mddi0_device = { + .name = "msm_mddi", + .id = 0, + .dev = { + .platform_data = &msm_mddi0_pdata + }, +}; + +static struct platform_device msm_serial0_device = { + .name = "msm_serial", + .id = 0, +}; + +static struct platform_device *devices[] __initdata = { + &msm_serial0_device, + &msm_mddi0_device, + &smc91x_device, +}; + +extern struct sys_timer msm_timer; + +static void __init halibut_init_irq(void) +{ + msm_init_irq(); +} + +static void __init halibut_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); + msm_add_devices(); +} + +static void __init halibut_map_io(void) +{ + msm_map_common_io(); +} + +MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") + +/* UART for LL DEBUG */ + .phys_io = MSM_UART1_PHYS, + .io_pg_offst = ((MSM_UART1_BASE) >> 18) & 0xfffc, + + .boot_params = 0x10000100, + .map_io = halibut_map_io, + .init_irq = halibut_init_irq, + .init_machine = halibut_init, + .timer = &msm_timer, +MACHINE_END diff --git a/arch/arm/mach-msm/common.c b/arch/arm/mach-msm/common.c new file mode 100644 index 0000000..3f5d336 --- /dev/null +++ b/arch/arm/mach-msm/common.c @@ -0,0 +1,116 @@ +/* linux/arch/arm/mach-msm/common.c + * + * Common setup code for MSM7K Boards + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include + +#include + +struct flash_platform_data msm_nand_data = { + .parts = 0, + .nr_parts = 0, +}; + +static struct resource msm_nand_resources[] = { + [0] = { + .start = 7, + .end = 7, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device msm_nand_device = { + .name = "msm_nand", + .id = -1, + .num_resources = ARRAY_SIZE(msm_nand_resources), + .resource = msm_nand_resources, + .dev = { + .platform_data = &msm_nand_data, + }, +}; + +static struct platform_device msm_smd_device = { + .name = "msm_smd", + .id = -1, +}; + +static struct resource msm_i2c_resources[] = { + { + .start = MSM_I2C_BASE, + .end = MSM_I2C_BASE + MSM_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_PWB_I2C, + .end = INT_PWB_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device msm_i2c_device = { + .name = "msm_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(msm_i2c_resources), + .resource = msm_i2c_resources, +}; + +static struct resource usb_resources[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device msm_hsusb_device = { + .name = "msm_hsusb", + .id = -1, + .num_resources = ARRAY_SIZE(usb_resources), + .resource = usb_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct platform_device *devices[] __initdata = { + &msm_nand_device, + &msm_smd_device, + &msm_i2c_device, + &msm_hsusb_device, +}; + +void __init msm_add_devices(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); +} diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c new file mode 100644 index 0000000..8b0f339 --- /dev/null +++ b/arch/arm/mach-msm/dma.c @@ -0,0 +1,214 @@ +/* linux/arch/arm/mach-msm/dma.c + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#define MSM_DMOV_CHANNEL_COUNT 16 + +enum { + MSM_DMOV_PRINT_ERRORS = 1, + MSM_DMOV_PRINT_IO = 2, + MSM_DMOV_PRINT_FLOW = 4 +}; + +static DEFINE_SPINLOCK(msm_dmov_lock); +static struct msm_dmov_cmd active_command; +static struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT]; +static struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT]; +unsigned int msm_dmov_print_mask = MSM_DMOV_PRINT_ERRORS; + +#define MSM_DMOV_DPRINTF(mask, format, args...) \ + do { \ + if ((mask) & msm_dmov_print_mask) \ + printk(KERN_ERR format, args); \ + } while (0) +#define PRINT_ERROR(format, args...) \ + MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_ERRORS, format, args); +#define PRINT_IO(format, args...) \ + MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_IO, format, args); +#define PRINT_FLOW(format, args...) \ + MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_FLOW, format, args); + +void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) +{ + unsigned long irq_flags; + unsigned int status; + + spin_lock_irqsave(&msm_dmov_lock, irq_flags); + status = readl(DMOV_STATUS(id)); + if (list_empty(&ready_commands[id]) && + (status & DMOV_STATUS_CMD_PTR_RDY)) { +#if 0 + if (list_empty(&active_commands[id])) { + PRINT_FLOW("msm_dmov_enqueue_cmd(%d), enable interrupt\n", id); + writel(DMOV_CONFIG_IRQ_EN, DMOV_CONFIG(id)); + } +#endif + PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", id, status); + list_add_tail(&cmd->list, &active_commands[id]); + writel(cmd->cmdptr, DMOV_CMD_PTR(id)); + } else { + if (list_empty(&active_commands[id])) + PRINT_ERROR("msm_dmov_enqueue_cmd(%d), error datamover stalled, status %x\n", id, status); + + PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status %x\n", id, status); + list_add_tail(&cmd->list, &ready_commands[id]); + } + spin_unlock_irqrestore(&msm_dmov_lock, irq_flags); +} + +struct msm_dmov_exec_cmdptr_cmd { + struct msm_dmov_cmd dmov_cmd; + struct completion complete; + unsigned id; + unsigned int result; + unsigned int flush[6]; +}; + +static void dmov_exec_cmdptr_complete_func(struct msm_dmov_cmd *_cmd, unsigned int result) +{ + struct msm_dmov_exec_cmdptr_cmd *cmd = container_of(_cmd, struct msm_dmov_exec_cmdptr_cmd, dmov_cmd); + cmd->result = result; + if (result != 0x80000002) { + cmd->flush[0] = readl(DMOV_FLUSH0(cmd->id)); + cmd->flush[1] = readl(DMOV_FLUSH1(cmd->id)); + cmd->flush[2] = readl(DMOV_FLUSH2(cmd->id)); + cmd->flush[3] = readl(DMOV_FLUSH3(cmd->id)); + cmd->flush[4] = readl(DMOV_FLUSH4(cmd->id)); + cmd->flush[5] = readl(DMOV_FLUSH5(cmd->id)); + } + complete(&cmd->complete); +} + +int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) +{ + struct msm_dmov_exec_cmdptr_cmd cmd; + + PRINT_FLOW("dmov_exec_cmdptr(%d, %x)\n", id, cmdptr); + + cmd.dmov_cmd.cmdptr = cmdptr; + cmd.dmov_cmd.complete_func = dmov_exec_cmdptr_complete_func; + cmd.id = id; + init_completion(&cmd.complete); + + msm_dmov_enqueue_cmd(id, &cmd.dmov_cmd); + wait_for_completion(&cmd.complete); + + if (cmd.result != 0x80000002) { + PRINT_ERROR("dmov_exec_cmdptr(%d): ERROR, result: %x\n", id, cmd.result); + PRINT_ERROR("dmov_exec_cmdptr(%d): flush: %x %x %x %x\n", + id, cmd.flush[0], cmd.flush[1], cmd.flush[2], cmd.flush[3]); + return -EIO; + } + PRINT_FLOW("dmov_exec_cmdptr(%d, %x) done\n", id, cmdptr); + return 0; +} + + +static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) +{ + unsigned int int_status, mask, id; + unsigned long irq_flags; + unsigned int ch_status; + unsigned int ch_result; + struct msm_dmov_cmd *cmd; + + spin_lock_irqsave(&msm_dmov_lock, irq_flags); + + int_status = readl(DMOV_ISR); /* read and clear interrupt */ + PRINT_FLOW("msm_datamover_irq_handler: DMOV_ISR %x\n", int_status); + + while (int_status) { + mask = int_status & -int_status; + id = fls(mask) - 1; + PRINT_FLOW("msm_datamover_irq_handler %08x %08x id %d\n", int_status, mask, id); + int_status &= ~mask; + ch_status = readl(DMOV_STATUS(id)); + if (!(ch_status & DMOV_STATUS_RSLT_VALID)) { + PRINT_FLOW("msm_datamover_irq_handler id %d, result not valid %x\n", id, ch_status); + continue; + } + do { + ch_result = readl(DMOV_RSLT(id)); + if (list_empty(&active_commands[id])) { + PRINT_ERROR("msm_datamover_irq_handler id %d, got result " + "with no active command, status %x, result %x\n", + id, ch_status, ch_result); + cmd = NULL; + } else + cmd = list_entry(active_commands[id].next, typeof(*cmd), list); + PRINT_FLOW("msm_datamover_irq_handler id %d, status %x, result %x\n", id, ch_status, ch_result); + if (ch_result & DMOV_RSLT_DONE) { + PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", + id, ch_status); + PRINT_IO("msm_datamover_irq_handler id %d, got result " + "for %p, result %x\n", id, cmd, ch_result); + if (cmd) { + list_del(&cmd->list); + cmd->complete_func(cmd, ch_result); + } + } + if (ch_result & DMOV_RSLT_FLUSH) { + unsigned int flush0 = readl(DMOV_FLUSH0(id)); + PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); + PRINT_FLOW("msm_datamover_irq_handler id %d, flush, result %x, flush0 %x\n", id, ch_result, flush0); + if (cmd) { + list_del(&cmd->list); + cmd->complete_func(cmd, ch_result); + } + } + if (ch_result & DMOV_RSLT_ERROR) { + unsigned int flush0 = readl(DMOV_FLUSH0(id)); + PRINT_ERROR("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); + PRINT_ERROR("msm_datamover_irq_handler id %d, error, result %x, flush0 %x\n", id, ch_result, flush0); + if (cmd) { + list_del(&cmd->list); + cmd->complete_func(cmd, ch_result); + } + /* this does not seem to work, once we get an error */ + /* the datamover will no longer accept commands */ + writel(0, DMOV_FLUSH0(id)); + } + ch_status = readl(DMOV_STATUS(id)); + PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); + if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { + cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); + list_del(&cmd->list); + list_add_tail(&cmd->list, &active_commands[id]); + PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); + writel(cmd->cmdptr, DMOV_CMD_PTR(id)); + } + } while (ch_status & DMOV_STATUS_RSLT_VALID); + PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); + } + spin_unlock_irqrestore(&msm_dmov_lock, irq_flags); + return IRQ_HANDLED; +} + +static int __init msm_init_datamover(void) +{ + int i; + for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) { + INIT_LIST_HEAD(&ready_commands[i]); + INIT_LIST_HEAD(&active_commands[i]); + writel(DMOV_CONFIG_IRQ_EN | DMOV_CONFIG_FORCE_TOP_PTR_RSLT | DMOV_CONFIG_FORCE_FLUSH_RSLT, DMOV_CONFIG(i)); + } + return request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL); +} + +arch_initcall(msm_init_datamover); + diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S new file mode 100644 index 0000000..2b1cb7f --- /dev/null +++ b/arch/arm/mach-msm/idle.S @@ -0,0 +1,36 @@ +/* linux/include/asm-arm/arch-msm/idle.S + * + * Idle processing for MSM7K - work around bugs with SWFI. + * + * Copyright (c) 2007 QUALCOMM Incorporated. + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +ENTRY(arch_idle) +#ifdef CONFIG_MSM7X00A_IDLE + mrc p15, 0, r1, c1, c0, 0 /* read current CR */ + bic r0, r1, #(1 << 2) /* clear dcache bit */ + bic r0, r0, #(1 << 12) /* clear icache bit */ + mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ + + mov r0, #0 /* prepare wfi value */ + mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ + mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ + mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ + + mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ +#endif + mov pc, lr diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c new file mode 100644 index 0000000..c39edb9 --- /dev/null +++ b/arch/arm/mach-msm/io.c @@ -0,0 +1,85 @@ +/* arch/arm/mach-msm/io.c + * + * MSM7K io support + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define MSM_DEVICE(name) { \ + .virtual = MSM_##name##_BASE, \ + .pfn = __phys_to_pfn(MSM_##name##_PHYS), \ + .length = MSM_##name##_SIZE, \ + .type = MT_DEVICE_NONSHARED, \ + } + +static struct map_desc msm_io_desc[] __initdata = { + MSM_DEVICE(VIC), + MSM_DEVICE(CSR), + MSM_DEVICE(GPT), + MSM_DEVICE(DMOV), + MSM_DEVICE(UART1), + MSM_DEVICE(UART2), + MSM_DEVICE(UART3), + MSM_DEVICE(I2C), + MSM_DEVICE(GPIO1), + MSM_DEVICE(GPIO2), + MSM_DEVICE(HSUSB), + MSM_DEVICE(CLK_CTL), + MSM_DEVICE(PMDH), + MSM_DEVICE(EMDH), + MSM_DEVICE(MDP), + { + .virtual = MSM_SHARED_RAM_BASE, + .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), + .length = MSM_SHARED_RAM_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init msm_map_common_io(void) +{ + /* Make sure the peripheral register window is closed, since + * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which + * pages are peripheral interface or not. + */ + asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); + + iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); +} + +void __iomem * +__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) +{ + if (mtype == MT_DEVICE) { + /* The peripherals in the 88000000 - D0000000 range + * are only accessable by type MT_DEVICE_NONSHARED. + * Adjust mtype as necessary to make this "just work." + */ + if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000)) + mtype = MT_DEVICE_NONSHARED; + } + + return __arm_ioremap(phys_addr, size, mtype); +} diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c new file mode 100644 index 0000000..2415804 --- /dev/null +++ b/arch/arm/mach-msm/irq.c @@ -0,0 +1,154 @@ +/* linux/arch/arm/mach-msm/irq.c + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include + +#define VIC_REG(off) (MSM_VIC_BASE + (off)) + +#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_EN0 VIC_REG(0x0010) +#define VIC_INT_EN1 VIC_REG(0x0014) +#define VIC_INT_ENCLEAR0 VIC_REG(0x0020) +#define VIC_INT_ENCLEAR1 VIC_REG(0x0024) +#define VIC_INT_ENSET0 VIC_REG(0x0030) +#define VIC_INT_ENSET1 VIC_REG(0x0034) +#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */ +#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */ +#define VIC_NO_PEND_VAL VIC_REG(0x0060) +#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */ +#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */ +#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */ +#define VIC_IRQ_STATUS0 VIC_REG(0x0080) +#define VIC_IRQ_STATUS1 VIC_REG(0x0084) +#define VIC_FIQ_STATUS0 VIC_REG(0x0090) +#define VIC_FIQ_STATUS1 VIC_REG(0x0094) +#define VIC_RAW_STATUS0 VIC_REG(0x00A0) +#define VIC_RAW_STATUS1 VIC_REG(0x00A4) +#define VIC_INT_CLEAR0 VIC_REG(0x00B0) +#define VIC_INT_CLEAR1 VIC_REG(0x00B4) +#define VIC_SOFTINT0 VIC_REG(0x00C0) +#define VIC_SOFTINT1 VIC_REG(0x00C4) +#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */ +#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */ +#define VIC_IRQ_VEC_WR VIC_REG(0x00D8) +#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0) +#define VIC_IRQ_IN_STACK VIC_REG(0x00E4) +#define VIC_TEST_BUS_SEL VIC_REG(0x00E8) + +#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4)) +#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4)) + +static void msm_irq_ack(unsigned int irq) +{ + unsigned reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0); + irq = 1 << (irq & 31); + writel(irq, reg); +} + +static void msm_irq_mask(unsigned int irq) +{ + unsigned reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0); + writel(1 << (irq & 31), reg); +} + +static void msm_irq_unmask(unsigned int irq) +{ + unsigned reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0); + writel(1 << (irq & 31), reg); +} + +static int msm_irq_set_wake(unsigned int irq, unsigned int on) +{ + return -EINVAL; +} + +static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + unsigned treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0); + unsigned preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0); + int b = 1 << (irq & 31); + + if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) + writel(readl(preg) | b, preg); + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) + writel(readl(preg) & (~b), preg); + + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { + writel(readl(treg) | b, treg); + set_irq_handler(irq, handle_edge_irq); + } + if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { + writel(readl(treg) & (~b), treg); + set_irq_handler(irq, handle_level_irq); + } + return 0; +} + +static struct irq_chip msm_irq_chip = { + .name = "msm", + .ack = msm_irq_ack, + .mask = msm_irq_mask, + .unmask = msm_irq_unmask, + .set_wake = msm_irq_set_wake, + .set_type = msm_irq_set_type, +}; + +void __init msm_init_irq(void) +{ + unsigned n; + + /* select level interrupts */ + writel(0, VIC_INT_TYPE0); + writel(0, VIC_INT_TYPE1); + + /* select highlevel interrupts */ + writel(0, VIC_INT_POLARITY0); + writel(0, VIC_INT_POLARITY1); + + /* select IRQ for all INTs */ + writel(0, VIC_INT_SELECT0); + writel(0, VIC_INT_SELECT1); + + /* disable all INTs */ + writel(0, VIC_INT_EN0); + writel(0, VIC_INT_EN1); + + /* don't use 1136 vic */ + writel(0, VIC_CONFIG); + + /* enable interrupt controller */ + writel(1, VIC_INT_MASTEREN); + + for (n = 0; n < NR_MSM_IRQS; n++) { + set_irq_chip(n, &msm_irq_chip); + set_irq_handler(n, handle_level_irq); + set_irq_flags(n, IRQF_VALID); + } +} diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c new file mode 100644 index 0000000..bd4732d --- /dev/null +++ b/arch/arm/mach-msm/timer.c @@ -0,0 +1,205 @@ +/* linux/arch/arm/mach-msm/timer.c + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) +#define MSM_DGT_SHIFT (5) + +#define TIMER_MATCH_VAL 0x0000 +#define TIMER_COUNT_VAL 0x0004 +#define TIMER_ENABLE 0x0008 +#define TIMER_ENABLE_CLR_ON_MATCH_EN 2 +#define TIMER_ENABLE_EN 1 +#define TIMER_CLEAR 0x000C + +#define CSR_PROTECTION 0x0020 +#define CSR_PROTECTION_EN 1 + +#define GPT_HZ 32768 +#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */ + +struct msm_clock { + struct clock_event_device clockevent; + struct clocksource clocksource; + struct irqaction irq; + uint32_t regbase; + uint32_t freq; + uint32_t shift; +}; + +static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static cycle_t msm_gpt_read(void) +{ + return readl(MSM_GPT_BASE + TIMER_COUNT_VAL); +} + +static cycle_t msm_dgt_read(void) +{ + return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT; +} + +static int msm_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); + uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL); + uint32_t alarm = now + (cycles << clock->shift); + int late; + + writel(alarm, clock->regbase + TIMER_MATCH_VAL); + now = readl(clock->regbase + TIMER_COUNT_VAL); + late = now - alarm; + if (late >= (-2 << clock->shift) && late < DGT_HZ*5) { + printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, " + "alarm already expired, now %x, alarm %x, late %d\n", + cycles, clock->clockevent.name, now, alarm, late); + return -ETIME; + } + return 0; +} + +static void msm_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); + switch (mode) { + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_PERIODIC: + break; + case CLOCK_EVT_MODE_ONESHOT: + writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + writel(0, clock->regbase + TIMER_ENABLE); + break; + } +} + +static struct msm_clock msm_clocks[] = { + { + .clockevent = { + .name = "gp_timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 200, + .set_next_event = msm_timer_set_next_event, + .set_mode = msm_timer_set_mode, + }, + .clocksource = { + .name = "gp_timer", + .rating = 200, + .read = msm_gpt_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 24, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + }, + .irq = { + .name = "gp_timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING, + .handler = msm_timer_interrupt, + .dev_id = &msm_clocks[0].clockevent, + .irq = INT_GP_TIMER_EXP + }, + .regbase = MSM_GPT_BASE, + .freq = GPT_HZ + }, + { + .clockevent = { + .name = "dg_timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32 + MSM_DGT_SHIFT, + .rating = 300, + .set_next_event = msm_timer_set_next_event, + .set_mode = msm_timer_set_mode, + }, + .clocksource = { + .name = "dg_timer", + .rating = 300, + .read = msm_dgt_read, + .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), + .shift = 24 - MSM_DGT_SHIFT, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + }, + .irq = { + .name = "dg_timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING, + .handler = msm_timer_interrupt, + .dev_id = &msm_clocks[1].clockevent, + .irq = INT_DEBUG_TIMER_EXP + }, + .regbase = MSM_DGT_BASE, + .freq = DGT_HZ >> MSM_DGT_SHIFT, + .shift = MSM_DGT_SHIFT + } +}; + +static void __init msm_timer_init(void) +{ + int i; + int res; + + for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) { + struct msm_clock *clock = &msm_clocks[i]; + struct clock_event_device *ce = &clock->clockevent; + struct clocksource *cs = &clock->clocksource; + writel(0, clock->regbase + TIMER_ENABLE); + writel(0, clock->regbase + TIMER_CLEAR); + writel(~0, clock->regbase + TIMER_MATCH_VAL); + + ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift); + /* allow at least 10 seconds to notice that the timer wrapped */ + ce->max_delta_ns = + clockevent_delta2ns(0xf0000000 >> clock->shift, ce); + /* 4 gets rounded down to 3 */ + ce->min_delta_ns = clockevent_delta2ns(4, ce); + ce->cpumask = cpumask_of_cpu(0); + + cs->mult = clocksource_hz2mult(clock->freq, cs->shift); + res = clocksource_register(cs); + if (res) + printk(KERN_ERR "msm_timer_init: clocksource_register " + "failed for %s\n", cs->name); + + res = setup_irq(clock->irq.irq, &clock->irq); + if (res) + printk(KERN_ERR "msm_timer_init: setup_irq " + "failed for %s\n", cs->name); + + clockevents_register_device(ce); + } +} + +struct sys_timer msm_timer = { + .init = msm_timer_init +}; diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index f65baa9..69c211f 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -78,7 +78,7 @@ static struct resource smc91x_resources[] = { [1] = { .start = INT_730_MPU_EXT_NIRQ, .end = 0, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 1306812..60c4057 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -209,7 +209,7 @@ static struct resource h2_smc91x_resources[] = { [1] = { .start = OMAP_GPIO_IRQ(0), .end = OMAP_GPIO_IRQ(0), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 4f84ae2..15b502e 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -208,7 +208,7 @@ static struct resource smc91x_resources[] = { [1] = { .start = OMAP_GPIO_IRQ(40), .end = OMAP_GPIO_IRQ(40), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 7e63a41..7d2d8af 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -202,7 +202,7 @@ static struct resource innovator1510_smc91x_resources[] = { [1] = { .start = OMAP1510_INT_ETHER, .end = OMAP1510_INT_ETHER, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; @@ -269,7 +269,7 @@ static struct resource innovator1610_smc91x_resources[] = { [1] = { .start = OMAP_GPIO_IRQ(0), .end = OMAP_GPIO_IRQ(0), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 22db19a..3903d37 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 5db182d..5b2d578 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include @@ -111,7 +110,7 @@ static struct resource osk5912_smc91x_resources[] = { [1] = { .start = OMAP_GPIO_IRQ(0), .end = OMAP_GPIO_IRQ(0), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index e47010f..ed7094a 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -42,7 +42,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index c275d51..a9a0f66 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -44,7 +44,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 1d5c8d5..da94aee 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -77,7 +77,7 @@ static struct resource smc91x_resources[] = { [1] = { .start = INT_730_MPU_EXT_NIRQ, .end = 0, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 214dd19..c82a1cd 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -117,7 +117,7 @@ static struct resource voiceblue_smc91x_resources[] = { [1] = { .start = OMAP_GPIO_IRQ(8), .end = OMAP_GPIO_IRQ(8), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 3bf01e2..94c299b 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -646,7 +646,7 @@ static void omap_pm_finish(void) } -static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) +static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) { return IRQ_HANDLED; } diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 7e76fbf..64235de 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -104,7 +104,7 @@ static struct resource sdp2430_smc91x_resources[] = { [1] = { .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 3bb49c1..7846551 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -127,7 +126,7 @@ static struct resource apollon_smc91x_resources[] = { [1] = { .start = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ), .end = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion/Kconfig new file mode 100644 index 0000000..1dcbb6a --- /dev/null +++ b/arch/arm/mach-orion/Kconfig @@ -0,0 +1,41 @@ +if ARCH_ORION + +menu "Orion Implementations" + +config MACH_DB88F5281 + bool "Marvell Orion-2 Development Board" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Marvell Orion-2 (88F5281) Development Board + +config MACH_RD88F5182 + bool "Marvell Orion-NAS Reference Design" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Marvell Orion-NAS (88F5182) RD2 + +config MACH_KUROBOX_PRO + bool "KuroBox Pro" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + KuroBox Pro platform. + +config MACH_DNS323 + bool "D-Link DNS-323" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + D-Link DNS-323 platform. + +config MACH_TS209 + bool "QNAP TS-109/TS-209" + help + Say 'Y' here if you want your kernel to support the + QNAP TS-109/TS-209 platform. + +endmenu + +endif diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion/Makefile new file mode 100644 index 0000000..f91d937 --- /dev/null +++ b/arch/arm/mach-orion/Makefile @@ -0,0 +1,6 @@ +obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o +obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o +obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o +obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o +obj-$(CONFIG_MACH_DNS323) += dns323-setup.o +obj-$(CONFIG_MACH_TS209) += ts209-setup.o diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion/Makefile.boot new file mode 100644 index 0000000..67039c3 --- /dev/null +++ b/arch/arm/mach-orion/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c new file mode 100644 index 0000000..488da38 --- /dev/null +++ b/arch/arm/mach-orion/addr-map.c @@ -0,0 +1,484 @@ +/* + * arch/arm/mach-orion/addr-map.c + * + * Address map functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include "common.h" + +/* + * The Orion has fully programable address map. There's a separate address + * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, + * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own + * address decode windows that allow it to access any of the Orion resources. + * + * CPU address decoding -- + * Linux assumes that it is the boot loader that already setup the access to + * DDR and internal registers. + * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. + * Setup access to various devices located on the device bus interface (e.g. + * flashes, RTC, etc) should be issued by machine-setup.c according to + * specific board population (by using orion_setup_cpu_win()). + * + * Non-CPU Masters address decoding -- + * Unlike the CPU, we setup the access from Orion's master interfaces to DDR + * banks only (the typical use case). + * Setup access for each master to DDR is issued by common.c. + * + * Note: although orion_setbits() and orion_clrbits() are not atomic + * no locking is necessary here since code in this file is only called + * at boot time when there is no concurrency issues. + */ + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0 +#define TARGET_PCI 3 +#define TARGET_PCIE 4 +#define TARGET_DEV_BUS 1 +#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ + ((n) == 1) ? 0xd : \ + ((n) == 2) ? 0xb : \ + ((n) == 3) ? 0x7 : 0xf) +#define ATTR_PCIE_MEM 0x59 +#define ATTR_PCIE_IO 0x51 +#define ATTR_PCI_MEM 0x59 +#define ATTR_PCI_IO 0x51 +#define ATTR_DEV_CS0 0x1e +#define ATTR_DEV_CS1 0x1d +#define ATTR_DEV_CS2 0x1b +#define ATTR_DEV_BOOT 0xf +#define WIN_EN 1 + +/* + * Helpers to get DDR banks info + */ +#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) +#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) +#define DDR_MAX_CS 4 +#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) +#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) +#define DDR_BANK_EN 1 + +/* + * CPU Address Decode Windows registers + */ +#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) +#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) +#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) +#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) +#define CPU_MAX_WIN 8 + +/* + * Use this CPU address decode windows allocation + */ +#define CPU_WIN_PCIE_IO 0 +#define CPU_WIN_PCI_IO 1 +#define CPU_WIN_PCIE_MEM 2 +#define CPU_WIN_PCI_MEM 3 +#define CPU_WIN_DEV_BOOT 4 +#define CPU_WIN_DEV_CS0 5 +#define CPU_WIN_DEV_CS1 6 +#define CPU_WIN_DEV_CS2 7 + +/* + * PCIE Address Decode Windows registers + */ +#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) +#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) +#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) +#define PCIE_WIN_CTRL(n) ORION_PCIE_REG(0x1820 + ((n) << 4)) +#define PCIE_WIN_BASE(n) ORION_PCIE_REG(0x1824 + ((n) << 4)) +#define PCIE_WIN_REMAP(n) ORION_PCIE_REG(0x182c + ((n) << 4)) +#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) +#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) +#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) +#define PCIE_MAX_BARS 3 +#define PCIE_MAX_WINS 5 + +/* + * Use PCIE BAR '1' for all DDR banks + */ +#define PCIE_DRAM_BAR 1 + +/* + * PCI Address Decode Windows registers + */ +#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ + ((n) == 1) ? ORION_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) +#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) +#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4)) +#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4)) +#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4)) +#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) + +/* + * PCI configuration heleprs for BAR settings + */ +#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) +#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) +#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) + +/* + * Gigabit Ethernet Address Decode Windows registers + */ +#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) +#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) +#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) +#define ETH_WIN_EN ORION_ETH_REG(0x290) +#define ETH_WIN_PROT ORION_ETH_REG(0x294) +#define ETH_MAX_WIN 6 +#define ETH_MAX_REMAP_WIN 4 + +/* + * USB Address Decode Windows registers + */ +#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \ + : ORION_USB1_REG(0x320 + ((w) << 4))) +#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \ + : ORION_USB1_REG(0x324 + ((w) << 4))) +#define USB_MAX_WIN 4 + +/* + * SATA Address Decode Windows registers + */ +#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) +#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) +#define SATA_MAX_WIN 4 + +static int __init orion_cpu_win_can_remap(u32 win) +{ + u32 dev, rev; + + orion_pcie_id(&dev, &rev); + if ((dev == MV88F5281_DEV_ID && win < 4) + || (dev == MV88F5182_DEV_ID && win < 2) + || (dev == MV88F5181_DEV_ID && win < 2)) + return 1; + + return 0; +} + +void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) +{ + u32 win, attr, ctrl; + + switch (target) { + case ORION_PCIE_IO: + target = TARGET_PCIE; + attr = ATTR_PCIE_IO; + win = CPU_WIN_PCIE_IO; + break; + case ORION_PCI_IO: + target = TARGET_PCI; + attr = ATTR_PCI_IO; + win = CPU_WIN_PCI_IO; + break; + case ORION_PCIE_MEM: + target = TARGET_PCIE; + attr = ATTR_PCIE_MEM; + win = CPU_WIN_PCIE_MEM; + break; + case ORION_PCI_MEM: + target = TARGET_PCI; + attr = ATTR_PCI_MEM; + win = CPU_WIN_PCI_MEM; + break; + case ORION_DEV_BOOT: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_BOOT; + win = CPU_WIN_DEV_BOOT; + break; + case ORION_DEV0: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_CS0; + win = CPU_WIN_DEV_CS0; + break; + case ORION_DEV1: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_CS1; + win = CPU_WIN_DEV_CS1; + break; + case ORION_DEV2: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_CS2; + win = CPU_WIN_DEV_CS2; + break; + case ORION_DDR: + case ORION_REGS: + /* + * Must be mapped by bootloader. + */ + default: + target = attr = win = -1; + BUG(); + } + + base &= 0xffff0000; + ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | + (target << 4) | WIN_EN); + + orion_write(CPU_WIN_BASE(win), base); + orion_write(CPU_WIN_CTRL(win), ctrl); + + if (orion_cpu_win_can_remap(win)) { + if (remap >= 0) { + orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); + orion_write(CPU_WIN_REMAP_HI(win), 0); + } else { + orion_write(CPU_WIN_REMAP_LO(win), base); + orion_write(CPU_WIN_REMAP_HI(win), 0); + } + } +} + +void __init orion_setup_cpu_wins(void) +{ + int i; + + /* + * First, disable and clear windows + */ + for (i = 0; i < CPU_MAX_WIN; i++) { + orion_write(CPU_WIN_BASE(i), 0); + orion_write(CPU_WIN_CTRL(i), 0); + if (orion_cpu_win_can_remap(i)) { + orion_write(CPU_WIN_REMAP_LO(i), 0); + orion_write(CPU_WIN_REMAP_HI(i), 0); + } + } + + /* + * Setup windows for PCI+PCIE IO+MAM space + */ + orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE, + ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP); + orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE, + ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP); + orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE, + ORION_PCIE_MEM_SIZE, -1); + orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE, + ORION_PCI_MEM_SIZE, -1); +} + +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks + * WIN[0-3] -> DRAM bank[0-3] + */ +void __init orion_setup_pcie_wins(void) +{ + u32 base, size, i; + + /* + * First, disable and clear BARs and windows + */ + for (i = 1; i < PCIE_MAX_BARS; i++) { + orion_write(PCIE_BAR_CTRL(i), 0); + orion_write(PCIE_BAR_LO(i), 0); + orion_write(PCIE_BAR_HI(i), 0); + } + + for (i = 0; i < PCIE_MAX_WINS; i++) { + orion_write(PCIE_WIN_CTRL(i), 0); + orion_write(PCIE_WIN_BASE(i), 0); + orion_write(PCIE_WIN_REMAP(i), 0); + } + + /* + * Setup windows for DDR banks. Count total DDR size on the fly. + */ + base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0))); + size = 0; + for (i = 0; i < DDR_MAX_CS; i++) { + u32 bank_base, bank_size; + bank_size = orion_read(DDR_SIZE_CS(i)); + bank_base = orion_read(DDR_BASE_CS(i)); + if (bank_size & DDR_BANK_EN) { + bank_size = DDR_REG_TO_SIZE(bank_size); + bank_base = DDR_REG_TO_BASE(bank_base); + orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000); + orion_write(PCIE_WIN_REMAP(i), 0); + orion_write(PCIE_WIN_CTRL(i), + ((bank_size-1) & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + (TARGET_DDR << 4) | + (PCIE_DRAM_BAR << 1) | WIN_EN); + size += bank_size; + } + } + + /* + * Setup BAR[1] to all DRAM banks + */ + orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000); + orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0); + orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR), + ((size - 1) & 0xffff0000) | WIN_EN); +} + +void __init orion_setup_pci_wins(void) +{ + u32 base, size, i; + + /* + * First, disable windows + */ + orion_write(PCI_BAR_ENABLE, 0xffffffff); + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + base = orion_read(DDR_BASE_CS(i)); + size = orion_read(DDR_SIZE_CS(i)); + if (size & DDR_BANK_EN) { + u32 bus, dev, func, reg, val; + size = DDR_REG_TO_SIZE(size); + base = DDR_REG_TO_BASE(base); + bus = orion_pci_local_bus_nr(); + dev = orion_pci_local_dev_nr(); + func = PCI_CONF_FUNC_BAR_CS(i); + reg = PCI_CONF_REG_BAR_LO_CS(i); + orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, + (base & 0xfffff000) | (val & 0xfff)); + reg = PCI_CONF_REG_BAR_HI_CS(i); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); + orion_write(PCI_BAR_SIZE_DDR_CS(i), + (size - 1) & 0xfffff000); + orion_write(PCI_BAR_REMAP_DDR_CS(i), + base & 0xfffff000); + orion_clrbits(PCI_BAR_ENABLE, (1 << i)); + } + } + + /* + * Disable automatic update of address remaping when writing to BARs + */ + orion_setbits(PCI_ADDR_DECODE_CTRL, 1); +} + +void __init orion_setup_usb_wins(void) +{ + int i; + u32 usb_if, dev, rev; + u32 max_usb_if = 1; + + orion_pcie_id(&dev, &rev); + if (dev == MV88F5182_DEV_ID) + max_usb_if = 2; + + for (usb_if = 0; usb_if < max_usb_if; usb_if++) { + /* + * First, disable and clear windows + */ + for (i = 0; i < USB_MAX_WIN; i++) { + orion_write(USB_WIN_BASE(usb_if, i), 0); + orion_write(USB_WIN_CTRL(usb_if, i), 0); + } + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + u32 base, size; + size = orion_read(DDR_SIZE_CS(i)); + base = orion_read(DDR_BASE_CS(i)); + if (size & DDR_BANK_EN) { + base = DDR_REG_TO_BASE(base); + size = DDR_REG_TO_SIZE(size); + orion_write(USB_WIN_CTRL(usb_if, i), + ((size-1) & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + (TARGET_DDR << 4) | WIN_EN); + orion_write(USB_WIN_BASE(usb_if, i), + base & 0xffff0000); + } + } + } +} + +void __init orion_setup_eth_wins(void) +{ + int i; + + /* + * First, disable and clear windows + */ + for (i = 0; i < ETH_MAX_WIN; i++) { + orion_write(ETH_WIN_BASE(i), 0); + orion_write(ETH_WIN_SIZE(i), 0); + orion_setbits(ETH_WIN_EN, 1 << i); + orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); + if (i < ETH_MAX_REMAP_WIN) + orion_write(ETH_WIN_REMAP(i), 0); + } + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + u32 base, size; + size = orion_read(DDR_SIZE_CS(i)); + base = orion_read(DDR_BASE_CS(i)); + if (size & DDR_BANK_EN) { + base = DDR_REG_TO_BASE(base); + size = DDR_REG_TO_SIZE(size); + orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); + orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + TARGET_DDR); + orion_clrbits(ETH_WIN_EN, 1 << i); + orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); + } + } +} + +void __init orion_setup_sata_wins(void) +{ + int i; + + /* + * First, disable and clear windows + */ + for (i = 0; i < SATA_MAX_WIN; i++) { + orion_write(SATA_WIN_BASE(i), 0); + orion_write(SATA_WIN_CTRL(i), 0); + } + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + u32 base, size; + size = orion_read(DDR_SIZE_CS(i)); + base = orion_read(DDR_BASE_CS(i)); + if (size & DDR_BANK_EN) { + base = DDR_REG_TO_BASE(base); + size = DDR_REG_TO_SIZE(size); + orion_write(SATA_WIN_CTRL(i), + ((size-1) & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + (TARGET_DDR << 4) | WIN_EN); + orion_write(SATA_WIN_BASE(i), + base & 0xffff0000); + } + } +} diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c new file mode 100644 index 0000000..5e20b6b --- /dev/null +++ b/arch/arm/mach-orion/common.c @@ -0,0 +1,315 @@ +/* + * arch/arm/mach-orion/common.c + * + * Core functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc orion_io_desc[] __initdata = { + { + .virtual = ORION_REGS_BASE, + .pfn = __phys_to_pfn(ORION_REGS_BASE), + .length = ORION_REGS_SIZE, + .type = MT_DEVICE + }, + { + .virtual = ORION_PCIE_IO_BASE, + .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE), + .length = ORION_PCIE_IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = ORION_PCI_IO_BASE, + .pfn = __phys_to_pfn(ORION_PCI_IO_BASE), + .length = ORION_PCI_IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = ORION_PCIE_WA_BASE, + .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE), + .length = ORION_PCIE_WA_SIZE, + .type = MT_DEVICE + }, +}; + +void __init orion_map_io(void) +{ + iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); +} + +/***************************************************************************** + * UART + ****************************************************************************/ + +static struct resource orion_uart_resources[] = { + { + .start = UART0_BASE, + .end = UART0_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION_UART0, + .end = IRQ_ORION_UART0, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART1_BASE, + .end = UART1_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION_UART1, + .end = IRQ_ORION_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct plat_serial8250_port orion_uart_data[] = { + { + .mapbase = UART0_BASE, + .membase = (char *)UART0_BASE, + .irq = IRQ_ORION_UART0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = ORION_TCLK, + }, + { + .mapbase = UART1_BASE, + .membase = (char *)UART1_BASE, + .irq = IRQ_ORION_UART1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = ORION_TCLK, + }, + { }, +}; + +static struct platform_device orion_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = orion_uart_data, + }, + .resource = orion_uart_resources, + .num_resources = ARRAY_SIZE(orion_uart_resources), +}; + +/******************************************************************************* + * USB Controller - 2 interfaces + ******************************************************************************/ + +static struct resource orion_ehci0_resources[] = { + { + .start = ORION_USB0_REG_BASE, + .end = ORION_USB0_REG_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION_USB0_CTRL, + .end = IRQ_ORION_USB0_CTRL, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource orion_ehci1_resources[] = { + { + .start = ORION_USB1_REG_BASE, + .end = ORION_USB1_REG_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ORION_USB1_CTRL, + .end = IRQ_ORION_USB1_CTRL, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = 0xffffffffUL; + +static struct platform_device orion_ehci0 = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = orion_ehci0_resources, + .num_resources = ARRAY_SIZE(orion_ehci0_resources), +}; + +static struct platform_device orion_ehci1 = { + .name = "orion-ehci", + .id = 1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = orion_ehci1_resources, + .num_resources = ARRAY_SIZE(orion_ehci1_resources), +}; + +/***************************************************************************** + * Gigabit Ethernet port + * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) + ****************************************************************************/ + +static struct resource orion_eth_shared_resources[] = { + { + .start = ORION_ETH_REG_BASE, + .end = ORION_ETH_REG_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion_eth_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .num_resources = 1, + .resource = orion_eth_shared_resources, +}; + +static struct resource orion_eth_resources[] = { + { + .name = "eth irq", + .start = IRQ_ORION_ETH_SUM, + .end = IRQ_ORION_ETH_SUM, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device orion_eth = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = orion_eth_resources, +}; + +void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) +{ + orion_eth.dev.platform_data = eth_data; + platform_device_register(&orion_eth_shared); + platform_device_register(&orion_eth); +} + +/***************************************************************************** + * I2C controller + * (The Orion and Discovery (MV643xx) families share the same I2C controller) + ****************************************************************************/ + +static struct mv64xxx_i2c_pdata orion_i2c_pdata = { + .freq_m = 8, /* assumes 166 MHz TCLK */ + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource orion_i2c_resources[] = { + { + .name = "i2c base", + .start = I2C_BASE, + .end = I2C_BASE + 0x20 -1, + .flags = IORESOURCE_MEM, + }, + { + .name = "i2c irq", + .start = IRQ_ORION_I2C, + .end = IRQ_ORION_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_i2c = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(orion_i2c_resources), + .resource = orion_i2c_resources, + .dev = { + .platform_data = &orion_i2c_pdata, + }, +}; + +/***************************************************************************** + * General + ****************************************************************************/ + +/* + * Identify device ID and rev from PCIE configuration header space '0'. + */ +static void orion_id(u32 *dev, u32 *rev, char **dev_name) +{ + orion_pcie_id(dev, rev); + + if (*dev == MV88F5281_DEV_ID) { + if (*rev == MV88F5281_REV_D2) { + *dev_name = "MV88F5281-D2"; + } else if (*rev == MV88F5281_REV_D1) { + *dev_name = "MV88F5281-D1"; + } else { + *dev_name = "MV88F5281-Rev-Unsupported"; + } + } else if (*dev == MV88F5182_DEV_ID) { + if (*rev == MV88F5182_REV_A2) { + *dev_name = "MV88F5182-A2"; + } else { + *dev_name = "MV88F5182-Rev-Unsupported"; + } + } else if (*dev == MV88F5181_DEV_ID) { + if (*rev == MV88F5181_REV_B1) { + *dev_name = "MV88F5181-Rev-B1"; + } else { + *dev_name = "MV88F5181-Rev-Unsupported"; + } + } else { + *dev_name = "Device-Unknown"; + } +} + +void __init orion_init(void) +{ + char *dev_name; + u32 dev, rev; + + orion_id(&dev, &rev, &dev_name); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); + + /* + * Setup Orion address map + */ + orion_setup_cpu_wins(); + orion_setup_usb_wins(); + orion_setup_eth_wins(); + orion_setup_pci_wins(); + orion_setup_pcie_wins(); + if (dev == MV88F5182_DEV_ID) + orion_setup_sata_wins(); + + /* + * REgister devices + */ + platform_device_register(&orion_uart); + platform_device_register(&orion_ehci0); + if (dev == MV88F5182_DEV_ID) + platform_device_register(&orion_ehci1); + platform_device_register(&orion_i2c); +} diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h new file mode 100644 index 0000000..06c10c0 --- /dev/null +++ b/arch/arm/mach-orion/common.h @@ -0,0 +1,78 @@ +#ifndef __ARCH_ORION_COMMON_H__ +#define __ARCH_ORION_COMMON_H__ + +/* + * Basic Orion init functions used early by machine-setup. + */ + +void __init orion_map_io(void); +void __init orion_init_irq(void); +void __init orion_init(void); + +/* + * Enumerations and functions for Orion windows mapping. Used by Orion core + * functions to map its interfaces and by the machine-setup to map its on- + * board devices. Details in /mach-orion/addr-map.c + */ + +enum orion_target { + ORION_DEV_BOOT = 0, + ORION_DEV0, + ORION_DEV1, + ORION_DEV2, + ORION_PCIE_MEM, + ORION_PCIE_IO, + ORION_PCI_MEM, + ORION_PCI_IO, + ORION_DDR, + ORION_REGS, + ORION_MAX_TARGETS +}; + +void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); +void orion_setup_cpu_wins(void); +void orion_setup_eth_wins(void); +void orion_setup_usb_wins(void); +void orion_setup_pci_wins(void); +void orion_setup_pcie_wins(void); +void orion_setup_sata_wins(void); + +/* + * Shared code used internally by other Orion core functions. + * (/mach-orion/pci.c) + */ + +struct pci_sys_data; +struct pci_bus; + +void orion_pcie_id(u32 *dev, u32 *rev); +u32 orion_pcie_local_bus_nr(void); +u32 orion_pci_local_bus_nr(void); +u32 orion_pci_local_dev_nr(void); +int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); +int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val); +int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val); + +/* + * Valid GPIO pins according to MPP setup, used by machine-setup. + * (/mach-orion/gpio.c). + */ + +void __init orion_gpio_set_valid_pins(u32 pins); +void gpio_display(void); /* debug */ + +/* + * Orion system timer (clocksource + clockevnt, /mach-orion/time.c) + */ +extern struct sys_timer orion_timer; + +/* + * Pull in Orion Ethernet platform_data, used by machine-setup + */ + +struct mv643xx_eth_platform_data; + +void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); + +#endif /* __ARCH_ORION_COMMON_H__ */ diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c new file mode 100644 index 0000000..cb2a95c --- /dev/null +++ b/arch/arm/mach-orion/db88f5281-setup.c @@ -0,0 +1,364 @@ +/* + * arch/arm/mach-orion/db88f5281-setup.c + * + * Marvell Orion-2 Development Board Setup + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * DB-88F5281 on board devices + ****************************************************************************/ + +/* + * 512K NOR flash Device bus boot chip select + */ + +#define DB88F5281_NOR_BOOT_BASE 0xf4000000 +#define DB88F5281_NOR_BOOT_SIZE SZ_512K + +/* + * 7-Segment on Device bus chip select 0 + */ + +#define DB88F5281_7SEG_BASE 0xfa000000 +#define DB88F5281_7SEG_SIZE SZ_1K + +/* + * 32M NOR flash on Device bus chip select 1 + */ + +#define DB88F5281_NOR_BASE 0xfc000000 +#define DB88F5281_NOR_SIZE SZ_32M + +/* + * 32M NAND flash on Device bus chip select 2 + */ + +#define DB88F5281_NAND_BASE 0xfa800000 +#define DB88F5281_NAND_SIZE SZ_1K + +/* + * PCI + */ + +#define DB88F5281_PCI_SLOT0_OFFS 7 +#define DB88F5281_PCI_SLOT0_IRQ_PIN 12 +#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13 + +/***************************************************************************** + * 512M NOR Flash on Device bus Boot CS + ****************************************************************************/ + +static struct physmap_flash_data db88f5281_boot_flash_data = { + .width = 1, /* 8 bit bus width */ +}; + +static struct resource db88f5281_boot_flash_resource = { + .flags = IORESOURCE_MEM, + .start = DB88F5281_NOR_BOOT_BASE, + .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device db88f5281_boot_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &db88f5281_boot_flash_data, + }, + .num_resources = 1, + .resource = &db88f5281_boot_flash_resource, +}; + +/***************************************************************************** + * 32M NOR Flash on Device bus CS1 + ****************************************************************************/ + +static struct physmap_flash_data db88f5281_nor_flash_data = { + .width = 4, /* 32 bit bus width */ +}; + +static struct resource db88f5281_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = DB88F5281_NOR_BASE, + .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1, +}; + +static struct platform_device db88f5281_nor_flash = { + .name = "physmap-flash", + .id = 1, + .dev = { + .platform_data = &db88f5281_nor_flash_data, + }, + .num_resources = 1, + .resource = &db88f5281_nor_flash_resource, +}; + +/***************************************************************************** + * 32M NAND Flash on Device bus CS2 + ****************************************************************************/ + +static struct mtd_partition db88f5281_nand_parts[] = { + { + .name = "kernel", + .offset = 0, + .size = SZ_2M, + }, + { + .name = "root", + .offset = SZ_2M, + .size = (SZ_16M - SZ_2M), + }, + { + .name = "user", + .offset = SZ_16M, + .size = SZ_8M, + }, + { + .name = "recovery", + .offset = (SZ_16M + SZ_8M), + .size = SZ_8M, + }, +}; + +static struct resource db88f5281_nand_resource = { + .flags = IORESOURCE_MEM, + .start = DB88F5281_NAND_BASE, + .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1, +}; + +static struct orion_nand_data db88f5281_nand_data = { + .parts = db88f5281_nand_parts, + .nr_parts = ARRAY_SIZE(db88f5281_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, +}; + +static struct platform_device db88f5281_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &db88f5281_nand_data, + }, + .resource = &db88f5281_nand_resource, + .num_resources = 1, +}; + +/***************************************************************************** + * 7-Segment on Device bus CS0 + * Dummy counter every 2 sec + ****************************************************************************/ + +static void __iomem *db88f5281_7seg; +static struct timer_list db88f5281_timer; + +static void db88f5281_7seg_event(unsigned long data) +{ + static int count = 0; + writel(0, db88f5281_7seg + (count << 4)); + count = (count + 1) & 7; + mod_timer(&db88f5281_timer, jiffies + 2 * HZ); +} + +static int __init db88f5281_7seg_init(void) +{ + if (machine_is_db88f5281()) { + db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE, + DB88F5281_7SEG_SIZE); + if (!db88f5281_7seg) { + printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n"); + return -EIO; + } + setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0); + mod_timer(&db88f5281_timer, jiffies + 2 * HZ); + } + + return 0; +} + +__initcall(db88f5281_7seg_init); + +/***************************************************************************** + * PCI + ****************************************************************************/ + +void __init db88f5281_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = DB88F5281_PCI_SLOT0_IRQ_PIN; + if (gpio_request(pin, "PCI Int1") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "db88f5281_pci_preinit faield to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); + } + + pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; + if (gpio_request(pin, "PCI Int2") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "db88f5281_pci_preinit faield " + "to set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); + } +} + +static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCIE IRQ is connected internally (not GPIO) + */ + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - DB88F5281_PCI_SLOT0_OFFS) { + case 0: + return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN); + case 1: + case 2: + return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN); + default: + return -1; + } +} + +static struct hw_pci db88f5281_pci __initdata = { + .nr_controllers = 2, + .preinit = db88f5281_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, + .map_irq = db88f5281_pci_map_irq, +}; + +static int __init db88f5281_pci_init(void) +{ + if (machine_is_db88f5281()) + pci_common_init(&db88f5281_pci); + + return 0; +} + +subsys_initcall(db88f5281_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ +static struct mv643xx_eth_platform_data db88f5281_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC DS1339 on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata db88f5281_i2c_rtc = { + .driver_name = "rtc-ds1307", + .type = "ds1339", + .addr = 0x68, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static struct platform_device *db88f5281_devs[] __initdata = { + &db88f5281_boot_flash, + &db88f5281_nor_flash, + &db88f5281_nand_flash, +}; + +static void __init db88f5281_init(void) +{ + /* + * Basic Orion setup. Need to be called early. + */ + orion_init(); + + /* + * Setup the CPU address decode windows for our on-board devices + */ + orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE, -1); + orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE, + DB88F5281_7SEG_SIZE, -1); + orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE, + DB88F5281_NOR_SIZE, -1); + orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE, + DB88F5281_NAND_SIZE, -1); + + /* + * Setup Multiplexing Pins: + * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input) + * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2] + * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3] + * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1) + * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3) + * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator) + * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2) + * MPP14: NAND_REn[2] MPP15: NAND_WEn[2] + * MPP16: UART1_RX MPP17: UART1_TX + * MPP18: UART1_CTS MPP19: UART1_RTS + * MPP-DEV: DEV_D[16:31] + */ + orion_write(MPP_0_7_CTRL, 0x00222203); + orion_write(MPP_8_15_CTRL, 0x44000000); + orion_write(MPP_16_19_CTRL, 0); + orion_write(MPP_DEV_CTRL, 0); + + orion_gpio_set_valid_pins(0x00003fc3); + + platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); + i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); + orion_eth_init(&db88f5281_eth_data); +} + +MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") + /* Maintainer: Tzachi Perelstein */ + .phys_io = ORION_REGS_BASE, + .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = db88f5281_init, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, +MACHINE_END diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c new file mode 100644 index 0000000..c8a806f --- /dev/null +++ b/arch/arm/mach-orion/dns323-setup.c @@ -0,0 +1,322 @@ +/* + * arch/arm/mach-orion/dns323-setup.c + * + * Copyright (C) 2007 Herbert Valerio Riedel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define DNS323_GPIO_LED_RIGHT_AMBER 1 +#define DNS323_GPIO_LED_LEFT_AMBER 2 +#define DNS323_GPIO_LED_POWER 5 +#define DNS323_GPIO_OVERTEMP 6 +#define DNS323_GPIO_RTC 7 +#define DNS323_GPIO_POWER_OFF 8 +#define DNS323_GPIO_KEY_POWER 9 +#define DNS323_GPIO_KEY_RESET 10 + +/**************************************************************************** + * PCI setup + */ + +static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* PCI-E */ + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; + + pr_err("%s: requested mapping for unknown bus\n", __func__); + + return -1; +} + +static struct hw_pci dns323_pci __initdata = { + .nr_controllers = 1, + .swizzle = pci_std_swizzle, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, + .map_irq = dns323_pci_map_irq, +}; + +static int __init dns323_pci_init(void) +{ + if (machine_is_dns323()) + pci_common_init(&dns323_pci); + + return 0; +} + +subsys_initcall(dns323_pci_init); + +/**************************************************************************** + * Ethernet + */ + +static struct mv643xx_eth_platform_data dns323_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/**************************************************************************** + * 8MiB NOR flash (Spansion S29GL064M90TFIR4) + * + * Layout as used by D-Link: + * 0x00000000-0x00010000 : "MTD1" + * 0x00010000-0x00020000 : "MTD2" + * 0x00020000-0x001a0000 : "Linux Kernel" + * 0x001a0000-0x007d0000 : "File System" + * 0x007d0000-0x00800000 : "u-boot" + */ + +#define DNS323_NOR_BOOT_BASE 0xf4000000 +#define DNS323_NOR_BOOT_SIZE SZ_8M + +static struct mtd_partition dns323_partitions[] = { + { + .name = "MTD1", + .size = 0x00010000, + .offset = 0, + }, { + .name = "MTD2", + .size = 0x00010000, + .offset = 0x00010000, + }, { + .name = "Linux Kernel", + .size = 0x00180000, + .offset = 0x00020000, + }, { + .name = "File System", + .size = 0x00630000, + .offset = 0x001A0000, + }, { + .name = "u-boot", + .size = 0x00030000, + .offset = 0x007d0000, + } +}; + +static struct physmap_flash_data dns323_nor_flash_data = { + .width = 1, + .parts = dns323_partitions, + .nr_parts = ARRAY_SIZE(dns323_partitions) +}; + +static struct resource dns323_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = DNS323_NOR_BOOT_BASE, + .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device dns323_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { .platform_data = &dns323_nor_flash_data, }, + .resource = &dns323_nor_flash_resource, + .num_resources = 1, +}; + +/**************************************************************************** + * GPIO LEDs (simple - doesn't use hardware blinking support) + */ + +static struct gpio_led dns323_leds[] = { + { + .name = "power:blue", + .gpio = DNS323_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "right:amber", + .gpio = DNS323_GPIO_LED_RIGHT_AMBER, + .active_low = 1, + }, { + .name = "left:amber", + .gpio = DNS323_GPIO_LED_LEFT_AMBER, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data dns323_led_data = { + .num_leds = ARRAY_SIZE(dns323_leds), + .leds = dns323_leds, +}; + +static struct platform_device dns323_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { .platform_data = &dns323_led_data, }, +}; + +/**************************************************************************** + * GPIO Attached Keys + */ + +static struct gpio_keys_button dns323_buttons[] = { + { + .code = KEY_RESTART, + .gpio = DNS323_GPIO_KEY_RESET, + .desc = "Reset Button", + .active_low = 1, + }, + { + .code = KEY_POWER, + .gpio = DNS323_GPIO_KEY_POWER, + .desc = "Power Button", + .active_low = 1, + } +}; + +static struct gpio_keys_platform_data dns323_button_data = { + .buttons = dns323_buttons, + .nbuttons = ARRAY_SIZE(dns323_buttons), +}; + +static struct platform_device dns323_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { .platform_data = &dns323_button_data, }, +}; + +/**************************************************************************** + * General Setup + */ + +static struct platform_device *dns323_plat_devices[] __initdata = { + &dns323_nor_flash, + &dns323_gpio_leds, + &dns323_button_device, +}; + +/* + * On the DNS-323 the following devices are attached via I2C: + * + * i2c addr | chip | description + * 0x3e | GMT G760Af | fan speed PWM controller + * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) + * 0x68 | ST M41T80 | RTC w/ alarm + */ +static struct i2c_board_info __initdata dns323_i2c_devices[] = { + { + I2C_BOARD_INFO("g760a", 0x3e), + .type = "g760a", + }, +#if 0 + /* this entry requires the new-style driver model lm75 driver, + * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */ + { + I2C_BOARD_INFO("lm75", 0x48), + .type = "g751", + }, +#endif + { + I2C_BOARD_INFO("rtc-m41t80", 0x68), + .type = "m41t80", + } +}; + +/* DNS-323 specific power off method */ +static void dns323_power_off(void) +{ + pr_info("%s: triggering power-off...\n", __func__); + gpio_set_value(DNS323_GPIO_POWER_OFF, 1); +} + +static void __init dns323_init(void) +{ + /* Setup basic Orion functions. Need to be called early. */ + orion_init(); + + /* setup flash mapping + * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 + */ + orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, + DNS323_NOR_BOOT_SIZE, -1); + + /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE + * + * Open a special address decode windows for the PCIE WA. + */ + orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); + orion_write(ORION_REGS_BASE | 0x20070, + (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + + /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ + orion_write(MPP_0_7_CTRL, 0); + orion_write(MPP_8_15_CTRL, 0); + orion_write(MPP_16_19_CTRL, 0); + orion_write(MPP_DEV_CTRL, 0); + + /* Define used GPIO pins + + GPIO Map: + + | 0 | | PEX_RST_OUT (not controlled by GPIO) + | 1 | Out | right amber LED (= sata ch0 LED) (low-active) + | 2 | Out | left amber LED (= sata ch1 LED) (low-active) + | 3 | Out | //unknown// + | 4 | Out | power button LED (low-active, together with pin #5) + | 5 | Out | power button LED (low-active, together with pin #4) + | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active) + | 7 | In | M41T80 nIRQ/OUT/SQW signal + | 8 | Out | triggers power off (high-active) + | 9 | In | power button switch (low-active) + | 10 | In | reset button switch (low-active) + | 11 | Out | //unknown// + | 12 | Out | //unknown// + | 13 | Out | //unknown// + | 14 | Out | //unknown// + | 15 | Out | //unknown// + */ + orion_gpio_set_valid_pins(0x07f6); + + /* register dns323 specific power-off method */ + if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) + || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)) + pr_err("DNS323: failed to setup power-off GPIO\n"); + + pm_power_off = dns323_power_off; + + /* register flash and other platform devices */ + platform_add_devices(dns323_plat_devices, + ARRAY_SIZE(dns323_plat_devices)); + + i2c_register_board_info(0, dns323_i2c_devices, + ARRAY_SIZE(dns323_i2c_devices)); + + orion_eth_init(&dns323_eth_data); +} + +/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ +MACHINE_START(DNS323, "D-Link DNS-323") + /* Maintainer: Herbert Valerio Riedel */ + .phys_io = ORION_REGS_BASE, + .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = dns323_init, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, +MACHINE_END diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c new file mode 100644 index 0000000..d5f00c8 --- /dev/null +++ b/arch/arm/mach-orion/gpio.c @@ -0,0 +1,225 @@ +/* + * arch/arm/mach-orion/gpio.c + * + * GPIO functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +static DEFINE_SPINLOCK(gpio_lock); +static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; +static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ + +void __init orion_gpio_set_valid_pins(u32 pins) +{ + gpio_valid[0] = pins; +} + +/* + * GENERIC_GPIO primitives + */ +int gpio_direction_input(unsigned pin) +{ + unsigned long flags; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Some callers might have not used the gpio_request(), + * so flag this pin as requested now. + */ + if (!gpio_label[pin]) + gpio_label[pin] = "?"; + + orion_setbits(GPIO_IO_CONF, 1 << pin); + + spin_unlock_irqrestore(&gpio_lock, flags); + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned pin, int value) +{ + unsigned long flags; + int mask; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Some callers might have not used the gpio_request(), + * so flag this pin as requested now. + */ + if (!gpio_label[pin]) + gpio_label[pin] = "?"; + + mask = 1 << pin; + orion_clrbits(GPIO_BLINK_EN, mask); + if (value) + orion_setbits(GPIO_OUT, mask); + else + orion_clrbits(GPIO_OUT, mask); + orion_clrbits(GPIO_IO_CONF, mask); + + spin_unlock_irqrestore(&gpio_lock, flags); + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + +int gpio_get_value(unsigned pin) +{ + int val, mask = 1 << pin; + + if (orion_read(GPIO_IO_CONF) & mask) + val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); + else + val = orion_read(GPIO_OUT); + + return val & mask; +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned pin, int value) +{ + unsigned long flags; + int mask = 1 << pin; + + spin_lock_irqsave(&gpio_lock, flags); + + orion_clrbits(GPIO_BLINK_EN, mask); + if (value) + orion_setbits(GPIO_OUT, mask); + else + orion_clrbits(GPIO_OUT, mask); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(gpio_set_value); + +void orion_gpio_set_blink(unsigned pin, int blink) +{ + unsigned long flags; + int mask = 1 << pin; + + spin_lock_irqsave(&gpio_lock, flags); + + orion_clrbits(GPIO_OUT, mask); + if (blink) + orion_setbits(GPIO_BLINK_EN, mask); + else + orion_clrbits(GPIO_BLINK_EN, mask); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(orion_gpio_set_blink); + +int gpio_request(unsigned pin, const char *label) +{ + int ret = 0; + unsigned long flags; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + if (gpio_label[pin]) { + pr_debug("%s: GPIO %d already used as %s\n", + __FUNCTION__, pin, gpio_label[pin]); + ret = -EBUSY; + } else + gpio_label[pin] = label ? label : "?"; + + spin_unlock_irqrestore(&gpio_lock, flags); + return ret; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned pin) +{ + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin); + return; + } + + if (!gpio_label[pin]) + pr_warning("%s: GPIO %d already freed\n", __FUNCTION__, pin); + else + gpio_label[pin] = NULL; +} +EXPORT_SYMBOL(gpio_free); + +/* Debug helper */ +void gpio_display(void) +{ + int i; + + for (i = 0; i < GPIO_MAX; i++) { + printk(KERN_DEBUG "Pin-%d: ", i); + + if (!test_bit(i, gpio_valid)) { + printk("non-GPIO\n"); + } else if (!gpio_label[i]) { + printk("GPIO, free\n"); + } else { + printk("GPIO, used by %s, ", gpio_label[i]); + if (orion_read(GPIO_IO_CONF) & (1 << i)) { + printk("input, active %s, level %s, edge %s\n", + ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", + ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", + ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); + } else { + printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); + } + } + } + + printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", + MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); + printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", + MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); + printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", + MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); + printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", + MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); + printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", + GPIO_OUT, orion_read(GPIO_OUT)); + printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", + GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); + printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", + GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); + printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", + GPIO_IN_POL, orion_read(GPIO_IN_POL)); + printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", + GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); + printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", + GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); + printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", + GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); + printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", + GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); +} diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c new file mode 100644 index 0000000..df7e12a --- /dev/null +++ b/arch/arm/mach-orion/irq.c @@ -0,0 +1,241 @@ +/* + * arch/arm/mach-orion/irq.c + * + * Core IRQ functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * Orion GPIO IRQ + * + * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same + * value of the line or the opposite value. + * + * Level IRQ handlers: DATA_IN is used directly as cause register. + * Interrupt are masked by LEVEL_MASK registers. + * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. + * Interrupt are masked by EDGE_MASK registers. + * Both-edge handlers: Similar to regular Edge handlers, but also swaps + * the polarity to catch the next line transaction. + * This is a race condition that might not perfectly + * work on some use cases. + * + * Every eight GPIO lines are grouped (OR'ed) before going up to main + * cause register. + * + * EDGE cause mask + * data-in /--------| |-----| |----\ + * -----| |----- ---- to main cause reg + * X \----------------| |----/ + * polarity LEVEL mask + * + ****************************************************************************/ +static void orion_gpio_irq_ack(u32 irq) +{ + int pin = irq_to_gpio(irq); + if (irq_desc[irq].status & IRQ_LEVEL) + /* + * Mask bit for level interrupt + */ + orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); + else + /* + * Clear casue bit for egde interrupt + */ + orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); +} + +static void orion_gpio_irq_mask(u32 irq) +{ + int pin = irq_to_gpio(irq); + if (irq_desc[irq].status & IRQ_LEVEL) + orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); + else + orion_clrbits(GPIO_EDGE_MASK, 1 << pin); +} + +static void orion_gpio_irq_unmask(u32 irq) +{ + int pin = irq_to_gpio(irq); + if (irq_desc[irq].status & IRQ_LEVEL) + orion_setbits(GPIO_LEVEL_MASK, 1 << pin); + else + orion_setbits(GPIO_EDGE_MASK, 1 << pin); +} + +static int orion_gpio_set_irq_type(u32 irq, u32 type) +{ + int pin = irq_to_gpio(irq); + struct irq_desc *desc; + + if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { + printk(KERN_ERR "orion_gpio_set_irq_type failed " + "(irq %d, pin %d).\n", irq, pin); + return -EINVAL; + } + + desc = irq_desc + irq; + + switch (type) { + case IRQT_HIGH: + desc->handle_irq = handle_level_irq; + desc->status |= IRQ_LEVEL; + orion_clrbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_LOW: + desc->handle_irq = handle_level_irq; + desc->status |= IRQ_LEVEL; + orion_setbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_RISING: + desc->handle_irq = handle_edge_irq; + desc->status &= ~IRQ_LEVEL; + orion_clrbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_FALLING: + desc->handle_irq = handle_edge_irq; + desc->status &= ~IRQ_LEVEL; + orion_setbits(GPIO_IN_POL, (1 << pin)); + break; + case IRQT_BOTHEDGE: + desc->handle_irq = handle_edge_irq; + desc->status &= ~IRQ_LEVEL; + /* + * set initial polarity based on current input level + */ + if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) + & (1 << pin)) + orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ + else + orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ + + break; + default: + printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); + return -EINVAL; + } + + desc->status &= ~IRQ_TYPE_SENSE_MASK; + desc->status |= type & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static struct irq_chip orion_gpio_irq_chip = { + .name = "Orion-IRQ-GPIO", + .ack = orion_gpio_irq_ack, + .mask = orion_gpio_irq_mask, + .unmask = orion_gpio_irq_unmask, + .set_type = orion_gpio_set_irq_type, +}; + +static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 cause, offs, pin; + + BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); + offs = (irq - IRQ_ORION_GPIO_0_7) * 8; + cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | + (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); + + for (pin = offs; pin < offs + 8; pin++) { + if (cause & (1 << pin)) { + irq = gpio_to_irq(pin); + desc = irq_desc + irq; + if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { + /* Swap polarity (race with GPIO line) */ + u32 polarity = orion_read(GPIO_IN_POL); + polarity ^= 1 << pin; + orion_write(GPIO_IN_POL, polarity); + } + desc_handle_irq(irq, desc); + } + } +} + +static void __init orion_init_gpio_irq(void) +{ + int i; + struct irq_desc *desc; + + /* + * Mask and clear GPIO IRQ interrupts + */ + orion_write(GPIO_LEVEL_MASK, 0x0); + orion_write(GPIO_EDGE_MASK, 0x0); + orion_write(GPIO_EDGE_CAUSE, 0x0); + + /* + * Register chained level handlers for GPIO IRQs by default. + * User can use set_type() if he wants to use edge types handlers. + */ + for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion_gpio_irq_chip); + set_irq_handler(i, handle_level_irq); + desc = irq_desc + i; + desc->status |= IRQ_LEVEL; + set_irq_flags(i, IRQF_VALID); + } + set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); +} + +/***************************************************************************** + * Orion Main IRQ + ****************************************************************************/ +static void orion_main_irq_mask(u32 irq) +{ + orion_clrbits(MAIN_IRQ_MASK, 1 << irq); +} + +static void orion_main_irq_unmask(u32 irq) +{ + orion_setbits(MAIN_IRQ_MASK, 1 << irq); +} + +static struct irq_chip orion_main_irq_chip = { + .name = "Orion-IRQ-Main", + .ack = orion_main_irq_mask, + .mask = orion_main_irq_mask, + .unmask = orion_main_irq_unmask, +}; + +static void __init orion_init_main_irq(void) +{ + int i; + + /* + * Mask and clear Main IRQ interrupts + */ + orion_write(MAIN_IRQ_MASK, 0x0); + orion_write(MAIN_IRQ_CAUSE, 0x0); + + /* + * Register level handler for Main IRQs + */ + for (i = 0; i < IRQ_ORION_GPIO_START; i++) { + set_irq_chip(i, &orion_main_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } +} + +void __init orion_init_irq(void) +{ + orion_init_main_irq(); + orion_init_gpio_irq(); +} diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c new file mode 100644 index 0000000..2d812ed --- /dev/null +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -0,0 +1,234 @@ +/* + * arch/arm/mach-orion/kurobox_pro-setup.c + * + * Maintainer: Ronen Shitrit + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * KUROBOX-PRO Info + ****************************************************************************/ + +/* + * 256K NOR flash Device bus boot chip select + */ + +#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000 +#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K + +/* + * 256M NAND flash on Device bus chip select 1 + */ + +#define KUROBOX_PRO_NAND_BASE 0xfc000000 +#define KUROBOX_PRO_NAND_SIZE SZ_2M + +/***************************************************************************** + * 256MB NAND Flash on Device bus CS0 + ****************************************************************************/ + +static struct mtd_partition kurobox_pro_nand_parts[] = { + { + .name = "uImage", + .offset = 0, + .size = SZ_4M, + }, + { + .name = "rootfs", + .offset = SZ_4M, + .size = SZ_64M, + }, + { + .name = "extra", + .offset = SZ_4M + SZ_64M, + .size = SZ_256M - (SZ_4M + SZ_64M), + }, +}; + +static struct resource kurobox_pro_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KUROBOX_PRO_NAND_BASE, + .end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1, +}; + +static struct orion_nand_data kurobox_pro_nand_data = { + .parts = kurobox_pro_nand_parts, + .nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, +}; + +static struct platform_device kurobox_pro_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &kurobox_pro_nand_data, + }, + .resource = &kurobox_pro_nand_resource, + .num_resources = 1, +}; + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data kurobox_pro_nor_flash_data = { + .width = 1, +}; + +static struct resource kurobox_pro_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = KUROBOX_PRO_NOR_BOOT_BASE, + .end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device kurobox_pro_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &kurobox_pro_nor_flash_data, + }, + .num_resources = 1, + .resource = &kurobox_pro_nor_flash_resource, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ + +static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCI isn't used on the Kuro + */ + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; + else + printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); + + return -1; +} + +static struct hw_pci kurobox_pro_pci __initdata = { + .nr_controllers = 1, + .swizzle = pci_std_swizzle, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, + .map_irq = kurobox_pro_pci_map_irq, +}; + +static int __init kurobox_pro_pci_init(void) +{ + if (machine_is_kurobox_pro()) + pci_common_init(&kurobox_pro_pci); + + return 0; +} + +subsys_initcall(kurobox_pro_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data kurobox_pro_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = { + .driver_name = "rtc-rs5c372", + .type = "rs5c372a", + .addr = 0x32, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static struct platform_device *kurobox_pro_devices[] __initdata = { + &kurobox_pro_nor_flash, + &kurobox_pro_nand_flash, +}; + +static void __init kurobox_pro_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion_init(); + + /* + * Setup the CPU address decode windows for our devices + */ + orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE, -1); + orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE, + KUROBOX_PRO_NAND_SIZE, -1); + /* + * Open a special address decode windows for the PCIE WA. + */ + orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); + orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | + (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + + /* + * Setup Multiplexing Pins -- + * MPP[0-1] Not used + * MPP[2] GPIO Micon + * MPP[3] GPIO RTC + * MPP[4-5] Not used + * MPP[6] Nand Flash REn + * MPP[7] Nand Flash WEn + * MPP[8-11] Not used + * MPP[12] SATA 0 presence Indication + * MPP[13] SATA 1 presence Indication + * MPP[14] SATA 0 active Indication + * MPP[15] SATA 1 active indication + * MPP[16-19] Not used + */ + orion_write(MPP_0_7_CTRL, 0x44220003); + orion_write(MPP_8_15_CTRL, 0x55550000); + orion_write(MPP_16_19_CTRL, 0x0); + + orion_gpio_set_valid_pins(0x0000000c); + + platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); + i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); + orion_eth_init(&kurobox_pro_eth_data); +} + +MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") + /* Maintainer: Ronen Shitrit */ + .phys_io = ORION_REGS_BASE, + .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = kurobox_pro_init, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, +MACHINE_END diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c new file mode 100644 index 0000000..0498d7c --- /dev/null +++ b/arch/arm/mach-orion/pci.c @@ -0,0 +1,557 @@ +/* + * arch/arm/mach-orion/pci.c + * + * PCI and PCIE functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * Orion has one PCIE controller and one PCI controller. + * + * Note1: The local PCIE bus number is '0'. The local PCI bus number + * follows the scanned PCIE bridged busses, if any. + * + * Note2: It is possible for PCI/PCIE agents to access many subsystem's + * space, by configuring BARs and Address Decode Windows, e.g. flashes on + * device bus, Orion registers, etc. However this code only enable the + * access to DDR banks. + ****************************************************************************/ + + +/***************************************************************************** + * PCIE controller + ****************************************************************************/ +#define PCIE_CTRL ORION_PCIE_REG(0x1a00) +#define PCIE_STAT ORION_PCIE_REG(0x1a04) +#define PCIE_DEV_ID ORION_PCIE_REG(0x0000) +#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004) +#define PCIE_DEV_REV ORION_PCIE_REG(0x0008) +#define PCIE_MASK ORION_PCIE_REG(0x1910) +#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8) +#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc) + +/* + * PCIE_STAT bits + */ +#define PCIE_STAT_LINK_DOWN 1 +#define PCIE_STAT_BUS_OFFS 8 +#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS) +#define PCIE_STAT_DEV_OFFS 20 +#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS) + +/* + * PCIE_CONF_ADDR bits + */ +#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc)) +#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) +#define PCIE_CONF_ADDR_EN (1 << 31) + +/* + * PCIE config cycles are done by programming the PCIE_CONF_ADDR register + * and then reading the PCIE_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion_pcie_lock); + +void orion_pcie_id(u32 *dev, u32 *rev) +{ + *dev = orion_read(PCIE_DEV_ID) >> 16; + *rev = orion_read(PCIE_DEV_REV) & 0xff; +} + +u32 orion_pcie_local_bus_nr(void) +{ + u32 stat = orion_read(PCIE_STAT); + return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS); +} + +static u32 orion_pcie_local_dev_nr(void) +{ + u32 stat = orion_read(PCIE_STAT); + return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS); +} + +static u32 orion_pcie_no_link(void) +{ + u32 stat = orion_read(PCIE_STAT); + return(stat & PCIE_STAT_LINK_DOWN); +} + +static void orion_pcie_set_bus_nr(int nr) +{ + orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK); + orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); +} + +static void orion_pcie_master_slave_enable(void) +{ + orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY); +} + +static void orion_pcie_enable_interrupts(void) +{ + /* + * Enable interrupts lines + * INTA[24] INTB[25] INTC[26] INTD[27] + */ + orion_setbits(PCIE_MASK, 0xf<<24); +} + +static int orion_pcie_valid_config(u32 bus, u32 dev) +{ + /* + * Don't go out when trying to access -- + * 1. our own device + * 2. where there's no device connected (no link) + * 3. nonexisting devices on local bus + */ + + if ((orion_pcie_local_bus_nr() == bus) && + (orion_pcie_local_dev_nr() == dev)) + return 0; + + if (orion_pcie_no_link()) + return 0; + + if (bus == orion_pcie_local_bus_nr()) + if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) || + ((orion_pcie_local_dev_nr() != 0) && (dev != 0))) + return 0; + + return 1; +} + +static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + unsigned long flags; + unsigned int dev, rev, pcie_addr; + + if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&orion_pcie_lock, flags); + + orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); + + orion_pcie_id(&dev, &rev); + if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { + /* extended register space */ + pcie_addr = ORION_PCIE_WA_BASE; + pcie_addr |= PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where); + *val = orion_read(pcie_addr); + } else + *val = orion_read(PCIE_CONF_DATA); + + if (size == 1) + *val = (*val >> (8*(where & 0x3))) & 0xff; + else if (size == 2) + *val = (*val >> (8*(where & 0x3))) & 0xffff; + + spin_unlock_irqrestore(&orion_pcie_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + + +static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) +{ + unsigned long flags; + int ret; + + if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&orion_pcie_lock, flags); + + ret = PCIBIOS_SUCCESSFUL; + + orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); + + if (size == 4) { + __raw_writel(val, PCIE_CONF_DATA); + } else if (size == 2) { + __raw_writew(val, PCIE_CONF_DATA + (where & 0x3)); + } else if (size == 1) { + __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3)); + } else { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&orion_pcie_lock, flags); + + return ret; +} + +struct pci_ops orion_pcie_ops = { + .read = orion_pcie_rd_conf, + .write = orion_pcie_wr_conf, +}; + + +static int orion_pcie_setup(struct pci_sys_data *sys) +{ + struct resource *res; + + /* + * Master + Slave enable + */ + orion_pcie_master_slave_enable(); + + /* + * Enable interrupts lines A-D + */ + orion_pcie_enable_interrupts(); + + /* + * Request resource + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("orion_pci_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCI-EX I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION_PCIE_IO_REMAP; + res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIE IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCI-EX Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION_PCIE_MEM_BASE; + res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCIE Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + +/***************************************************************************** + * PCI controller + ****************************************************************************/ +#define PCI_MODE ORION_PCI_REG(0xd00) +#define PCI_CMD ORION_PCI_REG(0xc00) +#define PCI_P2P_CONF ORION_PCI_REG(0x1d14) +#define PCI_CONF_ADDR ORION_PCI_REG(0xc78) +#define PCI_CONF_DATA ORION_PCI_REG(0xc7c) + +/* + * PCI_MODE bits + */ +#define PCI_MODE_64BIT (1 << 2) +#define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) + +/* + * PCI_CMD bits + */ +#define PCI_CMD_HOST_REORDER (1 << 29) + +/* + * PCI_P2P_CONF bits + */ +#define PCI_P2P_BUS_OFFS 16 +#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) +#define PCI_P2P_DEV_OFFS 24 +#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) + +/* + * PCI_CONF_ADDR bits + */ +#define PCI_CONF_REG(reg) ((reg) & 0xfc) +#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) +#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) +#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) +#define PCI_CONF_ADDR_EN (1 << 31) + +/* + * Internal configuration space + */ +#define PCI_CONF_FUNC_STAT_CMD 0 +#define PCI_CONF_REG_STAT_CMD 4 +#define PCIX_STAT 0x64 +#define PCIX_STAT_BUS_OFFS 8 +#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) + +/* + * PCI config cycles are done by programming the PCI_CONF_ADDR register + * and then reading the PCI_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion_pci_lock); + +u32 orion_pci_local_bus_nr(void) +{ + u32 conf = orion_read(PCI_P2P_CONF); + return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); +} + +u32 orion_pci_local_dev_nr(void) +{ + u32 conf = orion_read(PCI_P2P_CONF); + return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); +} + +int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, + u32 where, u32 size, u32 *val) +{ + unsigned long flags; + spin_lock_irqsave(&orion_pci_lock, flags); + + orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + + *val = orion_read(PCI_CONF_DATA); + + if (size == 1) + *val = (*val >> (8*(where & 0x3))) & 0xff; + else if (size == 2) + *val = (*val >> (8*(where & 0x3))) & 0xffff; + + spin_unlock_irqrestore(&orion_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, + u32 where, u32 size, u32 val) +{ + unsigned long flags; + int ret = PCIBIOS_SUCCESSFUL; + + spin_lock_irqsave(&orion_pci_lock, flags); + + orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + + if (size == 4) { + __raw_writel(val, PCI_CONF_DATA); + } else if (size == 2) { + __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); + } else if (size == 1) { + __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); + } else { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&orion_pci_lock, flags); + + return ret; +} + +static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 *val) +{ + /* + * Don't go out for local device + */ + if ((orion_pci_local_bus_nr() == bus->number) && + (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where, size, val); +} + +static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + /* + * Don't go out for local device + */ + if ((orion_pci_local_bus_nr() == bus->number) && + (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) + return PCIBIOS_DEVICE_NOT_FOUND; + + return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where, size, val); +} + +struct pci_ops orion_pci_ops = { + .read = orion_pci_rd_conf, + .write = orion_pci_wr_conf, +}; + +static void orion_pci_set_bus_nr(int nr) +{ + u32 p2p = orion_read(PCI_P2P_CONF); + + if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { + /* + * PCI-X mode + */ + u32 pcix_status, bus, dev; + bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; + dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; + orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); + pcix_status &= ~PCIX_STAT_BUS_MASK; + pcix_status |= (nr << PCIX_STAT_BUS_OFFS); + orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); + } else { + /* + * PCI Conventional mode + */ + p2p &= ~PCI_P2P_BUS_MASK; + p2p |= (nr << PCI_P2P_BUS_OFFS); + orion_write(PCI_P2P_CONF, p2p); + } +} + +static void orion_pci_master_slave_enable(void) +{ + u32 bus_nr, dev_nr, func, reg, val; + + bus_nr = orion_pci_local_bus_nr(); + dev_nr = orion_pci_local_dev_nr(); + func = PCI_CONF_FUNC_STAT_CMD; + reg = PCI_CONF_REG_STAT_CMD; + orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val); + val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); +} + +static int orion_pci_setup(struct pci_sys_data *sys) +{ + struct resource *res; + + /* + * Master + Slave enable + */ + orion_pci_master_slave_enable(); + + /* + * Force ordering + */ + orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + + /* + * Request resources + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("orion_pci_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION_PCI_IO_REMAP; + res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCI IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION_PCI_MEM_BASE; + res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCI Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + + +/***************************************************************************** + * General PCIE + PCI + ****************************************************************************/ +int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) +{ + int ret = 0; + + if (nr == 0) { + /* + * PCIE setup + */ + orion_pcie_set_bus_nr(0); + ret = orion_pcie_setup(sys); + } else if (nr == 1) { + /* + * PCI setup + */ + ret = orion_pci_setup(sys); + } + + return ret; +} + +struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_ops *ops; + struct pci_bus *bus; + + + if (nr == 0) { + u32 pci_bus; + /* + * PCIE scan + */ + ops = &orion_pcie_ops; + bus = pci_scan_bus(sys->busnr, ops, sys); + /* + * Set local PCI bus number to follow PCIE bridges (if any) + */ + pci_bus = bus->number + bus->subordinate - bus->secondary + 1; + orion_pci_set_bus_nr(pci_bus); + } else if (nr == 1) { + /* + * PCI scan + */ + ops = &orion_pci_ops; + bus = pci_scan_bus(sys->busnr, ops, sys); + } else { + BUG(); + bus = NULL; + } + + return bus; +} diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c new file mode 100644 index 0000000..026d743 --- /dev/null +++ b/arch/arm/mach-orion/rd88f5182-setup.c @@ -0,0 +1,306 @@ +/* + * arch/arm/mach-orion/rd88f5182-setup.c + * + * Marvell Orion-NAS Reference Design Setup + * + * Maintainer: Ronen Shitrit + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * RD-88F5182 Info + ****************************************************************************/ + +/* + * 512K NOR flash Device bus boot chip select + */ + +#define RD88F5182_NOR_BOOT_BASE 0xf4000000 +#define RD88F5182_NOR_BOOT_SIZE SZ_512K + +/* + * 16M NOR flash on Device bus chip select 1 + */ + +#define RD88F5182_NOR_BASE 0xfc000000 +#define RD88F5182_NOR_SIZE SZ_16M + +/* + * PCI + */ + +#define RD88F5182_PCI_SLOT0_OFFS 7 +#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 +#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 + +/* + * GPIO Debug LED + */ + +#define RD88F5182_GPIO_DBG_LED 0 + +/***************************************************************************** + * 16M NOR Flash on Device bus CS1 + ****************************************************************************/ + +static struct physmap_flash_data rd88f5182_nor_flash_data = { + .width = 1, +}; + +static struct resource rd88f5182_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = RD88F5182_NOR_BASE, + .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1, +}; + +static struct platform_device rd88f5182_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &rd88f5182_nor_flash_data, + }, + .num_resources = 1, + .resource = &rd88f5182_nor_flash_resource, +}; + +#ifdef CONFIG_LEDS + +/***************************************************************************** + * Use GPIO debug led as CPU active indication + ****************************************************************************/ + +static void rd88f5182_dbgled_event(led_event_t evt) +{ + int val; + + if (evt == led_idle_end) + val = 1; + else if (evt == led_idle_start) + val = 0; + else + return; + + gpio_set_value(RD88F5182_GPIO_DBG_LED, val); +} + +static int __init rd88f5182_dbgled_init(void) +{ + int pin; + + if (machine_is_rd88f5182()) { + pin = RD88F5182_GPIO_DBG_LED; + + if (gpio_request(pin, "DBGLED") == 0) { + if (gpio_direction_output(pin, 0) != 0) { + printk(KERN_ERR "rd88f5182_dbgled_init failed " + "to set output pin %d\n", pin); + gpio_free(pin); + return 0; + } + } else { + printk(KERN_ERR "rd88f5182_dbgled_init failed " + "to request gpio %d\n", pin); + return 0; + } + + leds_event = rd88f5182_dbgled_event; + } + return 0; +} + +__initcall(rd88f5182_dbgled_init); + +#endif + +/***************************************************************************** + * PCI + ****************************************************************************/ + +void __init rd88f5182_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; + if (gpio_request(pin, "PCI IntA") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit faield to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); + } + + pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; + if (gpio_request(pin, "PCI IntB") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit faield to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); + } +} + +static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCI-E isn't used on the RD2 + */ + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - RD88F5182_PCI_SLOT0_OFFS) { + case 0: + if (pin == 1) + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN); + else + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN); + default: + return -1; + } +} + +static struct hw_pci rd88f5182_pci __initdata = { + .nr_controllers = 2, + .preinit = rd88f5182_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, + .map_irq = rd88f5182_pci_map_irq, +}; + +static int __init rd88f5182_pci_init(void) +{ + if (machine_is_rd88f5182()) + pci_common_init(&rd88f5182_pci); + + return 0; +} + +subsys_initcall(rd88f5182_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data rd88f5182_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC DS1338 on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata rd88f5182_i2c_rtc = { + .driver_name = "rtc-ds1307", + .type = "ds1338", + .addr = 0x68, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static struct platform_device *rd88f5182_devices[] __initdata = { + &rd88f5182_nor_flash, +}; + +static void __init rd88f5182_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion_init(); + + /* + * Setup the CPU address decode windows for our devices + */ + orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE, -1); + orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE, + RD88F5182_NOR_SIZE, -1); + + /* + * Open a special address decode windows for the PCIE WA. + */ + orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); + orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | + (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + + /* + * Setup Multiplexing Pins -- + * MPP[0] Debug Led (GPIO - Out) + * MPP[1] Debug Led (GPIO - Out) + * MPP[2] N/A + * MPP[3] RTC_Int (GPIO - In) + * MPP[4] GPIO + * MPP[5] GPIO + * MPP[6] PCI_intA (GPIO - In) + * MPP[7] PCI_intB (GPIO - In) + * MPP[8-11] N/A + * MPP[12] SATA 0 presence Indication + * MPP[13] SATA 1 presence Indication + * MPP[14] SATA 0 active Indication + * MPP[15] SATA 1 active indication + * MPP[16-19] Not used + * MPP[20] PCI Clock to MV88F5182 + * MPP[21] PCI Clock to mini PCI CON11 + * MPP[22] USB 0 over current indication + * MPP[23] USB 1 over current indication + * MPP[24] USB 1 over current enable + * MPP[25] USB 0 over current enable + */ + + orion_write(MPP_0_7_CTRL, 0x00000003); + orion_write(MPP_8_15_CTRL, 0x55550000); + orion_write(MPP_16_19_CTRL, 0x5555); + + orion_gpio_set_valid_pins(0x000000fb); + + platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); + i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); + orion_eth_init(&rd88f5182_eth_data); +} + +MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") + /* Maintainer: Ronen Shitrit */ + .phys_io = ORION_REGS_BASE, + .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = rd88f5182_init, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, +MACHINE_END diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c new file mode 100644 index 0000000..bd4262d --- /dev/null +++ b/arch/arm/mach-orion/time.c @@ -0,0 +1,181 @@ +/* + * arch/arm/mach-orion/time.c + * + * Core time functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Timer0: clock_event_device, Tick. + * Timer1: clocksource, Free running. + * WatchDog: Not used. + * + * Timers are counting down. + */ +#define CLOCKEVENT 0 +#define CLOCKSOURCE 1 + +/* + * Timers bits + */ +#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1)) +#define TIMER_EN(x) (1 << ((x) * 2)) +#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1)) +#define BRIDGE_INT_TIMER_WD (1 << 3) +#define TIMER_WD_EN (1 << 4) +#define TIMER_WD_RELOAD_EN (1 << 5) + +static cycle_t orion_clksrc_read(void) +{ + return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE))); +} + +static struct clocksource orion_clksrc = { + .name = "orion_clocksource", + .shift = 20, + .rating = 300, + .read = orion_clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int +orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) +{ + unsigned long flags; + + if (delta == 0) + return -ETIME; + + local_irq_save(flags); + + /* + * Clear and enable timer interrupt bit + */ + orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); + + /* + * Setup new timer value + */ + orion_write(TIMER_VAL(CLOCKEVENT), delta); + + /* + * Disable auto reload and kickoff the timer + */ + orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT)); + orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT)); + + local_irq_restore(flags); + + return 0; +} + +static void +orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) +{ + unsigned long flags; + + local_irq_save(flags); + + if (mode == CLOCK_EVT_MODE_PERIODIC) { + /* + * Setup latch cycles in timer and enable reload interrupt. + */ + orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH); + orion_write(TIMER_VAL(CLOCKEVENT), LATCH); + orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | + TIMER_EN(CLOCKEVENT)); + } else { + /* + * Disable timer and interrupt + */ + orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | + TIMER_EN(CLOCKEVENT)); + } + + local_irq_restore(flags); +} + +static struct clock_event_device orion_clkevt = { + .name = "orion_tick", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 300, + .cpumask = CPU_MASK_CPU0, + .set_next_event = orion_clkevt_next_event, + .set_mode = orion_clkevt_mode, +}; + +static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) +{ + /* + * Clear cause bit and do event + */ + orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_clkevt.event_handler(&orion_clkevt); + return IRQ_HANDLED; +} + +static struct irqaction orion_timer_irq = { + .name = "orion_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = orion_timer_interrupt +}; + +static void orion_timer_init(void) +{ + /* + * Setup clocksource free running timer (no interrupt on reload) + */ + orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff); + orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff); + orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE)); + orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) | + TIMER_EN(CLOCKSOURCE)); + + /* + * Register clocksource + */ + orion_clksrc.mult = + clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift); + + clocksource_register(&orion_clksrc); + + /* + * Connect and enable tick handler + */ + setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq); + + /* + * Register clockevent + */ + orion_clkevt.mult = + div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift); + orion_clkevt.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &orion_clkevt); + orion_clkevt.min_delta_ns = + clockevent_delta2ns(1, &orion_clkevt); + + clockevents_register_device(&orion_clkevt); +} + +struct sys_timer orion_timer = { + .init = orion_timer_init, +}; diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c new file mode 100644 index 0000000..e3e930e --- /dev/null +++ b/arch/arm/mach-orion/ts209-setup.c @@ -0,0 +1,335 @@ +/* + * QNAP TS-109/TS-209 Board Setup + * + * Maintainer: Byron Bradley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 +#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M + +/**************************************************************************** + * 8MiB NOR flash. The struct mtd_partition is not in the same order as the + * partitions on the device because we want to keep compatability with + * existing QNAP firmware. + * + * Layout as used by QNAP: + * [2] 0x00000000-0x00200000 : "Kernel" + * [3] 0x00200000-0x00600000 : "RootFS1" + * [4] 0x00600000-0x00700000 : "RootFS2" + * [6] 0x00700000-0x00760000 : "NAS Config" (read-only) + * [5] 0x00760000-0x00780000 : "U-Boot Config" + * [1] 0x00780000-0x00800000 : "U-Boot" (read-only) + ***************************************************************************/ +static struct mtd_partition qnap_ts209_partitions[] = { + { + .name = "U-Boot", + .size = 0x00080000, + .offset = 0x00780000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .size = 0x00200000, + .offset = 0, + }, { + .name = "RootFS1", + .size = 0x00400000, + .offset = 0x00200000, + }, { + .name = "RootFS2", + .size = 0x00100000, + .offset = 0x00600000, + }, { + .name = "U-Boot Config", + .size = 0x00020000, + .offset = 0x00760000, + }, { + .name = "NAS Config", + .size = 0x00060000, + .offset = 0x00700000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct physmap_flash_data qnap_ts209_nor_flash_data = { + .width = 1, + .parts = qnap_ts209_partitions, + .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) +}; + +static struct resource qnap_ts209_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = QNAP_TS209_NOR_BOOT_BASE, + .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device qnap_ts209_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { .platform_data = &qnap_ts209_nor_flash_data, }, + .resource = &qnap_ts209_nor_flash_resource, + .num_resources = 1, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ + +#define QNAP_TS209_PCI_SLOT0_OFFS 7 +#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6 +#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 + +void __init qnap_ts209_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; + if (gpio_request(pin, "PCI Int1") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " + "%d\n", pin); + } + + pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; + if (gpio_request(pin, "PCI Int2") == 0) { + if (gpio_direction_input(pin) == 0) { + set_irq_type(gpio_to_irq(pin), IRQT_LOW); + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed " + "to set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " + "%d\n", pin); + } +} + +static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + /* + * PCIE IRQ is connected internally (not GPIO) + */ + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) { + case 0: + return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN); + case 1: + return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN); + default: + return -1; + } +} + +static struct hw_pci qnap_ts209_pci __initdata = { + .nr_controllers = 2, + .preinit = qnap_ts209_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, + .map_irq = qnap_ts209_pci_map_irq, +}; + +static int __init qnap_ts209_pci_init(void) +{ + if (machine_is_ts_x09()) + pci_common_init(&qnap_ts209_pci); + + return 0; +} + +subsys_initcall(qnap_ts209_pci_init); + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { + .phy_addr = 8, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC S35390A on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { + .driver_name = "rtc-s35390a", + .addr = 0x30, +}; + +/**************************************************************************** + * GPIO Attached Keys + * Power button is attached to the PIC microcontroller + ****************************************************************************/ + +#define QNAP_TS209_GPIO_KEY_MEDIA 1 +#define QNAP_TS209_GPIO_KEY_RESET 2 + +static struct gpio_keys_button qnap_ts209_buttons[] = { + { + .code = KEY_RESTART, + .gpio = QNAP_TS209_GPIO_KEY_MEDIA, + .desc = "USB Copy Button", + .active_low = 1, + }, + { + .code = KEY_POWER, + .gpio = QNAP_TS209_GPIO_KEY_RESET, + .desc = "Reset Button", + .active_low = 1, + } +}; + +static struct gpio_keys_platform_data qnap_ts209_button_data = { + .buttons = qnap_ts209_buttons, + .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), +}; + +static struct platform_device qnap_ts209_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { .platform_data = &qnap_ts209_button_data, }, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static struct platform_device *qnap_ts209_devices[] __initdata = { + &qnap_ts209_nor_flash, + &qnap_ts209_button_device, +}; + +/* + * QNAP TS-[12]09 specific power off method via UART1-attached PIC + */ + +#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2)) + +static void qnap_ts209_power_off(void) +{ + /* 19200 baud divisor */ + const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); + + pr_info("%s: triggering power-off...\n", __func__); + + /* hijack uart1 and reset into sane state (19200,8n1) */ + orion_write(UART1_REG(LCR), 0x83); + orion_write(UART1_REG(DLL), divisor & 0xff); + orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); + orion_write(UART1_REG(LCR), 0x03); + orion_write(UART1_REG(IER), 0x00); + orion_write(UART1_REG(FCR), 0x00); + orion_write(UART1_REG(MCR), 0x00); + + /* send the power-off command 'A' to PIC */ + orion_write(UART1_REG(TX), 'A'); +} + +static void __init qnap_ts209_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion_init(); + + /* + * Setup flash mapping + */ + orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE, -1); + + /* + * Open a special address decode windows for the PCIE WA. + */ + orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); + orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | + (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + + /* + * Setup Multiplexing Pins -- + * MPP[0] Reserved + * MPP[1] USB copy button (0 active) + * MPP[2] Load defaults button (0 active) + * MPP[3] GPIO RTC + * MPP[4-5] Reserved + * MPP[6] PCI Int A + * MPP[7] PCI Int B + * MPP[8-11] Reserved + * MPP[12] SATA 0 presence + * MPP[13] SATA 1 presence + * MPP[14] SATA 0 active + * MPP[15] SATA 1 active + * MPP[16] UART1 RXD + * MPP[17] UART1 TXD + * MPP[18] SW_RST (0 active) + * MPP[19] Reserved + * MPP[20] PCI clock 0 + * MPP[21] PCI clock 1 + * MPP[22] USB 0 over current + * MPP[23-25] Reserved + */ + orion_write(MPP_0_7_CTRL, 0x3); + orion_write(MPP_8_15_CTRL, 0x55550000); + orion_write(MPP_16_19_CTRL, 0x5500); + orion_gpio_set_valid_pins(0x3cc0fff); + + /* register ts209 specific power-off method */ + pm_power_off = qnap_ts209_power_off; + + platform_add_devices(qnap_ts209_devices, + ARRAY_SIZE(qnap_ts209_devices)); + i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); + orion_eth_init(&qnap_ts209_eth_data); +} + +MACHINE_START(TS209, "QNAP TS-109/TS-209") + /* Maintainer: Byron Bradley */ + .phys_io = ORION_REGS_BASE, + .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = qnap_ts209_init, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, +MACHINE_END diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 656d496..c73da5e 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -51,6 +51,50 @@ config PXA_SHARPSL SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) handheld computer. +config ARCH_PXA_ESERIES + bool "PXA based Toshiba e-series PDAs" + select PXA25x + +config MACH_E330 + bool "Toshiba e330" + default y + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e330 family PDA. + +config MACH_E740 + bool "Toshiba e740" + default y + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e740 family PDA. + +config MACH_E750 + bool "Toshiba e750" + default y + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e750 family PDA. + +config MACH_E400 + bool "Toshiba e400" + default y + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e400 family PDA. + +config MACH_E800 + bool "Toshiba e800" + default y + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e800 family PDA. + config MACH_TRIZEPS4 bool "Keith und Koep Trizeps4 DIMM-Module" select PXA27x @@ -63,11 +107,22 @@ config MACH_ZYLONITE bool "PXA3xx Development Platform" select PXA3xx +config MACH_LITTLETON + bool "PXA3xx Form Factor Platform (aka Littleton)" + select PXA3xx + select PXA_SSP + config MACH_ARMCORE bool "CompuLab CM-X270 modules" select PXA27x select IWMMXT +config MACH_MAGICIAN + bool "Enable HTC Magician Support" + depends on ARCH_PXA + select PXA27x + select IWMMXT + endchoice if PXA_SHARPSL diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 4263527..5e9aec5 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -3,7 +3,7 @@ # # Common support (must be linked before board specific support) -obj-y += clock.o generic.o irq.o dma.o time.o +obj-y += clock.o devices.o generic.o irq.o dma.o time.o obj-$(CONFIG_PXA25x) += pxa25x.o obj-$(CONFIG_PXA27x) += pxa27x.o obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o @@ -22,12 +22,15 @@ obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o obj-$(CONFIG_MACH_TOSA) += tosa.o obj-$(CONFIG_MACH_EM_X270) += em-x270.o +obj-$(CONFIG_MACH_MAGICIAN) += magician.o +obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o ifeq ($(CONFIG_MACH_ZYLONITE),y) obj-y += zylonite.o obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o endif +obj-$(CONFIG_MACH_LITTLETON) += littleton.o obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o @@ -41,13 +44,10 @@ led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o obj-$(CONFIG_LEDS) += $(led-y) # Misc features -obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PM) += pm.o sleep.o standby.o +obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o obj-$(CONFIG_PXA_SSP) += ssp.o -ifeq ($(CONFIG_PXA27x),y) -obj-$(CONFIG_PM) += standby.o -endif - ifeq ($(CONFIG_PCI),y) obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o endif diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index 40dea3d..efba65e 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c @@ -21,6 +21,7 @@ #include #include +#include #include "sharpsl.h" static DEFINE_SPINLOCK(corgi_ssp_lock); diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c new file mode 100644 index 0000000..cbc583b --- /dev/null +++ b/arch/arm/mach-pxa/cpu-pxa.c @@ -0,0 +1,294 @@ +/* + * linux/arch/arm/mach-pxa/cpu-pxa.c + * + * Copyright (C) 2002,2003 Intrinsyc Software + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * History: + * 31-Jul-2002 : Initial version [FB] + * 29-Jan-2003 : added PXA255 support [FB] + * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) + * + * Note: + * This driver may change the memory bus clock rate, but will not do any + * platform specific access timing changes... for example if you have flash + * memory connected to CS0, you will need to register a platform specific + * notifier which will adjust the memory access strobes to maintain a + * minimum strobe width. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef DEBUG +static unsigned int freq_debug; +MODULE_PARM(freq_debug, "i"); +MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); +#else +#define freq_debug 0 +#endif + +typedef struct { + unsigned int khz; + unsigned int membus; + unsigned int cccr; + unsigned int div2; +} pxa_freqs_t; + +/* Define the refresh period in mSec for the SDRAM and the number of rows */ +#define SDRAM_TREF 64 /* standard 64ms SDRAM */ +#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ +#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32)) + +#define CCLKCFG_TURBO 0x1 +#define CCLKCFG_FCS 0x2 +#define PXA25x_MIN_FREQ 99500 +#define PXA25x_MAX_FREQ 398100 +#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) +#define MDREFR_DRI_MASK 0xFFF + + +/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ +static pxa_freqs_t pxa255_run_freqs[] = +{ + /* CPU MEMBUS CCCR DIV2*/ + { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ + {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ + {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ + {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */ + {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ + {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */ + {0,} +}; +#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs) + +static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1]; + +/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ +static pxa_freqs_t pxa255_turbo_freqs[] = +{ + /* CPU MEMBUS CCCR DIV2*/ + { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */ + {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */ + {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */ + {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */ + {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */ + {0,} +}; +#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs) + +static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1]; + +extern unsigned get_clk_frequency_khz(int info); + +/* find a valid frequency point */ +static int pxa_verify_policy(struct cpufreq_policy *policy) +{ + struct cpufreq_frequency_table *pxa_freqs_table; + int ret; + + if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { + pxa_freqs_table = pxa255_run_freq_table; + } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { + pxa_freqs_table = pxa255_turbo_freq_table; + } else { + printk("CPU PXA: Unknown policy found. " + "Using CPUFREQ_POLICY_PERFORMANCE\n"); + pxa_freqs_table = pxa255_run_freq_table; + } + + ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); + + if (freq_debug) + pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n", + policy->min, policy->max); + + return ret; +} + +static int pxa_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_frequency_table *pxa_freqs_table; + pxa_freqs_t *pxa_freq_settings; + struct cpufreq_freqs freqs; + int idx; + unsigned long flags; + unsigned int unused, preset_mdrefr, postset_mdrefr; + void *ramstart = phys_to_virt(0xa0000000); + + /* Get the current policy */ + if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { + pxa_freq_settings = pxa255_run_freqs; + pxa_freqs_table = pxa255_run_freq_table; + } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { + pxa_freq_settings = pxa255_turbo_freqs; + pxa_freqs_table = pxa255_turbo_freq_table; + } else { + printk("CPU PXA: Unknown policy found. " + "Using CPUFREQ_POLICY_PERFORMANCE\n"); + pxa_freq_settings = pxa255_run_freqs; + pxa_freqs_table = pxa255_run_freq_table; + } + + /* Lookup the next frequency */ + if (cpufreq_frequency_table_target(policy, pxa_freqs_table, + target_freq, relation, &idx)) { + return -EINVAL; + } + + freqs.old = policy->cur; + freqs.new = pxa_freq_settings[idx].khz; + freqs.cpu = policy->cpu; + + if (freq_debug) + pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", + freqs.new / 1000, (pxa_freq_settings[idx].div2) ? + (pxa_freq_settings[idx].membus / 2000) : + (pxa_freq_settings[idx].membus / 1000)); + + /* + * Tell everyone what we're about to do... + * you should add a notify client with any platform specific + * Vcc changing capability + */ + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + /* Calculate the next MDREFR. If we're slowing down the SDRAM clock + * we need to preset the smaller DRI before the change. If we're speeding + * up we need to set the larger DRI value after the change. + */ + preset_mdrefr = postset_mdrefr = MDREFR; + if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) { + preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | + MDREFR_DRI(pxa_freq_settings[idx].membus); + } + postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | + MDREFR_DRI(pxa_freq_settings[idx].membus); + + /* If we're dividing the memory clock by two for the SDRAM clock, this + * must be set prior to the change. Clearing the divide must be done + * after the change. + */ + if (pxa_freq_settings[idx].div2) { + preset_mdrefr |= MDREFR_DB2_MASK; + postset_mdrefr |= MDREFR_DB2_MASK; + } else { + postset_mdrefr &= ~MDREFR_DB2_MASK; + } + + local_irq_save(flags); + + /* Set new the CCCR */ + CCCR = pxa_freq_settings[idx].cccr; + + asm volatile(" \n\ + ldr r4, [%1] /* load MDREFR */ \n\ + b 2f \n\ + .align 5 \n\ +1: \n\ + str %4, [%1] /* preset the MDREFR */ \n\ + mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ + str %5, [%1] /* postset the MDREFR */ \n\ + \n\ + b 3f \n\ +2: b 1b \n\ +3: nop \n\ + " + : "=&r" (unused) + : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), + "r" (preset_mdrefr), "r" (postset_mdrefr) + : "r4", "r5"); + local_irq_restore(flags); + + /* + * Tell everyone what we've just done... + * you should add a notify client with any platform specific + * SDRAM refresh timer adjustments + */ + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +static int pxa_cpufreq_init(struct cpufreq_policy *policy) +{ + int i; + + /* set default policy and cpuinfo */ + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->policy = CPUFREQ_POLICY_PERFORMANCE; + policy->cpuinfo.max_freq = PXA25x_MAX_FREQ; + policy->cpuinfo.min_freq = PXA25x_MIN_FREQ; + policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ + policy->cur = get_clk_frequency_khz(0); /* current freq */ + policy->min = policy->max = policy->cur; + + /* Generate the run cpufreq_frequency_table struct */ + for (i = 0; i < NUM_RUN_FREQS; i++) { + pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; + pxa255_run_freq_table[i].index = i; + } + + pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; + /* Generate the turbo cpufreq_frequency_table struct */ + for (i = 0; i < NUM_TURBO_FREQS; i++) { + pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz; + pxa255_turbo_freq_table[i].index = i; + } + pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; + + printk(KERN_INFO "PXA CPU frequency change support initialized\n"); + + return 0; +} + +static struct cpufreq_driver pxa_cpufreq_driver = { + .verify = pxa_verify_policy, + .target = pxa_set_target, + .init = pxa_cpufreq_init, + .name = "PXA25x", +}; + +static int __init pxa_cpu_init(void) +{ + int ret = -ENODEV; + if (cpu_is_pxa25x()) + ret = cpufreq_register_driver(&pxa_cpufreq_driver); + return ret; +} + +static void __exit pxa_cpu_exit(void) +{ + if (cpu_is_pxa25x()) + cpufreq_unregister_driver(&pxa_cpufreq_driver); +} + + +MODULE_AUTHOR ("Intrinsyc Software Inc."); +MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture"); +MODULE_LICENSE("GPL"); +module_init(pxa_cpu_init); +module_exit(pxa_cpu_exit); diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c new file mode 100644 index 0000000..50ff453 --- /dev/null +++ b/arch/arm/mach-pxa/devices.c @@ -0,0 +1,662 @@ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +void __init pxa_register_device(struct platform_device *dev, void *data) +{ + int ret; + + dev->dev.platform_data = data; + + ret = platform_device_register(dev); + if (ret) + dev_err(&dev->dev, "unable to register device: %d\n", ret); +} + +static struct resource pxamci_resources[] = { + [0] = { + .start = 0x41100000, + .end = 0x41100fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MMC, + .end = IRQ_MMC, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 21, + .end = 21, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = 22, + .end = 22, + .flags = IORESOURCE_DMA, + }, +}; + +static u64 pxamci_dmamask = 0xffffffffUL; + +struct platform_device pxa_device_mci = { + .name = "pxa2xx-mci", + .id = 0, + .dev = { + .dma_mask = &pxamci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pxamci_resources), + .resource = pxamci_resources, +}; + +void __init pxa_set_mci_info(struct pxamci_platform_data *info) +{ + pxa_register_device(&pxa_device_mci, info); +} + + +static struct pxa2xx_udc_mach_info pxa_udc_info; + +void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) +{ + memcpy(&pxa_udc_info, info, sizeof *info); +} + +static struct resource pxa2xx_udc_resources[] = { + [0] = { + .start = 0x40600000, + .end = 0x4060ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB, + .end = IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 udc_dma_mask = ~(u32)0; + +struct platform_device pxa_device_udc = { + .name = "pxa2xx-udc", + .id = -1, + .resource = pxa2xx_udc_resources, + .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), + .dev = { + .platform_data = &pxa_udc_info, + .dma_mask = &udc_dma_mask, + } +}; + +static struct resource pxafb_resources[] = { + [0] = { + .start = 0x44000000, + .end = 0x4400ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LCD, + .end = IRQ_LCD, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 fb_dma_mask = ~(u64)0; + +struct platform_device pxa_device_fb = { + .name = "pxa2xx-fb", + .id = -1, + .dev = { + .dma_mask = &fb_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pxafb_resources), + .resource = pxafb_resources, +}; + +void __init set_pxa_fb_info(struct pxafb_mach_info *info) +{ + pxa_register_device(&pxa_device_fb, info); +} + +void __init set_pxa_fb_parent(struct device *parent_dev) +{ + pxa_device_fb.dev.parent = parent_dev; +} + +static struct resource pxa_resource_ffuart[] = { + { + .start = __PREG(FFUART), + .end = __PREG(FFUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_FFUART, + .end = IRQ_FFUART, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device pxa_device_ffuart= { + .name = "pxa2xx-uart", + .id = 0, + .resource = pxa_resource_ffuart, + .num_resources = ARRAY_SIZE(pxa_resource_ffuart), +}; + +static struct resource pxa_resource_btuart[] = { + { + .start = __PREG(BTUART), + .end = __PREG(BTUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_BTUART, + .end = IRQ_BTUART, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device pxa_device_btuart = { + .name = "pxa2xx-uart", + .id = 1, + .resource = pxa_resource_btuart, + .num_resources = ARRAY_SIZE(pxa_resource_btuart), +}; + +static struct resource pxa_resource_stuart[] = { + { + .start = __PREG(STUART), + .end = __PREG(STUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_STUART, + .end = IRQ_STUART, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device pxa_device_stuart = { + .name = "pxa2xx-uart", + .id = 2, + .resource = pxa_resource_stuart, + .num_resources = ARRAY_SIZE(pxa_resource_stuart), +}; + +static struct resource pxa_resource_hwuart[] = { + { + .start = __PREG(HWUART), + .end = __PREG(HWUART) + 47, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_HWUART, + .end = IRQ_HWUART, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device pxa_device_hwuart = { + .name = "pxa2xx-uart", + .id = 3, + .resource = pxa_resource_hwuart, + .num_resources = ARRAY_SIZE(pxa_resource_hwuart), +}; + +static struct resource pxai2c_resources[] = { + { + .start = 0x40301680, + .end = 0x403016a3, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa_device_i2c = { + .name = "pxa2xx-i2c", + .id = 0, + .resource = pxai2c_resources, + .num_resources = ARRAY_SIZE(pxai2c_resources), +}; + +void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) +{ + pxa_register_device(&pxa_device_i2c, info); +} + +static struct resource pxai2s_resources[] = { + { + .start = 0x40400000, + .end = 0x40400083, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_I2S, + .end = IRQ_I2S, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa_device_i2s = { + .name = "pxa2xx-i2s", + .id = -1, + .resource = pxai2s_resources, + .num_resources = ARRAY_SIZE(pxai2s_resources), +}; + +static u64 pxaficp_dmamask = ~(u32)0; + +struct platform_device pxa_device_ficp = { + .name = "pxa2xx-ir", + .id = -1, + .dev = { + .dma_mask = &pxaficp_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) +{ + pxa_register_device(&pxa_device_ficp, info); +} + +struct platform_device pxa_device_rtc = { + .name = "sa1100-rtc", + .id = -1, +}; + +#ifdef CONFIG_PXA25x + +static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa25x_resource_ssp[] = { + [0] = { + .start = 0x41000000, + .end = 0x4100001f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SSP, + .end = IRQ_SSP, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* DRCMR for RX */ + .start = 13, + .end = 13, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 14, + .end = 14, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa25x_device_ssp = { + .name = "pxa25x-ssp", + .id = 0, + .dev = { + .dma_mask = &pxa25x_ssp_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = pxa25x_resource_ssp, + .num_resources = ARRAY_SIZE(pxa25x_resource_ssp), +}; + +static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa25x_resource_nssp[] = { + [0] = { + .start = 0x41400000, + .end = 0x4140002f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_NSSP, + .end = IRQ_NSSP, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* DRCMR for RX */ + .start = 15, + .end = 15, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 16, + .end = 16, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa25x_device_nssp = { + .name = "pxa25x-nssp", + .id = 1, + .dev = { + .dma_mask = &pxa25x_nssp_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = pxa25x_resource_nssp, + .num_resources = ARRAY_SIZE(pxa25x_resource_nssp), +}; + +static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa25x_resource_assp[] = { + [0] = { + .start = 0x41500000, + .end = 0x4150002f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_ASSP, + .end = IRQ_ASSP, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* DRCMR for RX */ + .start = 23, + .end = 23, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 24, + .end = 24, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa25x_device_assp = { + /* ASSP is basically equivalent to NSSP */ + .name = "pxa25x-nssp", + .id = 2, + .dev = { + .dma_mask = &pxa25x_assp_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = pxa25x_resource_assp, + .num_resources = ARRAY_SIZE(pxa25x_resource_assp), +}; +#endif /* CONFIG_PXA25x */ + +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) + +static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa27x_resource_ohci[] = { + [0] = { + .start = 0x4C000000, + .end = 0x4C00ff6f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USBH1, + .end = IRQ_USBH1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa27x_device_ohci = { + .name = "pxa27x-ohci", + .id = -1, + .dev = { + .dma_mask = &pxa27x_ohci_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(pxa27x_resource_ohci), + .resource = pxa27x_resource_ohci, +}; + +void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) +{ + pxa_register_device(&pxa27x_device_ohci, info); +} + +static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa27x_resource_ssp1[] = { + [0] = { + .start = 0x41000000, + .end = 0x4100003f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SSP, + .end = IRQ_SSP, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* DRCMR for RX */ + .start = 13, + .end = 13, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 14, + .end = 14, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa27x_device_ssp1 = { + .name = "pxa27x-ssp", + .id = 0, + .dev = { + .dma_mask = &pxa27x_ssp1_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = pxa27x_resource_ssp1, + .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1), +}; + +static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa27x_resource_ssp2[] = { + [0] = { + .start = 0x41700000, + .end = 0x4170003f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SSP2, + .end = IRQ_SSP2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* DRCMR for RX */ + .start = 15, + .end = 15, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 16, + .end = 16, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa27x_device_ssp2 = { + .name = "pxa27x-ssp", + .id = 1, + .dev = { + .dma_mask = &pxa27x_ssp2_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = pxa27x_resource_ssp2, + .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2), +}; + +static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa27x_resource_ssp3[] = { + [0] = { + .start = 0x41900000, + .end = 0x4190003f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SSP3, + .end = IRQ_SSP3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* DRCMR for RX */ + .start = 66, + .end = 66, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 67, + .end = 67, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa27x_device_ssp3 = { + .name = "pxa27x-ssp", + .id = 2, + .dev = { + .dma_mask = &pxa27x_ssp3_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = pxa27x_resource_ssp3, + .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), +}; +#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ + +#ifdef CONFIG_PXA3xx +static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa3xx_resource_ssp4[] = { + [0] = { + .start = 0x41a00000, + .end = 0x41a0003f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SSP4, + .end = IRQ_SSP4, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* DRCMR for RX */ + .start = 2, + .end = 2, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 3, + .end = 3, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa3xx_device_ssp4 = { + /* PXA3xx SSP is basically equivalent to PXA27x */ + .name = "pxa27x-ssp", + .id = 3, + .dev = { + .dma_mask = &pxa3xx_ssp4_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = pxa3xx_resource_ssp4, + .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), +}; + +static struct resource pxa3xx_resources_mci2[] = { + [0] = { + .start = 0x42000000, + .end = 0x42000fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MMC2, + .end = IRQ_MMC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 93, + .end = 93, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = 94, + .end = 94, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa3xx_device_mci2 = { + .name = "pxa2xx-mci", + .id = 1, + .dev = { + .dma_mask = &pxamci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2), + .resource = pxa3xx_resources_mci2, +}; + +void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info) +{ + pxa_register_device(&pxa3xx_device_mci2, info); +} + +static struct resource pxa3xx_resources_mci3[] = { + [0] = { + .start = 0x42500000, + .end = 0x42500fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MMC3, + .end = IRQ_MMC3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 100, + .end = 100, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = 101, + .end = 101, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device pxa3xx_device_mci3 = { + .name = "pxa2xx-mci", + .id = 2, + .dev = { + .dma_mask = &pxamci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3), + .resource = pxa3xx_resources_mci3, +}; + +void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) +{ + pxa_register_device(&pxa3xx_device_mci3, info); +} + +#endif /* CONFIG_PXA3xx */ diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 94c8d5c..96c7c89 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -1,4 +1,6 @@ extern struct platform_device pxa_device_mci; +extern struct platform_device pxa3xx_device_mci2; +extern struct platform_device pxa3xx_device_mci3; extern struct platform_device pxa_device_udc; extern struct platform_device pxa_device_fb; extern struct platform_device pxa_device_ffuart; @@ -12,3 +14,13 @@ extern struct platform_device pxa_device_rtc; extern struct platform_device pxa27x_device_i2c_power; extern struct platform_device pxa27x_device_ohci; + +extern struct platform_device pxa25x_device_ssp; +extern struct platform_device pxa25x_device_nssp; +extern struct platform_device pxa25x_device_assp; +extern struct platform_device pxa27x_device_ssp1; +extern struct platform_device pxa27x_device_ssp2; +extern struct platform_device pxa27x_device_ssp3; +extern struct platform_device pxa3xx_device_ssp4; + +void __init pxa_register_device(struct platform_device *dev, void *data); diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c new file mode 100644 index 0000000..ee0ae93 --- /dev/null +++ b/arch/arm/mach-pxa/eseries.c @@ -0,0 +1,101 @@ +/* + * Hardware definitions for the Toshiba eseries PDAs + * + * Copyright (c) 2003 Ian Molton + * + * This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + */ + +#include + +#include +#include +#include +#include + +#include + +/* Only e800 has 128MB RAM */ +static void __init eseries_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, struct meminfo *mi) +{ + mi->nr_banks=1; + mi->bank[0].start = 0xa0000000; + mi->bank[0].node = 0; + if (machine_is_e800()) + mi->bank[0].size = (128*1024*1024); + else + mi->bank[0].size = (64*1024*1024); +} + +/* e-series machine definitions */ + +#ifdef CONFIG_MACH_E330 +MACHINE_START(E330, "Toshiba e330") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E740 +MACHINE_START(E740, "Toshiba e740") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E750 +MACHINE_START(E750, "Toshiba e750") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E400 +MACHINE_START(E400, "Toshiba e400") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E800 +MACHINE_START(E800, "Toshiba e800") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .timer = &pxa_timer, +MACHINE_END +#endif + diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 1c34946..698aeec 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -33,13 +32,7 @@ #include #include -#include -#include -#include -#include -#include -#include "devices.h" #include "generic.h" /* @@ -203,7 +196,7 @@ static struct map_desc standard_io_desc[] __initdata = { }, { /* Mem Ctl */ .virtual = 0xf6000000, .pfn = __phys_to_pfn(0x48000000), - .length = 0x00100000, + .length = 0x00200000, .type = MT_DEVICE }, { /* USB host */ .virtual = 0xf8000000, @@ -233,245 +226,3 @@ void __init pxa_map_io(void) iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); get_clk_frequency_khz(1); } - - -static struct resource pxamci_resources[] = { - [0] = { - .start = 0x41100000, - .end = 0x41100fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_MMC, - .end = IRQ_MMC, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 pxamci_dmamask = 0xffffffffUL; - -struct platform_device pxa_device_mci = { - .name = "pxa2xx-mci", - .id = -1, - .dev = { - .dma_mask = &pxamci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(pxamci_resources), - .resource = pxamci_resources, -}; - -void __init pxa_set_mci_info(struct pxamci_platform_data *info) -{ - pxa_device_mci.dev.platform_data = info; -} - - -static struct pxa2xx_udc_mach_info pxa_udc_info; - -void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) -{ - memcpy(&pxa_udc_info, info, sizeof *info); -} - -static struct resource pxa2xx_udc_resources[] = { - [0] = { - .start = 0x40600000, - .end = 0x4060ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USB, - .end = IRQ_USB, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 udc_dma_mask = ~(u32)0; - -struct platform_device pxa_device_udc = { - .name = "pxa2xx-udc", - .id = -1, - .resource = pxa2xx_udc_resources, - .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), - .dev = { - .platform_data = &pxa_udc_info, - .dma_mask = &udc_dma_mask, - } -}; - -static struct resource pxafb_resources[] = { - [0] = { - .start = 0x44000000, - .end = 0x4400ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LCD, - .end = IRQ_LCD, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 fb_dma_mask = ~(u64)0; - -struct platform_device pxa_device_fb = { - .name = "pxa2xx-fb", - .id = -1, - .dev = { - .dma_mask = &fb_dma_mask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(pxafb_resources), - .resource = pxafb_resources, -}; - -void __init set_pxa_fb_info(struct pxafb_mach_info *info) -{ - pxa_device_fb.dev.platform_data = info; -} - -void __init set_pxa_fb_parent(struct device *parent_dev) -{ - pxa_device_fb.dev.parent = parent_dev; -} - -static struct resource pxa_resource_ffuart[] = { - { - .start = __PREG(FFUART), - .end = __PREG(FFUART) + 35, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_FFUART, - .end = IRQ_FFUART, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device pxa_device_ffuart= { - .name = "pxa2xx-uart", - .id = 0, - .resource = pxa_resource_ffuart, - .num_resources = ARRAY_SIZE(pxa_resource_ffuart), -}; - -static struct resource pxa_resource_btuart[] = { - { - .start = __PREG(BTUART), - .end = __PREG(BTUART) + 35, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_BTUART, - .end = IRQ_BTUART, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device pxa_device_btuart = { - .name = "pxa2xx-uart", - .id = 1, - .resource = pxa_resource_btuart, - .num_resources = ARRAY_SIZE(pxa_resource_btuart), -}; - -static struct resource pxa_resource_stuart[] = { - { - .start = __PREG(STUART), - .end = __PREG(STUART) + 35, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_STUART, - .end = IRQ_STUART, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device pxa_device_stuart = { - .name = "pxa2xx-uart", - .id = 2, - .resource = pxa_resource_stuart, - .num_resources = ARRAY_SIZE(pxa_resource_stuart), -}; - -static struct resource pxa_resource_hwuart[] = { - { - .start = __PREG(HWUART), - .end = __PREG(HWUART) + 47, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_HWUART, - .end = IRQ_HWUART, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device pxa_device_hwuart = { - .name = "pxa2xx-uart", - .id = 3, - .resource = pxa_resource_hwuart, - .num_resources = ARRAY_SIZE(pxa_resource_hwuart), -}; - -static struct resource pxai2c_resources[] = { - { - .start = 0x40301680, - .end = 0x403016a3, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_I2C, - .end = IRQ_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa_device_i2c = { - .name = "pxa2xx-i2c", - .id = 0, - .resource = pxai2c_resources, - .num_resources = ARRAY_SIZE(pxai2c_resources), -}; - -void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) -{ - pxa_device_i2c.dev.platform_data = info; -} - -static struct resource pxai2s_resources[] = { - { - .start = 0x40400000, - .end = 0x40400083, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_I2S, - .end = IRQ_I2S, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa_device_i2s = { - .name = "pxa2xx-i2s", - .id = -1, - .resource = pxai2s_resources, - .num_resources = ARRAY_SIZE(pxai2s_resources), -}; - -static u64 pxaficp_dmamask = ~(u32)0; - -struct platform_device pxa_device_ficp = { - .name = "pxa2xx-ir", - .id = -1, - .dev = { - .dma_mask = &pxaficp_dmamask, - .coherent_dma_mask = 0xffffffff, - }, -}; - -void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) -{ - pxa_device_ficp.dev.platform_data = info; -} - -struct platform_device pxa_device_rtc = { - .name = "sa1100-rtc", - .id = -1, -}; diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 465108d..0a94344 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -54,7 +54,7 @@ static struct resource smc91x_resources[] = { [1] = { .start = IRQ_GPIO(4), .end = IRQ_GPIO(4), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c new file mode 100644 index 0000000..0a4b54c --- /dev/null +++ b/arch/arm/mach-pxa/littleton.c @@ -0,0 +1,325 @@ +/* + * linux/arch/arm/mach-pxa/littleton.c + * + * Support for the Marvell Littleton Development Platform. + * + * Author: Jason Chagas (largely modified code) + * Created: Nov 20, 2006 + * Copyright: (C) Copyright 2006 Marvell International Ltd. + * + * 2007-11-22 modified to align with latest kernel + * eric miao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "generic.h" + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +/* Littleton MFP configurations */ +static mfp_cfg_t littleton_mfp_cfg[] __initdata = { + /* LCD */ + GPIO54_LCD_LDD_0, + GPIO55_LCD_LDD_1, + GPIO56_LCD_LDD_2, + GPIO57_LCD_LDD_3, + GPIO58_LCD_LDD_4, + GPIO59_LCD_LDD_5, + GPIO60_LCD_LDD_6, + GPIO61_LCD_LDD_7, + GPIO62_LCD_LDD_8, + GPIO63_LCD_LDD_9, + GPIO64_LCD_LDD_10, + GPIO65_LCD_LDD_11, + GPIO66_LCD_LDD_12, + GPIO67_LCD_LDD_13, + GPIO68_LCD_LDD_14, + GPIO69_LCD_LDD_15, + GPIO70_LCD_LDD_16, + GPIO71_LCD_LDD_17, + GPIO72_LCD_FCLK, + GPIO73_LCD_LCLK, + GPIO74_LCD_PCLK, + GPIO75_LCD_BIAS, + + /* SSP2 */ + GPIO25_SSP2_SCLK, + GPIO17_SSP2_FRM, + GPIO27_SSP2_TXD, + + /* Debug Ethernet */ + GPIO90_GPIO, +}; + +static struct resource smc91x_resources[] = { + [0] = { + .start = (LITTLETON_ETH_PHYS + 0x300), + .end = (LITTLETON_ETH_PHYS + 0xfffff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), + .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, + } +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULES) +/* use bit 30, 31 as the indicator of command parameter number */ +#define CMD0(x) ((0x00000000) | ((x) << 9)) +#define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1)) +#define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\ + ((x1) << 9) | 0x100 | (x2)) + +static uint32_t lcd_panel_reset[] = { + CMD0(0x1), /* reset */ + CMD0(0x0), /* nop */ + CMD0(0x0), /* nop */ + CMD0(0x0), /* nop */ +}; + +static uint32_t lcd_panel_on[] = { + CMD0(0x29), /* Display ON */ + CMD2(0xB8, 0xFF, 0xF9), /* Output Control */ + CMD0(0x11), /* Sleep out */ + CMD1(0xB0, 0x16), /* Wake */ +}; + +static uint32_t lcd_panel_off[] = { + CMD0(0x28), /* Display OFF */ + CMD2(0xB8, 0x80, 0x02), /* Output Control */ + CMD0(0x10), /* Sleep in */ + CMD1(0xB0, 0x00), /* Deep stand by in */ +}; + +static uint32_t lcd_vga_pass_through[] = { + CMD1(0xB0, 0x16), + CMD1(0xBC, 0x80), + CMD1(0xE1, 0x00), + CMD1(0x36, 0x50), + CMD1(0x3B, 0x00), +}; + +static uint32_t lcd_qvga_pass_through[] = { + CMD1(0xB0, 0x16), + CMD1(0xBC, 0x81), + CMD1(0xE1, 0x00), + CMD1(0x36, 0x50), + CMD1(0x3B, 0x22), +}; + +static uint32_t lcd_vga_transfer[] = { + CMD1(0xcf, 0x02), /* Blanking period control (1) */ + CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */ + CMD1(0xd1, 0x01), /* CKV timing control on/off */ + CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */ + CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */ + CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */ + CMD1(0xd5, 0x14), /* ASW timing control (2) */ + CMD0(0x21), /* Invert for normally black display */ + CMD0(0x29), /* Display on */ +}; + +static uint32_t lcd_qvga_transfer[] = { + CMD1(0xd6, 0x02), /* Blanking period control (1) */ + CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */ + CMD1(0xd8, 0x01), /* CKV timing control on/off */ + CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */ + CMD2(0xde, 0x05, 0x0a), /* OEV timing control */ + CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */ + CMD1(0xe0, 0x0a), /* ASW timing control (2) */ + CMD0(0x21), /* Invert for normally black display */ + CMD0(0x29), /* Display on */ +}; + +static uint32_t lcd_panel_config[] = { + CMD2(0xb8, 0xff, 0xf9), /* Output control */ + CMD0(0x11), /* sleep out */ + CMD1(0xba, 0x01), /* Display mode (1) */ + CMD1(0xbb, 0x00), /* Display mode (2) */ + CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */ + CMD1(0xbf, 0x10), /* Drive system change control */ + CMD1(0xb1, 0x56), /* Booster operation setup */ + CMD1(0xb2, 0x33), /* Booster mode setup */ + CMD1(0xb3, 0x11), /* Booster frequency setup */ + CMD1(0xb4, 0x02), /* Op amp/system clock */ + CMD1(0xb5, 0x35), /* VCS voltage */ + CMD1(0xb6, 0x40), /* VCOM voltage */ + CMD1(0xb7, 0x03), /* External display signal */ + CMD1(0xbd, 0x00), /* ASW slew rate */ + CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */ + CMD1(0xc0, 0x11), /* Sleep out FR count (A) */ + CMD1(0xc1, 0x11), /* Sleep out FR count (B) */ + CMD1(0xc2, 0x11), /* Sleep out FR count (C) */ + CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */ + CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */ + CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */ + CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */ + CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */ + CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */ + CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */ + CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */ + CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */ +}; + +static void ssp_reconfig(struct ssp_dev *dev, int nparam) +{ + static int last_nparam = -1; + + /* check if it is necessary to re-config SSP */ + if (nparam == last_nparam) + return; + + ssp_disable(dev); + ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0); + + last_nparam = nparam; +} + +static void ssp_send_cmd(uint32_t *cmd, int num) +{ + static int ssp_initialized; + static struct ssp_dev ssp2; + + int i; + + if (!ssp_initialized) { + ssp_init(&ssp2, 2, SSP_NO_IRQ); + ssp_initialized = 1; + } + + clk_enable(ssp2.ssp->clk); + for (i = 0; i < num; i++, cmd++) { + ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3); + ssp_write_word(&ssp2, *cmd & 0x3fffffff); + + /* FIXME: ssp_flush() is mandatory here to work */ + ssp_flush(&ssp2); + } + clk_disable(ssp2.ssp->clk); +} + +static void littleton_lcd_power(int on, struct fb_var_screeninfo *var) +{ + if (on) { + ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on)); + ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset)); + if (var->xres > 240) { + /* VGA */ + ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through)); + ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config)); + ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer)); + } else { + /* QVGA */ + ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through)); + ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config)); + ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer)); + } + } else + ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off)); +} + +static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = { + [0] = { + /* VGA */ + .pixclock = 38250, + .xres = 480, + .yres = 640, + .bpp = 16, + .hsync_len = 8, + .left_margin = 8, + .right_margin = 24, + .vsync_len = 2, + .upper_margin = 2, + .lower_margin = 4, + .sync = 0, + }, + [1] = { + /* QVGA */ + .pixclock = 153000, + .xres = 240, + .yres = 320, + .bpp = 16, + .hsync_len = 8, + .left_margin = 8, + .right_margin = 88, + .vsync_len = 2, + .upper_margin = 2, + .lower_margin = 2, + .sync = 0, + }, +}; + +static struct pxafb_mach_info littleton_lcd_info = { + .modes = tpo_tdo24mtea1_modes, + .num_modes = 2, + .lccr0 = LCCR0_Act, + .lccr3 = LCCR3_HSP | LCCR3_VSP, + .pxafb_lcd_power = littleton_lcd_power, +}; + +static void littleton_init_lcd(void) +{ + set_pxa_fb_info(&littleton_lcd_info); +} +#else +static inline void littleton_init_lcd(void) {}; +#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */ + +static void __init littleton_init(void) +{ + /* initialize MFP configurations */ + pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg)); + + /* + * Note: we depend bootloader set the correct + * value to MSC register for SMC91x. + */ + platform_device_register(&smc91x_device); + + littleton_init_lcd(); +} + +MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") + .phys_io = 0x40000000, + .boot_params = 0xa0000100, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, + .init_machine = littleton_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 2611644..02f1b95 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -38,6 +38,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 011a1a7..9deaafa 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include @@ -136,9 +137,13 @@ static struct sys_device lubbock_irq_device = { static int __init lubbock_irq_device_init(void) { - int ret = sysdev_class_register(&lubbock_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&lubbock_irq_device); + int ret = -ENODEV; + + if (machine_is_lubbock()) { + ret = sysdev_class_register(&lubbock_irq_sysclass); + if (ret == 0) + ret = sysdev_register(&lubbock_irq_device); + } return ret; } @@ -191,7 +196,7 @@ static struct resource smc91x_resources[] = { [1] = { .start = LUBBOCK_ETH_IRQ, .end = LUBBOCK_ETH_IRQ, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, [2] = { .name = "smc91x-attrib", @@ -206,30 +211,13 @@ static struct resource smc91x_resources[] = { * (to J5) and poking board registers (as done below). Else it's only useful * for the temperature sensors. */ -static struct resource pxa_ssp_resources[] = { - [0] = { - .start = __PREG(SSCR0_P(1)), - .end = __PREG(SSCR0_P(1)) + 0x14, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SSP, - .end = IRQ_SSP, - .flags = IORESOURCE_IRQ, - }, -}; - static struct pxa2xx_spi_master pxa_ssp_master_info = { - .ssp_type = PXA25x_SSP, - .clock_enable = CKEN_SSP, .num_chipselect = 0, }; static struct platform_device pxa_ssp = { .name = "pxa2xx-spi", .id = 1, - .resource = pxa_ssp_resources, - .num_resources = ARRAY_SIZE(pxa_ssp_resources), .dev = { .platform_data = &pxa_ssp_master_info, }, diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c new file mode 100644 index 0000000..d98ef7a --- /dev/null +++ b/arch/arm/mach-pxa/magician.c @@ -0,0 +1,218 @@ +/* + * Support for HTC Magician PDA phones: + * i-mate JAM, O2 Xda mini, Orange SPV M500, Qtek s100, Qtek s110 + * and T-Mobile MDA Compact. + * + * Copyright (c) 2006-2007 Philipp Zabel + * + * Based on hx4700.c, spitz.c and others. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "generic.h" + +/* + * IRDA + */ + +static void magician_irda_transceiver_mode(struct device *dev, int mode) +{ + gpio_set_value(GPIO83_MAGICIAN_nIR_EN, mode & IR_OFF); +} + +static struct pxaficp_platform_data magician_ficp_info = { + .transceiver_cap = IR_SIRMODE | IR_OFF, + .transceiver_mode = magician_irda_transceiver_mode, +}; + +/* + * GPIO Keys + */ + +static struct gpio_keys_button magician_button_table[] = { + {KEY_POWER, GPIO0_MAGICIAN_KEY_POWER, 0, "Power button"}, + {KEY_ESC, GPIO37_MAGICIAN_KEY_HANGUP, 0, "Hangup button"}, + {KEY_F10, GPIO38_MAGICIAN_KEY_CONTACTS, 0, "Contacts button"}, + {KEY_CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, 0, "Calendar button"}, + {KEY_CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, 0, "Camera button"}, + {KEY_UP, GPIO93_MAGICIAN_KEY_UP, 0, "Up button"}, + {KEY_DOWN, GPIO94_MAGICIAN_KEY_DOWN, 0, "Down button"}, + {KEY_LEFT, GPIO95_MAGICIAN_KEY_LEFT, 0, "Left button"}, + {KEY_RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, 0, "Right button"}, + {KEY_KPENTER, GPIO97_MAGICIAN_KEY_ENTER, 0, "Action button"}, + {KEY_RECORD, GPIO98_MAGICIAN_KEY_RECORD, 0, "Record button"}, + {KEY_VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, 0, "Volume up"}, + {KEY_VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, 0, "Volume down"}, + {KEY_PHONE, GPIO102_MAGICIAN_KEY_PHONE, 0, "Phone button"}, + {KEY_PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, 0, "Headset button"}, +}; + +static struct gpio_keys_platform_data gpio_keys_data = { + .buttons = magician_button_table, + .nbuttons = ARRAY_SIZE(magician_button_table), +}; + +static struct platform_device gpio_keys = { + .name = "gpio-keys", + .dev = { + .platform_data = &gpio_keys_data, + }, + .id = -1, +}; + +/* + * LCD - Toppoly TD028STEB1 + */ + +static struct pxafb_mode_info toppoly_modes[] = { + { + .pixclock = 96153, + .bpp = 16, + .xres = 240, + .yres = 320, + .hsync_len = 11, + .vsync_len = 3, + .left_margin = 19, + .upper_margin = 2, + .right_margin = 10, + .lower_margin = 2, + .sync = 0, + }, +}; + +static struct pxafb_mach_info toppoly_info = { + .modes = toppoly_modes, + .num_modes = 1, + .fixed_modes = 1, + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_PixRsEdg, +}; + +/* + * Backlight + */ + +static void magician_set_bl_intensity(int intensity) +{ + if (intensity) { + PWM_CTRL0 = 1; + PWM_PERVAL0 = 0xc8; + PWM_PWDUTY0 = intensity; + pxa_set_cken(CKEN_PWM0, 1); + } else { + pxa_set_cken(CKEN_PWM0, 0); + } +} + +static struct generic_bl_info backlight_info = { + .default_intensity = 0x64, + .limit_mask = 0x0b, + .max_intensity = 0xc7, + .set_bl_intensity = magician_set_bl_intensity, +}; + +static struct platform_device backlight = { + .name = "corgi-bl", + .dev = { + .platform_data = &backlight_info, + }, + .id = -1, +}; + + +/* + * USB OHCI + */ + +static int magician_ohci_init(struct device *dev) +{ + UHCHR = (UHCHR | UHCHR_SSEP2 | UHCHR_PCPL | UHCHR_CGR) & + ~(UHCHR_SSEP1 | UHCHR_SSEP3 | UHCHR_SSE); + + return 0; +} + +static struct pxaohci_platform_data magician_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .init = magician_ohci_init, + .power_budget = 0, +}; + + +/* + * StrataFlash + */ + +#define PXA_CS_SIZE 0x04000000 + +static struct resource strataflash_resource = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + PXA_CS_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct physmap_flash_data strataflash_data = { + .width = 4, +}; + +static struct platform_device strataflash = { + .name = "physmap-flash", + .id = -1, + .num_resources = 1, + .resource = &strataflash_resource, + .dev = { + .platform_data = &strataflash_data, + }, +}; + +/* + * Platform devices + */ + +static struct platform_device *devices[] __initdata = { + &gpio_keys, + &backlight, + &strataflash, +}; + +static void __init magician_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); + pxa_set_ohci_info(&magician_ohci_info); + pxa_set_ficp_info(&magician_ficp_info); + set_pxa_fb_info(&toppoly_info); +} + + +MACHINE_START(MAGICIAN, "HTC Magician") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .init_machine = magician_init, + .timer = &pxa_timer, +MACHINE_END diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index a4bc348..3faa817 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -38,6 +39,7 @@ #include #include +#include #include #include #include @@ -130,9 +132,13 @@ static struct sys_device mainstone_irq_device = { static int __init mainstone_irq_device_init(void) { - int ret = sysdev_class_register(&mainstone_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&mainstone_irq_device); + int ret = -ENODEV; + + if (machine_is_mainstone()) { + ret = sysdev_class_register(&mainstone_irq_sysclass); + if (ret == 0) + ret = sysdev_register(&mainstone_irq_device); + } return ret; } @@ -150,7 +156,7 @@ static struct resource smc91x_resources[] = { [1] = { .start = MAINSTONE_IRQ(3), .end = MAINSTONE_IRQ(3), - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; @@ -263,21 +269,60 @@ static struct platform_device mst_flash_device[2] = { }, }; -static void mainstone_backlight_power(int on) +#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE +static int mainstone_backlight_update_status(struct backlight_device *bl) { - if (on) { + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK || + bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + + if (brightness != 0) { pxa_gpio_mode(GPIO16_PWM0_MD); pxa_set_cken(CKEN_PWM0, 1); - PWM_CTRL0 = 0; - PWM_PWDUTY0 = 0x3ff; - PWM_PERVAL0 = 0x3ff; - } else { - PWM_CTRL0 = 0; - PWM_PWDUTY0 = 0x0; - PWM_PERVAL0 = 0x3FF; + } + PWM_CTRL0 = 0; + PWM_PWDUTY0 = brightness; + PWM_PERVAL0 = bl->props.max_brightness; + if (brightness == 0) pxa_set_cken(CKEN_PWM0, 0); + return 0; /* pointless return value */ +} + +static int mainstone_backlight_get_brightness(struct backlight_device *bl) +{ + return PWM_PWDUTY0; +} + +static /*const*/ struct backlight_ops mainstone_backlight_ops = { + .update_status = mainstone_backlight_update_status, + .get_brightness = mainstone_backlight_get_brightness, +}; + +static void __init mainstone_backlight_register(void) +{ + struct backlight_device *bl; + + bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev, + NULL, &mainstone_backlight_ops); + if (IS_ERR(bl)) { + printk(KERN_ERR "mainstone: unable to register backlight: %ld\n", + PTR_ERR(bl)); + return; } + + /* + * broken design - register-then-setup interfaces are + * utterly broken by definition. + */ + bl->props.max_brightness = 1023; + bl->props.brightness = 1023; + backlight_update_status(bl); } +#else +#define mainstone_backlight_register() do { } while (0) +#endif static struct pxafb_mode_info toshiba_ltm04c380k_mode = { .pixclock = 50000, @@ -311,7 +356,6 @@ static struct pxafb_mach_info mainstone_pxafb_info = { .num_modes = 1, .lccr0 = LCCR0_Act, .lccr3 = LCCR3_PCP, - .pxafb_backlight_power = mainstone_backlight_power, }; static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data) @@ -473,6 +517,7 @@ static void __init mainstone_init(void) mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; set_pxa_fb_info(&mainstone_pxafb_info); + mainstone_backlight_register(); pxa_set_mci_info(&mainstone_mci_platform_data); pxa_set_ficp_info(&mainstone_ficp_platform_data); diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c index 436f965..ec1b2d8 100644 --- a/arch/arm/mach-pxa/mfp.c +++ b/arch/arm/mach-pxa/mfp.c @@ -17,9 +17,11 @@ #include #include #include +#include #include #include +#include /* mfp_spin_lock is used to ensure that MFP register configuration * (most likely a read-modify-write operation) is atomic, and that @@ -28,43 +30,110 @@ static DEFINE_SPINLOCK(mfp_spin_lock); static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE); + +struct pxa3xx_mfp_pin { + unsigned long config; /* -1 for not configured */ + unsigned long mfpr_off; /* MFPRxx Register offset */ + unsigned long mfpr_run; /* Run-Mode Register Value */ + unsigned long mfpr_lpm; /* Low Power Mode Register Value */ +}; + static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; +/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ +const static unsigned long mfpr_lpm[] = { + MFPR_LPM_INPUT, + MFPR_LPM_DRIVE_LOW, + MFPR_LPM_DRIVE_HIGH, + MFPR_LPM_PULL_LOW, + MFPR_LPM_PULL_HIGH, + MFPR_LPM_FLOAT, +}; + +/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ +const static unsigned long mfpr_pull[] = { + MFPR_PULL_NONE, + MFPR_PULL_LOW, + MFPR_PULL_HIGH, + MFPR_PULL_BOTH, +}; + +/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ +const static unsigned long mfpr_edge[] = { + MFPR_EDGE_NONE, + MFPR_EDGE_RISE, + MFPR_EDGE_FALL, + MFPR_EDGE_BOTH, +}; + #define mfpr_readl(off) \ __raw_readl(mfpr_mmio_base + (off)) #define mfpr_writel(off, val) \ __raw_writel(val, mfpr_mmio_base + (off)) +#define mfp_configured(p) ((p)->config != -1) + /* * perform a read-back of any MFPR register to make sure the * previous writings are finished */ #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) -static inline void __mfp_config(int pin, unsigned long val) +static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p) { - unsigned long off = mfp_table[pin].mfpr_off; + if (mfp_configured(p)) + mfpr_writel(p->mfpr_off, p->mfpr_run); +} - mfp_table[pin].mfpr_val = val; - mfpr_writel(off, val); +static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p) +{ + if (mfp_configured(p)) { + unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR; + if (mfpr_clr != p->mfpr_run) + mfpr_writel(p->mfpr_off, mfpr_clr); + if (p->mfpr_lpm != mfpr_clr) + mfpr_writel(p->mfpr_off, p->mfpr_lpm); + } } -void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num) +void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num) { - int i, pin; - unsigned long val, flags; - mfp_cfg_t *mfp_cfg = mfp_cfgs; + unsigned long flags; + int i; spin_lock_irqsave(&mfp_spin_lock, flags); - for (i = 0; i < num; i++, mfp_cfg++) { - pin = MFP_CFG_PIN(*mfp_cfg); - val = MFP_CFG_VAL(*mfp_cfg); + for (i = 0; i < num; i++, mfp_cfgs++) { + unsigned long tmp, c = *mfp_cfgs; + struct pxa3xx_mfp_pin *p; + int pin, af, drv, lpm, edge, pull; + pin = MFP_PIN(c); BUG_ON(pin >= MFP_PIN_MAX); - - __mfp_config(pin, val); + p = &mfp_table[pin]; + + af = MFP_AF(c); + drv = MFP_DS(c); + lpm = MFP_LPM_STATE(c); + edge = MFP_LPM_EDGE(c); + pull = MFP_PULL(c); + + /* run-mode pull settings will conflict with MFPR bits of + * low power mode state, calculate mfpr_run and mfpr_lpm + * individually if pull != MFP_PULL_NONE + */ + tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); + + if (likely(pull == MFP_PULL_NONE)) { + p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; + p->mfpr_lpm = p->mfpr_run; + } else { + p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; + p->mfpr_run = tmp | mfpr_pull[pull]; + } + + p->config = c; __mfp_config_run(p); } mfpr_sync(); @@ -96,140 +165,82 @@ void pxa3xx_mfp_write(int mfp, unsigned long val) spin_unlock_irqrestore(&mfp_spin_lock, flags); } -void pxa3xx_mfp_set_afds(int mfp, int af, int ds) -{ - uint32_t mfpr_off, mfpr_val; - unsigned long flags; - - BUG_ON(mfp >= MFP_PIN_MAX); - - spin_lock_irqsave(&mfp_spin_lock, flags); - mfpr_off = mfp_table[mfp].mfpr_off; - - mfpr_val = mfpr_readl(mfpr_off); - mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK); - mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) | - ((ds & 0x7) << MFPR_DRV_OFFSET)); - - mfpr_writel(mfpr_off, mfpr_val); - mfpr_sync(); - - spin_unlock_irqrestore(&mfp_spin_lock, flags); -} - -void pxa3xx_mfp_set_rdh(int mfp, int rdh) +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) { - uint32_t mfpr_off, mfpr_val; - unsigned long flags; - - BUG_ON(mfp >= MFP_PIN_MAX); + struct pxa3xx_mfp_addr_map *p; + unsigned long offset, flags; + int i; spin_lock_irqsave(&mfp_spin_lock, flags); - mfpr_off = mfp_table[mfp].mfpr_off; - - mfpr_val = mfpr_readl(mfpr_off); - mfpr_val &= ~MFPR_RDH_MASK; - - if (likely(rdh)) - mfpr_val |= (1u << MFPR_SS_OFFSET); + for (p = map; p->start != MFP_PIN_INVALID; p++) { + offset = p->offset; + i = p->start; - mfpr_writel(mfpr_off, mfpr_val); - mfpr_sync(); + do { + mfp_table[i].mfpr_off = offset; + mfp_table[i].mfpr_run = 0; + mfp_table[i].mfpr_lpm = 0; + offset += 4; i++; + } while ((i <= p->end) && (p->end != -1)); + } spin_unlock_irqrestore(&mfp_spin_lock, flags); } -void pxa3xx_mfp_set_lpm(int mfp, int lpm) +void __init pxa3xx_init_mfp(void) { - uint32_t mfpr_off, mfpr_val; - unsigned long flags; - - BUG_ON(mfp >= MFP_PIN_MAX); - - spin_lock_irqsave(&mfp_spin_lock, flags); - - mfpr_off = mfp_table[mfp].mfpr_off; - mfpr_val = mfpr_readl(mfpr_off); - mfpr_val &= ~MFPR_LPM_MASK; - - if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET; - if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET; - if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET; - if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET; - if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET; - - mfpr_writel(mfpr_off, mfpr_val); - mfpr_sync(); + int i; - spin_unlock_irqrestore(&mfp_spin_lock, flags); + for (i = 0; i < ARRAY_SIZE(mfp_table); i++) + mfp_table[i].config = -1; } -void pxa3xx_mfp_set_pull(int mfp, int pull) +#ifdef CONFIG_PM +/* + * Configure the MFPs appropriately for suspend/resume. + * FIXME: this should probably depend on which system state we're + * entering - for instance, we might not want to place MFP pins in + * a pull-down mode if they're an active low chip select, and we're + * just entering standby. + */ +static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) { - uint32_t mfpr_off, mfpr_val; - unsigned long flags; - - BUG_ON(mfp >= MFP_PIN_MAX); - - spin_lock_irqsave(&mfp_spin_lock, flags); + int pin; - mfpr_off = mfp_table[mfp].mfpr_off; - mfpr_val = mfpr_readl(mfpr_off); - mfpr_val &= ~MFPR_PULL_MASK; - mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET); - - mfpr_writel(mfpr_off, mfpr_val); - mfpr_sync(); - - spin_unlock_irqrestore(&mfp_spin_lock, flags); + for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) { + struct pxa3xx_mfp_pin *p = &mfp_table[pin]; + __mfp_config_lpm(p); + } + return 0; } -void pxa3xx_mfp_set_edge(int mfp, int edge) +static int pxa3xx_mfp_resume(struct sys_device *d) { - uint32_t mfpr_off, mfpr_val; - unsigned long flags; - - BUG_ON(mfp >= MFP_PIN_MAX); - - spin_lock_irqsave(&mfp_spin_lock, flags); - - mfpr_off = mfp_table[mfp].mfpr_off; - mfpr_val = mfpr_readl(mfpr_off); - - mfpr_val &= ~MFPR_EDGE_MASK; - mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET; - mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET; + int pin; - mfpr_writel(mfpr_off, mfpr_val); - mfpr_sync(); - - spin_unlock_irqrestore(&mfp_spin_lock, flags); + for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) { + struct pxa3xx_mfp_pin *p = &mfp_table[pin]; + __mfp_config_run(p); + } + return 0; } -void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) -{ - struct pxa3xx_mfp_addr_map *p; - unsigned long offset, flags; - int i; - - spin_lock_irqsave(&mfp_spin_lock, flags); - - for (p = map; p->start != MFP_PIN_INVALID; p++) { - offset = p->offset; - i = p->start; - - do { - mfp_table[i].mfpr_off = offset; - mfp_table[i].mfpr_val = 0; - offset += 4; i++; - } while ((i <= p->end) && (p->end != -1)); - } +static struct sysdev_class mfp_sysclass = { + set_kset_name("mfp"), + .suspend = pxa3xx_mfp_suspend, + .resume = pxa3xx_mfp_resume, +}; - spin_unlock_irqrestore(&mfp_spin_lock, flags); -} +static struct sys_device mfp_device = { + .id = 0, + .cls = &mfp_sysclass, +}; -void __init pxa3xx_init_mfp(void) +static int __init mfp_init_devicefs(void) { - memset(mfp_table, 0, sizeof(mfp_table)); + sysdev_class_register(&mfp_sysclass); + return sysdev_register(&mfp_device); } +device_initcall(mfp_init_devicefs); +#endif diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 9732d5d..962cfbb 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -120,12 +120,15 @@ static struct clk pxa25x_clks[] = { INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), + + INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), + INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), + INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), + /* INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), - INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL), INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), - INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL), */ INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), }; @@ -236,6 +239,8 @@ static void __init pxa25x_init_pm(void) { pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; } +#else +static inline void pxa25x_init_pm(void) {} #endif /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm @@ -287,16 +292,15 @@ void __init pxa25x_init_irq(void) } static struct platform_device *pxa25x_devices[] __initdata = { - &pxa_device_mci, &pxa_device_udc, - &pxa_device_fb, &pxa_device_ffuart, &pxa_device_btuart, &pxa_device_stuart, - &pxa_device_i2c, &pxa_device_i2s, - &pxa_device_ficp, &pxa_device_rtc, + &pxa25x_device_ssp, + &pxa25x_device_nssp, + &pxa25x_device_assp, }; static int __init pxa25x_init(void) @@ -308,9 +312,9 @@ static int __init pxa25x_init(void) if ((ret = pxa_init_dma(16))) return ret; -#ifdef CONFIG_PM + pxa25x_init_pm(); -#endif + ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 8e126e6..f33c9d7 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -150,11 +151,12 @@ static struct clk pxa27x_clks[] = { INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), + INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), + INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), + INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), + /* INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), - INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL), - INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL), - INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL), INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), @@ -304,6 +306,8 @@ static void __init pxa27x_init_pm(void) { pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; } +#else +static inline void pxa27x_init_pm(void) {} #endif /* PXA27x: Various gpios can issue wakeup events. This logic only @@ -373,37 +377,6 @@ void __init pxa27x_init_irq(void) * device registration specific to PXA27x. */ -static u64 pxa27x_dmamask = 0xffffffffUL; - -static struct resource pxa27x_ohci_resources[] = { - [0] = { - .start = 0x4C000000, - .end = 0x4C00ff6f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBH1, - .end = IRQ_USBH1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa27x_device_ohci = { - .name = "pxa27x-ohci", - .id = -1, - .dev = { - .dma_mask = &pxa27x_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(pxa27x_ohci_resources), - .resource = pxa27x_ohci_resources, -}; - -void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) -{ - pxa27x_device_ohci.dev.platform_data = info; -} - static struct resource i2c_power_resources[] = { { .start = 0x40f00180, @@ -424,18 +397,16 @@ struct platform_device pxa27x_device_i2c_power = { }; static struct platform_device *devices[] __initdata = { - &pxa_device_mci, &pxa_device_udc, - &pxa_device_fb, &pxa_device_ffuart, &pxa_device_btuart, &pxa_device_stuart, - &pxa_device_i2c, &pxa_device_i2s, - &pxa_device_ficp, &pxa_device_rtc, &pxa27x_device_i2c_power, - &pxa27x_device_ohci, + &pxa27x_device_ssp1, + &pxa27x_device_ssp2, + &pxa27x_device_ssp3, }; static int __init pxa27x_init(void) @@ -446,9 +417,9 @@ static int __init pxa27x_init(void) if ((ret = pxa_init_dma(32))) return ret; -#ifdef CONFIG_PM + pxa27x_init_pm(); -#endif + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } return ret; diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 61d9c9d..0b2a15e 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -189,8 +190,237 @@ static struct clk pxa3xx_clks[] = { PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), + PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), + + PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), + PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), + PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), + PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), + + PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), + PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), + PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), +}; + +#ifdef CONFIG_PM +#define SLEEP_SAVE_SIZE 4 + +#define ISRAM_START 0x5c000000 +#define ISRAM_SIZE SZ_256K + +static void __iomem *sram; +static unsigned long wakeup_src; + +static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) +{ + pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB); + + if (CKENA & (1 << CKEN_USBH)) { + printk(KERN_ERR "PM: USB host clock not stopped?\n"); + CKENA &= ~(1 << CKEN_USBH); + } +// CKENA |= 1 << (CKEN_ISC & 31); + + /* + * Low power modes require the HSIO2 clock to be enabled. + */ + CKENB |= 1 << (CKEN_HSIO2 & 31); +} + +static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) +{ + CKENB &= ~(1 << (CKEN_HSIO2 & 31)); +} + +/* + * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic + * memory controller has to be reinitialised, so we place some code + * in the SRAM to perform this function. + * + * We disable FIQs across the standby - otherwise, we might receive a + * FIQ while the SDRAM is unavailable. + */ +static void pxa3xx_cpu_standby(unsigned int pwrmode) +{ + extern const char pm_enter_standby_start[], pm_enter_standby_end[]; + void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); + + memcpy_toio(sram + 0x8000, pm_enter_standby_start, + pm_enter_standby_end - pm_enter_standby_start); + + AD2D0SR = ~0; + AD2D1SR = ~0; + AD2D0ER = wakeup_src; + AD2D1ER = 0; + ASCR = ASCR; + ARSR = ARSR; + + local_fiq_disable(); + fn(pwrmode); + local_fiq_enable(); + + AD2D0ER = 0; + AD2D1ER = 0; + + printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR); +} + +static void pxa3xx_cpu_pm_enter(suspend_state_t state) +{ + /* + * Don't sleep if no wakeup sources are defined + */ + if (wakeup_src == 0) + return; + + switch (state) { + case PM_SUSPEND_STANDBY: + pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); + break; + + case PM_SUSPEND_MEM: + break; + } +} + +static int pxa3xx_cpu_pm_valid(suspend_state_t state) +{ + return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; +} + +static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { + .save_size = SLEEP_SAVE_SIZE, + .save = pxa3xx_cpu_pm_save, + .restore = pxa3xx_cpu_pm_restore, + .valid = pxa3xx_cpu_pm_valid, + .enter = pxa3xx_cpu_pm_enter, }; +static void __init pxa3xx_init_pm(void) +{ + sram = ioremap(ISRAM_START, ISRAM_SIZE); + if (!sram) { + printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); + return; + } + + /* + * Since we copy wakeup code into the SRAM, we need to ensure + * that it is preserved over the low power modes. Note: bit 8 + * is undocumented in the developer manual, but must be set. + */ + AD1R |= ADXR_L2 | ADXR_R0; + AD2R |= ADXR_L2 | ADXR_R0; + AD3R |= ADXR_L2 | ADXR_R0; + + /* + * Clear the resume enable registers. + */ + AD1D0ER = 0; + AD2D0ER = 0; + AD2D1ER = 0; + AD3ER = 0; + + pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; +} + +static int pxa3xx_set_wake(unsigned int irq, unsigned int on) +{ + unsigned long flags, mask = 0; + + switch (irq) { + case IRQ_SSP3: + mask = ADXER_MFP_WSSP3; + break; + case IRQ_MSL: + mask = ADXER_WMSL0; + break; + case IRQ_USBH2: + case IRQ_USBH1: + mask = ADXER_WUSBH; + break; + case IRQ_KEYPAD: + mask = ADXER_WKP; + break; + case IRQ_AC97: + mask = ADXER_MFP_WAC97; + break; + case IRQ_USIM: + mask = ADXER_WUSIM0; + break; + case IRQ_SSP2: + mask = ADXER_MFP_WSSP2; + break; + case IRQ_I2C: + mask = ADXER_MFP_WI2C; + break; + case IRQ_STUART: + mask = ADXER_MFP_WUART3; + break; + case IRQ_BTUART: + mask = ADXER_MFP_WUART2; + break; + case IRQ_FFUART: + mask = ADXER_MFP_WUART1; + break; + case IRQ_MMC: + mask = ADXER_MFP_WMMC1; + break; + case IRQ_SSP: + mask = ADXER_MFP_WSSP1; + break; + case IRQ_RTCAlrm: + mask = ADXER_WRTC; + break; + case IRQ_SSP4: + mask = ADXER_MFP_WSSP4; + break; + case IRQ_TSI: + mask = ADXER_WTSI; + break; + case IRQ_USIM2: + mask = ADXER_WUSIM1; + break; + case IRQ_MMC2: + mask = ADXER_MFP_WMMC2; + break; + case IRQ_NAND: + mask = ADXER_MFP_WFLASH; + break; + case IRQ_USB2: + mask = ADXER_WUSB2; + break; + case IRQ_WAKEUP0: + mask = ADXER_WEXTWAKE0; + break; + case IRQ_WAKEUP1: + mask = ADXER_WEXTWAKE1; + break; + case IRQ_MMC3: + mask = ADXER_MFP_GEN12; + break; + } + + local_irq_save(flags); + if (on) + wakeup_src |= mask; + else + wakeup_src &= ~mask; + local_irq_restore(flags); + + return 0; +} + +static void pxa3xx_init_irq_pm(void) +{ + pxa_init_irq_set_wake(pxa3xx_set_wake); +} + +#else +static inline void pxa3xx_init_pm(void) {} +static inline void pxa3xx_init_irq_pm(void) {} +#endif + void __init pxa3xx_init_irq(void) { /* enable CP6 access */ @@ -202,6 +432,7 @@ void __init pxa3xx_init_irq(void) pxa_init_irq_low(); pxa_init_irq_high(); pxa_init_irq_gpio(128); + pxa3xx_init_irq_pm(); } /* @@ -209,16 +440,16 @@ void __init pxa3xx_init_irq(void) */ static struct platform_device *devices[] __initdata = { - &pxa_device_mci, &pxa_device_udc, - &pxa_device_fb, &pxa_device_ffuart, &pxa_device_btuart, &pxa_device_stuart, - &pxa_device_i2c, &pxa_device_i2s, - &pxa_device_ficp, &pxa_device_rtc, + &pxa27x_device_ssp1, + &pxa27x_device_ssp2, + &pxa27x_device_ssp3, + &pxa3xx_device_ssp4, }; static int __init pxa3xx_init(void) @@ -231,6 +462,8 @@ static int __init pxa3xx_init(void) if ((ret = pxa_init_dma(32))) return ret; + pxa3xx_init_pm(); + return platform_add_devices(devices, ARRAY_SIZE(devices)); } return 0; diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index aff71fe..218a904 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -16,6 +16,7 @@ #include #include +#include #define MDREFR_KDIV 0x200a4000 // all banks #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 @@ -49,6 +50,7 @@ pxa_cpu_save_sp: str r0, [r1] mov pc, r2 +#ifdef CONFIG_PXA27x /* * pxa27x_cpu_suspend() * @@ -104,9 +106,11 @@ ENTRY(pxa27x_cpu_suspend) @ align execution to a cache line b pxa_cpu_do_suspend +#endif +#ifdef CONFIG_PXA25x /* - * pxa27x_cpu_suspend() + * pxa25x_cpu_suspend() * * Forces CPU into sleep state. * @@ -169,6 +173,7 @@ ENTRY(pxa25x_cpu_suspend) mcr p14, 0, r0, c6, c0, 0 orr r0, r0, #2 @ initiate change bit b pxa_cpu_do_suspend +#endif .ltorg .align 5 @@ -208,7 +213,7 @@ pxa_cpu_do_suspend: 20: b 20b @ loop waiting for sleep /* - * cpu_pxa_resume() + * pxa_cpu_resume() * * entry point from bootloader into kernel during resume * diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 422afee..00af7f2 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c @@ -32,45 +32,27 @@ #include #include #include +#include +#include +#include + #include #include #include #include #include - -#define PXA_SSP_PORTS 3 +#include #define TIMEOUT 100000 -struct ssp_info_ { - int irq; - u32 clock; -}; - -/* - * SSP port clock and IRQ settings - */ -static const struct ssp_info_ ssp_info[PXA_SSP_PORTS] = { -#if defined (CONFIG_PXA27x) - {IRQ_SSP, CKEN_SSP1}, - {IRQ_SSP2, CKEN_SSP2}, - {IRQ_SSP3, CKEN_SSP3}, -#else - {IRQ_SSP, CKEN_SSP}, - {IRQ_NSSP, CKEN_NSSP}, - {IRQ_ASSP, CKEN_ASSP}, -#endif -}; - -static DEFINE_MUTEX(mutex); -static int use_count[PXA_SSP_PORTS] = {0, 0, 0}; - static irqreturn_t ssp_interrupt(int irq, void *dev_id) { - struct ssp_dev *dev = (struct ssp_dev*) dev_id; - unsigned int status = SSSR_P(dev->port); + struct ssp_dev *dev = dev_id; + struct ssp_device *ssp = dev->ssp; + unsigned int status; - SSSR_P(dev->port) = status; /* clear status bits */ + status = __raw_readl(ssp->mmio_base + SSSR); + __raw_writel(status, ssp->mmio_base + SSSR); if (status & SSSR_ROR) printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port); @@ -99,15 +81,16 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id) */ int ssp_write_word(struct ssp_dev *dev, u32 data) { + struct ssp_device *ssp = dev->ssp; int timeout = TIMEOUT; - while (!(SSSR_P(dev->port) & SSSR_TNF)) { + while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) { if (!--timeout) return -ETIMEDOUT; cpu_relax(); } - SSDR_P(dev->port) = data; + __raw_writel(data, ssp->mmio_base + SSDR); return 0; } @@ -129,15 +112,16 @@ int ssp_write_word(struct ssp_dev *dev, u32 data) */ int ssp_read_word(struct ssp_dev *dev, u32 *data) { + struct ssp_device *ssp = dev->ssp; int timeout = TIMEOUT; - while (!(SSSR_P(dev->port) & SSSR_RNE)) { + while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) { if (!--timeout) return -ETIMEDOUT; cpu_relax(); } - *data = SSDR_P(dev->port); + *data = __raw_readl(ssp->mmio_base + SSDR); return 0; } @@ -151,17 +135,28 @@ int ssp_read_word(struct ssp_dev *dev, u32 *data) */ int ssp_flush(struct ssp_dev *dev) { + struct ssp_device *ssp = dev->ssp; int timeout = TIMEOUT * 2; + /* ensure TX FIFO is empty instead of not full */ + if (cpu_is_pxa3xx()) { + while (__raw_readl(ssp->mmio_base + SSSR) & 0xf00) { + if (!--timeout) + return -ETIMEDOUT; + cpu_relax(); + } + timeout = TIMEOUT * 2; + } + do { - while (SSSR_P(dev->port) & SSSR_RNE) { + while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) { if (!--timeout) return -ETIMEDOUT; - (void) SSDR_P(dev->port); + (void)__raw_readl(ssp->mmio_base + SSDR); } if (!--timeout) return -ETIMEDOUT; - } while (SSSR_P(dev->port) & SSSR_BSY); + } while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY); return 0; } @@ -173,7 +168,12 @@ int ssp_flush(struct ssp_dev *dev) */ void ssp_enable(struct ssp_dev *dev) { - SSCR0_P(dev->port) |= SSCR0_SSE; + struct ssp_device *ssp = dev->ssp; + uint32_t sscr0; + + sscr0 = __raw_readl(ssp->mmio_base + SSCR0); + sscr0 |= SSCR0_SSE; + __raw_writel(sscr0, ssp->mmio_base + SSCR0); } /** @@ -183,7 +183,12 @@ void ssp_enable(struct ssp_dev *dev) */ void ssp_disable(struct ssp_dev *dev) { - SSCR0_P(dev->port) &= ~SSCR0_SSE; + struct ssp_device *ssp = dev->ssp; + uint32_t sscr0; + + sscr0 = __raw_readl(ssp->mmio_base + SSCR0); + sscr0 &= ~SSCR0_SSE; + __raw_writel(sscr0, ssp->mmio_base + SSCR0); } /** @@ -192,14 +197,16 @@ void ssp_disable(struct ssp_dev *dev) * * Save the configured SSP state for suspend. */ -void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp) +void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state) { - ssp->cr0 = SSCR0_P(dev->port); - ssp->cr1 = SSCR1_P(dev->port); - ssp->to = SSTO_P(dev->port); - ssp->psp = SSPSP_P(dev->port); + struct ssp_device *ssp = dev->ssp; + + state->cr0 = __raw_readl(ssp->mmio_base + SSCR0); + state->cr1 = __raw_readl(ssp->mmio_base + SSCR1); + state->to = __raw_readl(ssp->mmio_base + SSTO); + state->psp = __raw_readl(ssp->mmio_base + SSPSP); - SSCR0_P(dev->port) &= ~SSCR0_SSE; + ssp_disable(dev); } /** @@ -208,16 +215,18 @@ void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp) * * Restore the SSP configuration saved previously by ssp_save_state. */ -void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp) +void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state) { - SSSR_P(dev->port) = SSSR_ROR | SSSR_TUR | SSSR_BCE; + struct ssp_device *ssp = dev->ssp; + uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; - SSCR0_P(dev->port) = ssp->cr0 & ~SSCR0_SSE; - SSCR1_P(dev->port) = ssp->cr1; - SSTO_P(dev->port) = ssp->to; - SSPSP_P(dev->port) = ssp->psp; + __raw_writel(sssr, ssp->mmio_base + SSSR); - SSCR0_P(dev->port) = ssp->cr0; + __raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); + __raw_writel(state->cr1, ssp->mmio_base + SSCR1); + __raw_writel(state->to, ssp->mmio_base + SSTO); + __raw_writel(state->psp, ssp->mmio_base + SSPSP); + __raw_writel(state->cr0, ssp->mmio_base + SSCR0); } /** @@ -231,15 +240,17 @@ void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp) */ int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed) { + struct ssp_device *ssp = dev->ssp; + dev->mode = mode; dev->flags = flags; dev->psp_flags = psp_flags; dev->speed = speed; /* set up port type, speed, port settings */ - SSCR0_P(dev->port) = (dev->speed | dev->mode); - SSCR1_P(dev->port) = dev->flags; - SSPSP_P(dev->port) = dev->psp_flags; + __raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0); + __raw_writel(dev->flags, ssp->mmio_base + SSCR1); + __raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP); return 0; } @@ -256,44 +267,32 @@ int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 spee */ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags) { + struct ssp_device *ssp; int ret; - if (port > PXA_SSP_PORTS || port == 0) + ssp = ssp_request(port, "SSP"); + if (ssp == NULL) return -ENODEV; - mutex_lock(&mutex); - if (use_count[port - 1]) { - mutex_unlock(&mutex); - return -EBUSY; - } - use_count[port - 1]++; - - if (!request_mem_region(__PREG(SSCR0_P(port)), 0x2c, "SSP")) { - use_count[port - 1]--; - mutex_unlock(&mutex); - return -EBUSY; - } + dev->ssp = ssp; dev->port = port; /* do we need to get irq */ if (!(init_flags & SSP_NO_IRQ)) { - ret = request_irq(ssp_info[port-1].irq, ssp_interrupt, + ret = request_irq(ssp->irq, ssp_interrupt, 0, "SSP", dev); if (ret) goto out_region; - dev->irq = ssp_info[port-1].irq; + dev->irq = ssp->irq; } else dev->irq = 0; /* turn on SSP port clock */ - pxa_set_cken(ssp_info[port-1].clock, 1); - mutex_unlock(&mutex); + clk_enable(ssp->clk); return 0; out_region: - release_mem_region(__PREG(SSCR0_P(port)), 0x2c); - use_count[port - 1]--; - mutex_unlock(&mutex); + ssp_free(ssp); return ret; } @@ -304,23 +303,240 @@ out_region: */ void ssp_exit(struct ssp_dev *dev) { - mutex_lock(&mutex); - SSCR0_P(dev->port) &= ~SSCR0_SSE; + struct ssp_device *ssp = dev->ssp; + + ssp_disable(dev); + free_irq(dev->irq, dev); + clk_disable(ssp->clk); + ssp_free(ssp); +} + +static DEFINE_MUTEX(ssp_lock); +static LIST_HEAD(ssp_list); + +struct ssp_device *ssp_request(int port, const char *label) +{ + struct ssp_device *ssp = NULL; + + mutex_lock(&ssp_lock); + + list_for_each_entry(ssp, &ssp_list, node) { + if (ssp->port_id == port && ssp->use_count == 0) { + ssp->use_count++; + ssp->label = label; + break; + } + } + + mutex_unlock(&ssp_lock); + + if (ssp->port_id != port) + return NULL; + + return ssp; +} +EXPORT_SYMBOL(ssp_request); + +void ssp_free(struct ssp_device *ssp) +{ + mutex_lock(&ssp_lock); + if (ssp->use_count) { + ssp->use_count--; + ssp->label = NULL; + } else + dev_err(&ssp->pdev->dev, "device already free\n"); + mutex_unlock(&ssp_lock); +} +EXPORT_SYMBOL(ssp_free); + +static int __devinit ssp_probe(struct platform_device *pdev, int type) +{ + struct resource *res; + struct ssp_device *ssp; + int ret = 0; + + ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL); + if (ssp == NULL) { + dev_err(&pdev->dev, "failed to allocate memory"); + return -ENOMEM; + } + + ssp->clk = clk_get(&pdev->dev, "SSPCLK"); + if (IS_ERR(ssp->clk)) { + ret = PTR_ERR(ssp->clk); + goto err_free; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free_clk; + } + + res = request_mem_region(res->start, res->end - res->start + 1, + pdev->name); + if (res == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free_clk; + } + + ssp->phys_base = res->start; + + ssp->mmio_base = ioremap(res->start, res->end - res->start + 1); + if (ssp->mmio_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + + ssp->irq = platform_get_irq(pdev, 0); + if (ssp->irq < 0) { + dev_err(&pdev->dev, "no IRQ resource defined\n"); + ret = -ENODEV; + goto err_free_io; + } + + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no SSP RX DRCMR defined\n"); + ret = -ENODEV; + goto err_free_io; + } + ssp->drcmr_rx = res->start; + + res = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (res == NULL) { + dev_err(&pdev->dev, "no SSP TX DRCMR defined\n"); + ret = -ENODEV; + goto err_free_io; + } + ssp->drcmr_tx = res->start; + + /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id + * starts from 0, do a translation here + */ + ssp->port_id = pdev->id + 1; + ssp->use_count = 0; + ssp->type = type; + + mutex_lock(&ssp_lock); + list_add(&ssp->node, &ssp_list); + mutex_unlock(&ssp_lock); + + platform_set_drvdata(pdev, ssp); + return 0; + +err_free_io: + iounmap(ssp->mmio_base); +err_free_mem: + release_mem_region(res->start, res->end - res->start + 1); +err_free_clk: + clk_put(ssp->clk); +err_free: + kfree(ssp); + return ret; +} + +static int __devexit ssp_remove(struct platform_device *pdev) +{ + struct resource *res; + struct ssp_device *ssp; + + ssp = platform_get_drvdata(pdev); + if (ssp == NULL) + return -ENODEV; + + iounmap(ssp->mmio_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start + 1); + + clk_put(ssp->clk); - if (dev->port > PXA_SSP_PORTS || dev->port == 0) { - printk(KERN_WARNING "SSP: tried to close invalid port\n"); - mutex_unlock(&mutex); - return; + mutex_lock(&ssp_lock); + list_del(&ssp->node); + mutex_unlock(&ssp_lock); + + kfree(ssp); + return 0; +} + +static int __devinit pxa25x_ssp_probe(struct platform_device *pdev) +{ + return ssp_probe(pdev, PXA25x_SSP); +} + +static int __devinit pxa25x_nssp_probe(struct platform_device *pdev) +{ + return ssp_probe(pdev, PXA25x_NSSP); +} + +static int __devinit pxa27x_ssp_probe(struct platform_device *pdev) +{ + return ssp_probe(pdev, PXA27x_SSP); +} + +static struct platform_driver pxa25x_ssp_driver = { + .driver = { + .name = "pxa25x-ssp", + }, + .probe = pxa25x_ssp_probe, + .remove = __devexit_p(ssp_remove), +}; + +static struct platform_driver pxa25x_nssp_driver = { + .driver = { + .name = "pxa25x-nssp", + }, + .probe = pxa25x_nssp_probe, + .remove = __devexit_p(ssp_remove), +}; + +static struct platform_driver pxa27x_ssp_driver = { + .driver = { + .name = "pxa27x-ssp", + }, + .probe = pxa27x_ssp_probe, + .remove = __devexit_p(ssp_remove), +}; + +static int __init pxa_ssp_init(void) +{ + int ret = 0; + + ret = platform_driver_register(&pxa25x_ssp_driver); + if (ret) { + printk(KERN_ERR "failed to register pxa25x_ssp_driver"); + return ret; + } + + ret = platform_driver_register(&pxa25x_nssp_driver); + if (ret) { + printk(KERN_ERR "failed to register pxa25x_nssp_driver"); + return ret; + } + + ret = platform_driver_register(&pxa27x_ssp_driver); + if (ret) { + printk(KERN_ERR "failed to register pxa27x_ssp_driver"); + return ret; } - pxa_set_cken(ssp_info[dev->port-1].clock, 0); - if (dev->irq) - free_irq(dev->irq, dev); - release_mem_region(__PREG(SSCR0_P(dev->port)), 0x2c); - use_count[dev->port - 1]--; - mutex_unlock(&mutex); + return ret; +} + +static void __exit pxa_ssp_exit(void) +{ + platform_driver_unregister(&pxa25x_ssp_driver); + platform_driver_unregister(&pxa25x_nssp_driver); + platform_driver_unregister(&pxa27x_ssp_driver); } +arch_initcall(pxa_ssp_init); +module_exit(pxa_ssp_exit); + EXPORT_SYMBOL(ssp_write_word); EXPORT_SYMBOL(ssp_read_word); EXPORT_SYMBOL(ssp_flush); diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S index d774430..167412e 100644 --- a/arch/arm/mach-pxa/standby.S +++ b/arch/arm/mach-pxa/standby.S @@ -17,6 +17,7 @@ .text +#ifdef CONFIG_PXA27x ENTRY(pxa_cpu_standby) ldr r0, =PSSR mov r1, #(PSSR_PH | PSSR_STS) @@ -29,3 +30,85 @@ ENTRY(pxa_cpu_standby) 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby str r1, [r0] @ make sure PSSR_PH/STS are clear mov pc, lr + +#endif + +#ifdef CONFIG_PXA3xx + +#define MDCNFG 0x0000 +#define MDCNFG_DMCEN (1 << 30) +#define DDR_HCAL 0x0060 +#define DDR_HCAL_HCRNG 0x1f +#define DDR_HCAL_HCPROG (1 << 28) +#define DDR_HCAL_HCEN (1 << 31) +#define DMCIER 0x0070 +#define DMCIER_EDLP (1 << 29) +#define DMCISR 0x0078 +#define RCOMP 0x0100 +#define RCOMP_SWEVAL (1 << 31) + +ENTRY(pm_enter_standby_start) + mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG) + add r1, r1, #0x00100000 + + /* + * Preload the TLB entry for accessing the dynamic memory + * controller registers. Note that page table lookups will + * fail until the dynamic memory controller has been + * reinitialised - and that includes MMU page table walks. + * This also means that only the dynamic memory controller + * can be reliably accessed in the code following standby. + */ + ldr r2, [r1] @ Dummy read MDCNFG + + mcr p14, 0, r0, c7, c0, 0 + .rept 8 + nop + .endr + + ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN + bic r0, r0, #DDR_HCAL_HCEN + str r0, [r1, #DDR_HCAL] +1: ldr r0, [r1, #DDR_HCAL] + tst r0, #DDR_HCAL_HCEN + bne 1b + + ldr r0, [r1, #RCOMP] @ Initiate RCOMP + orr r0, r0, #RCOMP_SWEVAL + str r0, [r1, #RCOMP] + + mov r0, #~0 @ Clear interrupts + str r0, [r1, #DMCISR] + + ldr r0, [r1, #DMCIER] @ set DMIER[EDLP] + orr r0, r0, #DMCIER_EDLP + str r0, [r1, #DMCIER] + + ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN + bic r0, r0, #DDR_HCAL_HCRNG + orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG + str r0, [r1, #DDR_HCAL] + +1: ldr r0, [r1, #DMCISR] + tst r0, #DMCIER_EDLP + beq 1b + + ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN] + orr r0, r0, #MDCNFG_DMCEN + str r0, [r1, #MDCNFG] +1: ldr r0, [r1, #MDCNFG] + tst r0, #MDCNFG_DMCEN + beq 1b + + ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG] + orr r0, r0, #2 @ HCRNG + str r0, [r1, #DDR_HCAL] + + ldr r0, [r1, #DMCIER] @ Clear the interrupt + bic r0, r0, #0x20000000 + str r0, [r1, #DMCIER] + + mov pc, lr +ENTRY(pm_enter_standby_end) + +#endif diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index fbfa192..ac0bbad 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -59,55 +59,17 @@ unsigned long long sched_clock(void) } +#define MIN_OSCR_DELTA 16 + static irqreturn_t pxa_ost0_interrupt(int irq, void *dev_id) { - int next_match; struct clock_event_device *c = dev_id; - if (c->mode == CLOCK_EVT_MODE_ONESHOT) { - /* Disarm the compare/match, signal the event. */ - OIER &= ~OIER_E0; - OSSR = OSSR_M0; - c->event_handler(c); - } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) { - /* Call the event handler as many times as necessary - * to recover missed events, if any (if we update - * OSMR0 and OSCR0 is still ahead of us, we've missed - * the event). As we're dealing with that, re-arm the - * compare/match for the next event. - * - * HACK ALERT: - * - * There's a latency between the instruction that - * writes to OSMR0 and the actual commit to the - * physical hardware, because the CPU doesn't (have - * to) run at bus speed, there's a write buffer - * between the CPU and the bus, etc. etc. So if the - * target OSCR0 is "very close", to the OSMR0 load - * value, the update to OSMR0 might not get to the - * hardware in time and we'll miss that interrupt. - * - * To be safe, if the new OSMR0 is "very close" to the - * target OSCR0 value, we call the event_handler as - * though the event actually happened. According to - * Nico's comment in the previous version of this - * code, experience has shown that 6 OSCR ticks is - * "very close" but he went with 8. We will use 16, - * based on the results of testing on PXA270. - * - * To be doubly sure, we also tell clkevt via - * clockevents_register_device() not to ask for - * anything that might put us "very close". - */ -#define MIN_OSCR_DELTA 16 - do { - OSSR = OSSR_M0; - next_match = (OSMR0 += LATCH); - c->event_handler(c); - } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA) - && (c->mode == CLOCK_EVT_MODE_PERIODIC)); - } + /* Disarm the compare/match, signal the event. */ + OIER &= ~OIER_E0; + OSSR = OSSR_M0; + c->event_handler(c); return IRQ_HANDLED; } @@ -133,14 +95,6 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) unsigned long irqflags; switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - raw_local_irq_save(irqflags); - OSSR = OSSR_M0; - OIER |= OIER_E0; - OSMR0 = OSCR + LATCH; - raw_local_irq_restore(irqflags); - break; - case CLOCK_EVT_MODE_ONESHOT: raw_local_irq_save(irqflags); OIER &= ~OIER_E0; @@ -158,13 +112,14 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) break; case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_PERIODIC: break; } } static struct clock_event_device ckevt_pxa_osmr0 = { .name = "osmr0", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .features = CLOCK_EVT_FEAT_ONESHOT, .shift = 32, .rating = 200, .cpumask = CPU_MASK_CPU0, @@ -226,7 +181,7 @@ static void __init pxa_timer_init(void) } #ifdef CONFIG_PM -static unsigned long osmr[4], oier; +static unsigned long osmr[4], oier, oscr; static void pxa_timer_suspend(void) { @@ -235,23 +190,26 @@ static void pxa_timer_suspend(void) osmr[2] = OSMR2; osmr[3] = OSMR3; oier = OIER; + oscr = OSCR; } static void pxa_timer_resume(void) { + /* + * Ensure that we have at least MIN_OSCR_DELTA between match + * register 0 and the OSCR, to guarantee that we will receive + * the one-shot timer interrupt. We adjust OSMR0 in preference + * to OSCR to guarantee that OSCR is monotonically incrementing. + */ + if (osmr[0] - oscr < MIN_OSCR_DELTA) + osmr[0] += MIN_OSCR_DELTA; + OSMR0 = osmr[0]; OSMR1 = osmr[1]; OSMR2 = osmr[2]; OSMR3 = osmr[3]; OIER = oier; - - /* - * OSCR0 is the system timer, which has to increase - * monotonically until it rolls over in hardware. The value - * (OSMR0 - LATCH) is OSCR0 at the most recent system tick, - * which is a handy value to restore to OSCR0. - */ - OSCR = OSMR0 - LATCH; + OSCR = oscr; } #else #define pxa_timer_suspend NULL diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 743a87b..7731d50 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -25,9 +25,13 @@ #include #include #include +#include #include "generic.h" +#define MAX_SLOTS 3 +struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS]; + int gpio_backlight; int gpio_eth_irq; @@ -43,7 +47,7 @@ static struct resource smc91x_resources[] = { [1] = { .start = -1, /* for run-time assignment */ .end = -1, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; @@ -156,6 +160,95 @@ static void __init zylonite_init_lcd(void) static inline void zylonite_init_lcd(void) {} #endif +#if defined(CONFIG_MMC) +static int zylonite_mci_ro(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + return gpio_get_value(zylonite_mmc_slot[pdev->id].gpio_wp); +} + +static int zylonite_mci_init(struct device *dev, + irq_handler_t zylonite_detect_int, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + int err, cd_irq, gpio_cd, gpio_wp; + + cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd); + gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd; + gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp; + + /* + * setup GPIO for Zylonite MMC controller + */ + err = gpio_request(gpio_cd, "mmc card detect"); + if (err) + goto err_request_cd; + gpio_direction_input(gpio_cd); + + err = gpio_request(gpio_wp, "mmc write protect"); + if (err) + goto err_request_wp; + gpio_direction_input(gpio_wp); + + err = request_irq(cd_irq, zylonite_detect_int, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "MMC card detect", data); + if (err) { + printk(KERN_ERR "%s: MMC/SD/SDIO: " + "can't request card detect IRQ\n", __func__); + goto err_request_irq; + } + + return 0; + +err_request_irq: + gpio_free(gpio_wp); +err_request_wp: + gpio_free(gpio_cd); +err_request_cd: + return err; +} + +static void zylonite_mci_exit(struct device *dev, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + int cd_irq, gpio_cd, gpio_wp; + + cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd); + gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd; + gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp; + + free_irq(cd_irq, data); + gpio_free(gpio_cd); + gpio_free(gpio_wp); +} + +static struct pxamci_platform_data zylonite_mci_platform_data = { + .detect_delay = 20, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = zylonite_mci_init, + .exit = zylonite_mci_exit, + .get_ro = zylonite_mci_ro, +}; + +static struct pxamci_platform_data zylonite_mci2_platform_data = { + .detect_delay = 20, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, +}; + +static void __init zylonite_init_mmc(void) +{ + pxa_set_mci_info(&zylonite_mci_platform_data); + pxa3xx_set_mci2_info(&zylonite_mci2_platform_data); + if (cpu_is_pxa310()) + pxa3xx_set_mci3_info(&zylonite_mci_platform_data); +} +#else +static inline void zylonite_init_mmc(void) {} +#endif + static void __init zylonite_init(void) { /* board-processor specific initialization */ @@ -171,6 +264,7 @@ static void __init zylonite_init(void) platform_device_register(&smc91x_device); zylonite_init_lcd(); + zylonite_init_mmc(); } MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 1832bc3..6ac04c0 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -53,13 +53,13 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = { /* BTUART */ GPIO111_UART2_RTS, - GPIO112_UART2_RXD, + GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL, GPIO113_UART2_TXD, - GPIO114_UART2_CTS, + GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH, /* STUART */ GPIO109_UART3_TXD, - GPIO110_UART3_RXD, + GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL, /* AC97 */ GPIO23_AC97_nACRESET, @@ -70,16 +70,16 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = { GPIO28_AC97_SYNC, /* Keypad */ - GPIO107_KP_DKIN_0, - GPIO108_KP_DKIN_1, - GPIO115_KP_MKIN_0, - GPIO116_KP_MKIN_1, - GPIO117_KP_MKIN_2, - GPIO118_KP_MKIN_3, - GPIO119_KP_MKIN_4, - GPIO120_KP_MKIN_5, - GPIO2_2_KP_MKIN_6, - GPIO3_2_KP_MKIN_7, + GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH, + GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH, + GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH, + GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH, + GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH, + GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH, + GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH, + GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH, + GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH, + GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH, GPIO121_KP_MKOUT_0, GPIO122_KP_MKOUT_1, GPIO123_KP_MKOUT_2, @@ -88,16 +88,33 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = { GPIO4_2_KP_MKOUT_5, GPIO5_2_KP_MKOUT_6, GPIO6_2_KP_MKOUT_7, + + /* MMC1 */ + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO7_MMC1_CLK, + GPIO8_MMC1_CMD, /* CMD0 for slot 0 */ + GPIO15_GPIO, /* CMD1 default as GPIO for slot 0 */ + + /* MMC2 */ + GPIO9_MMC2_DAT0, + GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH, + GPIO11_MMC2_DAT2, + GPIO12_MMC2_DAT3, + GPIO13_MMC2_CLK, + GPIO14_MMC2_CMD, }; static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { /* FFUART */ - GPIO30_UART1_RXD, + GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL, GPIO31_UART1_TXD, GPIO32_UART1_CTS, GPIO37_UART1_RTS, GPIO33_UART1_DCD, - GPIO34_UART1_DSR, + GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL, GPIO35_UART1_RI, GPIO36_UART1_DTR, @@ -108,7 +125,7 @@ static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { static mfp_cfg_t pxa310_mfp_cfg[] __initdata = { /* FFUART */ - GPIO99_UART1_RXD, + GPIO99_UART1_RXD | MFP_LPM_EDGE_FALL, GPIO100_UART1_TXD, GPIO101_UART1_CTS, GPIO106_UART1_RTS, @@ -116,6 +133,14 @@ static mfp_cfg_t pxa310_mfp_cfg[] __initdata = { /* Ethernet */ GPIO2_nCS3, GPIO102_GPIO, + + /* MMC3 */ + GPIO7_2_MMC3_DAT0, + GPIO8_2_MMC3_DAT1 | MFP_LPM_EDGE_BOTH, + GPIO9_2_MMC3_DAT2, + GPIO10_2_MMC3_DAT3, + GPIO103_MMC3_CLK, + GPIO105_MMC3_CMD, }; #define NUM_LCD_DETECT_PINS 7 @@ -174,6 +199,10 @@ void __init zylonite_pxa300_init(void) /* GPIO pin assignment */ gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20); + + /* MMC card detect & write protect for controller 0 */ + zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0); + zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2); } if (cpu_is_pxa300()) { @@ -184,5 +213,9 @@ void __init zylonite_pxa300_init(void) if (cpu_is_pxa310()) { pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg)); gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102); + + /* MMC card detect & write protect for controller 2 */ + zylonite_mmc_slot[2].gpio_cd = EXT_GPIO(30); + zylonite_mmc_slot[2].gpio_wp = EXT_GPIO(31); } } diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 94c7158..dfa7999 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -51,11 +51,11 @@ static mfp_cfg_t mfp_cfg[] __initdata = { GPIO17_2_LCD_BIAS, /* FFUART */ - GPIO41_UART1_RXD, + GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL, GPIO42_UART1_TXD, GPIO43_UART1_CTS, GPIO44_UART1_DCD, - GPIO45_UART1_DSR, + GPIO45_UART1_DSR | MFP_LPM_EDGE_FALL, GPIO46_UART1_RI, GPIO47_UART1_DTR, GPIO48_UART1_RTS, @@ -73,16 +73,16 @@ static mfp_cfg_t mfp_cfg[] __initdata = { GPIO33_I2C_SDA, /* Keypad */ - GPIO105_KP_DKIN_0, - GPIO106_KP_DKIN_1, - GPIO113_KP_MKIN_0, - GPIO114_KP_MKIN_1, - GPIO115_KP_MKIN_2, - GPIO116_KP_MKIN_3, - GPIO117_KP_MKIN_4, - GPIO118_KP_MKIN_5, - GPIO119_KP_MKIN_6, - GPIO120_KP_MKIN_7, + GPIO105_KP_DKIN_0 | MFP_LPM_EDGE_BOTH, + GPIO106_KP_DKIN_1 | MFP_LPM_EDGE_BOTH, + GPIO113_KP_MKIN_0 | MFP_LPM_EDGE_BOTH, + GPIO114_KP_MKIN_1 | MFP_LPM_EDGE_BOTH, + GPIO115_KP_MKIN_2 | MFP_LPM_EDGE_BOTH, + GPIO116_KP_MKIN_3 | MFP_LPM_EDGE_BOTH, + GPIO117_KP_MKIN_4 | MFP_LPM_EDGE_BOTH, + GPIO118_KP_MKIN_5 | MFP_LPM_EDGE_BOTH, + GPIO119_KP_MKIN_6 | MFP_LPM_EDGE_BOTH, + GPIO120_KP_MKIN_7 | MFP_LPM_EDGE_BOTH, GPIO121_KP_MKOUT_0, GPIO122_KP_MKOUT_1, GPIO123_KP_MKOUT_2, @@ -95,6 +95,23 @@ static mfp_cfg_t mfp_cfg[] __initdata = { /* Ethernet */ GPIO4_nCS3, GPIO90_GPIO, + + /* MMC1 */ + GPIO18_MMC1_DAT0, + GPIO19_MMC1_DAT1 | MFP_LPM_EDGE_BOTH, + GPIO20_MMC1_DAT2, + GPIO21_MMC1_DAT3, + GPIO22_MMC1_CLK, + GPIO23_MMC1_CMD,/* CMD0 for slot 0 */ + GPIO31_GPIO, /* CMD1 default as GPIO for slot 0 */ + + /* MMC2 */ + GPIO24_MMC2_DAT0, + GPIO25_MMC2_DAT1 | MFP_LPM_EDGE_BOTH, + GPIO26_MMC2_DAT2, + GPIO27_MMC2_DAT3, + GPIO28_MMC2_CLK, + GPIO29_MMC2_CMD, }; #define NUM_LCD_DETECT_PINS 7 @@ -169,5 +186,9 @@ void __init zylonite_pxa320_init(void) /* GPIO pin assignment */ gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14); gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9); + + /* MMC card detect & write protect for controller 0 */ + zylonite_mmc_slot[0].gpio_cd = mfp_to_gpio(MFP_PIN_GPIO1); + zylonite_mmc_slot[0].gpio_wp = mfp_to_gpio(MFP_PIN_GPIO5); } } diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 35156ca..39b3bb7 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -7,24 +7,21 @@ config MACH_REALVIEW_EB help Include support for the ARM(R) RealView Emulation Baseboard platform. -config REALVIEW_MPCORE - bool "Support MPcore tile" +config REALVIEW_EB_ARM11MP + bool "Support ARM11MPCore tile" depends on MACH_REALVIEW_EB select CACHE_L2X0 help - Enable support for the MPCore tile on the Realview platform. - Since there are device address and interrupt differences, a - kernel built with this option enabled is not compatible with - other tiles. + Enable support for the ARM11MPCore tile on the Realview platform. -config REALVIEW_MPCORE_REVB - bool "Support MPcore RevB tile" - depends on REALVIEW_MPCORE +config REALVIEW_EB_ARM11MP_REVB + bool "Support ARM11MPCore RevB tile" + depends on REALVIEW_EB_ARM11MP default n help - Enable support for the MPCore RevB tile on the Realview platform. - Since there are device address differences, a + Enable support for the ARM11MPCore RevB tile on the Realview + platform. Since there are device address differences, a kernel built with this option enabled is not compatible with - other tiles. + other revisions of the ARM11MPCore tile. endmenu diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index 36e76ba..ca1e390 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -4,6 +4,5 @@ obj-y := core.o clock.o obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index c7f1b44..56d20d9 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include @@ -37,7 +39,6 @@ #include #include #include -#include #include #include @@ -48,6 +49,9 @@ #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) +/* used by entry-macro.S */ +void __iomem *gic_cpu_base_addr; + /* * This is the RealView sched_clock implementation. This has * a resolution of 41.7ns, and a maximum value of about 179s. @@ -121,26 +125,6 @@ struct platform_device realview_flash_device = { .resource = &realview_flash_resource, }; -static struct resource realview_smc91x_resources[] = { - [0] = { - .start = REALVIEW_ETH_BASE, - .end = REALVIEW_ETH_BASE + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_ETH, - .end = IRQ_ETH, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device realview_smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(realview_smc91x_resources), - .resource = realview_smc91x_resources, -}; - static struct resource realview_i2c_resource = { .start = REALVIEW_I2C_BASE, .end = REALVIEW_I2C_BASE + SZ_4K - 1, @@ -484,45 +468,64 @@ void realview_leds_event(led_event_t ledevt) #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) #endif -/* - * Returns number of ms since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - */ -static unsigned long realview_gettimeoffset(void) +static void timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) { - unsigned long ticks1, ticks2, status; + unsigned long ctrl; - /* - * Get the current number of ticks. Note that there is a race - * condition between us reading the timer and checking for - * an interrupt. We get around this by ensuring that the - * counter has not reloaded between our two reads. - */ - ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; - do { - ticks1 = ticks2; - status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET) - + ((IRQ_TIMERINT0_1 >> 5) << 2)); - ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; - } while (ticks2 > ticks1); + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); - /* - * Number of ticks since last interrupt. - */ - ticks1 = TIMER_RELOAD - ticks2; + ctrl = TIMER_CTRL_PERIODIC; + ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl = TIMER_CTRL_ONESHOT; + ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + } - /* - * Interrupt pending? If so, we've reloaded once already. - * - * FIXME: Need to check this is effectively timer 0 that expires - */ - if (status & IRQMASK_TIMERINT0_1) - ticks1 += TIMER_RELOAD; + writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); +} - /* - * Convert the ticks to usecs - */ - return TICKS2USECS(ticks1); +static int timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); + + writel(evt, TIMER0_VA_BASE + TIMER_LOAD); + writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); + + return 0; +} + +static struct clock_event_device timer0_clockevent = { + .name = "timer0", + .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = timer_set_mode, + .set_next_event = timer_set_next_event, + .rating = 300, + .cpumask = CPU_MASK_ALL, +}; + +static void __init realview_clockevents_init(unsigned int timer_irq) +{ + timer0_clockevent.irq = timer_irq; + timer0_clockevent.mult = + div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); + timer0_clockevent.max_delta_ns = + clockevent_delta2ns(0xffffffff, &timer0_clockevent); + timer0_clockevent.min_delta_ns = + clockevent_delta2ns(0xf, &timer0_clockevent); + + clockevents_register_device(&timer0_clockevent); } /* @@ -530,19 +533,12 @@ static unsigned long realview_gettimeoffset(void) */ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) { - write_seqlock(&xtime_lock); + struct clock_event_device *evt = &timer0_clockevent; - // ...clear the interrupt + /* clear the interrupt */ writel(1, TIMER0_VA_BASE + TIMER_INTCLR); - timer_tick(); - -#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS) - smp_send_timer(); - update_process_times(user_mode(get_irq_regs())); -#endif - - write_sequnlock(&xtime_lock); + evt->event_handler(evt); return IRQ_HANDLED; } @@ -553,13 +549,49 @@ static struct irqaction realview_timer_irq = { .handler = realview_timer_interrupt, }; +static cycle_t realview_get_cycles(void) +{ + return ~readl(TIMER3_VA_BASE + TIMER_VALUE); +} + +static struct clocksource clocksource_realview = { + .name = "timer3", + .rating = 200, + .read = realview_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init realview_clocksource_init(void) +{ + /* setup timer 0 as free-running clocksource */ + writel(0, TIMER3_VA_BASE + TIMER_CTRL); + writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); + writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); + writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, + TIMER3_VA_BASE + TIMER_CTRL); + + clocksource_realview.mult = + clocksource_khz2mult(1000, clocksource_realview.shift); + clocksource_register(&clocksource_realview); +} + /* * Set up timer interrupt, and return the current time in seconds. */ -static void __init realview_timer_init(void) +void __init realview_timer_init(unsigned int timer_irq) { u32 val; +#ifdef CONFIG_SMP + /* + * The dummy clock device has to be registered before the main device + * so that the latter will broadcast the clock events + */ + dummy_timer_setup(smp_processor_id()); +#endif + /* * set clock frequency: * REALVIEW_REFCLK is 32KHz @@ -580,18 +612,11 @@ static void __init realview_timer_init(void) writel(0, TIMER2_VA_BASE + TIMER_CTRL); writel(0, TIMER3_VA_BASE + TIMER_CTRL); - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE); - writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC | - TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL); - /* * Make irqs happen for the system timer */ - setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq); -} + setup_irq(timer_irq, &realview_timer_irq); -struct sys_timer realview_timer = { - .init = realview_timer_init, - .offset = realview_gettimeoffset, -}; + realview_clocksource_init(); + realview_clockevents_init(timer_irq); +} diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 2b53420..492a14c 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -27,8 +27,6 @@ #include #include -extern struct sys_timer realview_timer; - #define AMBA_DEVICE(name,busid,base,plat) \ static struct amba_device name##_device = { \ .dev = { \ @@ -38,7 +36,7 @@ static struct amba_device name##_device = { \ }, \ .res = { \ .start = REALVIEW_##base##_BASE, \ - .end = (REALVIEW_##base##_BASE) + SZ_4K - 1,\ + .end = (REALVIEW_##base##_BASE) + SZ_4K - 1, \ .flags = IORESOURCE_MEM, \ }, \ .dma_mask = ~0, \ @@ -46,74 +44,19 @@ static struct amba_device name##_device = { \ /* .dma = base##_DMA,*/ \ } -/* - * These devices are connected via the core APB bridge - */ -#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } -#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } - -#define AACI_IRQ { IRQ_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } -#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } -#define KMI0_IRQ { IRQ_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } -#define KMI1_IRQ { IRQ_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } - -/* - * These devices are connected directly to the multi-layer AHB switch - */ -#define SMC_IRQ { NO_IRQ, NO_IRQ } -#define SMC_DMA { 0, 0 } -#define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } -#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } -#define CLCD_DMA { 0, 0 } -#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } -#define DMAC_DMA { 0, 0 } - -/* - * These devices are connected via the core APB bridge - */ -#define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } -#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } -#define WATCHDOG_DMA { 0, 0 } -#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } -#define GPIO0_DMA { 0, 0 } -#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } -#define RTC_IRQ { IRQ_RTCINT, NO_IRQ } -#define RTC_DMA { 0, 0 } - -/* - * These devices are connected via the DMA APB bridge - */ -#define SCI_IRQ { IRQ_SCIINT, NO_IRQ } -#define SCI_DMA { 7, 6 } -#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } -#define UART0_DMA { 15, 14 } -#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } -#define UART1_DMA { 13, 12 } -#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } -#define UART2_DMA { 11, 10 } -#define UART3_IRQ { IRQ_UART3, NO_IRQ } -#define UART3_DMA { 0x86, 0x87 } -#define SSP_IRQ { IRQ_SSPINT, NO_IRQ } -#define SSP_DMA { 9, 8 } - - extern struct platform_device realview_flash_device; -extern struct platform_device realview_smc91x_device; extern struct platform_device realview_i2c_device; extern struct mmc_platform_data realview_mmc0_plat_data; extern struct mmc_platform_data realview_mmc1_plat_data; extern struct clk realview_clcd_clk; extern struct clcd_board clcd_plat_data; +extern void __iomem *gic_cpu_base_addr; +#ifdef CONFIG_LOCAL_TIMERS +extern void __iomem *twd_base_addr; +extern unsigned int twd_size; +#endif extern void realview_leds_event(led_event_t ledevt); +extern void realview_timer_init(unsigned int timer_irq); #endif diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index c7bdf04..835c2de 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -14,19 +14,75 @@ #include #include #include +#include +#include +#include -#include #include #include #include #include #include -#define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \ - ((cpu) * REALVIEW_TWD_SIZE)) +static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); + +/* + * Used on SMP for either the local timer or IPI_TIMER + */ +void local_timer_interrupt(void) +{ + struct clock_event_device *clk = &__get_cpu_var(local_clockevent); + + clk->event_handler(clk); +} + +#ifdef CONFIG_LOCAL_TIMERS + +#define TWD_BASE(cpu) (twd_base_addr + (cpu) * twd_size) + +/* set up by the platform code */ +void __iomem *twd_base_addr; +unsigned int twd_size; static unsigned long mpcore_timer_rate; +static void local_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + void __iomem *base = TWD_BASE(smp_processor_id()); + unsigned long ctrl; + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* timer load already set up */ + ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE + | TWD_TIMER_CONTROL_PERIODIC; + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + } + + __raw_writel(ctrl, base + TWD_TIMER_CONTROL); +} + +static int local_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + void __iomem *base = TWD_BASE(smp_processor_id()); + unsigned long ctrl = __raw_readl(base + TWD_TIMER_CONTROL); + + __raw_writel(evt, base + TWD_TIMER_COUNTER); + __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, base + TWD_TIMER_CONTROL); + + return 0; +} + /* * local_timer_ack: checks for a local timer interrupt. * @@ -45,12 +101,11 @@ int local_timer_ack(void) return 0; } -void __cpuinit local_timer_setup(unsigned int cpu) +static void __cpuinit twd_calibrate_rate(unsigned int cpu) { void __iomem *base = TWD_BASE(cpu); - unsigned int load, offset; + unsigned long load, count; u64 waitjiffies; - unsigned int count; /* * If this is the first time round, we need to work out how fast @@ -88,36 +143,33 @@ void __cpuinit local_timer_setup(unsigned int cpu) load = mpcore_timer_rate / HZ; __raw_writel(load, base + TWD_TIMER_LOAD); - __raw_writel(0x7, base + TWD_TIMER_CONTROL); - - /* - * Now maneuver our local tick into the right part of the jiffy. - * Start by working out where within the tick our local timer - * interrupt should go. - */ - offset = ((mpcore_timer_rate / HZ) / (NR_CPUS + 1)) * (cpu + 1); - - /* - * gettimeoffset() will return a number of us since the last tick. - * Convert this number of us to a local timer tick count. - * Be careful of integer overflow whilst keeping maximum precision. - * - * with HZ=100 and 1MHz (fpga) ~ 1GHz processor: - * load = 1 ~ 10,000 - * mpcore_timer_rate/10000 = 100 ~ 100,000 - * - * so the multiply value will be less than 10^9 always. - */ - load = (system_timer->offset() * (mpcore_timer_rate / 10000)) / 100; - - /* Add on our offset to get the load value */ - load = (load + offset) % (mpcore_timer_rate / HZ); +} - __raw_writel(load, base + TWD_TIMER_COUNTER); +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit local_timer_setup(unsigned int cpu) +{ + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + + twd_calibrate_rate(cpu); + + clk->name = "local_timer"; + clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clk->rating = 350; + clk->set_mode = local_timer_set_mode; + clk->set_next_event = local_timer_set_next_event; + clk->irq = IRQ_LOCALTIMER; + clk->cpumask = cpumask_of_cpu(cpu); + clk->shift = 20; + clk->mult = div_sc(mpcore_timer_rate, NSEC_PER_SEC, clk->shift); + clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); + clk->min_delta_ns = clockevent_delta2ns(0xf, clk); /* Make sure our local interrupt controller has this enabled */ - __raw_writel(1 << IRQ_LOCALTIMER, - __io_address(REALVIEW_GIC_DIST_BASE) + GIC_DIST_ENABLE_SET); + get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER); + + clockevents_register_device(clk); } /* @@ -127,3 +179,26 @@ void __cpuexit local_timer_stop(unsigned int cpu) { __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL); } + +#else /* CONFIG_LOCAL_TIMERS */ + +static void dummy_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ +} + +void __cpuinit dummy_timer_setup(unsigned int cpu) +{ + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + + clk->name = "dummy_timer"; + clk->features = CLOCK_EVT_FEAT_DUMMY; + clk->rating = 200; + clk->set_mode = dummy_timer_set_mode; + clk->broadcast = smp_timer_broadcast; + clk->cpumask = cpumask_of_cpu(cpu); + + clockevents_register_device(clk); +} + +#endif /* !CONFIG_LOCAL_TIMERS */ diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index fce3596..5c55bbe 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -31,9 +31,13 @@ static unsigned int __init get_core_count(void) { unsigned int ncores; - ncores = __raw_readl(__io_address(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG); + if (core_tile_eb11mp()) { + ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); + ncores = (ncores & 0x03) + 1; + } else + ncores = 1; - return (ncores & 0x03) + 1; + return ncores; } static DEFINE_SPINLOCK(boot_lock); @@ -52,7 +56,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); + gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); /* * let the primary processor know we're out of the @@ -190,7 +194,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) /* * Enable the local timer for primary CPU */ - local_timer_setup(cpu); + if (core_tile_eb11mp()) + local_timer_setup(cpu); /* * Initialise the present map, which describes the set of CPUs diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index ecec2f8..60d9eb8 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -36,7 +36,9 @@ #include #include #include +#include +#include #include #include "core.h" @@ -58,26 +60,7 @@ static struct map_desc realview_eb_io_desc[] __initdata = { .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), .length = SZ_4K, .type = MT_DEVICE, - }, -#ifdef CONFIG_REALVIEW_MPCORE - { - .virtual = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE), - .pfn = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE), - .length = SZ_4K, - .type = MT_DEVICE, }, { - .virtual = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE), - .pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(REALVIEW_MPCORE_L220_BASE), - .pfn = __phys_to_pfn(REALVIEW_MPCORE_L220_BASE), - .length = SZ_8K, - .type = MT_DEVICE, - }, -#endif - { .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), .length = SZ_4K, @@ -103,11 +86,95 @@ static struct map_desc realview_eb_io_desc[] __initdata = { #endif }; +static struct map_desc realview_eb11mp_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + } +}; + static void __init realview_eb_map_io(void) { iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); + if (core_tile_eb11mp()) + iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); } +/* + * RealView EB AMBA devices + */ + +/* + * These devices are connected via the core APB bridge + */ +#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } +#define GPIO2_DMA { 0, 0 } +#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } +#define GPIO3_DMA { 0, 0 } + +#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } +#define AACI_DMA { 0x80, 0x81 } +#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } +#define MMCI0_DMA { 0x84, 0 } +#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } +#define KMI0_DMA { 0, 0 } +#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } +#define KMI1_DMA { 0, 0 } + +/* + * These devices are connected directly to the multi-layer AHB switch + */ +#define SMC_IRQ { NO_IRQ, NO_IRQ } +#define SMC_DMA { 0, 0 } +#define MPMC_IRQ { NO_IRQ, NO_IRQ } +#define MPMC_DMA { 0, 0 } +#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } +#define CLCD_DMA { 0, 0 } +#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } +#define DMAC_DMA { 0, 0 } + +/* + * These devices are connected via the core APB bridge + */ +#define SCTL_IRQ { NO_IRQ, NO_IRQ } +#define SCTL_DMA { 0, 0 } +#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } +#define WATCHDOG_DMA { 0, 0 } +#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } +#define GPIO0_DMA { 0, 0 } +#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } +#define GPIO1_DMA { 0, 0 } +#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ } +#define RTC_DMA { 0, 0 } + +/* + * These devices are connected via the DMA APB bridge + */ +#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } +#define SCI_DMA { 7, 6 } +#define UART0_IRQ { IRQ_EB_UART0, NO_IRQ } +#define UART0_DMA { 15, 14 } +#define UART1_IRQ { IRQ_EB_UART1, NO_IRQ } +#define UART1_DMA { 13, 12 } +#define UART2_IRQ { IRQ_EB_UART2, NO_IRQ } +#define UART2_DMA { 11, 10 } +#define UART3_IRQ { IRQ_EB_UART3, NO_IRQ } +#define UART3_DMA { 0x86, 0x87 } +#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ } +#define SSP_DMA { 9, 8 } + /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); @@ -153,38 +220,127 @@ static struct amba_device *amba_devs[] __initdata = { &kmi1_device, }; +/* + * RealView EB platform devices + */ + +static struct resource realview_eb_smc91x_resources[] = { + [0] = { + .start = REALVIEW_ETH_BASE, + .end = REALVIEW_ETH_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EB_ETH, + .end = IRQ_EB_ETH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device realview_eb_smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources), + .resource = realview_eb_smc91x_resources, +}; + static void __init gic_init_irq(void) { -#ifdef CONFIG_REALVIEW_MPCORE - unsigned int pldctrl; - writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); - pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); - pldctrl |= 0x00800000; /* New irq mode */ - writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); - writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); + if (core_tile_eb11mp()) { + unsigned int pldctrl; + + /* new irq mode */ + writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); + pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); + pldctrl |= 0x00800000; + writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); + writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); + + /* core tile GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); + gic_cpu_init(0, gic_cpu_base_addr); + +#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB + /* board GIC, secondary */ + gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64); + gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE)); + gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); #endif - gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); - gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); -#if defined(CONFIG_REALVIEW_MPCORE) && !defined(CONFIG_REALVIEW_MPCORE_REVB) - gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64); - gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE)); - gic_cascade_irq(1, IRQ_EB_IRQ1); + } else { + /* board GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); + gic_cpu_init(0, gic_cpu_base_addr); + } +} + +/* + * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile + */ +static void realview_eb11mp_fixup(void) +{ + /* AMBA devices */ + dmac_device.irq[0] = IRQ_EB11MP_DMA; + uart0_device.irq[0] = IRQ_EB11MP_UART0; + uart1_device.irq[0] = IRQ_EB11MP_UART1; + uart2_device.irq[0] = IRQ_EB11MP_UART2; + uart3_device.irq[0] = IRQ_EB11MP_UART3; + clcd_device.irq[0] = IRQ_EB11MP_CLCD; + wdog_device.irq[0] = IRQ_EB11MP_WDOG; + gpio0_device.irq[0] = IRQ_EB11MP_GPIO0; + gpio1_device.irq[0] = IRQ_EB11MP_GPIO1; + gpio2_device.irq[0] = IRQ_EB11MP_GPIO2; + rtc_device.irq[0] = IRQ_EB11MP_RTC; + sci0_device.irq[0] = IRQ_EB11MP_SCI; + ssp0_device.irq[0] = IRQ_EB11MP_SSP; + aaci_device.irq[0] = IRQ_EB11MP_AACI; + mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A; + mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B; + kmi0_device.irq[0] = IRQ_EB11MP_KMI0; + kmi1_device.irq[0] = IRQ_EB11MP_KMI1; + + /* platform devices */ + realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH; + realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; +} + +static void __init realview_eb_timer_init(void) +{ + unsigned int timer_irq; + + if (core_tile_eb11mp()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); + twd_size = REALVIEW_EB11MP_TWD_SIZE; #endif + timer_irq = IRQ_EB11MP_TIMER0_1; + } else + timer_irq = IRQ_EB_TIMER0_1; + + realview_timer_init(timer_irq); } +static struct sys_timer realview_eb_timer = { + .init = realview_eb_timer_init, +}; + static void __init realview_eb_init(void) { int i; -#ifdef CONFIG_REALVIEW_MPCORE - /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled - * Bits: .... ...0 0111 1001 0000 .... .... .... */ - l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff); -#endif + if (core_tile_eb11mp()) { + realview_eb11mp_fixup(); + + /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled + * Bits: .... ...0 0111 1001 0000 .... .... .... */ + l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); + } + clk_register(&realview_clcd_clk); platform_device_register(&realview_flash_device); - platform_device_register(&realview_smc91x_device); + platform_device_register(&realview_eb_smc91x_device); platform_device_register(&realview_i2c_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { @@ -204,6 +360,6 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB") .boot_params = 0x00000100, .map_io = realview_eb_map_io, .init_irq = gic_init_irq, - .timer = &realview_timer, + .timer = &realview_eb_timer, .init_machine = realview_eb_init, MACHINE_END diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index bcd562a..6aec86a 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -60,7 +60,7 @@ usb_simtec_powercontrol(int port, int to) static irqreturn_t usb_simtec_ocirq(int irq, void *pw) { - struct s3c2410_hcd_info *info = (struct s3c2410_hcd_info *)pw; + struct s3c2410_hcd_info *info = pw; if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) { pr_debug("usb_simtec: over-current irq (oc detected)\n"); diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c index 59703c6..06206ce 100644 --- a/arch/arm/mach-sa1100/ssp.c +++ b/arch/arm/mach-sa1100/ssp.c @@ -29,9 +29,8 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id) { unsigned int status = Ser4SSSR; - if (status & SSSR_ROR) { + if (status & SSSR_ROR) printk(KERN_WARNING "SSP: receiver overrun\n"); - } Ser4SSSR = SSSR_ROR; diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index fdf7b01..7298435 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -35,23 +36,6 @@ static int sa1100_set_rtc(void) return 0; } -/* IRQs are disabled before entering here from do_gettimeofday() */ -static unsigned long sa1100_gettimeoffset (void) -{ - unsigned long ticks_to_match, elapsed, usec; - - /* Get ticks before next timer match */ - ticks_to_match = OSMR0 - OSCR; - - /* We need elapsed ticks since last match */ - elapsed = LATCH - ticks_to_match; - - /* Now convert them to usec */ - usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH; - - return usec; -} - #ifdef CONFIG_NO_IDLE_HZ static unsigned long initial_match; static int match_posponed; @@ -96,6 +80,20 @@ static struct irqaction sa1100_timer_irq = { .handler = sa1100_timer_interrupt, }; +static cycle_t sa1100_read_oscr(void) +{ + return OSCR; +} + +static struct clocksource cksrc_sa1100_oscr = { + .name = "oscr", + .rating = 200, + .read = sa1100_read_oscr, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + static void __init sa1100_timer_init(void) { unsigned long flags; @@ -109,6 +107,11 @@ static void __init sa1100_timer_init(void) OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ OSMR0 = OSCR + LATCH; /* set initial match */ local_irq_restore(flags); + + cksrc_sa1100_oscr.mult = + clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift); + + clocksource_register(&cksrc_sa1100_oscr); } #ifdef CONFIG_NO_IDLE_HZ @@ -182,7 +185,6 @@ struct sys_timer sa1100_timer = { .init = sa1100_timer_init, .suspend = sa1100_timer_suspend, .resume = sa1100_timer_resume, - .offset = sa1100_gettimeoffset, #ifdef CONFIG_NO_IDLE_HZ .dyn_tick = &sa1100_dyn_tick, #endif diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7868f4d..35fb9fd 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -342,11 +342,33 @@ config CPU_XSC3 select CPU_TLB_V4WBI if MMU select IO_36 +# Feroceon +config CPU_FEROCEON + bool + depends on ARCH_ORION + default y + select CPU_32v5 + select CPU_ABRT_EV5T + select CPU_CACHE_VIVT + select CPU_CP15_MMU + select CPU_COPY_V4WB if MMU + select CPU_TLB_V4WBI if MMU + +config CPU_FEROCEON_OLD_ID + bool "Accept early Feroceon cores with an ARM926 ID" + depends on CPU_FEROCEON && !CPU_ARM926T + default y + help + This enables the usage of some old Feroceon cores + for which the CPU ID is equal to the ARM926 ID. + Relevant for Feroceon-1850 and early Feroceon-2850. + # ARMv6 config CPU_V6 bool "Support ARM V6 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 + depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A default y if ARCH_MX3 + default y if ARCH_MSM7X00A select CPU_32v6 select CPU_ABRT_EV6 select CPU_CACHE_V6 @@ -538,7 +560,7 @@ comment "Processor Features" config ARM_THUMB bool "Support Thumb user binaries" - depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON default y help Say Y if you want to include kernel support for running user space @@ -600,7 +622,7 @@ config CPU_DCACHE_SIZE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 7627027..44536a0 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_CPU_SA110) += proc-sa110.o obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o +obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V7) += proc-v7.o diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S new file mode 100644 index 0000000..fa0dc7e --- /dev/null +++ b/arch/arm/mm/proc-feroceon.S @@ -0,0 +1,506 @@ +/* + * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon + * + * Heavily based on proc-arm926.S + * Maintainer: Assaf Hoffman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "proc-macros.S" + +/* + * This is the maximum size of an area which will be invalidated + * using the single invalidate entry instructions. Anything larger + * than this, and we go for the whole cache. + * + * This value should be chosen such that we choose the cheapest + * alternative. + */ +#define CACHE_DLIMIT 16384 + +/* + * the cache line size of the I and D cache + */ +#define CACHE_DLINESIZE 32 + + .text +/* + * cpu_feroceon_proc_init() + */ +ENTRY(cpu_feroceon_proc_init) + mov pc, lr + +/* + * cpu_feroceon_proc_fin() + */ +ENTRY(cpu_feroceon_proc_fin) + stmfd sp!, {lr} + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + msr cpsr_c, ip + bl feroceon_flush_kern_cache_all + mrc p15, 0, r0, c1, c0, 0 @ ctrl register + bic r0, r0, #0x1000 @ ...i............ + bic r0, r0, #0x000e @ ............wca. + mcr p15, 0, r0, c1, c0, 0 @ disable caches + ldmfd sp!, {pc} + +/* + * cpu_feroceon_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the + * same state as it would be if it had been reset, and branch + * to what would be the reset vector. + * + * loc: location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_feroceon_reset) + mov ip, #0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches + mcr p15, 0, ip, c7, c10, 4 @ drain WB +#ifdef CONFIG_MMU + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs +#endif + mrc p15, 0, ip, c1, c0, 0 @ ctrl register + bic ip, ip, #0x000f @ ............wcam + bic ip, ip, #0x1100 @ ...i...s........ + mcr p15, 0, ip, c1, c0, 0 @ ctrl register + mov pc, r0 + +/* + * cpu_feroceon_do_idle() + * + * Called with IRQs disabled + */ + .align 10 +ENTRY(cpu_feroceon_do_idle) + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer + mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt + mov pc, lr + +/* + * flush_user_cache_all() + * + * Clean and invalidate all cache entries in a particular + * address space. + */ +ENTRY(feroceon_flush_user_cache_all) + /* FALLTHROUGH */ + +/* + * flush_kern_cache_all() + * + * Clean and invalidate the entire cache. + */ +ENTRY(feroceon_flush_kern_cache_all) + mov r2, #VM_EXEC + mov ip, #0 +__flush_whole_cache: +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache +#else +1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate + bne 1b +#endif + tst r2, #VM_EXEC + mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcrne p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * flush_user_cache_range(start, end, flags) + * + * Clean and invalidate a range of cache entries in the + * specified address range. + * + * - start - start address (inclusive) + * - end - end address (exclusive) + * - flags - vm_flags describing address space + */ +ENTRY(feroceon_flush_user_cache_range) + mov ip, #0 + sub r3, r1, r0 @ calculate total size + cmp r3, #CACHE_DLIMIT + bgt __flush_whole_cache +1: tst r2, #VM_EXEC +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE +#else + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE +#endif + cmp r0, r1 + blo 1b + tst r2, #VM_EXEC + mcrne p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * coherent_kern_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(feroceon_coherent_kern_range) + /* FALLTHROUGH */ + +/* + * coherent_user_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(feroceon_coherent_user_range) + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * flush_kern_dcache_page(void *page) + * + * Ensure no D cache aliasing occurs, either with itself or + * the I cache + * + * - addr - page aligned address + */ +ENTRY(feroceon_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ +1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_inv_range(start, end) + * + * Invalidate (discard) the specified virtual address range. + * May not write back any entries. If 'start' or 'end' + * are not cache line aligned, those lines must be written + * back. + * + * - start - virtual start address + * - end - virtual end address + * + * (same as v4wb) + */ +ENTRY(feroceon_dma_inv_range) +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + tst r0, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r0, c7, c10, 1 @ clean D entry + tst r1, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r1, c7, c10, 1 @ clean D entry +#endif + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_clean_range(start, end) + * + * Clean the specified virtual address range. + * + * - start - virtual start address + * - end - virtual end address + * + * (same as v4wb) + */ +ENTRY(feroceon_dma_clean_range) +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b +#endif + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_flush_range(start, end) + * + * Clean and invalidate the specified virtual address range. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(feroceon_dma_flush_range) + bic r0, r0, #CACHE_DLINESIZE - 1 +1: +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry +#else + mcr p15, 0, r0, c7, c10, 1 @ clean D entry +#endif + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +ENTRY(feroceon_cache_fns) + .long feroceon_flush_kern_cache_all + .long feroceon_flush_user_cache_all + .long feroceon_flush_user_cache_range + .long feroceon_coherent_kern_range + .long feroceon_coherent_user_range + .long feroceon_flush_kern_dcache_page + .long feroceon_dma_inv_range + .long feroceon_dma_clean_range + .long feroceon_dma_flush_range + +ENTRY(cpu_feroceon_dcache_clean_area) +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHE_DLINESIZE + subs r1, r1, #CACHE_DLINESIZE + bhi 1b +#endif + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* =============================== PageTable ============================== */ + +/* + * cpu_feroceon_switch_mm(pgd) + * + * Set the translation base pointer to be as described by pgd. + * + * pgd: new page tables + */ + .align 5 +ENTRY(cpu_feroceon_switch_mm) +#ifdef CONFIG_MMU + mov ip, #0 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache +#else +@ && 'Clean & Invalidate whole DCache' +1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate + bne 1b +#endif + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c2, c0, 0 @ load page table pointer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs +#endif + mov pc, lr + +/* + * cpu_feroceon_set_pte_ext(ptep, pte, ext) + * + * Set a PTE and flush it out + */ + .align 5 +ENTRY(cpu_feroceon_set_pte_ext) +#ifdef CONFIG_MMU + str r1, [r0], #-2048 @ linux version + + eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY + + bic r2, r1, #PTE_SMALL_AP_MASK + bic r2, r2, #PTE_TYPE_MASK + orr r2, r2, #PTE_TYPE_SMALL + + tst r1, #L_PTE_USER @ User? + orrne r2, r2, #PTE_SMALL_AP_URO_SRW + + tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? + orreq r2, r2, #PTE_SMALL_AP_UNO_SRW + + tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? + movne r2, #0 + +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + eor r3, r2, #0x0a @ C & small page? + tst r3, #0x0b + biceq r2, r2, #4 +#endif + str r2, [r0] @ hardware version + mov r0, r0 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, r0, c7, c10, 1 @ clean D entry +#endif + mcr p15, 0, r0, c7, c10, 4 @ drain WB +#endif + mov pc, lr + + __INIT + + .type __feroceon_setup, #function +__feroceon_setup: + mov r0, #0 + mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 +#ifdef CONFIG_MMU + mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 +#endif + + +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mov r0, #4 @ disable write-back on caches explicitly + mcr p15, 7, r0, c15, c0, 0 +#endif + + adr r5, feroceon_crval + ldmia r5, {r5, r6} + mrc p15, 0, r0, c1, c0 @ get control register v4 + bic r0, r0, r5 + orr r0, r0, r6 +#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN + orr r0, r0, #0x4000 @ .1.. .... .... .... +#endif + mov pc, lr + .size __feroceon_setup, . - __feroceon_setup + + /* + * R + * .RVI ZFRS BLDP WCAM + * .011 0001 ..11 0101 + * + */ + .type feroceon_crval, #object +feroceon_crval: + crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134 + + __INITDATA + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + .type feroceon_processor_functions, #object +feroceon_processor_functions: + .word v5t_early_abort + .word cpu_feroceon_proc_init + .word cpu_feroceon_proc_fin + .word cpu_feroceon_reset + .word cpu_feroceon_do_idle + .word cpu_feroceon_dcache_clean_area + .word cpu_feroceon_switch_mm + .word cpu_feroceon_set_pte_ext + .size feroceon_processor_functions, . - feroceon_processor_functions + + .section ".rodata" + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv5te" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v5" + .size cpu_elf_name, . - cpu_elf_name + + .type cpu_feroceon_name, #object +cpu_feroceon_name: + .asciz "Feroceon" + .size cpu_feroceon_name, . - cpu_feroceon_name + + .align + + .section ".proc.info.init", #alloc, #execinstr + +#ifdef CONFIG_CPU_FEROCEON_OLD_ID + .type __feroceon_old_id_proc_info,#object +__feroceon_old_id_proc_info: + .long 0x41069260 + .long 0xfffffff0 + .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + b __feroceon_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_feroceon_name + .long feroceon_processor_functions + .long v4wbi_tlb_fns + .long v4wb_user_fns + .long feroceon_cache_fns + .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info +#endif + + .type __feroceon_proc_info,#object +__feroceon_proc_info: + .long 0x56055310 + .long 0xfffffff0 + .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + b __feroceon_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_feroceon_name + .long feroceon_processor_functions + .long v4wbi_tlb_fns + .long v4wb_user_fns + .long feroceon_cache_fns + .size __feroceon_proc_info, . - __feroceon_proc_info diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c index 83a5f8b..f455233 100644 --- a/arch/arm/plat-omap/debug-devices.c +++ b/arch/arm/plat-omap/debug-devices.c @@ -29,7 +29,7 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index 0360b1f..45a77df 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -212,7 +212,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox) static irqreturn_t mbox_interrupt(int irq, void *p) { - struct omap_mbox *mbox = (struct omap_mbox *)p; + struct omap_mbox *mbox = p; if (is_mbox_irq(mbox, IRQ_TX)) __mbox_tx_interrupt(mbox); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index f7b9ccd..2af5bd5 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -98,9 +98,10 @@ static void omap_mcbsp_dump_reg(u8 id) static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) { - struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id); + struct omap_mcbsp *mcbsp_tx = dev_id; - DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2)); + DBG("TX IRQ callback : 0x%x\n", + OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2)); complete(&mcbsp_tx->tx_irq_completion); return IRQ_HANDLED; @@ -108,9 +109,10 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) { - struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id); + struct omap_mcbsp *mcbsp_rx = dev_id; - DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2)); + DBG("RX IRQ callback : 0x%x\n", + OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2)); complete(&mcbsp_rx->rx_irq_completion); return IRQ_HANDLED; @@ -118,9 +120,10 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data) { - struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data); + struct omap_mcbsp *mcbsp_dma_tx = data; - DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2)); + DBG("TX DMA callback : 0x%x\n", + OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2)); /* We can free the channels */ omap_free_dma(mcbsp_dma_tx->dma_tx_lch); @@ -131,9 +134,10 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data) static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data) { - struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data); + struct omap_mcbsp *mcbsp_dma_rx = data; - DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2)); + DBG("RX DMA callback : 0x%x\n", + OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2)); /* We can free the channels */ omap_free_dma(mcbsp_dma_rx->dma_rx_lch); diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 0a9a5e7..6a81366 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Fri May 11 19:53:41 2007 +# Last update: Tue Jan 1 10:57:48 2008 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -266,7 +266,7 @@ stork_egg ARCH_STORK_EGG STORK_EGG 248 wismo SA1100_WISMO WISMO 249 ezlinx ARCH_EZLINX EZLINX 250 at91rm9200 ARCH_AT91RM9200 AT91RM9200 251 -orion ARCH_ORION ORION 252 +adtech_orion ARCH_ADTECH_ORION ADTECH_ORION 252 neptune ARCH_NEPTUNE NEPTUNE 253 hackkit SA1100_HACKKIT HACKKIT 254 pxa_wins30 ARCH_PXA_WINS30 PXA_WINS30 255 @@ -661,7 +661,6 @@ a9200ec MACH_A9200EC A9200EC 645 pnx0105 MACH_PNX0105 PNX0105 646 adcpoecpu MACH_ADCPOECPU ADCPOECPU 647 csb637 MACH_CSB637 CSB637 648 -ml69q6203 MACH_ML69Q6203 ML69Q6203 649 mb9200 MACH_MB9200 MB9200 650 kulun MACH_KULUN KULUN 651 snapper MACH_SNAPPER SNAPPER 652 @@ -953,7 +952,6 @@ fred_jack MACH_FRED_JACK FRED_JACK 939 ttg_color1 MACH_TTG_COLOR1 TTG_COLOR1 940 nxeb500hmi MACH_NXEB500HMI NXEB500HMI 941 netdcu8 MACH_NETDCU8 NETDCU8 942 -ml675050_cpu_boa MACH_ML675050_CPU_BOA ML675050_CPU_BOA 943 ng_fvx538 MACH_NG_FVX538 NG_FVX538 944 ng_fvs338 MACH_NG_FVS338 NG_FVS338 945 pnx4103 MACH_PNX4103 PNX4103 946 @@ -1148,7 +1146,7 @@ aidx270 MACH_AIDX270 AIDX270 1134 rema MACH_REMA REMA 1135 bps1000 MACH_BPS1000 BPS1000 1136 hw90350 MACH_HW90350 HW90350 1137 -omap_sdp3430 MACH_OMAP_SDP3430 OMAP_SDP3430 1138 +omap_3430sdp MACH_OMAP_3430SDP OMAP_3430SDP 1138 bluetouch MACH_BLUETOUCH BLUETOUCH 1139 vstms MACH_VSTMS VSTMS 1140 xsbase270 MACH_XSBASE270 XSBASE270 1141 @@ -1214,7 +1212,7 @@ osstbox MACH_OSSTBOX OSSTBOX 1203 kbat9261 MACH_KBAT9261 KBAT9261 1204 ct1100 MACH_CT1100 CT1100 1205 akcppxa MACH_AKCPPXA AKCPPXA 1206 -zevio_1020 MACH_ZEVIO_1020 ZEVIO_1020 1207 +ochaya1020 MACH_OCHAYA1020 OCHAYA1020 1207 hitrack MACH_HITRACK HITRACK 1208 syme1 MACH_SYME1 SYME1 1209 syhl1 MACH_SYHL1 SYHL1 1210 @@ -1299,7 +1297,7 @@ xp179 MACH_XP179 XP179 1290 h4300 MACH_H4300 H4300 1291 goramo_mlr MACH_GORAMO_MLR GORAMO_MLR 1292 mxc30020evb MACH_MXC30020EVB MXC30020EVB 1293 -adsbitsymx MACH_ADSBITSIMX ADSBITSIMX 1294 +adsbitsyg5 MACH_ADSBITSYG5 ADSBITSYG5 1294 adsportalplus MACH_ADSPORTALPLUS ADSPORTALPLUS 1295 mmsp2plus MACH_MMSP2PLUS MMSP2PLUS 1296 em_x270 MACH_EM_X270 EM_X270 1297 @@ -1367,3 +1365,230 @@ db88f5281 MACH_DB88F5281 DB88F5281 1358 csb726 MACH_CSB726 CSB726 1359 tik27 MACH_TIK27 TIK27 1360 mx_uc7420 MACH_MX_UC7420 MX_UC7420 1361 +rirm3 MACH_RIRM3 RIRM3 1362 +pelco_odyssey MACH_PELCO_ODYSSEY PELCO_ODYSSEY 1363 +adx_abox MACH_ADX_ABOX ADX_ABOX 1365 +adx_tpid MACH_ADX_TPID ADX_TPID 1366 +minicheck MACH_MINICHECK MINICHECK 1367 +idam MACH_IDAM IDAM 1368 +mario_mx MACH_MARIO_MX MARIO_MX 1369 +vi1888 MACH_VI1888 VI1888 1370 +zr4230 MACH_ZR4230 ZR4230 1371 +t1_ix_blue MACH_T1_IX_BLUE T1_IX_BLUE 1372 +syhq2 MACH_SYHQ2 SYHQ2 1373 +computime_r3 MACH_COMPUTIME_R3 COMPUTIME_R3 1374 +oratis MACH_ORATIS ORATIS 1375 +mikko MACH_MIKKO MIKKO 1376 +holon MACH_HOLON HOLON 1377 +olip8 MACH_OLIP8 OLIP8 1378 +ghi270hg MACH_GHI270HG GHI270HG 1379 +davinci_dm6467_evm MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM 1380 +davinci_dm355_evm MACH_DAVINCI_DM350_EVM DAVINCI_DM350_EVM 1381 +blackriver MACH_BLACKRIVER BLACKRIVER 1383 +sandgate_wp MACH_SANDGATEWP SANDGATEWP 1384 +cdotbwsg MACH_CDOTBWSG CDOTBWSG 1385 +quark963 MACH_QUARK963 QUARK963 1386 +csb735 MACH_CSB735 CSB735 1387 +littleton MACH_LITTLETON LITTLETON 1388 +mio_p550 MACH_MIO_P550 MIO_P550 1389 +motion2440 MACH_MOTION2440 MOTION2440 1390 +imm500 MACH_IMM500 IMM500 1391 +homematic MACH_HOMEMATIC HOMEMATIC 1392 +ermine MACH_ERMINE ERMINE 1393 +kb9202b MACH_KB9202B KB9202B 1394 +hs1xx MACH_HS1XX HS1XX 1395 +studentmate2440 MACH_STUDENTMATE2440 STUDENTMATE2440 1396 +arvoo_l1_z1 MACH_ARVOO_L1_Z1 ARVOO_L1_Z1 1397 +dep2410k MACH_DEP2410K DEP2410K 1398 +xxsvideo MACH_XXSVIDEO XXSVIDEO 1399 +im4004 MACH_IM4004 IM4004 1400 +ochaya1050 MACH_OCHAYA1050 OCHAYA1050 1401 +lep9261 MACH_LEP9261 LEP9261 1402 +svenmeb MACH_SVENMEB SVENMEB 1403 +fortunet2ne MACH_FORTUNET2NE FORTUNET2NE 1404 +nxhx MACH_NXHX NXHX 1406 +realview_pb11mp MACH_REALVIEW_PB11MP REALVIEW_PB11MP 1407 +ids500 MACH_IDS500 IDS500 1408 +ors_n725 MACH_ORS_N725 ORS_N725 1409 +hsdarm MACH_HSDARM HSDARM 1410 +sha_pon003 MACH_SHA_PON003 SHA_PON003 1411 +sha_pon004 MACH_SHA_PON004 SHA_PON004 1412 +sha_pon007 MACH_SHA_PON007 SHA_PON007 1413 +sha_pon011 MACH_SHA_PON011 SHA_PON011 1414 +h6042 MACH_H6042 H6042 1415 +h6043 MACH_H6043 H6043 1416 +looxc550 MACH_LOOXC550 LOOXC550 1417 +cnty_titan MACH_CNTY_TITAN CNTY_TITAN 1418 +app3xx MACH_APP3XX APP3XX 1419 +sideoatsgrama MACH_SIDEOATSGRAMA SIDEOATSGRAMA 1420 +xscale_palmt700p MACH_XSCALE_PALMT700P XSCALE_PALMT700P 1421 +xscale_palmt700w MACH_XSCALE_PALMT700W XSCALE_PALMT700W 1422 +xscale_palmt750 MACH_XSCALE_PALMT750 XSCALE_PALMT750 1423 +xscale_palmt755p MACH_XSCALE_PALMT755P XSCALE_PALMT755P 1424 +ezreganut9200 MACH_EZREGANUT9200 EZREGANUT9200 1425 +sarge MACH_SARGE SARGE 1426 +a696 MACH_A696 A696 1427 +turtle1916 MACH_TURTLE TURTLE 1428 +mx27_3ds MACH_MX27_3DS MX27_3DS 1430 +bishop MACH_BISHOP BISHOP 1431 +pxx MACH_PXX PXX 1432 +redwood MACH_REDWOOD REDWOOD 1433 +omap_2430dlp MACH_OMAP_2430DLP OMAP_2430DLP 1436 +omap_2430osk MACH_OMAP_2430OSK OMAP_2430OSK 1437 +sardine MACH_SARDINE SARDINE 1438 +halibut MACH_HALIBUT HALIBUT 1439 +trout MACH_TROUT TROUT 1440 +goldfish MACH_GOLDFISH GOLDFISH 1441 +gesbc2440 MACH_GESBC2440 GESBC2440 1442 +nomad MACH_NOMAD NOMAD 1443 +rosalind MACH_ROSALIND ROSALIND 1444 +cc9p9215 MACH_CC9P9215 CC9P9215 1445 +cc9p9210 MACH_CC9P9210 CC9P9210 1446 +cc9p9215js MACH_CC9P9215JS CC9P9215JS 1447 +cc9p9210js MACH_CC9P9210JS CC9P9210JS 1448 +nasffe MACH_NASFFE NASFFE 1449 +tn2x0bd MACH_TN2X0BD TN2X0BD 1450 +gwmpxa MACH_GWMPXA GWMPXA 1451 +exyplus MACH_EXYPLUS EXYPLUS 1452 +jadoo21 MACH_JADOO21 JADOO21 1453 +looxn560 MACH_LOOXN560 LOOXN560 1454 +bonsai MACH_BONSAI BONSAI 1455 +adsmilgato MACH_ADSMILGATO ADSMILGATO 1456 +gba MACH_GBA GBA 1457 +h6044 MACH_H6044 H6044 1458 +app MACH_APP APP 1459 +tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 +herald MACH_HERMES HERMES 1461 +artemis MACH_ARTEMIS ARTEMIS 1462 +htctitan MACH_HTCTITAN HTCTITAN 1463 +qranium MACH_QRANIUM QRANIUM 1464 +adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465 +adx_medinet MACH_ADX_MEDINET ADX_MEDINET 1466 +bboard MACH_BBOARD BBOARD 1467 +cambria MACH_CAMBRIA CAMBRIA 1468 +mt7xxx MACH_MT7XXX MT7XXX 1469 +matrix512 MACH_MATRIX512 MATRIX512 1470 +matrix522 MACH_MATRIX522 MATRIX522 1471 +ipac5010 MACH_IPAC5010 IPAC5010 1472 +sakura MACH_SAKURA SAKURA 1473 +grocx MACH_GROCX GROCX 1474 +pm9263 MACH_PM9263 PM9263 1475 +sim_one MACH_SIM_ONE SIM_ONE 1476 +acq132 MACH_ACQ132 ACQ132 1477 +datr MACH_DATR DATR 1478 +actux1 MACH_ACTUX1 ACTUX1 1479 +actux2 MACH_ACTUX2 ACTUX2 1480 +actux3 MACH_ACTUX3 ACTUX3 1481 +flexit MACH_FLEXIT FLEXIT 1482 +bh2x0bd MACH_BH2X0BD BH2X0BD 1483 +atb2002 MACH_ATB2002 ATB2002 1484 +xenon MACH_XENON XENON 1485 +fm607 MACH_FM607 FM607 1486 +matrix514 MACH_MATRIX514 MATRIX514 1487 +matrix524 MACH_MATRIX524 MATRIX524 1488 +inpod MACH_INPOD INPOD 1489 +jive MACH_JIVE JIVE 1490 +tll_mx21 MACH_TLL_MX21 TLL_MX21 1491 +sbc2800 MACH_SBC2800 SBC2800 1492 +cc7ucamry MACH_CC7UCAMRY CC7UCAMRY 1493 +ubisys_p9_sc15 MACH_UBISYS_P9_SC15 UBISYS_P9_SC15 1494 +ubisys_p9_ssc2d10 MACH_UBISYS_P9_SSC2D10 UBISYS_P9_SSC2D10 1495 +ubisys_p9_rcu3 MACH_UBISYS_P9_RCU3 UBISYS_P9_RCU3 1496 +aml_m8000 MACH_AML_M8000 AML_M8000 1497 +snapper_270 MACH_SNAPPER_270 SNAPPER_270 1498 +omap_bbx MACH_OMAP_BBX OMAP_BBX 1499 +ucn2410 MACH_UCN2410 UCN2410 1500 +sam9_l9260 MACH_SAM9_L9260 SAM9_L9260 1501 +eti_c2 MACH_ETI_C2 ETI_C2 1502 +avalanche MACH_AVALANCHE AVALANCHE 1503 +realview_pb1176 MACH_REALVIEW_PB1176 REALVIEW_PB1176 1504 +dp1500 MACH_DP1500 DP1500 1505 +apple_iphone MACH_APPLE_IPHONE APPLE_IPHONE 1506 +yl9200 MACH_YL9200 YL9200 1507 +rd88f5182 MACH_RD88F5182 RD88F5182 1508 +kurobox_pro MACH_KUROBOX_PRO KUROBOX_PRO 1509 +se_poet MACH_SE_POET SE_POET 1510 +mx31_3ds MACH_MX31_3DS MX31_3DS 1511 +r270 MACH_R270 R270 1512 +armour21 MACH_ARMOUR21 ARMOUR21 1513 +dt2 MACH_DT2 DT2 1514 +vt4 MACH_VT4 VT4 1515 +tyco320 MACH_TYCO320 TYCO320 1516 +adma MACH_ADMA ADMA 1517 +wp188 MACH_WP188 WP188 1518 +corsica MACH_CORSICA CORSICA 1519 +bigeye MACH_BIGEYE BIGEYE 1520 +tll5000 MACH_TLL5000 TLL5000 1522 +hni270 MACH_HNI_X270 HNI_X270 1523 +qong MACH_QONG QONG 1524 +tcompact MACH_TCOMPACT TCOMPACT 1525 +puma5 MACH_PUMA5 PUMA5 1526 +elara MACH_ELARA ELARA 1527 +ellington MACH_ELLINGTON ELLINGTON 1528 +xda_atom MACH_XDA_ATOM XDA_ATOM 1529 +energizer2 MACH_ENERGIZER2 ENERGIZER2 1530 +odin MACH_ODIN ODIN 1531 +actux4 MACH_ACTUX4 ACTUX4 1532 +esl_omap MACH_ESL_OMAP ESL_OMAP 1533 +omap2evm MACH_OMAP2EVM OMAP2EVM 1534 +omap3evm MACH_OMAP3EVM OMAP3EVM 1535 +adx_pcu57 MACH_ADX_PCU57 ADX_PCU57 1536 +monaco MACH_MONACO MONACO 1537 +levante MACH_LEVANTE LEVANTE 1538 +tmxipx425 MACH_TMXIPX425 TMXIPX425 1539 +leep MACH_LEEP LEEP 1540 +raad MACH_RAAD RAAD 1541 +dns323 MACH_DNS323 DNS323 1542 +ap1000 MACH_AP1000 AP1000 1543 +a9sam6432 MACH_A9SAM6432 A9SAM6432 1544 +shiny MACH_SHINY SHINY 1545 +omap3_beagle MACH_OMAP3_BEAGLE OMAP3_BEAGLE 1546 +csr_bdb2 MACH_CSR_BDB2 CSR_BDB2 1547 +nokia_n810 MACH_NOKIA_N810 NOKIA_N810 1548 +c270 MACH_C270 C270 1549 +sentry MACH_SENTRY SENTRY 1550 +pcm038 MACH_PCM038 PCM038 1551 +anc300 MACH_ANC300 ANC300 1552 +htckaiser MACH_HTCKAISER HTCKAISER 1553 +sbat100 MACH_SBAT100 SBAT100 1554 +modunorm MACH_MODUNORM MODUNORM 1555 +pelos_twarm MACH_PELOS_TWARM PELOS_TWARM 1556 +flank MACH_FLANK FLANK 1557 +sirloin MACH_SIRLOIN SIRLOIN 1558 +brisket MACH_BRISKET BRISKET 1559 +chuck MACH_CHUCK CHUCK 1560 +otter MACH_OTTER OTTER 1561 +davinci_ldk MACH_DAVINCI_LDK DAVINCI_LDK 1562 +phreedom MACH_PHREEDOM PHREEDOM 1563 +sg310 MACH_SG310 SG310 1564 +ts_x09 MACH_TS209 TS209 1565 +at91cap9adk MACH_AT91CAP9ADK AT91CAP9ADK 1566 +tion9315 MACH_TION9315 TION9315 1567 +mast MACH_MAST MAST 1568 +pfw MACH_PFW PFW 1569 +yl_p2440 MACH_YL_P2440 YL_P2440 1570 +zsbc32 MACH_ZSBC32 ZSBC32 1571 +omap_pace2 MACH_OMAP_PACE2 OMAP_PACE2 1572 +imx_pace2 MACH_IMX_PACE2 IMX_PACE2 1573 +mx31moboard MACH_MX31MOBOARD MX31MOBOARD 1574 +mx37_3ds MACH_MX37_3DS MX37_3DS 1575 +rcc MACH_RCC RCC 1576 +dmp MACH_ARM9 ARM9 1577 +vision_ep9307 MACH_VISION_EP9307 VISION_EP9307 1578 +scly1000 MACH_SCLY1000 SCLY1000 1579 +fontel_ep MACH_FONTEL_EP FONTEL_EP 1580 +voiceblue3g MACH_VOICEBLUE3G VOICEBLUE3G 1581 +tt9200 MACH_TT9200 TT9200 1582 +digi2410 MACH_DIGI2410 DIGI2410 1583 +terastation_pro2 MACH_TERASTATION_PRO2 TERASTATION_PRO2 1584 +linkstation_pro MACH_LINKSTATION_PRO LINKSTATION_PRO 1585 +motorola_a780 MACH_MOTOROLA_A780 MOTOROLA_A780 1587 +motorola_e6 MACH_MOTOROLA_E6 MOTOROLA_E6 1588 +motorola_e2 MACH_MOTOROLA_E2 MOTOROLA_E2 1589 +motorola_e680 MACH_MOTOROLA_E680 MOTOROLA_E680 1590 +ur2410 MACH_UR2410 UR2410 1591 +tas9261 MACH_TAS9261 TAS9261 1592 +davinci_hermes_hd MACH_HERMES_HD HERMES_HD 1593 +davinci_perseo_hd MACH_PERSEO_HD PERSEO_HD 1594 +stargazer2 MACH_STARGAZER2 STARGAZER2 1595 +e350 MACH_E350 E350 1596 diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h index 791d023..c85860b 100644 --- a/arch/arm/vfp/vfp.h +++ b/arch/arm/vfp/vfp.h @@ -265,7 +265,11 @@ struct vfp_double { * which returns (double)0.0. This is useful for the compare with * zero instructions. */ +#ifdef CONFIG_VFPv3 +#define VFP_REG_ZERO 32 +#else #define VFP_REG_ZERO 16 +#endif extern u64 vfp_get_double(unsigned int reg); extern void vfp_put_double(u64 val, unsigned int reg); diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 0ac022f..353f9e5 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -99,12 +99,12 @@ vfp_support_entry: DBGSTR1 "save old state %p", r4 cmp r4, #0 beq no_old_VFP_process + VFPFSTMIA r4, r5 @ save the working registers VFPFMRX r5, FPSCR @ current status - VFPFMRX r6, FPINST @ FPINST (always there, rev0 onwards) - tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read? - VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading - @ nonexistant reg on rev0 - VFPFSTMIA r4 @ save the working registers + tst r1, #FPEXC_EX @ is there additional state to save? + VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set) + tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? + VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present) stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 @ and point r4 at the word at the @ start of the register dump @@ -114,13 +114,13 @@ no_old_VFP_process: DBGSTR1 "load state %p", r10 str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer @ Load the saved state back into the VFP - VFPFLDMIA r10 @ reload the working registers while + VFPFLDMIA r10, r5 @ reload the working registers while @ FPEXC is in a safe state ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 - tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write? - VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing - @ nonexistant reg on rev0 - VFPFMXR FPINST, r6 + tst r1, #FPEXC_EX @ is there additional state to restore? + VFPFMXR FPINST, r6, NE @ restore FPINST (only if FPEXC.EX is set) + tstne r1, #FPEXC_FP2V @ is there an FPINST2 to write? + VFPFMXR FPINST2, r8, NE @ FPINST2 if needed (and present) VFPFMXR FPSCR, r5 @ restore status check_for_exception: @@ -136,10 +136,14 @@ check_for_exception: look_for_VFP_exceptions: - tst r1, #FPEXC_EX + @ Check for synchronous or asynchronous exception + tst r1, #FPEXC_EX | FPEXC_DEX bne process_exception + @ On some implementations of the VFP subarch 1, setting FPSCR.IXE + @ causes all the CDP instructions to be bounced synchronously without + @ setting the FPEXC.EX bit VFPFMRX r5, FPSCR - tst r5, #FPSCR_IXE @ IXE doesn't set FPEXC_EX ! + tst r5, #FPSCR_IXE bne process_exception @ Fall into hand on to next handler - appropriate coproc instr @@ -150,10 +154,6 @@ look_for_VFP_exceptions: process_exception: DBGSTR "bounce" - sub r2, r2, #4 - str r2, [sp, #S_PC] @ retry the instruction on exit from - @ the imprecise exception handling in - @ the support code mov r2, sp @ nothing stacked - regdump is at TOS mov lr, r9 @ setup for a return to the user code. @@ -161,7 +161,7 @@ process_exception: @ r0 holds the trigger instruction @ r1 holds the FPEXC value @ r2 pointer to register dump - b VFP9_bounce @ we have handled this - the support + b VFP_bounce @ we have handled this - the support @ code will raise an exception if @ required. If not, the user code will @ retry the faulted instruction @@ -174,12 +174,12 @@ vfp_save_state: @ r0 - save location @ r1 - FPEXC DBGSTR1 "save VFP state %p", r0 + VFPFSTMIA r0, r2 @ save the working registers VFPFMRX r2, FPSCR @ current status - VFPFMRX r3, FPINST @ FPINST (always there, rev0 onwards) - tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read? - VFPFMRX r12, FPINST2, NE @ FPINST2 if needed - avoids reading - @ nonexistant reg on rev0 - VFPFSTMIA r0 @ save the working registers + tst r1, #FPEXC_EX @ is there additional state to save? + VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set) + tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? + VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present) stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 mov pc, lr #endif @@ -217,8 +217,15 @@ vfp_get_double: fmrrd r0, r1, d\dr mov pc, lr .endr +#ifdef CONFIG_VFPv3 + @ d16 - d31 registers + .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr + mov pc, lr + .endr +#endif - @ virtual register 16 for compare with zero + @ virtual register 16 (or 32 if VFPv3) for compare with zero mov r0, #0 mov r1, #0 mov pc, lr @@ -231,3 +238,10 @@ vfp_put_double: fmdrr d\dr, r0, r1 mov pc, lr .endr +#ifdef CONFIG_VFPv3 + @ d16 - d31 registers + .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr + mov pc, lr + .endr +#endif diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h index 7f343a4..15b95b5 100644 --- a/arch/arm/vfp/vfpinstr.h +++ b/arch/arm/vfp/vfpinstr.h @@ -52,11 +52,11 @@ #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) #define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) -#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12) +#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18) #define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5) -#define vfp_get_dm(inst) ((inst & 0x0000000f)) +#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1) #define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) -#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16) +#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3) #define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00) diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index b4e210d..32455c6 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -125,13 +125,13 @@ void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) send_sig_info(SIGFPE, &info, current); } -static void vfp_panic(char *reason) +static void vfp_panic(char *reason, u32 inst) { int i; printk(KERN_ERR "VFP: Error: %s\n", reason); printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", - fmrx(FPEXC), fmrx(FPSCR), fmrx(FPINST)); + fmrx(FPEXC), fmrx(FPSCR), inst); for (i = 0; i < 32; i += 2) printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n", i, vfp_get_float(i), i+1, vfp_get_float(i+1)); @@ -147,19 +147,16 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_ pr_debug("VFP: raising exceptions %08x\n", exceptions); if (exceptions == VFP_EXCEPTION_ERROR) { - vfp_panic("unhandled bounce"); + vfp_panic("unhandled bounce", inst); vfp_raise_sigfpe(0, regs); return; } /* - * If any of the status flags are set, update the FPSCR. + * Update the FPSCR with the additional exception flags. * Comparison instructions always return at least one of * these flags set. */ - if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V)) - fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V); - fpscr |= exceptions; fmxr(FPSCR, fpscr); @@ -220,35 +217,64 @@ static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs) /* * Package up a bounce condition. */ -void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) +void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) { - u32 fpscr, orig_fpscr, exceptions, inst; + u32 fpscr, orig_fpscr, fpsid, exceptions; pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc); /* - * Enable access to the VFP so we can handle the bounce. + * At this point, FPEXC can have the following configuration: + * + * EX DEX IXE + * 0 1 x - synchronous exception + * 1 x 0 - asynchronous exception + * 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later + * 0 0 1 - synchronous on VFP9 (non-standard subarch 1 + * implementation), undefined otherwise + * + * Clear various bits and enable access to the VFP so we can + * handle the bounce. */ - fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_FPV2|FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC)); + fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK)); + fpsid = fmrx(FPSID); orig_fpscr = fpscr = fmrx(FPSCR); /* - * If we are running with inexact exceptions enabled, we need to - * emulate the trigger instruction. Note that as we're emulating - * the trigger instruction, we need to increment PC. + * Check for the special VFP subarch 1 and FPSCR.IXE bit case */ - if (fpscr & FPSCR_IXE) { - regs->ARM_pc += 4; + if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT) + && (fpscr & FPSCR_IXE)) { + /* + * Synchronous exception, emulate the trigger instruction + */ goto emulate; } - barrier(); + if (fpexc & FPEXC_EX) { + /* + * Asynchronous exception. The instruction is read from FPINST + * and the interrupted instruction has to be restarted. + */ + trigger = fmrx(FPINST); + regs->ARM_pc -= 4; + } else if (!(fpexc & FPEXC_DEX)) { + /* + * Illegal combination of bits. It can be caused by an + * unallocated VFP instruction but with FPSCR.IXE set and not + * on VFP subarch 1. + */ + vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs); + return; + } /* - * Modify fpscr to indicate the number of iterations remaining + * Modify fpscr to indicate the number of iterations remaining. + * If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates + * whether FPEXC.VECITR or FPSCR.LEN is used. */ - if (fpexc & FPEXC_EX) { + if (fpexc & (FPEXC_EX | FPEXC_VV)) { u32 len; len = fpexc + (1 << FPEXC_LENGTH_BIT); @@ -262,15 +288,15 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) * FPEXC bounce reason, but this appears to be unreliable. * Emulate the bounced instruction instead. */ - inst = fmrx(FPINST); - exceptions = vfp_emulate_instruction(inst, fpscr, regs); + exceptions = vfp_emulate_instruction(trigger, fpscr, regs); if (exceptions) - vfp_raise_exceptions(exceptions, inst, orig_fpscr, regs); + vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); /* - * If there isn't a second FP instruction, exit now. + * If there isn't a second FP instruction, exit now. Note that + * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1. */ - if (!(fpexc & FPEXC_FPV2)) + if (fpexc ^ (FPEXC_EX | FPEXC_FP2V)) return; /* @@ -279,10 +305,9 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) */ barrier(); trigger = fmrx(FPINST2); - orig_fpscr = fpscr = fmrx(FPSCR); emulate: - exceptions = vfp_emulate_instruction(trigger, fpscr, regs); + exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs); if (exceptions) vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); } @@ -306,16 +331,9 @@ static int __init vfp_init(void) { unsigned int vfpsid; unsigned int cpu_arch = cpu_architecture(); - u32 access = 0; - if (cpu_arch >= CPU_ARCH_ARMv6) { - access = get_copro_access(); - - /* - * Enable full access to VFP (cp10 and cp11) - */ - set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); - } + if (cpu_arch >= CPU_ARCH_ARMv6) + vfp_enable(NULL); /* * First check that there is a VFP that we can use. @@ -329,15 +347,9 @@ static int __init vfp_init(void) vfp_vector = vfp_null_entry; printk(KERN_INFO "VFP support v0.3: "); - if (VFP_arch) { + if (VFP_arch) printk("not present\n"); - - /* - * Restore the copro access register. - */ - if (cpu_arch >= CPU_ARCH_ARMv6) - set_copro_access(access); - } else if (vfpsid & FPSID_NODOUBLE) { + else if (vfpsid & FPSID_NODOUBLE) { printk("no double precision support\n"); } else { smp_call_function(vfp_enable, NULL, 1, 1); diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c index 548a320..4316f5a 100644 --- a/arch/powerpc/sysdev/mv64x60_dev.c +++ b/arch/powerpc/sysdev/mv64x60_dev.c @@ -361,12 +361,6 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id) else pdata.timeout = 1000; /* 1 second */ - prop = of_get_property(np, "retries", NULL); - if (prop) - pdata.retries = *prop; - else - pdata.retries = 1; - pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id); if (!pdev) return -ENOMEM; diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c index 2744b8a..90fe904 100644 --- a/arch/ppc/syslib/mv64x60.c +++ b/arch/ppc/syslib/mv64x60.c @@ -411,7 +411,6 @@ static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = { .freq_m = 8, .freq_n = 3, .timeout = 1000, /* Default timeout of 1 second */ - .retries = 1, }; static struct resource mv64xxx_i2c_resources[] = { diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index c466c6c..b148bf0 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -648,7 +648,7 @@ config I2C_PCA_ISA config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" - depends on MV64X60 && EXPERIMENTAL + depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL help If you say yes to this option, support will be included for the built-in I2C interface on the Marvell 64xxx line of host bridges. diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index bb7bf68..036e6a8 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -1,6 +1,6 @@ /* - * Driver for the i2c controller on the Marvell line of host bridges for MIPS - * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0). + * Driver for the i2c controller on the Marvell line of host bridges + * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family). * * Author: Mark A. Greer * @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include @@ -86,6 +86,7 @@ struct mv64xxx_i2c_data { u32 cntl_bits; void __iomem *reg_base; u32 reg_base_p; + u32 reg_size; u32 addr1; u32 addr2; u32 bytes_left; @@ -463,17 +464,20 @@ static int __devinit mv64xxx_i2c_map_regs(struct platform_device *pd, struct mv64xxx_i2c_data *drv_data) { - struct resource *r; + int size; + struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0); - if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) && - request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE, - drv_data->adapter.name)) { + if (!r) + return -ENODEV; - drv_data->reg_base = ioremap(r->start, - MV64XXX_I2C_REG_BLOCK_SIZE); - drv_data->reg_base_p = r->start; - } else - return -ENOMEM; + size = r->end - r->start + 1; + + if (!request_mem_region(r->start, size, drv_data->adapter.name)) + return -EBUSY; + + drv_data->reg_base = ioremap(r->start, size); + drv_data->reg_base_p = r->start; + drv_data->reg_size = size; return 0; } @@ -483,8 +487,7 @@ mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) { if (drv_data->reg_base) { iounmap(drv_data->reg_base); - release_mem_region(drv_data->reg_base_p, - MV64XXX_I2C_REG_BLOCK_SIZE); + release_mem_region(drv_data->reg_base_p, drv_data->reg_size); } drv_data->reg_base = NULL; @@ -529,7 +532,6 @@ mv64xxx_i2c_probe(struct platform_device *pd) drv_data->adapter.owner = THIS_MODULE; drv_data->adapter.class = I2C_CLASS_HWMON; drv_data->adapter.timeout = pdata->timeout; - drv_data->adapter.retries = pdata->retries; drv_data->adapter.nr = pd->id; platform_set_drvdata(pd, drv_data); i2c_set_adapdata(&drv_data->adapter, drv_data); diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index 1654a33..1ea8482 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c @@ -65,6 +65,8 @@ struct pxamci_host { unsigned int dma_len; unsigned int dma_dir; + unsigned int dma_drcmrrx; + unsigned int dma_drcmrtx; }; static void pxamci_stop_clock(struct pxamci_host *host) @@ -131,13 +133,13 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) if (data->flags & MMC_DATA_READ) { host->dma_dir = DMA_FROM_DEVICE; dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG; - DRCMRTXMMC = 0; - DRCMRRXMMC = host->dma | DRCMR_MAPVLD; + DRCMR(host->dma_drcmrtx) = 0; + DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD; } else { host->dma_dir = DMA_TO_DEVICE; dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC; - DRCMRRXMMC = 0; - DRCMRTXMMC = host->dma | DRCMR_MAPVLD; + DRCMR(host->dma_drcmrrx) = 0; + DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD; } dcmd |= DCMD_BURST32 | DCMD_WIDTH1; @@ -375,14 +377,23 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (host->clkrt == CLKRT_OFF) clk_enable(host->clk); - /* - * clk might result in a lower divisor than we - * desire. check for that condition and adjust - * as appropriate. - */ - if (rate / clk > ios->clock) - clk <<= 1; - host->clkrt = fls(clk) - 1; + if (ios->clock == 26000000) { + /* to support 26MHz on pxa300/pxa310 */ + host->clkrt = 7; + } else { + /* to handle (19.5MHz, 26MHz) */ + if (!clk) + clk = 1; + + /* + * clk might result in a lower divisor than we + * desire. check for that condition and adjust + * as appropriate. + */ + if (rate / clk > ios->clock) + clk <<= 1; + host->clkrt = fls(clk) - 1; + } /* * we write clkrt on the next command @@ -459,7 +470,7 @@ static int pxamci_probe(struct platform_device *pdev) { struct mmc_host *mmc; struct pxamci_host *host = NULL; - struct resource *r; + struct resource *r, *dmarx, *dmatx; int ret, irq; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -519,7 +530,8 @@ static int pxamci_probe(struct platform_device *pdev) * Calculate minimum clock rate, rounding up. */ mmc->f_min = (host->clkrate + 63) / 64; - mmc->f_max = host->clkrate; + mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000 + : host->clkrate; mmc->ocr_avail = host->pdata ? host->pdata->ocr_mask : @@ -529,6 +541,9 @@ static int pxamci_probe(struct platform_device *pdev) if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) { mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; host->cmdat |= CMDAT_SDIO_INT_EN; + if (cpu_is_pxa300() || cpu_is_pxa310()) + mmc->caps |= MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_SD_HIGHSPEED; } host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); @@ -570,6 +585,20 @@ static int pxamci_probe(struct platform_device *pdev) platform_set_drvdata(pdev, mmc); + dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!dmarx) { + ret = -ENXIO; + goto out; + } + host->dma_drcmrrx = dmarx->start; + + dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (!dmatx) { + ret = -ENXIO; + goto out; + } + host->dma_drcmrtx = dmatx->start; + if (host->pdata && host->pdata->init) host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); @@ -613,8 +642,8 @@ static int pxamci_remove(struct platform_device *pdev) END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, host->base + MMC_I_MASK); - DRCMRRXMMC = 0; - DRCMRTXMMC = 0; + DRCMR(host->dma_drcmrrx) = 0; + DRCMR(host->dma_drcmrtx) = 0; free_irq(host->irq, host); pxa_free_dma(host->dma); diff --git a/drivers/mmc/host/pxamci.h b/drivers/mmc/host/pxamci.h index 748c770..f6c2e2f 100644 --- a/drivers/mmc/host/pxamci.h +++ b/drivers/mmc/host/pxamci.h @@ -68,7 +68,7 @@ #define PRG_DONE (1 << 1) #define DATA_TRAN_DONE (1 << 0) -#ifdef CONFIG_PXA27x +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define MMC_I_MASK_ALL 0x00001fff #else #define MMC_I_MASK_ALL 0x0000007f diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c index 7da7589..4020e9e 100644 --- a/drivers/net/smc91x.c +++ b/drivers/net/smc91x.c @@ -1775,7 +1775,8 @@ static int __init smc_findirq(void __iomem *ioaddr) * o actually GRAB the irq. * o GRAB the region */ -static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr) +static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr, + unsigned long irq_flags) { struct smc_local *lp = netdev_priv(dev); static int version_printed = 0; @@ -1941,7 +1942,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr) } /* Grab the IRQ */ - retval = request_irq(dev->irq, &smc_interrupt, SMC_IRQ_FLAGS, dev->name, dev); + retval = request_irq(dev->irq, &smc_interrupt, irq_flags, dev->name, dev); if (retval) goto err_out; @@ -2123,8 +2124,9 @@ static void smc_release_datacs(struct platform_device *pdev, struct net_device * static int smc_drv_probe(struct platform_device *pdev) { struct net_device *ndev; - struct resource *res; + struct resource *res, *ires; unsigned int __iomem *addr; + unsigned long irq_flags = SMC_IRQ_FLAGS; int ret; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); @@ -2150,12 +2152,17 @@ static int smc_drv_probe(struct platform_device *pdev) SET_NETDEV_DEV(ndev, &pdev->dev); ndev->dma = (unsigned char)-1; - ndev->irq = platform_get_irq(pdev, 0); - if (ndev->irq < 0) { + + ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!ires) { ret = -ENODEV; goto out_free_netdev; } + ndev->irq = ires->start; + if (SMC_IRQ_FLAGS == -1) + irq_flags = ires->flags & IRQF_TRIGGER_MASK; + ret = smc_request_attrib(pdev); if (ret) goto out_free_netdev; @@ -2181,7 +2188,7 @@ static int smc_drv_probe(struct platform_device *pdev) #endif platform_set_drvdata(pdev, ndev); - ret = smc_probe(ndev, addr); + ret = smc_probe(ndev, addr, irq_flags); if (ret != 0) goto out_iounmap; diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index 07b7f71..1d97eae 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -54,6 +54,7 @@ #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ #elif defined(CONFIG_BLACKFIN) @@ -158,7 +159,7 @@ #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) -#define SMC_IRQ_FLAGS (0) +#define SMC_IRQ_FLAGS (-1) #elif defined(CONFIG_SA1100_ASSABET) @@ -177,6 +178,7 @@ #define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) +#define SMC_IRQ_FLAGS (-1) /* from resource */ #elif defined(CONFIG_MACH_LOGICPD_PXA270) @@ -210,6 +212,7 @@ #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ /* We actually can't write halfwords properly if not word aligned */ static inline void @@ -238,6 +241,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) #define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_IRQ_FLAGS (-1) /* from resource */ #elif defined(CONFIG_ARCH_OMAP) @@ -252,17 +256,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) - -#include -#include - -#define SMC_IRQ_FLAGS (( \ - machine_is_omap_h2() \ - || machine_is_omap_h3() \ - || machine_is_omap_h4() \ - || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ - ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING) - +#define SMC_IRQ_FLAGS (-1) /* from resource */ #elif defined(CONFIG_SH_SH4202_MICRODEV) @@ -453,8 +447,7 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) - -#define SMC_IRQ_FLAGS (0) +#define SMC_IRQ_FLAGS (-1) /* from resource */ #else diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c index 874923f..e439044 100644 --- a/drivers/pcmcia/pxa2xx_base.c +++ b/drivers/pcmcia/pxa2xx_base.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c index 6f1e9a9..2eb3852 100644 --- a/drivers/rtc/rtc-sa1100.c +++ b/drivers/rtc/rtc-sa1100.c @@ -337,6 +337,8 @@ static int sa1100_rtc_probe(struct platform_device *pdev) if (IS_ERR(rtc)) return PTR_ERR(rtc); + device_init_wakeup(&pdev->dev, 1); + platform_set_drvdata(pdev, rtc); return 0; @@ -352,9 +354,38 @@ static int sa1100_rtc_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int sa1100_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (pdev->dev.power.power_state.event != state.event) { + if (state.event == PM_EVENT_SUSPEND && + device_may_wakeup(&pdev->dev)) + enable_irq_wake(IRQ_RTCAlrm); + + pdev->dev.power.power_state = state; + } + return 0; +} + +static int sa1100_rtc_resume(struct platform_device *pdev) +{ + if (pdev->dev.power.power_state.event != PM_EVENT_ON) { + if (device_may_wakeup(&pdev->dev)) + disable_irq_wake(IRQ_RTCAlrm); + pdev->dev.power.power_state = PMSG_ON; + } + return 0; +} +#else +#define sa1100_rtc_suspend NULL +#define sa1100_rtc_resume NULL +#endif + static struct platform_driver sa1100_rtc_driver = { .probe = sa1100_rtc_probe, .remove = sa1100_rtc_remove, + .suspend = sa1100_rtc_suspend, + .resume = sa1100_rtc_resume, .driver = { .name = "sa1100-rtc", }, diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c index facb678..6a48dfa 100644 --- a/drivers/serial/21285.c +++ b/drivers/serial/21285.c @@ -277,6 +277,8 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_iflag & INPCK) port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY; + tty_encode_baud_rate(tty, baud, baud); + /* * Which character status flags should we ignore? */ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index abf0504..aaaea81 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -153,6 +153,7 @@ config SPI_OMAP24XX config SPI_PXA2XX tristate "PXA2xx SSP SPI master" depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL + select PXA_SSP help This enables using a PXA2xx SSP port as a SPI master controller. The driver can be configured to use any SSP port and additional diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c index 1c2ab54..eb817b8 100644 --- a/drivers/spi/pxa2xx_spi.c +++ b/drivers/spi/pxa2xx_spi.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -36,6 +37,8 @@ #include #include +#include +#include #include MODULE_AUTHOR("Stephen Street"); @@ -80,6 +83,9 @@ struct driver_data { /* Driver model hookup */ struct platform_device *pdev; + /* SSP Info */ + struct ssp_device *ssp; + /* SPI framework hookup */ enum pxa_ssp_type ssp_type; struct spi_master *master; @@ -778,6 +784,16 @@ int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi, return retval; } +static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) +{ + unsigned long ssp_clk = clk_get_rate(ssp->clk); + + if (ssp->type == PXA25x_SSP) + return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; + else + return ((ssp_clk / rate - 1) & 0xfff) << 8; +} + static void pump_transfers(unsigned long data) { struct driver_data *drv_data = (struct driver_data *)data; @@ -785,6 +801,7 @@ static void pump_transfers(unsigned long data) struct spi_transfer *transfer = NULL; struct spi_transfer *previous = NULL; struct chip_data *chip = NULL; + struct ssp_device *ssp = drv_data->ssp; void *reg = drv_data->ioaddr; u32 clk_div = 0; u8 bits = 0; @@ -866,12 +883,7 @@ static void pump_transfers(unsigned long data) if (transfer->bits_per_word) bits = transfer->bits_per_word; - if (reg == SSP1_VIRT) - clk_div = SSP1_SerClkDiv(speed); - else if (reg == SSP2_VIRT) - clk_div = SSP2_SerClkDiv(speed); - else if (reg == SSP3_VIRT) - clk_div = SSP3_SerClkDiv(speed); + clk_div = ssp_get_clk_div(ssp, speed); if (bits <= 8) { drv_data->n_bytes = 1; @@ -1074,6 +1086,7 @@ static int setup(struct spi_device *spi) struct pxa2xx_spi_chip *chip_info = NULL; struct chip_data *chip; struct driver_data *drv_data = spi_master_get_devdata(spi->master); + struct ssp_device *ssp = drv_data->ssp; unsigned int clk_div; if (!spi->bits_per_word) @@ -1157,18 +1170,7 @@ static int setup(struct spi_device *spi) } } - if (drv_data->ioaddr == SSP1_VIRT) - clk_div = SSP1_SerClkDiv(spi->max_speed_hz); - else if (drv_data->ioaddr == SSP2_VIRT) - clk_div = SSP2_SerClkDiv(spi->max_speed_hz); - else if (drv_data->ioaddr == SSP3_VIRT) - clk_div = SSP3_SerClkDiv(spi->max_speed_hz); - else - { - dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n", - drv_data->ioaddr); - return -ENODEV; - } + clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); chip->speed_hz = spi->max_speed_hz; chip->cr0 = clk_div @@ -1183,15 +1185,15 @@ static int setup(struct spi_device *spi) /* NOTE: PXA25x_SSP _could_ use external clocking ... */ if (drv_data->ssp_type != PXA25x_SSP) - dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n", + dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", spi->bits_per_word, - (CLOCK_SPEED_HZ) + clk_get_rate(ssp->clk) / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), spi->mode & 0x3); else - dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n", + dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", spi->bits_per_word, - (CLOCK_SPEED_HZ/2) + clk_get_rate(ssp->clk) / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), spi->mode & 0x3); @@ -1323,14 +1325,14 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev) struct pxa2xx_spi_master *platform_info; struct spi_master *master; struct driver_data *drv_data = 0; - struct resource *memory_resource; - int irq; + struct ssp_device *ssp; int status = 0; platform_info = dev->platform_data; - if (platform_info->ssp_type == SSP_UNDEFINED) { - dev_err(&pdev->dev, "undefined SSP\n"); + ssp = ssp_request(pdev->id, pdev->name); + if (ssp == NULL) { + dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); return -ENODEV; } @@ -1338,12 +1340,14 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev) master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); if (!master) { dev_err(&pdev->dev, "can not alloc spi_master\n"); + ssp_free(ssp); return -ENOMEM; } drv_data = spi_master_get_devdata(master); drv_data->master = master; drv_data->master_info = platform_info; drv_data->pdev = pdev; + drv_data->ssp = ssp; master->bus_num = pdev->id; master->num_chipselect = platform_info->num_chipselect; @@ -1351,21 +1355,13 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev) master->setup = setup; master->transfer = transfer; - drv_data->ssp_type = platform_info->ssp_type; + drv_data->ssp_type = ssp->type; drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + sizeof(struct driver_data)), 8); - /* Setup register addresses */ - memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!memory_resource) { - dev_err(&pdev->dev, "memory resources not defined\n"); - status = -ENODEV; - goto out_error_master_alloc; - } - - drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start)); - drv_data->ssdr_physical = memory_resource->start + 0x00000010; - if (platform_info->ssp_type == PXA25x_SSP) { + drv_data->ioaddr = ssp->mmio_base; + drv_data->ssdr_physical = ssp->phys_base + SSDR; + if (ssp->type == PXA25x_SSP) { drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; drv_data->dma_cr1 = 0; drv_data->clear_sr = SSSR_ROR; @@ -1377,15 +1373,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev) drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; } - /* Attach to IRQ */ - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "irq resource not defined\n"); - status = -ENODEV; - goto out_error_master_alloc; - } - - status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data); + status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data); if (status < 0) { dev_err(&pdev->dev, "can not get IRQ\n"); goto out_error_master_alloc; @@ -1418,29 +1406,12 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev) goto out_error_dma_alloc; } - if (drv_data->ioaddr == SSP1_VIRT) { - DRCMRRXSSDR = DRCMR_MAPVLD - | drv_data->rx_channel; - DRCMRTXSSDR = DRCMR_MAPVLD - | drv_data->tx_channel; - } else if (drv_data->ioaddr == SSP2_VIRT) { - DRCMRRXSS2DR = DRCMR_MAPVLD - | drv_data->rx_channel; - DRCMRTXSS2DR = DRCMR_MAPVLD - | drv_data->tx_channel; - } else if (drv_data->ioaddr == SSP3_VIRT) { - DRCMRRXSS3DR = DRCMR_MAPVLD - | drv_data->rx_channel; - DRCMRTXSS3DR = DRCMR_MAPVLD - | drv_data->tx_channel; - } else { - dev_err(dev, "bad SSP type\n"); - goto out_error_dma_alloc; - } + DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; + DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; } /* Enable SOC clock */ - pxa_set_cken(platform_info->clock_enable, 1); + clk_enable(ssp->clk); /* Load default SSP configuration */ write_SSCR0(0, drv_data->ioaddr); @@ -1479,7 +1450,7 @@ out_error_queue_alloc: destroy_queue(drv_data); out_error_clock_enabled: - pxa_set_cken(platform_info->clock_enable, 0); + clk_disable(ssp->clk); out_error_dma_alloc: if (drv_data->tx_channel != -1) @@ -1488,17 +1459,18 @@ out_error_dma_alloc: pxa_free_dma(drv_data->rx_channel); out_error_irq_alloc: - free_irq(irq, drv_data); + free_irq(ssp->irq, drv_data); out_error_master_alloc: spi_master_put(master); + ssp_free(ssp); return status; } static int pxa2xx_spi_remove(struct platform_device *pdev) { struct driver_data *drv_data = platform_get_drvdata(pdev); - int irq; + struct ssp_device *ssp = drv_data->ssp; int status = 0; if (!drv_data) @@ -1520,28 +1492,21 @@ static int pxa2xx_spi_remove(struct platform_device *pdev) /* Disable the SSP at the peripheral and SOC level */ write_SSCR0(0, drv_data->ioaddr); - pxa_set_cken(drv_data->master_info->clock_enable, 0); + clk_disable(ssp->clk); /* Release DMA */ if (drv_data->master_info->enable_dma) { - if (drv_data->ioaddr == SSP1_VIRT) { - DRCMRRXSSDR = 0; - DRCMRTXSSDR = 0; - } else if (drv_data->ioaddr == SSP2_VIRT) { - DRCMRRXSS2DR = 0; - DRCMRTXSS2DR = 0; - } else if (drv_data->ioaddr == SSP3_VIRT) { - DRCMRRXSS3DR = 0; - DRCMRTXSS3DR = 0; - } + DRCMR(ssp->drcmr_rx) = 0; + DRCMR(ssp->drcmr_tx) = 0; pxa_free_dma(drv_data->tx_channel); pxa_free_dma(drv_data->rx_channel); } /* Release IRQ */ - irq = platform_get_irq(pdev, 0); - if (irq >= 0) - free_irq(irq, drv_data); + free_irq(ssp->irq, drv_data); + + /* Release SSP */ + ssp_free(ssp); /* Disconnect from the SPI framework */ spi_unregister_master(drv_data->master); @@ -1576,6 +1541,7 @@ static int suspend_devices(struct device *dev, void *pm_message) static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) { struct driver_data *drv_data = platform_get_drvdata(pdev); + struct ssp_device *ssp = drv_data->ssp; int status = 0; /* Check all childern for current power state */ @@ -1588,7 +1554,7 @@ static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) if (status != 0) return status; write_SSCR0(0, drv_data->ioaddr); - pxa_set_cken(drv_data->master_info->clock_enable, 0); + clk_disable(ssp->clk); return 0; } @@ -1596,10 +1562,11 @@ static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) static int pxa2xx_spi_resume(struct platform_device *pdev) { struct driver_data *drv_data = platform_get_drvdata(pdev); + struct ssp_device *ssp = drv_data->ssp; int status = 0; /* Enable the SSP clock */ - pxa_set_cken(drv_data->master_info->clock_enable, 1); + clk_disable(ssp->clk); /* Start the queue running */ status = start_queue(drv_data); diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 7580aa5..7a64990 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -33,6 +33,7 @@ config USB_ARCH_HAS_OHCI default y if ARCH_LH7A404 default y if ARCH_S3C2410 default y if PXA27x + default y if PXA3xx default y if ARCH_EP93XX default y if ARCH_AT91 default y if ARCH_PNX4008 diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index ecfe800..ddd4ee1 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -997,7 +997,7 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver #endif -#ifdef CONFIG_PXA27x +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #include "ohci-pxa27x.c" #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver #endif diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index 23d2fe5..ff9a798 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,8 @@ #define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 ) +static struct clk *usb_clk; + /* PMM_NPS_MODE -- PMM Non-power switching mode Ports are powered continuously. @@ -80,7 +83,7 @@ static int pxa27x_start_hc(struct device *dev) inf = dev->platform_data; - pxa_set_cken(CKEN_USBHOST, 1); + clk_enable(usb_clk); UHCHR |= UHCHR_FHR; udelay(11); @@ -123,7 +126,7 @@ static void pxa27x_stop_hc(struct device *dev) UHCCOMS |= 1; udelay(10); - pxa_set_cken(CKEN_USBHOST, 0); + clk_disable(usb_clk); } @@ -158,6 +161,10 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device return -ENOMEM; } + usb_clk = clk_get(&pdev->dev, "USBCLK"); + if (IS_ERR(usb_clk)) + return PTR_ERR(usb_clk); + hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x"); if (!hcd) return -ENOMEM; @@ -201,6 +208,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device release_mem_region(hcd->rsrc_start, hcd->rsrc_len); err1: usb_put_hcd(hcd); + clk_put(usb_clk); return retval; } @@ -225,6 +233,7 @@ void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev) iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); + clk_put(usb_clk); } /*-------------------------------------------------------------------------*/ diff --git a/include/asm-arm/arch-at91/at91_lcdc.h b/include/asm-arm/arch-at91/at91_lcdc.h deleted file mode 100644 index ab040a4..0000000 --- a/include/asm-arm/arch-at91/at91_lcdc.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * include/asm-arm/arch-at91/at91_lcdc.h - * - * LCD Controller (LCDC). - * Based on AT91SAM9261 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_LCDC_H -#define AT91_LCDC_H - -#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */ -#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */ -#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */ -#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */ -#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */ -#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */ - -#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */ -#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */ -#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */ - -#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */ -#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */ -#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */ -#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */ - -#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */ -#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */ -#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */ -#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */ - -#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */ -#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */ -#define AT91_LCDC_DISTYPE_STNMONO (0 << 0) -#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0) -#define AT91_LCDC_DISTYPE_TFT (2 << 0) -#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */ -#define AT91_LCDC_SCANMOD_SINGLE (0 << 2) -#define AT91_LCDC_SCANMOD_DUAL (1 << 2) -#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */ -#define AT91_LCDC_IFWIDTH_4 (0 << 3) -#define AT91_LCDC_IFWIDTH_8 (1 << 3) -#define AT91_LCDC_IFWIDTH_16 (2 << 3) -#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */ -#define AT91_LCDC_PIXELSIZE_1 (0 << 5) -#define AT91_LCDC_PIXELSIZE_2 (1 << 5) -#define AT91_LCDC_PIXELSIZE_4 (2 << 5) -#define AT91_LCDC_PIXELSIZE_8 (3 << 5) -#define AT91_LCDC_PIXELSIZE_16 (4 << 5) -#define AT91_LCDC_PIXELSIZE_24 (5 << 5) -#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */ -#define AT91_LCDC_INVVD_NORMAL (0 << 8) -#define AT91_LCDC_INVVD_INVERTED (1 << 8) -#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */ -#define AT91_LCDC_INVFRAME_NORMAL (0 << 9) -#define AT91_LCDC_INVFRAME_INVERTED (1 << 9) -#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */ -#define AT91_LCDC_INVLINE_NORMAL (0 << 10) -#define AT91_LCDC_INVLINE_INVERTED (1 << 10) -#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */ -#define AT91_LCDC_INVCLK_NORMAL (0 << 11) -#define AT91_LCDC_INVCLK_INVERTED (1 << 11) -#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */ -#define AT91_LCDC_INVDVAL_NORMAL (0 << 12) -#define AT91_LCDC_INVDVAL_INVERTED (1 << 12) -#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */ -#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) -#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) -#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */ -#define AT91_LCDC_MEMOR_BIG (0 << 31) -#define AT91_LCDC_MEMOR_LITTLE (1 << 31) - -#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */ -#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */ -#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */ -#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */ -#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */ - -#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */ -#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */ -#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */ -#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */ - -#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */ -#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */ -#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */ - -#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */ -#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */ - -#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */ -#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */ -#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */ -#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */ -#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */ -#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */ -#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */ -#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */ -#define AT91_LCDC_DP1_2_VAL (0xff) -#define AT91_LCDC_DP4_7_VAL (0xfffffff) -#define AT91_LCDC_DP3_5_VAL (0xfffff) -#define AT91_LCDC_DP2_3_VAL (0xfff) -#define AT91_LCDC_DP5_7_VAL (0xfffffff) -#define AT91_LCDC_DP3_4_VAL (0xffff) -#define AT91_LCDC_DP4_5_VAL (0xfffff) -#define AT91_LCDC_DP6_7_VAL (0xfffffff) - -#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */ -#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */ -#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */ -#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */ - -#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */ -#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */ -#define AT91_LCDC_PS_DIV1 (0 << 0) -#define AT91_LCDC_PS_DIV2 (1 << 0) -#define AT91_LCDC_PS_DIV4 (2 << 0) -#define AT91_LCDC_PS_DIV8 (3 << 0) -#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */ -#define AT91_LCDC_POL_NEGATIVE (0 << 2) -#define AT91_LCDC_POL_POSITIVE (1 << 2) -#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */ -#define AT91_LCDC_ENA_PWMDISABLE (0 << 3) -#define AT91_LCDC_ENA_PWMENABLE (1 << 3) - -#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */ -#define AT91_LCDC_CVAL (0xff) /* PWM compare value */ - -#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */ -#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */ -#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */ -#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */ -#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */ -#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */ -#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */ -#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */ -#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */ -#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */ -#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */ - -#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */ - -#endif diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h index 1ee14a1..9b1864b 100644 --- a/include/asm-arm/arch-ep93xx/gpio.h +++ b/include/asm-arm/arch-ep93xx/gpio.h @@ -5,16 +5,6 @@ #ifndef __ASM_ARCH_GPIO_H #define __ASM_ARCH_GPIO_H -#define GPIO_IN 0 -#define GPIO_OUT 1 - -#define EP93XX_GPIO_LOW 0 -#define EP93XX_GPIO_HIGH 1 - -extern void gpio_line_config(int line, int direction); -extern int gpio_line_get(int line); -extern void gpio_line_set(int line, int value); - /* GPIO port A. */ #define EP93XX_GPIO_LINE_A(x) ((x) + 0) #define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) @@ -38,7 +28,7 @@ extern void gpio_line_set(int line, int value); #define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7) /* GPIO port C. */ -#define EP93XX_GPIO_LINE_C(x) ((x) + 16) +#define EP93XX_GPIO_LINE_C(x) ((x) + 40) #define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0) #define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1) #define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2) @@ -71,7 +61,7 @@ extern void gpio_line_set(int line, int value); #define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7) /* GPIO port F. */ -#define EP93XX_GPIO_LINE_F(x) ((x) + 40) +#define EP93XX_GPIO_LINE_F(x) ((x) + 16) #define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0) #define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1) #define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2) @@ -103,5 +93,49 @@ extern void gpio_line_set(int line, int value); #define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6) #define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7) +/* maximum value for gpio line identifiers */ +#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7) + +/* maximum value for irq capable line identifiers */ +#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) + +/* new generic GPIO API - see Documentation/gpio.txt */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + if (gpio > EP93XX_GPIO_LINE_MAX) + return -EINVAL; + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); + +#include /* cansleep wrappers */ + +/* + * Map GPIO A0..A7 (0..7) to irq 64..71, + * B0..B7 (7..15) to irq 72..79, and + * F0..F7 (16..24) to irq 80..87. + */ + +static inline int gpio_to_irq(unsigned gpio) +{ + if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ) + return 64 + gpio; + + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq - gpio_to_irq(0); +} #endif diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h index 2a8c636..53d4a68 100644 --- a/include/asm-arm/arch-ep93xx/irqs.h +++ b/include/asm-arm/arch-ep93xx/irqs.h @@ -67,12 +67,6 @@ #define IRQ_EP93XX_SAI 60 #define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff -/* - * Map GPIO A0..A7 to irq 64..71, B0..B7 to 72..79, and - * F0..F7 to 80..87. - */ -#define IRQ_EP93XX_GPIO(x) (64 + (((x) + (((x) >> 2) & 8)) & 0x1f)) - #define NR_EP93XX_IRQS (64 + 24) #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h index d2523b3..2fa3d6b 100644 --- a/include/asm-arm/arch-ixp4xx/cpu.h +++ b/include/asm-arm/arch-ixp4xx/cpu.h @@ -28,4 +28,19 @@ extern unsigned int processor_id; #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ IXP465_PROCESSOR_ID_VALUE) +static inline u32 ixp4xx_read_feature_bits(void) +{ + unsigned int val = ~*IXP4XX_EXP_CFG2; + val &= ~IXP4XX_FEATURE_RESERVED; + if (!cpu_is_ixp46x()) + val &= ~IXP4XX_FEATURE_IXP46X_ONLY; + + return val; +} + +static inline void ixp4xx_write_feature_bits(u32 value) +{ + *IXP4XX_EXP_CFG2 = ~value; +} + #endif /* _ASM_ARCH_CPU_H */ diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index 297ceda..73e8dc3 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h @@ -27,13 +27,13 @@ #define pcibios_assign_all_busses() 1 +/* Register locations and bits */ +#include "ixp4xx-regs.h" + #ifndef __ASSEMBLER__ #include #endif -/* Register locations and bits */ -#include "ixp4xx-regs.h" - /* Platform helper functions and definitions */ #include "platform.h" diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index eeeea90..9c5d235 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h @@ -61,13 +61,13 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) return __arm_ioremap(addr, size, mtype); - return (void *)addr; + return (void __iomem *)addr; } static inline void __ixp4xx_iounmap(void __iomem *addr) { - if ((u32)addr >= VMALLOC_START) + if ((__force u32)addr >= VMALLOC_START) __iounmap(addr); } @@ -141,9 +141,9 @@ __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) static inline void __ixp4xx_writel(u32 value, volatile void __iomem *p) { - u32 addr = (u32)p; + u32 addr = (__force u32)p; if (addr >= VMALLOC_START) { - __raw_writel(value, addr); + __raw_writel(value, p); return; } @@ -208,11 +208,11 @@ __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) static inline unsigned long __ixp4xx_readl(const volatile void __iomem *p) { - u32 addr = (u32)p; + u32 addr = (__force u32)p; u32 data; if (addr >= VMALLOC_START) - return __raw_readl(addr); + return __raw_readl(p); if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) return 0xffffffff; @@ -438,7 +438,7 @@ __ixp4xx_ioread32(const void __iomem *addr) return (unsigned int)__ixp4xx_inl(port & PIO_MASK); else { #ifndef CONFIG_IXP4XX_INDIRECT_PCI - return le32_to_cpu(__raw_readl((u32)port)); + return le32_to_cpu((__force __le32)__raw_readl(addr)); #else return (unsigned int)__ixp4xx_readl(addr); #endif @@ -523,7 +523,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr) __ixp4xx_outl(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writel(cpu_to_le32(value), port); + __raw_writel((u32 __force)cpu_to_le32(value), addr); #else __ixp4xx_writel(value, addr); #endif diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h index 5d949d7..c704fe8 100644 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h @@ -15,10 +15,6 @@ * */ -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - #ifndef _ASM_ARM_IXP4XX_H_ #define _ASM_ARM_IXP4XX_H_ @@ -607,4 +603,36 @@ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ +/* "fuse" bits of IXP_EXP_CFG2 */ +#define IXP4XX_FEATURE_RCOMP (1 << 0) +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1) +#define IXP4XX_FEATURE_HASH (1 << 2) +#define IXP4XX_FEATURE_AES (1 << 3) +#define IXP4XX_FEATURE_DES (1 << 4) +#define IXP4XX_FEATURE_HDLC (1 << 5) +#define IXP4XX_FEATURE_AAL (1 << 6) +#define IXP4XX_FEATURE_HSS (1 << 7) +#define IXP4XX_FEATURE_UTOPIA (1 << 8) +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10) +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11) +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12) +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13) +#define IXP4XX_FEATURE_PCI (1 << 14) +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) +#define IXP4XX_FEATURE_USB_HOST (1 << 18) +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19) +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) +#define IXP4XX_FEATURE_RSA (1 << 21) +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) +#define IXP4XX_FEATURE_RESERVED (0xFF << 24) + +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ + IXP4XX_FEATURE_USB_HOST | \ + IXP4XX_FEATURE_NPEA_ETH | \ + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ + IXP4XX_FEATURE_RSA | \ + IXP4XX_FEATURE_XSCALE_MAX_FREQ) + #endif diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h new file mode 100644 index 0000000..37d0511 --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/npe.h @@ -0,0 +1,39 @@ +#ifndef __IXP4XX_NPE_H +#define __IXP4XX_NPE_H + +#include + +extern const char *npe_names[]; + +struct npe_regs { + u32 exec_addr, exec_data, exec_status_cmd, exec_count; + u32 action_points[4]; + u32 watchpoint_fifo, watch_count; + u32 profile_count; + u32 messaging_status, messaging_control; + u32 mailbox_status, /*messaging_*/ in_out_fifo; +}; + +struct npe { + struct resource *mem_res; + struct npe_regs __iomem *regs; + u32 regs_phys; + int id; + int valid; +}; + + +static inline const char *npe_name(struct npe *npe) +{ + return npe_names[npe->id]; +} + +int npe_running(struct npe *npe); +int npe_send_message(struct npe *npe, const void *msg, const char *what); +int npe_recv_message(struct npe *npe, void *msg, const char *what); +int npe_send_recv_message(struct npe *npe, void *msg, const char *what); +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); +struct npe *npe_request(int id); +void npe_release(struct npe *npe); + +#endif /* __IXP4XX_NPE_H */ diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index 2a44d3d..695b9c4 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h @@ -77,8 +77,7 @@ extern unsigned long ixp4xx_exp_bus_size; /* * The IXP4xx chips do not have an I2C unit, so GPIO lines are just - * used to - * Used as platform_data to provide GPIO pin information to the ixp42x + * used as platform_data to provide GPIO pin information to the ixp42x * I2C driver. */ struct ixp4xx_i2c_pins { @@ -86,6 +85,27 @@ struct ixp4xx_i2c_pins { unsigned long scl_pin; }; +#define IXP4XX_ETH_NPEA 0x00 +#define IXP4XX_ETH_NPEB 0x10 +#define IXP4XX_ETH_NPEC 0x20 + +/* Information about built-in Ethernet MAC interfaces */ +struct eth_plat_info { + u8 phy; /* MII PHY ID, 0 - 31 */ + u8 rxq; /* configurable, currently 0 - 31 only */ + u8 txreadyq; + u8 hwaddr[6]; +}; + +/* Information about built-in HSS (synchronous serial) interfaces */ +struct hss_plat_info { + int (*set_clock)(int port, unsigned int clock_type); + int (*open)(int port, void *pdev, + void (*set_carrier_cb)(void *pdev, int carrier)); + void (*close)(int port, void *pdev); + u8 txreadyq; +}; + /* * This structure provide a means for the board setup code * to give information to th pata_ixp4xx driver. It is diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h new file mode 100644 index 0000000..1e52b95 --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/qmgr.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + */ + +#ifndef IXP4XX_QMGR_H +#define IXP4XX_QMGR_H + +#include +#include + +#define HALF_QUEUES 32 +#define QUEUES 64 /* only 32 lower queues currently supported */ +#define MAX_QUEUE_LENGTH 4 /* in dwords */ + +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */ +#define QUEUE_STAT1_NEARLY_EMPTY 2 +#define QUEUE_STAT1_NEARLY_FULL 4 +#define QUEUE_STAT1_FULL 8 +#define QUEUE_STAT2_UNDERFLOW 1 +#define QUEUE_STAT2_OVERFLOW 2 + +#define QUEUE_WATERMARK_0_ENTRIES 0 +#define QUEUE_WATERMARK_1_ENTRY 1 +#define QUEUE_WATERMARK_2_ENTRIES 2 +#define QUEUE_WATERMARK_4_ENTRIES 3 +#define QUEUE_WATERMARK_8_ENTRIES 4 +#define QUEUE_WATERMARK_16_ENTRIES 5 +#define QUEUE_WATERMARK_32_ENTRIES 6 +#define QUEUE_WATERMARK_64_ENTRIES 7 + +/* queue interrupt request conditions */ +#define QUEUE_IRQ_SRC_EMPTY 0 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2 +#define QUEUE_IRQ_SRC_FULL 3 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6 +#define QUEUE_IRQ_SRC_NOT_FULL 7 + +struct qmgr_regs { + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */ + u32 stat1[4]; /* 0x400 - 0x40F */ + u32 stat2[2]; /* 0x410 - 0x417 */ + u32 statne_h; /* 0x418 - queue nearly empty */ + u32 statf_h; /* 0x41C - queue full */ + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */ + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */ + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */ + u32 reserved[1776]; + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */ +}; + +void qmgr_set_irq(unsigned int queue, int src, + void (*handler)(void *pdev), void *pdev); +void qmgr_enable_irq(unsigned int queue); +void qmgr_disable_irq(unsigned int queue); + +/* request_ and release_queue() must be called from non-IRQ context */ +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, + unsigned int nearly_empty_watermark, + unsigned int nearly_full_watermark); +void qmgr_release_queue(unsigned int queue); + + +static inline void qmgr_put_entry(unsigned int queue, u32 val) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + __raw_writel(val, &qmgr_regs->acc[queue][0]); +} + +static inline u32 qmgr_get_entry(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return __raw_readl(&qmgr_regs->acc[queue][0]); +} + +static inline int qmgr_get_stat1(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) + >> ((queue & 7) << 2)) & 0xF; +} + +static inline int qmgr_get_stat2(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) + >> ((queue & 0xF) << 1)) & 0x3; +} + +static inline int qmgr_stat_empty(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); +} + +static inline int qmgr_stat_nearly_empty(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); +} + +static inline int qmgr_stat_nearly_full(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); +} + +static inline int qmgr_stat_full(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); +} + +static inline int qmgr_stat_underflow(unsigned int queue) +{ + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); +} + +static inline int qmgr_stat_overflow(unsigned int queue) +{ + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); +} + +#endif diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index f7a35b7..34ef48f 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -13,7 +13,7 @@ #ifndef _ARCH_UNCOMPRESS_H_ #define _ARCH_UNCOMPRESS_H_ -#include +#include "ixp4xx-regs.h" #include #include diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h index 57fcf9f..6b95d77 100644 --- a/include/asm-arm/arch-ks8695/regs-gpio.h +++ b/include/asm-arm/arch-ks8695/regs-gpio.h @@ -49,5 +49,7 @@ #define IOPC_TM_FALLING (4) /* Falling Edge Detection */ #define IOPC_TM_EDGE (6) /* Both Edge Detection */ +/* Port Data Register */ +#define IOPD_(x) (1 << (x)) /* Signal Level of GPIO Pin x */ #endif diff --git a/include/asm-arm/arch-msm/board.h b/include/asm-arm/arch-msm/board.h new file mode 100644 index 0000000..763051f --- /dev/null +++ b/include/asm-arm/arch-msm/board.h @@ -0,0 +1,37 @@ +/* linux/include/asm-arm/arch-msm/board.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_BOARD_H +#define __ASM_ARCH_MSM_BOARD_H + +#include + +/* platform device data structures */ + +struct msm_mddi_platform_data +{ + void (*panel_power)(int on); + unsigned has_vsync_irq:1; +}; + +/* common init routines for use by arch/arm/mach-msm/board-*.c */ + +void __init msm_add_devices(void); +void __init msm_map_common_io(void); +void __init msm_init_irq(void); +void __init msm_init_gpio(void); + +#endif diff --git a/include/asm-arm/arch-msm/debug-macro.S b/include/asm-arm/arch-msm/debug-macro.S new file mode 100644 index 0000000..393d527 --- /dev/null +++ b/include/asm-arm/arch-msm/debug-macro.S @@ -0,0 +1,40 @@ +/* include/asm-arm/arch-msm7200/debug-macro.S + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + + .macro addruart,rx + @ see if the MMU is enabled and select appropriate base address + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, =MSM_UART1_PHYS + ldrne \rx, =MSM_UART1_BASE + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #0x0C] + .endm + + .macro waituart,rd,rx + @ wait for TX_READY +1: ldr \rd, [\rx, #0x08] + tst \rd, #0x04 + beq 1b + .endm + + .macro busyuart,rd,rx + .endm diff --git a/include/asm-arm/arch-msm/dma.h b/include/asm-arm/arch-msm/dma.h new file mode 100644 index 0000000..e4b565b --- /dev/null +++ b/include/asm-arm/arch-msm/dma.h @@ -0,0 +1,151 @@ +/* linux/include/asm-arm/arch-msm/dma.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_DMA_H + +#include +#include + +struct msm_dmov_cmd { + struct list_head list; + unsigned int cmdptr; + void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result); +/* void (*user_result_func)(struct msm_dmov_cmd *cmd); */ +}; + +void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); +void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd); +int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr); +/* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */ + + + +#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) +#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2)) +#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) +#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) + +/* only security domain 3 is available to the ARM11 + * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM + */ + +#define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch) +#define DMOV_CMD_LIST (0 << 29) /* does not work */ +#define DMOV_CMD_PTR_LIST (1 << 29) /* works */ +#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ +#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ +#define DMOV_CMD_ADDR(addr) ((addr) >> 3) + +#define DMOV_RSLT(ch) DMOV_SD3(0x040, ch) +#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ +#define DMOV_RSLT_ERROR (1 << 3) +#define DMOV_RSLT_FLUSH (1 << 2) +#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ +#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ + +#define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch) +#define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch) +#define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch) +#define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch) +#define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch) +#define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch) + +#define DMOV_STATUS(ch) DMOV_SD3(0x200, ch) +#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) +#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) +#define DMOV_STATUS_RSLT_VALID (1 << 1) +#define DMOV_STATUS_CMD_PTR_RDY (1 << 0) + +#define DMOV_ISR DMOV_SD3(0x380, 0) + +#define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch) +#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) +#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) +#define DMOV_CONFIG_IRQ_EN (1 << 0) + +/* channel assignments */ + +#define DMOV_NAND_CHAN 7 +#define DMOV_NAND_CRCI_CMD 5 +#define DMOV_NAND_CRCI_DATA 4 + +#define DMOV_SDC1_CHAN 8 +#define DMOV_SDC1_CRCI 6 + +#define DMOV_SDC2_CHAN 8 +#define DMOV_SDC2_CRCI 7 + +#define DMOV_TSIF_CHAN 10 +#define DMOV_TSIF_CRCI 10 + +#define DMOV_USB_CHAN 11 + +/* no client rate control ifc (eg, ram) */ +#define DMOV_NONE_CRCI 0 + + +/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover + * is going to walk a list of 32bit pointers as described below. Each + * pointer points to a *array* of dmov_s, etc structs. The last pointer + * in the list is marked with CMD_PTR_LP. The last struct in each array + * is marked with CMD_LC (see below). + */ +#define CMD_PTR_ADDR(addr) ((addr) >> 3) +#define CMD_PTR_LP (1 << 31) /* last pointer */ +#define CMD_PTR_PT (3 << 29) /* ? */ + +/* Single Item Mode */ +typedef struct { + unsigned cmd; + unsigned src; + unsigned dst; + unsigned len; +} dmov_s; + +/* Scatter/Gather Mode */ +typedef struct { + unsigned cmd; + unsigned src_dscr; + unsigned dst_dscr; + unsigned _reserved; +} dmov_sg; + +/* bits for the cmd field of the above structures */ + +#define CMD_LC (1 << 31) /* last command */ +#define CMD_FR (1 << 22) /* force result -- does not work? */ +#define CMD_OCU (1 << 21) /* other channel unblock */ +#define CMD_OCB (1 << 20) /* other channel block */ +#define CMD_TCB (1 << 19) /* ? */ +#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/ +#define CMD_SAH (1 << 17) /* source address hold -- does not work? */ + +#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */ +#define CMD_MODE_SG (1 << 0) /* untested */ +#define CMD_MODE_IND_SG (2 << 0) /* untested */ +#define CMD_MODE_BOX (3 << 0) /* untested */ + +#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */ +#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */ +#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */ + +#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */ +#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */ +#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */ + +#define CMD_DST_CRCI(n) (((n) & 15) << 7) +#define CMD_SRC_CRCI(n) (((n) & 15) << 3) + +#endif diff --git a/include/asm-arm/arch-msm/entry-macro.S b/include/asm-arm/arch-msm/entry-macro.S new file mode 100644 index 0000000..ee24aec --- /dev/null +++ b/include/asm-arm/arch-msm/entry-macro.S @@ -0,0 +1,38 @@ +/* include/asm-arm/arch-msm7200/entry-macro.S + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + @ enable imprecise aborts + cpsie a + mov \base, #MSM_VIC_BASE + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ 0xD0 has irq# or old irq# if the irq has been handled + @ 0xD4 has irq# or -1 if none pending *but* if you just + @ read 0xD4 you never get the first irq for some reason + ldr \irqnr, [\base, #0xD0] + ldr \irqnr, [\base, #0xD4] + cmp \irqnr, #0xffffffff + .endm diff --git a/include/asm-arm/arch-msm/hardware.h b/include/asm-arm/arch-msm/hardware.h new file mode 100644 index 0000000..89af2b7 --- /dev/null +++ b/include/asm-arm/arch-msm/hardware.h @@ -0,0 +1,18 @@ +/* linux/include/asm-arm/arch-msm/hardware.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_HARDWARE_H + +#endif diff --git a/include/asm-arm/arch-msm/io.h b/include/asm-arm/arch-msm/io.h new file mode 100644 index 0000000..4645ae2 --- /dev/null +++ b/include/asm-arm/arch-msm/io.h @@ -0,0 +1,33 @@ +/* include/asm-arm/arch-msm/io.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __arch_ioremap __msm_ioremap +#define __arch_iounmap __iounmap + +void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype); + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} +#define __io(a) __io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h new file mode 100644 index 0000000..565430c --- /dev/null +++ b/include/asm-arm/arch-msm/irqs.h @@ -0,0 +1,89 @@ +/* linux/include/asm-arm/arch-msm/irqs.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_IRQS_H + +/* MSM ARM11 Interrupt Numbers */ +/* See 80-VE113-1 A, pp219-221 */ + +#define INT_A9_M2A_0 0 +#define INT_A9_M2A_1 1 +#define INT_A9_M2A_2 2 +#define INT_A9_M2A_3 3 +#define INT_A9_M2A_4 4 +#define INT_A9_M2A_5 5 +#define INT_A9_M2A_6 6 +#define INT_GP_TIMER_EXP 7 +#define INT_DEBUG_TIMER_EXP 8 +#define INT_UART1 9 +#define INT_UART2 10 +#define INT_UART3 11 +#define INT_UART1_RX 12 +#define INT_UART2_RX 13 +#define INT_UART3_RX 14 +#define INT_USB_OTG 15 +#define INT_MDDI_PRI 16 +#define INT_MDDI_EXT 17 +#define INT_MDDI_CLIENT 18 +#define INT_MDP 19 +#define INT_GRAPHICS 20 +#define INT_ADM_AARM 21 +#define INT_ADSP_A11 22 +#define INT_ADSP_A9_A11 23 +#define INT_SDC1_0 24 +#define INT_SDC1_1 25 +#define INT_SDC2_0 26 +#define INT_SDC2_1 27 +#define INT_KEYSENSE 28 +#define INT_TCHSCRN_SSBI 29 +#define INT_TCHSCRN1 30 +#define INT_TCHSCRN2 31 + +#define INT_GPIO_GROUP1 (32 + 0) +#define INT_GPIO_GROUP2 (32 + 1) +#define INT_PWB_I2C (32 + 2) +#define INT_SOFTRESET (32 + 3) +#define INT_NAND_WR_ER_DONE (32 + 4) +#define INT_NAND_OP_DONE (32 + 5) +#define INT_PBUS_ARM11 (32 + 6) +#define INT_AXI_MPU_SMI (32 + 7) +#define INT_AXI_MPU_EBI1 (32 + 8) +#define INT_AD_HSSD (32 + 9) +#define INT_ARM11_PMU (32 + 10) +#define INT_ARM11_DMA (32 + 11) +#define INT_TSIF_IRQ (32 + 12) +#define INT_UART1DM_IRQ (32 + 13) +#define INT_UART1DM_RX (32 + 14) +#define INT_USB_HS (32 + 15) +#define INT_SDC3_0 (32 + 16) +#define INT_SDC3_1 (32 + 17) +#define INT_SDC4_0 (32 + 18) +#define INT_SDC4_1 (32 + 19) +#define INT_UART2DM_RX (32 + 20) +#define INT_UART2DM_IRQ (32 + 21) + +/* 22-31 are reserved */ + +#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31)) + +#define NR_MSM_IRQS 64 +#define NR_GPIO_IRQS 122 +#define NR_BOARD_IRQS 64 +#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) + +#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n)) + +#endif diff --git a/include/asm-arm/arch-msm/memory.h b/include/asm-arm/arch-msm/memory.h new file mode 100644 index 0000000..b5ce0e9 --- /dev/null +++ b/include/asm-arm/arch-msm/memory.h @@ -0,0 +1,27 @@ +/* linux/include/asm-arm/arch-msm/memory.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* physical offset of RAM */ +#define PHYS_OFFSET UL(0x10000000) + +/* bus address and physical addresses are identical */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif + diff --git a/include/asm-arm/arch-msm/msm_iomap.h b/include/asm-arm/arch-msm/msm_iomap.h new file mode 100644 index 0000000..b8955cc --- /dev/null +++ b/include/asm-arm/arch-msm/msm_iomap.h @@ -0,0 +1,104 @@ +/* linux/include/asm-arm/arch-msm/msm_iomap.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * The MSM peripherals are spread all over across 768MB of physical + * space, which makes just having a simple IO_ADDRESS macro to slide + * them into the right virtual location rough. Instead, we will + * provide a master phys->virt mapping for peripherals here. + * + */ + +#ifndef __ASM_ARCH_MSM_IOMAP_H +#define __ASM_ARCH_MSM_IOMAP_H + +#include + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * MSM_VIC_BASE must be an value that can be loaded via a "mov" + * instruction, otherwise entry-macro.S will not compile. + * + * If you add or remove entries here, you'll want to edit the + * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your + * changes. + * + */ + +#define MSM_VIC_BASE 0xE0000000 +#define MSM_VIC_PHYS 0xC0000000 +#define MSM_VIC_SIZE SZ_4K + +#define MSM_CSR_BASE 0xE0001000 +#define MSM_CSR_PHYS 0xC0100000 +#define MSM_CSR_SIZE SZ_4K + +#define MSM_GPT_PHYS MSM_CSR_PHYS +#define MSM_GPT_BASE MSM_CSR_BASE +#define MSM_GPT_SIZE SZ_4K + +#define MSM_DMOV_BASE 0xE0002000 +#define MSM_DMOV_PHYS 0xA9700000 +#define MSM_DMOV_SIZE SZ_4K + +#define MSM_UART1_BASE 0xE0003000 +#define MSM_UART1_PHYS 0xA9A00000 +#define MSM_UART1_SIZE SZ_4K + +#define MSM_UART2_BASE 0xE0004000 +#define MSM_UART2_PHYS 0xA9B00000 +#define MSM_UART2_SIZE SZ_4K + +#define MSM_UART3_BASE 0xE0005000 +#define MSM_UART3_PHYS 0xA9C00000 +#define MSM_UART3_SIZE SZ_4K + +#define MSM_I2C_BASE 0xE0006000 +#define MSM_I2C_PHYS 0xA9900000 +#define MSM_I2C_SIZE SZ_4K + +#define MSM_GPIO1_BASE 0xE0007000 +#define MSM_GPIO1_PHYS 0xA9200000 +#define MSM_GPIO1_SIZE SZ_4K + +#define MSM_GPIO2_BASE 0xE0008000 +#define MSM_GPIO2_PHYS 0xA9300000 +#define MSM_GPIO2_SIZE SZ_4K + +#define MSM_HSUSB_BASE 0xE0009000 +#define MSM_HSUSB_PHYS 0xA0800000 +#define MSM_HSUSB_SIZE SZ_4K + +#define MSM_CLK_CTL_BASE 0xE000A000 +#define MSM_CLK_CTL_PHYS 0xA8600000 +#define MSM_CLK_CTL_SIZE SZ_4K + +#define MSM_PMDH_BASE 0xE000B000 +#define MSM_PMDH_PHYS 0xAA600000 +#define MSM_PMDH_SIZE SZ_4K + +#define MSM_EMDH_BASE 0xE000C000 +#define MSM_EMDH_PHYS 0xAA700000 +#define MSM_EMDH_SIZE SZ_4K + +#define MSM_MDP_BASE 0xE0010000 +#define MSM_MDP_PHYS 0xAA200000 +#define MSM_MDP_SIZE 0x000F0000 + +#define MSM_SHARED_RAM_BASE 0xE0100000 +#define MSM_SHARED_RAM_PHYS 0x01F00000 +#define MSM_SHARED_RAM_SIZE SZ_1M + +#endif diff --git a/include/asm-arm/arch-msm/system.h b/include/asm-arm/arch-msm/system.h new file mode 100644 index 0000000..7c5544b --- /dev/null +++ b/include/asm-arm/arch-msm/system.h @@ -0,0 +1,23 @@ +/* linux/include/asm-arm/arch-msm/system.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +void arch_idle(void); + +static inline void arch_reset(char mode) +{ + for (;;) ; /* depends on IPC w/ other core */ +} diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h new file mode 100644 index 0000000..154b23f --- /dev/null +++ b/include/asm-arm/arch-msm/timex.h @@ -0,0 +1,20 @@ +/* linux/include/asm-arm/arch-msm/timex.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_TIMEX_H + +#define CLOCK_TICK_RATE 1000000 + +#endif diff --git a/include/asm-arm/arch-msm/uncompress.h b/include/asm-arm/arch-msm/uncompress.h new file mode 100644 index 0000000..e91ed78 --- /dev/null +++ b/include/asm-arm/arch-msm/uncompress.h @@ -0,0 +1,36 @@ +/* linux/include/asm-arm/arch-msm/uncompress.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H + +#include "hardware.h" + +static void putc(int c) +{ +} + +static inline void flush(void) +{ +} + +static inline void arch_decomp_setup(void) +{ +} + +static inline void arch_decomp_wdog(void) +{ +} + +#endif diff --git a/include/asm-arm/arch-msm/vmalloc.h b/include/asm-arm/arch-msm/vmalloc.h new file mode 100644 index 0000000..60f8d91 --- /dev/null +++ b/include/asm-arm/arch-msm/vmalloc.h @@ -0,0 +1,22 @@ +/* linux/include/asm-arm/arch-msm/vmalloc.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_VMALLOC_H +#define __ASM_ARCH_MSM_VMALLOC_H + +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) + +#endif + diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S new file mode 100644 index 0000000..e2a8064 --- /dev/null +++ b/include/asm-arm/arch-orion/debug-macro.S @@ -0,0 +1,17 @@ +/* + * linux/include/asm-arm/arch-orion/debug-macro.S + * + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + .macro addruart,rx + mov \rx, #0xf1000000 + orr \rx, \rx, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion/dma.h new file mode 100644 index 0000000..40a8c17 --- /dev/null +++ b/include/asm-arm/arch-orion/dma.h @@ -0,0 +1 @@ +/* empty */ diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S new file mode 100644 index 0000000..b76075a --- /dev/null +++ b/include/asm-arm/arch-orion/entry-macro.S @@ -0,0 +1,31 @@ +/* + * include/asm-arm/arch-orion/entry-macro.S + * + * Low-level IRQ helper macros for Orion platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =MAIN_IRQ_CAUSE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #0] @ main cause + ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask + mov \irqnr, #0 @ default irqnr + @ find cause bits that are unmasked + ands \irqstat, \irqstat, \tmp @ clear Z flag if any + clzne \irqnr, \irqstat @ calc irqnr + rsbne \irqnr, \irqnr, #31 + .endm diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion/gpio.h new file mode 100644 index 0000000..d66284f --- /dev/null +++ b/include/asm-arm/arch-orion/gpio.h @@ -0,0 +1,28 @@ +/* + * include/asm-arm/arch-orion/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +extern int gpio_request(unsigned pin, const char *label); +extern void gpio_free(unsigned pin); +extern int gpio_direction_input(unsigned pin); +extern int gpio_direction_output(unsigned pin, int value); +extern int gpio_get_value(unsigned pin); +extern void gpio_set_value(unsigned pin, int value); +extern void orion_gpio_set_blink(unsigned pin, int blink); +extern void gpio_display(void); /* debug */ + +static inline int gpio_to_irq(int pin) +{ + return pin + IRQ_ORION_GPIO_START; +} + +static inline int irq_to_gpio(int irq) +{ + return irq - IRQ_ORION_GPIO_START; +} + +#include /* cansleep wrappers */ diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h new file mode 100644 index 0000000..8a12d21 --- /dev/null +++ b/include/asm-arm/arch-orion/hardware.h @@ -0,0 +1,24 @@ +/* + * include/asm-arm/arch-orion/hardware.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#define __ASM_ARCH_HARDWARE_H__ + +#include "orion.h" + +#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE +#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE + +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0x1000 +#define PCIBIOS_MIN_MEM 0x01000000 +#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */ + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h new file mode 100644 index 0000000..e0b8c39 --- /dev/null +++ b/include/asm-arm/arch-orion/io.h @@ -0,0 +1,27 @@ +/* + * include/asm-arm/arch-orion/io.h + * + * Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include "orion.h" + +#define IO_SPACE_LIMIT 0xffffffff +#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} + +#define __io(a) __io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h new file mode 100644 index 0000000..eea65ca --- /dev/null +++ b/include/asm-arm/arch-orion/irqs.h @@ -0,0 +1,61 @@ +/* + * include/asm-arm/arch-orion/irqs.h + * + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H__ +#define __ASM_ARCH_IRQS_H__ + +#include "orion.h" /* need GPIO_MAX */ + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION_BRIDGE 0 +#define IRQ_ORION_DOORBELL_H2C 1 +#define IRQ_ORION_DOORBELL_C2H 2 +#define IRQ_ORION_UART0 3 +#define IRQ_ORION_UART1 4 +#define IRQ_ORION_I2C 5 +#define IRQ_ORION_GPIO_0_7 6 +#define IRQ_ORION_GPIO_8_15 7 +#define IRQ_ORION_GPIO_16_23 8 +#define IRQ_ORION_GPIO_24_31 9 +#define IRQ_ORION_PCIE0_ERR 10 +#define IRQ_ORION_PCIE0_INT 11 +#define IRQ_ORION_USB1_CTRL 12 +#define IRQ_ORION_DEV_BUS_ERR 14 +#define IRQ_ORION_PCI_ERR 15 +#define IRQ_ORION_USB_BR_ERR 16 +#define IRQ_ORION_USB0_CTRL 17 +#define IRQ_ORION_ETH_RX 18 +#define IRQ_ORION_ETH_TX 19 +#define IRQ_ORION_ETH_MISC 20 +#define IRQ_ORION_ETH_SUM 21 +#define IRQ_ORION_ETH_ERR 22 +#define IRQ_ORION_IDMA_ERR 23 +#define IRQ_ORION_IDMA_0 24 +#define IRQ_ORION_IDMA_1 25 +#define IRQ_ORION_IDMA_2 26 +#define IRQ_ORION_IDMA_3 27 +#define IRQ_ORION_CESA 28 +#define IRQ_ORION_SATA 29 +#define IRQ_ORION_XOR0 30 +#define IRQ_ORION_XOR1 31 + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) + +#endif /* __ASM_ARCH_IRQS_H__ */ diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion/memory.h new file mode 100644 index 0000000..d954dba --- /dev/null +++ b/include/asm-arm/arch-orion/memory.h @@ -0,0 +1,15 @@ +/* + * include/asm-arm/arch-orion/memory.h + * + * Marvell Orion memory definitions + */ + +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H + +#define PHYS_OFFSET UL(0x00000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h new file mode 100644 index 0000000..f787f75 --- /dev/null +++ b/include/asm-arm/arch-orion/orion.h @@ -0,0 +1,143 @@ +/* + * include/asm-arm/arch-orion/orion.h + * + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION_H__ +#define __ASM_ARCH_ORION_H__ + +/******************************************************************************* + * Orion Address Map + * Use the same mapping (1:1 virtual:physical) of internal registers and + * PCI system (PCI+PCIE) for all machines. + * Each machine defines the rest of its mapping (e.g. device bus flashes) + ******************************************************************************/ +#define ORION_REGS_BASE 0xf1000000 +#define ORION_REGS_SIZE SZ_1M + +#define ORION_PCI_SYS_MEM_BASE 0xe0000000 +#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE +#define ORION_PCIE_MEM_SIZE SZ_128M +#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE) +#define ORION_PCI_MEM_SIZE SZ_128M + +#define ORION_PCI_SYS_IO_BASE 0xf2000000 +#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE +#define ORION_PCIE_IO_SIZE SZ_1M +#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE) +#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE) +#define ORION_PCI_IO_SIZE SZ_1M +#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE) +/* Relevant only for Orion-NAS */ +#define ORION_PCIE_WA_BASE 0xf0000000 +#define ORION_PCIE_WA_SIZE SZ_16M + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ +#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000) +#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000) +#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000) +#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000) +#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000) +#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000) +#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000) +#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000) +#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000) + +#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x)) +#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x)) +#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x)) +#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x)) +#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x)) +#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x)) +#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x)) +#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x)) +#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x)) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010) +#define GPIO_OUT ORION_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108) +#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c) +#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) +#define I2C_BASE ORION_DEV_BUS_REG(0x1000) +#define UART0_BASE ORION_DEV_BUS_REG(0x2000) +#define UART1_BASE ORION_DEV_BUS_REG(0x2100) +#define GPIO_MAX 32 + +/*************************************************************************** + * Orion CPU Bridge Registers + **************************************************************************/ +#define CPU_CONF ORION_BRIDGE_REG(0x100) +#define CPU_CTRL ORION_BRIDGE_REG(0x104) +#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108) +#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c) +#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) +#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) +#define BRIDGE_MASK ORION_BRIDGE_REG(0x114) +#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) +#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) +#define TIMER_CTRL ORION_BRIDGE_REG(0x300) +#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8)) +#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8)) + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Helpers to access Orion registers + ******************************************************************************/ +#include +#include + +#define orion_read(r) __raw_readl(r) +#define orion_write(r, val) __raw_writel(val, r) + +/* + * These are not preempt safe. Locks, if needed, must be taken care by caller. + */ +#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) +#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_ORION_H__ */ diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/arch-orion/platform.h new file mode 100644 index 0000000..143c38e --- /dev/null +++ b/include/asm-arm/arch-orion/platform.h @@ -0,0 +1,25 @@ +/* + * asm-arm/arch-orion/platform.h + * + * Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_PLATFORM_H__ +#define __ASM_ARCH_PLATFORM_H__ + +/* + * Device bus NAND private data + */ +struct orion_nand_data { + struct mtd_partition *parts; + u32 nr_parts; + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 width; /* buswidth */ +}; + +#endif diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion/system.h new file mode 100644 index 0000000..17704c6 --- /dev/null +++ b/include/asm-arm/arch-orion/system.h @@ -0,0 +1,31 @@ +/* + * include/asm-arm/arch-orion/system.h + * + * Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + /* + * Enable and issue soft reset + */ + orion_setbits(CPU_RESET_MASK, (1 << 2)); + orion_setbits(CPU_SOFT_RESET, 1); +} + +#endif diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h new file mode 100644 index 0000000..26c2c91 --- /dev/null +++ b/include/asm-arm/arch-orion/timex.h @@ -0,0 +1,12 @@ +/* + * include/asm-arm/arch-orion/timex.h + * + * Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define ORION_TCLK 166666667 +#define CLOCK_TICK_RATE ORION_TCLK diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h new file mode 100644 index 0000000..a1a222f --- /dev/null +++ b/include/asm-arm/arch-orion/uncompress.h @@ -0,0 +1,44 @@ +/* + * include/asm-arm/arch-orion/uncompress.h + * + * Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + +#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14)) +#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0)) + +#define LSR_THRE 0x20 + +static void putc(const char c) +{ + int j = 0x1000; + while (--j && !(*MV_UART_LSR & LSR_THRE)) + barrier(); + *MV_UART_THR = c; +} + +static void flush(void) +{ +} + +static void orion_early_putstr(const char *ptr) +{ + char c; + while ((c = *ptr++) != '\0') { + if (c == '\n') + putc('\r'); + putc(c); + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h new file mode 100644 index 0000000..23e2a10 --- /dev/null +++ b/include/asm-arm/arch-orion/vmalloc.h @@ -0,0 +1,5 @@ +/* + * include/asm-arm/arch-orion/vmalloc.h + */ + +#define VMALLOC_END 0xf0000000 diff --git a/include/asm-arm/arch-pxa/littleton.h b/include/asm-arm/arch-pxa/littleton.h new file mode 100644 index 0000000..79d209b --- /dev/null +++ b/include/asm-arm/arch-pxa/littleton.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_ZYLONITE_H +#define __ASM_ARCH_ZYLONITE_H + +#define LITTLETON_ETH_PHYS 0x30000000 + +#endif /* __ASM_ARCH_ZYLONITE_H */ diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h new file mode 100644 index 0000000..337f51f --- /dev/null +++ b/include/asm-arm/arch-pxa/magician.h @@ -0,0 +1,111 @@ +/* + * GPIO and IRQ definitions for HTC Magician PDA phones + * + * Copyright (c) 2007 Philipp Zabel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _MAGICIAN_H_ +#define _MAGICIAN_H_ + +#include + +/* + * PXA GPIOs + */ + +#define GPIO0_MAGICIAN_KEY_POWER 0 +#define GPIO9_MAGICIAN_UNKNOWN 9 +#define GPIO10_MAGICIAN_GSM_IRQ 10 +#define GPIO11_MAGICIAN_GSM_OUT1 11 +#define GPIO13_MAGICIAN_CPLD_IRQ 13 +#define GPIO18_MAGICIAN_UNKNOWN 18 +#define GPIO22_MAGICIAN_VIBRA_EN 22 +#define GPIO26_MAGICIAN_GSM_POWER 26 +#define GPIO27_MAGICIAN_USBC_PUEN 27 +#define GPIO30_MAGICIAN_nCHARGE_EN 30 +#define GPIO37_MAGICIAN_KEY_HANGUP 37 +#define GPIO38_MAGICIAN_KEY_CONTACTS 38 +#define GPIO40_MAGICIAN_GSM_OUT2 40 +#define GPIO48_MAGICIAN_UNKNOWN 48 +#define GPIO56_MAGICIAN_UNKNOWN 56 +#define GPIO57_MAGICIAN_CAM_RESET 57 +#define GPIO83_MAGICIAN_nIR_EN 83 +#define GPIO86_MAGICIAN_GSM_RESET 86 +#define GPIO87_MAGICIAN_GSM_SELECT 87 +#define GPIO90_MAGICIAN_KEY_CALENDAR 90 +#define GPIO91_MAGICIAN_KEY_CAMERA 91 +#define GPIO93_MAGICIAN_KEY_UP 93 +#define GPIO94_MAGICIAN_KEY_DOWN 94 +#define GPIO95_MAGICIAN_KEY_LEFT 95 +#define GPIO96_MAGICIAN_KEY_RIGHT 96 +#define GPIO97_MAGICIAN_KEY_ENTER 97 +#define GPIO98_MAGICIAN_KEY_RECORD 98 +#define GPIO99_MAGICIAN_HEADPHONE_IN 99 +#define GPIO100_MAGICIAN_KEY_VOL_UP 100 +#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101 +#define GPIO102_MAGICIAN_KEY_PHONE 102 +#define GPIO103_MAGICIAN_LED_KP 103 +#define GPIO104_MAGICIAN_LCD_POWER_1 104 +#define GPIO105_MAGICIAN_LCD_POWER_2 105 +#define GPIO106_MAGICIAN_LCD_POWER_3 106 +#define GPIO107_MAGICIAN_DS1WM_IRQ 107 +#define GPIO108_MAGICIAN_GSM_READY 108 +#define GPIO114_MAGICIAN_UNKNOWN 114 +#define GPIO115_MAGICIAN_nPEN_IRQ 115 +#define GPIO116_MAGICIAN_nCAM_EN 116 +#define GPIO119_MAGICIAN_UNKNOWN 119 +#define GPIO120_MAGICIAN_UNKNOWN 120 + +/* + * PXA GPIO alternate function mode & direction + */ + +#define GPIO0_MAGICIAN_KEY_POWER_MD (0 | GPIO_IN) +#define GPIO9_MAGICIAN_UNKNOWN_MD (9 | GPIO_IN) +#define GPIO10_MAGICIAN_GSM_IRQ_MD (10 | GPIO_IN) +#define GPIO11_MAGICIAN_GSM_OUT1_MD (11 | GPIO_OUT) +#define GPIO13_MAGICIAN_CPLD_IRQ_MD (13 | GPIO_IN) +#define GPIO18_MAGICIAN_UNKNOWN_MD (18 | GPIO_OUT) +#define GPIO22_MAGICIAN_VIBRA_EN_MD (22 | GPIO_OUT) +#define GPIO26_MAGICIAN_GSM_POWER_MD (26 | GPIO_OUT) +#define GPIO27_MAGICIAN_USBC_PUEN_MD (27 | GPIO_OUT) +#define GPIO30_MAGICIAN_nCHARGE_EN_MD (30 | GPIO_OUT) +#define GPIO37_MAGICIAN_KEY_HANGUP_MD (37 | GPIO_OUT) +#define GPIO38_MAGICIAN_KEY_CONTACTS_MD (38 | GPIO_OUT) +#define GPIO40_MAGICIAN_GSM_OUT2_MD (40 | GPIO_OUT) +#define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT) +#define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT) +#define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT) +#define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT) +#define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT) +#define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT) +#define GPIO90_MAGICIAN_KEY_CALENDAR_MD (90 | GPIO_OUT) +#define GPIO91_MAGICIAN_KEY_CAMERA_MD (91 | GPIO_OUT) +#define GPIO93_MAGICIAN_KEY_UP_MD (93 | GPIO_IN) +#define GPIO94_MAGICIAN_KEY_DOWN_MD (94 | GPIO_IN) +#define GPIO95_MAGICIAN_KEY_LEFT_MD (95 | GPIO_IN) +#define GPIO96_MAGICIAN_KEY_RIGHT_MD (96 | GPIO_IN) +#define GPIO97_MAGICIAN_KEY_ENTER_MD (97 | GPIO_IN) +#define GPIO98_MAGICIAN_KEY_RECORD_MD (98 | GPIO_IN) +#define GPIO99_MAGICIAN_HEADPHONE_IN_MD (99 | GPIO_IN) +#define GPIO100_MAGICIAN_KEY_VOL_UP_MD (100 | GPIO_IN) +#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD (101 | GPIO_IN) +#define GPIO102_MAGICIAN_KEY_PHONE_MD (102 | GPIO_IN) +#define GPIO103_MAGICIAN_LED_KP_MD (103 | GPIO_OUT) +#define GPIO104_MAGICIAN_LCD_POWER_1_MD (104 | GPIO_OUT) +#define GPIO105_MAGICIAN_LCD_POWER_2_MD (105 | GPIO_OUT) +#define GPIO106_MAGICIAN_LCD_POWER_3_MD (106 | GPIO_OUT) +#define GPIO107_MAGICIAN_DS1WM_IRQ_MD (107 | GPIO_IN) +#define GPIO108_MAGICIAN_GSM_READY_MD (108 | GPIO_IN) +#define GPIO114_MAGICIAN_UNKNOWN_MD (114 | GPIO_OUT) +#define GPIO115_MAGICIAN_nPEN_IRQ_MD (115 | GPIO_IN) +#define GPIO116_MAGICIAN_nCAM_EN_MD (116 | GPIO_OUT) +#define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT) +#define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT) + +#endif /* _MAGICIAN_H_ */ diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h index a209966..bb41031 100644 --- a/include/asm-arm/arch-pxa/mfp-pxa300.h +++ b/include/asm-arm/arch-pxa/mfp-pxa300.h @@ -16,6 +16,7 @@ #define __ASM_ARCH_MFP_PXA300_H #include +#include /* GPIO */ #define GPIO46_GPIO MFP_CFG(GPIO46, AF1) diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h index 52deedc..576aa46 100644 --- a/include/asm-arm/arch-pxa/mfp-pxa320.h +++ b/include/asm-arm/arch-pxa/mfp-pxa320.h @@ -16,6 +16,7 @@ #define __ASM_ARCH_MFP_PXA320_H #include +#include /* GPIO */ #define GPIO46_GPIO MFP_CFG(GPIO46, AF0) diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h new file mode 100644 index 0000000..1f6b35c --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa3xx.h @@ -0,0 +1,252 @@ +#ifndef __ASM_ARCH_MFP_PXA3XX_H +#define __ASM_ARCH_MFP_PXA3XX_H + +#define MFPR_BASE (0x40e10000) +#define MFPR_SIZE (PAGE_SIZE) + +/* MFPR register bit definitions */ +#define MFPR_PULL_SEL (0x1 << 15) +#define MFPR_PULLUP_EN (0x1 << 14) +#define MFPR_PULLDOWN_EN (0x1 << 13) +#define MFPR_SLEEP_SEL (0x1 << 9) +#define MFPR_SLEEP_OE_N (0x1 << 7) +#define MFPR_EDGE_CLEAR (0x1 << 6) +#define MFPR_EDGE_FALL_EN (0x1 << 5) +#define MFPR_EDGE_RISE_EN (0x1 << 4) + +#define MFPR_SLEEP_DATA(x) ((x) << 8) +#define MFPR_DRIVE(x) (((x) & 0x7) << 10) +#define MFPR_AF_SEL(x) (((x) & 0x7) << 0) + +#define MFPR_EDGE_NONE (0) +#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) +#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) +#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) + +/* + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) + * + * Input 0 X(0) X(0) X(0) 0 + * Drive 0 0 0 0 X(1) 0 + * Drive 1 0 1 X(1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFPR_LPM_INPUT (0) +#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) +#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) +#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) +#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) +#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) +#define MFPR_LPM_MASK (0xe080) + +/* + * The pullup and pulldown state of the MFP pin at run mode is by default + * determined by the selected alternate function. In case that some buggy + * devices need to override this default behavior, the definitions below + * indicates the setting of corresponding MFPR bits + * + * Definition pull_sel pullup_en pulldown_en + * MFPR_PULL_NONE 0 0 0 + * MFPR_PULL_LOW 1 0 1 + * MFPR_PULL_HIGH 1 1 0 + * MFPR_PULL_BOTH 1 1 1 + */ +#define MFPR_PULL_NONE (0) +#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) +#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) +#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) + +/* PXA3xx common MFP configurations - processor specific ones defined + * in mfp-pxa300.h and mfp-pxa320.h + */ +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) + +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) + +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) + +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) + +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) + +#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) +#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) +#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) +#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) +#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) +#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) +#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) + +/* + * each MFP pin will have a MFPR register, since the offset of the + * register varies between processors, the processor specific code + * should initialize the pin offsets by pxa3xx_mfp_init_addr() + * + * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" + * structure, which represents a range of MFP pins from "start" to + * "end", with the offset begining at "offset", to define a single + * pin, let "end" = -1 + * + * use + * + * MFP_ADDR_X() to define a range of pins + * MFP_ADDR() to define a single pin + * MFP_ADDR_END to signal the end of pin offset definitions + */ +struct pxa3xx_mfp_addr_map { + unsigned int start; + unsigned int end; + unsigned long offset; +}; + +#define MFP_ADDR_X(start, end, offset) \ + { MFP_PIN_##start, MFP_PIN_##end, offset } + +#define MFP_ADDR(pin, offset) \ + { MFP_PIN_##pin, -1, offset } + +#define MFP_ADDR_END { MFP_PIN_INVALID, 0 } + +/* + * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access + * to the MFPR register + */ +unsigned long pxa3xx_mfp_read(int mfp); +void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); + +/* + * pxa3xx_mfp_config - configure the MFPR registers + * + * used by board specific initialization code + */ +void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num); + +/* + * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin + * index and MFPR register offset + * + * used by processor specific code + */ +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); +void __init pxa3xx_init_mfp(void); +#endif /* __ASM_ARCH_MFP_PXA3XX_H */ diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h index 03c508d..02f6157 100644 --- a/include/asm-arm/arch-pxa/mfp.h +++ b/include/asm-arm/arch-pxa/mfp.h @@ -16,9 +16,6 @@ #ifndef __ASM_ARCH_MFP_H #define __ASM_ARCH_MFP_H -#define MFPR_BASE (0x40e10000) -#define MFPR_SIZE (PAGE_SIZE) - #define mfp_to_gpio(m) ((m) % 128) /* list of all the configurable MFP pins */ @@ -217,114 +214,21 @@ enum { }; /* - * Table that determines the low power modes outputs, with actual settings - * used in parentheses for don't-care values. Except for the float output, - * the configured driven and pulled levels match, so if there is a need for - * non-LPM pulled output, the same configuration could probably be used. - * - * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel - * (bit 7) (bit 8) (bit 14d) (bit 13d) - * - * Drive 0 0 0 0 X (1) 0 - * Drive 1 0 1 X (1) 0 0 - * Pull hi (1) 1 X(1) 1 0 0 - * Pull lo (0) 1 X(0) 0 1 0 - * Z (float) 1 X(0) 0 0 0 - */ -#define MFP_LPM_DRIVE_LOW 0x8 -#define MFP_LPM_DRIVE_HIGH 0x6 -#define MFP_LPM_PULL_HIGH 0x7 -#define MFP_LPM_PULL_LOW 0x9 -#define MFP_LPM_FLOAT 0x1 -#define MFP_LPM_PULL_NEITHER 0x0 - -/* - * The pullup and pulldown state of the MFP pin is by default determined by - * selected alternate function. In case some buggy devices need to override - * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of - * the following definition as the parameter. - * - * Definition pull_sel pullup_en pulldown_en - * MFP_PULL_HIGH 1 1 0 - * MFP_PULL_LOW 1 0 1 - * MFP_PULL_BOTH 1 1 1 - * MFP_PULL_NONE 1 0 0 - * MFP_PULL_DEFAULT 0 X X - * - * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN - * bits, which will cause potential conflicts with the low power mode - * setting, device drivers should take care of this - */ -#define MFP_PULL_BOTH (0x7u) -#define MFP_PULL_HIGH (0x6u) -#define MFP_PULL_LOW (0x5u) -#define MFP_PULL_NONE (0x4u) -#define MFP_PULL_DEFAULT (0x0u) - -#define MFP_AF0 (0) -#define MFP_AF1 (1) -#define MFP_AF2 (2) -#define MFP_AF3 (3) -#define MFP_AF4 (4) -#define MFP_AF5 (5) -#define MFP_AF6 (6) -#define MFP_AF7 (7) - -#define MFP_DS01X (0) -#define MFP_DS02X (1) -#define MFP_DS03X (2) -#define MFP_DS04X (3) -#define MFP_DS06X (4) -#define MFP_DS08X (5) -#define MFP_DS10X (6) -#define MFP_DS12X (7) - -#define MFP_EDGE_BOTH 0x3 -#define MFP_EDGE_RISE 0x2 -#define MFP_EDGE_FALL 0x1 -#define MFP_EDGE_NONE 0x0 - -#define MFPR_AF_MASK 0x0007 -#define MFPR_DRV_MASK 0x1c00 -#define MFPR_RDH_MASK 0x0200 -#define MFPR_LPM_MASK 0xe180 -#define MFPR_PULL_MASK 0xe000 -#define MFPR_EDGE_MASK 0x0070 - -#define MFPR_ALT_OFFSET 0 -#define MFPR_ERE_OFFSET 4 -#define MFPR_EFE_OFFSET 5 -#define MFPR_EC_OFFSET 6 -#define MFPR_SON_OFFSET 7 -#define MFPR_SD_OFFSET 8 -#define MFPR_SS_OFFSET 9 -#define MFPR_DRV_OFFSET 10 -#define MFPR_PD_OFFSET 13 -#define MFPR_PU_OFFSET 14 -#define MFPR_PS_OFFSET 15 - -#define MFPR(af, drv, rdh, lpm, edge) \ - (((af) & 0x7) | (((drv) & 0x7) << 10) |\ - (((rdh) & 0x1) << 9) |\ - (((lpm) & 0x3) << 7) |\ - (((lpm) & 0x4) << 12)|\ - (((lpm) & 0x8) << 10)|\ - ((!(edge)) << 6) |\ - (((edge) & 0x1) << 5) |\ - (((edge) & 0x2) << 3)) - -/* * a possible MFP configuration is represented by a 32-bit integer - * bit 0..15 - MFPR value (16-bit) - * bit 16..31 - mfp pin index (used to obtain the MFPR offset) + * + * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) + * bit 10..12 - Alternate Function Selection + * bit 13..15 - Drive Strength + * bit 16..18 - Low Power Mode State + * bit 19..20 - Low Power Mode Edge Detection + * bit 21..22 - Run Mode Pull State * * to facilitate the definition, the following macros are provided * - * MFPR_DEFAULT - default MFPR value, with + * MFP_CFG_DEFAULT - default MFP configuration value, with * alternate function = 0, - * drive strength = fast 1mA (MFP_DS01X) + * drive strength = fast 3mA (MFP_DS03X) * low power mode = default - * release dalay hold = false (RDH bit) * edge detection = none * * MFP_CFG - default MFPR value with alternate function @@ -334,251 +238,74 @@ enum { * low power mode * MFP_CFG_X - default MFPR value with alternate function, * pin drive strength and low power mode - * - * use - * - * MFP_CFG_PIN - to get the MFP pin index - * MFP_CFG_VAL - to get the corresponding MFPR value */ -typedef uint32_t mfp_cfg_t; - -#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff) -#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff) - -/* - * MFP register defaults to - * drive strength fast 3mA (010'b) - * edge detection logic disabled - * alternate function 0 - */ -#define MFPR_DEFAULT (0x0840) +typedef unsigned long mfp_cfg_t; + +#define MFP_PIN(x) ((x) & 0x3ff) + +#define MFP_AF0 (0x0 << 10) +#define MFP_AF1 (0x1 << 10) +#define MFP_AF2 (0x2 << 10) +#define MFP_AF3 (0x3 << 10) +#define MFP_AF4 (0x4 << 10) +#define MFP_AF5 (0x5 << 10) +#define MFP_AF6 (0x6 << 10) +#define MFP_AF7 (0x7 << 10) +#define MFP_AF_MASK (0x7 << 10) +#define MFP_AF(x) (((x) >> 10) & 0x7) + +#define MFP_DS01X (0x0 << 13) +#define MFP_DS02X (0x1 << 13) +#define MFP_DS03X (0x2 << 13) +#define MFP_DS04X (0x3 << 13) +#define MFP_DS06X (0x4 << 13) +#define MFP_DS08X (0x5 << 13) +#define MFP_DS10X (0x6 << 13) +#define MFP_DS13X (0x7 << 13) +#define MFP_DS_MASK (0x7 << 13) +#define MFP_DS(x) (((x) >> 13) & 0x7) + +#define MFP_LPM_INPUT (0x0 << 16) +#define MFP_LPM_DRIVE_LOW (0x1 << 16) +#define MFP_LPM_DRIVE_HIGH (0x2 << 16) +#define MFP_LPM_PULL_LOW (0x3 << 16) +#define MFP_LPM_PULL_HIGH (0x4 << 16) +#define MFP_LPM_FLOAT (0x5 << 16) +#define MFP_LPM_STATE_MASK (0x7 << 16) +#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) + +#define MFP_LPM_EDGE_NONE (0x0 << 19) +#define MFP_LPM_EDGE_RISE (0x1 << 19) +#define MFP_LPM_EDGE_FALL (0x2 << 19) +#define MFP_LPM_EDGE_BOTH (0x3 << 19) +#define MFP_LPM_EDGE_MASK (0x3 << 19) +#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) + +#define MFP_PULL_NONE (0x0 << 21) +#define MFP_PULL_LOW (0x1 << 21) +#define MFP_PULL_HIGH (0x2 << 21) +#define MFP_PULL_BOTH (0x3 << 21) +#define MFP_PULL_MASK (0x3 << 21) +#define MFP_PULL(x) (((x) >> 21) & 0x3) + +#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\ + MFP_LPM_EDGE_NONE | MFP_PULL_NONE) #define MFP_CFG(pin, af) \ - ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af)) + ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) #define MFP_CFG_DRV(pin, af, drv) \ - ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_DRV_MASK) |\ - ((MFP_##drv) << 10) | (MFP_##af)) + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) #define MFP_CFG_LPM(pin, af, lpm) \ - ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_LPM_MASK) |\ - (((MFP_LPM_##lpm) & 0x3) << 7) |\ - (((MFP_LPM_##lpm) & 0x4) << 12) |\ - (((MFP_LPM_##lpm) & 0x8) << 10) |\ - (MFP_##af)) + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) #define MFP_CFG_X(pin, af, drv, lpm) \ - ((MFP_PIN_##pin << 16) |\ - (MFPR_DEFAULT & ~(MFPR_DRV_MASK | MFPR_LPM_MASK)) |\ - ((MFP_##drv) << 10) | (MFP_##af) |\ - (((MFP_LPM_##lpm) & 0x3) << 7) |\ - (((MFP_LPM_##lpm) & 0x4) << 12) |\ - (((MFP_LPM_##lpm) & 0x8) << 10)) - -/* common MFP configurations - processor specific ones defined - * in mfp-pxa3xx.h - */ -#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) -#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) -#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) -#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) -#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) -#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) -#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) -#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) -#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) -#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) -#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) -#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) -#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) -#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) -#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) -#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) -#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) -#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) -#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) -#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) -#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) -#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) -#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) -#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) -#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) -#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) -#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) -#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) -#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) -#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) -#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) -#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) -#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) -#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) -#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) -#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) -#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) -#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) -#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) -#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) -#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) -#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) -#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) -#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) -#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) -#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) - -#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) -#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) - -#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) -#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) -#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) - -#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) - -#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) -#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) -#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) -#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) -#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) -#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) -#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) -#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) -#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) -#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) -#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) -#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) -#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) -#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) -#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) -#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) -#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) -#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) -#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) -#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) -#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) -#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) -#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) -#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) -#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) -#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) -#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) -#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) -#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) -#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) -#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) -#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) -#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) -#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) -#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) -#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) -#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) -#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) -#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) -#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) -#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) -#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) -#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) -#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) -#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) -#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) -#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) -#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) -#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) -#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) -#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) -#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) -#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) -#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) -#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) -#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) -#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) -#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) -#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) -#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) -#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) -#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) -#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) -#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) -#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) - -#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) -#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) -#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) -#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) -#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) -#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) -#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) - -/* - * each MFP pin will have a MFPR register, since the offset of the - * register varies between processors, the processor specific code - * should initialize the pin offsets by pxa3xx_mfp_init_addr() - * - * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" - * structure, which represents a range of MFP pins from "start" to - * "end", with the offset begining at "offset", to define a single - * pin, let "end" = -1 - * - * use - * - * MFP_ADDR_X() to define a range of pins - * MFP_ADDR() to define a single pin - * MFP_ADDR_END to signal the end of pin offset definitions - */ -struct pxa3xx_mfp_addr_map { - unsigned int start; - unsigned int end; - unsigned long offset; -}; - -#define MFP_ADDR_X(start, end, offset) \ - { MFP_PIN_##start, MFP_PIN_##end, offset } - -#define MFP_ADDR(pin, offset) \ - { MFP_PIN_##pin, -1, offset } - -#define MFP_ADDR_END { MFP_PIN_INVALID, 0 } - -struct pxa3xx_mfp_pin { - unsigned long mfpr_off; /* MFPRxx register offset */ - unsigned long mfpr_val; /* MFPRxx register value */ -}; - -/* - * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access - * to the MFPR register - */ -unsigned long pxa3xx_mfp_read(int mfp); -void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); - -/* - * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength - * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off - * pxa3xx_mfp_set_lpm - set MFP low power mode state - * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode - * - * use these functions to override/change the default configuration - * done by pxa3xx_mfp_set_config(s) - */ -void pxa3xx_mfp_set_afds(int mfp, int af, int ds); -void pxa3xx_mfp_set_rdh(int mfp, int rdh); -void pxa3xx_mfp_set_lpm(int mfp, int lpm); -void pxa3xx_mfp_set_edge(int mfp, int edge); - -/* - * pxa3xx_mfp_config - configure the MFPR registers - * - * used by board specific initialization code - */ -void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num); - -/* - * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin - * index and MFPR register offset - * - * used by processor specific code - */ -void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); -void __init pxa3xx_init_mfp(void); + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) #endif /* __ASM_ARCH_MFP_H */ diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index ef4f570..6d1304c 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -17,5 +17,7 @@ struct pxamci_platform_data { }; extern void pxa_set_mci_info(struct pxamci_platform_data *info); +extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info); +extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info); #endif diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 1bd398d..442494d 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1597,176 +1597,10 @@ #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ - /* - * SSP Serial Port Registers - * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. - * PXA255, PXA26x and PXA27x have extra ports, registers and bits. + * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h */ - /* Common PXA2xx bits first */ -#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ -#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ -#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ -#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ -#define SSCR0_National (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ -#if defined(CONFIG_PXA25x) -#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ -#elif defined(CONFIG_PXA27x) -#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ -#define SSCR0_EDSS (1 << 20) /* Extended data size select */ -#define SSCR0_NCS (1 << 21) /* Network clock select */ -#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ -#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ -#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ -#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ -#define SSCR0_ADC (1 << 30) /* Audio clock select */ -#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ -#endif - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ -#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ -#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ -#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ - -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ - -#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */ -#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */ -#define SSCR0_NCS (1 << 21) /* Network Clock Select */ -#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ - -/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ -#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ -#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ -#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ -#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ -#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ -#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ -#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ -#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ -#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ -#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ -#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ -#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ -#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ -#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ -#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ -#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ -#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ - -#define SSSR_BCE (1 << 23) /* Bit Count Error */ -#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ -#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ -#define SSSR_EOC (1 << 20) /* End Of Chain */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ -#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ - -#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ -#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ -#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ -#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ -#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ -#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ -#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ -#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ -#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ - -#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ -#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ -#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ - -#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */ -#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */ -#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */ -#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */ -#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */ - -/* Support existing PXA25x drivers */ -#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */ -#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */ -#define SSSR SSSR_P1 /* SSP Status Register */ -#define SSITR SSITR_P1 /* SSP Interrupt Test Register */ -#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ - -/* PXA27x ports */ -#if defined (CONFIG_PXA27x) -#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */ -#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */ -#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */ -#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */ -#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */ -#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */ -#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */ -#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */ -#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */ -#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */ -#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */ -#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */ -#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */ -#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */ -#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */ -#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */ -#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */ -#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */ -#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */ -#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */ -#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */ -#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */ -#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */ -#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */ -#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */ -#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */ -#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */ -#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */ -#else /* PXA255 (only port 2) and PXA26x ports*/ -#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */ -#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */ -#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */ -#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */ -#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */ -#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */ -#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */ -#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */ -#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */ -#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */ -#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */ -#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */ -#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */ -#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */ -#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */ -#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */ -#endif - -#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL)) -#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL)) -#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL)) -#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL)) -#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL)) -#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL)) -#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL)) -#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL)) -#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL)) -#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL)) -#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) - /* * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h */ @@ -2014,71 +1848,8 @@ #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -/* - * Memory controller - */ - -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -/* - * More handy macros for PCMCIA - * - * Arg is socket number - */ -#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ -#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ -#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ - -/* MECR register defines */ -#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ -#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ - -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - - #ifdef CONFIG_PXA27x -#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - /* * Keypad */ @@ -2135,74 +1906,6 @@ #define KPAS_SO (0x1 << 31) #define KPASMKPx_SO (0x1 << 31) -/* - * UHC: USB Host Controller (OHCI-like) register definitions - */ -#define UHC_BASE_PHYS (0x4C000000) -#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */ -#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */ -#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */ -#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */ -#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */ -#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */ -#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */ -#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */ -#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */ -#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */ -#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */ -#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */ -#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */ -#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */ -#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */ -#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */ -#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */ -#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */ - -#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */ -#define UHCRHDA_NOCP (1 << 12) /* No over current protection */ - -#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */ -#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */ -#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */ -#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */ -#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */ - -#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */ -#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ -#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ -#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ -#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ -#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ -#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ -#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ -#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ -#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ - -#define UHCHR __REG(0x4C000064) /* UHC Reset Register */ -#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ -#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ -#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ -#define UHCHR_PCPL (1 << 7) /* Power control polarity low */ -#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ -#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ -#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ -#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ -#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ -#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ -#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ - -#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/ -#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ -#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ -#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ -#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ -#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort - Interrupt Enable*/ -#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ -#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ - -#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */ - /* Camera Interface */ #define CICR0 __REG(0x50000000) #define CICR1 __REG(0x50000004) @@ -2350,6 +2053,77 @@ #endif +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) +/* + * UHC: USB Host Controller (OHCI-like) register definitions + */ +#define UHC_BASE_PHYS (0x4C000000) +#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */ +#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */ +#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */ +#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */ +#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */ +#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */ +#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */ +#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */ +#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */ +#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */ +#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */ +#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */ +#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */ +#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */ +#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */ +#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */ +#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */ +#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */ + +#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */ +#define UHCRHDA_NOCP (1 << 12) /* No over current protection */ + +#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */ +#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */ +#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */ +#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */ +#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */ + +#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */ +#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ +#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ +#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ +#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ +#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ +#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ +#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ +#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ +#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ + +#define UHCHR __REG(0x4C000064) /* UHC Reset Register */ +#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ +#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ +#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ +#define UHCHR_PCPL (1 << 7) /* Power control polarity low */ +#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ +#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ +#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ +#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ +#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ +#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ +#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ + +#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/ +#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ +#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ +#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ +#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ +#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort + Interrupt Enable*/ +#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ +#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ + +#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */ + +#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ + /* PWRMODE register M field values */ #define PWRMODE_IDLE 0x1 diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h new file mode 100644 index 0000000..9553b54 --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h @@ -0,0 +1,84 @@ +/* + * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h + * + * Taken from pxa-regs.h by Russell King + * + * Author: Nicolas Pitre + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PXA2XX_REGS_H +#define __PXA2XX_REGS_H + +/* + * Memory controller + */ + +#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ +#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ +#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ +#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ +#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ +#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ +#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ +#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ + +/* + * More handy macros for PCMCIA + * + * Arg is socket number + */ +#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ +#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ +#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ + +/* MECR register defines */ +#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ +#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ + +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + + +#ifdef CONFIG_PXA27x + +#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ + +#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ +#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ +#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ +#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ +#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ +#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ +#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ +#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ +#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ + +#endif + +#endif diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h index acc7ec7..3459fb2 100644 --- a/include/asm-arm/arch-pxa/pxa2xx_spi.h +++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h @@ -22,32 +22,8 @@ #define PXA2XX_CS_ASSERT (0x01) #define PXA2XX_CS_DEASSERT (0x02) -#if defined(CONFIG_PXA25x) -#define CLOCK_SPEED_HZ 3686400 -#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00) -#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00) -#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00) -#elif defined(CONFIG_PXA27x) -#define CLOCK_SPEED_HZ 13000000 -#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00) -#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00) -#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00) -#endif - -#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1))))) -#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2))))) -#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3))))) - -enum pxa_ssp_type { - SSP_UNDEFINED = 0, - PXA25x_SSP, /* pxa 210, 250, 255, 26x */ - PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ - PXA27x_SSP, -}; - /* device.platform_data for SSP controller devices */ struct pxa2xx_spi_master { - enum pxa_ssp_type ssp_type; u32 clock_enable; u16 num_chipselect; u8 enable_dma; diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h index 3900a0c..66d5411 100644 --- a/include/asm-arm/arch-pxa/pxa3xx-regs.h +++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h @@ -14,6 +14,92 @@ #define __ASM_ARCH_PXA3XX_REGS_H /* + * Slave Power Managment Unit + */ +#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ +#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ +#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ +#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ +#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ +#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ +#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ +#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ +#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ +#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ +#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ +#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ +#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ +#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ + +/* + * Application Subsystem Configuration bits. + */ +#define ASCR_RDH (1 << 31) +#define ASCR_D1S (1 << 2) +#define ASCR_D2S (1 << 1) +#define ASCR_D3S (1 << 0) + +/* + * Application Reset Status bits. + */ +#define ARSR_GPR (1 << 3) +#define ARSR_LPMR (1 << 2) +#define ARSR_WDT (1 << 1) +#define ARSR_HWR (1 << 0) + +/* + * Application Subsystem Wake-Up bits. + */ +#define ADXER_WRTC (1 << 31) /* RTC */ +#define ADXER_WOST (1 << 30) /* OS Timer */ +#define ADXER_WTSI (1 << 29) /* Touchscreen */ +#define ADXER_WUSBH (1 << 28) /* USB host */ +#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ +#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ +#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ +#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ +#define ADXER_WKP (1 << 21) /* Keypad */ +#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ +#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ +#define ADXER_WOTG (1 << 16) /* USBOTG input */ +#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ +#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ +#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ +#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ +#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ +#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ +#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ +#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ +#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ +#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ +#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ +#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ +#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ +#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ +#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ +#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ + +/* + * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. + */ +#define ADXR_L2 (1 << 8) +#define ADXR_R5 (1 << 5) +#define ADXR_R4 (1 << 4) +#define ADXR_R3 (1 << 3) +#define ADXR_R2 (1 << 2) +#define ADXR_R1 (1 << 1) +#define ADXR_R0 (1 << 0) + +/* + * Values for PWRMODE CP15 register + */ +#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ +#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ +#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ +#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ +#define PXA3xx_PM_S0D0C1 0x01 + +/* * Application Subsystem Clock */ #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h new file mode 100644 index 0000000..991cb68 --- /dev/null +++ b/include/asm-arm/arch-pxa/regs-ssp.h @@ -0,0 +1,112 @@ +#ifndef __ASM_ARCH_REGS_SSP_H +#define __ASM_ARCH_REGS_SSP_H + +/* + * SSP Serial Port Registers + * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. + * PXA255, PXA26x and PXA27x have extra ports, registers and bits. + */ + +#define SSCR0 (0x00) /* SSP Control Register 0 */ +#define SSCR1 (0x04) /* SSP Control Register 1 */ +#define SSSR (0x08) /* SSP Status Register */ +#define SSITR (0x0C) /* SSP Interrupt Test Register */ +#define SSDR (0x10) /* SSP Data Write/Data Read Register */ + +#define SSTO (0x28) /* SSP Time Out Register */ +#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ +#define SSTSA (0x30) /* SSP Tx Timeslot Active */ +#define SSRSA (0x34) /* SSP Rx Timeslot Active */ +#define SSTSS (0x38) /* SSP Timeslot Status */ +#define SSACD (0x3C) /* SSP Audio Clock Divider */ + +/* Common PXA2xx bits first */ +#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ +#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ +#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ +#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ +#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ +#define SSCR0_National (0x2 << 4) /* National Microwire */ +#define SSCR0_ECS (1 << 6) /* External clock select */ +#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ +#if defined(CONFIG_PXA25x) +#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ +#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ +#elif defined(CONFIG_PXA27x) +#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ +#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ +#define SSCR0_EDSS (1 << 20) /* Extended data size select */ +#define SSCR0_NCS (1 << 21) /* Network clock select */ +#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ +#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ +#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ +#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ +#define SSCR0_ADC (1 << 30) /* Audio clock select */ +#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ +#endif + +#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ +#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ +#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ +#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ +#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ +#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ +#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ +#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ +#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ +#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ + +#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ +#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ +#define SSSR_BSY (1 << 4) /* SSP Busy */ +#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ +#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ +#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ + +#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */ +#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */ +#define SSCR0_NCS (1 << 21) /* Network Clock Select */ +#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ + +/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ +#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ +#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ +#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ +#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ +#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ +#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ +#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ +#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ +#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ +#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ +#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ +#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ +#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ +#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ +#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ +#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ +#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ +#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ + +#define SSSR_BCE (1 << 23) /* Bit Count Error */ +#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ +#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ +#define SSSR_EOC (1 << 20) /* End Of Chain */ +#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ +#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ + +#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ +#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ +#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ +#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ +#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ +#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ +#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ +#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ +#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ + +#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ +#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ +#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ + +#endif /* __ASM_ARCH_REGS_SSP_H */ diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h index ea20055..a012882 100644 --- a/include/asm-arm/arch-pxa/ssp.h +++ b/include/asm-arm/arch-pxa/ssp.h @@ -13,10 +13,37 @@ * PXA255 SSP, NSSP * PXA26x SSP, NSSP, ASSP * PXA27x SSP1, SSP2, SSP3 + * PXA3xx SSP1, SSP2, SSP3, SSP4 */ -#ifndef SSP_H -#define SSP_H +#ifndef __ASM_ARCH_SSP_H +#define __ASM_ARCH_SSP_H + +#include + +enum pxa_ssp_type { + SSP_UNDEFINED = 0, + PXA25x_SSP, /* pxa 210, 250, 255, 26x */ + PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ + PXA27x_SSP, +}; + +struct ssp_device { + struct platform_device *pdev; + struct list_head node; + + struct clk *clk; + void __iomem *mmio_base; + unsigned long phys_base; + + const char *label; + int port_id; + int type; + int use_count; + int irq; + int drcmr_rx; + int drcmr_tx; +}; /* * SSP initialisation flags @@ -31,6 +58,7 @@ struct ssp_state { }; struct ssp_dev { + struct ssp_device *ssp; u32 port; u32 mode; u32 flags; @@ -50,4 +78,6 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); void ssp_exit(struct ssp_dev *dev); -#endif +struct ssp_device *ssp_request(int port, const char *label); +void ssp_free(struct ssp_device *); +#endif /* __ASM_ARCH_SSP_H */ diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h index 178aa2e..dadf4c2 100644 --- a/include/asm-arm/arch-pxa/uncompress.h +++ b/include/asm-arm/arch-pxa/uncompress.h @@ -9,19 +9,21 @@ * published by the Free Software Foundation. */ -#define FFUART ((volatile unsigned long *)0x40100000) -#define BTUART ((volatile unsigned long *)0x40200000) -#define STUART ((volatile unsigned long *)0x40700000) -#define HWUART ((volatile unsigned long *)0x41600000) +#include +#include + +#define __REG(x) ((volatile unsigned long *)x) #define UART FFUART static inline void putc(char c) { - while (!(UART[5] & 0x20)) + if (!(UART[UART_IER] & IER_UUE)) + return; + while (!(UART[UART_LSR] & LSR_TDRQ)) barrier(); - UART[0] = c; + UART[UART_TX] = c; } /* diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h index f58b591..5f717d6 100644 --- a/include/asm-arm/arch-pxa/zylonite.h +++ b/include/asm-arm/arch-pxa/zylonite.h @@ -3,9 +3,18 @@ #define ZYLONITE_ETH_PHYS 0x14000000 +#define EXT_GPIO(x) (128 + (x)) + /* the following variables are processor specific and initialized * by the corresponding zylonite_pxa3xx_init() */ +struct platform_mmc_slot { + int gpio_cd; + int gpio_wp; +}; + +extern struct platform_mmc_slot zylonite_mmc_slot[]; + extern int gpio_backlight; extern int gpio_eth_irq; diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h new file mode 100644 index 0000000..3e437b7 --- /dev/null +++ b/include/asm-arm/arch-realview/board-eb.h @@ -0,0 +1,171 @@ +/* + * include/asm-arm/arch-realview/board-eb.h + * + * Copyright (C) 2007 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_BOARD_EB_H +#define __ASM_ARCH_BOARD_EB_H + +#include + +/* + * RealView EB + ARM11MPCore peripheral addresses + */ +#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB +#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ +#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_EB11MP_TWD_BASE 0x10100700 +#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ +#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ +#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ +#else +#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ +#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_EB11MP_TWD_BASE 0x1F000700 +#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ +#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ +#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ +#endif + +#define IRQ_EB_GIC_START 32 + +/* + * RealView EB interrupt sources + */ +#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */ +#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */ +#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */ +#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */ +#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */ +#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */ +#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */ +#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */ +#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */ +#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */ +#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */ +#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */ +#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */ +#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */ +#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */ +#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */ + +/* + * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile) + */ +#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0) +#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1) +#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2) +#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3) +#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4) +#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5) +#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6) +#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7) +#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8) +#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9) +#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */ +#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */ +#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */ +#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */ +#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14) +#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15) + +#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17) +#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18) +#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19) +#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20) +#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21) +#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22) +#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23) +#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24) +#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25) +#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26) +#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27) +#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28) + +#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29) +#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) +#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) + +#define IRQ_EB11MP_UART2 -1 +#define IRQ_EB11MP_UART3 -1 +#define IRQ_EB11MP_CLCD -1 +#define IRQ_EB11MP_DMA -1 +#define IRQ_EB11MP_WDOG -1 +#define IRQ_EB11MP_GPIO0 -1 +#define IRQ_EB11MP_GPIO1 -1 +#define IRQ_EB11MP_GPIO2 -1 +#define IRQ_EB11MP_SCI -1 +#define IRQ_EB11MP_SSP -1 + +#define NR_GIC_EB11MP 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_EB + */ +#define NR_IRQS_EB (IRQ_EB_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_EB) \ + && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB)) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_EB +#endif + +#if defined(CONFIG_REALVIEW_EB_ARM11MP) \ + && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_EB11MP +#endif + +/* + * Core tile identification (REALVIEW_SYS_PROCID) + */ +#define REALVIEW_EB_PROC_MASK 0xFF000000 +#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000 +#define REALVIEW_EB_PROC_ARM9 0x02000000 +#define REALVIEW_EB_PROC_ARM11 0x04000000 +#define REALVIEW_EB_PROC_ARM11MP 0x06000000 + +#define check_eb_proc(proc_type) \ + ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \ + == proc_type) + +#ifdef CONFIG_REALVIEW_EB_ARM11MP +#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP) +#else +#define core_tile_eb11mp() 0 +#endif + +#endif /* __ASM_ARCH_BOARD_EB_H */ diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 3b4e207..ff014d9 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -9,12 +9,14 @@ */ #include #include +#include .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h index aa78fe0..bad8d7c 100644 --- a/include/asm-arm/arch-realview/hardware.h +++ b/include/asm-arm/arch-realview/hardware.h @@ -23,7 +23,6 @@ #define __ASM_ARCH_HARDWARE_H #include -#include /* macro to get at IO space when running virtually */ #define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h index 5a5db56..ad0c911 100644 --- a/include/asm-arm/arch-realview/irqs.h +++ b/include/asm-arm/arch-realview/irqs.h @@ -19,103 +19,18 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 +#include -/* - * IRQ interrupts definitions are the same the INT definitions - * held within platform.h - */ -#define IRQ_GIC_START 32 -#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT) -#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT) -#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx) -#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx) -#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1) -#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3) -#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0) -#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1) -#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2) -#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3) -#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT) -#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT) -#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0) -#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1) -#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2) -#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3) -#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT) -#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT) -#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT) -#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT) -#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT) -#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT) -#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B) -#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B) -#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0) -#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1) -#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3) -#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD) -#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH) -#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD) -#define IRQ_DoC (IRQ_GIC_START + INT_DoC) -#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A) -#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A) -#define IRQ_AACI (IRQ_GIC_START + INT_AACI) -#define IRQ_ETH (IRQ_GIC_START + INT_ETH) -#define IRQ_USB (IRQ_GIC_START + INT_USB) -#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0) -#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1) -#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2) -#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3) -#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0) -#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1) -#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2) -#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3) -#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4) -#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5) -#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6) -#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7) +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 -#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) -#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2) +#define IRQ_GIC_START 32 -#define IRQMASK_WDOGINT INTMASK_WDOGINT -#define IRQMASK_SOFTINT INTMASK_SOFTINT -#define IRQMASK_COMMRx INTMASK_COMMRx -#define IRQMASK_COMMTx INTMASK_COMMTx -#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 -#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 -#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 -#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 -#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 -#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 -#define IRQMASK_RTCINT INTMASK_RTCINT -#define IRQMASK_SSPINT INTMASK_SSPINT -#define IRQMASK_UARTINT0 INTMASK_UARTINT0 -#define IRQMASK_UARTINT1 INTMASK_UARTINT1 -#define IRQMASK_UARTINT2 INTMASK_UARTINT2 -#define IRQMASK_SCIINT INTMASK_SCIINT -#define IRQMASK_CLCDINT INTMASK_CLCDINT -#define IRQMASK_DMAINT INTMASK_DMAINT -#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT -#define IRQMASK_MBXINT INTMASK_MBXINT -#define IRQMASK_GNDINT INTMASK_GNDINT -#define IRQMASK_MMCI0B INTMASK_MMCI0B -#define IRQMASK_MMCI1B INTMASK_MMCI1B -#define IRQMASK_KMI0 INTMASK_KMI0 -#define IRQMASK_KMI1 INTMASK_KMI1 -#define IRQMASK_SCI3 INTMASK_SCI3 -#define IRQMASK_UART3 INTMASK_UART3 -#define IRQMASK_CLCD INTMASK_CLCD -#define IRQMASK_TOUCH INTMASK_TOUCH -#define IRQMASK_KEYPAD INTMASK_KEYPAD -#define IRQMASK_DoC INTMASK_DoC -#define IRQMASK_MMCI0A INTMASK_MMCI0A -#define IRQMASK_MMCI1A INTMASK_MMCI1A -#define IRQMASK_AACI INTMASK_AACI -#define IRQMASK_ETH INTMASK_ETH -#define IRQMASK_USB INTMASK_USB +#ifndef NR_IRQS +#error "NR_IRQS not defined by the board-specific files" +#endif -#define NR_IRQS (IRQ_GIC_START + 96) +#endif diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h index 6e0eab9..4fd351b 100644 --- a/include/asm-arm/arch-realview/platform.h +++ b/include/asm-arm/arch-realview/platform.h @@ -18,8 +18,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __address_h -#define __address_h 1 +#ifndef __ASM_ARCH_PLATFORM_H +#define __ASM_ARCH_PLATFORM_H /* * Memory definitions @@ -81,11 +81,12 @@ #define REALVIEW_SYS_24MHz_OFFSET 0x5C #define REALVIEW_SYS_MISC_OFFSET 0x60 #define REALVIEW_SYS_IOSEL_OFFSET 0x70 -#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 -#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 -#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 -#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C -#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 +#define REALVIEW_SYS_PROCID_OFFSET 0x84 +#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 +#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 +#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 +#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC +#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 #define REALVIEW_SYS_BASE 0x10000000 #define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) @@ -114,6 +115,7 @@ #define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) #define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) #define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) +#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) #define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) #define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) #define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) @@ -203,30 +205,8 @@ /* Reserved 0x1001A000 - 0x1001FFFF */ #define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ -#ifndef CONFIG_REALVIEW_MPCORE #define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ #define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ -#else -#ifdef CONFIG_REALVIEW_MPCORE_REVB -#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */ -#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_TWD_BASE 0x10100700 -#define REALVIEW_TWD_SIZE 0x00000100 -#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ -#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */ -#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ -#else -#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */ -#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_TWD_BASE 0x1F000700 -#define REALVIEW_TWD_SIZE 0x00000100 -#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ -#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */ -#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ -#endif -#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ -#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ -#endif #define REALVIEW_SMC_BASE 0x10080000 /* SMC */ /* Reserved 0x10090000 - 0x100EFFFF */ @@ -283,134 +263,6 @@ #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ -/* ------------------------------------------------------------------------ - * Interrupts - bit assignment (primary) - * ------------------------------------------------------------------------ - */ -#ifndef CONFIG_REALVIEW_MPCORE -#define INT_WDOGINT 0 /* Watchdog timer */ -#define INT_SOFTINT 1 /* Software interrupt */ -#define INT_COMMRx 2 /* Debug Comm Rx interrupt */ -#define INT_COMMTx 3 /* Debug Comm Tx interrupt */ -#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ -#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ -#define INT_GPIOINT0 6 /* GPIO 0 */ -#define INT_GPIOINT1 7 /* GPIO 1 */ -#define INT_GPIOINT2 8 /* GPIO 2 */ -/* 9 reserved */ -#define INT_RTCINT 10 /* Real Time Clock */ -#define INT_SSPINT 11 /* Synchronous Serial Port */ -#define INT_UARTINT0 12 /* UART 0 on development chip */ -#define INT_UARTINT1 13 /* UART 1 on development chip */ -#define INT_UARTINT2 14 /* UART 2 on development chip */ -#define INT_UARTINT3 15 /* UART 3 on development chip */ -#define INT_SCIINT 16 /* Smart Card Interface */ -#define INT_MMCI0A 17 /* Multimedia Card 0A */ -#define INT_MMCI0B 18 /* Multimedia Card 0B */ -#define INT_AACI 19 /* Audio Codec */ -#define INT_KMI0 20 /* Keyboard/Mouse port 0 */ -#define INT_KMI1 21 /* Keyboard/Mouse port 1 */ -#define INT_CHARLCD 22 /* Character LCD */ -#define INT_CLCDINT 23 /* CLCD controller */ -#define INT_DMAINT 24 /* DMA controller */ -#define INT_PWRFAILINT 25 /* Power failure */ -#define INT_PISMO 26 -#define INT_DoC 27 /* Disk on Chip memory controller */ -#define INT_ETH 28 /* Ethernet controller */ -#define INT_USB 29 /* USB controller */ -#define INT_TSPENINT 30 /* Touchscreen pen */ -#define INT_TSKPADINT 31 /* Touchscreen keypad */ - -#else - -#define MAX_GIC_NR 2 - -#define INT_AACI 0 -#define INT_TIMERINT0_1 1 -#define INT_TIMERINT2_3 2 -#define INT_USB 3 -#define INT_UARTINT0 4 -#define INT_UARTINT1 5 -#define INT_RTCINT 6 -#define INT_KMI0 7 -#define INT_KMI1 8 -#define INT_ETH 9 -#define INT_EB_IRQ1 10 /* main GIC */ -#define INT_EB_IRQ2 11 /* tile GIC */ -#define INT_EB_FIQ1 12 /* main GIC */ -#define INT_EB_FIQ2 13 /* tile GIC */ -#define INT_MMCI0A 14 -#define INT_MMCI0B 15 - -#define INT_PMU_CPU0 17 -#define INT_PMU_CPU1 18 -#define INT_PMU_CPU2 19 -#define INT_PMU_CPU3 20 -#define INT_PMU_SCU0 21 -#define INT_PMU_SCU1 22 -#define INT_PMU_SCU2 23 -#define INT_PMU_SCU3 24 -#define INT_PMU_SCU4 25 -#define INT_PMU_SCU5 26 -#define INT_PMU_SCU6 27 -#define INT_PMU_SCU7 28 - -#define INT_L220_EVENT 29 -#define INT_L220_SLAVE 30 -#define INT_L220_DECODE 31 - -#define INT_UARTINT2 -1 -#define INT_UARTINT3 -1 -#define INT_CLCDINT -1 -#define INT_DMAINT -1 -#define INT_WDOGINT -1 -#define INT_GPIOINT0 -1 -#define INT_GPIOINT1 -1 -#define INT_GPIOINT2 -1 -#define INT_SCIINT -1 -#define INT_SSPINT -1 -#endif - -/* - * Interrupt bit positions - * - */ -#define INTMASK_WDOGINT (1 << INT_WDOGINT) -#define INTMASK_SOFTINT (1 << INT_SOFTINT) -#define INTMASK_COMMRx (1 << INT_COMMRx) -#define INTMASK_COMMTx (1 << INT_COMMTx) -#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) -#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) -#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) -#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) -#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) -#define INTMASK_RTCINT (1 << INT_RTCINT) -#define INTMASK_SSPINT (1 << INT_SSPINT) -#define INTMASK_UARTINT0 (1 << INT_UARTINT0) -#define INTMASK_UARTINT1 (1 << INT_UARTINT1) -#define INTMASK_UARTINT2 (1 << INT_UARTINT2) -#define INTMASK_UARTINT3 (1 << INT_UARTINT3) -#define INTMASK_SCIINT (1 << INT_SCIINT) -#define INTMASK_MMCI0A (1 << INT_MMCI0A) -#define INTMASK_MMCI0B (1 << INT_MMCI0B) -#define INTMASK_AACI (1 << INT_AACI) -#define INTMASK_KMI0 (1 << INT_KMI0) -#define INTMASK_KMI1 (1 << INT_KMI1) -#define INTMASK_CHARLCD (1 << INT_CHARLCD) -#define INTMASK_CLCDINT (1 << INT_CLCDINT) -#define INTMASK_DMAINT (1 << INT_DMAINT) -#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) -#define INTMASK_PISMO (1 << INT_PISMO) -#define INTMASK_DoC (1 << INT_DoC) -#define INTMASK_ETH (1 << INT_ETH) -#define INTMASK_USB (1 << INT_USB) -#define INTMASK_TSPENINT (1 << INT_TSPENINT) -#define INTMASK_TSKPADINT (1 << INT_TSKPADINT) - -#define MAXIRQNUM 31 -#define MAXFIQNUM 31 -#define MAXSWINUM 31 - /* * Application Flash * @@ -463,6 +315,4 @@ #define REALVIEW_CSR_BASE 0x10000000 #define REALVIEW_CSR_SIZE 0x10000000 -#endif - -/* END */ +#endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h index cc29364..08b3db8 100644 --- a/include/asm-arm/arch-realview/scu.h +++ b/include/asm-arm/arch-realview/scu.h @@ -1,8 +1,8 @@ #ifndef __ASMARM_ARCH_SCU_H #define __ASMARM_ARCH_SCU_H -#include +#include -#define SCU_BASE REALVIEW_MPCORE_SCU_BASE +#define SCU_BASE REALVIEW_EB11MP_SCU_BASE #endif diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h index f05631d..1cf4149 100644 --- a/include/asm-arm/arch-realview/uncompress.h +++ b/include/asm-arm/arch-realview/uncompress.h @@ -19,6 +19,8 @@ */ #include +#include + #define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) #define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) #define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 6c1c968..759a97b 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -94,6 +94,14 @@ # endif #endif +#if defined(CONFIG_CPU_FEROCEON) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE feroceon +# endif +#endif + #if defined(CONFIG_CPU_V6) //# ifdef _CACHE # define MULTI_CACHE 1 diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h index f31cda5..392eb53 100644 --- a/include/asm-arm/fpstate.h +++ b/include/asm-arm/fpstate.h @@ -17,14 +17,18 @@ /* * VFP storage area has: * - FPEXC, FPSCR, FPINST and FPINST2. - * - 16 double precision data registers - * - an implementation-dependant word of state for FLDMX/FSTMX + * - 16 or 32 double precision data registers + * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6) * * FPEXC will always be non-zero once the VFP has been used in this process. */ struct vfp_hard_struct { +#ifdef CONFIG_VFPv3 + __u64 fpregs[32]; +#else __u64 fpregs[16]; +#endif #if __LINUX_ARM_ARCH__ < 6 __u32 fpmx_state; #endif @@ -35,6 +39,7 @@ struct vfp_hard_struct { */ __u32 fpinst; __u32 fpinst2; + #ifdef CONFIG_SMP __u32 cpu; #endif diff --git a/include/asm-arm/hardware/arm_twd.h b/include/asm-arm/hardware/arm_twd.h index 131d5b4..e521b70 100644 --- a/include/asm-arm/hardware/arm_twd.h +++ b/include/asm-arm/hardware/arm_twd.h @@ -1,7 +1,7 @@ #ifndef __ASM_HARDWARE_TWD_H #define __ASM_HARDWARE_TWD_H -#define TWD_TIMER_LOAD 0x00 +#define TWD_TIMER_LOAD 0x00 #define TWD_TIMER_COUNTER 0x04 #define TWD_TIMER_CONTROL 0x08 #define TWD_TIMER_INTSTAT 0x0C @@ -13,4 +13,9 @@ #define TWD_WDOG_RESETSTAT 0x30 #define TWD_WDOG_DISABLE 0x34 +#define TWD_TIMER_CONTROL_ENABLE (1 << 0) +#define TWD_TIMER_CONTROL_ONESHOT (0 << 1) +#define TWD_TIMER_CONTROL_PERIODIC (1 << 1) +#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) + #endif diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 5599d4e..a4ce457 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -185,6 +185,14 @@ # define CPU_NAME cpu_xsc3 # endif # endif +# ifdef CONFIG_CPU_FEROCEON +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_feroceon +# endif +# endif # ifdef CONFIG_CPU_V6 # ifdef CPU_NAME # undef MULTI_CPU diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index f67acce..ae0a31e 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -61,6 +61,11 @@ extern void smp_cross_call(cpumask_t callmap); extern void smp_send_timer(void); /* + * Broadcast a clock event to other CPUs. + */ +extern void smp_timer_broadcast(cpumask_t mask); + +/* * Boot a secondary CPU, and assign it the specified idle task. * This also gives us the initial stack to use for this CPU. */ @@ -96,6 +101,11 @@ extern void platform_cpu_die(unsigned int cpu); extern int platform_cpu_kill(unsigned int cpu); extern void platform_cpu_enable(unsigned int cpu); +/* + * Local timer interrupt handling function (can be IPI'ed). + */ +extern void local_timer_interrupt(void); + #ifdef CONFIG_LOCAL_TIMERS /* * Setup a local timer interrupt for a CPU. @@ -112,6 +122,10 @@ extern void local_timer_stop(unsigned int cpu); */ extern int local_timer_ack(void); +static inline void dummy_timer_setup(unsigned int cpu) +{ +} + #else static inline void local_timer_setup(unsigned int cpu) @@ -122,6 +136,8 @@ static inline void local_timer_stop(unsigned int cpu) { } +extern void dummy_timer_setup(unsigned int cpu); + #endif /* diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h index bd6be9d..5f9a2cb 100644 --- a/include/asm-arm/vfp.h +++ b/include/asm-arm/vfp.h @@ -7,7 +7,11 @@ #define FPSID cr0 #define FPSCR cr1 +#define MVFR1 cr6 +#define MVFR0 cr7 #define FPEXC cr8 +#define FPINST cr9 +#define FPINST2 cr10 /* FPSID bits */ #define FPSID_IMPLEMENTER_BIT (24) @@ -28,6 +32,19 @@ /* FPEXC bits */ #define FPEXC_EX (1 << 31) #define FPEXC_EN (1 << 30) +#define FPEXC_DEX (1 << 29) +#define FPEXC_FP2V (1 << 28) +#define FPEXC_VV (1 << 27) +#define FPEXC_TFV (1 << 26) +#define FPEXC_LENGTH_BIT (8) +#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) +#define FPEXC_IDF (1 << 7) +#define FPEXC_IXF (1 << 4) +#define FPEXC_UFF (1 << 3) +#define FPEXC_OFF (1 << 2) +#define FPEXC_DZF (1 << 1) +#define FPEXC_IOF (1 << 0) +#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) /* FPSCR bits */ #define FPSCR_DEFAULT_NAN (1<<25) @@ -55,20 +72,9 @@ #define FPSCR_IXC (1<<4) #define FPSCR_IDC (1<<7) -/* - * VFP9-S specific. - */ -#define FPINST cr9 -#define FPINST2 cr10 - -/* FPEXC bits */ -#define FPEXC_FPV2 (1<<28) -#define FPEXC_LENGTH_BIT (8) -#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) -#define FPEXC_INV (1 << 7) -#define FPEXC_UFC (1 << 3) -#define FPEXC_OFC (1 << 2) -#define FPEXC_IOC (1 << 0) +/* MVFR0 bits */ +#define MVFR0_A_SIMD_BIT (0) +#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) /* Bit patterns for decoding the packaged operation descriptors */ #define VFPOPDESC_LENGTH_BIT (9) diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h index 27fe028..cccb389 100644 --- a/include/asm-arm/vfpmacros.h +++ b/include/asm-arm/vfpmacros.h @@ -15,19 +15,33 @@ .endm @ read all the working registers back into the VFP - .macro VFPFLDMIA, base + .macro VFPFLDMIA, base, tmp #if __LINUX_ARM_ARCH__ < 6 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} #else LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} #endif +#ifdef CONFIG_VFPv3 + VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 + and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field + cmp \tmp, #2 @ 32 x 64bit registers? + ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} + addne \base, \base, #32*4 @ step over unused register space +#endif .endm @ write all the working registers out of the VFP - .macro VFPFSTMIA, base + .macro VFPFSTMIA, base, tmp #if __LINUX_ARM_ARCH__ < 6 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} #else STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} #endif +#ifdef CONFIG_VFPv3 + VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 + and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field + cmp \tmp, #2 @ 32 x 64bit registers? + stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} + addne \base, \base, #32*4 @ step over unused register space +#endif .endm diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h index d2ae618..69327b7 100644 --- a/include/linux/mv643xx.h +++ b/include/linux/mv643xx.h @@ -15,6 +15,7 @@ #include #include +#include /****************************************/ /* Processor Address Space */ @@ -863,7 +864,6 @@ /* I2C Registers */ /****************************************/ -#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c" #define MV64XXX_I2C_OFFSET 0xc000 #define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020 @@ -968,14 +968,6 @@ struct mpsc_pdata { u32 brg_clk_freq; }; -/* i2c Platform Device, Driver Data */ -struct mv64xxx_i2c_pdata { - u32 freq_m; - u32 freq_n; - u32 timeout; /* In milliseconds */ - u32 retries; -}; - /* Watchdog Platform Device, Driver Data */ #define MV64x60_WDT_NAME "mv64x60_wdt" diff --git a/include/linux/mv643xx_i2c.h b/include/linux/mv643xx_i2c.h new file mode 100644 index 0000000..5db5152 --- /dev/null +++ b/include/linux/mv643xx_i2c.h @@ -0,0 +1,22 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _MV64XXX_I2C_H_ +#define _MV64XXX_I2C_H_ + +#include + +#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c" + +/* i2c Platform Device, Driver Data */ +struct mv64xxx_i2c_pdata { + u32 freq_m; + u32 freq_n; + u32 timeout; /* In milliseconds */ +}; + +#endif /*_MV64XXX_I2C_H_*/ diff --git a/sound/oss/waveartist.c b/sound/oss/waveartist.c index b48c729..8849041 100644 --- a/sound/oss/waveartist.c +++ b/sound/oss/waveartist.c @@ -835,7 +835,7 @@ static struct audio_driver waveartist_audio_driver = { static irqreturn_t waveartist_intr(int irq, void *dev_id) { - wavnc_info *devc = (wavnc_info *)dev_id; + wavnc_info *devc = dev_id; int irqstatus, status; spin_lock(&waveartist_lock);