GIT b9c19c4d6584df499a24cde817fb12640247d48a git://www.linux-mips.org/pub/scm/upstream.git#for-akpm commit b9c19c4d6584df499a24cde817fb12640247d48a Author: Florian Fainelli Date: Tue Jan 15 19:42:57 2008 +0100 [MIPS] Cobalt 64-bits kernels can be safely unmarked experimental 64-bits Cobalt kernels run fine. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle commit cd98e32d3736ff8b71606ad718383fe9274428e3 Author: Ralf Baechle Date: Tue Jan 15 19:23:23 2008 +0000 [MIPS] Qemu: Remove platform. The Qemu platform was originally implemented to have an easily supportable platform until Qemu reaches a state where it emulates a real world system. Since the latest release Qemu is capable of emulating the MIPSsim and Malta platforms, so this goal has been reached. The Qemu plaform is also rather underfeatured so less useful than a Malta emulation. Signed-off-by: Ralf Baechle commit ac5d1b833fec2e844d89477d9bf738a296224cf6 Author: Vitaly Wool Date: Sat Jan 12 16:03:40 2008 +0300 [MIPS] pnx8xxx: clocksource cleanups Signed-off-by: Vitaly Wool Signed-off-by: Ralf Baechle commit ddbae5f76262ad1f3f60ae76cfb128fe72ad3153 Author: Daniel Walker Date: Thu Jan 10 20:53:21 2008 -0800 [MIPS] Lasat: Convert pvc_sem semaphore to mutex I also changed the name to pvc_mutex, and moved the define to the file it's used in which allows it to be static. Signed-off-by: Daniel Walker Signed-off-by: Ralf Baechle commit 3cc125fe027df8d8752a3a7a50b58b7f36811bb8 Author: Florian Fainelli Date: Mon Jan 7 19:00:46 2008 +0100 [MIPS] MTX-1: Add GPIO system button This patch adds support for the GPIO connected system button on the MTX-1 boards. Default configuration is updated accordingly. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle commit 2604b2703a549680d904c1aa545212a3e2dd353a Author: Ralf Baechle Date: Tue Jan 15 19:23:22 2008 +0000 [MIPS] Delete CONFIG_MSP_FPGA Originally noticed by Jiri Olsa . Signed-off-by: Ralf Baechle commit 3a703034caf089021b0487b27a56d441831ae128 Author: Yoichi Yuasa Date: Wed Dec 12 22:39:54 2007 +0900 [MIPS] move the eXcite local config to excitedirectory Moved the eXcite local config to excite directory. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit c90c93b09a5f19eac5fd56a131d9e2cfce031660 Author: Yoichi Yuasa Date: Wed Dec 12 22:23:13 2007 +0900 [MIPS] add cpu_wait() to machine_halt() Added cpu_wait() to machine_halt(). For the power reduction in halt. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 9eb4dd854b15df2b1d23002a36488c43e68ce8be Author: Yoichi Yuasa Date: Wed Dec 12 22:20:19 2007 +0900 [MIPS] remove unneeded button check for reset Removed unneeded button check for reset. Because, the Cobalt has power switch. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 1494072d727930b8895d9949d02a9d58dc887277 Author: Yoichi Yuasa Date: Wed Dec 12 22:11:09 2007 +0900 [MIPS] move vr41xx_calculate_clock_frequency() to plat_time_init() Moved vr41xx_calculate_clock_frequency() to plat_time_init(). This function relates to the timer function. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 32d26ddc90063e1bcd3dc1be78ad7c1b5303bd46 Author: Yoichi Yuasa Date: Sun Dec 9 21:19:36 2007 +0900 [MIPS] time: remove unused mips_timer_state() Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 2922d5430cc60a017c8e6cff6b34b0b4804850ff Author: Ralf Baechle Date: Tue Jan 15 19:23:21 2008 +0000 [MIPS] Altas, Malta: Switch boot file format to raw. A raw binary boots about twice as fast as SREC. The possibility to generate SREC binaries remains by simply using the vmlinux.srec target but seems only useful for the probably hypothetical case where one of these systems is booted over a serial interface. Signed-off-by: Ralf Baechle commit 4235d0ad10632e69ba838aea03e97c25cf8b1a98 Author: Ralf Baechle Date: Tue Jan 15 19:23:20 2008 +0000 [MIPS] fixmap: delete unused __set_fixmap, set_fixmap and set_fixmap_nocache Signed-off-by: Ralf Baechle commit eb0b540e47bf72c7e074aae5f08e39176c46630b Author: Ralf Baechle Date: Tue Jan 15 19:23:20 2008 +0000 [MIPS] Extend performance counter event field. The latest draft version of the MIPS Architecture Specification extends the 6 bit event field by adding a directly adjacent 4-bit EventExt field for a total of 10 bits. Signed-off-by: Ralf Baechle commit 7c78279ea67af306a33648ae2fd0876452d5308a Author: Thomas Bogendoerfer Date: Fri Jan 4 23:31:07 2008 +0100 [MIPS] RM: Collected changes - EISA support for non PCI RMs (RM200 and RM400-xxx). The major part is the splitting of the EISA and onboard ISA of the RM200, which makes the EISA bus on the RM200 look like on other RMs. - 64bit kernel support - system type detection is now common for big and little endian - moved sniprom code to arch/mips/fw - added call_o32 function to arch/mips/fw/lib, which uses a private stack for calling prom functions - fix problem with ISA interrupts, which makes using PIT clockevent possible Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle commit b7691b3dbb514c8787fb631724f898cf5bfd30a9 Author: Manuel Lauss Date: Thu Dec 6 09:07:55 2007 +0100 [MIPS] Alchemy: Au1210/Au1250 CPU support This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle commit acc4f02ba2c317d7c64f3aaefd5024680dda959c Author: Ralf Baechle Date: Tue Jan 15 19:23:19 2008 +0000 [MIPS] Eleminate local symbols from the symbol table. These symbols appear in oprofile output, stacktraces and similar but only make the output harder to read. Many identical symbol names such as "both_aligned" were also being used in multiple source files making it impossible to see which file actually was meant. So let's get rid of them. Signed-off-by: Ralf Baechle commit 03172571cca8d2662d62fff7c6f3a87f25de60e7 Author: Ralf Baechle Date: Tue Jan 15 19:23:18 2008 +0000 [MIPS] Fulong: don't reinitialize pci_probe_only to it's default value. Signed-off-by: Ralf Baechle commit bcf19859084b839f276fdb9e34438ffdae39973f Author: Ralf Baechle Date: Tue Jan 15 19:23:17 2008 +0000 [MIPS] BCM1480: Use constants instead of magic numbers in PCI code. Signed-off-by: Ralf Baechle commit 4c780dc03351ded1bcd23460335d91608e6fbb16 Author: Thomas Bogendoerfer Date: Sun Dec 2 13:00:32 2007 +0100 [MIPS] IP28 support Add support for SGI IP28 machines (Indigo 2 with R10k CPUs) This work is mainly based on Peter Fuersts work. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle commit d19ab81d25fb85710d00ab589ba348be374e3b23 Author: Ralf Baechle Date: Tue Jan 15 19:23:15 2008 +0000 [MIPS] Remove CONFIG_SIBYTE_PT{1120,1125,SWARM} According to Broadcom the PT systems are production test systems which never reached customers so no need to keep the fragmentary support we currently have. Signed-off-by: Ralf Baechle commit 220b2a38b387fd1911c6f6a902b3eb0650613f88 Author: Thomas Bogendoerfer Date: Tue Nov 27 19:31:33 2007 +0100 [MIPS] Use correct dma flushing in dma_cache_sync() Not cache coherent R10k systems (like IP28) need to do real cache invalidates in dma_cache_sync(). Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle commit 54834cd244869b00d9f33a30d2cb0db8bab5412e Author: Thomas Bogendoerfer Date: Sun Nov 25 11:47:56 2007 +0100 [MIPS] IP28: added cache barrier to assembly routines IP28 needs special treatment to avoid speculative accesses. gcc takes care for .c code, but for assembly code we need to do it manually. This is taken from Peter Fuersts IP28 patches. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle commit 673d10d7466946497e596f60c70f188c50eda6e3 Author: Atsushi Nemoto Date: Sat Nov 24 01:20:27 2007 +0900 [MIPS] TXx9 watchdog support for rbhma3100,rbhma4200,rbhma4500 This patch adds support for txx9wdt driver to rbhma3100, rbhma4200 and rbhma4500 platform. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle commit 766e8c902953da934085326d68b2e17ee62794e3 Author: Thomas Bogendoerfer Date: Sun Nov 25 11:27:06 2007 +0100 [MIPS] IP22/IP28: fix extracting board/chip rev Taken from Peter Fuersts IP28 patches Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle commit 6ad4c6abc609f12798a524e6ba580d1a6d2fac19 Author: Thomas Bogendoerfer Date: Mon Nov 26 23:40:01 2007 +0100 [MIPS] Use real cache invalidate R10k non coherent machines need a real dma cache invalidate to get rid of speculative stores in cache. For other machines this promises a slight speedup. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle commit ca66e6876966bbc877c66341c606cf71af2c278c Author: Ralf Baechle Date: Mon Nov 19 12:23:51 2007 +0000 [MIPS] SMP: Call platform methods via ops structure. Signed-off-by: Ralf Baechle commit af22a9d46800e524597997e8383ce738157ec520 Author: Ralf Baechle Date: Tue Jan 15 19:23:13 2008 +0000 [MIPS] Cleanup pcspeaker platform device registration. Move registration into the actual platform code instead of making a desparate attempt at sharing the hand full of likes of code in pcspeaker.c. Signed-off-by: Ralf Baechle commit 45fdbd5eea40e7e15c90c9e85fbb430e1463890b Author: Ralf Baechle Date: Fri Mar 2 20:42:04 2007 +0000 [MIPS] MT: Scheduler support for SMT Signed-off-by: Ralf Baechle commit c24c4a888eb6fcf9a2c0dad390fbdc14052e9c68 Author: Franck Bui-Huu Date: Thu Oct 18 09:11:17 2007 +0200 [MIPS] tlbex.c: cleanup debug code Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle commit 43c4e109cda141e3e983a38de33d843ab655b513 Author: Franck Bui-Huu Date: Thu Oct 18 09:11:16 2007 +0200 [MIPS] tlbex.c: use __cacheline_aligned instead of __tlb_handler_align Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle commit 96ea3f0e1096e2b26a31d81e3864efd4942843c2 Author: Franck Bui-Huu Date: Thu Oct 18 09:11:15 2007 +0200 [MIPS] tlbex.c: cleanup include files Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle commit ff5e75b098e5a5b2c93d0b14aad8e8a25e015575 Author: Franck Bui-Huu Date: Thu Oct 18 09:11:14 2007 +0200 [MIPS] tlbex.c: Cleanup __init usages. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle commit 76e29185a175bb212a278d3b5cb5d3ad2453c89c Author: Robert P. J. Day Date: Tue Nov 6 01:55:12 2007 -0500 [MIPS] Delete now-unreferenced i2c-yosemite.h header file. Given that the corresponding source file i2c-yosemite.c file was removed in commit daa4a68f901c4d6491baa1a01f5c869a553c3f6c, and that no one else includes this file, it seems safe to delete it. Signed-off-by: Robert P. J. Day Signed-off-by: Ralf Baechle commit 2b6ad7d4307048625a28993917709735d3900da5 Author: Lucas Woods Date: Tue Nov 6 07:13:47 2007 +1100 [MIPS] Remove duplicate includes. Signed-off-by: Lucas Woods Signed-off-by: Ralf Baechle commit 8135665ee71ffeef6720d3bf59660e0ed15fc5cf Author: Roel Kluin <12o3l@tiscali.nl> Date: Fri Nov 2 19:59:05 2007 +0100 [MIPS] ARC: Use strchr instead of strstr. Use strchr instead of strstr when searching for a single character Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Signed-off-by: Ralf Baechle commit 286ce11f916a339256a70bcd99ce635f9a92f9ef Author: Ralf Baechle Date: Tue Jan 15 19:23:09 2008 +0000 [MIPS] Remove useless S-cache flushes. Signed-off-by: Ralf Baechle commit 1269c1877b3e6d2fddb105ba07a78067e1934b87 Author: Ralf Baechle Date: Tue Jan 15 19:23:09 2008 +0000 [MIPS] Use pte_present instead of open coded test for _PAGE_PRESENT. Signed-off-by: Ralf Baechle commit c3acaa54e9570ef7cb550532304ec99534c748a6 Author: Andrew Sharp Date: Wed Oct 31 14:11:24 2007 -0700 [MIPS] Put cast inside macro instead of all the callers Since all the callers of the PHYS_TO_XKPHYS macro call with a constant, put the cast to LL inside the macro where it really should be rather than in all the callers. This makes macros like PHYS_TO_XKSEG_UNCACHED work without gcc whining. Signed-off-by: Andrew Sharp Signed-off-by: Ralf Baechle commit 0ac62828a80beea6d2069e002b13d6c2ac870ae1 Author: Yoichi Yuasa Date: Thu Nov 1 21:35:39 2007 +0900 [MIPS] clean up au1xxx_irqmap.c include files Clean up au1xxx_irqmap.c include files. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 24f8b972de6f3e3de107f23db13fa225bb69b696 Author: Yoichi Yuasa Date: Fri Oct 26 22:42:31 2007 +0900 [MIPS] remove unused mips_machtype Removed unused mips_machtype. These are only set but not used. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle commit 9ce517b8f3580f9e0e385a1ac9883e7be146f62f Author: Christoph Hellwig Date: Mon Oct 29 14:23:43 2007 +0000 [MIPS] CFE: Make code remotely resemble Linux code. Signed-off-by: Ralf Baechle commit ec969ffed97ba2bad117f848fdbb0d59ba4a1957 Author: Atsushi Nemoto Date: Wed Oct 24 23:16:56 2007 +0900 [MIPS] cleanup tx39/tx49 setup code Remove some unnecessary codes, includes and files. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle commit 0f22533b2119f942af6c2ea126e9029903da0dc2 Author: Maciej W. Rozycki Date: Tue Oct 23 12:43:25 2007 +0100 [MIPS] R4000/R4400 daddiu erratum workaround This complements the generic R4000/R4400 errata workaround code and adds bits for the daddiu problem. In most places it just modifies handwritten assembly code so that the assembler is allowed to use a temporary register as daddiu may now be treated as a macro that expands to a sequence of li and daddu. It is the AT register or, where AT is unavailable or used explicitly for another purpose, an explicitly-named register is selected, using the .set at= feature added recently to gas. This feature is only used if CONFIG_CPU_DADDI_WORKAROUNDS has been set, so if the workaround remains disabled, the required version of binutils stays unchanged. Similarly, daddiu instructions put in branch delay slots in noreorder fragments are now taken out of them and the assembler is allowed to reorder them itself as possible (which it does making the whole idea of scheduling them into delay slots manually questionable). Also in the very few places where such a simple conversion was not possible, a handcoded longer sequence is implemented. Other than that there are changes to code responsible for building the TLB fault and page clear/copy handlers to avoid daddiu as appropriate. These are only effective if the erratum is verified to be present at the run time. Finally there is a trivial update to __delay(), because it uses daddiu in a branch delay slot. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle commit 106caef8d18564150294c156adae950d42f47402 Author: Maciej W. Rozycki Date: Tue Oct 23 12:43:11 2007 +0100 [MIPS] R4000/R4400 errata workarounds This is the gereric part of R4000/R4400 errata workarounds. They include compiler and assembler support as well as some source code modifications to address the problems with some combinations of multiply/divide+shift instructions as well as the daddi and daddiu instructions. Changes included are as follows: 1. New Kconfig options to select workarounds by platforms as necessary. 2. Arch top-level Makefile to pass necessary options to the compiler; also incompatible configurations are detected (-mno-sym32 unsupported as horribly intrusive for little gain). 3. Bug detection updated and shuffled -- the multiply/divide+shift problem is lethal enough that if not worked around it makes the kernel crash in time_init() because of a division by zero; the daddiu erratum might also trigger early potentially, though I have not observed it. On the other hand the daddi detection code requires the exception subsystem to have been initialised (and is there mainly for information). 4. r4k_daddiu_bug() added so that the existence of the erratum can be queried by code at the run time as necessary; useful for generated code like TLB fault and copy/clear page handlers. 5. __udelay() updated as it uses multiplication in inline assembly. Note that -mdaddi requires modified toolchain (which has been maintained by myself and available from my site for ~4years now -- versions covered are GCC 2.95.4 - 4.1.2 and binutils from 2.13 onwards). The -mfix-r4000 and -mfix-r4400 have been standard for a while though. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle commit 9a2eba940625020c09ec21ef3306793bd5f9db43 Author: Alejandro Martinez Ruiz Date: Mon Oct 22 21:36:44 2007 +0200 [MIPS] Converting most array size calculations to use ARRAY_SIZE(). Signed-off-by: Alejandro Martinez Ruiz Signed-off-by: Ralf Baechle commit cd10ad996ea529355d30800ad4ed2badcabf4a48 Author: Ralf Baechle Date: Tue Jan 15 19:23:06 2008 +0000 [MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers. Signed-off-by: Ralf Baechle commit 504232a92cf14168814e89bc63e0b1473b3617b1 Author: Ralf Baechle Date: Tue Jan 15 19:23:05 2008 +0000 [MIPS] Delete unused CONFIG_64BIT_CONTEXT The merge of the code to use this was never completed so delete it for the time being. Signed-off-by: Ralf Baechle commit 3bf3add934a9df850a04739ea203e71e814baa1a Author: Ralf Baechle Date: Tue Jan 15 19:23:05 2008 +0000 [MIPS] Delete unused CONFIG_DMA_IP32. The functionality of the former dma-ip32.c has been folded into dma-default.c. Signed-off-by: Ralf Baechle Signed-off-by: Andrew Morton --- arch/mips/Kconfig | 181 ++- arch/mips/Makefile | 40 arch/mips/au1000/common/au1xxx_irqmap.c | 23 arch/mips/au1000/common/dbdma.c | 2 arch/mips/au1000/db1x00/init.c | 11 arch/mips/au1000/mtx-1/init.c | 2 arch/mips/au1000/mtx-1/platform.c | 27 arch/mips/au1000/pb1000/init.c | 2 arch/mips/au1000/pb1100/init.c | 2 arch/mips/au1000/pb1200/init.c | 2 arch/mips/au1000/pb1500/init.c | 2 arch/mips/au1000/pb1550/init.c | 2 arch/mips/au1000/xxs1500/init.c | 2 arch/mips/basler/excite/Kconfig | 9 arch/mips/basler/excite/excite_prom.c | 2 arch/mips/cobalt/reset.c | 24 arch/mips/configs/atlas_defconfig | 2 arch/mips/configs/bigsur_defconfig | 2 arch/mips/configs/capcella_defconfig | 2 arch/mips/configs/cobalt_defconfig | 2 arch/mips/configs/db1000_defconfig | 2 arch/mips/configs/db1100_defconfig | 2 arch/mips/configs/db1200_defconfig | 2 arch/mips/configs/db1500_defconfig | 2 arch/mips/configs/db1550_defconfig | 2 arch/mips/configs/decstation_defconfig | 2 arch/mips/configs/e55_defconfig | 2 arch/mips/configs/emma2rh_defconfig | 2 arch/mips/configs/excite_defconfig | 2 arch/mips/configs/fulong_defconfig | 2 arch/mips/configs/ip22_defconfig | 2 arch/mips/configs/ip27_defconfig | 2 arch/mips/configs/ip32_defconfig | 2 arch/mips/configs/jazz_defconfig | 2 arch/mips/configs/jmr3927_defconfig | 17 arch/mips/configs/lasat_defconfig | 2 arch/mips/configs/malta_defconfig | 2 arch/mips/configs/mipssim_defconfig | 2 arch/mips/configs/mpc30x_defconfig | 2 arch/mips/configs/msp71xx_defconfig | 2 arch/mips/configs/mtx1_defconfig | 3 arch/mips/configs/pb1100_defconfig | 2 arch/mips/configs/pb1500_defconfig | 2 arch/mips/configs/pb1550_defconfig | 2 arch/mips/configs/pnx8550-jbs_defconfig | 2 arch/mips/configs/pnx8550-stb810_defconfig | 2 arch/mips/configs/qemu_defconfig | 2 arch/mips/configs/rbhma4200_defconfig | 17 arch/mips/configs/rbhma4500_defconfig | 17 arch/mips/configs/rm200_defconfig | 2 arch/mips/configs/sb1250-swarm_defconfig | 2 arch/mips/configs/sead_defconfig | 2 arch/mips/configs/tb0219_defconfig | 2 arch/mips/configs/tb0226_defconfig | 2 arch/mips/configs/tb0287_defconfig | 2 arch/mips/configs/workpad_defconfig | 2 arch/mips/configs/wrppmc_defconfig | 2 arch/mips/configs/yosemite_defconfig | 2 arch/mips/dec/time.c | 1 arch/mips/defconfig | 2 arch/mips/fw/arc/cmdline.c | 2 arch/mips/fw/arc/init.c | 8 arch/mips/fw/cfe/cfe_api.c | 184 +-- arch/mips/fw/cfe/cfe_api_int.h | 188 +-- arch/mips/fw/lib/Makefile | 5 arch/mips/fw/lib/call_o32.S | 97 + arch/mips/fw/sni/Makefile | 5 arch/mips/fw/sni/sniprom.c | 151 +++ arch/mips/gt64120/wrppmc/setup.c | 2 arch/mips/jazz/setup.c | 7 arch/mips/jmr3927/rbhma3100/init.c | 4 arch/mips/jmr3927/rbhma3100/setup.c | 60 + arch/mips/kernel/cpu-bugs64.c | 47 arch/mips/kernel/cpu-probe.c | 9 arch/mips/kernel/genex.S | 8 arch/mips/kernel/kspd.c | 3 arch/mips/kernel/mips-mt.c | 1 arch/mips/kernel/pcspeaker.c | 28 arch/mips/kernel/proc.c | 1 arch/mips/kernel/rtlx.c | 1 arch/mips/kernel/setup.c | 7 arch/mips/kernel/smp-mt.c | 193 ++- arch/mips/kernel/smp.c | 53 - arch/mips/kernel/smtc-proc.c | 1 arch/mips/kernel/smtc.c | 1 arch/mips/kernel/time.c | 2 arch/mips/kernel/vpe.c | 1 arch/mips/lasat/picvue.c | 2 arch/mips/lasat/picvue.h | 3 arch/mips/lasat/picvue_proc.c | 18 arch/mips/lemote/lm2e/pci.c | 3 arch/mips/lemote/lm2e/prom.c | 2 arch/mips/lib/csum_partial.S | 275 +++-- arch/mips/lib/memcpy-inatomic.S | 141 +- arch/mips/lib/memcpy.S | 250 ++-- arch/mips/lib/memset.S | 44 arch/mips/lib/strlen_user.S | 6 arch/mips/lib/strncpy_user.S | 15 arch/mips/lib/strnlen_user.S | 7 arch/mips/lib/uncached.c | 12 arch/mips/mips-boards/generic/init.c | 8 arch/mips/mips-boards/malta/malta_smtc.c | 66 - arch/mips/mipssim/Makefile | 2 arch/mips/mipssim/sim_setup.c | 16 arch/mips/mipssim/sim_smp.c | 123 -- arch/mips/mipssim/sim_smtc.c | 117 ++ arch/mips/mm/c-r4k.c | 17 arch/mips/mm/dma-default.c | 2 arch/mips/mm/pg-r4k.c | 66 - arch/mips/mm/tlbex.c | 252 ++--- arch/mips/oprofile/op_model_mipsxx.c | 2 arch/mips/pci/pci-bcm1480.c | 4 arch/mips/pci/pci-bcm1480ht.c | 4 arch/mips/philips/pnx8550/common/setup.c | 2 arch/mips/philips/pnx8550/common/time.c | 35 arch/mips/philips/pnx8550/jbs/init.c | 3 arch/mips/philips/pnx8550/stb810/prom_init.c | 2 arch/mips/pmc-sierra/yosemite/i2c-yosemite.h | 96 - arch/mips/pmc-sierra/yosemite/prom.c | 7 arch/mips/pmc-sierra/yosemite/smp.c | 149 +- arch/mips/qemu/Makefile | 10 arch/mips/qemu/q-console.c | 26 arch/mips/qemu/q-firmware.c | 24 arch/mips/qemu/q-irq.c | 37 arch/mips/qemu/q-mem.c | 5 arch/mips/qemu/q-reset.c | 33 arch/mips/qemu/q-setup.c | 22 arch/mips/qemu/q-smp.c | 55 - arch/mips/sgi-ip22/Makefile | 8 arch/mips/sgi-ip22/ip22-mc.c | 4 arch/mips/sgi-ip22/ip28-berr.c | 502 ++++++++++ arch/mips/sgi-ip27/ip27-init.c | 1 arch/mips/sgi-ip27/ip27-klnuma.c | 1 arch/mips/sgi-ip27/ip27-smp.c | 109 +- arch/mips/sibyte/bcm1480/smp.c | 101 +- arch/mips/sibyte/cfe/Makefile | 1 arch/mips/sibyte/cfe/setup.c | 14 arch/mips/sibyte/cfe/smp.c | 110 -- arch/mips/sibyte/sb1250/smp.c | 100 + arch/mips/sni/Makefile | 2 arch/mips/sni/a20r.c | 13 arch/mips/sni/eisa.c | 50 arch/mips/sni/irq.c | 4 arch/mips/sni/pcit.c | 7 arch/mips/sni/rm200.c | 326 ++++++ arch/mips/sni/setup.c | 143 ++ arch/mips/sni/sniprom.c | 251 ----- arch/mips/sni/time.c | 1 arch/mips/tx4927/common/Makefile | 2 arch/mips/tx4927/common/tx4927_setup.c | 186 --- arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 96 + arch/mips/tx4938/common/Makefile | 2 arch/mips/tx4938/common/setup.c | 45 arch/mips/tx4938/toshiba_rbtx4938/prom.c | 1 arch/mips/tx4938/toshiba_rbtx4938/setup.c | 31 arch/mips/vr41xx/common/init.c | 4 arch/mips/vr41xx/nec-cmbvr4133/setup.c | 4 include/asm-mips/addrspace.h | 2 include/asm-mips/asm.h | 8 include/asm-mips/bootinfo.h | 105 -- include/asm-mips/bugs.h | 25 include/asm-mips/cpu-info.h | 5 include/asm-mips/cpu.h | 4 include/asm-mips/delay.h | 23 include/asm-mips/dma.h | 7 include/asm-mips/fixmap.h | 10 include/asm-mips/fw/cfe/cfe_api.h | 87 - include/asm-mips/fw/cfe/cfe_error.h | 19 include/asm-mips/mach-cobalt/cobalt.h | 15 include/asm-mips/mach-ip28/cpu-feature-overrides.h | 50 include/asm-mips/mach-ip28/ds1286.h | 4 include/asm-mips/mach-ip28/spaces.h | 22 include/asm-mips/mach-ip28/war.h | 25 include/asm-mips/mach-qemu/cpu-feature-overrides.h | 32 include/asm-mips/mach-qemu/war.h | 25 include/asm-mips/mipsprom.h | 2 include/asm-mips/pmc-sierra/msp71xx/msp_regs.h | 4 include/asm-mips/r4kcache.h | 7 include/asm-mips/sgi/ioc.h | 4 include/asm-mips/sibyte/board.h | 6 include/asm-mips/sibyte/sb1250.h | 2 include/asm-mips/sibyte/swarm.h | 18 include/asm-mips/smp-ops.h | 56 + include/asm-mips/smp.h | 64 - include/asm-mips/sni.h | 159 +-- include/asm-mips/stackframe.h | 9 include/asm-mips/time.h | 9 include/asm-mips/topology.h | 16 include/asm-mips/tx4927/tx4927_pci.h | 1 include/asm-mips/uaccess.h | 13 include/asm-mips/war.h | 62 + 191 files changed, 3623 insertions(+), 2894 deletions(-) diff -puN arch/mips/Kconfig~git-mips arch/mips/Kconfig --- a/arch/mips/Kconfig~git-mips +++ a/arch/mips/Kconfig @@ -37,16 +37,6 @@ config BASLER_EXCITE The eXcite is a smart camera platform manufactured by Basler Vision Technologies AG. -config BASLER_EXCITE_PROTOTYPE - bool "Support for pre-release units" - depends on BASLER_EXCITE - default n - help - Pre-series (prototype) units are different from later ones in - some ways. Select this option if you have one of these. Please - note that a kernel built with this option selected will not be - able to run on normal units. - config BCM47XX bool "BCM47XX based boards" select CEVT_R4K @@ -82,7 +72,7 @@ config MIPS_COBALT select SYS_HAS_CPU_NEVADA select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select GENERIC_HARDIRQS_NO__DO_IRQ @@ -91,6 +81,9 @@ config MACH_DECSTATION select BOOT_ELF32 select CEVT_R4K select CSRC_R4K + select CPU_DADDI_WORKAROUNDS if 64BIT + select CPU_R4000_WORKAROUNDS if 64BIT + select CPU_R4400_WORKAROUNDS if 64BIT select DMA_NONCOHERENT select NO_IOPORT select IRQ_CPU @@ -124,12 +117,12 @@ config MACH_JAZZ select ARCH_MAY_HAVE_PC_FDC select CEVT_R4K select CSRC_R4K + select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN select GENERIC_ISA_DMA select IRQ_CPU select I8253 select I8259 select ISA - select PCSPEAKER select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL @@ -187,6 +180,7 @@ config LEMOTE_FULONG config MIPS_ATLAS bool "MIPS Atlas board" select BOOT_ELF32 + select BOOT_RAW select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT @@ -219,6 +213,7 @@ config MIPS_MALTA bool "MIPS Malta board" select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 + select BOOT_RAW select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT @@ -364,35 +359,6 @@ config PMC_YOSEMITE Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra. -config QEMU - bool "Qemu" - select CEVT_R4K - select CSRC_R4K - select DMA_COHERENT - select GENERIC_ISA_DMA - select HAVE_STD_PC_SERIAL_PORT - select I8253 - select I8259 - select IRQ_CPU - select ISA - select PCSPEAKER - select SWAP_IO_SPACE - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ - select NR_CPUS_DEFAULT_1 - select SYS_SUPPORTS_SMP - help - Qemu is a software emulator which among other architectures also - can simulate a MIPS32 4Kc system. This patch adds support for the - system architecture that currently is being simulated by Qemu. It - will eventually be removed again when Qemu has the capability to - simulate actual MIPS hardware platforms. More information on Qemu - can be found at http://www.linux-mips.org/wiki/Qemu. - config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC @@ -400,6 +366,7 @@ config SGI_IP22 select BOOT_ELF32 select CEVT_R4K select CSRC_R4K + select DEFAULT_SGI_PARTITION select DMA_NONCOHERENT select HW_HAS_EISA select I8253 @@ -407,6 +374,12 @@ config SGI_IP22 select IP22_CPU_SCACHE select IRQ_CPU select GENERIC_ISA_DMA_SUPPORT_BROKEN + select SGI_HAS_DS1286 + select SGI_HAS_I8042 + select SGI_HAS_INDYDOG + select SGI_HAS_SEEQ + select SGI_HAS_WD93 + select SGI_HAS_ZILOG select SWAP_IO_SPACE select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 @@ -424,6 +397,7 @@ config SGI_IP27 select ARC select ARC64 select BOOT_ELF64 + select DEFAULT_SGI_PARTITION select DMA_IP27 select SYS_HAS_EARLY_PRINTK select HW_HAS_PCI @@ -440,6 +414,36 @@ config SGI_IP27 workstations. To compile a Linux kernel that runs on these, say Y here. +config SGI_IP28 + bool "SGI IP28 (Indigo2 R10k) (EXPERIMENTAL)" + depends on EXPERIMENTAL + select ARC + select ARC64 + select BOOT_ELF64 + select CEVT_R4K + select CSRC_R4K + select DEFAULT_SGI_PARTITION + select DMA_NONCOHERENT + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select IRQ_CPU + select HW_HAS_EISA + select I8253 + select I8259 + select SGI_HAS_DS1286 + select SGI_HAS_I8042 + select SGI_HAS_INDYDOG + select SGI_HAS_SEEQ + select SGI_HAS_WD93 + select SGI_HAS_ZILOG + select SWAP_IO_SPACE + select SYS_HAS_CPU_R10000 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + This is the SGI Indigo2 with R10000 processor. To compile a Linux + kernel that runs on these, say Y here. + config SGI_IP32 bool "SGI IP32 (O2)" select ARC @@ -545,19 +549,6 @@ config SIBYTE_SENTOSA select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_PTSWARM - bool "Sibyte BCM91250PT-PTSWARM" - depends on EXPERIMENTAL - select BOOT_ELF32 - select DMA_COHERENT - select NR_CPUS_DEFAULT_2 - select SIBYTE_SB1250 - select SWAP_IO_SPACE - select SYS_HAS_CPU_SB1 - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_SUPPORTS_LITTLE_ENDIAN - config SIBYTE_BIGSUR bool "Sibyte BCM91480B-BigSur" select BOOT_ELF32 @@ -575,10 +566,12 @@ config SNI_RM bool "SNI RM200/300/400" select ARC if CPU_LITTLE_ENDIAN select ARC32 if CPU_LITTLE_ENDIAN + select SNIPROM if CPU_BIG_ENDIAN select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select CEVT_R4K select CSRC_R4K + select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN select DMA_NONCOHERENT select GENERIC_ISA_DMA select HW_HAS_EISA @@ -587,7 +580,6 @@ config SNI_RM select I8253 select I8259 select ISA - select PCSPEAKER select SWAP_IO_SPACE if CPU_BIG_ENDIAN select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 @@ -690,6 +682,7 @@ config WR_PPMC endchoice source "arch/mips/au1000/Kconfig" +source "arch/mips/basler/excite/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" @@ -797,10 +790,6 @@ config DMA_COHERENT config DMA_IP27 bool -config DMA_IP32 - bool - select DMA_NEED_PCI_MAP_STATE - config DMA_NONCOHERENT bool select DMA_NEED_PCI_MAP_STATE @@ -956,16 +945,40 @@ config EMMA2RH config SERIAL_RM9000 bool +config SGI_HAS_DS1286 + bool + +config SGI_HAS_INDYDOG + bool + +config SGI_HAS_SEEQ + bool + +config SGI_HAS_WD93 + bool + +config SGI_HAS_ZILOG + bool + +config SGI_HAS_I8042 + bool + +config DEFAULT_SGI_PARTITION + bool + config ARC32 bool +config SNIPROM + bool + config BOOT_ELF32 bool config MIPS_L1_CACHE_SHIFT int default "4" if MACH_DECSTATION - default "7" if SGI_IP27 || SNI_RM + default "7" if SGI_IP27 || SGI_IP28 || SNI_RM default "4" if PMC_MSP4200_EVAL default "5" @@ -974,7 +987,7 @@ config HAVE_STD_PC_SERIAL_PORT config ARC_CONSOLE bool "ARC console support" - depends on SGI_IP22 || (SNI_RM && CPU_LITTLE_ENDIAN) + depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN) config ARC_MEMORY bool @@ -983,7 +996,7 @@ config ARC_MEMORY config ARC_PROMLIB bool - depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP32 + depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32 default y config ARC64 @@ -1443,7 +1456,9 @@ config MIPS_MT_SMP select MIPS_MT select NR_CPUS_DEFAULT_2 select SMP + select SYS_SUPPORTS_SCHED_SMT if SMP select SYS_SUPPORTS_SMP + select SMP_UP help This is a kernel model which is also known a VSMP or lately has been marketesed into SMVP. @@ -1460,6 +1475,7 @@ config MIPS_MT_SMTC select NR_CPUS_DEFAULT_8 select SMP select SYS_SUPPORTS_SMP + select SMP_UP help This is a kernel model which is known a SMTC or lately has been marketesed into SMVP. @@ -1469,6 +1485,19 @@ endchoice config MIPS_MT bool +config SCHED_SMT + bool "SMT (multithreading) scheduler support" + depends on SYS_SUPPORTS_SCHED_SMT + default n + help + SMT scheduler support improves the CPU scheduler's decision making + when dealing with MIPS MT enabled cores at a cost of slightly + increased overhead in some places. If unsure say N here. + +config SYS_SUPPORTS_SCHED_SMT + bool + + config SYS_SUPPORTS_MULTITHREADING bool @@ -1589,15 +1618,6 @@ config CPU_HAS_SMARTMIPS config CPU_HAS_WB bool -config 64BIT_CONTEXT - bool "Save 64bit integer registers" - depends on 32BIT && CPU_LOONGSON2 - help - Loongson2 CPU is 64bit , when used in 32BIT mode, its integer - registers can still be accessed as 64bit, mainly for multimedia - instructions. We must have all 64bit save/restored to make sure - those instructions to get correct result. - # # Vectored interrupt mode is an R2 feature # @@ -1619,6 +1639,19 @@ config GENERIC_CLOCKEVENTS_BROADCAST bool # +# CPU non-features +# +config CPU_DADDI_WORKAROUNDS + bool + +config CPU_R4000_WORKAROUNDS + bool + select CPU_R4400_WORKAROUNDS + +config CPU_R4400_WORKAROUNDS + bool + +# # Use the generic interrupt handling code in kernel/irq/: # config GENERIC_HARDIRQS @@ -1721,6 +1754,9 @@ config SMP If you don't know what to do here, say N. +config SMP_UP + bool + config SYS_SUPPORTS_SMP bool @@ -1978,9 +2014,6 @@ config MMU config I8253 bool -config PCSPEAKER - bool - config ZONE_DMA32 bool diff -puN arch/mips/Makefile~git-mips arch/mips/Makefile --- a/arch/mips/Makefile~git-mips +++ a/arch/mips/Makefile @@ -141,6 +141,10 @@ cflags-$(CONFIG_CPU_R8000) += -march=r80 cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ -Wa,--trap +cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) +cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) +cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) + ifdef CONFIG_CPU_SB1 ifdef CONFIG_SB1_PASS_1_WORKAROUNDS MODFLAGS += -msb1-pass1-workarounds @@ -152,6 +156,8 @@ endif # libs-$(CONFIG_ARC) += arch/mips/fw/arc/ libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ +libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ +libs-y += arch/mips/fw/lib/ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ # @@ -308,7 +314,7 @@ core-$(CONFIG_MIPS_ATLAS) += arch/mips/m cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 -all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec +all-$(CONFIG_MIPS_ATLAS) := vmlinux.bin # # MIPS Malta board @@ -316,7 +322,7 @@ all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 -all-$(CONFIG_MIPS_MALTA) := vmlinux.srec +all-$(CONFIG_MIPS_MALTA) := vmlinux.bin # # MIPS SEAD board @@ -349,14 +355,6 @@ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclu load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 # -# Qemu simulating MIPS32 4Kc -# -core-$(CONFIG_QEMU) += arch/mips/qemu/ -cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu -load-$(CONFIG_QEMU) += 0xffffffff80010000 -all-$(CONFIG_QEMU) := vmlinux.bin - -# # Basler eXcite # core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ @@ -475,6 +473,20 @@ endif endif # +# SGI IP28 (Indigo2 R10k) +# +# Set the load address to >= 0xa800000020080000 if you want to leave space for +# symmon, 0xa800000020004000 for production kernels ? Note that the value must +# be 16kb aligned or the handling of the current variable will break. +# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys +# +#core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ arch/mips/arc/arc_con.o +core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ +cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28 +#cflags-$(CONFIG_SGI_IP28) += -Iinclude/asm-mips/mach-ip28 +load-$(CONFIG_SGI_IP28) += 0xa800000020004000 + +# # SGI-IP32 (O2) # # Set the load address to >= 80069000 if you want to leave space for symmon, @@ -602,9 +614,11 @@ ifdef CONFIG_64BIT endif endif - ifeq ($(KBUILD_SYM32), y) - ifeq ($(call cc-option-yn,-msym32), y) - cflags-y += -msym32 -DKBUILD_64BIT_SYM32 + ifeq ($(KBUILD_SYM32)$(call cc-option-yn,-msym32), yy) + cflags-y += -msym32 -DKBUILD_64BIT_SYM32 + else + ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y) + $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32) endif endif endif diff -puN arch/mips/au1000/common/au1xxx_irqmap.c~git-mips arch/mips/au1000/common/au1xxx_irqmap.c --- a/arch/mips/au1000/common/au1xxx_irqmap.c~git-mips +++ a/arch/mips/au1000/common/au1xxx_irqmap.c @@ -25,27 +25,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include +#include + +#include /* The IC0 interrupt table. This is processor, rather than * board dependent, so no reason to keep this info in the board diff -puN arch/mips/au1000/common/dbdma.c~git-mips arch/mips/au1000/common/dbdma.c --- a/arch/mips/au1000/common/dbdma.c~git-mips +++ a/arch/mips/au1000/common/dbdma.c @@ -179,7 +179,7 @@ static dbdev_tab_t dbdev_tab[] = { { 0, 0, 0, 0, 0, 0, 0 }, }; -#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) +#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; diff -puN arch/mips/au1000/db1x00/init.c~git-mips arch/mips/au1000/db1x00/init.c --- a/arch/mips/au1000/db1x00/init.c~git-mips +++ a/arch/mips/au1000/db1x00/init.c @@ -57,17 +57,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - /* Set the platform # */ -#if defined(CONFIG_MIPS_DB1550) - mips_machtype = MACH_DB1550; -#elif defined(CONFIG_MIPS_DB1500) - mips_machtype = MACH_DB1500; -#elif defined(CONFIG_MIPS_DB1100) - mips_machtype = MACH_DB1100; -#else - mips_machtype = MACH_DB1000; -#endif - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff -puN arch/mips/au1000/mtx-1/init.c~git-mips arch/mips/au1000/mtx-1/init.c --- a/arch/mips/au1000/mtx-1/init.c~git-mips +++ a/arch/mips/au1000/mtx-1/init.c @@ -54,8 +54,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machtype = MACH_MTX1; /* set the platform # */ - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff -puN arch/mips/au1000/mtx-1/platform.c~git-mips arch/mips/au1000/mtx-1/platform.c --- a/arch/mips/au1000/mtx-1/platform.c~git-mips +++ a/arch/mips/au1000/mtx-1/platform.c @@ -22,9 +22,32 @@ #include #include #include +#include +#include #include +static struct gpio_keys_button mtx1_gpio_button[] = { + { + .gpio = 207, + .code = BTN_0, + .desc = "System button", + } +}; + +static struct gpio_keys_platform_data mtx1_buttons_data = { + .buttons = mtx1_gpio_button, + .nbuttons = ARRAY_SIZE(mtx1_gpio_button), +}; + +static struct platform_device mtx1_button = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &mtx1_buttons_data, + } +}; + static struct resource mtx1_wdt_res[] = { [0] = { .start = 15, @@ -66,11 +89,13 @@ static struct platform_device mtx1_gpio_ static struct __initdata platform_device * mtx1_devs[] = { &mtx1_gpio_leds, - &mtx1_wdt + &mtx1_wdt, + &mtx1_button }; static int __init mtx1_register_devices(void) { + gpio_direction_input(207); return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); } diff -puN arch/mips/au1000/pb1000/init.c~git-mips arch/mips/au1000/pb1000/init.c --- a/arch/mips/au1000/pb1000/init.c~git-mips +++ a/arch/mips/au1000/pb1000/init.c @@ -52,8 +52,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machtype = MACH_PB1000; - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff -puN arch/mips/au1000/pb1100/init.c~git-mips arch/mips/au1000/pb1100/init.c --- a/arch/mips/au1000/pb1100/init.c~git-mips +++ a/arch/mips/au1000/pb1100/init.c @@ -53,8 +53,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg3; - mips_machtype = MACH_PB1100; - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff -puN arch/mips/au1000/pb1200/init.c~git-mips arch/mips/au1000/pb1200/init.c --- a/arch/mips/au1000/pb1200/init.c~git-mips +++ a/arch/mips/au1000/pb1200/init.c @@ -53,8 +53,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machtype = MACH_PB1200; - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff -puN arch/mips/au1000/pb1500/init.c~git-mips arch/mips/au1000/pb1500/init.c --- a/arch/mips/au1000/pb1500/init.c~git-mips +++ a/arch/mips/au1000/pb1500/init.c @@ -53,8 +53,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machtype = MACH_PB1500; - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff -puN arch/mips/au1000/pb1550/init.c~git-mips arch/mips/au1000/pb1550/init.c --- a/arch/mips/au1000/pb1550/init.c~git-mips +++ a/arch/mips/au1000/pb1550/init.c @@ -53,8 +53,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machtype = MACH_PB1550; - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff -puN arch/mips/au1000/xxs1500/init.c~git-mips arch/mips/au1000/xxs1500/init.c --- a/arch/mips/au1000/xxs1500/init.c~git-mips +++ a/arch/mips/au1000/xxs1500/init.c @@ -52,8 +52,6 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; - mips_machtype = MACH_XXS1500; /* set the platform # */ - prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff -puN /dev/null arch/mips/basler/excite/Kconfig --- /dev/null +++ a/arch/mips/basler/excite/Kconfig @@ -0,0 +1,9 @@ +config BASLER_EXCITE_PROTOTYPE + bool "Support for pre-release units" + depends on BASLER_EXCITE + default n + help + Pre-series (prototype) units are different from later ones in + some ways. Select this option if you have one of these. Please + note that a kernel built with this option selected will not be + able to run on normal units. diff -puN arch/mips/basler/excite/excite_prom.c~git-mips arch/mips/basler/excite/excite_prom.c --- a/arch/mips/basler/excite/excite_prom.c~git-mips +++ a/arch/mips/basler/excite/excite_prom.c @@ -135,8 +135,6 @@ void __init prom_init(void) #ifdef CONFIG_64BIT # error 64 bit support not implemented #endif /* CONFIG_64BIT */ - - mips_machtype = MACH_TITAN_EXCITE; } /* This is called from free_initmem(), so we need to provide it */ diff -puN arch/mips/cobalt/reset.c~git-mips arch/mips/cobalt/reset.c --- a/arch/mips/cobalt/reset.c~git-mips +++ a/arch/mips/cobalt/reset.c @@ -10,9 +10,10 @@ */ #include #include -#include #include +#include + #include #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000)) @@ -29,28 +30,15 @@ device_initcall(ledtrig_power_off_init); void cobalt_machine_halt(void) { - int state, last, diff; - unsigned long mark; - /* * turn on power off LED on RaQ - * - * restart if ENTER and SELECT are pressed */ - - last = COBALT_KEY_PORT; - led_trigger_event(power_off_led_trigger, LED_FULL); - for (state = 0;;) { - diff = COBALT_KEY_PORT ^ last; - last ^= diff; - - if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT))) - writeb(RESET, RESET_PORT); - - for (mark = jiffies; jiffies - mark < HZ;) - ; + local_irq_disable(); + while (1) { + if (cpu_wait) + cpu_wait(); } } diff -puN arch/mips/configs/atlas_defconfig~git-mips arch/mips/configs/atlas_defconfig --- a/arch/mips/configs/atlas_defconfig~git-mips +++ a/arch/mips/configs/atlas_defconfig @@ -37,7 +37,6 @@ CONFIG_MIPS_ATLAS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_MIPS_ATLAS=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/bigsur_defconfig~git-mips arch/mips/configs/bigsur_defconfig --- a/arch/mips/configs/bigsur_defconfig~git-mips +++ a/arch/mips/configs/bigsur_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_SIBYTE_BIGSUR=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/capcella_defconfig~git-mips arch/mips/configs/capcella_defconfig --- a/arch/mips/configs/capcella_defconfig~git-mips +++ a/arch/mips/configs/capcella_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/cobalt_defconfig~git-mips arch/mips/configs/cobalt_defconfig --- a/arch/mips/configs/cobalt_defconfig~git-mips +++ a/arch/mips/configs/cobalt_defconfig @@ -24,7 +24,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/db1000_defconfig~git-mips arch/mips/configs/db1000_defconfig --- a/arch/mips/configs/db1000_defconfig~git-mips +++ a/arch/mips/configs/db1000_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/db1100_defconfig~git-mips arch/mips/configs/db1100_defconfig --- a/arch/mips/configs/db1100_defconfig~git-mips +++ a/arch/mips/configs/db1100_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/db1200_defconfig~git-mips arch/mips/configs/db1200_defconfig --- a/arch/mips/configs/db1200_defconfig~git-mips +++ a/arch/mips/configs/db1200_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/db1500_defconfig~git-mips arch/mips/configs/db1500_defconfig --- a/arch/mips/configs/db1500_defconfig~git-mips +++ a/arch/mips/configs/db1500_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/db1550_defconfig~git-mips arch/mips/configs/db1550_defconfig --- a/arch/mips/configs/db1550_defconfig~git-mips +++ a/arch/mips/configs/db1550_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/decstation_defconfig~git-mips arch/mips/configs/decstation_defconfig --- a/arch/mips/configs/decstation_defconfig~git-mips +++ a/arch/mips/configs/decstation_defconfig @@ -37,7 +37,6 @@ CONFIG_MACH_DECSTATION=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_MACH_DECSTATION=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/e55_defconfig~git-mips arch/mips/configs/e55_defconfig --- a/arch/mips/configs/e55_defconfig~git-mips +++ a/arch/mips/configs/e55_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/emma2rh_defconfig~git-mips arch/mips/configs/emma2rh_defconfig --- a/arch/mips/configs/emma2rh_defconfig~git-mips +++ a/arch/mips/configs/emma2rh_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set CONFIG_MARKEINS=y # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_MARKEINS=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/excite_defconfig~git-mips arch/mips/configs/excite_defconfig --- a/arch/mips/configs/excite_defconfig~git-mips +++ a/arch/mips/configs/excite_defconfig @@ -38,7 +38,6 @@ CONFIG_BASLER_EXCITE=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_BASLER_EXCITE=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/fulong_defconfig~git-mips arch/mips/configs/fulong_defconfig --- a/arch/mips/configs/fulong_defconfig~git-mips +++ a/arch/mips/configs/fulong_defconfig @@ -23,7 +23,6 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -33,7 +32,6 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/ip22_defconfig~git-mips arch/mips/configs/ip22_defconfig --- a/arch/mips/configs/ip22_defconfig~git-mips +++ a/arch/mips/configs/ip22_defconfig @@ -25,7 +25,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -36,7 +35,6 @@ CONFIG_SGI_IP22=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/ip27_defconfig~git-mips arch/mips/configs/ip27_defconfig --- a/arch/mips/configs/ip27_defconfig~git-mips +++ a/arch/mips/configs/ip27_defconfig @@ -24,7 +24,6 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_SGI_IP27=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/ip32_defconfig~git-mips arch/mips/configs/ip32_defconfig --- a/arch/mips/configs/ip32_defconfig~git-mips +++ a/arch/mips/configs/ip32_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_SGI_IP32=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/jazz_defconfig~git-mips arch/mips/configs/jazz_defconfig --- a/arch/mips/configs/jazz_defconfig~git-mips +++ a/arch/mips/configs/jazz_defconfig @@ -37,7 +37,6 @@ CONFIG_MACH_JAZZ=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_MACH_JAZZ=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/jmr3927_defconfig~git-mips arch/mips/configs/jmr3927_defconfig --- a/arch/mips/configs/jmr3927_defconfig~git-mips +++ a/arch/mips/configs/jmr3927_defconfig @@ -24,7 +24,6 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set CONFIG_TOSHIBA_JMR3927=y @@ -464,7 +462,6 @@ CONFIG_SERIAL_TXX9_STDSERIAL=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set # CONFIG_R3964 is not set @@ -482,6 +479,20 @@ CONFIG_DEVPORT=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_TXX9_WDT=y + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set # # Multifunction device drivers diff -puN arch/mips/configs/lasat_defconfig~git-mips arch/mips/configs/lasat_defconfig --- a/arch/mips/configs/lasat_defconfig~git-mips +++ a/arch/mips/configs/lasat_defconfig @@ -25,7 +25,6 @@ CONFIG_LASAT=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -36,7 +35,6 @@ CONFIG_LASAT=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/malta_defconfig~git-mips arch/mips/configs/malta_defconfig --- a/arch/mips/configs/malta_defconfig~git-mips +++ a/arch/mips/configs/malta_defconfig @@ -25,7 +25,6 @@ CONFIG_MIPS_MALTA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -36,7 +35,6 @@ CONFIG_MIPS_MALTA=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/mipssim_defconfig~git-mips arch/mips/configs/mipssim_defconfig --- a/arch/mips/configs/mipssim_defconfig~git-mips +++ a/arch/mips/configs/mipssim_defconfig @@ -26,7 +26,6 @@ CONFIG_MIPS_SIM=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -37,7 +36,6 @@ CONFIG_MIPS_SIM=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/mpc30x_defconfig~git-mips arch/mips/configs/mpc30x_defconfig --- a/arch/mips/configs/mpc30x_defconfig~git-mips +++ a/arch/mips/configs/mpc30x_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/msp71xx_defconfig~git-mips arch/mips/configs/msp71xx_defconfig --- a/arch/mips/configs/msp71xx_defconfig~git-mips +++ a/arch/mips/configs/msp71xx_defconfig @@ -38,7 +38,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_VR41XX is not set CONFIG_PMC_MSP=y # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_PMC_MSP=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/mtx1_defconfig~git-mips arch/mips/configs/mtx1_defconfig --- a/arch/mips/configs/mtx1_defconfig~git-mips +++ a/arch/mips/configs/mtx1_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set @@ -1617,6 +1615,7 @@ CONFIG_INPUT_EVBUG=m # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_SUNKBD=m CONFIG_KEYBOARD_LKKBD=m CONFIG_KEYBOARD_XTKBD=m diff -puN arch/mips/configs/pb1100_defconfig~git-mips arch/mips/configs/pb1100_defconfig --- a/arch/mips/configs/pb1100_defconfig~git-mips +++ a/arch/mips/configs/pb1100_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/pb1500_defconfig~git-mips arch/mips/configs/pb1500_defconfig --- a/arch/mips/configs/pb1500_defconfig~git-mips +++ a/arch/mips/configs/pb1500_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/pb1550_defconfig~git-mips arch/mips/configs/pb1550_defconfig --- a/arch/mips/configs/pb1550_defconfig~git-mips +++ a/arch/mips/configs/pb1550_defconfig @@ -38,7 +38,6 @@ CONFIG_MIPS_PB1550=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -48,7 +47,6 @@ CONFIG_MIPS_PB1550=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/pnx8550-jbs_defconfig~git-mips arch/mips/configs/pnx8550-jbs_defconfig --- a/arch/mips/configs/pnx8550-jbs_defconfig~git-mips +++ a/arch/mips/configs/pnx8550-jbs_defconfig @@ -37,7 +37,6 @@ CONFIG_PNX8550_JBS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_PNX8550_JBS=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/pnx8550-stb810_defconfig~git-mips arch/mips/configs/pnx8550-stb810_defconfig --- a/arch/mips/configs/pnx8550-stb810_defconfig~git-mips +++ a/arch/mips/configs/pnx8550-stb810_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y CONFIG_PNX8550_STB810=y # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_PNX8550_STB810=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/qemu_defconfig~git-mips arch/mips/configs/qemu_defconfig --- a/arch/mips/configs/qemu_defconfig~git-mips +++ a/arch/mips/configs/qemu_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -CONFIG_QEMU=y # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_QEMU=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/rbhma4200_defconfig~git-mips arch/mips/configs/rbhma4200_defconfig --- a/arch/mips/configs/rbhma4200_defconfig~git-mips +++ a/arch/mips/configs/rbhma4200_defconfig @@ -24,7 +24,6 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set @@ -431,7 +429,6 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set # CONFIG_R3964 is not set @@ -449,6 +446,20 @@ CONFIG_DEVPORT=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_TXX9_WDT=m + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set # # Multifunction device drivers diff -puN arch/mips/configs/rbhma4500_defconfig~git-mips arch/mips/configs/rbhma4500_defconfig --- a/arch/mips/configs/rbhma4500_defconfig~git-mips +++ a/arch/mips/configs/rbhma4500_defconfig @@ -24,7 +24,6 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set @@ -450,7 +448,6 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set # CONFIG_R3964 is not set @@ -479,6 +476,20 @@ CONFIG_SPI_AT25=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_TXX9_WDT=m + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set # # Multifunction device drivers diff -puN arch/mips/configs/rm200_defconfig~git-mips arch/mips/configs/rm200_defconfig --- a/arch/mips/configs/rm200_defconfig~git-mips +++ a/arch/mips/configs/rm200_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_ZONE_DMA=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/sb1250-swarm_defconfig~git-mips arch/mips/configs/sb1250-swarm_defconfig --- a/arch/mips/configs/sb1250-swarm_defconfig~git-mips +++ a/arch/mips/configs/sb1250-swarm_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_SIBYTE_SWARM=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/sead_defconfig~git-mips arch/mips/configs/sead_defconfig --- a/arch/mips/configs/sead_defconfig~git-mips +++ a/arch/mips/configs/sead_defconfig @@ -37,7 +37,6 @@ CONFIG_MIPS_SEAD=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_MIPS_SEAD=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/tb0219_defconfig~git-mips arch/mips/configs/tb0219_defconfig --- a/arch/mips/configs/tb0219_defconfig~git-mips +++ a/arch/mips/configs/tb0219_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/tb0226_defconfig~git-mips arch/mips/configs/tb0226_defconfig --- a/arch/mips/configs/tb0226_defconfig~git-mips +++ a/arch/mips/configs/tb0226_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/tb0287_defconfig~git-mips arch/mips/configs/tb0287_defconfig --- a/arch/mips/configs/tb0287_defconfig~git-mips +++ a/arch/mips/configs/tb0287_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/workpad_defconfig~git-mips arch/mips/configs/workpad_defconfig --- a/arch/mips/configs/workpad_defconfig~git-mips +++ a/arch/mips/configs/workpad_defconfig @@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/configs/wrppmc_defconfig~git-mips arch/mips/configs/wrppmc_defconfig --- a/arch/mips/configs/wrppmc_defconfig~git-mips +++ a/arch/mips/configs/wrppmc_defconfig @@ -37,7 +37,6 @@ CONFIG_WR_PPMC=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_WR_PPMC=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/configs/yosemite_defconfig~git-mips arch/mips/configs/yosemite_defconfig --- a/arch/mips/configs/yosemite_defconfig~git-mips +++ a/arch/mips/configs/yosemite_defconfig @@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set CONFIG_PMC_YOSEMITE=y -# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,7 +46,6 @@ CONFIG_PMC_YOSEMITE=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff -puN arch/mips/dec/time.c~git-mips arch/mips/dec/time.c --- a/arch/mips/dec/time.c~git-mips +++ a/arch/mips/dec/time.c @@ -161,7 +161,6 @@ static cycle_t dec_ioasic_hpt_read(void) void __init plat_time_init(void) { - mips_timer_state = dec_timer_state; mips_timer_ack = dec_timer_ack; if (!cpu_has_counter && IOASIC) diff -puN arch/mips/defconfig~git-mips arch/mips/defconfig --- a/arch/mips/defconfig~git-mips +++ a/arch/mips/defconfig @@ -25,7 +25,6 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -36,7 +35,6 @@ CONFIG_SGI_IP22=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff -puN arch/mips/fw/arc/cmdline.c~git-mips arch/mips/fw/arc/cmdline.c --- a/arch/mips/fw/arc/cmdline.c~git-mips +++ a/arch/mips/fw/arc/cmdline.c @@ -52,7 +52,7 @@ static char * __init move_firmware_args( strcat(cp, used_arc[i][1]); cp += strlen(used_arc[i][1]); /* ... and now the argument */ - s = strstr(prom_argv(actr), "="); + s = strchr(prom_argv(actr), '='); if (s) { s++; strcpy(cp, s); diff -puN arch/mips/fw/arc/init.c~git-mips arch/mips/fw/arc/init.c --- a/arch/mips/fw/arc/init.c~git-mips +++ a/arch/mips/fw/arc/init.c @@ -12,6 +12,7 @@ #include #include +#include #undef DEBUG_PROM_INIT @@ -48,4 +49,11 @@ void __init prom_init(void) ArcRead(0, &c, 1, &cnt); ArcEnterInteractiveMode(); #endif +#ifdef CONFIG_SGI_IP27 + { + extern struct plat_smp_ops ip27_smp_ops; + + register_smp_ops(&ip27_smp_ops); + } +#endif } diff -puN arch/mips/fw/cfe/cfe_api.c~git-mips arch/mips/fw/cfe/cfe_api.c --- a/arch/mips/fw/cfe/cfe_api.c~git-mips +++ a/arch/mips/fw/cfe/cfe_api.c @@ -16,19 +16,16 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* ********************************************************************* - * - * Broadcom Common Firmware Environment (CFE) - * - * Device Function stubs File: cfe_api.c - * - * This module contains device function stubs (small routines to - * call the standard "iocb" interface entry point to CFE). - * There should be one routine here per iocb function call. - * - * Authors: Mitch Lichtenberg, Chris Demetriou - * - ********************************************************************* */ +/* + * + * Broadcom Common Firmware Environment (CFE) + * + * This module contains device function stubs (small routines to + * call the standard "iocb" interface entry point to CFE). + * There should be one routine here per iocb function call. + * + * Authors: Mitch Lichtenberg, Chris Demetriou + */ #include #include "cfe_api_int.h" @@ -37,12 +34,8 @@ #define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n)) #define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x)) -#ifdef CFE_API_IMPL_NAMESPACE -#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a) -#endif -int cfe_iocb_dispatch(cfe_xiocb_t * xiocb); +int cfe_iocb_dispatch(struct cfe_xiocb *xiocb); -#if defined(CFE_API_common) || defined(CFE_API_ALL) /* * Declare the dispatch function with args of "intptr_t". * This makes sure whatever model we're compiling in @@ -53,27 +46,25 @@ int cfe_iocb_dispatch(cfe_xiocb_t * xioc */ static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0; -static cfe_xuint_t cfe_handle = 0; +static u64 cfe_handle = 0; -int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept) +int cfe_init(u64 handle, u64 ept) { cfe_dispfunc = NATIVE_FROM_XPTR(ept); cfe_handle = handle; return 0; } -int cfe_iocb_dispatch(cfe_xiocb_t * xiocb) +int cfe_iocb_dispatch(struct cfe_xiocb * xiocb) { if (!cfe_dispfunc) return -1; return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb); } -#endif /* CFE_API_common || CFE_API_ALL */ -#if defined(CFE_API_close) || defined(CFE_API_ALL) int cfe_close(int handle) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE; xiocb.xiocb_status = 0; @@ -86,18 +77,16 @@ int cfe_close(int handle) return xiocb.xiocb_status; } -#endif /* CFE_API_close || CFE_API_ALL */ -#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL) int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); + xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl); xiocb.plist.xiocb_cpuctl.cpu_number = cpu; xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START; xiocb.plist.xiocb_cpuctl.gp_val = gp; @@ -109,18 +98,16 @@ int cfe_cpu_start(int cpu, void (*fn) (v return xiocb.xiocb_status; } -#endif /* CFE_API_cpu_start || CFE_API_ALL */ -#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL) int cfe_cpu_stop(int cpu) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); + xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl); xiocb.plist.xiocb_cpuctl.cpu_number = cpu; xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP; @@ -128,18 +115,16 @@ int cfe_cpu_stop(int cpu) return xiocb.xiocb_status; } -#endif /* CFE_API_cpu_stop || CFE_API_ALL */ -#if defined(CFE_API_enumenv) || defined(CFE_API_ALL) int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_ENV_SET; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.xiocb_psize = sizeof(struct xiocb_envbuf); xiocb.plist.xiocb_envbuf.enum_idx = idx; xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); xiocb.plist.xiocb_envbuf.name_length = namelen; @@ -150,20 +135,17 @@ int cfe_enumenv(int idx, char *name, int return xiocb.xiocb_status; } -#endif /* CFE_API_enumenv || CFE_API_ALL */ -#if defined(CFE_API_enummem) || defined(CFE_API_ALL) int -cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length, - cfe_xuint_t * type) +cfe_enummem(int idx, int flags, u64 *start, u64 *length, u64 *type) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = flags; - xiocb.xiocb_psize = sizeof(xiocb_meminfo_t); + xiocb.xiocb_psize = sizeof(struct xiocb_meminfo); xiocb.plist.xiocb_meminfo.mi_idx = idx; cfe_iocb_dispatch(&xiocb); @@ -177,30 +159,26 @@ cfe_enummem(int idx, int flags, cfe_xuin return 0; } -#endif /* CFE_API_enummem || CFE_API_ALL */ -#if defined(CFE_API_exit) || defined(CFE_API_ALL) int cfe_exit(int warm, int status) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_RESTART; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0; - xiocb.xiocb_psize = sizeof(xiocb_exitstat_t); + xiocb.xiocb_psize = sizeof(struct xiocb_exitstat); xiocb.plist.xiocb_exitstat.status = status; cfe_iocb_dispatch(&xiocb); return xiocb.xiocb_status; } -#endif /* CFE_API_exit || CFE_API_ALL */ -#if defined(CFE_API_flushcache) || defined(CFE_API_ALL) int cfe_flushcache(int flg) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE; xiocb.xiocb_status = 0; @@ -212,34 +190,30 @@ int cfe_flushcache(int flg) return xiocb.xiocb_status; } -#endif /* CFE_API_flushcache || CFE_API_ALL */ -#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL) int cfe_getdevinfo(char *name) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.xiocb_psize = sizeof(struct xiocb_buffer); xiocb.plist.xiocb_buffer.buf_offset = 0; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); + xiocb.plist.xiocb_buffer.buf_length = strlen(name); cfe_iocb_dispatch(&xiocb); if (xiocb.xiocb_status < 0) return xiocb.xiocb_status; - return xiocb.plist.xiocb_buffer.buf_devflags; + return xiocb.plist.xiocb_buffer.buf_ioctlcmd; } -#endif /* CFE_API_getdevinfo || CFE_API_ALL */ -#if defined(CFE_API_getenv) || defined(CFE_API_ALL) int cfe_getenv(char *name, char *dest, int destlen) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; *dest = 0; @@ -247,10 +221,10 @@ int cfe_getenv(char *name, char *dest, i xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.xiocb_psize = sizeof(struct xiocb_envbuf); xiocb.plist.xiocb_envbuf.enum_idx = 0; xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); + xiocb.plist.xiocb_envbuf.name_length = strlen(name); xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest); xiocb.plist.xiocb_envbuf.val_length = destlen; @@ -258,18 +232,16 @@ int cfe_getenv(char *name, char *dest, i return xiocb.xiocb_status; } -#endif /* CFE_API_getenv || CFE_API_ALL */ -#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL) int cfe_getfwinfo(cfe_fwinfo_t * info) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t); + xiocb.xiocb_psize = sizeof(struct xiocb_fwinfo); cfe_iocb_dispatch(&xiocb); @@ -292,12 +264,10 @@ int cfe_getfwinfo(cfe_fwinfo_t * info) return 0; } -#endif /* CFE_API_getfwinfo || CFE_API_ALL */ -#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL) int cfe_getstdhandle(int flg) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE; xiocb.xiocb_status = 0; @@ -311,23 +281,17 @@ int cfe_getstdhandle(int flg) return xiocb.xiocb_status; return xiocb.xiocb_handle; } -#endif /* CFE_API_getstdhandle || CFE_API_ALL */ -#if defined(CFE_API_getticks) || defined(CFE_API_ALL) int64_t -#ifdef CFE_API_IMPL_NAMESPACE -__cfe_getticks(void) -#else cfe_getticks(void) -#endif { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_time_t); + xiocb.xiocb_psize = sizeof(struct xiocb_time); xiocb.plist.xiocb_time.ticks = 0; cfe_iocb_dispatch(&xiocb); @@ -335,18 +299,16 @@ cfe_getticks(void) return xiocb.plist.xiocb_time.ticks; } -#endif /* CFE_API_getticks || CFE_API_ALL */ -#if defined(CFE_API_inpstat) || defined(CFE_API_ALL) int cfe_inpstat(int handle) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_inpstat_t); + xiocb.xiocb_psize = sizeof(struct xiocb_inpstat); xiocb.plist.xiocb_inpstat.inp_status = 0; cfe_iocb_dispatch(&xiocb); @@ -355,20 +317,18 @@ int cfe_inpstat(int handle) return xiocb.xiocb_status; return xiocb.plist.xiocb_inpstat.inp_status; } -#endif /* CFE_API_inpstat || CFE_API_ALL */ -#if defined(CFE_API_ioctl) || defined(CFE_API_ALL) int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, - int length, int *retlen, cfe_xuint_t offset) + int length, int *retlen, u64 offset) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.xiocb_psize = sizeof(struct xiocb_buffer); xiocb.plist.xiocb_buffer.buf_offset = offset; xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); @@ -380,21 +340,19 @@ cfe_ioctl(int handle, unsigned int ioctl *retlen = xiocb.plist.xiocb_buffer.buf_retlen; return xiocb.xiocb_status; } -#endif /* CFE_API_ioctl || CFE_API_ALL */ -#if defined(CFE_API_open) || defined(CFE_API_ALL) int cfe_open(char *name) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.xiocb_psize = sizeof(struct xiocb_buffer); xiocb.plist.xiocb_buffer.buf_offset = 0; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); + xiocb.plist.xiocb_buffer.buf_length = strlen(name); cfe_iocb_dispatch(&xiocb); @@ -402,27 +360,21 @@ int cfe_open(char *name) return xiocb.xiocb_status; return xiocb.xiocb_handle; } -#endif /* CFE_API_open || CFE_API_ALL */ -#if defined(CFE_API_read) || defined(CFE_API_ALL) int cfe_read(int handle, unsigned char *buffer, int length) { return cfe_readblk(handle, 0, buffer, length); } -#endif /* CFE_API_read || CFE_API_ALL */ -#if defined(CFE_API_readblk) || defined(CFE_API_ALL) -int -cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer, - int length) +int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_READ; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.xiocb_psize = sizeof(struct xiocb_buffer); xiocb.plist.xiocb_buffer.buf_offset = offset; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); xiocb.plist.xiocb_buffer.buf_length = length; @@ -433,62 +385,41 @@ cfe_readblk(int handle, cfe_xint_t offse return xiocb.xiocb_status; return xiocb.plist.xiocb_buffer.buf_retlen; } -#endif /* CFE_API_readblk || CFE_API_ALL */ -#if defined(CFE_API_setenv) || defined(CFE_API_ALL) int cfe_setenv(char *name, char *val) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_ENV_SET; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.xiocb_psize = sizeof(struct xiocb_envbuf); xiocb.plist.xiocb_envbuf.enum_idx = 0; xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); + xiocb.plist.xiocb_envbuf.name_length = strlen(name); xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); - xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val); + xiocb.plist.xiocb_envbuf.val_length = strlen(val); cfe_iocb_dispatch(&xiocb); return xiocb.xiocb_status; } -#endif /* CFE_API_setenv || CFE_API_ALL */ -#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \ - && !defined(CFE_API_STRLEN_CUSTOM) -int cfe_strlen(char *name) -{ - int count = 0; - - while (*name++) - count++; - - return count; -} -#endif /* CFE_API_strlen || CFE_API_ALL */ - -#if defined(CFE_API_write) || defined(CFE_API_ALL) int cfe_write(int handle, unsigned char *buffer, int length) { return cfe_writeblk(handle, 0, buffer, length); } -#endif /* CFE_API_write || CFE_API_ALL */ -#if defined(CFE_API_writeblk) || defined(CFE_API_ALL) -int -cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer, - int length) +int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) { - cfe_xiocb_t xiocb; + struct cfe_xiocb xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.xiocb_psize = sizeof(struct xiocb_buffer); xiocb.plist.xiocb_buffer.buf_offset = offset; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); xiocb.plist.xiocb_buffer.buf_length = length; @@ -499,4 +430,3 @@ cfe_writeblk(int handle, cfe_xint_t offs return xiocb.xiocb_status; return xiocb.plist.xiocb_buffer.buf_retlen; } -#endif /* CFE_API_writeblk || CFE_API_ALL */ diff -puN arch/mips/fw/cfe/cfe_api_int.h~git-mips arch/mips/fw/cfe/cfe_api_int.h --- a/arch/mips/fw/cfe/cfe_api_int.h~git-mips +++ a/arch/mips/fw/cfe/cfe_api_int.h @@ -15,28 +15,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* ********************************************************************* - * - * Broadcom Common Firmware Environment (CFE) - * - * Device function prototypes File: cfe_api_int.h - * - * This header defines all internal types and macros for the - * library. This is stuff that's not exported to an app - * using the library. - * - * Authors: Mitch Lichtenberg, Chris Demetriou - * - ********************************************************************* */ - #ifndef CFE_API_INT_H #define CFE_API_INT_H -/* ********************************************************************* - * Constants - ********************************************************************* */ - +/* + * Constants. + */ #define CFE_CMD_FW_GETINFO 0 #define CFE_CMD_FW_RESTART 1 #define CFE_CMD_FW_BOOT 2 @@ -64,89 +48,101 @@ #define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ -/* ********************************************************************* - * Structures - ********************************************************************* */ - -typedef uint64_t cfe_xuint_t; -typedef int64_t cfe_xint_t; -typedef int64_t cfe_xptr_t; +/* + * Structures. + */ + +/* eeek, signed "pointers" */ +typedef s64 cfe_xptr_t; -typedef struct xiocb_buffer_s { - cfe_xuint_t buf_offset; /* offset on device (bytes) */ +struct xiocb_buffer { + u64 buf_offset; /* offset on device (bytes) */ cfe_xptr_t buf_ptr; /* pointer to a buffer */ - cfe_xuint_t buf_length; /* length of this buffer */ - cfe_xuint_t buf_retlen; /* returned length (for read ops) */ - cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ -} xiocb_buffer_t; - -#define buf_devflags buf_ioctlcmd /* returned device info flags */ - -typedef struct xiocb_inpstat_s { - cfe_xuint_t inp_status; /* 1 means input available */ -} xiocb_inpstat_t; + u64 buf_length; /* length of this buffer */ + u64 buf_retlen; /* returned length (for read ops) */ + u64 buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ +}; + +struct xiocb_inpstat { + u64 inp_status; /* 1 means input available */ +}; -typedef struct xiocb_envbuf_s { - cfe_xint_t enum_idx; /* 0-based enumeration index */ +struct xiocb_envbuf { + s64 enum_idx; /* 0-based enumeration index */ cfe_xptr_t name_ptr; /* name string buffer */ - cfe_xint_t name_length; /* size of name buffer */ + s64 name_length; /* size of name buffer */ cfe_xptr_t val_ptr; /* value string buffer */ - cfe_xint_t val_length; /* size of value string buffer */ -} xiocb_envbuf_t; + s64 val_length; /* size of value string buffer */ +}; -typedef struct xiocb_cpuctl_s { - cfe_xuint_t cpu_number; /* cpu number to control */ - cfe_xuint_t cpu_command; /* command to issue to CPU */ - cfe_xuint_t start_addr; /* CPU start address */ - cfe_xuint_t gp_val; /* starting GP value */ - cfe_xuint_t sp_val; /* starting SP value */ - cfe_xuint_t a1_val; /* starting A1 value */ -} xiocb_cpuctl_t; - -typedef struct xiocb_time_s { - cfe_xint_t ticks; /* current time in ticks */ -} xiocb_time_t; - -typedef struct xiocb_exitstat_s { - cfe_xint_t status; -} xiocb_exitstat_t; - -typedef struct xiocb_meminfo_s { - cfe_xint_t mi_idx; /* 0-based enumeration index */ - cfe_xint_t mi_type; /* type of memory block */ - cfe_xuint_t mi_addr; /* physical start address */ - cfe_xuint_t mi_size; /* block size */ -} xiocb_meminfo_t; - -typedef struct xiocb_fwinfo_s { - cfe_xint_t fwi_version; /* major, minor, eco version */ - cfe_xint_t fwi_totalmem; /* total installed mem */ - cfe_xint_t fwi_flags; /* various flags */ - cfe_xint_t fwi_boardid; /* board ID */ - cfe_xint_t fwi_bootarea_va; /* VA of boot area */ - cfe_xint_t fwi_bootarea_pa; /* PA of boot area */ - cfe_xint_t fwi_bootarea_size; /* size of boot area */ - cfe_xint_t fwi_reserved1; - cfe_xint_t fwi_reserved2; - cfe_xint_t fwi_reserved3; -} xiocb_fwinfo_t; - -typedef struct cfe_xiocb_s { - cfe_xuint_t xiocb_fcode; /* IOCB function code */ - cfe_xint_t xiocb_status; /* return status */ - cfe_xint_t xiocb_handle; /* file/device handle */ - cfe_xuint_t xiocb_flags; /* flags for this IOCB */ - cfe_xuint_t xiocb_psize; /* size of parameter list */ +struct xiocb_cpuctl { + u64 cpu_number; /* cpu number to control */ + u64 cpu_command; /* command to issue to CPU */ + u64 start_addr; /* CPU start address */ + u64 gp_val; /* starting GP value */ + u64 sp_val; /* starting SP value */ + u64 a1_val; /* starting A1 value */ +}; + +struct xiocb_time { + s64 ticks; /* current time in ticks */ +}; + +struct xiocb_exitstat{ + s64 status; +}; + +struct xiocb_meminfo { + s64 mi_idx; /* 0-based enumeration index */ + s64 mi_type; /* type of memory block */ + u64 mi_addr; /* physical start address */ + u64 mi_size; /* block size */ +}; + +struct xiocb_fwinfo { + s64 fwi_version; /* major, minor, eco version */ + s64 fwi_totalmem; /* total installed mem */ + s64 fwi_flags; /* various flags */ + s64 fwi_boardid; /* board ID */ + s64 fwi_bootarea_va; /* VA of boot area */ + s64 fwi_bootarea_pa; /* PA of boot area */ + s64 fwi_bootarea_size; /* size of boot area */ + s64 fwi_reserved1; + s64 fwi_reserved2; + s64 fwi_reserved3; +}; + +struct cfe_xiocb { + u64 xiocb_fcode; /* IOCB function code */ + s64 xiocb_status; /* return status */ + s64 xiocb_handle; /* file/device handle */ + u64 xiocb_flags; /* flags for this IOCB */ + u64 xiocb_psize; /* size of parameter list */ union { - xiocb_buffer_t xiocb_buffer; /* buffer parameters */ - xiocb_inpstat_t xiocb_inpstat; /* input status parameters */ - xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */ - xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */ - xiocb_time_t xiocb_time; /* timer parameters */ - xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */ - xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */ - xiocb_exitstat_t xiocb_exitstat; /* Exit Status */ + /* buffer parameters */ + struct xiocb_buffer xiocb_buffer; + + /* input status parameters */ + struct xiocb_inpstat xiocb_inpstat; + + /* environment function parameters */ + struct xiocb_envbuf xiocb_envbuf; + + /* CPU control parameters */ + struct xiocb_cpuctl xiocb_cpuctl; + + /* timer parameters */ + struct xiocb_time xiocb_time; + + /* memory arena info parameters */ + struct xiocb_meminfo xiocb_meminfo; + + /* firmware information */ + struct xiocb_fwinfo xiocb_fwinfo; + + /* Exit Status */ + struct xiocb_exitstat xiocb_exitstat; } plist; -} cfe_xiocb_t; +}; -#endif /* CFE_API_INT_H */ +#endif /* CFE_API_INT_H */ diff -puN /dev/null arch/mips/fw/lib/Makefile --- /dev/null +++ a/arch/mips/fw/lib/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for generic prom monitor library routines under Linux. +# + +lib-$(CONFIG_64BIT) += call_o32.o diff -puN /dev/null arch/mips/fw/lib/call_o32.S --- /dev/null +++ a/arch/mips/fw/lib/call_o32.S @@ -0,0 +1,97 @@ +/* + * arch/mips/dec/prom/call_o32.S + * + * O32 interface for the 64 (or N32) ABI. + * + * Copyright (C) 2002 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + +/* Maximum number of arguments supported. Must be even! */ +#define O32_ARGC 32 +/* Number of static registers we save. */ +#define O32_STATC 11 +/* Frame size for static register */ +#define O32_FRAMESZ (SZREG * O32_STATC) +/* Frame size on new stack */ +#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC) + + .text + +/* + * O32 function call dispatcher, for interfacing 32-bit ROM routines. + * + * The standard 64 (N32) calling sequence is supported, with a0 + * holding a function pointer, a1 a new stack pointer, a2-a7 -- its + * first six arguments and the stack -- remaining ones (up to O32_ARGC, + * including a2-a7). Static registers, gp and fp are preserved, v0 holds + * a result. This code relies on the called o32 function for sp and ra + * restoration and this dispatcher has to be placed in a KSEGx (or KUSEG) + * address space. Any pointers passed have to point to addresses within + * one of these spaces as well. + */ +NESTED(call_o32, O32_FRAMESZ, ra) + REG_SUBU sp,O32_FRAMESZ + + REG_S ra,O32_FRAMESZ-1*SZREG(sp) + REG_S fp,O32_FRAMESZ-2*SZREG(sp) + REG_S gp,O32_FRAMESZ-3*SZREG(sp) + REG_S s7,O32_FRAMESZ-4*SZREG(sp) + REG_S s6,O32_FRAMESZ-5*SZREG(sp) + REG_S s5,O32_FRAMESZ-6*SZREG(sp) + REG_S s4,O32_FRAMESZ-7*SZREG(sp) + REG_S s3,O32_FRAMESZ-8*SZREG(sp) + REG_S s2,O32_FRAMESZ-9*SZREG(sp) + REG_S s1,O32_FRAMESZ-10*SZREG(sp) + REG_S s0,O32_FRAMESZ-11*SZREG(sp) + + move jp,a0 + REG_SUBU s0,a1,O32_FRAMESZ_NEW + REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0) + + sll a0,a2,zero + sll a1,a3,zero + sll a2,a4,zero + sll a3,a5,zero + sw a6,0x10(s0) + sw a7,0x14(s0) + + PTR_LA t0,O32_FRAMESZ(sp) + PTR_LA t1,0x18(s0) + li t2,O32_ARGC-6 +1: + lw t3,(t0) + REG_ADDU t0,SZREG + sw t3,(t1) + REG_SUBU t2,1 + REG_ADDU t1,4 + bnez t2,1b + + move sp,s0 + + jalr jp + + REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp) + + REG_L s0,O32_FRAMESZ-11*SZREG(sp) + REG_L s1,O32_FRAMESZ-10*SZREG(sp) + REG_L s2,O32_FRAMESZ-9*SZREG(sp) + REG_L s3,O32_FRAMESZ-8*SZREG(sp) + REG_L s4,O32_FRAMESZ-7*SZREG(sp) + REG_L s5,O32_FRAMESZ-6*SZREG(sp) + REG_L s6,O32_FRAMESZ-5*SZREG(sp) + REG_L s7,O32_FRAMESZ-4*SZREG(sp) + REG_L gp,O32_FRAMESZ-3*SZREG(sp) + REG_L fp,O32_FRAMESZ-2*SZREG(sp) + REG_L ra,O32_FRAMESZ-1*SZREG(sp) + + REG_ADDU sp,O32_FRAMESZ + jr ra +END(call_o32) diff -puN /dev/null arch/mips/fw/sni/Makefile --- /dev/null +++ a/arch/mips/fw/sni/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the SNI prom monitor routines under Linux. +# + +lib-$(CONFIG_SNIPROM) += sniprom.o diff -puN /dev/null arch/mips/fw/sni/sniprom.c --- /dev/null +++ a/arch/mips/fw/sni/sniprom.c @@ -0,0 +1,151 @@ +/* + * Big Endian PROM code for SNI RM machines + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org) + * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* special SNI prom calls */ +/* + * This does not exist in all proms - SINIX compares + * the prom env variable "version" against "2.0008" + * or greater. If lesser it tries to probe interesting + * registers + */ +#define PROM_GET_MEMCONF 58 +#define PROM_GET_HWCONF 61 + +#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000) +#define PROM_ENTRY(x) (PROM_VEC + (x)) + +#define ___prom_putchar ((int *(*)(int))PROM_ENTRY(PROM_PUTCHAR)) +#define ___prom_getenv ((char *(*)(char *))PROM_ENTRY(PROM_GETENV)) +#define ___prom_get_memconf ((void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF)) +#define ___prom_get_hwconf ((u32 (*)(void))PROM_ENTRY(PROM_GET_HWCONF)) + +#ifdef CONFIG_64BIT + +static u8 o32_stk[16384]; +#define O32_STK &o32_stk[sizeof(o32_stk)] + +#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \ + __asm__(#fun " = call_o32") + +int __PROM_O32(__prom_putchar, (int *(*)(int), void *, int)); +char *__PROM_O32(__prom_getenv, (char *(*)(char *), void *, char *)); +void __PROM_O32(__prom_get_memconf, (void (*)(void *), void *, void *)); +u32 __PROM_O32(__prom_get_hwconf, (u32 (*)(void), void *)); + +#define _prom_putchar(x) __prom_putchar(___prom_putchar, O32_STK, x) +#define _prom_getenv(x) __prom_getenv(___prom_getenv, O32_STK, x) +#define _prom_get_memconf(x) __prom_get_memconf(___prom_get_memconf, O32_STK, x) +#define _prom_get_hwconf() __prom_get_hwconf(___prom_get_hwconf, O32_STK) + +#else +#define _prom_putchar(x) ___prom_putchar(x) +#define _prom_getenv(x) ___prom_getenv(x) +#define _prom_get_memconf(x) ___prom_get_memconf(x) +#define _prom_get_hwconf(x) ___prom_get_hwconf(x) +#endif + +void prom_putchar(char c) +{ + _prom_putchar(c); +} + + +char *prom_getenv(char *s) +{ + return _prom_getenv(s); +} + +void *prom_get_hwconf(void) +{ + u32 hwconf = _prom_get_hwconf(); + + if (hwconf == 0xffffffff) + return NULL; + + return (void *)CKSEG1ADDR(hwconf); +} + +void __init prom_free_prom_memory(void) +{ +} + +/* + * /proc/cpuinfo system type + * + */ +char *system_type = "Unknown"; +const char *get_system_type(void) +{ + return system_type; +} + +static void __init sni_mem_init(void) +{ + int i, memsize; + struct membank { + u32 size; + u32 base; + u32 size2; + u32 pad1; + u32 pad2; + } memconf[8]; + int brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE; + + + /* MemSIZE from prom in 16MByte chunks */ + memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16; + + pr_debug("IDProm memsize: %u MByte\n", memsize); + + /* get memory bank layout from prom */ + _prom_get_memconf(&memconf); + + pr_debug("prom_get_mem_conf memory configuration:\n"); + for (i = 0; i < 8 && memconf[i].size; i++) { + if (brd_type == SNI_BRD_PCI_TOWER || + brd_type == SNI_BRD_PCI_TOWER_CPLUS) { + if (memconf[i].base >= 0x20000000 && + memconf[i].base < 0x30000000) + memconf[i].base -= 0x20000000; + } + pr_debug("Bank%d: %08x @ %08x\n", i, + memconf[i].size, memconf[i].base); + add_memory_region(memconf[i].base, memconf[i].size, + BOOT_MEM_RAM); + } +} + +void __init prom_init(void) +{ + int argc = fw_arg0; + u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1); + int i; + + sni_mem_init(); + + /* copy prom cmdline parameters to kernel cmdline */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i])); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } +} diff -puN arch/mips/gt64120/wrppmc/setup.c~git-mips arch/mips/gt64120/wrppmc/setup.c --- a/arch/mips/gt64120/wrppmc/setup.c~git-mips +++ a/arch/mips/gt64120/wrppmc/setup.c @@ -121,8 +121,6 @@ const char *get_system_type(void) */ void __init prom_init(void) { - mips_machtype = MACH_WRPPMC; - add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); diff -puN arch/mips/jazz/setup.c~git-mips arch/mips/jazz/setup.c --- a/arch/mips/jazz/setup.c~git-mips +++ a/arch/mips/jazz/setup.c @@ -200,12 +200,19 @@ static struct platform_device jazz_cmos_ .resource = jazz_cmos_rsrc }; +static struct platform_device pcspeaker_pdev = { + .name = "pcspkr", + .id = -1, +}; + static int __init jazz_setup_devinit(void) { platform_device_register(&jazz_serial8250_device); platform_device_register(&jazz_esp_pdev); platform_device_register(&jazz_sonic_pdev); platform_device_register(&jazz_cmos_pdev); + platform_device_register(&pcspeaker_pdev); + return 0; } diff -puN arch/mips/jmr3927/rbhma3100/init.c~git-mips arch/mips/jmr3927/rbhma3100/init.c --- a/arch/mips/jmr3927/rbhma3100/init.c~git-mips +++ a/arch/mips/jmr3927/rbhma3100/init.c @@ -52,10 +52,6 @@ void __init prom_init(void) puts("Warning: TX3927 TLB off\n"); #endif -#ifdef CONFIG_TOSHIBA_JMR3927 - mips_machtype = MACH_TOSHIBA_JMR3927; -#endif - prom_init_cmdline(); add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); } diff -puN arch/mips/jmr3927/rbhma3100/setup.c~git-mips arch/mips/jmr3927/rbhma3100/setup.c --- a/arch/mips/jmr3927/rbhma3100/setup.c~git-mips +++ a/arch/mips/jmr3927/rbhma3100/setup.c @@ -29,21 +29,17 @@ #include #include -#include #include #include -#include #include #include #include #include +#include #ifdef CONFIG_SERIAL_TXX9 -#include -#include #include #endif -#include #include #include #include @@ -238,6 +234,8 @@ static void __init tx3927_setup(void) tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; /* Disable PCI snoop */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; + /* do reset on watchdog */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; #ifdef DO_WRITE_THROUGH /* Enable PCI SNOOP - with write through only */ @@ -388,3 +386,55 @@ static int __init jmr3927_rtc_init(void) return IS_ERR(dev) ? PTR_ERR(dev) : 0; } device_initcall(jmr3927_rtc_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init jmr3927_wdt_init(void) +{ + return txx9_wdt_init(TX3927_TMR_REG(2)); +} +device_initcall(jmr3927_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "imbus_clk")) + return (struct clk *)JMR3927_IMCLK; + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff -puN arch/mips/kernel/cpu-bugs64.c~git-mips arch/mips/kernel/cpu-bugs64.c --- a/arch/mips/kernel/cpu-bugs64.c~git-mips +++ a/arch/mips/kernel/cpu-bugs64.c @@ -18,6 +18,15 @@ #include #include +static char bug64hit[] __initdata = + "reliable operation impossible!\n%s"; +static char nowar[] __initdata = + "Please report to ."; +static char r4kwar[] __initdata = + "Enable CPU_R4000_WORKAROUNDS to rectify."; +static char daddiwar[] __initdata = + "Enable CPU_DADDI_WORKAROUNDS to rectify."; + static inline void align_mod(const int align, const int mod) { asm volatile( @@ -155,13 +164,7 @@ static inline void check_mult_sh(void) } printk("no.\n"); - panic("Reliable operation impossible!\n" -#ifndef CONFIG_CPU_R4000 - "Configure for R4000 to enable the workaround." -#else - "Please report to ." -#endif - ); + panic(bug64hit, !R4000_WAR ? r4kwar : nowar); } static volatile int daddi_ov __initdata = 0; @@ -233,15 +236,11 @@ static inline void check_daddi(void) } printk("no.\n"); - panic("Reliable operation impossible!\n" -#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400) - "Configure for R4000 or R4400 to enable the workaround." -#else - "Please report to ." -#endif - ); + panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); } +int daddiu_bug __initdata = -1; + static inline void check_daddiu(void) { long v, w, tmp; @@ -281,7 +280,9 @@ static inline void check_daddiu(void) : "=&r" (v), "=&r" (w), "=&r" (tmp) : "I" (0xffffffffffffdb9aUL), "I" (0x1234)); - if (v == w) { + daddiu_bug = v != w; + + if (!daddiu_bug) { printk("no.\n"); return; } @@ -303,18 +304,16 @@ static inline void check_daddiu(void) } printk("no.\n"); - panic("Reliable operation impossible!\n" -#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400) - "Configure for R4000 or R4400 to enable the workaround." -#else - "Please report to ." -#endif - ); + panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); } -void __init check_bugs64(void) +void __init check_bugs64_early(void) { check_mult_sh(); - check_daddi(); check_daddiu(); } + +void __init check_bugs64(void) +{ + check_daddi(); +} diff -puN arch/mips/kernel/cpu-probe.c~git-mips arch/mips/kernel/cpu-probe.c --- a/arch/mips/kernel/cpu-probe.c~git-mips +++ a/arch/mips/kernel/cpu-probe.c @@ -188,6 +188,8 @@ static inline void check_wait(void) case CPU_AU1500: case CPU_AU1550: case CPU_AU1200: + case CPU_AU1210: + case CPU_AU1250: if (allow_au1k_wait) cpu_wait = au1k_wait; break; @@ -733,6 +735,11 @@ static inline void cpu_probe_alchemy(str break; case 4: c->cputype = CPU_AU1200; + if (2 == (c->processor_id & 0xff)) + c->cputype = CPU_AU1250; + break; + case 5: + c->cputype = CPU_AU1210; break; default: panic("Unknown Au Core!"); @@ -858,6 +865,8 @@ static __init const char *cpu_to_name(st case CPU_AU1100: name = "Au1100"; break; case CPU_AU1550: name = "Au1550"; break; case CPU_AU1200: name = "Au1200"; break; + case CPU_AU1210: name = "Au1210"; break; + case CPU_AU1250: name = "Au1250"; break; case CPU_4KEC: name = "MIPS 4KEc"; break; case CPU_4KSC: name = "MIPS 4KSc"; break; case CPU_VR41XX: name = "NEC Vr41xx"; break; diff -puN arch/mips/kernel/genex.S~git-mips arch/mips/kernel/genex.S --- a/arch/mips/kernel/genex.S~git-mips +++ a/arch/mips/kernel/genex.S @@ -6,7 +6,7 @@ * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002 Maciej W. Rozycki + * Copyright (C) 2002, 2007 Maciej W. Rozycki */ #include @@ -471,7 +471,13 @@ NESTED(nmi_handler, PT_SIZE, sp) jr k0 rfe #else +#ifndef CONFIG_CPU_DADDI_WORKAROUNDS LONG_ADDIU k0, 4 /* stall on $k0 */ +#else + .set at=v1 + LONG_ADDIU k0, 4 + .set noat +#endif MTC0 k0, CP0_EPC /* I hope three instructions between MTC0 and ERET are enough... */ ori k1, _THREAD_MASK diff -puN arch/mips/kernel/kspd.c~git-mips arch/mips/kernel/kspd.c --- a/arch/mips/kernel/kspd.c~git-mips +++ a/arch/mips/kernel/kspd.c @@ -161,8 +161,7 @@ static unsigned int translate_open_flags int i; unsigned int ret = 0; - for (i = 0; i < (sizeof(open_flags_table) / sizeof(struct apsp_table)); - i++) { + for (i = 0; i < ARRAY_SIZE(open_flags_table); i++) { if( (flags & open_flags_table[i].sp) ) { ret |= open_flags_table[i].ap; } diff -puN arch/mips/kernel/mips-mt.c~git-mips arch/mips/kernel/mips-mt.c --- a/arch/mips/kernel/mips-mt.c~git-mips +++ a/arch/mips/kernel/mips-mt.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff -puN arch/mips/kernel/pcspeaker.c~git-mips /dev/null --- a/arch/mips/kernel/pcspeaker.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2006 IBM Corporation - * - * Implements device information for i8253 timer chip - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version - * 2 as published by the Free Software Foundation - */ - -#include - -static __init int add_pcspkr(void) -{ - struct platform_device *pd; - int ret; - - pd = platform_device_alloc("pcspkr", -1); - if (!pd) - return -ENOMEM; - - ret = platform_device_add(pd); - if (ret) - platform_device_put(pd); - - return ret; -} -device_initcall(add_pcspkr); diff -puN arch/mips/kernel/proc.c~git-mips arch/mips/kernel/proc.c --- a/arch/mips/kernel/proc.c~git-mips +++ a/arch/mips/kernel/proc.c @@ -62,6 +62,7 @@ static int show_cpuinfo(struct seq_file ); seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); + seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", cpu_has_vce ? "%u" : "not available"); diff -puN arch/mips/kernel/rtlx.c~git-mips arch/mips/kernel/rtlx.c --- a/arch/mips/kernel/rtlx.c~git-mips +++ a/arch/mips/kernel/rtlx.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include #include diff -puN arch/mips/kernel/setup.c~git-mips arch/mips/kernel/setup.c --- a/arch/mips/kernel/setup.c~git-mips +++ a/arch/mips/kernel/setup.c @@ -8,7 +8,7 @@ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 Ralf Baechle * Copyright (C) 1996 Stoned Elipot * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2000 2001, 2002 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki */ #include #include @@ -24,10 +24,12 @@ #include #include +#include #include #include #include #include +#include #include struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; @@ -561,6 +563,7 @@ void __init setup_arch(char **cmdline_p) } #endif cpu_report(); + check_bugs_early(); #if defined(CONFIG_VT) #if defined(CONFIG_VGA_CONSOLE) @@ -573,9 +576,7 @@ void __init setup_arch(char **cmdline_p) arch_mem_init(cmdline_p); resource_init(); -#ifdef CONFIG_SMP plat_smp_setup(); -#endif } static int __init fpu_disable(char *s) diff -puN arch/mips/kernel/smp-mt.c~git-mips arch/mips/kernel/smp-mt.c --- a/arch/mips/kernel/smp-mt.c~git-mips +++ a/arch/mips/kernel/smp-mt.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -30,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -215,68 +215,67 @@ static void __init smp_tc_init(unsigned write_tc_c0_tchalt(TCHALT_H); } -/* - * Common setup before any secondaries are started - * Make sure all CPU's are in a sensible state before we boot any of the - * secondarys - */ -void __init plat_smp_setup(void) +static void vsmp_send_ipi_single(int cpu, unsigned int action) { - unsigned int mvpconf0, ntc, tc, ncpu = 0; - -#ifdef CONFIG_MIPS_MT_FPAFF - /* If we have an FPU, enroll ourselves in the FPU-full mask */ - if (cpu_has_fpu) - cpu_set(0, mt_fpu_cpumask); -#endif /* CONFIG_MIPS_MT_FPAFF */ - if (!cpu_has_mipsmt) - return; - - /* disable MT so we can configure */ - dvpe(); - dmt(); + int i; + unsigned long flags; + int vpflags; - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); + local_irq_save(flags); - mvpconf0 = read_c0_mvpconf0(); - ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT; + vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ - /* we'll always have more TC's than VPE's, so loop setting everything - to a sensible state */ - for (tc = 0; tc <= ntc; tc++) { - settc(tc); + switch (action) { + case SMP_CALL_FUNCTION: + i = C_SW1; + break; - smp_tc_init(tc, mvpconf0); - ncpu = smp_vpe_init(tc, mvpconf0, ncpu); + case SMP_RESCHEDULE_YOURSELF: + default: + i = C_SW0; + break; } - /* Release config state */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); + /* 1:1 mapping of vpe and tc... */ + settc(cpu); + write_vpe_c0_cause(read_vpe_c0_cause() | i); + evpe(vpflags); - /* We'll wait until starting the secondaries before starting MVPE */ + local_irq_restore(flags); +} - printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); +static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + vsmp_send_ipi_single(i, action); } -void __init plat_prepare_cpus(unsigned int max_cpus) +static void __cpuinit vsmp_init_secondary(void) { - mips_mt_set_cpuoptions(); + /* Enable per-cpu interrupts */ - /* set up ipi interrupts */ - if (cpu_has_vint) { - set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); - set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); - } + /* This is Malta specific: IPI,performance and timer inetrrupts */ + write_c0_status((read_c0_status() & ~ST0_IM ) | + (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7)); +} - cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; - cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; +static void __cpuinit vsmp_smp_finish(void) +{ + write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); - setup_irq(cpu_ipi_resched_irq, &irq_resched); - setup_irq(cpu_ipi_call_irq, &irq_call); +#ifdef CONFIG_MIPS_MT_FPAFF + /* If we have an FPU, enroll ourselves in the FPU-full mask */ + if (cpu_has_fpu) + cpu_set(smp_processor_id(), mt_fpu_cpumask); +#endif /* CONFIG_MIPS_MT_FPAFF */ - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); + local_irq_enable(); +} + +static void vsmp_cpus_done(void) +{ } /* @@ -287,7 +286,7 @@ void __init plat_prepare_cpus(unsigned i * (unsigned long)idle->thread_info the gp * assumes a 1:1 mapping of TC => VPE */ -void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) +static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); dvpe(); @@ -321,57 +320,81 @@ void __cpuinit prom_boot_secondary(int c evpe(EVPE_ENABLE); } -void __cpuinit prom_init_secondary(void) -{ - /* Enable per-cpu interrupts */ - - /* This is Malta specific: IPI,performance and timer inetrrupts */ - write_c0_status((read_c0_status() & ~ST0_IM ) | - (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7)); -} - -void __cpuinit prom_smp_finish(void) +/* + * Common setup before any secondaries are started + * Make sure all CPU's are in a sensible state before we boot any of the + * secondarys + */ +static void __init vsmp_smp_setup(void) { - write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); + unsigned int mvpconf0, ntc, tc, ncpu = 0; + unsigned int nvpe; #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) - cpu_set(smp_processor_id(), mt_fpu_cpumask); + cpu_set(0, mt_fpu_cpumask); #endif /* CONFIG_MIPS_MT_FPAFF */ + if (!cpu_has_mipsmt) + return; - local_irq_enable(); -} + /* disable MT so we can configure */ + dvpe(); + dmt(); -void prom_cpus_done(void) -{ -} + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); -void core_send_ipi(int cpu, unsigned int action) -{ - int i; - unsigned long flags; - int vpflags; + mvpconf0 = read_c0_mvpconf0(); + ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT; - local_irq_save(flags); + nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; + smp_num_siblings = nvpe; - vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ + /* we'll always have more TC's than VPE's, so loop setting everything + to a sensible state */ + for (tc = 0; tc <= ntc; tc++) { + settc(tc); - switch (action) { - case SMP_CALL_FUNCTION: - i = C_SW1; - break; + smp_tc_init(tc, mvpconf0); + ncpu = smp_vpe_init(tc, mvpconf0, ncpu); + } - case SMP_RESCHEDULE_YOURSELF: - default: - i = C_SW0; - break; + /* Release config state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + + /* We'll wait until starting the secondaries before starting MVPE */ + + printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); +} + +static void __init vsmp_prepare_cpus(unsigned int max_cpus) +{ + mips_mt_set_cpuoptions(); + + /* set up ipi interrupts */ + if (cpu_has_vint) { + set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); } - /* 1:1 mapping of vpe and tc... */ - settc(cpu); - write_vpe_c0_cause(read_vpe_c0_cause() | i); - evpe(vpflags); + cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; + cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; - local_irq_restore(flags); + setup_irq(cpu_ipi_resched_irq, &irq_resched); + setup_irq(cpu_ipi_call_irq, &irq_call); + + set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); + set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); } + +struct plat_smp_ops vsmp_smp_ops = { + .send_ipi_single = vsmp_send_ipi_single, + .send_ipi_mask = vsmp_send_ipi_mask, + .init_secondary = vsmp_init_secondary, + .smp_finish = vsmp_smp_finish, + .cpus_done = vsmp_cpus_done, + .boot_secondary = vsmp_boot_secondary, + .smp_setup = vsmp_smp_setup, + .prepare_cpus = vsmp_prepare_cpus, +}; diff -puN arch/mips/kernel/smp.c~git-mips arch/mips/kernel/smp.c --- a/arch/mips/kernel/smp.c~git-mips +++ a/arch/mips/kernel/smp.c @@ -37,7 +37,6 @@ #include #include #include -#include #include #ifdef CONFIG_MIPS_MT_SMTC @@ -56,6 +55,44 @@ EXPORT_SYMBOL(cpu_online_map); extern void __init calibrate_delay(void); extern void cpu_idle(void); +/* Number of TCs (or siblings in Intel speak) per CPU core */ +int smp_num_siblings = 1; +EXPORT_SYMBOL(smp_num_siblings); + +/* representing the TCs (or siblings in Intel speak) of each logical CPU */ +cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; +EXPORT_SYMBOL(cpu_sibling_map); + +/* representing cpus for which sibling maps can be computed */ +static cpumask_t cpu_sibling_setup_map; + +static inline void set_cpu_sibling_map(int cpu) +{ + int i; + + cpu_set(cpu, cpu_sibling_setup_map); + + if (smp_num_siblings > 1) { + for_each_cpu_mask(i, cpu_sibling_setup_map) { + if (cpu_data[cpu].core == cpu_data[i].core) { + cpu_set(i, cpu_sibling_map[cpu]); + cpu_set(cpu, cpu_sibling_map[i]); + } + } + } else + cpu_set(cpu, cpu_sibling_map[cpu]); +} + +struct plat_smp_ops *mp_ops; + +__cpuinit void register_smp_ops(struct plat_smp_ops *ops) +{ + if (ops) + printk(KERN_WARNING "Overriding previous set SMP ops\n"); + + mp_ops = ops; +} + /* * First C code run on the secondary CPUs after being started up by * the master. @@ -72,7 +109,7 @@ asmlinkage __cpuinit void start_secondar cpu_report(); per_cpu_trap_init(); mips_clockevent_init(); - prom_init_secondary(); + mp_ops->init_secondary(); /* * XXX parity protection should be folded in here when it's converted @@ -84,7 +121,8 @@ asmlinkage __cpuinit void start_secondar cpu = smp_processor_id(); cpu_data[cpu].udelay_val = loops_per_jiffy; - prom_smp_finish(); + mp_ops->smp_finish(); + set_cpu_sibling_map(cpu); cpu_set(cpu, cpu_callin_map); @@ -155,7 +193,7 @@ int smp_call_function_mask(cpumask_t mas smp_mb(); /* Send a message to all other CPUs and wait for them to respond */ - core_send_ipi_mask(mask, SMP_CALL_FUNCTION); + mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); /* Wait for response */ /* FIXME: lock-up detection, backtrace on lock-up */ @@ -249,7 +287,7 @@ void smp_send_stop(void) void __init smp_cpus_done(unsigned int max_cpus) { - prom_cpus_done(); + mp_ops->cpus_done(); } /* called from main before smp_init() */ @@ -257,7 +295,8 @@ void __init smp_prepare_cpus(unsigned in { init_new_context(current, &init_mm); current_thread_info()->cpu = 0; - plat_prepare_cpus(max_cpus); + mp_ops->prepare_cpus(max_cpus); + set_cpu_sibling_map(0); #ifndef CONFIG_HOTPLUG_CPU cpu_present_map = cpu_possible_map; #endif @@ -295,7 +334,7 @@ int __cpuinit __cpu_up(unsigned int cpu) if (IS_ERR(idle)) panic(KERN_ERR "Fork failed for CPU %d", cpu); - prom_boot_secondary(cpu, idle); + mp_ops->boot_secondary(cpu, idle); /* * Trust is futile. We should really have timeouts ... diff -puN arch/mips/kernel/smtc-proc.c~git-mips arch/mips/kernel/smtc-proc.c --- a/arch/mips/kernel/smtc-proc.c~git-mips +++ a/arch/mips/kernel/smtc-proc.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff -puN arch/mips/kernel/smtc.c~git-mips arch/mips/kernel/smtc.c --- a/arch/mips/kernel/smtc.c~git-mips +++ a/arch/mips/kernel/smtc.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff -puN arch/mips/kernel/time.c~git-mips arch/mips/kernel/time.c --- a/arch/mips/kernel/time.c~git-mips +++ a/arch/mips/kernel/time.c @@ -50,8 +50,6 @@ int update_persistent_clock(struct times return rtc_mips_set_mmss(now.tv_sec); } -int (*mips_timer_state)(void); - int null_perf_irq(void) { return 0; diff -puN arch/mips/kernel/vpe.c~git-mips arch/mips/kernel/vpe.c --- a/arch/mips/kernel/vpe.c~git-mips +++ a/arch/mips/kernel/vpe.c @@ -53,7 +53,6 @@ #include #include #include -#include typedef void *vpe_handle; diff -puN arch/mips/lasat/picvue.c~git-mips arch/mips/lasat/picvue.c --- a/arch/mips/lasat/picvue.c~git-mips +++ a/arch/mips/lasat/picvue.c @@ -22,8 +22,6 @@ struct pvc_defs *picvue; -DECLARE_MUTEX(pvc_sem); - static void pvc_reg_write(u32 val) { *picvue->reg = val; diff -puN arch/mips/lasat/picvue.h~git-mips arch/mips/lasat/picvue.h --- a/arch/mips/lasat/picvue.h~git-mips +++ a/arch/mips/lasat/picvue.h @@ -4,8 +4,6 @@ * Brian Murphy * */ -#include - struct pvc_defs { volatile u32 *reg; u32 data_shift; @@ -45,4 +43,3 @@ void pvc_move(u8 cmd); void pvc_clear(void); void pvc_home(void); -extern struct semaphore pvc_sem; diff -puN arch/mips/lasat/picvue_proc.c~git-mips arch/mips/lasat/picvue_proc.c --- a/arch/mips/lasat/picvue_proc.c~git-mips +++ a/arch/mips/lasat/picvue_proc.c @@ -13,9 +13,11 @@ #include #include +#include #include "picvue.h" +static DEFINE_MUTEX(pvc_mutex); static char pvc_lines[PVC_NLINES][PVC_LINELEN+1]; static int pvc_linedata[PVC_NLINES]; static struct proc_dir_entry *pvc_display_dir; @@ -48,9 +50,9 @@ static int pvc_proc_read_line(char *page return 0; } - down(&pvc_sem); + mutex_lock(&pvc_mutex); page += sprintf(page, "%s\n", pvc_lines[lineno]); - up(&pvc_sem); + mutex_unlock(&pvc_mutex); return page - origpage; } @@ -73,10 +75,10 @@ static int pvc_proc_write_line(struct fi if (buffer[count-1] == '\n') count--; - down(&pvc_sem); + mutex_lock(&pvc_mutex); strncpy(pvc_lines[lineno], buffer, count); pvc_lines[lineno][count] = '\0'; - up(&pvc_sem); + mutex_unlock(&pvc_mutex); tasklet_schedule(&pvc_display_tasklet); @@ -89,7 +91,7 @@ static int pvc_proc_write_scroll(struct int origcount = count; int cmd = simple_strtol(buffer, NULL, 10); - down(&pvc_sem); + mutex_lock(&pvc_mutex); if (scroll_interval != 0) del_timer(&timer); @@ -106,7 +108,7 @@ static int pvc_proc_write_scroll(struct } add_timer(&timer); } - up(&pvc_sem); + mutex_unlock(&pvc_mutex); return origcount; } @@ -117,9 +119,9 @@ static int pvc_proc_read_scroll(char *pa { char *origpage = page; - down(&pvc_sem); + mutex_lock(&pvc_mutex); page += sprintf(page, "%d\n", scroll_dir * scroll_interval); - up(&pvc_sem); + mutex_unlock(&pvc_mutex); return page - origpage; } diff -puN arch/mips/lemote/lm2e/pci.c~git-mips arch/mips/lemote/lm2e/pci.c --- a/arch/mips/lemote/lm2e/pci.c~git-mips +++ a/arch/mips/lemote/lm2e/pci.c @@ -81,9 +81,6 @@ static void __init ict_pcimap(void) static int __init pcibios_init(void) { - extern int pci_probe_only; - pci_probe_only = 0; - ict_pcimap(); register_pci_controller(&loongson2e_pci_controller); diff -puN arch/mips/lemote/lm2e/prom.c~git-mips arch/mips/lemote/lm2e/prom.c --- a/arch/mips/lemote/lm2e/prom.c~git-mips +++ a/arch/mips/lemote/lm2e/prom.c @@ -57,8 +57,6 @@ void __init prom_init(void) arg = (int *)fw_arg1; env = (int *)fw_arg2; - mips_machtype = MACH_LEMOTE_FULONG; - prom_init_cmdline(); if ((strstr(arcs_cmdline, "console=")) == NULL) diff -puN arch/mips/lib/csum_partial.S~git-mips arch/mips/lib/csum_partial.S --- a/arch/mips/lib/csum_partial.S~git-mips +++ a/arch/mips/lib/csum_partial.S @@ -7,6 +7,7 @@ * * Copyright (C) 1998, 1999 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki */ #include #include @@ -52,9 +53,12 @@ #define UNIT(unit) ((unit)*NBYTES) #define ADDC(sum,reg) \ + .set push; \ + .set noat; \ ADD sum, reg; \ sltu v1, sum, reg; \ - ADD sum, v1 + ADD sum, v1; \ + .set pop #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ LOAD _t0, (offset + UNIT(0))(src); \ @@ -92,13 +96,13 @@ LEAF(csum_partial) move t7, zero sltiu t8, a1, 0x8 - bnez t8, small_csumcpy /* < 8 bytes to copy */ + bnez t8, .Lsmall_csumcpy /* < 8 bytes to copy */ move t2, a1 andi t7, src, 0x1 /* odd buffer? */ -hword_align: - beqz t7, word_align +.Lhword_align: + beqz t7, .Lword_align andi t8, src, 0x2 lbu t0, (src) @@ -110,8 +114,8 @@ hword_align: PTR_ADDU src, src, 0x1 andi t8, src, 0x2 -word_align: - beqz t8, dword_align +.Lword_align: + beqz t8, .Ldword_align sltiu t8, a1, 56 lhu t0, (src) @@ -120,12 +124,12 @@ word_align: sltiu t8, a1, 56 PTR_ADDU src, src, 0x2 -dword_align: - bnez t8, do_end_words +.Ldword_align: + bnez t8, .Ldo_end_words move t8, a1 andi t8, src, 0x4 - beqz t8, qword_align + beqz t8, .Lqword_align andi t8, src, 0x8 lw t0, 0x00(src) @@ -134,8 +138,8 @@ dword_align: PTR_ADDU src, src, 0x4 andi t8, src, 0x8 -qword_align: - beqz t8, oword_align +.Lqword_align: + beqz t8, .Loword_align andi t8, src, 0x10 #ifdef USE_DOUBLE @@ -152,8 +156,8 @@ qword_align: PTR_ADDU src, src, 0x8 andi t8, src, 0x10 -oword_align: - beqz t8, begin_movement +.Loword_align: + beqz t8, .Lbegin_movement LONG_SRL t8, a1, 0x7 #ifdef USE_DOUBLE @@ -168,51 +172,55 @@ oword_align: PTR_ADDU src, src, 0x10 LONG_SRL t8, a1, 0x7 -begin_movement: +.Lbegin_movement: beqz t8, 1f andi t2, a1, 0x40 -move_128bytes: +.Lmove_128bytes: CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4) LONG_SUBU t8, t8, 0x01 - bnez t8, move_128bytes - PTR_ADDU src, src, 0x80 + .set reorder /* DADDI_WAR */ + PTR_ADDU src, src, 0x80 + bnez t8, .Lmove_128bytes + .set noreorder 1: beqz t2, 1f andi t2, a1, 0x20 -move_64bytes: +.Lmove_64bytes: CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) PTR_ADDU src, src, 0x40 1: - beqz t2, do_end_words + beqz t2, .Ldo_end_words andi t8, a1, 0x1c -move_32bytes: +.Lmove_32bytes: CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) andi t8, a1, 0x1c PTR_ADDU src, src, 0x20 -do_end_words: - beqz t8, small_csumcpy +.Ldo_end_words: + beqz t8, .Lsmall_csumcpy andi t2, a1, 0x3 LONG_SRL t8, t8, 0x2 -end_words: +.Lend_words: lw t0, (src) LONG_SUBU t8, t8, 0x1 ADDC(sum, t0) - bnez t8, end_words - PTR_ADDU src, src, 0x4 + .set reorder /* DADDI_WAR */ + PTR_ADDU src, src, 0x4 + bnez t8, .Lend_words + .set noreorder /* unknown src alignment and < 8 bytes to go */ -small_csumcpy: +.Lsmall_csumcpy: move a1, t2 andi t0, a1, 4 @@ -246,6 +254,8 @@ small_csumcpy: 1: ADDC(sum, t1) /* fold checksum */ + .set push + .set noat #ifdef USE_DOUBLE dsll32 v1, sum, 0 daddu sum, v1 @@ -266,6 +276,7 @@ small_csumcpy: srl sum, sum, 8 or sum, v1 andi sum, 0xffff + .set pop 1: .set reorder /* Add the passed partial csum. */ @@ -373,7 +384,11 @@ small_csumcpy: #define ADDRMASK (NBYTES-1) +#ifndef CONFIG_CPU_DADDI_WORKAROUNDS .set noat +#else + .set at=v1 +#endif LEAF(__csum_partial_copy_user) PTR_ADDU AT, src, len /* See (1) above. */ @@ -398,95 +413,101 @@ FEXPORT(csum_partial_copy_nocheck) */ sltu t2, len, NBYTES and t1, dst, ADDRMASK - bnez t2, copy_bytes_checklen + bnez t2, .Lcopy_bytes_checklen and t0, src, ADDRMASK andi odd, dst, 0x1 /* odd buffer? */ - bnez t1, dst_unaligned + bnez t1, .Ldst_unaligned nop - bnez t0, src_unaligned_dst_aligned + bnez t0, .Lsrc_unaligned_dst_aligned /* * use delay slot for fall-through * src and dst are aligned; need to compute rem */ -both_aligned: +.Lboth_aligned: SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter - beqz t0, cleanup_both_aligned # len < 8*NBYTES + beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES nop SUB len, 8*NBYTES # subtract here for bgez loop .align 4 1: -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) -EXC( LOAD t4, UNIT(4)(src), l_exc_copy) -EXC( LOAD t5, UNIT(5)(src), l_exc_copy) -EXC( LOAD t6, UNIT(6)(src), l_exc_copy) -EXC( LOAD t7, UNIT(7)(src), l_exc_copy) +EXC( LOAD t0, UNIT(0)(src), .Ll_exc) +EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) +EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) +EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) +EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy) +EXC( LOAD t5, UNIT(5)(src), .Ll_exc_copy) +EXC( LOAD t6, UNIT(6)(src), .Ll_exc_copy) +EXC( LOAD t7, UNIT(7)(src), .Ll_exc_copy) SUB len, len, 8*NBYTES ADD src, src, 8*NBYTES -EXC( STORE t0, UNIT(0)(dst), s_exc) +EXC( STORE t0, UNIT(0)(dst), .Ls_exc) ADDC(sum, t0) -EXC( STORE t1, UNIT(1)(dst), s_exc) +EXC( STORE t1, UNIT(1)(dst), .Ls_exc) ADDC(sum, t1) -EXC( STORE t2, UNIT(2)(dst), s_exc) +EXC( STORE t2, UNIT(2)(dst), .Ls_exc) ADDC(sum, t2) -EXC( STORE t3, UNIT(3)(dst), s_exc) +EXC( STORE t3, UNIT(3)(dst), .Ls_exc) ADDC(sum, t3) -EXC( STORE t4, UNIT(4)(dst), s_exc) +EXC( STORE t4, UNIT(4)(dst), .Ls_exc) ADDC(sum, t4) -EXC( STORE t5, UNIT(5)(dst), s_exc) +EXC( STORE t5, UNIT(5)(dst), .Ls_exc) ADDC(sum, t5) -EXC( STORE t6, UNIT(6)(dst), s_exc) +EXC( STORE t6, UNIT(6)(dst), .Ls_exc) ADDC(sum, t6) -EXC( STORE t7, UNIT(7)(dst), s_exc) +EXC( STORE t7, UNIT(7)(dst), .Ls_exc) ADDC(sum, t7) + .set reorder /* DADDI_WAR */ + ADD dst, dst, 8*NBYTES bgez len, 1b - ADD dst, dst, 8*NBYTES + .set noreorder ADD len, 8*NBYTES # revert len (see above) /* * len == the number of bytes left to copy < 8*NBYTES */ -cleanup_both_aligned: +.Lcleanup_both_aligned: #define rem t7 - beqz len, done + beqz len, .Ldone sltu t0, len, 4*NBYTES - bnez t0, less_than_4units + bnez t0, .Lless_than_4units and rem, len, (NBYTES-1) # rem = len % NBYTES /* * len >= 4*NBYTES */ -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) +EXC( LOAD t0, UNIT(0)(src), .Ll_exc) +EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) +EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) +EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) SUB len, len, 4*NBYTES ADD src, src, 4*NBYTES -EXC( STORE t0, UNIT(0)(dst), s_exc) +EXC( STORE t0, UNIT(0)(dst), .Ls_exc) ADDC(sum, t0) -EXC( STORE t1, UNIT(1)(dst), s_exc) +EXC( STORE t1, UNIT(1)(dst), .Ls_exc) ADDC(sum, t1) -EXC( STORE t2, UNIT(2)(dst), s_exc) +EXC( STORE t2, UNIT(2)(dst), .Ls_exc) ADDC(sum, t2) -EXC( STORE t3, UNIT(3)(dst), s_exc) +EXC( STORE t3, UNIT(3)(dst), .Ls_exc) ADDC(sum, t3) - beqz len, done - ADD dst, dst, 4*NBYTES -less_than_4units: + .set reorder /* DADDI_WAR */ + ADD dst, dst, 4*NBYTES + beqz len, .Ldone + .set noreorder +.Lless_than_4units: /* * rem = len % NBYTES */ - beq rem, len, copy_bytes + beq rem, len, .Lcopy_bytes nop 1: -EXC( LOAD t0, 0(src), l_exc) +EXC( LOAD t0, 0(src), .Ll_exc) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), s_exc) +EXC( STORE t0, 0(dst), .Ls_exc) ADDC(sum, t0) + .set reorder /* DADDI_WAR */ + ADD dst, dst, NBYTES bne rem, len, 1b - ADD dst, dst, NBYTES + .set noreorder /* * src and dst are aligned, need to copy rem bytes (rem < NBYTES) @@ -500,20 +521,20 @@ EXC( STORE t0, 0(dst), s_exc) * more instruction-level parallelism. */ #define bits t2 - beqz len, done + beqz len, .Ldone ADD t1, dst, len # t1 is just past last byte of dst li bits, 8*NBYTES SLL rem, len, 3 # rem = number of bits to keep -EXC( LOAD t0, 0(src), l_exc) +EXC( LOAD t0, 0(src), .Ll_exc) SUB bits, bits, rem # bits = number of bits to discard SHIFT_DISCARD t0, t0, bits -EXC( STREST t0, -1(t1), s_exc) +EXC( STREST t0, -1(t1), .Ls_exc) SHIFT_DISCARD_REVERT t0, t0, bits .set reorder ADDC(sum, t0) - b done + b .Ldone .set noreorder -dst_unaligned: +.Ldst_unaligned: /* * dst is unaligned * t0 = src & ADDRMASK @@ -524,25 +545,25 @@ dst_unaligned: * Set match = (src and dst have same alignment) */ #define match rem -EXC( LDFIRST t3, FIRST(0)(src), l_exc) +EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc) ADD t2, zero, NBYTES -EXC( LDREST t3, REST(0)(src), l_exc_copy) +EXC( LDREST t3, REST(0)(src), .Ll_exc_copy) SUB t2, t2, t1 # t2 = number of bytes copied xor match, t0, t1 -EXC( STFIRST t3, FIRST(0)(dst), s_exc) +EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc) SLL t4, t1, 3 # t4 = number of bits to discard SHIFT_DISCARD t3, t3, t4 /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */ ADDC(sum, t3) - beq len, t2, done + beq len, t2, .Ldone SUB len, len, t2 ADD dst, dst, t2 - beqz match, both_aligned + beqz match, .Lboth_aligned ADD src, src, t2 -src_unaligned_dst_aligned: +.Lsrc_unaligned_dst_aligned: SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter - beqz t0, cleanup_src_unaligned + beqz t0, .Lcleanup_src_unaligned and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES 1: /* @@ -551,49 +572,53 @@ src_unaligned_dst_aligned: * It's OK to load FIRST(N+1) before REST(N) because the two addresses * are to the same unit (unless src is aligned, but it's not). */ -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) +EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy) SUB len, len, 4*NBYTES -EXC( LDREST t0, REST(0)(src), l_exc_copy) -EXC( LDREST t1, REST(1)(src), l_exc_copy) -EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) -EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) -EXC( LDREST t2, REST(2)(src), l_exc_copy) -EXC( LDREST t3, REST(3)(src), l_exc_copy) +EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) +EXC( LDREST t1, REST(1)(src), .Ll_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy) +EXC( LDREST t2, REST(2)(src), .Ll_exc_copy) +EXC( LDREST t3, REST(3)(src), .Ll_exc_copy) ADD src, src, 4*NBYTES #ifdef CONFIG_CPU_SB1 nop # improves slotting #endif -EXC( STORE t0, UNIT(0)(dst), s_exc) +EXC( STORE t0, UNIT(0)(dst), .Ls_exc) ADDC(sum, t0) -EXC( STORE t1, UNIT(1)(dst), s_exc) +EXC( STORE t1, UNIT(1)(dst), .Ls_exc) ADDC(sum, t1) -EXC( STORE t2, UNIT(2)(dst), s_exc) +EXC( STORE t2, UNIT(2)(dst), .Ls_exc) ADDC(sum, t2) -EXC( STORE t3, UNIT(3)(dst), s_exc) +EXC( STORE t3, UNIT(3)(dst), .Ls_exc) ADDC(sum, t3) + .set reorder /* DADDI_WAR */ + ADD dst, dst, 4*NBYTES bne len, rem, 1b - ADD dst, dst, 4*NBYTES + .set noreorder -cleanup_src_unaligned: - beqz len, done +.Lcleanup_src_unaligned: + beqz len, .Ldone and rem, len, NBYTES-1 # rem = len % NBYTES - beq rem, len, copy_bytes + beq rem, len, .Lcopy_bytes nop 1: -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) +EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), s_exc) +EXC( STORE t0, 0(dst), .Ls_exc) ADDC(sum, t0) + .set reorder /* DADDI_WAR */ + ADD dst, dst, NBYTES bne len, rem, 1b - ADD dst, dst, NBYTES + .set noreorder -copy_bytes_checklen: - beqz len, done +.Lcopy_bytes_checklen: + beqz len, .Ldone nop -copy_bytes: +.Lcopy_bytes: /* 0 < len < NBYTES */ #ifdef CONFIG_CPU_LITTLE_ENDIAN #define SHIFT_START 0 @@ -604,14 +629,14 @@ copy_bytes: #endif move t2, zero # partial word li t3, SHIFT_START # shift -/* use l_exc_copy here to return correct sum on fault */ +/* use .Ll_exc_copy here to return correct sum on fault */ #define COPY_BYTE(N) \ -EXC( lbu t0, N(src), l_exc_copy); \ +EXC( lbu t0, N(src), .Ll_exc_copy); \ SUB len, len, 1; \ -EXC( sb t0, N(dst), s_exc); \ +EXC( sb t0, N(dst), .Ls_exc); \ SLLV t0, t0, t3; \ addu t3, SHIFT_INC; \ - beqz len, copy_bytes_done; \ + beqz len, .Lcopy_bytes_done; \ or t2, t0 COPY_BYTE(0) @@ -622,15 +647,17 @@ EXC( sb t0, N(dst), s_exc); \ COPY_BYTE(4) COPY_BYTE(5) #endif -EXC( lbu t0, NBYTES-2(src), l_exc_copy) +EXC( lbu t0, NBYTES-2(src), .Ll_exc_copy) SUB len, len, 1 -EXC( sb t0, NBYTES-2(dst), s_exc) +EXC( sb t0, NBYTES-2(dst), .Ls_exc) SLLV t0, t0, t3 or t2, t0 -copy_bytes_done: +.Lcopy_bytes_done: ADDC(sum, t2) -done: +.Ldone: /* fold checksum */ + .set push + .set noat #ifdef USE_DOUBLE dsll32 v1, sum, 0 daddu sum, v1 @@ -651,13 +678,14 @@ done: srl sum, sum, 8 or sum, v1 andi sum, 0xffff + .set pop 1: .set reorder ADDC(sum, psum) jr ra .set noreorder -l_exc_copy: +.Ll_exc_copy: /* * Copy bytes from src until faulting load address (or until a * lb faults) @@ -672,15 +700,17 @@ l_exc_copy: li t2, SHIFT_START LOAD t0, THREAD_BUADDR(t0) 1: -EXC( lbu t1, 0(src), l_exc) +EXC( lbu t1, 0(src), .Ll_exc) ADD src, src, 1 sb t1, 0(dst) # can't fault -- we're copy_from_user SLLV t1, t1, t2 addu t2, SHIFT_INC ADDC(sum, t1) + .set reorder /* DADDI_WAR */ + ADD dst, dst, 1 bne src, t0, 1b - ADD dst, dst, 1 -l_exc: + .set noreorder +.Ll_exc: LOAD t0, TI_TASK($28) nop LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address @@ -697,19 +727,30 @@ l_exc: * Clear len bytes starting at dst. Can't call __bzero because it * might modify len. An inefficient loop for these rare times... */ - beqz len, done - SUB src, len, 1 + .set reorder /* DADDI_WAR */ + SUB src, len, 1 + beqz len, .Ldone + .set noreorder 1: sb zero, 0(dst) ADD dst, dst, 1 + .set push + .set noat +#ifndef CONFIG_CPU_DADDI_WORKAROUNDS bnez src, 1b SUB src, src, 1 +#else + li v1, 1 + bnez src, 1b + SUB src, src, v1 +#endif li v1, -EFAULT - b done + b .Ldone sw v1, (errptr) -s_exc: +.Ls_exc: li v0, -1 /* invalid checksum */ li v1, -EFAULT jr ra sw v1, (errptr) + .set pop END(__csum_partial_copy_user) diff -puN arch/mips/lib/memcpy-inatomic.S~git-mips arch/mips/lib/memcpy-inatomic.S --- a/arch/mips/lib/memcpy-inatomic.S~git-mips +++ a/arch/mips/lib/memcpy-inatomic.S @@ -9,6 +9,7 @@ * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. * Copyright (C) 2002 Broadcom, Inc. * memcpy/copy_user author: Mark Vandevoorde + * Copyright (C) 2007 Maciej W. Rozycki * * Mnemonic names for arguments to memcpy/__copy_user */ @@ -175,7 +176,11 @@ .text .set noreorder +#ifndef CONFIG_CPU_DADDI_WORKAROUNDS .set noat +#else + .set at=v1 +#endif /* * A combined memcpy/__copy_user @@ -204,36 +209,36 @@ LEAF(__copy_user_inatomic) and t1, dst, ADDRMASK PREF( 0, 1*32(src) ) PREF( 1, 1*32(dst) ) - bnez t2, copy_bytes_checklen + bnez t2, .Lcopy_bytes_checklen and t0, src, ADDRMASK PREF( 0, 2*32(src) ) PREF( 1, 2*32(dst) ) - bnez t1, dst_unaligned + bnez t1, .Ldst_unaligned nop - bnez t0, src_unaligned_dst_aligned + bnez t0, .Lsrc_unaligned_dst_aligned /* * use delay slot for fall-through * src and dst are aligned; need to compute rem */ -both_aligned: - SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter - beqz t0, cleanup_both_aligned # len < 8*NBYTES - and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) +.Lboth_aligned: + SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter + beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES + and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) PREF( 0, 3*32(src) ) PREF( 1, 3*32(dst) ) .align 4 1: -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) +EXC( LOAD t0, UNIT(0)(src), .Ll_exc) +EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) +EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) +EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) SUB len, len, 8*NBYTES -EXC( LOAD t4, UNIT(4)(src), l_exc_copy) -EXC( LOAD t7, UNIT(5)(src), l_exc_copy) +EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy) +EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy) STORE t0, UNIT(0)(dst) STORE t1, UNIT(1)(dst) -EXC( LOAD t0, UNIT(6)(src), l_exc_copy) -EXC( LOAD t1, UNIT(7)(src), l_exc_copy) +EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy) +EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy) ADD src, src, 8*NBYTES ADD dst, dst, 8*NBYTES STORE t2, UNIT(-6)(dst) @@ -250,39 +255,43 @@ EXC( LOAD t1, UNIT(7)(src), l_exc_copy) /* * len == rem == the number of bytes left to copy < 8*NBYTES */ -cleanup_both_aligned: - beqz len, done +.Lcleanup_both_aligned: + beqz len, .Ldone sltu t0, len, 4*NBYTES - bnez t0, less_than_4units + bnez t0, .Lless_than_4units and rem, len, (NBYTES-1) # rem = len % NBYTES /* * len >= 4*NBYTES */ -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) +EXC( LOAD t0, UNIT(0)(src), .Ll_exc) +EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) +EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) +EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) SUB len, len, 4*NBYTES ADD src, src, 4*NBYTES STORE t0, UNIT(0)(dst) STORE t1, UNIT(1)(dst) STORE t2, UNIT(2)(dst) STORE t3, UNIT(3)(dst) - beqz len, done - ADD dst, dst, 4*NBYTES -less_than_4units: + .set reorder /* DADDI_WAR */ + ADD dst, dst, 4*NBYTES + beqz len, .Ldone + .set noreorder +.Lless_than_4units: /* * rem = len % NBYTES */ - beq rem, len, copy_bytes + beq rem, len, .Lcopy_bytes nop 1: -EXC( LOAD t0, 0(src), l_exc) +EXC( LOAD t0, 0(src), .Ll_exc) ADD src, src, NBYTES SUB len, len, NBYTES STORE t0, 0(dst) + .set reorder /* DADDI_WAR */ + ADD dst, dst, NBYTES bne rem, len, 1b - ADD dst, dst, NBYTES + .set noreorder /* * src and dst are aligned, need to copy rem bytes (rem < NBYTES) @@ -296,17 +305,17 @@ EXC( LOAD t0, 0(src), l_exc) * more instruction-level parallelism. */ #define bits t2 - beqz len, done + beqz len, .Ldone ADD t1, dst, len # t1 is just past last byte of dst li bits, 8*NBYTES SLL rem, len, 3 # rem = number of bits to keep -EXC( LOAD t0, 0(src), l_exc) +EXC( LOAD t0, 0(src), .Ll_exc) SUB bits, bits, rem # bits = number of bits to discard SHIFT_DISCARD t0, t0, bits STREST t0, -1(t1) jr ra move len, zero -dst_unaligned: +.Ldst_unaligned: /* * dst is unaligned * t0 = src & ADDRMASK @@ -317,22 +326,22 @@ dst_unaligned: * Set match = (src and dst have same alignment) */ #define match rem -EXC( LDFIRST t3, FIRST(0)(src), l_exc) +EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc) ADD t2, zero, NBYTES -EXC( LDREST t3, REST(0)(src), l_exc_copy) +EXC( LDREST t3, REST(0)(src), .Ll_exc_copy) SUB t2, t2, t1 # t2 = number of bytes copied xor match, t0, t1 STFIRST t3, FIRST(0)(dst) - beq len, t2, done + beq len, t2, .Ldone SUB len, len, t2 ADD dst, dst, t2 - beqz match, both_aligned + beqz match, .Lboth_aligned ADD src, src, t2 -src_unaligned_dst_aligned: +.Lsrc_unaligned_dst_aligned: SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter PREF( 0, 3*32(src) ) - beqz t0, cleanup_src_unaligned + beqz t0, .Lcleanup_src_unaligned and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES PREF( 1, 3*32(dst) ) 1: @@ -342,15 +351,15 @@ src_unaligned_dst_aligned: * It's OK to load FIRST(N+1) before REST(N) because the two addresses * are to the same unit (unless src is aligned, but it's not). */ -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) +EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy) SUB len, len, 4*NBYTES -EXC( LDREST t0, REST(0)(src), l_exc_copy) -EXC( LDREST t1, REST(1)(src), l_exc_copy) -EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) -EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) -EXC( LDREST t2, REST(2)(src), l_exc_copy) -EXC( LDREST t3, REST(3)(src), l_exc_copy) +EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) +EXC( LDREST t1, REST(1)(src), .Ll_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy) +EXC( LDREST t2, REST(2)(src), .Ll_exc_copy) +EXC( LDREST t3, REST(3)(src), .Ll_exc_copy) PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) ADD src, src, 4*NBYTES #ifdef CONFIG_CPU_SB1 @@ -361,32 +370,36 @@ EXC( LDREST t3, REST(3)(src), l_exc_copy STORE t2, UNIT(2)(dst) STORE t3, UNIT(3)(dst) PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) + .set reorder /* DADDI_WAR */ + ADD dst, dst, 4*NBYTES bne len, rem, 1b - ADD dst, dst, 4*NBYTES + .set noreorder -cleanup_src_unaligned: - beqz len, done +.Lcleanup_src_unaligned: + beqz len, .Ldone and rem, len, NBYTES-1 # rem = len % NBYTES - beq rem, len, copy_bytes + beq rem, len, .Lcopy_bytes nop 1: -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) +EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) ADD src, src, NBYTES SUB len, len, NBYTES STORE t0, 0(dst) + .set reorder /* DADDI_WAR */ + ADD dst, dst, NBYTES bne len, rem, 1b - ADD dst, dst, NBYTES + .set noreorder -copy_bytes_checklen: - beqz len, done +.Lcopy_bytes_checklen: + beqz len, .Ldone nop -copy_bytes: +.Lcopy_bytes: /* 0 < len < NBYTES */ #define COPY_BYTE(N) \ -EXC( lb t0, N(src), l_exc); \ +EXC( lb t0, N(src), .Ll_exc); \ SUB len, len, 1; \ - beqz len, done; \ + beqz len, .Ldone; \ sb t0, N(dst) COPY_BYTE(0) @@ -397,16 +410,16 @@ EXC( lb t0, N(src), l_exc); \ COPY_BYTE(4) COPY_BYTE(5) #endif -EXC( lb t0, NBYTES-2(src), l_exc) +EXC( lb t0, NBYTES-2(src), .Ll_exc) SUB len, len, 1 jr ra sb t0, NBYTES-2(dst) -done: +.Ldone: jr ra nop END(__copy_user_inatomic) -l_exc_copy: +.Ll_exc_copy: /* * Copy bytes from src until faulting load address (or until a * lb faults) @@ -421,12 +434,14 @@ l_exc_copy: nop LOAD t0, THREAD_BUADDR(t0) 1: -EXC( lb t1, 0(src), l_exc) +EXC( lb t1, 0(src), .Ll_exc) ADD src, src, 1 sb t1, 0(dst) # can't fault -- we're copy_from_user + .set reorder /* DADDI_WAR */ + ADD dst, dst, 1 bne src, t0, 1b - ADD dst, dst, 1 -l_exc: + .set noreorder +.Ll_exc: LOAD t0, TI_TASK($28) nop LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address diff -puN arch/mips/lib/memcpy.S~git-mips arch/mips/lib/memcpy.S --- a/arch/mips/lib/memcpy.S~git-mips +++ a/arch/mips/lib/memcpy.S @@ -9,6 +9,7 @@ * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. * Copyright (C) 2002 Broadcom, Inc. * memcpy/copy_user author: Mark Vandevoorde + * Copyright (C) 2007 Maciej W. Rozycki * * Mnemonic names for arguments to memcpy/__copy_user */ @@ -175,7 +176,11 @@ .text .set noreorder +#ifndef CONFIG_CPU_DADDI_WORKAROUNDS .set noat +#else + .set at=v1 +#endif /* * A combined memcpy/__copy_user @@ -186,7 +191,7 @@ .align 5 LEAF(memcpy) /* a0=dst a1=src a2=len */ move v0, dst /* return value */ -__memcpy: +.L__memcpy: FEXPORT(__copy_user) /* * Note: dst & src may be unaligned, len may be 0 @@ -194,6 +199,7 @@ FEXPORT(__copy_user) */ #define rem t8 + R10KCBARRIER(0(ra)) /* * The "issue break"s below are very approximate. * Issue delays for dcache fills will perturb the schedule, as will @@ -207,44 +213,45 @@ FEXPORT(__copy_user) and t1, dst, ADDRMASK PREF( 0, 1*32(src) ) PREF( 1, 1*32(dst) ) - bnez t2, copy_bytes_checklen + bnez t2, .Lcopy_bytes_checklen and t0, src, ADDRMASK PREF( 0, 2*32(src) ) PREF( 1, 2*32(dst) ) - bnez t1, dst_unaligned + bnez t1, .Ldst_unaligned nop - bnez t0, src_unaligned_dst_aligned + bnez t0, .Lsrc_unaligned_dst_aligned /* * use delay slot for fall-through * src and dst are aligned; need to compute rem */ -both_aligned: +.Lboth_aligned: SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter - beqz t0, cleanup_both_aligned # len < 8*NBYTES + beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) PREF( 0, 3*32(src) ) PREF( 1, 3*32(dst) ) .align 4 1: -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + R10KCBARRIER(0(ra)) +EXC( LOAD t0, UNIT(0)(src), .Ll_exc) +EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) +EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) +EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) SUB len, len, 8*NBYTES -EXC( LOAD t4, UNIT(4)(src), l_exc_copy) -EXC( LOAD t7, UNIT(5)(src), l_exc_copy) -EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) -EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) -EXC( LOAD t0, UNIT(6)(src), l_exc_copy) -EXC( LOAD t1, UNIT(7)(src), l_exc_copy) +EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy) +EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy) +EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p8u) +EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p7u) +EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy) +EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy) ADD src, src, 8*NBYTES ADD dst, dst, 8*NBYTES -EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) -EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) -EXC( STORE t4, UNIT(-4)(dst), s_exc_p4u) -EXC( STORE t7, UNIT(-3)(dst), s_exc_p3u) -EXC( STORE t0, UNIT(-2)(dst), s_exc_p2u) -EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u) +EXC( STORE t2, UNIT(-6)(dst), .Ls_exc_p6u) +EXC( STORE t3, UNIT(-5)(dst), .Ls_exc_p5u) +EXC( STORE t4, UNIT(-4)(dst), .Ls_exc_p4u) +EXC( STORE t7, UNIT(-3)(dst), .Ls_exc_p3u) +EXC( STORE t0, UNIT(-2)(dst), .Ls_exc_p2u) +EXC( STORE t1, UNIT(-1)(dst), .Ls_exc_p1u) PREF( 0, 8*32(src) ) PREF( 1, 8*32(dst) ) bne len, rem, 1b @@ -253,39 +260,45 @@ EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u) /* * len == rem == the number of bytes left to copy < 8*NBYTES */ -cleanup_both_aligned: - beqz len, done +.Lcleanup_both_aligned: + beqz len, .Ldone sltu t0, len, 4*NBYTES - bnez t0, less_than_4units + bnez t0, .Lless_than_4units and rem, len, (NBYTES-1) # rem = len % NBYTES /* * len >= 4*NBYTES */ -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) +EXC( LOAD t0, UNIT(0)(src), .Ll_exc) +EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) +EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) +EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) SUB len, len, 4*NBYTES ADD src, src, 4*NBYTES -EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) -EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) -EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) -EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) - beqz len, done - ADD dst, dst, 4*NBYTES -less_than_4units: + R10KCBARRIER(0(ra)) +EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u) + .set reorder /* DADDI_WAR */ + ADD dst, dst, 4*NBYTES + beqz len, .Ldone + .set noreorder +.Lless_than_4units: /* * rem = len % NBYTES */ - beq rem, len, copy_bytes + beq rem, len, .Lcopy_bytes nop 1: -EXC( LOAD t0, 0(src), l_exc) + R10KCBARRIER(0(ra)) +EXC( LOAD t0, 0(src), .Ll_exc) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), s_exc_p1u) +EXC( STORE t0, 0(dst), .Ls_exc_p1u) + .set reorder /* DADDI_WAR */ + ADD dst, dst, NBYTES bne rem, len, 1b - ADD dst, dst, NBYTES + .set noreorder /* * src and dst are aligned, need to copy rem bytes (rem < NBYTES) @@ -299,17 +312,17 @@ EXC( STORE t0, 0(dst), s_exc_p1u) * more instruction-level parallelism. */ #define bits t2 - beqz len, done + beqz len, .Ldone ADD t1, dst, len # t1 is just past last byte of dst li bits, 8*NBYTES SLL rem, len, 3 # rem = number of bits to keep -EXC( LOAD t0, 0(src), l_exc) +EXC( LOAD t0, 0(src), .Ll_exc) SUB bits, bits, rem # bits = number of bits to discard SHIFT_DISCARD t0, t0, bits -EXC( STREST t0, -1(t1), s_exc) +EXC( STREST t0, -1(t1), .Ls_exc) jr ra move len, zero -dst_unaligned: +.Ldst_unaligned: /* * dst is unaligned * t0 = src & ADDRMASK @@ -320,22 +333,23 @@ dst_unaligned: * Set match = (src and dst have same alignment) */ #define match rem -EXC( LDFIRST t3, FIRST(0)(src), l_exc) +EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc) ADD t2, zero, NBYTES -EXC( LDREST t3, REST(0)(src), l_exc_copy) +EXC( LDREST t3, REST(0)(src), .Ll_exc_copy) SUB t2, t2, t1 # t2 = number of bytes copied xor match, t0, t1 -EXC( STFIRST t3, FIRST(0)(dst), s_exc) - beq len, t2, done + R10KCBARRIER(0(ra)) +EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc) + beq len, t2, .Ldone SUB len, len, t2 ADD dst, dst, t2 - beqz match, both_aligned + beqz match, .Lboth_aligned ADD src, src, t2 -src_unaligned_dst_aligned: +.Lsrc_unaligned_dst_aligned: SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter PREF( 0, 3*32(src) ) - beqz t0, cleanup_src_unaligned + beqz t0, .Lcleanup_src_unaligned and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES PREF( 1, 3*32(dst) ) 1: @@ -345,52 +359,59 @@ src_unaligned_dst_aligned: * It's OK to load FIRST(N+1) before REST(N) because the two addresses * are to the same unit (unless src is aligned, but it's not). */ -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) + R10KCBARRIER(0(ra)) +EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) +EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy) SUB len, len, 4*NBYTES -EXC( LDREST t0, REST(0)(src), l_exc_copy) -EXC( LDREST t1, REST(1)(src), l_exc_copy) -EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) -EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) -EXC( LDREST t2, REST(2)(src), l_exc_copy) -EXC( LDREST t3, REST(3)(src), l_exc_copy) +EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) +EXC( LDREST t1, REST(1)(src), .Ll_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy) +EXC( LDREST t2, REST(2)(src), .Ll_exc_copy) +EXC( LDREST t3, REST(3)(src), .Ll_exc_copy) PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) ADD src, src, 4*NBYTES #ifdef CONFIG_CPU_SB1 nop # improves slotting #endif -EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) -EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) -EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) -EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) +EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u) PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) + .set reorder /* DADDI_WAR */ + ADD dst, dst, 4*NBYTES bne len, rem, 1b - ADD dst, dst, 4*NBYTES + .set noreorder -cleanup_src_unaligned: - beqz len, done +.Lcleanup_src_unaligned: + beqz len, .Ldone and rem, len, NBYTES-1 # rem = len % NBYTES - beq rem, len, copy_bytes + beq rem, len, .Lcopy_bytes nop 1: -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDREST t0, REST(0)(src), l_exc_copy) + R10KCBARRIER(0(ra)) +EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) +EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), s_exc_p1u) +EXC( STORE t0, 0(dst), .Ls_exc_p1u) + .set reorder /* DADDI_WAR */ + ADD dst, dst, NBYTES bne len, rem, 1b - ADD dst, dst, NBYTES + .set noreorder -copy_bytes_checklen: - beqz len, done +.Lcopy_bytes_checklen: + beqz len, .Ldone nop -copy_bytes: +.Lcopy_bytes: /* 0 < len < NBYTES */ + R10KCBARRIER(0(ra)) #define COPY_BYTE(N) \ -EXC( lb t0, N(src), l_exc); \ +EXC( lb t0, N(src), .Ll_exc); \ SUB len, len, 1; \ - beqz len, done; \ -EXC( sb t0, N(dst), s_exc_p1) + beqz len, .Ldone; \ +EXC( sb t0, N(dst), .Ls_exc_p1) COPY_BYTE(0) COPY_BYTE(1) @@ -400,16 +421,16 @@ EXC( sb t0, N(dst), s_exc_p1) COPY_BYTE(4) COPY_BYTE(5) #endif -EXC( lb t0, NBYTES-2(src), l_exc) +EXC( lb t0, NBYTES-2(src), .Ll_exc) SUB len, len, 1 jr ra -EXC( sb t0, NBYTES-2(dst), s_exc_p1) -done: +EXC( sb t0, NBYTES-2(dst), .Ls_exc_p1) +.Ldone: jr ra nop END(memcpy) -l_exc_copy: +.Ll_exc_copy: /* * Copy bytes from src until faulting load address (or until a * lb faults) @@ -424,12 +445,14 @@ l_exc_copy: nop LOAD t0, THREAD_BUADDR(t0) 1: -EXC( lb t1, 0(src), l_exc) +EXC( lb t1, 0(src), .Ll_exc) ADD src, src, 1 sb t1, 0(dst) # can't fault -- we're copy_from_user + .set reorder /* DADDI_WAR */ + ADD dst, dst, 1 bne src, t0, 1b - ADD dst, dst, 1 -l_exc: + .set noreorder +.Ll_exc: LOAD t0, TI_TASK($28) nop LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address @@ -446,20 +469,33 @@ l_exc: * Clear len bytes starting at dst. Can't call __bzero because it * might modify len. An inefficient loop for these rare times... */ - beqz len, done - SUB src, len, 1 + .set reorder /* DADDI_WAR */ + SUB src, len, 1 + beqz len, .Ldone + .set noreorder 1: sb zero, 0(dst) ADD dst, dst, 1 +#ifndef CONFIG_CPU_DADDI_WORKAROUNDS bnez src, 1b SUB src, src, 1 +#else + .set push + .set noat + li v1, 1 + bnez src, 1b + SUB src, src, v1 + .set pop +#endif jr ra nop -#define SEXC(n) \ -s_exc_p ## n ## u: \ - jr ra; \ - ADD len, len, n*NBYTES +#define SEXC(n) \ + .set reorder; /* DADDI_WAR */ \ +.Ls_exc_p ## n ## u: \ + ADD len, len, n*NBYTES; \ + jr ra; \ + .set noreorder SEXC(8) SEXC(7) @@ -470,10 +506,12 @@ SEXC(3) SEXC(2) SEXC(1) -s_exc_p1: +.Ls_exc_p1: + .set reorder /* DADDI_WAR */ + ADD len, len, 1 jr ra - ADD len, len, 1 -s_exc: + .set noreorder +.Ls_exc: jr ra nop @@ -484,38 +522,44 @@ LEAF(memmove) sltu t0, a1, t0 # dst + len <= src -> memcpy sltu t1, a0, t1 # dst >= src + len -> memcpy and t0, t1 - beqz t0, __memcpy + beqz t0, .L__memcpy move v0, a0 /* return value */ - beqz a2, r_out + beqz a2, .Lr_out END(memmove) /* fall through to __rmemcpy */ LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ sltu t0, a1, a0 - beqz t0, r_end_bytes_up # src >= dst + beqz t0, .Lr_end_bytes_up # src >= dst nop ADD a0, a2 # dst = dst + len ADD a1, a2 # src = src + len -r_end_bytes: +.Lr_end_bytes: + R10KCBARRIER(0(ra)) lb t0, -1(a1) SUB a2, a2, 0x1 sb t0, -1(a0) SUB a1, a1, 0x1 - bnez a2, r_end_bytes - SUB a0, a0, 0x1 + .set reorder /* DADDI_WAR */ + SUB a0, a0, 0x1 + bnez a2, .Lr_end_bytes + .set noreorder -r_out: +.Lr_out: jr ra move a2, zero -r_end_bytes_up: +.Lr_end_bytes_up: + R10KCBARRIER(0(ra)) lb t0, (a1) SUB a2, a2, 0x1 sb t0, (a0) ADD a1, a1, 0x1 - bnez a2, r_end_bytes_up - ADD a0, a0, 0x1 + .set reorder /* DADDI_WAR */ + ADD a0, a0, 0x1 + bnez a2, .Lr_end_bytes_up + .set noreorder jr ra move a2, zero diff -puN arch/mips/lib/memset.S~git-mips arch/mips/lib/memset.S --- a/arch/mips/lib/memset.S~git-mips +++ a/arch/mips/lib/memset.S @@ -5,6 +5,7 @@ * * Copyright (C) 1998, 1999, 2000 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki */ #include #include @@ -71,34 +72,45 @@ LEAF(memset) FEXPORT(__bzero) sltiu t0, a2, LONGSIZE /* very small region? */ - bnez t0, small_memset + bnez t0, .Lsmall_memset andi t0, a0, LONGMASK /* aligned? */ +#ifndef CONFIG_CPU_DADDI_WORKAROUNDS beqz t0, 1f PTR_SUBU t0, LONGSIZE /* alignment in bytes */ +#else + .set noat + li AT, LONGSIZE + beqz t0, 1f + PTR_SUBU t0, AT /* alignment in bytes */ + .set at +#endif + R10KCBARRIER(0(ra)) #ifdef __MIPSEB__ - EX(LONG_S_L, a1, (a0), first_fixup) /* make word/dword aligned */ + EX(LONG_S_L, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */ #endif #ifdef __MIPSEL__ - EX(LONG_S_R, a1, (a0), first_fixup) /* make word/dword aligned */ + EX(LONG_S_R, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */ #endif PTR_SUBU a0, t0 /* long align ptr */ PTR_ADDU a2, t0 /* correct size */ 1: ori t1, a2, 0x3f /* # of full blocks */ xori t1, 0x3f - beqz t1, memset_partial /* no block to fill */ + beqz t1, .Lmemset_partial /* no block to fill */ andi t0, a2, 0x40-LONGSIZE PTR_ADDU t1, a0 /* end address */ .set reorder 1: PTR_ADDIU a0, 64 - f_fill64 a0, -64, a1, fwd_fixup + R10KCBARRIER(0(ra)) + f_fill64 a0, -64, a1, .Lfwd_fixup bne t1, a0, 1b .set noreorder -memset_partial: +.Lmemset_partial: + R10KCBARRIER(0(ra)) PTR_LA t1, 2f /* where to start */ #if LONGSIZE == 4 PTR_SUBU t1, t0 @@ -106,7 +118,7 @@ memset_partial: .set noat LONG_SRL AT, t0, 1 PTR_SUBU t1, AT - .set noat + .set at #endif jr t1 PTR_ADDU a0, t0 /* dest ptr */ @@ -114,26 +126,28 @@ memset_partial: .set push .set noreorder .set nomacro - f_fill64 a0, -64, a1, partial_fixup /* ... but first do longs ... */ + f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */ 2: .set pop andi a2, LONGMASK /* At most one long to go */ beqz a2, 1f PTR_ADDU a0, a2 /* What's left */ + R10KCBARRIER(0(ra)) #ifdef __MIPSEB__ - EX(LONG_S_R, a1, -1(a0), last_fixup) + EX(LONG_S_R, a1, -1(a0), .Llast_fixup) #endif #ifdef __MIPSEL__ - EX(LONG_S_L, a1, -1(a0), last_fixup) + EX(LONG_S_L, a1, -1(a0), .Llast_fixup) #endif 1: jr ra move a2, zero -small_memset: +.Lsmall_memset: beqz a2, 2f PTR_ADDU t1, a0, a2 1: PTR_ADDIU a0, 1 /* fill bytewise */ + R10KCBARRIER(0(ra)) bne t1, a0, 1b sb a1, -1(a0) @@ -141,11 +155,11 @@ small_memset: move a2, zero END(memset) -first_fixup: +.Lfirst_fixup: jr ra nop -fwd_fixup: +.Lfwd_fixup: PTR_L t0, TI_TASK($28) LONG_L t0, THREAD_BUADDR(t0) andi a2, 0x3f @@ -153,7 +167,7 @@ fwd_fixup: jr ra LONG_SUBU a2, t0 -partial_fixup: +.Lpartial_fixup: PTR_L t0, TI_TASK($28) LONG_L t0, THREAD_BUADDR(t0) andi a2, LONGMASK @@ -161,6 +175,6 @@ partial_fixup: jr ra LONG_SUBU a2, t0 -last_fixup: +.Llast_fixup: jr ra andi v1, a2, LONGMASK diff -puN arch/mips/lib/strlen_user.S~git-mips arch/mips/lib/strlen_user.S --- a/arch/mips/lib/strlen_user.S~git-mips +++ a/arch/mips/lib/strlen_user.S @@ -24,16 +24,16 @@ LEAF(__strlen_user_asm) LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 - bnez v0, fault + bnez v0, .Lfault FEXPORT(__strlen_user_nocheck_asm) move v0, a0 -1: EX(lb, t0, (v0), fault) +1: EX(lb, t0, (v0), .Lfault) PTR_ADDIU v0, 1 bnez t0, 1b PTR_SUBU v0, a0 jr ra END(__strlen_user_asm) -fault: move v0, zero +.Lfault: move v0, zero jr ra diff -puN arch/mips/lib/strncpy_user.S~git-mips arch/mips/lib/strncpy_user.S --- a/arch/mips/lib/strncpy_user.S~git-mips +++ a/arch/mips/lib/strncpy_user.S @@ -30,29 +30,30 @@ LEAF(__strncpy_from_user_asm) LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a1 - bnez v0, fault + bnez v0, .Lfault FEXPORT(__strncpy_from_user_nocheck_asm) move v0, zero move v1, a1 .set noreorder -1: EX(lbu, t0, (v1), fault) +1: EX(lbu, t0, (v1), .Lfault) PTR_ADDIU v1, 1 + R10KCBARRIER(0(ra)) beqz t0, 2f sb t0, (a0) PTR_ADDIU v0, 1 - bne v0, a2, 1b - PTR_ADDIU a0, 1 .set reorder + PTR_ADDIU a0, 1 + bne v0, a2, 1b 2: PTR_ADDU t0, a1, v0 xor t0, a1 - bltz t0, fault + bltz t0, .Lfault jr ra # return n END(__strncpy_from_user_asm) -fault: li v0, -EFAULT +.Lfault: li v0, -EFAULT jr ra .section __ex_table,"a" - PTR 1b, fault + PTR 1b, .Lfault .previous diff -puN arch/mips/lib/strnlen_user.S~git-mips arch/mips/lib/strnlen_user.S --- a/arch/mips/lib/strnlen_user.S~git-mips +++ a/arch/mips/lib/strnlen_user.S @@ -28,18 +28,19 @@ LEAF(__strnlen_user_asm) LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 - bnez v0, fault + bnez v0, .Lfault FEXPORT(__strnlen_user_nocheck_asm) move v0, a0 PTR_ADDU a1, a0 # stop pointer 1: beq v0, a1, 1f # limit reached? - EX(lb, t0, (v0), fault) + EX(lb, t0, (v0), .Lfault) PTR_ADDU v0, 1 bnez t0, 1b 1: PTR_SUBU v0, a0 jr ra END(__strnlen_user_asm) -fault: move v0, zero +.Lfault: + move v0, zero jr ra diff -puN arch/mips/lib/uncached.c~git-mips arch/mips/lib/uncached.c --- a/arch/mips/lib/uncached.c~git-mips +++ a/arch/mips/lib/uncached.c @@ -46,9 +46,9 @@ unsigned long __init run_uncached(void * if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) usp = CKSEG1ADDR(sp); #ifdef CONFIG_64BIT - else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) && - (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0)) - usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, + else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0, 0) && + (long long)sp < (long long)PHYS_TO_XKPHYS(8, 0)) + usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED, XKPHYS_TO_PHYS((long long)sp)); #endif else { @@ -58,9 +58,9 @@ unsigned long __init run_uncached(void * if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2) ufunc = CKSEG1ADDR(lfunc); #ifdef CONFIG_64BIT - else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0LL, 0) && - (long long)lfunc < (long long)PHYS_TO_XKPHYS(8LL, 0)) - ufunc = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, + else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0, 0) && + (long long)lfunc < (long long)PHYS_TO_XKPHYS(8, 0)) + ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED, XKPHYS_TO_PHYS((long long)lfunc)); #endif else { diff -puN arch/mips/mips-boards/generic/init.c~git-mips arch/mips/mips-boards/generic/init.c --- a/arch/mips/mips-boards/generic/init.c~git-mips +++ a/arch/mips/mips-boards/generic/init.c @@ -250,6 +250,8 @@ void __init mips_ejtag_setup(void) flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } +extern struct plat_smp_ops msmtc_smp_ops; + void __init prom_init(void) { prom_argc = fw_arg0; @@ -416,4 +418,10 @@ void __init prom_init(void) #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif +#ifdef CONFIG_MIPS_MT_SMP + register_smp_ops(&vsmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); +#endif } diff -puN arch/mips/mips-boards/malta/malta_smtc.c~git-mips arch/mips/mips-boards/malta/malta_smtc.c --- a/arch/mips/mips-boards/malta/malta_smtc.c~git-mips +++ a/arch/mips/mips-boards/malta/malta_smtc.c @@ -15,26 +15,24 @@ * Cause the specified action to be performed on a targeted "CPU" */ -void core_send_ipi(int cpu, unsigned int action) +static void msmtc_send_ipi_single(int cpu, unsigned int action) { /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ smtc_send_ipi(cpu, LINUX_SMP_IPI, action); } -/* - * Platform "CPU" startup hook - */ - -void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) +static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action) { - smtc_boot_secondary(cpu, idle); + unsigned int i; + + for_each_cpu_mask(i, mask) + msmtc_send_ipi_single(i, action); } /* * Post-config but pre-boot cleanup entry point */ - -void __cpuinit prom_init_secondary(void) +static void __cpuinit msmtc_init_secondary(void) { void smtc_init_secondary(void); int myvpe; @@ -50,45 +48,61 @@ void __cpuinit prom_init_secondary(void) set_c0_status(0x100 << cp0_perfcount_irq); } - smtc_init_secondary(); + smtc_init_secondary(); } /* - * Platform SMP pre-initialization - * - * As noted above, we can assume a single CPU for now - * but it may be multithreaded. + * Platform "CPU" startup hook */ - -void __cpuinit plat_smp_setup(void) +static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) { - if (read_c0_config3() & (1<<2)) - mipsmt_build_cpu_map(0); + smtc_boot_secondary(cpu, idle); } -void __init plat_prepare_cpus(unsigned int max_cpus) +/* + * SMP initialization finalization entry point + */ +static void __cpuinit msmtc_smp_finish(void) { - if (read_c0_config3() & (1<<2)) - mipsmt_prepare_cpus(); + smtc_smp_finish(); } /* - * SMP initialization finalization entry point + * Hook for after all CPUs are online */ -void __cpuinit prom_smp_finish(void) +static void msmtc_cpus_done(void) { - smtc_smp_finish(); } /* - * Hook for after all CPUs are online + * Platform SMP pre-initialization + * + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. */ -void prom_cpus_done(void) +static void __init msmtc_smp_setup(void) { + mipsmt_build_cpu_map(0); } +static void __init msmtc_prepare_cpus(unsigned int max_cpus) +{ + mipsmt_prepare_cpus(); +} + +struct plat_smp_ops msmtc_smp_ops = { + .send_ipi_single = msmtc_send_ipi_single, + .send_ipi_mask = msmtc_send_ipi_mask, + .init_secondary = msmtc_init_secondary, + .smp_finish = msmtc_smp_finish, + .cpus_done = msmtc_cpus_done, + .boot_secondary = msmtc_boot_secondary, + .smp_setup = msmtc_smp_setup, + .prepare_cpus = msmtc_prepare_cpus, +}; + #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF /* * IRQ affinity hook diff -puN arch/mips/mipssim/Makefile~git-mips arch/mips/mipssim/Makefile --- a/arch/mips/mipssim/Makefile~git-mips +++ a/arch/mips/mipssim/Makefile @@ -21,6 +21,6 @@ obj-y := sim_platform.o sim_setup.o sim_ sim_cmdline.o obj-$(CONFIG_EARLY_PRINTK) += sim_console.o -obj-$(CONFIG_SMP) += sim_smp.o +obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o EXTRA_CFLAGS += -Werror diff -puN arch/mips/mipssim/sim_setup.c~git-mips arch/mips/mipssim/sim_setup.c --- a/arch/mips/mipssim/sim_setup.c~git-mips +++ a/arch/mips/mipssim/sim_setup.c @@ -60,6 +60,8 @@ void __init plat_mem_setup(void) #endif } +extern struct plat_smp_ops ssmtc_smp_ops; + void __init prom_init(void) { set_io_port_base(0xbfd00000); @@ -67,8 +69,20 @@ void __init prom_init(void) pr_info("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); -} +#ifdef CONFIG_MIPS_MT_SMP + if (cpu_has_mipsmt) + register_smp_ops(&vsmp_smp_ops); + else + register_smp_ops(&up_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMTC + if (cpu_has_mipsmt) + register_smp_ops(&ssmtc_smp_ops); + else + register_smp_ops(&up_smp_ops); +#endif +} static void __init serial_init(void) { diff -puN arch/mips/mipssim/sim_smp.c~git-mips /dev/null --- a/arch/mips/mipssim/sim_smp.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -/* - * Simulator Platform-specific hooks for SMP operation - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#ifdef CONFIG_MIPS_MT_SMTC -#include -#endif /* CONFIG_MIPS_MT_SMTC */ - -/* VPE/SMP Prototype implements platform interfaces directly */ -#if !defined(CONFIG_MIPS_MT_SMP) - -/* - * Cause the specified action to be performed on a targeted "CPU" - */ - -void core_send_ipi(int cpu, unsigned int action) -{ -#ifdef CONFIG_MIPS_MT_SMTC - smtc_send_ipi(cpu, LINUX_SMP_IPI, action); -#endif /* CONFIG_MIPS_MT_SMTC */ -/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ - -} - -/* - * Platform "CPU" startup hook - */ - -void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) -{ -#ifdef CONFIG_MIPS_MT_SMTC - smtc_boot_secondary(cpu, idle); -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -/* - * Post-config but pre-boot cleanup entry point - */ - -void __cpuinit prom_init_secondary(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - void smtc_init_secondary(void); - - smtc_init_secondary(); -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -void plat_smp_setup(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - if (read_c0_config3() & (1 << 2)) - mipsmt_build_cpu_map(0); -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -/* - * Platform SMP pre-initialization - */ - -void plat_prepare_cpus(unsigned int max_cpus) -{ -#ifdef CONFIG_MIPS_MT_SMTC - /* - * As noted above, we can assume a single CPU for now - * but it may be multithreaded. - */ - - if (read_c0_config3() & (1 << 2)) { - mipsmt_prepare_cpus(); - } -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -/* - * SMP initialization finalization entry point - */ - -void __cpuinit prom_smp_finish(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - smtc_smp_finish(); -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -/* - * Hook for after all CPUs are online - */ - -void prom_cpus_done(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - -#endif /* CONFIG_MIPS_MT_SMTC */ -} -#endif /* CONFIG_MIPS32R2_MT_SMP */ diff -puN /dev/null arch/mips/mipssim/sim_smtc.c --- /dev/null +++ a/arch/mips/mipssim/sim_smtc.c @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +/* + * Simulator Platform-specific hooks for SMTC operation + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void ssmtc_send_ipi_single(int cpu, unsigned int action) +{ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ +} + +static inline void ssmtc_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + ssmtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit ssmtc_init_secondary(void) +{ + void smtc_init_secondary(void); + + smtc_init_secondary(); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit ssmtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ +static void ssmtc_cpus_done(void) +{ +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +static void __init ssmtc_smp_setup(void) +{ + if (read_c0_config3() & (1 << 2)) + mipsmt_build_cpu_map(0); +} + +/* + * Platform SMP pre-initialization + */ +static void ssmtc_prepare_cpus(unsigned int max_cpus) +{ + /* + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + + if (read_c0_config3() & (1 << 2)) { + mipsmt_prepare_cpus(); + } +} + +struct plat_smp_ops ssmtc_smp_ops = { + .send_ipi_single = ssmtc_send_ipi_single, + .send_ipi_mask = ssmtc_send_ipi_mask, + .init_secondary = ssmtc_init_secondary, + .smp_finish = ssmtc_smp_finish, + .cpus_done = ssmtc_cpus_done, + .boot_secondary = ssmtc_boot_secondary, + .smp_setup = ssmtc_smp_setup, + .prepare_cpus = ssmtc_prepare_cpus, +}; diff -puN arch/mips/mm/c-r4k.c~git-mips arch/mips/mm/c-r4k.c --- a/arch/mips/mm/c-r4k.c~git-mips +++ a/arch/mips/mm/c-r4k.c @@ -449,7 +449,7 @@ static inline void local_r4k_flush_cache * If the page isn't marked valid, the page cannot possibly be * in the cache. */ - if (!(pte_val(*ptep) & _PAGE_PRESENT)) + if (!(pte_present(*ptep))) return; if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) @@ -468,8 +468,6 @@ static inline void local_r4k_flush_cache if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { r4k_blast_dcache_page(addr); - if (exec && !cpu_icache_snoops_remote_store) - r4k_blast_scache_page(addr); } if (exec) { if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { @@ -533,13 +531,6 @@ static inline void local_r4k_flush_icach R4600_HIT_CACHEOP_WAR_IMPL; protected_blast_dcache_range(start, end); } - - if (!cpu_icache_snoops_remote_store && scache_size) { - if (end - start > scache_size) - r4k_blast_scache(); - else - protected_blast_scache_range(start, end); - } } if (end - start > icache_size) @@ -598,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned l if (size >= scache_size) r4k_blast_scache(); else - blast_scache_range(addr, addr + size); + blast_inv_scache_range(addr, addr + size); return; } @@ -606,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned l r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; - blast_dcache_range(addr, addr + size); + blast_inv_dcache_range(addr, addr + size); } bc_inv(addr, size); @@ -989,6 +980,8 @@ static void __init probe_pcache(void) case CPU_AU1100: case CPU_AU1550: case CPU_AU1200: + case CPU_AU1210: + case CPU_AU1250: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } diff -puN arch/mips/mm/dma-default.c~git-mips arch/mips/mm/dma-default.c --- a/arch/mips/mm/dma-default.c~git-mips +++ a/arch/mips/mm/dma-default.c @@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, BUG_ON(direction == DMA_NONE); if (!plat_device_is_coherent(dev)) - dma_cache_wback_inv((unsigned long)vaddr, size); + __dma_sync((unsigned long)vaddr, size, direction); } EXPORT_SYMBOL(dma_cache_sync); diff -puN arch/mips/mm/pg-r4k.c~git-mips arch/mips/mm/pg-r4k.c --- a/arch/mips/mm/pg-r4k.c~git-mips +++ a/arch/mips/mm/pg-r4k.c @@ -4,6 +4,7 @@ * for more details. * * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2007 Maciej W. Rozycki */ #include #include @@ -12,6 +13,7 @@ #include #include +#include #include #include #include @@ -255,64 +257,58 @@ static inline void build_store_reg(int r __build_store_reg(reg); } -static inline void build_addiu_a2_a0(unsigned long offset) +static inline void build_addiu_rt_rs(unsigned int rt, unsigned int rs, + unsigned long offset) { union mips_instruction mi; BUG_ON(offset > 0x7fff); - mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; - mi.i_format.rs = 4; /* $a0 */ - mi.i_format.rt = 6; /* $a2 */ - mi.i_format.simmediate = offset; + if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) { + mi.i_format.opcode = addiu_op; + mi.i_format.rs = 0; /* $zero */ + mi.i_format.rt = 25; /* $t9 */ + mi.i_format.simmediate = offset; + emit_instruction(mi); + mi.r_format.opcode = spec_op; + mi.r_format.rs = rs; + mi.r_format.rt = 25; /* $t9 */ + mi.r_format.rd = rt; + mi.r_format.re = 0; + mi.r_format.func = daddu_op; + } else { + mi.i_format.opcode = cpu_has_64bit_gp_regs ? + daddiu_op : addiu_op; + mi.i_format.rs = rs; + mi.i_format.rt = rt; + mi.i_format.simmediate = offset; + } emit_instruction(mi); } -static inline void build_addiu_a2(unsigned long offset) +static inline void build_addiu_a2_a0(unsigned long offset) { - union mips_instruction mi; - - BUG_ON(offset > 0x7fff); - - mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; - mi.i_format.rs = 6; /* $a2 */ - mi.i_format.rt = 6; /* $a2 */ - mi.i_format.simmediate = offset; + build_addiu_rt_rs(6, 4, offset); /* $a2, $a0, offset */ +} - emit_instruction(mi); +static inline void build_addiu_a2(unsigned long offset) +{ + build_addiu_rt_rs(6, 6, offset); /* $a2, $a2, offset */ } static inline void build_addiu_a1(unsigned long offset) { - union mips_instruction mi; - - BUG_ON(offset > 0x7fff); - - mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; - mi.i_format.rs = 5; /* $a1 */ - mi.i_format.rt = 5; /* $a1 */ - mi.i_format.simmediate = offset; + build_addiu_rt_rs(5, 5, offset); /* $a1, $a1, offset */ load_offset -= offset; - - emit_instruction(mi); } static inline void build_addiu_a0(unsigned long offset) { - union mips_instruction mi; - - BUG_ON(offset > 0x7fff); - - mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; - mi.i_format.rs = 4; /* $a0 */ - mi.i_format.rt = 4; /* $a0 */ - mi.i_format.simmediate = offset; + build_addiu_rt_rs(4, 4, offset); /* $a0, $a0, offset */ store_offset -= offset; - - emit_instruction(mi); } static inline void build_bne(unsigned int *dest) diff -puN arch/mips/mm/tlbex.c~git-mips arch/mips/mm/tlbex.c --- a/arch/mips/mm/tlbex.c~git-mips +++ a/arch/mips/mm/tlbex.c @@ -6,7 +6,7 @@ * Synthesize TLB refill handlers at runtime. * * Copyright (C) 2004,2005,2006 by Thiemo Seufer - * Copyright (C) 2005 Maciej W. Rozycki + * Copyright (C) 2005, 2007 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) * * ... and the days got worse and worse and now you see @@ -19,20 +19,15 @@ * (Condolences to Napoleon XIV) */ -#include - -#include #include #include #include #include -#include -#include +#include #include #include #include -#include #include static inline int r45k_bvahwbug(void) @@ -66,7 +61,7 @@ static inline int __maybe_unused r10000_ * why; it's not an issue caused by the core RTL. * */ -static __init int __attribute__((unused)) m4kc_tlbp_war(void) +static int __init m4kc_tlbp_war(void) { return (current_cpu_data.processor_id & 0xffff00) == (PRID_COMP_MIPS | PRID_IMP_4KC); @@ -140,7 +135,7 @@ struct insn { | (e) << RE_SH \ | (f) << FUNC_SH) -static __initdata struct insn insn_table[] = { +static struct insn insn_table[] __initdata = { { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, @@ -193,7 +188,7 @@ static __initdata struct insn insn_table #undef M -static __init u32 build_rs(u32 arg) +static u32 __init build_rs(u32 arg) { if (arg & ~RS_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -201,7 +196,7 @@ static __init u32 build_rs(u32 arg) return (arg & RS_MASK) << RS_SH; } -static __init u32 build_rt(u32 arg) +static u32 __init build_rt(u32 arg) { if (arg & ~RT_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -209,7 +204,7 @@ static __init u32 build_rt(u32 arg) return (arg & RT_MASK) << RT_SH; } -static __init u32 build_rd(u32 arg) +static u32 __init build_rd(u32 arg) { if (arg & ~RD_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -217,7 +212,7 @@ static __init u32 build_rd(u32 arg) return (arg & RD_MASK) << RD_SH; } -static __init u32 build_re(u32 arg) +static u32 __init build_re(u32 arg) { if (arg & ~RE_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -225,7 +220,7 @@ static __init u32 build_re(u32 arg) return (arg & RE_MASK) << RE_SH; } -static __init u32 build_simm(s32 arg) +static u32 __init build_simm(s32 arg) { if (arg > 0x7fff || arg < -0x8000) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -233,7 +228,7 @@ static __init u32 build_simm(s32 arg) return arg & 0xffff; } -static __init u32 build_uimm(u32 arg) +static u32 __init build_uimm(u32 arg) { if (arg & ~IMM_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -241,7 +236,7 @@ static __init u32 build_uimm(u32 arg) return arg & IMM_MASK; } -static __init u32 build_bimm(s32 arg) +static u32 __init build_bimm(s32 arg) { if (arg > 0x1ffff || arg < -0x20000) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -252,7 +247,7 @@ static __init u32 build_bimm(s32 arg) return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); } -static __init u32 build_jimm(u32 arg) +static u32 __init build_jimm(u32 arg) { if (arg & ~((JIMM_MASK) << 2)) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -260,7 +255,7 @@ static __init u32 build_jimm(u32 arg) return (arg >> 2) & JIMM_MASK; } -static __init u32 build_func(u32 arg) +static u32 __init build_func(u32 arg) { if (arg & ~FUNC_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -268,7 +263,7 @@ static __init u32 build_func(u32 arg) return arg & FUNC_MASK; } -static __init u32 build_set(u32 arg) +static u32 __init build_set(u32 arg) { if (arg & ~SET_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -293,7 +288,7 @@ static void __init build_insn(u32 **buf, break; } - if (!ip) + if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) panic("Unsupported TLB synthesizer instruction %d", opc); op = ip->match; @@ -315,69 +310,69 @@ static void __init build_insn(u32 **buf, } #define I_u1u2u3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2u1u3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u3u1u2(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, c, a); \ } #define I_u1u2s3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2s3u1(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ signed int b, unsigned int c) \ { \ build_insn(buf, insn##op, c, a, b); \ } #define I_u2u1s3(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u1u2(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ unsigned int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1s2(op) \ - static inline void __init i##op(u32 **buf, unsigned int a, \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ signed int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1(op) \ - static inline void __init i##op(u32 **buf, unsigned int a) \ + static void __init __maybe_unused i##op(u32 **buf, unsigned int a) \ { \ build_insn(buf, insn##op, a); \ } #define I_0(op) \ - static inline void __init i##op(u32 **buf) \ + static void __init __maybe_unused i##op(u32 **buf) \ { \ build_insn(buf, insn##op); \ } @@ -457,7 +452,7 @@ struct label { enum label_id lab; }; -static __init void build_label(struct label **lab, u32 *addr, +static void __init build_label(struct label **lab, u32 *addr, enum label_id l) { (*lab)->addr = addr; @@ -466,7 +461,7 @@ static __init void build_label(struct la } #define L_LA(lb) \ - static inline void l##lb(struct label **lab, u32 *addr) \ + static inline void __init l##lb(struct label **lab, u32 *addr) \ { \ build_label(lab, addr, label##lb); \ } @@ -525,37 +520,46 @@ L_LA(_r3000_write_probe_fail) #define i_ssnop(buf) i_sll(buf, 0, 0, 1) #define i_ehb(buf) i_sll(buf, 0, 0, 3) -#ifdef CONFIG_64BIT -static __init int __maybe_unused in_compat_space_p(long addr) +static int __init __maybe_unused in_compat_space_p(long addr) { /* Is this address in 32bit compat space? */ +#ifdef CONFIG_64BIT return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); +#else + return 1; +#endif } -static __init int __maybe_unused rel_highest(long val) +static int __init __maybe_unused rel_highest(long val) { +#ifdef CONFIG_64BIT return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; +#else + return 0; +#endif } -static __init int __maybe_unused rel_higher(long val) +static int __init __maybe_unused rel_higher(long val) { +#ifdef CONFIG_64BIT return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; -} +#else + return 0; #endif +} -static __init int rel_hi(long val) +static int __init rel_hi(long val) { return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; } -static __init int rel_lo(long val) +static int __init rel_lo(long val) { return ((val & 0xffff) ^ 0x8000) - 0x8000; } -static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) +static void __init i_LA_mostly(u32 **buf, unsigned int rs, long addr) { -#ifdef CONFIG_64BIT if (!in_compat_space_p(addr)) { i_lui(buf, rs, rel_highest(addr)); if (rel_higher(addr)) @@ -567,16 +571,18 @@ static __init void i_LA_mostly(u32 **buf } else i_dsll32(buf, rs, rs, 0); } else -#endif i_lui(buf, rs, rel_hi(addr)); } -static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, - long addr) +static void __init __maybe_unused i_LA(u32 **buf, unsigned int rs, long addr) { i_LA_mostly(buf, rs, addr); - if (rel_lo(addr)) - i_ADDIU(buf, rs, rs, rel_lo(addr)); + if (rel_lo(addr)) { + if (!in_compat_space_p(addr)) + i_daddiu(buf, rs, rs, rel_lo(addr)); + else + i_addiu(buf, rs, rs, rel_lo(addr)); + } } /* @@ -589,7 +595,7 @@ struct reloc { enum label_id lab; }; -static __init void r_mips_pc16(struct reloc **rel, u32 *addr, +static void __init r_mips_pc16(struct reloc **rel, u32 *addr, enum label_id l) { (*rel)->addr = addr; @@ -614,7 +620,7 @@ static inline void __resolve_relocs(stru } } -static __init void resolve_relocs(struct reloc *rel, struct label *lab) +static void __init resolve_relocs(struct reloc *rel, struct label *lab) { struct label *l; @@ -624,7 +630,7 @@ static __init void resolve_relocs(struct __resolve_relocs(rel, l); } -static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, +static void __init move_relocs(struct reloc *rel, u32 *first, u32 *end, long off) { for (; rel->lab != label_invalid; rel++) @@ -632,7 +638,7 @@ static __init void move_relocs(struct re rel->addr += off; } -static __init void move_labels(struct label *lab, u32 *first, u32 *end, +static void __init move_labels(struct label *lab, u32 *first, u32 *end, long off) { for (; lab->lab != label_invalid; lab++) @@ -640,7 +646,7 @@ static __init void move_labels(struct la lab->addr += off; } -static __init void copy_handler(struct reloc *rel, struct label *lab, +static void __init copy_handler(struct reloc *rel, struct label *lab, u32 *first, u32 *end, u32 *target) { long off = (long)(target - first); @@ -651,7 +657,7 @@ static __init void copy_handler(struct r move_labels(lab, first, end, off); } -static __init int __maybe_unused insn_has_bdelay(struct reloc *rel, +static int __init __maybe_unused insn_has_bdelay(struct reloc *rel, u32 *addr) { for (; rel->lab != label_invalid; rel++) { @@ -714,6 +720,22 @@ il_bgez(u32 **p, struct reloc **r, unsig i_bgez(p, reg, 0); } +/* + * For debug purposes. + */ +static inline void dump_handler(const u32 *handler, int count) +{ + int i; + + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + + for (i = 0; i < count; i++) + pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); + + pr_debug("\t.set pop\n"); +} + /* The only general purpose registers allowed in TLB handlers. */ #define K0 26 #define K1 27 @@ -743,11 +765,11 @@ il_bgez(u32 **p, struct reloc **r, unsig * We deliberately chose a buffer size of 128, so we won't scribble * over anything important on overflow before we panic. */ -static __initdata u32 tlb_handler[128]; +static u32 tlb_handler[128] __initdata; /* simply assume worst case size for labels and relocs */ -static __initdata struct label labels[128]; -static __initdata struct reloc relocs[128]; +static struct label labels[128] __initdata; +static struct reloc relocs[128] __initdata; /* * The R3000 TLB handler is simple. @@ -756,7 +778,6 @@ static void __init build_r3000_tlb_refil { long pgdc = (long)pgd_current; u32 *p; - int i; memset(tlb_handler, 0, sizeof(tlb_handler)); p = tlb_handler; @@ -785,13 +806,9 @@ static void __init build_r3000_tlb_refil pr_info("Synthesized TLB refill handler (%u instructions).\n", (unsigned int)(p - tlb_handler)); - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (p - tlb_handler); i++) - pr_debug("\t.word 0x%08x\n", tlb_handler[i]); - pr_debug("\t.set pop\n"); - memcpy((void *)ebase, tlb_handler, 0x80); + + dump_handler((u32 *)ebase, 32); } /* @@ -801,7 +818,7 @@ static void __init build_r3000_tlb_refil * other one.To keep things simple, we first assume linear space, * then we relocate it to the final handler layout as needed. */ -static __initdata u32 final_handler[64]; +static u32 final_handler[64] __initdata; /* * Hazards @@ -825,7 +842,7 @@ static __initdata u32 final_handler[64]; * * As if we MIPS hackers wouldn't know how to nop pipelines happy ... */ -static __init void __maybe_unused build_tlb_probe_entry(u32 **p) +static void __init __maybe_unused build_tlb_probe_entry(u32 **p) { switch (current_cpu_type()) { /* Found by experiment: R4600 v2.0 needs this, too. */ @@ -849,7 +866,7 @@ static __init void __maybe_unused build_ */ enum tlb_write_entry { tlb_random, tlb_indexed }; -static __init void build_tlb_write_entry(u32 **p, struct label **l, +static void __init build_tlb_write_entry(u32 **p, struct label **l, struct reloc **r, enum tlb_write_entry wmode) { @@ -860,6 +877,12 @@ static __init void build_tlb_write_entry case tlb_indexed: tlbw = i_tlbwi; break; } + if (cpu_has_mips_r2) { + i_ehb(p); + tlbw(p); + return; + } + switch (current_cpu_type()) { case CPU_R4000PC: case CPU_R4000SC: @@ -894,6 +917,8 @@ static __init void build_tlb_write_entry case CPU_AU1500: case CPU_AU1550: case CPU_AU1200: + case CPU_AU1210: + case CPU_AU1250: case CPU_PR4450: i_nop(p); tlbw(p); @@ -935,14 +960,6 @@ static __init void build_tlb_write_entry tlbw(p); break; - case CPU_4KEC: - case CPU_24K: - case CPU_34K: - case CPU_74K: - i_ehb(p); - tlbw(p); - break; - case CPU_RM9000: /* * When the JTLB is updated by tlbwi or tlbwr, a subsequent @@ -993,7 +1010,7 @@ static __init void build_tlb_write_entry * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pmd entry. */ -static __init void +static void __init build_get_pmde64(u32 **p, struct label **l, struct reloc **r, unsigned int tmp, unsigned int ptr) { @@ -1054,7 +1071,7 @@ build_get_pmde64(u32 **p, struct label * * BVADDR is the faulting address, PTR is scratch. * PTR will hold the pgd for vmalloc. */ -static __init void +static void __init build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, unsigned int bvaddr, unsigned int ptr) { @@ -1087,7 +1104,10 @@ build_get_pgd_vmalloc64(u32 **p, struct } else { i_LA_mostly(p, ptr, modd); il_b(p, r, label_vmalloc_done); - i_daddiu(p, ptr, ptr, rel_lo(modd)); + if (in_compat_space_p(modd)) + i_addiu(p, ptr, ptr, rel_lo(modd)); + else + i_daddiu(p, ptr, ptr, rel_lo(modd)); } l_vmalloc(l, *p); @@ -1108,7 +1128,10 @@ build_get_pgd_vmalloc64(u32 **p, struct } else { i_LA_mostly(p, ptr, swpd); il_b(p, r, label_vmalloc_done); - i_daddiu(p, ptr, ptr, rel_lo(swpd)); + if (in_compat_space_p(swpd)) + i_addiu(p, ptr, ptr, rel_lo(swpd)); + else + i_daddiu(p, ptr, ptr, rel_lo(swpd)); } } @@ -1118,7 +1141,7 @@ build_get_pgd_vmalloc64(u32 **p, struct * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pgd entry. */ -static __init void __maybe_unused +static void __init __maybe_unused build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { long pgdc = (long)pgd_current; @@ -1153,7 +1176,7 @@ build_get_pgde32(u32 **p, unsigned int t #endif /* !CONFIG_64BIT */ -static __init void build_adjust_context(u32 **p, unsigned int ctx) +static void __init build_adjust_context(u32 **p, unsigned int ctx) { unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); @@ -1179,7 +1202,7 @@ static __init void build_adjust_context( i_andi(p, ctx, ctx, mask); } -static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) +static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { /* * Bug workaround for the Nevada. It seems as if under certain @@ -1204,7 +1227,7 @@ static __init void build_get_ptep(u32 ** i_ADDU(p, ptr, ptr, tmp); /* add in offset */ } -static __init void build_update_entries(u32 **p, unsigned int tmp, +static void __init build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) { /* @@ -1254,7 +1277,6 @@ static void __init build_r4000_tlb_refil struct reloc *r = relocs; u32 *f; unsigned int final_len; - int i; memset(tlb_handler, 0, sizeof(tlb_handler)); memset(labels, 0, sizeof(labels)); @@ -1356,20 +1378,9 @@ static void __init build_r4000_tlb_refil pr_info("Synthesized TLB refill handler (%u instructions).\n", final_len); - f = final_handler; -#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2) - if (final_len > 32) - final_len = 64; - else - f = final_handler + 32; -#endif /* CONFIG_64BIT */ - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < final_len; i++) - pr_debug("\t.word 0x%08x\n", f[i]); - pr_debug("\t.set pop\n"); - memcpy((void *)ebase, final_handler, 0x100); + + dump_handler((u32 *)ebase, 64); } /* @@ -1381,18 +1392,15 @@ static void __init build_r4000_tlb_refil extern void tlb_do_page_fault_0(void); extern void tlb_do_page_fault_1(void); -#define __tlb_handler_align \ - __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) - /* * 128 instructions for the fastpath handler is generous and should * never be exceeded. */ #define FASTPATH_SIZE 128 -u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; -u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; -u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; +u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; +u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; +u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; static void __init iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) @@ -1600,7 +1608,6 @@ static void __init build_r3000_tlb_load_ u32 *p = handle_tlbl; struct label *l = labels; struct reloc *r = relocs; - int i; memset(handle_tlbl, 0, sizeof(handle_tlbl)); memset(labels, 0, sizeof(labels)); @@ -1623,11 +1630,7 @@ static void __init build_r3000_tlb_load_ pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbl)); - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (p - handle_tlbl); i++) - pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); - pr_debug("\t.set pop\n"); + dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); } static void __init build_r3000_tlb_store_handler(void) @@ -1635,7 +1638,6 @@ static void __init build_r3000_tlb_store u32 *p = handle_tlbs; struct label *l = labels; struct reloc *r = relocs; - int i; memset(handle_tlbs, 0, sizeof(handle_tlbs)); memset(labels, 0, sizeof(labels)); @@ -1658,11 +1660,7 @@ static void __init build_r3000_tlb_store pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbs)); - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (p - handle_tlbs); i++) - pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); - pr_debug("\t.set pop\n"); + dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); } static void __init build_r3000_tlb_modify_handler(void) @@ -1670,7 +1668,6 @@ static void __init build_r3000_tlb_modif u32 *p = handle_tlbm; struct label *l = labels; struct reloc *r = relocs; - int i; memset(handle_tlbm, 0, sizeof(handle_tlbm)); memset(labels, 0, sizeof(labels)); @@ -1693,11 +1690,7 @@ static void __init build_r3000_tlb_modif pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbm)); - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (p - handle_tlbm); i++) - pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); - pr_debug("\t.set pop\n"); + dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); } /* @@ -1750,7 +1743,6 @@ static void __init build_r4000_tlb_load_ u32 *p = handle_tlbl; struct label *l = labels; struct reloc *r = relocs; - int i; memset(handle_tlbl, 0, sizeof(handle_tlbl)); memset(labels, 0, sizeof(labels)); @@ -1783,11 +1775,7 @@ static void __init build_r4000_tlb_load_ pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbl)); - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (p - handle_tlbl); i++) - pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); - pr_debug("\t.set pop\n"); + dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); } static void __init build_r4000_tlb_store_handler(void) @@ -1795,7 +1783,6 @@ static void __init build_r4000_tlb_store u32 *p = handle_tlbs; struct label *l = labels; struct reloc *r = relocs; - int i; memset(handle_tlbs, 0, sizeof(handle_tlbs)); memset(labels, 0, sizeof(labels)); @@ -1819,11 +1806,7 @@ static void __init build_r4000_tlb_store pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbs)); - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (p - handle_tlbs); i++) - pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); - pr_debug("\t.set pop\n"); + dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); } static void __init build_r4000_tlb_modify_handler(void) @@ -1831,7 +1814,6 @@ static void __init build_r4000_tlb_modif u32 *p = handle_tlbm; struct label *l = labels; struct reloc *r = relocs; - int i; memset(handle_tlbm, 0, sizeof(handle_tlbm)); memset(labels, 0, sizeof(labels)); @@ -1856,11 +1838,7 @@ static void __init build_r4000_tlb_modif pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbm)); - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (p - handle_tlbm); i++) - pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); - pr_debug("\t.set pop\n"); + dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); } void __init build_tlb_refill_handler(void) diff -puN arch/mips/oprofile/op_model_mipsxx.c~git-mips arch/mips/oprofile/op_model_mipsxx.c --- a/arch/mips/oprofile/op_model_mipsxx.c~git-mips +++ a/arch/mips/oprofile/op_model_mipsxx.c @@ -19,7 +19,7 @@ #define M_PERFCTL_SUPERVISOR (1UL << 2) #define M_PERFCTL_USER (1UL << 3) #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) -#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5) +#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) #define M_PERFCTL_MT_EN(filter) ((filter) << 20) #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) diff -puN arch/mips/pci/pci-bcm1480.c~git-mips arch/mips/pci/pci-bcm1480.c --- a/arch/mips/pci/pci-bcm1480.c~git-mips +++ a/arch/mips/pci/pci-bcm1480.c @@ -178,8 +178,8 @@ struct pci_ops bcm1480_pci_ops = { static struct resource bcm1480_mem_resource = { .name = "BCM1480 PCI MEM", - .start = 0x30000000UL, - .end = 0x3fffffffUL, + .start = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, + .end = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL, .flags = IORESOURCE_MEM, }; diff -puN arch/mips/pci/pci-bcm1480ht.c~git-mips arch/mips/pci/pci-bcm1480ht.c --- a/arch/mips/pci/pci-bcm1480ht.c~git-mips +++ a/arch/mips/pci/pci-bcm1480ht.c @@ -173,8 +173,8 @@ struct pci_ops bcm1480ht_pci_ops = { static struct resource bcm1480ht_mem_resource = { .name = "BCM1480 HT MEM", - .start = 0x40000000UL, - .end = 0x5fffffffUL, + .start = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES, + .end = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES + 0x1fffffffUL, .flags = IORESOURCE_MEM, }; diff -puN arch/mips/philips/pnx8550/common/setup.c~git-mips arch/mips/philips/pnx8550/common/setup.c --- a/arch/mips/philips/pnx8550/common/setup.c~git-mips +++ a/arch/mips/philips/pnx8550/common/setup.c @@ -74,7 +74,7 @@ struct resource standard_io_resources[] }, }; -#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) +#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources) extern struct resource pci_io_resource; extern struct resource pci_mem_resource; diff -puN arch/mips/philips/pnx8550/common/time.c~git-mips arch/mips/philips/pnx8550/common/time.c --- a/arch/mips/philips/pnx8550/common/time.c~git-mips +++ a/arch/mips/philips/pnx8550/common/time.c @@ -47,11 +47,6 @@ static struct clocksource pnx_clocksourc .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static void timer_ack(void) -{ - write_c0_compare(cpj); -} - static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *c = dev_id; @@ -94,30 +89,22 @@ static struct clock_event_device pnx8xxx .set_next_event = pnx8xxx_set_next_event, }; -/* - * plat_time_init() - it does the following things: - * - * 1) plat_time_init() - - * a) (optional) set up RTC routines, - * b) (optional) calibrate and set the mips_hpt_frequency - * (only needed if you intended to use cpu counter as timer interrupt - * source) - */ +static inline void timer_ack(void) +{ + write_c0_compare(cpj); +} __init void plat_time_init(void) { - unsigned int configPR; - unsigned int n; - unsigned int m; - unsigned int p; - unsigned int pow2p; + unsigned int configPR; + unsigned int n; + unsigned int m; + unsigned int p; + unsigned int pow2p; clockevents_register_device(&pnx8xxx_clockevent); clocksource_register(&pnx_clocksource); - setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); - setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); - /* Timer 1 start */ configPR = read_c0_config7(); configPR &= ~0x00000008; @@ -158,6 +145,6 @@ __init void plat_time_init(void) write_c0_count2(0); write_c0_compare2(0xffffffff); + setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); + setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); } - - diff -puN arch/mips/philips/pnx8550/jbs/init.c~git-mips arch/mips/philips/pnx8550/jbs/init.c --- a/arch/mips/philips/pnx8550/jbs/init.c~git-mips +++ a/arch/mips/philips/pnx8550/jbs/init.c @@ -45,11 +45,8 @@ const char *get_system_type(void) void __init prom_init(void) { - unsigned long memsize; - mips_machtype = MACH_PHILIPS_JBS; - //memsize = 0x02800000; /* Trimedia uses memory above */ memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); diff -puN arch/mips/philips/pnx8550/stb810/prom_init.c~git-mips arch/mips/philips/pnx8550/stb810/prom_init.c --- a/arch/mips/philips/pnx8550/stb810/prom_init.c~git-mips +++ a/arch/mips/philips/pnx8550/stb810/prom_init.c @@ -41,8 +41,6 @@ void __init prom_init(void) prom_init_cmdline(); - mips_machtype = MACH_PHILIPS_STB810; - memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); } diff -puN arch/mips/pmc-sierra/yosemite/i2c-yosemite.h~git-mips /dev/null --- a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/mips/pmc-sierra/yosemite/i2c-yosemite.h - * - * Copyright (C) 2003 PMC-Sierra Inc. - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __I2C_YOSEMITE_H -#define __I2C_YOSEMITE_H - -/* Read and Write operations to the chip */ - -#define TITAN_I2C_BASE 0xbb000000 /* XXX Needs to change */ - -#define TITAN_I2C_WRITE(offset, data) \ - *(volatile unsigned long *)(TITAN_I2C_BASE + offset) = data - -#define TITAN_I2C_READ(offset) *(volatile unsigned long *)(TITAN_I2C_BASE + offset) - - -/* Local constansts*/ -#define TITAN_I2C_MAX_FILTER 15 -#define TITAN_I2C_MAX_CLK 1023 -#define TITAN_I2C_MAX_ARBF 15 -#define TITAN_I2C_MAX_NAK 15 -#define TITAN_I2C_MAX_MASTERCODE 7 -#define TITAN_I2C_MAX_WORDS_PER_RW 4 -#define TITAN_I2C_MAX_POLL 100 - -/* Registers used for I2C work */ -#define TITAN_I2C_SCMB_CONTROL 0x0180 /* SCMB Control */ -#define TITAN_I2C_SCMB_CLOCK_A 0x0184 /* SCMB Clock A */ -#define TITAN_I2C_SCMB_CLOCK_B 0x0188 /* SCMB Clock B */ -#define TITAN_I2C_CONFIG 0x01A0 /* I2C Config */ -#define TITAN_I2C_COMMAND 0x01A4 /* I2C Command */ -#define TITAN_I2C_SLAVE_ADDRESS 0x01A8 /* I2C Slave Address */ -#define TITAN_I2C_DATA 0x01AC /* I2C Data [15:0] */ -#define TITAN_I2C_INTERRUPTS 0x01BC /* I2C Interrupts */ - -/* Error */ -#define TITAN_I2C_ERR_ARB_LOST (-9220) -#define TITAN_I2C_ERR_NO_RESP (-9221) -#define TITAN_I2C_ERR_DATA_COLLISION (-9222) -#define TITAN_I2C_ERR_TIMEOUT (-9223) -#define TITAN_I2C_ERR_OK 0 - -/* I2C Command Type */ -typedef enum { - TITAN_I2C_CMD_WRITE = 0, - TITAN_I2C_CMD_READ = 1, - TITAN_I2C_CMD_READ_WRITE = 2 -} titan_i2c_cmd_type; - -/* I2C structures */ -typedef struct { - int filtera; /* Register 0x0184, bits 15 - 12 */ - int clka; /* Register 0x0184, bits 9 - 0 */ - int filterb; /* Register 0x0188, bits 15 - 12 */ - int clkb; /* Register 0x0188, bits 9 - 0 */ -} titan_i2c_config; - -/* I2C command type */ -typedef struct { - titan_i2c_cmd_type type; /* Type of command */ - int num_arb; /* Register 0x01a0, bits 15 - 12 */ - int num_nak; /* Register 0x01a0, bits 11 - 8 */ - int addr_size; /* Register 0x01a0, bit 7 */ - int mst_code; /* Register 0x01a0, bits 6 - 4 */ - int arb_en; /* Register 0x01a0, bit 1 */ - int speed; /* Register 0x01a0, bit 0 */ - int slave_addr; /* Register 0x01a8 */ - int write_size; /* Register 0x01a4, bits 10 - 8 */ - unsigned int *data; /* Register 0x01ac */ -} titan_i2c_command; - -#endif /* __I2C_YOSEMITE_H */ diff -puN arch/mips/pmc-sierra/yosemite/prom.c~git-mips arch/mips/pmc-sierra/yosemite/prom.c --- a/arch/mips/pmc-sierra/yosemite/prom.c~git-mips +++ a/arch/mips/pmc-sierra/yosemite/prom.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,8 @@ static void prom_halt(void) __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); } +extern struct plat_smp_ops yos_smp_ops; + /* * Init routine which accepts the variables from PMON */ @@ -126,9 +129,9 @@ void __init prom_init(void) env++; } - mips_machtype = MACH_TITAN_YOSEMITE; - prom_grab_secondary(); + + register_smp_ops(&yos_smp_ops); } void __init prom_free_prom_memory(void) diff -puN arch/mips/pmc-sierra/yosemite/smp.c~git-mips arch/mips/pmc-sierra/yosemite/smp.c --- a/arch/mips/pmc-sierra/yosemite/smp.c~git-mips +++ a/arch/mips/pmc-sierra/yosemite/smp.c @@ -42,70 +42,6 @@ void __init prom_grab_secondary(void) launchstack + LAUNCHSTACK_SIZE, 0); } -/* - * Detect available CPUs, populate phys_cpu_present_map before smp_init - * - * We don't want to start the secondary CPU yet nor do we have a nice probing - * feature in PMON so we just assume presence of the secondary core. - */ -void __init plat_smp_setup(void) -{ - int i; - - cpus_clear(phys_cpu_present_map); - - for (i = 0; i < 2; i++) { - cpu_set(i, phys_cpu_present_map); - __cpu_number_map[i] = i; - __cpu_logical_map[i] = i; - } -} - -void __init plat_prepare_cpus(unsigned int max_cpus) -{ - /* - * Be paranoid. Enable the IPI only if we're really about to go SMP. - */ - if (cpus_weight(cpu_possible_map)) - set_c0_status(STATUSF_IP5); -} - -/* - * Firmware CPU startup hook - * Complicated by PMON's weird interface which tries to minimic the UNIX fork. - * It launches the next * available CPU and copies some information on the - * stack so the first thing we do is throw away that stuff and load useful - * values into the registers ... - */ -void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) -{ - unsigned long gp = (unsigned long) task_thread_info(idle); - unsigned long sp = __KSTK_TOS(idle); - - secondary_sp = sp; - secondary_gp = gp; - - spin_unlock(&launch_lock); -} - -/* Hook for after all CPUs are online */ -void prom_cpus_done(void) -{ -} - -/* - * After we've done initial boot, this function is called to allow the - * board code to clean up state, if needed - */ -void __cpuinit prom_init_secondary(void) -{ - set_c0_status(ST0_CO | ST0_IE | ST0_IM); -} - -void __cpuinit prom_smp_finish(void) -{ -} - void titan_mailbox_irq(void) { int cpu = smp_processor_id(); @@ -133,7 +69,7 @@ void titan_mailbox_irq(void) /* * Send inter-processor interrupt */ -void core_send_ipi(int cpu, unsigned int action) +static void yos_send_ipi_single(int cpu, unsigned int action) { /* * Generate an INTMSG so that it can be sent over to the @@ -159,3 +95,86 @@ void core_send_ipi(int cpu, unsigned int break; } } + +static void yos_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + yos_send_ipi_single(i, action); +} + +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +static void __cpuinit yos_init_secondary(void) +{ + set_c0_status(ST0_CO | ST0_IE | ST0_IM); +} + +static void __cpuinit yos_smp_finish(void) +{ +} + +/* Hook for after all CPUs are online */ +static void yos_cpus_done(void) +{ +} + +/* + * Firmware CPU startup hook + * Complicated by PMON's weird interface which tries to minimic the UNIX fork. + * It launches the next * available CPU and copies some information on the + * stack so the first thing we do is throw away that stuff and load useful + * values into the registers ... + */ +static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long) task_thread_info(idle); + unsigned long sp = __KSTK_TOS(idle); + + secondary_sp = sp; + secondary_gp = gp; + + spin_unlock(&launch_lock); +} + +/* + * Detect available CPUs, populate phys_cpu_present_map before smp_init + * + * We don't want to start the secondary CPU yet nor do we have a nice probing + * feature in PMON so we just assume presence of the secondary core. + */ +static void __init yos_smp_setup(void) +{ + int i; + + cpus_clear(phys_cpu_present_map); + + for (i = 0; i < 2; i++) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = i; + __cpu_logical_map[i] = i; + } +} + +static void __init yos_prepare_cpus(unsigned int max_cpus) +{ + /* + * Be paranoid. Enable the IPI only if we're really about to go SMP. + */ + if (cpus_weight(cpu_possible_map)) + set_c0_status(STATUSF_IP5); +} + +struct plat_smp_ops yos_smp_ops = { + .send_ipi_single = yos_send_ipi_single, + .send_ipi_mask = yos_send_ipi_mask, + .init_secondary = yos_init_secondary, + .smp_finish = yos_smp_finish, + .cpus_done = yos_cpus_done, + .boot_secondary = yos_boot_secondary, + .smp_setup = yos_smp_setup, + .prepare_cpus = yos_prepare_cpus, +}; diff -puN arch/mips/qemu/Makefile~git-mips /dev/null --- a/arch/mips/qemu/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for Qemu specific kernel interface routines under Linux. -# - -obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o - -obj-$(CONFIG_EARLY_PRINTK) += q-console.o -obj-$(CONFIG_SMP) += q-smp.o - -EXTRA_CFLAGS += -Werror diff -puN arch/mips/qemu/q-console.c~git-mips /dev/null --- a/arch/mips/qemu/q-console.c +++ /dev/null @@ -1,26 +0,0 @@ -#include -#include -#include -#include - -#define PORT(offset) (0x3f8 + (offset)) - -static inline unsigned int serial_in(int offset) -{ - return inb(PORT(offset)); -} - -static inline void serial_out(int offset, int value) -{ - outb(value, PORT(offset)); -} - -int prom_putchar(char c) -{ - while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(UART_TX, c); - - return 1; -} diff -puN arch/mips/qemu/q-firmware.c~git-mips /dev/null --- a/arch/mips/qemu/q-firmware.c +++ /dev/null @@ -1,24 +0,0 @@ -#include -#include -#include -#include -#include - -#define QEMU_PORT_BASE 0xb4000000 - -void __init prom_init(void) -{ - int *cmdline; - - cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260); - if (*cmdline == 0x12345678) { - if (*(char *)(cmdline + 1)) - strcpy(arcs_cmdline, (char *)(cmdline + 1)); - add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM); - } else { - add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); - } - - - set_io_port_base(QEMU_PORT_BASE); -} diff -puN arch/mips/qemu/q-irq.c~git-mips /dev/null --- a/arch/mips/qemu/q-irq.c +++ /dev/null @@ -1,37 +0,0 @@ -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause(); - - if (pending & 0x8000) { - do_IRQ(Q_COUNT_COMPARE_IRQ); - return; - } - if (pending & 0x0400) { - int irq = i8259_irq(); - - if (likely(irq >= 0)) - do_IRQ(irq); - - return; - } -} - -void __init arch_init_irq(void) -{ - mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ - - mips_cpu_irq_init(); - init_i8259_irqs(); - set_c0_status(0x400); -} diff -puN arch/mips/qemu/q-mem.c~git-mips /dev/null --- a/arch/mips/qemu/q-mem.c +++ /dev/null @@ -1,5 +0,0 @@ -#include - -void __init prom_free_prom_memory(void) -{ -} diff -puN arch/mips/qemu/q-reset.c~git-mips /dev/null --- a/arch/mips/qemu/q-reset.c +++ /dev/null @@ -1,33 +0,0 @@ - -#include -#include -#include -#include - -static void qemu_machine_restart(char *command) -{ - volatile unsigned int *reg = (unsigned int *)QEMU_RESTART_REG; - - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - *reg = 42; - while (1) - cpu_wait(); -} - -static void qemu_machine_halt(void) -{ - volatile unsigned int *reg = (unsigned int *)QEMU_HALT_REG; - - *reg = 42; - while (1) - cpu_wait(); -} - -void qemu_reboot_setup(void) -{ - _machine_restart = qemu_machine_restart; - _machine_halt = qemu_machine_halt; -} diff -puN arch/mips/qemu/q-setup.c~git-mips /dev/null --- a/arch/mips/qemu/q-setup.c +++ /dev/null @@ -1,22 +0,0 @@ -#include - -#include -#include -#include - -extern void qemu_reboot_setup(void); - -const char *get_system_type(void) -{ - return "Qemu"; -} - -void __init plat_time_init(void) -{ - setup_pit_timer(); -} - -void __init plat_mem_setup(void) -{ - qemu_reboot_setup(); -} diff -puN arch/mips/qemu/q-smp.c~git-mips /dev/null --- a/arch/mips/qemu/q-smp.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org) - * - * Symmetric Uniprocessor (TM) Support - */ -#include -#include - -/* - * Send inter-processor interrupt - */ -void core_send_ipi(int cpu, unsigned int action) -{ - panic(KERN_ERR "%s called", __FUNCTION__); -} - -/* - * After we've done initial boot, this function is called to allow the - * board code to clean up state, if needed - */ -void __cpuinit prom_init_secondary(void) -{ -} - -void __cpuinit prom_smp_finish(void) -{ -} - -/* Hook for after all CPUs are online */ -void prom_cpus_done(void) -{ -} - -void __init prom_prepare_cpus(unsigned int max_cpus) -{ - cpus_clear(phys_cpu_present_map); -} - -/* - * Firmware CPU startup hook - */ -void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) -{ -} - -void __init plat_smp_setup(void) -{ -} -void __init plat_prepare_cpus(unsigned int max_cpus) -{ -} diff -puN arch/mips/sgi-ip22/Makefile~git-mips arch/mips/sgi-ip22/Makefile --- a/arch/mips/sgi-ip22/Makefile~git-mips +++ a/arch/mips/sgi-ip22/Makefile @@ -3,9 +3,11 @@ # under Linux. # -obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-berr.o \ - ip22-time.o ip22-nvram.o ip22-platform.o ip22-reset.o ip22-setup.o +obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \ + ip22-platform.o ip22-reset.o ip22-setup.o +obj-$(CONFIG_SGI_IP22) += ip22-berr.o +obj-$(CONFIG_SGI_IP28) += ip28-berr.o obj-$(CONFIG_EISA) += ip22-eisa.o -EXTRA_CFLAGS += -Werror +# EXTRA_CFLAGS += -Werror diff -puN arch/mips/sgi-ip22/ip22-mc.c~git-mips arch/mips/sgi-ip22/ip22-mc.c --- a/arch/mips/sgi-ip22/ip22-mc.c~git-mips +++ a/arch/mips/sgi-ip22/ip22-mc.c @@ -4,6 +4,7 @@ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org) + * Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28 */ #include @@ -137,9 +138,12 @@ void __init sgimc_init(void) /* Step 2: Enable all parity checking in cpu control register * zero. */ + /* don't touch parity settings for IP28 */ +#ifndef CONFIG_SGI_IP28 tmp = sgimc->cpuctrl0; tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | SGIMC_CCTRL0_R4KNOCHKPARR); +#endif sgimc->cpuctrl0 = tmp; /* Step 3: Setup the MC write buffer depth, this is controlled diff -puN /dev/null arch/mips/sgi-ip22/ip28-berr.c --- /dev/null +++ a/arch/mips/sgi-ip22/ip28-berr.c @@ -0,0 +1,502 @@ +/* + * ip28-berr.c: Bus error handling. + * + * Copyright (C) 2002, 2003 Ladislav Michl (ladis@linux-mips.org) + * Copyright (C) 2005 Peter Fuerst (pf@net.alphadv.de) - IP28 + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int count_be_is_fixup; +static unsigned int count_be_handler; +static unsigned int count_be_interrupt; +static int debug_be_interrupt; + +static unsigned int cpu_err_stat; /* Status reg for CPU */ +static unsigned int gio_err_stat; /* Status reg for GIO */ +static unsigned int cpu_err_addr; /* Error address reg for CPU */ +static unsigned int gio_err_addr; /* Error address reg for GIO */ +static unsigned int extio_stat; +static unsigned int hpc3_berr_stat; /* Bus error interrupt status */ + +struct hpc3_stat { + unsigned long addr; + unsigned int ctrl; + unsigned int cbp; + unsigned int ndptr; +}; + +static struct { + struct hpc3_stat pbdma[8]; + struct hpc3_stat scsi[2]; + struct hpc3_stat ethrx, ethtx; +} hpc3; + +static struct { + unsigned long err_addr; + struct { + u32 lo; + u32 hi; + } tags[1][2], tagd[4][2], tagi[4][2]; /* Way 0/1 */ +} cache_tags; + +static inline void save_cache_tags(unsigned busaddr) +{ + unsigned long addr = CAC_BASE | busaddr; + int i; + cache_tags.err_addr = addr; + + /* + * Starting with a bus-address, save secondary cache (indexed by + * PA[23..18:7..6]) tags first. + */ + addr &= ~1L; +#define tag cache_tags.tags[0] + cache_op(Index_Load_Tag_S, addr); + tag[0].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ + tag[0].hi = read_c0_taghi(); /* PA[39:36] */ + cache_op(Index_Load_Tag_S, addr | 1L); + tag[1].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ + tag[1].hi = read_c0_taghi(); /* PA[39:36] */ +#undef tag + + /* + * Save all primary data cache (indexed by VA[13:5]) tags which + * might fit to this bus-address, knowing that VA[11:0] == PA[11:0]. + * Saving all tags and evaluating them later is easier and safer + * than relying on VA[13:12] from the secondary cache tags to pick + * matching primary tags here already. + */ + addr &= (0xffL << 56) | ((1 << 12) - 1); +#define tag cache_tags.tagd[i] + for (i = 0; i < 4; ++i, addr += (1 << 12)) { + cache_op(Index_Load_Tag_D, addr); + tag[0].lo = read_c0_taglo(); /* PA[35:12] */ + tag[0].hi = read_c0_taghi(); /* PA[39:36] */ + cache_op(Index_Load_Tag_D, addr | 1L); + tag[1].lo = read_c0_taglo(); /* PA[35:12] */ + tag[1].hi = read_c0_taghi(); /* PA[39:36] */ + } +#undef tag + + /* + * Save primary instruction cache (indexed by VA[13:6]) tags + * the same way. + */ + addr &= (0xffL << 56) | ((1 << 12) - 1); +#define tag cache_tags.tagi[i] + for (i = 0; i < 4; ++i, addr += (1 << 12)) { + cache_op(Index_Load_Tag_I, addr); + tag[0].lo = read_c0_taglo(); /* PA[35:12] */ + tag[0].hi = read_c0_taghi(); /* PA[39:36] */ + cache_op(Index_Load_Tag_I, addr | 1L); + tag[1].lo = read_c0_taglo(); /* PA[35:12] */ + tag[1].hi = read_c0_taghi(); /* PA[39:36] */ + } +#undef tag +} + +#define GIO_ERRMASK 0xff00 +#define CPU_ERRMASK 0x3f00 + +static void save_and_clear_buserr(void) +{ + int i; + + /* save status registers */ + cpu_err_addr = sgimc->cerr; + cpu_err_stat = sgimc->cstat; + gio_err_addr = sgimc->gerr; + gio_err_stat = sgimc->gstat; + extio_stat = sgioc->extio; + hpc3_berr_stat = hpc3c0->bestat; + + hpc3.scsi[0].addr = (unsigned long)&hpc3c0->scsi_chan0; + hpc3.scsi[0].ctrl = hpc3c0->scsi_chan0.ctrl; /* HPC3_SCTRL_ACTIVE ? */ + hpc3.scsi[0].cbp = hpc3c0->scsi_chan0.cbptr; + hpc3.scsi[0].ndptr = hpc3c0->scsi_chan0.ndptr; + + hpc3.scsi[1].addr = (unsigned long)&hpc3c0->scsi_chan1; + hpc3.scsi[1].ctrl = hpc3c0->scsi_chan1.ctrl; /* HPC3_SCTRL_ACTIVE ? */ + hpc3.scsi[1].cbp = hpc3c0->scsi_chan1.cbptr; + hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr; + + hpc3.ethrx.addr = (unsigned long)&hpc3c0->ethregs.rx_cbptr; + hpc3.ethrx.ctrl = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */ + hpc3.ethrx.cbp = hpc3c0->ethregs.rx_cbptr; + hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr; + + hpc3.ethtx.addr = (unsigned long)&hpc3c0->ethregs.tx_cbptr; + hpc3.ethtx.ctrl = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */ + hpc3.ethtx.cbp = hpc3c0->ethregs.tx_cbptr; + hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr; + + for (i = 0; i < 8; ++i) { + /* HPC3_PDMACTRL_ISACT ? */ + hpc3.pbdma[i].addr = (unsigned long)&hpc3c0->pbdma[i]; + hpc3.pbdma[i].ctrl = hpc3c0->pbdma[i].pbdma_ctrl; + hpc3.pbdma[i].cbp = hpc3c0->pbdma[i].pbdma_bptr; + hpc3.pbdma[i].ndptr = hpc3c0->pbdma[i].pbdma_dptr; + } + i = 0; + if (gio_err_stat & CPU_ERRMASK) + i = gio_err_addr; + if (cpu_err_stat & CPU_ERRMASK) + i = cpu_err_addr; + save_cache_tags(i); + + sgimc->cstat = sgimc->gstat = 0; +} + +static void print_cache_tags(void) +{ + u32 scb, scw; + int i; + + printk(KERN_ERR "Cache tags @ %08x:\n", (unsigned)cache_tags.err_addr); + + /* PA[31:12] shifted to PTag0 (PA[35:12]) format */ + scw = (cache_tags.err_addr >> 4) & 0x0fffff00; + + scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 5) - 1); + for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */ + if ((cache_tags.tagd[i][0].lo & 0x0fffff00) != scw && + (cache_tags.tagd[i][1].lo & 0x0fffff00) != scw) + continue; + printk(KERN_ERR + "D: 0: %08x %08x, 1: %08x %08x (VA[13:5] %04x)\n", + cache_tags.tagd[i][0].hi, cache_tags.tagd[i][0].lo, + cache_tags.tagd[i][1].hi, cache_tags.tagd[i][1].lo, + scb | (1 << 12)*i); + } + scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 6) - 1); + for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */ + if ((cache_tags.tagi[i][0].lo & 0x0fffff00) != scw && + (cache_tags.tagi[i][1].lo & 0x0fffff00) != scw) + continue; + printk(KERN_ERR + "I: 0: %08x %08x, 1: %08x %08x (VA[13:6] %04x)\n", + cache_tags.tagi[i][0].hi, cache_tags.tagi[i][0].lo, + cache_tags.tagi[i][1].hi, cache_tags.tagi[i][1].lo, + scb | (1 << 12)*i); + } + i = read_c0_config(); + scb = i & (1 << 13) ? 7:6; /* scblksize = 2^[7..6] */ + scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */ + + i = ((1 << scw) - 1) & ~((1 << scb) - 1); + printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x (PA[%u:%u] %05x)\n", + cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo, + cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo, + scw-1, scb, i & (unsigned)cache_tags.err_addr); +} + +static inline const char *cause_excode_text(int cause) +{ + static const char *txt[32] = + { "Interrupt", + "TLB modification", + "TLB (load or instruction fetch)", + "TLB (store)", + "Address error (load or instruction fetch)", + "Address error (store)", + "Bus error (instruction fetch)", + "Bus error (data: load or store)", + "Syscall", + "Breakpoint", + "Reserved instruction", + "Coprocessor unusable", + "Arithmetic Overflow", + "Trap", + "14", + "Floating-Point", + "16", "17", "18", "19", "20", "21", "22", + "Watch Hi/Lo", + "24", "25", "26", "27", "28", "29", "30", "31", + }; + return txt[(cause & 0x7c) >> 2]; +} + +static void print_buserr(const struct pt_regs *regs) +{ + const int field = 2 * sizeof(unsigned long); + int error = 0; + + if (extio_stat & EXTIO_MC_BUSERR) { + printk(KERN_ERR "MC Bus Error\n"); + error |= 1; + } + if (extio_stat & EXTIO_HPC3_BUSERR) { + printk(KERN_ERR "HPC3 Bus Error 0x%x:\n", + hpc3_berr_stat, + (hpc3_berr_stat & HPC3_BESTAT_PIDMASK) >> + HPC3_BESTAT_PIDSHIFT, + (hpc3_berr_stat & HPC3_BESTAT_CTYPE) ? "PIO" : "DMA", + hpc3_berr_stat & HPC3_BESTAT_BLMASK); + error |= 2; + } + if (extio_stat & EXTIO_EISA_BUSERR) { + printk(KERN_ERR "EISA Bus Error\n"); + error |= 4; + } + if (cpu_err_stat & CPU_ERRMASK) { + printk(KERN_ERR "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n", + cpu_err_stat, + cpu_err_stat & SGIMC_CSTAT_RD ? "RD " : "", + cpu_err_stat & SGIMC_CSTAT_PAR ? "PAR " : "", + cpu_err_stat & SGIMC_CSTAT_ADDR ? "ADDR " : "", + cpu_err_stat & SGIMC_CSTAT_SYSAD_PAR ? "SYSAD " : "", + cpu_err_stat & SGIMC_CSTAT_SYSCMD_PAR ? "SYSCMD " : "", + cpu_err_stat & SGIMC_CSTAT_BAD_DATA ? "BAD_DATA " : "", + cpu_err_addr); + error |= 8; + } + if (gio_err_stat & GIO_ERRMASK) { + printk(KERN_ERR "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x%08x\n", + gio_err_stat, + gio_err_stat & SGIMC_GSTAT_RD ? "RD " : "", + gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "", + gio_err_stat & SGIMC_GSTAT_TIME ? "TIME " : "", + gio_err_stat & SGIMC_GSTAT_PROM ? "PROM " : "", + gio_err_stat & SGIMC_GSTAT_ADDR ? "ADDR " : "", + gio_err_stat & SGIMC_GSTAT_BC ? "BC " : "", + gio_err_stat & SGIMC_GSTAT_PIO_RD ? "PIO_RD " : "", + gio_err_stat & SGIMC_GSTAT_PIO_WR ? "PIO_WR " : "", + gio_err_addr); + error |= 16; + } + if (!error) + printk(KERN_ERR "MC: Hmm, didn't find any error condition.\n"); + else { + printk(KERN_ERR "CP0: config %08x, " + "MC: cpuctrl0/1: %08x/%05x, giopar: %04x\n" + "MC: cpu/gio_memacc: %08x/%05x, memcfg0/1: %08x/%08x\n", + read_c0_config(), + sgimc->cpuctrl0, sgimc->cpuctrl0, sgimc->giopar, + sgimc->cmacc, sgimc->gmacc, + sgimc->mconfig0, sgimc->mconfig1); + print_cache_tags(); + } + printk(KERN_ALERT "%s, epc == %0*lx, ra == %0*lx\n", + cause_excode_text(regs->cp0_cause), + field, regs->cp0_epc, field, regs->regs[31]); +} + +/* + * Check, whether MC's (virtual) DMA address caused the bus error. + * See "Virtual DMA Specification", Draft 1.5, Feb 13 1992, SGI + */ + +static int addr_is_ram(unsigned long addr, unsigned sz) +{ + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long a = boot_mem_map.map[i].addr; + if (a <= addr && addr+sz <= a+boot_mem_map.map[i].size) + return 1; + } + return 0; +} + +static int check_microtlb(u32 hi, u32 lo, unsigned long vaddr) +{ + /* This is likely rather similar to correct code ;-) */ + + vaddr &= 0x7fffffff; /* Doc. states that top bit is ignored */ + + /* If tlb-entry is valid and VPN-high (bits [30:21] ?) matches... */ + if ((lo & 2) && (vaddr >> 21) == ((hi<<1) >> 22)) { + u32 ctl = sgimc->dma_ctrl; + if (ctl & 1) { + unsigned int pgsz = (ctl & 2) ? 14:12; /* 16k:4k */ + /* PTEIndex is VPN-low (bits [22:14]/[20:12] ?) */ + unsigned long pte = (lo >> 6) << 12; /* PTEBase */ + pte += 8*((vaddr >> pgsz) & 0x1ff); + if (addr_is_ram(pte, 8)) { + /* + * Note: Since DMA hardware does look up + * translation on its own, this PTE *must* + * match the TLB/EntryLo-register format ! + */ + unsigned long a = *(unsigned long *) + PHYS_TO_XKSEG_UNCACHED(pte); + a = (a & 0x3f) << 6; /* PFN */ + a += vaddr & ((1 << pgsz) - 1); + return (cpu_err_addr == a); + } + } + } + return 0; +} + +static int check_vdma_memaddr(void) +{ + if (cpu_err_stat & CPU_ERRMASK) { + u32 a = sgimc->maddronly; + + if (!(sgimc->dma_ctrl & 0x100)) /* Xlate-bit clear ? */ + return (cpu_err_addr == a); + + if (check_microtlb(sgimc->dtlb_hi0, sgimc->dtlb_lo0, a) || + check_microtlb(sgimc->dtlb_hi1, sgimc->dtlb_lo1, a) || + check_microtlb(sgimc->dtlb_hi2, sgimc->dtlb_lo2, a) || + check_microtlb(sgimc->dtlb_hi3, sgimc->dtlb_lo3, a)) + return 1; + } + return 0; +} + +static int check_vdma_gioaddr(void) +{ + if (gio_err_stat & GIO_ERRMASK) { + u32 a = sgimc->gio_dma_trans; + a = (sgimc->gmaddronly & ~a) | (sgimc->gio_dma_sbits & a); + return (gio_err_addr == a); + } + return 0; +} + +/* + * MC sends an interrupt whenever bus or parity errors occur. In addition, + * if the error happened during a CPU read, it also asserts the bus error + * pin on the R4K. Code in bus error handler save the MC bus error registers + * and then clear the interrupt when this happens. + */ + +static int ip28_be_interrupt(const struct pt_regs *regs) +{ + int i; + + save_and_clear_buserr(); + /* + * Try to find out, whether we got here by a mispredicted speculative + * load/store operation. If so, it's not fatal, we can go on. + */ + /* Any cause other than "Interrupt" (ExcCode 0) is fatal. */ + if (regs->cp0_cause & CAUSEF_EXCCODE) + goto mips_be_fatal; + + /* Any cause other than "Bus error interrupt" (IP6) is weird. */ + if ((regs->cp0_cause & CAUSEF_IP6) != CAUSEF_IP6) + goto mips_be_fatal; + + if (extio_stat & (EXTIO_HPC3_BUSERR | EXTIO_EISA_BUSERR)) + goto mips_be_fatal; + + /* Any state other than "Memory bus error" is fatal. */ + if (cpu_err_stat & CPU_ERRMASK & ~SGIMC_CSTAT_ADDR) + goto mips_be_fatal; + + /* GIO errors other than timeouts are fatal */ + if (gio_err_stat & GIO_ERRMASK & ~SGIMC_GSTAT_TIME) + goto mips_be_fatal; + + /* + * Now we have an asynchronous bus error, speculatively or DMA caused. + * Need to search all DMA descriptors for the error address. + */ + for (i = 0; i < sizeof(hpc3)/sizeof(struct hpc3_stat); ++i) { + struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i; + if ((cpu_err_stat & CPU_ERRMASK) && + (cpu_err_addr == hp->ndptr || cpu_err_addr == hp->cbp)) + break; + if ((gio_err_stat & GIO_ERRMASK) && + (gio_err_addr == hp->ndptr || gio_err_addr == hp->cbp)) + break; + } + if (i < sizeof(hpc3)/sizeof(struct hpc3_stat)) { + struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i; + printk(KERN_ERR "at DMA addresses: HPC3 @ %08lx:" + " ctl %08x, ndp %08x, cbp %08x\n", + CPHYSADDR(hp->addr), hp->ctrl, hp->ndptr, hp->cbp); + goto mips_be_fatal; + } + /* Check MC's virtual DMA stuff. */ + if (check_vdma_memaddr()) { + printk(KERN_ERR "at GIO DMA: mem address 0x%08x.\n", + sgimc->maddronly); + goto mips_be_fatal; + } + if (check_vdma_gioaddr()) { + printk(KERN_ERR "at GIO DMA: gio address 0x%08x.\n", + sgimc->gmaddronly); + goto mips_be_fatal; + } + /* A speculative bus error... */ + if (debug_be_interrupt) { + print_buserr(regs); + printk(KERN_ERR "discarded!\n"); + } + return MIPS_BE_DISCARD; + +mips_be_fatal: + print_buserr(regs); + return MIPS_BE_FATAL; +} + +void ip22_be_interrupt(int irq) +{ + const struct pt_regs *regs = get_irq_regs(); + + count_be_interrupt++; + + if (ip28_be_interrupt(regs) != MIPS_BE_DISCARD) { + /* Assume it would be too dangerous to continue ... */ + die_if_kernel("Oops", regs); + force_sig(SIGBUS, current); + } else if (debug_be_interrupt) + show_regs((struct pt_regs *)regs); +} + +static int ip28_be_handler(struct pt_regs *regs, int is_fixup) +{ + /* + * We arrive here only in the unusual case of do_be() invocation, + * i.e. by a bus error exception without a bus error interrupt. + */ + if (is_fixup) { + count_be_is_fixup++; + save_and_clear_buserr(); + return MIPS_BE_FIXUP; + } + count_be_handler++; + return ip28_be_interrupt(regs); +} + +void __init ip22_be_init(void) +{ + board_be_handler = ip28_be_handler; +} + +int ip28_show_be_info(struct seq_file *m) +{ + seq_printf(m, "IP28 be fixups\t\t: %u\n", count_be_is_fixup); + seq_printf(m, "IP28 be interrupts\t: %u\n", count_be_interrupt); + seq_printf(m, "IP28 be handler\t\t: %u\n", count_be_handler); + + return 0; +} + +static int __init debug_be_setup(char *str) +{ + debug_be_interrupt++; + return 1; +} +__setup("ip28_debug_be", debug_be_setup); diff -puN arch/mips/sgi-ip27/ip27-init.c~git-mips arch/mips/sgi-ip27/ip27-init.c --- a/arch/mips/sgi-ip27/ip27-init.c~git-mips +++ a/arch/mips/sgi-ip27/ip27-init.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff -puN arch/mips/sgi-ip27/ip27-klnuma.c~git-mips arch/mips/sgi-ip27/ip27-klnuma.c --- a/arch/mips/sgi-ip27/ip27-klnuma.c~git-mips +++ a/arch/mips/sgi-ip27/ip27-klnuma.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff -puN arch/mips/sgi-ip27/ip27-smp.c~git-mips arch/mips/sgi-ip27/ip27-smp.c --- a/arch/mips/sgi-ip27/ip27-smp.c~git-mips +++ a/arch/mips/sgi-ip27/ip27-smp.c @@ -140,30 +140,51 @@ static __init void intr_clear_all(nasid_ REMOTE_HUB_CLR_INTR(nasid, i); } -void __init plat_smp_setup(void) +static void ip27_send_ipi_single(int destid, unsigned int action) { - cnodeid_t cnode; + int irq; - for_each_online_node(cnode) { - if (cnode == 0) - continue; - intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); + switch (action) { + case SMP_RESCHEDULE_YOURSELF: + irq = CPU_RESCHED_A_IRQ; + break; + case SMP_CALL_FUNCTION: + irq = CPU_CALL_A_IRQ; + break; + default: + panic("sendintr"); } - replicate_kernel_text(); + irq += cputoslice(destid); /* - * Assumption to be fixed: we're always booted on logical / physical - * processor 0. While we're always running on logical processor 0 - * this still means this is physical processor zero; it might for - * example be disabled in the firwware. + * Convert the compact hub number to the NASID to get the correct + * part of the address space. Then set the interrupt bit associated + * with the CPU we want to send the interrupt to. */ - alloc_cpupda(0, 0); + REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cpu_to_node(destid)), irq); } -void __init plat_prepare_cpus(unsigned int max_cpus) +static void ip27_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + ip27_send_ipi_single(i, action); +} + +static void __cpuinit ip27_init_secondary(void) +{ + per_cpu_init(); + local_irq_enable(); +} + +static void __cpuinit ip27_smp_finish(void) +{ +} + +static void __init ip27_cpus_done(void) { - /* We already did everything necessary earlier */ } /* @@ -171,7 +192,7 @@ void __init plat_prepare_cpus(unsigned i * set sp to the kernel stack of the newly created idle process, gp to the proc * struct so that current_thread_info() will work. */ -void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) +static void __cpuinit ip27_boot_secondary(int cpu, struct task_struct *idle) { unsigned long gp = (unsigned long)task_thread_info(idle); unsigned long sp = __KSTK_TOS(idle); @@ -181,41 +202,39 @@ void __cpuinit prom_boot_secondary(int c 0, (void *) sp, (void *) gp); } -void __cpuinit prom_init_secondary(void) +static void __init ip27_smp_setup(void) { - per_cpu_init(); - local_irq_enable(); -} - -void __init prom_cpus_done(void) -{ -} - -void __cpuinit prom_smp_finish(void) -{ -} - -void core_send_ipi(int destid, unsigned int action) -{ - int irq; + cnodeid_t cnode; - switch (action) { - case SMP_RESCHEDULE_YOURSELF: - irq = CPU_RESCHED_A_IRQ; - break; - case SMP_CALL_FUNCTION: - irq = CPU_CALL_A_IRQ; - break; - default: - panic("sendintr"); + for_each_online_node(cnode) { + if (cnode == 0) + continue; + intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); } - irq += cputoslice(destid); + replicate_kernel_text(); /* - * Convert the compact hub number to the NASID to get the correct - * part of the address space. Then set the interrupt bit associated - * with the CPU we want to send the interrupt to. + * Assumption to be fixed: we're always booted on logical / physical + * processor 0. While we're always running on logical processor 0 + * this still means this is physical processor zero; it might for + * example be disabled in the firwware. */ - REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cpu_to_node(destid)), irq); + alloc_cpupda(0, 0); } + +static void __init ip27_prepare_cpus(unsigned int max_cpus) +{ + /* We already did everything necessary earlier */ +} + +struct plat_smp_ops ip27_smp_ops = { + .send_ipi_single = ip27_send_ipi_single, + .send_ipi_mask = ip27_send_ipi_mask, + .init_secondary = ip27_init_secondary, + .smp_finish = ip27_smp_finish, + .cpus_done = ip27_cpus_done, + .boot_secondary = ip27_boot_secondary, + .smp_setup = ip27_smp_setup, + .prepare_cpus = ip27_prepare_cpus, +}; diff -puN arch/mips/sibyte/bcm1480/smp.c~git-mips arch/mips/sibyte/bcm1480/smp.c --- a/arch/mips/sibyte/bcm1480/smp.c~git-mips +++ a/arch/mips/sibyte/bcm1480/smp.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -67,28 +68,114 @@ void __cpuinit bcm1480_smp_init(void) change_c0_status(ST0_IM, imask); } -void __cpuinit bcm1480_smp_finish(void) +/* + * These are routines for dealing with the sb1250 smp capabilities + * independent of board/firmware + */ + +/* + * Simple enough; everything is set up, so just poke the appropriate mailbox + * register, and we should be set + */ +static void bcm1480_send_ipi_single(int cpu, unsigned int action) +{ + __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); +} + +static void bcm1480_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + bcm1480_send_ipi_single(i, action); +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit bcm1480_init_secondary(void) +{ + extern void bcm1480_smp_init(void); + + bcm1480_smp_init(); +} + +/* + * Do any tidying up before marking online and running the idle + * loop + */ +static void __cpuinit bcm1480_smp_finish(void) { extern void sb1480_clockevent_init(void); sb1480_clockevent_init(); local_irq_enable(); + bcm1480_smp_finish(); } /* - * These are routines for dealing with the sb1250 smp capabilities - * independent of board/firmware + * Final cleanup after all secondaries booted */ +static void bcm1480_cpus_done(void) +{ +} /* - * Simple enough; everything is set up, so just poke the appropriate mailbox - * register, and we should be set + * Setup the PC, SP, and GP of a secondary processor and start it + * running! */ -void core_send_ipi(int cpu, unsigned int action) +static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle) { - __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); + int retval; + + retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, + __KSTK_TOS(idle), + (unsigned long)task_thread_info(idle), 0); + if (retval != 0) + printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); } +/* + * Use CFE to find out how many CPUs are available, setting up + * phys_cpu_present_map and the logical/physical mappings. + * XXXKW will the boot CPU ever not be physical 0? + * + * Common setup before any secondaries are started + */ +static void __init bcm1480_smp_setup(void) +{ + int i, num; + + cpus_clear(phys_cpu_present_map); + cpu_set(0, phys_cpu_present_map); + __cpu_number_map[0] = 0; + __cpu_logical_map[0] = 0; + + for (i = 1, num = 0; i < NR_CPUS; i++) { + if (cfe_cpu_stop(i) == 0) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = ++num; + __cpu_logical_map[num] = i; + } + } + printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); +} + +static void __init bcm1480_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops bcm1480_smp_ops = { + .send_ipi_single = bcm1480_send_ipi_single, + .send_ipi_mask = bcm1480_send_ipi_mask, + .init_secondary = bcm1480_init_secondary, + .smp_finish = bcm1480_smp_finish, + .cpus_done = bcm1480_cpus_done, + .boot_secondary = bcm1480_boot_secondary, + .smp_setup = bcm1480_smp_setup, + .prepare_cpus = bcm1480_prepare_cpus, +}; + void bcm1480_mailbox_interrupt(void) { int cpu = smp_processor_id(); diff -puN arch/mips/sibyte/cfe/Makefile~git-mips arch/mips/sibyte/cfe/Makefile --- a/arch/mips/sibyte/cfe/Makefile~git-mips +++ a/arch/mips/sibyte/cfe/Makefile @@ -1,3 +1,2 @@ lib-y = setup.o -lib-$(CONFIG_SMP) += smp.o lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o diff -puN arch/mips/sibyte/cfe/setup.c~git-mips arch/mips/sibyte/cfe/setup.c --- a/arch/mips/sibyte/cfe/setup.c~git-mips +++ a/arch/mips/sibyte/cfe/setup.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -232,6 +233,9 @@ static int __init initrd_setup(char *str #endif +extern struct plat_smp_ops sb_smp_ops; +extern struct plat_smp_ops bcm1480_smp_ops; + /* * prom_init is called just after the cpu type is determined, from setup_arch() */ @@ -297,9 +301,6 @@ void __init prom_init(void) * command line */ strcpy(arcs_cmdline, "root=/dev/ram0 "); -#ifdef CONFIG_SIBYTE_PTSWARM - strcat(arcs_cmdline, "console=ttyS0,115200 "); -#endif } else { /* The loader should have set the command line */ /* too early for panic to do any good */ @@ -340,6 +341,13 @@ void __init prom_init(void) arcs_cmdline[CL_SIZE-1] = 0; prom_meminit(); + +#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) + register_smp_ops(&sb_smp_ops); +#endif +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + register_smp_ops(&bcm1480_smp_ops); +#endif } void __init prom_free_prom_memory(void) diff -puN arch/mips/sibyte/cfe/smp.c~git-mips /dev/null --- a/arch/mips/sibyte/cfe/smp.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#include -#include -#include -#include - -#include -#include - -/* - * Use CFE to find out how many CPUs are available, setting up - * phys_cpu_present_map and the logical/physical mappings. - * XXXKW will the boot CPU ever not be physical 0? - * - * Common setup before any secondaries are started - */ -void __init plat_smp_setup(void) -{ - int i, num; - - cpus_clear(phys_cpu_present_map); - cpu_set(0, phys_cpu_present_map); - __cpu_number_map[0] = 0; - __cpu_logical_map[0] = 0; - - for (i = 1, num = 0; i < NR_CPUS; i++) { - if (cfe_cpu_stop(i) == 0) { - cpu_set(i, phys_cpu_present_map); - __cpu_number_map[i] = ++num; - __cpu_logical_map[num] = i; - } - } - printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); -} - -void __init plat_prepare_cpus(unsigned int max_cpus) -{ -} - -/* - * Setup the PC, SP, and GP of a secondary processor and start it - * running! - */ -void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) -{ - int retval; - - retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, - __KSTK_TOS(idle), - (unsigned long)task_thread_info(idle), 0); - if (retval != 0) - printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); -} - -/* - * Code to run on secondary just after probing the CPU - */ -void __cpuinit prom_init_secondary(void) -{ -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) - extern void bcm1480_smp_init(void); - bcm1480_smp_init(); -#elif defined(CONFIG_SIBYTE_SB1250) - extern void sb1250_smp_init(void); - sb1250_smp_init(); -#else -#error invalid SMP configuration -#endif -} - -/* - * Do any tidying up before marking online and running the idle - * loop - */ -void __cpuinit prom_smp_finish(void) -{ -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) - extern void bcm1480_smp_finish(void); - bcm1480_smp_finish(); -#elif defined(CONFIG_SIBYTE_SB1250) - extern void sb1250_smp_finish(void); - sb1250_smp_finish(); -#else -#error invalid SMP configuration -#endif -} - -/* - * Final cleanup after all secondaries booted - */ -void prom_cpus_done(void) -{ -} diff -puN arch/mips/sibyte/sb1250/smp.c~git-mips arch/mips/sibyte/sb1250/smp.c --- a/arch/mips/sibyte/sb1250/smp.c~git-mips +++ a/arch/mips/sibyte/sb1250/smp.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -55,7 +56,43 @@ void __cpuinit sb1250_smp_init(void) change_c0_status(ST0_IM, imask); } -void __cpuinit sb1250_smp_finish(void) +/* + * These are routines for dealing with the sb1250 smp capabilities + * independent of board/firmware + */ + +/* + * Simple enough; everything is set up, so just poke the appropriate mailbox + * register, and we should be set + */ +static void sb1250_send_ipi_single(int cpu, unsigned int action) +{ + __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); +} + +static inline void sb1250_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + sb1250_send_ipi_single(i, action); +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit sb1250_init_secondary(void) +{ + extern void sb1250_smp_init(void); + + sb1250_smp_init(); +} + +/* + * Do any tidying up before marking online and running the idle + * loop + */ +static void __cpuinit sb1250_smp_finish(void) { extern void sb1250_clockevent_init(void); @@ -64,19 +101,68 @@ void __cpuinit sb1250_smp_finish(void) } /* - * These are routines for dealing with the sb1250 smp capabilities - * independent of board/firmware + * Final cleanup after all secondaries booted */ +static void sb1250_cpus_done(void) +{ +} /* - * Simple enough; everything is set up, so just poke the appropriate mailbox - * register, and we should be set + * Setup the PC, SP, and GP of a secondary processor and start it + * running! */ -void core_send_ipi(int cpu, unsigned int action) +static void __cpuinit sb1250_boot_secondary(int cpu, struct task_struct *idle) { - __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); + int retval; + + retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, + __KSTK_TOS(idle), + (unsigned long)task_thread_info(idle), 0); + if (retval != 0) + printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); } +/* + * Use CFE to find out how many CPUs are available, setting up + * phys_cpu_present_map and the logical/physical mappings. + * XXXKW will the boot CPU ever not be physical 0? + * + * Common setup before any secondaries are started + */ +static void __init sb1250_smp_setup(void) +{ + int i, num; + + cpus_clear(phys_cpu_present_map); + cpu_set(0, phys_cpu_present_map); + __cpu_number_map[0] = 0; + __cpu_logical_map[0] = 0; + + for (i = 1, num = 0; i < NR_CPUS; i++) { + if (cfe_cpu_stop(i) == 0) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = ++num; + __cpu_logical_map[num] = i; + } + } + printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); +} + +static void __init sb1250_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops sb_smp_ops = { + .send_ipi_single = sb1250_send_ipi_single, + .send_ipi_mask = sb1250_send_ipi_mask, + .init_secondary = sb1250_init_secondary, + .smp_finish = sb1250_smp_finish, + .cpus_done = sb1250_cpus_done, + .boot_secondary = sb1250_boot_secondary, + .smp_setup = sb1250_smp_setup, + .prepare_cpus = sb1250_prepare_cpus, +}; + void sb1250_mailbox_interrupt(void) { int cpu = smp_processor_id(); diff -puN arch/mips/sni/Makefile~git-mips arch/mips/sni/Makefile --- a/arch/mips/sni/Makefile~git-mips +++ a/arch/mips/sni/Makefile @@ -3,6 +3,6 @@ # obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o -obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o +obj-$(CONFIG_EISA) += eisa.o EXTRA_CFLAGS += -Werror diff -puN arch/mips/sni/a20r.c~git-mips arch/mips/sni/a20r.c --- a/arch/mips/sni/a20r.c~git-mips +++ a/arch/mips/sni/a20r.c @@ -117,10 +117,19 @@ static struct resource sc26xx_rsrc[] = { } }; +static unsigned int sc26xx_data[2] = { + /* DTR | RTS | DSR | CTS | DCD | RI */ + (8 << 0) | (4 << 4) | (6 << 8) | (0 << 12) | (6 << 16) | (0 << 20), + (3 << 0) | (2 << 4) | (1 << 8) | (2 << 12) | (3 << 16) | (4 << 20) +}; + static struct platform_device sc26xx_pdev = { .name = "SC26xx", .num_resources = ARRAY_SIZE(sc26xx_rsrc), - .resource = sc26xx_rsrc + .resource = sc26xx_rsrc, + .dev = { + .platform_data = sc26xx_data, + } }; static u32 a20r_ack_hwint(void) @@ -231,9 +240,9 @@ static int __init snirm_a20r_setup_devin platform_device_register(&sc26xx_pdev); platform_device_register(&a20r_serial8250_device); platform_device_register(&a20r_ds1216_device); + sni_eisa_root_init(); break; } - return 0; } diff -puN /dev/null arch/mips/sni/eisa.c --- /dev/null +++ a/arch/mips/sni/eisa.c @@ -0,0 +1,50 @@ +/* + * Virtual EISA root driver. + * Acts as a placeholder if we don't have a proper EISA bridge. + * + * (C) 2003 Marc Zyngier + * modified for SNI usage by Thomas Bogendoerfer + * + * This code is released under the GPL version 2. + */ + +#include +#include +#include +#include + +/* The default EISA device parent (virtual root device). + * Now use a platform device, since that's the obvious choice. */ + +static struct platform_device eisa_root_dev = { + .name = "eisa", + .id = 0, +}; + +static struct eisa_root_device eisa_bus_root = { + .dev = &eisa_root_dev.dev, + .bus_base_addr = 0, + .res = &ioport_resource, + .slots = EISA_MAX_SLOTS, + .dma_mask = 0xffffffff, + .force_probe = 1, +}; + +int __init sni_eisa_root_init(void) +{ + int r; + + r = platform_device_register(&eisa_root_dev); + if (!r) + return r; + + eisa_root_dev.dev.driver_data = &eisa_bus_root; + + if (eisa_root_register(&eisa_bus_root)) { + /* A real bridge may have been registered before + * us. So quietly unregister. */ + platform_device_unregister(&eisa_root_dev); + return -1; + } + return 0; +} diff -puN arch/mips/sni/irq.c~git-mips arch/mips/sni/irq.c --- a/arch/mips/sni/irq.c~git-mips +++ a/arch/mips/sni/irq.c @@ -35,14 +35,14 @@ static irqreturn_t sni_isa_irq_handler(i if (unlikely(irq < 0)) return IRQ_NONE; - do_IRQ(irq); + generic_handle_irq(irq); return IRQ_HANDLED; } struct irqaction sni_isa_irq = { .handler = sni_isa_irq_handler, .name = "ISA", - .flags = IRQF_SHARED + .flags = IRQF_SHARED | IRQF_DISABLED }; /* diff -puN arch/mips/sni/pcit.c~git-mips arch/mips/sni/pcit.c --- a/arch/mips/sni/pcit.c~git-mips +++ a/arch/mips/sni/pcit.c @@ -76,6 +76,11 @@ static struct platform_device pcit_cmos_ .resource = pcit_cmos_rsrc }; +static struct platform_device pcit_pcspeaker_pdev = { + .name = "pcspkr", + .id = -1, +}; + static struct resource sni_io_resource = { .start = 0x00000000UL, .end = 0x03bfffffUL, @@ -277,11 +282,13 @@ static int __init snirm_pcit_setup_devin case SNI_BRD_PCI_TOWER: platform_device_register(&pcit_serial8250_device); platform_device_register(&pcit_cmos_device); + platform_device_register(&pcit_pcspeaker_pdev); break; case SNI_BRD_PCI_TOWER_CPLUS: platform_device_register(&pcit_cplus_serial8250_device); platform_device_register(&pcit_cmos_device); + platform_device_register(&pcit_pcspeaker_pdev); break; } return 0; diff -puN arch/mips/sni/rm200.c~git-mips arch/mips/sni/rm200.c --- a/arch/mips/sni/rm200.c~git-mips +++ a/arch/mips/sni/rm200.c @@ -5,30 +5,36 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) + * Copyright (C) 2006,2007 Thomas Bogendoerfer (tsbogend@alpha.franken.de) + * + * i8259 parts ripped out of arch/mips/kernel/i8259.c */ +#include #include #include #include #include +#include #include #include #include -#define PORT(_base,_irq) \ +#define RM200_I8259A_IRQ_BASE 32 + +#define MEMPORT(_base,_irq) \ { \ - .iobase = _base, \ + .mapbase = _base, \ .irq = _irq, \ .uartclk = 1843200, \ - .iotype = UPIO_PORT, \ - .flags = UPF_BOOT_AUTOCONF, \ + .iotype = UPIO_MEM, \ + .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP, \ } static struct plat_serial8250_port rm200_data[] = { - PORT(0x3f8, 4), - PORT(0x2f8, 3), + MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4), + MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3), { }, }; @@ -112,15 +118,311 @@ static int __init snirm_setup_devinit(vo platform_device_register(&rm200_ds1216_device); platform_device_register(&snirm_82596_rm200_pdev); platform_device_register(&snirm_53c710_rm200_pdev); + sni_eisa_root_init(); } return 0; } device_initcall(snirm_setup_devinit); +/* + * RM200 has an ISA and an EISA bus. The iSA bus is only used + * for onboard devices and also has twi i8259 PICs. Since these + * PICs are no accessible via inb/outb the following code uses + * readb/writeb to access them + */ + +DEFINE_SPINLOCK(sni_rm200_i8259A_lock); +#define PIC_CMD 0x00 +#define PIC_IMR 0x01 +#define PIC_ISR PIC_CMD +#define PIC_POLL PIC_ISR +#define PIC_OCW3 PIC_ISR + +/* i8259A PIC related value */ +#define PIC_CASCADE_IR 2 +#define MASTER_ICW4_DEFAULT 0x01 +#define SLAVE_ICW4_DEFAULT 0x01 + +/* + * This contains the irq mask for both 8259A irq controllers, + */ +static unsigned int rm200_cached_irq_mask = 0xffff; +static __iomem u8 *rm200_pic_master; +static __iomem u8 *rm200_pic_slave; + +#define cached_master_mask (rm200_cached_irq_mask) +#define cached_slave_mask (rm200_cached_irq_mask >> 8) + +static void sni_rm200_disable_8259A_irq(unsigned int irq) +{ + unsigned int mask; + unsigned long flags; + + irq -= RM200_I8259A_IRQ_BASE; + mask = 1 << irq; + spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); + rm200_cached_irq_mask |= mask; + if (irq & 8) + writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); + else + writeb(cached_master_mask, rm200_pic_master + PIC_IMR); + spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); +} + +static void sni_rm200_enable_8259A_irq(unsigned int irq) +{ + unsigned int mask; + unsigned long flags; + + irq -= RM200_I8259A_IRQ_BASE; + mask = ~(1 << irq); + spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); + rm200_cached_irq_mask &= mask; + if (irq & 8) + writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); + else + writeb(cached_master_mask, rm200_pic_master + PIC_IMR); + spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); +} + +static inline int sni_rm200_i8259A_irq_real(unsigned int irq) +{ + int value; + int irqmask = 1 << irq; + + if (irq < 8) { + writeb(0x0B, rm200_pic_master + PIC_CMD); + value = readb(rm200_pic_master + PIC_CMD) & irqmask; + writeb(0x0A, rm200_pic_master + PIC_CMD); + return value; + } + writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */ + value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8); + writeb(0x0A, rm200_pic_slave + PIC_CMD); + return value; +} + +/* + * Careful! The 8259A is a fragile beast, it pretty + * much _has_ to be done exactly like this (mask it + * first, _then_ send the EOI, and the order of EOI + * to the two 8259s is important! + */ +void sni_rm200_mask_and_ack_8259A(unsigned int irq) +{ + unsigned int irqmask; + unsigned long flags; + + irq -= RM200_I8259A_IRQ_BASE; + irqmask = 1 << irq; + spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); + /* + * Lightweight spurious IRQ detection. We do not want + * to overdo spurious IRQ handling - it's usually a sign + * of hardware problems, so we only do the checks we can + * do without slowing down good hardware unnecessarily. + * + * Note that IRQ7 and IRQ15 (the two spurious IRQs + * usually resulting from the 8259A-1|2 PICs) occur + * even if the IRQ is masked in the 8259A. Thus we + * can check spurious 8259A IRQs without doing the + * quite slow i8259A_irq_real() call for every IRQ. + * This does not cover 100% of spurious interrupts, + * but should be enough to warn the user that there + * is something bad going on ... + */ + if (rm200_cached_irq_mask & irqmask) + goto spurious_8259A_irq; + rm200_cached_irq_mask |= irqmask; + +handle_real_irq: + if (irq & 8) { + readb(rm200_pic_slave + PIC_IMR); + writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); + writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD); + writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD); + } else { + readb(rm200_pic_master + PIC_IMR); + writeb(cached_master_mask, rm200_pic_master + PIC_IMR); + writeb(0x60+irq, rm200_pic_master + PIC_CMD); + } + spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); + return; + +spurious_8259A_irq: + /* + * this is the slow path - should happen rarely. + */ + if (sni_rm200_i8259A_irq_real(irq)) + /* + * oops, the IRQ _is_ in service according to the + * 8259A - not spurious, go handle it. + */ + goto handle_real_irq; + + { + static int spurious_irq_mask; + /* + * At this point we can be sure the IRQ is spurious, + * lets ACK and report it. [once per IRQ] + */ + if (!(spurious_irq_mask & irqmask)) { + printk(KERN_DEBUG + "spurious RM200 8259A interrupt: IRQ%d.\n", irq); + spurious_irq_mask |= irqmask; + } + atomic_inc(&irq_err_count); + /* + * Theoretically we do not have to handle this IRQ, + * but in Linux this does not cause problems and is + * simpler for us. + */ + goto handle_real_irq; + } +} + +static struct irq_chip sni_rm200_i8259A_chip = { + .name = "RM200-XT-PIC", + .mask = sni_rm200_disable_8259A_irq, + .unmask = sni_rm200_enable_8259A_irq, + .mask_ack = sni_rm200_mask_and_ack_8259A, +}; + +/* + * Do the traditional i8259 interrupt polling thing. This is for the few + * cases where no better interrupt acknowledge method is available and we + * absolutely must touch the i8259. + */ +static inline int sni_rm200_i8259_irq(void) +{ + int irq; + + spin_lock(&sni_rm200_i8259A_lock); + + /* Perform an interrupt acknowledge cycle on controller 1. */ + writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */ + irq = readb(rm200_pic_master + PIC_CMD) & 7; + if (irq == PIC_CASCADE_IR) { + /* + * Interrupt is cascaded so perform interrupt + * acknowledge on controller 2. + */ + writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */ + irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8; + } + + if (unlikely(irq == 7)) { + /* + * This may be a spurious interrupt. + * + * Read the interrupt status register (ISR). If the most + * significant bit is not set then there is no valid + * interrupt. + */ + writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */ + if (~readb(rm200_pic_master + PIC_ISR) & 0x80) + irq = -1; + } + + spin_unlock(&sni_rm200_i8259A_lock); + + return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq; +} + +void sni_rm200_init_8259A(void) +{ + unsigned long flags; + + spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); + + writeb(0xff, rm200_pic_master + PIC_IMR); + writeb(0xff, rm200_pic_slave + PIC_IMR); + + writeb(0x11, rm200_pic_master + PIC_CMD); + writeb(0, rm200_pic_master + PIC_IMR); + writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR); + writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR); + writeb(0x11, rm200_pic_slave + PIC_CMD); + writeb(8, rm200_pic_slave + PIC_IMR); + writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR); + writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR); + udelay(100); /* wait for 8259A to initialize */ + + writeb(cached_master_mask, rm200_pic_master + PIC_IMR); + writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); + + spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); +} + +/* + * IRQ2 is cascade interrupt to second interrupt controller + */ +static struct irqaction sni_rm200_irq2 = { + no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL +}; + +static struct resource sni_rm200_pic1_resource = { + .name = "onboard ISA pic1", + .start = 0x16000020, + .end = 0x16000023, + .flags = IORESOURCE_BUSY +}; + +static struct resource sni_rm200_pic2_resource = { + .name = "onboard ISA pic2", + .start = 0x160000a0, + .end = 0x160000a3, + .flags = IORESOURCE_BUSY +}; + +/* ISA irq handler */ +static irqreturn_t sni_rm200_i8259A_irq_handler(int dummy, void *p) +{ + int irq; + + irq = sni_rm200_i8259_irq(); + if (unlikely(irq < 0)) + return IRQ_NONE; + + do_IRQ(irq); + return IRQ_HANDLED; +} + +struct irqaction sni_rm200_i8259A_irq = { + .handler = sni_rm200_i8259A_irq_handler, + .name = "onboard ISA", + .flags = IRQF_SHARED +}; + +void __init sni_rm200_i8259_irqs(void) +{ + int i; + + rm200_pic_master = ioremap_nocache(0x16000020, 4); + if (!rm200_pic_master) + return; + rm200_pic_slave = ioremap_nocache(0x160000a0, 4); + if (!rm200_pic_master) { + iounmap(rm200_pic_master); + return; + } + + insert_resource(&iomem_resource, &sni_rm200_pic1_resource); + insert_resource(&iomem_resource, &sni_rm200_pic2_resource); + + sni_rm200_init_8259A(); + + for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) + set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip, + handle_level_irq); + + setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); +} + -#define SNI_RM200_INT_STAT_REG 0xbc000000 -#define SNI_RM200_INT_ENA_REG 0xbc080000 +#define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000) +#define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000) #define SNI_RM200_INT_START 24 #define SNI_RM200_INT_END 28 @@ -181,17 +483,17 @@ void __init sni_rm200_irq_init(void) * (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f; + sni_rm200_i8259_irqs(); mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) set_irq_chip(i, &rm200_irq_type); sni_hwint = sni_rm200_hwint; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq); + setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); + setup_irq(SNI_RM200_INT_START + 1, &sni_isa_irq); } void __init sni_rm200_init(void) { - set_io_port_base(SNI_PORT_BASE + 0x02000000); - ioport_resource.end += 0x02000000; } diff -puN arch/mips/sni/setup.c~git-mips arch/mips/sni/setup.c --- a/arch/mips/sni/setup.c~git-mips +++ a/arch/mips/sni/setup.c @@ -19,11 +19,17 @@ #include #endif +#ifdef CONFIG_SNIPROM +#include +#endif + +#include #include #include #include unsigned int sni_brd_type; +EXPORT_SYMBOL(sni_brd_type); extern void sni_machine_restart(char *command); extern void sni_machine_power_off(void); @@ -47,20 +53,152 @@ static void __init sni_display_setup(voi #endif } +static void __init sni_console_setup(void) +{ +#ifndef CONFIG_ARC + char *ctype; + char *cdev; + char *baud; + int port; + static char options[8]; + + cdev = prom_getenv("console_dev"); + if (strncmp(cdev, "tty", 3) == 0) { + ctype = prom_getenv("console"); + switch (*ctype) { + default: + case 'l': + port = 0; + baud = prom_getenv("lbaud"); + break; + case 'r': + port = 1; + baud = prom_getenv("rbaud"); + break; + } + if (baud) + strcpy(options, baud); + if (strncmp(cdev, "tty552", 6) == 0) + add_preferred_console("ttyS", port, + baud ? options : NULL); + else + add_preferred_console("ttySC", port, + baud ? options : NULL); + } +#endif +} + +#ifdef DEBUG +static void __init sni_idprom_dump(void) +{ + int i; + + pr_debug("SNI IDProm dump:\n"); + for (i = 0; i < 256; i++) { + if (i%16 == 0) + pr_debug("%04x ", i); + + printk("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i)); + + if (i % 16 == 15) + printk("\n"); + } +} +#endif void __init plat_mem_setup(void) { + int cputype; + set_io_port_base(SNI_PORT_BASE); // ioport_resource.end = sni_io_resource.end; /* * Setup (E)ISA I/O memory access stuff */ - isa_slot_offset = 0xb0000000; + isa_slot_offset = CKSEG1ADDR(0xb0000000); #ifdef CONFIG_EISA EISA_bus = 1; #endif + sni_brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE; + cputype = *(unsigned char *)SNI_IDPROM_CPUTYPE; + switch (sni_brd_type) { + case SNI_BRD_TOWER_OASIC: + switch (cputype) { + case SNI_CPU_M8030: + system_type = "RM400-330"; + break; + case SNI_CPU_M8031: + system_type = "RM400-430"; + break; + case SNI_CPU_M8037: + system_type = "RM400-530"; + break; + case SNI_CPU_M8034: + system_type = "RM400-730"; + break; + default: + system_type = "RM400-xxx"; + break; + } + break; + case SNI_BRD_MINITOWER: + switch (cputype) { + case SNI_CPU_M8021: + case SNI_CPU_M8043: + system_type = "RM400-120"; + break; + case SNI_CPU_M8040: + system_type = "RM400-220"; + break; + case SNI_CPU_M8053: + system_type = "RM400-225"; + break; + case SNI_CPU_M8050: + system_type = "RM400-420"; + break; + default: + system_type = "RM400-xxx"; + break; + } + break; + case SNI_BRD_PCI_TOWER: + system_type = "RM400-Cxx"; + break; + case SNI_BRD_RM200: + system_type = "RM200-xxx"; + break; + case SNI_BRD_PCI_MTOWER: + system_type = "RM300-Cxx"; + break; + case SNI_BRD_PCI_DESKTOP: + switch (read_c0_prid() & 0xff00) { + case PRID_IMP_R4600: + case PRID_IMP_R4700: + system_type = "RM200-C20"; + break; + case PRID_IMP_R5000: + system_type = "RM200-C40"; + break; + default: + system_type = "RM200-Cxx"; + break; + } + break; + case SNI_BRD_PCI_TOWER_CPLUS: + system_type = "RM400-Exx"; + break; + case SNI_BRD_PCI_MTOWER_CPLUS: + system_type = "RM300-Exx"; + break; + } + pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, system_type); + +#ifdef DEBUG + sni_idprom_dump(); +#endif + switch (sni_brd_type) { case SNI_BRD_10: case SNI_BRD_10NEW: @@ -89,9 +227,10 @@ void __init plat_mem_setup(void) pm_power_off = sni_machine_power_off; sni_display_setup(); + sni_console_setup(); } -#if CONFIG_PCI +#ifdef CONFIG_PCI #include #include