GIT a76422b5f7b5290f829181ef4df217d4439d3afb git://www.linux-mips.org/pub/scm/upstream.git#for-akpm commit Author: Daniel Laird Date: Thu Mar 6 09:07:18 2008 +0000 [MIPS] Move arch/mips/philips to arch/mips/nxp Signed-off-by: daniel.j.laird commit c0948bec7f912352a13c93dfe140fdf8097e6e75 Author: Harvey Harrison Date: Tue Mar 4 17:17:16 2008 -0800 [MIPS] replace __inline with inline Signed-off-by: Harvey Harrison Signed-off-by: Ralf Baechle commit 8420a75b456fa1772542bdcecea735638c74c4fd Author: Chris Dearman Date: Fri Sep 21 14:50:08 2007 +0100 [MIPS] Add CoreFPGA5 support; distinguish between SOCit/ROCit Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle commit 408c2a226676943233320bcf3fd0b656323d9ea4 Author: Chris Dearman Date: Wed Oct 3 10:43:56 2007 +0100 [MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle commit 63051fa3a87abfa84bc2e61ca37e882f8d8405d7 Author: Chris Dearman Date: Wed Sep 19 00:58:24 2007 +0100 [MIPS] Allow setting of the cache attribute at run time. Slightly tacky, but there is a precedent in the sparc archirecture code. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle commit 5bc8fd2013a56a770386f1a1ada6a60b8b28e9f0 Author: Chris Dearman Date: Wed Sep 19 00:51:57 2007 +0100 [MIPS] Tidy up cache attributes Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle commit 47e570cbad0f6fa2513803676f01bdac4b4eefe2 Author: Chris Dearman Date: Wed Sep 19 00:46:32 2007 +0100 [MIPS] All MIPS32 processors support64-bit physical addresses. Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle commit d81a78a1e54541b7cee1266ad4ab65bb90495e4c Author: Chris Dearman Date: Fri Sep 14 21:21:58 2007 +0100 [MIPS] Remove TLB sanitation code It is not being used by Malta and shouldn't be needed for MIPSsim. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle commit 57fb6ac011c7cc44684425ddf1e65716a116b572 Author: Chris Dearman Date: Thu Sep 13 12:32:02 2007 +0100 [MIPS] Basic SPRAM support Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle commit a9346df10923802a19775ca08c44daaa9a2e530c Author: Thiemo Seufer Date: Mon Feb 18 19:32:49 2008 +0000 [MIPS] Reimplement clear_page/copy_page Fold the SB-1 specific implementation of clear_page/copy_page in the generic version, and rewrite that one in tlbex style. The immediate benefits: - It converts the compile-time workaround for SB-1 pass 1 prefetches to a more efficient run-time check. - It allows adjustment of loop unfolling, which helps to reduce the number of redundant cdex cache ops. - It fixes some esoteric cornercases (the cache line length calculations can go wrong, and support for 64k pages without prefetch instructions will overflow the addiu immediate). - Somewhat better guesses of "good" prefetch values. Signed-off-by: Thiemo Seufer Signed-off-by: Ralf Baechle arch/mips/Kconfig | 4 +- arch/mips/Kconfig.debug | 10 - arch/mips/Makefile | 12 +- arch/mips/configs/mipssim_defconfig | 1 - arch/mips/configs/pnx8550-jbs_defconfig | 1 - arch/mips/configs/pnx8550-stb810_defconfig | 1 - arch/mips/kernel/Makefile | 3 +- arch/mips/kernel/cpu-probe.c | 12 +- arch/mips/kernel/smp-mt.c | 47 -- arch/mips/kernel/smtc.c | 8 - arch/mips/kernel/spram.c | 221 ++++++++ arch/mips/kernel/traps.c | 13 +- arch/mips/math-emu/ieee754dp.h | 2 +- arch/mips/math-emu/ieee754sp.h | 2 +- arch/mips/mips-boards/generic/init.c | 16 +- arch/mips/mipssim/sim_setup.c | 6 - arch/mips/mm/Makefile | 37 +- arch/mips/mm/c-r4k.c | 39 ++- arch/mips/mm/init.c | 2 +- arch/mips/mm/page.c | 684 ++++++++++++++++++++++++ arch/mips/mm/pg-r4k.c | 534 ------------------ arch/mips/mm/pg-sb1.c | 302 ----------- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/uasm.c | 26 +- arch/mips/mm/uasm.h | 5 + arch/mips/nxp/pnx8550/common/Makefile | 29 + arch/mips/nxp/pnx8550/common/gdb_hook.c | 109 ++++ arch/mips/nxp/pnx8550/common/int.c | 238 ++++++++ arch/mips/nxp/pnx8550/common/pci.c | 133 +++++ arch/mips/nxp/pnx8550/common/platform.c | 132 +++++ arch/mips/nxp/pnx8550/common/proc.c | 112 ++++ arch/mips/nxp/pnx8550/common/prom.c | 129 +++++ arch/mips/nxp/pnx8550/common/reset.c | 49 ++ arch/mips/nxp/pnx8550/common/setup.c | 157 ++++++ arch/mips/nxp/pnx8550/common/time.c | 150 ++++++ arch/mips/nxp/pnx8550/jbs/Makefile | 4 + arch/mips/nxp/pnx8550/jbs/board_setup.c | 65 +++ arch/mips/nxp/pnx8550/jbs/init.c | 53 ++ arch/mips/nxp/pnx8550/jbs/irqmap.c | 35 ++ arch/mips/nxp/pnx8550/stb810/Makefile | 4 + arch/mips/nxp/pnx8550/stb810/board_setup.c | 49 ++ arch/mips/nxp/pnx8550/stb810/irqmap.c | 22 + arch/mips/nxp/pnx8550/stb810/prom_init.c | 46 ++ arch/mips/philips/pnx8550/common/Makefile | 29 - arch/mips/philips/pnx8550/common/gdb_hook.c | 109 ---- arch/mips/philips/pnx8550/common/int.c | 238 -------- arch/mips/philips/pnx8550/common/pci.c | 133 ----- arch/mips/philips/pnx8550/common/platform.c | 132 ----- arch/mips/philips/pnx8550/common/proc.c | 112 ---- arch/mips/philips/pnx8550/common/prom.c | 129 ----- arch/mips/philips/pnx8550/common/reset.c | 49 -- arch/mips/philips/pnx8550/common/setup.c | 157 ------ arch/mips/philips/pnx8550/common/time.c | 150 ------ arch/mips/philips/pnx8550/jbs/Makefile | 4 - arch/mips/philips/pnx8550/jbs/board_setup.c | 65 --- arch/mips/philips/pnx8550/jbs/init.c | 53 -- arch/mips/philips/pnx8550/jbs/irqmap.c | 36 -- arch/mips/philips/pnx8550/stb810/Makefile | 4 - arch/mips/philips/pnx8550/stb810/board_setup.c | 49 -- arch/mips/philips/pnx8550/stb810/irqmap.c | 23 - arch/mips/philips/pnx8550/stb810/prom_init.c | 46 -- include/asm-mips/cpu.h | 2 +- include/asm-mips/io.h | 2 +- include/asm-mips/mips-boards/generic.h | 1 + include/asm-mips/pgtable-32.h | 4 +- include/asm-mips/pgtable-bits.h | 91 ++-- include/asm-mips/pgtable.h | 57 ++- 67 files changed, 2624 insertions(+), 2557 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ade230d..b700da4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -309,12 +309,12 @@ config MACH_VR41XX select GENERIC_HARDIRQS_NO__DO_IRQ config PNX8550_JBS - bool "Philips PNX8550 based JBS board" + bool "NXP PNX8550 based JBS board" select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN config PNX8550_STB810 - bool "Philips PNX8550 based STB810 board" + bool "NXP PNX8550 based STB810 board" select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index fd7124c..f18cf92 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -73,14 +73,4 @@ config RUNTIME_DEBUG include/asm-mips/debug.h for debuging macros. If unsure, say N. -config MIPS_UNCACHED - bool "Run uncached" - depends on DEBUG_KERNEL && !SMP && !SGI_IP27 - help - If you say Y here there kernel will disable all CPU caches. This will - reduce the system's performance dramatically but can help finding - otherwise hard to track bugs. It can also useful if you're doing - hardware debugging with a logic analyzer and need to see all traffic - on the bus. - endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 3fb7f30..57c7ced 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -408,21 +408,21 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000 load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 # -# Common Philips PNX8550 +# Common NXP PNX8550 # -core-$(CONFIG_SOC_PNX8550) += arch/mips/philips/pnx8550/common/ +core-$(CONFIG_SOC_PNX8550) += arch/mips/nxp/pnx8550/common/ cflags-$(CONFIG_SOC_PNX8550) += -Iinclude/asm-mips/mach-pnx8550 # -# Philips PNX8550 JBS board +# NXP PNX8550 JBS board # -libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/ +libs-$(CONFIG_PNX8550_JBS) += arch/mips/nxp/pnx8550/jbs/ #cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 -# Philips PNX8550 STB810 board +# NXP PNX8550 STB810 board # -libs-$(CONFIG_PNX8550_STB810) += arch/mips/philips/pnx8550/stb810/ +libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/ load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 # NEC EMMA2RH boards diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 6db0bda..4f6bce9 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -641,7 +641,6 @@ CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set -# CONFIG_MIPS_UNCACHED is not set # # Security options diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 518a608..780c7fc 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -1223,7 +1223,6 @@ CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" # CONFIG_KGDB is not set CONFIG_SYS_SUPPORTS_KGDB=y # CONFIG_RUNTIME_DEBUG is not set -# CONFIG_MIPS_UNCACHED is not set # # Security options diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index 68351eb..267f21e 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -1213,7 +1213,6 @@ CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" # CONFIG_KGDB is not set CONFIG_SYS_SUPPORTS_KGDB=y # CONFIG_RUNTIME_DEBUG is not set -# CONFIG_MIPS_UNCACHED is not set # # Security options diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index ffa0836..1d859ca 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -6,7 +6,8 @@ extra-y := head.o init_task.o vmlinux.lds obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ ptrace.o reset.o semaphore.o setup.o signal.o syscall.o \ - time.o topology.o traps.o unaligned.o + time.o topology.o traps.o unaligned.o \ + spram.o obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5861a43..b56fb6f 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -675,6 +675,8 @@ static void __init decode_configs(struct cpuinfo_mips *c) return; } +extern void spram_config(void); + static inline void cpu_probe_mips(struct cpuinfo_mips *c) { decode_configs(c); @@ -712,6 +714,8 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) c->cputype = CPU_74K; break; } + + spram_config(); } static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) @@ -778,7 +782,7 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) } } -static inline void cpu_probe_philips(struct cpuinfo_mips *c) +static inline void cpu_probe_nxp(struct cpuinfo_mips *c) { decode_configs(c); switch (c->processor_id & 0xff00) { @@ -787,7 +791,7 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c) c->isa_level = MIPS_CPU_ISA_M32R1; break; default: - panic("Unknown Philips Core!"); /* REVISIT: die? */ + panic("Unknown NXP Core!"); /* REVISIT: die? */ break; } } @@ -925,8 +929,8 @@ __init void cpu_probe(void) case PRID_COMP_SANDCRAFT: cpu_probe_sandcraft(c); break; - case PRID_COMP_PHILIPS: - cpu_probe_philips(c); + case PRID_COMP_NXP: + cpu_probe_nxp(c); break; default: c->cputype = CPU_UNKNOWN; diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 89e6f6a..e9c393a 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -58,53 +58,6 @@ static void dump_mtregisters(int vpe, int tc) } #endif -void __init sanitize_tlb_entries(void) -{ - int i, tlbsiz; - unsigned long mvpconf0, ncpu; - - if (!cpu_has_mipsmt) - return; - - /* Enable VPC */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - back_to_back_c0_hazard(); - - /* Disable TLB sharing */ - clear_c0_mvpcontrol(MVPCONTROL_STLB); - - mvpconf0 = read_c0_mvpconf0(); - - printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0, - (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT, - (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT); - - tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT; - ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; - - printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu); - - if (tlbsiz > 0) { - /* share them out across the vpe's */ - tlbsiz /= ncpu; - - printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz); - - for (i = 0; i < ncpu; i++) { - settc(i); - - if (i == 0) - write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25)); - else - write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) | - (tlbsiz << 25)); - } - } - - clear_c0_mvpcontrol(MVPCONTROL_VPC); -} - static void ipi_resched_dispatch(void) { do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index b42e71c..4705b3c 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -174,14 +174,6 @@ static int clock_hang_reported[NR_CPUS]; #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ -/* Initialize shared TLB - the should probably migrate to smtc_setup_cpus() */ - -void __init sanitize_tlb_entries(void) -{ - printk("Deprecated sanitize_tlb_entries() invoked\n"); -} - - /* * Configure shared TLB - VPC configuration bit must be set by caller */ diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c new file mode 100644 index 0000000..31bb952 --- /dev/null +++ b/arch/mips/kernel/spram.c @@ -0,0 +1,221 @@ +/* + * MIPS SPRAM support + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Copyright (C) 2007, 2008 MIPS Technologies, Inc. + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* + * These definitions are correct for the 24K/34K/74K SPRAM sample + * implementation. The 4KS interpreted the tags differently... + */ +#define SPRAM_TAG0_ENABLE 0x00000080 +#define SPRAM_TAG0_PA_MASK 0xfffff000 +#define SPRAM_TAG1_SIZE_MASK 0xfffff000 + +#define SPRAM_TAG_STRIDE 8 + +#define ERRCTL_SPRAM (1 << 28) + +/* errctl access */ +#define read_c0_errctl(x) read_c0_ecc(x) +#define write_c0_errctl(x) write_c0_ecc(x) + +/* + * Different semantics to the set_c0_* function built by __BUILD_SET_C0 + */ +static __init unsigned int bis_c0_errctl(unsigned int set) +{ + unsigned int res; + res = read_c0_errctl(); + write_c0_errctl(res | set); + return res; +} + +static __init void ispram_store_tag(unsigned int offset, unsigned int data) +{ + unsigned int errctl; + + /* enable SPRAM tag access */ + errctl = bis_c0_errctl(ERRCTL_SPRAM); + ehb(); + + write_c0_taglo(data); + ehb(); + + cache_op(Index_Store_Tag_I, CKSEG0|offset); + ehb(); + + write_c0_errctl(errctl); + ehb(); +} + + +static __init unsigned int ispram_load_tag(unsigned int offset) +{ + unsigned int data; + unsigned int errctl; + + /* enable SPRAM tag access */ + errctl = bis_c0_errctl(ERRCTL_SPRAM); + ehb(); + cache_op(Index_Load_Tag_I, CKSEG0 | offset); + ehb(); + data = read_c0_taglo(); + ehb(); + write_c0_errctl(errctl); + ehb(); + + return data; +} + +static __init void dspram_store_tag(unsigned int offset, unsigned int data) +{ + unsigned int errctl; + + /* enable SPRAM tag access */ + errctl = bis_c0_errctl(ERRCTL_SPRAM); + ehb(); + write_c0_dtaglo(data); + ehb(); + cache_op(Index_Store_Tag_D, CKSEG0 | offset); + ehb(); + write_c0_errctl(errctl); + ehb(); +} + + +static __init unsigned int dspram_load_tag(unsigned int offset) +{ + unsigned int data; + unsigned int errctl; + + errctl = bis_c0_errctl(ERRCTL_SPRAM); + ehb(); + cache_op(Index_Load_Tag_D, CKSEG0 | offset); + ehb(); + data = read_c0_dtaglo(); + ehb(); + write_c0_errctl(errctl); + ehb(); + + return data; +} + +static __init void probe_spram(char *type, + unsigned int base, + unsigned int (*read)(unsigned int), + void (*write)(unsigned int, unsigned int)) +{ + unsigned int firstsize = 0, lastsize = 0; + unsigned int firstpa = 0, lastpa = 0, pa = 0; + unsigned int offset = 0; + unsigned int size, tag0, tag1; + unsigned int enabled; + int i; + + /* + * The limit is arbitrary but avoids the loop running away if + * the SPRAM tags are implemented differently + */ + + for (i = 0; i < 8; i++) { + tag0 = read(offset); + tag1 = read(offset+SPRAM_TAG_STRIDE); + pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n", + type, i, tag0, tag1); + + size = tag1 & SPRAM_TAG1_SIZE_MASK; + + if (size == 0) + break; + + if (i != 0) { + /* tags may repeat... */ + if ((pa == firstpa && size == firstsize) || + (pa == lastpa && size == lastsize)) + break; + } + + /* Align base with size */ + base = (base + size - 1) & ~(size-1); + + /* reprogram the base address base address and enable */ + tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE; + write(offset, tag0); + + base += size; + + /* reread the tag */ + tag0 = read(offset); + pa = tag0 & SPRAM_TAG0_PA_MASK; + enabled = tag0 & SPRAM_TAG0_ENABLE; + + if (i == 0) { + firstpa = pa; + firstsize = size; + } + + lastpa = pa; + lastsize = size; + + if (strcmp(type, "DSPRAM") == 0) { + unsigned int *vp = (unsigned int *)(CKSEG1 | pa); + unsigned int v; +#define TDAT 0x5a5aa5a5 + vp[0] = TDAT; + vp[1] = ~TDAT; + + mb(); + + v = vp[0]; + if (v != TDAT) + printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n", + vp, TDAT, v); + v = vp[1]; + if (v != ~TDAT) + printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n", + vp+1, ~TDAT, v); + } + + pr_info("%s%d: PA=%08x,Size=%08x%s\n", + type, i, pa, size, enabled ? ",enabled" : ""); + offset += 2 * SPRAM_TAG_STRIDE; + } +} + +__init void spram_config(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config0; + + switch (c->cputype) { + case CPU_24K: + case CPU_34K: + case CPU_74K: + config0 = read_c0_config(); + /* FIXME: addresses are Malta specific */ + if (config0 & (1<<24)) { + probe_spram("ISPRAM", 0x1c000000, + &ispram_load_tag, &ispram_store_tag); + } + if (config0 & (1<<23)) + probe_spram("DSPRAM", 0x1c100000, + &dspram_load_tag, &dspram_store_tag); + } +} diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index fcae667..23a4232 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1287,6 +1287,17 @@ int cp0_compare_irq; int cp0_perfcount_irq; EXPORT_SYMBOL_GPL(cp0_perfcount_irq); +static int __initdata noulri; + +static int __init ulri_disable(char *s) +{ + pr_info("Disabling ulri\n"); + noulri = 1; + + return 1; +} +__setup("noulri", ulri_disable); + void __init per_cpu_trap_init(void) { unsigned int cpu = smp_processor_id(); @@ -1327,7 +1338,7 @@ void __init per_cpu_trap_init(void) if (cpu_has_mips_r2) { unsigned int enable = 0x0000000f; - if (cpu_has_userlocal) + if (!noulri && cpu_has_userlocal) enable |= (1 << 29); write_c0_hwrena(enable); diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h index 8977eb5..7627865 100644 --- a/arch/mips/math-emu/ieee754dp.h +++ b/arch/mips/math-emu/ieee754dp.h @@ -46,7 +46,7 @@ #define DPDNORMX DPDNORMx(xm, xe) #define DPDNORMY DPDNORMx(ym, ye) -static __inline ieee754dp builddp(int s, int bx, u64 m) +static inline ieee754dp builddp(int s, int bx, u64 m) { ieee754dp r; diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h index 9917c1e..d9e3586 100644 --- a/arch/mips/math-emu/ieee754sp.h +++ b/arch/mips/math-emu/ieee754sp.h @@ -51,7 +51,7 @@ #define SPDNORMX SPDNORMx(xm, xe) #define SPDNORMY SPDNORMx(ym, ye) -static __inline ieee754sp buildsp(int s, int bx, unsigned m) +static inline ieee754sp buildsp(int s, int bx, unsigned m) { ieee754sp r; diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 1695dca..07671fb 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -295,15 +295,21 @@ void __init prom_init(void) break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_24K: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: + /* + * SOCit/ROCit support is essentially identical + * but make an attempt to distinguish them + */ mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; break; + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_FPGA4: + case MIPS_REVISION_CORID_CORE_FPGA5: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: default: - mips_display_message("CC Error"); - while (1); /* We die here... */ + /* See above */ + mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; + break; } } diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c index d49fe73..7c7148e 100644 --- a/arch/mips/mipssim/sim_setup.c +++ b/arch/mips/mipssim/sim_setup.c @@ -39,9 +39,6 @@ static void __init serial_init(void); unsigned int _isbonito = 0; -extern void __init sanitize_tlb_entries(void); - - const char *get_system_type(void) { return "MIPSsim"; @@ -55,9 +52,6 @@ void __init plat_mem_setup(void) pr_info("Linux started...\n"); -#ifdef CONFIG_MIPS_MT_SMP - sanitize_tlb_entries(); -#endif } extern struct plat_smp_ops ssmtc_smp_ops; diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index c6f832e..4873102 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -4,30 +4,29 @@ obj-y += cache.o dma-default.o extable.o fault.o \ init.o pgtable.o tlbex.o tlbex-fault.o \ - uasm.o + uasm.o page.o obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o -obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o -obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o -obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o pg-sb1.o \ - tlb-r4k.o -obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o -obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o +obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o +obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o +obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o +obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o +obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 2c4f7e1..0aa27cc 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -1206,9 +1207,45 @@ void au1x00_fixup_config_od(void) } } +static int __initdata cca = -1; +unsigned long _page_cachable_default; +EXPORT_SYMBOL_GPL(_page_cachable_default); + +static int __init cca_setup(char *str) +{ + get_option(&str, &cca); + + return 1; +} + +__setup("cca=", cca_setup); + static void __init coherency_setup(void) { - change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); + if (cca < 0 || cca > 7) + cca = read_c0_config() & CONF_CM_CMASK; + _page_cachable_default = cca << _CACHE_SHIFT; + + pr_debug("Using cache attribute %d\n", cca); + + protection_map[0] = PAGE_NONE; + protection_map[1] = PAGE_READONLY; + protection_map[2] = PAGE_COPY; + protection_map[3] = PAGE_COPY; + protection_map[4] = PAGE_READONLY; + protection_map[5] = PAGE_READONLY; + protection_map[6] = PAGE_COPY; + protection_map[7] = PAGE_COPY; + protection_map[8] = PAGE_NONE; + protection_map[9] = PAGE_READONLY; + protection_map[10] = PAGE_SHARED; + protection_map[11] = PAGE_SHARED; + protection_map[12] = PAGE_READONLY; + protection_map[13] = PAGE_READONLY; + protection_map[14] = PAGE_SHARED; + protection_map[15] = PAGE_SHARED; + + change_c0_config(CONF_CM_CMASK, cca); /* * c0_status.cu=0 specifies that updates by the sc instruction use diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index c7aed13..235833a 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -142,7 +142,7 @@ void *kmap_coherent(struct page *page, unsigned long addr) #endif vaddr = __fix_to_virt(FIX_CMAP_END - idx); pte = mk_pte(page, PAGE_KERNEL); -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) entrylo = pte.pte_high; #else entrylo = pte_val(pte) >> 6; diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c new file mode 100644 index 0000000..8525fb3 --- /dev/null +++ b/arch/mips/mm/page.c @@ -0,0 +1,684 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2007 Maciej W. Rozycki + * Copyright (C) 2008 Thiemo Seufer + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SIBYTE_DMA_PAGEOPS +#include +#include +#include +#endif + +#include "uasm.h" + +/* Registers used in the assembled routines. */ +#define ZERO 0 +#define AT 2 +#define A0 4 +#define A1 5 +#define A2 6 +#define T0 8 +#define T1 9 +#define T2 10 +#define T3 11 +#define T9 25 +#define RA 31 + +/* Handle labels (which must be positive integers). */ +enum label_id { + label_clear_nopref = 1, + label_clear_pref, + label_copy_nopref, + label_copy_pref_both, + label_copy_pref_store, +}; + +UASM_L_LA(_clear_nopref) +UASM_L_LA(_clear_pref) +UASM_L_LA(_copy_nopref) +UASM_L_LA(_copy_pref_both) +UASM_L_LA(_copy_pref_store) + +/* We need one branch and therefore one relocation per target label. */ +static struct uasm_label __initdata labels[5]; +static struct uasm_reloc __initdata relocs[5]; + +#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) +#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) + +/* + * Maximum sizes: + * + * R4000 128 bytes S-cache: 0x058 bytes + * R4600 v1.7: 0x05c bytes + * R4600 v2.0: 0x060 bytes + * With prefetching, 16 word strides 0x120 bytes + */ + +static u32 clear_page_array[0x120 / 4]; + +#ifdef CONFIG_SIBYTE_DMA_PAGEOPS +void clear_page_cpu(void *page) __attribute__((alias("clear_page_array"))); +#else +void clear_page(void *page) __attribute__((alias("clear_page_array"))); +#endif + +EXPORT_SYMBOL(clear_page); + +/* + * Maximum sizes: + * + * R4000 128 bytes S-cache: 0x11c bytes + * R4600 v1.7: 0x080 bytes + * R4600 v2.0: 0x07c bytes + * With prefetching, 16 word strides 0x540 bytes + */ +static u32 copy_page_array[0x540 / 4]; + +#ifdef CONFIG_SIBYTE_DMA_PAGEOPS +void +copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array"))); +#else +void copy_page(void *to, void *from) __attribute__((alias("copy_page_array"))); +#endif + +EXPORT_SYMBOL(copy_page); + + +static int pref_bias_clear_store __initdata; +static int pref_bias_copy_load __initdata; +static int pref_bias_copy_store __initdata; + +static u32 pref_src_mode __initdata; +static u32 pref_dst_mode __initdata; + +static int clear_word_size __initdata; +static int copy_word_size __initdata; + +static int half_clear_loop_size __initdata; +static int half_copy_loop_size __initdata; + +static int cache_line_size __initdata; +#define cache_line_mask() (cache_line_size - 1) + +static inline void __init +pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) +{ + if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) { + if (off > 0x7fff) { + uasm_i_lui(buf, T9, uasm_rel_hi(off)); + uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off)); + } else + uasm_i_addiu(buf, T9, ZERO, off); + uasm_i_daddu(buf, reg1, reg2, T9); + } else { + if (off > 0x7fff) { + uasm_i_lui(buf, T9, uasm_rel_hi(off)); + uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off)); + UASM_i_ADDU(buf, reg1, reg2, T9); + } else + UASM_i_ADDIU(buf, reg1, reg2, off); + } +} + +static void __init set_prefetch_parameters(void) +{ + if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) + clear_word_size = 8; + else + clear_word_size = 4; + + if (cpu_has_64bit_gp_regs) + copy_word_size = 8; + else + copy_word_size = 4; + + /* + * The pref's used here are using "streaming" hints, which cause the + * copied data to be kicked out of the cache sooner. A page copy often + * ends up copying a lot more data than is commonly used, so this seems + * to make sense in terms of reducing cache pollution, but I've no real + * performance data to back this up. + */ + if (cpu_has_prefetch) { + /* + * XXX: Most prefetch bias values in here are based on + * guesswork. + */ + cache_line_size = cpu_dcache_line_size(); + switch (current_cpu_type()) { + case CPU_TX49XX: + /* TX49 supports only Pref_Load */ + pref_bias_copy_load = 256; + break; + + case CPU_RM9000: + /* + * As a workaround for erratum G105 which make the + * PrepareForStore hint unusable we fall back to + * StoreRetained on the RM9000. Once it is known which + * versions of the RM9000 we'll be able to condition- + * alize this. + */ + + case CPU_R10000: + case CPU_R12000: + case CPU_R14000: + /* + * Those values have been experimentally tuned for an + * Origin 200. + */ + pref_bias_clear_store = 512; + pref_bias_copy_load = 256; + pref_bias_copy_store = 256; + pref_src_mode = Pref_LoadStreamed; + pref_dst_mode = Pref_StoreStreamed; + break; + + case CPU_SB1: + case CPU_SB1A: + pref_bias_clear_store = 128; + pref_bias_copy_load = 128; + pref_bias_copy_store = 128; + /* + * SB1 pass1 Pref_LoadStreamed/Pref_StoreStreamed + * hints are broken. + */ + if (current_cpu_type() == CPU_SB1 && + (current_cpu_data.processor_id & 0xff) < 0x02) { + pref_src_mode = Pref_Load; + pref_dst_mode = Pref_Store; + } else { + pref_src_mode = Pref_LoadStreamed; + pref_dst_mode = Pref_StoreStreamed; + } + break; + + default: + pref_bias_clear_store = 128; + pref_bias_copy_load = 256; + pref_bias_copy_store = 128; + pref_src_mode = Pref_LoadStreamed; + pref_dst_mode = Pref_PrepareForStore; + break; + } + } else { + if (cpu_has_cache_cdex_s) + cache_line_size = cpu_scache_line_size(); + else if (cpu_has_cache_cdex_p) + cache_line_size = cpu_dcache_line_size(); + } + /* + * Too much unrolling will overflow the available space in + * clear_space_array / copy_page_array. 8 words sounds generous, + * but a R4000 with 128 byte L2 line length can exceed even that. + */ + half_clear_loop_size = min(8 * clear_word_size, + max(cache_line_size >> 1, + 4 * clear_word_size)); + half_copy_loop_size = min(8 * copy_word_size, + max(cache_line_size >> 1, + 4 * copy_word_size)); +} + +static void __init build_clear_store(u32 **buf, int off) +{ + if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) { + uasm_i_sd(buf, ZERO, off, A0); + } else { + uasm_i_sw(buf, ZERO, off, A0); + } +} + +static inline void __init build_clear_pref(u32 **buf, int off) +{ + if (off & cache_line_mask()) + return; + + if (pref_bias_clear_store) { + uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off, + A0); + } else if (cpu_has_cache_cdex_s) { + uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); + } else if (cpu_has_cache_cdex_p) { + if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + } + + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) + uasm_i_lw(buf, ZERO, ZERO, AT); + + uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); + } +} + +void __init build_clear_page(void) +{ + int off; + u32 *buf = (u32 *)&clear_page_array; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + int i; + + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + set_prefetch_parameters(); + + /* + * This algorithm makes the following assumptions: + * - The prefetch bias is a multiple of 2 words. + * - The prefetch bias is less than one page. + */ + BUG_ON(pref_bias_clear_store % (2 * clear_word_size)); + BUG_ON(PAGE_SIZE < pref_bias_clear_store); + + off = PAGE_SIZE - pref_bias_clear_store; + if (off > 0xffff) + pg_addiu(&buf, A2, A0, off); + else + uasm_i_ori(&buf, A2, A0, off); + + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) + uasm_i_lui(&buf, AT, 0xa000); + + off = min(8, pref_bias_clear_store / cache_line_size) * + cache_line_size; + while (off) { + build_clear_pref(&buf, -off); + off -= cache_line_size; + } + uasm_l_clear_pref(&l, buf); + do { + build_clear_pref(&buf, off); + build_clear_store(&buf, off); + off += clear_word_size; + } while (off < half_clear_loop_size); + pg_addiu(&buf, A0, A0, 2 * off); + off = -off; + do { + build_clear_pref(&buf, off); + if (off == -clear_word_size) + uasm_il_bne(&buf, &r, A0, A2, label_clear_pref); + build_clear_store(&buf, off); + off += clear_word_size; + } while (off < 0); + + if (pref_bias_clear_store) { + pg_addiu(&buf, A2, A0, pref_bias_clear_store); + uasm_l_clear_nopref(&l, buf); + off = 0; + do { + build_clear_store(&buf, off); + off += clear_word_size; + } while (off < half_clear_loop_size); + pg_addiu(&buf, A0, A0, 2 * off); + off = -off; + do { + if (off == -clear_word_size) + uasm_il_bne(&buf, &r, A0, A2, + label_clear_nopref); + build_clear_store(&buf, off); + off += clear_word_size; + } while (off < 0); + } + + uasm_i_jr(&buf, RA); + uasm_i_nop(&buf); + + BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array)); + + uasm_resolve_relocs(relocs, labels); + + pr_debug("Synthesized clear page handler (%u instructions).\n", + (u32)(buf - clear_page_array)); + + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (buf - clear_page_array); i++) + pr_debug("\t.word 0x%08x\n", clear_page_array[i]); + pr_debug("\t.set pop\n"); +} + +static void __init build_copy_load(u32 **buf, int reg, int off) +{ + if (cpu_has_64bit_gp_regs) { + uasm_i_ld(buf, reg, off, A1); + } else { + uasm_i_lw(buf, reg, off, A1); + } +} + +static void __init build_copy_store(u32 **buf, int reg, int off) +{ + if (cpu_has_64bit_gp_regs) { + uasm_i_sd(buf, reg, off, A0); + } else { + uasm_i_sw(buf, reg, off, A0); + } +} + +static inline void build_copy_load_pref(u32 **buf, int off) +{ + if (off & cache_line_mask()) + return; + + if (pref_bias_copy_load) + uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1); +} + +static inline void build_copy_store_pref(u32 **buf, int off) +{ + if (off & cache_line_mask()) + return; + + if (pref_bias_copy_store) { + uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off, + A0); + } else if (cpu_has_cache_cdex_s) { + uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); + } else if (cpu_has_cache_cdex_p) { + if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + } + + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) + uasm_i_lw(buf, ZERO, ZERO, AT); + + uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); + } +} + +void __init build_copy_page(void) +{ + int off; + u32 *buf = (u32 *)©_page_array; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + int i; + + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + set_prefetch_parameters(); + + /* + * This algorithm makes the following assumptions: + * - All prefetch biases are multiples of 8 words. + * - The prefetch biases are less than one page. + * - The store prefetch bias isn't greater than the load + * prefetch bias. + */ + BUG_ON(pref_bias_copy_load % (8 * copy_word_size)); + BUG_ON(pref_bias_copy_store % (8 * copy_word_size)); + BUG_ON(PAGE_SIZE < pref_bias_copy_load); + BUG_ON(pref_bias_copy_store > pref_bias_copy_load); + + off = PAGE_SIZE - pref_bias_copy_load; + if (off > 0xffff) + pg_addiu(&buf, A2, A0, off); + else + uasm_i_ori(&buf, A2, A0, off); + + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) + uasm_i_lui(&buf, AT, 0xa000); + + off = min(8, pref_bias_copy_load / cache_line_size) * cache_line_size; + while (off) { + build_copy_load_pref(&buf, -off); + off -= cache_line_size; + } + off = min(8, pref_bias_copy_store / cache_line_size) * cache_line_size; + while (off) { + build_copy_store_pref(&buf, -off); + off -= cache_line_size; + } + uasm_l_copy_pref_both(&l, buf); + do { + build_copy_load_pref(&buf, off); + build_copy_load(&buf, T0, off); + build_copy_load_pref(&buf, off + copy_word_size); + build_copy_load(&buf, T1, off + copy_word_size); + build_copy_load_pref(&buf, off + 2 * copy_word_size); + build_copy_load(&buf, T2, off + 2 * copy_word_size); + build_copy_load_pref(&buf, off + 3 * copy_word_size); + build_copy_load(&buf, T3, off + 3 * copy_word_size); + build_copy_store_pref(&buf, off); + build_copy_store(&buf, T0, off); + build_copy_store_pref(&buf, off + copy_word_size); + build_copy_store(&buf, T1, off + copy_word_size); + build_copy_store_pref(&buf, off + 2 * copy_word_size); + build_copy_store(&buf, T2, off + 2 * copy_word_size); + build_copy_store_pref(&buf, off + 3 * copy_word_size); + build_copy_store(&buf, T3, off + 3 * copy_word_size); + off += 4 * copy_word_size; + } while (off < half_copy_loop_size); + pg_addiu(&buf, A1, A1, 2 * off); + pg_addiu(&buf, A0, A0, 2 * off); + off = -off; + do { + build_copy_load_pref(&buf, off); + build_copy_load(&buf, T0, off); + build_copy_load_pref(&buf, off + copy_word_size); + build_copy_load(&buf, T1, off + copy_word_size); + build_copy_load_pref(&buf, off + 2 * copy_word_size); + build_copy_load(&buf, T2, off + 2 * copy_word_size); + build_copy_load_pref(&buf, off + 3 * copy_word_size); + build_copy_load(&buf, T3, off + 3 * copy_word_size); + build_copy_store_pref(&buf, off); + build_copy_store(&buf, T0, off); + build_copy_store_pref(&buf, off + copy_word_size); + build_copy_store(&buf, T1, off + copy_word_size); + build_copy_store_pref(&buf, off + 2 * copy_word_size); + build_copy_store(&buf, T2, off + 2 * copy_word_size); + build_copy_store_pref(&buf, off + 3 * copy_word_size); + if (off == -(4 * copy_word_size)) + uasm_il_bne(&buf, &r, A2, A0, label_copy_pref_both); + build_copy_store(&buf, T3, off + 3 * copy_word_size); + off += 4 * copy_word_size; + } while (off < 0); + + if (pref_bias_copy_load - pref_bias_copy_store) { + pg_addiu(&buf, A2, A0, + pref_bias_copy_load - pref_bias_copy_store); + uasm_l_copy_pref_store(&l, buf); + off = 0; + do { + build_copy_load(&buf, T0, off); + build_copy_load(&buf, T1, off + copy_word_size); + build_copy_load(&buf, T2, off + 2 * copy_word_size); + build_copy_load(&buf, T3, off + 3 * copy_word_size); + build_copy_store_pref(&buf, off); + build_copy_store(&buf, T0, off); + build_copy_store_pref(&buf, off + copy_word_size); + build_copy_store(&buf, T1, off + copy_word_size); + build_copy_store_pref(&buf, off + 2 * copy_word_size); + build_copy_store(&buf, T2, off + 2 * copy_word_size); + build_copy_store_pref(&buf, off + 3 * copy_word_size); + build_copy_store(&buf, T3, off + 3 * copy_word_size); + off += 4 * copy_word_size; + } while (off < half_copy_loop_size); + pg_addiu(&buf, A1, A1, 2 * off); + pg_addiu(&buf, A0, A0, 2 * off); + off = -off; + do { + build_copy_load(&buf, T0, off); + build_copy_load(&buf, T1, off + copy_word_size); + build_copy_load(&buf, T2, off + 2 * copy_word_size); + build_copy_load(&buf, T3, off + 3 * copy_word_size); + build_copy_store_pref(&buf, off); + build_copy_store(&buf, T0, off); + build_copy_store_pref(&buf, off + copy_word_size); + build_copy_store(&buf, T1, off + copy_word_size); + build_copy_store_pref(&buf, off + 2 * copy_word_size); + build_copy_store(&buf, T2, off + 2 * copy_word_size); + build_copy_store_pref(&buf, off + 3 * copy_word_size); + if (off == -(4 * copy_word_size)) + uasm_il_bne(&buf, &r, A2, A0, + label_copy_pref_store); + build_copy_store(&buf, T3, off + 3 * copy_word_size); + off += 4 * copy_word_size; + } while (off < 0); + } + + if (pref_bias_copy_store) { + pg_addiu(&buf, A2, A0, pref_bias_copy_store); + uasm_l_copy_nopref(&l, buf); + off = 0; + do { + build_copy_load(&buf, T0, off); + build_copy_load(&buf, T1, off + copy_word_size); + build_copy_load(&buf, T2, off + 2 * copy_word_size); + build_copy_load(&buf, T3, off + 3 * copy_word_size); + build_copy_store(&buf, T0, off); + build_copy_store(&buf, T1, off + copy_word_size); + build_copy_store(&buf, T2, off + 2 * copy_word_size); + build_copy_store(&buf, T3, off + 3 * copy_word_size); + off += 4 * copy_word_size; + } while (off < half_copy_loop_size); + pg_addiu(&buf, A1, A1, 2 * off); + pg_addiu(&buf, A0, A0, 2 * off); + off = -off; + do { + build_copy_load(&buf, T0, off); + build_copy_load(&buf, T1, off + copy_word_size); + build_copy_load(&buf, T2, off + 2 * copy_word_size); + build_copy_load(&buf, T3, off + 3 * copy_word_size); + build_copy_store(&buf, T0, off); + build_copy_store(&buf, T1, off + copy_word_size); + build_copy_store(&buf, T2, off + 2 * copy_word_size); + if (off == -(4 * copy_word_size)) + uasm_il_bne(&buf, &r, A2, A0, + label_copy_nopref); + build_copy_store(&buf, T3, off + 3 * copy_word_size); + off += 4 * copy_word_size; + } while (off < 0); + } + + uasm_i_jr(&buf, RA); + uasm_i_nop(&buf); + + BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array)); + + uasm_resolve_relocs(relocs, labels); + + pr_debug("Synthesized copy page handler (%u instructions).\n", + (u32)(buf - copy_page_array)); + + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (buf - copy_page_array); i++) + pr_debug("\t.word 0x%08x\n", copy_page_array[i]); + pr_debug("\t.set pop\n"); +} + +#ifdef CONFIG_SIBYTE_DMA_PAGEOPS + +/* + * Pad descriptors to cacheline, since each is exclusively owned by a + * particular CPU. + */ +struct dmadscr { + u64 dscr_a; + u64 dscr_b; + u64 pad_a; + u64 pad_b; +} ____cacheline_aligned_in_smp page_descr[DM_NUM_CHANNELS]; + +void sb1_dma_init(void) +{ + int i; + + for (i = 0; i < DM_NUM_CHANNELS; i++) { + const u64 base_val = CPHYSADDR((unsigned long)&page_descr[i]) | + V_DM_DSCR_BASE_RINGSZ(1); + void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); + + __raw_writeq(base_val, base_reg); + __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); + __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); + } +} + +void clear_page(void *page) +{ + u64 to_phys = CPHYSADDR((unsigned long)page); + unsigned int cpu = smp_processor_id(); + + /* if the page is not in KSEG0, use old way */ + if ((long)KSEGX((unsigned long)page) != (long)CKSEG0) + return clear_page_cpu(page); + + page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | + M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; + page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); + __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); + + /* + * Don't really want to do it this way, but there's no + * reliable way to delay completion detection. + */ + while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) + & M_DM_DSCR_BASE_INTERRUPT)) + ; + __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); +} + +void copy_page(void *to, void *from) +{ + u64 from_phys = CPHYSADDR((unsigned long)from); + u64 to_phys = CPHYSADDR((unsigned long)to); + unsigned int cpu = smp_processor_id(); + + /* if any page is not in KSEG0, use old way */ + if ((long)KSEGX((unsigned long)to) != (long)CKSEG0 + || (long)KSEGX((unsigned long)from) != (long)CKSEG0) + return copy_page_cpu(to, from); + + page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | + M_DM_DSCRA_INTERRUPT; + page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); + __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); + + /* + * Don't really want to do it this way, but there's no + * reliable way to delay completion detection. + */ + while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) + & M_DM_DSCR_BASE_INTERRUPT)) + ; + __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); +} + +#endif /* CONFIG_SIBYTE_DMA_PAGEOPS */ diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c deleted file mode 100644 index 9185fbf..0000000 --- a/arch/mips/mm/pg-r4k.c +++ /dev/null @@ -1,534 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2007 Maciej W. Rozycki - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define half_scache_line_size() (cpu_scache_line_size() >> 1) -#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) -#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) - - -/* - * Maximum sizes: - * - * R4000 128 bytes S-cache: 0x58 bytes - * R4600 v1.7: 0x5c bytes - * R4600 v2.0: 0x60 bytes - * With prefetching, 16 byte strides 0xa0 bytes - */ - -static unsigned int clear_page_array[0x130 / 4]; - -void clear_page(void * page) __attribute__((alias("clear_page_array"))); - -EXPORT_SYMBOL(clear_page); - -/* - * Maximum sizes: - * - * R4000 128 bytes S-cache: 0x11c bytes - * R4600 v1.7: 0x080 bytes - * R4600 v2.0: 0x07c bytes - * With prefetching, 16 byte strides 0x0b8 bytes - */ -static unsigned int copy_page_array[0x148 / 4]; - -void copy_page(void *to, void *from) __attribute__((alias("copy_page_array"))); - -EXPORT_SYMBOL(copy_page); - -/* - * This is suboptimal for 32-bit kernels; we assume that R10000 is only used - * with 64-bit kernels. The prefetch offsets have been experimentally tuned - * an Origin 200. - */ -static int pref_offset_clear __initdata = 512; -static int pref_offset_copy __initdata = 256; - -static unsigned int pref_src_mode __initdata; -static unsigned int pref_dst_mode __initdata; - -static int load_offset __initdata; -static int store_offset __initdata; - -static unsigned int __initdata *dest, *epc; - -static unsigned int instruction_pending; -static union mips_instruction delayed_mi; - -static void __init emit_instruction(union mips_instruction mi) -{ - if (instruction_pending) - *epc++ = delayed_mi.word; - - instruction_pending = 1; - delayed_mi = mi; -} - -static inline void flush_delay_slot_or_nop(void) -{ - if (instruction_pending) { - *epc++ = delayed_mi.word; - instruction_pending = 0; - return; - } - - *epc++ = 0; -} - -static inline unsigned int *label(void) -{ - if (instruction_pending) { - *epc++ = delayed_mi.word; - instruction_pending = 0; - } - - return epc; -} - -static inline void build_insn_word(unsigned int word) -{ - union mips_instruction mi; - - mi.word = word; - - emit_instruction(mi); -} - -static inline void build_nop(void) -{ - build_insn_word(0); /* nop */ -} - -static inline void build_src_pref(int advance) -{ - if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) { - union mips_instruction mi; - - mi.i_format.opcode = pref_op; - mi.i_format.rs = 5; /* $a1 */ - mi.i_format.rt = pref_src_mode; - mi.i_format.simmediate = load_offset + advance; - - emit_instruction(mi); - } -} - -static inline void __build_load_reg(int reg) -{ - union mips_instruction mi; - unsigned int width; - - if (cpu_has_64bit_gp_regs) { - mi.i_format.opcode = ld_op; - width = 8; - } else { - mi.i_format.opcode = lw_op; - width = 4; - } - mi.i_format.rs = 5; /* $a1 */ - mi.i_format.rt = reg; /* $reg */ - mi.i_format.simmediate = load_offset; - - load_offset += width; - emit_instruction(mi); -} - -static inline void build_load_reg(int reg) -{ - if (cpu_has_prefetch) - build_src_pref(pref_offset_copy); - - __build_load_reg(reg); -} - -static inline void build_dst_pref(int advance) -{ - if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) { - union mips_instruction mi; - - mi.i_format.opcode = pref_op; - mi.i_format.rs = 4; /* $a0 */ - mi.i_format.rt = pref_dst_mode; - mi.i_format.simmediate = store_offset + advance; - - emit_instruction(mi); - } -} - -static inline void build_cdex_s(void) -{ - union mips_instruction mi; - - if ((store_offset & (cpu_scache_line_size() - 1))) - return; - - mi.c_format.opcode = cache_op; - mi.c_format.rs = 4; /* $a0 */ - mi.c_format.c_op = 3; /* Create Dirty Exclusive */ - mi.c_format.cache = 3; /* Secondary Data Cache */ - mi.c_format.simmediate = store_offset; - - emit_instruction(mi); -} - -static inline void build_cdex_p(void) -{ - union mips_instruction mi; - - if (store_offset & (cpu_dcache_line_size() - 1)) - return; - - if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { - build_nop(); - build_nop(); - build_nop(); - build_nop(); - } - - if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) - build_insn_word(0x8c200000); /* lw $zero, ($at) */ - - mi.c_format.opcode = cache_op; - mi.c_format.rs = 4; /* $a0 */ - mi.c_format.c_op = 3; /* Create Dirty Exclusive */ - mi.c_format.cache = 1; /* Data Cache */ - mi.c_format.simmediate = store_offset; - - emit_instruction(mi); -} - -static void __init __build_store_reg(int reg) -{ - union mips_instruction mi; - unsigned int width; - - if (cpu_has_64bit_gp_regs || - (cpu_has_64bit_zero_reg && reg == 0)) { - mi.i_format.opcode = sd_op; - width = 8; - } else { - mi.i_format.opcode = sw_op; - width = 4; - } - mi.i_format.rs = 4; /* $a0 */ - mi.i_format.rt = reg; /* $reg */ - mi.i_format.simmediate = store_offset; - - store_offset += width; - emit_instruction(mi); -} - -static inline void build_store_reg(int reg) -{ - int pref_off = cpu_has_prefetch ? - (reg ? pref_offset_copy : pref_offset_clear) : 0; - if (pref_off) - build_dst_pref(pref_off); - else if (cpu_has_cache_cdex_s) - build_cdex_s(); - else if (cpu_has_cache_cdex_p) - build_cdex_p(); - - __build_store_reg(reg); -} - -static inline void build_addiu_rt_rs(unsigned int rt, unsigned int rs, - unsigned long offset) -{ - union mips_instruction mi; - - BUG_ON(offset > 0x7fff); - - if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) { - mi.i_format.opcode = addiu_op; - mi.i_format.rs = 0; /* $zero */ - mi.i_format.rt = 25; /* $t9 */ - mi.i_format.simmediate = offset; - emit_instruction(mi); - - mi.r_format.opcode = spec_op; - mi.r_format.rs = rs; - mi.r_format.rt = 25; /* $t9 */ - mi.r_format.rd = rt; - mi.r_format.re = 0; - mi.r_format.func = daddu_op; - } else { - mi.i_format.opcode = cpu_has_64bit_gp_regs ? - daddiu_op : addiu_op; - mi.i_format.rs = rs; - mi.i_format.rt = rt; - mi.i_format.simmediate = offset; - } - emit_instruction(mi); -} - -static inline void build_addiu_a2_a0(unsigned long offset) -{ - build_addiu_rt_rs(6, 4, offset); /* $a2, $a0, offset */ -} - -static inline void build_addiu_a2(unsigned long offset) -{ - build_addiu_rt_rs(6, 6, offset); /* $a2, $a2, offset */ -} - -static inline void build_addiu_a1(unsigned long offset) -{ - build_addiu_rt_rs(5, 5, offset); /* $a1, $a1, offset */ - - load_offset -= offset; -} - -static inline void build_addiu_a0(unsigned long offset) -{ - build_addiu_rt_rs(4, 4, offset); /* $a0, $a0, offset */ - - store_offset -= offset; -} - -static inline void build_bne(unsigned int *dest) -{ - union mips_instruction mi; - - mi.i_format.opcode = bne_op; - mi.i_format.rs = 6; /* $a2 */ - mi.i_format.rt = 4; /* $a0 */ - mi.i_format.simmediate = dest - epc - 1; - - *epc++ = mi.word; - flush_delay_slot_or_nop(); -} - -static inline void build_jr_ra(void) -{ - union mips_instruction mi; - - mi.r_format.opcode = spec_op; - mi.r_format.rs = 31; - mi.r_format.rt = 0; - mi.r_format.rd = 0; - mi.r_format.re = 0; - mi.r_format.func = jr_op; - - *epc++ = mi.word; - flush_delay_slot_or_nop(); -} - -void __init build_clear_page(void) -{ - unsigned int loop_start; - unsigned long off; - int i; - - epc = (unsigned int *) &clear_page_array; - instruction_pending = 0; - store_offset = 0; - - if (cpu_has_prefetch) { - switch (current_cpu_type()) { - case CPU_TX49XX: - /* TX49 supports only Pref_Load */ - pref_offset_clear = 0; - pref_offset_copy = 0; - break; - - case CPU_RM9000: - /* - * As a workaround for erratum G105 which make the - * PrepareForStore hint unusable we fall back to - * StoreRetained on the RM9000. Once it is known which - * versions of the RM9000 we'll be able to condition- - * alize this. - */ - - case CPU_R10000: - case CPU_R12000: - case CPU_R14000: - pref_src_mode = Pref_LoadStreamed; - pref_dst_mode = Pref_StoreStreamed; - break; - - default: - pref_src_mode = Pref_LoadStreamed; - pref_dst_mode = Pref_PrepareForStore; - break; - } - } - - off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0); - if (off > 0x7fff) { - build_addiu_a2_a0(off >> 1); - build_addiu_a2(off >> 1); - } else - build_addiu_a2_a0(off); - - if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) - build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ - -dest = label(); - do { - build_store_reg(0); - build_store_reg(0); - build_store_reg(0); - build_store_reg(0); - } while (store_offset < half_scache_line_size()); - build_addiu_a0(2 * store_offset); - loop_start = store_offset; - do { - build_store_reg(0); - build_store_reg(0); - build_store_reg(0); - build_store_reg(0); - } while ((store_offset - loop_start) < half_scache_line_size()); - build_bne(dest); - - if (cpu_has_prefetch && pref_offset_clear) { - build_addiu_a2_a0(pref_offset_clear); - dest = label(); - loop_start = store_offset; - do { - __build_store_reg(0); - __build_store_reg(0); - __build_store_reg(0); - __build_store_reg(0); - } while ((store_offset - loop_start) < half_scache_line_size()); - build_addiu_a0(2 * store_offset); - loop_start = store_offset; - do { - __build_store_reg(0); - __build_store_reg(0); - __build_store_reg(0); - __build_store_reg(0); - } while ((store_offset - loop_start) < half_scache_line_size()); - build_bne(dest); - } - - build_jr_ra(); - - BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); - - pr_info("Synthesized clear page handler (%u instructions).\n", - (unsigned int)(epc - clear_page_array)); - - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (epc - clear_page_array); i++) - pr_debug("\t.word 0x%08x\n", clear_page_array[i]); - pr_debug("\t.set pop\n"); -} - -void __init build_copy_page(void) -{ - unsigned int loop_start; - unsigned long off; - int i; - - epc = (unsigned int *) ©_page_array; - store_offset = load_offset = 0; - instruction_pending = 0; - - off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0); - if (off > 0x7fff) { - build_addiu_a2_a0(off >> 1); - build_addiu_a2(off >> 1); - } else - build_addiu_a2_a0(off); - - if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) - build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ - -dest = label(); - loop_start = store_offset; - do { - build_load_reg( 8); - build_load_reg( 9); - build_load_reg(10); - build_load_reg(11); - build_store_reg( 8); - build_store_reg( 9); - build_store_reg(10); - build_store_reg(11); - } while ((store_offset - loop_start) < half_scache_line_size()); - build_addiu_a0(2 * store_offset); - build_addiu_a1(2 * load_offset); - loop_start = store_offset; - do { - build_load_reg( 8); - build_load_reg( 9); - build_load_reg(10); - build_load_reg(11); - build_store_reg( 8); - build_store_reg( 9); - build_store_reg(10); - build_store_reg(11); - } while ((store_offset - loop_start) < half_scache_line_size()); - build_bne(dest); - - if (cpu_has_prefetch && pref_offset_copy) { - build_addiu_a2_a0(pref_offset_copy); - dest = label(); - loop_start = store_offset; - do { - __build_load_reg( 8); - __build_load_reg( 9); - __build_load_reg(10); - __build_load_reg(11); - __build_store_reg( 8); - __build_store_reg( 9); - __build_store_reg(10); - __build_store_reg(11); - } while ((store_offset - loop_start) < half_scache_line_size()); - build_addiu_a0(2 * store_offset); - build_addiu_a1(2 * load_offset); - loop_start = store_offset; - do { - __build_load_reg( 8); - __build_load_reg( 9); - __build_load_reg(10); - __build_load_reg(11); - __build_store_reg( 8); - __build_store_reg( 9); - __build_store_reg(10); - __build_store_reg(11); - } while ((store_offset - loop_start) < half_scache_line_size()); - build_bne(dest); - } - - build_jr_ra(); - - BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); - - pr_info("Synthesized copy page handler (%u instructions).\n", - (unsigned int)(epc - copy_page_array)); - - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - for (i = 0; i < (epc - copy_page_array); i++) - pr_debug("\t.word 0x%08x\n", copy_page_array[i]); - pr_debug("\t.set pop\n"); -} diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c deleted file mode 100644 index 89925ec..0000000 --- a/arch/mips/mm/pg-sb1.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000 SiByte, Inc. - * Copyright (C) 2005 Thiemo Seufer - * - * Written by Justin Carlson of SiByte, Inc. - * and Kip Walker of Broadcom Corp. - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS -#define SB1_PREF_LOAD_STREAMED_HINT "0" -#define SB1_PREF_STORE_STREAMED_HINT "1" -#else -#define SB1_PREF_LOAD_STREAMED_HINT "4" -#define SB1_PREF_STORE_STREAMED_HINT "5" -#endif - -static inline void clear_page_cpu(void *page) -{ - unsigned char *addr = (unsigned char *) page; - unsigned char *end = addr + PAGE_SIZE; - - /* - * JDCXXX - This should be bottlenecked by the write buffer, but these - * things tend to be mildly unpredictable...should check this on the - * performance model - * - * We prefetch 4 lines ahead. We're also "cheating" slightly here... - * since we know we're on an SB1, we force the assembler to take - * 64-bit operands to speed things up - */ - __asm__ __volatile__( - " .set push \n" - " .set mips4 \n" - " .set noreorder \n" -#ifdef CONFIG_CPU_HAS_PREFETCH - " daddiu %0, %0, 128 \n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" - /* Prefetch the first 4 lines */ - " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n" - "1: sd $0, -128(%0) \n" /* Throw out a cacheline of 0's */ - " sd $0, -120(%0) \n" - " sd $0, -112(%0) \n" - " sd $0, -104(%0) \n" - " daddiu %0, %0, 32 \n" - " bnel %0, %1, 1b \n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n" - " daddiu %0, %0, -128 \n" -#endif - " sd $0, 0(%0) \n" /* Throw out a cacheline of 0's */ - "1: sd $0, 8(%0) \n" - " sd $0, 16(%0) \n" - " sd $0, 24(%0) \n" - " daddiu %0, %0, 32 \n" - " bnel %0, %1, 1b \n" - " sd $0, 0(%0) \n" - " .set pop \n" - : "+r" (addr) - : "r" (end) - : "memory"); -} - -static inline void copy_page_cpu(void *to, void *from) -{ - unsigned char *src = (unsigned char *)from; - unsigned char *dst = (unsigned char *)to; - unsigned char *end = src + PAGE_SIZE; - - /* - * The pref's used here are using "streaming" hints, which cause the - * copied data to be kicked out of the cache sooner. A page copy often - * ends up copying a lot more data than is commonly used, so this seems - * to make sense in terms of reducing cache pollution, but I've no real - * performance data to back this up - */ - __asm__ __volatile__( - " .set push \n" - " .set mips4 \n" - " .set noreorder \n" -#ifdef CONFIG_CPU_HAS_PREFETCH - " daddiu %0, %0, 128 \n" - " daddiu %1, %1, 128 \n" - " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" - /* Prefetch the first 4 lines */ - " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n" - " pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n" - " pref " SB1_PREF_LOAD_STREAMED_HINT ", -64(%0)\n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n" - " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n" - "1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n" -# ifdef CONFIG_64BIT - " ld $8, -128(%0) \n" /* Block copy a cacheline */ - " ld $9, -120(%0) \n" - " ld $10, -112(%0) \n" - " ld $11, -104(%0) \n" - " sd $8, -128(%1) \n" - " sd $9, -120(%1) \n" - " sd $10, -112(%1) \n" - " sd $11, -104(%1) \n" -# else - " lw $2, -128(%0) \n" /* Block copy a cacheline */ - " lw $3, -124(%0) \n" - " lw $6, -120(%0) \n" - " lw $7, -116(%0) \n" - " lw $8, -112(%0) \n" - " lw $9, -108(%0) \n" - " lw $10, -104(%0) \n" - " lw $11, -100(%0) \n" - " sw $2, -128(%1) \n" - " sw $3, -124(%1) \n" - " sw $6, -120(%1) \n" - " sw $7, -116(%1) \n" - " sw $8, -112(%1) \n" - " sw $9, -108(%1) \n" - " sw $10, -104(%1) \n" - " sw $11, -100(%1) \n" -# endif - " daddiu %0, %0, 32 \n" - " daddiu %1, %1, 32 \n" - " bnel %0, %2, 1b \n" - " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n" - " daddiu %0, %0, -128 \n" - " daddiu %1, %1, -128 \n" -#endif -#ifdef CONFIG_64BIT - " ld $8, 0(%0) \n" /* Block copy a cacheline */ - "1: ld $9, 8(%0) \n" - " ld $10, 16(%0) \n" - " ld $11, 24(%0) \n" - " sd $8, 0(%1) \n" - " sd $9, 8(%1) \n" - " sd $10, 16(%1) \n" - " sd $11, 24(%1) \n" -#else - " lw $2, 0(%0) \n" /* Block copy a cacheline */ - "1: lw $3, 4(%0) \n" - " lw $6, 8(%0) \n" - " lw $7, 12(%0) \n" - " lw $8, 16(%0) \n" - " lw $9, 20(%0) \n" - " lw $10, 24(%0) \n" - " lw $11, 28(%0) \n" - " sw $2, 0(%1) \n" - " sw $3, 4(%1) \n" - " sw $6, 8(%1) \n" - " sw $7, 12(%1) \n" - " sw $8, 16(%1) \n" - " sw $9, 20(%1) \n" - " sw $10, 24(%1) \n" - " sw $11, 28(%1) \n" -#endif - " daddiu %0, %0, 32 \n" - " daddiu %1, %1, 32 \n" - " bnel %0, %2, 1b \n" -#ifdef CONFIG_64BIT - " ld $8, 0(%0) \n" -#else - " lw $2, 0(%0) \n" -#endif - " .set pop \n" - : "+r" (src), "+r" (dst) - : "r" (end) -#ifdef CONFIG_64BIT - : "$8", "$9", "$10", "$11", "memory"); -#else - : "$2", "$3", "$6", "$7", "$8", "$9", "$10", "$11", "memory"); -#endif -} - - -#ifdef CONFIG_SIBYTE_DMA_PAGEOPS - -/* - * Pad descriptors to cacheline, since each is exclusively owned by a - * particular CPU. - */ -typedef struct dmadscr_s { - u64 dscr_a; - u64 dscr_b; - u64 pad_a; - u64 pad_b; -} dmadscr_t; - -static dmadscr_t page_descr[DM_NUM_CHANNELS] - __attribute__((aligned(SMP_CACHE_BYTES))); - -void sb1_dma_init(void) -{ - int i; - - for (i = 0; i < DM_NUM_CHANNELS; i++) { - const u64 base_val = CPHYSADDR((unsigned long)&page_descr[i]) | - V_DM_DSCR_BASE_RINGSZ(1); - void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); - - __raw_writeq(base_val, base_reg); - __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); - __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); - } -} - -void clear_page(void *page) -{ - u64 to_phys = CPHYSADDR((unsigned long)page); - unsigned int cpu = smp_processor_id(); - - /* if the page is not in KSEG0, use old way */ - if ((long)KSEGX((unsigned long)page) != (long)CKSEG0) - return clear_page_cpu(page); - - page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | - M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; - page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); - __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); - - /* - * Don't really want to do it this way, but there's no - * reliable way to delay completion detection. - */ - while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) - & M_DM_DSCR_BASE_INTERRUPT)) - ; - __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); -} - -void copy_page(void *to, void *from) -{ - u64 from_phys = CPHYSADDR((unsigned long)from); - u64 to_phys = CPHYSADDR((unsigned long)to); - unsigned int cpu = smp_processor_id(); - - /* if any page is not in KSEG0, use old way */ - if ((long)KSEGX((unsigned long)to) != (long)CKSEG0 - || (long)KSEGX((unsigned long)from) != (long)CKSEG0) - return copy_page_cpu(to, from); - - page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | - M_DM_DSCRA_INTERRUPT; - page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); - __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); - - /* - * Don't really want to do it this way, but there's no - * reliable way to delay completion detection. - */ - while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) - & M_DM_DSCR_BASE_INTERRUPT)) - ; - __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); -} - -#else /* !CONFIG_SIBYTE_DMA_PAGEOPS */ - -void clear_page(void *page) -{ - return clear_page_cpu(page); -} - -void copy_page(void *to, void *from) -{ - return copy_page_cpu(to, from); -} - -#endif /* !CONFIG_SIBYTE_DMA_PAGEOPS */ - -EXPORT_SYMBOL(clear_page); -EXPORT_SYMBOL(copy_page); - -void __init build_clear_page(void) -{ -} - -void __init build_copy_page(void) -{ -} diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 74ae034..ffa780b 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -299,7 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) idx = read_c0_index(); ptep = pte_offset_map(pmdp, address); -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) write_c0_entrylo0(ptep->pte_high); ptep++; write_c0_entrylo1(ptep->pte_high); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index e3f74ed..903a417 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -58,13 +58,13 @@ enum opcode { insn_invalid, insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, - insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, - insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, - insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, - insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, - insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, - insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, - insn_tlbwr, insn_xor, insn_xori + insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, + insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, + insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, + insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, + insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, + insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, + insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori }; struct insn { @@ -94,6 +94,7 @@ static struct insn insn_table[] __initdata = { { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, @@ -116,6 +117,7 @@ static struct insn insn_table[] __initdata = { { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, @@ -337,6 +339,7 @@ I_u1s2(_bgezl) I_u1s2(_bltz) I_u1s2(_bltzl) I_u1u2s3(_bne) +I_u2s3u1(_cache) I_u1u2u3(_dmfc0) I_u1u2u3(_dmtc0) I_u2u1s3(_daddiu) @@ -359,6 +362,7 @@ I_u2s3u1(_lw) I_u1u2u3(_mfc0) I_u1u2u3(_mtc0) I_u2u1u3(_ori) +I_u2s3u1(_pref) I_0(_rfe) I_u2s3u1(_sc) I_u2s3u1(_scd) @@ -555,6 +559,14 @@ uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) } void __init +uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, + unsigned int reg2, int lid) +{ + uasm_r_mips_pc16(r, *p, lid); + uasm_i_bne(p, reg1, reg2, 0); +} + +void __init uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) { uasm_r_mips_pc16(r, *p, lid); diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h index a10fc11..1255293 100644 --- a/arch/mips/mm/uasm.h +++ b/arch/mips/mm/uasm.h @@ -55,6 +55,7 @@ Ip_u1s2(_bgezl); Ip_u1s2(_bltz); Ip_u1s2(_bltzl); Ip_u1u2s3(_bne); +Ip_u2s3u1(_cache); Ip_u1u2u3(_dmfc0); Ip_u1u2u3(_dmtc0); Ip_u2u1s3(_daddiu); @@ -77,6 +78,7 @@ Ip_u2s3u1(_lw); Ip_u1u2u3(_mfc0); Ip_u1u2u3(_mtc0); Ip_u2u1u3(_ori); +Ip_u2s3u1(_pref); Ip_0(_rfe); Ip_u2s3u1(_sc); Ip_u2s3u1(_scd); @@ -185,6 +187,9 @@ uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); void __init uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); void __init +uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, + unsigned int reg2, int lid); +void __init uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); void __init uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/nxp/pnx8550/common/Makefile new file mode 100644 index 0000000..31cc1a5 --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/Makefile @@ -0,0 +1,29 @@ +# +# Per Hallsmark, per.hallsmark@mvista.com +# +# ######################################################################## +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# ####################################################################### +# +# Makefile for the PNX8550 specific kernel interface routines +# under Linux. +# + +obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_KGDB) += gdb_hook.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/nxp/pnx8550/common/gdb_hook.c b/arch/mips/nxp/pnx8550/common/gdb_hook.c new file mode 100644 index 0000000..ad4624f --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/gdb_hook.c @@ -0,0 +1,109 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * This is the interface to the remote debugger stub. + * + */ +#include +#include +#include +#include +#include + +#include +#include + +#include + +static struct serial_state rs_table[IP3106_NR_PORTS] = { +}; +static struct async_struct kdb_port_info = {0}; + +void rs_kgdb_hook(int tty_no) +{ + struct serial_state *ser = &rs_table[tty_no]; + + kdb_port_info.state = ser; + kdb_port_info.magic = SERIAL_MAGIC; + kdb_port_info.port = tty_no; + kdb_port_info.flags = ser->flags; + + /* + * Clear all interrupts + */ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + + /* + * Now, initialize the UART + */ + ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT; + ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud +} + +int putDebugChar(char c) +{ + /* Wait until FIFO not full */ + while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + /* Send one char */ + ip3106_fifo(UART_BASE, kdb_port_info.port) = c; + + return 1; +} + +char getDebugChar(void) +{ + char ch; + + /* Wait until there is a char in the FIFO */ + while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RXFIFO) >> 8)) + ; + /* Read one char */ + ch = ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RBRTHR; + /* Advance the RX FIFO read pointer */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT; + return (ch); +} + +void rs_disable_debug_interrupts(void) +{ + ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */ +} + +void rs_enable_debug_interrupts(void) +{ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */ +} diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c new file mode 100644 index 0000000..aad0342 --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/int.c @@ -0,0 +1,238 @@ +/* + * + * Copyright (C) 2005 Embedded Alley Solutions, Inc + * Ported to 2.6. + * + * Per Hallsmark, per.hallsmark@mvista.com + * Copyright (C) 2000, 2001 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* default prio for interrupts */ +/* first one is a no-no so therefore always prio 0 (disabled) */ +static char gic_prio[PNX8550_INT_GIC_TOTINT] = { + 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49 + 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69 + 1 // 70 +}; + +static void hw0_irqdispatch(int irq) +{ + /* find out which interrupt */ + irq = PNX8550_GIC_VECTOR_0 >> 3; + + if (irq == 0) { + printk("hw0_irqdispatch: irq 0, spurious interrupt?\n"); + return; + } + do_IRQ(PNX8550_INT_GIC_MIN + irq); +} + + +static void timer_irqdispatch(int irq) +{ + irq = (0x01c0 & read_c0_config7()) >> 6; + + if (unlikely(irq == 0)) { + printk("timer_irqdispatch: irq 0, spurious interrupt?\n"); + return; + } + + if (irq & 0x1) + do_IRQ(PNX8550_INT_TIMER1); + if (irq & 0x2) + do_IRQ(PNX8550_INT_TIMER2); + if (irq & 0x4) + do_IRQ(PNX8550_INT_TIMER3); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP2) + hw0_irqdispatch(2); + else if (pending & STATUSF_IP7) { + if (read_c0_config7() & 0x01c0) + timer_irqdispatch(7); + } else + spurious_interrupt(); +} + +static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) +{ + unsigned long status = read_c0_status(); + + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + + write_c0_status(status); +} + +static inline void mask_gic_int(unsigned int irq_nr) +{ + /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */ + PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */ +} + +static inline void unmask_gic_int(unsigned int irq_nr) +{ + /* set prio mask to lower four bits and enable interrupt */ + PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; +} + +static inline void mask_irq(unsigned int irq_nr) +{ + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { + modify_cp0_intmask(1 << irq_nr, 0); + } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_GIC_MAX)) { + mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); + } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_TIMER_MAX)) { + modify_cp0_intmask(1 << 7, 0); + } else { + printk("mask_irq: irq %d doesn't exist!\n", irq_nr); + } +} + +static inline void unmask_irq(unsigned int irq_nr) +{ + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { + modify_cp0_intmask(0, 1 << irq_nr); + } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_GIC_MAX)) { + unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); + } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_TIMER_MAX)) { + modify_cp0_intmask(0, 1 << 7); + } else { + printk("mask_irq: irq %d doesn't exist!\n", irq_nr); + } +} + +int pnx8550_set_gic_priority(int irq, int priority) +{ + int gic_irq = irq-PNX8550_INT_GIC_MIN; + int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf; + + gic_prio[gic_irq] = priority; + PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]); + + return prev_priority; +} + +static struct irq_chip level_irq_type = { + .name = "PNX Level IRQ", + .ack = mask_irq, + .mask = mask_irq, + .mask_ack = mask_irq, + .unmask = unmask_irq, +}; + +static struct irqaction gic_action = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "GIC", +}; + +static struct irqaction timer_action = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "Timer", +}; + +void __init arch_init_irq(void) +{ + int i; + int configPR; + + for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + mask_irq(i); /* mask the irq just in case */ + } + + /* init of GIC/IPC interrupts */ + /* should be done before cp0 since cp0 init enables the GIC int */ + for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) { + int gic_int_line = i - PNX8550_INT_GIC_MIN; + if (gic_int_line == 0 ) + continue; // don't fiddle with int 0 + /* + * enable change of TARGET, ENABLE and ACTIVE_LOW bits + * set TARGET 0 to route through hw0 interrupt + * set ACTIVE_LOW 0 active high (correct?) + * + * We really should setup an interrupt description table + * to do this nicely. + * Note, PCI INTA is active low on the bus, but inverted + * in the GIC, so to us it's active high. + */ + PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000; + + /* mask/priority is still 0 so we will not get any + * interrupts until it is unmasked */ + + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + } + + /* Priority level 0 */ + PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0; + + /* Set int vector table address */ + PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; + + set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, + handle_level_irq); + setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); + + /* init of Timer interrupts */ + for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + + /* Stop Timer 1-3 */ + configPR = read_c0_config7(); + configPR |= 0x00000038; + write_c0_config7(configPR); + + set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, + handle_level_irq); + setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); +} + +EXPORT_SYMBOL(pnx8550_set_gic_priority); diff --git a/arch/mips/nxp/pnx8550/common/pci.c b/arch/mips/nxp/pnx8550/common/pci.c new file mode 100644 index 0000000..eee4f3d --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/pci.c @@ -0,0 +1,133 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +static struct resource pci_io_resource = { + .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */ + .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE, + .name = "pci IO space", + .flags = IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + .start = PNX8550_PCIMEM, + .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1, + .name = "pci memory space", + .flags = IORESOURCE_MEM +}; + +extern struct pci_ops pnx8550_pci_ops; + +static struct pci_controller pnx8550_controller = { + .pci_ops = &pnx8550_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, +}; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +static inline unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +static int __init pnx8550_pci_setup(void) +{ + int pci_mem_code; + int mem_size = get_system_mem_size() >> 20; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* Calc the PCI mem size code */ + if (mem_size >= 128) + pci_mem_code = SIZE_128M; + else if (mem_size >= 64) + pci_mem_code = SIZE_64M; + else if (mem_size >= 32) + pci_mem_code = SIZE_32M; + else + pci_mem_code = SIZE_16M; + + /* Set PCI_XIO registers */ + outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO); + outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI); + outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO); + outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI); + + /* Send memory transaction via PCI_BASE2 */ + outl(0x00000001, PCI_BASE | PCI_IO); + + /* Unlock the setup register */ + outl(0xca, PCI_BASE | PCI_UNLOCKREG); + + /* + * BAR0 of PNX8550 (pci base 10) must be zero in order for ide + * to work, and in order for bus_to_baddr to work without any + * hacks. + */ + outl(0x00000000, PCI_BASE | PCI_BASE10); + + /* + *These two bars are set by default or the boot code. + * However, it's safer to set them here so we're not boot + * code dependent. + */ + outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */ + outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */ + + outl(PCI_EN_TA | + PCI_EN_PCI2MMI | + PCI_EN_XIO | + PCI_SETUP_BASE18_SIZE(SIZE_32M) | + PCI_SETUP_BASE18_EN | + PCI_SETUP_BASE14_EN | + PCI_SETUP_BASE10_PREF | + PCI_SETUP_BASE10_SIZE(pci_mem_code) | + PCI_SETUP_CFGMANAGE_EN | + PCI_SETUP_PCIARB_EN, + PCI_BASE | + PCI_SETUP); /* PCI_SETUP */ + outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */ + + register_pci_controller(&pnx8550_controller); + + return 0; +} + +arch_initcall(pnx8550_pci_setup); diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/nxp/pnx8550/common/platform.c new file mode 100644 index 0000000..c7c763d --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/platform.c @@ -0,0 +1,132 @@ +/* + * Platform device support for NXP PNX8550 SoCs + * + * Copyright 2005, Embedded Alley Solutions, Inc + * + * Based on arch/mips/au1000/common/platform.c + * Platform device support for Au1x00 SoCs. + * + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct resource pnx8550_usb_ohci_resources[] = { + [0] = { + .start = PNX8550_USB_OHCI_OP_BASE, + .end = PNX8550_USB_OHCI_OP_BASE + + PNX8550_USB_OHCI_OP_LEN, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8550_INT_USB, + .end = PNX8550_INT_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource pnx8550_uart_resources[] = { + [0] = { + .start = PNX8550_UART_PORT0, + .end = PNX8550_UART_PORT0 + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8550_UART_INT(0), + .end = PNX8550_UART_INT(0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = PNX8550_UART_PORT1, + .end = PNX8550_UART_PORT1 + 0xfff, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = PNX8550_UART_INT(1), + .end = PNX8550_UART_INT(1), + .flags = IORESOURCE_IRQ, + }, +}; + +struct pnx8xxx_port pnx8xxx_ports[] = { + [0] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX8550_UART_PORT0, + .mapbase = PNX8550_UART_PORT0, + .irq = PNX8550_UART_INT(0), + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 0, + }, + }, + [1] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX8550_UART_PORT1, + .mapbase = PNX8550_UART_PORT1, + .irq = PNX8550_UART_INT(1), + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 1, + }, + }, +}; + +/* The dmamask must be set for OHCI to work */ +static u64 ohci_dmamask = ~(u32)0; + +static u64 uart_dmamask = ~(u32)0; + +static struct platform_device pnx8550_usb_ohci_device = { + .name = "pnx8550-ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources), + .resource = pnx8550_usb_ohci_resources, +}; + +static struct platform_device pnx8550_uart_device = { + .name = "pnx8xxx-uart", + .id = -1, + .dev = { + .dma_mask = &uart_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = pnx8xxx_ports, + }, + .num_resources = ARRAY_SIZE(pnx8550_uart_resources), + .resource = pnx8550_uart_resources, +}; + +static struct platform_device *pnx8550_platform_devices[] __initdata = { + &pnx8550_usb_ohci_device, + &pnx8550_uart_device, +}; + +static int __init pnx8550_platform_init(void) +{ + return platform_add_devices(pnx8550_platform_devices, + ARRAY_SIZE(pnx8550_platform_devices)); +} + +arch_initcall(pnx8550_platform_init); diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/nxp/pnx8550/common/proc.c new file mode 100644 index 0000000..18b125e --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/proc.c @@ -0,0 +1,112 @@ +/* + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) +{ + int len = 0; + int configPR = read_c0_config7(); + + if (offset==0) { + len += sprintf(&page[len], "Timer: count, compare, tc, status\n"); + len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n", + read_c0_count(), read_c0_compare(), + (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); + len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n", + read_c0_count2(), read_c0_compare2(), + (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); + len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n", + read_c0_count3(), read_c0_compare3(), + (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); + } + + return len; +} + +static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) +{ + int len = 0; + + if (offset==0) { + len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1()); + len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2()); + len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3()); + len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7()); + len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status()); + len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause()); + len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count()); + len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2()); + len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3()); + len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare()); + len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2()); + len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3()); + } + + return len; +} + +static struct proc_dir_entry* pnx8550_dir = NULL; +static struct proc_dir_entry* pnx8550_timers = NULL; +static struct proc_dir_entry* pnx8550_registers = NULL; + +static int pnx8550_proc_init( void ) +{ + + // Create /proc/pnx8550 + pnx8550_dir = proc_mkdir("pnx8550", NULL); + if (!pnx8550_dir) { + printk(KERN_ERR "Can't create pnx8550 proc dir\n"); + return -1; + } + + // Create /proc/pnx8550/timers + pnx8550_timers = create_proc_read_entry( + "timers", + 0, + pnx8550_dir, + pnx8550_timers_read, + NULL); + + if (!pnx8550_timers) + printk(KERN_ERR "Can't create pnx8550 timers proc file\n"); + + // Create /proc/pnx8550/registers + pnx8550_registers = create_proc_read_entry( + "registers", + 0, + pnx8550_dir, + pnx8550_registers_read, + NULL); + + if (!pnx8550_registers) + printk(KERN_ERR "Can't create pnx8550 registers proc file\n"); + + return 0; +} + +__initcall(pnx8550_proc_init); diff --git a/arch/mips/nxp/pnx8550/common/prom.c b/arch/mips/nxp/pnx8550/common/prom.c new file mode 100644 index 0000000..2f56745 --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/prom.c @@ -0,0 +1,129 @@ +/* + * + * Per Hallsmark, per.hallsmark@mvista.com + * + * Based on jmr3927/common/prom.c + * + * 2004 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include + +#include +#include + +/* #define DEBUG_CMDLINE */ + +extern int prom_argc; +extern char **prom_argv, **prom_envp; + +typedef struct +{ + char *name; +/* char *val; */ +}t_env_var; + + +char * prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + int i; + + arcs_cmdline[0] = '\0'; + for (i = 0; i < prom_argc; i++) { + strcat(arcs_cmdline, prom_argv[i]); + strcat(arcs_cmdline, " "); + } +} + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * Environment variables are stored in the form of "memsize=64". + */ + + t_env_var *env = (t_env_var *)prom_envp; + int i; + + i = strlen(envname); + + while(env->name) { + if(strncmp(envname, env->name, i) == 0) { + return(env->name + strlen(envname) + 1); + } + env++; + } + return(NULL); +} + +inline unsigned char str2hexnum(unsigned char c) +{ + if(c >= '0' && c <= '9') + return c - '0'; + if(c >= 'a' && c <= 'f') + return c - 'a' + 10; + if(c >= 'A' && c <= 'F') + return c - 'A' + 10; + return 0; /* foo */ +} + +inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for(i = 0; i < 6; i++) { + unsigned char num; + + if((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + return 0; +} + +void __init prom_free_prom_memory(void) +{ +} + +extern int pnx8550_console_port; + +/* used by early printk */ +void prom_putchar(char c) +{ + if (pnx8550_console_port != -1) { + /* Wait until FIFO not full */ + while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + /* Send one char */ + ip3106_fifo(UART_BASE, pnx8550_console_port) = c; + } +} + +EXPORT_SYMBOL(prom_getcmdline); +EXPORT_SYMBOL(get_ethernet_addr); +EXPORT_SYMBOL(str2eaddr); diff --git a/arch/mips/nxp/pnx8550/common/reset.c b/arch/mips/nxp/pnx8550/common/reset.c new file mode 100644 index 0000000..7b2cbc5 --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/reset.c @@ -0,0 +1,49 @@ +/*. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the PNX8550 board. + * + */ +#include +#include +#include + +void pnx8550_machine_restart(char *command) +{ + char head[] = "************* Machine restart *************"; + char foot[] = "*******************************************"; + + printk("\n\n"); + printk("%s\n", head); + if (command != NULL) + printk("* %s\n", command); + printk("%s\n", foot); + + PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST; +} + +void pnx8550_machine_halt(void) +{ + printk("*** Machine halt. (Not implemented) ***\n"); +} + +void pnx8550_machine_power_off(void) +{ + printk("*** Machine power off. (Not implemented) ***\n"); +} diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c new file mode 100644 index 0000000..92d764c --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/setup.c @@ -0,0 +1,157 @@ +/* + * + * 2.6 port, Embedded Alley Solutions, Inc + * + * Based on Per Hallsmark, per.hallsmark@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +extern void __init board_setup(void); +extern void pnx8550_machine_restart(char *); +extern void pnx8550_machine_halt(void); +extern void pnx8550_machine_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; +extern void rs_kgdb_hook(int tty_no); +extern char *prom_getcmdline(void); + +struct resource standard_io_resources[] = { + { + .start = 0x00, + .end = 0x1f, + .name = "dma1", + .flags = IORESOURCE_BUSY + }, { + .start = 0x40, + .end = 0x5f, + .name = "timer", + .flags = IORESOURCE_BUSY + }, { + .start = 0x80, + .end = 0x8f, + .name = "dma page reg", + .flags = IORESOURCE_BUSY + }, { + .start = 0xc0, + .end = 0xdf, + .name = "dma2", + .flags = IORESOURCE_BUSY + }, +}; + +#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources) + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +int pnx8550_console_port = -1; + +void __init plat_mem_setup(void) +{ + int i; + char* argptr; + + board_setup(); /* board specific setup */ + + _machine_restart = pnx8550_machine_restart; + _machine_halt = pnx8550_machine_halt; + pm_power_off = pnx8550_machine_power_off; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* IO/MEM resources. */ + set_io_port_base(KSEG1); + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + /* Request I/O space for devices on this board */ + for (i = 0; i < STANDARD_IO_RESOURCES; i++) + request_resource(&ioport_resource, standard_io_resources + i); + + /* Place the Mode Control bit for GPIO pin 16 in primary function */ + /* Pin 16 is used by UART1, UA1_TX */ + outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) | + (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT), + PNX8550_GPIO_MC1); + + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=ttyS")) != NULL) { + argptr += strlen("console=ttyS"); + pnx8550_console_port = *argptr == '0' ? 0 : 1; + + /* We must initialize the UART (console) before early printk */ + /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ + ip3106_lcr(UART_BASE, pnx8550_console_port) = + PNX8XXX_UART_LCR_8BIT; + ip3106_baud(UART_BASE, pnx8550_console_port) = 5; + } + +#ifdef CONFIG_KGDB + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + int line; + argptr += strlen("kgdb=ttyS"); + line = *argptr == '0' ? 0 : 1; + rs_kgdb_hook(line); + pr_info("KGDB: Using ttyS%i for session, " + "please connect your debugger\n", line ? 1 : 0); + } +#endif + return; +} diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c new file mode 100644 index 0000000..62f495b --- /dev/null +++ b/arch/mips/nxp/pnx8550/common/time.c @@ -0,0 +1,150 @@ +/* + * Copyright 2001, 2002, 2003 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + * + * Common time service routines for MIPS machines. See + * Documents/MIPS/README.txt. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +static unsigned long cpj; + +static cycle_t hpt_read(void) +{ + return read_c0_count2(); +} + +static struct clocksource pnx_clocksource = { + .name = "pnx8xxx", + .rating = 200, + .read = hpt_read, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + /* clear MATCH, signal the event */ + c->event_handler(c); + + return IRQ_HANDLED; +} + +static struct irqaction pnx8xxx_timer_irq = { + .handler = pnx8xxx_timer_interrupt, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "pnx8xxx_timer", +}; + +static irqreturn_t monotonic_interrupt(int irq, void *dev_id) +{ + /* Timer 2 clear interrupt */ + write_c0_compare2(-1); + return IRQ_HANDLED; +} + +static struct irqaction monotonic_irqaction = { + .handler = monotonic_interrupt, + .flags = IRQF_DISABLED, + .name = "Monotonic timer", +}; + +static int pnx8xxx_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + write_c0_compare(delta); + return 0; +} + +static struct clock_event_device pnx8xxx_clockevent = { + .name = "pnx8xxx_clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = pnx8xxx_set_next_event, +}; + +static inline void timer_ack(void) +{ + write_c0_compare(cpj); +} + +__init void plat_time_init(void) +{ + unsigned int configPR; + unsigned int n; + unsigned int m; + unsigned int p; + unsigned int pow2p; + + clockevents_register_device(&pnx8xxx_clockevent); + clocksource_register(&pnx_clocksource); + + /* Timer 1 start */ + configPR = read_c0_config7(); + configPR &= ~0x00000008; + write_c0_config7(configPR); + + /* Timer 2 start */ + configPR = read_c0_config7(); + configPR &= ~0x00000010; + write_c0_config7(configPR); + + /* Timer 3 stop */ + configPR = read_c0_config7(); + configPR |= 0x00000020; + write_c0_config7(configPR); + + + /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */ + /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */ + + n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16; + m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8; + p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2; + pow2p = (1 << p); + + db_assert(m != 0 && pow2p != 0); + + /* + * Compute the frequency as in the PNX8550 User Manual 1.0, p.186 + * (a.k.a. 8-10). Divide by HZ for a timer offset that results in + * HZ timer interrupts per second. + */ + mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); + cpj = (mips_hpt_frequency + HZ / 2) / HZ; + write_c0_count(0); + timer_ack(); + + /* Setup Timer 2 */ + write_c0_count2(0); + write_c0_compare2(0xffffffff); + + setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); + setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); +} diff --git a/arch/mips/nxp/pnx8550/jbs/Makefile b/arch/mips/nxp/pnx8550/jbs/Makefile new file mode 100644 index 0000000..ad6a8ca --- /dev/null +++ b/arch/mips/nxp/pnx8550/jbs/Makefile @@ -0,0 +1,4 @@ + +# Makefile for the NXP JBS Board. + +lib-y := init.o board_setup.o irqmap.o diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c new file mode 100644 index 0000000..f92826e --- /dev/null +++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c @@ -0,0 +1,65 @@ +/* + * JBS Specific board startup routines. + * + * Copyright 2005, Embedded Alley Solutions, Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +void __init board_setup(void) +{ + unsigned long config0, configpr; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7<<25) | (7<<28)); + config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | + (CONF_CM_DEFAULT<<28)); + write_c0_config(config0); + BARRIER; + + configpr = read_c0_config7(); + configpr |= (1<<19); /* enable tlb */ + write_c0_config7(configpr); + BARRIER; +} diff --git a/arch/mips/nxp/pnx8550/jbs/init.c b/arch/mips/nxp/pnx8550/jbs/init.c new file mode 100644 index 0000000..d59b4a4 --- /dev/null +++ b/arch/mips/nxp/pnx8550/jbs/init.c @@ -0,0 +1,53 @@ +/* + * + * Copyright 2005 Embedded Alley Solutions, Inc + * source@embeddedalley.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "NXP PNX8550/JBS"; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + //memsize = 0x02800000; /* Trimedia uses memory above */ + memsize = 0x08000000; /* Trimedia uses memory above */ + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/arch/mips/nxp/pnx8550/jbs/irqmap.c b/arch/mips/nxp/pnx8550/jbs/irqmap.c new file mode 100644 index 0000000..7fc8984 --- /dev/null +++ b/arch/mips/nxp/pnx8550/jbs/irqmap.c @@ -0,0 +1,35 @@ +/* + * NXP JBS board irqmap. + * + * Copyright 2005 Embedded Alley Solutions, Inc + * source@embeddealley.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +char pnx8550_irq_tab[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +}; diff --git a/arch/mips/nxp/pnx8550/stb810/Makefile b/arch/mips/nxp/pnx8550/stb810/Makefile new file mode 100644 index 0000000..ab91d72 --- /dev/null +++ b/arch/mips/nxp/pnx8550/stb810/Makefile @@ -0,0 +1,4 @@ + +# Makefile for the NXP STB810 Board. + +lib-y := prom_init.o board_setup.o irqmap.o diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/nxp/pnx8550/stb810/board_setup.c new file mode 100644 index 0000000..1282c27 --- /dev/null +++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c @@ -0,0 +1,49 @@ +/* + * STB810 specific board startup routines. + * + * Based on the arch/mips/nxp/pnx8550/jbs/board_setup.c + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +void __init board_setup(void) +{ + unsigned long config0, configpr; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7<<25) | (7<<28)); + config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | + (CONF_CM_DEFAULT<<28)); + write_c0_config(config0); + + configpr = read_c0_config7(); + configpr |= (1<<19); /* enable tlb */ + write_c0_config7(configpr); +} diff --git a/arch/mips/nxp/pnx8550/stb810/irqmap.c b/arch/mips/nxp/pnx8550/stb810/irqmap.c new file mode 100644 index 0000000..8c03496 --- /dev/null +++ b/arch/mips/nxp/pnx8550/stb810/irqmap.c @@ -0,0 +1,22 @@ +/* + * NXP STB810 board irqmap. + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +char pnx8550_irq_tab[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +}; diff --git a/arch/mips/nxp/pnx8550/stb810/prom_init.c b/arch/mips/nxp/pnx8550/stb810/prom_init.c new file mode 100644 index 0000000..ca7f4ad --- /dev/null +++ b/arch/mips/nxp/pnx8550/stb810/prom_init.c @@ -0,0 +1,46 @@ +/* + * STB810 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "NXP PNX8950/STB810"; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + + prom_init_cmdline(); + + memsize = 0x08000000; /* Trimedia uses memory above */ + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/arch/mips/philips/pnx8550/common/Makefile b/arch/mips/philips/pnx8550/common/Makefile deleted file mode 100644 index 31cc1a5..0000000 --- a/arch/mips/philips/pnx8550/common/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# Per Hallsmark, per.hallsmark@mvista.com -# -# ######################################################################## -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# ####################################################################### -# -# Makefile for the PNX8550 specific kernel interface routines -# under Linux. -# - -obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_KGDB) += gdb_hook.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/philips/pnx8550/common/gdb_hook.c b/arch/mips/philips/pnx8550/common/gdb_hook.c deleted file mode 100644 index ad4624f..0000000 --- a/arch/mips/philips/pnx8550/common/gdb_hook.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * This is the interface to the remote debugger stub. - * - */ -#include -#include -#include -#include -#include - -#include -#include - -#include - -static struct serial_state rs_table[IP3106_NR_PORTS] = { -}; -static struct async_struct kdb_port_info = {0}; - -void rs_kgdb_hook(int tty_no) -{ - struct serial_state *ser = &rs_table[tty_no]; - - kdb_port_info.state = ser; - kdb_port_info.magic = SERIAL_MAGIC; - kdb_port_info.port = tty_no; - kdb_port_info.flags = ser->flags; - - /* - * Clear all interrupts - */ - /* Clear all the transmitter FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST; - /* Clear all the receiver FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST; - /* Clear all interrupts */ - ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX | - IP3106_UART_INT_ALLTX; - - /* - * Now, initialize the UART - */ - ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT; - ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud -} - -int putDebugChar(char c) -{ - /* Wait until FIFO not full */ - while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16) - ; - /* Send one char */ - ip3106_fifo(UART_BASE, kdb_port_info.port) = c; - - return 1; -} - -char getDebugChar(void) -{ - char ch; - - /* Wait until there is a char in the FIFO */ - while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) & - IP3106_UART_FIFO_RXFIFO) >> 8)) - ; - /* Read one char */ - ch = ip3106_fifo(UART_BASE, kdb_port_info.port) & - IP3106_UART_FIFO_RBRTHR; - /* Advance the RX FIFO read pointer */ - ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT; - return (ch); -} - -void rs_disable_debug_interrupts(void) -{ - ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */ -} - -void rs_enable_debug_interrupts(void) -{ - /* Clear all the transmitter FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST; - /* Clear all the receiver FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST; - /* Clear all interrupts */ - ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX | - IP3106_UART_INT_ALLTX; - ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */ -} diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c deleted file mode 100644 index aad0342..0000000 --- a/arch/mips/philips/pnx8550/common/int.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * - * Copyright (C) 2005 Embedded Alley Solutions, Inc - * Ported to 2.6. - * - * Per Hallsmark, per.hallsmark@mvista.com - * Copyright (C) 2000, 2001 MIPS Technologies, Inc. - * Copyright (C) 2001 Ralf Baechle - * - * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* default prio for interrupts */ -/* first one is a no-no so therefore always prio 0 (disabled) */ -static char gic_prio[PNX8550_INT_GIC_TOTINT] = { - 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49 - 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69 - 1 // 70 -}; - -static void hw0_irqdispatch(int irq) -{ - /* find out which interrupt */ - irq = PNX8550_GIC_VECTOR_0 >> 3; - - if (irq == 0) { - printk("hw0_irqdispatch: irq 0, spurious interrupt?\n"); - return; - } - do_IRQ(PNX8550_INT_GIC_MIN + irq); -} - - -static void timer_irqdispatch(int irq) -{ - irq = (0x01c0 & read_c0_config7()) >> 6; - - if (unlikely(irq == 0)) { - printk("timer_irqdispatch: irq 0, spurious interrupt?\n"); - return; - } - - if (irq & 0x1) - do_IRQ(PNX8550_INT_TIMER1); - if (irq & 0x2) - do_IRQ(PNX8550_INT_TIMER2); - if (irq & 0x4) - do_IRQ(PNX8550_INT_TIMER3); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP2) - hw0_irqdispatch(2); - else if (pending & STATUSF_IP7) { - if (read_c0_config7() & 0x01c0) - timer_irqdispatch(7); - } else - spurious_interrupt(); -} - -static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) -{ - unsigned long status = read_c0_status(); - - status &= ~((clr_mask & 0xFF) << 8); - status |= (set_mask & 0xFF) << 8; - - write_c0_status(status); -} - -static inline void mask_gic_int(unsigned int irq_nr) -{ - /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */ - PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */ -} - -static inline void unmask_gic_int(unsigned int irq_nr) -{ - /* set prio mask to lower four bits and enable interrupt */ - PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; -} - -static inline void mask_irq(unsigned int irq_nr) -{ - if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { - modify_cp0_intmask(1 << irq_nr, 0); - } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && - (irq_nr <= PNX8550_INT_GIC_MAX)) { - mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); - } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && - (irq_nr <= PNX8550_INT_TIMER_MAX)) { - modify_cp0_intmask(1 << 7, 0); - } else { - printk("mask_irq: irq %d doesn't exist!\n", irq_nr); - } -} - -static inline void unmask_irq(unsigned int irq_nr) -{ - if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { - modify_cp0_intmask(0, 1 << irq_nr); - } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && - (irq_nr <= PNX8550_INT_GIC_MAX)) { - unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); - } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && - (irq_nr <= PNX8550_INT_TIMER_MAX)) { - modify_cp0_intmask(0, 1 << 7); - } else { - printk("mask_irq: irq %d doesn't exist!\n", irq_nr); - } -} - -int pnx8550_set_gic_priority(int irq, int priority) -{ - int gic_irq = irq-PNX8550_INT_GIC_MIN; - int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf; - - gic_prio[gic_irq] = priority; - PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]); - - return prev_priority; -} - -static struct irq_chip level_irq_type = { - .name = "PNX Level IRQ", - .ack = mask_irq, - .mask = mask_irq, - .mask_ack = mask_irq, - .unmask = unmask_irq, -}; - -static struct irqaction gic_action = { - .handler = no_action, - .flags = IRQF_DISABLED, - .name = "GIC", -}; - -static struct irqaction timer_action = { - .handler = no_action, - .flags = IRQF_DISABLED, - .name = "Timer", -}; - -void __init arch_init_irq(void) -{ - int i; - int configPR; - - for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); - mask_irq(i); /* mask the irq just in case */ - } - - /* init of GIC/IPC interrupts */ - /* should be done before cp0 since cp0 init enables the GIC int */ - for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) { - int gic_int_line = i - PNX8550_INT_GIC_MIN; - if (gic_int_line == 0 ) - continue; // don't fiddle with int 0 - /* - * enable change of TARGET, ENABLE and ACTIVE_LOW bits - * set TARGET 0 to route through hw0 interrupt - * set ACTIVE_LOW 0 active high (correct?) - * - * We really should setup an interrupt description table - * to do this nicely. - * Note, PCI INTA is active low on the bus, but inverted - * in the GIC, so to us it's active high. - */ - PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000; - - /* mask/priority is still 0 so we will not get any - * interrupts until it is unmasked */ - - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); - } - - /* Priority level 0 */ - PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0; - - /* Set int vector table address */ - PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; - - set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, - handle_level_irq); - setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); - - /* init of Timer interrupts */ - for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); - - /* Stop Timer 1-3 */ - configPR = read_c0_config7(); - configPR |= 0x00000038; - write_c0_config7(configPR); - - set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, - handle_level_irq); - setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); -} - -EXPORT_SYMBOL(pnx8550_set_gic_priority); diff --git a/arch/mips/philips/pnx8550/common/pci.c b/arch/mips/philips/pnx8550/common/pci.c deleted file mode 100644 index eee4f3d..0000000 --- a/arch/mips/philips/pnx8550/common/pci.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include - -#include -#include -#include - -static struct resource pci_io_resource = { - .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */ - .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE, - .name = "pci IO space", - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .start = PNX8550_PCIMEM, - .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1, - .name = "pci memory space", - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops pnx8550_pci_ops; - -static struct pci_controller pnx8550_controller = { - .pci_ops = &pnx8550_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; - -/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ -static inline unsigned long get_system_mem_size(void) -{ - /* Read IP2031_RANK0_ADDR_LO */ - unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); - /* Read IP2031_RANK1_ADDR_HI */ - unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); - - return dram_r1_hi - dram_r0_lo + 1; -} - -static int __init pnx8550_pci_setup(void) -{ - int pci_mem_code; - int mem_size = get_system_mem_size() >> 20; - - /* Clear the Global 2 Register, PCI Inta Output Enable Registers - Bit 1:Enable DAC Powerdown - -> 0:DACs are enabled and are working normally - 1:DACs are powerdown - Bit 0:Enable of PCI inta output - -> 0 = Disable PCI inta output - 1 = Enable PCI inta output - */ - PNX8550_GLB2_ENAB_INTA_O = 0; - - /* Calc the PCI mem size code */ - if (mem_size >= 128) - pci_mem_code = SIZE_128M; - else if (mem_size >= 64) - pci_mem_code = SIZE_64M; - else if (mem_size >= 32) - pci_mem_code = SIZE_32M; - else - pci_mem_code = SIZE_16M; - - /* Set PCI_XIO registers */ - outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO); - outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI); - outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO); - outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI); - - /* Send memory transaction via PCI_BASE2 */ - outl(0x00000001, PCI_BASE | PCI_IO); - - /* Unlock the setup register */ - outl(0xca, PCI_BASE | PCI_UNLOCKREG); - - /* - * BAR0 of PNX8550 (pci base 10) must be zero in order for ide - * to work, and in order for bus_to_baddr to work without any - * hacks. - */ - outl(0x00000000, PCI_BASE | PCI_BASE10); - - /* - *These two bars are set by default or the boot code. - * However, it's safer to set them here so we're not boot - * code dependent. - */ - outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */ - outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */ - - outl(PCI_EN_TA | - PCI_EN_PCI2MMI | - PCI_EN_XIO | - PCI_SETUP_BASE18_SIZE(SIZE_32M) | - PCI_SETUP_BASE18_EN | - PCI_SETUP_BASE14_EN | - PCI_SETUP_BASE10_PREF | - PCI_SETUP_BASE10_SIZE(pci_mem_code) | - PCI_SETUP_CFGMANAGE_EN | - PCI_SETUP_PCIARB_EN, - PCI_BASE | - PCI_SETUP); /* PCI_SETUP */ - outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */ - - register_pci_controller(&pnx8550_controller); - - return 0; -} - -arch_initcall(pnx8550_pci_setup); diff --git a/arch/mips/philips/pnx8550/common/platform.c b/arch/mips/philips/pnx8550/common/platform.c deleted file mode 100644 index c839436..0000000 --- a/arch/mips/philips/pnx8550/common/platform.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Platform device support for Philips PNX8550 SoCs - * - * Copyright 2005, Embedded Alley Solutions, Inc - * - * Based on arch/mips/au1000/common/platform.c - * Platform device support for Au1x00 SoCs. - * - * Copyright 2004, Matt Porter - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static struct resource pnx8550_usb_ohci_resources[] = { - [0] = { - .start = PNX8550_USB_OHCI_OP_BASE, - .end = PNX8550_USB_OHCI_OP_BASE + - PNX8550_USB_OHCI_OP_LEN, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PNX8550_INT_USB, - .end = PNX8550_INT_USB, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource pnx8550_uart_resources[] = { - [0] = { - .start = PNX8550_UART_PORT0, - .end = PNX8550_UART_PORT0 + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PNX8550_UART_INT(0), - .end = PNX8550_UART_INT(0), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = PNX8550_UART_PORT1, - .end = PNX8550_UART_PORT1 + 0xfff, - .flags = IORESOURCE_MEM, - }, - [3] = { - .start = PNX8550_UART_INT(1), - .end = PNX8550_UART_INT(1), - .flags = IORESOURCE_IRQ, - }, -}; - -struct pnx8xxx_port pnx8xxx_ports[] = { - [0] = { - .port = { - .type = PORT_PNX8XXX, - .iotype = UPIO_MEM, - .membase = (void __iomem *)PNX8550_UART_PORT0, - .mapbase = PNX8550_UART_PORT0, - .irq = PNX8550_UART_INT(0), - .uartclk = 3692300, - .fifosize = 16, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - }, - [1] = { - .port = { - .type = PORT_PNX8XXX, - .iotype = UPIO_MEM, - .membase = (void __iomem *)PNX8550_UART_PORT1, - .mapbase = PNX8550_UART_PORT1, - .irq = PNX8550_UART_INT(1), - .uartclk = 3692300, - .fifosize = 16, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - }, -}; - -/* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = ~(u32)0; - -static u64 uart_dmamask = ~(u32)0; - -static struct platform_device pnx8550_usb_ohci_device = { - .name = "pnx8550-ohci", - .id = -1, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources), - .resource = pnx8550_usb_ohci_resources, -}; - -static struct platform_device pnx8550_uart_device = { - .name = "pnx8xxx-uart", - .id = -1, - .dev = { - .dma_mask = &uart_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = pnx8xxx_ports, - }, - .num_resources = ARRAY_SIZE(pnx8550_uart_resources), - .resource = pnx8550_uart_resources, -}; - -static struct platform_device *pnx8550_platform_devices[] __initdata = { - &pnx8550_usb_ohci_device, - &pnx8550_uart_device, -}; - -static int __init pnx8550_platform_init(void) -{ - return platform_add_devices(pnx8550_platform_devices, - ARRAY_SIZE(pnx8550_platform_devices)); -} - -arch_initcall(pnx8550_platform_init); diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c deleted file mode 100644 index 18b125e..0000000 --- a/arch/mips/philips/pnx8550/common/proc.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - - -static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) -{ - int len = 0; - int configPR = read_c0_config7(); - - if (offset==0) { - len += sprintf(&page[len], "Timer: count, compare, tc, status\n"); - len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n", - read_c0_count(), read_c0_compare(), - (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); - len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n", - read_c0_count2(), read_c0_compare2(), - (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); - len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n", - read_c0_count3(), read_c0_compare3(), - (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); - } - - return len; -} - -static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) -{ - int len = 0; - - if (offset==0) { - len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1()); - len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2()); - len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3()); - len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7()); - len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status()); - len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause()); - len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count()); - len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2()); - len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3()); - len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare()); - len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2()); - len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3()); - } - - return len; -} - -static struct proc_dir_entry* pnx8550_dir = NULL; -static struct proc_dir_entry* pnx8550_timers = NULL; -static struct proc_dir_entry* pnx8550_registers = NULL; - -static int pnx8550_proc_init( void ) -{ - - // Create /proc/pnx8550 - pnx8550_dir = proc_mkdir("pnx8550", NULL); - if (!pnx8550_dir) { - printk(KERN_ERR "Can't create pnx8550 proc dir\n"); - return -1; - } - - // Create /proc/pnx8550/timers - pnx8550_timers = create_proc_read_entry( - "timers", - 0, - pnx8550_dir, - pnx8550_timers_read, - NULL); - - if (!pnx8550_timers) - printk(KERN_ERR "Can't create pnx8550 timers proc file\n"); - - // Create /proc/pnx8550/registers - pnx8550_registers = create_proc_read_entry( - "registers", - 0, - pnx8550_dir, - pnx8550_registers_read, - NULL); - - if (!pnx8550_registers) - printk(KERN_ERR "Can't create pnx8550 registers proc file\n"); - - return 0; -} - -__initcall(pnx8550_proc_init); diff --git a/arch/mips/philips/pnx8550/common/prom.c b/arch/mips/philips/pnx8550/common/prom.c deleted file mode 100644 index 2f56745..0000000 --- a/arch/mips/philips/pnx8550/common/prom.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * - * Per Hallsmark, per.hallsmark@mvista.com - * - * Based on jmr3927/common/prom.c - * - * 2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include - -#include -#include - -/* #define DEBUG_CMDLINE */ - -extern int prom_argc; -extern char **prom_argv, **prom_envp; - -typedef struct -{ - char *name; -/* char *val; */ -}t_env_var; - - -char * prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - int i; - - arcs_cmdline[0] = '\0'; - for (i = 0; i < prom_argc; i++) { - strcat(arcs_cmdline, prom_argv[i]); - strcat(arcs_cmdline, " "); - } -} - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * Environment variables are stored in the form of "memsize=64". - */ - - t_env_var *env = (t_env_var *)prom_envp; - int i; - - i = strlen(envname); - - while(env->name) { - if(strncmp(envname, env->name, i) == 0) { - return(env->name + strlen(envname) + 1); - } - env++; - } - return(NULL); -} - -inline unsigned char str2hexnum(unsigned char c) -{ - if(c >= '0' && c <= '9') - return c - '0'; - if(c >= 'a' && c <= 'f') - return c - 'a' + 10; - if(c >= 'A' && c <= 'F') - return c - 'A' + 10; - return 0; /* foo */ -} - -inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for(i = 0; i < 6; i++) { - unsigned char num; - - if((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - return 0; -} - -void __init prom_free_prom_memory(void) -{ -} - -extern int pnx8550_console_port; - -/* used by early printk */ -void prom_putchar(char c) -{ - if (pnx8550_console_port != -1) { - /* Wait until FIFO not full */ - while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16) - ; - /* Send one char */ - ip3106_fifo(UART_BASE, pnx8550_console_port) = c; - } -} - -EXPORT_SYMBOL(prom_getcmdline); -EXPORT_SYMBOL(get_ethernet_addr); -EXPORT_SYMBOL(str2eaddr); diff --git a/arch/mips/philips/pnx8550/common/reset.c b/arch/mips/philips/pnx8550/common/reset.c deleted file mode 100644 index 7b2cbc5..0000000 --- a/arch/mips/philips/pnx8550/common/reset.c +++ /dev/null @@ -1,49 +0,0 @@ -/*. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Reset the PNX8550 board. - * - */ -#include -#include -#include - -void pnx8550_machine_restart(char *command) -{ - char head[] = "************* Machine restart *************"; - char foot[] = "*******************************************"; - - printk("\n\n"); - printk("%s\n", head); - if (command != NULL) - printk("* %s\n", command); - printk("%s\n", foot); - - PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST; -} - -void pnx8550_machine_halt(void) -{ - printk("*** Machine halt. (Not implemented) ***\n"); -} - -void pnx8550_machine_power_off(void) -{ - printk("*** Machine power off. (Not implemented) ***\n"); -} diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c deleted file mode 100644 index 92d764c..0000000 --- a/arch/mips/philips/pnx8550/common/setup.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * - * 2.6 port, Embedded Alley Solutions, Inc - * - * Based on Per Hallsmark, per.hallsmark@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -extern void __init board_setup(void); -extern void pnx8550_machine_restart(char *); -extern void pnx8550_machine_halt(void); -extern void pnx8550_machine_power_off(void); -extern struct resource ioport_resource; -extern struct resource iomem_resource; -extern void rs_kgdb_hook(int tty_no); -extern char *prom_getcmdline(void); - -struct resource standard_io_resources[] = { - { - .start = 0x00, - .end = 0x1f, - .name = "dma1", - .flags = IORESOURCE_BUSY - }, { - .start = 0x40, - .end = 0x5f, - .name = "timer", - .flags = IORESOURCE_BUSY - }, { - .start = 0x80, - .end = 0x8f, - .name = "dma page reg", - .flags = IORESOURCE_BUSY - }, { - .start = 0xc0, - .end = 0xdf, - .name = "dma2", - .flags = IORESOURCE_BUSY - }, -}; - -#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources) - -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ -unsigned long get_system_mem_size(void) -{ - /* Read IP2031_RANK0_ADDR_LO */ - unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); - /* Read IP2031_RANK1_ADDR_HI */ - unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); - - return dram_r1_hi - dram_r0_lo + 1; -} - -int pnx8550_console_port = -1; - -void __init plat_mem_setup(void) -{ - int i; - char* argptr; - - board_setup(); /* board specific setup */ - - _machine_restart = pnx8550_machine_restart; - _machine_halt = pnx8550_machine_halt; - pm_power_off = pnx8550_machine_power_off; - - /* Clear the Global 2 Register, PCI Inta Output Enable Registers - Bit 1:Enable DAC Powerdown - -> 0:DACs are enabled and are working normally - 1:DACs are powerdown - Bit 0:Enable of PCI inta output - -> 0 = Disable PCI inta output - 1 = Enable PCI inta output - */ - PNX8550_GLB2_ENAB_INTA_O = 0; - - /* IO/MEM resources. */ - set_io_port_base(KSEG1); - ioport_resource.start = 0; - ioport_resource.end = ~0; - iomem_resource.start = 0; - iomem_resource.end = ~0; - - /* Request I/O space for devices on this board */ - for (i = 0; i < STANDARD_IO_RESOURCES; i++) - request_resource(&ioport_resource, standard_io_resources + i); - - /* Place the Mode Control bit for GPIO pin 16 in primary function */ - /* Pin 16 is used by UART1, UA1_TX */ - outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) | - (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT), - PNX8550_GPIO_MC1); - - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "console=ttyS")) != NULL) { - argptr += strlen("console=ttyS"); - pnx8550_console_port = *argptr == '0' ? 0 : 1; - - /* We must initialize the UART (console) before early printk */ - /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ - ip3106_lcr(UART_BASE, pnx8550_console_port) = - PNX8XXX_UART_LCR_8BIT; - ip3106_baud(UART_BASE, pnx8550_console_port) = 5; - } - -#ifdef CONFIG_KGDB - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { - int line; - argptr += strlen("kgdb=ttyS"); - line = *argptr == '0' ? 0 : 1; - rs_kgdb_hook(line); - pr_info("KGDB: Using ttyS%i for session, " - "please connect your debugger\n", line ? 1 : 0); - } -#endif - return; -} diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c deleted file mode 100644 index 62f495b..0000000 --- a/arch/mips/philips/pnx8550/common/time.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright 2001, 2002, 2003 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - * - * Common time service routines for MIPS machines. See - * Documents/MIPS/README.txt. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -static unsigned long cpj; - -static cycle_t hpt_read(void) -{ - return read_c0_count2(); -} - -static struct clocksource pnx_clocksource = { - .name = "pnx8xxx", - .rating = 200, - .read = hpt_read, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *c = dev_id; - - /* clear MATCH, signal the event */ - c->event_handler(c); - - return IRQ_HANDLED; -} - -static struct irqaction pnx8xxx_timer_irq = { - .handler = pnx8xxx_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, - .name = "pnx8xxx_timer", -}; - -static irqreturn_t monotonic_interrupt(int irq, void *dev_id) -{ - /* Timer 2 clear interrupt */ - write_c0_compare2(-1); - return IRQ_HANDLED; -} - -static struct irqaction monotonic_irqaction = { - .handler = monotonic_interrupt, - .flags = IRQF_DISABLED, - .name = "Monotonic timer", -}; - -static int pnx8xxx_set_next_event(unsigned long delta, - struct clock_event_device *evt) -{ - write_c0_compare(delta); - return 0; -} - -static struct clock_event_device pnx8xxx_clockevent = { - .name = "pnx8xxx_clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = pnx8xxx_set_next_event, -}; - -static inline void timer_ack(void) -{ - write_c0_compare(cpj); -} - -__init void plat_time_init(void) -{ - unsigned int configPR; - unsigned int n; - unsigned int m; - unsigned int p; - unsigned int pow2p; - - clockevents_register_device(&pnx8xxx_clockevent); - clocksource_register(&pnx_clocksource); - - /* Timer 1 start */ - configPR = read_c0_config7(); - configPR &= ~0x00000008; - write_c0_config7(configPR); - - /* Timer 2 start */ - configPR = read_c0_config7(); - configPR &= ~0x00000010; - write_c0_config7(configPR); - - /* Timer 3 stop */ - configPR = read_c0_config7(); - configPR |= 0x00000020; - write_c0_config7(configPR); - - - /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */ - /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */ - - n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16; - m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8; - p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2; - pow2p = (1 << p); - - db_assert(m != 0 && pow2p != 0); - - /* - * Compute the frequency as in the PNX8550 User Manual 1.0, p.186 - * (a.k.a. 8-10). Divide by HZ for a timer offset that results in - * HZ timer interrupts per second. - */ - mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); - cpj = (mips_hpt_frequency + HZ / 2) / HZ; - write_c0_count(0); - timer_ack(); - - /* Setup Timer 2 */ - write_c0_count2(0); - write_c0_compare2(0xffffffff); - - setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); - setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); -} diff --git a/arch/mips/philips/pnx8550/jbs/Makefile b/arch/mips/philips/pnx8550/jbs/Makefile deleted file mode 100644 index e8228db..0000000 --- a/arch/mips/philips/pnx8550/jbs/Makefile +++ /dev/null @@ -1,4 +0,0 @@ - -# Makefile for the Philips JBS Board. - -lib-y := init.o board_setup.o irqmap.o diff --git a/arch/mips/philips/pnx8550/jbs/board_setup.c b/arch/mips/philips/pnx8550/jbs/board_setup.c deleted file mode 100644 index f92826e..0000000 --- a/arch/mips/philips/pnx8550/jbs/board_setup.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * JBS Specific board startup routines. - * - * Copyright 2005, Embedded Alley Solutions, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") - -void __init board_setup(void) -{ - unsigned long config0, configpr; - - config0 = read_c0_config(); - - /* clear all three cache coherency fields */ - config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); - write_c0_config(config0); - BARRIER; - - configpr = read_c0_config7(); - configpr |= (1<<19); /* enable tlb */ - write_c0_config7(configpr); - BARRIER; -} diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c deleted file mode 100644 index 90b4d35..0000000 --- a/arch/mips/philips/pnx8550/jbs/init.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * Copyright 2005 Embedded Alley Solutions, Inc - * source@embeddedalley.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -int prom_argc; -char **prom_argv, **prom_envp; -extern void __init prom_init_cmdline(void); -extern char *prom_getenv(char *envname); - -const char *get_system_type(void) -{ - return "Philips PNX8550/JBS"; -} - -void __init prom_init(void) -{ - unsigned long memsize; - - //memsize = 0x02800000; /* Trimedia uses memory above */ - memsize = 0x08000000; /* Trimedia uses memory above */ - add_memory_region(0, memsize, BOOT_MEM_RAM); -} diff --git a/arch/mips/philips/pnx8550/jbs/irqmap.c b/arch/mips/philips/pnx8550/jbs/irqmap.c deleted file mode 100644 index 98c3429..0000000 --- a/arch/mips/philips/pnx8550/jbs/irqmap.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Philips JBS board irqmap. - * - * Copyright 2005 Embedded Alley Solutions, Inc - * source@embeddealley.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include - -char pnx8550_irq_tab[][5] __initdata = { - [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, - [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, - [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, -}; - diff --git a/arch/mips/philips/pnx8550/stb810/Makefile b/arch/mips/philips/pnx8550/stb810/Makefile deleted file mode 100644 index f14b592..0000000 --- a/arch/mips/philips/pnx8550/stb810/Makefile +++ /dev/null @@ -1,4 +0,0 @@ - -# Makefile for the Philips STB810 Board. - -lib-y := prom_init.o board_setup.o irqmap.o diff --git a/arch/mips/philips/pnx8550/stb810/board_setup.c b/arch/mips/philips/pnx8550/stb810/board_setup.c deleted file mode 100644 index 345d71e..0000000 --- a/arch/mips/philips/pnx8550/stb810/board_setup.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * STB810 specific board startup routines. - * - * Based on the arch/mips/philips/pnx8550/jbs/board_setup.c - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -void __init board_setup(void) -{ - unsigned long config0, configpr; - - config0 = read_c0_config(); - - /* clear all three cache coherency fields */ - config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); - write_c0_config(config0); - - configpr = read_c0_config7(); - configpr |= (1<<19); /* enable tlb */ - write_c0_config7(configpr); -} diff --git a/arch/mips/philips/pnx8550/stb810/irqmap.c b/arch/mips/philips/pnx8550/stb810/irqmap.c deleted file mode 100644 index 5ee11e1..0000000 --- a/arch/mips/philips/pnx8550/stb810/irqmap.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Philips STB810 board irqmap. - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -char pnx8550_irq_tab[][5] __initdata = { - [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, - [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, - [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, -}; - diff --git a/arch/mips/philips/pnx8550/stb810/prom_init.c b/arch/mips/philips/pnx8550/stb810/prom_init.c deleted file mode 100644 index 832dd60..0000000 --- a/arch/mips/philips/pnx8550/stb810/prom_init.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * STB810 specific prom routines - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -int prom_argc; -char **prom_argv, **prom_envp; -extern void __init prom_init_cmdline(void); -extern char *prom_getenv(char *envname); - -const char *get_system_type(void) -{ - return "Philips PNX8550/STB810"; -} - -void __init prom_init(void) -{ - unsigned long memsize; - - prom_argc = (int) fw_arg0; - prom_argv = (char **) fw_arg1; - prom_envp = (char **) fw_arg2; - - prom_init_cmdline(); - - memsize = 0x08000000; /* Trimedia uses memory above */ - add_memory_region(0, memsize, BOOT_MEM_RAM); -} diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index bf5bbc7..6723c95 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -29,7 +29,7 @@ #define PRID_COMP_ALCHEMY 0x030000 #define PRID_COMP_SIBYTE 0x040000 #define PRID_COMP_SANDCRAFT 0x050000 -#define PRID_COMP_PHILIPS 0x060000 +#define PRID_COMP_NXP 0x060000 #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index e62058b..f18d281 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -273,7 +273,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, * memory-like regions on I/O busses. */ #define ioremap_cachable(offset, size) \ - __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT) + __ioremap_mode((offset), (size), _page_cachable_default) /* * These two are MIPS specific ioremap variant. ioremap_cacheable_cow diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index 1c39d33..33407be 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -68,6 +68,7 @@ #define MIPS_REVISION_CORID_CORE_FPGA3 9 #define MIPS_REVISION_CORID_CORE_24K 10 #define MIPS_REVISION_CORID_CORE_FPGA4 11 +#define MIPS_REVISION_CORID_CORE_FPGA5 12 /**** Artificial corid defines ****/ /* diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index a094709..6847c73 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -105,7 +105,7 @@ static inline void pmd_clear(pmd_t *pmdp) pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); } -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define pte_page(x) pfn_to_page(pte_pfn(x)) #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) static inline pte_t @@ -128,7 +128,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) #endif -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */ +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ #define __pgd_offset(address) pgd_index(address) #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 7494ba9..60e2f93 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -32,14 +32,14 @@ * unpredictable things. The code (when it is written) to deal with * this problem will be in the update_mmu_cache() code for the r4k. */ -#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define _PAGE_PRESENT (1<<6) /* implemented in software */ #define _PAGE_READ (1<<7) /* implemented in software */ #define _PAGE_WRITE (1<<8) /* implemented in software */ #define _PAGE_ACCESSED (1<<9) /* implemented in software */ #define _PAGE_MODIFIED (1<<10) /* implemented in software */ -#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ +#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ #define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */ #define _PAGE_GLOBAL (1<<0) @@ -47,15 +47,9 @@ #define _PAGE_SILENT_READ (1<<1) /* synonym */ #define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ #define _PAGE_SILENT_WRITE (1<<2) +#define _CACHE_SHIFT 3 #define _CACHE_MASK (7<<3) -/* MIPS32 defines only values 2 and 3. The rest are implementation - * dependent. - */ -#define _CACHE_UNCACHED (2<<3) -#define _CACHE_CACHABLE_NONCOHERENT (3<<3) -#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */ - #else #define _PAGE_PRESENT (1<<0) /* implemented in software */ @@ -74,75 +68,72 @@ #define _PAGE_SILENT_WRITE (1<<10) #define _CACHE_UNCACHED (1<<11) #define _CACHE_MASK (1<<11) -#define _CACHE_CACHABLE_NONCOHERENT 0 #else + #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ #define _PAGE_GLOBAL (1<<6) #define _PAGE_VALID (1<<7) #define _PAGE_SILENT_READ (1<<7) /* synonym */ #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ #define _PAGE_SILENT_WRITE (1<<8) +#define _CACHE_SHIFT 9 #define _CACHE_MASK (7<<9) -#ifdef CONFIG_CPU_SB1 +#endif +#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ + + +/* + * Cache attributes + */ +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +#define _CACHE_CACHABLE_NONCOHERENT 0 + +#elif defined(CONFIG_CPU_SB1) /* No penalty for being coherent on the SB1, so just use it for "noncoherent" spaces, too. Shouldn't hurt. */ -#define _CACHE_UNCACHED (2<<9) -#define _CACHE_CACHABLE_COW (5<<9) -#define _CACHE_CACHABLE_NONCOHERENT (5<<9) -#define _CACHE_UNCACHED_ACCELERATED (7<<9) +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) +#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) #elif defined(CONFIG_CPU_RM9000) -#define _CACHE_WT (0 << 9) -#define _CACHE_WTWA (1 << 9) -#define _CACHE_UC_B (2 << 9) -#define _CACHE_WB (3 << 9) -#define _CACHE_CWBEA (4 << 9) -#define _CACHE_CWB (5 << 9) -#define _CACHE_UCNB (6 << 9) -#define _CACHE_FPC (7 << 9) +#define _CACHE_WT (0<<_CACHE_SHIFT) +#define _CACHE_WTWA (1<<_CACHE_SHIFT) +#define _CACHE_UC_B (2<<_CACHE_SHIFT) +#define _CACHE_WB (3<<_CACHE_SHIFT) +#define _CACHE_CWBEA (4<<_CACHE_SHIFT) +#define _CACHE_CWB (5<<_CACHE_SHIFT) +#define _CACHE_UCNB (6<<_CACHE_SHIFT) +#define _CACHE_FPC (7<<_CACHE_SHIFT) -#define _CACHE_UNCACHED _CACHE_UC_B -#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB +#define _CACHE_UNCACHED _CACHE_UC_B +#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB #else -#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ -#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ +#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ +#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ +#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ +#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ #endif -#endif -#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */ #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#ifdef CONFIG_MIPS_UNCACHED -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif defined(CONFIG_DMA_NONCOHERENT) -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#elif defined(CONFIG_CPU_RM9000) -#define PAGE_CACHABLE_DEFAULT _CACHE_CWB -#else -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW -#endif - -#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) -#else -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) -#endif +#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT) #endif /* _ASM_PGTABLE_BITS_H */ diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 17a7703..582f56f 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -23,15 +23,15 @@ struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ - _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) + _PAGE_GLOBAL | _page_cachable_default) #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -40,23 +40,30 @@ struct vm_area_struct; * read. Also, write permissions imply read permissions. This is the closest * we can get by reasonable means.. */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED + +/* + * Dummy values to fill the table in mmap.c + * The real values will be generated at runtime + */ +#define __P000 __pgprot(0) +#define __P001 __pgprot(0) +#define __P010 __pgprot(0) +#define __P011 __pgprot(0) +#define __P100 __pgprot(0) +#define __P101 __pgprot(0) +#define __P110 __pgprot(0) +#define __P111 __pgprot(0) + +#define __S000 __pgprot(0) +#define __S001 __pgprot(0) +#define __S010 __pgprot(0) +#define __S011 __pgprot(0) +#define __S100 __pgprot(0) +#define __S101 __pgprot(0) +#define __S110 __pgprot(0) +#define __S111 __pgprot(0) + +extern unsigned long _page_cachable_default; /* * ZERO_PAGE is a global shared page that is always zero; used @@ -79,7 +86,7 @@ extern void paging_init(void); #define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) #define pmd_page_vaddr(pmd) pmd_val(pmd) -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) @@ -182,7 +189,7 @@ extern pgd_t swapper_pg_dir[]; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } @@ -309,7 +316,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot) */ #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { pte.pte_low &= _PAGE_CHG_MASK;