Subject: Update interrupt mapping for the Axon south bridge
From: Murali Iyer <mniyer@us.ibm.com>

Slide down the SPE and IPI IRQs to make room
for Axon southbridge interrupts

Signed-off-by: Murali Iyer <mniyer@us.ibm.com>
Signed-off-by: Shaun Wetzstein <shaun@us.ibm.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>

Index: linux-2.6.16/arch/powerpc/platforms/cell/interrupt.h
===================================================================
--- linux-2.6.16.orig/arch/powerpc/platforms/cell/interrupt.h
+++ linux-2.6.16/arch/powerpc/platforms/cell/interrupt.h
@@ -38,12 +38,12 @@
 
 enum {
 	IIC_EXT_OFFSET   = 0x00, /* Start of south bridge IRQs */
-	IIC_NUM_EXT      = 0x40, /* Number of south bridge IRQs */
-	IIC_SPE_OFFSET   = 0x40, /* Start of SPE interrupts */
+	IIC_NUM_EXT      = 0x80, /* Number of south bridge IRQs */
+	IIC_SPE_OFFSET   = 0x80, /* Start of SPE interrupts */
 	IIC_CLASS_STRIDE = 0x10, /* SPE IRQs per class    */
-	IIC_IPI_OFFSET   = 0x70, /* Start of IPI IRQs */
+	IIC_IPI_OFFSET   = 0xB0, /* Start of IPI IRQs */
 	IIC_NUM_IPIS     = 0x10, /* IRQs reserved for IPI */
-	IIC_NODE_STRIDE  = 0x80, /* Total IRQs per node   */
+	IIC_NODE_STRIDE  = 0x100, /* Total IRQs per node   */
 };
 
 struct iic_pending_bits {