Subject: cell: fake mmu_psize array to enable 64k pages

Firmware currently does not have the right properties for
enabling 64k pages, so just claim we have them anyway.
Obviously, this patch must not get merged, instead the
firmware will have to fix their device tree.

Similarly, the firmware does not set up HID6 correctly
and we need some more changes to have that done for
secondary CPUs.

Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
---

Index: linus-2.6/arch/powerpc/mm/hash_utils_64.c
===================================================================
--- linus-2.6.orig/arch/powerpc/mm/hash_utils_64.c
+++ linus-2.6/arch/powerpc/mm/hash_utils_64.c
@@ -144,6 +144,30 @@ struct mmu_psize_def mmu_psize_defaults_
 	},
 };
 
+struct mmu_psize_def mmu_psize_defaults_cell[] = {
+	[MMU_PAGE_4K] = {
+		.shift	= 12,
+		.sllp	= 0,
+		.penc	= 0,
+		.avpnm	= 0,
+		.tlbiel = 1,
+	},
+	[MMU_PAGE_64K] = {
+		.shift	= 16,
+		.sllp	= SLB_VSID_L | SLB_VSID_LP_01,
+		.penc	= 1,
+		.avpnm	= 0,
+		.tlbiel = 1,
+	},
+	[MMU_PAGE_16M] = {
+		.shift	= 24,
+		.sllp	= SLB_VSID_L,
+		.penc	= 0,
+		.avpnm	= 0x1UL,
+		.tlbiel = 0,
+	},
+};
+
 
 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 		      unsigned long pstart, unsigned long mode, int psize)
@@ -294,6 +318,12 @@ static void __init htab_init_page_sizes(
 	memcpy(mmu_psize_defs, mmu_psize_defaults_old,
 	       sizeof(mmu_psize_defaults_old));
 
+	if (machine_is(cell)) {
+		memcpy(mmu_psize_defs, mmu_psize_defaults_cell,
+		       sizeof(mmu_psize_defaults_cell));
+		goto found;
+	}
+
 	/*
 	 * Try to find the available page sizes in the device-tree
 	 */
Index: linus-2.6/arch/powerpc/kernel/cpu_setup_power4.S
===================================================================
--- linus-2.6.orig/arch/powerpc/kernel/cpu_setup_power4.S
+++ linus-2.6/arch/powerpc/kernel/cpu_setup_power4.S
@@ -93,6 +93,7 @@ _GLOBAL(__setup_cpu_ppc970)
 #define CS_HID1		8
 #define	CS_HID4		16
 #define CS_HID5		24
+#define CS_HID6		0 /* for CBE */
 #define CS_SIZE		32
 
 	.data
@@ -115,17 +116,19 @@ _GLOBAL(__save_cpu_setup)
 	/* Get storage ptr */
 	LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
 
-	/* We only deal with 970 for now */
+	/* We only deal with 970 and cbe for now */
 	mfspr	r0,SPRN_PVR
 	srwi	r0,r0,16
+	cmpwi	r0,0x70
+	beq	2f
 	cmpwi	r0,0x39
 	beq	1f
 	cmpwi	r0,0x3c
 	beq	1f
 	cmpwi	r0,0x44
-	bne	2f
+	bne	3f
 
-1:	/* Save HID0,1,4 and 5 */
+1:	/* 970: Save HID0,1,4 and 5 */
 	mfspr	r3,SPRN_HID0
 	std	r3,CS_HID0(r5)
 	mfspr	r3,SPRN_HID1
@@ -134,8 +137,13 @@ _GLOBAL(__save_cpu_setup)
 	std	r3,CS_HID4(r5)
 	mfspr	r3,SPRN_HID5
 	std	r3,CS_HID5(r5)
+	b	3f
+
+2:	/* cbe: save HID6 */
+	mfspr	r3,SPRN_HID6
+	std	r3,CS_HID6(r5)
 
-2:
+3:
 	mtcr	r7
 	blr
 
@@ -152,6 +160,8 @@ _GLOBAL(__restore_cpu_setup)
 	/* We only deal with 970 for now */
 	mfspr	r0,SPRN_PVR
 	srwi	r0,r0,16
+	cmpwi	r0,0x70
+	beq	2f
 	cmpwi	r0,0x39
 	beq	1f
 	cmpwi	r0,0x3c
@@ -159,6 +169,8 @@ _GLOBAL(__restore_cpu_setup)
 	cmpwi	r0,0x44
 	bnelr
 
+
+/* setup for 970 */
 1:	/* Before accessing memory, we make sure rm_ci is clear */
 	li	r0,0
 	mfspr	r3,SPRN_HID4
@@ -214,3 +226,8 @@ _GLOBAL(__restore_cpu_setup)
 	isync
 	blr
 
+/* setup for cbe */
+2:	/* restore HID6 */
+	ld	r3,CS_HID6(r5)
+	mtspr	SPRN_HID6,r3
+	blr