IA64: Fix up PGD offset calculation in nested_dtlb handler The nested_dtlb handler does not properly isolate the region offset for the pgd offset calculation. It takes the address including the region and simply right shifts. This will mean that the region may show up in multiple locations of the generated offset. We can avoid that issue by generating the offset from register r21 instead that contains the address without the region number shifted 3 bits righ. If we add 3 bits to the existing shift then we get the right offset. Signed-off-by: Christoph Lameter Index: linux-2.6.18-mm3/arch/ia64/kernel/ivt.S =================================================================== --- linux-2.6.18-mm3.orig/arch/ia64/kernel/ivt.S 2006-10-07 18:05:52.615960757 -0700 +++ linux-2.6.18-mm3/arch/ia64/kernel/ivt.S 2006-10-08 17:57:38.175470725 -0700 @@ -445,10 +445,10 @@ ENTRY(nested_dtlb_miss) ;; cmp.eq p6,p7=5,r17 // is faulting address in region 5? add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address - add r18=PGDIR_SHIFT-PAGE_SHIFT,r18 + add r18=PGDIR_SHIFT-PAGE_SHIFT+3,r18 ;; shr.u r22=r16,r22 - shr.u r18=r16,r18 + shr.u r18=r21,r18 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place srlz.d