From dan.yeisley@unisys.com Mon Dec 5 05:59:09 2005 From: Daniel Yeisley Subject: PCI Quirk: 1K I/O space granularity on Intel P64H2 To: gregkh@suse.de Date: Mon, 05 Dec 2005 07:06:43 -0500 Message-Id: <1133784403.15921.33.camel@localhost.localdomain> I've implemented a quirk to take advantage of the 1KB I/O space granularity option on the Intel P64H2 PCI Bridge. I had to change probe.c because it sets the resource start and end to be aligned on 4k boundaries (after the quirk sets them to 1k boundaries). I've tested this patch on a Unisys ES7000-600 both with and without the 1KB option enabled. I also tested this on a 2 processor Dell box that doesn't have a P64H2 to make sure there were no negative affects there. Signed-off-by: Dan Yeisley Signed-off-by: Greg Kroah-Hartman --- drivers/pci/probe.c | 6 ++++-- drivers/pci/quirks.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-) --- gregkh-2.6.orig/drivers/pci/probe.c +++ gregkh-2.6/drivers/pci/probe.c @@ -264,8 +264,10 @@ void __devinit pci_read_bridge_bases(str if (base <= limit) { res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; - res->start = base; - res->end = limit + 0xfff; + if (!res->start) + res->start = base; + if (!res->end) + res->end = limit + 0xfff; } res = child->resource[1]; --- gregkh-2.6.orig/drivers/pci/quirks.c +++ gregkh-2.6/drivers/pci/quirks.c @@ -1342,6 +1342,32 @@ void pci_fixup_device(enum pci_fixup_pas pci_do_fixups(dev, start, end); } +/* Enable 1k I/O space granularity on the Intel P64H2 */ +static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) +{ + u16 en1k; + u8 io_base_lo, io_limit_lo; + unsigned long base, limit; + struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; + + pci_read_config_word(dev, 0x40, &en1k); + + if (en1k & 0x200) { + printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); + + pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); + pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); + base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; + limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; + + if (base <= limit) { + res->start = base; + res->end = limit + 0x3ff; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); + EXPORT_SYMBOL(pcie_mch_quirk); #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(pci_fixup_device);