From kaneshige.kenji@jp.fujitsu.com Wed Nov 23 18:43:14 2005 Message-ID: <438527E1.20709@jp.fujitsu.com> Date: Thu, 24 Nov 2005 11:39:29 +0900 From: Kenji Kaneshige To: Greg KH , CC: Kenji Kaneshige Subject: shpchp: fix improper write to Command Completion Detect bit Current SHPCHP driver writes a '0' to the Command Completion Detect bit to clear the Command Complete Interrupt Pending. But according to the SHPC spec (See 4.7.3.1 System Interrupts), SHPCHP driver must write '1'. This patch fixes this bug. Signed-off-by: Kenji Kaneshige Signed-off-by: Greg Kroah-Hartman --- drivers/pci/hotplug/shpchp_hpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- gregkh-2.6.orig/drivers/pci/hotplug/shpchp_hpc.c +++ gregkh-2.6/drivers/pci/hotplug/shpchp_hpc.c @@ -1058,11 +1058,11 @@ static irqreturn_t shpc_isr(int IRQ, voi if (intr_loc & 0x0001) { /* * Command Complete Interrupt Pending - * RO only - clear by writing 0 to the Command Completion + * RO only - clear by writing 1 to the Command Completion * Detect bit in Controller SERR-INT register */ temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); - temp_dword &= 0xfffeffff; + temp_dword &= 0xfffdffff; writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); wake_up_interruptible(&ctrl->queue); }