diff --git a/src/i830_driver.c b/src/i830_driver.c
index a19c8eb..969468d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2099,21 +2099,27 @@ RestoreHWState(ScrnInfoPtr pScrn)
    OUTREG(VCLK_DIVISOR_VGA0, pI830->saveVCLK_DIVISOR_VGA0);
    OUTREG(VCLK_DIVISOR_VGA1, pI830->saveVCLK_DIVISOR_VGA1);
    OUTREG(VCLK_POST_DIV, pI830->saveVCLK_POST_DIV);
+   /* make sure the VGA regs are up to date before we enable the DPLLs */
+   POSTING_READ(VCLK_POST_DIV);
 
    /* If the pipe A PLL is active, we can restore the pipe & plane config */
    if (pI830->saveDPLL_A & DPLL_VCO_ENABLE)
    {
       OUTREG(DPLL_A, pI830->saveDPLL_A & ~DPLL_VCO_ENABLE);
+      POSTING_READ(DPLL_A);
       usleep(150);
    }
    OUTREG(FPA0, pI830->saveFPA0);
    OUTREG(FPA1, pI830->saveFPA1);
+   POSTING_READ(FPA1); /* make sure they hit before we enable */
    OUTREG(DPLL_A, pI830->saveDPLL_A);
+   POSTING_READ(DPLL_A); /* flush it out */
    i830_dpll_settle();
    if (IS_I965G(pI830))
       OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD);
    else
       OUTREG(DPLL_A, pI830->saveDPLL_A);
+   POSTING_READ(DPLL_A); /* flush again */
    i830_dpll_settle();
 
    /* Restore mode config */
@@ -2130,13 +2136,16 @@ RestoreHWState(ScrnInfoPtr pScrn)
    OUTREG(DSPAPOS, pI830->saveDSPAPOS);
    OUTREG(PIPEASRC, pI830->savePIPEASRC);
    OUTREG(DSPABASE, pI830->saveDSPABASE);
+   POSTING_READ(DSPABASE); /* make sure it hits before we enable the pipe */
    if (IS_I965G(pI830))
    {
       OUTREG(DSPASURF, pI830->saveDSPASURF);
       OUTREG(DSPATILEOFF, pI830->saveDSPATILEOFF);
+      POSTING_READ(DSPASURF); /* again, before pipe enable */
    }
 
    OUTREG(PIPEACONF, pI830->savePIPEACONF);
+   POSTING_READ(PIPEACONF); /* flush it out */
    i830WaitForVblank(pScrn);
 
    /*
@@ -2165,16 +2174,20 @@ RestoreHWState(ScrnInfoPtr pScrn)
       if (pI830->saveDPLL_B & DPLL_VCO_ENABLE)
       {
 	 OUTREG(DPLL_B, pI830->saveDPLL_B & ~DPLL_VCO_ENABLE);
+	 POSTING_READ(DPLL_B);
 	 usleep(150);
       }
       OUTREG(FPB0, pI830->saveFPB0);
       OUTREG(FPB1, pI830->saveFPB1);
+      POSTING_READ(FPB1); /* make sure they hit before we enable */
       OUTREG(DPLL_B, pI830->saveDPLL_B);
+      POSTING_READ(DPLL_B); /* flush it out */
       i830_dpll_settle();
       if (IS_I965G(pI830))
 	 OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD);
       else
 	 OUTREG(DPLL_B, pI830->saveDPLL_B);
+      POSTING_READ(DPLL_B); /* flush again */
       i830_dpll_settle();
    
       /* Restore mode config */
@@ -2190,13 +2203,16 @@ RestoreHWState(ScrnInfoPtr pScrn)
       OUTREG(DSPBPOS, pI830->saveDSPBPOS);
       OUTREG(PIPEBSRC, pI830->savePIPEBSRC);
       OUTREG(DSPBBASE, pI830->saveDSPBBASE);
+      POSTING_READ(DSPBBASE); /* make sure it hits before we enable the pipe */
       if (IS_I965G(pI830))
       {
 	 OUTREG(DSPBSURF, pI830->saveDSPBSURF);
 	 OUTREG(DSPBTILEOFF, pI830->saveDSPBTILEOFF);
+	 POSTING_READ(DSPBSURF); /* again, before pipe enable */
       }
 
       OUTREG(PIPEBCONF, pI830->savePIPEBCONF);
+      POSTING_READ(PIPEBCONF); /* flush it out */
       i830WaitForVblank(pScrn);
 
       /*
@@ -2219,6 +2235,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
    }
 
    OUTREG(VGACNTRL, pI830->saveVGACNTRL);
+   POSTING_READ(VGACNTRL); /* flush it out before we hit the palettes */
 
    /* Restore outputs */
    for (i = 0; i < xf86_config->num_output; i++) {