From pfg@sgi.com Wed May 12 13:05:21 2004 Return-Path: X-Original-To: jbarnes@spamtin.engr.sgi.com Delivered-To: jbarnes@spamtin.engr.sgi.com Received: from internal-mail-relay.corp.sgi.com (internal-mail-relay.corp.sgi.com [198.149.32.51]) by spamtin.engr.sgi.com (Postfix) with ESMTP id 2E7BF2405455 for ; Wed, 12 May 2004 13:05:23 -0700 (PDT) Received: from cthulhu.engr.sgi.com (cthulhu.engr.sgi.com [192.26.80.2]) by internal-mail-relay.corp.sgi.com (8.12.9/8.12.10/SGI_generic_relay-1.2) with ESMTP id i4CK5Mfu43141500; Wed, 12 May 2004 13:05:22 -0700 (PDT) Received: from info.engr.sgi.com (info.engr.sgi.com [192.26.80.216]) by cthulhu.engr.sgi.com (SGI-8.12.5/8.12.5) with ESMTP id i4CK5L7510035603; Wed, 12 May 2004 13:05:21 -0700 (PDT) Received: from info.engr.sgi.com (localhost [127.0.0.1]) by info.engr.sgi.com (SGI-8.12.5/8.12.5) with ESMTP id i4CK5Lla15403427; Wed, 12 May 2004 13:05:21 -0700 (PDT) Received: (from sgiweb@localhost) by info.engr.sgi.com (SGI-8.12.5/8.12.5/Submit) id i4CK5Lm511043638; Wed, 12 May 2004 13:05:21 -0700 (PDT) Date: Wed, 12 May 2004 13:05:21 -0700 (PDT) Message-Id: <200405122005.i4CK5Lm511043638@info.engr.sgi.com> X-BugWorks-Action: ADD X-BugWorks-Incident: 914286 X-BugWorks-Changed: incident_id X-BugWorks-Interface: BugWorks X-BugWorks-To: pfg@sgi.com kaos@sgi.com X-BugWorks-Cc: erikj@sgi.com steiner@sgi.com ioif@sgi.com jbarnes@sgi.com Reply-To: sgi.bugs.snlinux@fido.engr.sgi.com Errors-To: bugworks@sgi.com References: From: pfg@sgi.com (pfg@sgi.com via BugWorks) Subject: ADD 914286 - 2.6.6 PCI bridge errors To: undisclosed-recipients:; X-Spam-Checker-Version: SpamAssassin 2.63 (2004-01-11) on spamtin.engr.sgi.com X-Spam-Level: X-Spam-Status: No, hits=-4.9 required=5.0 tests=BAYES_00 autolearn=ham version=2.63 Status: R X-Status: N X-KMail-EncryptionState: X-KMail-SignatureState: X-KMail-MDN-Sent: View Incident: http://co-op.engr.sgi.com/BugWorks/query.cgi/914286 Status: open Priority: 2 Assigned Group: linux-ioinfr Project: snlinux Assigned Engineer: pfg Submitter: kaos CC List: erikj steiner ioif jbarnes Opened Date: 05/09/04 Booting kernel.org-sgidev 2.6.6 tree on budgie.melbourne gets these PCI error messages. They do not appear with 2.6.5 on the same system. Boot processor id 0x0/0x0 task migration cache decay timeout: 10 msecs. CPU 1: base freq=200.000MHz, ITC ratio=13/2, ITC freq=1300.000MHz+/--1ppm Calibrating delay loop... 16.44 BogoMIPS CPU 2: base freq=200.000MHz, ITC ratio=13/2, ITC freq=1300.000MHz+/--1ppm Calibrating delay loop... 16.44 BogoMIPS ..... ========================== ADDITIONAL INFORMATION (ADD) From: pfg@sgi.com (BugWorks) Date: May 12 2004 01:05:21PM ========================== I have a patch that should fix this. Can you apply and boot and make sure it does ? Thanks. --- 0/linux/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c +++ 1/linux/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c @@ -1615,6 +1615,46 @@ piomap->bp_kvaddr + offset, len, valp); } +static uint64_t +pcibr_disable_mst_timeout(pcibr_soft_t pcibr_soft) +{ + uint64_t old_enable; + uint64_t new_enable; + uint64_t intr_bits; + + intr_bits = PIC_ISR_PCI_MST_TIMEOUT + | PIC_ISR_PCIX_MTOUT | PIC_ISR_PCIX_SPLIT_EMSG; + old_enable = pcireg_intr_enable_get(pcibr_soft); + pcireg_intr_enable_bit_clr(pcibr_soft, intr_bits); + new_enable = pcireg_intr_enable_get(pcibr_soft); + + if (old_enable == new_enable) { + return 0; /* was already disabled */ + } else { + return 1; + } +} + +static int +pcibr_enable_mst_timeout(pcibr_soft_t pcibr_soft) +{ + uint64_t old_enable; + uint64_t new_enable; + uint64_t intr_bits; + + intr_bits = PIC_ISR_PCI_MST_TIMEOUT + | PIC_ISR_PCIX_MTOUT | PIC_ISR_PCIX_SPLIT_EMSG; + old_enable = pcireg_intr_enable_get(pcibr_soft); + pcireg_intr_enable_bit_set(pcibr_soft, intr_bits); + new_enable = pcireg_intr_enable_get(pcibr_soft); + + if (old_enable == new_enable) { + return 0; /* was alread enabled */ + } else { + return 1; + } +} + /* * pcibr_probe_slot: read a config space word * while trapping any errors; return zero if @@ -1628,7 +1668,7 @@ int len, void *valp) { - int rv; + int rv, changed; /* * Sanity checks ... @@ -1642,15 +1682,19 @@ return -1; /* invalid alignment */ } + changed = pcibr_disable_mst_timeout(pcibr_soft); + rv = snia_badaddr_val((void *)addr, len, valp); /* Clear the int_view register incase it was set */ pcireg_intr_reset_set(pcibr_soft, BRIDGE_IRR_MULTI_CLR); + if (changed) { + pcibr_enable_mst_timeout(pcibr_soft); + } return (rv ? 1 : 0); /* return 1 for snia_badaddr_val error, 0 if ok */ } - void pcibr_device_info_free(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot) {