===== arch/ia64/sn/io/machvec/pci_bus_cvlink.c 1.38 vs edited =====
--- 1.38/arch/ia64/sn/io/machvec/pci_bus_cvlink.c	Wed Apr 28 09:20:53 2004
+++ edited/arch/ia64/sn/io/machvec/pci_bus_cvlink.c	Wed May 12 11:53:18 2004
@@ -328,6 +328,34 @@
 			cmd |= PCI_COMMAND_MEMORY;
 	}
 
+        /*
+	 * Assign addresses to the ROMs, but don't enable them yet
+	 * Also note that we only map display card ROMs due to PIO mapping
+	 * space scarcity.
+	 */
+        if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
+                unsigned long addr;
+                size = dev->resource[PCI_ROM_RESOURCE].end -
+                        dev->resource[PCI_ROM_RESOURCE].start;
+
+                if (size) {
+                        addr = (unsigned long) pciio_pio_addr(vhdl, 0,
+					      PCIIO_SPACE_ROM,
+					      0, size, 0, PIOMAP_FIXED);
+                        if (!addr) {
+                                dev->resource[PCI_ROM_RESOURCE].start = 0;
+                                dev->resource[PCI_ROM_RESOURCE].end = 0;
+                                printk("sn_pci_fixup(): ROM pio map failure "
+				       "for %s\n", dev->slot_name);
+                        }
+                        addr |= __IA64_UNCACHED_OFFSET;
+                        dev->resource[PCI_ROM_RESOURCE].start = addr;
+                        dev->resource[PCI_ROM_RESOURCE].end = addr + size;
+                        if (dev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_MEM)
+                                cmd |= PCI_COMMAND_MEMORY;
+                }
+        }
+
 	/*
 	 * Update the Command Word on the Card.
 	 */