Index: extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h =================================================================== RCS file: /cvs/xorg/xc/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h,v retrieving revision 1.1.1.1 diff -u -r1.1.1.1 radeon_dri.h --- extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h 16 Jun 2004 09:18:24 -0000 1.1.1.1 +++ extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h 10 Jan 2005 19:30:42 -0000 @@ -54,7 +54,7 @@ #define RADEON_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */ #define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */ #define RADEON_DEFAULT_PAGE_FLIP 0 /* page flipping diabled */ -#define RADEON_BUFFER_ALIGN 0x00000fff +#define RADEON_BUFFER_ALIGN 0x0000ffff /** * \brief Radeon DRI driver private data. Index: extras/drm/shared/radeon_cp.c =================================================================== RCS file: /cvs/xorg/xc/extras/drm/shared/radeon_cp.c,v retrieving revision 1.1.1.1 diff -u -r1.1.1.1 radeon_cp.c --- extras/drm/shared/radeon_cp.c 16 Jun 2004 09:16:10 -0000 1.1.1.1 +++ extras/drm/shared/radeon_cp.c 10 Jan 2005 19:30:43 -0000 @@ -36,7 +36,268 @@ #define RADEON_FIFO_DEBUG 0 +#if 1 +static u32 R200_cp_microcode[][2] { + { 0x4200e000, 0000000000 }, // 00: iREQ;oAddr=base;oDATA=PM4;oREQ;oRDY;base++; + { 0x4000e000, 0000000000 }, // 01: iREQ;oAddr=base;oDATA=PM4;oREQ;oRDY; + { 0x000000b3, 0x00000008 }, // 02: goto @P_PACKETTYPE1; + { 0x000000b7, 0x00000008 }, // 03: goto @DP_GUI_MASTER_CNTL_HANDLER; + { 0x6c5a504f, 0000000000 }, // 04: constBytes % @H_NOP,@H_PAINT,@H_BITBLT,@H_SMALLTEXT; + { 0x4f4f497a, 0000000000 }, // 05: constBytes % @H_HOSTDATA_R3BLT,@H_POLYLINE,@H_NOP,@H_NOP; + { 0x5a578288, 0000000000 }, // 06: constBytes % @H_POLYSCANLINE,@H_NEXTCHAR,@H_PAINT_BB,@H_BITBLT; + { 0x4f91906a, 0000000000 }, // 07: constBytes % @H_BITBLT_TRANSPARENT,@H_PLY_NEXTSCAN,@H_SETSCISSORS,@H_NOP; + { 0x4f4f4f4f, 0000000000 }, // 08: constBytes % @H_NOP,@H_NOP,@H_NOP,@H_NOP; + { 0x4fe64f44, 0000000000 }, // 09: constBytes % @H_LOADMICROCODE,@H_NOP,@WAIT_FOR_IDLE,@H_NOP; + { 0xe99c9c9c, 0000000000 }, // 0A: constBytes % @H_3D_DRAW_VBUF,@H_3D_DRAW_IMMD,@H_3D_DRAW_INDX,@H_3D_DRAW_N3FV3F; + { 0xe04ff0e2, 0000000000 }, // 0B: constBytes % @H_LOAD_PALETTE,@H_3D_DRAW_V3F,@H_NOP,@H_3D_LOAD_VBPNTR; + { 0xa1d14f4f, 0000000000 }, // 0C: constBytes % @H_NOP,@H_NOP,@H_3D_CLEAR_ZMASK,@H_INDX_BUFFER; + { 0xd69d9d9d, 0000000000 }, // 0D: constBytes % @H_3D_DRAW_VBUF_2,@H_3D_DRAW_IMMD_2,@H_3D_DRAW_INDX_2,@H_3D_CLEAR_HIZ; + { 0x4f0f9fdb, 0000000000 }, // 0E: constBytes % @H_3D_CLEAR_CMASK,@H_3D_DRAW_128,@H_MPEG_INDEX,@H_NOP; + { 0x000ca000, 0x00000004 }, // 0F: @H_MPEG_INDEX: iREQ;oRDY;acc=pm4;cont; + { 0x000d0012, 0x00000038 }, // 10: jacceven @MPI_0;acc=acc>>1; + { 0x0000e8b4, 0x00000004 }, // 11: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PVS_CODE_CNTL_0;cont; + { 0x000d0014, 0x00000038 }, // 12: @MPI_0: jacceven @MPI_1;acc=acc>>1; + { 0x0000e8b6, 0x00000004 }, // 13: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PVS_CODE_CNTL_1;cont; + { 0x000d0016, 0x00000038 }, // 14: @MPI_1: jacceven @MPI_2;acc=acc>>1; + { 0x0000e854, 0x00000004 }, // 15: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_0;cont; + { 0x000d0018, 0x00000038 }, // 16: @MPI_2: jacceven @MPI_3;acc=acc>>1; + { 0x0000e855, 0x00000004 }, // 17: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_1;cont; + { 0x000d001a, 0x00000038 }, // 18: @MPI_3: jacceven @MPI_4;acc=acc>>1; + { 0x0000e856, 0x00000004 }, // 19: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_2;cont; + { 0x000d001c, 0x00000038 }, // 1A: @MPI_4: jacceven @MPI_5;acc=acc>>1; + { 0x0000e857, 0x00000004 }, // 1B: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_3;cont; + { 0x000d001e, 0x00000038 }, // 1C: @MPI_5: jacceven @MPI_6;acc=acc>>1; + { 0x0000e824, 0x00000004 }, // 1D: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_OUT_VTX_FMT_0;cont; + { 0x000d0020, 0x00000038 }, // 1E: @MPI_6: jacceven @MPI_7;acc=acc>>1; + { 0x0000e825, 0x00000004 }, // 1F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_OUT_VTX_FMT_1;cont; + { 0x000d0022, 0x00000038 }, // 20: @MPI_7: jacceven @MPI_8;acc=acc>>1; + { 0x0000e830, 0x00000004 }, // 21: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_NUM_ARRAYS;cont; + { 0x000d0024, 0x00000038 }, // 22: @MPI_8: jacceven @MPI_9;acc=acc>>1; + { 0x0000f0c0, 0x00000004 }, // 23: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRS_COUNT;cont; + { 0x000d0026, 0x00000038 }, // 24: @MPI_9: jacceven @MPI_10;acc=acc>>1; + { 0x0000f0c1, 0x00000004 }, // 25: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRS_INST_COUNT;cont; + { 0x000d0028, 0x00000038 }, // 26: @MPI_10: jacceven @MPI_11;acc=acc>>1; + { 0x0000f041, 0x00000004 }, // 27: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmTX_ENABLE;cont; + { 0x000d002a, 0x00000038 }, // 28: @MPI_11: jacceven @MPI_12;acc=acc>>1; + { 0x0000f184, 0x00000004 }, // 29: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_0;cont; + { 0x000d002c, 0x00000038 }, // 2A: @MPI_12: jacceven @MPI_13;acc=acc>>1; + { 0x0000f185, 0x00000004 }, // 2B: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_1;cont; + { 0x000d002e, 0x00000038 }, // 2C: @MPI_13: jacceven @MPI_14;acc=acc>>1; + { 0x0000f186, 0x00000004 }, // 2D: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_2;cont; + { 0x000d0030, 0x00000038 }, // 2E: @MPI_14: jacceven @MPI_15;acc=acc>>1; + { 0x0000f187, 0x00000004 }, // 2F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_3;cont; + { 0x000d0032, 0x00000038 }, // 30: @MPI_15: jacceven @MPI_16;acc=acc>>1; + { 0x0000f180, 0x00000004 }, // 31: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CONFIG;cont; + { 0x000d0034, 0x00000038 }, // 32: @MPI_16: jacceven @MPI_17;acc=acc>>1; + { 0x0000f393, 0x00000004 }, // 33: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRB3D_DSTCACHE_CTLSTAT;cont; + { 0x000d0036, 0x00000038 }, // 34: @MPI_17: jacceven @MPI_18;acc=acc>>1; + { 0x0000f38a, 0x00000004 }, // 35: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRB3D_COLOROFFSET0;cont; + { 0x000d0038, 0x00000038 }, // 36: @MPI_18: jacceven @MPI_19;acc=acc>>1; + { 0x0000f38e, 0x00000004 }, // 37: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRB3D_COLORPITCH0;cont; + { 0x0000e821, 0x00000004 }, // 38: @MPI_19: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VF_CNTL;cont; + { 0x0140a000, 0x00000004 }, // 39: iREQ;oRDY;index=pm4[13:0];cont; + { 0x00000043, 0x00000018 }, // 3A: @MPI_INDEX_LOOP: jindexz @MPI_END; + { 0x00cce800, 0x00000004 }, // 3B: iREQ;oREQ;oRDY;acc=pm4;oaddr=ram;odata=pm4;address=mmVAP_PORT_DATA0;index--;cont; + { 0x001b0001, 0x00000004 }, // 3C: accl+=ram;address=01;cont; + { 0x08004800, 0x00000004 }, // 3D: oREQ;oaddr=ram;odata=acc;address=mmVAP_PORT_DATA0;cont; + { 0x001b0001, 0x00000004 }, // 3E: accl+=ram;address=01;cont; + { 0x08004800, 0x00000004 }, // 3F: oREQ;oaddr=ram;odata=acc;address=mmVAP_PORT_DATA0;cont; + { 0x001b0001, 0x00000004 }, // 40: accl+=ram;address=01;cont; + { 0x08004800, 0x00000004 }, // 41: oREQ;oaddr=ram;odata=acc;address=mmVAP_PORT_DATA0;cont; + { 0x0000003a, 0x00000008 }, // 42: goto @MPI_INDEX_LOOP; + { 0x0000a000, 0000000000 }, // 43: @MPI_END: iREQ;oRDY; + { 0x02c0a000, 0x00000004 }, // 44: @H_LOADMICROCODE: iREQ;oRDY;LDBASEINDEXPM4;cont; + { 0x000ca000, 0x00000004 }, // 45: @H_LOADMICROCODE_LOOP: iREQ;oRDY;acc=pm4;cont; + { 0x00130000, 0x00000004 }, // 46: scr=accl;cont; + { 0x000c2000, 0x00000004 }, // 47: iREQ;acc=pm4;cont; + { 0xc980c045, 0x00000008 }, // 48: oREQ;oRDY;oAddr=base;dst=ram;odata=acc;index-- base++;goto @H_LOADMICROCODE_LOOP; + { 0x2000451d, 0x00000004 }, // 49: @H_POLYLINE: oREQ;oaddr=ram;odata=0;address=mmBRUSH_Y_X;cont; + { 0x0000e580, 0x00000004 }, // 4A: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmDST_LINE_START;cont; + { 0x000ce581, 0x00000004 }, // 4B: iREQ;oREQ;oRDY;acc=pm4;oaddr=ram;odata=pm4;address=mmDST_LINE_END;cont; + { 0x08004580, 0x00000004 }, // 4C: @H_POLYLINE_LOOP: oREQ;oaddr=ram;odata=acc;address=mmDST_LINE_START;cont; + { 0x000ce581, 0x00000004 }, // 4D: iREQ;oREQ;oRDY;acc=pm4;oaddr=ram;odata=pm4;address=mmDST_LINE_END;cont; + { 0x0000004c, 0x00000008 }, // 4E: goto @H_POLYLINE_LOOP; + { 0x0000a000, 0000000000 }, // 4F: @H_NOP: iREQ;oRDY; + { 0x000c2000, 0x00000004 }, // 50: @H_PAINT: iREQ;acc=pm4;cont; + { 0x0000e50e, 0x00000004 }, // 51: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_Y_X;cont; + { 0x00032000, 0x00000004 }, // 52: iREQ;ACCL=pm4[15:0]-ACCL;cont; + { 0x00022056, 0x00000028 }, // 53: iREQ;ACCH=pm4[31:16]-ACCH;jacclsign @HH_PAINT_END; + { 0x00000056, 0x00000024 }, // 54: jacchsign @HH_PAINT_END; + { 0x0800450f, 0x00000004 }, // 55: oREQ;oData=acc;oAddr=ram;address=mmDST_HEIGHT_WIDTH;cont; + { 0x0000a050, 0x00000008 }, // 56: @HH_PAINT_END: iREQ;oRDY;goto @H_PAINT; + { 0x0000e565, 0x00000004 }, // 57: @H_PAINT_BB: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_X_Y;cont; + { 0x0000e566, 0x00000004 }, // 58: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_WIDTH_HEIGHT;cont; + { 0x00000057, 0x00000008 }, // 59: @HH_PAINT_BB_END: goto @H_PAINT_BB; + { 0x03cca5b4, 0x00000004 }, // 5A: @H_BITBLT_HACK: @H_BITBLT: iREQ;oRDY;acc=pm4;ldbase;address=mmDP_CNTL_XDIR_YDIR_YMAJOR;cont; + { 0x05432000, 0x00000004 }, // 5B: iREQ;accl=pm4[15:0]-accl;scr32=acc;cont; + { 0x00022000, 0x00000004 }, // 5C: iREQ;acch=pm4[31:16]-acch;cont; + { 0x4ccce063, 0x00000030 }, // 5D: iREQ;oREQ;oRDY;odata=acc;oaddr=base;base=accsign;acc=pm4;call @H_BITBLT_ADDHW; + { 0x08274565, 0x00000004 }, // 5E: oREQ;acc=scr32;odata=acc;oaddr=ram;address=mmDST_X_Y;cont; + { 0x00000063, 0x00000030 }, // 5F: call @H_BITBLT_ADDHW; + { 0x08004564, 0x00000004 }, // 60: oREQ;odata=acc;oaddr=ram;address=mmSRC_X_Y;cont; + { 0x0000e566, 0x00000004 }, // 61: iREQ;oREQ;oRDY;odata=pm4;oaddr=ram;address=mmDST_WIDTH_HEIGHT;cont; + { 0x0000005a, 0x00000008 }, // 62: goto @H_BITBLT_HACK; + { 0x00802066, 0x00000010 }, // 63: @H_BITBLT_ADDHW: iREQ;index++;jtstb @H_BITBLT_SKIPH; + { 0x00202000, 0x00000004 }, // 64: iREQ;accl=pm4[15:0]+accl;cont; + { 0x001b00ff, 0x00000004 }, // 65: accl+=ram;address=ff;cont; + { 0x01000069, 0x00000010 }, // 66: @H_BITBLT_SKIPH: index=0;jtstb @H_BITBLT_SKIPW; + { 0x001f2000, 0x00000004 }, // 67: iREQ;acch=pm4[31:16]+acch;cont; + { 0x001c00ff, 0x00000004 }, // 68: acch+=ram;address=ff;cont; + { 0000000000, 0x0000000c }, // 69: @H_BITBLT_SKIPW: retmark; + { 0x00000085, 0x00000030 }, // 6A: @H_BITBLT_TRANSPARENT: call @H_COLORCMP; + { 0x0000005a, 0x00000008 }, // 6B: goto @H_BITBLT; + { 0x0000e576, 0x00000004 }, // 6C: @H_SMALLTEXT: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDP_SRC_FRGD_CLR;cont; + { 0x000ca000, 0x00000004 }, // 6D: iREQ;acc=pm4;oRDY;cont; + { 0x00012000, 0x00000004 }, // 6E: @ST_CHARLOOP: iREQ;accl=pm4[7:0]+accl;cont; + { 0x00082000, 0x00000004 }, // 6F: iREQ;scr=acch-pm4[15:8];cont; + { 0x1800650e, 0x00000004 }, // 70: iREQ;oREQ;oData=scraccl;oAddr=ram;address=mmDST_Y_X;cont; + { 0x00092000, 0x00000004 }, // 71: iREQ;scr=pm4[31:24]*pm4[23:16];cont; + { 0x000a2000, 0x00000004 }, // 72: iREQ;scr=scr+31;oData=pm4;cont; + { 0x000f0000, 0x00000004 }, // 73: scr=scr>>5;cont; + { 0x00400000, 0x00000004 }, // 74: index=scr;cont; + { 0x00000079, 0x00000018 }, // 75: jindexz @ST_CHARLOOP_CONT; + { 0x0000e563, 0x00000004 }, // 76: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_WIDTH_8;cont; + { 0x00c0e5f0, 0x000000c2 }, // 77: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmHOST_DATA0;wc_indexnz;index--;ccont_indexz;vcnt_sel_index; + { 0x0000006e, 0x00000008 }, // 78: goto @ST_CHARLOOP; + { 0x0000a06e, 0x00000008 }, // 79: @ST_CHARLOOP_CONT: iREQ;oRDY;goto @ST_CHARLOOP; + { 0x0000e576, 0x00000004 }, // 7A: @H_HOSTDATA_R3BLT: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDP_SRC_FRGD_CLR;cont; + { 0x0000e577, 0x00000004 }, // 7B: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDP_SRC_BKGD_CLR;cont; + { 0x0000e50e, 0x00000004 }, // 7C: @HD_OUTERLOOPSTART: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_Y_X;cont; + { 0x0000e50f, 0x00000004 }, // 7D: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_WIDTH;cont; + { 0x0140a000, 0x00000004 }, // 7E: iREQ;oRDY;index=pm4[13:0];cont; + { 0x0000007c, 0x00000018 }, // 7F: @N_NEXTCHAR_CONT: jindexz @HD_OUTERLOOPSTART; + { 0x00c0e5f0, 0x000000c2 }, // 80: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmHOST_DATA0;index--;wc_indexnz;ccont_indexz;vcnt_sel_index; + { 0x0000007c, 0x00000008 }, // 81: goto @HD_OUTERLOOPSTART; + { 0x0014e50e, 0x00000004 }, // 82: @H_NEXTCHAR: iREQ;oREQ;oRDY;scr=acch;oData=pm4;oAddr=ram;address=mmDST_Y_X;cont; + { 0x0040e50f, 0x00000004 }, // 83: iREQ;oREQ;oRDY;index=scr;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_WIDTH;cont; + { 0x00c0007f, 0x00000008 }, // 84: index--;goto @N_NEXTCHAR_CONT; + { 0x0000e570, 0x00000004 }, // 85: @H_COLORCMP: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmCLR_CMP_CNTL;cont; + { 0x0000e571, 0x00000004 }, // 86: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmCLR_CMP_CLR_SRC;cont; + { 0x0000e572, 0x0000000c }, // 87: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmCLR_CMP_CLR_DST;retmark; + { 0x0000a000, 0x00000004 }, // 88: @H_POLYSCANLINE: iREQ;oRDY;cont; + { 0x0140a000, 0x00000004 }, // 89: @H_POLYSCANLINE1: iREQ;index=pm4[13:0];oRDY;cont; + { 0x0000e568, 0x00000004 }, // 8A: @H_POLYSCANLINE2: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_Y;cont; + { 0x000c2000, 0x00000004 }, // 8B: @PLY_SUBPACKETBODY: iREQ;acc=pm4;cont; + { 0x00000089, 0x00000018 }, // 8C: jindexz @H_POLYSCANLINE1; + { 0x000b0000, 0x00000004 }, // 8D: scr=acch-accl;cont; + { 0x18c0e562, 0x00000004 }, // 8E: iREQ;oREQ;oRDY;oData=scraccl;oAddr=ram;address=mmDST_WIDTH_X;index--;cont; + { 0x0000008b, 0x00000008 }, // 8F: goto @PLY_SUBPACKETBODY; + { 0x00c0008a, 0x00000008 }, // 90: @H_PLY_NEXTSCAN: index--;goto @H_POLYSCANLINE2; + { 0x000700e8, 0x00000004 }, // 91: @H_SETSCISSORS: acc=ram[addr];address=@V_24BPPMODE;cont; + { 0x00000097, 0x00000038 }, // 92: jacceven @H_SETSC_N24; + { 0x000ca099, 0x00000030 }, // 93: @H_SETSC_24: iREQ;oRDY;acc=pm4;call @SC_TRIPLICATEX; + { 0x080045bb, 0x00000004 }, // 94: oREQ;oData=acc;oAddr=ram;address=mmSC_TOP_LEFT;cont; + { 0x000c209a, 0x00000030 }, // 95: iREQ;acc=pm4;call @SC_TRIPLICATEX_A2; + { 0x0800e5bc, 0000000000 }, // 96: iREQ;oRDY;oREQ;oData=acc;oAddr=ram;address=mmSC_BOTTOM_RIGHT; + { 0x0000e5bb, 0x00000004 }, // 97: @H_SETSC_N24: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmSC_TOP_LEFT;cont; + { 0x0000e5bc, 0000000000 }, // 98: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmSC_BOTTOM_RIGHT; + { 0x00120000, 0x0000000c }, // 99: @SC_TRIPLICATEX: accl=accl*3;retmark; + { 0x00120000, 0x00000004 }, // 9A: @SC_TRIPLICATEX_A2: accl=accl*3;cont; + { 0x001b0002, 0x0000000c }, // 9B: accl+=ram;address=2;retmark; + { 0x0000a000, 0x00000004 }, // 9C: @H_3D_DRAW_VBUF: @H_3D_DRAW_IMMD: @H_3D_DRAW_INDX: iREQ;oRDY;cont; + { 0x0000e821, 0x00000004 }, // 9D: @H_3D_DRAW_VBUF_2: @H_3D_DRAW_IMMD_2: @H_3D_DRAW_INDX_2: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_VF_CNTL;cont; + { 0x0000e800, 0000000000 }, // 9E: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_PORT_DATA0; + { 0x0000e821, 0x00000004 }, // 9F: @H_3D_DRAW_128: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_VF_CNTL;cont; + { 0x0000e82e, 0000000000 }, // A0: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_PORT_DATA_IDX_128; + { 0x02cca000, 0x00000004 }, // A1: @H_INDX_BUFFER: iREQ;oRDY;ldbaseindexpm4;acc=pm4;cont; + { 0x00140000, 0x00000004 }, // A2: scr=acch;cont; + { 0x000ce1cc, 0x00000004 }, // A3: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmCP_IB2_BASE;acc=pm4;cont; + { 0x050de1cd, 0x00000004 }, // A4: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmCP_IB2_BUFSZ;cnt=pm4[22:0]-1;acc=acc>>1;cont; + { 0x00400000, 0x00000004 }, // A5: index=scr;cont; + { 0x000000a9, 0x00000018 }, // A6: @H_INDX_BUFFER_KILL: jindexz @H_INDX_BUFFER_CONT; + { 0x00c0a000, 0x00000004 }, // A7: iREQ;oRDY;index--;cont; + { 0x000000a6, 0x00000008 }, // A8: goto @H_INDX_BUFFER_KILL; + { 0x000000ab, 0x00000020 }, // A9: @H_INDX_BUFFER_CONT: jscrsign @H_INDEX_BUFFER_NOINC; + { 0x4200e000, 0000000000 }, // AA: iREQ;oRDY;oREQ;oData=pm4;oAddr=base;base++; + { 0x000000b2, 0x00000038 }, // AB: @H_INDEX_BUFFER_NOINC: jacceven @H_INDEX_ALIGNED; + { 0x000ca000, 0x00000004 }, // AC: iREQ;oRDY;acc=pm4;cont; + { 0x00140000, 0x00000004 }, // AD: scr=acch;cont; + { 0x000c2000, 0x00000004 }, // AE: @H_INDEX_WORD_LOOP: iREQ;acc=pm4;cont; + { 0x00160000, 0x00000004 }, // AF: acch=scr;cont; + { 0x700ce000, 0x00000004 }, // B0: iREQ;oRDY;oREQ;oData=acclacch;oAddr=base;acc=pm4;cont; + { 0x001400ae, 0x00000008 }, // B1: goto @H_INDEX_WORD_LOOP;scr=acch; + { 0x4000e000, 0000000000 }, // B2: @H_INDEX_ALIGNED: iREQ;oRDY;oREQ;oData=pm4;oAddr=base; + { 0x02400000, 0x00000004 }, // B3: @P_PACKETTYPE1: base=acc[10:0];cont; + { 0x400ee000, 0x00000004 }, // B4: iREQ;oREQ;oRDY;oAddr=base;acc=acc>>11;oData=pm4;cont; + { 0x02400000, 0x00000004 }, // B5: base=acc[10:0];cont; + { 0x4000e000, 0000000000 }, // B6: iREQ;oREQ;oRDY;oAddr=base;oData=pm4; + { 0x000c2000, 0x00000004 }, // B7: @DP_GUI_MASTER_CNTL_HANDLER: iREQ;ACC=PM4;cont; + { 0x0240e51b, 0x00000004 }, // B8: oREQ;iREQ;oDATA=pm4;base=acc[10:0];oRDY;cont;ADDRESS=mmDP_GUI_MASTER_CNTL; + { 0x0080e50a, 0x00000005 }, // B9: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSRC_PITCH_OFFSET;oAddr=ram;cont; + { 0x0080e50b, 0x00000005 }, // BA: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmDST_PITCH_OFFSET;oAddr=ram;cont; + { 0x00220000, 0x00000004 }, // BB: rf=acc;address=0;cont; + { 0x000700e8, 0x00000004 }, // BC: acc=ram[addr];address=@V_24BPPMODE;cont; + { 0x000000c5, 0x00000038 }, // BD: jacceven @GMC_SC_N24; + { 0x000c209a, 0x00000030 }, // BE: @GMC_SC_24: iREQ;acc=pm4;call @SC_TRIPLICATEX_A2; + { 0x0880e5bd, 0x00000005 }, // BF: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSRC_SC_BOTTOM_RIGHT;oAddr=ram;oData=acc;cont; + { 0x000c2099, 0x00000030 }, // C0: iREQ;acc=pm4;call @SC_TRIPLICATEX; + { 0x0800e5bb, 0x00000005 }, // C1: wc_tstb;iREQ;oREQ;oRDY;ADDRESS=mmSC_TOP_LEFT;oAddr=ram;oData=acc;cont; + { 0x000c209a, 0x00000030 }, // C2: iREQ;acc=pm4;call @SC_TRIPLICATEX_A2; + { 0x0880e5bc, 0x00000005 }, // C3: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSC_BOTTOM_RIGHT;oAddr=ram;oData=acc;cont; + { 0x000000c8, 0x00000008 }, // C4: goto @PR_LOADBRUSH; + { 0x0080e5bd, 0x00000005 }, // C5: @GMC_SC_N24: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSRC_SC_BOTTOM_RIGHT;oAddr=ram;cont; + { 0x0000e5bb, 0x00000005 }, // C6: wc_tstb;iREQ;oREQ;oRDY;ADDRESS=mmSC_TOP_LEFT;oAddr=ram;cont; + { 0x0080e5bc, 0x00000005 }, // C7: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSC_BOTTOM_RIGHT;oAddr=ram;cont; + { 0x00210000, 0x00000004 }, // C8: @PR_LOADBRUSH: acc=rf;address=0;cont; + { 0x02800000, 0x00000004 }, // C9: LDBRUSH;cont; + { 0x00c000cc, 0x00000018 }, // CA: index--;jindexz @PR_BRUSHLOOPEND; + { 0x4180e000, 0x00000040 }, // CB: @PR_BRUSHLOOPSTART: iREQ;oREQ;oAddr=base;oRDY;index-- base++;ccont_indexz; + { 0x000000ce, 0x00000024 }, // CC: @PR_BRUSHLOOPEND: jacchsign @PR_WR_BRUSH_Y_X; + { 0x01000000, 0x0000000c }, // CD: @PR_RET: index=0;retmark; + { 0x0100e51d, 0x0000000c }, // CE: @PR_WR_BRUSH_Y_X: index=0;iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmBRUSH_Y_X;retmark; + { 0x000045bb, 0x00000004 }, // CF: @GMC_SC_TL_OVERWRITE: oREQ;ADDRESS=mmSC_TOP_LEFT;oAddr=ram;oData=pm4;cont; + { 0x000080c8, 0x00000008 }, // D0: oRDY;goto @PR_LOADBRUSH; + { 0x0000f3ce, 0x00000004 }, // D1: @H_3D_CLEAR_ZMASK: iREQ;oRDY;oREQ;odata=pm4;oAddr=ram;address=mmZB_ZMASK_WRINDEX;cont; + { 0x0140a000, 0x00000004 }, // D2: iREQ;oRDY;index=pm4[13:0];cont; + { 0x00cc2000, 0x00000004 }, // D3: iREQ;acc=pm4;index--;cont; + { 0x08c053cf, 0x00000040 }, // D4: oREQ;odata=acc;oAddr=ram;address=mmZB_ZMASK_DWORD;index--;ccont_indexz; + { 0x00008000, 0000000000 }, // D5: oRDY; + { 0x0000f3d2, 0x00000004 }, // D6: @H_3D_CLEAR_HIZ: iREQ;oRDY;oREQ;odata=pm4;oAddr=ram;address=mmZB_HIZ_WRINDEX;cont; + { 0x0140a000, 0x00000004 }, // D7: iREQ;oRDY;index=pm4[13:0];cont; + { 0x00cc2000, 0x00000004 }, // D8: iREQ;acc=pm4;index--;cont; + { 0x08c053d3, 0x00000040 }, // D9: oREQ;odata=acc;oAddr=ram;address=mmZB_HIZ_DWORD;index--;ccont_indexz; + { 0x00008000, 0000000000 }, // DA: oRDY; + { 0x0000f39d, 0x00000004 }, // DB: @H_3D_CLEAR_CMASK: iREQ;oRDY;oREQ;odata=pm4;oAddr=ram;address=mmRB3D_CMASK_WRINDEX;cont; + { 0x0140a000, 0x00000004 }, // DC: iREQ;oRDY;index=pm4[13:0];cont; + { 0x00cc2000, 0x00000004 }, // DD: iREQ;acc=pm4;index--;cont; + { 0x08c0539e, 0x00000040 }, // DE: oREQ;odata=acc;oAddr=ram;address=mmRB3D_CMASK_DWORD;index--;ccont_indexz; + { 0x00008000, 0000000000 }, // DF: oRDY; + { 0x03c00830, 0x00000004 }, // E0: @H_3D_LOAD_VBPNTR: ldbase;address=mmVAP_VTX_NUM_ARRAYS;oAddr=ram;cont; + { 0x4200e000, 0000000000 }, // E1: iREQ;oREQ;oRDY;odata=pm4;oAddr=base;base++; + { 0x0000a000, 0x00000004 }, // E2: @H_LOAD_PALETTE: iREQ;oRDY;cont; + { 0x200045e0, 0x00000004 }, // E3: oREQ;address=mmSRC_CLUT_ADDRESS;odata=0;oaddr=ram;cont; + { 0x0000e5e1, 0000000000 }, // E4: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmSRC_CLUT_DATA; + { 0x00000001, 0000000000 }, // E5: @C_00000001: constant 00000001; + { 0x000700e5, 0x00000004 }, // E6: @WAIT_FOR_IDLE: acc=ram[addr];address=@C_00000001;cont; + { 0x0800e394, 0000000000 }, // E7: iREQ;oRDY;oREQ;oData=acc;oAddr=ram;address=mmNQWAIT_UNTIL; + { 0000000000, 0000000000 }, // E8: @V_24BPPMODE: constant 0; + { 0x0000e8c4, 0x00000004 }, // E9: @H_3D_DRAW_N3FV3F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_NORM_0_X;cont; + { 0x0000e8c5, 0x00000004 }, // EA: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_NORM_0_Y;cont; + { 0x0000e8c6, 0x00000004 }, // EB: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_NORM_0_Z;cont; + { 0x0000e928, 0x00000004 }, // EC: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_X_3;cont; + { 0x0000e929, 0x00000004 }, // ED: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Y_3;cont; + { 0x0000e92a, 0x00000004 }, // EE: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Z_3;cont; + { 0x000000e9, 0x00000008 }, // EF: goto @H_3D_DRAW_N3FV3F; + { 0x0000e928, 0x00000004 }, // F0: @H_3D_DRAW_V3F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_X_3;cont; + { 0x0000e929, 0x00000004 }, // F1: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Y_3;cont; + { 0x0000e92a, 0x00000004 }, // F2: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Z_3;cont; + { 0x000000f0, 0x00000008 }, // F3: goto @H_3D_DRAW_V3F; + { 0000000000, 0000000000 }, // F4: + { 0000000000, 0000000000 }, // F5: + { 0000000000, 0000000000 }, // F6: + { 0000000000, 0000000000 }, // F7: + { 0000000000, 0000000000 }, // F8: + { 0000000000, 0000000000 }, // F9: + { 0000000000, 0000000000 }, // FA: + { 0000000000, 0000000000 }, // FB: + { 0000000000, 0000000000 }, // FC: + { 0000000000, 0000000000 }, // FD: + { 0000000000, 0000000000 }, // FE: + { 0000000000, 0000000000 }, // FF: +}; // Array aPM4_Microcode contains 256 micro-instructions. + +#else /* CP microcode (from ATI) */ static u32 R200_cp_microcode[][2] = { { 0x21007000, 0000000000 }, @@ -297,7 +558,7 @@ { 0000000000, 0000000000 }, }; - +#endif // 0 static u32 radeon_cp_microcode[][2] = { { 0x21007000, 0000000000 }, { 0x20007000, 0000000000 }, @@ -982,9 +1243,11 @@ if ( on ) { RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); + DRM_DEBUG("Setting PCI_GART\n"); /* set PCI GART page-table base address */ RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); + DRM_DEBUG("Setting AIC_PT_BASE 0x%lx \n", dev_priv->bus_pci_gart ); /* set address range for PCI address translate */ @@ -992,6 +1255,10 @@ RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start + dev_priv->gart_size - 1); + DRM_DEBUG("Setting AIC_LO_BASE 0x%lx \n", dev_priv->gart_vm_start ); + DRM_DEBUG("Setting AIC_HI_BASE 0x%lx \n", (dev_priv->gart_vm_start + + dev_priv->gart_size -1 )); + /* Turn off AGP aperture -- is this required for PCI GART? */ RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ Index: lib/Xpm/Imakefile =================================================================== RCS file: /cvs/xorg/xc/lib/Xpm/Imakefile,v retrieving revision 1.5 diff -u -r1.5 Imakefile --- lib/Xpm/Imakefile 11 Dec 2004 16:04:34 -0000 1.5 +++ lib/Xpm/Imakefile 10 Jan 2005 19:30:48 -0000 @@ -27,7 +27,7 @@ */ #if defined(LinuxArchitecture) -ZFILEDEF = -DSTAT_ZFILE +ZFILEDEF = -DSTAT_ZFILE -DNO_ZPIPE #endif #if defined(UltrixArchitecture) || \ (defined(MipsArchitecture) && !defined(SGIArchitecture)) Index: programs/Xserver/GL/dri/dri.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/GL/dri/dri.c,v retrieving revision 1.7 diff -u -r1.7 dri.c --- programs/Xserver/GL/dri/dri.c 8 Dec 2004 05:52:20 -0000 1.7 +++ programs/Xserver/GL/dri/dri.c 10 Jan 2005 19:30:51 -0000 @@ -284,7 +284,7 @@ return FALSE; } DRIDrvMsg(pScreen->myNum, X_INFO, - "[drm] added %d byte SAREA at 0x%08lx\n", + "[drm] added %d byte SAREA at 0x%016lx\n", pDRIPriv->pDriverInfo->SAREASize, pDRIPriv->hSAREA); if (drmMap( pDRIPriv->drmFD, @@ -300,7 +300,7 @@ return FALSE; } memset(pDRIPriv->pSAREA, 0, pDRIPriv->pDriverInfo->SAREASize); - DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] mapped SAREA 0x%08lx to %p\n", + DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] mapped SAREA 0x%016lx to %p\n", pDRIPriv->hSAREA, pDRIPriv->pSAREA); if (drmAddMap( pDRIPriv->drmFD, @@ -318,7 +318,7 @@ "[drm] drmAddMap failed\n"); return FALSE; } - DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] framebuffer handle = 0x%08lx\n", + DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] framebuffer handle = 0x%016lx\n", pDRIPriv->hFrameBuffer); /* Add tags for reserved contexts */ @@ -381,7 +381,7 @@ pDRIPriv->myContextPriv = pDRIContextPriv; DRIDrvMsg(pScreen->myNum, X_INFO, - "X context handle = 0x%08lx\n", pDRIPriv->myContext); + "X context handle = 0x%016lx\n", pDRIPriv->myContext); /* Now that we have created the X server's context, we can grab the * hardware lock for the X server. @@ -565,14 +565,14 @@ drmUnlock(pDRIPriv->drmFD, pDRIPriv->myContext); lockRefCount=0; DRIDrvMsg(pScreen->myNum, X_INFO, - "[drm] unmapping %d bytes of SAREA 0x%08lx at %p\n", + "[drm] unmapping %d bytes of SAREA 0x%016lx at %p\n", pDRIInfo->SAREASize, pDRIPriv->hSAREA, pDRIPriv->pSAREA); if (drmUnmap(pDRIPriv->pSAREA, pDRIInfo->SAREASize)) { DRIDrvMsg(pScreen->myNum, X_ERROR, "[drm] unable to unmap %d bytes" - " of SAREA 0x%08lx at %p\n", + " of SAREA 0x%016lx at %p\n", pDRIInfo->SAREASize, pDRIPriv->hSAREA, pDRIPriv->pSAREA); Index: programs/Xserver/GL/dri/dri.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/GL/dri/dri.h,v retrieving revision 1.3 diff -u -r1.3 dri.h --- programs/Xserver/GL/dri/dri.h 16 Jun 2004 09:37:58 -0000 1.3 +++ programs/Xserver/GL/dri/dri.h 10 Jan 2005 19:30:51 -0000 @@ -141,7 +141,7 @@ int ddxDriverMajorVersion; int ddxDriverMinorVersion; int ddxDriverPatchVersion; - CARD32 frameBufferPhysicalAddress; + CARD64 frameBufferPhysicalAddress; long frameBufferSize; long frameBufferStride; long SAREASize; Index: programs/Xserver/hw/xfree86/common/compiler.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/common/compiler.h,v retrieving revision 1.3 diff -u -r1.3 compiler.h --- programs/Xserver/hw/xfree86/common/compiler.h 27 Aug 2004 19:27:12 -0000 1.3 +++ programs/Xserver/hw/xfree86/common/compiler.h 10 Jan 2005 19:30:55 -0000 @@ -124,7 +124,8 @@ # if !defined(__arm__) # if !defined(__sparc__) && !defined(__arm32__) \ - && !(defined(__alpha__) && defined(linux)) + && !(defined(__alpha__) && defined(linux)) \ + && !(defined(__ia64__) && defined(linux)) \ extern void outb(unsigned short, unsigned char); extern void outw(unsigned short, unsigned short); @@ -464,10 +465,12 @@ # ifndef __INTEL_COMPILER # define mem_barrier() __asm__ __volatile__ ("mf" ::: "memory") # define write_mem_barrier() __asm__ __volatile__ ("mf" ::: "memory") +# define io_mem_barrier() __asm__ __volatile__ ("mf.a" ::: "memory") # else # include "ia64intrin.h" # define mem_barrier() __mf() # define write_mem_barrier() __mf() +# define io_mem_barrier() __mfa # endif /* @@ -494,10 +497,22 @@ # undef outb # undef outw # undef outl - -# define outb(a,b) _outb(b,a) -# define outw(a,b) _outw(b,a) -# define outl(a,b) _outl(b,a) +# define outb ia64_outb +# define outw ia64_outw +# define outl ia64_outl +# undef inb +# undef inw +# undef inl +# define inb ia64_inb +# define inw ia64_inw +# define inl ia64_inl + +extern void ia64_outb(unsigned long port, unsigned char val); +extern void ia64_outw(unsigned long port, unsigned short val); +extern void ia64_outl(unsigned long port, unsigned int val); +extern unsigned int inb(unsigned long port); +extern unsigned int inw(unsigned long port); +extern unsigned int inl(unsigned long port); # elif defined(linux) && defined(__amd64__) Index: programs/Xserver/hw/xfree86/common/xf86Bus.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/common/xf86Bus.c,v retrieving revision 1.3 diff -u -r1.3 xf86Bus.c --- programs/Xserver/hw/xfree86/common/xf86Bus.c 6 Jul 2004 14:49:13 -0000 1.3 +++ programs/Xserver/hw/xfree86/common/xf86Bus.c 10 Jan 2005 19:30:55 -0000 @@ -1771,7 +1771,7 @@ range.type = (range.type & ~ResAccMask) | (access & ResAccMask); } range.type &= ~ResEstimated; /* Not allowed for drivers */ -#if !(defined(__alpha__) && defined(linux)) +#if !((defined(__alpha__) || (defined(__ia64__))) && defined(linux)) /* On Alpha Linux, do not check for conflicts, trust the kernel. */ if (checkConflict(&range, Acc, entityIndex, SETUP,TRUE)) res = xf86AddResToList(res,&range,entityIndex); @@ -2391,8 +2391,9 @@ #endif } xf86FreeResList(acc); - +/* XXX shm@engr */ #if !(defined(__alpha__) && defined(linux)) && \ + !(defined(__ia64__) && defined(linux)) && \ !(defined(__sparc64__) && defined(__OpenBSD__)) /* * No need to validate on Alpha Linux or OpenBSD/sparc64, Index: programs/Xserver/hw/xfree86/common/xf86pciBus.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c,v retrieving revision 1.6 diff -u -r1.6 xf86pciBus.c --- programs/Xserver/hw/xfree86/common/xf86pciBus.c 11 Nov 2004 20:10:28 -0000 1.6 +++ programs/Xserver/hw/xfree86/common/xf86pciBus.c 10 Jan 2005 19:30:56 -0000 @@ -1682,10 +1682,12 @@ m = m->next; } } else { +#if defined(__snia__) if (!xf86IsSubsetOf(range, m) || ChkConflict(&range, avoid, SETUP) || (mem && ChkConflict(&range, mem, SETUP))) ret = 0; +#endif } xf86FreeResList(avoid); Index: programs/Xserver/hw/xfree86/drivers/ati/Imakefile =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile,v retrieving revision 1.12 diff -u -r1.12 Imakefile --- programs/Xserver/hw/xfree86/drivers/ati/Imakefile 6 Dec 2004 15:53:00 -0000 1.12 +++ programs/Xserver/hw/xfree86/drivers/ati/Imakefile 10 Jan 2005 19:30:56 -0000 @@ -116,7 +116,7 @@ # define ATIAvoidNonPCI NO #endif -#if ATIAvoidNonPCI +#if 1 NONPCIDEFINES = -DAVOID_NON_PCI Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v retrieving revision 1.13 diff -u -r1.13 radeon_accel.c --- programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c 12 Dec 2004 20:42:29 -0000 1.13 +++ programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c 10 Jan 2005 19:30:56 -0000 @@ -129,6 +129,10 @@ RADEONTRACE(("FIFO timed out: %d entries, stat=0x%08x\n", INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, INREG(RADEON_RBBM_STATUS))); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "FIFO timed out: %d entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "FIFO timed out, resetting engine...\n"); RADEONEngineReset(pScrn); Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c,v retrieving revision 1.2 diff -u -r1.2 radeon_bios.c --- programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c 12 Dec 2004 00:14:32 -0000 1.2 +++ programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c 10 Jan 2005 19:30:56 -0000 @@ -51,7 +51,7 @@ (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), RADEON_VBIOS_SIZE); } else { - xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); + //xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Video BIOS not detected in PCI space!\n"); Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v retrieving revision 1.10 diff -u -r1.10 radeon_dri.c --- programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c 12 Dec 2004 19:28:37 -0000 1.10 +++ programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c 10 Jan 2005 19:30:56 -0000 @@ -810,7 +810,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] %d kB allocated with handle 0x%08lx\n", + "[agp] %d kB allocated with handle 0x%016lx\n", info->gartSize*1024, info->agpMemHandle); if (drmAgpBind(info->drmFD, @@ -828,7 +828,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] ring handle = 0x%08lx\n", info->ringHandle); + "[agp] ring handle = 0x%016lx\n", info->ringHandle); if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, (drmAddressPtr)&info->ring) < 0) { @@ -836,7 +836,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Ring mapped at 0x%08lx\n", + "[agp] Ring mapped at 0x%016lx\n", (unsigned long)info->ring); if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize, @@ -846,7 +846,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] ring read ptr handle = 0x%08lx\n", + "[agp] ring read ptr handle = 0x%016lx\n", info->ringReadPtrHandle); if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, @@ -856,7 +856,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Ring read ptr mapped at 0x%08lx\n", + "[agp] Ring read ptr mapped at 0x%016lx\n", (unsigned long)info->ringReadPtr); if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize, @@ -866,7 +866,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] vertex/indirect buffers handle = 0x%08lx\n", + "[agp] vertex/indirect buffers handle = 0x%016lx\n", info->bufHandle); if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, @@ -876,7 +876,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Vertex/indirect buffers mapped at 0x%08lx\n", + "[agp] Vertex/indirect buffers mapped at 0x%016lx\n", (unsigned long)info->buf); if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize, @@ -886,7 +886,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] GART texture map handle = 0x%08lx\n", + "[agp] GART texture map handle = 0x%016lx\n", info->gartTexHandle); if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize, @@ -896,7 +896,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] GART Texture map mapped at 0x%08lx\n", + "[agp] GART Texture map mapped at 0x%016lx\n", (unsigned long)info->gartTex); RADEONSetAgpBase(info); @@ -919,7 +919,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] %d kB allocated with handle 0x%08lx\n", + "[pci] %d kB allocated with handle 0x%016lx\n", info->gartSize*1024, info->pciMemHandle); RADEONDRIInitGARTValues(info); @@ -931,7 +931,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] ring handle = 0x%08lx\n", info->ringHandle); + "[pci] ring handle = 0x%016lx\n", info->ringHandle); if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, (drmAddressPtr)&info->ring) < 0) { @@ -939,10 +939,10 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring mapped at 0x%08lx\n", + "[pci] Ring mapped at 0x%016lx\n", (unsigned long)info->ring); xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring contents 0x%08lx\n", + "[pci] Ring contents 0x%016lx\n", *(unsigned long *)(pointer)info->ring); if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize, @@ -952,7 +952,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] ring read ptr handle = 0x%08lx\n", + "[pci] ring read ptr handle = 0x%016lx\n", info->ringReadPtrHandle); if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, @@ -962,10 +962,10 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring read ptr mapped at 0x%08lx\n", + "[pci] Ring read ptr mapped at 0x%016lx\n", (unsigned long)info->ringReadPtr); xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring read ptr contents 0x%08lx\n", + "[pci] Ring read ptr contents 0x%016lx\n", *(unsigned long *)(pointer)info->ringReadPtr); if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize, @@ -975,7 +975,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] vertex/indirect buffers handle = 0x%08lx\n", + "[pci] vertex/indirect buffers handle = 0x%016lx\n", info->bufHandle); if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, @@ -985,10 +985,10 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Vertex/indirect buffers mapped at 0x%08lx\n", + "[pci] Vertex/indirect buffers mapped at 0x%016lx\n", (unsigned long)info->buf); xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Vertex/indirect buffers contents 0x%08lx\n", + "[pci] Vertex/indirect buffers contents 0x%016lx\n", *(unsigned long *)(pointer)info->buf); if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize, @@ -998,7 +998,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] GART texture map handle = 0x%08lx\n", + "[pci] GART texture map handle = 0x%016lx\n", info->gartTexHandle); if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize, @@ -1008,7 +1008,7 @@ return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] GART Texture map mapped at 0x%08lx\n", + "[pci] GART Texture map mapped at 0x%016lx\n", (unsigned long)info->gartTex); return TRUE; @@ -1021,12 +1021,16 @@ { /* Map registers */ info->registerSize = RADEON_MMIOSIZE; - if (drmAddMap(info->drmFD, info->MMIOAddr, info->registerSize, - DRM_REGISTERS, DRM_READ_ONLY, &info->registerHandle) < 0) { + if (drmAddMap(info->drmFD, + pciBusAddrToHostAddr(info->PciTag, PCI_MEM, info->MMIOAddr), + info->registerSize, + DRM_REGISTERS, + DRM_READ_ONLY, + &info->registerHandle) < 0) { return FALSE; } xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] register handle = 0x%08lx\n", info->registerHandle); + "[drm] register handle = 0x%016lx\n", info->registerHandle); return TRUE; } @@ -1276,7 +1280,9 @@ pDRIInfo->ddxDriverMajorVersion = RADEON_VERSION_MAJOR; pDRIInfo->ddxDriverMinorVersion = RADEON_VERSION_MINOR; pDRIInfo->ddxDriverPatchVersion = RADEON_VERSION_PATCH; - pDRIInfo->frameBufferPhysicalAddress = info->LinearAddr; + pDRIInfo->frameBufferPhysicalAddress = pciBusAddrToHostAddr(info->PciTag, + PCI_MEM, + info->LinearAddr); pDRIInfo->frameBufferSize = info->FbMapSize; pDRIInfo->frameBufferStride = (pScrn->displayWidth * info->CurrentLayout.pixel_bytes); @@ -1286,6 +1292,10 @@ ? SAREA_MAX_DRAWABLES : RADEON_MAX_DRAWABLES); + xf86DrvMsg(pScreen->myNum, X_INFO, + "[drm] frameBuffer handle = 0x%016lx\n", + pDRIInfo->frameBufferPhysicalAddress); + #ifdef PER_CONTEXT_SAREA /* This is only here for testing per-context SAREAs. When used, the magic number below would be properly defined in a header file. */ Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v retrieving revision 1.31 diff -u -r1.31 radeon_driver.c --- programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 12 Dec 2004 19:28:37 -0000 1.31 +++ programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 10 Jan 2005 19:30:57 -0000 @@ -2505,6 +2505,8 @@ } } + info->IsPCI = TRUE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", (info->IsPCI) ? "PCI" : "AGP"); @@ -4650,7 +4652,9 @@ info->PaletteSavedOnVT = FALSE; +#if !defined (__ia64__) RADEONSave(pScrn); +#endif /* __ia64__ */ if ((!info->IsSecondary) && info->IsMobility) { if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { Index: programs/Xserver/hw/xfree86/int10/generic.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/int10/generic.c,v retrieving revision 1.2 diff -u -r1.2 generic.c --- programs/Xserver/hw/xfree86/int10/generic.c 23 Apr 2004 19:54:06 -0000 1.2 +++ programs/Xserver/hw/xfree86/int10/generic.c 10 Jan 2005 19:30:58 -0000 @@ -123,13 +123,11 @@ * 64kB at a time. */ (void)memset((char *)base + V_BIOS, 0, SYS_BIOS - V_BIOS); -#if 0 for (cs = V_BIOS; cs < SYS_BIOS; cs += V_BIOS_SIZE) if (xf86ReadBIOS(cs, 0, (unsigned char *)base + cs, V_BIOS_SIZE) < V_BIOS_SIZE) xf86DrvMsg(screen, X_WARNING, "Unable to retrieve all of segment 0x%06X.\n", cs); -#endif INTPriv(pInt)->highMemory = V_BIOS; xf86int10ParseBiosLocation(options,&bios); Index: programs/Xserver/hw/xfree86/loader/xf86sym.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/loader/xf86sym.c,v retrieving revision 1.8 diff -u -r1.8 xf86sym.c --- programs/Xserver/hw/xfree86/loader/xf86sym.c 29 Oct 2004 02:07:15 -0000 1.8 +++ programs/Xserver/hw/xfree86/loader/xf86sym.c 10 Jan 2005 19:30:58 -0000 @@ -1093,12 +1093,12 @@ #endif #endif #if defined(__ia64__) - SYMFUNC(_outw) - SYMFUNC(_outb) - SYMFUNC(_outl) - SYMFUNC(_inb) - SYMFUNC(_inw) - SYMFUNC(_inl) + SYMFUNC(ia64_outb) + SYMFUNC(ia64_outw) + SYMFUNC(ia64_outl) + SYMFUNC(ia64_inb) + SYMFUNC(ia64_inw) + SYMFUNC(ia64_inl) #endif #if defined(__arm__) SYMFUNC(outw) Index: programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h,v retrieving revision 1.2 diff -u -r1.2 xf86_OSproc.h --- programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h 23 Apr 2004 19:54:07 -0000 1.2 +++ programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h 10 Jan 2005 19:30:58 -0000 @@ -256,6 +256,8 @@ #endif /* NEED_OS_RAC_PROTOS */ extern Bool xf86GetPciSizeFromOS(PCITAG tag, int indx, int* bits); +extern Bool xf86GetPciOffsetFromOS(PCITAG tag, int indx, unsigned long* bases); +extern unsigned long xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base); extern void xf86MakeNewMapping(int, int, unsigned long, unsigned long, pointer); extern void xf86InitVidMem(void); Index: programs/Xserver/hw/xfree86/os-support/bus/Imakefile =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/bus/Imakefile,v retrieving revision 1.5 diff -u -r1.5 Imakefile --- programs/Xserver/hw/xfree86/os-support/bus/Imakefile 15 Sep 2004 09:23:58 -0000 1.5 +++ programs/Xserver/hw/xfree86/os-support/bus/Imakefile 10 Jan 2005 19:30:58 -0000 @@ -126,8 +126,8 @@ PCIARCHOBJ = sparcPci.o # endif #elif defined(ia64Architecture) -PCIARCHSRC = 460gxPCI.c e8870PCI.c zx1PCI.c -PCIARCHOBJ = 460gxPCI.o e8870PCI.o zx1PCI.o +PCIARCHSRC = 460gxPCI.c e8870PCI.c zx1PCI.c altixPCI.c +PCIARCHOBJ = 460gxPCI.o e8870PCI.o zx1PCI.o altixPCI.o #endif SRCS = Pci.c $(PCIDRVRSRC) $(SBUSDRVSRC) $(PCIARCHSRC) Index: programs/Xserver/hw/xfree86/os-support/bus/Pci.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.h,v retrieving revision 1.4 diff -u -r1.4 Pci.h --- programs/Xserver/hw/xfree86/os-support/bus/Pci.h 11 Aug 2004 21:14:17 -0000 1.4 +++ programs/Xserver/hw/xfree86/os-support/bus/Pci.h 10 Jan 2005 19:30:58 -0000 @@ -254,7 +254,6 @@ # if defined(linux) # define ARCH_PCI_INIT linuxPciInit # define INCLUDE_XF86_MAP_PCI_MEM -# define INCLUDE_XF86_NO_DOMAIN # elif defined(FreeBSD) # define ARCH_PCI_INIT freebsdPciInit # define INCLUDE_XF86_MAP_PCI_MEM Index: programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c,v retrieving revision 1.4 diff -u -r1.4 linuxPci.c --- programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c 30 Nov 2004 08:38:44 -0000 1.4 +++ programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c 10 Jan 2005 19:30:58 -0000 @@ -59,13 +59,14 @@ static CARD32 linuxPciCfgRead(PCITAG tag, int off); static void linuxPciCfgWrite(PCITAG, int off, CARD32 val); static void linuxPciCfgSetBits(PCITAG tag, int off, CARD32 mask, CARD32 bits); +static ADDRESS linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr); static pciBusFuncs_t linuxFuncs0 = { /* pciReadLong */ linuxPciCfgRead, /* pciWriteLong */ linuxPciCfgWrite, /* pciSetBitsLong */ linuxPciCfgSetBits, /* pciAddrHostToBus */ pciAddrNOOP, -/* pciAddrBusToHost */ pciAddrNOOP +/* pciAddrBusToHost */ linuxTransAddrBusToHost }; static pciBusInfo_t linuxPci0 = { @@ -113,7 +114,7 @@ if (fd != -1) close(fd); if (bus < 256) { - sprintf(file,"/proc/bus/pci/%02x",bus); + sprintf(file,"/proc/bus/pci/%02x",bus); if (stat(file, &ignored) < 0) sprintf(file, "/proc/bus/pci/0000:%02x/%02x.%1x", bus, dev, func); @@ -345,6 +346,25 @@ return result + 1; /* Domain 0 is reserved */ } +/* + * This function will convert a BAR address into a host address + * suitable for passing into the mmap function of a /proc/bus + * device. + */ +ADDRESS +linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr) +{ + ADDRESS ret = xf86GetOSOffsetFromPCI(tag, PCI_MEM|PCI_IO, addr); + if (ret) + return ret; + else + /* + * if it is not a BAR address, it must be legacy, (or wrong) + * return it as is .. + */ + return addr; +} + static pointer linuxMapPci(int ScreenNum, int Flags, PCITAG Tag, ADDRESS Base, unsigned long Size, int mmap_ioctl) @@ -376,7 +396,7 @@ if (Flags & VIDMEM_FRAMEBUFFER) mmapflags = MAP_SHARED | MAP_WRITECOMBINED; else - mmapflags = MAP_SHARED | MAP_NONCACHED + mmapflags = MAP_SHARED | MAP_NONCACHED; #else /* !__ia64__ */ @@ -414,33 +434,63 @@ return NULL; } +#define MAX_DOMAINS 257 +static pointer DomainMmappedIO[MAX_DOMAINS]; +static pointer DomainMmappedMem[MAX_DOMAINS]; + pointer xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, ADDRESS Base, unsigned long Size) { - return linuxMapPci(ScreenNum, Flags, Tag, Base, Size, PCIIOC_MMAP_IS_MEM); -} + char path[38]; /* /sys/class/pci_bus/DDDD:BB/legacy_mem */ + int domain = xf86GetPciDomain(Tag); + int bus = PCI_BUS_FROM_TAG(Tag); + int fd; -#define MAX_DOMAINS 257 -static pointer DomainMmappedIO[MAX_DOMAINS]; + if (Base > 1024*1024) + return linuxMapPci(ScreenNum, Flags, Tag, Base, Size, PCIIOC_MMAP_IS_MEM); + + if ((domain <= 0) || (domain >= MAX_DOMAINS)) + FatalError("xf86MapDomainMem(): domain out of range\n"); + + /* Hack, need to deal with domains correctly */ + sprintf(path, "/sys/class/pci_bus/%04x:%02x/legacy_mem", 0, bus); + + /* Permanently map all of memory space */ + if (!DomainMmappedMem[domain]) { + fd = open(path, O_RDWR); + DomainMmappedMem[domain] = mmap(0, Size, PROT_READ|PROT_WRITE, + MAP_SHARED, fd, 0); + close(fd); + if (!DomainMmappedMem[domain]) + FatalError("xf86MapDomainMem(): mmap() failure\n"); + } + + return (pointer)((char *)DomainMmappedMem[domain] + Base); +} /* This has no means of returning failure, so all errors are fatal */ IOADDRESS xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, IOADDRESS Base, unsigned long Size) { + char path[37]; /* /sys/class/pci_bus/DDDD:BB/legacy_io */ int domain = xf86GetPciDomain(Tag); + int bus = PCI_BUS_FROM_TAG(Tag); + int fd; if ((domain <= 0) || (domain >= MAX_DOMAINS)) FatalError("xf86MapDomainIO(): domain out of range\n"); + /* Hack, need to deal with domains properly */ + sprintf(path, "/sys/class/pci_bus/%04x:%02x/legacy_io", 0, bus); + /* Permanently map all of I/O space */ if (!DomainMmappedIO[domain]) { - DomainMmappedIO[domain] = linuxMapPci(ScreenNum, Flags, Tag, - 0, linuxGetIOSize(Tag), - PCIIOC_MMAP_IS_IO); - if (!DomainMmappedIO[domain]) - FatalError("xf86MapDomainIO(): mmap() failure\n"); + fd = open(path, O_RDWR); + if (fd == -1) + FatalError("xf86MapDomainIO(): open() failure\n"); + DomainMmappedIO[domain] = fd << 24; /* encode fd in address */ } return (IOADDRESS)DomainMmappedIO[domain] + Base; @@ -454,6 +504,55 @@ unsigned long size; int len, pagemask = getpagesize() - 1; +#if defined (__ia64__) + unsigned int i, dom, bus, dev, func; + unsigned int fd; + char file[256]; + unsigned char *head = Buf; + char *enable = "1"; + + ErrorF("Came to read domain memory with Base = 0x%lx, Tag = 0x%lx, size = 0x%x\n", + Base, Tag, Len); + + if ((Base & 0xfffff) == 0xC0000) { + dom = PCI_DOM_FROM_TAG(Tag); + bus = PCI_BUS_FROM_TAG(Tag); + dev = PCI_DEV_FROM_TAG(Tag); + func = PCI_FUNC_FROM_TAG(Tag); + + /* + * Need to handle PCI bridges, which will have an additional path + * element at the end, e.g. + * /sys/devices/pci:///rom instead of + * /sys/devices/pci://rom + */ + sprintf(file, "/sys/devices/pci%04x:%02x/%04x:%02x:%02x.%1x/rom", + dom, bus, dom, bus, dev, func); + + ErrorF("Opening rom file %s\n", file); + + if ((fd = open(file, O_RDWR))) { + Base = 0x0; + } + + /* enable the ROM first */ + write(fd, enable, 1); + + /* copy the ROM */ + for (i = 0; read(fd, Buf, 1); Buf++,i++) + ; + + ErrorF("Read %d bytes from rom device, signature = 0x%x, 0x%x\n", + i, head[0], head[1]); + write(fd, 0, 1); + close(fd); + + return Len; + + } +#endif /* __ia64__ */ + + /* Ensure page boundaries */ offset = Base & ~pagemask; size = ((Base + Len + pagemask) & ~pagemask) - offset; @@ -463,11 +562,15 @@ if (!ptr) return -1; + ErrorF("About to memcpy\n"); + /* Using memcpy() here can hang the system */ src = ptr + (Base - offset); for (len = Len; len-- > 0;) *Buf++ = *src++; + ErrorF("Done with memcpy\n"); + xf86UnMapVidMem(-1, ptr, size); return Len; Index: programs/Xserver/hw/xfree86/os-support/linux/lnx_ia64.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/linux/lnx_ia64.c,v retrieving revision 1.1 diff -u -r1.1 lnx_ia64.c --- programs/Xserver/hw/xfree86/os-support/linux/lnx_ia64.c 15 Sep 2004 09:23:59 -0000 1.1 +++ programs/Xserver/hw/xfree86/os-support/linux/lnx_ia64.c 10 Jan 2005 19:30:58 -0000 @@ -40,6 +40,10 @@ || !stat("/proc/bus/mckinley/zx2",&unused)) return ZX1_CHIPSET; + if (!stat("/proc/sgi_sn/licenseID", &unused)) + return ALTIX_CHIPSET; + return NONE_CHIPSET; } #endif + Index: programs/Xserver/hw/xfree86/os-support/linux/lnx_pci.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/linux/lnx_pci.c,v retrieving revision 1.2 diff -u -r1.2 lnx_pci.c --- programs/Xserver/hw/xfree86/os-support/linux/lnx_pci.c 23 Apr 2004 19:54:08 -0000 1.2 +++ programs/Xserver/hw/xfree86/os-support/linux/lnx_pci.c 10 Jan 2005 19:30:58 -0000 @@ -83,3 +83,142 @@ fclose(file); return FALSE; } + + + +/* Query the kvirt address (64bit) of a BAR range from TAG */ +Bool +xf86GetPciOffsetFromOS(PCITAG tag, int index, unsigned long* bases) +{ + FILE *file; + char c[0x200]; + char *res; + unsigned int bus, devfn, dev, fn; + unsigned PCIADDR_TYPE offset[7]; + unsigned int num; + + if (index > 7) + return FALSE; + + if (!(file = fopen("/proc/bus/pci/devices","r"))) + return FALSE; + do { + res = fgets(c,0x1ff,file); + if (res) { + num = sscanf(res, + /*bus+dev vendorid deviceid irq */ + "%02x%02x\t%*04x%*04x\t%*x" + /* 7 PCI resource base addresses */ + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + /* 7 PCI resource sizes, and then optionally a driver name */ + "\t" PCIADDR_IGNORE_FMT + "\t" PCIADDR_IGNORE_FMT + "\t" PCIADDR_IGNORE_FMT + "\t" PCIADDR_IGNORE_FMT + "\t" PCIADDR_IGNORE_FMT + "\t" PCIADDR_IGNORE_FMT + "\t" PCIADDR_IGNORE_FMT, + &bus,&devfn,&offset[0],&offset[1],&offset[2],&offset[3], + &offset[4],&offset[5],&offset[6]); + if (num != 9) { /* apparantly not 2.3 style */ + fclose(file); + return FALSE; + } + + dev = devfn >> 3; + fn = devfn & 0x7; + + if (tag == pciTag(bus,dev,fn)) { + /* return the offset for the index requested */ + *bases = offset[index]; + fclose(file); + return TRUE; + } + } + } while (res); + + fclose(file); + return FALSE; +} + +/* Query the kvirt address (64bit) of a BAR range from size for a given TAG */ +unsigned long +xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base) +{ + FILE *file; + char c[0x200]; + char *res; + unsigned int bus, devfn, dev, fn; + unsigned PCIADDR_TYPE offset[7]; + unsigned PCIADDR_TYPE size[7]; + unsigned int num; + unsigned int ndx; + + if (!(file = fopen("/proc/bus/pci/devices","r"))) + return NULL; + do { + res = fgets(c,0x1ff,file); + if (res) { + num = sscanf(res, + /*bus+dev vendorid deviceid irq */ + "%02x%02x\t%*04x%*04x\t%*x" + /* 7 PCI resource base addresses */ + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + /* 7 PCI resource sizes, and then optionally a driver name */ + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT + "\t" PCIADDR_FMT, + &bus,&devfn,&offset[0],&offset[1],&offset[2],&offset[3], + &offset[4],&offset[5],&offset[6], &size[0], &size[1], &size[2], + &size[3], &size[4], &size[5], &size[6]); + if (num != 16) { /* apparantly not 2.3 style */ + fclose(file); + return NULL; + } + + dev = devfn >> 3; + fn = devfn & 0x7; + if (tag == pciTag(bus,dev,fn)) { + /* ok now look through all the BAR values of this device */ + for (ndx=0; ndx<7; ndx++) { + unsigned long savePtr; + /* + * remember to lop of the last 4bits of the BAR values as they are + * memory attributes + */ + if (ndx == 6) + savePtr = (0xFFFFFFF0) & + pciReadLong(tag, PCI_CMD_BIOS_REG); + else /* this the ROM bar */ + savePtr = (0xFFFFFFF0) & + pciReadLong(tag, PCI_CMD_BASE_REG + (0x4 * ndx)); + /* find the index of the incoming base */ + if (base >= savePtr && base <= (savePtr + size[ndx])) { + fclose(file); + return ( ~(0xFUL) & (offset[ndx] + (base - savePtr))); + } + } + } + } + } while (res); + + fclose(file); + return NULL; + +} Index: programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.c,v retrieving revision 1.1 diff -u -r1.1 ia64Pci.c --- programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.c 15 Sep 2004 09:23:59 -0000 1.1 +++ programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.c 10 Jan 2005 19:30:58 -0000 @@ -29,19 +29,166 @@ * This file contains the glue needed to support various IA-64 chipsets. */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "compiler.h" #include "460gxPCI.h" #include "e8870PCI.h" #include "zx1PCI.h" +#include "altixPCI.h" #include "Pci.h" #include "ia64Pci.h" +static int ia64_port_to_fd(unsigned long port) +{ + return (port >> 24) & 0xffffffff; +} + +void ia64_outb(unsigned long port, unsigned char val) +{ + int fd = ia64_port_to_fd(port); + + if (!fd) { + ErrorF("bad I/O context\n"); + goto out; + } + if (lseek(fd, port & 0xffff, SEEK_SET) == -1) { + ErrorF("I/O lseek failed\n"); + goto out; + } + if (write(fd, &val, 1) != 1) { + ErrorF("I/O write failed\n"); + goto out; + } + out: + return; +} + +void ia64_outw(unsigned long port, unsigned short val) +{ + int fd = ia64_port_to_fd(port); + + if (!fd) { + ErrorF("bad I/O context\n"); + goto out; + } + if (lseek(fd, port & 0xffff, SEEK_SET) == -1) { + ErrorF("I/O lseek failed\n"); + goto out; + } + if (write(fd, &val, 2) != 2) { + ErrorF("I/O write failed\n"); + goto out; + } + out: + return; +} + +void ia64_outl(unsigned long port, unsigned int val) +{ + int fd = ia64_port_to_fd(port); + + if (!fd) { + ErrorF("bad I/O context\n"); + goto out; + } + if (lseek(fd, port & 0xffff, SEEK_SET) == -1) { + ErrorF("I/O lseek failed\n"); + goto out; + } + if (write(fd, &val, 4) != 4) { + ErrorF("I/O write failed\n"); + goto out; + } + out: + return; +} + +unsigned int ia64_inb(unsigned long port) +{ + int fd = ia64_port_to_fd(port); + unsigned char val; + + if (!fd) { + ErrorF("bad I/O context\n"); + val = -1; + goto out; + } + if (lseek(fd, port & 0xffff, SEEK_SET) == -1) { + ErrorF("I/O lseek failed\n"); + val = -1; + goto out; + } + if (read(fd, &val, 1) != 1) { + ErrorF("I/O read failed\n"); + val = -1; + goto out; + } + out: + return val; +} + +unsigned int ia64_inw(unsigned long port) +{ + int fd = ia64_port_to_fd(port); + unsigned short val; + + if (!fd) { + ErrorF("bad I/O context\n"); + val = -1; + goto out; + } + if (lseek(fd, port & 0xffff, SEEK_SET) == -1) { + ErrorF("I/O lseek failed\n"); + val = -1; + goto out; + } + if (read(fd, &val, 2) != 2) { + ErrorF("I/O read failed\n"); + val = -1; + goto out; + } + out: + return val; +} + +unsigned int ia64_inl(unsigned long port) +{ + int fd = ia64_port_to_fd(port); + unsigned int val; + + if (!fd) { + ErrorF("bad I/O context\n"); + val = -1; + goto out; + } + if (lseek(fd, port & 0xffff, SEEK_SET) == -1) { + ErrorF("I/O lseek failed\n"); + val = -1; + goto out; + } + if (read(fd, &val, 4) != 4) { + ErrorF("I/O read failed\n"); + val = -1; + goto out; + } + out: + return val; +} + void ia64ScanPCIWrapper(scanpciWrapperOpt flags) { static IA64Chipset chipset = NONE_CHIPSET; - - if (flags == SCANPCI_INIT) { + if (flags == SCANPCI_INIT) { /* PCI configuration space probes should be done first */ if (xorgProbe460GX(flags)) { chipset = I460GX_CHIPSET; @@ -55,27 +202,33 @@ #ifdef OS_PROBE_PCI_CHIPSET chipset = OS_PROBE_PCI_CHIPSET(flags); switch (chipset) { - case ZX1_CHIPSET: - xf86PreScanZX1(); - return; - default: - return; + case ZX1_CHIPSET: + xf86PreScanZX1(); + return; + case ALTIX_CHIPSET: + xf86PreScanAltix(); + return; + default: + return; } #endif } else /* if (flags == SCANPCI_TERM) */ { switch (chipset) { - case I460GX_CHIPSET: - xf86PostScan460GX(); - return; - case E8870_CHIPSET: - xf86PostScanE8870(); - return; - case ZX1_CHIPSET: - xf86PostScanZX1(); - return; - default: - return; + case I460GX_CHIPSET: + xf86PostScan460GX(); + return; + case E8870_CHIPSET: + xf86PostScanE8870(); + return; + case ZX1_CHIPSET: + xf86PostScanZX1(); + return; + case ALTIX_CHIPSET: + xf86PostScanAltix(); + return; + default: + return; } } } Index: programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.h,v retrieving revision 1.1 diff -u -r1.1 ia64Pci.h --- programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.h 15 Sep 2004 09:23:59 -0000 1.1 +++ programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.h 10 Jan 2005 19:30:58 -0000 @@ -32,7 +32,8 @@ NONE_CHIPSET, I460GX_CHIPSET, E8870_CHIPSET, - ZX1_CHIPSET + ZX1_CHIPSET, + ALTIX_CHIPSET } IA64Chipset; # ifdef OS_PROBE_PCI_CHIPSET Index: programs/Xserver/hw/xfree86/vgahw/vgaHW.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c,v retrieving revision 1.4 diff -u -r1.4 vgaHW.c --- programs/Xserver/hw/xfree86/vgahw/vgaHW.c 3 Aug 2004 09:33:54 -0000 1.4 +++ programs/Xserver/hw/xfree86/vgahw/vgaHW.c 10 Jan 2005 19:30:59 -0000 @@ -24,6 +24,8 @@ #include "xf86cmap.h" +#define DEBUG + #ifndef SAVE_FONT1 #define SAVE_FONT1 #endif --- /dev/null 2005-01-11 11:29:08.627929972 -0800 +++ programs/Xserver/hw/xfree86/os-support/bus/altixPCI.c 2004-12-17 16:43:46.979666467 -0800 @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * Copyright (C) 2004 Silicon Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +/* + * This file contains the glue necessary for support of SGI's Altix chipset. + */ + +#include "altixPCI.h" +#include "xf86.h" +#include "Pci.h" + +void +xf86PreScanAltix(void) +{ + ErrorF("Came to pre-scan an Altix\n"); + /* XXX Fill me in... */ +} + +void +xf86PostScanAltix(void) +{ + pciConfigPtr pPCI, *ppPCI, *ppPCI2; + pciBusInfo_t *pBusInfo; + int idx=0; + int prevBusNum, curBusNum; + + + ErrorF("Came to post-scan an Altix\n"); + + /* since the Altix IO infrastructure does not have an explicit Bridge + * we will create a bridge device (for now one per Bus) + * + * We will store the bus num and insert a fake device for every + * new bus that we encounter. Then we need to make the pciBusInfo->primary_bus + * and ->bridge pointers, point to the "fake" device that we just created. + */ + + pBusInfo = pciBusInfo[0]; + ppPCI = ppPCI2 = xf86scanpci(0); + prevBusNum = curBusNum = ppPCI[0]->busnum; + ErrorF("Detected a new Bus : Tag = %d %d %d\n", curBusNum, 0, 0); + pBusInfo = pciBusInfo[curBusNum]; + pBusInfo->bridge = ppPCI2[idx]; + pBusInfo->secondary = FALSE; + pBusInfo->primary_bus = curBusNum; + + /* Add a fake PCI-to-PCI bridge to represent each Bus */ + while (ppPCI2[idx] != NULL) { + + if (ppPCI2[idx]->busnum != prevBusNum) { + curBusNum = ppPCI2[idx]->busnum; + + ErrorF("Detected a new Bus : Tag = %d %d %d\n", curBusNum, 0, 0); +#if 0 /* not yet .. we need to fill this in */ + pPCI = xnfcalloc(1, sizeof(pciDevice)); + pPCI->busnum = curBusNum; + pPCI->devnum = 0; + pPCI->funcnum = 0; + pPCI->tag = PCI_MAKE_TAG(curBusNum, pPCI->devnum, 0); + pPCI->pci_device_vendor = VENDOR_SGI; + pPCI->pci_base_class = PCI_CLASS_BRIDGE; + pPCI->pci_sub_class = PCI_SUBCLASS_BRIDGE_PCI; + pPCI->pci_header_type = 1; + pPCI->pci_primary_bus_number = curBusNum; + pPCI->pci_secondary_bus_number = 0; + pPCI->pci_subordinate_bus_number = 0; + pPCI->fakeDevice = TRUE; +#endif /* not yet */ + + pBusInfo = pciBusInfo[curBusNum]; + pBusInfo->bridge = ppPCI2[idx]; + pBusInfo->secondary = FALSE; + pBusInfo->primary_bus = curBusNum; + ppPCI2[idx]->businfo = pBusInfo; + ppPCI2[idx]->pci_base_class = PCI_CLASS_DISPLAY; + ppPCI2[idx]->pci_sub_class = PCI_SUBCLASS_PREHISTORIC_VGA; + + +#if 0 /* not yet */ + /* Plug in chipset routines */ + pBusInfo->funcs = &zx1BusFuncs; + + /* Set bridge control register for scanpci utility */ + pPCI->pci_bridge_control = ControlZX1Bridge(zx1_busno[i], 0, 0); +#endif /* not yet */ + + prevBusNum = curBusNum; + + } +#if 0 /* not yet */ +#ifdef OLD_FORMAT + xf86MsgVerb(X_INFO, 2, "PCI: BusID 0x%.2x,0x%02x,0x%1x " + "ID 0x%04x,0x%04x Rev 0x%02x Class 0x%02x,0x%02x\n", + pPCI->busnum, pPCI->devnum, pPCI->funcnum, + pPCI->pci_vendor, pPCI->pci_device, pPCI->pci_rev_id, + pPCI->pci_base_class, pPCI->pci_sub_class); +#else + xf86MsgVerb(X_INFO, 2, "PCI: %.2x:%02x:%1x: chip %04x,%04x" + " card %04x,%04x rev %02x class %02x,%02x,%02x hdr %02x\n", + pPCI->busnum, pPCI->devnum, pPCI->funcnum, + pPCI->pci_vendor, pPCI->pci_device, + pPCI->pci_subsys_vendor, pPCI->pci_subsys_card, + pPCI->pci_rev_id, pPCI->pci_base_class, + pPCI->pci_sub_class, pPCI->pci_prog_if, + pPCI->pci_header_type); +#endif +#endif /* not yet */ + + /* increment the index */ + idx ++; + } +#if 0 /* not yet */ + *ppPCI = NULL; /* Terminate array */ +#endif /* not yet */ + + + return; +} --- /dev/null 2005-01-11 11:29:08.627929972 -0800 +++ programs/Xserver/hw/xfree86/os-support/bus/altixPCI.h 2004-12-17 16:44:10.163259933 -0800 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * Copyright (C) 2004 Silicon Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifndef PCI_ALTIX_H +#define PCI_ALTIX_H 1 + +#include +#include + +Bool xorgProbeAltix(scanpciWrapperOpt flags); +void xf86PreScanAltix(void); +void xf86PostScanAltix(void); + +/* Some defines for PCI */ +#define VENDOR_SGI 0x10A9 +#define CHIP_TIO_CA 0x1010 +#define CHIP_PIC_PCI 0x1011 + +#endif