Index: extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h =================================================================== RCS file: /cvs/xorg/xc/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h,v retrieving revision 1.1.1.1 diff -r1.1.1.1 radeon_dri.h 57c57 < #define RADEON_BUFFER_ALIGN 0x00000fff --- > #define RADEON_BUFFER_ALIGN 0x0000ffff Index: extras/drm/shared/radeon_cp.c =================================================================== RCS file: /cvs/xorg/xc/extras/drm/shared/radeon_cp.c,v retrieving revision 1.1.1.1 diff -r1.1.1.1 radeon_cp.c 38a39 > #if 1 39a41,300 > static u32 R200_cp_microcode[][2] { > { 0x4200e000, 0000000000 }, // 00: iREQ;oAddr=base;oDATA=PM4;oREQ;oRDY;base++; > { 0x4000e000, 0000000000 }, // 01: iREQ;oAddr=base;oDATA=PM4;oREQ;oRDY; > { 0x000000b3, 0x00000008 }, // 02: goto @P_PACKETTYPE1; > { 0x000000b7, 0x00000008 }, // 03: goto @DP_GUI_MASTER_CNTL_HANDLER; > { 0x6c5a504f, 0000000000 }, // 04: constBytes % @H_NOP,@H_PAINT,@H_BITBLT,@H_SMALLTEXT; > { 0x4f4f497a, 0000000000 }, // 05: constBytes % @H_HOSTDATA_R3BLT,@H_POLYLINE,@H_NOP,@H_NOP; > { 0x5a578288, 0000000000 }, // 06: constBytes % @H_POLYSCANLINE,@H_NEXTCHAR,@H_PAINT_BB,@H_BITBLT; > { 0x4f91906a, 0000000000 }, // 07: constBytes % @H_BITBLT_TRANSPARENT,@H_PLY_NEXTSCAN,@H_SETSCISSORS,@H_NOP; > { 0x4f4f4f4f, 0000000000 }, // 08: constBytes % @H_NOP,@H_NOP,@H_NOP,@H_NOP; > { 0x4fe64f44, 0000000000 }, // 09: constBytes % @H_LOADMICROCODE,@H_NOP,@WAIT_FOR_IDLE,@H_NOP; > { 0xe99c9c9c, 0000000000 }, // 0A: constBytes % @H_3D_DRAW_VBUF,@H_3D_DRAW_IMMD,@H_3D_DRAW_INDX,@H_3D_DRAW_N3FV3F; > { 0xe04ff0e2, 0000000000 }, // 0B: constBytes % @H_LOAD_PALETTE,@H_3D_DRAW_V3F,@H_NOP,@H_3D_LOAD_VBPNTR; > { 0xa1d14f4f, 0000000000 }, // 0C: constBytes % @H_NOP,@H_NOP,@H_3D_CLEAR_ZMASK,@H_INDX_BUFFER; > { 0xd69d9d9d, 0000000000 }, // 0D: constBytes % @H_3D_DRAW_VBUF_2,@H_3D_DRAW_IMMD_2,@H_3D_DRAW_INDX_2,@H_3D_CLEAR_HIZ; > { 0x4f0f9fdb, 0000000000 }, // 0E: constBytes % @H_3D_CLEAR_CMASK,@H_3D_DRAW_128,@H_MPEG_INDEX,@H_NOP; > { 0x000ca000, 0x00000004 }, // 0F: @H_MPEG_INDEX: iREQ;oRDY;acc=pm4;cont; > { 0x000d0012, 0x00000038 }, // 10: jacceven @MPI_0;acc=acc>>1; > { 0x0000e8b4, 0x00000004 }, // 11: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PVS_CODE_CNTL_0;cont; > { 0x000d0014, 0x00000038 }, // 12: @MPI_0: jacceven @MPI_1;acc=acc>>1; > { 0x0000e8b6, 0x00000004 }, // 13: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PVS_CODE_CNTL_1;cont; > { 0x000d0016, 0x00000038 }, // 14: @MPI_1: jacceven @MPI_2;acc=acc>>1; > { 0x0000e854, 0x00000004 }, // 15: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_0;cont; > { 0x000d0018, 0x00000038 }, // 16: @MPI_2: jacceven @MPI_3;acc=acc>>1; > { 0x0000e855, 0x00000004 }, // 17: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_1;cont; > { 0x000d001a, 0x00000038 }, // 18: @MPI_3: jacceven @MPI_4;acc=acc>>1; > { 0x0000e856, 0x00000004 }, // 19: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_2;cont; > { 0x000d001c, 0x00000038 }, // 1A: @MPI_4: jacceven @MPI_5;acc=acc>>1; > { 0x0000e857, 0x00000004 }, // 1B: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_PROG_STREAM_CNTL_3;cont; > { 0x000d001e, 0x00000038 }, // 1C: @MPI_5: jacceven @MPI_6;acc=acc>>1; > { 0x0000e824, 0x00000004 }, // 1D: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_OUT_VTX_FMT_0;cont; > { 0x000d0020, 0x00000038 }, // 1E: @MPI_6: jacceven @MPI_7;acc=acc>>1; > { 0x0000e825, 0x00000004 }, // 1F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_OUT_VTX_FMT_1;cont; > { 0x000d0022, 0x00000038 }, // 20: @MPI_7: jacceven @MPI_8;acc=acc>>1; > { 0x0000e830, 0x00000004 }, // 21: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_NUM_ARRAYS;cont; > { 0x000d0024, 0x00000038 }, // 22: @MPI_8: jacceven @MPI_9;acc=acc>>1; > { 0x0000f0c0, 0x00000004 }, // 23: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRS_COUNT;cont; > { 0x000d0026, 0x00000038 }, // 24: @MPI_9: jacceven @MPI_10;acc=acc>>1; > { 0x0000f0c1, 0x00000004 }, // 25: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRS_INST_COUNT;cont; > { 0x000d0028, 0x00000038 }, // 26: @MPI_10: jacceven @MPI_11;acc=acc>>1; > { 0x0000f041, 0x00000004 }, // 27: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmTX_ENABLE;cont; > { 0x000d002a, 0x00000038 }, // 28: @MPI_11: jacceven @MPI_12;acc=acc>>1; > { 0x0000f184, 0x00000004 }, // 29: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_0;cont; > { 0x000d002c, 0x00000038 }, // 2A: @MPI_12: jacceven @MPI_13;acc=acc>>1; > { 0x0000f185, 0x00000004 }, // 2B: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_1;cont; > { 0x000d002e, 0x00000038 }, // 2C: @MPI_13: jacceven @MPI_14;acc=acc>>1; > { 0x0000f186, 0x00000004 }, // 2D: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_2;cont; > { 0x000d0030, 0x00000038 }, // 2E: @MPI_14: jacceven @MPI_15;acc=acc>>1; > { 0x0000f187, 0x00000004 }, // 2F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CODE_ADDR_3;cont; > { 0x000d0032, 0x00000038 }, // 30: @MPI_15: jacceven @MPI_16;acc=acc>>1; > { 0x0000f180, 0x00000004 }, // 31: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmUS_CONFIG;cont; > { 0x000d0034, 0x00000038 }, // 32: @MPI_16: jacceven @MPI_17;acc=acc>>1; > { 0x0000f393, 0x00000004 }, // 33: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRB3D_DSTCACHE_CTLSTAT;cont; > { 0x000d0036, 0x00000038 }, // 34: @MPI_17: jacceven @MPI_18;acc=acc>>1; > { 0x0000f38a, 0x00000004 }, // 35: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRB3D_COLOROFFSET0;cont; > { 0x000d0038, 0x00000038 }, // 36: @MPI_18: jacceven @MPI_19;acc=acc>>1; > { 0x0000f38e, 0x00000004 }, // 37: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmRB3D_COLORPITCH0;cont; > { 0x0000e821, 0x00000004 }, // 38: @MPI_19: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VF_CNTL;cont; > { 0x0140a000, 0x00000004 }, // 39: iREQ;oRDY;index=pm4[13:0];cont; > { 0x00000043, 0x00000018 }, // 3A: @MPI_INDEX_LOOP: jindexz @MPI_END; > { 0x00cce800, 0x00000004 }, // 3B: iREQ;oREQ;oRDY;acc=pm4;oaddr=ram;odata=pm4;address=mmVAP_PORT_DATA0;index--;cont; > { 0x001b0001, 0x00000004 }, // 3C: accl+=ram;address=01;cont; > { 0x08004800, 0x00000004 }, // 3D: oREQ;oaddr=ram;odata=acc;address=mmVAP_PORT_DATA0;cont; > { 0x001b0001, 0x00000004 }, // 3E: accl+=ram;address=01;cont; > { 0x08004800, 0x00000004 }, // 3F: oREQ;oaddr=ram;odata=acc;address=mmVAP_PORT_DATA0;cont; > { 0x001b0001, 0x00000004 }, // 40: accl+=ram;address=01;cont; > { 0x08004800, 0x00000004 }, // 41: oREQ;oaddr=ram;odata=acc;address=mmVAP_PORT_DATA0;cont; > { 0x0000003a, 0x00000008 }, // 42: goto @MPI_INDEX_LOOP; > { 0x0000a000, 0000000000 }, // 43: @MPI_END: iREQ;oRDY; > { 0x02c0a000, 0x00000004 }, // 44: @H_LOADMICROCODE: iREQ;oRDY;LDBASEINDEXPM4;cont; > { 0x000ca000, 0x00000004 }, // 45: @H_LOADMICROCODE_LOOP: iREQ;oRDY;acc=pm4;cont; > { 0x00130000, 0x00000004 }, // 46: scr=accl;cont; > { 0x000c2000, 0x00000004 }, // 47: iREQ;acc=pm4;cont; > { 0xc980c045, 0x00000008 }, // 48: oREQ;oRDY;oAddr=base;dst=ram;odata=acc;index-- base++;goto @H_LOADMICROCODE_LOOP; > { 0x2000451d, 0x00000004 }, // 49: @H_POLYLINE: oREQ;oaddr=ram;odata=0;address=mmBRUSH_Y_X;cont; > { 0x0000e580, 0x00000004 }, // 4A: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmDST_LINE_START;cont; > { 0x000ce581, 0x00000004 }, // 4B: iREQ;oREQ;oRDY;acc=pm4;oaddr=ram;odata=pm4;address=mmDST_LINE_END;cont; > { 0x08004580, 0x00000004 }, // 4C: @H_POLYLINE_LOOP: oREQ;oaddr=ram;odata=acc;address=mmDST_LINE_START;cont; > { 0x000ce581, 0x00000004 }, // 4D: iREQ;oREQ;oRDY;acc=pm4;oaddr=ram;odata=pm4;address=mmDST_LINE_END;cont; > { 0x0000004c, 0x00000008 }, // 4E: goto @H_POLYLINE_LOOP; > { 0x0000a000, 0000000000 }, // 4F: @H_NOP: iREQ;oRDY; > { 0x000c2000, 0x00000004 }, // 50: @H_PAINT: iREQ;acc=pm4;cont; > { 0x0000e50e, 0x00000004 }, // 51: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_Y_X;cont; > { 0x00032000, 0x00000004 }, // 52: iREQ;ACCL=pm4[15:0]-ACCL;cont; > { 0x00022056, 0x00000028 }, // 53: iREQ;ACCH=pm4[31:16]-ACCH;jacclsign @HH_PAINT_END; > { 0x00000056, 0x00000024 }, // 54: jacchsign @HH_PAINT_END; > { 0x0800450f, 0x00000004 }, // 55: oREQ;oData=acc;oAddr=ram;address=mmDST_HEIGHT_WIDTH;cont; > { 0x0000a050, 0x00000008 }, // 56: @HH_PAINT_END: iREQ;oRDY;goto @H_PAINT; > { 0x0000e565, 0x00000004 }, // 57: @H_PAINT_BB: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_X_Y;cont; > { 0x0000e566, 0x00000004 }, // 58: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_WIDTH_HEIGHT;cont; > { 0x00000057, 0x00000008 }, // 59: @HH_PAINT_BB_END: goto @H_PAINT_BB; > { 0x03cca5b4, 0x00000004 }, // 5A: @H_BITBLT_HACK: @H_BITBLT: iREQ;oRDY;acc=pm4;ldbase;address=mmDP_CNTL_XDIR_YDIR_YMAJOR;cont; > { 0x05432000, 0x00000004 }, // 5B: iREQ;accl=pm4[15:0]-accl;scr32=acc;cont; > { 0x00022000, 0x00000004 }, // 5C: iREQ;acch=pm4[31:16]-acch;cont; > { 0x4ccce063, 0x00000030 }, // 5D: iREQ;oREQ;oRDY;odata=acc;oaddr=base;base=accsign;acc=pm4;call @H_BITBLT_ADDHW; > { 0x08274565, 0x00000004 }, // 5E: oREQ;acc=scr32;odata=acc;oaddr=ram;address=mmDST_X_Y;cont; > { 0x00000063, 0x00000030 }, // 5F: call @H_BITBLT_ADDHW; > { 0x08004564, 0x00000004 }, // 60: oREQ;odata=acc;oaddr=ram;address=mmSRC_X_Y;cont; > { 0x0000e566, 0x00000004 }, // 61: iREQ;oREQ;oRDY;odata=pm4;oaddr=ram;address=mmDST_WIDTH_HEIGHT;cont; > { 0x0000005a, 0x00000008 }, // 62: goto @H_BITBLT_HACK; > { 0x00802066, 0x00000010 }, // 63: @H_BITBLT_ADDHW: iREQ;index++;jtstb @H_BITBLT_SKIPH; > { 0x00202000, 0x00000004 }, // 64: iREQ;accl=pm4[15:0]+accl;cont; > { 0x001b00ff, 0x00000004 }, // 65: accl+=ram;address=ff;cont; > { 0x01000069, 0x00000010 }, // 66: @H_BITBLT_SKIPH: index=0;jtstb @H_BITBLT_SKIPW; > { 0x001f2000, 0x00000004 }, // 67: iREQ;acch=pm4[31:16]+acch;cont; > { 0x001c00ff, 0x00000004 }, // 68: acch+=ram;address=ff;cont; > { 0000000000, 0x0000000c }, // 69: @H_BITBLT_SKIPW: retmark; > { 0x00000085, 0x00000030 }, // 6A: @H_BITBLT_TRANSPARENT: call @H_COLORCMP; > { 0x0000005a, 0x00000008 }, // 6B: goto @H_BITBLT; > { 0x0000e576, 0x00000004 }, // 6C: @H_SMALLTEXT: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDP_SRC_FRGD_CLR;cont; > { 0x000ca000, 0x00000004 }, // 6D: iREQ;acc=pm4;oRDY;cont; > { 0x00012000, 0x00000004 }, // 6E: @ST_CHARLOOP: iREQ;accl=pm4[7:0]+accl;cont; > { 0x00082000, 0x00000004 }, // 6F: iREQ;scr=acch-pm4[15:8];cont; > { 0x1800650e, 0x00000004 }, // 70: iREQ;oREQ;oData=scraccl;oAddr=ram;address=mmDST_Y_X;cont; > { 0x00092000, 0x00000004 }, // 71: iREQ;scr=pm4[31:24]*pm4[23:16];cont; > { 0x000a2000, 0x00000004 }, // 72: iREQ;scr=scr+31;oData=pm4;cont; > { 0x000f0000, 0x00000004 }, // 73: scr=scr>>5;cont; > { 0x00400000, 0x00000004 }, // 74: index=scr;cont; > { 0x00000079, 0x00000018 }, // 75: jindexz @ST_CHARLOOP_CONT; > { 0x0000e563, 0x00000004 }, // 76: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_WIDTH_8;cont; > { 0x00c0e5f0, 0x000000c2 }, // 77: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmHOST_DATA0;wc_indexnz;index--;ccont_indexz;vcnt_sel_index; > { 0x0000006e, 0x00000008 }, // 78: goto @ST_CHARLOOP; > { 0x0000a06e, 0x00000008 }, // 79: @ST_CHARLOOP_CONT: iREQ;oRDY;goto @ST_CHARLOOP; > { 0x0000e576, 0x00000004 }, // 7A: @H_HOSTDATA_R3BLT: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDP_SRC_FRGD_CLR;cont; > { 0x0000e577, 0x00000004 }, // 7B: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDP_SRC_BKGD_CLR;cont; > { 0x0000e50e, 0x00000004 }, // 7C: @HD_OUTERLOOPSTART: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_Y_X;cont; > { 0x0000e50f, 0x00000004 }, // 7D: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_WIDTH;cont; > { 0x0140a000, 0x00000004 }, // 7E: iREQ;oRDY;index=pm4[13:0];cont; > { 0x0000007c, 0x00000018 }, // 7F: @N_NEXTCHAR_CONT: jindexz @HD_OUTERLOOPSTART; > { 0x00c0e5f0, 0x000000c2 }, // 80: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmHOST_DATA0;index--;wc_indexnz;ccont_indexz;vcnt_sel_index; > { 0x0000007c, 0x00000008 }, // 81: goto @HD_OUTERLOOPSTART; > { 0x0014e50e, 0x00000004 }, // 82: @H_NEXTCHAR: iREQ;oREQ;oRDY;scr=acch;oData=pm4;oAddr=ram;address=mmDST_Y_X;cont; > { 0x0040e50f, 0x00000004 }, // 83: iREQ;oREQ;oRDY;index=scr;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_WIDTH;cont; > { 0x00c0007f, 0x00000008 }, // 84: index--;goto @N_NEXTCHAR_CONT; > { 0x0000e570, 0x00000004 }, // 85: @H_COLORCMP: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmCLR_CMP_CNTL;cont; > { 0x0000e571, 0x00000004 }, // 86: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmCLR_CMP_CLR_SRC;cont; > { 0x0000e572, 0x0000000c }, // 87: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmCLR_CMP_CLR_DST;retmark; > { 0x0000a000, 0x00000004 }, // 88: @H_POLYSCANLINE: iREQ;oRDY;cont; > { 0x0140a000, 0x00000004 }, // 89: @H_POLYSCANLINE1: iREQ;index=pm4[13:0];oRDY;cont; > { 0x0000e568, 0x00000004 }, // 8A: @H_POLYSCANLINE2: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmDST_HEIGHT_Y;cont; > { 0x000c2000, 0x00000004 }, // 8B: @PLY_SUBPACKETBODY: iREQ;acc=pm4;cont; > { 0x00000089, 0x00000018 }, // 8C: jindexz @H_POLYSCANLINE1; > { 0x000b0000, 0x00000004 }, // 8D: scr=acch-accl;cont; > { 0x18c0e562, 0x00000004 }, // 8E: iREQ;oREQ;oRDY;oData=scraccl;oAddr=ram;address=mmDST_WIDTH_X;index--;cont; > { 0x0000008b, 0x00000008 }, // 8F: goto @PLY_SUBPACKETBODY; > { 0x00c0008a, 0x00000008 }, // 90: @H_PLY_NEXTSCAN: index--;goto @H_POLYSCANLINE2; > { 0x000700e8, 0x00000004 }, // 91: @H_SETSCISSORS: acc=ram[addr];address=@V_24BPPMODE;cont; > { 0x00000097, 0x00000038 }, // 92: jacceven @H_SETSC_N24; > { 0x000ca099, 0x00000030 }, // 93: @H_SETSC_24: iREQ;oRDY;acc=pm4;call @SC_TRIPLICATEX; > { 0x080045bb, 0x00000004 }, // 94: oREQ;oData=acc;oAddr=ram;address=mmSC_TOP_LEFT;cont; > { 0x000c209a, 0x00000030 }, // 95: iREQ;acc=pm4;call @SC_TRIPLICATEX_A2; > { 0x0800e5bc, 0000000000 }, // 96: iREQ;oRDY;oREQ;oData=acc;oAddr=ram;address=mmSC_BOTTOM_RIGHT; > { 0x0000e5bb, 0x00000004 }, // 97: @H_SETSC_N24: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmSC_TOP_LEFT;cont; > { 0x0000e5bc, 0000000000 }, // 98: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmSC_BOTTOM_RIGHT; > { 0x00120000, 0x0000000c }, // 99: @SC_TRIPLICATEX: accl=accl*3;retmark; > { 0x00120000, 0x00000004 }, // 9A: @SC_TRIPLICATEX_A2: accl=accl*3;cont; > { 0x001b0002, 0x0000000c }, // 9B: accl+=ram;address=2;retmark; > { 0x0000a000, 0x00000004 }, // 9C: @H_3D_DRAW_VBUF: @H_3D_DRAW_IMMD: @H_3D_DRAW_INDX: iREQ;oRDY;cont; > { 0x0000e821, 0x00000004 }, // 9D: @H_3D_DRAW_VBUF_2: @H_3D_DRAW_IMMD_2: @H_3D_DRAW_INDX_2: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_VF_CNTL;cont; > { 0x0000e800, 0000000000 }, // 9E: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_PORT_DATA0; > { 0x0000e821, 0x00000004 }, // 9F: @H_3D_DRAW_128: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_VF_CNTL;cont; > { 0x0000e82e, 0000000000 }, // A0: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmVAP_PORT_DATA_IDX_128; > { 0x02cca000, 0x00000004 }, // A1: @H_INDX_BUFFER: iREQ;oRDY;ldbaseindexpm4;acc=pm4;cont; > { 0x00140000, 0x00000004 }, // A2: scr=acch;cont; > { 0x000ce1cc, 0x00000004 }, // A3: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmCP_IB2_BASE;acc=pm4;cont; > { 0x050de1cd, 0x00000004 }, // A4: iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmCP_IB2_BUFSZ;cnt=pm4[22:0]-1;acc=acc>>1;cont; > { 0x00400000, 0x00000004 }, // A5: index=scr;cont; > { 0x000000a9, 0x00000018 }, // A6: @H_INDX_BUFFER_KILL: jindexz @H_INDX_BUFFER_CONT; > { 0x00c0a000, 0x00000004 }, // A7: iREQ;oRDY;index--;cont; > { 0x000000a6, 0x00000008 }, // A8: goto @H_INDX_BUFFER_KILL; > { 0x000000ab, 0x00000020 }, // A9: @H_INDX_BUFFER_CONT: jscrsign @H_INDEX_BUFFER_NOINC; > { 0x4200e000, 0000000000 }, // AA: iREQ;oRDY;oREQ;oData=pm4;oAddr=base;base++; > { 0x000000b2, 0x00000038 }, // AB: @H_INDEX_BUFFER_NOINC: jacceven @H_INDEX_ALIGNED; > { 0x000ca000, 0x00000004 }, // AC: iREQ;oRDY;acc=pm4;cont; > { 0x00140000, 0x00000004 }, // AD: scr=acch;cont; > { 0x000c2000, 0x00000004 }, // AE: @H_INDEX_WORD_LOOP: iREQ;acc=pm4;cont; > { 0x00160000, 0x00000004 }, // AF: acch=scr;cont; > { 0x700ce000, 0x00000004 }, // B0: iREQ;oRDY;oREQ;oData=acclacch;oAddr=base;acc=pm4;cont; > { 0x001400ae, 0x00000008 }, // B1: goto @H_INDEX_WORD_LOOP;scr=acch; > { 0x4000e000, 0000000000 }, // B2: @H_INDEX_ALIGNED: iREQ;oRDY;oREQ;oData=pm4;oAddr=base; > { 0x02400000, 0x00000004 }, // B3: @P_PACKETTYPE1: base=acc[10:0];cont; > { 0x400ee000, 0x00000004 }, // B4: iREQ;oREQ;oRDY;oAddr=base;acc=acc>>11;oData=pm4;cont; > { 0x02400000, 0x00000004 }, // B5: base=acc[10:0];cont; > { 0x4000e000, 0000000000 }, // B6: iREQ;oREQ;oRDY;oAddr=base;oData=pm4; > { 0x000c2000, 0x00000004 }, // B7: @DP_GUI_MASTER_CNTL_HANDLER: iREQ;ACC=PM4;cont; > { 0x0240e51b, 0x00000004 }, // B8: oREQ;iREQ;oDATA=pm4;base=acc[10:0];oRDY;cont;ADDRESS=mmDP_GUI_MASTER_CNTL; > { 0x0080e50a, 0x00000005 }, // B9: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSRC_PITCH_OFFSET;oAddr=ram;cont; > { 0x0080e50b, 0x00000005 }, // BA: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmDST_PITCH_OFFSET;oAddr=ram;cont; > { 0x00220000, 0x00000004 }, // BB: rf=acc;address=0;cont; > { 0x000700e8, 0x00000004 }, // BC: acc=ram[addr];address=@V_24BPPMODE;cont; > { 0x000000c5, 0x00000038 }, // BD: jacceven @GMC_SC_N24; > { 0x000c209a, 0x00000030 }, // BE: @GMC_SC_24: iREQ;acc=pm4;call @SC_TRIPLICATEX_A2; > { 0x0880e5bd, 0x00000005 }, // BF: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSRC_SC_BOTTOM_RIGHT;oAddr=ram;oData=acc;cont; > { 0x000c2099, 0x00000030 }, // C0: iREQ;acc=pm4;call @SC_TRIPLICATEX; > { 0x0800e5bb, 0x00000005 }, // C1: wc_tstb;iREQ;oREQ;oRDY;ADDRESS=mmSC_TOP_LEFT;oAddr=ram;oData=acc;cont; > { 0x000c209a, 0x00000030 }, // C2: iREQ;acc=pm4;call @SC_TRIPLICATEX_A2; > { 0x0880e5bc, 0x00000005 }, // C3: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSC_BOTTOM_RIGHT;oAddr=ram;oData=acc;cont; > { 0x000000c8, 0x00000008 }, // C4: goto @PR_LOADBRUSH; > { 0x0080e5bd, 0x00000005 }, // C5: @GMC_SC_N24: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSRC_SC_BOTTOM_RIGHT;oAddr=ram;cont; > { 0x0000e5bb, 0x00000005 }, // C6: wc_tstb;iREQ;oREQ;oRDY;ADDRESS=mmSC_TOP_LEFT;oAddr=ram;cont; > { 0x0080e5bc, 0x00000005 }, // C7: wc_tstb;index++;iREQ;oREQ;oRDY;ADDRESS=mmSC_BOTTOM_RIGHT;oAddr=ram;cont; > { 0x00210000, 0x00000004 }, // C8: @PR_LOADBRUSH: acc=rf;address=0;cont; > { 0x02800000, 0x00000004 }, // C9: LDBRUSH;cont; > { 0x00c000cc, 0x00000018 }, // CA: index--;jindexz @PR_BRUSHLOOPEND; > { 0x4180e000, 0x00000040 }, // CB: @PR_BRUSHLOOPSTART: iREQ;oREQ;oAddr=base;oRDY;index-- base++;ccont_indexz; > { 0x000000ce, 0x00000024 }, // CC: @PR_BRUSHLOOPEND: jacchsign @PR_WR_BRUSH_Y_X; > { 0x01000000, 0x0000000c }, // CD: @PR_RET: index=0;retmark; > { 0x0100e51d, 0x0000000c }, // CE: @PR_WR_BRUSH_Y_X: index=0;iREQ;oRDY;oREQ;oData=pm4;oAddr=ram;address=mmBRUSH_Y_X;retmark; > { 0x000045bb, 0x00000004 }, // CF: @GMC_SC_TL_OVERWRITE: oREQ;ADDRESS=mmSC_TOP_LEFT;oAddr=ram;oData=pm4;cont; > { 0x000080c8, 0x00000008 }, // D0: oRDY;goto @PR_LOADBRUSH; > { 0x0000f3ce, 0x00000004 }, // D1: @H_3D_CLEAR_ZMASK: iREQ;oRDY;oREQ;odata=pm4;oAddr=ram;address=mmZB_ZMASK_WRINDEX;cont; > { 0x0140a000, 0x00000004 }, // D2: iREQ;oRDY;index=pm4[13:0];cont; > { 0x00cc2000, 0x00000004 }, // D3: iREQ;acc=pm4;index--;cont; > { 0x08c053cf, 0x00000040 }, // D4: oREQ;odata=acc;oAddr=ram;address=mmZB_ZMASK_DWORD;index--;ccont_indexz; > { 0x00008000, 0000000000 }, // D5: oRDY; > { 0x0000f3d2, 0x00000004 }, // D6: @H_3D_CLEAR_HIZ: iREQ;oRDY;oREQ;odata=pm4;oAddr=ram;address=mmZB_HIZ_WRINDEX;cont; > { 0x0140a000, 0x00000004 }, // D7: iREQ;oRDY;index=pm4[13:0];cont; > { 0x00cc2000, 0x00000004 }, // D8: iREQ;acc=pm4;index--;cont; > { 0x08c053d3, 0x00000040 }, // D9: oREQ;odata=acc;oAddr=ram;address=mmZB_HIZ_DWORD;index--;ccont_indexz; > { 0x00008000, 0000000000 }, // DA: oRDY; > { 0x0000f39d, 0x00000004 }, // DB: @H_3D_CLEAR_CMASK: iREQ;oRDY;oREQ;odata=pm4;oAddr=ram;address=mmRB3D_CMASK_WRINDEX;cont; > { 0x0140a000, 0x00000004 }, // DC: iREQ;oRDY;index=pm4[13:0];cont; > { 0x00cc2000, 0x00000004 }, // DD: iREQ;acc=pm4;index--;cont; > { 0x08c0539e, 0x00000040 }, // DE: oREQ;odata=acc;oAddr=ram;address=mmRB3D_CMASK_DWORD;index--;ccont_indexz; > { 0x00008000, 0000000000 }, // DF: oRDY; > { 0x03c00830, 0x00000004 }, // E0: @H_3D_LOAD_VBPNTR: ldbase;address=mmVAP_VTX_NUM_ARRAYS;oAddr=ram;cont; > { 0x4200e000, 0000000000 }, // E1: iREQ;oREQ;oRDY;odata=pm4;oAddr=base;base++; > { 0x0000a000, 0x00000004 }, // E2: @H_LOAD_PALETTE: iREQ;oRDY;cont; > { 0x200045e0, 0x00000004 }, // E3: oREQ;address=mmSRC_CLUT_ADDRESS;odata=0;oaddr=ram;cont; > { 0x0000e5e1, 0000000000 }, // E4: iREQ;oREQ;oRDY;oData=pm4;oAddr=ram;address=mmSRC_CLUT_DATA; > { 0x00000001, 0000000000 }, // E5: @C_00000001: constant 00000001; > { 0x000700e5, 0x00000004 }, // E6: @WAIT_FOR_IDLE: acc=ram[addr];address=@C_00000001;cont; > { 0x0800e394, 0000000000 }, // E7: iREQ;oRDY;oREQ;oData=acc;oAddr=ram;address=mmNQWAIT_UNTIL; > { 0000000000, 0000000000 }, // E8: @V_24BPPMODE: constant 0; > { 0x0000e8c4, 0x00000004 }, // E9: @H_3D_DRAW_N3FV3F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_NORM_0_X;cont; > { 0x0000e8c5, 0x00000004 }, // EA: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_NORM_0_Y;cont; > { 0x0000e8c6, 0x00000004 }, // EB: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_NORM_0_Z;cont; > { 0x0000e928, 0x00000004 }, // EC: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_X_3;cont; > { 0x0000e929, 0x00000004 }, // ED: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Y_3;cont; > { 0x0000e92a, 0x00000004 }, // EE: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Z_3;cont; > { 0x000000e9, 0x00000008 }, // EF: goto @H_3D_DRAW_N3FV3F; > { 0x0000e928, 0x00000004 }, // F0: @H_3D_DRAW_V3F: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_X_3;cont; > { 0x0000e929, 0x00000004 }, // F1: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Y_3;cont; > { 0x0000e92a, 0x00000004 }, // F2: iREQ;oREQ;oRDY;oaddr=ram;odata=pm4;address=mmVAP_VTX_ST_POS_0_Z_3;cont; > { 0x000000f0, 0x00000008 }, // F3: goto @H_3D_DRAW_V3F; > { 0000000000, 0000000000 }, // F4: > { 0000000000, 0000000000 }, // F5: > { 0000000000, 0000000000 }, // F6: > { 0000000000, 0000000000 }, // F7: > { 0000000000, 0000000000 }, // F8: > { 0000000000, 0000000000 }, // F9: > { 0000000000, 0000000000 }, // FA: > { 0000000000, 0000000000 }, // FB: > { 0000000000, 0000000000 }, // FC: > { 0000000000, 0000000000 }, // FD: > { 0000000000, 0000000000 }, // FE: > { 0000000000, 0000000000 }, // FF: > }; // Array aPM4_Microcode contains 256 micro-instructions. > > #else 300c561 < --- > #endif // 0 984a1246 > DRM_DEBUG("Setting PCI_GART\n"); 987a1250 > DRM_DEBUG("Setting AIC_PT_BASE 0x%lx \n", dev_priv->bus_pci_gart ); 994a1258,1261 > DRM_DEBUG("Setting AIC_LO_BASE 0x%lx \n", dev_priv->gart_vm_start ); > DRM_DEBUG("Setting AIC_HI_BASE 0x%lx \n", (dev_priv->gart_vm_start + > dev_priv->gart_size -1 )); > Index: lib/Xpm/Imakefile =================================================================== RCS file: /cvs/xorg/xc/lib/Xpm/Imakefile,v retrieving revision 1.4 diff -r1.4 Imakefile 30c30 < ZFILEDEF = -DSTAT_ZFILE --- > ZFILEDEF = -DSTAT_ZFILE -DNO_ZPIPE Index: programs/Xserver/GL/dri/dri.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/GL/dri/dri.c,v retrieving revision 1.6 diff -r1.6 dri.c 278c278 < "[drm] added %d byte SAREA at 0x%08lx\n", --- > "[drm] added %d byte SAREA at 0x%016lx\n", 294c294 < DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] mapped SAREA 0x%08lx to %p\n", --- > DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] mapped SAREA 0x%016lx to %p\n", 312c312 < DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] framebuffer handle = 0x%08lx\n", --- > DRIDrvMsg(pScreen->myNum, X_INFO, "[drm] framebuffer handle = 0x%016lx\n", 375c375 < "X context handle = 0x%08lx\n", pDRIPriv->myContext); --- > "X context handle = 0x%016lx\n", pDRIPriv->myContext); 559c559 < "[drm] unmapping %d bytes of SAREA 0x%08lx at %p\n", --- > "[drm] unmapping %d bytes of SAREA 0x%016lx at %p\n", 566c566 < " of SAREA 0x%08lx at %p\n", --- > " of SAREA 0x%016lx at %p\n", Index: programs/Xserver/GL/dri/dri.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/GL/dri/dri.h,v retrieving revision 1.3 diff -r1.3 dri.h 144c144 < CARD32 frameBufferPhysicalAddress; --- > CARD64 frameBufferPhysicalAddress; Index: programs/Xserver/hw/xfree86/common/compiler.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/common/compiler.h,v retrieving revision 1.3 diff -r1.3 compiler.h 61c61 < #if defined(__SUNPRO_C) --- > #if defined(__SUNPRO_C) 127c127,128 < && !(defined(__alpha__) && defined(linux)) --- > && !(defined(__alpha__) && defined(linux)) \ > && !(defined(__ia64__) && defined(linux)) \ 165c166 < # if (defined(linux) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)) && defined(__alpha__) --- > # if (defined(linux) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)) && (defined(__alpha__)) 397c398 < # define mem_barrier() __asm__ __volatile__("mb" : : : "memory") --- > # define mem_barrier() __asm__ __volatile__("mf" : : : "memory") 399c400 < # define write_mem_barrier() __asm__ __volatile__("wmb" : : : "memory") --- > # define write_mem_barrier() __asm__ __volatile__("mf" : : : "memory") 404d404 < 466a467 > # define io_mem_barrier() __asm__ __volatile__ ("mf.a" ::: "memory") 470a472 > # define io_mem_barrier() __mfa 493c495,507 < # endif --- > # endif /* __INTEL_COMPILER */ > > /* > * It seems like the in/out routines in this file could be consolidated a bit > * and/or split into multiple, arch specific header files. > * > * Many also assume that the 'port' value passed in is an actual address, > * rather than relative to some 'IOBase' value. This means that callers > * have to be fixed up to get their own 'IOBase' (which will be PCI device > * specific), or the inX/outX routines need to be changed to take a PCI > * tag so that platforms can route the PIOs to the correct bus. > */ > 497c511,513 < --- > > #if !defined(__altix__) > 501a518,640 > #else /* __altix */ > > /* > * Deal with outX on platforms where it's simply a store. > */ > > #undef outb > #undef outw > #undef outl > > static __inline__ void outb(unsigned long port, unsigned char val) > { > volatile unsigned char *addr = (unsigned char *)port; > > ErrorF("outb(0x%lx) = 0x%x\n", port, val); > *addr = val; > io_mem_barrier(); > } > > static __inline__ void outw(unsigned long port, unsigned short val) > { > volatile unsigned short *addr = (unsigned char *)port; > > ErrorF("outw(0x%lx) = 0x%x\n", port, val); > *addr = val; > io_mem_barrier(); > } > > static __inline__ void outl(unsigned long port, unsigned int val) > { > volatile unsigned int *addr = (unsigned char *)port; > > ErrorF("outl(0x%lx) = 0x%x\n", port, val); > *addr = val; > io_mem_barrier(); > } > > # undef inb > # undef inw > # undef inl > > /* > * Deal with master aborts on a really funky platform. The kernel will send > * a SIGBUS to applications that have mapped /proc/bus/pci/... when an I/O > * error, like a master abort, occurs. > * > * On ia64, an error caused by an uncached read may (and probably will) be > * reported to software *way* after the instruction that did the read. The > * only way to be sure that any errors that might occur have been flushed out > * is to use the value we get back in a statement that affects control flow. > * > * Note that on some platforms, an PIO read does *not* guarantee that DMA > * initiated prior to the PIO is complete. > */ > extern int ia64_io_error; > > static __inline__ unsigned int inb(unsigned long port) > { > unsigned int val; > > /* The SIGBUS handler will set this for us if an error occurs */ > ia64_io_error = 0; > > val = (unsigned int) (*((volatile unsigned char *)port)); > > /* Use val in an expression to flush out errors */ > if (val && ia64_io_error) > val = -1; > > /* Double check for an error */ > if (ia64_io_error) > val = -1; > > ErrorF("inb(0x%lx) = 0x%x\n", port, val); > /* val was actually read from the hardware */ > return val; > } > > static __inline__ unsigned int inw(unsigned long port) > { > unsigned int val; > > /* The SIGBUS handler will set this for us if an error occurs */ > ia64_io_error = 0; > > val = (unsigned int) (*((volatile unsigned short *)port)); > > /* Use val in an expression to flush out errors */ > if (val && ia64_io_error) > val = -1; > > /* Double check for an error */ > if (ia64_io_error) > val = -1; > > ErrorF("inw(0x%lx) = 0x%x\n", port, val); > /* val was actually read from the hardware */ > return val; > } > > static __inline__ unsigned int inl(unsigned long port) > { > unsigned int val; > > /* The SIGBUS handler will set this for us if an error occurs */ > ia64_io_error = 0; > > val = (unsigned int) (*((volatile unsigned int *)port)); > > /* Use val in an expression to flush out errors */ > if (val && ia64_io_error) > val = -1; > > /* Double check for an error */ > if (ia64_io_error) > val = -1; > > ErrorF("inl(0x%lx) = 0x%x\n", port, val); > /* val was actually read from the hardware */ > return val; > } > #endif /* __altix__ */ > Index: programs/Xserver/hw/xfree86/common/xf86Bus.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/common/xf86Bus.c,v retrieving revision 1.3 diff -r1.3 xf86Bus.c 1774c1774 < #if !(defined(__alpha__) && defined(linux)) --- > #if !((defined(__alpha__) || (defined(__ia64__))) && defined(linux)) 2394c2394 < --- > /* XXX shm@engr */ 2395a2396 > !(defined(__ia64__) && defined(linux)) && \ Index: programs/Xserver/hw/xfree86/common/xf86Init.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/common/xf86Init.c,v retrieving revision 1.15 diff -r1.15 xf86Init.c 241c241 < #ifdef SIGBUS --- > #if 0 /*def SIGBUS */ Index: programs/Xserver/hw/xfree86/common/xf86pciBus.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c,v retrieving revision 1.6 diff -r1.6 xf86pciBus.c 1684a1685 > #if defined(__snia__) 1688a1690 > #endif Index: programs/Xserver/hw/xfree86/drivers/ati/Imakefile =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile,v retrieving revision 1.12 diff -r1.12 Imakefile 119c119 < #if ATIAvoidNonPCI --- > #if 1 Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v retrieving revision 1.11 diff -r1.11 radeon_accel.c 131a132,135 > xf86DrvMsg(pScrn->scrnIndex, X_INFO, > "FIFO timed out: %d entries, stat=0x%08x\n", > INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, > INREG(RADEON_RBBM_STATUS)); Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v retrieving revision 1.7 diff -r1.7 radeon_dri.c 798c798 < "[agp] %d kB allocated with handle 0x%08lx\n", --- > "[agp] %d kB allocated with handle 0x%016lx\n", 816c816 < "[agp] ring handle = 0x%08lx\n", info->ringHandle); --- > "[agp] ring handle = 0x%016lx\n", info->ringHandle); 824c824 < "[agp] Ring mapped at 0x%08lx\n", --- > "[agp] Ring mapped at 0x%016lx\n", 834c834 < "[agp] ring read ptr handle = 0x%08lx\n", --- > "[agp] ring read ptr handle = 0x%016lx\n", 844c844 < "[agp] Ring read ptr mapped at 0x%08lx\n", --- > "[agp] Ring read ptr mapped at 0x%016lx\n", 854c854 < "[agp] vertex/indirect buffers handle = 0x%08lx\n", --- > "[agp] vertex/indirect buffers handle = 0x%016lx\n", 864c864 < "[agp] Vertex/indirect buffers mapped at 0x%08lx\n", --- > "[agp] Vertex/indirect buffers mapped at 0x%016lx\n", 874c874 < "[agp] GART texture map handle = 0x%08lx\n", --- > "[agp] GART texture map handle = 0x%016lx\n", 884c884 < "[agp] GART Texture map mapped at 0x%08lx\n", --- > "[agp] GART Texture map mapped at 0x%016lx\n", 907c907 < "[pci] %d kB allocated with handle 0x%08lx\n", --- > "[pci] %d kB allocated with handle 0x%016lx\n", 919c919 < "[pci] ring handle = 0x%08lx\n", info->ringHandle); --- > "[pci] ring handle = 0x%016lx\n", info->ringHandle); 927c927 < "[pci] Ring mapped at 0x%08lx\n", --- > "[pci] Ring mapped at 0x%016lx\n", 930c930 < "[pci] Ring contents 0x%08lx\n", --- > "[pci] Ring contents 0x%016lx\n", 940c940 < "[pci] ring read ptr handle = 0x%08lx\n", --- > "[pci] ring read ptr handle = 0x%016lx\n", 950c950 < "[pci] Ring read ptr mapped at 0x%08lx\n", --- > "[pci] Ring read ptr mapped at 0x%016lx\n", 953c953 < "[pci] Ring read ptr contents 0x%08lx\n", --- > "[pci] Ring read ptr contents 0x%016lx\n", 963c963 < "[pci] vertex/indirect buffers handle = 0x%08lx\n", --- > "[pci] vertex/indirect buffers handle = 0x%016lx\n", 973c973 < "[pci] Vertex/indirect buffers mapped at 0x%08lx\n", --- > "[pci] Vertex/indirect buffers mapped at 0x%016lx\n", 976c976 < "[pci] Vertex/indirect buffers contents 0x%08lx\n", --- > "[pci] Vertex/indirect buffers contents 0x%016lx\n", 986c986 < "[pci] GART texture map handle = 0x%08lx\n", --- > "[pci] GART texture map handle = 0x%016lx\n", 996c996 < "[pci] GART Texture map mapped at 0x%08lx\n", --- > "[pci] GART Texture map mapped at 0x%016lx\n", 1009,1010c1009,1014 < if (drmAddMap(info->drmFD, info->MMIOAddr, info->registerSize, < DRM_REGISTERS, DRM_READ_ONLY, &info->registerHandle) < 0) { --- > if (drmAddMap(info->drmFD, > pciBusAddrToHostAddr(info->PciTag, PCI_MEM, info->MMIOAddr), > info->registerSize, > DRM_REGISTERS, > DRM_READ_ONLY, > &info->registerHandle) < 0) { 1014c1018 < "[drm] register handle = 0x%08lx\n", info->registerHandle); --- > "[drm] register handle = 0x%016lx\n", info->registerHandle); 1257c1261,1263 < pDRIInfo->frameBufferPhysicalAddress = info->LinearAddr; --- > pDRIInfo->frameBufferPhysicalAddress = pciBusAddrToHostAddr(info->PciTag, > PCI_MEM, > info->LinearAddr); 1266a1273,1276 > xf86DrvMsg(pScreen->myNum, X_INFO, > "[drm] frameBuffer handle = 0x%016lx\n", > pDRIInfo->frameBufferPhysicalAddress); > Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v retrieving revision 1.27 diff -r1.27 radeon_driver.c 2485a2486,2487 > info->IsPCI = TRUE; > 4623a4626 > #if !defined (__ia64__) 4624a4628 > #endif /* __ia64__ */ 4681,4685d4684 < } else if (info->ChipFamily >= CHIP_FAMILY_R300) { < info->directRenderingEnabled = FALSE; < xf86DrvMsg(scrnIndex, X_WARNING, < "Direct rendering not yet supported on " < "Radeon 9500 and newer cards\n"); Index: programs/Xserver/hw/xfree86/int10/generic.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/int10/generic.c,v retrieving revision 1.2 diff -r1.2 generic.c 126d125 < #if 0 132d130 < #endif 282a281 > 345c344 < LockLegacyVGA(pInt, &vga); --- > LockLegacyVGA(pInt, &vga); 347c346 < UnlockLegacyVGA(pInt, &vga); --- > UnlockLegacyVGA(pInt, &vga); Index: programs/Xserver/hw/xfree86/int10/xf86x86emu.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/int10/xf86x86emu.c,v retrieving revision 1.2 diff -r1.2 xf86x86emu.c 37a38 > ErrorF("Came to exec BIOS\n"); 42a44 > ErrorF("Done exec BIOS\n"); Index: programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h,v retrieving revision 1.2 diff -r1.2 xf86_OSproc.h 258a259,260 > extern Bool xf86GetPciOffsetFromOS(PCITAG tag, int indx, unsigned long* bases); > extern unsigned long xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base); Index: programs/Xserver/hw/xfree86/os-support/bus/Imakefile =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/bus/Imakefile,v retrieving revision 1.5 diff -r1.5 Imakefile 129,130c129,130 < PCIARCHSRC = 460gxPCI.c e8870PCI.c zx1PCI.c < PCIARCHOBJ = 460gxPCI.o e8870PCI.o zx1PCI.o --- > PCIARCHSRC = 460gxPCI.c e8870PCI.c zx1PCI.c altixPCI.c > PCIARCHOBJ = 460gxPCI.o e8870PCI.o zx1PCI.o altixPCI.o Index: programs/Xserver/hw/xfree86/os-support/bus/Pci.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.h,v retrieving revision 1.4 diff -r1.4 Pci.h 200c200 < /* #define DEBUGPCI 2 */ /* Disable/enable trace in PCI code */ --- > /*#define DEBUGPCI 2 */ /* Disable/enable trace in PCI code */ 257c257,258 < # define INCLUDE_XF86_NO_DOMAIN --- > /* # define INCLUDE_XF86_NO_DOMAIN > */ Index: programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c,v retrieving revision 1.4 diff -r1.4 linuxPci.c 61a62 > static ADDRESS linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr); 68c69 < /* pciAddrBusToHost */ pciAddrNOOP --- > /* pciAddrBusToHost */ linuxTransAddrBusToHost 116,117c117 < sprintf(file,"/proc/bus/pci/%02x",bus); < if (stat(file, &ignored) < 0) --- > if (stat("/proc/bus/pci/01", &ignored) < 0) 347a348,366 > /* > * This function will convert a BAR address into a host address > * suitable for passing into the mmap function of a /proc/bus > * device. > */ > ADDRESS > linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr) > { > ADDRESS ret = xf86GetOSOffsetFromPCI(tag, PCI_MEM|PCI_IO, addr); > if (ret) > return ret; > else > /* > * if it is not a BAR address, it must be legacy, (or wrong) > * return it as is .. > */ > return addr; > } > 367a387,392 > #if 0 > if (mmap_ioctl == PCIIOC_MMAP_IS_IO) { > if (ioctl(fd, PCIIOC_MMAP_IS_MEM, 0) < 0) > break; > } > #endif // 0 368a394 > 379c405 < mmapflags = MAP_SHARED | MAP_NONCACHED --- > mmapflags = MAP_SHARED | MAP_NONCACHED; 456a483,524 > ErrorF("Came to read domain memory with Base = 0x%lx, Tag = 0x%lx, size = 0x%lx\n", > Base, Tag, Len); > > #if defined (__ia64__) > unsigned int i, dom, bus, dev, func; > unsigned int fd; > char file[256]; > unsigned char *head = Buf; > > if (Base == 0xC0000) { > dom = PCI_DOM_FROM_TAG(Tag); > bus = PCI_BUS_FROM_TAG(Tag); > dev = PCI_DEV_FROM_TAG(Tag); > func = PCI_FUNC_FROM_TAG(Tag); > > sprintf(file, "/sys/devices/pci%04x:%02x/%04x:%02x:%02x.%1x/rom", > dom, bus, dom, bus, dev, func); > > ErrorF("Opening rom file %s\n", file); > > if ((fd = open(file, O_RDWR))) { > Base = 0x0; > } > > /* enable the ROM first */ > write(fd, 1, 1); > > /* copy the ROM */ > for (i = 0; read(fd, Buf, 1); Buf++,i++) > ; > > ErrorF("Read %d bytes from rom device, signature = 0x%x, 0x%x\n", > i, head[0], head[1]); > write(fd, 0, 1); > close(fd); > > return Len; > > } > #endif /* __ia64__ */ > > 465a534,535 > ErrorF("About to memcpy\n"); > 470a541,542 > ErrorF("Done with memcpy\n"); > Index: programs/Xserver/hw/xfree86/os-support/linux/lnx_ia64.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/linux/lnx_ia64.c,v retrieving revision 1.1 diff -r1.1 lnx_ia64.c 42a43,45 > if (!stat("/proc/sgi_sn/licenseID", &unused)) > return ALTIX_CHIPSET; > Index: programs/Xserver/hw/xfree86/os-support/linux/lnx_pci.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/linux/lnx_pci.c,v retrieving revision 1.2 diff -r1.2 lnx_pci.c 85a86,235 > > > > /* Query the kvirt address (64bit) of a BAR range from TAG */ > Bool > xf86GetPciOffsetFromOS(PCITAG tag, int index, unsigned long* bases) > { > FILE *file; > char c[0x200]; > char *res; > unsigned int bus, devfn, dev, fn; > unsigned PCIADDR_TYPE offset[7]; > unsigned int num; > > if (index > 7) > return FALSE; > > ErrorF("incoming tag 0x%x\n", tag); > if (!(file = fopen("/proc/bus/pci/devices","r"))) > return FALSE; > do { > res = fgets(c,0x1ff,file); > if (res) { > num = sscanf(res, > /*bus+dev vendorid deviceid irq */ > "%02x%02x\t%*04x%*04x\t%*x" > /* 7 PCI resource base addresses */ > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > /* 7 PCI resource sizes, and then optionally a driver name */ > "\t" PCIADDR_IGNORE_FMT > "\t" PCIADDR_IGNORE_FMT > "\t" PCIADDR_IGNORE_FMT > "\t" PCIADDR_IGNORE_FMT > "\t" PCIADDR_IGNORE_FMT > "\t" PCIADDR_IGNORE_FMT > "\t" PCIADDR_IGNORE_FMT, > &bus,&devfn,&offset[0],&offset[1],&offset[2],&offset[3], > &offset[4],&offset[5],&offset[6]); > if (num != 9) { /* apparantly not 2.3 style */ > fclose(file); > return FALSE; > } > > dev = devfn >> 3; > fn = devfn & 0x7; > ErrorF(" for device tag 0x%x, we have 0x%lx, 0x%lx,0x%lx, 0x%lx,0x%lx,0x%lx, 0x%lx \n", > pciTag(bus,dev,fn), > offset[0],offset[1],offset[2],offset[3], > offset[4],offset[5],offset[6]); > if (tag == pciTag(bus,dev,fn)) { > /* return the offset for the index requested */ > *bases = offset[index]; > fclose(file); > return TRUE; > } > } > } while (res); > > fclose(file); > return FALSE; > } > > /* Query the kvirt address (64bit) of a BAR range from size for a given TAG */ > unsigned long > xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base) > { > FILE *file; > char c[0x200]; > char *res; > unsigned int bus, devfn, dev, fn; > unsigned PCIADDR_TYPE offset[7]; > unsigned PCIADDR_TYPE size[7]; > unsigned int num; > unsigned int ndx; > > ErrorF("incoming tag 0x%x\n", tag); > if (!(file = fopen("/proc/bus/pci/devices","r"))) > return NULL; > do { > res = fgets(c,0x1ff,file); > if (res) { > num = sscanf(res, > /*bus+dev vendorid deviceid irq */ > "%02x%02x\t%*04x%*04x\t%*x" > /* 7 PCI resource base addresses */ > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > /* 7 PCI resource sizes, and then optionally a driver name */ > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT > "\t" PCIADDR_FMT, > &bus,&devfn,&offset[0],&offset[1],&offset[2],&offset[3], > &offset[4],&offset[5],&offset[6], &size[0], &size[1], &size[2], > &size[3], &size[4], &size[5], &size[6]); > if (num != 16) { /* apparantly not 2.3 style */ > fclose(file); > return NULL; > } > > dev = devfn >> 3; > fn = devfn & 0x7; > ErrorF(" for device tag 0x%x, we have 0x%lx, 0x%lx,0x%lx, 0x%lx,0x%lx,0x%lx, 0x%lx \n", > pciTag(bus,dev,fn), > offset[0],offset[1],offset[2],offset[3], > offset[4],offset[5],offset[6]); > if (tag == pciTag(bus,dev,fn)) { > /* ok now look through all the BAR values of this device */ > for (ndx=0; ndx<7; ndx++) { > unsigned long savePtr; > /* > * remember to lop of the last 4bits of the BAR values as they are > * memory attributes > */ > if (ndx == 6) > savePtr = (0xFFFFFFF0) & > pciReadLong(tag, PCI_CMD_BIOS_REG); > else /* this the ROM bar */ > savePtr = (0xFFFFFFF0) & > pciReadLong(tag, PCI_CMD_BASE_REG + (0x4 * ndx)); > ErrorF("using Bar Value 0x%lx\n", savePtr); > /* find the index of the incoming base */ > if (base >= savePtr && base <= (savePtr + size[ndx])) { > ErrorF("returning HostAddr 0x%lx\n", offset[ndx]); > fclose(file); > return ( ~(0xFUL) & (offset[ndx] + (base - savePtr))); > } > } > } > } > } while (res); > > fclose(file); > return NULL; > > } Index: programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.c,v retrieving revision 1.1 diff -r1.1 ia64Pci.c 31a32,33 > #include > 34a37 > #include "altixPCI.h" 37a41,63 > > /* Used by the in/out routines to check for master aborts */ > int ia64_io_error; > > void ia64SigBusHandler(int signo, siginfo_t *sinfo, void *unused) > { > ErrorF("Got a SigBUS \n"); > ia64_io_error = 1; > } > > void > ia64SigBusSetup(void) > { > struct sigaction saction; > > ErrorF("Installed a handler for SigBUS \n"); > saction.sa_sigaction = ia64SigBusHandler; > saction.sa_flags = SA_SIGINFO; > sigaction(SIGBUS, &saction, NULL); > } > > > 44c70 < --- > 58,62c84,91 < case ZX1_CHIPSET: < xf86PreScanZX1(); < return; < default: < return; --- > case ZX1_CHIPSET: > xf86PreScanZX1(); > return; > case ALTIX_CHIPSET: > xf86PreScanAltix(); > return; > default: > return; 68,78c97,111 < case I460GX_CHIPSET: < xf86PostScan460GX(); < return; < case E8870_CHIPSET: < xf86PostScanE8870(); < return; < case ZX1_CHIPSET: < xf86PostScanZX1(); < return; < default: < return; --- > case I460GX_CHIPSET: > xf86PostScan460GX(); > return; > case E8870_CHIPSET: > xf86PostScanE8870(); > return; > case ZX1_CHIPSET: > xf86PostScanZX1(); > return; > case ALTIX_CHIPSET: > xf86PostScanAltix(); > ia64SigBusSetup(); > return; > default: > return; Index: programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/os-support/shared/ia64Pci.h,v retrieving revision 1.1 diff -r1.1 ia64Pci.h 35c35,36 < ZX1_CHIPSET --- > ZX1_CHIPSET, > ALTIX_CHIPSET Index: programs/Xserver/hw/xfree86/vgahw/vgaHW.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c,v retrieving revision 1.4 diff -r1.4 vgaHW.c 26a27,28 > #define DEBUG > 250c252,253 < outb(hwp->PIOOffset + VGA_MISC_OUT_W, value); --- > /* outb(hwp->PIOOffset + VGA_MISC_OUT_W, value);*/ > *(CARD8 *)(hwp->PIOOffset + VGA_MISC_OUT_W)=value; 256c259,260 < return inb(hwp->PIOOffset + VGA_MISC_OUT_R); --- > /* return inb(hwp->PIOOffset + VGA_MISC_OUT_R); */ > return *(CARD8 *)(hwp->PIOOffset + VGA_MISC_OUT_R);