commit 2ed949ae84a8798cb6275a8630b61afd4421371f
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Sun Jun 17 14:58:58 2007 +0200

    use true/false from kernel

diff --git a/ath/if_ath.c b/ath/if_ath.c
index a2f282e..0403417 100644
--- a/ath/if_ath.c
+++ b/ath/if_ath.c
@@ -218,8 +218,8 @@ static	int ath_dwelltime = 200;		/* 5 channels/second */
 static	int ath_calinterval = 30;		/* calibrate every 30 secs */
 static	int ath_countrycode = CTRY_DEFAULT;	/* country code */
 static	int ath_regdomain = 0;			/* regulatory domain */
-static	int ath_outdoor = TRUE;		/* enable outdoor use */
-static	int ath_xchanmode = TRUE;		/* enable extended channels */
+static	int ath_outdoor = true;		/* enable outdoor use */
+static	int ath_xchanmode = true;		/* enable extended channels */
 
 #ifdef AR_DEBUG
 static	int ath_debug = 0;
@@ -899,7 +899,7 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs)
 			if (status & AR5K_INT_TXURN) {
 				sc->sc_stats.ast_txurn++;
 				/* bump tx trigger level */
-				ath_hal_updatetxtriglevel(ah, TRUE);
+				ath_hal_updatetxtriglevel(ah, true);
 			}
 			if (status & AR5K_INT_RX)
 				ATH_SCHEDULE_TQUEUE(&sc->sc_rxtq, &needmark);
@@ -1073,7 +1073,7 @@ ath_init(struct net_device *dev)
 	sc->sc_curchan.freq = ic->ic_ibss_chan->ic_freq;
 	sc->sc_curchan.channel_flags = ath_chan2flags(ic, ic->ic_ibss_chan);
 #endif
-	if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, FALSE, &status)) {
+	if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, false, &status)) {
 		printk(KERN_ERR "unable to reset hardware; hal status %u\n",
 			status);
 		error = -EIO;
@@ -1271,7 +1271,7 @@ ath_reset(struct net_device *dev)
 	
 	opmode = (ic->ic_opmode == IEEE80211_M_AHDEMO) ? 0 : ic->ic_opmode;
 	/* NB: indicate channel change so we do a full reset */
-	if (!ath_hal_reset(ah, opmode, &sc->sc_curchan, TRUE, &status))
+	if (!ath_hal_reset(ah, opmode, &sc->sc_curchan, true, &status))
 		if_printf(dev, "%s: unable to reset hardware: '%s' (%u)\n",
 			__func__, hal_status_desc[status], status);
 	ath_update_txpow(sc);		/* update tx power state */
@@ -1376,7 +1376,7 @@ static int
 ath_start_raw(struct sk_buff *skb, struct net_device *dev)
 {
 #define	CTS_DURATION \
-	ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, TRUE)
+	ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, true)
 /*#define	updateCTSForBursting(_ah, _ds, _txq) \
 	ath_hal_updateCTSForBursting(_ah, _ds, \
 	    _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \
@@ -1577,8 +1577,8 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev)
 	ds->ds_data = bf->bf_skbaddr;
 	ath_hal_filltxdesc(ah, ds
 		, skb->len		/* segment length */
-		, TRUE		/* first segment */
-		, TRUE		/* last segment */
+		, true		/* first segment */
+		, true		/* last segment */
 		, ds			/* first descriptor */
 	);
 
@@ -2601,8 +2601,8 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf,
 	/* NB: beacon's BufLen must be a multiple of 4 bytes */
 	ath_hal_filltxdesc(ah, ds
 		, roundup(skb->len, 4)		/* buffer length */
-		, TRUE			/* first segment */
-		, TRUE			/* last segment */
+		, true			/* first segment */
+		, true			/* last segment */
 		, ds				/* first descriptor */
 	);
 #undef USE_SHPREAMBLE
@@ -4163,7 +4163,7 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf *
     struct sk_buff *skb)
 {
 #define	CTS_DURATION \
-	ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, TRUE)
+	ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, true)
 /*#define	updateCTSForBursting(_ah, _ds, _txq) \
 	ath_hal_updateCTSForBursting(_ah, _ds, \
 	    _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \
@@ -4288,10 +4288,10 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf *
 	 */
 	if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
 	    (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
-		short_preamble = TRUE;
+		short_preamble = true;
 		sc->sc_stats.ast_tx_shortpre++;
 	} else {
-		short_preamble = FALSE;
+		short_preamble = false;
 	}
 
 	an = ATH_NODE(ni);
@@ -4486,14 +4486,14 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf *
 			if (flags & AR5K_TXDESC_RTSENA)		/* SIFS + CTS */
 				ctsduration += rt->rates[cix].sp_ack_duration;
 			ctsduration += ath_hal_computetxtime(ah,
-				rt, pktlen, rix, TRUE);
+				rt, pktlen, rix, true);
 			if ((flags & AR5K_TXDESC_NOACK) == 0)	/* SIFS + ACK */
 				ctsduration += rt->rates[cix].sp_ack_duration;
 		} else {
 			if (flags & AR5K_TXDESC_RTSENA)		/* SIFS + CTS */
 				ctsduration += rt->rates[cix].lp_ack_duration;
 			ctsduration += ath_hal_computetxtime(ah,
-				rt, pktlen, rix, FALSE);
+				rt, pktlen, rix, false);
 			if ((flags & AR5K_TXDESC_NOACK) == 0)	/* SIFS + ACK */
 				ctsduration += rt->rates[cix].lp_ack_duration;
 		}
@@ -4564,8 +4564,8 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf *
 	ds->ds_data = bf->bf_skbaddr;
 	ath_hal_filltxdesc(ah, ds
 		, skb->len		/* segment length */
-		, TRUE		/* first segment */
-		, TRUE		/* last segment */
+		, true		/* first segment */
+		, true		/* last segment */
 		, ds			/* first descriptor */
 	);
 	DPRINTF(sc, ATH_DEBUG_XMIT, "%s: Q%d: %08x %08x %08x %08x %08x %08x\n",
@@ -5124,7 +5124,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
 		ath_hal_intrset(ah, 0);		/* disable interrupts */
 		ath_draintxq(sc);		/* clear pending tx frames */
 		ath_stoprecv(sc);		/* turn off frame recv */
-		if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, TRUE, &status)) {
+		if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, true, &status)) {
 			printk(KERN_ERR "ath_chan_set: unable to reset "
 				"channel %u (%u Mhz)\n", 0,
 //				ieee80211_chan2ieee(ic, chan),
diff --git a/ath/if_athvar.h b/ath/if_athvar.h
index 8d61385..7689ff5 100644
--- a/ath/if_athvar.h
+++ b/ath/if_athvar.h
@@ -434,7 +434,7 @@ void	ath_sysctl_unregister(void);
 #define	ath_hal_updatetxtriglevel(_ah, _inc) \
 	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
 #define	ath_hal_setpower(_ah, _mode, _sleepduration) \
-	((*(_ah)->ah_setPowerMode)((_ah), (_mode), TRUE, (_sleepduration)))
+	((*(_ah)->ah_setPowerMode)((_ah), (_mode), true, (_sleepduration)))
 #define	ath_hal_keycachesize(_ah) \
 	((*(_ah)->ah_getKeyCacheSize)((_ah)))
 #define	ath_hal_keyreset(_ah, _ix) \
diff --git a/openhal/ath5k.h b/openhal/ath5k.h
index 8bf0bb3..a3f8980 100644
--- a/openhal/ath5k.h
+++ b/openhal/ath5k.h
@@ -58,18 +58,6 @@
 #define howmany(x, y)   (((x)+((y)-1))/(y))
 
 /*
- * C doesn't support boolean ;-(
- * TODO: See if there is a bool definition somewere else
- * in the kernel, we shouldn't redefine it if it does...
- */
-#ifndef TRUE
-#define	TRUE	1
-#endif
-#ifndef FALSE
-#define	FALSE	0
-#endif
-
-/*
  * Error codes reported from HAL to the driver
  */
 enum ath5k_status {
@@ -91,7 +79,7 @@ enum ath5k_status {
 #define AR5K_TUNE_DMA_BEACON_RESP		2
 #define AR5K_TUNE_SW_BEACON_RESP		10
 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF	0
-#define AR5K_TUNE_RADAR_ALERT			FALSE
+#define AR5K_TUNE_RADAR_ALERT			false
 #define AR5K_TUNE_MIN_TX_FIFO_THRES		1
 #define AR5K_TUNE_MAX_TX_FIFO_THRES		((MAX_PDU_LENGTH / 64) + 1)
 #define AR5K_TUNE_RSSI_THRES			1792
@@ -110,8 +98,8 @@ enum ath5k_status {
 #define AR5K_TUNE_NOISE_FLOOR			-72
 #define AR5K_TUNE_MAX_TXPOWER			60
 #define AR5K_TUNE_DEFAULT_TXPOWER		30
-#define AR5K_TUNE_TPC_TXPOWER			TRUE
-#define AR5K_TUNE_ANT_DIVERSITY			TRUE
+#define AR5K_TUNE_TPC_TXPOWER			true
+#define AR5K_TUNE_ANT_DIVERSITY			true
 #define AR5K_TUNE_HWTXTRIES			4
 
 /* token to use for aifs, cwmin, cwmax in MadWiFi */
@@ -765,7 +753,7 @@ struct ath5k_keyval {
 
 #define AR5K_ASSERT_ENTRY(_e, _s) do {		\
 	if (_e >= _s)				\
-		return (FALSE);			\
+		return (false);			\
 } while (0)
 
 
diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c
index b20bc3d..56962b2 100644
--- a/openhal/ath5k_hw.c
+++ b/openhal/ath5k_hw.c
@@ -268,13 +268,13 @@ ath5k_hw_bitswap(u_int32_t val, u_int bits)
 inline u_int
 ath5k_hw_htoclock(u_int usec, bool turbo)
 {
-	return (turbo == TRUE ? (usec * 80) : (usec * 40));
+	return (turbo == true ? (usec * 80) : (usec * 40));
 }
 
 inline u_int
 ath5k_hw_clocktoh(u_int clock, bool turbo)
 {
-	return (turbo == TRUE ? (clock / 80) : (clock / 40));
+	return (turbo == true ? (clock / 80) : (clock / 40));
 }
 
 /*
@@ -336,7 +336,7 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
 
 	for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
 		data = AR5K_REG_READ(reg);
-		if ((is_set == TRUE) && (data & flag))
+		if ((is_set == true) && (data & flag))
 			break;
 		else if ((data & flag) == val)
 			break;
@@ -344,9 +344,9 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
 	}
 
 	if (i <= 0)
-		return (FALSE);
+		return (false);
 
-	return (TRUE);
+	return (true);
 }
 
 
@@ -410,14 +410,14 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status)
 
 	hal->ah_op_mode = IEEE80211_IF_TYPE_STA;
 	hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
-	hal->ah_turbo = FALSE;
+	hal->ah_turbo = false;
 	hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
 	hal->ah_imr = 0;
 	hal->ah_atim_window = 0;
 	hal->ah_aifs = AR5K_TUNE_AIFS;
 	hal->ah_cw_min = AR5K_TUNE_CWMIN;
 	hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
-	hal->ah_software_retry = FALSE;
+	hal->ah_software_retry = false;
 	hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
 
 	switch (device) {
@@ -427,13 +427,13 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status)
 			/*
 			 * Known single chip solutions
 			 */
-			hal->ah_single_chip = TRUE;
+			hal->ah_single_chip = true;
 			break;
 		default:
 			/*
 			 * Multi chip solutions
 			 */
-			hal->ah_single_chip = FALSE;
+			hal->ah_single_chip = false;
 			break;
 	}
 
@@ -446,7 +446,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status)
 	ath5k_hw_fill(hal);
 
 	/* Bring device out of sleep and reset it's units */
-	if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, TRUE) != TRUE)
+	if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true) != true)
 		goto failed;
 
 	/* Get MAC, PHY and RADIO revisions */
@@ -503,7 +503,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status)
 	}
 
 	/* Get misc capabilities */
-	if (hal->ah_get_capabilities(hal) != TRUE) {
+	if (hal->ah_get_capabilities(hal) != true) {
 		*status = AR5K_EEREAD;
 		AR5K_PRINTF("unable to get device capabilities: 0x%04x\n",
 		    device);
@@ -595,7 +595,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial)
 			clock |= AR5K_PHY_PLL_40MHZ;
 		} else {
 			AR5K_PRINT("invalid radio frequency mode\n");
-			return (FALSE);
+			return (false);
 		}
 
 		if (flags & CHANNEL_CCK) {
@@ -611,7 +611,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial)
 			mode |= AR5K_PHY_MODE_MOD_OFDM;
 		} else {
 			AR5K_PRINT("invalid radio frequency mode\n");
-			return (FALSE);
+			return (false);
 		}
 
 		if (flags & CHANNEL_TURBO) {
@@ -625,12 +625,12 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial)
 	 */
 
 	else {
-		if (initial == TRUE) {
+		if (initial == true) {
 			/* ...reset hardware */
 			if (ath5k_hw_nic_reset(hal,
-				AR5K_RESET_CTL_PCI) == FALSE) {
+				AR5K_RESET_CTL_PCI) == false) {
 				AR5K_PRINT("failed to reset the PCI chipset\n");
-				return (FALSE);
+				return (false);
 			}
 
 			udelay(1000);
@@ -638,9 +638,9 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial)
 
 		/* ...wakeup */
 		if (ath5k_hw_set_power(hal,
-			AR5K_PM_AWAKE, TRUE, 0) == FALSE) {
+			AR5K_PM_AWAKE, true, 0) == false) {
 			AR5K_PRINT("failed to resume the MAC Chip\n");
-			return (FALSE);
+			return (false);
 		}
 
 		/* ...enable Atheros turbo mode if requested */
@@ -648,19 +648,19 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial)
 			AR5K_REG_WRITE(AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE);
 
 		/* ...reset chipset */
-		if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == FALSE) {
+		if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == false) {
 			AR5K_PRINT("failed to reset the AR5210 chipset\n");
-			return (FALSE);
+			return (false);
 		}
 
 		udelay(1000);
 	}
 
 	/* ...reset chipset and PCI device */
-	if (hal->ah_single_chip == FALSE &&
-	ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == FALSE) {
+	if (hal->ah_single_chip == false &&
+	ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == false) {
 		AR5K_PRINT("failed to reset the MAC Chip + PCI\n");
-		return (FALSE);
+		return (false);
 	}
 
 	if (hal->ah_version == AR5K_AR5210)
@@ -668,15 +668,15 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial)
 
 	/* ...wakeup */
 	if (ath5k_hw_set_power(hal,
-		AR5K_PM_AWAKE, TRUE, 0) == FALSE) {
+		AR5K_PM_AWAKE, true, 0) == false) {
 		AR5K_PRINT("failed to resume the MAC Chip\n");
-		return (FALSE);
+		return (false);
 	}
 
 	/* ...final warm reset */
-	if (ath5k_hw_nic_reset(hal, 0) == FALSE) {
+	if (ath5k_hw_nic_reset(hal, 0) == false) {
 		AR5K_PRINT("failed to warm reset the MAC Chip\n");
-		return (FALSE);
+		return (false);
 	}
 
 	if (hal->ah_version != AR5K_AR5210){
@@ -688,7 +688,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial)
 		AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo);
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -821,7 +821,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	 */
 	/*DCU/Antenna selection not available on 5210*/
 	if (hal->ah_version != AR5K_AR5210) {
-		if (change_channel == TRUE) {
+		if (change_channel == true) {
 			/*Sequence number for queue 0 -do this for all queues ?*/
 			s_seq = AR5K_REG_READ(AR5K_QUEUE_DFS_SEQNUM(0));
 			/*Default antenna*/
@@ -834,14 +834,14 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	s_led[1] = AR5K_REG_READ(AR5K_GPIOCR);
 	s_led[2] = AR5K_REG_READ(AR5K_GPIODO);
 
-	if (change_channel == TRUE && hal->ah_rf_banks != NULL)
+	if (change_channel == true && hal->ah_rf_banks != NULL)
 		ath5k_hw_get_rf_gain(hal);
 
 
 	/*Wakeup the device*/
-	if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, FALSE) == FALSE) {
+	if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) {
 		*status = AR5K_EIO;
-		return (FALSE);
+		return (false);
 	}
 
 	/*
@@ -861,7 +861,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 		else {
 			AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio);
 			*status = AR5K_EINVAL;
-			return (FALSE);
+			return (false);
 		}
 
 		switch (channel->channel_flags & CHANNEL_MODES) {
@@ -894,7 +894,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 		case CHANNEL_XR:
 			if (hal->ah_version == AR5K_AR5211) {
 				AR5K_PRINTF("XR mode not available on 5211");
-				return (FALSE);
+				return (false);
 			}
 			mode = AR5K_INI_VAL_XR;
 			freq = AR5K_INI_RFGAIN_5GHZ;
@@ -903,7 +903,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 		default:
 			AR5K_PRINTF("invalid channel: %d\n", channel->freq);
 			*status = AR5K_EINVAL;
-			return (FALSE);
+			return (false);
 		}
 
 		/* PHY access enable */
@@ -956,7 +956,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	/*For 5212*/
 	if (hal->ah_version == AR5K_AR5212) {
 		for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) {
-			if (change_channel == TRUE &&
+			if (change_channel == true &&
 			    ar5212_ini[i].ini_register >= AR5K_PCU_MIN &&
 			    ar5212_ini[i].ini_register <= AR5K_PCU_MAX)
 				continue;
@@ -974,7 +974,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	/*For 5211*/
 	if (hal->ah_version == AR5K_AR5211) {
 		for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) {
-			if (change_channel == TRUE &&
+			if (change_channel == true &&
 			    ar5211_ini[i].ini_register >= AR5K_PCU_MIN &&
 			    ar5211_ini[i].ini_register <= AR5K_PCU_MAX)
 				continue;
@@ -987,7 +987,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	/*For 5210*/
 	if (hal->ah_version == AR5K_AR5210)
 		for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) {
-			if (change_channel == TRUE &&
+			if (change_channel == true &&
 			    ar5210_ini[i].ini_register >= AR5K_PCU_MIN &&
 			    ar5210_ini[i].ini_register <= AR5K_PCU_MAX)
 				continue;
@@ -1013,9 +1013,9 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 		 * Write initial RF gain settings
 		 * This should work for both 5111/5112
 		 */
-		if (ath5k_hw_rfgain(hal, phy, freq) == FALSE) {
+		if (ath5k_hw_rfgain(hal, phy, freq) == false) {
 			*status = AR5K_EIO;
-			return (FALSE);
+			return (false);
 		}
 
 		udelay(1000);
@@ -1036,12 +1036,12 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 					data = AR5K_RATE_DUR(rt->rates[i].rate_code);
 					AR5K_REG_WRITE(data,
 					    ath_hal_computetxtime(hal, rt, 14,
-					    rt->rates[i].control_rate, FALSE));
+					    rt->rates[i].control_rate, false));
 					if (HAS_SHPREAMBLE(i)) {
 						AR5K_REG_WRITE(data +
 						    (AR5K_SET_SHORT_PREAMBLE << 2),
 						    ath_hal_computetxtime(hal, rt, 14,
-						    rt->rates[i].control_rate, FALSE));
+						    rt->rates[i].control_rate, false));
 					}
 				}
 	
@@ -1057,7 +1057,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 				for (i = 0; i < rt->rate_count; i++) {
 					AR5K_REG_WRITE(AR5K_RATE_DUR(rt->rates[i].rate_code),
 					    ath_hal_computetxtime(hal, rt, 14,
-					    rt->rates[i].control_rate, FALSE));
+					    rt->rates[i].control_rate, false));
 				}
 
 			}
@@ -1079,18 +1079,18 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 		 * Set TX power (XXX use txpower from net80211)
 		 */
 		if (ath5k_hw_txpower(hal, channel,
-			AR5K_TUNE_DEFAULT_TXPOWER) == FALSE) {
+			AR5K_TUNE_DEFAULT_TXPOWER) == false) {
 			*status = AR5K_EIO;
-			return (FALSE);
+			return (false);
 		}
 
 		/*
 		 * Write RF registers
 		 * TODO:Does this work on 5211 (5111) ?
 		 */
-		if (ath5k_hw_rfregs(hal, channel, mode) == FALSE) {
+		if (ath5k_hw_rfregs(hal, channel, mode) == false) {
 			*status = AR5K_EINPROGRESS;
-			return (FALSE);
+			return (false);
 		}
 
 		/*
@@ -1112,7 +1112,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 
 				if (!coef_exp) {
 					*status = AR5K_EINVAL;
-					return (FALSE);
+					return (false);
 				}
 
 				coef_exp = 14 - (coef_exp - 24);
@@ -1243,9 +1243,9 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	/*
 	 * Set channel and calibrate the PHY
 	 */
-	if (ath5k_hw_channel(hal, channel) == FALSE) {
+	if (ath5k_hw_channel(hal, channel) == false) {
 		*status = AR5K_EIO;
-		return (FALSE);
+		return (false);
 	}
 
 	/*
@@ -1273,10 +1273,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 				AR5K_PHY_AGCCTL_CAL);
 
 	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-		AR5K_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) {
+		AR5K_PHY_AGCCTL_CAL, 0, false) == false) {
 		AR5K_PRINTF("calibration timeout (%uMHz)\n",
 		    channel->freq);
-		return (FALSE);
+		return (false);
 	}
 
 	/*
@@ -1286,10 +1286,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 				AR5K_PHY_AGCCTL_NF);
 
 	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-		AR5K_PHY_AGCCTL_NF, 0, FALSE) == FALSE) {
+		AR5K_PHY_AGCCTL_NF, 0, false) == false) {
 		AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
 				channel->freq);
-		return (FALSE);
+		return (false);
 	}
 
 	/* Wait until the noise floor is calibrated and read the value */
@@ -1308,13 +1308,13 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
 		AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
 			channel->freq);
-		return (FALSE);
+		return (false);
 	}
 	
-	hal->ah_calibration = FALSE;
+	hal->ah_calibration = false;
 
 	if (!(channel->channel_flags & CHANNEL_B)) {
-		hal->ah_calibration = TRUE;
+		hal->ah_calibration = true;
 		AR5K_REG_WRITE_BITS(AR5K_PHY_IQ,
 		    AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
 		AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ,
@@ -1329,10 +1329,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 		if (hal->ah_version != AR5K_AR5210)
 			AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i);
 
-		if (ath5k_hw_reset_tx_queue(hal, i) == FALSE) {
+		if (ath5k_hw_reset_tx_queue(hal, i) == false) {
 			AR5K_PRINTF("failed to reset TX queue #%d\n", i);
 			*status = AR5K_EINVAL;
-			return (FALSE);
+			return (false);
 		}
 	}
 
@@ -1375,7 +1375,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 	AR5K_REG_DISABLE_BITS(AR5K_BEACON,
 	    AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -1384,7 +1384,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode,
 bool
 ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val)
 {
-	bool ret = FALSE;
+	bool ret = false;
 	u_int32_t mask = val ? val : ~0;
 
 	AR5K_TRACE;
@@ -1411,7 +1411,7 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val)
 		    AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 	}
 
-	ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, FALSE);
+	ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false);
 
 	/*
 	 * Reset configuration register (for hw byte-swap)
@@ -1444,7 +1444,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode,
 		staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
 		/* fallthrough */
 	case AR5K_PM_NETWORK_SLEEP:
-		if (set_chip == TRUE) {
+		if (set_chip == true) {
 			AR5K_REG_WRITE(AR5K_SLEEP_CTL,
 			    AR5K_SLEEP_CTL_SLE | sleep_duration);
 		}
@@ -1452,7 +1452,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode,
 		break;
 
 	case AR5K_PM_FULL_SLEEP:
-		if (set_chip == TRUE) {
+		if (set_chip == true) {
 			AR5K_REG_WRITE(AR5K_SLEEP_CTL,
 			    AR5K_SLEEP_CTL_SLE_SLP);
 		}
@@ -1460,7 +1460,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode,
 		break;
 
 	case AR5K_PM_AWAKE:
-		if (set_chip == FALSE)
+		if (set_chip == false)
 			goto commit;
 
 		AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE_WAKE);
@@ -1479,13 +1479,13 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode,
 
 		/* Fail if the chip didn't wake up */
 		if (i <= 0)
-			return (FALSE);
+			return (false);
 
 		staid &= ~AR5K_STA_ID1_PWR_SV;
 		break;
 
 	default:
-		return (FALSE);
+		return (false);
 	}
 
  commit:
@@ -1493,7 +1493,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode,
 
 	AR5K_REG_WRITE(AR5K_STA_ID1, staid);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -1547,7 +1547,7 @@ ath5k_hw_stop_rx_dma(struct ath_hal *hal)
 	     i--)
 		udelay(10);
 
-	return (i > 0 ? TRUE : FALSE);
+	return (i > 0 ? true : false);
 }
 
 /*
@@ -1589,7 +1589,7 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue)
 
 	/* Return if queue is declared inactive */
 	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-		return (FALSE);
+		return (false);
 
 	if (hal->ah_version == AR5K_AR5210) {
 
@@ -1616,20 +1616,20 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue)
 						AR5K_BCR_BDMAE);
 				break;
 			default:
-				return (FALSE);
+				return (false);
 		}
 		/* Start queue */
 		AR5K_REG_WRITE(AR5K_CR, tx_queue);
 	} else {
 		/* Return if queue is disabled */
 		if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue))
-			return (FALSE);
+			return (false);
 
 		/* Start queue */
 		AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue);
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -1647,7 +1647,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue)
 
 	/* Return if queue is declared inactive */
 	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-		return (FALSE);
+		return (false);
 
 	if (hal->ah_version == AR5K_AR5210) {
 		tx_queue = AR5K_REG_READ(AR5K_CR);
@@ -1666,7 +1666,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue)
 				AR5K_REG_WRITE(AR5K_BSR, 0);
 				break;
 			default:
-				return (FALSE);
+				return (false);
 		}
 
 		/* Stop queue */
@@ -1689,7 +1689,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue)
 	}
 
 	/*TODO: Check for success else return false*/
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -1751,7 +1751,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
 				tx_reg = AR5K_NOQCU_TXDP1;
 				break;
 			default:
-				return (FALSE);
+				return (false);
 		}
 	} else {
 		/*
@@ -1760,7 +1760,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
 		 * (this won't work if the queue is still active)
 		 */
 		if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue))
-			return (FALSE);
+			return (false);
 
 		tx_reg = AR5K_QUEUE_TXDP(queue);
 	}
@@ -1768,7 +1768,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
 	/* Set descriptor pointer */
 	AR5K_REG_WRITE(tx_reg, phys_addr);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -1778,7 +1778,7 @@ bool
 ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase)
 {
 	u_int32_t trigger_level, imr;
-	bool status = FALSE;
+	bool status = false;
 	AR5K_TRACE;
 
 	/*
@@ -1790,7 +1790,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase)
 	trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_TXCFG),
 			AR5K_TXCFG_TXFULL);
 
-	if (increase == FALSE) {
+	if (increase == false) {
 		if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
 			goto done;
 	} else
@@ -1806,7 +1806,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase)
 		AR5K_REG_WRITE_BITS(AR5K_TXCFG,
 				AR5K_TXCFG_TXFULL, trigger_level);
 
-	status = TRUE;
+	status = true;
 
  done:
 	/*
@@ -1828,7 +1828,7 @@ bool
 ath5k_hw_is_intr_pending(struct ath_hal *hal)
 {
 	AR5K_TRACE;
-	return (AR5K_REG_READ(AR5K_INTPEND) == TRUE ? TRUE : FALSE);
+	return (AR5K_REG_READ(AR5K_INTPEND) == true ? true : false);
 }
 
 /*
@@ -1848,7 +1848,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
 	if (hal->ah_version == AR5K_AR5210) {
 		if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) {
 			*interrupt_mask = data;
-			return (FALSE);
+			return (false);
 		}
 	}
 
@@ -1863,7 +1863,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
 	*interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr;
 
 	if (data == AR5K_INT_NOCARD)
-		return (FALSE);
+		return (false);
 
 	if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
 		*interrupt_mask |= AR5K_INT_RX;
@@ -1885,7 +1885,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
 	 * Special interrupt handling (not caught by the driver)
 	 */
 	if (((*interrupt_mask) & AR5K_ISR_RXPHY) &&
-	    hal->ah_radar.r_enabled == TRUE)
+	    hal->ah_radar.r_enabled == true)
 		ath5k_radar_alert(hal);
 
 	/* 
@@ -1903,7 +1903,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
 	if (*interrupt_mask == 0)
 		AR5K_PRINTF("0x%08x\n", data);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -1994,7 +1994,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, bool enable)
 	 * possible radar activity.
 	 */
 	if (hal->ah_version == AR5K_AR5210) {
-		if (enable == TRUE) {
+		if (enable == true) {
 			AR5K_REG_ENABLE_BITS(AR5K_IMR,
 					AR5K_IMR_RXPHY);
 		} else {
@@ -2003,7 +2003,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, bool enable)
 		}
 	} else {
 		/*Also set AR5K_PHY_RADAR register on 5111/5112*/
-		if (enable == TRUE) {
+		if (enable == true) {
 			AR5K_REG_WRITE(AR5K_PHY_RADAR,
 				AR5K_PHY_RADAR_ENABLE);
 			AR5K_REG_ENABLE_BITS(AR5K_PIMR,
@@ -2035,7 +2035,7 @@ ath5k_hw_eeprom_is_busy(struct ath_hal *hal)
 {
 	AR5K_TRACE;
 	return (AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ?
-		TRUE : FALSE);
+		true : false);
 }
 
 /*
@@ -2535,10 +2535,10 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write,
 	u_int16_t ee_regdomain;
 
 	/* Read current value */
-	if (write != TRUE) {
+	if (write != true) {
 		ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain;
 		*regdomain = ath5k_regdomain_to_ieee(ee_regdomain);
-		return (TRUE);
+		return (true);
 	}
 
 	ee_regdomain = ath5k_regdomain_from_ieee(*regdomain);
@@ -2546,14 +2546,14 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write,
 	/* Try to write a new value */
 	if (hal->ah_capabilities.cap_eeprom.ee_protect &
 	    AR5K_EEPROM_PROTECT_WR_128_191)
-		return (FALSE);
+		return (false);
 	if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN,
 	    ee_regdomain) != 0)
-		return (FALSE);
+		return (false);
 
 	hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -2567,15 +2567,15 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
 
 	ieee_regdomain = ath5k_regdomain_to_ieee(regdomain);
 
-	if (ath5k_eeprom_regulation_domain(hal, TRUE,
-		&ieee_regdomain) == TRUE) {
+	if (ath5k_eeprom_regulation_domain(hal, true,
+		&ieee_regdomain) == true) {
 		*status = AR5K_OK;
-		return (TRUE);
+		return (true);
 	}
 
 	*status = AR5K_EIO;
 
-	return (FALSE);
+	return (false);
 }
 
 /*
@@ -2648,7 +2648,7 @@ ath5k_hw_get_capabilities(struct ath_hal *hal)
 	else
 		hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
 
-	return (TRUE);
+	return (true);
 }
 
 
@@ -2757,7 +2757,7 @@ ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
 	AR5K_REG_WRITE(AR5K_STA_ID0, low_id);
 	AR5K_REG_WRITE(AR5K_STA_ID1, high_id);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -2816,9 +2816,9 @@ ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)
 		AR5K_REG_WRITE(AR5K_BSS_IDM0, low_id); 
 		AR5K_REG_WRITE(AR5K_BSS_IDM1, high_id); 
 
-		return (TRUE); 
+		return (true); 
 	} else
-		return (FALSE);
+		return (false);
 }
 
 /*
@@ -2871,7 +2871,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
 
 	AR5K_TRACE;
 	if (index >= 64)
-	    return (FALSE);
+	    return (false);
 	else if (index >= 32)
 	    AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1,
 		(1 << (index - 32)));
@@ -2879,7 +2879,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
 	    AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0,
 		(1 << index));
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -2891,7 +2891,7 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
 
 	AR5K_TRACE;
 	if (index >= 64)
-	    return (FALSE);
+	    return (false);
 	else if (index >= 32)
 	    AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1,
 		(1 << (index - 32)));
@@ -2899,7 +2899,7 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
 	    AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0,
 		(1 << index));
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -3234,18 +3234,18 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr)
 			AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, phys_addr);
 			AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE);
 
-			return (FALSE);
+			return (false);
 		}
-		ret= TRUE;
+		ret= true;
 
 	} else {
 	/*5211/5212*/
 		ret = ath5k_hw_register_timeout(hal,
 			AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
-			AR5K_QCU_STS_FRMPENDCNT, 0, FALSE);
+			AR5K_QCU_STS_FRMPENDCNT, 0, false);
 
 		if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
-			return (FALSE);
+			return (false);
 	}
 
 	return (ret);
@@ -3294,12 +3294,12 @@ ath5k_hw_set_ack_timeout(struct ath_hal *hal, u_int timeout)
 	AR5K_TRACE;
 	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
 	    hal->ah_turbo) <= timeout)
-		return (FALSE);
+		return (false);
 
 	AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
 	    ath5k_hw_htoclock(timeout, hal->ah_turbo));
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -3322,12 +3322,12 @@ ath5k_hw_set_cts_timeout(struct ath_hal *hal, u_int timeout)
 	AR5K_TRACE;
 	if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
 	    hal->ah_turbo) <= timeout)
-		return (FALSE);
+		return (false);
 
 	AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
 	    ath5k_hw_htoclock(timeout, hal->ah_turbo));
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -3356,9 +3356,9 @@ ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher)
 	 * Only WEP for now
 	 */
 	if (cipher == AR5K_CIPHER_WEP)
-		return (TRUE);
+		return (true);
 
-	return (FALSE);
+	return (false);
 }
 
 /*
@@ -3390,7 +3390,7 @@ ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry)
 		AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry),
 				AR5K_KEYTABLE_TYPE_NULL);
 
-	return (FALSE); /*????*/
+	return (false); /*????*/
 }
 
 /*
@@ -3407,9 +3407,9 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry)
 	 */
 	if (AR5K_REG_READ(AR5K_KEYTABLE_MAC1(entry)) &
 	    AR5K_KEYTABLE_VALID)
-		return (TRUE);
+		return (true);
 
-	return (FALSE);
+	return (false);
 }
 
 /*
@@ -3454,7 +3454,7 @@ ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry,
 
 	default:
 		/* Unsupported key length (not WEP40/104/128) */
-		return (FALSE);
+		return (false);
 	}
 
 	for (i = 0; i < AR5K_ELEMENTS(key_v); i++)
@@ -3487,7 +3487,7 @@ ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
 	AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id);
 	AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id);
 
-	return (TRUE);
+	return (true);
 }
 
 
@@ -3562,7 +3562,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type,
 	if (queue_info != NULL) {
 		queue_info->tqi_type = queue_type;
 		if (ath5k_hw_setup_tx_queueprops(hal, queue, queue_info)
-		    != TRUE)
+		    != true)
 			return (-1);
 	}
 	/*
@@ -3586,7 +3586,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue,
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
 
 	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) 
-		return (FALSE);
+		return (false);
 
 	memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
 
@@ -3598,7 +3598,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue,
 		hal->ah_txq[queue].tqi_flags |=
 			AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -3609,7 +3609,7 @@ ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info
 {
 	AR5K_TRACE;
 	memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info));
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -3626,7 +3626,7 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue)
 	/*For SIMR setup*/
 	AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue);
 
-	return (FALSE); /*???*/
+	return (false); /*???*/
 }
 
 /*
@@ -3647,19 +3647,19 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue)
 	tq = &hal->ah_txq[queue];
 
 	if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
-		return (TRUE);
+		return (true);
 
 	if (hal->ah_version == AR5K_AR5210) {
 		/* Only handle data queues, others will be ignored */
 		if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
-			return (TRUE);
+			return (true);
 
 		/*
 		 * Write initial mode register settings
 		 */
 		for (i = 0; i < AR5K_ELEMENTS(ar5210_mode); i++)
 			AR5K_REG_WRITE((u_int32_t)ar5210_mode[i].mode_register,
-				hal->ah_turbo == TRUE ?
+				hal->ah_turbo == true ?
 				ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base);
 	}
 
@@ -3697,7 +3697,7 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue)
 	/*
 	 * Calculate and set retry limits
 	 */
-	if (hal->ah_software_retry == TRUE) {
+	if (hal->ah_software_retry == true) {
 		/* XXX Need to test this */
 		retry_lg = hal->ah_limit_tx_retries;
 		retry_sh = retry_lg =
@@ -3845,7 +3845,7 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue)
 			AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN));
 	}	
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -3859,11 +3859,11 @@ ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) {
 
 	/* Return if queue is declared inactive */
 	if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-		return (FALSE);
+		return (false);
 
 	/* XXX: How about AR5K_CFG_TXCNT ? */
 	if (hal->ah_version == AR5K_AR5210)
-		return (FALSE);
+		return (false);
 
 	return (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT);
 }
@@ -3876,7 +3876,7 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time)
 {
 	AR5K_TRACE;
 	if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
-		return (FALSE);
+		return (false);
 
 	if (hal->ah_version == AR5K_AR5210)
 		AR5K_REG_WRITE(AR5K_SLOT_TIME,
@@ -3884,7 +3884,7 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time)
 	else
 		AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -3930,7 +3930,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	 * Validate input
 	 */
 	if (tx_tries0 == 0)
-		return (FALSE);
+		return (false);
 
 	/* Initialize control descriptor */
 	tx_desc->tx_control_0 = 0;
@@ -3941,7 +3941,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	/*Verify packet length*/
 	if ((tx_desc->tx_control_0 = (packet_length &
 			AR5K_2W_TX_DESC_CTL0_FRAME_LEN)) != packet_length)
-		return (FALSE);
+		return (false);
 	/*
 	 * Verify header length
 	 * XXX: I only found that on 5210 code, does it work on 5211 ?
@@ -3949,7 +3949,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	if (hal->ah_version == AR5K_AR5210)
 		if ((tx_desc->tx_control_0 = (header_length &
 				AR5K_2W_TX_DESC_CTL0_HEADER_LEN)) != header_length)
-			return (FALSE);
+			return (false);
 
 	/*Diferences between 5210-5211*/
 	if (hal->ah_version == AR5K_AR5210) {
@@ -4006,7 +4006,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 			rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4028,7 +4028,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	 * Validate input
 	 */
 	if (tx_tries0 == 0)
-		return (FALSE);
+		return (false);
 
 	/* Initialize status descriptor */
 	tx_desc->tx_control_0 = 0;
@@ -4039,7 +4039,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	/* Setup status descriptor */
 	if ((tx_desc->tx_control_0 = (packet_length &
 			AR5K_4W_TX_DESC_CTL0_FRAME_LEN)) != packet_length)
-		return (FALSE);
+		return (false);
 
 	tx_desc->tx_control_0 |=
 		AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
@@ -4083,7 +4083,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
 		if ((flags & AR5K_TXDESC_RTSENA) &&
 		    (flags & AR5K_TXDESC_CTSENA))
-			return (FALSE);
+			return (false);
 		tx_desc->tx_control_2 |=
 		    rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
 		tx_desc->tx_control_3 |=
@@ -4091,7 +4091,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 		    AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4123,10 +4123,10 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 
 #undef _XTX_TRIES
 
-		return (TRUE);
+		return (true);
 	}
 
-	return(FALSE);
+	return(false);
 }
 
 /*
@@ -4146,15 +4146,15 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	/* Validate segment length and initialize the descriptor */
 	if ((tx_desc->tx_control_1 = (segment_length &
 			AR5K_2W_TX_DESC_CTL1_BUF_LEN)) != segment_length)
-		return (FALSE);
+		return (false);
 
-	if (first_segment != TRUE)
+	if (first_segment != true)
 		tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
 
-	if (last_segment != TRUE)
+	if (last_segment != true)
 		tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE;
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4179,15 +4179,15 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	/* Validate segment length and initialize the descriptor */
 	if ((tx_desc->tx_control_1 = (segment_length &
 			AR5K_4W_TX_DESC_CTL1_BUF_LEN)) != segment_length)
-		return (FALSE);
+		return (false);
 
-	if (first_segment != TRUE)
+	if (first_segment != true)
 		tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
 
-	if (last_segment != TRUE)
+	if (last_segment != true)
 		tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE;
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4370,12 +4370,12 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
 	/*Setup descriptor*/
 	if ((rx_desc->rx_control_1 = (size &
 	    AR5K_DESC_RX_CTL1_BUF_LEN)) != size)
-		return (FALSE);
+		return (false);
 
 	if (flags & AR5K_RXDESC_INTREQ)
 		rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4607,13 +4607,13 @@ ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
 {
 	AR5K_TRACE;
 	if (gpio > AR5K_NUM_GPIO)
-		return (FALSE);
+		return (false);
 
 	AR5K_REG_WRITE(AR5K_GPIOCR,
 	    (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio))
 	    | AR5K_GPIOCR_OUT(gpio));
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4624,13 +4624,13 @@ ath5k_hw_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
 {
 	AR5K_TRACE;
 	if (gpio > AR5K_NUM_GPIO)
-		return (FALSE);
+		return (false);
 
 	AR5K_REG_WRITE(AR5K_GPIOCR,
 	    (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio))
 	    | AR5K_GPIOCR_IN(gpio));
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4658,7 +4658,7 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
 	AR5K_TRACE;
 
 	if (gpio > AR5K_NUM_GPIO)
-		return (FALSE);
+		return (false);
 
 	/* GPIO output magic */
 	data =  AR5K_REG_READ(AR5K_GPIODO);
@@ -4668,7 +4668,7 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
 
 	AR5K_REG_WRITE(AR5K_GPIODO, data);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -4779,13 +4779,13 @@ ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags)
 	if (flags & CHANNEL_2GHZ) {
 		if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) &&
 		    (freq <= hal->ah_capabilities.cap_range.range_2ghz_max))
-			return (TRUE);
+			return (true);
 	} else if (flags & CHANNEL_5GHZ) 
 		if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) &&
 		    (freq <= hal->ah_capabilities.cap_range.range_5ghz_max))
-			return (TRUE);
+			return (true);
 
-	return (FALSE);
+	return (false);
 }
 
 /*
@@ -4806,7 +4806,7 @@ ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels,
 
 	if ((all_channels = kmalloc(sizeof(struct ath5k_channel) * max_channels,
 	    GFP_KERNEL)) == NULL)
-		return (FALSE);
+		return (false);
 
 	i = c = 0;
 	domain_current = hal->ah_regdomain;
@@ -4827,7 +4827,7 @@ ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels,
 debugchan:
 		for (i = min; (i <= max) && (c < max_channels); i++) {
 			freq = ath_hal_ieee2mhz(i, flags);
-			if (ath5k_check_channel(hal, freq, flags) == FALSE)
+			if (ath5k_check_channel(hal, freq, flags) == false)
 				continue;
 			all_channels[c].freq = freq;
 			all_channels[c].channel_flags = flags;
@@ -4866,7 +4866,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/
 		/* Check if channel is supported by the chipset */
 		if (ath5k_check_channel(hal,
 		    ath5k_5ghz_channels[i].rc_channel,
-		    CHANNEL_5GHZ) == FALSE)
+		    CHANNEL_5GHZ) == false)
 			continue;
 
 		/* Match regulation domain */
@@ -4897,7 +4897,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/
 		/* Check if channel is supported by the chipset */
 		if (ath5k_check_channel(hal,
 		    ath5k_2ghz_channels[i].rc_channel,
-		    CHANNEL_2GHZ) == FALSE)
+		    CHANNEL_2GHZ) == false)
 			continue;
 
 		/* Match regulation domain */
@@ -4926,7 +4926,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/
 	memcpy(channels, all_channels, sizeof(struct ath5k_channel) * max_channels);
 	*channels_size = c;
 	kfree(all_channels);
-	return (TRUE);
+	return (true);
 }
 EXPORT_SYMBOL(ath_hal_init_channels);
 
@@ -4968,7 +4968,7 @@ ath5k_get_regdomain(struct ath_hal *hal)
 	u_int16_t code;
 #endif
 
-	ath5k_eeprom_regulation_domain(hal, FALSE, &ieee_regdomain);
+	ath5k_eeprom_regulation_domain(hal, false, &ieee_regdomain);
 	hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
 
 #ifdef COUNTRYCODE
@@ -5018,7 +5018,7 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 	    channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) {
 		AR5K_PRINTF("channel out of supported range (%u MHz)\n",
 		    channel->freq);
-		return (FALSE);
+		return (false);
 	}
 
 	/*
@@ -5031,15 +5031,15 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 	else
 		ret = ath5k_hw_rf5112_channel(hal, channel);
 
-	if (ret == FALSE)
+	if (ret == false)
 		return (ret);
 
 	hal->ah_current_channel.freq = channel->freq;
 	hal->ah_current_channel.channel_flags = channel->channel_flags;
 	hal->ah_turbo = channel->channel_flags == CHANNEL_T ?
-	    TRUE : FALSE;
+	    true : false;
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5079,7 +5079,7 @@ ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 	AR5K_PHY_WRITE(0x30, 0);
 	udelay(1000);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5106,9 +5106,9 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan)
 		athchan->a2_athchan = ((channel - 14) * 4) + 132;
 		athchan->a2_flags = 0x46;
 	} else
-		return (FALSE);
+		return (false);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5131,8 +5131,8 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 	if (channel->channel_flags & CHANNEL_2GHZ) {
 		/* Map 2GHz channel to 5GHz Atheros channel ID */
 		if (ath5k_hw_rf5111_chan2athchan(ieee_channel,
-			&ath_channel_2ghz) == FALSE)
-			return (FALSE);
+			&ath_channel_2ghz) == false)
+			return (false);
 
 		ath_channel = ath_channel_2ghz.a2_athchan;
 		data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff)
@@ -5152,7 +5152,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 	AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8));
 	AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00));
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5178,7 +5178,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 			data0 = ((2 * (c - 672)) - 3040) / 10;
 			data1 = 0;
 		} else
-			return (FALSE);
+			return (false);
 
 		data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
 	} else {
@@ -5192,7 +5192,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 			data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
 			data2 = ath5k_hw_bitswap(1, 2);
 		} else
-			return (FALSE);
+			return (false);
 	}
 
 	data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
@@ -5200,7 +5200,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel)
 	AR5K_PHY_WRITE(0x27, data & 0xff);
 	AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5224,7 +5224,7 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){
 bool
 ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 {
-	bool ret = TRUE;
+	bool ret = true;
 	u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor;
 	u_int i;
 
@@ -5263,7 +5263,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 
 	AGC_ENABLE;
 
-	if (ret == FALSE)
+	if (ret == false)
 		return (ret);
 
 	/*
@@ -5307,10 +5307,10 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 				AR5K_PHY_AGCCTL_CAL);
 
 	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-		AR5K_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) {
+		AR5K_PHY_AGCCTL_CAL, 0, false) == false) {
 		AR5K_PRINTF("calibration timeout (%uMHz)\n",
 			channel->freq);
-		ret = FALSE;
+		ret = false;
 	}
 
 	/* Reset to normal state */
@@ -5318,8 +5318,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 	AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, phy_agc);
 	AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat);
 
-	if (ret == FALSE)
-		return (FALSE);
+	if (ret == false)
+		return (false);
 
 	/*
  	 * Enable noise floor calibration and wait until completion
@@ -5328,10 +5328,10 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 				AR5K_PHY_AGCCTL_NF);
 
 	if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
-		AR5K_PHY_AGCCTL_NF, 0, FALSE) == FALSE) {
+		AR5K_PHY_AGCCTL_NF, 0, false) == false) {
 		AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
 				channel->freq);
-		return (FALSE);
+		return (false);
 	}
 
 	/* Wait until the noise floor is calibrated */
@@ -5350,7 +5350,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 	if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
 		AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
 			channel->freq);
-		return (FALSE);
+		return (false);
 	}
 
 
@@ -5364,7 +5364,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 #undef AGC_ENABLE
 #undef AGC_DISABLE
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5377,11 +5377,11 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 	int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd;
 	AR5K_TRACE;
 
-	if (hal->ah_calibration == FALSE ||
+	if (hal->ah_calibration == false ||
 	    AR5K_REG_READ(AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
 		goto done;
 
-	hal->ah_calibration = FALSE;
+	hal->ah_calibration = false;
 
 	iq_corr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_CORR);
 	i_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_I);
@@ -5415,7 +5415,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel)
 		hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 bool
@@ -5424,7 +5424,7 @@ ath5k_hw_phy_disable(struct ath_hal *hal)
 	AR5K_TRACE;
 	/*Just a try M.F.*/
 	AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE);
-	return (TRUE);
+	return (true);
 }
 
 void /*TODO:Boundary check*/
@@ -5446,7 +5446,7 @@ ath5k_hw_get_def_antenna(struct ath_hal *hal)
 	if (hal->ah_version != AR5K_AR5210)
 		return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA);
 
-	return (FALSE); /*XXX: What do we return for 5210 ?*/
+	return (false); /*XXX: What do we return for 5210 ?*/
 }
 
 u_int
@@ -5471,7 +5471,7 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit
 	entry = ((first - 1) / 8) + offset;
 	position = (first - 1) % 8;
 
-	if (set == TRUE)
+	if (set == true)
 		data = ath5k_hw_bitswap(reg, bits);
 
 	for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
@@ -5479,7 +5479,7 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit
 		mask = (((1 << last) - 1) ^ ((1 << position) - 1)) <<
 		    (col * 8);
 
-		if (set == TRUE) {
+		if (set == true) {
 			rf[entry] &= ~mask;
 			rf[entry] |= ((data << position) << (col * 8)) & mask;
 			data >>= (8 - position);
@@ -5492,7 +5492,7 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit
 		left -= 8 - position;
 	}
 
-	data = set == TRUE ? 1 : ath5k_hw_bitswap(data, bits);
+	data = set == true ? 1 : ath5k_hw_bitswap(data, bits);
 
 	return (data);
 }
@@ -5509,10 +5509,10 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal)
 	rf = hal->ah_rf_banks;
 	hal->ah_gain.g_f_corr = 0;
 
-	if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1)
+	if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1)
 		return (0);
 
-	step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE);
+	step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false);
 	mix = hal->ah_gain.g_step->gos_param[0];
 
 	switch (mix) {
@@ -5546,7 +5546,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal)
 
 	if (hal->ah_radio == AR5K_RF5111) {
 		step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		    0, 6, 37, 0, FALSE);
+		    0, 6, 37, 0, false);
 		level[0] = 0;
 		level[1] = (step == 0x3f) ? 0x32 : step + 4;
 		level[2] = (step != 0x3f) ? 0x40 : level[0];
@@ -5558,7 +5558,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal)
 		    (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
 	} else {
 		mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		    0, 1, 36, 0, FALSE);
+		    0, 1, 36, 0, false);
 		level[0] = level[2] = 0;
 
 		if (mix == 1) {
@@ -5651,20 +5651,20 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode)
 		hal->ah_rf_banks_size = sizeof(rf5112_rf);
 		func = ath5k_hw_rf5112_rfregs;
 	} else
-		return (FALSE);
+		return (false);
 
 	if (hal->ah_rf_banks == NULL) {
 		/* XXX do extra checks? */
 		if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size,
 		    GFP_KERNEL)) == NULL) {
 			AR5K_PRINT("out of memory\n");
-			return (FALSE);
+			return (false);
 		}
 	}
 
 	ret = (func)(hal, channel, mode);
 
-	if (ret == TRUE)
+	if (ret == true)
 		hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
 
 	return (ret);
@@ -5691,7 +5691,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int
 		if (rf5111_rf[i].rf_bank >=
 		    AR5K_RF5111_INI_RF_MAX_BANKS) {
 			AR5K_PRINT("invalid bank\n");
-			return (FALSE);
+			return (false);
 		}
 
 		if (bank != rf5111_rf[i].rf_bank) {
@@ -5710,12 +5710,12 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int
 		obdb = 0;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
-			ee->ee_ob[ee_mode][obdb], 3, 119, 0, TRUE))
-			return (FALSE);
+			ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
+			return (false);
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
-			ee->ee_ob[ee_mode][obdb], 3, 122, 0, TRUE))
-			return (FALSE);
+			ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
+			return (false);
 
 		obdb = 1;
 	} else {
@@ -5727,37 +5727,37 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int
 			    (channel->freq > 4000 ? 0 : -1)));
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_pwd_84, 1, 51, 3, TRUE))
-			return (FALSE);
+			ee->ee_pwd_84, 1, 51, 3, true))
+			return (false);
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_pwd_90, 1, 45, 3, TRUE))
-			return (FALSE);
+			ee->ee_pwd_90, 1, 45, 3, true))
+			return (false);
 	}
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		!ee->ee_xpd[ee_mode], 1, 95, 0, TRUE))
-		return (FALSE);
+		!ee->ee_xpd[ee_mode], 1, 95, 0, true))
+		return (false);
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		ee->ee_x_gain[ee_mode], 4, 96, 0, TRUE))
-		return (FALSE);
+		ee->ee_x_gain[ee_mode], 4, 96, 0, true))
+		return (false);
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, TRUE))
-		return (FALSE);
+		obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
+		return (false);
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE))
-		return (FALSE);
+		obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
+		return (false);
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE))
-		return (FALSE);
+		ee->ee_i_gain[ee_mode], 6, 29, 0, true))
+		return (false);
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		ee->ee_xpd[ee_mode], 1, 4, 0, TRUE))
-		return (FALSE);
+		ee->ee_xpd[ee_mode], 1, 4, 0, true))
+		return (false);
 
 	/* Write RF values */
 	for (i = 0; i < rf_size; i++) {
@@ -5765,7 +5765,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int
 		AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]);
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5798,7 +5798,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int
 		if (rf_ini[i].rf_bank >=
 		    AR5K_RF5112_INI_RF_MAX_BANKS) {
 			AR5K_PRINT("invalid bank\n");
-			return (FALSE);
+			return (false);
 		}
 
 		if (bank != rf_ini[i].rf_bank) {
@@ -5817,12 +5817,12 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int
 		obdb = 0;
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 287, 0, TRUE))
-			return (FALSE);
+			ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
+			return (false);
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 290, 0, TRUE))
-			return (FALSE);
+			ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
+			return (false);
 	} else {
 		/* For 11a, Turbo and XR */
 		ee_mode = AR5K_EEPROM_MODE_11A;
@@ -5832,34 +5832,34 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int
 			    (channel->freq > 4000 ? 0 : -1)));
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 279, 0, TRUE))
-			return (FALSE);
+			ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
+			return (false);
 
 		if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-			ee->ee_ob[ee_mode][obdb], 3, 282, 0, TRUE))
-			return (FALSE);
+			ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
+			return (false);
 	}
 
 #ifdef notyet
 	ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-	    ee->ee_x_gain[ee_mode], 2, 270, 0, TRUE);
+	    ee->ee_x_gain[ee_mode], 2, 270, 0, true);
 	ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-	    ee->ee_x_gain[ee_mode], 2, 257, 0, TRUE);
+	    ee->ee_x_gain[ee_mode], 2, 257, 0, true);
 #endif
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
-		ee->ee_xpd[ee_mode], 1, 302, 0, TRUE))
-		return (FALSE);
+		ee->ee_xpd[ee_mode], 1, 302, 0, true))
+		return (false);
 
 	if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
-		ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE))
-		return (FALSE);
+		ee->ee_i_gain[ee_mode], 6, 14, 0, true))
+		return (false);
 
 	/* Write RF values */
 	for (i = 0; i < rf_size; i++)
 		AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]);
 
-	return (TRUE);
+	return (true);
 }
 
 /*
@@ -5936,7 +5936,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq)
 	case AR5K_INI_PHY_5112:
 		break;
 	default:
-		return (FALSE);
+		return (false);
 	}
 
 	switch (freq) {
@@ -5944,7 +5944,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq)
 	case AR5K_INI_RFGAIN_5GHZ:
 		break;
 	default:
-		return (FALSE);
+		return (false);
 	}
 
 	for (i = 0; i < AR5K_ELEMENTS(ath5k_rfg); i++) {
@@ -5953,7 +5953,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq)
 		    ath5k_rfg[i].rfg_value[phy][freq]);
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 enum ath5k_rfgain
@@ -6052,7 +6052,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow
 	AR5K_TRACE;
 	if (txpower > AR5K_TUNE_MAX_TXPOWER) {
 		AR5K_PRINTF("invalid tx power: %u\n", txpower);
-		return (FALSE);
+		return (false);
 	}
 
 	/* Reset TX power values */
@@ -6088,7 +6088,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow
 	    AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16)
 	    | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0));
 
-	if (hal->ah_txpower.txp_tpc == TRUE) {
+	if (hal->ah_txpower.txp_tpc == true) {
 		AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX,
 		    AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
 		    AR5K_TUNE_MAX_TXPOWER);
@@ -6098,7 +6098,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow
 		    AR5K_TUNE_MAX_TXPOWER);
 	}
 
-	return (TRUE);
+	return (true);
 }
 
 bool
@@ -6226,7 +6226,7 @@ ath5k_hw_dump_state(struct ath_hal *hal)
 bool /*what about VEOL cap ?*/
 ath5k_hw_has_veol(struct ath_hal *hal)
 {
-	return (TRUE);
+	return (true);
 }
 
 void /*Unimplemented*/
@@ -6253,7 +6253,7 @@ const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize)
 	 * We'll ignore this right now. This seems to be some kind of an obscure
 	 * debugging interface for the binary-only HAL.
 	 */
-	return (FALSE);
+	return (false);
 }
 
 bool /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/
@@ -6267,9 +6267,9 @@ ath5k_hw_detect_card_present(struct ath_hal *hal)
 	 * way to do this.
 	 */
 	if (ath5k_hw_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0)
-		return (FALSE);
+		return (false);
 
-	return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE);
+	return (magic == AR5K_EEPROM_MAGIC_VALUE ? true : false);
 }
 
 enum ath5k_status
@@ -6341,7 +6341,7 @@ ath5k_hw_set_capability(struct ath_hal *hal,
 	if (status)
 		*status = AR5K_OK;
 
-	return (FALSE);
+	return (false);
 }
 
 bool
@@ -6349,9 +6349,9 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal)
 {
 	AR5K_TRACE;
 	if (hal->ah_version == AR5K_AR5210)
-		return(TRUE);
+		return(true);
 
-	return (FALSE);
+	return (false);
 }
 
 bool
@@ -6361,7 +6361,7 @@ ath5k_hw_init_pspoll(struct ath_hal *hal)
 	/*
 	 * Not used
 	 */
-	return (FALSE);
+	return (false);
 }
 
 bool
@@ -6373,10 +6373,10 @@ ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
 		AR5K_REG_DISABLE_BITS(AR5K_STA_ID1,
 			AR5K_STA_ID1_NO_PSPOLL |
 			AR5K_STA_ID1_DEFAULT_ANTENNA);
-		return (TRUE);
+		return (true);
 	}
 
-	return (FALSE);
+	return (false);
 }
 
 bool
@@ -6387,10 +6387,10 @@ ath5k_hw_disable_pspoll(struct ath_hal *hal)
 		AR5K_REG_ENABLE_BITS(AR5K_STA_ID1,
 			AR5K_STA_ID1_NO_PSPOLL |
 			AR5K_STA_ID1_DEFAULT_ANTENNA);
-		return (TRUE);
+		return (true);
 	}
 
-	return (FALSE);
+	return (false);
 }
 
 const char * /*O.K. - TODO:Get rid of this*/