commit 9f55076a5d63e32aba592df0c1323b0d48032e27 Author: Jiri Slaby Date: Wed Jul 18 08:23:23 2007 +0200 ath5k_hw whitespace cleanup diff --git a/ath5k_hw.c b/ath5k_hw.c index f74fddc..80a6ca8 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -600,10 +600,9 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) /* * Get the PHY Chip revision */ -static u16 -ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) +static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) { - int i; + unsigned int i; u32 srev; u16 ret; @@ -633,12 +632,10 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) if (hal->ah_version == AR5K_AR5210) { srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf; - - ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; + ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; } else { srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff; - - ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); } /* Reset to the 5GHz mode */ @@ -651,15 +648,15 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) * Get the rate table for a specific operation mode * TODO:Limit this per chipset */ -const struct ath5k_rate_table * -ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, + unsigned int mode) { AR5K_TRACE; - /* Get rate tables */ if (!test_bit(mode, hal->ah_capabilities.cap_mode)) return NULL; + /* Get rate tables */ switch (mode) { case MODE_IEEE80211A: return &ath5k_rt_11a; @@ -671,8 +668,6 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) return &ath5k_rt_11g; case MODE_ATHEROS_TURBOG: return &ath5k_rt_xr; - default: - return NULL; } return NULL; @@ -1018,13 +1013,12 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* Set antenna mode */ AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44), - hal->ah_antenna[ee_mode][0], 0xfffffc06); - - if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] = AR5K_ANT_FIXED_B; - else - ant[0] = ant[1] = AR5K_ANT_FIXED_A; + hal->ah_antenna[ee_mode][0], 0xfffffc06); + if (freq == AR5K_INI_RFGAIN_2GHZ) + ant[0] = ant[1] = AR5K_ANT_FIXED_B; + else + ant[0] = ant[1] = AR5K_ANT_FIXED_A; ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]], AR5K_PHY_ANT_SWITCH_TABLE_0); @@ -1067,8 +1061,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ, - AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, - ee->ee_margin_tx_rx[ee_mode]); + AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, + ee->ee_margin_tx_rx[ee_mode]); } } else { @@ -1152,8 +1146,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL, 0, false)) { - AR5K_PRINTF("calibration timeout (%uMHz)\n", - channel->freq); + AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); return -EAGAIN; } @@ -1194,9 +1187,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (!(channel->val & CHANNEL_B)) { hal->ah_calibration = true; AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); + AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_RUN); + AR5K_PHY_IQ_RUN); } /* @@ -1250,8 +1243,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Disable beacons and reset the register */ - AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, - AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); + AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE | + AR5K_BEACON_RESET_TSF); return 0; } @@ -1281,11 +1274,8 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) val &= AR5K_RESET_CTL_CHIP; mask &= AR5K_RESET_CTL_CHIP; } else { - val &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; - - mask &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; } ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false); @@ -1309,8 +1299,8 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration) { + unsigned int i; u32 staid; - int i; AR5K_TRACE; staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1); @@ -1345,7 +1335,7 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, for (i = 5000; i > 0; i--) { /* Check if the chip did wake up */ if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) & - AR5K_PCICFG_SPWR_DN) == 0) + AR5K_PCICFG_SPWR_DN) == 0) break; /* Wait a bit and retry */ @@ -1384,8 +1374,6 @@ ath5k_hw_get_power_mode(struct ath_hw *hal) } - - /***********************\ DMA Related Functions \***********************/ @@ -1507,8 +1495,8 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) { - int i = 100, pending; - u32 tx_queue; + unsigned int i = 100; + u32 tx_queue, pending; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1564,10 +1552,10 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) * Get the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) */ -u32 -ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) +u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) { u16 tx_reg; + AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1601,6 +1589,7 @@ ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) { u16 tx_reg; + AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1646,6 +1635,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) { u32 trigger_level, imr; bool status = false; + AR5K_TRACE; /* @@ -1814,7 +1804,7 @@ enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) } /* - * Enalbe HW radar detection + * Enable HW radar detection */ void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) @@ -1833,13 +1823,10 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) * possible radar activity. */ if (hal->ah_version == AR5K_AR5210) { - if (enable == true) { - AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, - AR5K_IMR_RXPHY); - } else { - AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, - AR5K_IMR_RXPHY); - } + if (enable == true) + AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); + else + AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); } else { /*Also set AR5K_PHY_RADAR register on 5111/5112*/ if (enable == true) { @@ -1891,8 +1878,8 @@ static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) return -EIO; - *data = (u16) - (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff); + *data = (u16)(ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & + 0xffff); return 0; } udelay(15); @@ -1962,9 +1949,8 @@ static u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) val = (5 * bin) + 4800; else - val = bin > 62 ? - (10 * 62) + (5 * (bin - 62)) + 5100 : - (bin * 10) + 5100; + val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : + (bin * 10) + 5100; } else { if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) val = bin + 2300; @@ -2050,8 +2036,7 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, ee->ee_thr_62[mode] = val & 0xff; if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) - ee->ee_thr_62[mode] = - mode == AR5K_EEPROM_MODE_11A ? 15 : 28; + ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; AR5K_EEPROM_READ(o++, val); ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; @@ -2103,7 +2088,7 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, } if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && - mode == AR5K_EEPROM_MODE_11A) { + mode == AR5K_EEPROM_MODE_11A) { ee->ee_i_cal[mode] = (val >> 8) & 0x3f; ee->ee_q_cal[mode] = (val >> 3) & 0x1f; } @@ -2124,10 +2109,10 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, static int ath5k_eeprom_init(struct ath_hw *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + unsigned int mode, i; + int ret; u32 offset; u16 val; - int ret, i; - unsigned int mode; /* Initial TX thermal adjustment values */ ee->ee_tx_clip = 4; @@ -2197,8 +2182,7 @@ static int ath5k_eeprom_init(struct ath_hw *hal) */ mode = AR5K_EEPROM_MODE_11A; - ee->ee_turbo_max_power[mode] = - AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); + ee->ee_turbo_max_power[mode] = AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); @@ -2251,13 +2235,13 @@ static int ath5k_eeprom_init(struct ath_hw *hal) if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); } if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { @@ -2286,9 +2270,9 @@ static int ath5k_eeprom_init(struct ath_hw *hal) if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); AR5K_EEPROM_READ(offset++, val); ee->ee_turbo_max_power[mode] = val & 0x7f; @@ -2296,11 +2280,10 @@ static int ath5k_eeprom_init(struct ath_hw *hal) AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; - } AR5K_EEPROM_READ(offset++, val); ee->ee_i_cal[mode] = (val >> 8) & 0x3f; @@ -2336,8 +2319,7 @@ static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) if (ret) return ret; - for (offset = 0x1f, octet = 0, total = 0; - offset >= 0x1d; offset--) { + for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { ret = ath5k_hw_eeprom_read(hal, offset, &data); if (ret) return ret; @@ -2377,8 +2359,7 @@ static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_EEPROM_PROTECT_WR_128_191) return false; - if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, - ee_regdomain) != 0) + if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0) return false; hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; @@ -2548,8 +2529,7 @@ ath5k_hw_set_opmode(struct ath_hw *hal) /* * Get station id */ -void -ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) +void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) { AR5K_TRACE; memcpy(mac, hal->ah_sta_id, ETH_ALEN); @@ -2610,7 +2590,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, } AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM, - tim_offset ? tim_offset + 4 : 0); + tim_offset ? tim_offset + 4 : 0); ath5k_hw_enable_pspoll(hal, NULL, 0); } @@ -2625,7 +2605,6 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) AR5K_TRACE; if (hal->ah_version == AR5K_AR5212) { - low_id = AR5K_LOW_ID(mask); high_id = AR5K_HIGH_ID(mask); @@ -2633,8 +2612,9 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); return true; - } else - return false; + } + + return false; } /* @@ -2687,13 +2667,12 @@ ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) AR5K_TRACE; if (index >= 64) - return false; + return false; else if (index >= 32) - AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, - (1 << (index - 32))); + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, + (1 << (index - 32))); else - AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, - (1 << index)); + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; } @@ -2707,13 +2686,12 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) AR5K_TRACE; if (index >= 64) - return false; + return false; else if (index >= 32) - AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, - (1 << (index - 32))); + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, + (1 << (index - 32))); else - AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, - (1 << index)); + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; } @@ -2735,8 +2713,7 @@ ath5k_hw_get_rx_filter(struct ath_hw *hal) if (data & AR5K_PHY_ERR_FIL_RADAR) filter |= AR5K_RX_FILTER_PHYRADAR; - if (data & (AR5K_PHY_ERR_FIL_OFDM | - AR5K_PHY_ERR_FIL_CCK)) + if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) filter |= AR5K_RX_FILTER_PHYERR; } @@ -2758,8 +2735,7 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) if (filter & AR5K_RX_FILTER_PHYRADAR) data |= AR5K_PHY_ERR_FIL_RADAR; if (filter & AR5K_RX_FILTER_PHYERR) - data |= AR5K_PHY_ERR_FIL_OFDM | - AR5K_PHY_ERR_FIL_CCK; + data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; } /* @@ -2773,11 +2749,9 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) /*Zero length DMA*/ if (data) - AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, - AR5K_RXCFG_ZLFDMA); + AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); else - AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, - AR5K_RXCFG_ZLFDMA); + AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); /*Write RX Filter register*/ ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER); @@ -2826,7 +2800,7 @@ void ath5k_hw_reset_tsf(struct ath_hw *hal) */ void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, - u32 interval) + u32 interval) { u32 timer1, timer2, timer3; @@ -2852,8 +2826,7 @@ ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, 0x00000003; } - timer3 = next_beacon + - (hal->ah_atim_window ? hal->ah_atim_window : 1); + timer3 = next_beacon + (hal->ah_atim_window ? hal->ah_atim_window : 1); /* * Set the beacon register and enable all timers. @@ -2906,9 +2879,9 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * (Contention Free Period) and timer registers */ cfp_period = state->bs_cfp_period * state->bs_dtim_period * - state->bs_interval; + state->bs_interval; next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * - state->bs_interval; + state->bs_interval; AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | @@ -2945,8 +2918,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * setting value to a largest value and seeing which values register. */ - AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, - AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); + AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, + state->bs_bmiss_threshold); /* * Set sleep control register @@ -2960,21 +2933,21 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * Set enhanced sleep registers on 5212 */ if (hal->ah_version == AR5K_AR5212) { - if ((state->bs_sleep_duration > state->bs_interval) && - (roundup(state->bs_sleep_duration, interval) == - state->bs_sleep_duration)) + if (state->bs_sleep_duration > state->bs_interval && + roundup(state->bs_sleep_duration, interval) == + state->bs_sleep_duration) interval = state->bs_sleep_duration; - if (state->bs_sleep_duration > dtim && - (dtim == 0 || roundup(state->bs_sleep_duration, dtim) == - state->bs_sleep_duration)) + if (state->bs_sleep_duration > dtim && (dtim == 0 || + roundup(state->bs_sleep_duration, dtim) == + state->bs_sleep_duration)) dtim = state->bs_sleep_duration; if (interval > dtim) return; - next_beacon = interval == dtim ? - state->bs_next_dtim: state->bs_next_beacon; + next_beacon = interval == dtim ? state->bs_next_dtim : + state->bs_next_beacon; ath5k_hw_reg_write(hal, AR5K_REG_SM((state->bs_next_dtim - 3) << 3, @@ -3009,8 +2982,7 @@ ath5k_hw_reset_beacon(struct ath_hw *hal) * Disable some beacon register values */ AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_DEFAULT_ANTENNA | - AR5K_STA_ID1_PCF); + AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON); } @@ -3021,8 +2993,8 @@ ath5k_hw_reset_beacon(struct ath_hw *hal) bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) { + unsigned int i; bool ret; - int i; AR5K_TRACE; @@ -3032,9 +3004,13 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) * Wait for beaconn queue to finish by checking * Control Register and Beacon Status Register. */ - for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && - (ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && - (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); + for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) { + if (!(ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) + || + !(ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_BSR_TXQ1F)) + break; + udelay(10); + } /* Timeout... */ if (i <= 0) { @@ -3042,12 +3018,12 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) * Re-schedule the beacon queue */ ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1); - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, + AR5K_BCR); return false; } - ret= true; - + ret = true; } else { /*5211/5212*/ ret = ath5k_hw_register_timeout(hal, @@ -3096,11 +3072,11 @@ ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), - hal->ah_turbo) <= timeout) + hal->ah_turbo) <= timeout) return false; AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, - ath5k_hw_htoclock(timeout, hal->ah_turbo)); + ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; } @@ -3112,8 +3088,9 @@ unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), - AR5K_TIME_OUT_ACK), hal->ah_turbo)); + + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, + AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), hal->ah_turbo)); } /* @@ -3124,11 +3101,11 @@ ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), - hal->ah_turbo) <= timeout) + hal->ah_turbo) <= timeout) return false; AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, - ath5k_hw_htoclock(timeout, hal->ah_turbo)); + ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; } @@ -3140,8 +3117,8 @@ unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), - AR5K_TIME_OUT_CTS), hal->ah_turbo)); + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, + AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), hal->ah_turbo)); } /* @@ -3298,7 +3275,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, case AR5K_TX_QUEUE_XR_DATA: if (hal->ah_version != AR5K_AR5212) AR5K_PRINTF("XR data queues only " - "supported in 5212!"); + "supported in 5212!\n"); queue = AR5K_TX_QUEUE_ID_XR_DATA; break; default: @@ -3422,14 +3399,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; hal->ah_aifs = AR5K_TUNE_AIFS; /*XR is only supported on 5212*/ - if (IS_CHAN_XR(hal->ah_current_channel) - && (hal->ah_version == AR5K_AR5212)) { + if (IS_CHAN_XR(hal->ah_current_channel) && + hal->ah_version == AR5K_AR5212) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; hal->ah_aifs = AR5K_TUNE_AIFS_XR; /*B mode is not supported on 5210*/ - } else if (IS_CHAN_B(hal->ah_current_channel) - && (hal->ah_version != AR5K_AR5210)) { + } else if (IS_CHAN_B(hal->ah_current_channel) && + hal->ah_version != AR5K_AR5210) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; hal->ah_aifs = AR5K_TUNE_AIFS_11B; @@ -3439,12 +3416,10 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) while (cw_min < hal->ah_cw_min) cw_min = (cw_min << 1) | 1; - cw_min = tq->tqi_cw_min < 0 ? - (cw_min >> (-tq->tqi_cw_min)) : - ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); - cw_max = tq->tqi_cw_max < 0 ? - (cw_max >> (-tq->tqi_cw_max)) : - ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); + cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) : + ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); + cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) : + ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); /* * Calculate and set retry limits @@ -3452,9 +3427,8 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) if (hal->ah_software_retry == true) { /* XXX Need to test this */ retry_lg = hal->ah_limit_tx_retries; - retry_sh = retry_lg = - retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? - AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; + retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? + AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; } else { retry_lg = AR5K_INIT_LG_RETRY; retry_sh = AR5K_INIT_SH_RETRY; @@ -3509,7 +3483,8 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_CBR); if (tq->tqi_cbr_overflow_limit) - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, + AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_CBR_THRES_ENABLE); } @@ -3547,12 +3522,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) */ switch (tq->tqi_type) { case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, + AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_DBA_GT | AR5K_QCU_MISC_CBREXP_BCN | AR5K_QCU_MISC_BCN_ENABLE); - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, + AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << AR5K_DCU_MISC_ARBLOCK_CTL_S) | AR5K_DCU_MISC_POST_FR_BKOFF_DIS | @@ -3594,7 +3571,7 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXOK) | AR5K_REG_SM(hal->ah_txq_interrupts, - AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); + AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, @@ -3651,8 +3628,8 @@ ath5k_hw_get_slot_time(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) - return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) & - 0xffff, hal->ah_turbo)); + return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, + AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo)); else return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff; } @@ -4120,29 +4097,24 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, * Frame receive status */ desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, + AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; + desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, + desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, + AR5K_OLD_RX_DESC_STATUS0_MORE; + desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); desc->ds_us.rx.rs_status = 0; /* * Key table status */ - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) - desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, + if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) + desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); else desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; @@ -4150,10 +4122,9 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, /* * Receive/descriptor errors */ - if ((rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) + if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) + == 0) { + if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; if (rx_status->rx_status_1 & @@ -4201,19 +4172,16 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, */ desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & AR5K_NEW_RX_DESC_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); + desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); + desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA; desc->ds_us.rx.rs_more = rx_status->rx_status_0 & AR5K_NEW_RX_DESC_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); + desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, + AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); desc->ds_us.rx.rs_status = 0; /* @@ -4244,8 +4212,7 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; - if (rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) + if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } @@ -4253,8 +4220,6 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, } - - /****************\ GPIO Functions \****************/ @@ -4275,8 +4240,7 @@ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); else - AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, - AR5K_PCICFG_LED); + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LED); /* * Some blinking values, define at your wish @@ -4284,28 +4248,23 @@ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) switch (state) { case AR5K_LED_SCAN: case AR5K_LED_AUTH: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_PEND; - led_5210 = AR5K_PCICFG_LED_PEND| - AR5K_PCICFG_LED_BCTL; + led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND; + led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL; break; case AR5K_LED_INIT: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_NONE; + led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE; led_5210 = AR5K_PCICFG_LED_PEND; break; case AR5K_LED_ASSOC: case AR5K_LED_RUN: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_ASSOC; + led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC; led_5210 = AR5K_PCICFG_LED_ASSOC; break; default: - led = AR5K_PCICFG_LEDMODE_PROM | - AR5K_PCICFG_LED_NONE; + led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE; led_5210 = AR5K_PCICFG_LED_PEND; break; } @@ -4373,7 +4332,7 @@ int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) return -EINVAL; /* GPIO output magic */ - data = ath5k_hw_reg_read(hal, AR5K_GPIODO); + data = ath5k_hw_reg_read(hal, AR5K_GPIODO); data &= ~(1 << gpio); data |= (val & 1) << gpio; @@ -4399,9 +4358,9 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, * Set the GPIO interrupt */ data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) & - ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | - AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | - (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); + ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | + AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | + (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); ath5k_hw_reg_write(hal, interrupt_level ? data : (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); @@ -4413,8 +4372,6 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, } - - /*********************************\ Regulatory Domain/Channels Setup \*********************************/ @@ -4489,7 +4446,8 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) /* * Set channel on RF5110 */ -static int ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +static int ath5k_hw_rf5110_channel(struct ath_hw *hal, + struct ieee80211_channel *channel) { u32 data; @@ -4687,7 +4645,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal, * Disable beacons and RX/TX queues, wait */ AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210, - AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210); ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); @@ -4920,16 +4878,15 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { last = (position + left > 8) ? 8 : position + left; - mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << - (col * 8); + mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8); if (set == true) { rf[entry] &= ~mask; rf[entry] |= ((data << position) << (col * 8)) & mask; data >>= (8 - position); } else { - data = (((rf[entry] & mask) >> (col * 8)) >> - position) << shift; + data = (((rf[entry] & mask) >> (col * 8)) >> position) + << shift; shift += last - position; } @@ -4987,20 +4944,20 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) rf = hal->ah_rf_banks; if (hal->ah_radio == AR5K_RF5111) { - step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 6, 37, 0, false); + step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 6, 37, 0, + false); level[0] = 0; level[1] = (step == 0x3f) ? 0x32 : step + 4; level[2] = (step != 0x3f) ? 0x40 : level[0]; level[3] = level[2] + 0x32; hal->ah_gain.g_high = level[3] - - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); hal->ah_gain.g_low = level[0] + - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); } else { - mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 1, 36, 0, false); + mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, + false); level[0] = level[2] = 0; if (mix == 1) { @@ -5011,10 +4968,10 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) } } - return ((hal->ah_gain.g_current >= level[0] && - hal->ah_gain.g_current <= level[1]) || - (hal->ah_gain.g_current >= level[2] && - hal->ah_gain.g_current <= level[3])); + return (hal->ah_gain.g_current >= level[0] && + hal->ah_gain.g_current <= level[1]) || + (hal->ah_gain.g_current >= level[2] && + hal->ah_gain.g_current <= level[3]); } static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) @@ -5063,10 +5020,8 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) done: #ifdef AR5K_DEBUG AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", - ret, - hal->ah_gain.g_step_idx, - hal->ah_gain.g_current, - hal->ah_gain.g_target); + ret, hal->ah_gain.g_step_idx, hal->ah_gain.g_current, + hal->ah_gain.g_target); #endif return ret; @@ -5120,9 +5075,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); u32 *rf; - int i, obdb = -1, bank = -1; + const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); + unsigned int i; + int obdb = -1, bank = -1; u32 ee_mode; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5165,10 +5121,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal, } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); + (channel->freq > 4000 ? 0 : -1))); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_84, 1, 51, 3, true)) @@ -5219,12 +5175,12 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal, static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) { + const struct ath5k_ini_rf *rf_ini; struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - unsigned int rf_size; u32 *rf; - int i, obdb = -1, bank = -1; + unsigned int rf_size, i; + int obdb = -1, bank = -1; u32 ee_mode; - const struct ath5k_ini_rf *rf_ini; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5338,10 +5294,10 @@ static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, if (freq == AR5K_INI_RFGAIN_5GHZ) { /* For 11a and Turbo */ - obdb = channel->freq >= 5725 ? 3 : + obdb = channel->freq >= 5725 ? 3 : (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); } ob = ee->ee_ob[ee_mode][obdb]; @@ -5375,7 +5331,7 @@ static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) { - int i; + unsigned int i; switch (phy) { case AR5K_INI_PHY_5111: @@ -5449,10 +5405,11 @@ done: /* * Initialize the tx power table (not fully implemented) */ -static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power) +static void ath5k_txpower_table(struct ath_hw *hal, + struct ieee80211_channel *channel, s16 max_power) { - u16 txpower, *rates; unsigned int i, min, max, n; + u16 txpower, *rates; rates = hal->ah_txpower.txp_rates; @@ -5487,7 +5444,8 @@ static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *ch * Set transmition power */ static int /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower) +ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, + unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; unsigned int i; @@ -5510,8 +5468,8 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned */ for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { ath5k_hw_reg_write(hal, - ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) - | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ), + ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) | + (((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff), AR5K_PHY_PCDAC_TXPOWER(i)); } @@ -5724,8 +5682,7 @@ ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_NO_PSPOLL | - AR5K_STA_ID1_DEFAULT_ANTENNA); + AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; } @@ -5738,8 +5695,7 @@ ath5k_hw_disable_pspoll(struct ath_hw *hal) AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_NO_PSPOLL | - AR5K_STA_ID1_DEFAULT_ANTENNA); + AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; }