commit 50b76de6e6c38b5bee038446e998aae8a3233df9 Author: Jiri Slaby Date: Sun Jun 17 23:10:44 2007 +0200 openhal/ath5k_hw.c cleanup diff --git a/openhal/ath5k.h b/openhal/ath5k.h index a3f8980..25949f0 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -925,8 +925,6 @@ struct ath5k_capabilities { * Misc defines */ -#define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0])) - struct ath_hal; typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 56962b2..3fd4cc2 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -36,9 +36,9 @@ */ static const struct { - u_int16_t vendor; - u_int16_t device; - u_int8_t mac_version; + u16 vendor; + u16 device; + u8 mac_version; } ath5k_known_products[] = { /* * From pcidevs_data.h @@ -79,11 +79,11 @@ static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -bool ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); -bool ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t, bool); -u_int16_t ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); +bool ath5k_hw_nic_reset(struct ath_hal *, u32); +bool ath5k_hw_nic_wakeup(struct ath_hal *, u16, bool); +u16 ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); void ath5k_hw_fill(struct ath_hal *); -bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, u_int); +bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, unsigned int); AR5K_HAL_FUNCTIONS(extern, ath5k_hw,); @@ -136,14 +136,14 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; * TODO:Left here for combatibility, change it in at5k */ const char * -ath_hal_probe(u_int16_t vendor, u_int16_t device) +ath_hal_probe(u16 vendor, u16 device) { int i; /* * Perform a linear search on the table of supported devices */ - for (i = 0; i < AR5K_ELEMENTS(ath5k_known_products); i++) { + for (i = 0; i < ARRAY_SIZE(ath5k_known_products); i++) { if (vendor == ath5k_known_products[i].vendor && device == ath5k_known_products[i].device){ switch (ath5k_known_products[i].mac_version) { @@ -154,12 +154,12 @@ ath_hal_probe(u_int16_t vendor, u_int16_t device) case AR5K_AR5212: return("AR5212"); default: - return (""); + return ""; } } } - return (NULL); + return NULL; } EXPORT_SYMBOL(ath_hal_probe); @@ -167,12 +167,12 @@ EXPORT_SYMBOL(ath_hal_probe); * Calculate transmition time of a frame * TODO: Left here for combatibility, change it in ath5k */ -u_int16_t /*TODO: Is this really hardware dependent ?*/ +u16 /*TODO: Is this really hardware dependent ?*/ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, - u_int32_t frame_length, u_int16_t rate_index, bool short_preamble) + u32 frame_length, u16 rate_index, bool short_preamble) { const struct ath5k_rate *rate; - u_int32_t value; + u32 value; AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); @@ -198,7 +198,7 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * Orthogonal Frequency Division Multiplexing */ if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); + return 0; value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length); break; @@ -208,7 +208,7 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * Atheros "Turbo Mode" (doubled rates) */ if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); + return 0; value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length); break; @@ -218,15 +218,15 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * Atheros "eXtended Range" (XR) */ if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); + return 0; value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length); break; default: - return (0); + return 0; } - return (value); + return value; } EXPORT_SYMBOL(ath_hal_computetxtime); @@ -234,14 +234,14 @@ EXPORT_SYMBOL(ath_hal_computetxtime); * Return the supported 802.11 operation modes * TODO:Left here for combatibility, change it in at5k */ -u_int/*TODO:Fix this */ +unsigned int/*TODO:Fix this */ ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) { switch(hal->ah_version){ case AR5K_AR5212: - return (AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G); + return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; case AR5K_AR5211: - return (AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G); + return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; default : return(AR5K_MODE_11A); } @@ -252,29 +252,29 @@ EXPORT_SYMBOL(ath_hal_getwirelessmodes); * Functions used internaly */ -static u_int32_t -ath5k_hw_bitswap(u_int32_t val, u_int bits) +static u32 +ath5k_hw_bitswap(u32 val, unsigned int bits) { - u_int32_t retval = 0, bit, i; + u32 retval = 0, bit, i; for (i = 0; i < bits; i++) { bit = (val >> i) & 1; retval = (retval << 1) | bit; } - return (retval); + return retval; } -inline u_int -ath5k_hw_htoclock(u_int usec, bool turbo) +inline unsigned int +ath5k_hw_htoclock(unsigned int usec, bool turbo) { - return (turbo == true ? (usec * 80) : (usec * 40)); + return turbo == true ? (usec * 80) : (usec * 40); } -inline u_int -ath5k_hw_clocktoh(u_int clock, bool turbo) +inline unsigned int +ath5k_hw_clocktoh(unsigned int clock, bool turbo) { - return (turbo == true ? (clock / 80) : (clock / 40)); + return turbo == true ? (clock / 80) : (clock / 40); } /* @@ -328,11 +328,11 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) * Check if a register write has been completed */ static bool -ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, - u_int32_t val, bool is_set) +ath5k_hw_register_timeout(struct ath_hal *hal, u32 reg, u32 flag, + u32 val, bool is_set) { int i; - u_int32_t data; + u32 data; for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { data = AR5K_REG_READ(reg); @@ -344,9 +344,9 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, } if (i <= 0) - return (false); + return false; - return (true); + return true; } @@ -362,10 +362,10 @@ struct ath_hal * ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) { struct ath_hal *hal = NULL; - u_int8_t mac[ETH_ALEN]; - u_int8_t mac_version = 255; /*Initialize this to something else than ath5k_version*/ + u8 mac[ETH_ALEN]; + u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ int i; - u_int32_t srev; + u32 srev; *status = AR5K_EINVAL; /*TODO:Use eeprom_magic to verify chipset*/ @@ -373,7 +373,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /* * Check if device is a known one */ - for (i = 0; i < AR5K_ELEMENTS(ath5k_known_products); i++) { + for (i = 0; i < ARRAY_SIZE(ath5k_known_products); i++) { if (device == ath5k_known_products[i].device) mac_version = ath5k_known_products[i].mac_version; } @@ -382,19 +382,17 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) if (mac_version == 255) { *status = AR5K_ENOTSUPP; AR5K_PRINTF("device not supported: 0x%04x\n", device); - return (NULL); + return NULL; } /*If we passed the test malloc a hal struct*/ - if ((hal = kmalloc(sizeof(struct ath_hal), GFP_KERNEL)) == NULL) { + hal = kzalloc(sizeof(struct ath_hal), GFP_KERNEL); + if (hal == NULL) { *status = AR5K_ENOMEM; AR5K_PRINT("out of memory\n"); - return (NULL); + return NULL; } - /*Initialize it*/ - memset(hal, 0, sizeof(struct ath_hal)); - hal->ah_sc = sc; hal->ah_sh = sh; hal->ah_device = device; @@ -553,20 +551,20 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) *status = AR5K_OK; - return (hal); + return hal; failed: kfree(hal); - return (NULL); + return NULL; } /* * Bring up MAC + PHY Chips */ bool -ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) +ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) { - u_int32_t turbo, mode, clock; + u32 turbo, mode, clock; turbo = 0; mode = 0; @@ -595,7 +593,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) clock |= AR5K_PHY_PLL_40MHZ; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (false); + return false; } if (flags & CHANNEL_CCK) { @@ -611,7 +609,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) mode |= AR5K_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (false); + return false; } if (flags & CHANNEL_TURBO) { @@ -630,17 +628,17 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI) == false) { AR5K_PRINT("failed to reset the PCI chipset\n"); - return (false); + return false; } - udelay(1000); + mdelay(1); } /* ...wakeup */ if (ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0) == false) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return (false); + return false; } /* ...enable Atheros turbo mode if requested */ @@ -650,17 +648,17 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) /* ...reset chipset */ if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == false) { AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return (false); + return false; } - udelay(1000); + mdelay(1); } /* ...reset chipset and PCI device */ if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == false) { AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); - return (false); + return false; } if (hal->ah_version == AR5K_AR5210) @@ -670,13 +668,13 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) if (ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0) == false) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return (false); + return false; } /* ...final warm reset */ if (ath5k_hw_nic_reset(hal, 0) == false) { AR5K_PRINT("failed to warm reset the MAC Chip\n"); - return (false); + return false; } if (hal->ah_version != AR5K_AR5210){ @@ -688,18 +686,18 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); } - return (true); + return true; } /* * Get the PHY Chip revision */ -u_int16_t +u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) { int i; - u_int32_t srev; - u_int16_t ret; + u32 srev; + u16 ret; AR5K_TRACE; @@ -714,10 +712,10 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); break; default: - return (0); + return 0; } - udelay(2000); + mdelay(2); /* ...wait until PHY is ready and read the selected radio revision */ AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16); @@ -728,17 +726,17 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) if (hal->ah_version == AR5K_AR5210) { srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf; - ret = (u_int16_t) ath5k_hw_bitswap(srev, 4) + 1; + ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; } else { srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff; - ret = (u_int16_t) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); } /* Reset to the 5GHz mode */ AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); - return (ret); + return ret; } /* @@ -746,27 +744,26 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) * TODO:Limit this per chipset */ const struct ath5k_rate_table * -ath5k_hw_get_rate_table(struct ath_hal *hal, u_int mode) +ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode) { - AR5K_TRACE; switch (mode) { case AR5K_MODE_11A: - return (&hal->ah_rt_11a); + return &hal->ah_rt_11a; case AR5K_MODE_TURBO: - return (&hal->ah_rt_turbo); + return &hal->ah_rt_turbo; case AR5K_MODE_11B: - return (&hal->ah_rt_11b); + return &hal->ah_rt_11b; case AR5K_MODE_11G: - return (&hal->ah_rt_11g); + return &hal->ah_rt_11g; case AR5K_MODE_XR: - return (&hal->ah_rt_xr); + return &hal->ah_rt_xr; default: - return (NULL); + return NULL; } - return (NULL); + return NULL; } /* @@ -780,9 +777,7 @@ ath5k_hw_detach(struct ath_hal *hal) if (hal->ah_rf_banks != NULL) kfree(hal->ah_rf_banks); - /* - * Free HAL structure, assume interrupts are down - */ + /* assume interrupts are down */ kfree(hal); } @@ -801,9 +796,9 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int8_t mac[ETH_ALEN]; - u_int32_t data, noise_floor, s_seq, s_ant, s_led[3]; - u_int i, phy, mode, freq, off, ee_mode, ant[2]; + u8 mac[ETH_ALEN]; + u32 data, noise_floor, s_seq, s_ant, s_led[3]; + unsigned int i, phy, mode, freq, off, ee_mode, ant[2]; const struct ath5k_rate_table *rt; AR5K_TRACE; @@ -841,7 +836,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /*Wakeup the device*/ if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) { *status = AR5K_EIO; - return (false); + return false; } /* @@ -861,7 +856,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, else { AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); *status = AR5K_EINVAL; - return (false); + return false; } switch (channel->channel_flags & CHANNEL_MODES) { @@ -894,7 +889,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, case CHANNEL_XR: if (hal->ah_version == AR5K_AR5211) { AR5K_PRINTF("XR mode not available on 5211"); - return (false); + return false; } mode = AR5K_INI_VAL_XR; freq = AR5K_INI_RFGAIN_5GHZ; @@ -903,7 +898,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, default: AR5K_PRINTF("invalid channel: %d\n", channel->freq); *status = AR5K_EINVAL; - return (false); + return false; } /* PHY access enable */ @@ -923,7 +918,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < AR5K_ELEMENTS(ar5212_mode); i++) { + for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) { if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) off = AR5K_INI_PHY_511X; else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && @@ -936,15 +931,15 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_mode[i].mode_register, + AR5K_REG_WRITE((u32)ar5212_mode[i].mode_register, ar5212_mode[i].mode_value[off][mode]); } } /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < AR5K_ELEMENTS(ar5211_mode); i++) { + for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, + AR5K_REG_WRITE((u32)ar5211_mode[i].mode_register, ar5211_mode[i].mode_value[mode]); } } @@ -955,7 +950,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) { + for (i = 0; i < ARRAY_SIZE(ar5212_ini); i++) { if (change_channel == true && ar5212_ini[i].ini_register >= AR5K_PCU_MIN && ar5212_ini[i].ini_register <= AR5K_PCU_MAX) @@ -966,27 +961,27 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, (hal->ah_radio == AR5K_RF5112 && ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_ini[i].ini_register, + AR5K_REG_WRITE((u32)ar5212_ini[i].ini_register, ar5212_ini[i].ini_value); } } } /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { + for (i = 0; i < ARRAY_SIZE(ar5211_ini); i++) { if (change_channel == true && ar5211_ini[i].ini_register >= AR5K_PCU_MIN && ar5211_ini[i].ini_register <= AR5K_PCU_MAX) continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, + AR5K_REG_WRITE((u32)ar5211_ini[i].ini_register, ar5211_ini[i].ini_value); } } /*For 5210*/ if (hal->ah_version == AR5K_AR5210) - for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) { + for (i = 0; i < ARRAY_SIZE(ar5210_ini); i++) { if (change_channel == true && ar5210_ini[i].ini_register >= AR5K_PCU_MIN && ar5210_ini[i].ini_register <= AR5K_PCU_MAX) @@ -1015,10 +1010,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_rfgain(hal, phy, freq) == false) { *status = AR5K_EIO; - return (false); + return false; } - udelay(1000); + mdelay(1); /* * Set rate duration table on 5212 @@ -1081,7 +1076,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER) == false) { *status = AR5K_EIO; - return (false); + return false; } /* @@ -1090,7 +1085,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_rfregs(hal, channel, mode) == false) { *status = AR5K_EINPROGRESS; - return (false); + return false; } /* @@ -1100,7 +1095,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /* Write OFDM timings on 5212*/ if (hal->ah_version == AR5K_AR5212) { if (channel->channel_flags & CHANNEL_OFDM) { - u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, + u32 coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man, clock; clock = channel->channel_flags & CHANNEL_T ? 80 : 40; @@ -1112,7 +1107,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (!coef_exp) { *status = AR5K_EINVAL; - return (false); + return false; } coef_exp = 14 - (coef_exp - 24); @@ -1193,10 +1188,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, } } else { - udelay(1000); + mdelay(1); /* Disable phy and wait */ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); - udelay(1000); + mdelay(1); } /* @@ -1245,7 +1240,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_channel(hal, channel) == false) { *status = AR5K_EIO; - return (false); + return false; } /* @@ -1263,7 +1258,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, udelay(100 + data); } else { - udelay(1000); + mdelay(1); } /* @@ -1276,7 +1271,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_CAL, 0, false) == false) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); - return (false); + return false; } /* @@ -1289,12 +1284,12 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return (false); + return false; } /* Wait until the noise floor is calibrated and read the value */ for (i = 20; i > 0; i--) { - udelay(1000); + mdelay(1); noise_floor = AR5K_REG_READ(AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & @@ -1308,7 +1303,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return (false); + return false; } hal->ah_calibration = false; @@ -1332,7 +1327,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_reset_tx_queue(hal, i) == false) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); *status = AR5K_EINVAL; - return (false); + return false; } } @@ -1375,17 +1370,17 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_REG_DISABLE_BITS(AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); - return (true); + return true; } /* * Reset chipset */ bool -ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) +ath5k_hw_nic_reset(struct ath_hal *hal, u32 val) { bool ret = false; - u_int32_t mask = val ? val : ~0; + u32 mask = val ? val : ~0; AR5K_TRACE; @@ -1419,7 +1414,7 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) if ((val & AR5K_RESET_CTL_PCU) == 0) AR5K_REG_WRITE(AR5K_CFG, AR5K_INIT_CFG); - return (ret); + return ret; } /* @@ -1431,9 +1426,9 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) */ bool ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, - bool set_chip, u_int16_t sleep_duration) + bool set_chip, u16 sleep_duration) { - u_int32_t staid; + u32 staid; int i; AR5K_TRACE; @@ -1479,13 +1474,13 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, /* Fail if the chip didn't wake up */ if (i <= 0) - return (false); + return false; staid &= ~AR5K_STA_ID1_PWR_SV; break; default: - return (false); + return false; } commit: @@ -1493,7 +1488,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, AR5K_REG_WRITE(AR5K_STA_ID1, staid); - return (true); + return true; } /* @@ -1504,7 +1499,7 @@ enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal) { AR5K_TRACE; - return (hal->ah_power_mode); + return hal->ah_power_mode; } @@ -1547,23 +1542,23 @@ ath5k_hw_stop_rx_dma(struct ath_hal *hal) i--) udelay(10); - return (i > 0 ? true : false); + return i > 0 ? true : false; } /* * Get the address of the RX Descriptor */ -u_int32_t +u32 ath5k_hw_get_rx_buf(struct ath_hal *hal) { - return (AR5K_REG_READ(AR5K_RXDP)); + return AR5K_REG_READ(AR5K_RXDP); } /* * Set the address of the RX Descriptor */ void -ath5k_hw_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) +ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr) { AR5K_TRACE; @@ -1580,16 +1575,16 @@ ath5k_hw_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) * (see also QCU/DCU functions) */ bool -ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) +ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue) { - u_int32_t tx_queue; + u32 tx_queue; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; if (hal->ah_version == AR5K_AR5210) { @@ -1616,20 +1611,20 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) AR5K_BCR_BDMAE); break; default: - return (false); + return false; } /* Start queue */ AR5K_REG_WRITE(AR5K_CR, tx_queue); } else { /* Return if queue is disabled */ if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) - return (false); + return false; /* Start queue */ AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); } - return (true); + return true; } /* @@ -1637,17 +1632,17 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) +ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue) { int i = 100, pending; - u_int32_t tx_queue; + u32 tx_queue; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; if (hal->ah_version == AR5K_AR5210) { tx_queue = AR5K_REG_READ(AR5K_CR); @@ -1666,7 +1661,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) AR5K_REG_WRITE(AR5K_BSR, 0); break; default: - return (false); + return false; } /* Stop queue */ @@ -1689,17 +1684,17 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) } /*TODO: Check for success else return false*/ - return (true); + return true; } /* * Get the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) */ -u_int32_t -ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) +u32 +ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue) { - u_int16_t tx_reg; + u16 tx_reg; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1717,13 +1712,13 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) tx_reg = AR5K_NOQCU_TXDP1; break; default: - return (0xffffffff); + return 0xffffffff; } } else { tx_reg = AR5K_QUEUE_TXDP(queue); } - return (AR5K_REG_READ(tx_reg)); + return AR5K_REG_READ(tx_reg); } /* @@ -1731,9 +1726,9 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) +ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr) { - u_int16_t tx_reg; + u16 tx_reg; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1751,7 +1746,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) tx_reg = AR5K_NOQCU_TXDP1; break; default: - return (false); + return false; } } else { /* @@ -1760,7 +1755,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) * (this won't work if the queue is still active) */ if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) - return (false); + return false; tx_reg = AR5K_QUEUE_TXDP(queue); } @@ -1768,7 +1763,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) /* Set descriptor pointer */ AR5K_REG_WRITE(tx_reg, phys_addr); - return (true); + return true; } /* @@ -1777,7 +1772,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) bool ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) { - u_int32_t trigger_level, imr; + u32 trigger_level, imr; bool status = false; AR5K_TRACE; @@ -1814,7 +1809,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) */ ath5k_hw_set_intr(hal, imr); - return (status); + return status; } /* @@ -1828,16 +1823,16 @@ bool ath5k_hw_is_intr_pending(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_INTPEND) == true ? true : false); + return AR5K_REG_READ(AR5K_INTPEND) == true ? true : false; } /* * Get interrupt mask (ISR) */ bool -ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) +ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask) { - u_int32_t data; + u32 data; AR5K_TRACE; @@ -1848,7 +1843,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) if (hal->ah_version == AR5K_AR5210) { if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) { *interrupt_mask = data; - return (false); + return false; } } @@ -1863,7 +1858,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; if (data == AR5K_INT_NOCARD) - return (false); + return false; if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) *interrupt_mask |= AR5K_INT_RX; @@ -1885,7 +1880,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) * Special interrupt handling (not caught by the driver) */ if (((*interrupt_mask) & AR5K_ISR_RXPHY) && - hal->ah_radar.r_enabled == true) + hal->ah_radar.r_enabled == true) ath5k_radar_alert(hal); /* @@ -1900,21 +1895,21 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) * In case we didn't handle anything, * print the register value. */ - if (*interrupt_mask == 0) + if (*interrupt_mask == 0 && printk_ratelimit()) AR5K_PRINTF("0x%08x\n", data); - return (true); + return true; } /* * Return the interrupt mask stored previously * TODO: Remove ? */ -u_int32_t +u32 ath5k_hw_get_intr(struct ath_hal *hal) { AR5K_TRACE; - return (hal->ah_imr); + return hal->ah_imr; } /* @@ -1971,7 +1966,7 @@ ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) /* ..re-enable interrupts */ AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); - return (old_mask); + return old_mask; } /* @@ -2034,17 +2029,16 @@ bool ath5k_hw_eeprom_is_busy(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? - true : false); + return AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? true : false; } /* * Read from eeprom */ int -ath5k_hw_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) +ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data) { - u_int32_t status, timeout; + u32 status, timeout; AR5K_TRACE; /* @@ -2063,25 +2057,25 @@ ath5k_hw_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) - return (EIO); - *data = (u_int16_t) + return EIO; + *data = (u16) (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); - return (0); + return 0; } udelay(15); } - return (ETIMEDOUT); + return ETIMEDOUT; } /* * Write to eeprom - currently disabled, use at your own risk */ int -ath5k_hw_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) +ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data) { #if 0 - u_int32_t status, timeout; + u32 status, timeout; AR5K_TRACE; @@ -2115,23 +2109,23 @@ ath5k_hw_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_WRDONE) { if (status & AR5K_EEPROM_STAT_WRERR) - return (EIO); - return (0); + return EIO; + return 0; } udelay(15); } #endif AR5K_PRINTF("EEPROM Write is disabled!"); - return (ETIMEDOUT); + return ETIMEDOUT; } -u_int16_t -ath5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) +u16 +ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode) { - u_int16_t val; + u16 val; if (bin == AR5K_EEPROM_CHANNEL_DIS) - return (bin); + return bin; if (mode == AR5K_EEPROM_MODE_11A) { if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) @@ -2147,18 +2141,18 @@ ath5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) val = bin + 2400; } - return (val); + return val; } /* * Read antenna infos from eeprom */ int -ath5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) +ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t o = *offset; - u_int16_t val; + u32 o = *offset; + u16 val; int ret, i = 0; AR5K_EEPROM_READ(o++, val); @@ -2206,18 +2200,18 @@ ath5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) /* return new offset */ *offset = o; - return (0); + return 0; } /* * Read supported modes from eeprom */ int -ath5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) +ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t o = *offset; - u_int16_t val; + u32 o = *offset; + u16 val; int ret; AR5K_EEPROM_READ(o++, val); @@ -2290,7 +2284,7 @@ ath5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) /* return new offset */ *offset = o; - return (0); + return 0; } /* @@ -2300,10 +2294,10 @@ int ath5k_eeprom_init(struct ath_hal *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t offset; - u_int16_t val; + u32 offset; + u16 val; int ret, i; - u_int mode; + unsigned int mode; /* Initial TX thermal adjustment values */ ee->ee_tx_clip = 4; @@ -2321,7 +2315,7 @@ ath5k_eeprom_init(struct ath_hal *hal) /* Return if we have an old EEPROM */ if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) - return (0); + return 0; #ifdef notyet /* @@ -2334,7 +2328,7 @@ ath5k_eeprom_init(struct ath_hal *hal) } if (cksum != AR5K_EEPROM_INFO_CKSUM) { AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); - return (AR5K_EEBADSUM); + return AR5K_EEBADSUM; } #endif @@ -2379,10 +2373,10 @@ ath5k_eeprom_init(struct ath_hal *hal) offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); + return ret; AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); ee->ee_ob[mode][3] = (val >> 5) & 0x7; ee->ee_db[mode][3] = (val >> 2) & 0x7; ee->ee_ob[mode][2] = (val << 1) & 0x7; @@ -2396,7 +2390,7 @@ ath5k_eeprom_init(struct ath_hal *hal) ee->ee_db[mode][0] = val & 0x7; if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); + return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { AR5K_EEPROM_READ(offset++, val); @@ -2410,15 +2404,15 @@ ath5k_eeprom_init(struct ath_hal *hal) offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); + return ret; AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); + return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); @@ -2443,15 +2437,15 @@ ath5k_eeprom_init(struct ath_hal *hal) offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); + return ret; AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); + return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); @@ -2486,30 +2480,30 @@ ath5k_eeprom_init(struct ath_hal *hal) * Read 5GHz EEPROM channels */ - return (0); + return 0; } /* * Read the MAC address from eeprom */ int -ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) +ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) { - u_int32_t total, offset; - u_int16_t data; + u32 total, offset; + u16 data; int octet; - u_int8_t mac_d[ETH_ALEN]; + u8 mac_d[ETH_ALEN]; memset(mac, 0, ETH_ALEN); memset(&mac_d, 0, ETH_ALEN); if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) - return (AR5K_EIO); + return AR5K_EIO; for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { if (hal->ah_eeprom_read(hal, offset, &data) != 0) - return (AR5K_EIO); + return AR5K_EIO; total += data; mac_d[octet + 1] = data & 0xff; @@ -2520,9 +2514,9 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) memcpy(mac, mac_d, ETH_ALEN); if ((!total) || total == (3 * 0xffff)) - return (AR5K_EINVAL); + return AR5K_EINVAL; - return (0); + return 0; } /* @@ -2532,13 +2526,13 @@ bool ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, ieee80211_regdomain_t *regdomain) { - u_int16_t ee_regdomain; + u16 ee_regdomain; /* Read current value */ if (write != true) { ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; *regdomain = ath5k_regdomain_to_ieee(ee_regdomain); - return (true); + return true; } ee_regdomain = ath5k_regdomain_from_ieee(*regdomain); @@ -2546,36 +2540,35 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, /* Try to write a new value */ if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_EEPROM_PROTECT_WR_128_191) - return (false); + return false; if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain) != 0) - return (false); + return false; hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; - return (true); + return true; } /* * Use the above to write a new regulatory domain */ bool -ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - enum ath5k_status *status) +ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, + enum ath5k_status *status) { ieee80211_regdomain_t ieee_regdomain; ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); - if (ath5k_eeprom_regulation_domain(hal, true, - &ieee_regdomain) == true) { + if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true){ *status = AR5K_OK; - return (true); + return true; } *status = AR5K_EIO; - return (false); + return false; } /* @@ -2584,7 +2577,7 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, bool ath5k_hw_get_capabilities(struct ath_hal *hal) { - u_int16_t ee_header; + u16 ee_header; AR5K_TRACE; /* Capabilities stored in the EEPROM */ @@ -2648,12 +2641,9 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) else hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; - return (true); + return true; } - - - /*********************************\ Protocol Control Unit Functions \*********************************/ @@ -2664,7 +2654,7 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) void ath5k_hw_set_opmode(struct ath_hal *hal) { - u_int32_t pcu_reg, beacon_reg, low_id, high_id; + u32 pcu_reg, beacon_reg, low_id, high_id; pcu_reg = 0; beacon_reg = 0; @@ -2713,8 +2703,6 @@ ath5k_hw_set_opmode(struct ath_hal *hal) */ if (hal->ah_version == AR5K_AR5210) AR5K_REG_WRITE(AR5K_BCR, beacon_reg); - - return; } void /*TODO: Get rid of this, clean up the driver code, only set_opmode is needed*/ @@ -2722,7 +2710,6 @@ ath5k_hw_set_pcu_config(struct ath_hal *hal) { AR5K_TRACE; ath5k_hw_set_opmode(hal); - return; } /* @@ -2733,7 +2720,7 @@ ath5k_hw_set_pcu_config(struct ath_hal *hal) * Get station id */ void -ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) +ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac) { AR5K_TRACE; memcpy(mac, hal->ah_sta_id, ETH_ALEN); @@ -2743,9 +2730,9 @@ ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) * Set station id */ bool -ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) +ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac) { - u_int32_t low_id, high_id; + u32 low_id, high_id; AR5K_TRACE; /* Set new station ID */ @@ -2757,18 +2744,18 @@ ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) AR5K_REG_WRITE(AR5K_STA_ID0, low_id); AR5K_REG_WRITE(AR5K_STA_ID1, high_id); - return (true); + return true; } /* * Set BSSID */ void -ath5k_hw_set_associd(struct ath_hal *hal, const u_int8_t *bssid, - u_int16_t assoc_id) +ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, + u16 assoc_id) { - u_int32_t low_id, high_id; - u_int16_t tim_offset = 0; + u32 low_id, high_id; + u16 tim_offset = 0; /* * Set simple BSSID mask on 5212 @@ -2803,9 +2790,9 @@ ath5k_hw_set_associd(struct ath_hal *hal, const u_int8_t *bssid, * Set BSSID mask on 5212 */ bool -ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) +ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask) { - u_int32_t low_id, high_id; + u32 low_id, high_id; AR5K_TRACE; if (hal->ah_version == AR5K_AR5212) { @@ -2816,9 +2803,9 @@ ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) AR5K_REG_WRITE(AR5K_BSS_IDM0, low_id); AR5K_REG_WRITE(AR5K_BSS_IDM1, high_id); - return (true); + return true; } else - return (false); + return false; } /* @@ -2853,8 +2840,8 @@ ath5k_hw_stop_pcu_recv(struct ath_hal *hal) * Set multicast filter */ void -ath5k_hw_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, - u_int32_t filter1) +ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, + u32 filter1) { AR5K_TRACE; /* Set the multicat filter */ @@ -2866,12 +2853,12 @@ ath5k_hw_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, * Set multicast filter by index */ bool -ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) +ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index) { AR5K_TRACE; if (index >= 64) - return (false); + return false; else if (index >= 32) AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1, (1 << (index - 32))); @@ -2879,19 +2866,19 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0, (1 << index)); - return (true); + return true; } /* * Clear Multicast filter by index */ bool -ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) +ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index) { AR5K_TRACE; if (index >= 64) - return (false); + return false; else if (index >= 32) AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1, (1 << (index - 32))); @@ -2899,16 +2886,16 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0, (1 << index)); - return (true); + return true; } /* * Get current rx filter */ -u_int32_t +u32 ath5k_hw_get_rx_filter(struct ath_hal *hal) { - u_int32_t data, filter = 0; + u32 data, filter = 0; AR5K_TRACE; filter = AR5K_REG_READ(AR5K_RX_FILTER); @@ -2924,16 +2911,16 @@ ath5k_hw_get_rx_filter(struct ath_hal *hal) filter |= AR5K_RX_FILTER_PHYERR; } - return (filter); + return filter; } /* * Set rx filter */ void -ath5k_hw_set_rx_filter(struct ath_hal *hal, u_int32_t filter) +ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter) { - u_int32_t data = 0; + u32 data = 0; AR5K_TRACE; @@ -2979,23 +2966,23 @@ ath5k_hw_set_rx_filter(struct ath_hal *hal, u_int32_t filter) /* * Get a 32bit TSF */ -u_int32_t +u32 ath5k_hw_get_tsf32(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_TSF_L32)); + return AR5K_REG_READ(AR5K_TSF_L32); } /* * Get the full 64bit TSF */ -u_int64_t +u64 ath5k_hw_get_tsf64(struct ath_hal *hal) { - u_int64_t tsf = AR5K_REG_READ(AR5K_TSF_U32); + u64 tsf = AR5K_REG_READ(AR5K_TSF_U32); AR5K_TRACE; - return (AR5K_REG_READ(AR5K_TSF_L32) | (tsf << 32)); + return AR5K_REG_READ(AR5K_TSF_L32) | (tsf << 32); } /* @@ -3013,10 +3000,10 @@ ath5k_hw_reset_tsf(struct ath_hal *hal) * Initialize beacon timers */ void -ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, - u_int32_t interval) +ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, + u32 interval) { - u_int32_t timer1, timer2, timer3; + u32 timer1, timer2, timer3; AR5K_TRACE; /* @@ -3063,7 +3050,7 @@ ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, void ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state) { - u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; + u32 cfp_period, next_cfp, dtim, interval, next_beacon; /* * TODO: should be changed through *state @@ -3073,9 +3060,9 @@ ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state * ok ? Is it O.K. for tsf here to be 0 or should we use * get_tsf ? */ - u_int32_t dtim_count = 0; /* XXX */ - u_int32_t cfp_count = 0; /* XXX */ - u_int32_t tsf = 0; /* XXX */ + u32 dtim_count = 0; /* XXX */ + u32 cfp_count = 0; /* XXX */ + u32 tsf = 0; /* XXX */ AR5K_TRACE; /* Return on an invalid beacon state */ @@ -3234,7 +3221,7 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, phys_addr); AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE); - return (false); + return false; } ret= true; @@ -3245,10 +3232,10 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) AR5K_QCU_STS_FRMPENDCNT, 0, false); if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) - return (false); + return false; } - return (ret); + return ret; } /* @@ -3278,7 +3265,6 @@ void /*Unimplemented*/ ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; - return; } /* @@ -3289,23 +3275,23 @@ ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stat * Set ACK timeout on PCU */ bool -ath5k_hw_set_ack_timeout(struct ath_hal *hal, u_int timeout) +ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), hal->ah_turbo) <= timeout) - return (false); + return false; AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_htoclock(timeout, hal->ah_turbo)); - return (true); + return true; } /* * Read the ACK timeout from PCU */ -u_int +unsigned int ath5k_hw_get_ack_timeout(struct ath_hal *hal) { AR5K_TRACE; @@ -3317,23 +3303,23 @@ ath5k_hw_get_ack_timeout(struct ath_hal *hal) * Set CTS timeout on PCU */ bool -ath5k_hw_set_cts_timeout(struct ath_hal *hal, u_int timeout) +ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), hal->ah_turbo) <= timeout) - return (false); + return false; AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_htoclock(timeout, hal->ah_turbo)); - return (true); + return true; } /* * Read CTS timeout from PCU */ -u_int +unsigned int ath5k_hw_get_cts_timeout(struct ath_hal *hal) { AR5K_TRACE; @@ -3356,26 +3342,26 @@ ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) * Only WEP for now */ if (cipher == AR5K_CIPHER_WEP) - return (true); + return true; - return (false); + return false; } /* * Get key cache size */ -u_int32_t +u32 ath5k_hw_get_keycache_size(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_KEYCACHE_SIZE); + return AR5K_KEYCACHE_SIZE; } /* * Reset encryption key */ bool -ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) +ath5k_hw_reset_key(struct ath_hal *hal, u16 entry) { int i; @@ -3390,14 +3376,14 @@ ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), AR5K_KEYTABLE_TYPE_NULL); - return (false); /*????*/ + return false; /*????*/ } /* * Check if a key entry is valid */ bool -ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) +ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry) { AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); @@ -3407,20 +3393,20 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) */ if (AR5K_REG_READ(AR5K_KEYTABLE_MAC1(entry)) & AR5K_KEYTABLE_VALID) - return (true); + return true; - return (false); + return false; } /* * Set encryption key */ bool -ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, - const struct ath5k_keyval *keyval, const u_int8_t *mac, int xor_notused) +ath5k_hw_set_key(struct ath_hal *hal, u16 entry, + const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused) { int i; - u_int32_t key_v[AR5K_KEYCACHE_SIZE - 2]; + u32 key_v[AR5K_KEYCACHE_SIZE - 2]; AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); @@ -3454,20 +3440,20 @@ ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, default: /* Unsupported key length (not WEP40/104/128) */ - return (false); + return false; } - for (i = 0; i < AR5K_ELEMENTS(key_v); i++) + for (i = 0; i < ARRAY_SIZE(key_v); i++) AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), key_v[i]); - return (ath5k_hw_set_key_lladdr(hal, entry, mac)); + return ath5k_hw_set_key_lladdr(hal, entry, mac); } bool -ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, - const u_int8_t *mac) +ath5k_hw_set_key_lladdr(struct ath_hal *hal, u16 entry, + const u8 *mac) { - u_int32_t low_id, high_id; + u32 low_id, high_id; AR5K_TRACE; /* Invalid entry (key table overflow) */ @@ -3487,7 +3473,7 @@ ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id); - return (true); + return true; } @@ -3504,7 +3490,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info) { - u_int queue; + unsigned int queue; AR5K_TRACE; /* @@ -3521,7 +3507,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; break; default: - return (-1); + return -1; } } else { switch (queue_type) { @@ -3531,7 +3517,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, AR5K_TX_QUEUE_INACTIVE; queue++) { if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) - return (-1); + return -1; } break; case AR5K_TX_QUEUE_UAPSD: @@ -3549,7 +3535,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, queue = AR5K_TX_QUEUE_ID_XR_DATA; break; default: - return (-1); + return -1; } } @@ -3563,7 +3549,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, queue_info->tqi_type = queue_type; if (ath5k_hw_setup_tx_queueprops(hal, queue, queue_info) != true) - return (-1); + return -1; } /* * We use ah_txq_interrupts to hold a temp value for @@ -3572,7 +3558,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, */ AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); - return (queue); + return queue; } /* @@ -3586,7 +3572,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); @@ -3598,7 +3584,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - return (true); + return true; } /* @@ -3609,14 +3595,14 @@ ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info { AR5K_TRACE; memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); - return (true); + return true; } /* * Set a transmit queue inactive */ bool -ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) +ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3626,16 +3612,16 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) /*For SIMR setup*/ AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - return (false); /*???*/ + return false; /*???*/ } /* * Set DFS params for a transmit queue */ bool -ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) +ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue) { - u_int32_t cw_min, cw_max, retry_lg, retry_sh; + u32 cw_min, cw_max, retry_lg, retry_sh; struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; struct ath5k_ar5210_ini_mode ar5210_mode[] = @@ -3647,18 +3633,18 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) tq = &hal->ah_txq[queue]; if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (true); + return true; if (hal->ah_version == AR5K_AR5210) { /* Only handle data queues, others will be ignored */ if (tq->tqi_type != AR5K_TX_QUEUE_DATA) - return (true); + return true; /* * Write initial mode register settings */ - for (i = 0; i < AR5K_ELEMENTS(ar5210_mode); i++) - AR5K_REG_WRITE((u_int32_t)ar5210_mode[i].mode_register, + for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++) + AR5K_REG_WRITE((u32)ar5210_mode[i].mode_register, hal->ah_turbo == true ? ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base); } @@ -3845,38 +3831,38 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); } - return (true); + return true; } /* * Get number of pending frames * for a specific queue [5211+] */ -u_int32_t -ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) { +u32 +ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; /* XXX: How about AR5K_CFG_TXCNT ? */ if (hal->ah_version == AR5K_AR5210) - return (false); + return false; - return (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT); + return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT; } /* * Set slot time */ bool -ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) +ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time) { AR5K_TRACE; if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) - return (false); + return false; if (hal->ah_version == AR5K_AR5210) AR5K_REG_WRITE(AR5K_SLOT_TIME, @@ -3884,13 +3870,13 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) else AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); - return (true); + return true; } /* * Get slot time */ -u_int +unsigned int ath5k_hw_get_slot_time(struct ath_hal *hal) { AR5K_TRACE; @@ -3898,7 +3884,7 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) return (ath5k_hw_clocktoh(AR5K_REG_READ(AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo)); else - return (AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff); + return AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff; } @@ -3917,11 +3903,11 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) */ static bool ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, - u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - u_int flags, u_int rtscts_rate, u_int rtscts_duration) + unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, + unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, + unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) { - u_int32_t frame_type; + u32 frame_type; struct ath5k_hw_2w_tx_desc *tx_desc; tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; @@ -3930,7 +3916,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Validate input */ if (tx_tries0 == 0) - return (false); + return false; /* Initialize control descriptor */ tx_desc->tx_control_0 = 0; @@ -3941,7 +3927,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /*Verify packet length*/ if ((tx_desc->tx_control_0 = (packet_length & AR5K_2W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return (false); + return false; /* * Verify header length * XXX: I only found that on 5210 code, does it work on 5211 ? @@ -3949,7 +3935,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (hal->ah_version == AR5K_AR5210) if ((tx_desc->tx_control_0 = (header_length & AR5K_2W_TX_DESC_CTL0_HEADER_LEN)) != header_length) - return (false); + return false; /*Diferences between 5210-5211*/ if (hal->ah_version == AR5K_AR5210) { @@ -4006,7 +3992,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; } - return (true); + return true; } /* @@ -4014,9 +4000,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, - u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - u_int flags, u_int rtscts_rate, u_int rtscts_duration) + unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, + unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, + unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4028,7 +4014,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Validate input */ if (tx_tries0 == 0) - return (false); + return false; /* Initialize status descriptor */ tx_desc->tx_control_0 = 0; @@ -4039,7 +4025,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Setup status descriptor */ if ((tx_desc->tx_control_0 = (packet_length & AR5K_4W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return (false); + return false; tx_desc->tx_control_0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | @@ -4083,7 +4069,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { if ((flags & AR5K_TXDESC_RTSENA) && (flags & AR5K_TXDESC_CTSENA)) - return (false); + return false; tx_desc->tx_control_2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION; tx_desc->tx_control_3 |= @@ -4091,7 +4077,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); } - return (true); + return true; } /* @@ -4099,8 +4085,8 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - u_int tx_rate3, u_int tx_tries3) + unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, + unsigned int tx_rate3, u_int tx_tries3) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4123,7 +4109,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, #undef _XTX_TRIES - return (true); + return true; } return(false); @@ -4134,7 +4120,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) + unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4146,7 +4132,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_2W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return (false); + return false; if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN; @@ -4154,7 +4140,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (last_segment != true) tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE; - return (true); + return true; } /* @@ -4163,7 +4149,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, bool first_segment, bool last_segment, + unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4179,7 +4165,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_4W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return (false); + return false; if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN; @@ -4187,7 +4173,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (last_segment != true) tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE; - return (true); + return true; } /* @@ -4204,7 +4190,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Get descriptor status @@ -4246,7 +4232,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return (AR5K_OK); + return AR5K_OK; } /* @@ -4264,7 +4250,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Get descriptor status @@ -4335,7 +4321,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return (AR5K_OK); + return AR5K_OK; } /* @@ -4347,7 +4333,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) */ bool ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t size, u_int flags) + u32 size, unsigned int flags) { struct ath5k_rx_desc *rx_desc; @@ -4370,12 +4356,12 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, /*Setup descriptor*/ if ((rx_desc->rx_control_1 = (size & AR5K_DESC_RX_CTL1_BUF_LEN)) != size) - return (false); + return false; if (flags & AR5K_RXDESC_INTREQ) rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; - return (true); + return true; } /* @@ -4383,7 +4369,7 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) + u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_old_rx_status *rx_status; @@ -4391,7 +4377,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Frame receive status @@ -4450,7 +4436,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; } - return (AR5K_OK); + return AR5K_OK; } /* @@ -4458,7 +4444,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, */ static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) + u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_new_rx_status *rx_status; struct ath5k_hw_rx_error *rx_err; @@ -4471,7 +4457,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Frame receive status @@ -4530,7 +4516,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } - return (AR5K_OK); + return AR5K_OK; } @@ -4546,9 +4532,9 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, void ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) { - u_int32_t led; + u32 led; /*5210 has different led mode handling*/ - u_int32_t led_5210; + u32 led_5210; AR5K_TRACE; @@ -4603,45 +4589,45 @@ ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) * Set GPIO outputs */ bool -ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) +ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (false); + return false; AR5K_REG_WRITE(AR5K_GPIOCR, (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio)); - return (true); + return true; } /* * Set GPIO inputs */ bool -ath5k_hw_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) +ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (false); + return false; AR5K_REG_WRITE(AR5K_GPIOCR, (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio)); - return (true); + return true; } /* * Get GPIO state */ -u_int32_t -ath5k_hw_get_gpio(struct ath_hal *hal, u_int32_t gpio) +u32 +ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (0xffffffff); + return 0xffffffff; /* GPIO input magic */ return (((AR5K_REG_READ(AR5K_GPIODI) & @@ -4652,13 +4638,13 @@ ath5k_hw_get_gpio(struct ath_hal *hal, u_int32_t gpio) * Set GPIO state */ bool -ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) +ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val) { - u_int32_t data; + u32 data; AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (false); + return false; /* GPIO output magic */ data = AR5K_REG_READ(AR5K_GPIODO); @@ -4668,17 +4654,17 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) AR5K_REG_WRITE(AR5K_GPIODO, data); - return (true); + return true; } /* * Initialize the GPIO interrupt (RFKill switch) */ void -ath5k_hw_set_gpio_intr(struct ath_hal *hal, u_int gpio, - u_int32_t interrupt_level) +ath5k_hw_set_gpio_intr(struct ath_hal *hal, unsigned int gpio, + u32 interrupt_level) { - u_int32_t data; + u32 data; AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4719,8 +4705,8 @@ ath5k_hw_set_gpio_intr(struct ath_hal *hal, u_int gpio, /* * Convert MHz frequency to IEEE channel number. */ -u_int -ath_hal_mhz2ieee(u_int freq, u_int flags) +unsigned int +ath_hal_mhz2ieee(unsigned int freq, u_int flags) { if (flags & CHANNEL_2GHZ) { /* 2GHz band */ if (freq == 2484) /* Japan */ @@ -4745,8 +4731,8 @@ EXPORT_SYMBOL(ath_hal_mhz2ieee); /* * Convert IEEE channel number to MHz frequency. */ -u_int -ath_hal_ieee2mhz(u_int chan, u_int flags) +unsigned int +ath_hal_ieee2mhz(unsigned int chan, u_int flags) { if (flags & CHANNEL_2GHZ) { /* 2GHz band */ if (chan == 14) @@ -4773,19 +4759,19 @@ EXPORT_SYMBOL(ath_hal_ieee2mhz); * Check if a channel is supported */ bool -ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) +ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags) { /* Check if the channel is in our supported range */ if (flags & CHANNEL_2GHZ) { if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) - return (true); + return true; } else if (flags & CHANNEL_5GHZ) if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) - return (true); + return true; - return (false); + return false; } /* @@ -4795,18 +4781,18 @@ ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) */ bool ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, - u_int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u_int16_t mode, + unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended) { - u_int i, c; - u_int32_t domain_current; - u_int domain_5ghz, domain_2ghz; + unsigned int i, c; + u32 domain_current; + unsigned int domain_5ghz, domain_2ghz; struct ath5k_channel *all_channels; enum ieee80211_countrycode country_current; if ((all_channels = kmalloc(sizeof(struct ath5k_channel) * max_channels, GFP_KERNEL)) == NULL) - return (false); + return false; i = c = 0; domain_current = hal->ah_regdomain; @@ -4818,7 +4804,7 @@ ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, */ if (domain_current == DMN_DEFAULT || CHAN_DEBUG == 1) { int min, max, freq; - u_int flags; + unsigned int flags; min = 1; /* 2GHz channel 1 -2412Mhz */ max = 26;/* 2GHz channel 26 (non-ieee) -2732Mhz */ @@ -4861,7 +4847,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ * and mode. 5GHz... */ for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && - (i < AR5K_ELEMENTS(ath5k_5ghz_channels)) && + (i < ARRAY_SIZE(ath5k_5ghz_channels)) && (c < max_channels); i++) { /* Check if channel is supported by the chipset */ if (ath5k_check_channel(hal, @@ -4891,7 +4877,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ * ...and 2GHz. */ for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && - (i < AR5K_ELEMENTS(ath5k_2ghz_channels)) && + (i < ARRAY_SIZE(ath5k_2ghz_channels)) && (c < max_channels); i++) { /* Check if channel is supported by the chipset */ @@ -4926,7 +4912,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ memcpy(channels, all_channels, sizeof(struct ath5k_channel) * max_channels); *channels_size = c; kfree(all_channels); - return (true); + return true; } EXPORT_SYMBOL(ath_hal_init_channels); @@ -4934,10 +4920,10 @@ EXPORT_SYMBOL(ath_hal_init_channels); * Regdomain stuff, these also don't belong here etc */ -u_int16_t +u16 ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) { - u_int32_t regdomain = (u_int32_t)ieee; + u32 regdomain = (u32)ieee; /* * Use the default regulation domain if the value is empty @@ -4945,27 +4931,27 @@ ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) */ if (ieee80211_regdomain2flag(regdomain, IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) - return ((u_int16_t)AR5K_TUNE_REGDOMAIN); + return (u16)AR5K_TUNE_REGDOMAIN; /* It is supported, just return the value */ - return (regdomain); + return regdomain; } ieee80211_regdomain_t -ath5k_regdomain_to_ieee(u_int16_t regdomain) +ath5k_regdomain_to_ieee(u16 regdomain) { ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; - return (ieee); + return ieee; } -u_int16_t +u16 ath5k_get_regdomain(struct ath_hal *hal) { - u_int16_t regdomain; + u16 regdomain; ieee80211_regdomain_t ieee_regdomain; #ifdef COUNTRYCODE - u_int16_t code; + u16 code; #endif ath5k_eeprom_regulation_domain(hal, false, &ieee_regdomain); @@ -4983,14 +4969,14 @@ ath5k_get_regdomain(struct ath_hal *hal) regdomain = ath5k_regdomain_from_ieee(ieee_regdomain); hal->ah_capabilities.cap_regdomain.reg_current = regdomain; - return (regdomain); + return regdomain; } -u_int16_t /*TODO:Get rid of this*/ +u16 /*TODO:Get rid of this*/ ath5k_hw_get_regdomain(struct ath_hal *hal) { AR5K_TRACE; - return (ath5k_get_regdomain(hal)); + return ath5k_get_regdomain(hal); } @@ -5018,7 +5004,7 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { AR5K_PRINTF("channel out of supported range (%u MHz)\n", channel->freq); - return (false); + return false; } /* @@ -5032,23 +5018,23 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) ret = ath5k_hw_rf5112_channel(hal, channel); if (ret == false) - return (ret); + return ret; hal->ah_current_channel.freq = channel->freq; hal->ah_current_channel.channel_flags = channel->channel_flags; hal->ah_turbo = channel->channel_flags == CHANNEL_T ? true : false; - return (true); + return true; } /* * Convertion needed for RF5110 */ -u_int32_t +u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) { - u_int32_t athchan; + u32 athchan; /* * Convert IEEE channel/MHz to an internal channel value used @@ -5060,7 +5046,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) channel->channel_flags) - 24) / 2, 5) << 1) | (1 << 6) | 0x1; - return (athchan); + return athchan; } /* @@ -5069,7 +5055,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) bool ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int32_t data; + u32 data; /* * Set the channel and wait @@ -5079,14 +5065,14 @@ ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x30, 0); udelay(1000); - return (true); + return true; } /* * Convertion needed for 5111 */ bool -ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) +ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan) { int channel; @@ -5106,9 +5092,9 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) athchan->a2_athchan = ((channel - 14) * 4) + 132; athchan->a2_flags = 0x46; } else - return (false); + return false; - return (true); + return true; } /* @@ -5117,8 +5103,8 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) bool ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int ieee_channel, ath_channel; - u_int32_t data0, data1, clock; + unsigned int ieee_channel, ath_channel; + u32 data0, data1, clock; struct ath5k_athchan_2ghz ath_channel_2ghz; /* @@ -5132,7 +5118,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) /* Map 2GHz channel to 5GHz Atheros channel ID */ if (ath5k_hw_rf5111_chan2athchan(ieee_channel, &ath_channel_2ghz) == false) - return (false); + return false; ath_channel = ath_channel_2ghz.a2_athchan; data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) @@ -5152,7 +5138,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); - return (true); + return true; } /* @@ -5161,8 +5147,8 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) bool ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int32_t data, data0, data1, data2; - u_int16_t c; + u32 data, data0, data1, data2; + u16 c; data = data0 = data1 = data2 = 0; c = channel->freq; @@ -5178,7 +5164,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) data0 = ((2 * (c - 672)) - 3040) / 10; data1 = 0; } else - return (false); + return false; data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); } else { @@ -5192,7 +5178,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); data2 = ath5k_hw_bitswap(1, 2); } else - return (false); + return false; } data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; @@ -5200,7 +5186,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x27, data & 0xff); AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); - return (true); + return true; } /* @@ -5216,7 +5202,7 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ else ret = ath5k_hw_rf511x_calibrate(hal,channel); - return (ret); + return ret; } /* * Perform a PHY calibration on RF5110 @@ -5225,8 +5211,8 @@ bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { bool ret = true; - u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor; - u_int i; + u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; + unsigned int i; #define AGC_DISABLE { \ AR5K_REG_ENABLE_BITS(AR5K_PHY_AGC, \ @@ -5264,7 +5250,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AGC_ENABLE; if (ret == false) - return (ret); + return ret; /* * Calibrate the radio chip @@ -5319,7 +5305,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat); if (ret == false) - return (false); + return false; /* * Enable noise floor calibration and wait until completion @@ -5331,7 +5317,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return (false); + return false; } /* Wait until the noise floor is calibrated */ @@ -5350,7 +5336,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return (false); + return false; } @@ -5364,7 +5350,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) #undef AGC_ENABLE #undef AGC_DISABLE - return (true); + return true; } /* @@ -5373,8 +5359,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int32_t i_pwr, q_pwr; - int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; + u32 i_pwr, q_pwr; + s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; AR5K_TRACE; if (hal->ah_calibration == false || @@ -5393,13 +5379,13 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) goto done; i_coff = ((-iq_corr) / i_coffd) & 0x3f; - q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; + q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; /* Commit new IQ value */ AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | - ((u_int32_t)q_coff) | - ((u_int32_t)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + ((u32)q_coff) | + ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); done: /* Start noise floor calibration */ @@ -5415,7 +5401,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } - return (true); + return true; } bool @@ -5424,21 +5410,19 @@ ath5k_hw_phy_disable(struct ath_hal *hal) AR5K_TRACE; /*Just a try M.F.*/ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); - return (true); + return true; } void /*TODO:Boundary check*/ -ath5k_hw_set_def_antenna(struct ath_hal *hal, u_int ant) +ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant) { AR5K_TRACE; /*Just a try M.F.*/ if (hal->ah_version != AR5K_AR5210) AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant); - - return; } -u_int +unsigned int ath5k_hw_get_def_antenna(struct ath_hal *hal) { AR5K_TRACE; @@ -5446,26 +5430,26 @@ ath5k_hw_get_def_antenna(struct ath_hal *hal) if (hal->ah_version != AR5K_AR5210) return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); - return (false); /*XXX: What do we return for 5210 ?*/ + return false; /*XXX: What do we return for 5210 ?*/ } -u_int -ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, - u_int32_t first, u_int32_t col, bool set) +unsigned int +ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, + u32 first, u32 col, bool set) { - u_int32_t mask, entry, last, data, shift, position; - int32_t left; + u32 mask, entry, last, data, shift, position; + s32 left; int i; data = 0; if (rf == NULL) /* should not happen */ - return (0); + return 0; if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { AR5K_PRINTF("invalid values at offset %u\n", offset); - return (0); + return 0; } entry = ((first - 1) / 8) + offset; @@ -5494,23 +5478,23 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit data = set == true ? 1 : ath5k_hw_bitswap(data, bits); - return (data); + return data; } -u_int32_t +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) { - u_int32_t mix, step; - u_int32_t *rf; + u32 mix, step; + u32 *rf; if (hal->ah_rf_banks == NULL) - return (0); + return 0; rf = hal->ah_rf_banks; hal->ah_gain.g_f_corr = 0; if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1) - return (0); + return 0; step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false); mix = hal->ah_gain.g_step->gos_param[0]; @@ -5530,17 +5514,17 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) break; } - return (hal->ah_gain.g_f_corr); + return hal->ah_gain.g_f_corr; } bool ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) { - u_int32_t step, mix, level[4]; - u_int32_t *rf; + u32 step, mix, level[4]; + u32 *rf; if (hal->ah_rf_banks == NULL) - return (0); + return 0; rf = hal->ah_rf_banks; @@ -5575,7 +5559,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) hal->ah_gain.g_current <= level[3])); } -int32_t +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) { int ret = 0; @@ -5588,7 +5572,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { if (hal->ah_gain.g_step_idx == 0) - return (-1); + return -1; for (hal->ah_gain.g_target = hal->ah_gain.g_current; hal->ah_gain.g_target >= hal->ah_gain.g_high && hal->ah_gain.g_step_idx > 0; @@ -5605,7 +5589,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) - return (-2); + return -2; for (hal->ah_gain.g_target = hal->ah_gain.g_current; hal->ah_gain.g_target <= hal->ah_gain.g_low && hal->ah_gain.g_step_idx < (go->go_steps_count - 1); @@ -5629,14 +5613,14 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) hal->ah_gain.g_target); #endif - return (ret); + return ret; } /* * Initialize RF */ bool -ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) +ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) { ath5k_rfgain_t *func = NULL; bool ret; @@ -5651,14 +5635,14 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) hal->ah_rf_banks_size = sizeof(rf5112_rf); func = ath5k_hw_rf5112_rfregs; } else - return (false); + return false; if (hal->ah_rf_banks == NULL) { /* XXX do extra checks? */ if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, GFP_KERNEL)) == NULL) { AR5K_PRINT("out of memory\n"); - return (false); + return false; } } @@ -5667,20 +5651,20 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) if (ret == true) hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; - return (ret); + return ret; } /* * Initialize RF5111 */ bool -ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) +ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - const u_int rf_size = AR5K_ELEMENTS(rf5111_rf); - u_int32_t *rf; + const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); + u32 *rf; int i, obdb = -1, bank = -1; - u_int32_t ee_mode; + u32 ee_mode; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5691,7 +5675,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (rf5111_rf[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (false); + return false; } if (bank != rf5111_rf[i].rf_bank) { @@ -5711,11 +5695,11 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], ee->ee_ob[ee_mode][obdb], 3, 119, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], ee->ee_ob[ee_mode][obdb], 3, 122, 0, true)) - return (false); + return false; obdb = 1; } else { @@ -5728,36 +5712,36 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_84, 1, 51, 3, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_90, 1, 45, 3, true)) - return (false); + return false; } if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], !ee->ee_xpd[ee_mode], 1, 95, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_x_gain[ee_mode], 4, 96, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 29, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_xpd[ee_mode], 1, 4, 0, true)) - return (false); + return false; /* Write RF values */ for (i = 0; i < rf_size; i++) { @@ -5765,20 +5749,20 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]); } - return (true); + return true; } /* * Initialize RF5112 */ bool -ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) +ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int rf_size; - u_int32_t *rf; + unsigned int rf_size; + u32 *rf; int i, obdb = -1, bank = -1; - u_int32_t ee_mode; + u32 ee_mode; const struct ath5k_ini_rf *rf_ini; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5787,18 +5771,17 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { rf_ini = rf5112a_rf; - rf_size = AR5K_ELEMENTS(rf5112a_rf); + rf_size = ARRAY_SIZE(rf5112a_rf); } else { rf_ini = rf5112_rf; - rf_size = AR5K_ELEMENTS(rf5112_rf); + rf_size = ARRAY_SIZE(rf5112_rf); } /* Copy values to modify them */ for (i = 0; i < rf_size; i++) { - if (rf_ini[i].rf_bank >= - AR5K_RF5112_INI_RF_MAX_BANKS) { + if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (false); + return false; } if (bank != rf_ini[i].rf_bank) { @@ -5818,11 +5801,11 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 287, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 290, 0, true)) - return (false); + return false; } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; @@ -5833,11 +5816,11 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 282, 0, true)) - return (false); + return false; } #ifdef notyet @@ -5849,17 +5832,17 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_xpd[ee_mode], 1, 302, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 14, 0, true)) - return (false); + return false; /* Write RF values */ for (i = 0; i < rf_size; i++) AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); - return (true); + return true; } /* @@ -5868,13 +5851,13 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int * doesn't ar5k_rfregs work ? */ void -ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int freq, - u_int ee_mode) +ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, + unsigned int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - struct ath5k_ar5211_ini_rf rf[AR5K_ELEMENTS(ar5211_rf)]; - u_int32_t ob, db, obdb, xpds, xpdp, x_gain; - u_int i; + struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)]; + u32 ob, db, obdb, xpds, xpdp, x_gain; + unsigned int i; memcpy(rf, ar5211_rf, sizeof(rf)); obdb = 0; @@ -5917,9 +5900,9 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | ((xpds << 3) & 0x8); - for (i = 0; i < AR5K_ELEMENTS(rf); i++) { + for (i = 0; i < ARRAY_SIZE(rf); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, + AR5K_REG_WRITE((u32)rf[i].rf_register, rf[i].rf_value[freq]); } @@ -5927,7 +5910,7 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int } bool -ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) +ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq) { int i; @@ -5936,7 +5919,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) case AR5K_INI_PHY_5112: break; default: - return (false); + return false; } switch (freq) { @@ -5944,28 +5927,28 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) case AR5K_INI_RFGAIN_5GHZ: break; default: - return (false); + return false; } - for (i = 0; i < AR5K_ELEMENTS(ath5k_rfg); i++) { + for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ath5k_rfg[i].rfg_register, + AR5K_REG_WRITE((u32)ath5k_rfg[i].rfg_register, ath5k_rfg[i].rfg_value[phy][freq]); } - return (true); + return true; } enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal) { - u_int32_t data, type; + u32 data, type; AR5K_TRACE; - if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active) - || (hal->ah_version <= AR5K_AR5211)) - return (AR5K_RFGAIN_INACTIVE); + if (hal->ah_rf_banks == NULL || !hal->ah_gain.g_active || + hal->ah_version <= AR5K_AR5211) + return AR5K_RFGAIN_INACTIVE; if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) goto done; @@ -5973,8 +5956,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) data = AR5K_REG_READ(AR5K_PHY_PAPD_PROBE); if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { - hal->ah_gain.g_current = - data >> AR5K_PHY_PAPD_PROBE_GAINF_S; + hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) @@ -5995,7 +5977,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) } done: - return (hal->ah_rf_gain); + return hal->ah_rf_gain; } /* @@ -6006,9 +5988,9 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) * Initialize the tx power table (not fully implemented) */ void -ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t max_power) +ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_power) { - u_int16_t txpower, *rates; + u16 txpower, *rates; int i, min, max, n; rates = hal->ah_txpower.txp_rates; @@ -6028,7 +6010,7 @@ ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t hal->ah_txpower.txp_ofdm = rates[0]; /* Calculate the power table */ - n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac); + n = ARRAY_SIZE(hal->ah_txpower.txp_pcdac); min = AR5K_EEPROM_PCDAC_START; max = AR5K_EEPROM_PCDAC_STOP; for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) @@ -6044,7 +6026,7 @@ ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t * Set transmition power */ bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpower) +ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; int i; @@ -6052,7 +6034,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow AR5K_TRACE; if (txpower > AR5K_TUNE_MAX_TXPOWER) { AR5K_PRINTF("invalid tx power: %u\n", txpower); - return (false); + return false; } /* Reset TX power values */ @@ -6098,18 +6080,18 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow AR5K_TUNE_MAX_TXPOWER); } - return (true); + return true; } bool -ath5k_hw_set_txpower_limit(struct ath_hal *hal, u_int power) +ath5k_hw_set_txpower_limit(struct ath_hal *hal, unsigned int power) { /*Just a try M.F.*/ struct ath5k_channel *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n",power); - return (ath5k_hw_txpower(hal, channel, power)); + return ath5k_hw_txpower(hal, channel, power); } @@ -6226,15 +6208,14 @@ ath5k_hw_dump_state(struct ath_hal *hal) bool /*what about VEOL cap ?*/ ath5k_hw_has_veol(struct ath_hal *hal) { - return (true); + return true; } void /*Unimplemented*/ -ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) +ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u32 *i) { AR5K_TRACE; /* XXX */ - return; } void /*Added struct ath5k_node_stats argument*/ @@ -6246,20 +6227,20 @@ ath5k_hw_set_rx_signal(struct ath_hal *hal, const struct ath5k_node_stats *stats bool /*Added arguments*/ ath5k_hw_get_diag_state(struct ath_hal *hal, int request, -const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) + const void *args, u32 argsize, void **result, u32 *resultsize) { AR5K_TRACE; /* * We'll ignore this right now. This seems to be some kind of an obscure * debugging interface for the binary-only HAL. */ - return (false); + return false; } bool /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ ath5k_hw_detect_card_present(struct ath_hal *hal) { - u_int16_t magic; + u16 magic; AR5K_TRACE; /* * Checking the EEPROM's magic value could be an indication @@ -6267,14 +6248,14 @@ ath5k_hw_detect_card_present(struct ath_hal *hal) * way to do this. */ if (ath5k_hw_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (false); + return false; - return (magic == AR5K_EEPROM_MAGIC_VALUE ? true : false); + return magic == AR5K_EEPROM_MAGIC_VALUE ? true : false; } -enum ath5k_status -ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, - u_int32_t capability, u_int32_t *result) +enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, + enum ath5k_capability_type cap_type, + u32 capability, u32 *result) { AR5K_TRACE; @@ -6325,7 +6306,7 @@ ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type } no: - return (AR5K_EINVAL); + return AR5K_EINVAL; yes: return AR5K_OK; @@ -6334,14 +6315,14 @@ ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type bool ath5k_hw_set_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, - u_int32_t capability, u_int32_t setting, + u32 capability, u32 setting, enum ath5k_status *status) { AR5K_TRACE; if (status) *status = AR5K_OK; - return (false); + return false; } bool @@ -6351,7 +6332,7 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) if (hal->ah_version == AR5K_AR5210) return(true); - return (false); + return false; } bool @@ -6361,22 +6342,22 @@ ath5k_hw_init_pspoll(struct ath_hal *hal) /* * Not used */ - return (false); + return false; } bool -ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, - u_int16_t assoc_id) +ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, + u16 assoc_id) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); - return (true); + return true; } - return (false); + return false; } bool @@ -6387,20 +6368,20 @@ ath5k_hw_disable_pspoll(struct ath_hal *hal) AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); - return (true); + return true; } - return (false); + return false; } const char * /*O.K. - TODO:Get rid of this*/ -ath5k_printver(enum ath5k_srev_type type, u_int32_t val) +ath5k_printver(enum ath5k_srev_type type, u32 val) { struct ath5k_srev_name names[] = AR5K_SREV_NAME; const char *name = "xxxx"; int i; - for (i = 0; i < AR5K_ELEMENTS(names); i++) { + for (i = 0; i < ARRAY_SIZE(names); i++) { if (type == AR5K_VERSION_DEV) { if (names[i].sr_type == type && names[i].sr_val == val) { @@ -6418,7 +6399,7 @@ ath5k_printver(enum ath5k_srev_type type, u_int32_t val) } } - return (name); + return name; } void /*O.K. - TODO: Implement this in if_ath.c (ath_intr)*/ @@ -6484,7 +6465,7 @@ ath5k_hw_fill(struct ath_hal *hal) hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc; hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; - } else if (hal->ah_version != AR5K_AR5212) { + } else { hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc;