commit b1836b874d1fa17b9cdfe470122b5e2b2f9749bf Author: Jiri Slaby Date: Mon Jun 18 09:25:54 2007 +0200 add compat defs diff --git a/ath/if_ath.c b/ath/if_ath.c index ed6de19..81f0ca1 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -362,7 +362,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Attach the hal */ - ah = _ath_hal_attach(devid, sc, sc->sc_iobase, &status); + ah = ath_hal_attach(devid, sc, sc->sc_iobase, &status); if (ah == NULL) { printk(KERN_ERR "%s: unable to attach hardware: '%s' (HAL status %u)\n", __func__, hal_status_desc[status], status); diff --git a/openhal/Makefile b/openhal/Makefile index 9007072..38bb7b8 100644 --- a/openhal/Makefile +++ b/openhal/Makefile @@ -1,2 +1,4 @@ obj-m += ath_hal.o ath_hal-objs := ah_osdep.o ath5k_hw.o ieee80211_regdomain.o + +EXTRA_CFLAGS+=-DCONFIG_OPENHAL_COMPAT diff --git a/openhal/ah_osdep.c b/openhal/ah_osdep.c index 9f1a7c4..f76c0a2 100644 --- a/openhal/ah_osdep.c +++ b/openhal/ah_osdep.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2006-2007 Nick Kossifidis + * Copyright (c) 2007 Jiri Slaby * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -15,7 +16,7 @@ static char dev_info[] = "ath_hal"; -struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, +struct ath_hal *ath_hal_attach(u16 devid, void *sc, void __iomem *h, enum ath5k_status *s) { struct ath_hal *ah = ath5k_hw_init(devid, sc, h, s); @@ -28,7 +29,7 @@ struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, return ah; } -EXPORT_SYMBOL(_ath_hal_attach); +EXPORT_SYMBOL(ath_hal_attach); void ath_hal_detach(struct ath_hal *ah) { diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 25949f0..07a146e 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -891,8 +891,8 @@ struct ath5k_capabilities { * Active regulation domain settings */ struct { - ieee80211_regdomain_t reg_current; - ieee80211_regdomain_t reg_hw; + enum ieee80211_regdomain reg_current; + enum ieee80211_regdomain reg_hw; } cap_regdomain; /* @@ -1172,8 +1172,8 @@ bool ath_hal_init_channels(struct ath_hal *, struct ath5k_channel *, bool, bool); const char *ath5k_printver(enum ath5k_srev_type, u32); void ath5k_radar_alert(struct ath_hal *); -ieee80211_regdomain_t ath5k_regdomain_to_ieee(u16); -u16 ath5k_regdomain_from_ieee(ieee80211_regdomain_t); +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16); +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain); u16 ath5k_get_regdomain(struct ath_hal *); u32 ath5k_bitswap(u32, u_int); inline u_int ath5k_clocktoh(u_int, bool); @@ -1184,7 +1184,7 @@ bool ath5k_register_timeout(struct ath_hal *, u32, u32, int ath5k_eeprom_init(struct ath_hal *); int ath5k_eeprom_read_mac(struct ath_hal *, u8 *); bool ath5k_eeprom_regulation_domain(struct ath_hal *, bool, - ieee80211_regdomain_t *); + enum ieee80211_regdomain *); int ath5k_eeprom_read_ants(struct ath_hal *, u32 *, u_int); int ath5k_eeprom_read_modes(struct ath_hal *, u32 *, u_int); u16 ath5k_eeprom_bin2freq(struct ath_hal *, u16, u_int); @@ -1216,6 +1216,71 @@ void ath5k_txpower_table(struct ath_hal *, struct ath5k_channel *, s16); /*added*/ extern u_int ath_hal_getwirelessmodes(struct ath_hal *, enum ieee80211_countrycode); void ath_hal_detach(struct ath_hal *ah); -struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, +struct ath_hal *ath_hal_attach(u16 devid, void *sc, void __iomem *h, enum ath5k_status *s); + +/* COMPAT stuff */ + +#ifdef CONFIG_OPENHAL_COMPAT +typedef u32 ieee80211_regdomain_t; + +typedef struct ath5k_node_stats AR5K_NODE_STATS; +typedef struct ath5k_rate_table AR5K_RATE_TABLE; +typedef struct ath5k_channel AR5K_CHANNEL; +typedef struct ath5k_keyval AR5K_KEYVAL; +typedef struct ath5k_txq_info AR5K_TXQ_INFO; + +typedef enum ieee80211_if_types AR5K_OPMODE; +typedef enum ath5k_int AR5K_INT; +typedef enum ath5k_status AR5K_STATUS; +typedef enum ath5k_pkt_type AR5K_PKT_TYPE; + +typedef void *AR5K_SOFTC; +typedef int AR5K_BUS_TAG; +typedef __iomem void *AR5K_BUS_HANDLE; +typedef u_int32_t AR5K_BUS_ADDR; + +typedef bool AR5K_BOOL; + +#define TRUE true +#define FALSE false + +#define AR5K_M_STA IEEE80211_IF_TYPE_STA +#define AR5K_M_IBSS IEEE80211_IF_TYPE_IBSS +#define AR5K_M_HOSTAP IEEE80211_IF_TYPE_AP +#define AR5K_M_MONITOR IEEE80211_IF_TYPE_MNTR + +#define PCI_PRODUCT_ATHEROS_AR5210_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT +#define PCI_PRODUCT_ATHEROS_AR5210 PCI_DEVICE_ID_ATHEROS_AR5210 +#define PCI_PRODUCT_ATHEROS_AR5210_AP PCI_DEVICE_ID_ATHEROS_AR5210_AP +#define PCI_PRODUCT_ATHEROS_AR5212_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM +#define PCI_PRODUCT_ATHEROS_AR5211 PCI_DEVICE_ID_ATHEROS_AR5211 +#define PCI_PRODUCT_ATHEROS_AR5211_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT +#define PCI_PRODUCT_ATHEROS_AR5311 PCI_DEVICE_ID_ATHEROS_AR5311 +#define PCI_PRODUCT_ATHEROS_AR5211_LEGACY PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY +#define PCI_PRODUCT_ATHEROS_AR5211_FPGA11B PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B +#define PCI_PRODUCT_ATHEROS_AR5212_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT +#define PCI_PRODUCT_ATHEROS_AR5212 PCI_DEVICE_ID_ATHEROS_AR5212 +#define PCI_PRODUCT_ATHEROS_AR5212_FPGA PCI_DEVICE_ID_ATHEROS_AR5212_FPGA +#define PCI_PRODUCT_ATHEROS_AR5212_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM +#define PCI_PRODUCT_ATHEROS_AR5212_REV2 PCI_DEVICE_ID_ATHEROS_AR5212_REV2 +#define PCI_PRODUCT_ATHEROS_AR5212_REV7 PCI_DEVICE_ID_ATHEROS_AR5212_REV7 +#define PCI_PRODUCT_ATHEROS_AR5212_REV8 PCI_DEVICE_ID_ATHEROS_AR5212_REV8 +#define PCI_PRODUCT_ATHEROS_AR5212_0014 PCI_DEVICE_ID_ATHEROS_AR5212_0014 +#define PCI_PRODUCT_ATHEROS_AR5212_0015 PCI_DEVICE_ID_ATHEROS_AR5212_0015 +#define PCI_PRODUCT_ATHEROS_AR5212_0016 PCI_DEVICE_ID_ATHEROS_AR5212_0016 +#define PCI_PRODUCT_ATHEROS_AR5212_0017 PCI_DEVICE_ID_ATHEROS_AR5212_0017 +#define PCI_PRODUCT_ATHEROS_AR5212_0018 PCI_DEVICE_ID_ATHEROS_AR5212_0018 +#define PCI_PRODUCT_ATHEROS_AR5212_0019 PCI_DEVICE_ID_ATHEROS_AR5212_0019 +#define PCI_PRODUCT_ATHEROS_AR2413 PCI_DEVICE_ID_ATHEROS_AR2413 +#define PCI_PRODUCT_ATHEROS_AR5413 PCI_DEVICE_ID_ATHEROS_AR5413 +#define PCI_PRODUCT_ATHEROS_AR5424 PCI_DEVICE_ID_ATHEROS_AR5424 + +static inline struct ath_hal *_ath_hal_attach(u16 devid, AR5K_SOFTC sc, + AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void *s) +{ + return ath_hal_attach(devid, sc, h, s); +} +#endif + #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 3fd4cc2..4a1e44c 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -2524,7 +2524,7 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) */ bool ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, - ieee80211_regdomain_t *regdomain) + enum ieee80211_regdomain *regdomain) { u16 ee_regdomain; @@ -2557,7 +2557,7 @@ bool ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, enum ath5k_status *status) { - ieee80211_regdomain_t ieee_regdomain; + enum ieee80211_regdomain ieee_regdomain; ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); @@ -4921,7 +4921,7 @@ EXPORT_SYMBOL(ath_hal_init_channels); */ u16 -ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) +ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) { u32 regdomain = (u32)ieee; @@ -4930,17 +4930,17 @@ ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) * or not supported by the net80211 regulation code. */ if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) return (u16)AR5K_TUNE_REGDOMAIN; /* It is supported, just return the value */ return regdomain; } -ieee80211_regdomain_t +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) { - ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; + enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; return ieee; } @@ -4949,7 +4949,7 @@ u16 ath5k_get_regdomain(struct ath_hal *hal) { u16 regdomain; - ieee80211_regdomain_t ieee_regdomain; + enum ieee80211_regdomain ieee_regdomain; #ifdef COUNTRYCODE u16 code; #endif diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 39e07fa..1c68e8f 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -19,8 +19,6 @@ #ifndef _NET80211_IEEE80211_REGDOMAIN_H_ #define _NET80211_IEEE80211_REGDOMAIN_H_ -typedef u32 ieee80211_regdomain_t; - enum ieee80211_regdomain { DMN_DEFAULT = 0x00, DMN_NULL_WORLD = 0x03,