commit 1ee6c2c27fab905aa282016b1c0451d90eb4d15d Author: Jiri Slaby Date: Tue Aug 7 08:12:34 2007 +0200 remove trailing whitespace diff --git a/ath5k.h b/ath5k.h index fd85a9c..b57e16b 100644 --- a/ath5k.h +++ b/ath5k.h @@ -576,7 +576,7 @@ struct ath5k_athchan_2ghz { struct ath5k_rate { u8 valid; /* Valid for rate control */ u32 modulation; - u16 rate_kbps; + u16 rate_kbps; u8 rate_code; /* Rate mapping for h/w descriptors */ u8 dot11_rate; u8 control_rate; @@ -585,7 +585,7 @@ struct ath5k_rate { }; struct ath5k_rate_table { - u16 rate_count; + u16 rate_count; u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ struct ath5k_rate rates[AR5K_MAX_RATES]; }; @@ -742,7 +742,7 @@ enum ath5k_int { | AR5K_INT_SWBA | AR5K_INT_BMISS | AR5K_INT_GPIO, - AR5K_INT_NOCARD = 0xffffffff /*Declare that the card + AR5K_INT_NOCARD = 0xffffffff /*Declare that the card has been removed*/ }; diff --git a/ath5k_base.c b/ath5k_base.c index 8a14496..9af70e1 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -538,7 +538,7 @@ static void ath_beacon_send(struct ath_softc *sc) struct ath_hw *ah = sc->ah; DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__); - + if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA || sc->opmode == IEEE80211_IF_TYPE_MNTR)) { printk(KERN_WARNING "ath: bf=%p bf_skb=%p\n", bf, @@ -651,7 +651,7 @@ static void ath_beacon_config(struct ath_softc *sc) /* current TSF converted to TU */ tsf = ath5k_hw_get_tsf64(ah); tsftu = TSF_TO_TU((u32)(tsf >> 32), (u32)tsf); - + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: intval %u hw tsftu %u\n", __func__, intval, tsftu); @@ -669,10 +669,10 @@ static void ath_beacon_config(struct ath_softc *sc) * can be too short for ibss merges. */ nexttbtt = tsftu + 2 * intval; - + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u " "intval %u\n", __func__, nexttbtt, intval); - + /* * In IBSS mode enable the beacon timers but only * enable SWBA interrupts if we need to manually diff --git a/ath5k_hw.c b/ath5k_hw.c index 85f5a9f..ba76103 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -402,15 +402,15 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, hal->ah_phy = AR5K_PHY(0); - /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a - * temporary variable for setting our BSSID. Right bellow we update + /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a + * temporary variable for setting our BSSID. Right bellow we update * it with ath5k_hw_get_lladdr() */ memset(mac, 0xff, ETH_ALEN); ath5k_hw_set_associd(hal, mac, 0); ath5k_hw_get_lladdr(hal, mac); ath5k_hw_set_opmode(hal); - + #ifdef AR5K_DEBUG ath5k_hw_dump_state(hal); #endif @@ -487,7 +487,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) /* * Get channel mode flags */ - + if (hal->ah_radio >= AR5K_RF5112) { mode = AR5K_PHY_MODE_RAD_RF5112; clock = AR5K_PHY_PLL_RF5112; @@ -879,7 +879,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5210_ini), ar5210_ini, change_channel); } - + /* * 5211/5212 Specific */ @@ -921,7 +921,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (AR5K_SET_SHORT_PREAMBLE << 2)); } } - + } else { /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ @@ -1095,7 +1095,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*PISR/SISR Not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR); - /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so + /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so * direct write using ath5k_hw_reg_write seems wrong. Test with: * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); @@ -1173,7 +1173,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) noise_floor = AR5K_PHY_NF_AVAL(noise_floor); - + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) break; } @@ -1183,7 +1183,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, channel->freq); return -EIO; } - + hal->ah_calibration = false; if (!(channel->val & CHANNEL_B)) { @@ -1243,7 +1243,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_SPENDING); } - /* + /* * Disable beacons and reset the register */ AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE | @@ -1465,7 +1465,7 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) break; case AR5K_TX_QUEUE_BEACON: tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BSR); break; case AR5K_TX_QUEUE_CAB: @@ -1554,7 +1554,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) /* * Get the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) - */ + */ u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) { u16 tx_reg; @@ -1614,7 +1614,7 @@ int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) } } else { /* - * Set the transmit queue descriptor pointer for + * Set the transmit queue descriptor pointer for * the selected queue on QCU for 5211+ * (this won't work if the queue is still active) */ @@ -1740,8 +1740,8 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) *interrupt_mask |= AR5K_INT_BNR; } - /* - * XXX: BMISS interrupts may occur after association. + /* + * XXX: BMISS interrupts may occur after association. * I found this on 5210 code but it needs testing */ #if 0 @@ -2427,7 +2427,7 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) if (AR5K_EEPROM_HDR_11A(ee_header)) { hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ hal->ah_capabilities.cap_range.range_5ghz_max = 6100; - + /* Set supported modes */ set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); set_bit(MODE_ATHEROS_TURBO, @@ -2436,12 +2436,12 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) set_bit(MODE_ATHEROS_TURBOG, hal->ah_capabilities.cap_mode); } - + /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ hal->ah_capabilities.cap_range.range_2ghz_max = 2732; - + if (AR5K_EEPROM_HDR_11B(ee_header)) set_bit(MODE_IEEE80211B, hal->ah_capabilities.cap_mode); @@ -2610,10 +2610,10 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) low_id = AR5K_LOW_ID(mask); high_id = AR5K_HIGH_ID(mask); - ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); - ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); - return true; + return true; } return false; @@ -2849,7 +2849,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * { u32 cfp_period, next_cfp, dtim, interval, next_beacon; - /* + /* * TODO: should be changed through *state * review struct ath5k_beacon_state struct * @@ -2873,8 +2873,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * PCF support? */ if (state->bs_cfp_period > 0) { - /* - * Enable PCF mode and set the CFP + /* + * Enable PCF mode and set the CFP * (Contention Free Period) and timer registers */ cfp_period = state->bs_cfp_period * state->bs_dtim_period * @@ -2944,7 +2944,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * if (interval > dtim) return; - + next_beacon = interval == dtim ? state->bs_next_dtim : state->bs_next_beacon; @@ -3203,7 +3203,7 @@ int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) /* Invalid entry (key table overflow) */ AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - /* MAC may be NULL if it's a broadcast key. In this case no need to + /* MAC may be NULL if it's a broadcast key. In this case no need to * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ if (unlikely(mac == NULL)) { low_id = 0xffffffff; @@ -3255,7 +3255,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, switch (queue_type) { case AR5K_TX_QUEUE_DATA: for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != + hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; queue++) { if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) @@ -3279,7 +3279,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, break; default: return -EINVAL; - } + } } /* @@ -3313,13 +3313,13 @@ int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) return -EIO; memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); /*XXX: Is this supported on 5210 ?*/ - if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && + if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) @@ -3362,7 +3362,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) u32 cw_min, cw_max, retry_lg, retry_sh; struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; - struct ath5k_ar5210_ini_mode ar5210_mode[] = + struct ath5k_ar5210_ini_mode ar5210_mode[] = AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs); AR5K_TRACE; @@ -3533,7 +3533,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) ath5k_hw_reg_write(hal, ((AR5K_TUNE_BEACON_INTERVAL - - (AR5K_TUNE_SW_BEACON_RESP - + (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | AR5K_QCU_RDYTIMECFG_ENABLE, @@ -3572,7 +3572,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); - } + } return 0; } @@ -4051,10 +4051,10 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0; /* - *Clear ds_hw + *Clear ds_hw * If we don't clean the status descriptor, - * while scanning we get too many results, - * most of them virtual, after some secs + * while scanning we get too many results, + * most of them virtual, after some secs * of scanning system hangs. M.F. */ memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); @@ -4382,7 +4382,7 @@ bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags) if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) return true; - } else if (flags & CHANNEL_5GHZ) + } else if (flags & CHANNEL_5GHZ) if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) return true; @@ -4466,7 +4466,7 @@ static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, { int channel; - /* Cast this value to catch negative channel numbers (>= -19) */ + /* Cast this value to catch negative channel numbers (>= -19) */ channel = (int)ieee; /* @@ -4735,7 +4735,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal, if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) noise_floor = AR5K_PHY_NF_AVAL(noise_floor); - + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) break; } @@ -5261,7 +5261,7 @@ static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal, } /* - * Initialize 5211 RF + * Initialize 5211 RF * TODO: is this needed ? i mean 5211 has a 5111 RF * doesn't ar5k_rfregs work ? */ @@ -5459,7 +5459,7 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, /* Initialize TX power table */ ath5k_txpower_table(hal, channel, txpower); - /* + /* * Write TX power values */ for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { @@ -5621,7 +5621,7 @@ int ath5k_hw_get_capability(struct ath_hw *hal, AR5K_TRACE; switch (cap_type) { - case AR5K_CAP_NUM_TXQUEUES: + case AR5K_CAP_NUM_TXQUEUES: if (result) { if (hal->ah_version == AR5K_AR5210) *result = AR5K_NUM_TX_QUEUES_NOQCU; @@ -5650,15 +5650,14 @@ int ath5k_hw_get_capability(struct ath_hw *hal, goto yes; else goto no; - default: + default: goto no; } - no: +no: return -EINVAL; - yes: +yes: return 0; - } bool diff --git a/ath5k_hw.h b/ath5k_hw.h index cd4fbad..2dfcf92 100644 --- a/ath5k_hw.h +++ b/ath5k_hw.h @@ -469,8 +469,8 @@ struct ath5k_hw_tx_status { /* Some registers can hold multiple values of interest. For this * reason when we want to write to these registers we must first - * retrieve the values which we do not want to clear (lets call this - * old_data) and then set the register with this and our new_value: + * retrieve the values which we do not want to clear (lets call this + * old_data) and then set the register with this and our new_value: * ( old_data | new_value) */ #define AR5K_REG_WRITE_BITS(hal, _reg, _flags, _val) \ ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & ~(_flags)) | \ @@ -827,7 +827,7 @@ struct ath5k_ini_rf { { 7, 0x98c4, \ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } - + /* RF5112A mode-specific init registers */ #define AR5K_RF5112A_INI_RF { \ { 1, 0x98d4, \ diff --git a/ath5k_reg.h b/ath5k_reg.h index ec79bb7..59547d1 100644 --- a/ath5k_reg.h +++ b/ath5k_reg.h @@ -39,9 +39,9 @@ * maintained by Reyk Floeter * * I tried to document those registers by looking at ar5k code, some - * 802.11 (802.11e mostly) papers and by reading various public available + * 802.11 (802.11e mostly) papers and by reading various public available * Atheros presentations and papers like these: - * + * * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf * @@ -70,7 +70,7 @@ #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ #define AR5K_CR_RXD 0x00000020 /* RX Disable */ -#define AR5K_CR_SWI 0x00000040 +#define AR5K_CR_SWI 0x00000040 /* * RX Descriptor Pointer register @@ -95,7 +95,7 @@ #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ #define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ -#define AR5K_CFG_PCI_THRES_S 17 +#define AR5K_CFG_PCI_THRES_S 17 /* * Interrupt enable register @@ -119,7 +119,7 @@ #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ -#define AR5K_BCR_BCGET 0x00000010 +#define AR5K_BCR_BCGET 0x00000010 /* * First RTS duration register [5211] @@ -135,7 +135,7 @@ #define AR5K_RTSD0_18_S 24 -/* +/* * 0x002c is Beacon Status Register on 5210 * and second RTS duration register on 5211 */ @@ -145,7 +145,7 @@ * * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning - * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). + * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. @@ -160,7 +160,7 @@ #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ -#define AR5K_BSR_SWBA_CNT 0x00ff0000 +#define AR5K_BSR_SWBA_CNT 0x00ff0000 /* * Second RTS duration register [5211] @@ -191,7 +191,7 @@ #define AR5K_TXCFG_TXFULL_128B 0x00000020 #define AR5K_TXCFG_TXFULL_192B 0x00000030 #define AR5K_TXCFG_TXFULL_256B 0x00000040 -#define AR5K_TXCFG_TXCONT_EN 0x00000080 +#define AR5K_TXCFG_TXCONT_EN 0x00000080 #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ #define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ @@ -219,10 +219,10 @@ * MIB control register */ #define AR5K_MIBC 0x0040 /* Register Address */ -#define AR5K_MIBC_COW 0x00000001 +#define AR5K_MIBC_COW 0x00000001 #define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ #define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ -#define AR5K_MIBC_MCS 0x00000008 +#define AR5K_MIBC_MCS 0x00000008 /* * Timeout prescale register @@ -260,13 +260,13 @@ * Misc settings register */ #define AR5K_MISC 0x0058 /* Register Address */ -#define AR5K_MISC_DMA_OBS_M 0x000001e0 +#define AR5K_MISC_DMA_OBS_M 0x000001e0 #define AR5K_MISC_DMA_OBS_S 5 -#define AR5K_MISC_MISC_OBS_M 0x00000e00 +#define AR5K_MISC_MISC_OBS_M 0x00000e00 #define AR5K_MISC_MISC_OBS_S 9 -#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 +#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 #define AR5K_MISC_MAC_OBS_LSB_S 12 -#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 +#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 #define AR5K_MISC_MAC_OBS_MSB_S 15 #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ @@ -303,9 +303,9 @@ #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ #define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ -#define AR5K_ISR_RXKCM 0x00008000 +#define AR5K_ISR_RXKCM 0x00008000 #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ -#define AR5K_ISR_BRSSI 0x00020000 +#define AR5K_ISR_BRSSI 0x00020000 #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ @@ -323,7 +323,7 @@ /* * Secondary status registers [5211+] (0 - 4) * - * I guess from the names that these give the status for each + * I guess from the names that these give the status for each * queue, that's why only masks are defined here, haven't got * any info about them (couldn't find them anywhere in ar5k code). */ @@ -337,9 +337,9 @@ #define AR5K_SISR2 0x008c /* Register Address [5211+] */ #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ -#define AR5K_SISR2_MCABT 0x00100000 -#define AR5K_SISR2_SSERR 0x00200000 -#define AR5K_SISR2_DPERR 0x00400000 +#define AR5K_SISR2_MCABT 0x00100000 +#define AR5K_SISR2_SSERR 0x00200000 +#define AR5K_SISR2_DPERR 0x00400000 #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ @@ -385,11 +385,11 @@ #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ -#define AR5K_IMR_SWI 0x00002000 +#define AR5K_IMR_SWI 0x00002000 #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ -#define AR5K_IMR_RXKCM 0x00008000 +#define AR5K_IMR_RXKCM 0x00008000 #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ -#define AR5K_IMR_BRSSI 0x00020000 +#define AR5K_IMR_BRSSI 0x00020000 #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ @@ -422,9 +422,9 @@ #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ #define AR5K_SIMR2_QCU_TXURN_S 0 -#define AR5K_SIMR2_MCABT 0x00100000 -#define AR5K_SIMR2_SSERR 0x00200000 -#define AR5K_SIMR2_DPERR 0x00400000 +#define AR5K_SIMR2_MCABT 0x00100000 +#define AR5K_SIMR2_SSERR 0x00200000 +#define AR5K_SIMR2_DPERR 0x00400000 #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ @@ -452,13 +452,13 @@ /* * Decompression configuration registers [5212+] */ -#define AR5K_DCCFG 0x0420 +#define AR5K_DCCFG 0x0420 /* * Compression configuration registers [5212+] */ -#define AR5K_CCFG 0x0600 -#define AR5K_CCFG_CUP 0x0604 +#define AR5K_CCFG 0x0600 +#define AR5K_CCFG_CUP 0x0604 /* * Compression performance counter registers [5212+] @@ -473,11 +473,11 @@ /* * Queue control unit (QCU) registers [5211+] * - * Card has 12 TX Queues but i see that only 0-9 are used (?) - * both in binary HAL (see ah.h) and ar5k. Each queue has it's own - * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) + * Card has 12 TX Queues but i see that only 0-9 are used (?) + * both in binary HAL (see ah.h) and ar5k. Each queue has it's own + * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) * configuration register (0x08c0 - 0x08ec), a ready time configuration - * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - + * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some * global registers, QCU transmit enable/disable and "one shot arm (?)" * set/clear, which contain status for all queues (we shift by 1 for each @@ -493,7 +493,7 @@ #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) - + /* * QCU Transmit descriptor pointer registers */ @@ -595,7 +595,7 @@ /* - * Distributed Coordination Function (DCF) control unit (DCU) + * Distributed Coordination Function (DCF) control unit (DCU) * registers [5211+] * * These registers control the various characteristics of each queue @@ -607,7 +607,7 @@ * a sequence number register (0x1140 - 0x116c). It seems that "global" * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). * We use the same macros here for easier register access. - * + * */ /* @@ -655,15 +655,15 @@ /* * DCU misc registers [5211+] * - * For some of the registers i couldn't find in the code - * (only backoff stuff is there realy) i tried to match the - * names with 802.11e parameters etc, so i guess VIRTCOL here + * For some of the registers i couldn't find in the code + * (only backoff stuff is there realy) i tried to match the + * names with 802.11e parameters etc, so i guess VIRTCOL here * means Virtual Collision and HCFPOLL means Hybrid Coordination * factor Poll (CF- Poll). Arbiter lockout control controls the * behaviour on low priority queues when we have multiple queues * with pending frames. Intra-frame lockout means we wait until * the queue's current frame transmits (with post frame backoff and bursting) - * before we transmit anything else and global lockout means we + * before we transmit anything else and global lockout means we * wait for the whole queue to finish before higher priority queues * can transmit (this is used on beacon and CAB queues). * No lockout means there is no special handling. @@ -684,11 +684,11 @@ #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ -#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 +#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ -#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 +#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) @@ -721,11 +721,11 @@ * DCU global IFS misc registers */ #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ -#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 +#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ -#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 -#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 +#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 +#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* * DCU frame prefetch control register @@ -780,7 +780,7 @@ #define AR5K_SLEEP_CTL_SLE_S 16 #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ -#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 +#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ /* @@ -822,7 +822,7 @@ #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ -#define AR5K_PCICFG_LEDBLINK 0x00700000 +#define AR5K_PCICFG_LEDBLINK 0x00700000 #define AR5K_PCICFG_LEDBLINK_S 20 #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ #define AR5K_PCICFG_LEDSTATE \ @@ -915,7 +915,7 @@ * For more infos check eeprom_* functs and the ar5k.c * file posted in madwifi-devel mailing list. * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 - * + * */ #define AR5K_EEPROM_BASE 0x6000 @@ -1046,7 +1046,7 @@ /* * Protocol Control Unit (PCU) registers */ -/* +/* * Used for checking initial register writes * during channel reset (see reset func) */ @@ -1318,7 +1318,7 @@ #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ #define AR5K_DIAG_SW (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) -#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 +#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ @@ -1332,11 +1332,11 @@ #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 #define AR5K_DIAG_SW_LOOP_BACK (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) -#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 +#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 #define AR5K_DIAG_SW_CORR_FCS (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) -#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 +#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 #define AR5K_DIAG_SW_CHAN_INFO (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) @@ -1349,11 +1349,11 @@ #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ #define AR5K_DIAG_SW_SCRAM_SEED_S 10 #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ -#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 +#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 #define AR5K_DIAG_SW_FRAME_NV0 (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) -#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 +#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 #define AR5K_DIAG_SW_OBSPT_S 18 /* @@ -1625,8 +1625,8 @@ * There is another frame control register for [5111+] * at address 0x9944 (see below) but the 2 first flags * are common here between 5110 frame control register - * and [5111+] turbo mode register, so this also works as - * a "turbo mode register" for 5110. We treat this one as + * and [5111+] turbo mode register, so this also works as + * a "turbo mode register" for 5110. We treat this one as * a frame control register for 5110 below. */ #define AR5K_PHY_TURBO 0x9804 @@ -1746,13 +1746,13 @@ * * We sent such data packets during rf initialization and channel change * through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions. - * + * * The data packets we send during initializadion are inside ath5k_ini_rf * struct (see ath5k_hw.h) and each one is related to an "rf register bank". * We use *rfregs functions to modify them acording to current operation * mode and eeprom values and pass them all together to the chip. * - * It's obvious from the code that 0x989c is the buffer register but + * It's obvious from the code that 0x989c is the buffer register but * for the other special registers that we write to after sending each * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers * for now. It's interesting that they are also used for some other operations. @@ -1866,34 +1866,34 @@ /* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... at power on. */ -#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 +#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 /* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1 after DFS is enabled */ #define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d -/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ +/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ * power out threshold. * 7-bits, standard power range {0..127} in 1/2 dBm units. */ -#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 +#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 #define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24 -/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ +/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ * 6-bits, dBm range {0..63} in dBm units. */ -#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 +#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 #define AR5K_PHY_RADAR_RADARRSSITHR_S 18 -/* Pulse height threshold ........ ......11 1111.... ........ +/* Pulse height threshold ........ ......11 1111.... ........ * 6-bits, dBm range {0..63} in dBm units. */ #define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000 #define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12 -/* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... +/* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... * 6-bits, dBm range {0..63} in dBm units. */ #define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0 #define AR5K_PHY_RADAR_PULSERSSITHR_S 6 -/* Inband threshold ........ ........ ........ ..11111. +/* Inband threshold ........ ........ ........ ..11111. * 5-bits, units unknown {0..31} (? MHz ?) */ #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e #define AR5K_PHY_RADAR_INBANDTHR_S 1 @@ -1963,7 +1963,7 @@ after DFS is enabled */ #define AR5K_PHY_CCKTXCTL 0xa204 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 - + /* * PHY 2GHz gain register [5111+] */ diff --git a/ath5k_regdom.c b/ath5k_regdom.c index 455b923..c345da8 100644 --- a/ath5k_regdom.c +++ b/ath5k_regdom.c @@ -74,7 +74,7 @@ static const struct ath5k_regdommap { enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom dmn, u16 mhz) { unsigned int i; - + for (i = 0; i < ARRAY_SIZE(r_map); i++) { if (r_map[i].dmn == dmn) { if (mhz >= 2000 && mhz <= 3000)