commit 2f875dbedbd9d9cc0f106fd01f70d2332d890a08
Author: Jiri Slaby <ku@bellona.localdomain>
Date:   Wed Aug 8 21:49:23 2007 +0200

    fix some whitespace (checkpatch)

diff --git a/ath5k.h b/ath5k.h
index b679055..2913a0a 100644
--- a/ath5k.h
+++ b/ath5k.h
@@ -195,7 +195,8 @@ struct ath5k_srev_name {
 #define MODULATION_CCK_SP 	IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/
 
 #define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code
-					enables short preamble, see ar5212_reg.h */
+					enables short preamble, see
+					ar5212_reg.h */
 #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP)
 #define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0
 
@@ -227,7 +228,7 @@ struct ath_tx_status {
  * Queue types used to classify tx queues.
  */
 enum ath5k_tx_queue {
-	AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/
+	AR5K_TX_QUEUE_INACTIVE = 0, /* q is unused -- see ath5k_hw_release_tx_queue */
 	AR5K_TX_QUEUE_DATA,	  /*A normal data queue*/
 	AR5K_TX_QUEUE_XR_DATA,	  /*An XR-data queue*/
 	AR5K_TX_QUEUE_BEACON,	  /*The beacon queue*/
@@ -354,9 +355,9 @@ enum ath5k_pkt_type {
 	(AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS))
 
 #define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp)				\
-	AR5K_CCK_PHY_TIME(_sp) +					\
-	((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) +		\
-	AR5K_CCK_SIFS_TIME
+	(AR5K_CCK_PHY_TIME(_sp) +					\
+	((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) +			\
+	AR5K_CCK_SIFS_TIME)
 
 /* OFDM */
 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
@@ -371,8 +372,8 @@ enum ath5k_pkt_type {
 			AR5K_OFDM_NUM_BITS_PER_SYM(_kbps))
 
 #define AR5K_OFDM_TX_TIME(_kbps, _frmlen)				\
-	AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME +			\
-	(AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)
+	(AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME +		\
+	(AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME))
 
 /* TURBO */
 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
@@ -387,8 +388,8 @@ enum ath5k_pkt_type {
 			AR5K_TURBO_NUM_BITS_PER_SYM(_kbps))
 
 #define AR5K_TURBO_TX_TIME(_kbps, _frmlen)				\
-	AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME +		\
-	(AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)
+	(AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME +		\
+	(AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME))
 
 /* eXtendent Range (?)*/
 #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76)
@@ -401,9 +402,9 @@ enum ath5k_pkt_type {
 #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen)				\
 	DIV_ROUND_UP(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps))
 
-#define AR5K_XR_TX_TIME(_kbps, _frmlen)				\
-	AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME +		\
-	(AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)
+#define AR5K_XR_TX_TIME(_kbps, _frmlen)					\
+	(AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME +		\
+	(AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME))
 
 /*
  * DMA size definitions (2^n+2)
@@ -545,11 +546,11 @@ struct ath_desc {
 #define	CHANNEL_108G	CHANNEL_TG
 #define	CHANNEL_X	(CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 
-#define	CHANNEL_ALL 	(CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\
-			 CHANNEL_5GHZ | CHANNEL_TURBO)
+#define	CHANNEL_ALL 	(CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
+		CHANNEL_TURBO)
 
-#define	CHANNEL_ALL_NOTURBO 	(CHANNEL_ALL &~ CHANNEL_TURBO)
-#define CHANNEL_MODES	CHANNEL_ALL
+#define	CHANNEL_ALL_NOTURBO 	(CHANNEL_ALL & ~CHANNEL_TURBO)
+#define CHANNEL_MODES		CHANNEL_ALL
 
 /*
  * Used internaly in OpenHAL (ar5211.c/ar5212.c
@@ -916,7 +917,8 @@ struct ath_hw {
 	struct {
 		u16		txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
 		u16		txp_rates[AR5K_MAX_RATES];
-		s16		txp_min, txp_max;
+		s16		txp_min;
+		s16		txp_max;
 		bool		txp_tpc;
 		s16		txp_ofdm;
 	} ah_txpower;
@@ -978,7 +980,7 @@ void ath5k_hw_set_opmode(struct ath_hw *hal);
 void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac);
 bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac);
 void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id);
-bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask);
+bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask);
 /* Receive start/stop functions */
 void ath5k_hw_start_rx_pcu(struct ath_hw *hal);
 void ath5k_hw_stop_pcu_recv(struct ath_hw *hal);
@@ -1039,7 +1041,7 @@ enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal);
 /* Misc functions */
 int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power);
 void ath5k_hw_dump_state(struct ath_hw *hal);
-int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result);
+int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
 bool ath5k_hw_query_pspoll_support(struct ath_hw *hal);
 bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id);
 bool ath5k_hw_disable_pspoll(struct ath_hw *hal);
diff --git a/ath5k_base.c b/ath5k_base.c
index 0d5281b..d8f4b8e 100644
--- a/ath5k_base.c
+++ b/ath5k_base.c
@@ -33,10 +33,10 @@
 #include <linux/cache.h>
 #include <linux/pci.h>
 #include <linux/ethtool.h>
+#include <linux/uaccess.h>
 
 #include <net/ieee80211_radiotap.h>
 
-#include <asm/uaccess.h>
 #include <asm/unaligned.h>
 
 #include "ath5k_base.h"
@@ -133,10 +133,10 @@ static void ath_printrxbuf(struct ath_buf *bf, int done)
 	struct ath_desc *ds = bf->desc;
 
 	printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n",
-	    ds, (unsigned long long)bf->daddr,
-	    ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
-	    ds->ds_hw[0], ds->ds_hw[1],
-	    !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
+		ds, (unsigned long long)bf->daddr,
+		ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
+		ds->ds_hw[0], ds->ds_hw[1],
+		!done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
 }
 
 static void ath_printtxbuf(struct ath_buf *bf, int done)
@@ -144,11 +144,10 @@ static void ath_printtxbuf(struct ath_buf *bf, int done)
 	struct ath_desc *ds = bf->desc;
 
 	printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x "
-			"%08x %c\n",
-	    ds, (unsigned long long)bf->daddr,
-	    ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
-	    ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
-	    !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
+		"%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link,
+		ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
+		ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
+		!done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
 }
 #endif
 
@@ -214,11 +213,10 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 			ds->ds_txstat.ts_longretry / 6;
 		if (unlikely(ds->ds_txstat.ts_status)) {
 			sc->ll_stats.dot11ACKFailureCount++;
-			if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) {
+			if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
 				txs.excessive_retries = 1;
-			} else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) {
+			else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
 				txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
-			}
 		} else {
 			txs.flags |= IEEE80211_TX_STATUS_ACK;
 			txs.ack_signal = ds->ds_txstat.ts_rssi;
@@ -348,7 +346,7 @@ static inline u64 ath_extend_tsf(struct ath_hw *ah, u32 rstamp)
 	if ((tsf & 0x7fff) < rstamp)
 		tsf -= 0x8000;
 
-	return (tsf &~ 0x7fff) | rstamp;
+	return (tsf & ~0x7fff) | rstamp;
 }
 
 static void ath_tasklet_rx(unsigned long data)
@@ -423,7 +421,7 @@ static void ath_tasklet_rx(unsigned long data)
 			}
 
 			/* let crypto-error packets fall through in MNTR */
-			if ((stat &~ (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
+			if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
 					sc->opmode != IEEE80211_IF_TYPE_MNTR)
 				goto next;
 		}
@@ -435,8 +433,10 @@ accept:
 				PCI_DMA_FROMDEVICE);
 		bf->skb = NULL;
 
-		if (unlikely((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()))
-			printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb));
+		if (unlikely((ieee80211_get_hdrlen_from_skb(skb) & 3) &&
+					net_ratelimit()))
+			printk(KERN_DEBUG "rx len is not %%4: %u\n",
+					ieee80211_get_hdrlen_from_skb(skb));
 
 		skb_put(skb, len);
 
@@ -639,7 +639,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
  */
 static void ath_beacon_config(struct ath_softc *sc)
 {
-#define TSF_TO_TU(_h,_l)        (((_h) << 22) | ((_l) >> 10))
+#define TSF_TO_TU(_h, _l)	(((_h) << 22) | ((_l) >> 10))
 	struct ath_hw *ah = sc->ah;
 	u32 uninitialized_var(nexttbtt), intval, tsftu;
 	u64 tsf;
@@ -853,8 +853,8 @@ static int ath_init(struct ath_softc *sc)
 	/*
 	 * Enable interrupts.
 	 */
-	sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN
-		  | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
+	sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
+		AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
 
 	ath5k_hw_set_intr(sc->ah, sc->imask);
 
@@ -1022,7 +1022,8 @@ static int ath_stop_hw(struct ath_softc *sc)
 		 * (and system).  This varies by chip and is mostly an
 		 * issue with newer parts that go to sleep more quickly.
 		 */
-		if (sc->ah->ah_mac_version >= 7 && sc->ah->ah_mac_revision >= 8) {
+		if (sc->ah->ah_mac_version >= 7 &&
+				sc->ah->ah_mac_revision >= 8) {
 			/*
 			 * XXX
 			 * don't put newer MAC revisions > 7.8 to sleep because
@@ -1030,8 +1031,7 @@ static int ath_stop_hw(struct ath_softc *sc)
 			 */
 			DPRINTF(sc, ATH_DEBUG_RESET, "%s: mac version > 7.8, "
 				"not putting device to sleep\n", __func__);
-		}
-		else {
+		} else {
 			DPRINTF(sc, ATH_DEBUG_RESET,
 				"%s: putting device to full sleep\n", __func__);
 			ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
@@ -1069,7 +1069,7 @@ static void ath_setcurmode(struct ath_softc *sc, unsigned int mode)
 			{   2, 400, 100 },
 			{   0, 500, 130 }
 		};
-		const struct ath5k_rate_table* rt =
+		const struct ath5k_rate_table *rt =
 				ath5k_hw_get_rate_table(sc->ah, mode);
 		unsigned int i, j;
 
@@ -1188,7 +1188,8 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf,
 		flags |= AR5K_TXDESC_NOACK;
 
 	if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit())
-		printk(KERN_DEBUG "tx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb));
+		printk(KERN_DEBUG "tx len is not %%4: %u\n",
+				ieee80211_get_hdrlen_from_skb(skb));
 
 	hdrpad = 0;
 	pktlen = skb->len - hdrpad + FCS_LEN;
@@ -1367,9 +1368,8 @@ static void ath_remove_interface(struct ieee80211_hw *hw,
 	struct ath_softc *sc = hw->priv;
 
 	mutex_lock(&sc->lock);
-	if (sc->iface_id != conf->if_id) {
+	if (sc->iface_id != conf->if_id)
 		goto end;
-	}
 
 	sc->iface_id = 0;
 end:
@@ -1810,21 +1810,19 @@ static void ath_dump_modes(struct ieee80211_hw_mode *modes)
 		printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m,
 				modes[m].num_channels, modes[m].num_rates);
 		printk(KERN_DEBUG " channels:\n");
-		for (i = 0; i < modes[m].num_channels; i++) {
+		for (i = 0; i < modes[m].num_channels; i++)
 			printk(KERN_DEBUG "  %3d %d %.4x %.4x\n",
 					modes[m].channels[i].chan,
 					modes[m].channels[i].freq,
 					modes[m].channels[i].val,
 					modes[m].channels[i].flag);
-		}
 		printk(KERN_DEBUG " rates:\n");
-		for (i = 0; i < modes[m].num_rates; i++) {
+		for (i = 0; i < modes[m].num_rates; i++)
 			printk(KERN_DEBUG "  %4d %.4x %.4x %.4x\n",
 					modes[m].rates[i].rate,
 					modes[m].rates[i].val,
 					modes[m].rates[i].flags,
 					modes[m].rates[i].val2);
-		}
 	}
 }
 #else
@@ -2209,12 +2207,12 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 static const char *ath_chip_name(u8 mac_version)
 {
 	switch (mac_version) {
-		case AR5K_AR5210:
-			return "AR5210";
-		case AR5K_AR5211:
-			return "AR5211";
-		case AR5K_AR5212:
-			return "AR5212";
+	case AR5K_AR5210:
+		return "AR5210";
+	case AR5K_AR5211:
+		return "AR5211";
+	case AR5K_AR5212:
+		return "AR5212";
 	}
 	return "Unknown";
 }
@@ -2380,7 +2378,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 	struct ath_softc *sc = hw->priv;
 
 	if (sc->led_soft)
-	    	ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
+		ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
 
 	ath_stop_hw(sc);
 	pci_save_state(pdev);
@@ -2414,8 +2412,8 @@ static int ath_pci_resume(struct pci_dev *pdev)
 
 	ath_init(sc);
 	if (sc->led_soft) {
-	    	ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
-	    	ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0);
+		ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
+		ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0);
 	}
 
 	return 0;
@@ -2449,7 +2447,7 @@ static int maxcalibrate = INT_MAX / 1000;
 static ctl_table ath_static_sysctls[] = {
 #if AR_DEBUG
 	{ .ctl_name	= CTL_AUTO,
-	   .procname	= "debug",
+	  .procname	= "debug",
 	  .mode		= 0644,
 	  .data		= &ath_debug,
 	  .maxlen	= sizeof(ath_debug),
diff --git a/ath5k_hw.c b/ath5k_hw.c
index def9b8f..56f78d3 100644
--- a/ath5k_hw.c
+++ b/ath5k_hw.c
@@ -325,20 +325,20 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
 
 	switch (device) {
-		case PCI_DEVICE_ID_ATHEROS_AR2413:
-		case PCI_DEVICE_ID_ATHEROS_AR5413:
-		case PCI_DEVICE_ID_ATHEROS_AR5424:
-			/*
-			 * Known single chip solutions
-			 */
-			hal->ah_single_chip = true;
-			break;
-		default:
-			/*
-			 * Multi chip solutions
-			 */
-			hal->ah_single_chip = false;
-			break;
+	case PCI_DEVICE_ID_ATHEROS_AR2413:
+	case PCI_DEVICE_ID_ATHEROS_AR5413:
+	case PCI_DEVICE_ID_ATHEROS_AR5424:
+		/*
+		 * Known single chip solutions
+		 */
+		hal->ah_single_chip = true;
+		break;
+	default:
+		/*
+		 * Multi chip solutions
+		 */
+		hal->ah_single_chip = false;
+		break;
 	}
 
 	/*
@@ -379,15 +379,16 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
 	hal->ah_mac_srev = srev;
 	hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
 	hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
-	hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff;
-	hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ);
+	hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) &
+			0xffffffff;
+	hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,
+			CHANNEL_5GHZ);
 
-	if (hal->ah_version == AR5K_AR5210) {
+	if (hal->ah_version == AR5K_AR5210)
 		hal->ah_radio_2ghz_revision = 0;
-	} else {
+	else
 		hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal,
 				CHANNEL_2GHZ);
-	}
 
 	/* Single chip radio */
 	if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision)
@@ -511,11 +512,10 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 			mode |= AR5K_PHY_MODE_MOD_CCK;
 		} else if (flags & CHANNEL_G) {
 			/* Dynamic OFDM/CCK is not supported by the AR5211 */
-			if (hal->ah_version == AR5K_AR5211) {
+			if (hal->ah_version == AR5K_AR5211)
 				mode |= AR5K_PHY_MODE_MOD_CCK;
-			} else {
+			else
 				mode |= AR5K_PHY_MODE_MOD_DYN;
-			}
 		} else if (flags & CHANNEL_OFDM) {
 			mode |= AR5K_PHY_MODE_MOD_OFDM;
 		} else {
@@ -523,17 +523,9 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 			return -EINVAL;
 		}
 
-		if (flags & CHANNEL_TURBO) {
-			turbo = AR5K_PHY_TURBO_MODE |
-			    AR5K_PHY_TURBO_SHORT;
-		}
-	}
-
-	/*
-	 * Reset and wakeup the device
-	 */
-
-	else {
+		if (flags & CHANNEL_TURBO)
+			turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
+	} else { /* Reset and wakeup the device */
 		if (initial == true) {
 			/* ...reset hardware */
 			if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) {
@@ -553,7 +545,8 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 
 		/* ...enable Atheros turbo mode if requested */
 		if (flags & CHANNEL_TURBO)
-			ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO);
+			ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE,
+					AR5K_PHY_TURBO);
 
 		/* ...reset chipset */
 		if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) {
@@ -587,7 +580,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
 		return -EIO;
 	}
 
-	if (hal->ah_version != AR5K_AR5210){
+	if (hal->ah_version != AR5K_AR5210) {
 		/* ...set the PHY operating mode */
 		ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL);
 		udelay(300);
@@ -637,7 +630,8 @@ static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan)
 		ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
 	} else {
 		srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff;
-		ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8);
+		ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
+				((srev & 0x0f) << 4), 8);
 	}
 
 	/* Reset to the 5GHz mode */
@@ -721,15 +715,16 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	/*DCU/Antenna selection not available on 5210*/
 	if (hal->ah_version != AR5K_AR5210) {
 		if (change_channel == true) {
-			/*Sequence number for queue 0 -do this for all queues ?*/
-			s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0));
+			/* Seq number for queue 0 -do this for all queues ? */
+			s_seq = ath5k_hw_reg_read(hal,
+					AR5K_QUEUE_DFS_SEQNUM(0));
 			/*Default antenna*/
 			s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA);
 		}
 	}
 
 	/*GPIOs*/
-	s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) &	AR5K_PCICFG_LEDSTATE;
+	s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
 	s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR);
 	s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO);
 
@@ -807,7 +802,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 
 		/*
 		 * Write initial RF registers on 5211
-		 * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ?
+		 * do we need that ? Is ath5k_hw_rfregs going to work for
+		 * 5211 (5111) ?
 		 */
 		if (hal->ah_version == AR5K_AR5211)
 			ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode);
@@ -822,11 +818,11 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) {
 			if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X)
 				off = AR5K_INI_PHY_511X;
-			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 &&
-			    hal->ah_radio == AR5K_RF5111)
+			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111
+					&& hal->ah_radio == AR5K_RF5111)
 				off = AR5K_INI_PHY_5111;
-			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 &&
-			    hal->ah_radio == AR5K_RF5112)
+			else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112
+					&& hal->ah_radio == AR5K_RF5112)
 				off = AR5K_INI_PHY_5112;
 			else
 				continue;
@@ -888,9 +884,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		 * Write initial RF gain settings
 		 * This should work for both 5111/5112
 		 */
-		if (ath5k_hw_rfgain(hal, phy, freq) == false) {
+		if (ath5k_hw_rfgain(hal, phy, freq) == false)
 			return -EIO;
-		}
 
 		mdelay(1);
 
@@ -913,37 +908,38 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 						ath_hal_computetxtime(hal, rt,
 						14, rt->rates[i].control_rate,
 						false), data);
-					if (HAS_SHPREAMBLE(i)) {
+					if (HAS_SHPREAMBLE(i))
 						ath5k_hw_reg_write(hal,
-						    ath_hal_computetxtime(hal, rt, 14,
-						    rt->rates[i].control_rate, false),
-						    data +
+						    ath_hal_computetxtime(hal,
+						    rt, 14,
+						    rt->rates[i].control_rate,
+						    false), data +
 						    (AR5K_SET_SHORT_PREAMBLE << 2));
-					}
 				}
 
 			} else {
-			/*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/
+			/* For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is
+			 * O.K. for both a/g - OFDM) */
 
-				/*Get rate table for this operation mode*/
+				/* Get rate table for this operation mode */
 				rt = ath5k_hw_get_rate_table(hal,
 				    channel->val & CHANNEL_TURBO ?
 				    MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG);
 
-				/*Write rate duration table*/
-				for (i = 0; i < rt->rate_count; i++) {
+				/* Write rate duration table */
+				for (i = 0; i < rt->rate_count; i++)
 					ath5k_hw_reg_write(hal,
 						ath_hal_computetxtime(hal, rt,
 						14, rt->rates[i].control_rate,
 						false),
 						AR5K_RATE_DUR(rt->rates[i].rate_code));
-				}
 
 			}
 		}
 
 		/* Fix for first revision of the RF5112 RF chipset */
-		if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision<
+		if (hal->ah_radio >= AR5K_RF5112 &&
+				hal->ah_radio_5ghz_revision <
 				AR5K_SREV_RAD_5112A) {
 			ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD,
 					AR5K_PHY_CCKTXCTL);
@@ -976,22 +972,23 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		/* Write OFDM timings on 5212*/
 		if (hal->ah_version == AR5K_AR5212) {
 			if (channel->val & CHANNEL_OFDM) {
-				u32 coef_scaled, coef_exp, coef_man, ds_coef_exp,
-				    ds_coef_man, clock;
+				u32 coef_scaled, coef_exp, coef_man,
+					ds_coef_exp, ds_coef_man, clock;
 
 				clock = channel->val & CHANNEL_T ? 80 : 40;
-				coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq;
+				coef_scaled = ((5 * (clock << 24)) / 2) /
+					channel->freq;
 
 				for (coef_exp = 31; coef_exp > 0; coef_exp--)
 					if ((coef_scaled >> coef_exp) & 0x1)
 						break;
 
-				if (!coef_exp) {
+				if (!coef_exp)
 					return -EINVAL;
-				}
 
 				coef_exp = 14 - (coef_exp - 24);
-				coef_man = coef_scaled + (1 << (24 - coef_exp - 1));
+				coef_man = coef_scaled +
+					(1 << (24 - coef_exp - 1));
 				ds_coef_man = coef_man >> (24 - coef_exp);
 				ds_coef_exp = coef_exp - 16;
 
@@ -1037,12 +1034,15 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			AR5K_PHY(0x5a));
 
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11),
-		    (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f);
+			(ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
+			0xffffc07f);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12),
-		    (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff);
+			(ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
+			0xfffc0fff);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14),
-		    (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
-		    ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000);
+			(ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
+			((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
+			0xffff0000);
 
 		ath5k_hw_reg_write(hal,
 			(ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
@@ -1051,9 +1051,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 			(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
 
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a),
-		    ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
+			ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19),
-		    (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
+			(ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
 		AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01);
 
 		AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
@@ -1061,11 +1061,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 		    (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
 		    ee->ee_q_cal[ee_mode]);
 
-		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 			AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ,
 				AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 				ee->ee_margin_tx_rx[ee_mode]);
-		}
 
 	} else {
 		mdelay(1);
@@ -1131,9 +1130,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	 * 5111/5112 Specific
 	 */
 	if (hal->ah_version != AR5K_AR5210) {
-		data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M;
+		data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) &
+			AR5K_PHY_RX_DELAY_M;
 		data = (channel->val & CHANNEL_CCK) ?
-		    ((data << 2) / 22) : (data / 10);
+			((data << 2) / 22) : (data / 10);
 
 		udelay(100 + data);
 	} else {
@@ -1210,9 +1210,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 	}
 
 	/* Pre-enable interrupts on 5211/5212*/
-	if (hal->ah_version != AR5K_AR5210) {
-		ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL);
-	}
+	if (hal->ah_version != AR5K_AR5210)
+		ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX |
+				AR5K_INT_FATAL);
 
 	/*
 	 * Set RF kill flags if supported by the device (read from the EEPROM)
@@ -1222,7 +1222,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
 #if 0
 	if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
 		ath5k_hw_set_gpio_input(hal, 0);
-		if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0)
+		hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0);
+		if (hal->ah_gpio[0] == 0)
 			ath5k_hw_set_gpio_intr(hal, 0, 1);
 		else
 			ath5k_hw_set_gpio_intr(hal, 0, 0);
@@ -1313,19 +1314,19 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
 		staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
 		/* fallthrough */
 	case AR5K_PM_NETWORK_SLEEP:
-		if (set_chip == true) {
+		if (set_chip == true)
 			ath5k_hw_reg_write(hal,
 				AR5K_SLEEP_CTL_SLE | sleep_duration,
 				AR5K_SLEEP_CTL);
-		}
+
 		staid |= AR5K_STA_ID1_PWR_SV;
 		break;
 
 	case AR5K_PM_FULL_SLEEP:
-		if (set_chip == true) {
+		if (set_chip == true)
 			ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP,
 				AR5K_SLEEP_CTL);
-		}
+
 		staid |= AR5K_STA_ID1_PWR_SV;
 		break;
 
@@ -1333,7 +1334,8 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
 		if (set_chip == false)
 			goto commit;
 
-		ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL);
+		ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE,
+				AR5K_SLEEP_CTL);
 
 		for (i = 5000; i > 0; i--) {
 			/* Check if the chip did wake up */
@@ -1460,22 +1462,21 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue)
 		 * Set the queue by type on 5210
 		 */
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-				tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
-				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V |
-					AR5K_BCR_BDMAE, AR5K_BSR);
-				break;
-			case AR5K_TX_QUEUE_CAB:
-				tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
-				ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV |
-					AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
+		case AR5K_TX_QUEUE_DATA:
+			tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+			tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
+			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
 					AR5K_BSR);
-				break;
-			default:
-				return -EINVAL;
+			break;
+		case AR5K_TX_QUEUE_CAB:
+			tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
+			ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
+				AR5K_BCR_BDMAE, AR5K_BSR);
+			break;
+		default:
+			return -EINVAL;
 		}
 		/* Start queue */
 		ath5k_hw_reg_write(hal, tx_queue, AR5K_CR);
@@ -1515,17 +1516,17 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 		 * Set by queue type
 		 */
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				/* XXX Fix me... */
-				tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
-				ath5k_hw_reg_write(hal, 0, AR5K_BSR);
-				break;
-			default:
-				return false;
+		case AR5K_TX_QUEUE_DATA:
+			tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			/* XXX Fix me... */
+			tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
+			ath5k_hw_reg_write(hal, 0, AR5K_BSR);
+			break;
+		default:
+			return false;
 		}
 
 		/* Stop queue */
@@ -1538,8 +1539,9 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 
 		/*Check for pending frames*/
 		do {
-			pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) &
-						AR5K_QCU_STS_FRMPENDCNT;
+			pending = ath5k_hw_reg_read(hal,
+				AR5K_QUEUE_STATUS(queue)) &
+				AR5K_QCU_STS_FRMPENDCNT;
 			udelay(100);
 		} while (--i && pending);
 
@@ -1547,7 +1549,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue)
 		ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD);
 	}
 
-	/*TODO: Check for success else return false*/
+	/* TODO: Check for success else return false */
 	return true;
 }
 
@@ -1568,15 +1570,15 @@ u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue)
 	/*5210 doesn't have QCU*/
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_reg = AR5K_NOQCU_TXDP0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				tx_reg = AR5K_NOQCU_TXDP1;
-				break;
-			default:
-				return 0xffffffff;
+		case AR5K_TX_QUEUE_DATA:
+			tx_reg = AR5K_NOQCU_TXDP0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			tx_reg = AR5K_NOQCU_TXDP1;
+			break;
+		default:
+			return 0xffffffff;
 		}
 	} else {
 		tx_reg = AR5K_QUEUE_TXDP(queue);
@@ -1602,15 +1604,15 @@ int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr)
 	 */
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (hal->ah_txq[queue].tqi_type) {
-			case AR5K_TX_QUEUE_DATA:
-				tx_reg = AR5K_NOQCU_TXDP0;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				tx_reg = AR5K_NOQCU_TXDP1;
-				break;
-			default:
-				return -EINVAL;
+		case AR5K_TX_QUEUE_DATA:
+			tx_reg = AR5K_NOQCU_TXDP0;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			tx_reg = AR5K_NOQCU_TXDP1;
+			break;
+		default:
+			return -EINVAL;
 		}
 	} else {
 		/*
@@ -1908,7 +1910,8 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data)
 	if (hal->ah_version == AR5K_AR5210) {
 		AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE);
 	} else {
-		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD,
+				AR5K_EEPROM_CMD_RESET);
 	}
 
 	/*
@@ -1920,7 +1923,8 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data)
 	} else {
 		ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE);
 		ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA);
-		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE);
+		AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD,
+				AR5K_EEPROM_CMD_WRITE);
 	}
 
 	/*
@@ -2185,7 +2189,8 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 	 */
 	mode = AR5K_EEPROM_MODE_11A;
 
-	ee->ee_turbo_max_power[mode] = AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
+	ee->ee_turbo_max_power[mode] =
+			AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
 
 	offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version);
 
@@ -2247,9 +2252,8 @@ static int ath5k_eeprom_init(struct ath_hw *hal)
 			ath5k_eeprom_bin2freq(hal, val & 0xff, mode);
 	}
 
-	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
+	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 		ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
-	}
 
 	/*
 	 * Get values for 802.11g (2.4GHz)
@@ -2412,12 +2416,13 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 	} else {
 		/*
 		 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
-		 * XXX and from 2312 to 2732GHz. There are problems with the current
-		 * XXX ieee80211 implementation because the IEEE channel mapping
-		 * XXX does not support negative channel numbers (2312MHz is channel
-		 * XXX -19). Of course, this doesn't matter because these channels
-		 * XXX are out of range but some regulation domains like MKK (Japan)
-		 * XXX will support frequencies somewhere around 4.8GHz.
+		 * XXX and from 2312 to 2732GHz. There are problems with the
+		 * XXX current ieee80211 implementation because the IEEE
+		 * XXX channel mapping does not support negative channel
+		 * XXX numbers (2312MHz is channel -19). Of course, this
+		 * XXX doesn't matter because these channels are out of range
+		 * XXX but some regulation domains like MKK (Japan) will
+		 * XXX support frequencies somewhere around 4.8GHz.
 		 */
 
 		/*
@@ -2437,8 +2442,10 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 						hal->ah_capabilities.cap_mode);
 		}
 
-		/* Enable  802.11b if a 2GHz capable radio (2111/5112) is connected */
-		if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) {
+		/* Enable  802.11b if a 2GHz capable radio (2111/5112) is
+		 * connected */
+		if (AR5K_EEPROM_HDR_11B(ee_header) ||
+				AR5K_EEPROM_HDR_11G(ee_header)) {
 			hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
 			hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
 
@@ -2457,7 +2464,8 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal)
 
 	/* Set number of supported TX queues */
 	if (hal->ah_version == AR5K_AR5210)
-		hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;
+		hal->ah_capabilities.cap_queues.q_tx_num =
+			AR5K_NUM_TX_QUEUES_NOQCU;
 	else
 		hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
 
@@ -2601,7 +2609,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id)
  * Set BSSID mask on 5212
  */
 bool
-ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask)
+ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask)
 {
 	u32 low_id, high_id;
 	AR5K_TRACE;
@@ -2844,7 +2852,8 @@ void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval)
  * Set beacon timers
  */
 void
-ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state)
+ath5k_hw_set_beacon_timers(struct ath_hw *hal,
+		const struct ath5k_beacon_state *state)
 {
 	u32 cfp_period, next_cfp, dtim, interval, next_beacon;
 
@@ -2885,7 +2894,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *
 				AR5K_STA_ID1_DEFAULT_ANTENNA |
 				AR5K_STA_ID1_PCF);
 		ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD);
-		ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR);
+		ath5k_hw_reg_write(hal, state->bs_cfp_max_duration,
+				AR5K_CFP_DUR);
 		ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period :
 						next_cfp)) << 3, AR5K_TIMER2);
 	} else {
@@ -3039,7 +3049,8 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr)
  * Update mib counters (statistics)
  */
 void
-ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics)
+ath5k_hw_update_mib_counters(struct ath_hw *hal,
+		struct ath5k_mib_stats *statistics)
 {
 	AR5K_TRACE;
 	/* Read-And-Clear */
@@ -3240,44 +3251,44 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type,
 	/*5210 only has 2 queues*/
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (queue_type) {
-			case AR5K_TX_QUEUE_DATA:
-				queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-			case AR5K_TX_QUEUE_CAB:
-				queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
-				break;
-			default:
-				return -EINVAL;
+		case AR5K_TX_QUEUE_DATA:
+			queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+		case AR5K_TX_QUEUE_CAB:
+			queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
+			break;
+		default:
+			return -EINVAL;
 		}
 	} else {
 		switch (queue_type) {
-			case AR5K_TX_QUEUE_DATA:
-				for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
-					hal->ah_txq[queue].tqi_type !=
-					AR5K_TX_QUEUE_INACTIVE; queue++) {
+		case AR5K_TX_QUEUE_DATA:
+			for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
+				hal->ah_txq[queue].tqi_type !=
+				AR5K_TX_QUEUE_INACTIVE; queue++) {
 
-					if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
-						return -EINVAL;
-				}
-				break;
-			case AR5K_TX_QUEUE_UAPSD:
-				queue = AR5K_TX_QUEUE_ID_UAPSD;
-				break;
-			case AR5K_TX_QUEUE_BEACON:
-				queue = AR5K_TX_QUEUE_ID_BEACON;
-				break;
-			case AR5K_TX_QUEUE_CAB:
-				queue = AR5K_TX_QUEUE_ID_CAB;
-				break;
-			case AR5K_TX_QUEUE_XR_DATA:
-				if (hal->ah_version != AR5K_AR5212)
-					AR5K_PRINTF("XR data queues only "
-							"supported in 5212!\n");
-				queue = AR5K_TX_QUEUE_ID_XR_DATA;
-				break;
-			default:
-				return -EINVAL;
+				if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
+					return -EINVAL;
+			}
+			break;
+		case AR5K_TX_QUEUE_UAPSD:
+			queue = AR5K_TX_QUEUE_ID_UAPSD;
+			break;
+		case AR5K_TX_QUEUE_BEACON:
+			queue = AR5K_TX_QUEUE_ID_BEACON;
+			break;
+		case AR5K_TX_QUEUE_CAB:
+			queue = AR5K_TX_QUEUE_ID_CAB;
+			break;
+		case AR5K_TX_QUEUE_XR_DATA:
+			if (hal->ah_version != AR5K_AR5212)
+				AR5K_PRINTF("XR data queues only supported in "
+						"5212!\n");
+			queue = AR5K_TX_QUEUE_ID_XR_DATA;
+			break;
+		default:
+			return -EINVAL;
 		}
 	}
 
@@ -3461,7 +3472,8 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 			AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
 			AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
 			AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,
-			AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue));
+				AR5K_DCU_LCL_IFS_AIFS),
+			AR5K_QUEUE_DFS_LOCAL_IFS(queue));
 
 		/*
 		 * Set misc registers
@@ -3483,12 +3495,11 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 					AR5K_QCU_MISC_CBR_THRES_ENABLE);
 		}
 
-		if (tq->tqi_ready_time) {
+		if (tq->tqi_ready_time)
 			ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time,
 				AR5K_QCU_RDYTIMECFG_INTVAL) |
 				AR5K_QCU_RDYTIMECFG_ENABLE,
 				AR5K_QUEUE_RDYTIMECFG(queue));
-		}
 
 		if (tq->tqi_burst_time) {
 			ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time,
@@ -3496,48 +3507,43 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue)
 				AR5K_DCU_CHAN_TIME_ENABLE,
 				AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
 
-			if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) {
-				AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+			if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
+				AR5K_REG_ENABLE_BITS(hal,
+					AR5K_QUEUE_MISC(queue),
 					AR5K_QCU_MISC_TXE);
-			}
 		}
 
-		if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) {
+		if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
 			ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
 				AR5K_QUEUE_DFS_MISC(queue));
-		}
 
-		if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
+		if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
 			ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG,
 				AR5K_QUEUE_DFS_MISC(queue));
-		}
 
 		/*
 		 * Set registers by queue type
 		 */
 		switch (tq->tqi_type) {
-			case AR5K_TX_QUEUE_BEACON:
-				AR5K_REG_ENABLE_BITS(hal,
-					AR5K_QUEUE_MISC(queue),
-					AR5K_QCU_MISC_FRSHED_DBA_GT |
-					AR5K_QCU_MISC_CBREXP_BCN |
-					AR5K_QCU_MISC_BCN_ENABLE);
+		case AR5K_TX_QUEUE_BEACON:
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
+				AR5K_QCU_MISC_FRSHED_DBA_GT |
+				AR5K_QCU_MISC_CBREXP_BCN |
+				AR5K_QCU_MISC_BCN_ENABLE);
 
-				AR5K_REG_ENABLE_BITS(hal,
-					AR5K_QUEUE_DFS_MISC(queue),
-					(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
-					AR5K_DCU_MISC_ARBLOCK_CTL_S) |
-					AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
-					AR5K_DCU_MISC_BCN_ENABLE);
-
-				ath5k_hw_reg_write(hal,
-					((AR5K_TUNE_BEACON_INTERVAL -
-					(AR5K_TUNE_SW_BEACON_RESP -
-					AR5K_TUNE_DMA_BEACON_RESP) -
-					AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
-					AR5K_QCU_RDYTIMECFG_ENABLE,
-					AR5K_QUEUE_RDYTIMECFG(queue));
-				break;
+			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue),
+				(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
+				AR5K_DCU_MISC_ARBLOCK_CTL_S) |
+				AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
+				AR5K_DCU_MISC_BCN_ENABLE);
+
+			ath5k_hw_reg_write(hal, ((AR5K_TUNE_BEACON_INTERVAL -
+				(AR5K_TUNE_SW_BEACON_RESP -
+				AR5K_TUNE_DMA_BEACON_RESP) -
+				AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
+				AR5K_QCU_RDYTIMECFG_ENABLE,
+				AR5K_QUEUE_RDYTIMECFG(queue));
+			break;
 
 		case AR5K_TX_QUEUE_CAB:
 			AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue),
@@ -3650,8 +3656,8 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 {
 	u32 frame_type;
 	struct ath5k_hw_2w_tx_desc *tx_desc;
-
-	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
+	
+	tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
 
 	if (tx_tries0 == 0)
 		return -EINVAL;
@@ -3671,7 +3677,8 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	 * XXX: I only found that on 5210 code, does it work on 5211 ?
 	 */
 	if (hal->ah_version == AR5K_AR5210) {
-		tx_desc->tx_control_0 = hdr_len & AR5K_2W_TX_DESC_CTL0_HEADER_LEN;
+		tx_desc->tx_control_0 = hdr_len &
+				AR5K_2W_TX_DESC_CTL0_HEADER_LEN;
 		if (tx_desc->tx_control_0 != hdr_len)
 			return -EINVAL;
 	}
@@ -3679,17 +3686,17 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	/*Diferences between 5210-5211*/
 	if (hal->ah_version == AR5K_AR5210) {
 		switch (type) {
-			case AR5K_PKT_TYPE_BEACON:
-			case AR5K_PKT_TYPE_PROBE_RESP:
-				frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
-			case AR5K_PKT_TYPE_PIFS:
-				frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
-			default:
-				frame_type = type /*<< 2 ?*/;
+		case AR5K_PKT_TYPE_BEACON:
+		case AR5K_PKT_TYPE_PROBE_RESP:
+			frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
+		case AR5K_PKT_TYPE_PIFS:
+			frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
+		default:
+			frame_type = type /*<< 2 ?*/;
 		}
 
 		tx_desc->tx_control_0 =
-			AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE)|
+			AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
 			AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
 	} else {
 		tx_desc->tx_control_0 |=
@@ -3726,10 +3733,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	 * RTS/CTS Duration [5210 ?]
 	 */
 	if ((hal->ah_version == AR5K_AR5210) &&
-			(flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) {
-		tx_desc->tx_control_1 |=
-			rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
-	}
+			(flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
+		tx_desc->tx_control_1 |= rtscts_duration &
+				AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
 
 	return 0;
 }
@@ -3748,7 +3754,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal,
 
 	AR5K_TRACE;
 
-	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+	tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
 
 	/*
 	 * Validate input
@@ -3803,7 +3809,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal,
 	 * RTS/CTS
 	 */
 	if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
-		if ((flags & AR5K_TXDESC_RTSENA) &&(flags & AR5K_TXDESC_CTSENA))
+		if ((flags & AR5K_TXDESC_RTSENA) &&
+				(flags & AR5K_TXDESC_CTSENA))
 			return -EINVAL;
 		tx_desc->tx_control_2 |= rtscts_duration &
 				AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
@@ -3825,7 +3832,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	struct ath5k_hw_4w_tx_desc *tx_desc;
 
 	if (hal->ah_version == AR5K_AR5212) {
-		tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
+		tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
 
 #define _XTX_TRIES(_n)							\
 	if (tx_tries##_n) {						\
@@ -3846,7 +3853,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc,
 		return true;
 	}
 
-	return(false);
+	return false;
 }
 
 /*
@@ -3858,7 +3865,7 @@ static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal,
 {
 	struct ath5k_hw_2w_tx_desc *tx_desc;
 
-	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
+	tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
 
 	/* Clear status descriptor */
 	memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
@@ -3889,8 +3896,8 @@ static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal,
 	struct ath5k_hw_tx_status *tx_status;
 
 	AR5K_TRACE;
-	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
-	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2];
+	tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
 
 	/* Clear status descriptor */
 	memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status));
@@ -3918,8 +3925,8 @@ static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal,
 	struct ath5k_hw_tx_status *tx_status;
 	struct ath5k_hw_2w_tx_desc *tx_desc;
 
-	tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0;
-	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0];
+	tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0];
 
 	/* No frame has been send or error */
 	if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
@@ -3969,8 +3976,8 @@ static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal,
 	struct ath5k_hw_4w_tx_desc *tx_desc;
 
 	AR5K_TRACE;
-	tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
-	tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2];
+	tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
+	tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
 
 	/* No frame has been send or error */
 	if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
@@ -4047,7 +4054,7 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc,
 	struct ath5k_rx_desc *rx_desc;
 
 	AR5K_TRACE;
-	rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0;
+	rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0;
 
 	/*
 	 *Clear ds_hw
@@ -4081,7 +4088,7 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 {
 	struct ath5k_hw_old_rx_status *rx_status;
 
-	rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0];
+	rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
 	if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE)
@@ -4094,15 +4101,15 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
 		AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
 	desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
-	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
+		AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
 	desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
-	    	AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
+		AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
 	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
 		AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
 	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
 		AR5K_OLD_RX_DESC_STATUS0_MORE;
 	desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
-	    	AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
+		AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
@@ -4110,7 +4117,7 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal,
 	 */
 	if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
 		desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
-		    	AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
+			AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
 	else
 		desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
 
@@ -4152,10 +4159,10 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 	struct ath5k_hw_rx_error *rx_err;
 
 	AR5K_TRACE;
-	rx_status = (struct ath5k_hw_new_rx_status*)&desc->ds_hw[0];
+	rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0];
 
 	/* Overlay on error */
-	rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0];
+	rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
 	if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE)
@@ -4196,7 +4203,8 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal,
 		if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
 
-		if (rx_status->rx_status_1 &AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR){
+		if (rx_status->rx_status_1 &
+				AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) {
 			desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
 			desc->ds_us.rx.rs_phyerr =
 				AR5K_REG_MS(rx_err->rx_error_1,
@@ -4516,12 +4524,12 @@ static int ath5k_hw_rf5111_channel(struct ath_hw *hal,
 
 	if (ath_channel < 145 || !(ath_channel & 1)) {
 		clock = 1;
-		data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2)
-		    | (clock << 1) | (1 << 10) | 1;
+		data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) |
+			(clock << 1) | (1 << 10) | 1;
 	} else {
 		clock = 0;
-		data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2)
-		    | (clock << 1) | (1 << 10) | 1;
+		data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff)
+			<< 2) | (clock << 1) | (1 << 10) | 1;
 	}
 
 	ath5k_hw_reg_write(hal, (data1 & 0xff) | ((data0 & 0xff) << 8),
@@ -4985,11 +4993,10 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 				hal->ah_gain.g_target >=  hal->ah_gain.g_high &&
 				hal->ah_gain.g_step_idx > 0;
 				hal->ah_gain.g_step =
-					&go->go_step[hal->ah_gain.g_step_idx]) {
+					&go->go_step[hal->ah_gain.g_step_idx])
 			hal->ah_gain.g_target -= 2 *
 			    (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
 			    hal->ah_gain.g_step->gos_gain);
-		}
 
 		ret = 1;
 		goto done;
@@ -5002,11 +5009,10 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal)
 				hal->ah_gain.g_target <= hal->ah_gain.g_low &&
 				hal->ah_gain.g_step_idx < go->go_steps_count-1;
 				hal->ah_gain.g_step =
-					&go->go_step[hal->ah_gain.g_step_idx]) {
+					&go->go_step[hal->ah_gain.g_step_idx])
 			hal->ah_gain.g_target -= 2 *
 			    (go->go_step[++hal->ah_gain.g_step_idx].gos_gain -
 			    hal->ah_gain.g_step->gos_gain);
-		}
 
 		ret = 2;
 		goto done;
@@ -5484,13 +5490,12 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel,
 		AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
 		AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
 
-	if (hal->ah_txpower.txp_tpc == true) {
+	if (hal->ah_txpower.txp_tpc == true)
 		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
 			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
-	} else {
+	else
 		ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX |
 			AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
-	}
 
 	return 0;
 }
@@ -5502,7 +5507,7 @@ int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power)
 
 	AR5K_TRACE;
 #ifdef AR5K_DEBUG
-	AR5K_PRINTF("changing txpower to %d\n",power);
+	AR5K_PRINTF("changing txpower to %d\n", power);
 #endif
 	return ath5k_hw_txpower(hal, channel, power);
 }
diff --git a/ath5k_hw.h b/ath5k_hw.h
index 2dfcf92..bd5162e 100644
--- a/ath5k_hw.h
+++ b/ath5k_hw.h
@@ -492,14 +492,15 @@ struct ath5k_hw_tx_status {
 #define AR5K_PHY_READ(hal, _reg)					\
 	ath5k_hw_reg_read(hal, (hal)->ah_phy + ((_reg) << 2))
 
-#define AR5K_REG_WAIT(_i)						\
+#define AR5K_REG_WAIT(_i) do {						\
 	if (_i % 64)							\
-		udelay(1);
+		udelay(1);						\
+} while (0)
 
-#define AR5K_EEPROM_READ(_o, _v)	{				\
+#define AR5K_EEPROM_READ(_o, _v) do {					\
 	if ((ret = ath5k_hw_eeprom_read(hal, (_o), &(_v))) != 0)	\
 		return (ret);						\
-}
+} while (0)
 
 #define AR5K_EEPROM_READ_HDR(_o, _v)					\
 	AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v);	\
@@ -584,7 +585,7 @@ struct ath5k_hw_tx_status {
 	(AR5K_INIT_PROG_IFS)						\
 )
 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO	(			\
-	(AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\
+	(AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
 	(AR5K_INIT_PROG_IFS_TURBO)					\
 )
 #define AR5K_INIT_BEACON_CONTROL		(			\
@@ -621,328 +622,328 @@ struct ath5k_ini_rf {
 };
 
 /* RF5111 mode-specific init registers */
-#define AR5K_RF5111_INI_RF	{						\
-	{ 0, 0x989c,								\
-	/*     mode a/XR  mode aTurbo   mode b     mode g     mode gTurbo */    \
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 0, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },	\
-	{ 0, 0x989c,								\
-	    { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },	\
-	{ 0, 0x98d4,								\
-	    { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },	\
-	{ 1, 0x98d4,								\
-	    { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },	\
-	{ 2, 0x98d4,								\
-	    { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },	\
-	{ 3, 0x98d8,								\
-	    { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },	\
-	{ 6, 0x98d4,								\
-	    { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },	\
-	{ 7, 0x989c,								\
-	    { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },	\
-	{ 7, 0x989c,								\
-	    { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },	\
-	{ 7, 0x989c,								\
-	    { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },	\
-	{ 7, 0x98cc,								\
-	    { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },	\
+#define AR5K_RF5111_INI_RF	{					      \
+	{ 0, 0x989c,							      \
+	/*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */  \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \
+	{ 0, 0x989c,							      \
+	    { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \
+	{ 0, 0x98d4,							      \
+	    { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \
+	{ 1, 0x98d4,							      \
+	    { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
+	{ 2, 0x98d4,							      \
+	    { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \
+	{ 3, 0x98d8,							      \
+	    { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \
+	{ 6, 0x98d4,							      \
+	    { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \
+	{ 7, 0x989c,							      \
+	    { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \
+	{ 7, 0x98cc,							      \
+	    { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \
 }
 
 /* RF5112 mode-specific init registers */
-#define AR5K_RF5112_INI_RF	{						\
-	{ 1, 0x98d4,								\
-		/*     mode a/XR  mode aTurbo   mode b     mode g     mode gTurbo */    \
-	    { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },	\
-	{ 2, 0x98d0,								\
-	    { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },	\
-	{ 3, 0x98dc,								\
-	    { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },	\
-	{ 6, 0x989c,								\
-	    { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },	\
-	{ 6, 0x989c,								\
-	    { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },	\
-	{ 6, 0x989c,								\
-	    { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },	\
-	{ 6, 0x989c,								\
-	    { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },	\
-	{ 6, 0x98d0,								\
-	    { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },	\
-	{ 7, 0x989c,								\
-	    { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },	\
-	{ 7, 0x989c,								\
-	    { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },	\
-	{ 7, 0x98c4,								\
-	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },	\
+#define AR5K_RF5112_INI_RF	{					      \
+	{ 1, 0x98d4,							      \
+	/*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */  \
+	    { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
+	{ 2, 0x98d0,							      \
+	    { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \
+	{ 3, 0x98dc,							      \
+	    { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \
+	{ 6, 0x989c,							      \
+	    { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \
+	{ 6, 0x98d0,							      \
+	    { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \
+	{ 7, 0x989c,							      \
+	    { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \
+	{ 7, 0x98c4,							      \
+	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
 	}
 
 /* RF5112A mode-specific init registers */
-#define AR5K_RF5112A_INI_RF     {						\
-	{ 1, 0x98d4,								\
-	/*     mode a/XR  mode aTurbo   mode b     mode g     mode gTurbo */    \
-	    { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },	\
-	{ 2, 0x98d0,								\
-	    { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },	\
-	{ 3, 0x98dc,								\
-	    { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },	\
-	{ 6, 0x989c,								\
-	    { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },	\
-	{ 6, 0x989c,								\
-	    { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
-	{ 6, 0x989c,								\
-	    { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },	\
-	{ 6, 0x989c,								\
-	    { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },	\
-	{ 6, 0x989c,								\
-	    { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },	\
-	{ 6, 0x989c,								\
-	    { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },	\
-	{ 6, 0x98d8,								\
-	    { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },	\
-	{ 7, 0x989c,								\
-	    { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },	\
-	{ 7, 0x989c,								\
-	    { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },	\
-	{ 7, 0x989c,								\
-	    { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },	\
-	{ 7, 0x98c4,								\
-	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },	\
+#define AR5K_RF5112A_INI_RF     {					      \
+	{ 1, 0x98d4,							      \
+	/*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */  \
+	    { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
+	{ 2, 0x98d0,							      \
+	    { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \
+	{ 3, 0x98dc,							      \
+	    { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \
+	{ 6, 0x989c,							      \
+	    { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \
+	{ 6, 0x98d8,							      \
+	    { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \
+	{ 7, 0x989c,							      \
+	    { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \
+	{ 7, 0x989c,							      \
+	    { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \
+	{ 7, 0x98c4,							      \
+	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
 }
 
 /*
@@ -956,136 +957,136 @@ struct ath5k_ini_rfgain {
 #define AR5K_INI_RFGAIN_2GHZ	1
 };
 
-#define AR5K_INI_RFGAIN	{							\
-	{ 0x9a00, {								\
-		/* 5111 5Ghz  5111 2Ghz        5112 5Ghz   5112 2Ghz */		\
-		{ 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } },	\
-	{ 0x9a04, {								\
-		{ 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } },	\
-	{ 0x9a08, {								\
-		{ 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } },	\
-	{ 0x9a0c, {								\
-		{ 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } },	\
-	{ 0x9a10, {								\
-		{ 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } },	\
-	{ 0x9a14, {								\
-		{ 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } },	\
-	{ 0x9a18, {								\
-		{ 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } },	\
-	{ 0x9a1c, {								\
-		{ 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } },	\
-	{ 0x9a20, {								\
-		{ 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } },	\
-	{ 0x9a24, {								\
-		{ 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } },	\
-	{ 0x9a28, {								\
-		{ 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } },	\
-	{ 0x9a2c, {								\
-		{ 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } },	\
-	{ 0x9a30, {								\
-		{ 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } },	\
-	{ 0x9a34, {								\
-		{ 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } },	\
-	{ 0x9a38, {								\
-		{ 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } },	\
-	{ 0x9a3c, {								\
-		{ 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } },	\
-	{ 0x9a40, {								\
-		{ 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } },	\
-	{ 0x9a44, {								\
-		{ 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } },	\
-	{ 0x9a48, {								\
-		{ 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } },	\
-	{ 0x9a4c, {								\
-		{ 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } },	\
-	{ 0x9a50, {								\
-		{ 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } },	\
-	{ 0x9a54, {								\
-		{ 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } },	\
-	{ 0x9a58, {								\
-		{ 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } },	\
-	{ 0x9a5c, {								\
-		{ 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } },	\
-	{ 0x9a60, {								\
-		{ 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } },	\
-	{ 0x9a64, {								\
-		{ 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } },	\
-	{ 0x9a68, {								\
-		{ 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } },	\
-	{ 0x9a6c, {								\
-		{ 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } },	\
-	{ 0x9a70, {								\
-		{ 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } },	\
-	{ 0x9a74, {								\
-		{ 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } },	\
-	{ 0x9a78, {								\
-		{ 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } },	\
-	{ 0x9a7c, {								\
-		{ 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } },	\
-	{ 0x9a80, {								\
-		{ 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } },	\
-	{ 0x9a84, {								\
-		{ 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } },	\
-	{ 0x9a88, {								\
-		{ 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } },	\
-	{ 0x9a8c, {								\
-		{ 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } },	\
-	{ 0x9a90, {								\
-		{ 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } },	\
-	{ 0x9a94, {								\
-		{ 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } },	\
-	{ 0x9a98, {								\
-		{ 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } },	\
-	{ 0x9a9c, {								\
-		{ 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } },	\
-	{ 0x9aa0, {								\
-		{ 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } },	\
-	{ 0x9aa4, {								\
-		{ 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } },	\
-	{ 0x9aa8, {								\
-		{ 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } },	\
-	{ 0x9aac, {								\
-		{ 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } },	\
-	{ 0x9ab0, {								\
-		{ 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } },	\
-	{ 0x9ab4, {								\
-		{ 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } },	\
-	{ 0x9ab8, {								\
-		{ 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } },	\
-	{ 0x9abc, {								\
-		{ 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } },	\
-	{ 0x9ac0, {								\
-		{ 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } },	\
-	{ 0x9ac4, {								\
-		{ 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } },	\
-	{ 0x9ac8, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } },	\
-	{ 0x9acc, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } },	\
-	{ 0x9ad0, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } },	\
-	{ 0x9ad4, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } },	\
-	{ 0x9ad8, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9adc, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9ae0, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9ae4, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9ae8, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9aec, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9af0, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9af4, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9af8, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
-	{ 0x9afc, {								\
-		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },	\
+#define AR5K_INI_RFGAIN	{						    \
+	{ 0x9a00, {							    \
+		/* 5111 5Ghz  5111 2Ghz       5112 5Ghz   5112 2Ghz */	    \
+		{ 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \
+	{ 0x9a04, {							    \
+		{ 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \
+	{ 0x9a08, {							    \
+		{ 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \
+	{ 0x9a0c, {							    \
+		{ 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \
+	{ 0x9a10, {							    \
+		{ 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \
+	{ 0x9a14, {							    \
+		{ 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \
+	{ 0x9a18, {							    \
+		{ 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \
+	{ 0x9a1c, {							    \
+		{ 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \
+	{ 0x9a20, {							    \
+		{ 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \
+	{ 0x9a24, {							    \
+		{ 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \
+	{ 0x9a28, {							    \
+		{ 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \
+	{ 0x9a2c, {							    \
+		{ 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \
+	{ 0x9a30, {							    \
+		{ 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \
+	{ 0x9a34, {							    \
+		{ 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \
+	{ 0x9a38, {							    \
+		{ 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \
+	{ 0x9a3c, {							    \
+		{ 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \
+	{ 0x9a40, {							    \
+		{ 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \
+	{ 0x9a44, {							    \
+		{ 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \
+	{ 0x9a48, {							    \
+		{ 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \
+	{ 0x9a4c, {							    \
+		{ 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \
+	{ 0x9a50, {							    \
+		{ 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \
+	{ 0x9a54, {							    \
+		{ 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \
+	{ 0x9a58, {							    \
+		{ 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \
+	{ 0x9a5c, {							    \
+		{ 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \
+	{ 0x9a60, {							    \
+		{ 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \
+	{ 0x9a64, {							    \
+		{ 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \
+	{ 0x9a68, {							    \
+		{ 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \
+	{ 0x9a6c, {							    \
+		{ 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \
+	{ 0x9a70, {							    \
+		{ 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \
+	{ 0x9a74, {							    \
+		{ 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \
+	{ 0x9a78, {							    \
+		{ 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \
+	{ 0x9a7c, {							    \
+		{ 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \
+	{ 0x9a80, {							    \
+		{ 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \
+	{ 0x9a84, {							    \
+		{ 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \
+	{ 0x9a88, {							    \
+		{ 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \
+	{ 0x9a8c, {							    \
+		{ 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \
+	{ 0x9a90, {							    \
+		{ 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \
+	{ 0x9a94, {							    \
+		{ 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \
+	{ 0x9a98, {							    \
+		{ 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \
+	{ 0x9a9c, {							    \
+		{ 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \
+	{ 0x9aa0, {							    \
+		{ 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \
+	{ 0x9aa4, {							    \
+		{ 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \
+	{ 0x9aa8, {							    \
+		{ 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \
+	{ 0x9aac, {							    \
+		{ 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \
+	{ 0x9ab0, {							    \
+		{ 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \
+	{ 0x9ab4, {							    \
+		{ 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \
+	{ 0x9ab8, {							    \
+		{ 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \
+	{ 0x9abc, {							    \
+		{ 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \
+	{ 0x9ac0, {							    \
+		{ 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \
+	{ 0x9ac4, {							    \
+		{ 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \
+	{ 0x9ac8, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \
+	{ 0x9acc, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \
+	{ 0x9ad0, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \
+	{ 0x9ad4, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \
+	{ 0x9ad8, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9adc, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9ae0, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9ae4, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9ae8, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9aec, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9af0, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9af4, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9af8, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
+	{ 0x9afc, {							    \
+		{ 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
 }
 
 
@@ -1355,7 +1356,7 @@ struct ath5k_ini {
 	{ AR5K_DIAG_SW_5211,	0x00000000 },	\
 	{ AR5K_ADDAC_TEST,	0x00000000 },	\
 	{ AR5K_DEFAULT_ANTENNA,	0x00000000 },	\
-        /* PHY registers */			\
+	/* PHY registers */			\
 	{ AR5K_PHY_AGC,	0x00000000 },		\
 	{ AR5K_PHY(3),	0x2d849093 },		\
 	{ AR5K_PHY(4),	0x7d32e000 },		\
@@ -1670,7 +1671,7 @@ struct ath5k_ini {
 	{ AR5K_PHY_PCDAC_TXPOWER(28), 0x10ff10ff },	\
 	{ AR5K_PHY_PCDAC_TXPOWER(29), 0x10ff10ff },	\
 	{ AR5K_PHY_PCDAC_TXPOWER(30), 0x10ff10ff },	\
-	{ AR5K_PHY_PCDAC_TXPOWER(31),0x10ff10ff },	\
+	{ AR5K_PHY_PCDAC_TXPOWER(31), 0x10ff10ff },	\
 	{ AR5K_PHY(644), 0x0080a333 },		\
 	{ AR5K_PHY(645), 0x00206c10 },		\
 	{ AR5K_PHY(646), 0x009c4060 },		\
@@ -1757,7 +1758,7 @@ struct ath5k_ini {
 
 /* RF 5112 Initial BB Gain settings */
 #define AR5K_RF5112_BBGAIN_INI {		\
- 	{ AR5K_BB_GAIN(0), 0x00000000 },	\
+	{ AR5K_BB_GAIN(0), 0x00000000 },	\
 	{ AR5K_BB_GAIN(1), 0x00000001 },	\
 	{ AR5K_BB_GAIN(2), 0x00000002 },	\
 	{ AR5K_BB_GAIN(3), 0x00000003 },	\
@@ -1828,7 +1829,7 @@ struct ath5k_ar5210_ini_mode{
 	u32 mode_base, mode_turbo;
 };
 
-#define AR5K_AR5210_INI_MODE(hal, _aifs) {				\
+#define AR5K_AR5210_INI_MODE(hal, _aifs) {			\
 	{ AR5K_SLOT_TIME,					\
 	    AR5K_INIT_SLOT_TIME,				\
 	    AR5K_INIT_SLOT_TIME_TURBO },			\
@@ -1922,9 +1923,9 @@ struct ath5k_ar5212_ini_mode {
 #define AR5K_INI_FLAG_BOTH	(AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112)
 
 #define AR5K_AR5212_INI_MODE {							\
-	{ 0x0030, AR5K_INI_FLAG_511X, {						\
-		{ 0, },								\
-		{ 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 }	\
+	{ 0x0030, AR5K_INI_FLAG_511X, {					       \
+		{ 0, },							       \
+		{ 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \
 	} },									\
 	{ 0x1040, AR5K_INI_FLAG_511X, {						\
 		{ 0, },								\
@@ -2011,7 +2012,7 @@ struct ath5k_ar5212_ini_mode {
 		{ 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 }	\
 	} },									\
 	{ 0x9858, AR5K_INI_FLAG_511X, {						\
- 		{ 0, },								\
+		{ 0, },								\
 		{ 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e }	\
 	} },									\
 	{ 0x9860, AR5K_INI_FLAG_511X, {						\