commit a26f2991cbe2904ae658396caa605a0770091b41 Author: Jiri Slaby Date: Thu Jun 21 11:40:56 2007 +0200 rename ath_hal to ath_hw diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 2a9f98d..935b8fe 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -122,7 +122,7 @@ static struct ieee80211_ops ath_hw_ops = { /* * Read from a device register */ -static inline u32 ath_hw_reg_read(struct ath_hal *hw, u16 reg) +static inline u32 ath_hw_reg_read(struct ath_hw *hw, u16 reg) { return readl(hw->ah_sh + reg); } @@ -130,7 +130,7 @@ static inline u32 ath_hw_reg_read(struct ath_hal *hw, u16 reg) /* * Write to a device register */ -static inline void ath_hw_reg_write(struct ath_hal *hw, u32 val, u16 reg) +static inline void ath_hw_reg_write(struct ath_hw *hw, u32 val, u16 reg) { writel(val, hw->ah_sh + reg); } @@ -144,7 +144,7 @@ static inline void ath_hw_reg_write(struct ath_hal *hw, u32 val, u16 reg) * Return 1 if there is an interrupt for us, or 0 if there is none or if * the device has been removed. */ -static inline int ath_hw_irq_pending(struct ath_hal *hw) +static inline int ath_hw_irq_pending(struct ath_hw *hw) { return ath_hw_reg_read(hw, ATH_HW_IRQ_PENDING) == ATH_HW_IRQ_PENDING_TRUE; } @@ -156,7 +156,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) { struct net_device *dev = dev_id; struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; enum ath5k_int status; int needmark; @@ -263,7 +263,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; - struct ath_hal *ah; + struct ath_hw *ah; enum ath5k_status status; int error = 0, i; diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 97cc7cc..aa3b8c3 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -957,7 +957,7 @@ struct ath5k_capabilities { #define AR5K_MAX_GPIO 10 #define AR5K_MAX_RF_BANKS 8 -struct ath_hal { +struct ath_hw { u32 ah_magic; u16 ah_device; u16 ah_sub_vendor; @@ -1045,161 +1045,161 @@ struct ath_hal { /* * Function pointers */ - bool (*ah_setup_tx_desc)(struct ath_hal *, struct ath_desc *, + bool (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); - bool (*ah_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, + bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); - bool (*ah_fill_tx_desc)(struct ath_hal *, struct ath_desc *, + bool (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); - enum ath5k_status (*ah_proc_tx_desc)(struct ath_hal *, + enum ath5k_status (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); - enum ath5k_status (*ah_proc_rx_desc)(struct ath_hal *, + enum ath5k_status (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); }; /* * Prototypes */ -typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); +typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ath5k_channel *, u_int); /* General Functions */ -u16 ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); -unsigned int ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) ; +u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); +unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ -struct ath_hal *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); -//bool ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial); -//u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip); -const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode); -void ath5k_hw_detach(struct ath_hal *hal); +struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); +//bool ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial); +//u16 ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip); +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); +void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ -bool ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); -//bool ath5k_hw_nic_reset(struct ath_hal *hal, u32 val); +bool ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); +//bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ -bool ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); -enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal); +bool ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); /* DMA Related Functions */ -void ath5k_hw_start_rx(struct ath_hal *hal); -bool ath5k_hw_stop_rx_dma(struct ath_hal *hal); -u32 ath5k_hw_get_rx_buf(struct ath_hal *hal); -void ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr); -bool ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue); -u32 ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr); -bool ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase); +void ath5k_hw_start_rx(struct ath_hw *hal); +bool ath5k_hw_stop_rx_dma(struct ath_hw *hal); +u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); +void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); +bool ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); +bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); /* Interrupt handling */ -bool ath5k_hw_is_intr_pending(struct ath_hal *hal); -bool ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask); -u32 ath5k_hw_get_intr(struct ath_hal *hal); -enum ath5k_int ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask); -void ath5k_hw_radar_alert(struct ath_hal *hal, bool enable); +bool ath5k_hw_is_intr_pending(struct ath_hw *hal); +bool ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask); +u32 ath5k_hw_get_intr(struct ath_hw *hal); +enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); +void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ -bool ath5k_hw_eeprom_is_busy(struct ath_hal *hal); -int ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data); -int ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data); -u16 ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode); -int ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_init(struct ath_hal *hal); -int ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac); -bool ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, enum ieee80211_regdomain *regdomain); -bool ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, enum ath5k_status *status); -bool ath5k_hw_get_capabilities(struct ath_hal *hal); +bool ath5k_hw_eeprom_is_busy(struct ath_hw *hal); +int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data); +int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data); +u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); +int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); +int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); +int ath5k_eeprom_init(struct ath_hw *hal); +int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac); +bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain); +bool ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, enum ath5k_status *status); +bool ath5k_hw_get_capabilities(struct ath_hw *hal); /* Protocol Control Unit Functions */ -void ath5k_hw_set_opmode(struct ath_hal *hal); -void ath5k_hw_set_pcu_config(struct ath_hal *hal); +void ath5k_hw_set_opmode(struct ath_hw *hal); +void ath5k_hw_set_pcu_config(struct ath_hw *hal); /* BSSID Functions */ -void ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac); -bool ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac); -void ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, u16 assoc_id); -bool ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask); +void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); +bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); +void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); +bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); /* Receive start/stop functions */ -void ath5k_hw_start_rx_pcu(struct ath_hal *hal); -void ath5k_hw_stop_pcu_recv(struct ath_hal *hal); +void ath5k_hw_start_rx_pcu(struct ath_hw *hal); +void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); /* RX Filter functions */ -void ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, u32 filter1); -bool ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index); -bool ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index); -u32 ath5k_hw_get_rx_filter(struct ath_hal *hal); -void ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter); +void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); +bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); +u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); +void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); /* Beacon related functions */ -u32 ath5k_hw_get_tsf32(struct ath_hal *hal); -u64 ath5k_hw_get_tsf64(struct ath_hal *hal); -void ath5k_hw_reset_tsf(struct ath_hal *hal); -void ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, u32 interval); -void ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state); -void ath5k_hw_reset_beacon(struct ath_hal *hal); -bool ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr); -void ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statistics); -void ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) ; +u32 ath5k_hw_get_tsf32(struct ath_hw *hal); +u64 ath5k_hw_get_tsf64(struct ath_hw *hal); +void ath5k_hw_reset_tsf(struct ath_hw *hal); +void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); +void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); +void ath5k_hw_reset_beacon(struct ath_hw *hal); +bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); +void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); +void ath5k_hw_proc_mib_event(struct ath_hw *hal, const struct ath5k_node_stats *stats) ; /* ACK/CTS Timeouts */ -bool ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout); -unsigned int ath5k_hw_get_ack_timeout(struct ath_hal *hal); -bool ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout); -unsigned int ath5k_hw_get_cts_timeout(struct ath_hal *hal); +bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); +bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); /* Key table (WEP) functions */ -bool ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher); -u32 ath5k_hw_get_keycache_size(struct ath_hal *hal); -bool ath5k_hw_reset_key(struct ath_hal *hal, u16 entry); -bool ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry); -bool ath5k_hw_set_key(struct ath_hal *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused); -bool ath5k_hw_set_key_lladdr(struct ath_hal *hal, u16 entry, const u8 *mac); +bool ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher); +u32 ath5k_hw_get_keycache_size(struct ath_hw *hal); +bool ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); +bool ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); +bool ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused); +bool ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); /* Queue Control Unit, DFS Control Unit Functions */ -int ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); -bool ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, const struct ath5k_txq_info *queue_info); -bool ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info *queue_info); -bool ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue); -u32 ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time); -unsigned int ath5k_hw_get_slot_time(struct ath_hal *hal); +int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); +bool ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); +bool ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); +bool ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); +unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); /* Hardware Descriptor Functions */ /* RX Descriptor */ -bool ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u32 size, unsigned int flags); +bool ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); /* GPIO Functions */ -void ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state); -bool ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio); -bool ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio); -u32 ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio); -bool ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val); -void ath5k_hw_set_gpio_intr(struct ath_hal *hal, unsigned int gpio, u32 interrupt_level); +void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); +bool ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); +bool ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); +u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); +bool ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); +void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); /* Regulatory Domain/Channels Setup */ unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); -bool ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags); -bool ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); -u16 ath5k_get_regdomain(struct ath_hal *hal); +bool ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags); +bool ath_hal_init_channels(struct ath_hw *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); +u16 ath5k_get_regdomain(struct ath_hw *hal); /* PHY/RF access functions */ -bool ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel); u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel); -bool ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ath5k_channel *channel); bool ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan); -bool ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_phy_disable(struct ath_hal *hal); -void ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant); -unsigned int ath5k_hw_get_def_antenna(struct ath_hal *hal); +bool ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_phy_disable(struct ath_hw *hal); +void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); +unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 first, u32 col, bool set); -u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal); -bool ath5k_hw_rfregs_gain_readback(struct ath_hal *hal); -s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal); -bool ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); -bool ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); -bool ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); -void ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode); -bool ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq); -enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal); +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal); +bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal); +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal); +bool ath5k_hw_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); +bool ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); +bool ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); +void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode); +bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ -void ath5k_hw_dump_state(struct ath_hal *hal); -enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; -bool ath5k_hw_set_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; -bool ath5k_hw_query_pspoll_support(struct ath_hal *hal); -bool ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, u16 assoc_id); -bool ath5k_hw_disable_pspoll(struct ath_hal *hal); +void ath5k_hw_dump_state(struct ath_hw *hal); +enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; +bool ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; +bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); +bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); +bool ath5k_hw_disable_pspoll(struct ath_hw *hal); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 1aba99b..a1473a1 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -78,33 +78,33 @@ static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -static bool ath5k_hw_nic_reset(struct ath_hal *, u32); -static bool ath5k_hw_nic_wakeup(struct ath_hal *, u16, bool); -static u16 ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); -static bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, +static bool ath5k_hw_nic_reset(struct ath_hw *, u32); +static bool ath5k_hw_nic_wakeup(struct ath_hw *, u16, bool); +static u16 ath5k_hw_radio_revision(struct ath_hw *, enum ath5k_chip); +static bool ath5k_hw_txpower(struct ath_hw *, struct ath5k_channel *, unsigned int); -static bool ath5k_hw_setup_4word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_setup_xr_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_fill_4word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *); -static bool ath5k_hw_setup_2word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_fill_2word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); /* @@ -156,7 +156,7 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; * TODO: Left here for combatibility, change it in ath5k */ u16 /*TODO: Is this really hardware dependent ?*/ -ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, +ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble) { const struct ath5k_rate *rate; @@ -222,7 +222,7 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * TODO:Left here for combatibility, change it in at5k */ unsigned int/*TODO:Fix this */ -ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) +ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) { switch(hal->ah_version){ case AR5K_AR5212: @@ -277,7 +277,7 @@ ath5k_hw_rtcopy(struct ath5k_rate_table *dst, const struct ath5k_rate_table *src /* * Read from a device register */ -static inline u32 ath5k_hw_reg_read(struct ath_hal *hal, u16 reg) +static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg) { return readl(hal->ah_sh + reg); } @@ -285,7 +285,7 @@ static inline u32 ath5k_hw_reg_read(struct ath_hal *hal, u16 reg) /* * Write to a device register */ -static inline void ath5k_hw_reg_write(struct ath_hal *hal, u32 val, u16 reg) +static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg) { writel(val, hal->ah_sh + reg); } @@ -314,7 +314,7 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) * Check if a register write has been completed */ static bool -ath5k_hw_register_timeout(struct ath_hal *hal, u32 reg, u32 flag, +ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, u32 val, bool is_set) { int i; @@ -344,10 +344,10 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u32 reg, u32 flag, /* * Check if the device is supported and initialize the needed structs */ -struct ath_hal * +struct ath_hw * ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) { - struct ath_hal *hal = NULL; + struct ath_hw *hal = NULL; u8 mac[ETH_ALEN]; u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ int i; @@ -372,7 +372,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) } /*If we passed the test malloc a hal struct*/ - hal = kzalloc(sizeof(struct ath_hal), GFP_KERNEL); + hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); if (hal == NULL) { *status = AR5K_ENOMEM; AR5K_PRINT("out of memory\n"); @@ -568,7 +568,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) * Bring up MAC + PHY Chips */ static bool -ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) +ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) { u32 turbo, mode, clock; @@ -699,7 +699,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) * Get the PHY Chip revision */ static u16 -ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) +ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip) { int i; u32 srev; @@ -750,7 +750,7 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) * TODO:Limit this per chipset */ const struct ath5k_rate_table * -ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode) +ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) { AR5K_TRACE; @@ -776,7 +776,7 @@ ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode) * Free the hal struct */ void -ath5k_hw_detach(struct ath_hal *hal) +ath5k_hw_detach(struct ath_hw *hal) { AR5K_TRACE; @@ -798,7 +798,7 @@ ath5k_hw_detach(struct ath_hal *hal) * Main reset function */ bool -ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, +ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -1383,7 +1383,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, * Reset chipset */ static bool -ath5k_hw_nic_reset(struct ath_hal *hal, u32 val) +ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) { bool ret = false; u32 mask = val ? val : ~0; @@ -1431,7 +1431,7 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u32 val) * Sleep control */ bool -ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, +ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration) { u32 staid; @@ -1502,7 +1502,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, * TODO:Remove ? */ enum ath5k_power_mode -ath5k_hw_get_power_mode(struct ath_hal *hal) +ath5k_hw_get_power_mode(struct ath_hw *hal) { AR5K_TRACE; return hal->ah_power_mode; @@ -1523,7 +1523,7 @@ ath5k_hw_get_power_mode(struct ath_hal *hal) * Start DMA receive */ void -ath5k_hw_start_rx(struct ath_hal *hal) +ath5k_hw_start_rx(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXE); @@ -1533,7 +1533,7 @@ ath5k_hw_start_rx(struct ath_hal *hal) * Stop DMA receive */ bool -ath5k_hw_stop_rx_dma(struct ath_hal *hal) +ath5k_hw_stop_rx_dma(struct ath_hw *hal) { int i; @@ -1555,7 +1555,7 @@ ath5k_hw_stop_rx_dma(struct ath_hal *hal) * Get the address of the RX Descriptor */ u32 -ath5k_hw_get_rx_buf(struct ath_hal *hal) +ath5k_hw_get_rx_buf(struct ath_hw *hal) { return AR5K_REG_READ(AR5K_RXDP); } @@ -1564,7 +1564,7 @@ ath5k_hw_get_rx_buf(struct ath_hal *hal) * Set the address of the RX Descriptor */ void -ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr) +ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) { AR5K_TRACE; @@ -1581,7 +1581,7 @@ ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr) * (see also QCU/DCU functions) */ bool -ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue) +ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) { u32 tx_queue; @@ -1638,7 +1638,7 @@ ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue) +ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) { int i = 100, pending; u32 tx_queue; @@ -1698,7 +1698,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue) * (see also QCU/DCU functions) */ u32 -ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue) +ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) { u16 tx_reg; AR5K_TRACE; @@ -1732,7 +1732,7 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr) +ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) { u16 tx_reg; AR5K_TRACE; @@ -1776,7 +1776,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr) * Update tx trigger level */ bool -ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) +ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) { u32 trigger_level, imr; bool status = false; @@ -1826,7 +1826,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) * Check if we have pending interrupts */ bool -ath5k_hw_is_intr_pending(struct ath_hal *hal) +ath5k_hw_is_intr_pending(struct ath_hw *hal) { AR5K_TRACE; return AR5K_REG_READ(AR5K_INTPEND) == true ? true : false; @@ -1836,7 +1836,7 @@ ath5k_hw_is_intr_pending(struct ath_hal *hal) * Get interrupt mask (ISR) */ bool -ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask) +ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) { u32 data; @@ -1905,7 +1905,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask) * TODO: Remove ? */ u32 -ath5k_hw_get_intr(struct ath_hal *hal) +ath5k_hw_get_intr(struct ath_hw *hal) { AR5K_TRACE; return hal->ah_imr; @@ -1915,7 +1915,7 @@ ath5k_hw_get_intr(struct ath_hal *hal) * Set interrupt mask */ enum ath5k_int -ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) +ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) { enum ath5k_int old_mask, int_mask; @@ -1972,7 +1972,7 @@ ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) * Enalbe HW radar detection */ void -ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) +ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) { AR5K_TRACE; @@ -2025,7 +2025,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) * Check if eeprom is busy */ bool -ath5k_hw_eeprom_is_busy(struct ath_hal *hal) +ath5k_hw_eeprom_is_busy(struct ath_hw *hal) { AR5K_TRACE; return AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? true : false; @@ -2035,7 +2035,7 @@ ath5k_hw_eeprom_is_busy(struct ath_hal *hal) * Read from eeprom */ int -ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data) +ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) { u32 status, timeout; @@ -2071,7 +2071,7 @@ ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data) * Write to eeprom - currently disabled, use at your own risk */ int -ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data) +ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) { #if 0 u32 status, timeout; @@ -2119,7 +2119,7 @@ ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data) } u16 -ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode) +ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) { u16 val; @@ -2147,7 +2147,7 @@ ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode) * Read antenna infos from eeprom */ int -ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode) +ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 o = *offset; @@ -2206,7 +2206,7 @@ ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode) * Read supported modes from eeprom */ int -ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode) +ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 o = *offset; @@ -2290,7 +2290,7 @@ ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode) * Initialize eeprom & capabilities structs */ int -ath5k_eeprom_init(struct ath_hal *hal) +ath5k_eeprom_init(struct ath_hw *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 offset; @@ -2486,7 +2486,7 @@ ath5k_eeprom_init(struct ath_hal *hal) * Read the MAC address from eeprom */ int -ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) +ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) { u32 total, offset; u16 data; @@ -2522,7 +2522,7 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) * Read/Write refulatory domain */ bool -ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, +ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain) { u16 ee_regdomain; @@ -2553,7 +2553,7 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, * Use the above to write a new regulatory domain */ bool -ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, +ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, enum ath5k_status *status) { enum ieee80211_regdomain ieee_regdomain; @@ -2574,7 +2574,7 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, * Fill the capabilities struct */ bool -ath5k_hw_get_capabilities(struct ath_hal *hal) +ath5k_hw_get_capabilities(struct ath_hw *hal) { u16 ee_header; @@ -2651,7 +2651,7 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) * Set Operation mode */ void -ath5k_hw_set_opmode(struct ath_hal *hal) +ath5k_hw_set_opmode(struct ath_hw *hal) { u32 pcu_reg, beacon_reg, low_id, high_id; @@ -2705,7 +2705,7 @@ ath5k_hw_set_opmode(struct ath_hal *hal) } void /*TODO: Get rid of this, clean up the driver code, only set_opmode is needed*/ -ath5k_hw_set_pcu_config(struct ath_hal *hal) +ath5k_hw_set_pcu_config(struct ath_hw *hal) { AR5K_TRACE; ath5k_hw_set_opmode(hal); @@ -2719,7 +2719,7 @@ ath5k_hw_set_pcu_config(struct ath_hal *hal) * Get station id */ void -ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac) +ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) { AR5K_TRACE; memcpy(mac, hal->ah_sta_id, ETH_ALEN); @@ -2729,7 +2729,7 @@ ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac) * Set station id */ bool -ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac) +ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac) { u32 low_id, high_id; @@ -2750,7 +2750,7 @@ ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac) * Set BSSID */ void -ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, +ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id) { u32 low_id, high_id; @@ -2789,7 +2789,7 @@ ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, * Set BSSID mask on 5212 */ bool -ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask) +ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) { u32 low_id, high_id; AR5K_TRACE; @@ -2815,7 +2815,7 @@ ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask) * Start receive on PCU */ void -ath5k_hw_start_rx_pcu(struct ath_hal *hal) +ath5k_hw_start_rx_pcu(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); @@ -2825,7 +2825,7 @@ ath5k_hw_start_rx_pcu(struct ath_hal *hal) * Stop receive on PCU */ void -ath5k_hw_stop_pcu_recv(struct ath_hal *hal) +ath5k_hw_stop_pcu_recv(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); @@ -2839,7 +2839,7 @@ ath5k_hw_stop_pcu_recv(struct ath_hal *hal) * Set multicast filter */ void -ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, +ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1) { AR5K_TRACE; @@ -2852,7 +2852,7 @@ ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, * Set multicast filter by index */ bool -ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index) +ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) { AR5K_TRACE; @@ -2872,7 +2872,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index) * Clear Multicast filter by index */ bool -ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index) +ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) { AR5K_TRACE; @@ -2892,7 +2892,7 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index) * Get current rx filter */ u32 -ath5k_hw_get_rx_filter(struct ath_hal *hal) +ath5k_hw_get_rx_filter(struct ath_hw *hal) { u32 data, filter = 0; @@ -2917,7 +2917,7 @@ ath5k_hw_get_rx_filter(struct ath_hal *hal) * Set rx filter */ void -ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter) +ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) { u32 data = 0; @@ -2966,7 +2966,7 @@ ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter) * Get a 32bit TSF */ u32 -ath5k_hw_get_tsf32(struct ath_hal *hal) +ath5k_hw_get_tsf32(struct ath_hw *hal) { AR5K_TRACE; return AR5K_REG_READ(AR5K_TSF_L32); @@ -2976,7 +2976,7 @@ ath5k_hw_get_tsf32(struct ath_hal *hal) * Get the full 64bit TSF */ u64 -ath5k_hw_get_tsf64(struct ath_hal *hal) +ath5k_hw_get_tsf64(struct ath_hw *hal) { u64 tsf = AR5K_REG_READ(AR5K_TSF_U32); AR5K_TRACE; @@ -2988,7 +2988,7 @@ ath5k_hw_get_tsf64(struct ath_hal *hal) * Force a TSF reset */ void -ath5k_hw_reset_tsf(struct ath_hal *hal) +ath5k_hw_reset_tsf(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_ENABLE_BITS(AR5K_BEACON, @@ -2999,7 +2999,7 @@ ath5k_hw_reset_tsf(struct ath_hal *hal) * Initialize beacon timers */ void -ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, +ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval) { u32 timer1, timer2, timer3; @@ -3047,7 +3047,7 @@ ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, * Set beacon timers */ void -ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state) +ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state) { u32 cfp_period, next_cfp, dtim, interval, next_beacon; @@ -3173,7 +3173,7 @@ ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state * Reset beacon timers */ void -ath5k_hw_reset_beacon(struct ath_hal *hal) +ath5k_hw_reset_beacon(struct ath_hw *hal) { AR5K_TRACE; /* @@ -3195,7 +3195,7 @@ ath5k_hw_reset_beacon(struct ath_hal *hal) * TODO: This function's name is misleading, rename */ bool -ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) +ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) { bool ret; int i; @@ -3241,7 +3241,7 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) * Update mib counters (statistics) */ void -ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statistics) +ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics) { AR5K_TRACE; /* Read-And-Clear */ @@ -3261,7 +3261,7 @@ ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statis } void /*Unimplemented*/ -ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) +ath5k_hw_proc_mib_event(struct ath_hw *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; } @@ -3274,7 +3274,7 @@ ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stat * Set ACK timeout on PCU */ bool -ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout) +ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), @@ -3291,7 +3291,7 @@ ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout) * Read the ACK timeout from PCU */ unsigned int -ath5k_hw_get_ack_timeout(struct ath_hal *hal) +ath5k_hw_get_ack_timeout(struct ath_hw *hal) { AR5K_TRACE; return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), @@ -3302,7 +3302,7 @@ ath5k_hw_get_ack_timeout(struct ath_hal *hal) * Set CTS timeout on PCU */ bool -ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout) +ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), @@ -3319,7 +3319,7 @@ ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout) * Read CTS timeout from PCU */ unsigned int -ath5k_hw_get_cts_timeout(struct ath_hal *hal) +ath5k_hw_get_cts_timeout(struct ath_hw *hal) { AR5K_TRACE; return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), @@ -3334,7 +3334,7 @@ ath5k_hw_get_cts_timeout(struct ath_hal *hal) * Return which ciphers are supported by hw */ bool -ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) +ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher) { AR5K_TRACE; /* @@ -3350,7 +3350,7 @@ ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) * Get key cache size */ u32 -ath5k_hw_get_keycache_size(struct ath_hal *hal) +ath5k_hw_get_keycache_size(struct ath_hw *hal) { AR5K_TRACE; return AR5K_KEYCACHE_SIZE; @@ -3360,7 +3360,7 @@ ath5k_hw_get_keycache_size(struct ath_hal *hal) * Reset encryption key */ bool -ath5k_hw_reset_key(struct ath_hal *hal, u16 entry) +ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) { int i; @@ -3382,7 +3382,7 @@ ath5k_hw_reset_key(struct ath_hal *hal, u16 entry) * Check if a key entry is valid */ bool -ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry) +ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) { AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); @@ -3401,7 +3401,7 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry) * Set encryption key */ bool -ath5k_hw_set_key(struct ath_hal *hal, u16 entry, +ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused) { int i; @@ -3449,7 +3449,7 @@ ath5k_hw_set_key(struct ath_hal *hal, u16 entry, } bool -ath5k_hw_set_key_lladdr(struct ath_hal *hal, u16 entry, +ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) { u32 low_id, high_id; @@ -3486,7 +3486,7 @@ Queue Control Unit, DFS Control Unit Functions * Initialize a transmit queue */ int -ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, +ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info) { unsigned int queue; @@ -3564,7 +3564,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, * Setup a transmit queue */ bool -ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, +ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info) { AR5K_TRACE; @@ -3590,7 +3590,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, * Get properties for a specific transmit queue */ bool -ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info *queue_info) +ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info) { AR5K_TRACE; memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); @@ -3601,7 +3601,7 @@ ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info * Set a transmit queue inactive */ bool -ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue) +ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3618,7 +3618,7 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue) * Set DFS params for a transmit queue */ bool -ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue) +ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) { u32 cw_min, cw_max, retry_lg, retry_sh; struct ath5k_txq_info *tq = &hal->ah_txq[queue]; @@ -3838,7 +3838,7 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue) * for a specific queue [5211+] */ u32 -ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue) { +ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3857,7 +3857,7 @@ ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue) { * Set slot time */ bool -ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time) +ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time) { AR5K_TRACE; if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) @@ -3876,7 +3876,7 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time) * Get slot time */ unsigned int -ath5k_hw_get_slot_time(struct ath_hal *hal) +ath5k_hw_get_slot_time(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) @@ -3899,7 +3899,7 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) * Initialize the 2-word tx descriptor on 5210/5211 */ static bool -ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) @@ -3996,7 +3996,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Initialize the 4-word tx descriptor on 5212 */ static bool -ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) @@ -4081,7 +4081,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Initialize a 4-word XR tx descriptor on 5212 */ static bool -ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3) { @@ -4116,7 +4116,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Fill the 2-word tx descriptor on 5210/5211 */ static bool -ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4145,7 +4145,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * XXX: Added an argument *last_desc -need revision */ static bool -ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { @@ -4177,7 +4177,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Proccess the tx status descriptor on 5210/5211 */ static enum ath5k_status -ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) +ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4236,7 +4236,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) * Proccess a tx descriptor on 5212 */ static enum ath5k_status -ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) +ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4329,7 +4329,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) * Initialize an rx descriptor */ bool -ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags) { struct ath5k_rx_desc *rx_desc; @@ -4365,7 +4365,7 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, * Proccess the rx status descriptor on 5210/5211 */ static enum ath5k_status -ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_old_rx_status *rx_status; @@ -4440,7 +4440,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, * Proccess the rx status descriptor on 5212 */ static enum ath5k_status -ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_new_rx_status *rx_status; @@ -4527,7 +4527,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, * Set led state */ void -ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) +ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) { u32 led; /*5210 has different led mode handling*/ @@ -4586,7 +4586,7 @@ ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) * Set GPIO outputs */ bool -ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio) +ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4603,7 +4603,7 @@ ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio) * Set GPIO inputs */ bool -ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio) +ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4620,7 +4620,7 @@ ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio) * Get GPIO state */ u32 -ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio) +ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4635,7 +4635,7 @@ ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio) * Set GPIO state */ bool -ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val) +ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) { u32 data; AR5K_TRACE; @@ -4658,7 +4658,7 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val) * Initialize the GPIO interrupt (RFKill switch) */ void -ath5k_hw_set_gpio_intr(struct ath_hal *hal, unsigned int gpio, +ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level) { u32 data; @@ -4754,7 +4754,7 @@ ath_hal_ieee2mhz(unsigned int chan, u_int flags) * Check if a channel is supported */ bool -ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags) +ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags) { /* Check if the channel is in our supported range */ if (flags & CHANNEL_2GHZ) { @@ -4775,7 +4775,7 @@ ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags) * also left here temporarily for combatibility. */ bool -ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, +ath_hal_init_channels(struct ath_hw *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended) { @@ -4911,7 +4911,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ } u16 -ath5k_get_regdomain(struct ath_hal *hal) +ath5k_get_regdomain(struct ath_hw *hal) { u16 regdomain; enum ieee80211_regdomain ieee_regdomain; @@ -4945,7 +4945,7 @@ ath5k_get_regdomain(struct ath_hal *hal) * Set a channel on the radio chip */ bool -ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel) { bool ret; @@ -5008,7 +5008,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) * Set channel on RF5110 */ bool -ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ath5k_channel *channel) { u32 data; @@ -5056,7 +5056,7 @@ ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athch * Set channel on 5111 */ bool -ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel) { unsigned int ieee_channel, ath_channel; u32 data0, data1, clock; @@ -5100,7 +5100,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) * Set channel on 5112 */ bool -ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ath5k_channel *channel) { u32 data, data0, data1, data2; u16 c; @@ -5148,7 +5148,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) * Perform a PHY calibration */ bool -ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ +ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ath5k_channel *channel){ bool ret; @@ -5163,7 +5163,7 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ * Perform a PHY calibration on RF5110 */ bool -ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) { bool ret = true; u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; @@ -5312,7 +5312,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) * Perform a PHY calibration on RF5111/5112 */ bool -ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) { u32 i_pwr, q_pwr; s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; @@ -5360,7 +5360,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) } bool -ath5k_hw_phy_disable(struct ath_hal *hal) +ath5k_hw_phy_disable(struct ath_hw *hal) { AR5K_TRACE; /*Just a try M.F.*/ @@ -5369,7 +5369,7 @@ ath5k_hw_phy_disable(struct ath_hal *hal) } void /*TODO:Boundary check*/ -ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant) +ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant) { AR5K_TRACE; /*Just a try M.F.*/ @@ -5378,7 +5378,7 @@ ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant) } unsigned int -ath5k_hw_get_def_antenna(struct ath_hal *hal) +ath5k_hw_get_def_antenna(struct ath_hw *hal) { AR5K_TRACE; /*Just a try M.F.*/ @@ -5437,7 +5437,7 @@ ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, } u32 -ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) +ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal) { u32 mix, step; u32 *rf; @@ -5473,7 +5473,7 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) } bool -ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) +ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) { u32 step, mix, level[4]; u32 *rf; @@ -5515,7 +5515,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) } s32 -ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) +ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) { int ret = 0; const struct ath5k_gain_opt *go; @@ -5575,7 +5575,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) * Initialize RF */ bool -ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) { ath5k_rfgain_t *func = NULL; bool ret; @@ -5613,7 +5613,7 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int * Initialize RF5111 */ bool -ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); @@ -5711,7 +5711,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsig * Initialize RF5112 */ bool -ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; unsigned int rf_size; @@ -5806,7 +5806,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsig * doesn't ar5k_rfregs work ? */ void -ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, +ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -5865,7 +5865,7 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsig } bool -ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq) +ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) { int i; @@ -5895,7 +5895,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq) } enum ath5k_rfgain -ath5k_hw_get_rf_gain(struct ath_hal *hal) +ath5k_hw_get_rf_gain(struct ath_hw *hal) { u32 data, type; @@ -5943,7 +5943,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) * Initialize the tx power table (not fully implemented) */ static void -ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_power) +ath5k_txpower_table(struct ath_hw *hal, struct ath5k_channel *channel, s16 max_power) { u16 txpower, *rates; int i, min, max, n; @@ -5981,7 +5981,7 @@ ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_ * Set transmition power */ static bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int txpower) +ath5k_hw_txpower(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; int i; @@ -6039,7 +6039,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, unsigned in } bool -ath5k_hw_set_txpower_limit(struct ath_hal *hal, unsigned int power) +ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) { /*Just a try M.F.*/ struct ath5k_channel *channel = &hal->ah_current_channel; @@ -6057,7 +6057,7 @@ ath5k_hw_set_txpower_limit(struct ath_hal *hal, unsigned int power) \****************/ void /*O.K.*/ -ath5k_hw_dump_state(struct ath_hal *hal) +ath5k_hw_dump_state(struct ath_hw *hal) { #ifdef AR5K_DEBUG #define AR5K_PRINT_REGISTER(_x) \ @@ -6160,7 +6160,7 @@ ath5k_hw_dump_state(struct ath_hal *hal) #endif } -enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, +enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 *result) { @@ -6220,7 +6220,7 @@ enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, } bool -ath5k_hw_set_capability(struct ath_hal *hal, +ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) @@ -6233,7 +6233,7 @@ ath5k_hw_set_capability(struct ath_hal *hal, } bool -ath5k_hw_query_pspoll_support(struct ath_hal *hal) +ath5k_hw_query_pspoll_support(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) @@ -6243,7 +6243,7 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) } bool -ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, +ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id) { AR5K_TRACE; @@ -6258,7 +6258,7 @@ ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, } bool -ath5k_hw_disable_pspoll(struct ath_hal *hal) +ath5k_hw_disable_pspoll(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) {