commit 7c167b519a5822d7df15b612730c515610fcc171 Author: Jiri Slaby Date: Thu Jun 21 12:03:22 2007 +0200 get rid of ath5k_status diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 935b8fe..c37bb0a 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -264,7 +264,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; struct ath_hw *ah; - enum ath5k_status status; int error = 0, i; DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); @@ -273,9 +272,9 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) /* * Attach the hal */ - ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase, &status); - if (ah == NULL) { - error = ENXIO; + ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase); + if (IS_ERR(ah)) { + error = PTR_ERR(ah); goto bad; } sc->sc_ah = ah; diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 55e3df7..01f7d29 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -124,9 +124,6 @@ struct ath_buf { #endif }; -struct ath_hal; -struct ath_desc; - /* * Data transmit queue state. One of these exists for each * hardware transmit queue. Packets sent to us from above @@ -200,7 +197,7 @@ struct ath_softc { size_t sc_desc_len; /* size of TX/RX descriptors */ u16 sc_cachelsz; /* cache line size */ dma_addr_t sc_desc_daddr; /* DMA (physical) address */ - struct ath_hal *sc_ah; /* Atheros HAL */ + struct ath_hw *sc_ah; /* Atheros HAL */ struct ath_ratectrl *sc_rc; /* tx rate control support */ void (*sc_setdefantenna)(struct ath_softc *, u_int); unsigned int sc_invalid : 1, /* disable hardware accesses */ @@ -318,54 +315,54 @@ void ath_sysctl_register(void); void ath_sysctl_unregister(void); #define ath_hal_ciphersupported(_ah, _cipher) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_CIPHER, _cipher, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_CIPHER, _cipher, NULL) == 0) #define ath_hal_getregdomain(_ah, _prd) \ ath5k_hw_get_capability(_ah, AR5K_CAP_REG_DMN, 0, (_prd)) #define ath_hal_getcountrycode(_ah, _pcc) \ (*(_pcc) = (_ah)->ah_country_code) #define ath_hal_tkipsplit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == 0) #define ath_hal_hwphycounters(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == 0) #define ath_hal_hasdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == 0) #define ath_hal_getdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == 0) #define ath_hal_setdiversity(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_DIVERSITY, 1, _v, NULL) #define ath_hal_getdiag(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIAG, 0, _pv) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIAG, 0, _pv) == 0) #define ath_hal_setdiag(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_DIAG, 0, _v, NULL) #define ath_hal_getnumtxqueues(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == 0) #define ath_hal_hasveol(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) #define ath_hal_hastxpowlimit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 0, NULL) == 0) #define ath_hal_settxpowlimit(_ah, _pow) \ ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) #define ath_hal_gettxpowlimit(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == 0) #define ath_hal_getmaxtxpow(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == 0) #define ath_hal_gettpscale(_ah, _scale) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 3, _scale) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 3, _scale) == 0) #define ath_hal_settpscale(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_TXPOW, 3, _v, NULL) #define ath_hal_hastpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == 0) #define ath_hal_gettpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == 0) #define ath_hal_settpc(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_TPC, 1, _v, NULL) #define ath_hal_hasbursting(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) #ifdef notyet #define ath_hal_hasmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == 0) #define ath_hal_getmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == 0) #else #define ath_hal_getmcastkeysearch(_ah) 0 #endif diff --git a/openhal/ath5k.h b/openhal/ath5k.h index aa3b8c3..5fe1004 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -96,22 +96,6 @@ #define howmany(x, y) (((x)+((y)-1))/(y)) /* - * Error codes reported from HAL to the driver - */ -enum ath5k_status { - AR5K_OK = 0, /* Everything went O.K.*/ - AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/ - AR5K_EIO = 2, /* Hardware I/O Error*/ - AR5K_EELOCKED = 3, /* Unable to access EEPROM*/ - AR5K_EEBADSUM = 4, /* Invalid EEPROM checksum*/ - AR5K_EEREAD = 5, /* Unable to get device caps from EEPROM */ - AR5K_EEBADMAC = 6, /* Unable to read MAC address from EEPROM */ - AR5K_EINVAL = 7, /* Invalid parameter to function */ - AR5K_ENOTSUPP = 8, /* Hardware revision not supported */ - AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */ -}; - -/* * Some tuneable values (these should be changeable by the user) */ #define AR5K_TUNE_DMA_BEACON_RESP 2 @@ -1054,10 +1038,9 @@ struct ath_hw { unsigned int, unsigned int); bool (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); - enum ath5k_status (*ah_proc_tx_desc)(struct ath_hw *, + int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); + int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); - enum ath5k_status (*ah_proc_rx_desc)(struct ath_hw *, - struct ath_desc *, u32, struct ath_desc *); }; /* @@ -1069,13 +1052,13 @@ typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ath5k_channel *, u_int); u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ -struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); +struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh); //bool ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial); //u16 ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ -bool ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel); //bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ bool ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); @@ -1106,7 +1089,7 @@ int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_eeprom_init(struct ath_hw *hal); int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac); bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain); -bool ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, enum ath5k_status *status); +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); bool ath5k_hw_get_capabilities(struct ath_hw *hal); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); @@ -1197,8 +1180,8 @@ bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ void ath5k_hw_dump_state(struct ath_hw *hal); -enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; -bool ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); +int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting); bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); bool ath5k_hw_disable_pspoll(struct ath_hw *hal); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index a1473a1..f0e2516 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -92,20 +92,18 @@ static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int); static bool ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hw *, - struct ath_desc *); +static int ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *); static bool ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); static bool ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hw *, +static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); +static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, + struct ath_desc *); +static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hw *, - struct ath_desc *, u32, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hw *, - struct ath_desc *, u32, struct ath_desc *); /* * Supported channels @@ -345,14 +343,13 @@ ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, * Check if the device is supported and initialize the needed structs */ struct ath_hw * -ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) +ath5k_hw_init(u16 device, void *sc, void __iomem *sh) { struct ath_hw *hal = NULL; u8 mac[ETH_ALEN]; u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ - int i; + int i, ret; u32 srev; - *status = AR5K_EINVAL; /*TODO:Use eeprom_magic to verify chipset*/ @@ -366,7 +363,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /*If there wasn't a match, the device is not supported*/ if (mac_version == 255) { - *status = AR5K_ENOTSUPP; + ret = -EOPNOTSUPP; AR5K_PRINTF("device not supported: 0x%04x\n", device); return NULL; } @@ -374,7 +371,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /*If we passed the test malloc a hal struct*/ hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); if (hal == NULL) { - *status = AR5K_ENOMEM; + ret = -ENOMEM; AR5K_PRINT("out of memory\n"); return NULL; } @@ -501,22 +498,22 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) */ if (ath5k_eeprom_init(hal) != 0) { - *status = AR5K_EELOCKED; + ret = -EIO; AR5K_PRINT("unable to init EEPROM\n"); goto failed; } /* Get misc capabilities */ if (ath5k_hw_get_capabilities(hal) != true) { - *status = AR5K_EEREAD; + ret = -EIO; AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", device); goto failed; } /* Get MAC address */ - if ((*status = ath5k_eeprom_read_mac(hal, mac)) != 0) { - *status = AR5K_EEBADMAC; + if (ath5k_eeprom_read_mac(hal, mac)) { + ret = -EIO; AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", device); goto failed; @@ -555,13 +552,11 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) hal->ah_gain.g_active = 1; } - *status = AR5K_OK; - return hal; failed: kfree(hal); - return NULL; + return ERR_PTR(ret); } /* @@ -797,9 +792,8 @@ ath5k_hw_detach(struct ath_hw *hal) /* * Main reset function */ -bool -ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, - struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, + struct ath5k_channel *channel, bool change_channel) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u8 mac[ETH_ALEN]; @@ -809,7 +803,6 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_TRACE; - *status = AR5K_OK; s_seq = 0; s_ant = 1; ee_mode = 0; @@ -840,10 +833,8 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Wakeup the device*/ - if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) { - *status = AR5K_EIO; - return false; - } + if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) + return -EIO; /* * Initialize operating mode @@ -861,8 +852,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, phy = AR5K_INI_PHY_5112; else { AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); - *status = AR5K_EINVAL; - return false; + return -EINVAL; } switch (channel->channel_flags & CHANNEL_MODES) { @@ -895,7 +885,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, case CHANNEL_XR: if (hal->ah_version == AR5K_AR5211) { AR5K_PRINTF("XR mode not available on 5211"); - return false; + return -EINVAL; } mode = AR5K_INI_VAL_XR; freq = AR5K_INI_RFGAIN_5GHZ; @@ -903,8 +893,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, break; default: AR5K_PRINTF("invalid channel: %d\n", channel->freq); - *status = AR5K_EINVAL; - return false; + return -EINVAL; } /* PHY access enable */ @@ -1015,8 +1004,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * This should work for both 5111/5112 */ if (ath5k_hw_rfgain(hal, phy, freq) == false) { - *status = AR5K_EIO; - return false; + return -EIO; } mdelay(1); @@ -1081,8 +1069,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER) == false) { - *status = AR5K_EIO; - return false; + return -EIO; } /* @@ -1090,8 +1077,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * TODO:Does this work on 5211 (5111) ? */ if (ath5k_hw_rfregs(hal, channel, mode) == false) { - *status = AR5K_EINPROGRESS; - return false; + return -EINPROGRESS; } /* @@ -1112,8 +1098,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, break; if (!coef_exp) { - *status = AR5K_EINVAL; - return false; + return -EINVAL; } coef_exp = 14 - (coef_exp - 24); @@ -1244,10 +1229,8 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Set channel and calibrate the PHY */ - if (ath5k_hw_channel(hal, channel) == false) { - *status = AR5K_EIO; - return false; - } + if (ath5k_hw_channel(hal, channel) == false) + return -EIO; /* * Enable the PHY and wait until completion @@ -1277,7 +1260,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_CAL, 0, false) == false) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); - return false; + return -EAGAIN; } /* @@ -1290,7 +1273,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return false; + return -EAGAIN; } /* Wait until the noise floor is calibrated and read the value */ @@ -1309,7 +1292,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return false; + return -EIO; } hal->ah_calibration = false; @@ -1332,8 +1315,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_reset_tx_queue(hal, i) == false) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); - *status = AR5K_EINVAL; - return false; + return -EINVAL; } } @@ -1376,7 +1358,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_REG_DISABLE_BITS(AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); - return true; + return 0; } /* @@ -2497,12 +2479,12 @@ ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) memset(&mac_d, 0, ETH_ALEN); if (ath5k_hw_eeprom_read(hal, 0x20, &data) != 0) - return AR5K_EIO; + return -EIO; for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { if (ath5k_hw_eeprom_read(hal, offset, &data) != 0) - return AR5K_EIO; + return -EIO; total += data; mac_d[octet + 1] = data & 0xff; @@ -2513,7 +2495,7 @@ ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) memcpy(mac, mac_d, ETH_ALEN); if ((!total) || total == (3 * 0xffff)) - return AR5K_EINVAL; + return -EINVAL; return 0; } @@ -2552,22 +2534,16 @@ ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, /* * Use the above to write a new regulatory domain */ -bool -ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, - enum ath5k_status *status) +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain) { enum ieee80211_regdomain ieee_regdomain; ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); - if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true){ - *status = AR5K_OK; - return true; - } - - *status = AR5K_EIO; + if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true) + return 0; - return false; + return -EIO; } /* @@ -4176,8 +4152,8 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, /* * Proccess the tx status descriptor on 5210/5211 */ -static enum ath5k_status -ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) +static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, + struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4187,7 +4163,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Get descriptor status @@ -4229,14 +4205,14 @@ ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return AR5K_OK; + return 0; } /* * Proccess a tx descriptor on 5212 */ -static enum ath5k_status -ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) +static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, + struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4247,7 +4223,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Get descriptor status @@ -4318,7 +4294,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return AR5K_OK; + return 0; } /* @@ -4364,9 +4340,8 @@ ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, /* * Proccess the rx status descriptor on 5210/5211 */ -static enum ath5k_status -ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, - u32 phys_addr, struct ath_desc *next) +static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, + struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_old_rx_status *rx_status; @@ -4374,7 +4349,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Frame receive status @@ -4433,15 +4408,14 @@ ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; } - return AR5K_OK; + return 0; } /* * Proccess the rx status descriptor on 5212 */ -static enum ath5k_status -ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, - u32 phys_addr, struct ath_desc *next) +static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, + struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_new_rx_status *rx_status; struct ath5k_hw_rx_error *rx_err; @@ -4454,7 +4428,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Frame receive status @@ -4513,7 +4487,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } - return AR5K_OK; + return 0; } @@ -6160,9 +6134,9 @@ ath5k_hw_dump_state(struct ath_hw *hal) #endif } -enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, - u32 capability, u32 *result) + u32 capability, u32 *result) { AR5K_TRACE; @@ -6213,23 +6187,19 @@ enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, } no: - return AR5K_EINVAL; + return -EINVAL; yes: - return AR5K_OK; + return 0; } -bool -ath5k_hw_set_capability(struct ath_hw *hal, +int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, - u32 capability, u32 setting, - enum ath5k_status *status) + u32 capability, u32 setting) { AR5K_TRACE; - if (status) - *status = AR5K_OK; - return false; + return 0; } bool