commit fda53aa14f88128d0be6e79f4b2bcbd0d2efad08 Author: Jiri Slaby Date: Thu Jun 21 12:50:48 2007 +0200 involve hw_attach and detach (i.e. we now inits the card) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c37bb0a..2ec4b0c 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -156,7 +156,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) { struct net_device *dev = dev_id; struct ath_softc *sc = dev->priv; - struct ath_hw *ah = sc->sc_ah; + struct ath_hw *ah = sc->ah; enum ath5k_int status; int needmark; @@ -263,23 +263,13 @@ static irqreturn_t ath_intr(int irq, void *dev_id) static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; - struct ath_hw *ah; + struct ath_hw *ah = sc->ah; int error = 0, i; DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); return 0; /* - * Attach the hal - */ - ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase); - if (IS_ERR(ah)) { - error = PTR_ERR(ah); - goto bad; - } - sc->sc_ah = ah; - - /* * Check if the MAC has multi-rate retry support. * We do this by trying to setup a fake extended * descriptor. MAC's that don't have support will @@ -638,11 +628,6 @@ bad2: ath_tx_cleanup(sc); ath_desc_free(sc); #endif -bad: - if (ah) { - ath5k_hw_detach(ah); - } - sc->sc_invalid = 1; return error; } @@ -667,7 +652,6 @@ static void ath_detach(struct ieee80211_hw *hw) // ath_rate_detach(sc->sc_rc); // ath_desc_free(sc); // ath_tx_cleanup(sc); -// ath5k_hw_detach(sc->sc_ah); /* * NB: can't reclaim these until after ieee80211_ifdetach @@ -675,7 +659,6 @@ static void ath_detach(struct ieee80211_hw *hw) * state and potentially want to use them. */ // ath_dynamic_sysctl_unregister(sc); -// ath_rawdev_detach(sc); // unregister_netdev(dev); } @@ -774,7 +757,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, * interrupts until setup is complete. */ sc->sc_invalid = 1; - sc->sc_iobase = mem; + sc->iobase = mem; sc->sc_cachelsz = csz * sizeof(u32); /* convert to bytes */ mutex_init(&sc->lock); spin_lock_init(&sc->sc_txbuflock); @@ -794,9 +777,15 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, goto err_free; } + sc->ah = ath5k_hw_attach(pdev->device, id->driver_data, sc, sc->iobase); + if (IS_ERR(sc->ah)) { + ret = PTR_ERR(sc->ah); + goto err_irq; + } + ret = ath_attach(pdev, hw); if (ret) - goto err_irq; + goto err_ah; dev_info(&pdev->dev, "%s chip found\n", ath_chip_name(id->driver_data)); @@ -804,6 +793,8 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, sc->sc_invalid = 0; return 0; +err_ah: + ath5k_hw_detach(sc->ah); err_irq: free_irq(pdev->irq, sc); err_free: @@ -824,8 +815,9 @@ static void __devexit ath_pci_remove(struct pci_dev *pdev) struct ath_softc *sc = hw->priv; ath_detach(hw); + ath5k_hw_detach(sc->ah); free_irq(pdev->irq, sc); - pci_iounmap(pdev, sc->sc_iobase); + pci_iounmap(pdev, sc->iobase); pci_release_region(pdev, 0); pci_disable_device(pdev); ieee80211_free_hw(hw); @@ -838,7 +830,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) struct ath_softc *sc = hw->priv; if (sc->sc_softled) - ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, 1); + ath5k_hw_set_gpio(sc->ah, sc->sc_ledpin, 1); // ath_stop(hw); pci_save_state(pdev); @@ -872,8 +864,8 @@ static int ath_pci_resume(struct pci_dev *pdev) // ath_init(hw); if (sc->sc_softled) { - ath5k_hw_set_gpio_output(sc->sc_ah, sc->sc_ledpin); - ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, 0); + ath5k_hw_set_gpio_output(sc->ah, sc->sc_ledpin); + ath5k_hw_set_gpio(sc->ah, sc->sc_ledpin, 0); } return 0; diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 01f7d29..decb45a 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -174,11 +174,12 @@ struct ath_txq { } while (0) struct ath_softc { - void __iomem *sc_iobase; /* address of the device */ + void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ // struct net_device_stats sc_devstats; /* device statistics */ struct ath_stats sc_stats; /* private statistics */ struct ieee80211_hw *hw; /* IEEE 802.11 common */ + struct ath_hw *ah; /* Atheros HW */ enum ieee80211_if_types sc_opmode; int sc_regdomain; @@ -197,7 +198,6 @@ struct ath_softc { size_t sc_desc_len; /* size of TX/RX descriptors */ u16 sc_cachelsz; /* cache line size */ dma_addr_t sc_desc_daddr; /* DMA (physical) address */ - struct ath_hw *sc_ah; /* Atheros HAL */ struct ath_ratectrl *sc_rc; /* tx rate control support */ void (*sc_setdefantenna)(struct ath_softc *, u_int); unsigned int sc_invalid : 1, /* disable hardware accesses */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 5fe1004..f40d7ec 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -943,8 +943,6 @@ struct ath5k_capabilities { struct ath_hw { u32 ah_magic; - u16 ah_device; - u16 ah_sub_vendor; void *ah_sc; void __iomem *ah_sh; @@ -1052,16 +1050,14 @@ typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ath5k_channel *, u_int); u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ -struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh); -//bool ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial); -//u16 ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip); +struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel); //bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ -bool ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); /* DMA Related Functions */ void ath5k_hw_start_rx(struct ath_hw *hal); @@ -1080,17 +1076,11 @@ u32 ath5k_hw_get_intr(struct ath_hw *hal); enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ -bool ath5k_hw_eeprom_is_busy(struct ath_hw *hal); -int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data); -int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data); u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_init(struct ath_hw *hal); -int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac); bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain); int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); -bool ath5k_hw_get_capabilities(struct ath_hw *hal); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); void ath5k_hw_set_pcu_config(struct ath_hw *hal); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index f0e2516..8318143 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -78,8 +78,8 @@ static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -static bool ath5k_hw_nic_reset(struct ath_hw *, u32); -static bool ath5k_hw_nic_wakeup(struct ath_hw *, u16, bool); +static int ath5k_hw_nic_reset(struct ath_hw *, u32); +static int ath5k_hw_nic_wakeup(struct ath_hw *, u16, bool); static u16 ath5k_hw_radio_revision(struct ath_hw *, enum ath5k_chip); static bool ath5k_hw_txpower(struct ath_hw *, struct ath5k_channel *, unsigned int); @@ -104,6 +104,10 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); +static int ath5k_hw_get_capabilities(struct ath_hw *); + +static int ath5k_eeprom_init(struct ath_hw *); +static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *); /* * Supported channels @@ -311,9 +315,8 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) /* * Check if a register write has been completed */ -static bool -ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, - u32 val, bool is_set) +static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, + u32 val, bool is_set) { int i; u32 data; @@ -327,10 +330,7 @@ ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, udelay(15); } - if (i <= 0) - return false; - - return true; + return (i <= 0) ? -EAGAIN : 0; } @@ -342,44 +342,26 @@ ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, /* * Check if the device is supported and initialize the needed structs */ -struct ath_hw * -ath5k_hw_init(u16 device, void *sc, void __iomem *sh) +struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, + void __iomem *sh) { - struct ath_hw *hal = NULL; + struct ath_hw *hal; u8 mac[ETH_ALEN]; - u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ - int i, ret; + int ret; u32 srev; /*TODO:Use eeprom_magic to verify chipset*/ - /* - * Check if device is a known one - */ - for (i = 0; i < ARRAY_SIZE(ath5k_known_products); i++) { - if (device == ath5k_known_products[i].device) - mac_version = ath5k_known_products[i].mac_version; - } - - /*If there wasn't a match, the device is not supported*/ - if (mac_version == 255) { - ret = -EOPNOTSUPP; - AR5K_PRINTF("device not supported: 0x%04x\n", device); - return NULL; - } - /*If we passed the test malloc a hal struct*/ hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); if (hal == NULL) { ret = -ENOMEM; AR5K_PRINT("out of memory\n"); - return NULL; + goto err; } hal->ah_sc = sc; hal->ah_sh = sh; - hal->ah_device = device; - hal->ah_sub_vendor = 0; /* XXX unknown?! */ /* * HAL information @@ -447,24 +429,24 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; /* Bring device out of sleep and reset it's units */ - if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true) != true) - goto failed; + ret = ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true); + if (ret) + goto err_free; /* Get MAC, PHY and RADIO revisions */ srev = AR5K_REG_READ(AR5K_SREV); hal->ah_mac_srev = srev; hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); - hal->ah_phy_revision = - AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; - hal->ah_radio_5ghz_revision = - ath5k_hw_radio_revision(hal, AR5K_CHIP_5GHZ); + hal->ah_phy_revision = AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; + hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal, + AR5K_CHIP_5GHZ); if (hal->ah_version == AR5K_AR5210) { hal->ah_radio_2ghz_revision = 0; } else { - hal->ah_radio_2ghz_revision = - ath5k_hw_radio_revision(hal, AR5K_CHIP_2GHZ); + hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal, + AR5K_CHIP_2GHZ); } /* Single chip radio */ @@ -475,8 +457,8 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) if (hal->ah_version == AR5K_AR5210) hal->ah_radio = AR5K_RF5110; else - hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ? - AR5K_RF5111 : AR5K_RF5112; + hal->ah_radio = hal->ah_radio_5ghz_revision < + AR5K_SREV_RAD_5112 ? AR5K_RF5111 : AR5K_RF5112; hal->ah_phy = AR5K_PHY(0); @@ -497,26 +479,26 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) * Get card capabilities, values, ... */ - if (ath5k_eeprom_init(hal) != 0) { - ret = -EIO; + ret = ath5k_eeprom_init(hal); + if (ret) { AR5K_PRINT("unable to init EEPROM\n"); - goto failed; + goto err_free; } /* Get misc capabilities */ - if (ath5k_hw_get_capabilities(hal) != true) { - ret = -EIO; + ret = ath5k_hw_get_capabilities(hal); + if (ret) { AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", - device); - goto failed; + device); + goto err_free; } /* Get MAC address */ - if (ath5k_eeprom_read_mac(hal, mac)) { - ret = -EIO; + ret = ath5k_eeprom_read_mac(hal, mac); + if (ret) { AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", - device); - goto failed; + device); + goto err_free; } ath5k_hw_set_lladdr(hal, mac); @@ -553,19 +535,19 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) } return hal; - - failed: +err_free: kfree(hal); +err: return ERR_PTR(ret); } /* * Bring up MAC + PHY Chips */ -static bool -ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) +static int ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) { u32 turbo, mode, clock; + int ret; turbo = 0; mode = 0; @@ -594,7 +576,7 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) clock |= AR5K_PHY_PLL_40MHZ; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return false; + return -EINVAL; } if (flags & CHANNEL_CCK) { @@ -610,7 +592,7 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) mode |= AR5K_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return false; + return -EINVAL; } if (flags & CHANNEL_TURBO) { @@ -626,20 +608,19 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) else { if (initial == true) { /* ...reset hardware */ - if (ath5k_hw_nic_reset(hal, - AR5K_RESET_CTL_PCI) == false) { + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) { AR5K_PRINT("failed to reset the PCI chipset\n"); - return false; + return -EIO; } mdelay(1); } /* ...wakeup */ - if (ath5k_hw_set_power(hal, - AR5K_PM_AWAKE, true, 0) == false) { + ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); + if (ret) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return false; + return ret; } /* ...enable Atheros turbo mode if requested */ @@ -647,35 +628,35 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE); /* ...reset chipset */ - if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == false) { + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) { AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return false; + return -EIO; } mdelay(1); } /* ...reset chipset and PCI device */ - if (hal->ah_single_chip == false && - ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == false) { + if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal, + AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) { AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); - return false; + return -EIO; } if (hal->ah_version == AR5K_AR5210) udelay(2300); /* ...wakeup */ - if (ath5k_hw_set_power(hal, - AR5K_PM_AWAKE, true, 0) == false) { + ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); + if (ret) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return false; + return ret; } /* ...final warm reset */ - if (ath5k_hw_nic_reset(hal, 0) == false) { + if (ath5k_hw_nic_reset(hal, 0)) { AR5K_PRINT("failed to warm reset the MAC Chip\n"); - return false; + return -EIO; } if (hal->ah_version != AR5K_AR5210){ @@ -687,7 +668,7 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); } - return true; + return 0; } /* @@ -770,8 +751,7 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) /* * Free the hal struct */ -void -ath5k_hw_detach(struct ath_hw *hal) +void ath5k_hw_detach(struct ath_hw *hal) { AR5K_TRACE; @@ -782,9 +762,6 @@ ath5k_hw_detach(struct ath_hw *hal) kfree(hal); } - - - /*******************************\ Reset Functions \*******************************/ @@ -1257,7 +1234,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, false) == false) { + AR5K_PHY_AGCCTL_CAL, 0, false)) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); return -EAGAIN; @@ -1270,7 +1247,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, false) == false) { + AR5K_PHY_AGCCTL_NF, 0, false)) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); return -EAGAIN; @@ -1364,10 +1341,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Reset chipset */ -static bool -ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) +static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) { - bool ret = false; + int ret; u32 mask = val ? val : ~0; AR5K_TRACE; @@ -1412,8 +1388,7 @@ ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) /* * Sleep control */ -bool -ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration) { u32 staid; @@ -1462,21 +1437,20 @@ ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, /* Fail if the chip didn't wake up */ if (i <= 0) - return false; + return -EIO; staid &= ~AR5K_STA_ID1_PWR_SV; break; default: - return false; + return -EINVAL; } - commit: +commit: hal->ah_power_mode = mode; - AR5K_REG_WRITE(AR5K_STA_ID1, staid); - return true; + return 0; } /* @@ -2004,20 +1978,9 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) \*************************/ /* - * Check if eeprom is busy - */ -bool -ath5k_hw_eeprom_is_busy(struct ath_hw *hal) -{ - AR5K_TRACE; - return AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? true : false; -} - -/* * Read from eeprom */ -int -ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) +static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) { u32 status, timeout; @@ -2038,7 +2001,7 @@ ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) - return EIO; + return -EIO; *data = (u16) (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); return 0; @@ -2046,14 +2009,13 @@ ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) udelay(15); } - return ETIMEDOUT; + return -ETIMEDOUT; } /* * Write to eeprom - currently disabled, use at your own risk */ -int -ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) +static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) { #if 0 u32 status, timeout; @@ -2097,7 +2059,7 @@ ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) } #endif AR5K_PRINTF("EEPROM Write is disabled!"); - return ETIMEDOUT; + return -EIO; } u16 @@ -2271,8 +2233,7 @@ ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode) /* * Initialize eeprom & capabilities structs */ -int -ath5k_eeprom_init(struct ath_hw *hal) +static int ath5k_eeprom_init(struct ath_hw *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 offset; @@ -2309,7 +2270,7 @@ ath5k_eeprom_init(struct ath_hw *hal) } if (cksum != AR5K_EEPROM_INFO_CKSUM) { AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); - return AR5K_EEBADSUM; + return -EIO; } #endif @@ -2353,7 +2314,8 @@ ath5k_eeprom_init(struct ath_hw *hal) offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) return ret; AR5K_EEPROM_READ(offset++, val); @@ -2370,7 +2332,8 @@ ath5k_eeprom_init(struct ath_hw *hal) ee->ee_ob[mode][0] = (val >> 3) & 0x7; ee->ee_db[mode][0] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { @@ -2384,7 +2347,8 @@ ath5k_eeprom_init(struct ath_hw *hal) mode = AR5K_EEPROM_MODE_11B; offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) return ret; AR5K_EEPROM_READ(offset++, val); @@ -2392,7 +2356,8 @@ ath5k_eeprom_init(struct ath_hw *hal) ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { @@ -2417,7 +2382,8 @@ ath5k_eeprom_init(struct ath_hw *hal) mode = AR5K_EEPROM_MODE_11G; offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) return ret; AR5K_EEPROM_READ(offset++, val); @@ -2425,7 +2391,8 @@ ath5k_eeprom_init(struct ath_hw *hal) ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { @@ -2467,24 +2434,25 @@ ath5k_eeprom_init(struct ath_hw *hal) /* * Read the MAC address from eeprom */ -int -ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) +static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) { + u8 mac_d[ETH_ALEN]; u32 total, offset; u16 data; - int octet; - u8 mac_d[ETH_ALEN]; + int octet, ret; memset(mac, 0, ETH_ALEN); memset(&mac_d, 0, ETH_ALEN); - if (ath5k_hw_eeprom_read(hal, 0x20, &data) != 0) - return -EIO; + ret = ath5k_hw_eeprom_read(hal, 0x20, &data); + if (ret) + return ret; for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { - if (ath5k_hw_eeprom_read(hal, offset, &data) != 0) - return -EIO; + ret = ath5k_hw_eeprom_read(hal, offset, &data); + if (ret) + return ret; total += data; mac_d[octet + 1] = data & 0xff; @@ -2494,7 +2462,7 @@ ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) memcpy(mac, mac_d, ETH_ALEN); - if ((!total) || total == (3 * 0xffff)) + if (!total || total == 3 * 0xffff) return -EINVAL; return 0; @@ -2549,8 +2517,7 @@ int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain) /* * Fill the capabilities struct */ -bool -ath5k_hw_get_capabilities(struct ath_hw *hal) +static int ath5k_hw_get_capabilities(struct ath_hw *hal) { u16 ee_header; @@ -2616,7 +2583,7 @@ ath5k_hw_get_capabilities(struct ath_hw *hal) else hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; - return true; + return 0; } /*********************************\ @@ -3204,7 +3171,7 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) /*5211/5212*/ ret = ath5k_hw_register_timeout(hal, AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), - AR5K_QCU_STS_FRMPENDCNT, 0, false); + AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true; if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) return false; @@ -5222,7 +5189,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, false) == false) { + AR5K_PHY_AGCCTL_CAL, 0, false)) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); ret = false; @@ -5243,7 +5210,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, false) == false) { + AR5K_PHY_AGCCTL_NF, 0, false)) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); return false;