commit c7386335a5a34b03530adba5f07b2571f23b5f2b Author: Jiri Slaby Date: Sat Jun 23 13:51:55 2007 +0200 remove AR5K_MODEs and AR5K_CHIPs diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 4c6bfcc..08ae745 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -341,13 +341,13 @@ static int ath_getchannels(struct ieee80211_hw *hw) modes[A].rates = sc->rates; modes[A].num_rates = ath_copy_rates(modes[A].rates, - ath5k_hw_get_rate_table(ah, AR5K_MODE_11A)); + ath5k_hw_get_rate_table(ah, MODE_IEEE80211A)); modes[B].rates = &modes[A].rates[modes[A].num_rates]; modes[B].num_rates = ath_copy_rates(modes[B].rates, - ath5k_hw_get_rate_table(ah, AR5K_MODE_11B)); + ath5k_hw_get_rate_table(ah, MODE_IEEE80211B)); modes[G].rates = &modes[B].rates[modes[B].num_rates]; modes[G].num_rates = ath_copy_rates(modes[G].rates, - ath5k_hw_get_rate_table(ah, AR5K_MODE_11G)); + ath5k_hw_get_rate_table(ah, MODE_IEEE80211G)); /* * In debugging mode, enable all channels supported by the chipset diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 1aa8e37..54c1a78 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -13,35 +13,22 @@ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for Atheros Wireless LAN devices. - * - * ar5k is a free replacement of the binary-only HAL used by some drivers - * for Atheros chipsets. While using a different ABI, it tries to be - * source-compatible with the original (non-free) HAL interface. - * - * Many thanks to various contributors who supported the development of - * ar5k with hard work and useful information. And, of course, for all the - * people who encouraged me to continue this work which has been based - * on my initial approach found on http://team.vantronix.net/ar5k/. */ #ifndef _AR5K_H #define _AR5K_H /* Set this to 1 to disable regulatory domain restrictions for channel tests. - * WARNING: This is for debuging only and has side effects (eg. scan takes too long - * and results timeouts). It's also illegal to tune to some of the supported frequencies - * in some countries, so use this at your own risk, you 've been warned. */ + * WARNING: This is for debuging only and has side effects (eg. scan takes too + * long and results timeouts). It's also illegal to tune to some of the + * supported frequencies in some countries, so use this at your own risk, + * you've been warned. */ #define CHAN_DEBUG 1 -/* Uncomment this for debuging (warning that results TOO much output) */ +/* Uncomment this for debuging (warning that it results in TOO much output) */ /*#define AR5K_DEBUG 1 */ +#include #include #include "ath5k_hw.h" @@ -556,22 +543,6 @@ struct ath_desc { #define AR5K_TXDESC_INTREQ 0x0010 #define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ -/* - * 802.11 operating modes... - */ -#define AR5K_MODE_11A 0x01 -#define AR5K_MODE_11B 0x02 -#define AR5K_MODE_11G 0x04 -#define AR5K_MODE_TURBO 0x08 -#define AR5K_MODE_108G 0x10 -#define AR5K_MODE_XR 0x20 -#define AR5K_MODE_ALL (AR5K_MODE_11A | \ - AR5K_MODE_11B | \ - AR5K_MODE_11G | \ - AR5K_MODE_TURBO | \ - AR5K_MODE_108G | \ - AR5K_MODE_XR) - #define AR5K_SLOT_TIME_9 396 #define AR5K_SLOT_TIME_20 880 #define AR5K_SLOT_TIME_MAX 0xffff @@ -606,16 +577,8 @@ struct ath_desc { * Used internaly in OpenHAL (ar5211.c/ar5212.c * for reset_tx_queue). Also see struct struct ieee80211_channel. */ -#define IS_CHAN_XR(_c) \ - ((_c.val & CHANNEL_XR) != 0) - -#define IS_CHAN_B(_c) \ - ((_c.val & CHANNEL_B) != 0) - -enum ath5k_chip{ - AR5K_CHIP_5GHZ = CHANNEL_5GHZ, - AR5K_CHIP_2GHZ = CHANNEL_2GHZ, -}; +#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) +#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) /* * The following structure will be used to map 2GHz channels to @@ -789,7 +752,7 @@ enum ath5k_ant_setting { */ /* - * These are maped to take advantage of some common bits + * These are mapped to take advantage of some common bits * between the MAC chips, to be able to set intr properties * easier. Some of them are not used yet inside OpenHAL. */ @@ -889,7 +852,7 @@ struct ath5k_capabilities { * Supported PHY modes * (ie. CHANNEL_A, CHANNEL_B, ...) */ - u16 cap_mode; + DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); /* * Frequency range (without regulation restrictions) diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 6826e9c..091010b 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -40,7 +40,7 @@ static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ static int ath5k_hw_nic_reset(struct ath_hw *, u32); static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool); -static u16 ath5k_hw_radio_revision(struct ath_hw *, enum ath5k_chip); +static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int); static bool ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int); static bool ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, @@ -369,14 +369,13 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); hal->ah_phy_revision = AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; - hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal, - AR5K_CHIP_5GHZ); + hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ); if (hal->ah_version == AR5K_AR5210) { hal->ah_radio_2ghz_revision = 0; } else { hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal, - AR5K_CHIP_2GHZ); + CHANNEL_2GHZ); } /* Single chip radio */ @@ -593,7 +592,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) * Get the PHY Chip revision */ static u16 -ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip) +ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) { int i; u32 srev; @@ -604,11 +603,11 @@ ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip) /* * Set the radio chip access register */ - switch (chip) { - case AR5K_CHIP_2GHZ: + switch (chan) { + case CHANNEL_2GHZ: AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_2GHZ); break; - case AR5K_CHIP_5GHZ: + case CHANNEL_5GHZ: AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); break; default: @@ -649,19 +648,19 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) AR5K_TRACE; /* Get rate tables */ - if (!(hal->ah_capabilities.cap_mode & mode)) + if (!test_bit(mode, hal->ah_capabilities.cap_mode)) return NULL; switch (mode) { - case AR5K_MODE_11A: + case MODE_IEEE80211A: return &ath5k_rt_11a; - case AR5K_MODE_TURBO: + case MODE_ATHEROS_TURBO: return &ath5k_rt_turbo; - case AR5K_MODE_11B: + case MODE_IEEE80211B: return &ath5k_rt_11b; - case AR5K_MODE_11G: + case MODE_IEEE80211G: return &ath5k_rt_11g; - case AR5K_MODE_XR: + case MODE_ATHEROS_TURBOG: return &ath5k_rt_xr; default: return NULL; @@ -917,7 +916,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (!(channel->val & CHANNEL_B)) { /*Get rate table for this operation mode*/ - rt = ath5k_hw_get_rate_table(hal, AR5K_MODE_11B); + rt = ath5k_hw_get_rate_table(hal, + MODE_IEEE80211B); /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { @@ -939,7 +939,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Get rate table for this operation mode*/ rt = ath5k_hw_get_rate_table(hal, channel->val & CHANNEL_TURBO ? - AR5K_MODE_TURBO : AR5K_MODE_XR); + MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG); /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { @@ -2446,7 +2446,8 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) hal->ah_capabilities.cap_range.range_2ghz_max = 0; /* Set supported modes */ - hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO; + set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); + set_bit(MODE_ATHEROS_TURBO, hal->ah_capabilities.cap_mode); } else { /* * XXX The tranceiver supports frequencies from 4920 to 6100GHz @@ -2467,8 +2468,12 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) hal->ah_capabilities.cap_range.range_5ghz_max = 6100; /* Set supported modes */ - hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO | - (hal->ah_version == AR5K_AR5212 ? AR5K_MODE_XR : 0); + set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); + set_bit(MODE_ATHEROS_TURBO, + hal->ah_capabilities.cap_mode); + if (hal->ah_version == AR5K_AR5212) + set_bit(MODE_ATHEROS_TURBOG, + hal->ah_capabilities.cap_mode); } /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ @@ -2477,10 +2482,12 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) hal->ah_capabilities.cap_range.range_2ghz_max = 2732; if (AR5K_EEPROM_HDR_11B(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; + set_bit(MODE_IEEE80211B, + hal->ah_capabilities.cap_mode); if (AR5K_EEPROM_HDR_11G(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; + set_bit(MODE_IEEE80211G, + hal->ah_capabilities.cap_mode); } }