commit 251729806f557f9fbf5b6aa3e4762fca31cfe10e Author: Jiri Slaby Date: Sat Jun 23 15:01:12 2007 +0200 get rid of AR5K_REG_READ/WRITE macros. add hw as parameter to other macros diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index df71d23..9d0e883 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -252,7 +252,7 @@ static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, u32 data; for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { - data = AR5K_REG_READ(reg); + data = ath5k_hw_reg_read(hal, reg); if ((is_set == true) && (data & flag)) break; else if ((data & flag) == val) @@ -364,11 +364,11 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, goto err_free; /* Get MAC, PHY and RADIO revisions */ - srev = AR5K_REG_READ(AR5K_SREV); + srev = ath5k_hw_reg_read(hal, AR5K_SREV); hal->ah_mac_srev = srev; hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); - hal->ah_phy_revision = AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; + hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff; hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ); if (hal->ah_version == AR5K_AR5210) { @@ -542,7 +542,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) /* ...enable Atheros turbo mode if requested */ if (flags & CHANNEL_TURBO) - AR5K_REG_WRITE(AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE); + ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO); /* ...reset chipset */ if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) { @@ -578,11 +578,11 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) if (hal->ah_version != AR5K_AR5210){ /* ...set the PHY operating mode */ - AR5K_REG_WRITE(AR5K_PHY_PLL, clock); + ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL); udelay(300); - AR5K_REG_WRITE(AR5K_PHY_MODE, mode); - AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); + ath5k_hw_reg_write(hal, mode, AR5K_PHY_MODE); + ath5k_hw_reg_write(hal, turbo, AR5K_PHY_TURBO); } return 0; @@ -605,10 +605,10 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) */ switch (chan) { case CHANNEL_2GHZ: - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_2GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); break; case CHANNEL_5GHZ: - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); break; default: return 0; @@ -617,23 +617,23 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) mdelay(2); /* ...wait until PHY is ready and read the selected radio revision */ - AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16); + ath5k_hw_reg_write(hal, 0x00001c16, AR5K_PHY(0x34)); for (i = 0; i < 8; i++) - AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000); + ath5k_hw_reg_write(hal, 0x00010000, AR5K_PHY(0x20)); if (hal->ah_version == AR5K_AR5210) { - srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf; + srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf; ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; } else { - srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff; + srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff; ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); } /* Reset to the 5GHz mode */ - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); return ret; } @@ -715,16 +715,16 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (hal->ah_version != AR5K_AR5210) { if (change_channel == true) { /*Sequence number for queue 0 -do this for all queues ?*/ - s_seq = AR5K_REG_READ(AR5K_QUEUE_DFS_SEQNUM(0)); + s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0)); /*Default antenna*/ - s_ant = AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); } } /*GPIOs*/ - s_led[0] = AR5K_REG_READ(AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; - s_led[1] = AR5K_REG_READ(AR5K_GPIOCR); - s_led[2] = AR5K_REG_READ(AR5K_GPIODO); + s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; + s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR); + s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO); if (change_channel == true && hal->ah_rf_banks != NULL) ath5k_hw_get_rf_gain(hal); @@ -795,7 +795,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, } /* PHY access enable */ - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); /* * Write initial RF registers on 5211 @@ -824,16 +824,18 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5212_mode[i].mode_register, - ar5212_mode[i].mode_value[off][mode]); + ath5k_hw_reg_write(hal, + ar5212_mode[i].mode_value[off][mode], + (u32)ar5212_mode[i].mode_register); } } /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5211_mode[i].mode_register, - ar5211_mode[i].mode_value[mode]); + ath5k_hw_reg_write(hal, + ar5211_mode[i].mode_value[mode], + (u32)ar5211_mode[i].mode_register); } } @@ -854,8 +856,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (hal->ah_radio == AR5K_RF5112 && ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5212_ini[i].ini_register, - ar5212_ini[i].ini_value); + ath5k_hw_reg_write(hal, + ar5212_ini[i].ini_value, + (u32)ar5212_ini[i].ini_register); } } } @@ -868,8 +871,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5211_ini[i].ini_register, - ar5211_ini[i].ini_value); + ath5k_hw_reg_write(hal, + ar5211_ini[i].ini_value, + (u32)ar5211_ini[i].ini_register); } } /*For 5210*/ @@ -883,13 +887,13 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, switch (ar5210_ini[i].ini_mode) { case AR5K_INI_READ: /* Cleared on read */ - AR5K_REG_READ(ar5210_ini[i].ini_register); + ath5k_hw_reg_read(hal, ar5210_ini[i].ini_register); break; case AR5K_INI_WRITE: default: - AR5K_REG_WRITE(ar5210_ini[i].ini_register, - ar5210_ini[i].ini_value); + ath5k_hw_reg_write(hal, ar5210_ini[i].ini_value, + ar5210_ini[i].ini_register); } } @@ -922,14 +926,16 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { data = AR5K_RATE_DUR(rt->rates[i].rate_code); - AR5K_REG_WRITE(data, - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false)); + ath5k_hw_reg_write(hal, + ath_hal_computetxtime(hal, rt, + 14, rt->rates[i].control_rate, + false), data); if (HAS_SHPREAMBLE(i)) { - AR5K_REG_WRITE(data + - (AR5K_SET_SHORT_PREAMBLE << 2), + ath5k_hw_reg_write(hal, ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false)); + rt->rates[i].control_rate, false), + data + + (AR5K_SET_SHORT_PREAMBLE << 2)); } } @@ -943,24 +949,26 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { - AR5K_REG_WRITE(AR5K_RATE_DUR(rt->rates[i].rate_code), - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false)); + ath5k_hw_reg_write(hal, + ath_hal_computetxtime(hal, rt, + 14, rt->rates[i].control_rate, + false), + AR5K_RATE_DUR(rt->rates[i].rate_code)); } } } /* Fix for first revision of the RF5112 RF chipset */ - if (hal->ah_radio >= AR5K_RF5112 && - hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { - AR5K_REG_WRITE(AR5K_PHY_CCKTXCTL, - AR5K_PHY_CCKTXCTL_WORLD); + if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision< + AR5K_SREV_RAD_5112A) { + ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD, + AR5K_PHY_CCKTXCTL); if (channel->val & CHANNEL_A) data = 0xffb81020; else data = 0xffb80d20; - AR5K_REG_WRITE(AR5K_PHY_FRAME_CTL, data); + ath5k_hw_reg_write(hal, data, AR5K_PHY_FRAME_CTL); } /* @@ -1005,9 +1013,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ds_coef_man = coef_man >> (24 - coef_exp); ds_coef_exp = coef_exp - 16; - AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); - AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); } } @@ -1016,15 +1024,15 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (enable 2111 frequency converter + CCK)*/ if (hal->ah_radio == AR5K_RF5111) { if (channel->val & CHANNEL_B) - AR5K_REG_ENABLE_BITS(AR5K_TXCFG, + AR5K_REG_ENABLE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_B_MODE); else - AR5K_REG_DISABLE_BITS(AR5K_TXCFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_B_MODE); } /* Set antenna mode */ - AR5K_REG_MASKED_BITS(AR5K_PHY(0x44), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44), hal->ah_antenna[ee_mode][0], 0xfffffc06); if (freq == AR5K_INI_RFGAIN_2GHZ) @@ -1033,46 +1041,47 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ant[0] = ant[1] = AR5K_ANT_FIXED_A; - AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_0, - hal->ah_antenna[ee_mode][ant[0]]); - AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_1, - hal->ah_antenna[ee_mode][ant[1]]); + ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]], + AR5K_PHY_ANT_SWITCH_TABLE_0); + ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[1]], + AR5K_PHY_ANT_SWITCH_TABLE_1); /* Commit values from EEPROM */ if (hal->ah_radio == AR5K_RF5111) - AR5K_REG_WRITE_BITS(AR5K_PHY_FRAME_CTL, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_FRAME_CTL, AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); - AR5K_REG_WRITE(AR5K_PHY(0x5a), - AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); + ath5k_hw_reg_write(hal, + AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), + AR5K_PHY(0x5a)); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x11), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11), (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x12), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12), (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x14), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14), (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); - AR5K_REG_WRITE(AR5K_PHY(0x0d), - (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | - (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | - (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | - (ee->ee_tx_frm2xpa_enable[ee_mode])); + ath5k_hw_reg_write(hal, + (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | + (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | + (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | + (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x0a), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a), ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x19), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19), (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x49), 4, 0xffffff01); + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01); - AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | ee->ee_q_cal[ee_mode]); if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - AR5K_REG_WRITE_BITS(AR5K_PHY_GAIN_2GHZ, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ, AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, ee->ee_margin_tx_rx[ee_mode]); } @@ -1080,7 +1089,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, } else { mdelay(1); /* Disable phy and wait */ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); mdelay(1); } @@ -1089,12 +1098,12 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, */ /*DCU/Antenna selection not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_SEQNUM(0), s_seq); - AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, s_ant); + ath5k_hw_reg_write(hal, s_seq, AR5K_QUEUE_DFS_SEQNUM(0)); + ath5k_hw_reg_write(hal, s_ant, AR5K_DEFAULT_ANTENNA); } - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, s_led[0]); - AR5K_REG_WRITE(AR5K_GPIOCR, s_led[1]); - AR5K_REG_WRITE(AR5K_GPIODO, s_led[2]); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, s_led[0]); + ath5k_hw_reg_write(hal, s_led[1], AR5K_GPIOCR); + ath5k_hw_reg_write(hal, s_led[2], AR5K_GPIODO); /* * Misc @@ -1104,14 +1113,14 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ath5k_hw_set_opmode(hal); /*PISR/SISR Not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_PISR, 0xffffffff); + ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR); /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so - * direct write using AR5K_REG_WRITE seems wrong. Test with: - * AR5K_REG_WRITE_BITS(AR5K_RSSI_THR, + * direct write using ath5k_hw_reg_write seems wrong. Test with: + * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); * with different variables and check results compared - * to AR5K_REG_WRITE() */ - AR5K_REG_WRITE(AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES); + * to ath5k_hw_reg_write(hal, ) */ + ath5k_hw_reg_write(hal, AR5K_TUNE_RSSI_THRES, AR5K_RSSI_THR); } /* @@ -1119,9 +1128,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, *(passing dma size not available on 5210) */ if (hal->ah_version != AR5K_AR5210) { - AR5K_REG_WRITE_BITS(AR5K_TXCFG, AR5K_TXCFG_SDMAMR, + AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); - AR5K_REG_WRITE_BITS(AR5K_RXCFG, AR5K_RXCFG_SDMAMW, + AR5K_REG_WRITE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_512B); } @@ -1134,13 +1143,13 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Enable the PHY and wait until completion */ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); /* * 5111/5112 Specific */ if (hal->ah_version != AR5K_AR5210) { - data = AR5K_REG_READ(AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; + data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; data = (channel->val & CHANNEL_CCK) ? ((data << 2) / 22) : (data / 10); @@ -1152,7 +1161,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Enable calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -1165,7 +1174,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Enable noise floor calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -1178,7 +1187,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* Wait until the noise floor is calibrated and read the value */ for (i = 20; i > 0; i--) { mdelay(1); - noise_floor = AR5K_REG_READ(AR5K_PHY_NF); + noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) @@ -1198,9 +1207,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (!(channel->val & CHANNEL_B)) { hal->ah_calibration = true; - AR5K_REG_WRITE_BITS(AR5K_PHY_IQ, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); - AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); } @@ -1210,7 +1219,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { /*No QCU on 5210*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i); + AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i); if (ath5k_hw_reset_tx_queue(hal, i) == false) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); @@ -1242,19 +1251,20 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * Set the 32MHz reference clock on 5212 phy clock sleep register */ if (hal->ah_version == AR5K_AR5212) { - AR5K_REG_WRITE(AR5K_PHY_SCR, AR5K_PHY_SCR_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SLMT, AR5K_PHY_SLMT_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SCAL, AR5K_PHY_SCAL_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SCLOCK, AR5K_PHY_SCLOCK_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SDELAY, AR5K_PHY_SDELAY_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SPENDING, hal->ah_radio == AR5K_RF5111 ? - AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112); + ath5k_hw_reg_write(hal, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR); + ath5k_hw_reg_write(hal, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); + ath5k_hw_reg_write(hal, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL); + ath5k_hw_reg_write(hal, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); + ath5k_hw_reg_write(hal, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); + ath5k_hw_reg_write(hal, hal->ah_radio == AR5K_RF5111 ? + AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112, + AR5K_PHY_SPENDING); } /* * Disable beacons and reset the register */ - AR5K_REG_DISABLE_BITS(AR5K_BEACON, + AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); return 0; @@ -1271,12 +1281,12 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) AR5K_TRACE; /* Read-and-clear RX Descriptor Pointer*/ - AR5K_REG_READ(AR5K_RXDP); + ath5k_hw_reg_read(hal, AR5K_RXDP); /* * Reset the device and wait until success */ - AR5K_REG_WRITE(AR5K_RESET_CTL, val); + ath5k_hw_reg_write(hal, val, AR5K_RESET_CTL); /* Wait at least 128 PCI clocks */ udelay(15); @@ -1298,7 +1308,7 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) * Reset configuration register (for hw byte-swap) */ if ((val & AR5K_RESET_CTL_PCU) == 0) - AR5K_REG_WRITE(AR5K_CFG, AR5K_INIT_CFG); + ath5k_hw_reg_write(hal, AR5K_INIT_CFG, AR5K_CFG); return ret; } @@ -1317,7 +1327,7 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, int i; AR5K_TRACE; - staid = AR5K_REG_READ(AR5K_STA_ID1); + staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1); switch (mode) { case AR5K_PM_AUTO: @@ -1325,16 +1335,17 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, /* fallthrough */ case AR5K_PM_NETWORK_SLEEP: if (set_chip == true) { - AR5K_REG_WRITE(AR5K_SLEEP_CTL, - AR5K_SLEEP_CTL_SLE | sleep_duration); + ath5k_hw_reg_write(hal, + AR5K_SLEEP_CTL_SLE | sleep_duration, + AR5K_SLEEP_CTL); } staid |= AR5K_STA_ID1_PWR_SV; break; case AR5K_PM_FULL_SLEEP: if (set_chip == true) { - AR5K_REG_WRITE(AR5K_SLEEP_CTL, - AR5K_SLEEP_CTL_SLE_SLP); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP, + AR5K_SLEEP_CTL); } staid |= AR5K_STA_ID1_PWR_SV; break; @@ -1343,18 +1354,18 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, if (set_chip == false) goto commit; - AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE_WAKE); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL); for (i = 5000; i > 0; i--) { /* Check if the chip did wake up */ - if ((AR5K_REG_READ(AR5K_PCICFG) & + if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_SPWR_DN) == 0) break; /* Wait a bit and retry */ udelay(200); - AR5K_REG_WRITE(AR5K_SLEEP_CTL, - AR5K_SLEEP_CTL_SLE_WAKE); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, + AR5K_SLEEP_CTL); } /* Fail if the chip didn't wake up */ @@ -1370,7 +1381,7 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, commit: hal->ah_power_mode = mode; - AR5K_REG_WRITE(AR5K_STA_ID1, staid); + ath5k_hw_reg_write(hal, staid, AR5K_STA_ID1); return 0; } @@ -1404,7 +1415,7 @@ void ath5k_hw_start_rx(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXE); + ath5k_hw_reg_write(hal, AR5K_CR_RXE, AR5K_CR); } /* @@ -1416,13 +1427,13 @@ ath5k_hw_stop_rx_dma(struct ath_hw *hal) int i; AR5K_TRACE; - AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXD); + ath5k_hw_reg_write(hal, AR5K_CR_RXD, AR5K_CR); /* * It may take some time to disable the DMA receive unit */ for (i = 2000; - i > 0 && (AR5K_REG_READ(AR5K_CR) & AR5K_CR_RXE) != 0; + i > 0 && (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_RXE) != 0; i--) udelay(10); @@ -1435,7 +1446,7 @@ ath5k_hw_stop_rx_dma(struct ath_hw *hal) u32 ath5k_hw_get_rx_buf(struct ath_hw *hal) { - return AR5K_REG_READ(AR5K_RXDP); + return ath5k_hw_reg_read(hal, AR5K_RXDP); } /* @@ -1447,7 +1458,7 @@ ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) AR5K_TRACE; /*TODO:Shouldn't we check if RX is enabled first ?*/ - AR5K_REG_WRITE(AR5K_RXDP, phys_addr); + ath5k_hw_reg_write(hal, phys_addr, AR5K_RXDP); } /* @@ -1472,7 +1483,7 @@ ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) if (hal->ah_version == AR5K_AR5210) { - tx_queue = AR5K_REG_READ(AR5K_CR); + tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); /* * Set the queue by type on 5210 @@ -1483,29 +1494,27 @@ ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) break; case AR5K_TX_QUEUE_BEACON: tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - AR5K_REG_WRITE(AR5K_BSR, - AR5K_BCR_TQ1V | - AR5K_BCR_BDMAE); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | + AR5K_BCR_BDMAE, AR5K_BSR); break; case AR5K_TX_QUEUE_CAB: tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - AR5K_REG_WRITE(AR5K_BSR, - AR5K_BCR_TQ1FV | - AR5K_BCR_TQ1V | - AR5K_BCR_BDMAE); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | + AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, + AR5K_BSR); break; default: return false; } /* Start queue */ - AR5K_REG_WRITE(AR5K_CR, tx_queue); + ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); } else { /* Return if queue is disabled */ - if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXD, queue)) return false; /* Start queue */ - AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); + AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXE, queue); } return true; @@ -1529,7 +1538,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) return false; if (hal->ah_version == AR5K_AR5210) { - tx_queue = AR5K_REG_READ(AR5K_CR); + tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); /* * Set by queue type @@ -1542,29 +1551,29 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) case AR5K_TX_QUEUE_CAB: /* XXX Fix me... */ tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; - AR5K_REG_WRITE(AR5K_BSR, 0); + ath5k_hw_reg_write(hal, 0, AR5K_BSR); break; default: return false; } /* Stop queue */ - AR5K_REG_WRITE(AR5K_CR, tx_queue); + ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); } else { /* * Schedule TX disable and wait until queue is empty */ - AR5K_REG_WRITE_Q(AR5K_QCU_TXD, queue); + AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXD, queue); /*Check for pending frames*/ do { - pending = AR5K_REG_READ(AR5K_QUEUE_STATUS(queue)) & + pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) & AR5K_QCU_STS_FRMPENDCNT; udelay(100); } while (--i && pending); /* Clear register */ - AR5K_REG_WRITE(AR5K_QCU_TXD, 0); + ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD); } /*TODO: Check for success else return false*/ @@ -1602,7 +1611,7 @@ ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) tx_reg = AR5K_QUEUE_TXDP(queue); } - return AR5K_REG_READ(tx_reg); + return ath5k_hw_reg_read(hal, tx_reg); } /* @@ -1638,14 +1647,14 @@ ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) * the selected queue on QCU for 5211+ * (this won't work if the queue is still active) */ - if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, queue)) return false; tx_reg = AR5K_QUEUE_TXDP(queue); } /* Set descriptor pointer */ - AR5K_REG_WRITE(tx_reg, phys_addr); + ath5k_hw_reg_write(hal, phys_addr, tx_reg); return true; } @@ -1666,7 +1675,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) imr = ath5k_hw_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); /*TODO: Boundary check on trigger_level*/ - trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_TXCFG), + trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TXCFG), AR5K_TXCFG_TXFULL); if (increase == false) { @@ -1680,9 +1689,9 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) * Update trigger level on success */ if (hal->ah_version == AR5K_AR5210) - AR5K_REG_WRITE(AR5K_TRIG_LVL, trigger_level); + ath5k_hw_reg_write(hal, trigger_level, AR5K_TRIG_LVL); else - AR5K_REG_WRITE_BITS(AR5K_TXCFG, + AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_TXFULL, trigger_level); status = true; @@ -1706,7 +1715,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) bool ath5k_hw_is_intr_pending(struct ath_hw *hal) { AR5K_TRACE; - return AR5K_REG_READ(AR5K_INTPEND); + return ath5k_hw_reg_read(hal, AR5K_INTPEND); } /* @@ -1724,7 +1733,7 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) * on 5210 */ if (hal->ah_version == AR5K_AR5210) { - if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) { + if ((data = ath5k_hw_reg_read(hal, AR5K_ISR)) == AR5K_INT_NOCARD) { *interrupt_mask = data; return false; } @@ -1733,7 +1742,7 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) /* * Read interrupt status from the Read-And-Clear shadow register */ - data = AR5K_REG_READ(AR5K_RAC_PISR); + data = ath5k_hw_reg_read(hal, AR5K_RAC_PISR); /* * Get abstract interrupt mask (HAL-compatible) @@ -1789,7 +1798,7 @@ ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) * Disable card interrupts to prevent any race conditions * (they will be re-enabled afterwards). */ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_DISABLE); + ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); old_mask = hal->ah_imr; @@ -1816,20 +1825,20 @@ ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) if (hal->ah_version != AR5K_AR5210) { if (new_mask & AR5K_INT_FATAL) { int_mask |= AR5K_IMR_HIUERR; - AR5K_REG_ENABLE_BITS(AR5K_SIMR2, + AR5K_REG_ENABLE_BITS(hal, AR5K_SIMR2, AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR); } } - AR5K_REG_WRITE(AR5K_PIMR, int_mask); + ath5k_hw_reg_write(hal, int_mask, AR5K_PIMR); /* Store new interrupt mask */ hal->ah_imr = new_mask; /* ..re-enable interrupts */ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); + ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); return old_mask; } @@ -1847,7 +1856,7 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) */ /*Disable interupts*/ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_DISABLE); + ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); /* * Set the RXPHY interrupt to be able to detect @@ -1855,29 +1864,29 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) */ if (hal->ah_version == AR5K_AR5210) { if (enable == true) { - AR5K_REG_ENABLE_BITS(AR5K_IMR, + AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); } else { - AR5K_REG_DISABLE_BITS(AR5K_IMR, + AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); } } else { /*Also set AR5K_PHY_RADAR register on 5111/5112*/ if (enable == true) { - AR5K_REG_WRITE(AR5K_PHY_RADAR, - AR5K_PHY_RADAR_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_PIMR, - AR5K_IMR_RXPHY); + ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_ENABLE, + AR5K_PHY_RADAR); + AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, + AR5K_IMR_RXPHY); } else { - AR5K_REG_WRITE(AR5K_PHY_RADAR, - AR5K_PHY_RADAR_DISABLE); - AR5K_REG_DISABLE_BITS(AR5K_PIMR, - AR5K_IMR_RXPHY); + ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_DISABLE, + AR5K_PHY_RADAR); + AR5K_REG_DISABLE_BITS(hal, AR5K_PIMR, + AR5K_IMR_RXPHY); } } /*Re-enable interrupts*/ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); + ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); } @@ -1899,21 +1908,21 @@ static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) * Initialize EEPROM access */ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE); - (void)AR5K_REG_READ(AR5K_EEPROM_BASE + (4 * offset)); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); + (void)ath5k_hw_reg_read(hal, AR5K_EEPROM_BASE + (4 * offset)); } else { - AR5K_REG_WRITE(AR5K_EEPROM_BASE, offset); - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, + ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_READ); } for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { - status = AR5K_REG_READ(AR5K_EEPROM_STATUS); + status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) return -EIO; *data = (u16) - (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); + (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff); return 0; } udelay(15); @@ -1937,9 +1946,9 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) */ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); } else { - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); } /* @@ -1947,11 +1956,11 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) */ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_EEPROM_BASE + (4 * offset), data); + ath5k_hw_reg_write(hal, data, AR5K_EEPROM_BASE + (4 * offset)); } else { - AR5K_REG_WRITE(AR5K_EEPROM_BASE, offset); - AR5K_REG_WRITE(AR5K_EEPROM_DATA, data); - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); + ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); + ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); } /* @@ -1959,7 +1968,7 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) */ for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { - status = AR5K_REG_READ(AR5K_EEPROM_STATUS); + status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_WRDONE) { if (status & AR5K_EEPROM_STAT_WRERR) return EIO; @@ -2553,14 +2562,14 @@ ath5k_hw_set_opmode(struct ath_hw *hal) */ low_id = AR5K_LOW_ID(hal->ah_sta_id); high_id = AR5K_HIGH_ID(hal->ah_sta_id); - AR5K_REG_WRITE(AR5K_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_STA_ID1, pcu_reg | high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(hal, pcu_reg | high_id, AR5K_STA_ID1); /* * Set Beacon Control Register on 5210 */ if (hal->ah_version == AR5K_AR5210) - AR5K_REG_WRITE(AR5K_BCR, beacon_reg); + ath5k_hw_reg_write(hal, beacon_reg, AR5K_BCR); } /* @@ -2592,8 +2601,8 @@ ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac) low_id = AR5K_LOW_ID(mac); high_id = AR5K_HIGH_ID(mac); - AR5K_REG_WRITE(AR5K_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_STA_ID1, high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(hal, high_id, AR5K_STA_ID1); return true; } @@ -2612,8 +2621,8 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, * Set simple BSSID mask on 5212 */ if (hal->ah_version == AR5K_AR5212) { - AR5K_REG_WRITE(AR5K_BSS_IDM0, 0xfffffff); - AR5K_REG_WRITE(AR5K_BSS_IDM1, 0xfffffff); + ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM1); } /* @@ -2621,9 +2630,9 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, */ low_id = AR5K_LOW_ID(bssid); high_id = AR5K_HIGH_ID(bssid); - AR5K_REG_WRITE(AR5K_BSS_ID0, low_id); - AR5K_REG_WRITE(AR5K_BSS_ID1, high_id | - ((assoc_id & 0x3fff) << AR5K_BSS_ID1_AID_S)); + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_ID0); + ath5k_hw_reg_write(hal, high_id | ((assoc_id & 0x3fff) << + AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); memcpy(&hal->ah_bssid, bssid, ETH_ALEN); if (assoc_id == 0) { @@ -2631,7 +2640,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, return; } - AR5K_REG_WRITE_BITS(AR5K_BEACON, AR5K_BEACON_TIM, + AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM, tim_offset ? tim_offset + 4 : 0); ath5k_hw_enable_pspoll(hal, NULL, 0); @@ -2651,8 +2660,8 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) low_id = AR5K_LOW_ID(mask); high_id = AR5K_HIGH_ID(mask); - AR5K_REG_WRITE(AR5K_BSS_IDM0, low_id); - AR5K_REG_WRITE(AR5K_BSS_IDM1, high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); return true; } else @@ -2670,7 +2679,7 @@ void ath5k_hw_start_rx_pcu(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); + AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); } /* @@ -2680,7 +2689,7 @@ void ath5k_hw_stop_pcu_recv(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); + AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); } /* @@ -2696,8 +2705,8 @@ ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, { AR5K_TRACE; /* Set the multicat filter */ - AR5K_REG_WRITE(AR5K_MCAST_FILTER0, filter0); - AR5K_REG_WRITE(AR5K_MCAST_FILTER1, filter1); + ath5k_hw_reg_write(hal, filter0, AR5K_MCAST_FILTER0); + ath5k_hw_reg_write(hal, filter1, AR5K_MCAST_FILTER1); } /* @@ -2711,10 +2720,10 @@ ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) if (index >= 64) return false; else if (index >= 32) - AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1, + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, (1 << (index - 32))); else - AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0, + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; @@ -2731,10 +2740,10 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) if (index >= 64) return false; else if (index >= 32) - AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1, + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, (1 << (index - 32))); else - AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0, + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; @@ -2749,11 +2758,11 @@ ath5k_hw_get_rx_filter(struct ath_hw *hal) u32 data, filter = 0; AR5K_TRACE; - filter = AR5K_REG_READ(AR5K_RX_FILTER); + filter = ath5k_hw_reg_read(hal, AR5K_RX_FILTER); /*Radar detection for 5212*/ if (hal->ah_version == AR5K_AR5212) { - data = AR5K_REG_READ(AR5K_PHY_ERR_FIL); + data = ath5k_hw_reg_read(hal, AR5K_PHY_ERR_FIL); if (data & AR5K_PHY_ERR_FIL_RADAR) filter |= AR5K_RX_FILTER_PHYRADAR; @@ -2795,18 +2804,18 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) /*Zero length DMA*/ if (data) - AR5K_REG_ENABLE_BITS(AR5K_RXCFG, + AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); else - AR5K_REG_DISABLE_BITS(AR5K_RXCFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); /*Write RX Filter register*/ - AR5K_REG_WRITE(AR5K_RX_FILTER, filter & 0xff); + ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER); /*Write PHY error filter register on 5212*/ if (hal->ah_version == AR5K_AR5212) - AR5K_REG_WRITE(AR5K_PHY_ERR_FIL, data); + ath5k_hw_reg_write(hal, data, AR5K_PHY_ERR_FIL); } @@ -2821,7 +2830,7 @@ u32 ath5k_hw_get_tsf32(struct ath_hw *hal) { AR5K_TRACE; - return AR5K_REG_READ(AR5K_TSF_L32); + return ath5k_hw_reg_read(hal, AR5K_TSF_L32); } /* @@ -2830,10 +2839,10 @@ ath5k_hw_get_tsf32(struct ath_hw *hal) u64 ath5k_hw_get_tsf64(struct ath_hw *hal) { - u64 tsf = AR5K_REG_READ(AR5K_TSF_U32); + u64 tsf = ath5k_hw_reg_read(hal, AR5K_TSF_U32); AR5K_TRACE; - return AR5K_REG_READ(AR5K_TSF_L32) | (tsf << 32); + return ath5k_hw_reg_read(hal, AR5K_TSF_L32) | (tsf << 32); } /* @@ -2843,7 +2852,7 @@ void ath5k_hw_reset_tsf(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_ENABLE_BITS(AR5K_BEACON, + AR5K_REG_ENABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_RESET_TSF); } @@ -2885,14 +2894,14 @@ ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, * Set the beacon register and enable all timers. * (next beacon, DMA beacon, software beacon, ATIM window time) */ - AR5K_REG_WRITE(AR5K_TIMER0, next_beacon); - AR5K_REG_WRITE(AR5K_TIMER1, timer1); - AR5K_REG_WRITE(AR5K_TIMER2, timer2); - AR5K_REG_WRITE(AR5K_TIMER3, timer3); + ath5k_hw_reg_write(hal, next_beacon, AR5K_TIMER0); + ath5k_hw_reg_write(hal, timer1, AR5K_TIMER1); + ath5k_hw_reg_write(hal, timer2, AR5K_TIMER2); + ath5k_hw_reg_write(hal, timer3, AR5K_TIMER3); - AR5K_REG_WRITE(AR5K_BEACON, interval & - (AR5K_BEACON_PERIOD | AR5K_BEACON_RESET_TSF | - AR5K_BEACON_ENABLE)); + ath5k_hw_reg_write(hal, interval & (AR5K_BEACON_PERIOD | + AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE), + AR5K_BEACON); } /* @@ -2936,16 +2945,16 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * state->bs_interval; - AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, + AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_CFP_PERIOD, cfp_period); - AR5K_REG_WRITE(AR5K_CFP_DUR, state->bs_cfp_max_duration); - AR5K_REG_WRITE(AR5K_TIMER2, - (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); + ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD); + ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR); + ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period : + next_cfp)) << 3, AR5K_TIMER2); } else { /* Disable PCF mode */ - AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); } @@ -2953,17 +2962,16 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * /* * Enable the beacon timer register */ - AR5K_REG_WRITE(AR5K_TIMER0, state->bs_next_beacon); + ath5k_hw_reg_write(hal, state->bs_next_beacon, AR5K_TIMER0); /* * Start the beacon timers */ - AR5K_REG_WRITE(AR5K_BEACON, - (AR5K_REG_READ(AR5K_BEACON) &~ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_BEACON) &~ (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, - AR5K_BEACON_PERIOD)); + AR5K_BEACON_PERIOD), AR5K_BEACON); /* * Write new beacon miss threshold, if it appears to be valid @@ -2972,7 +2980,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * setting value to a largest value and seeing which values register. */ - AR5K_REG_WRITE_BITS(AR5K_RSSI_THR, + AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); /* @@ -2980,7 +2988,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * XXX: Didn't find this in 5210 code but since this register * exists also in ar5k's 5210 headers i leave it as common code. */ - AR5K_REG_WRITE_BITS(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, + AR5K_REG_WRITE_BITS(hal, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, (state->bs_sleep_duration - 3) << 3); /* @@ -3003,21 +3011,20 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * next_beacon = interval == dtim ? state->bs_next_dtim: state->bs_next_beacon; - AR5K_REG_WRITE(AR5K_SLEEP0, + ath5k_hw_reg_write(hal, AR5K_REG_SM((state->bs_next_dtim - 3) << 3, AR5K_SLEEP0_NEXT_DTIM) | AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | AR5K_SLEEP0_ENH_SLEEP_EN | - AR5K_SLEEP0_ASSUME_DTIM); + AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); - AR5K_REG_WRITE(AR5K_SLEEP1, - AR5K_REG_SM((next_beacon - 3) << 3, + ath5k_hw_reg_write(hal, AR5K_REG_SM((next_beacon - 3) << 3, AR5K_SLEEP1_NEXT_TIM) | - AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO)); + AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); - AR5K_REG_WRITE(AR5K_SLEEP2, + ath5k_hw_reg_write(hal, AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | - AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER)); + AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); } } @@ -3031,15 +3038,15 @@ ath5k_hw_reset_beacon(struct ath_hw *hal) /* * Disable beacon timer */ - AR5K_REG_WRITE(AR5K_TIMER0, 0); + ath5k_hw_reg_write(hal, 0, AR5K_TIMER0); /* * Disable some beacon register values */ - AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_BEACON, AR5K_BEACON_PERIOD); + ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON); } /* @@ -3061,16 +3068,16 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) * Control Register and Beacon Status Register. */ for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && - (AR5K_REG_READ(AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && - (AR5K_REG_READ(AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); + (ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && + (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); /* Timeout... */ if (i <= 0) { /* * Re-schedule the beacon queue */ - AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, phys_addr); - AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE); + ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR); return false; } @@ -3082,7 +3089,7 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true; - if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) return false; } @@ -3097,18 +3104,18 @@ ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statist { AR5K_TRACE; /* Read-And-Clear */ - statistics->ackrcv_bad += AR5K_REG_READ(AR5K_ACK_FAIL); - statistics->rts_bad += AR5K_REG_READ(AR5K_RTS_FAIL); - statistics->rts_good += AR5K_REG_READ(AR5K_RTS_OK); - statistics->fcs_bad += AR5K_REG_READ(AR5K_FCS_FAIL); - statistics->beacons += AR5K_REG_READ(AR5K_BEACON_CNT); + statistics->ackrcv_bad += ath5k_hw_reg_read(hal, AR5K_ACK_FAIL); + statistics->rts_bad += ath5k_hw_reg_read(hal, AR5K_RTS_FAIL); + statistics->rts_good += ath5k_hw_reg_read(hal, AR5K_RTS_OK); + statistics->fcs_bad += ath5k_hw_reg_read(hal, AR5K_FCS_FAIL); + statistics->beacons += ath5k_hw_reg_read(hal, AR5K_BEACON_CNT); /* Reset profile count registers on 5212*/ if (hal->ah_version == AR5K_AR5212) { - AR5K_REG_WRITE(AR5K_PROFCNT_TX, 0); - AR5K_REG_WRITE(AR5K_PROFCNT_RX, 0); - AR5K_REG_WRITE(AR5K_PROFCNT_RXCLR, 0); - AR5K_REG_WRITE(AR5K_PROFCNT_CYCLE, 0); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_TX); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RX); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RXCLR); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_CYCLE); } } @@ -3133,7 +3140,7 @@ ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) hal->ah_turbo) <= timeout) return false; - AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, + AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; @@ -3146,7 +3153,7 @@ unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), hal->ah_turbo)); } @@ -3161,7 +3168,7 @@ ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) hal->ah_turbo) <= timeout) return false; - AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, + AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; @@ -3174,7 +3181,7 @@ unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), hal->ah_turbo)); } @@ -3210,12 +3217,12 @@ ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) - AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), 0); + ath5k_hw_reg_write(hal, 0, AR5K_KEYTABLE_OFF(entry, i)); /* Set NULL encryption on non-5210*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), - AR5K_KEYTABLE_TYPE_NULL); + ath5k_hw_reg_write(hal, AR5K_KEYTABLE_TYPE_NULL, + AR5K_KEYTABLE_TYPE(entry)); return false; /*????*/ } @@ -3232,7 +3239,7 @@ ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) /* * Check the validation flag at the end of the entry */ - if (AR5K_REG_READ(AR5K_KEYTABLE_MAC1(entry)) & + if (ath5k_hw_reg_read(hal, AR5K_KEYTABLE_MAC1(entry)) & AR5K_KEYTABLE_VALID) return true; @@ -3285,7 +3292,7 @@ ath5k_hw_set_key(struct ath_hw *hal, u16 entry, } for (i = 0; i < ARRAY_SIZE(key_v); i++) - AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), key_v[i]); + ath5k_hw_reg_write(hal, key_v[i], AR5K_KEYTABLE_OFF(entry, i)); return ath5k_hw_set_key_lladdr(hal, entry, mac); } @@ -3311,8 +3318,8 @@ ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID; } - AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id); - AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_KEYTABLE_MAC0(entry)); + ath5k_hw_reg_write(hal, high_id, AR5K_KEYTABLE_MAC1(entry)); return true; } @@ -3466,7 +3473,7 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; struct ath5k_ar5210_ini_mode ar5210_mode[] = - AR5K_AR5210_INI_MODE(hal->ah_aifs + tq->tqi_aifs); + AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs); AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3485,9 +3492,10 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) * Write initial mode register settings */ for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++) - AR5K_REG_WRITE((u32)ar5210_mode[i].mode_register, - hal->ah_turbo == true ? - ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base); + ath5k_hw_reg_write(hal, hal->ah_turbo == true ? + ar5210_mode[i].mode_turbo : + ar5210_mode[i].mode_base, + (u32)ar5210_mode[i].mode_register); } /* @@ -3537,23 +3545,25 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) /*No QCU/DCU [5210]*/ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_NODCU_RETRY_LMT, + ath5k_hw_reg_write(hal, (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_NODCU_RETRY_LMT_SLG_RETRY) | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_NODCU_RETRY_LMT_SSH_RETRY) | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) - | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY)); + | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), + AR5K_NODCU_RETRY_LMT); } else { /*QCU/DCU [5211+]*/ - AR5K_REG_WRITE(AR5K_QUEUE_DFS_RETRY_LIMIT(queue), + ath5k_hw_reg_write(hal, AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_DCU_RETRY_LMT_SLG_RETRY) | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_DCU_RETRY_LMT_SSH_RETRY) | AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | - AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY)); + AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), + AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); /*===Rest is also for QCU/DCU only [5211+]===*/ @@ -3561,58 +3571,58 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) * Set initial content window (cw_min/cw_max) * and arbitrated interframe space (aifs)... */ - AR5K_REG_WRITE(AR5K_QUEUE_DFS_LOCAL_IFS(queue), + ath5k_hw_reg_write(hal, AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, - AR5K_DCU_LCL_IFS_AIFS)); + AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue)); /* * Set misc registers */ - AR5K_REG_WRITE(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_DCU_EARLY); + ath5k_hw_reg_write(hal, AR5K_QCU_MISC_DCU_EARLY, + AR5K_QUEUE_MISC(queue)); if (tq->tqi_cbr_period) { - AR5K_REG_WRITE(AR5K_QUEUE_CBRCFG(queue), - AR5K_REG_SM(tq->tqi_cbr_period, - AR5K_QCU_CBRCFG_INTVAL) | + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_cbr_period, + AR5K_QCU_CBRCFG_INTVAL) | AR5K_REG_SM(tq->tqi_cbr_overflow_limit, - AR5K_QCU_CBRCFG_ORN_THRES)); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_CBRCFG_ORN_THRES), + AR5K_QUEUE_CBRCFG(queue)); + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_CBR); if (tq->tqi_cbr_overflow_limit) - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_CBR_THRES_ENABLE); } if (tq->tqi_ready_time) { - AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), - AR5K_REG_SM(tq->tqi_ready_time, - AR5K_QCU_RDYTIMECFG_INTVAL) | - AR5K_QCU_RDYTIMECFG_ENABLE); + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time, + AR5K_QCU_RDYTIMECFG_INTVAL) | + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); } if (tq->tqi_burst_time) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_CHANNEL_TIME(queue), - AR5K_REG_SM(tq->tqi_burst_time, + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time, AR5K_DCU_CHAN_TIME_DUR) | - AR5K_DCU_CHAN_TIME_ENABLE); + AR5K_DCU_CHAN_TIME_ENABLE, + AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_TXE); } } if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), - AR5K_DCU_MISC_POST_FR_BKOFF_DIS); + ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, + AR5K_QUEUE_DFS_MISC(queue)); } if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), - AR5K_DCU_MISC_BACKOFF_FRAG); + ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG, + AR5K_QUEUE_DFS_MISC(queue)); } /* @@ -3620,38 +3630,39 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) */ switch (tq->tqi_type) { case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_DBA_GT | AR5K_QCU_MISC_CBREXP_BCN | AR5K_QCU_MISC_BCN_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << AR5K_DCU_MISC_ARBLOCK_CTL_S) | AR5K_DCU_MISC_POST_FR_BKOFF_DIS | AR5K_DCU_MISC_BCN_ENABLE); - AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), + ath5k_hw_reg_write(hal, ((AR5K_TUNE_BEACON_INTERVAL - (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | - AR5K_QCU_RDYTIMECFG_ENABLE); + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); break; case AR5K_TX_QUEUE_CAB: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_DBA_GT | AR5K_QCU_MISC_CBREXP | AR5K_QCU_MISC_CBREXP_BCN); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << AR5K_DCU_MISC_ARBLOCK_CTL_S)); break; case AR5K_TX_QUEUE_UAPSD: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_CBREXP); break; @@ -3663,13 +3674,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) /* * Enable tx queue in the secondary interrupt mask registers */ - AR5K_REG_WRITE(AR5K_SIMR0, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXOK) | - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXDESC)); - AR5K_REG_WRITE(AR5K_SIMR1, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR1_QCU_TXERR)); - AR5K_REG_WRITE(AR5K_SIMR2, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR0_QCU_TXOK) | + AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); } return true; @@ -3706,10 +3718,10 @@ ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time) return false; if (hal->ah_version == AR5K_AR5210) - AR5K_REG_WRITE(AR5K_SLOT_TIME, - ath5k_hw_htoclock(slot_time, hal->ah_turbo)); + ath5k_hw_reg_write(hal, ath5k_hw_htoclock(slot_time, + hal->ah_turbo), AR5K_SLOT_TIME); else - AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); + ath5k_hw_reg_write(hal, slot_time, AR5K_DCU_GBL_IFS_SLOT); return true; } @@ -3722,10 +3734,10 @@ ath5k_hw_get_slot_time(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) - return (ath5k_hw_clocktoh(AR5K_REG_READ(AR5K_SLOT_TIME) & + return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo)); else - return AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff; + return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff; } @@ -4377,10 +4389,10 @@ ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) /*Reset led status*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_DISABLE_BITS(AR5K_PCICFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); else - AR5K_REG_DISABLE_BITS(AR5K_PCICFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LED); /* @@ -4417,9 +4429,9 @@ ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) /*Write new status to the register*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led); else - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led_5210); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led_5210); } /* @@ -4432,9 +4444,8 @@ ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) if (gpio > AR5K_NUM_GPIO) return false; - AR5K_REG_WRITE(AR5K_GPIOCR, - (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) - | AR5K_GPIOCR_OUT(gpio)); + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ + AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); return true; } @@ -4449,9 +4460,8 @@ ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) if (gpio > AR5K_NUM_GPIO) return false; - AR5K_REG_WRITE(AR5K_GPIOCR, - (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) - | AR5K_GPIOCR_IN(gpio)); + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ + AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); return true; } @@ -4467,7 +4477,7 @@ ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) return 0xffffffff; /* GPIO input magic */ - return (((AR5K_REG_READ(AR5K_GPIODI) & + return (((ath5k_hw_reg_read(hal, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) & 0x1); } @@ -4484,12 +4494,12 @@ ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) return false; /* GPIO output magic */ - data = AR5K_REG_READ(AR5K_GPIODO); + data = ath5k_hw_reg_read(hal, AR5K_GPIODO); data &= ~(1 << gpio); data |= (val&1) << gpio; - AR5K_REG_WRITE(AR5K_GPIODO, data); + ath5k_hw_reg_write(hal, data, AR5K_GPIODO); return true; } @@ -4510,18 +4520,18 @@ ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, /* * Set the GPIO interrupt */ - data = (AR5K_REG_READ(AR5K_GPIOCR) & + data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) & ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); - AR5K_REG_WRITE(AR5K_GPIOCR, - interrupt_level ? data : (data | AR5K_GPIOCR_INT_SELH)); + ath5k_hw_reg_write(hal, interrupt_level ? data : + (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); hal->ah_imr |= AR5K_IMR_GPIO; /* Enable GPIO interrupts */ - AR5K_REG_ENABLE_BITS(AR5K_PIMR, AR5K_IMR_GPIO); + AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, AR5K_IMR_GPIO); } @@ -4688,8 +4698,8 @@ ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) * Set the channel and wait */ data = ath5k_hw_rf5110_chan2athchan(channel); - AR5K_PHY_WRITE(0x27, data); - AR5K_PHY_WRITE(0x30, 0); + AR5K_PHY_WRITE(hal, 0x27, data); + AR5K_PHY_WRITE(hal, 0x30, 0); udelay(1000); return true; @@ -4762,8 +4772,8 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) | (clock << 1) | (1 << 10) | 1; } - AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); - AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); + AR5K_PHY_WRITE(hal, 0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); + AR5K_PHY_WRITE(hal, 0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); return true; } @@ -4810,8 +4820,8 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; - AR5K_PHY_WRITE(0x27, data & 0xff); - AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); + AR5K_PHY_WRITE(hal, 0x27, data & 0xff); + AR5K_PHY_WRITE(hal, 0x36, (data >> 8) & 0x7f); return true; } @@ -4842,23 +4852,23 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) unsigned int i; #define AGC_DISABLE { \ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGC, \ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, \ AR5K_PHY_AGC_DISABLE); \ udelay(10); \ } #define AGC_ENABLE { \ - AR5K_REG_DISABLE_BITS(AR5K_PHY_AGC, \ + AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, \ AR5K_PHY_AGC_DISABLE); \ } /* * Disable beacons and RX/TX queues, wait */ - AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW_5210, + AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210, AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); - beacon = AR5K_REG_READ(AR5K_BEACON_5210); - AR5K_REG_WRITE(AR5K_BEACON_5210, beacon & ~AR5K_BEACON_ENABLE); + beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210); + ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); udelay(2300); @@ -4871,7 +4881,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Activate PHY and wait */ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); udelay(1000); AGC_ENABLE; @@ -4884,31 +4894,28 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) */ /* Remember normal state */ - phy_sig = AR5K_REG_READ(AR5K_PHY_SIG); - phy_agc = AR5K_REG_READ(AR5K_PHY_AGCCOARSE); - phy_sat = AR5K_REG_READ(AR5K_PHY_ADCSAT); + phy_sig = ath5k_hw_reg_read(hal, AR5K_PHY_SIG); + phy_agc = ath5k_hw_reg_read(hal, AR5K_PHY_AGCCOARSE); + phy_sat = ath5k_hw_reg_read(hal, AR5K_PHY_ADCSAT); /* Update radio registers */ - AR5K_REG_WRITE(AR5K_PHY_SIG, - (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | - AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR)); + ath5k_hw_reg_write(hal, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | + AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); - AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, - (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | + ath5k_hw_reg_write(hal, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | AR5K_PHY_AGCCOARSE_LO)) | AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | - AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO)); + AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); - AR5K_REG_WRITE(AR5K_PHY_ADCSAT, - (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | + ath5k_hw_reg_write(hal, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | AR5K_PHY_ADCSAT_THR)) | AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | - AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR)); + AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); udelay(20); AGC_DISABLE; - AR5K_REG_WRITE(AR5K_PHY_RFSTG, AR5K_PHY_RFSTG_DISABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); AGC_ENABLE; udelay(1000); @@ -4916,7 +4923,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Enable calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -4927,9 +4934,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) } /* Reset to normal state */ - AR5K_REG_WRITE(AR5K_PHY_SIG, phy_sig); - AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, phy_agc); - AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat); + ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG); + ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE); + ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT); if (ret == false) return false; @@ -4937,7 +4944,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Enable noise floor calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -4950,7 +4957,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* Wait until the noise floor is calibrated */ for (i = 20; i > 0; i--) { udelay(1000); - noise_floor = AR5K_REG_READ(AR5K_PHY_NF); + noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) @@ -4970,9 +4977,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Re-enable RX/TX and beacons */ - AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW_5210, + AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW_5210, AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); - AR5K_REG_WRITE(AR5K_BEACON_5210, beacon); + ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210); #undef AGC_ENABLE #undef AGC_DISABLE @@ -4991,14 +4998,14 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) AR5K_TRACE; if (hal->ah_calibration == false || - AR5K_REG_READ(AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) + ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) goto done; hal->ah_calibration = false; - iq_corr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_CORR); - i_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_I); - q_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_Q); + iq_corr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_CORR); + i_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_I); + q_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_Q); i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; q_coffd = q_pwr >> 6; @@ -5009,22 +5016,21 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; /* Commit new IQ value */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); done: /* Start noise floor calibration */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); /* Request RF gain */ if (channel->val & CHANNEL_5GHZ) { - AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE, - AR5K_REG_SM(hal->ah_txpower.txp_max, + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txpower.txp_max, AR5K_PHY_PAPD_PROBE_TXPOWER) | - AR5K_PHY_PAPD_PROBE_TX_NEXT); + AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } @@ -5036,7 +5042,7 @@ ath5k_hw_phy_disable(struct ath_hw *hal) { AR5K_TRACE; /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); return true; } @@ -5046,7 +5052,7 @@ ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant) AR5K_TRACE; /*Just a try M.F.*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant); + ath5k_hw_reg_write(hal, ant, AR5K_DEFAULT_ANTENNA); } unsigned int @@ -5055,7 +5061,7 @@ ath5k_hw_get_def_antenna(struct ath_hw *hal) AR5K_TRACE; /*Just a try M.F.*/ if (hal->ah_version != AR5K_AR5210) - return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + return ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); return false; /*XXX: What do we return for 5210 ?*/ } @@ -5373,7 +5379,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un /* Write RF values */ for (i = 0; i < rf_size; i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]); + ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register); } return true; @@ -5467,7 +5473,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un /* Write RF values */ for (i = 0; i < rf_size; i++) - AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); + ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register); return true; } @@ -5529,8 +5535,8 @@ ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un for (i = 0; i < ARRAY_SIZE(rf); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)rf[i].rf_register, - rf[i].rf_value[freq]); + ath5k_hw_reg_write(hal, rf[i].rf_value[freq], + (u32)rf[i].rf_register); } hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; @@ -5559,8 +5565,8 @@ ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ath5k_rfg[i].rfg_register, - ath5k_rfg[i].rfg_value[phy][freq]); + ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[phy][freq], + (u32)ath5k_rfg[i].rfg_register); } return true; @@ -5580,7 +5586,7 @@ ath5k_hw_get_rf_gain(struct ath_hw *hal) if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) goto done; - data = AR5K_REG_READ(AR5K_PHY_PAPD_PROBE); + data = ath5k_hw_reg_read(hal, AR5K_PHY_PAPD_PROBE); if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; @@ -5675,36 +5681,34 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned * Write TX power values */ for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { - AR5K_REG_WRITE(AR5K_PHY_PCDAC_TXPOWER(i), - ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) - | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ) - ); + ath5k_hw_reg_write(hal, + ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) + | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ), + AR5K_PHY_PCDAC_TXPOWER(i)); } - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE1, - AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16) - | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(3, 24) | + AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | + AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE2, - AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16) - | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(7, 24) | + AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | + AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE3, - AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16) - | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(10, 24) | + AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | + AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE4, - AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) - | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(14, 24) | + AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | + AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); if (hal->ah_txpower.txp_tpc == true) { - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX, - AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | - AR5K_TUNE_MAX_TXPOWER); + ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); } else { - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX, - AR5K_PHY_TXPOWER_RATE_MAX | - AR5K_TUNE_MAX_TXPOWER); + ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); } return true; @@ -5733,7 +5737,7 @@ ath5k_hw_dump_state(struct ath_hw *hal) { #ifdef AR5K_DEBUG #define AR5K_PRINT_REGISTER(_x) \ - AR5K_PRINTF("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_##_x)); + AR5K_PRINTF("(%s: %08x) ", #_x, ath5k_hw_reg_read(hal, AR5K_##_x)); AR5K_PRINT("MAC registers:\n"); AR5K_PRINT_REGISTER(CR); @@ -5916,7 +5920,7 @@ ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; @@ -5930,7 +5934,7 @@ ath5k_hw_disable_pspoll(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, + AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; diff --git a/openhal/ath5k_hw.h b/openhal/ath5k_hw.h index 417812f..92ff4cf 100644 --- a/openhal/ath5k_hw.h +++ b/openhal/ath5k_hw.h @@ -206,9 +206,9 @@ struct ath5k_eeprom_info { #define AR5K_INIT_CFG 0x00000000 #endif -#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg) +/*#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg) -#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg) +#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg)*/ #define AR5K_REG_SM(_val, _flags) \ (((_val) << _flags##_S) & (_flags)) @@ -221,32 +221,32 @@ struct ath5k_eeprom_info { * retrieve the values which we do not want to clear (lets call this * old_data) and then set the register with this and our new_value: * ( old_data | new_value) */ -#define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ - AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ - (((_val) << _flags##_S) & (_flags))) +#define AR5K_REG_WRITE_BITS(hal, _reg, _flags, _val) \ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & ~(_flags)) | \ + (((_val) << _flags##_S) & (_flags)), _reg) -#define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \ - AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags)) +#define AR5K_REG_MASKED_BITS(hal, _reg, _flags, _mask) \ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & \ + (_mask)) | (_flags), _reg) -#define AR5K_REG_ENABLE_BITS(_reg, _flags) \ - AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) +#define AR5K_REG_ENABLE_BITS(hal, _reg, _flags) \ + ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) | (_flags), _reg) -#define AR5K_REG_DISABLE_BITS(_reg, _flags) \ - AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) +#define AR5K_REG_DISABLE_BITS(hal, _reg, _flags) \ + ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) & ~(_flags), _reg) -#define AR5K_PHY_WRITE(_reg, _val) \ - AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val) +#define AR5K_PHY_WRITE(hal, _reg, _val) \ + ath5k_hw_reg_write(hal, _val, (hal)->ah_phy + ((_reg) << 2)) -#define AR5K_PHY_READ(_reg) \ - AR5K_REG_READ(hal->ah_phy + ((_reg) << 2)) +#define AR5K_PHY_READ(hal, _reg) \ + ath5k_hw_reg_read(hal, (hal)->ah_phy + ((_reg) << 2)) #define AR5K_REG_WAIT(_i) \ if (_i % 64) \ udelay(1); #define AR5K_EEPROM_READ(_o, _v) { \ - if ((ret = ath5k_hw_eeprom_read(hal, (_o), \ - &(_v))) != 0) \ + if ((ret = ath5k_hw_eeprom_read(hal, (_o), &(_v))) != 0) \ return (ret); \ } @@ -254,11 +254,11 @@ struct ath5k_eeprom_info { AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ /* Read status of selected queue */ -#define AR5K_REG_READ_Q(_reg, _queue) \ - (AR5K_REG_READ(_reg) & (1 << _queue)) \ +#define AR5K_REG_READ_Q(hal, _reg, _queue) \ + (ath5k_hw_reg_read(hal, _reg) & (1 << _queue)) \ -#define AR5K_REG_WRITE_Q(_reg, _queue) \ - AR5K_REG_WRITE(_reg, (1 << _queue)) +#define AR5K_REG_WRITE_Q(hal, _reg, _queue) \ + ath5k_hw_reg_write(hal, (1 << _queue), _reg) #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ _reg |= 1 << _queue; \ @@ -1337,7 +1337,7 @@ struct ath5k_ar5210_ini_mode{ u32 mode_base, mode_turbo; }; -#define AR5K_AR5210_INI_MODE(_aifs) { \ +#define AR5K_AR5210_INI_MODE(hal, _aifs) { \ { AR5K_SLOT_TIME, \ AR5K_INIT_SLOT_TIME, \ AR5K_INIT_SLOT_TIME_TURBO }, \ @@ -1356,8 +1356,8 @@ struct ath5k_ar5210_ini_mode{ AR5K_INIT_PROTO_TIME_CNTRL, \ AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ { AR5K_PHY(17), \ - (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x1C, \ - (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ + (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x1C, \ + (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ { AR5K_PHY_FRAME_CTL_5210, \ AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ AR5K_PHY_FRAME_CTL_TXURN_ERR | \