commit 1b6d6e26678e785cbb2b107079bc45e8b367fed8 Author: Jiri Slaby Date: Sat Jul 14 13:45:20 2007 +0200 headers cleanup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index d877636..5b39237 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1541,7 +1541,6 @@ static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, txq = &sc->txqs[qnum]; if (!txq->setup) { txq->qnum = qnum; - txq->intrcnt = 0; txq->link = NULL; INIT_LIST_HEAD(&txq->q); spin_lock_init(&txq->lock); diff --git a/ath/if_athioctl.h b/ath/if_athioctl.h index 24ab592..6359248 100644 --- a/ath/if_athioctl.h +++ b/ath/if_athioctl.h @@ -45,83 +45,82 @@ #include struct ath_stats { - u_int32_t ast_watchdog; /* device reset by watchdog */ - u_int32_t ast_hardware; /* fatal hardware error interrupts */ - u_int32_t ast_bmiss; /* beacon miss interrupts */ - u_int32_t ast_bstuck; /* beacon stuck interrupts */ - u_int32_t ast_rxorn; /* rx overrun interrupts */ - u_int32_t ast_rxeol; /* rx eol interrupts */ - u_int32_t ast_txurn; /* tx underrun interrupts */ - u_int32_t ast_mib; /* mib interrupts */ - u_int32_t ast_intrcoal; /* interrupts coalesced */ - u_int32_t ast_tx_packets; /* packet sent on the interface */ - u_int32_t ast_tx_mgmt; /* management frames transmitted */ - u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ - u_int32_t ast_tx_invalid; /* frames discarded 'cuz device gone */ - u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ - u_int32_t ast_tx_encap; /* tx encapsulation failed */ - u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ - u_int32_t ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ - u_int32_t ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ - u_int32_t ast_tx_linear; /* tx linearized to cluster */ - u_int32_t ast_tx_nodata; /* tx discarded empty frame */ - u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ - u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ - u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ - u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ - u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ - u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ - u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ - u_int32_t ast_tx_noack; /* tx frames with no ack marked */ - u_int32_t ast_tx_rts; /* tx frames with rts enabled */ - u_int32_t ast_tx_cts; /* tx frames with cts enabled */ - u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ - u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ - u_int32_t ast_tx_protect; /* tx frames with protection */ - u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ - u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ - u_int32_t ast_rx_nobuf; /* rx setup failed 'cuz no skb */ - u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ - u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ - u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ - u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ - u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ - u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ - u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ - u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ - u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ - u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ - u_int32_t ast_rx_packets; /* packet recv on the interface */ - u_int32_t ast_rx_mgt; /* management frames received */ - u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ - int8_t ast_tx_rssi; /* tx rssi of last ack */ - int8_t ast_rx_rssi; /* rx rssi from histogram */ - u_int32_t ast_be_xmit; /* beacons transmitted */ - u_int32_t ast_be_nobuf; /* beacon setup failed 'cuz no skb */ - u_int32_t ast_per_cal; /* periodic calibration calls */ - u_int32_t ast_per_calfail;/* periodic calibration failed */ - u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ - u_int32_t ast_rate_calls; /* rate control checks */ - u_int32_t ast_rate_raise; /* rate control raised xmit rate */ - u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ - u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ - u_int32_t ast_ant_txswitch;/* tx antenna switches */ - u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ - u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ + __u32 ast_watchdog; /* device reset by watchdog */ + __u32 ast_hardware; /* fatal hardware error interrupts */ + __u32 ast_bmiss; /* beacon miss interrupts */ + __u32 ast_bstuck; /* beacon stuck interrupts */ + __u32 ast_rxorn; /* rx overrun interrupts */ + __u32 ast_rxeol; /* rx eol interrupts */ + __u32 ast_txurn; /* tx underrun interrupts */ + __u32 ast_mib; /* mib interrupts */ + __u32 ast_intrcoal; /* interrupts coalesced */ + __u32 ast_tx_packets; /* packet sent on the interface */ + __u32 ast_tx_mgmt; /* management frames transmitted */ + __u32 ast_tx_discard; /* frames discarded prior to assoc */ + __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ + __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ + __u32 ast_tx_encap; /* tx encapsulation failed */ + __u32 ast_tx_nonode; /* tx failed 'cuz no node */ + __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ + __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ + __u32 ast_tx_linear; /* tx linearized to cluster */ + __u32 ast_tx_nodata; /* tx discarded empty frame */ + __u32 ast_tx_busdma; /* tx failed for dma resrcs */ + __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ + __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ + __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ + __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ + __u32 ast_tx_longretry;/* tx on-chip retries (long) */ + __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ + __u32 ast_tx_noack; /* tx frames with no ack marked */ + __u32 ast_tx_rts; /* tx frames with rts enabled */ + __u32 ast_tx_cts; /* tx frames with cts enabled */ + __u32 ast_tx_shortpre;/* tx frames with short preamble */ + __u32 ast_tx_altrate; /* tx frames with alternate rate */ + __u32 ast_tx_protect; /* tx frames with protection */ + __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ + __u32 ast_tx_ctsext; /* tx frames with cts extension */ + __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ + __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ + __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ + __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ + __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ + __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ + __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ + __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ + __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ + __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ + __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ + __u32 ast_rx_packets; /* packet recv on the interface */ + __u32 ast_rx_mgt; /* management frames received */ + __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ + __s8 ast_tx_rssi; /* tx rssi of last ack */ + __s8 ast_rx_rssi; /* rx rssi from histogram */ + __u32 ast_be_xmit; /* beacons transmitted */ + __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ + __u32 ast_per_cal; /* periodic calibration calls */ + __u32 ast_per_calfail;/* periodic calibration failed */ + __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ + __u32 ast_rate_calls; /* rate control checks */ + __u32 ast_rate_raise; /* rate control raised xmit rate */ + __u32 ast_rate_drop; /* rate control dropped xmit rate */ + __u32 ast_ant_defswitch;/* rx/default antenna switches */ + __u32 ast_ant_txswitch;/* tx antenna switches */ + __u32 ast_ant_rx[8]; /* rx frames with antenna */ + __u32 ast_ant_tx[8]; /* tx frames with antenna */ }; struct ath_diag { char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ - u_int16_t ad_id; + __u16 ad_id; #define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ #define ATH_DIAG_IN 0x4000 /* copy in parameters */ #define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ #define ATH_DIAG_ID 0x0fff - u_int16_t ad_in_size; /* pack to fit, yech */ + __u16 ad_in_size; /* pack to fit, yech */ void __user *ad_in_data; void __user *ad_out_data; u_int ad_out_size; - }; /* @@ -137,12 +136,12 @@ struct ath_diag { struct ath_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; - u_int8_t wr_flags; /* XXX for padding */ - u_int8_t wr_rate; + __u8 wr_flags; /* XXX for padding */ + __u8 wr_rate; __le16 wr_chan_freq; __le16 wr_chan_flags; - u_int8_t wr_antenna; - u_int8_t wr_antsignal; + __u8 wr_antenna; + __u8 wr_antsignal; }; #define ATH_TX_RADIOTAP_PRESENT ( \ @@ -157,22 +156,17 @@ struct ath_rx_radiotap_header { struct ath_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; - u_int8_t wt_flags; /* XXX for padding */ - u_int8_t wt_rate; - u_int8_t wt_txpower; - u_int8_t wt_antenna; + __u8 wt_flags; /* XXX for padding */ + __u8 wt_rate; + __u8 wt_txpower; + __u8 wt_antenna; __le16 wt_tx_flags; - u_int8_t wt_rts_retries; - u_int8_t wt_data_retries; + __u8 wt_rts_retries; + __u8 wt_data_retries; }; - -#ifdef __linux__ #define SIOCGATHSTATS (SIOCDEVPRIVATE+0) #define SIOCGATHDIAG (SIOCDEVPRIVATE+1) -#else -#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) -#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) + #endif -#endif /* _DEV_ATH_ATHIOCTL_H */ diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 92445c7..f44464b 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -57,33 +57,19 @@ * MAXFRAMEBODY - WEP - QOS - RSN/WPA: * 2312 - 8 - 2 - 12 = 2290 */ -#define ATH_MAX_MTU 2290 -#define ATH_MIN_MTU 32 +#define ATH_MAX_MTU 2290 +#define ATH_MIN_MTU 32 #define ATH_RXBUF 40 /* number of RX buffers */ #define ATH_TXBUF 200 /* number of TX buffers */ #define ATH_TXDESC 1 /* number of descriptors per buffer */ -#define ATH_BCBUF 1 /* number of beacon buffers */ +#define ATH_BCBUF 1 /* number of beacon buffers */ #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ -#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ -#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ -#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ - -/* driver-specific node state */ -struct ath_node { -#ifdef BLE - struct ieee80211_node an_node; /* base class */ -#endif - u8 an_tx_mgtrate; /* h/w rate for management/ctl frames */ - u8 an_tx_mgtratesp;/* short preamble h/w rate for " " */ - u32 an_avgrssi; /* average rssi over all rx frames */ - struct ath5k_node_stats an_halstats; /* rssi statistics used by hal */ - /* variable-length rate control state follows */ -}; -#define ATH_NODE(ni) ((struct ath_node *)(ni)) -#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) +#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ +#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ +#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ #define ATH_RSSI_LPF_LEN 10 #define ATH_RSSI_DUMMY_MARKER 0x127 @@ -117,20 +103,10 @@ struct ath_buf { */ struct ath_txq { unsigned int qnum; /* hardware q number */ - unsigned int intrcnt; /* interrupt count */ u32 *link; /* link ptr in last TX desc */ struct list_head q; /* transmit queue */ spinlock_t lock; /* lock on q and link */ - /* - * State for patching up CTS when bursting. - */ - struct ath_buf *linkbuf; /* va of last buffer */ - struct ath_desc *lastdsWithCTS; /* first desc of last descriptor that - * contains CTS */ - struct ath_desc *gatingds; /* final desc of the gating desc that - * determines whether lastdsWithCTS has - * been DMA'ed or not */ - bool setup; + bool setup; }; #if CHAN_DEBUG @@ -156,15 +132,6 @@ struct ath_softc { #endif int debug; -#ifdef BLE - void (*sc_recv_mgmt)(struct ieee80211com *, - struct sk_buff *, - struct ieee80211_node *, - int, int, u32); - int (*sc_newstate)(struct ieee80211com *, - enum ieee80211_state, int); - void (*sc_node_free)(struct ieee80211_node *); -#endif struct ath_buf *bufptr; /* allocated buffer ptr */ struct ath_desc *desc; /* TX/RX descriptors */ dma_addr_t desc_daddr; /* DMA (physical) address */ @@ -245,7 +212,6 @@ struct ath_softc { struct tasklet_struct rxtq; /* rx intr tasklet */ #ifdef BLE struct tasklet_struct rxorntq; /* rxorn intr tasklet */ -//#ifdef BLE u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ @@ -286,14 +252,6 @@ struct ath_softc { #endif }; -/*#define ATH_TXBUF_LOCK(_sc) spin_lock(&(_sc)->sc_txbuflock) -#define ATH_TXBUF_UNLOCK(_sc) spin_unlock(&(_sc)->sc_txbuflock) -#define ATH_TXBUF_LOCK_BH(_sc) spin_lock_bh(&(_sc)->sc_txbuflock) -#define ATH_TXBUF_UNLOCK_BH(_sc) spin_unlock_bh(&(_sc)->sc_txbuflock)*/ -#define ATH_TXBUF_LOCK_ASSERT(_sc) \ - KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), "txbuf not locked!") - -int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); void ath_sysctl_unregister(void); @@ -303,32 +261,10 @@ void ath_sysctl_unregister(void); (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == 0) #define ath_hal_hwphycounters(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == 0) -#define ath_hal_hasdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == 0) -#define ath_hal_getdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == 0) -#define ath_hal_setdiversity(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_DIVERSITY, 1, _v, NULL) -#define ath_hal_getdiag(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIAG, 0, _pv) == 0) -#define ath_hal_setdiag(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_DIAG, 0, _v, NULL) #define ath_hal_getnumtxqueues(_ah, _pv) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == 0) #define ath_hal_hasveol(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) -#define ath_hal_hastxpowlimit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 0, NULL) == 0) -#define ath_hal_settxpowlimit(_ah, _pow) \ - ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) -#define ath_hal_gettxpowlimit(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == 0) -#define ath_hal_getmaxtxpow(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == 0) -#define ath_hal_gettpscale(_ah, _scale) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 3, _scale) == 0) -#define ath_hal_settpscale(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_TXPOW, 3, _v, NULL) #define ath_hal_hastpc(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == 0) #define ath_hal_gettpc(_ah) \ @@ -339,13 +275,5 @@ void ath_sysctl_unregister(void); (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) #define ath_hal_hasbssidmask(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) -#ifdef notyet -#define ath_hal_hasmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == 0) -#define ath_hal_getmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == 0) -#else -#define ath_hal_getmcastkeysearch(_ah) 0 -#endif -#endif /* _DEV_ATH_ATHVAR_H */ +#endif