commit caf93d3ffbdc75dbd3dd32712b4749458b4149ea Author: Jiri Slaby Date: Sun Jun 17 14:54:42 2007 +0200 get rid of typedefs, blaah diff --git a/ath/if_ath.c b/ath/if_ath.c index 0a76149..a2f282e 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -181,7 +181,7 @@ static void ath_setup_stationkey(struct ieee80211_node *); static void ath_newassoc(struct ieee80211_node *, int); #endif static int ath_getchannels(struct net_device *, u_int cc, - AR5K_BOOL outdoor, AR5K_BOOL xchanmode); + bool outdoor, bool xchanmode); #ifdef BLE static void ath_led_event(struct ath_softc *, int); #endif @@ -305,29 +305,29 @@ enum { P80211ENUM_truth_true = 0x01 }; -typedef struct { - u_int32_t did; - u_int16_t status; - u_int16_t len; - u_int32_t data; -} p80211item_uint32_t; +struct p80211item_u32 { + u32 did; + u16 status; + u16 len; + u32 data; +}; -typedef struct { - u_int32_t msgcode; - u_int32_t msglen; +struct wlan_ng_prism2_header { + u32 msgcode; + u32 msglen; #define WLAN_DEVNAMELEN_MAX 16 - u_int8_t devname[WLAN_DEVNAMELEN_MAX]; - p80211item_uint32_t hosttime; - p80211item_uint32_t mactime; - p80211item_uint32_t channel; - p80211item_uint32_t rssi; - p80211item_uint32_t sq; - p80211item_uint32_t signal; - p80211item_uint32_t noise; - p80211item_uint32_t rate; - p80211item_uint32_t istx; - p80211item_uint32_t frmlen; -} wlan_ng_prism2_header; + u8 devname[WLAN_DEVNAMELEN_MAX]; + struct p80211item_u32 hosttime; + struct p80211item_u32 mactime; + struct p80211item_u32 channel; + struct p80211item_u32 rssi; + struct p80211item_u32 sq; + struct p80211item_u32 signal; + struct p80211item_u32 noise; + struct p80211item_u32 rate; + struct p80211item_u32 istx; + struct p80211item_u32 frmlen; +}; int ath_attach(u_int16_t devid, struct net_device *dev) @@ -335,7 +335,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) struct ath_softc *sc = dev->priv; // struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah; - AR5K_STATUS status; + enum ath5k_status status; int error = 0, i; u_int8_t csz; @@ -831,7 +831,7 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs) struct net_device *dev = dev_id; struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - AR5K_INT status; + enum ath5k_int status; int needmark; if (sc->sc_invalid) { @@ -1044,7 +1044,7 @@ ath_init(struct net_device *dev) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - AR5K_STATUS status; + enum ath5k_status status; int error = 0; ATH_LOCK(sc); @@ -1252,7 +1252,7 @@ ath_reset(struct net_device *dev) struct ath_softc *sc = dev->priv; // struct ath_hal *ah = sc->sc_ah; // struct ieee80211_channel *c; -// AR5K_STATUS status; +// enum ath5k_status status; // int opmode; DPRINTF(sc, ATH_DEBUG_RESET, "%s: resetting\n", dev->name); @@ -1395,7 +1395,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) u_int flags = 0; struct ieee80211_frame *wh; struct ath_desc *ds; - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; uint8_t testmac[ETH_ALEN]; if ((sc->sc_dev.flags & IFF_RUNNING) == 0 || sc->sc_invalid) { @@ -2430,7 +2430,7 @@ ath_updateslot(struct net_device *dev) static int ath_beaconq_setup(struct ath_hal *ah) { - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; memset(&qi, 0, sizeof(qi)); qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; @@ -2450,7 +2450,7 @@ ath_beaconq_config(struct ath_softc *sc) #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) // struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); if (sc->sc_opmode == IEEE80211_IF_TYPE_AP) { @@ -3169,9 +3169,9 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) int headroom_needed = 0; if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { - headroom_needed = sizeof(wlan_ng_prism2_header); + headroom_needed = sizeof(struct wlan_ng_prism2_header); } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_PRISM) { - headroom_needed = sizeof(wlan_ng_prism2_header); + headroom_needed = sizeof(struct wlan_ng_prism2_header); } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_RADIOTAP) { headroom_needed = sizeof(struct ath_rx_radiotap_header); } @@ -3684,7 +3684,7 @@ ath_rx_tasklet(TQUEUE_ARG data) // struct ath_node *an; int len;//, type; u_int phyerr; - AR5K_STATUS status; + enum ath5k_status status; DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s\n", __func__); do { @@ -4005,7 +4005,7 @@ ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) { #define N(a) (sizeof(a)/sizeof(a[0])) struct ath_hal *ah = sc->sc_ah; - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; int qnum; memset(&qi, 0, sizeof(qi)); @@ -4095,7 +4095,7 @@ ath_txq_update(struct ath_softc *sc, int ac) struct ath_txq *txq = sc->sc_ac2q[ac]; // struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; struct ath_hal *ah = sc->sc_ah; - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); qi.tqi_aifs = wmep->wmep_aifsn; @@ -4181,8 +4181,8 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * struct ieee80211_frame *wh; u_int subtype, flags, ctsduration; AR5K_PKT_TYPE atype; - const AR5K_RATE_TABLE *rt; - AR5K_BOOL short_preamble; + const struct ath5k_rate_table *rt; + bool short_preamble; struct ath_node *an; struct llc *llc; int eapol; @@ -4653,7 +4653,7 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) // struct ieee80211_node *ni; // struct ath_node *an; // int sr, lr, pri; - AR5K_STATUS status; + enum ath5k_status status; DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", __func__, txq->axq_qnum, @@ -4980,7 +4980,7 @@ ath_stoprecv(struct ath_softc *sc) #ifdef BLE STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { struct ath_desc *ds = bf->bf_desc; - AR5K_STATUS status = ath_hal_rxprocdesc(ah, ds, + enum ath5k_status status = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, PA2DESC(sc, ds->ds_link)); if (status == AR5K_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) ath_printrxbuf(bf, status == AR5K_OK); @@ -5090,7 +5090,7 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) { struct ath_hal *ah = sc->sc_ah; - AR5K_CHANNEL hchan; + struct ath5k_channel hchan; /* * Convert to a HAL channel description with @@ -5113,7 +5113,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) ath_hal_mhz2ieee(hchan.freq, hchan.channel_flags), hchan.freq); if (hchan.freq != sc->sc_curchan.freq || hchan.channel_flags != sc->sc_curchan.channel_flags) { - AR5K_STATUS status; + enum ath5k_status status; /* * To switch channels clear any pending DMA operations; @@ -5410,15 +5410,15 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) #endif static int ath_getchannels(struct net_device *dev, u_int cc, - AR5K_BOOL outdoor, AR5K_BOOL xchanmode) + bool outdoor, bool xchanmode) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - AR5K_CHANNEL *chans; + struct ath5k_channel *chans; int i, ix; u_int nchan; #define IEEE80211_CHAN_MAX 255 - chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(AR5K_CHANNEL), GFP_KERNEL); + chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(struct ath5k_channel), GFP_KERNEL); if (chans == NULL) { printk(KERN_ERR "unable to allocate channel table\n"); return ENOMEM; @@ -5439,7 +5439,7 @@ ath_getchannels(struct net_device *dev, u_int cc, * them in the table according to their channel number. */ for (i = 0; i < nchan; i++) { - AR5K_CHANNEL *c = &chans[i]; + struct ath5k_channel *c = &chans[i]; ix = ath_hal_mhz2ieee(c->freq, c->channel_flags); if (ix > IEEE80211_CHAN_MAX) { printk(KERN_ERR "bad hal channel %u (%u/%x) ignored\n", @@ -5544,7 +5544,7 @@ ath_rate_setup(struct net_device *dev, u_int mode) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; // struct ieee80211_rateset *rs; // int i, maxrates; @@ -5615,7 +5615,7 @@ ath_setcurmode(struct ath_softc *sc, unsigned int mode) { 0, 500, 130 }, }; #endif - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; // int i, j; memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 16edb96..8d61385 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -156,10 +156,10 @@ struct ath_node { #ifdef BLE struct ieee80211_node an_node; /* base class */ #endif - u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ - u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */ - u_int32_t an_avgrssi; /* average rssi over all rx frames */ - AR5K_NODE_STATS an_halstats; /* rssi statistics used by hal */ + u8 an_tx_mgtrate; /* h/w rate for management/ctl frames */ + u8 an_tx_mgtratesp;/* short preamble h/w rate for " " */ + u32 an_avgrssi; /* average rssi over all rx frames */ + struct ath5k_node_stats an_halstats; /* rssi statistics used by hal */ /* variable-length rate control state follows */ }; #define ATH_NODE(ni) ((struct ath_node *)(ni)) @@ -205,7 +205,7 @@ struct ath_txq { u_int axq_qnum; /* hardware q number */ u_int axq_depth; /* queue depth (stat only) */ u_int axq_intrcnt; /* interrupt count */ - u_int32_t *axq_link; /* link ptr in last TX desc */ + u32 *axq_link; /* link ptr in last TX desc */ struct list_head axq_q; /* transmit queue */ spinlock_t axq_lock; /* lock on q and link */ /* @@ -260,7 +260,7 @@ struct ath_softc { void (*sc_recv_mgmt)(struct ieee80211com *, struct sk_buff *, struct ieee80211_node *, - int, int, u_int32_t); + int, int, u32); int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); void (*sc_node_free)(struct ieee80211_node *); @@ -268,7 +268,7 @@ struct ath_softc { void *sc_bdev; /* associated bus device */ struct ath_desc *sc_desc; /* TX/RX descriptors */ size_t sc_desc_len; /* size of TX/RX descriptors */ - u_int16_t sc_cachelsz; /* cache line size */ + u16 sc_cachelsz; /* cache line size */ dma_addr_t sc_desc_daddr; /* DMA (physical) address */ struct ath_hal *sc_ah; /* Atheros HAL */ struct ath_ratectrl *sc_rc; /* tx rate control support */ @@ -288,25 +288,25 @@ struct ath_softc { sc_hasclrkey:1, /* CLR key supported */ sc_rawdev_enabled : 1; /* enable sc_rawdev */ /* rate tables */ - const AR5K_RATE_TABLE *sc_rates[NUM_IEEE80211_MODES]; - const AR5K_RATE_TABLE *sc_currates; /* current rate table */ + const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; + const struct ath5k_rate_table *sc_currates; /* current rate table */ unsigned int sc_curmode; /* current phy mode */ - u_int16_t sc_curtxpow; /* current tx power limit */ - AR5K_CHANNEL sc_curchan; /* current h/w channel */ - u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ + u16 sc_curtxpow; /* current tx power limit */ + struct ath5k_channel sc_curchan; /* current h/w channel */ + u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ struct { - u_int8_t ieeerate; /* IEEE rate */ - u_int8_t rxflags; /* radiotap rx flags */ - u_int8_t txflags; /* radiotap tx flags */ - u_int16_t ledon; /* softled on time */ - u_int16_t ledoff; /* softled off time */ + u8 ieeerate; /* IEEE rate */ + u8 rxflags; /* radiotap rx flags */ + u8 txflags; /* radiotap tx flags */ + u16 ledon; /* softled on time */ + u16 ledoff; /* softled off time */ } sc_hwmap[32]; /* h/w rate ix mappings */ - u_int8_t sc_protrix; /* protection rate index */ + u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ - AR5K_INT sc_imask; /* interrupt mask copy */ + enum ath5k_int sc_imask; /* interrupt mask copy */ u_int sc_keymax; /* size of key cache */ #ifdef BLE - u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ + u8 sc_keymap[ATH_KEYBYTES];/* key use bit map */ struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ #endif @@ -314,20 +314,20 @@ struct ath_softc { u_int sc_ledon; /* pin setting for LED on */ u_int sc_ledidle; /* idle polling interval */ int sc_ledevent; /* time of last LED event */ - u_int8_t sc_rxrate; /* current rx rate for LED */ - u_int8_t sc_txrate; /* current tx rate for LED */ - u_int16_t sc_ledoff; /* off time for current blink */ + u8 sc_rxrate; /* current rx rate for LED */ + u8 sc_txrate; /* current tx rate for LED */ + u16 sc_ledoff; /* off time for current blink */ struct timer_list sc_ledtimer; /* led off timer */ - u_int32_t sc_rxfilter; + u32 sc_rxfilter; union { struct ath_tx_radiotap_header th; - u_int8_t pad[64]; + u8 pad[64]; } u_tx_rt; int sc_tx_th_len; union { struct ath_rx_radiotap_header th; - u_int8_t pad[64]; + u8 pad[64]; } u_rx_rt; int sc_rx_th_len; @@ -336,11 +336,11 @@ struct ath_softc { int sc_rxbufsize; /* rx size based on mtu */ struct list_head *sc_rxbuf; /* receive buffer */ - u_int32_t *sc_rxlink; /* link ptr in last RX desc */ + u32 *sc_rxlink; /* link ptr in last RX desc */ struct tq_struct sc_rxtq; /* rx intr tasklet */ struct tq_struct sc_rxorntq; /* rxorn intr tasklet */ - u_int8_t sc_defant; /* current default antenna */ - u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ + u8 sc_defant; /* current default antenna */ + u8 sc_rxotherant; /* rx's on non-default antenna*/ struct list_head *sc_txbuf; /* transmit buffer */ spinlock_t sc_txbuflock; /* txbuf lock */ @@ -354,7 +354,7 @@ struct ath_softc { struct list_head *sc_bbuf; /* beacon buffers */ u_int sc_bhalq; /* HAL q for outgoing beacons */ u_int sc_bmisscount; /* missed beacon transmits */ - u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ + u32 sc_ant_tx[8]; /* recent tx frames/antenna */ struct ath_txq *sc_cabq; /* tx q for cab frames */ struct ath_buf *sc_bufptr; /* allocated buffer ptr */ #ifdef BLE @@ -394,7 +394,7 @@ struct ath_softc { #define ATH_TXBUF_LOCK_ASSERT(_sc) \ KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), ("txbuf not locked!")) -int ath_attach(u_int16_t, struct net_device *); +int ath_attach(u16, struct net_device *); int ath_detach(struct net_device *); void ath_resume(struct net_device *); void ath_suspend(struct net_device *); @@ -407,7 +407,7 @@ irqreturn_t ath_intr(int, void *); #else irqreturn_t ath_intr(int, void *, struct pt_regs *regs); #endif -void bus_read_cachesize(struct ath_softc *, u_int8_t *); +void bus_read_cachesize(struct ath_softc *, u8 *); int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); void ath_sysctl_unregister(void); diff --git a/openhal/ah_osdep.c b/openhal/ah_osdep.c index d2a14be..9f1a7c4 100644 --- a/openhal/ah_osdep.c +++ b/openhal/ah_osdep.c @@ -16,7 +16,7 @@ static char dev_info[] = "ath_hal"; struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, - AR5K_STATUS *s) + enum ath5k_status *s) { struct ath_hal *ah = ath5k_hw_init(devid, sc, h, s); diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 7b62b51..8bf0bb3 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -68,12 +68,11 @@ #ifndef FALSE #define FALSE 0 #endif -typedef u_int8_t AR5K_BOOL; /* * Error codes reported from HAL to the driver */ -typedef enum { +enum ath5k_status { AR5K_OK = 0, /* Everything went O.K.*/ AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/ AR5K_EIO = 2, /* Hardware I/O Error*/ @@ -84,7 +83,7 @@ typedef enum { AR5K_EINVAL = 7, /* Invalid parameter to function */ AR5K_ENOTSUPP = 8, /* Hardware revision not supported */ AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */ -} AR5K_STATUS; +}; /* * Some tuneable values (these should be changeable by the user) @@ -116,7 +115,7 @@ typedef enum { #define AR5K_TUNE_HWTXTRIES 4 /* token to use for aifs, cwmin, cwmax in MadWiFi */ -#define AR5K_TXQ_USEDEFAULT ((u_int32_t) -1) +#define AR5K_TXQ_USEDEFAULT ((u32) -1) /* GENERIC CHIPSET DEFINITIONS */ @@ -211,14 +210,6 @@ struct ath5k_srev_name { #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) #define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 -/*typedef enum { - AR5K_M_STA = IEEE80211_IF_TYPE_STA, - AR5K_M_IBSS = IEEE80211_IF_TYPE_IBSS, - AR5K_M_HOSTAP = IEEE80211_IF_TYPE_AP, - AR5K_M_MONITOR = IEEE80211_IF_TYPE_MNTR, -} AR5K_OPMODE;*/ - - /****************\ TX DEFINITIONS \****************/ @@ -227,15 +218,15 @@ struct ath5k_srev_name { * Tx Descriptor */ struct ath_tx_status { - u_int16_t ts_seqnum; - u_int16_t ts_tstamp; - u_int8_t ts_status; - u_int8_t ts_rate; + u16 ts_seqnum; + u16 ts_tstamp; + u8 ts_status; + u8 ts_rate; int8_t ts_rssi; - u_int8_t ts_shortretry; - u_int8_t ts_longretry; - u_int8_t ts_virtcol; - u_int8_t ts_antenna; + u8 ts_shortretry; + u8 ts_longretry; + u8 ts_virtcol; + u8 ts_antenna; }; #define AR5K_TXSTAT_ALTRATE 0x80 @@ -246,14 +237,14 @@ struct ath_tx_status { /* * Queue types used to classify tx queues. */ -typedef enum { +enum ath5k_tx_queue { AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ AR5K_TX_QUEUE_DATA, /*A normal data queue*/ AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ -} AR5K_TX_QUEUE; +}; #define AR5K_NUM_TX_QUEUES 10 #define AR5K_NUM_TX_QUEUES_NOQCU 2 @@ -265,12 +256,12 @@ typedef enum { * highest. Normal data that hasn't been classified * goes to the Best Effort AC. */ -typedef enum { +enum ath5k_tx_queue_subtype { AR5K_WME_AC_BK = 0, /*Background traffic*/ AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ AR5K_WME_AC_VI, /*Video traffic*/ AR5K_WME_AC_VO, /*Voice traffic*/ -} AR5K_TX_QUEUE_SUBTYPE; +}; /* * Queue ID numbers as returned by the HAL, each number @@ -278,7 +269,7 @@ typedef enum { * (eg 5210) all data goes in one queue. These match * d80211 definitions (net80211/MadWiFi don't use them). */ -typedef enum { +enum ath5k_tx_queue_id { AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ @@ -288,7 +279,7 @@ typedef enum { AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ AR5K_TX_QUEUE_ID_UAPSD = 8, AR5K_TX_QUEUE_ID_XR_DATA = 9, -} AR5K_TX_QUEUE_ID; +}; /* @@ -306,32 +297,32 @@ typedef enum { /* * A struct to hold tx queue's parameters */ -typedef struct { - AR5K_TX_QUEUE tqi_type; /* See AR5K_TX_QUEUE */ - AR5K_TX_QUEUE_SUBTYPE tqi_subtype; /* See AR5K_TX_QUEUE_SUBTYPE */ - u_int16_t tqi_flags; /* Tx queue flags (see above) */ - u_int32_t tqi_aifs; /* Arbitrated Interframe Space */ - int32_t tqi_cw_min; /* Minimum Contention Window */ - int32_t tqi_cw_max; /* Maximum Contention Window */ - u_int32_t tqi_cbr_period; /* Constant bit rate period */ - u_int32_t tqi_cbr_overflow_limit; - u_int32_t tqi_burst_time; - u_int32_t tqi_ready_time; /* Not used */ - u_int32_t tqi_comp_buffer;/* Compression Buffer's phys addr */ -} AR5K_TXQ_INFO; +struct ath5k_txq_info { + enum ath5k_tx_queue tqi_type; + enum ath5k_tx_queue_subtype tqi_subtype; + u16 tqi_flags; /* Tx queue flags (see above) */ + u32 tqi_aifs; /* Arbitrated Interframe Space */ + s32 tqi_cw_min; /* Minimum Contention Window */ + s32 tqi_cw_max; /* Maximum Contention Window */ + u32 tqi_cbr_period; /* Constant bit rate period */ + u32 tqi_cbr_overflow_limit; + u32 tqi_burst_time; + u32 tqi_ready_time; /* Not used */ + u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ +}; /* * Transmit packet types. * These are not fully used inside OpenHAL yet */ -typedef enum { +enum ath5k_pkt_type { AR5K_PKT_TYPE_NORMAL = 0, AR5K_PKT_TYPE_ATIM = 1, AR5K_PKT_TYPE_PSPOLL = 2, AR5K_PKT_TYPE_BEACON = 3, AR5K_PKT_TYPE_PROBE_RESP = 4, AR5K_PKT_TYPE_PIFS = 5, -} AR5K_PKT_TYPE; +}; /* * TX power and TPC settings @@ -427,7 +418,7 @@ typedef enum { /* * DMA size definitions (2^n+2) */ -typedef enum { +enum ath5k_dmasize { AR5K_DMASIZE_4B = 0, AR5K_DMASIZE_8B, AR5K_DMASIZE_16B, @@ -436,7 +427,7 @@ typedef enum { AR5K_DMASIZE_128B, AR5K_DMASIZE_256B, AR5K_DMASIZE_512B -} ath5k_dmasize_t; +}; @@ -448,15 +439,15 @@ typedef enum { * Rx Descriptor */ struct ath_rx_status { - u_int16_t rs_datalen; - u_int16_t rs_tstamp; - u_int8_t rs_status; - u_int8_t rs_phyerr; + u16 rs_datalen; + u16 rs_tstamp; + u8 rs_status; + u8 rs_phyerr; int8_t rs_rssi; - u_int8_t rs_keyix; - u_int8_t rs_rate; - u_int8_t rs_antenna; - u_int8_t rs_more; + u8 rs_keyix; + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; }; #define AR5K_RXERR_CRC 0x01 @@ -464,8 +455,8 @@ struct ath_rx_status { #define AR5K_RXERR_FIFO 0x04 #define AR5K_RXERR_DECRYPT 0x08 #define AR5K_RXERR_MIC 0x10 -#define AR5K_RXKEYIX_INVALID ((u_int8_t) - 1) -#define AR5K_TXKEYIX_INVALID ((u_int32_t) - 1) +#define AR5K_RXKEYIX_INVALID ((u8) - 1) +#define AR5K_TXKEYIX_INVALID ((u32) - 1) /* * RX filters @@ -482,13 +473,13 @@ struct ath_rx_status { #define AR5K_RX_FILTER_PHYERROR 0x00000100 /* Don't filter phy errors */ #define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ -typedef struct { - u_int32_t ackrcv_bad; - u_int32_t rts_bad; - u_int32_t rts_good; - u_int32_t fcs_bad; - u_int32_t beacons; -} AR5K_MIB_STATS; +struct ath5k_mib_stats { + u32 ackrcv_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 beacons; +}; @@ -504,21 +495,21 @@ typedef struct { /* * Per-station beacon timer state. */ -typedef struct { - u_int32_t bs_next_beacon; - u_int32_t bs_next_dtim; - u_int32_t bs_interval; /*in TU's -see net80211/ieee80211_var.h- +struct ath5k_beacon_state { + u32 bs_next_beacon; + u32 bs_next_dtim; + u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- can also include the above flags*/ - u_int8_t bs_dtim_period; - u_int8_t bs_cfp_period; - u_int16_t bs_cfp_max_duration; /*if non-zero hw is setup to coexist with + u8 bs_dtim_period; + u8 bs_cfp_period; + u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with a Point Coordination Function capable AP*/ - u_int16_t bs_cfp_du_remain; - u_int16_t bs_tim_offset; - u_int16_t bs_sleep_duration; - u_int16_t bs_bmiss_threshold; - u_int32_t bs_cfp_next; -} AR5K_BEACON_STATE; + u16 bs_cfp_du_remain; + u16 bs_tim_offset; + u16 bs_sleep_duration; + u16 bs_bmiss_threshold; + u32 bs_cfp_next; +}; @@ -531,11 +522,11 @@ typedef struct { * Atheros descriptor */ struct ath_desc { - u_int32_t ds_link; - u_int32_t ds_data; - u_int32_t ds_ctl0; - u_int32_t ds_ctl1; - u_int32_t ds_hw[4]; + u32 ds_link; + u32 ds_data; + u32 ds_ctl0; + u32 ds_ctl1; + u32 ds_hw[4]; union { struct ath_rx_status rx; @@ -575,11 +566,11 @@ struct ath_desc { /* * Channel definitions */ -typedef struct { - u_int16_t freq; /* setting in Mhz */ - u_int16_t channel_flags; - u_int8_t private_flags; /* not used in OpenHAL yet*/ -} AR5K_CHANNEL; +struct ath5k_channel { + u16 freq; /* setting in Mhz */ + u16 channel_flags; + u8 private_flags; /* not used in OpenHAL yet*/ +}; #define AR5K_SLOT_TIME_9 396 #define AR5K_SLOT_TIME_20 880 @@ -613,7 +604,7 @@ typedef struct { /* * Used internaly in OpenHAL (ar5211.c/ar5212.c - * for reset_tx_queue). Also see struct AR5K_CHANNEL. + * for reset_tx_queue). Also see struct struct ath5k_channel. */ #define IS_CHAN_XR(_c) \ ((_c.channel_flags & CHANNEL_XR) != 0) @@ -621,18 +612,18 @@ typedef struct { #define IS_CHAN_B(_c) \ ((_c.channel_flags & CHANNEL_B) != 0) -typedef enum { +enum ath5k_chip{ AR5K_CHIP_5GHZ = CHANNEL_5GHZ, AR5K_CHIP_2GHZ = CHANNEL_2GHZ, -} AR5K_CHIP; +}; /* * The following structure will be used to map 2GHz channels to * 5GHz Atheros channels. */ struct ath5k_athchan_2ghz { - u_int32_t a2_flags; - u_int16_t a2_athchan; + u32 a2_flags; + u16 a2_athchan; }; /* @@ -641,22 +632,22 @@ struct ath5k_athchan_2ghz { #define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ -typedef struct { - u_int8_t valid; /* Valid for rate control */ - u_int32_t modulation; - u_int16_t rate_kbps; - u_int8_t rate_code; /* Rate mapping for h/w descriptors */ - u_int8_t dot11_rate; - u_int8_t control_rate; - u_int16_t lp_ack_duration;/* long preamble ACK duration */ - u_int16_t sp_ack_duration;/* short preamble ACK duration*/ -} AR5K_RATE; - -typedef struct { - u_int16_t rate_count; - u_int8_t rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ - AR5K_RATE rates[AR5K_MAX_RATES]; -} AR5K_RATE_TABLE; +struct ath5k_rate { + u8 valid; /* Valid for rate control */ + u32 modulation; + u16 rate_kbps; + u8 rate_code; /* Rate mapping for h/w descriptors */ + u8 dot11_rate; + u8 control_rate; + u16 lp_ack_duration;/* long preamble ACK duration */ + u16 sp_ack_duration;/* short preamble ACK duration*/ +}; + +struct ath5k_rate_table { + u16 rate_count; + u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ + struct ath5k_rate rates[AR5K_MAX_RATES]; +}; /* * Rate tables... @@ -740,7 +731,7 @@ typedef struct { */ /* key types */ -typedef enum { +enum ath5k_cipher { AR5K_CIPHER_WEP = 0, AR5K_CIPHER_AES_OCB = 1, AR5K_CIPHER_AES_CCM = 2, @@ -749,21 +740,19 @@ typedef enum { AR5K_CIPHER_CLR = 5, /* no encryption */ AR5K_CIPHER_MIC = 127 /* used for Message Integrity Code */ -} AR5K_CIPHER; +}; #define AR5K_KEYVAL_LENGTH_40 5 #define AR5K_KEYVAL_LENGTH_104 13 #define AR5K_KEYVAL_LENGTH_128 16 #define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128 -typedef struct { +struct ath5k_keyval { int wk_len; /* key's length */ - u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX]; - u_int8_t wk_type; /* see above */ - u_int8_t wk_mic[8]; /* TKIP MIC key */ -} AR5K_KEYVAL; - - + u8 wk_key[AR5K_KEYVAL_LENGTH_MAX]; + u8 wk_type; /* see above */ + u8 wk_mic[8]; /* TKIP MIC key */ +}; /***********************\ HW RELATED DEFINITIONS @@ -780,18 +769,18 @@ typedef struct { } while (0) -typedef struct { - u_int32_t ns_avgbrssi; /* average beacon rssi */ - u_int32_t ns_avgrssi; /* average data rssi */ - u_int32_t ns_avgtxrssi; /* average tx rssi */ -} AR5K_NODE_STATS; +struct ath5k_node_stats { + u32 ns_avgbrssi; /* average beacon rssi */ + u32 ns_avgrssi; /* average data rssi */ + u32 ns_avgtxrssi; /* average tx rssi */ +}; -typedef enum { +enum ath5k_ant_setting { AR5K_ANT_VARIABLE = 0, /* variable by programming */ AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ AR5K_ANT_MAX = 3, -} AR5K_ANT_SETTING; +}; /* * HAL interrupt abstraction @@ -802,7 +791,7 @@ typedef enum { * between the MAC chips, to be able to set intr properties * easier. Some of them are not used yet inside OpenHAL. */ -typedef enum { +enum ath5k_int { AR5K_INT_RX = 0x00000001, AR5K_INT_RXDESC = 0x00000002, AR5K_INT_RXNOFRM = 0x00000008, @@ -836,24 +825,18 @@ typedef enum { | AR5K_INT_GPIO, AR5K_INT_NOCARD = 0xffffffff /*Declare that the card has been removed*/ -} AR5K_INT; +}; /* * Power management */ -typedef enum { +enum ath5k_power_mode { AR5K_PM_UNDEFINED = 0, AR5K_PM_AUTO, AR5K_PM_AWAKE, AR5K_PM_FULL_SLEEP, AR5K_PM_NETWORK_SLEEP, -} AR5K_POWER_MODE; - - -/* - * LED states - */ -typedef int AR5K_LED_STATE; +}; /* * These match net80211 definitions (not used in @@ -875,7 +858,7 @@ typedef int AR5K_LED_STATE; * get_capability function is not yet fully implemented * in OpenHAL so most of these don't work yet... */ -typedef enum { +enum ath5k_capability_type { AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ AR5K_CAP_CIPHER = 1, /* Can handle encryption */ AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ @@ -897,23 +880,23 @@ typedef enum { AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ -} AR5K_CAPABILITY_TYPE; +}; -typedef struct { +struct ath5k_capabilities { /* * Supported PHY modes * (ie. CHANNEL_A, CHANNEL_B, ...) */ - u_int16_t cap_mode; + u16 cap_mode; /* * Frequency range (without regulation restrictions) */ struct { - u_int16_t range_2ghz_min; - u_int16_t range_2ghz_max; - u_int16_t range_5ghz_min; - u_int16_t range_5ghz_max; + u16 range_2ghz_min; + u16 range_2ghz_max; + u16 range_5ghz_min; + u16 range_5ghz_max; } cap_range; /* @@ -933,9 +916,9 @@ typedef struct { * Queue information */ struct { - u_int8_t q_tx_num; + u8 q_tx_num; } cap_queues; -} ath5k_capabilities_t; +}; /***************************************\ @@ -945,7 +928,6 @@ typedef struct { /* * Regulation stuff */ -typedef enum ieee80211_countrycode AR5K_CTRY_CODE; /* Default regulation domain if stored value EEPROM value is invalid */ #define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ @@ -959,295 +941,295 @@ typedef enum ieee80211_countrycode AR5K_CTRY_CODE; struct ath_hal; -typedef AR5K_BOOL (ath5k_rfgain_t) - (struct ath_hal *, AR5K_CHANNEL *, u_int); +typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); /* * HAL Functions that have different implementations for each chipset... */ #define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ath5k_##_n##_##_f #define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ - _t const AR5K_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, u_int mode); \ + _t const struct ath5k_rate_table *(_a _n##_get_rate_table)(struct ath_hal *, \ + u_int mode); \ _t void (_a _n##_detach)(struct ath_hal *); \ /* Reset functions */ \ - _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, enum ieee80211_if_types, AR5K_CHANNEL *, \ - AR5K_BOOL change_channel, AR5K_STATUS *status); \ - _t void (_a _n##_set_opmode)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_phy_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ + _t bool (_a _n##_reset)(struct ath_hal *, enum ieee80211_if_types, \ + struct ath5k_channel *, bool change_channel, enum ath5k_status *status);\ + _t void (_a _n##_set_opmode)(struct ath_hal *); \ + _t bool (_a _n##_phy_calibrate)(struct ath_hal*, struct ath5k_channel *); \ /* Transmit functions */ \ - _t AR5K_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, AR5K_BOOL level); \ - _t int (_a _n##_setup_tx_queue)(struct ath_hal *, AR5K_TX_QUEUE, AR5K_TXQ_INFO *); \ - _t AR5K_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ - const AR5K_TXQ_INFO *); \ - _t AR5K_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ - _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u_int32_t phys_addr); \ - _t AR5K_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, \ - u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index,\ - u_int antenna_mode, u_int flags, u_int rtscts_rate, \ - u_int rtscts_duration); \ - _t AR5K_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ - u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ - _t AR5K_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ - AR5K_BOOL firstSeg, AR5K_BOOL lastSeg, const struct ath_desc *);\ - _t AR5K_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ - _t AR5K_BOOL (_a _n##_has_veol)(struct ath_hal *); \ + _t bool (_a _n##_update_tx_triglevel)(struct ath_hal*, bool level); \ + _t int (_a _n##_setup_tx_queue)(struct ath_hal *, enum ath5k_tx_queue, \ + struct ath5k_txq_info *); \ + _t bool (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ + const struct ath5k_txq_info *); \ + _t bool (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ + _t u32 (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u32 phys_addr); \ + _t bool (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int packet_length, u_int header_length, enum ath5k_pkt_type type, \ + u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \ + u_int antenna_mode, u_int flags, u_int rtscts_rate, \ + u_int rtscts_duration); \ + _t bool (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ + u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ + _t bool (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ + bool firstSeg, bool lastSeg, const struct ath_desc *); \ + _t enum ath5k_status (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ + _t bool (_a _n##_has_veol)(struct ath_hal *); \ /* Receive Functions */ \ - _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \ - _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \ + _t u32 (_a _n##_get_rx_buf)(struct ath_hal*); \ + _t void (_a _n##_put_rx_buf)(struct ath_hal*, u32 rxdp); \ _t void (_a _n##_start_rx)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \ + _t bool (_a _n##_stop_rx_dma)(struct ath_hal*); \ _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \ _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \ - _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u_int32_t filter0, \ - u_int32_t filter1); \ - _t AR5K_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, u_int32_t index); \ - _t AR5K_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*,u_int32_t index); \ - _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \ - _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \ - _t AR5K_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t size, u_int flags); \ - _t AR5K_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t phyAddr, struct ath_desc *next); \ - _t void (_a _n##_set_rx_signal)(struct ath_hal *, const AR5K_NODE_STATS *); \ + _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u32 filter0, \ + u32 filter1); \ + _t bool (_a _n##_set_mcast_filterindex)(struct ath_hal*, u32 index); \ + _t bool (_a _n##_clear_mcast_filter_idx)(struct ath_hal*, u32 index); \ + _t u32 (_a _n##_get_rx_filter)(struct ath_hal*); \ + _t void (_a _n##_set_rx_filter)(struct ath_hal*, u32); \ + _t bool (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u32 size, u_int flags); \ + _t enum ath5k_status (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u32 phyAddr, struct ath_desc *next); \ + _t void (_a _n##_set_rx_signal)(struct ath_hal *, const struct ath5k_node_stats *); \ /* Misc Functions */ \ - _t void (_a _n##_dump_state)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ - u_int32_t argsize, void **result, u_int32_t *resultsize); \ - _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \ - _t AR5K_BOOL (_a _n##_set_lladdr)(struct ath_hal *, const u_int8_t*); \ - _t AR5K_BOOL (_a _n##_set_regdomain)(struct ath_hal*, u_int16_t, AR5K_STATUS *); \ - _t void (_a _n##_set_ledstate)(struct ath_hal*, AR5K_LED_STATE); \ - _t void (_a _n##_set_associd)(struct ath_hal*, const u_int8_t *bssid, \ - u_int16_t assocId); \ - _t AR5K_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, u_int32_t gpio); \ - _t AR5K_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, u_int32_t gpio); \ - _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \ - _t AR5K_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, u_int32_t val); \ - _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \ - _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \ - _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \ - _t void (_a _n##_reset_tsf)(struct ath_hal*); \ - _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \ - _t void (_a _n##_update_mib_counters)(struct ath_hal*, AR5K_MIB_STATS*); \ - _t AR5K_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \ - _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ - _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \ - _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \ + _t void (_a _n##_dump_state)(struct ath_hal *); \ + _t bool (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ + u32 argsize, void **result, u32 *resultsize); \ + _t void (_a _n##_get_lladdr)(struct ath_hal *, u8 *); \ + _t bool (_a _n##_set_lladdr)(struct ath_hal *, const u8*); \ + _t bool (_a _n##_set_regdomain)(struct ath_hal*, u16, enum ath5k_status *); \ + _t void (_a _n##_set_ledstate)(struct ath_hal*, unsigned int); \ + _t void (_a _n##_set_associd)(struct ath_hal*, const u8 *bssid, \ + u16 assocId); \ + _t bool (_a _n##_set_gpio_input)(struct ath_hal *, u32 gpio); \ + _t bool (_a _n##_set_gpio_output)(struct ath_hal *, u32 gpio); \ + _t u32 (_a _n##_get_gpio)(struct ath_hal *, u32 gpio); \ + _t bool (_a _n##_set_gpio)(struct ath_hal *, u32 gpio, u32 val); \ + _t void (_a _n##_set_gpio_intr)(struct ath_hal *, u_int, u32); \ + _t u32 (_a _n##_get_tsf32)(struct ath_hal *); \ + _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal *); \ + _t void (_a _n##_reset_tsf)(struct ath_hal *); \ + _t u16 (_a _n##_get_regdomain)(struct ath_hal *); \ + _t bool (_a _n##_detect_card_present)(struct ath_hal *); \ + _t void (_a _n##_update_mib_counters)(struct ath_hal *, struct ath5k_mib_stats *); \ + _t enum ath5k_rfgain (_a _n##_get_rf_gain)(struct ath_hal *); \ + _t bool (_a _n##_set_slot_time)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_slot_time)(struct ath_hal *); \ + _t bool (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_ack_timeout)(struct ath_hal *); \ + _t bool (_a _n##_set_cts_timeout)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_cts_timeout)(struct ath_hal *); \ /* Key Cache Functions */ \ - _t AR5K_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, AR5K_CIPHER); \ - _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_reset_key)(struct ath_hal*, u_int16_t); \ - _t AR5K_BOOL (_a _n##_is_key_valid)(struct ath_hal *, u_int16_t); \ - _t AR5K_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, const AR5K_KEYVAL *, \ - const u_int8_t *, int); \ - _t AR5K_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, u_int16_t, const u_int8_t *); \ + _t bool (_a _n##_is_cipher_supported)(struct ath_hal*, enum ath5k_cipher); \ + _t u32 (_a _n##_get_keycache_size)(struct ath_hal*); \ + _t bool (_a _n##_reset_key)(struct ath_hal*, u16); \ + _t bool (_a _n##_is_key_valid)(struct ath_hal *, u16); \ + _t bool (_a _n##_set_key)(struct ath_hal*, u16, const struct ath5k_keyval *, \ + const u8 *, int); \ + _t bool (_a _n##_set_key_lladdr)(struct ath_hal*, u16, const u8 *); \ /* Power Management Functions */ \ - _t AR5K_BOOL (_a _n##_set_power)(struct ath_hal*, AR5K_POWER_MODE mode, \ - AR5K_BOOL set_chip, u_int16_t sleep_duration); \ - _t AR5K_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, u_int16_t); \ - _t AR5K_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \ + _t bool (_a _n##_set_power)(struct ath_hal*, enum ath5k_power_mode mode, \ + bool set_chip, u16 sleep_duration); \ + _t enum ath5k_power_mode (_a _n##_get_power_mode)(struct ath_hal*); \ + _t bool (_a _n##_query_pspoll_support)(struct ath_hal*); \ + _t bool (_a _n##_init_pspoll)(struct ath_hal*); \ + _t bool (_a _n##_enable_pspoll)(struct ath_hal *, u8 *, u16); \ + _t bool (_a _n##_disable_pspoll)(struct ath_hal *); \ /* Beacon Management Functions */ \ - _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, u_int32_t intval); \ - _t void (_a _n##_set_beacon_timers)(struct ath_hal *, const AR5K_BEACON_STATE *); \ + _t void (_a _n##_init_beacon)(struct ath_hal *, u32 nexttbtt, u32 intval); \ + _t void (_a _n##_set_beacon_timers)(struct ath_hal *, \ + const struct ath5k_beacon_state *); \ _t void (_a _n##_reset_beacon)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, unsigned long); \ + _t bool (_a _n##_wait_for_beacon)(struct ath_hal *, unsigned long); \ /* Interrupt functions */ \ - _t AR5K_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_get_isr)(struct ath_hal *, u_int32_t *); \ - _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \ - _t AR5K_INT (_a _n##_set_intr)(struct ath_hal *, AR5K_INT); \ + _t bool (_a _n##_is_intr_pending)(struct ath_hal *); \ + _t bool (_a _n##_get_isr)(struct ath_hal *, u32 *); \ + _t u32 (_a _n##_get_intr)(struct ath_hal *); \ + _t enum ath5k_int (_a _n##_set_intr)(struct ath_hal *, enum ath5k_int); \ /* Chipset functions (ar5k-specific, non-HAL) */ \ - _t AR5K_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \ - _t void (_a _n##_radar_alert)(struct ath_hal *, AR5K_BOOL enable); \ - _t AR5K_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \ - _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, u_int16_t *data); \ - _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, u_int16_t data); \ + _t bool (_a _n##_get_capabilities)(struct ath_hal *); \ + _t void (_a _n##_radar_alert)(struct ath_hal *, bool enable); \ + _t bool (_a _n##_eeprom_is_busy)(struct ath_hal *); \ + _t int (_a _n##_eeprom_read)(struct ath_hal *, u32 offset, u16 *data); \ + _t int (_a _n##_eeprom_write)(struct ath_hal *, u32 offset, u16 data); \ /* Functions not found in OpenBSD */ \ - _t AR5K_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, AR5K_TXQ_INFO *); \ - _t AR5K_STATUS (_a _n##_get_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, \ - u_int32_t, u_int32_t *); \ - _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ - _t AR5K_BOOL (_a _n##_phy_disable)(struct ath_hal *); \ + _t bool (_a _n##_get_tx_queueprops)(struct ath_hal *, int, struct ath5k_txq_info *); \ + _t enum ath5k_status (_a _n##_get_capability)(struct ath_hal *, \ + enum ath5k_capability_type, u32, u32 *); \ + _t u32 (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ + _t bool (_a _n##_phy_disable)(struct ath_hal *); \ _t void (_a _n##_set_pcu_config)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ + _t bool (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \ _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n ##_set_bssid_mask)(struct ath_hal *, const u_int8_t*); \ + _t bool (_a _n ##_set_bssid_mask)(struct ath_hal *, const u8 *); \ /*Totaly unimplemented*/ \ - _t AR5K_BOOL (_a _n##_set_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, u_int32_t,\ - u_int32_t,AR5K_STATUS *) ; \ - _t void (_a _n##_proc_mib_event)(struct ath_hal *, const AR5K_NODE_STATS *) ; \ - _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *); + _t bool (_a _n##_set_capability)(struct ath_hal *, enum ath5k_capability_type, u32, \ + u32,enum ath5k_status *); \ + _t void (_a _n##_proc_mib_event)(struct ath_hal *, const struct ath5k_node_stats *); \ + _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u32 *); #define AR5K_MAX_GPIO 10 #define AR5K_MAX_RF_BANKS 8 struct ath_hal { - u_int32_t ah_magic; - u_int16_t ah_device; - u_int16_t ah_sub_vendor; + u32 ah_magic; + u16 ah_device; + u16 ah_sub_vendor; void *ah_sc; void __iomem *ah_sh; - AR5K_CTRY_CODE ah_country_code; + enum ieee80211_countrycode ah_country_code; - AR5K_INT ah_imr; + enum ath5k_int ah_imr; enum ieee80211_if_types ah_op_mode; - AR5K_POWER_MODE ah_power_mode; - AR5K_CHANNEL ah_current_channel; - AR5K_BOOL ah_turbo; - AR5K_BOOL ah_calibration; - AR5K_BOOL ah_running; - AR5K_BOOL ah_single_chip; - AR5K_RFGAIN ah_rf_gain; - - AR5K_RATE_TABLE ah_rt_11a; - AR5K_RATE_TABLE ah_rt_11b; - AR5K_RATE_TABLE ah_rt_11g; - AR5K_RATE_TABLE ah_rt_turbo; - AR5K_RATE_TABLE ah_rt_xr; - - u_int32_t ah_mac_srev; - u_int16_t ah_mac_version; - u_int16_t ah_mac_revision; - u_int16_t ah_phy_revision; - u_int16_t ah_radio_5ghz_revision; - u_int16_t ah_radio_2ghz_revision; + enum ath5k_power_mode ah_power_mode; + struct ath5k_channel ah_current_channel; + bool ah_turbo; + bool ah_calibration; + bool ah_running; + bool ah_single_chip; + enum ath5k_rfgain ah_rf_gain; + + struct ath5k_rate_table ah_rt_11a; + struct ath5k_rate_table ah_rt_11b; + struct ath5k_rate_table ah_rt_11g; + struct ath5k_rate_table ah_rt_turbo; + struct ath5k_rate_table ah_rt_xr; + + u32 ah_mac_srev; + u16 ah_mac_version; + u16 ah_mac_revision; + u16 ah_phy_revision; + u16 ah_radio_5ghz_revision; + u16 ah_radio_2ghz_revision; enum ath5k_version ah_version; enum ath5k_radio ah_radio; - u_int32_t ah_phy; + u32 ah_phy; - AR5K_BOOL ah_5ghz; - AR5K_BOOL ah_2ghz; + bool ah_5ghz; + bool ah_2ghz; #define ah_regdomain ah_capabilities.cap_regdomain.reg_current -#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw #define ah_modes ah_capabilities.cap_mode #define ah_ee_version ah_capabilities.cap_eeprom.ee_version - u_int32_t ah_atim_window; - u_int32_t ah_aifs; - u_int32_t ah_cw_min; - u_int32_t ah_cw_max; - AR5K_BOOL ah_software_retry; - u_int32_t ah_limit_tx_retries; + u32 ah_atim_window; + u32 ah_aifs; + u32 ah_cw_min; + u32 ah_cw_max; + bool ah_software_retry; + u32 ah_limit_tx_retries; - u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; - AR5K_BOOL ah_ant_diversity; + u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + bool ah_ant_diversity; - u_int8_t ah_sta_id[ETH_ALEN]; - u_int8_t ah_bssid[ETH_ALEN]; + u8 ah_sta_id[ETH_ALEN]; + u8 ah_bssid[ETH_ALEN]; - u_int32_t ah_gpio[AR5K_MAX_GPIO]; + u32 ah_gpio[AR5K_MAX_GPIO]; int ah_gpio_npins; - ath5k_capabilities_t ah_capabilities; + struct ath5k_capabilities ah_capabilities; - AR5K_TXQ_INFO ah_txq[AR5K_NUM_TX_QUEUES]; - u_int32_t ah_txq_interrupts; + struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; + u32 ah_txq_interrupts; - u_int32_t *ah_rf_banks; + u32 *ah_rf_banks; size_t ah_rf_banks_size; struct ath5k_gain ah_gain; - u_int32_t ah_offset[AR5K_MAX_RF_BANKS]; + u32 ah_offset[AR5K_MAX_RF_BANKS]; struct { - u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; - u_int16_t txp_rates[AR5K_MAX_RATES]; - int16_t txp_min, txp_max; - AR5K_BOOL txp_tpc; - int16_t txp_ofdm; + u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; + u16 txp_rates[AR5K_MAX_RATES]; + s16 txp_min, txp_max; + bool txp_tpc; + s16 txp_ofdm; } ah_txpower; struct { - AR5K_BOOL r_enabled; + bool r_enabled; int r_last_alert; - AR5K_CHANNEL r_last_channel; + struct ath5k_channel r_last_channel; } ah_radar; /* * Function pointers */ AR5K_HAL_FUNCTIONS(, ah, *) - }; /* * Prototypes */ -const char *ath_hal_probe(u16, u16); -struct ath_hal *ath5k_hw_init(u16, void *, void __iomem *, - AR5K_STATUS *); -u_int16_t ath_hal_computetxtime(struct ath_hal *, const AR5K_RATE_TABLE *, - u_int32_t, u_int16_t, AR5K_BOOL); -u_int ath_hal_mhz2ieee(u_int, u_int); -u_int ath_hal_ieee2mhz(u_int, u_int); -AR5K_BOOL ath_hal_init_channels(struct ath_hal *, AR5K_CHANNEL *, - u_int, u_int *, AR5K_CTRY_CODE, u_int16_t, - AR5K_BOOL, AR5K_BOOL); -const char* ath5k_printver(enum ath5k_srev_type, u_int32_t); -void ath5k_radar_alert(struct ath_hal *); -ieee80211_regdomain_t ath5k_regdomain_to_ieee(u_int16_t); -u_int16_t ath5k_regdomain_from_ieee(ieee80211_regdomain_t); -u_int16_t ath5k_get_regdomain(struct ath_hal *); -u_int32_t ath5k_bitswap(u_int32_t, u_int); -inline u_int ath5k_clocktoh(u_int, AR5K_BOOL); -inline u_int ath5k_htoclock(u_int, AR5K_BOOL); -void ath5k_rt_copy(AR5K_RATE_TABLE *, const AR5K_RATE_TABLE *); -AR5K_BOOL ath5k_register_timeout(struct ath_hal *, u_int32_t, u_int32_t, - u_int32_t, AR5K_BOOL); -int ath5k_eeprom_init(struct ath_hal *); -int ath5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); -AR5K_BOOL ath5k_eeprom_regulation_domain(struct ath_hal *, AR5K_BOOL, +const char *ath_hal_probe(u16, u16); +struct ath_hal *ath5k_hw_init(u16, void *, void __iomem *, enum ath5k_status *); +u16 ath_hal_computetxtime(struct ath_hal *, const struct ath5k_rate_table *, + u32, u16, bool); +u_int ath_hal_mhz2ieee(u_int, u_int); +u_int ath_hal_ieee2mhz(u_int, u_int); +bool ath_hal_init_channels(struct ath_hal *, struct ath5k_channel *, + u_int, u_int *, enum ieee80211_countrycode, u16, + bool, bool); +const char *ath5k_printver(enum ath5k_srev_type, u32); +void ath5k_radar_alert(struct ath_hal *); +ieee80211_regdomain_t ath5k_regdomain_to_ieee(u16); +u16 ath5k_regdomain_from_ieee(ieee80211_regdomain_t); +u16 ath5k_get_regdomain(struct ath_hal *); +u32 ath5k_bitswap(u32, u_int); +inline u_int ath5k_clocktoh(u_int, bool); +inline u_int ath5k_htoclock(u_int, bool); +void ath5k_rt_copy(struct ath5k_rate_table *, const struct ath5k_rate_table *); +bool ath5k_register_timeout(struct ath_hal *, u32, u32, + u32, bool); +int ath5k_eeprom_init(struct ath_hal *); +int ath5k_eeprom_read_mac(struct ath_hal *, u8 *); +bool ath5k_eeprom_regulation_domain(struct ath_hal *, bool, ieee80211_regdomain_t *); -int ath5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); -int ath5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); -u_int16_t ath5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); - -AR5K_BOOL ath5k_hw_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_hw_rf5110_channel(struct ath_hal *, AR5K_CHANNEL *); -u_int32_t ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *); -AR5K_BOOL ath5k_hw_rf5111_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_hw_rf5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); -AR5K_BOOL ath5k_hw_rf5112_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); - -AR5K_BOOL ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); -AR5K_BOOL ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); -AR5K_BOOL ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); - -AR5K_BOOL ath5k_hw_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -AR5K_BOOL ath5k_hw_rf5111_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -AR5K_BOOL ath5k_hw_rf5112_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -void ath5k_hw_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int, u_int); -u_int ath5k_hw_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, - u_int32_t, u_int32_t, AR5K_BOOL); -u_int32_t ath5k_hw_rfregs_gainf_corr(struct ath_hal *); -AR5K_BOOL ath5k_hw_rfregs_gain_readback(struct ath_hal *); -int32_t ath5k_hw_rfregs_gain_adjust(struct ath_hal *); -AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); -void ath5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); +int ath5k_eeprom_read_ants(struct ath_hal *, u32 *, u_int); +int ath5k_eeprom_read_modes(struct ath_hal *, u32 *, u_int); +u16 ath5k_eeprom_bin2freq(struct ath_hal *, u16, u_int); + +bool ath5k_hw_channel(struct ath_hal *, struct ath5k_channel *); +bool ath5k_hw_rf5110_channel(struct ath_hal *, struct ath5k_channel *); +u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *); +bool ath5k_hw_rf5111_channel(struct ath_hal *, struct ath5k_channel *); +bool ath5k_hw_rf5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); +bool ath5k_hw_rf5112_channel(struct ath_hal *, struct ath5k_channel *); +bool ath5k_check_channel(struct ath_hal *, u16, u_int flags); + +bool ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); + +bool ath5k_hw_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); +bool ath5k_hw_rf5111_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); +bool ath5k_hw_rf5112_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); +void ath5k_hw_ar5211_rfregs(struct ath_hal *, struct ath5k_channel *, u_int, u_int); +u_int ath5k_hw_rfregs_op(u32 *, u32, u32, u32, + u32, u32, bool); +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *); +bool ath5k_hw_rfregs_gain_readback(struct ath_hal *); +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *); +bool ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); +void ath5k_txpower_table(struct ath_hal *, struct ath5k_channel *, s16); /*added*/ -extern u_int ath_hal_getwirelessmodes(struct ath_hal *, AR5K_CTRY_CODE); +extern u_int ath_hal_getwirelessmodes(struct ath_hal *, enum ieee80211_countrycode); void ath_hal_detach(struct ath_hal *ah); struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, - AR5K_STATUS *s); + enum ath5k_status *s); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 85f4e88..b20bc3d 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -25,6 +25,7 @@ #include #include +#include #include "ah_devid.h" #include "ath5k.h" @@ -71,18 +72,18 @@ static const struct { }; /*Rate tables*/ -static const AR5K_RATE_TABLE ath5k_rt_11a = AR5K_RATES_11A; -static const AR5K_RATE_TABLE ath5k_rt_11b = AR5K_RATES_11B; -static const AR5K_RATE_TABLE ath5k_rt_11g = AR5K_RATES_11G; -static const AR5K_RATE_TABLE ath5k_rt_turbo = AR5K_RATES_TURBO; -static const AR5K_RATE_TABLE ath5k_rt_xr = AR5K_RATES_XR; +static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; +static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; +static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G; +static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; +static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -AR5K_BOOL ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); -AR5K_BOOL ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t, AR5K_BOOL); -u_int16_t ath5k_hw_radio_revision(struct ath_hal *, AR5K_CHIP); +bool ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); +bool ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t, bool); +u_int16_t ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); void ath5k_hw_fill(struct ath_hal *); -AR5K_BOOL ath5k_hw_txpower(struct ath_hal *, AR5K_CHANNEL *, u_int); +bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, u_int); AR5K_HAL_FUNCTIONS(extern, ath5k_hw,); @@ -167,10 +168,10 @@ EXPORT_SYMBOL(ath_hal_probe); * TODO: Left here for combatibility, change it in ath5k */ u_int16_t /*TODO: Is this really hardware dependent ?*/ -ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates, - u_int32_t frame_length, u_int16_t rate_index, AR5K_BOOL short_preamble) +ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, + u_int32_t frame_length, u_int16_t rate_index, bool short_preamble) { - const AR5K_RATE *rate; + const struct ath5k_rate *rate; u_int32_t value; AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); @@ -234,7 +235,7 @@ EXPORT_SYMBOL(ath_hal_computetxtime); * TODO:Left here for combatibility, change it in at5k */ u_int/*TODO:Fix this */ -ath_hal_getwirelessmodes(struct ath_hal *hal, AR5K_CTRY_CODE country) +ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) { switch(hal->ah_version){ case AR5K_AR5212: @@ -265,13 +266,13 @@ ath5k_hw_bitswap(u_int32_t val, u_int bits) } inline u_int -ath5k_hw_htoclock(u_int usec, AR5K_BOOL turbo) +ath5k_hw_htoclock(u_int usec, bool turbo) { return (turbo == TRUE ? (usec * 80) : (usec * 40)); } inline u_int -ath5k_hw_clocktoh(u_int clock, AR5K_BOOL turbo) +ath5k_hw_clocktoh(u_int clock, bool turbo) { return (turbo == TRUE ? (clock / 80) : (clock / 40)); } @@ -280,9 +281,9 @@ ath5k_hw_clocktoh(u_int clock, AR5K_BOOL turbo) * Copy a rate table to a new one */ inline void -ath5k_hw_rtcopy(AR5K_RATE_TABLE *dst, const AR5K_RATE_TABLE *src) +ath5k_hw_rtcopy(struct ath5k_rate_table *dst, const struct ath5k_rate_table *src) { - memset(dst, 0, sizeof(AR5K_RATE_TABLE)); + memset(dst, 0, sizeof(struct ath5k_rate_table)); dst->rate_count = src->rate_count; memcpy(dst->rates, src->rates, sizeof(dst->rates)); } @@ -326,9 +327,9 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) /* * Check if a register write has been completed */ -static AR5K_BOOL +static bool ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, - u_int32_t val, AR5K_BOOL is_set) + u_int32_t val, bool is_set) { int i; u_int32_t data; @@ -358,7 +359,7 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, * Check if the device is supported and initialize the needed structs */ struct ath_hal * -ath5k_hw_init(u16 device, void *sc, void __iomem *sh, AR5K_STATUS *status) +ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) { struct ath_hal *hal = NULL; u_int8_t mac[ETH_ALEN]; @@ -562,8 +563,8 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, AR5K_STATUS *status) /* * Bring up MAC + PHY Chips */ -AR5K_BOOL -ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, AR5K_BOOL initial) +bool +ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) { u_int32_t turbo, mode, clock; @@ -694,7 +695,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, AR5K_BOOL initial) * Get the PHY Chip revision */ u_int16_t -ath5k_hw_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) +ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) { int i; u_int32_t srev; @@ -744,7 +745,7 @@ ath5k_hw_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) * Get the rate table for a specific operation mode * TODO:Limit this per chipset */ -const AR5K_RATE_TABLE * +const struct ath5k_rate_table * ath5k_hw_get_rate_table(struct ath_hal *hal, u_int mode) { @@ -795,15 +796,15 @@ ath5k_hw_detach(struct ath_hal *hal) /* * Main reset function */ -AR5K_BOOL +bool ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, - AR5K_CHANNEL *channel, AR5K_BOOL change_channel, AR5K_STATUS *status) + struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int8_t mac[ETH_ALEN]; u_int32_t data, noise_floor, s_seq, s_ant, s_led[3]; u_int i, phy, mode, freq, off, ee_mode, ant[2]; - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; AR5K_TRACE; @@ -1380,10 +1381,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /* * Reset chipset */ -AR5K_BOOL +bool ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) { - AR5K_BOOL ret = FALSE; + bool ret = FALSE; u_int32_t mask = val ? val : ~0; AR5K_TRACE; @@ -1428,9 +1429,9 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) /* * Sleep control */ -AR5K_BOOL -ath5k_hw_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, - AR5K_BOOL set_chip, u_int16_t sleep_duration) +bool +ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, + bool set_chip, u_int16_t sleep_duration) { u_int32_t staid; int i; @@ -1499,7 +1500,7 @@ ath5k_hw_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, * Get power mode (sleep state) * TODO:Remove ? */ -AR5K_POWER_MODE +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal) { AR5K_TRACE; @@ -1530,7 +1531,7 @@ ath5k_hw_start_rx(struct ath_hal *hal) /* * Stop DMA receive */ -AR5K_BOOL +bool ath5k_hw_stop_rx_dma(struct ath_hal *hal) { int i; @@ -1578,7 +1579,7 @@ ath5k_hw_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) * Start DMA transmit for a specific queue * (see also QCU/DCU functions) */ -AR5K_BOOL +bool ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) { u_int32_t tx_queue; @@ -1635,7 +1636,7 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) * Stop DMA transmit for a specific queue * (see also QCU/DCU functions) */ -AR5K_BOOL +bool ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) { int i = 100, pending; @@ -1729,7 +1730,7 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) * Set the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) */ -AR5K_BOOL +bool ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) { u_int16_t tx_reg; @@ -1773,11 +1774,11 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) /* * Update tx trigger level */ -AR5K_BOOL -ath5k_hw_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) +bool +ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) { u_int32_t trigger_level, imr; - AR5K_BOOL status = FALSE; + bool status = FALSE; AR5K_TRACE; /* @@ -1823,7 +1824,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) /* * Check if we have pending interrupts */ -AR5K_BOOL +bool ath5k_hw_is_intr_pending(struct ath_hal *hal) { AR5K_TRACE; @@ -1833,7 +1834,7 @@ ath5k_hw_is_intr_pending(struct ath_hal *hal) /* * Get interrupt mask (ISR) */ -AR5K_BOOL +bool ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) { u_int32_t data; @@ -1919,10 +1920,10 @@ ath5k_hw_get_intr(struct ath_hal *hal) /* * Set interrupt mask */ -AR5K_INT -ath5k_hw_set_intr(struct ath_hal *hal, AR5K_INT new_mask) +enum ath5k_int +ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) { - AR5K_INT old_mask, int_mask; + enum ath5k_int old_mask, int_mask; /* * Disable card interrupts to prevent any race conditions @@ -1977,7 +1978,7 @@ ath5k_hw_set_intr(struct ath_hal *hal, AR5K_INT new_mask) * Enalbe HW radar detection */ void -ath5k_hw_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) +ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) { AR5K_TRACE; @@ -2029,7 +2030,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) /* * Check if eeprom is busy */ -AR5K_BOOL +bool ath5k_hw_eeprom_is_busy(struct ath_hal *hal) { AR5K_TRACE; @@ -2527,8 +2528,8 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) /* * Read/Write refulatory domain */ -AR5K_BOOL -ath5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, +bool +ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, ieee80211_regdomain_t *regdomain) { u_int16_t ee_regdomain; @@ -2558,9 +2559,9 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, /* * Use the above to write a new regulatory domain */ -AR5K_BOOL +bool ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - AR5K_STATUS *status) + enum ath5k_status *status) { ieee80211_regdomain_t ieee_regdomain; @@ -2580,7 +2581,7 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, /* * Fill the capabilities struct */ -AR5K_BOOL +bool ath5k_hw_get_capabilities(struct ath_hal *hal) { u_int16_t ee_header; @@ -2741,7 +2742,7 @@ ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) /* * Set station id */ -AR5K_BOOL +bool ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) { u_int32_t low_id, high_id; @@ -2801,7 +2802,7 @@ ath5k_hw_set_associd(struct ath_hal *hal, const u_int8_t *bssid, /* * Set BSSID mask on 5212 */ -AR5K_BOOL +bool ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) { u_int32_t low_id, high_id; @@ -2864,7 +2865,7 @@ ath5k_hw_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, /* * Set multicast filter by index */ -AR5K_BOOL +bool ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) { @@ -2884,7 +2885,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) /* * Clear Multicast filter by index */ -AR5K_BOOL +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) { @@ -3060,13 +3061,13 @@ ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, * Set beacon timers */ void -ath5k_hw_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) +ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state) { u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; /* * TODO: should be changed through *state - * review AR5K_BEACON_STATE struct + * review struct ath5k_beacon_state struct * * XXX: These are used for cfp period bellow, are they * ok ? Is it O.K. for tsf here to be 0 or should we use @@ -3207,10 +3208,10 @@ ath5k_hw_reset_beacon(struct ath_hal *hal) * Wait for beacon queue to finish * TODO: This function's name is misleading, rename */ -AR5K_BOOL +bool ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) { - AR5K_BOOL ret; + bool ret; int i; AR5K_TRACE; @@ -3254,7 +3255,7 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) * Update mib counters (statistics) */ void -ath5k_hw_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) +ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statistics) { AR5K_TRACE; /* Read-And-Clear */ @@ -3274,7 +3275,7 @@ ath5k_hw_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) } void /*Unimplemented*/ -ath5k_hw_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) +ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; return; @@ -3287,7 +3288,7 @@ ath5k_hw_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) /* * Set ACK timeout on PCU */ -AR5K_BOOL +bool ath5k_hw_set_ack_timeout(struct ath_hal *hal, u_int timeout) { AR5K_TRACE; @@ -3315,7 +3316,7 @@ ath5k_hw_get_ack_timeout(struct ath_hal *hal) /* * Set CTS timeout on PCU */ -AR5K_BOOL +bool ath5k_hw_set_cts_timeout(struct ath_hal *hal, u_int timeout) { AR5K_TRACE; @@ -3347,8 +3348,8 @@ ath5k_hw_get_cts_timeout(struct ath_hal *hal) /* * Return which ciphers are supported by hw */ -AR5K_BOOL -ath5k_hw_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) +bool +ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) { AR5K_TRACE; /* @@ -3373,7 +3374,7 @@ ath5k_hw_get_keycache_size(struct ath_hal *hal) /* * Reset encryption key */ -AR5K_BOOL +bool ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) { int i; @@ -3395,7 +3396,7 @@ ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) /* * Check if a key entry is valid */ -AR5K_BOOL +bool ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) { AR5K_TRACE; @@ -3414,9 +3415,9 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) /* * Set encryption key */ -AR5K_BOOL +bool ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, - const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) + const struct ath5k_keyval *keyval, const u_int8_t *mac, int xor_notused) { int i; u_int32_t key_v[AR5K_KEYCACHE_SIZE - 2]; @@ -3462,7 +3463,7 @@ ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, return (ath5k_hw_set_key_lladdr(hal, entry, mac)); } -AR5K_BOOL +bool ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, const u_int8_t *mac) { @@ -3500,8 +3501,8 @@ Queue Control Unit, DFS Control Unit Functions * Initialize a transmit queue */ int -ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, - AR5K_TXQ_INFO *queue_info) +ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, + struct ath5k_txq_info *queue_info) { u_int queue; AR5K_TRACE; @@ -3555,7 +3556,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, /* * Setup internal queue structure */ - memset(&hal->ah_txq[queue], 0, sizeof(AR5K_TXQ_INFO)); + memset(&hal->ah_txq[queue], 0, sizeof(struct ath5k_txq_info)); hal->ah_txq[queue].tqi_type = queue_type; if (queue_info != NULL) { @@ -3577,9 +3578,9 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, /* * Setup a transmit queue */ -AR5K_BOOL +bool ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, - const AR5K_TXQ_INFO *queue_info) + const struct ath5k_txq_info *queue_info) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3587,7 +3588,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) return (FALSE); - memcpy(&hal->ah_txq[queue], queue_info, sizeof(AR5K_TXQ_INFO)); + memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); /*XXX: Is this supported on 5210 ?*/ if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && @@ -3603,18 +3604,18 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, /* * Get properties for a specific transmit queue */ -AR5K_BOOL -ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) +bool +ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info *queue_info) { AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); return (TRUE); } /* * Set a transmit queue inactive */ -AR5K_BOOL +bool ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) { AR5K_TRACE; @@ -3631,11 +3632,11 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) /* * Set DFS params for a transmit queue */ -AR5K_BOOL +bool ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) { u_int32_t cw_min, cw_max, retry_lg, retry_sh; - AR5K_TXQ_INFO *tq = &hal->ah_txq[queue]; + struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; struct ath5k_ar5210_ini_mode ar5210_mode[] = AR5K_AR5210_INI_MODE(hal->ah_aifs + tq->tqi_aifs); @@ -3870,7 +3871,7 @@ ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) { /* * Set slot time */ -AR5K_BOOL +bool ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) { AR5K_TRACE; @@ -3914,9 +3915,9 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) /* * Initialize the 2-word tx descriptor on 5210/5211 */ -static AR5K_BOOL +static bool ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, + u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { @@ -4011,9 +4012,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Initialize the 4-word tx descriptor on 5212 */ -static AR5K_BOOL +static bool ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, + u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { @@ -4096,7 +4097,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Initialize a 4-word XR tx descriptor on 5212 */ -static AR5K_BOOL +static bool ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, u_int tx_rate3, u_int tx_tries3) @@ -4131,9 +4132,9 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Fill the 2-word tx descriptor on 5210/5211 */ -static AR5K_BOOL +static bool ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) + u_int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4160,9 +4161,9 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Fill the 4-word tx descriptor on 5212 * XXX: Added an argument *last_desc -need revision */ -static AR5K_BOOL +static bool ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, + u_int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4192,7 +4193,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the tx status descriptor on 5210/5211 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; @@ -4251,7 +4252,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* * Proccess a tx descriptor on 5212 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; @@ -4344,7 +4345,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* * Initialize an rx descriptor */ -AR5K_BOOL +bool ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t size, u_int flags) { @@ -4380,7 +4381,7 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the rx status descriptor on 5210/5211 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { @@ -4455,7 +4456,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the rx status descriptor on 5212 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { @@ -4543,7 +4544,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, * Set led state */ void -ath5k_hw_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) +ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) { u_int32_t led; /*5210 has different led mode handling*/ @@ -4601,7 +4602,7 @@ ath5k_hw_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) /* * Set GPIO outputs */ -AR5K_BOOL +bool ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; @@ -4618,7 +4619,7 @@ ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) /* * Set GPIO inputs */ -AR5K_BOOL +bool ath5k_hw_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; @@ -4650,7 +4651,7 @@ ath5k_hw_get_gpio(struct ath_hal *hal, u_int32_t gpio) /* * Set GPIO state */ -AR5K_BOOL +bool ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) { u_int32_t data; @@ -4771,7 +4772,7 @@ EXPORT_SYMBOL(ath_hal_ieee2mhz); /* * Check if a channel is supported */ -AR5K_BOOL +bool ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) { /* Check if the channel is in our supported range */ @@ -4792,18 +4793,18 @@ ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) * TODO: Do this in the driver, only check_channel is hw related * also left here temporarily for combatibility. */ -AR5K_BOOL -ath_hal_init_channels(struct ath_hal *hal, AR5K_CHANNEL *channels, - u_int max_channels, u_int *channels_size, AR5K_CTRY_CODE country, u_int16_t mode, - AR5K_BOOL outdoor, AR5K_BOOL extended) +bool +ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, + u_int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u_int16_t mode, + bool outdoor, bool extended) { u_int i, c; u_int32_t domain_current; u_int domain_5ghz, domain_2ghz; - AR5K_CHANNEL *all_channels; - AR5K_CTRY_CODE country_current; + struct ath5k_channel *all_channels; + enum ieee80211_countrycode country_current; - if ((all_channels = kmalloc(sizeof(AR5K_CHANNEL) * max_channels, + if ((all_channels = kmalloc(sizeof(struct ath5k_channel) * max_channels, GFP_KERNEL)) == NULL) return (FALSE); @@ -4922,7 +4923,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ } done: - memcpy(channels, all_channels, sizeof(AR5K_CHANNEL) * max_channels); + memcpy(channels, all_channels, sizeof(struct ath5k_channel) * max_channels); *channels_size = c; kfree(all_channels); return (TRUE); @@ -5002,10 +5003,10 @@ ath5k_hw_get_regdomain(struct ath_hal *hal) /* * Set a channel on the radio chip */ -AR5K_BOOL -ath5k_hw_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - AR5K_BOOL ret; + bool ret; /* * Check bounds supported by the PHY @@ -5045,7 +5046,7 @@ ath5k_hw_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) * Convertion needed for RF5110 */ u_int32_t -ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *channel) +ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) { u_int32_t athchan; @@ -5065,8 +5066,8 @@ ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *channel) /* * Set channel on RF5110 */ -AR5K_BOOL -ath5k_hw_rf5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) { u_int32_t data; @@ -5084,7 +5085,7 @@ ath5k_hw_rf5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Convertion needed for 5111 */ -AR5K_BOOL +bool ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) { int channel; @@ -5113,8 +5114,8 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) /* * Set channel on 5111 */ -AR5K_BOOL -ath5k_hw_rf5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) { u_int ieee_channel, ath_channel; u_int32_t data0, data1, clock; @@ -5157,8 +5158,8 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Set channel on 5112 */ -AR5K_BOOL -ath5k_hw_rf5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) { u_int32_t data, data0, data1, data2; u_int16_t c; @@ -5205,10 +5206,10 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Perform a PHY calibration */ -AR5K_BOOL -ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel){ +bool +ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ - AR5K_BOOL ret; + bool ret; if (hal->ah_radio == AR5K_RF5110) ret = ath5k_hw_rf5110_calibrate(hal,channel); @@ -5220,10 +5221,10 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel){ /* * Perform a PHY calibration on RF5110 */ -AR5K_BOOL -ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { - AR5K_BOOL ret = TRUE; + bool ret = TRUE; u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor; u_int i; @@ -5369,8 +5370,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Perform a PHY calibration on RF5111/5112 */ -AR5K_BOOL -ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { u_int32_t i_pwr, q_pwr; int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; @@ -5417,7 +5418,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) return (TRUE); } -AR5K_BOOL +bool ath5k_hw_phy_disable(struct ath_hal *hal) { AR5K_TRACE; @@ -5450,7 +5451,7 @@ ath5k_hw_get_def_antenna(struct ath_hal *hal) u_int ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, - u_int32_t first, u_int32_t col, AR5K_BOOL set) + u_int32_t first, u_int32_t col, bool set) { u_int32_t mask, entry, last, data, shift, position; int32_t left; @@ -5532,7 +5533,7 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) return (hal->ah_gain.g_f_corr); } -AR5K_BOOL +bool ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) { u_int32_t step, mix, level[4]; @@ -5634,11 +5635,11 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) /* * Initialize RF */ -AR5K_BOOL -ath5k_hw_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +bool +ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) { ath5k_rfgain_t *func = NULL; - AR5K_BOOL ret; + bool ret; if (hal->ah_radio == AR5K_RF5111) { hal->ah_rf_banks_size = sizeof(rf5111_rf); @@ -5672,8 +5673,8 @@ ath5k_hw_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) /* * Initialize RF5111 */ -AR5K_BOOL -ath5k_hw_rf5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +bool +ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; const u_int rf_size = AR5K_ELEMENTS(rf5111_rf); @@ -5770,8 +5771,8 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) /* * Initialize RF5112 */ -AR5K_BOOL -ath5k_hw_rf5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +bool +ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int rf_size; @@ -5867,7 +5868,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) * doesn't ar5k_rfregs work ? */ void -ath5k_hw_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, +ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int freq, u_int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -5925,7 +5926,7 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; } -AR5K_BOOL +bool ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) { int i; @@ -5955,7 +5956,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) return (TRUE); } -AR5K_RFGAIN +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal) { u_int32_t data, type; @@ -6005,7 +6006,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) * Initialize the tx power table (not fully implemented) */ void -ath5k_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t max_power) +ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t max_power) { u_int16_t txpower, *rates; int i, min, max, n; @@ -6042,10 +6043,10 @@ ath5k_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t max_powe /* * Set transmition power */ -AR5K_BOOL /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower) +bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ +ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpower) { - AR5K_BOOL tpc = hal->ah_txpower.txp_tpc; + bool tpc = hal->ah_txpower.txp_tpc; int i; AR5K_TRACE; @@ -6100,11 +6101,11 @@ ath5k_hw_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower) return (TRUE); } -AR5K_BOOL +bool ath5k_hw_set_txpower_limit(struct ath_hal *hal, u_int power) { /*Just a try M.F.*/ - AR5K_CHANNEL *channel = &hal->ah_current_channel; + struct ath5k_channel *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n",power); @@ -6222,7 +6223,7 @@ ath5k_hw_dump_state(struct ath_hal *hal) #endif } -AR5K_BOOL /*what about VEOL cap ?*/ +bool /*what about VEOL cap ?*/ ath5k_hw_has_veol(struct ath_hal *hal) { return (TRUE); @@ -6236,14 +6237,14 @@ ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) return; } -void /*Added AR5K_NODE_STATS argument*/ -ath5k_hw_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) +void /*Added struct ath5k_node_stats argument*/ +ath5k_hw_set_rx_signal(struct ath_hal *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; /* Signal state monitoring is not yet supported */ } -AR5K_BOOL /*Added arguments*/ +bool /*Added arguments*/ ath5k_hw_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) { @@ -6255,7 +6256,7 @@ const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) return (FALSE); } -AR5K_BOOL /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ +bool /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ ath5k_hw_detect_card_present(struct ath_hal *hal) { u_int16_t magic; @@ -6271,8 +6272,8 @@ ath5k_hw_detect_card_present(struct ath_hal *hal) return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); } -AR5K_STATUS -ath5k_hw_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, +enum ath5k_status +ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, u_int32_t capability, u_int32_t *result) { AR5K_TRACE; @@ -6330,11 +6331,12 @@ ath5k_hw_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, } -AR5K_BOOL -ath5k_hw_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) +bool +ath5k_hw_set_capability(struct ath_hal *hal, + enum ath5k_capability_type cap_type, + u_int32_t capability, u_int32_t setting, + enum ath5k_status *status) { - AR5K_TRACE; if (status) *status = AR5K_OK; @@ -6342,7 +6344,7 @@ ath5k_hw_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, return (FALSE); } -AR5K_BOOL +bool ath5k_hw_query_pspoll_support(struct ath_hal *hal) { AR5K_TRACE; @@ -6352,7 +6354,7 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) return (FALSE); } -AR5K_BOOL +bool ath5k_hw_init_pspoll(struct ath_hal *hal) { AR5K_TRACE; @@ -6362,7 +6364,7 @@ ath5k_hw_init_pspoll(struct ath_hal *hal) return (FALSE); } -AR5K_BOOL +bool ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, u_int16_t assoc_id) { @@ -6377,7 +6379,7 @@ ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, return (FALSE); } -AR5K_BOOL +bool ath5k_hw_disable_pspoll(struct ath_hal *hal) { AR5K_TRACE; diff --git a/openhal/ath5k_hw.h b/openhal/ath5k_hw.h index 1458dfe..3b53963 100644 --- a/openhal/ath5k_hw.h +++ b/openhal/ath5k_hw.h @@ -21,11 +21,11 @@ * Gain settings */ -typedef enum { +enum ath5k_rfgain { AR5K_RFGAIN_INACTIVE = 0, AR5K_RFGAIN_READ_REQUESTED, AR5K_RFGAIN_NEED_CHANGE, -} AR5K_RFGAIN; +}; #define AR5K_GAIN_CRN_FIX_BITS_5111 4 #define AR5K_GAIN_CRN_FIX_BITS_5112 7 @@ -55,19 +55,19 @@ struct ath5k_gain_opt_step { }; struct ath5k_gain_opt { - u_int32_t go_default; - u_int32_t go_steps_count; + u32 go_default; + u32 go_steps_count; const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; }; struct ath5k_gain { - u_int32_t g_step_idx; - u_int32_t g_current; - u_int32_t g_target; - u_int32_t g_low; - u_int32_t g_high; - u_int32_t g_f_corr; - u_int32_t g_active; + u32 g_step_idx; + u32 g_current; + u32 g_target; + u32 g_low; + u32 g_high; + u32 g_f_corr; + u32 g_active; const struct ath5k_gain_opt_step *g_step; }; @@ -146,47 +146,47 @@ struct ath5k_gain { #define AR5K_EEPROM_N_IQ_CAL 2 struct ath5k_eeprom_info { - u_int16_t ee_magic; - u_int16_t ee_protect; - u_int16_t ee_regdomain; - u_int16_t ee_version; - u_int16_t ee_header; - u_int16_t ee_ant_gain; - u_int16_t ee_misc0; - u_int16_t ee_misc1; - u_int16_t ee_cck_ofdm_gain_delta; - u_int16_t ee_cck_ofdm_power_delta; - u_int16_t ee_scaled_cck_delta; - u_int16_t ee_tx_clip; - u_int16_t ee_pwd_84; - u_int16_t ee_pwd_90; - u_int16_t ee_gain_select; - - u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES]; - u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES]; - u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES]; - u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES]; - u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES]; - u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; - u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; - u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xpd[AR5K_EEPROM_N_MODES]; - u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; - u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; - u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; - u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; - - u_int16_t ee_ctls; - u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS]; + u16 ee_magic; + u16 ee_protect; + u16 ee_regdomain; + u16 ee_version; + u16 ee_header; + u16 ee_ant_gain; + u16 ee_misc0; + u16 ee_misc1; + u16 ee_cck_ofdm_gain_delta; + u16 ee_cck_ofdm_power_delta; + u16 ee_scaled_cck_delta; + u16 ee_tx_clip; + u16 ee_pwd_84; + u16 ee_pwd_90; + u16 ee_gain_select; + + u16 ee_i_cal[AR5K_EEPROM_N_MODES]; + u16 ee_q_cal[AR5K_EEPROM_N_MODES]; + u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; + u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; + u16 ee_xr_power[AR5K_EEPROM_N_MODES]; + u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; + u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; + u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; + u16 ee_thr_62[AR5K_EEPROM_N_MODES]; + u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; + u16 ee_xpd[AR5K_EEPROM_N_MODES]; + u16 ee_x_gain[AR5K_EEPROM_N_MODES]; + u16 ee_i_gain[AR5K_EEPROM_N_MODES]; + u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_false_detect[AR5K_EEPROM_N_MODES]; + u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; + u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; + + u16 ee_ctls; + u16 ee_ctl[AR5K_EEPROM_MAX_CTLS]; int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; @@ -361,9 +361,9 @@ struct ath5k_eeprom_info { #define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS struct ath5k_ini_rf { - u_int8_t rf_bank; - u_int16_t rf_register; - u_int32_t rf_value[5]; + u8 rf_bank; + u16 rf_register; + u32 rf_value[5]; }; #define AR5K_RF5111_INI_RF { \ @@ -686,8 +686,8 @@ struct ath5k_ini_rf { } struct ath5k_ini_rfgain { - u_int16_t rfg_register; - u_int32_t rfg_value[2][2]; + u16 rfg_register; + u32 rfg_value[2][2]; #define AR5K_INI_RFGAIN_5GHZ 0 #define AR5K_INI_RFGAIN_2GHZ 1 @@ -833,14 +833,14 @@ struct ath5k_rx_desc { /* * RX control word 0 */ - u_int32_t rx_control_0; + u32 rx_control_0; #define AR5K_DESC_RX_CTL0 0x00000000 /* * RX control word 1 */ - u_int32_t rx_control_1; + u32 rx_control_1; #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 @@ -850,7 +850,7 @@ struct ath5k_hw_old_rx_status { /* * RX status word 0 */ - u_int32_t rx_status_0; + u32 rx_status_0; #define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff #define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 @@ -864,7 +864,7 @@ struct ath5k_hw_old_rx_status { /* * RX status word 1 */ - u_int32_t rx_status_1; + u32 rx_status_1; #define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 #define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 @@ -885,7 +885,7 @@ struct ath5k_hw_new_rx_status { /* * RX status word 0 */ - u_int32_t rx_status_0; + u32 rx_status_0; #define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff #define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 @@ -900,7 +900,7 @@ struct ath5k_hw_new_rx_status { /* * RX status word 1 */ - u_int32_t rx_status_1; + u32 rx_status_1; #define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 #define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 @@ -920,14 +920,14 @@ struct ath5k_hw_rx_error { /* * RX error word 0 */ - u_int32_t rx_error_0; + u32 rx_error_0; #define AR5K_RX_DESC_ERROR0 0x00000000 /* * RX error word 1 */ - u_int32_t rx_error_1; + u32 rx_error_1; #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 @@ -946,7 +946,7 @@ struct ath5k_hw_2w_tx_desc { /* * TX control word 0 */ - u_int32_t tx_control_0; + u32 tx_control_0; #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ @@ -971,7 +971,7 @@ struct ath5k_hw_2w_tx_desc { /* * TX control word 1 */ - u_int32_t tx_control_1; + u32 tx_control_1; #define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff #define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 @@ -997,7 +997,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 0 */ - u_int32_t tx_control_0; + u32 tx_control_0; #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 @@ -1014,7 +1014,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 1 */ - u_int32_t tx_control_1; + u32 tx_control_1; #define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff #define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 @@ -1033,7 +1033,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 2 */ - u_int32_t tx_control_2; + u32 tx_control_2; #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff #define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 @@ -1049,7 +1049,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 3 */ - u_int32_t tx_control_3; + u32 tx_control_3; #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 @@ -1066,7 +1066,7 @@ struct ath5k_hw_tx_status { /* * TX status word 0 */ - u_int32_t tx_status_0; + u32 tx_status_0; #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 @@ -1092,7 +1092,7 @@ struct ath5k_hw_tx_status { /* * TX status word 1 */ - u_int32_t tx_status_1; + u32 tx_status_1; #define AR5K_DESC_TX_STATUS1_DONE 0x00000001 #define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe @@ -1112,8 +1112,8 @@ struct ath5k_hw_tx_status { */ struct ath5k_ini { - u_int16_t ini_register; - u_int32_t ini_value; + u16 ini_register; + u32 ini_value; enum { AR5K_INI_WRITE = 0, @@ -1333,8 +1333,8 @@ struct ath5k_ini { } struct ath5k_ar5210_ini_mode{ - u_int16_t mode_register; - u_int32_t mode_base, mode_turbo; + u16 mode_register; + u32 mode_base, mode_turbo; }; #define AR5K_AR5210_INI_MODE(_aifs) { \ @@ -1554,9 +1554,9 @@ struct ath5k_ar5210_ini_mode{ } struct ath5k_ar5212_ini { - u_int8_t ini_flags; - u_int16_t ini_register; - u_int32_t ini_value; + u8 ini_flags; + u16 ini_register; + u32 ini_value; #define AR5K_INI_FLAG_511X 0x00 #define AR5K_INI_FLAG_5111 0x01 @@ -1938,8 +1938,8 @@ struct ath5k_ar5212_ini { } struct ath5k_ar5211_ini_mode { - u_int16_t mode_register; - u_int32_t mode_value[4]; + u16 mode_register; + u32 mode_value[4]; }; #define AR5K_AR5211_INI_MODE { \ @@ -1981,9 +1981,9 @@ struct ath5k_ar5211_ini_mode { } struct ath5k_ar5212_ini_mode { - u_int16_t mode_register; - u_int8_t mode_flags; - u_int32_t mode_value[2][5]; + u16 mode_register; + u8 mode_flags; + u32 mode_value[2][5]; }; #define AR5K_AR5212_INI_MODE { \ @@ -2154,8 +2154,8 @@ struct ath5k_ar5212_ini_mode { } struct ath5k_ar5211_ini_rf { - u_int16_t rf_register; - u_int32_t rf_value[2]; + u16 rf_register; + u32 rf_value[2]; }; #define AR5K_AR5211_INI_RF { \