commit 4cb2e576787a095150c2d0ab8c633dd0b8358e62 Author: Jiri Slaby Date: Sat Jun 16 18:17:24 2007 +0200 compilable, woow diff --git a/ath/Makefile b/ath/Makefile index 14dd268..808a66b 100644 --- a/ath/Makefile +++ b/ath/Makefile @@ -15,7 +15,7 @@ bus=pci endif obj-m += ath_$(bus).o -ath_ahb-objs := if_ath.o if_ath_ahb.o radar.o -ath_pci-objs := if_ath.o if_ath_pci.o radar.o +ath_ahb-objs := if_ath.o if_ath_ahb.o #radar.o +ath_pci-objs := if_ath.o if_ath_pci.o #radar.o -EXTRA_CFLAGS += -I../openhal/ +EXTRA_CFLAGS += -I$(src)/../openhal diff --git a/ath/if_ath.c b/ath/if_ath.c index 7fe48a5..7533e01 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -36,8 +36,6 @@ * $Id: if_ath.c 2408 2007-05-30 22:58:20Z mickflemm $ */ -__FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.76 2005/01/24 20:31:24 sam Exp $"); - /* * Driver for the Atheros Wireless LAN controller. * @@ -63,19 +61,13 @@ __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.76 2005/01/24 20:31:24 sam Exp #include #include -#include "if_ethersubr.h" /* for ETHER_IS_MULTICAST */ -#include "if_media.h" -#include "if_llc.h" - -#include - /* * #define AR_DEBUG here if you need to debug the ath_pci module (athdebug) * disable this if not needed because it adds an amount of load */ #define AR_DEBUG -#include "radar.h" +/*#include "radar.h"*/ #include "if_athvar.h" #include "ah_desc.h" @@ -91,6 +83,13 @@ __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.76 2005/01/24 20:31:24 sam Exp #include "ath_hw.h" +#define KASSERT(exp, msg...) do { \ + if (unlikely(!(exp))) { \ + printk(msg); \ + BUG(); \ + } \ +} while (0) + /* unaligned little endian access */ #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) @@ -110,41 +109,49 @@ static void ath_bmiss_tasklet(TQUEUE_ARG); static void ath_radar_tasklet(TQUEUE_ARG); static int ath_stop_locked(struct net_device *); static int ath_stop(struct net_device *); +#ifdef BLE static int ath_media_change(struct net_device *); static int ath_key_alloc(struct ieee80211com *, - const struct ieee80211_key *); + const struct ieee80211_key_conf *); static int ath_key_delete(struct ieee80211com *, - const struct ieee80211_key *); -static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, + const struct ieee80211_key_conf *); +static int ath_key_set(struct ieee80211com *, + const struct ieee80211_key_conf *, const u_int8_t mac[IEEE80211_ADDR_LEN]); static void ath_key_update_begin(struct ieee80211com *); static void ath_key_update_end(struct ieee80211com *); static void ath_mode_init(struct net_device *); +#endif static void ath_setslottime(struct ath_softc *); -static void ath_updateslot(struct net_device *); +//static void ath_updateslot(struct net_device *); static int ath_beaconq_setup(struct ath_hal *); -static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); -static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); +//static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); +static void ath_beacon_setup(struct ath_softc *, struct ath_buf *, + struct ieee80211_tx_control *); static void ath_beacon_send(struct net_device *); static void ath_beacon_free(struct ath_softc *); -static void ath_beacon_config(struct ath_softc *); -static void ath_descdma_cleanup(struct ath_softc *sc, ath_bufhead *); +//static void ath_beacon_config(struct ath_softc *); +static void ath_descdma_cleanup(struct ath_softc *sc, struct list_head *); static int ath_desc_alloc(struct ath_softc *); static void ath_desc_free(struct ath_softc *); +#ifdef BLE static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); static void ath_node_free(struct ieee80211_node *); static u_int8_t ath_node_getrssi(const struct ieee80211_node *); +#endif static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); +#ifdef BLE static void ath_recv_mgmt(struct ieee80211com *, struct sk_buff *, struct ieee80211_node *, int subtype, int rssi, u_int32_t rstamp); +#endif static void ath_setdefantenna(struct ath_softc *, u_int); static void ath_rx_tasklet(TQUEUE_ARG data); static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); -static int ath_tx_setup(struct ath_softc *, int, int); -static int ath_wme_update(struct ieee80211com *); +//static int ath_wme_update(struct ieee80211com *); static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); static void ath_tx_cleanup(struct ath_softc *); +#ifdef BLE static int ath_start(struct sk_buff *, struct net_device *); static int ath_tx_setup(struct ath_softc *, int ac, int txq); static int ath_tx_start(struct net_device *, struct ieee80211_node *, @@ -154,12 +161,14 @@ static void ath_tx_tasklet_q0123(TQUEUE_ARG data); static void ath_tx_tasklet(TQUEUE_ARG data); static void ath_tx_timeout(struct net_device *); static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); +#endif static void ath_draintxq(struct ath_softc *); static void ath_stoprecv(struct ath_softc *); static int ath_startrecv(struct ath_softc *); -static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); +//static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); static void ath_next_scan(unsigned long); static void ath_calibrate(unsigned long); +#ifdef BLE static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); #if IEEE80211_VLAN_TAG_USED static void ath_vlan_register(struct net_device *, struct vlan_group *); @@ -170,21 +179,24 @@ static struct iw_statistics *ath_iw_getstats(struct net_device *); static struct iw_handler_def ath_iw_handler_def; static void ath_setup_stationkey(struct ieee80211_node *); static void ath_newassoc(struct ieee80211_node *, int); +#endif static int ath_getchannels(struct net_device *, u_int cc, AR5K_BOOL outdoor, AR5K_BOOL xchanmode); +#ifdef BLE static void ath_led_event(struct ath_softc *, int); +#endif static void ath_led_off(unsigned long arg); static void ath_update_txpow(struct ath_softc *); - +#ifdef BLE static int ath_set_mac_address(struct net_device *, void *); static int ath_change_mtu(struct net_device *, int); static int ath_ioctl(struct net_device *, struct ifreq *, int); - +#endif static int ath_rate_setup(struct net_device *, u_int mode); -static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); +static void ath_setcurmode(struct ath_softc *, unsigned int); -static int ath_rawdev_attach(struct ath_softc *); -static void ath_rawdev_detach(struct ath_softc *); +//static int ath_rawdev_attach(struct ath_softc *); +//static void ath_rawdev_detach(struct ath_softc *); static void ath_dynamic_sysctl_register(struct ath_softc *); static void ath_dynamic_sysctl_unregister(struct ath_softc *); static void ath_announce(struct ath_softc *); @@ -321,7 +333,7 @@ int ath_attach(u_int16_t devid, struct net_device *dev) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; +// struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah; AR5K_STATUS status; int error = 0, i; @@ -381,8 +393,8 @@ ath_attach(u_int16_t devid, struct net_device *dev) */ sc->sc_keymax = ath_hal_keycachesize(ah); if (sc->sc_keymax > ATH_KEYMAX) { - if_printf(dev, "Warning, using only %u of %u key cache slots\n", - ATH_KEYMAX, sc->sc_keymax); + printk(KERN_WARNING "Warning, using only %u of %u key cache " + "slots\n", ATH_KEYMAX, sc->sc_keymax); sc->sc_keymax = ATH_KEYMAX; } @@ -398,12 +410,14 @@ ath_attach(u_int16_t devid, struct net_device *dev) * could leave the +32, +64, and +32+64 slots free. * XXX only for splitmic. */ +#ifdef BLE for (i = 0; i < IEEE80211_WEP_NKID; i++) { setbit(sc->sc_keymap, i); setbit(sc->sc_keymap, i+32); setbit(sc->sc_keymap, i+64); setbit(sc->sc_keymap, i+32+64); } +#endif /* * Collect the channel list using the default country @@ -427,20 +441,20 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Setup rate tables for all potential media types. */ - ath_rate_setup(dev, IEEE80211_MODE_11A); - ath_rate_setup(dev, IEEE80211_MODE_11B); - ath_rate_setup(dev, IEEE80211_MODE_11G); - ath_rate_setup(dev, IEEE80211_MODE_TURBO_A); - ath_rate_setup(dev, IEEE80211_MODE_TURBO_G); + ath_rate_setup(dev, MODE_IEEE80211A); + ath_rate_setup(dev, MODE_IEEE80211B); + ath_rate_setup(dev, MODE_IEEE80211G); + ath_rate_setup(dev, MODE_ATHEROS_TURBO); + ath_rate_setup(dev, MODE_ATHEROS_TURBOG); /* NB: setup here so ath_rate_update is happy */ - ath_setcurmode(sc, IEEE80211_MODE_11A); + ath_setcurmode(sc, MODE_IEEE80211A); /* * Allocate tx+rx descriptors and populate the lists. */ error = ath_desc_alloc(sc); if (error != 0) { - if_printf(dev, "failed to allocate descriptors: %d\n", error); + printk(KERN_ERR "failed to allocate descriptors: %d\n", error); goto bad; } @@ -454,18 +468,19 @@ ath_attach(u_int16_t devid, struct net_device *dev) */ sc->sc_bhalq = ath_beaconq_setup(ah); if (sc->sc_bhalq == (u_int) -1) { - if_printf(dev, "unable to setup a beacon xmit queue!\n"); + printk(KERN_ERR "unable to setup a beacon xmit queue!\n"); goto bad2; } sc->sc_cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); if (sc->sc_cabq == NULL) { - if_printf(dev, "unable to setup CAB xmit queue!\n"); + printk(KERN_ERR "unable to setup CAB xmit queue!\n"); error = EIO; goto bad2; } +#ifdef BLE /* NB: insure BK queue is the lowest priority h/w queue */ if (!ath_tx_setup(sc, WME_AC_BK, AR5K_WME_AC_BK)) { - if_printf(dev, "unable to setup xmit queue for %s traffic!\n", + printk(KERN_ERR "unable to setup xmit queue for %s traffic!\n", ieee80211_wme_acnames[WME_AC_BK]); error = EIO; goto bad2; @@ -518,7 +533,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) error = EIO; goto bad2; } - +#endif init_timer(&sc->sc_scan_ch); sc->sc_scan_ch.function = ath_next_scan; sc->sc_scan_ch.data = (unsigned long) dev; @@ -546,6 +561,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); } +#ifdef BLE ether_setup(dev); dev->open = ath_init; dev->stop = ath_stop; @@ -569,7 +585,6 @@ ath_attach(u_int16_t devid, struct net_device *dev) dev->vlan_rx_register = ath_vlan_register; dev->vlan_rx_kill_vid = ath_vlan_kill_vid; #endif /* IEEE80211_VLAN_TAG_USED */ - ic->ic_dev = dev; ic->ic_devstats = &sc->sc_devstats; ic->ic_init = ath_init; @@ -589,7 +604,6 @@ ath_attach(u_int16_t devid, struct net_device *dev) | IEEE80211_C_SHSLOT /* short slot time supported */ | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ ; - /* * initialize management queue */ @@ -646,6 +660,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) * 32-bit boundary for 4-address and QoS frames. */ ic->ic_flags |= IEEE80211_F_DATAPAD; +#endif /* * Query the hal about antenna support. @@ -663,9 +678,9 @@ ath_attach(u_int16_t devid, struct net_device *dev) sc->sc_rawdev.type = ARPHRD_IEEE80211; /* get mac address from hardware */ - ath_hal_getmac(ah, ic->ic_myaddr); - IEEE80211_ADDR_COPY(dev->dev_addr, ic->ic_myaddr); - +// ath_hal_getmac(ah, ic->ic_myaddr); BLEE +// IEEE80211_ADDR_COPY(dev->dev_addr, ic->ic_myaddr); +#ifdef BLE /* call MI attach routine. */ ieee80211_ifattach(ic); /* override default methods */ @@ -684,7 +699,8 @@ ath_attach(u_int16_t devid, struct net_device *dev) ic->ic_crypto.cs_key_update_end = ath_key_update_end; radar_init(ic); - +#endif +#if 0 /* complete initialization */ ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); @@ -693,20 +709,21 @@ ath_attach(u_int16_t devid, struct net_device *dev) goto bad3; } +#endif /* * Attach dynamic MIB vars and announce support * now that we have a device name with unit number. */ ath_dynamic_sysctl_register(sc); - ath_rate_dynamic_sysctl_register(sc); - ieee80211_sysctl_register(ic); - ieee80211_announce(ic); +// ath_rate_dynamic_sysctl_register(sc); ath_announce(sc); + return 0; -bad3: - ieee80211_ifdetach(ic); - ath_rate_detach(sc->sc_rc); +//bad3: +// ieee80211_ifdetach(ic); +// ath_rate_detach(sc->sc_rc); bad2: +#ifdef BLE if (sc->sc_txq[WME_AC_BK].axq_qnum != (u_int) -1) { ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_BK]); } @@ -719,6 +736,7 @@ bad2: if (sc->sc_txq[WME_AC_VO].axq_qnum != (u_int) -1) { ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VO]); } +#endif ath_tx_cleanup(sc); ath_desc_free(sc); bad: @@ -733,7 +751,7 @@ int ath_detach(struct net_device *dev) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; +// struct ieee80211com *ic = &sc->sc_ic; DPRINTF(sc, ATH_DEBUG_ANY, "%s: flags %x\n", __func__, dev->flags); ath_stop(dev); @@ -750,8 +768,8 @@ ath_detach(struct net_device *dev) * it last * Other than that, it's straightforward... */ - ieee80211_ifdetach(ic); - ath_rate_detach(sc->sc_rc); +// ieee80211_ifdetach(ic); +// ath_rate_detach(sc->sc_rc); ath_desc_free(sc); ath_tx_cleanup(sc); ath_hal_detach(sc->sc_ah); @@ -762,8 +780,8 @@ ath_detach(struct net_device *dev) * state and potentially want to use them. */ ath_dynamic_sysctl_unregister(sc); - ath_rawdev_detach(sc); - unregister_netdev(dev); +// ath_rawdev_detach(sc); +// unregister_netdev(dev); return 0; } @@ -902,8 +920,10 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs) * Let the hal handle the event. We assume it will * clear whatever condition caused the interrupt. */ +#ifdef BLE ath_hal_mibevent(ah, &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); +#endif ath_hal_intrset(ah, sc->sc_imask); } } @@ -920,7 +940,7 @@ ath_fatal_tasklet(TQUEUE_ARG data) { struct net_device *dev = (struct net_device *)data; - if_printf(dev, "hardware error; resetting\n"); + printk(KERN_ERR "hardware error; resetting\n"); ath_reset(dev); } @@ -928,6 +948,7 @@ static void ath_radar_tasklet (TQUEUE_ARG data) { struct net_device *dev = (struct net_device *)data; +#ifdef BLE struct ath_softc *sc = dev->priv; struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_channel *c; @@ -944,6 +965,7 @@ ath_radar_tasklet (TQUEUE_ARG data) ic->ic_des_chan = c; ic->ic_ibss_chan = c; ieee80211_new_state (ic, IEEE80211_S_INIT, -1); +#endif ath_init (dev); } @@ -952,20 +974,21 @@ ath_rxorn_tasklet(TQUEUE_ARG data) { struct net_device *dev = (struct net_device *)data; - if_printf(dev, "rx FIFO overrun; resetting\n"); + printk(KERN_WARNING "rx FIFO overrun; resetting\n"); ath_reset(dev); } static void ath_bmiss_tasklet(TQUEUE_ARG data) { +#ifdef BLE struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; struct ieee80211com *ic = &sc->sc_ic; DPRINTF(sc, ATH_DEBUG_ANY, "%s\n", __func__); KASSERT(ic->ic_opmode == IEEE80211_M_STA, - ("unexpected operating mode %u", ic->ic_opmode)); + "unexpected operating mode %u", ic->ic_opmode); if (ic->ic_state == IEEE80211_S_RUN) { if (sc->sc_bmisscount >= 1) { /* @@ -992,8 +1015,9 @@ ath_bmiss_tasklet(TQUEUE_ARG data) IEEE80211_FC0_SUBTYPE_PROBE_REQ, 0); } } +#endif } - +#ifdef BLE static u_int ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) { @@ -1009,33 +1033,30 @@ ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) }; enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); - KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); - KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); + KASSERT(mode < N(modeflags), "unexpected phy mode %u", mode); + KASSERT(modeflags[mode] != 0, "mode %u undefined", mode); return modeflags[mode]; #undef N } - +#endif static int ath_init(struct net_device *dev) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; - struct ieee80211_node *ni; struct ath_hal *ah = sc->sc_ah; AR5K_STATUS status; int error = 0; - int opmode; ATH_LOCK(sc); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, ic->ic_opmode); +// DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, ic->ic_opmode); /* * Stop anything previously setup. This is safe * whether this is the first time through or not. */ ath_stop_locked(dev); - +#ifdef BLE /* * Change our interface type if we are in monitor mode. */ @@ -1051,14 +1072,13 @@ ath_init(struct net_device *dev) */ sc->sc_curchan.freq = ic->ic_ibss_chan->ic_freq; sc->sc_curchan.channel_flags = ath_chan2flags(ic, ic->ic_ibss_chan); - opmode = (ic->ic_opmode == IEEE80211_M_AHDEMO) ? 0 : ic->ic_opmode; - if (!ath_hal_reset(ah, opmode, &sc->sc_curchan, FALSE, &status)) { - if_printf(dev, "unable to reset hardware; hal status %u\n", +#endif + if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, FALSE, &status)) { + printk(KERN_ERR "unable to reset hardware; hal status %u\n", status); error = -EIO; goto done; } - /* * This is needed only to setup initial state * but it's best done after a reset. @@ -1079,7 +1099,7 @@ ath_init(struct net_device *dev) * here except setup the interrupt mask. */ if (ath_startrecv(sc) != 0) { - if_printf(dev, "unable to start recv logic\n"); + printk(KERN_ERR "unable to start recv logic\n"); error = -EIO; goto done; } @@ -1090,6 +1110,7 @@ ath_init(struct net_device *dev) sc->sc_imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL; // TODO: compiler warning integer overflow in expression +#ifdef BLE /* * Enable MIB interrupts when there are hardware phy counters. * Note we only do this (at the moment) for station mode. @@ -1114,6 +1135,7 @@ ath_init(struct net_device *dev) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); } else ieee80211_new_state(ic, IEEE80211_S_RUN, -1); +#endif done: ATH_UNLOCK(sc); return error; @@ -1123,7 +1145,7 @@ static int ath_stop_locked(struct net_device *dev) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; +// struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u flags 0x%x\n", @@ -1147,7 +1169,7 @@ ath_stop_locked(struct net_device *dev) * Note that some of this work is not possible if the * hardware is gone (invalid). */ - ieee80211_new_state(ic, IEEE80211_S_INIT, -1); +// ieee80211_new_state(ic, IEEE80211_S_INIT, -1); netif_stop_queue(dev); if (sc->sc_rawdev_enabled) netif_stop_queue(&sc->sc_rawdev); @@ -1228,14 +1250,13 @@ static int ath_reset(struct net_device *dev) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah = sc->sc_ah; - struct ieee80211_channel *c; - AR5K_STATUS status; - int opmode; +// struct ath_hal *ah = sc->sc_ah; +// struct ieee80211_channel *c; +// AR5K_STATUS status; +// int opmode; DPRINTF(sc, ATH_DEBUG_RESET, "%s: resetting\n", dev->name); - +#ifdef BLE /* * Convert to a HAL channel description with the flags * constrained to reflect the current operating mode. @@ -1269,7 +1290,7 @@ ath_reset(struct net_device *dev) if (ic->ic_state == IEEE80211_S_RUN) netif_wake_queue(dev); /* restart xmit */ - +#endif if (sc->sc_rawdev_enabled) netif_wake_queue(&sc->sc_rawdev); return 0; @@ -1278,6 +1299,7 @@ ath_reset(struct net_device *dev) #define NUM_RADIOTAP_ELEMENTS 18 +#ifdef BLE static int radiotap_elem_to_bytes[NUM_RADIOTAP_ELEMENTS] = {8, /* IEEE80211_RADIOTAP_TSFT */ 1, /* IEEE80211_RADIOTAP_FLAGS */ @@ -1299,7 +1321,6 @@ static int radiotap_elem_to_bytes[NUM_RADIOTAP_ELEMENTS] = 1, /* IEEE80211_RADIOTAP_DATA_RETRIES */ }; - /* * the following rt_* functions deal with verifying that a valid * radiotap header is on a packet as well as functions to extracting @@ -1347,6 +1368,7 @@ static u_int8_t *rt_el_offset(struct ieee80211_radiotap_header *th, u_int32_t el return offset; } + /* * ath_start for raw 802.11 packets. */ @@ -1374,7 +1396,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) struct ieee80211_frame *wh; struct ath_desc *ds; const AR5K_RATE_TABLE *rt; - uint8_t testmac[IEEE80211_ADDR_LEN]; + uint8_t testmac[ETH_ALEN]; if ((sc->sc_dev.flags & IFF_RUNNING) == 0 || sc->sc_invalid) { /* device is not up... silently discard packet */ @@ -1407,7 +1429,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) } rt = sc->sc_currates; - KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); + KASSERT(rt != NULL, "no rate table, mode %u", sc->sc_curmode); flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; try0 = ATH_TXMAXTRY; dot11_rate = 0; @@ -1865,7 +1887,7 @@ ath_media_change(struct net_device *dev) #ifdef AR_DEBUG static void ath_keyprint(const char *tag, u_int ix, - const AR5K_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) + const AR5K_KEYVAL *hk, const u_int8_t mac[ETH_ALEN]) { static const char *ciphers[] = { "WEP", @@ -1880,7 +1902,7 @@ ath_keyprint(const char *tag, u_int ix, printk("%s: [%02u] %-7s ", tag, ix, ciphers[hk->wk_type]); for (i = 0, n = hk->wk_len; i < n; i++) printk("%02x", hk->wk_key[i]); - printk(" mac %s", ether_sprintf(mac)); +// printk(" mac %s", ether_sprintf(mac)); if (hk->wk_type == AR5K_CIPHER_TKIP) { printk(" mic "); for (i = 0; i < sizeof(hk->wk_mic); i++) @@ -1897,7 +1919,7 @@ ath_keyprint(const char *tag, u_int ix, */ static int ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, - AR5K_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) + AR5K_KEYVAL *hk, const u_int8_t mac[ETH_ALEN]) { #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; @@ -2313,15 +2335,15 @@ static void ath_mode_init(struct net_device *dev) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; +// struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; u_int32_t rfilt, mfilt[2], val; u_int8_t pos; struct dev_mc_list *mc; /* configure rx filter */ - rfilt = ath_calcrxfilter(sc, ic->ic_state); - ath_hal_setrxfilter(ah, rfilt); +// rfilt = ath_calcrxfilter(sc, ic->ic_state); +// ath_hal_setrxfilter(ah, rfilt); /* configure operational mode */ ath_hal_setopmode(ah); @@ -2334,8 +2356,8 @@ ath_mode_init(struct net_device *dev) * * XXX should get from lladdr instead of arpcom but that's more work */ - IEEE80211_ADDR_COPY(ic->ic_myaddr, dev->dev_addr); - ath_hal_setmac(ah, ic->ic_myaddr); +// IEEE80211_ADDR_COPY(ic->ic_myaddr, dev->dev_addr); + ath_hal_setmac(ah, dev->dev_addr); /* calculate and install multicast filter */ if ((dev->flags & IFF_ALLMULTI) == 0) { @@ -2356,7 +2378,7 @@ ath_mode_init(struct net_device *dev) DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", __func__, rfilt, mfilt[0], mfilt[1]); } - +#endif /* * Set the slot time based on the current setting. * This is called by ath_updateslot below and when a non-ERP node @@ -2365,7 +2387,7 @@ ath_mode_init(struct net_device *dev) static void ath_setslottime(struct ath_softc *sc) { - struct ieee80211com *ic = &sc->sc_ic; +// struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; /* If the user has asked to lock the slot-time, ignore the @@ -2373,14 +2395,14 @@ ath_setslottime(struct ath_softc *sc) * that require a slot time larger than the standard ones. -TvE */ if (!sc->sc_lockslottime) { - if (ic->ic_flags & IEEE80211_F_SHSLOT) - ath_hal_setslottime(ah, AR5K_SLOT_TIME_9); - else +// if (ic->ic_flags & IEEE80211_F_SHSLOT) +// ath_hal_setslottime(ah, AR5K_SLOT_TIME_9); +// else ath_hal_setslottime(ah, AR5K_SLOT_TIME_20); } sc->sc_updateslot = OK; } - +#ifdef BLE /* * Callback from the 802.11 layer to update the * slot time based on the current setting. @@ -2401,7 +2423,7 @@ ath_updateslot(struct net_device *dev) else ath_setslottime(sc); } - +#endif /* * Setup a h/w transmit queue for beacons. */ @@ -2414,11 +2436,11 @@ ath_beaconq_setup(struct ath_hal *ah) qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; - /* NB: for dynamic turbo, don't enable any other interrupts */ - qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - return ath_hal_setuptxqueue(ah, AR5K_TX_QUEUE_BEACON, &qi); + /* NB: for dynamic turbo, don't enable any other interrupts */ + qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + return ath_hal_setuptxqueue(ah, AR5K_TX_QUEUE_BEACON, &qi); } - +#ifdef BLE /* * Setup the transmit queue parameters for the beacon queue. */ @@ -2426,37 +2448,39 @@ static int ath_beaconq_config(struct ath_softc *sc) { #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) - struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah = sc->sc_ah; - AR5K_TXQ_INFO qi; +// struct ieee80211com *ic = &sc->sc_ic; + struct ath_hal *ah = sc->sc_ah; + AR5K_TXQ_INFO qi; - ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); - if (ic->ic_opmode == IEEE80211_M_HOSTAP) { - /* - * Always burst out beacon and CAB traffic. - */ - qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; - qi.tqi_cw_min = ATH_BEACON_CWMIN_DEFAULT; - qi.tqi_cw_max = ATH_BEACON_CWMAX_DEFAULT; - } else { - struct wmeParams *wmep = - &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; - /* - * Adhoc mode; important thing is to use 2x cwmin. - */ - qi.tqi_aifs = wmep->wmep_aifsn; - qi.tqi_cw_min = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); - qi.tqi_cw_max = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); - } + ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); + if (sc->sc_opmode == IEEE80211_IF_TYPE_AP) { + /* + * Always burst out beacon and CAB traffic. + */ + qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; + qi.tqi_cw_min = ATH_BEACON_CWMIN_DEFAULT; + qi.tqi_cw_max = ATH_BEACON_CWMAX_DEFAULT; + } else { +#ifdef BLE + struct wmeParams *wmep = + &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; + /* + * Adhoc mode; important thing is to use 2x cwmin. + */ + qi.tqi_aifs = wmep->wmep_aifsn; + qi.tqi_cw_min = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); + qi.tqi_cw_max = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); +#endif + } - if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { - printk("%s: unable to update parameters for " - "beacon hardware queue! (%s)\n", __func__, sc->sc_dev.name); - return 0; - } else { - ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ - return 1; - } + if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { + printk("%s: unable to update parameters for " + "beacon hardware queue! (%s)\n", __func__, sc->sc_dev.name); + return 0; + } else { + ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ + return 1; + } #undef ATH_EXPONENT_TO_VALUE } @@ -2501,21 +2525,19 @@ ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) return 0; // TODO: return value } - +#endif /* * Setup the beacon frame for transmit. */ static void -ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) +ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, + struct ieee80211_tx_control *ctl) { #define USE_SHPREAMBLE(_ic) \ (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ == IEEE80211_F_SHPREAMBLE) - struct ieee80211_node *ni = bf->bf_node; - struct ieee80211com *ic = ni->ni_ic; struct sk_buff *skb = bf->bf_skb; struct ath_hal *ah = sc->sc_ah; - struct ath_node *an = ATH_NODE(ni); struct ath_desc *ds; int antenna = sc->sc_txantenna; int flags; @@ -2527,7 +2549,7 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) "%s: skb %p [data %p len %u] skbaddr %llx\n", __func__, skb, skb->data, skb->len, ito64(bf->bf_skbaddr)); if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { - if_printf(&sc->sc_dev, "%s: DMA mapping failed\n", __func__); + printk(KERN_ERR "%s: DMA mapping failed\n", __func__); return; } @@ -2535,7 +2557,7 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) ds = bf->bf_desc; flags = AR5K_TXDESC_NOACK; - if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { + if (sc->sc_opmode == IEEE80211_IF_TYPE_IBSS && sc->sc_hasveol) { ds->ds_link = bf->bf_daddr; /* self-linked */ flags |= AR5K_TXDESC_VEOL; /* @@ -2557,15 +2579,18 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) * Calculate rate code. * XXX everything at min xmit rate */ +#ifdef BLE if (USE_SHPREAMBLE(ic)) rate = an->an_tx_mgtratesp; else rate = an->an_tx_mgtrate; +#endif + rate = 0; ath_hal_setuptxdesc(ah, ds - , skb->len + IEEE80211_CRC_LEN /* frame length */ - , sizeof(struct ieee80211_frame)/* header length */ + , skb->len + FCS_LEN /* frame length */ + , ieee80211_get_hdrlen_from_skb(skb) /* header length */ , AR5K_PKT_TYPE_BEACON /* Atheros packet type */ - , ni->ni_txpower /* txpower XXX */ + , min((u8)60u, ctl->power_level) /* txpower XXX */ , rate, 1 /* series 0 rate/tries */ , AR5K_TXKEYIX_INVALID /* no encryption */ , antenna /* antenna mode */ @@ -2595,20 +2620,20 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) static void ath_beacon_send(struct net_device *dev) { + struct ieee80211_tx_control ctl; struct ath_softc *sc = dev->priv; - struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); - struct ieee80211com *ic = &sc->sc_ic; + struct ath_buf *bf = NULL;//STAILQ_FIRST(&sc->sc_bbuf); struct ath_hal *ah = sc->sc_ah; struct sk_buff *skb; int ncabq, otherant; DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__); - if (ic->ic_opmode == IEEE80211_M_STA || - ic->ic_opmode == IEEE80211_M_MONITOR || + if (sc->sc_opmode == IEEE80211_IF_TYPE_STA || + sc->sc_opmode == IEEE80211_IF_TYPE_MNTR || bf == NULL || bf->bf_skb == NULL) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_skb=%p\n", - __func__, ic->ic_flags, bf, bf ? bf->bf_skb : NULL); + DPRINTF(sc, ATH_DEBUG_ANY, "%s: bf=%p bf_skb=%p\n", + __func__, bf, bf ? bf->bf_skb : NULL); return; } /* @@ -2646,6 +2671,7 @@ ath_beacon_send(struct net_device *dev) */ skb = bf->bf_skb; ncabq = sc->sc_cabq->axq_depth; +#ifdef BLE if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, skb, ncabq)) { DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: update, beacon len changed %d to %d\n", @@ -2662,6 +2688,7 @@ ath_beacon_send(struct net_device *dev) return; } } +#endif /* * Handle slot time change when a non-ERP station joins/leaves @@ -2690,7 +2717,7 @@ ath_beacon_send(struct net_device *dev) /* * Construct tx descriptor. */ - ath_beacon_setup(sc, bf); + ath_beacon_setup(sc, bf, &ctl); /* * Stop any current dma and put the new frame on the queue. @@ -2714,9 +2741,11 @@ ath_beacon_send(struct net_device *dev) * * NB: only at DTIM */ - if (ic->ic_opmode == IEEE80211_M_HOSTAP && +#ifdef BLE + if (sc->sc_opmode == IEEE80211_IF_TYPE_AP && ncabq > 0 && sc->sc_boff.bo_tim[4] & 1) ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); +#endif ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); ath_hal_txstart(ah, sc->sc_bhalq); DPRINTF(sc, ATH_DEBUG_BEACON_PROC, @@ -2735,7 +2764,7 @@ ath_bstuck_tasklet(TQUEUE_ARG data) struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; - if_printf(dev, "stuck beacon; resetting (bmiss count %u)\n", + printk(KERN_WARNING "stuck beacon; resetting (bmiss count %u)\n", sc->sc_bmisscount); ath_reset(dev); } @@ -2748,20 +2777,24 @@ ath_beacon_free(struct ath_softc *sc) { struct ath_buf *bf; - STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { - if (bf->bf_skb != NULL) { - bus_unmap_single(sc->sc_bdev, - bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); - dev_kfree_skb(bf->bf_skb); - bf->bf_skb = NULL; - } - if (bf->bf_node != NULL) { - ieee80211_free_node(bf->bf_node); - bf->bf_node = NULL; - } - } + bf = NULL; +// STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { + if (bf->bf_skb != NULL) { + bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr, + bf->bf_skb->len, BUS_DMA_TODEVICE); + dev_kfree_skb(bf->bf_skb); + bf->bf_skb = NULL; + } +#ifdef BLE + if (bf->bf_node != NULL) { + ieee80211_free_node(bf->bf_node); + bf->bf_node = NULL; + } +#endif +// } } +#ifdef BLE /* * Configure the beacon and sleep timers. * @@ -2782,8 +2815,6 @@ ath_beacon_config(struct ath_softc *sc) { #define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) struct ath_hal *ah = sc->sc_ah; - struct ieee80211com *ic = &sc->sc_ic; - struct ieee80211_node *ni = ic->ic_bss; u_int32_t nexttbtt, intval; u_int64_t tsf; u_int32_t tsftu; @@ -2959,10 +2990,12 @@ ath_beacon_config(struct ath_softc *sc) } #undef TSF_TO_TU } +#endif static void -ath_descdma_cleanup(struct ath_softc *sc, ath_bufhead *head) +ath_descdma_cleanup(struct ath_softc *sc, struct list_head *head) { +#ifdef BLE struct ath_buf *bf; struct ieee80211_node *ni; @@ -2985,6 +3018,7 @@ ath_descdma_cleanup(struct ath_softc *sc, ath_bufhead *head) } STAILQ_INIT(head); +#endif } static int @@ -3004,7 +3038,7 @@ ath_desc_alloc(struct ath_softc *sc) sc->sc_desc = bus_alloc_consistent(sc->sc_bdev, sc->sc_desc_len, &sc->sc_desc_daddr); if (sc->sc_desc == NULL) { - if_printf(&sc->sc_dev, "%s, could not allocate descriptors\n", __func__); + printk(KERN_ERR "%s, could not allocate descriptors\n", __func__); return ENOMEM; } ds = sc->sc_desc; @@ -3019,25 +3053,25 @@ ath_desc_alloc(struct ath_softc *sc) memset(bf, 0, bsize); sc->sc_bufptr = bf; - STAILQ_INIT(&sc->sc_rxbuf); +// STAILQ_INIT(&sc->sc_rxbuf); for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { bf->bf_desc = ds; bf->bf_daddr = DS2PHYS(sc, ds); - STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); +// STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); } - STAILQ_INIT(&sc->sc_txbuf); +// STAILQ_INIT(&sc->sc_txbuf); for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { bf->bf_desc = ds; bf->bf_daddr = DS2PHYS(sc, ds); - STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); +// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); } - STAILQ_INIT(&sc->sc_bbuf); +// STAILQ_INIT(&sc->sc_bbuf); for (i = 0; i < ATH_BCBUF; i++, bf++, ds++) { bf->bf_desc = ds; bf->bf_daddr = DS2PHYS(sc, ds); - STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); +// STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); } return 0; @@ -3052,9 +3086,9 @@ bad: static void ath_desc_free(struct ath_softc *sc) { - ath_descdma_cleanup(sc, &sc->sc_bbuf); - ath_descdma_cleanup(sc, &sc->sc_txbuf); - ath_descdma_cleanup(sc, &sc->sc_rxbuf); + ath_descdma_cleanup(sc, sc->sc_bbuf); + ath_descdma_cleanup(sc, sc->sc_txbuf); + ath_descdma_cleanup(sc, sc->sc_rxbuf); /* Free memory associated with all descriptors */ bus_free_consistent(sc->sc_bdev, sc->sc_desc_len, @@ -3064,6 +3098,7 @@ ath_desc_free(struct ath_softc *sc) sc->sc_bufptr = NULL; } +#ifdef BLE static struct ieee80211_node * ath_node_alloc(struct ieee80211_node_table *nt) { @@ -3123,6 +3158,7 @@ ath_node_getrssi(const struct ieee80211_node *ni) return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; #undef AR5K_EP_RND } +#endif static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) @@ -3132,7 +3168,7 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) struct ath_desc *ds; int headroom_needed = 0; - if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) { + if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { headroom_needed = sizeof(wlan_ng_prism2_header); } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_PRISM) { headroom_needed = sizeof(wlan_ng_prism2_header); @@ -3192,7 +3228,7 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) bf->bf_skbaddr = bus_map_single(sc->sc_bdev, skb->data, sc->sc_rxbufsize, BUS_DMA_FROMDEVICE); if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { - if_printf(&sc->sc_dev, "%s: DMA mapping failed\n", __func__); + printk(KERN_ERR "%s: DMA mapping failed\n", __func__); dev_kfree_skb(skb); bf->bf_skb = NULL; sc->sc_stats.ast_rx_busdma++; @@ -3229,6 +3265,7 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) return 0; } +#ifdef BLE /* * Add additional headers to a transmitted frame and netif_rx it on * a monitor or raw device @@ -3237,7 +3274,6 @@ static void ath_tx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; u_int32_t tsf; /* @@ -3376,8 +3412,8 @@ ath_tx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) bad: dev_kfree_skb(skb); - return; } +#endif /* * Add additional headers to a received frame and netif_rx it on @@ -3386,6 +3422,7 @@ ath_tx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) static void ath_rx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) { +#ifdef BLE #define IS_QOS_DATA(wh) \ ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK|IEEE80211_FC0_SUBTYPE_MASK))==\ (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) @@ -3531,6 +3568,7 @@ ath_rx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) dev_kfree_skb(skb); return; #undef IS_QOS_DATA +#endif } /* @@ -3550,7 +3588,7 @@ ath_tsf_extend(struct ath_hal *ah, uint32_t rstamp) return ((tsf & ~(uint64_t)0x7fff) | rstamp); } - +#ifdef BLE /* * Intercept management frames to collect beacon rssi data * and to do ibss merges. @@ -3614,7 +3652,7 @@ ath_recv_mgmt(struct ieee80211com *ic, struct sk_buff *skb, break; } } - +#endif /* * Set the default antenna. */ @@ -3640,21 +3678,20 @@ ath_rx_tasklet(TQUEUE_ARG data) struct net_device *dev = (struct net_device *)data; struct ath_buf *bf; struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; struct ath_desc *ds; struct sk_buff *skb; - struct ieee80211_node *ni; - struct ath_node *an; - int len, type; +// struct ath_node *an; + int len;//, type; u_int phyerr; AR5K_STATUS status; DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s\n", __func__); do { - bf = STAILQ_FIRST(&sc->sc_rxbuf); +// bf = STAILQ_FIRST(&sc->sc_rxbuf); + bf = NULL; if (bf == NULL) { /* XXX ??? can this happen */ - if_printf(dev, "%s: no buffer!\n", __func__); + printk(KERN_ERR "%s: no buffer!\n", __func__); break; } ds = bf->bf_desc; @@ -3664,7 +3701,7 @@ ath_rx_tasklet(TQUEUE_ARG data) } skb = bf->bf_skb; if (skb == NULL) { /* XXX ??? can this happen */ - if_printf(dev, "%s: no skbuff!\n", __func__); + printk(KERN_ERR "%s: no skbuff!\n", __func__); continue; } /* XXX sync descriptor memory */ @@ -3687,7 +3724,7 @@ ath_rx_tasklet(TQUEUE_ARG data) #endif if (status == AR5K_EINPROGRESS) break; - STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); +// STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); if (ds->ds_rxstat.rs_more) { /* * Frame spans multiple descriptors; this @@ -3700,7 +3737,7 @@ ath_rx_tasklet(TQUEUE_ARG data) * Enable this if you want to see * error frames in Monitor mode. */ - if (ic->ic_opmode != IEEE80211_M_MONITOR) { + if (sc->sc_opmode != IEEE80211_IF_TYPE_MNTR) { sc->sc_stats.ast_rx_toobig++; goto rx_next; } @@ -3745,6 +3782,7 @@ ath_rx_tasklet(TQUEUE_ARG data) * the 802.11 header for notifcation. */ /* XXX frag's and qos frames */ +#ifdef BLE len = ds->ds_rxstat.rs_datalen; if (len >= sizeof (struct ieee80211_frame)) { bus_dma_sync_single(sc->sc_bdev, @@ -3757,10 +3795,11 @@ ath_rx_tasklet(TQUEUE_ARG data) ds->ds_rxstat.rs_keyix ); } +#endif } // TODO: correct? - ic->ic_devstats->rx_errors++; +// ic->ic_devstats->rx_errors++; /* * accept error frames on the raw device @@ -3777,7 +3816,7 @@ ath_rx_tasklet(TQUEUE_ARG data) */ if ((ds->ds_rxstat.rs_status &~ (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || - sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) + sc->sc_opmode != IEEE80211_IF_TYPE_MNTR) goto rx_next; } rx_accept: @@ -3796,7 +3835,7 @@ rx_accept: bf->bf_skb = NULL; sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; - +#ifdef BLE if (len < IEEE80211_ACK_LEN) { DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", __func__, len); @@ -3804,10 +3843,9 @@ rx_accept: dev_kfree_skb(skb); goto rx_next; } - - KASSERT(len <= skb_tailroom(skb), - ("not enough tailroom (%d vs %d)", - len, skb_tailroom(skb))); +#endif + KASSERT(len <= skb_tailroom(skb), "not enough tailroom " + "(%d vs %d)", len, skb_tailroom(skb)); skb_put(skb, len); skb->protocol = __constant_htons(ETH_P_CONTROL); @@ -3821,7 +3859,7 @@ rx_accept: } } - if (ic->ic_opmode == IEEE80211_M_MONITOR) { + if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { /* * Monitor mode: discard anything shorter than * an ack or cts, clean the skbuff, fabricate @@ -3849,6 +3887,7 @@ rx_accept: * From this point on we assume the frame is at least * as large as ieee80211_frame_min; verify that. */ +#ifdef BLE if (len < IEEE80211_MIN_LEN) { DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", __func__, len); @@ -3946,12 +3985,14 @@ rx_accept: } else if (jiffies - sc->sc_ledevent >= sc->sc_ledidle) ath_led_event(sc, ATH_LED_POLL); } +#endif rx_next: - STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); +// STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); + ; } while (ath_rxbuf_init(sc, bf) == 0); /* rx signal state monitoring */ - ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); +// ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); #undef PA2DESC } @@ -4006,14 +4047,14 @@ ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) txq->axq_depth = 0; txq->axq_intrcnt = 0; txq->axq_link = NULL; - STAILQ_INIT(&txq->axq_q); +// STAILQ_INIT(&txq->axq_q); ATH_TXQ_LOCK_INIT(sc, txq); sc->sc_txqsetup |= 1<sc_txq[qnum]; #undef N } - +#ifdef BLE /* * Setup a hardware data transmit queue for the specified * access control. The hal may not support all requested @@ -4051,9 +4092,8 @@ ath_txq_update(struct ath_softc *sc, int ac) { #define ATH_EXPONENT_TO_VALUE(v) ((1<sc_ic; struct ath_txq *txq = sc->sc_ac2q[ac]; - struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; +// struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; struct ath_hal *ah = sc->sc_ah; AR5K_TXQ_INFO qi; @@ -4089,7 +4129,7 @@ ath_wme_update(struct ieee80211com *ic) !ath_txq_update(sc, WME_AC_VI) || !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; } - +#endif /* * Reclaim resources for a setup queue. */ @@ -4117,7 +4157,7 @@ ath_tx_cleanup(struct ath_softc *sc) ath_tx_cleanupq(sc, &sc->sc_txq[i]); } } - +#ifdef BLE static int ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf *bf, struct sk_buff *skb) @@ -4608,22 +4648,21 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) { struct ath_hal *ah = sc->sc_ah; - struct ieee80211com *ic = &sc->sc_ic; struct ath_buf *bf; struct ath_desc *ds; - struct ieee80211_node *ni; - struct ath_node *an; - int sr, lr, pri; +// struct ieee80211_node *ni; +// struct ath_node *an; +// int sr, lr, pri; AR5K_STATUS status; DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", __func__, txq->axq_qnum, - (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), + (caddr_t)ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), txq->axq_link); for (;;) { ATH_TXQ_LOCK(txq); txq->axq_intrcnt = 0; /* reset periodic desc intr count */ - bf = STAILQ_FIRST(&txq->axq_q); +// bf = STAILQ_FIRST(&txq->axq_q); if (bf == NULL) { txq->axq_link = NULL; ATH_TXQ_UNLOCK(txq); @@ -4643,9 +4682,9 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) txq->axq_lastdsWithCTS = NULL; if (ds == txq->axq_gatingds) txq->axq_gatingds = NULL; - ATH_TXQ_REMOVE_HEAD(txq, bf_list); +// ATH_TXQ_REMOVE_HEAD(txq, bf_list); ATH_TXQ_UNLOCK(txq); - +#ifdef BLE ni = bf->bf_node; if (ni != NULL) { an = ATH_NODE(ni); @@ -4690,6 +4729,7 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) */ ieee80211_free_node(ni); } +#endif bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); @@ -4699,10 +4739,10 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) dev_kfree_skb(bf->bf_skb); } bf->bf_skb = NULL; - bf->bf_node = NULL; +// bf->bf_node = NULL; ATH_TXBUF_LOCK(sc); - STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); +// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); ATH_TXBUF_UNLOCK(sc); } } @@ -4716,7 +4756,6 @@ ath_tx_tasklet_q0(TQUEUE_ARG data) { struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; ath_tx_processq(sc, &sc->sc_txq[0]); ath_tx_processq(sc, sc->sc_cabq); @@ -4748,7 +4787,6 @@ ath_tx_tasklet_q0123(TQUEUE_ARG data) { struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; /* * Process each active queue. @@ -4785,7 +4823,6 @@ ath_tx_tasklet(TQUEUE_ARG data) { struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; int i; /* @@ -4823,6 +4860,7 @@ ath_tx_timeout(struct net_device *dev) sc->sc_stats.ast_watchdog++; ath_init(dev); } +#endif static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) @@ -4830,7 +4868,6 @@ ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) #ifdef AR_DEBUG struct ath_hal *ah = sc->sc_ah; #endif - struct ieee80211_node *ni; struct ath_buf *bf; /* @@ -4839,13 +4876,14 @@ ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) */ for (;;) { ATH_TXQ_LOCK_BH(txq); - bf = STAILQ_FIRST(&txq->axq_q); +// bf = STAILQ_FIRST(&txq->axq_q); + bf = NULL; if (bf == NULL) { txq->axq_link = NULL; ATH_TXQ_UNLOCK_BH(txq); break; } - ATH_TXQ_REMOVE_HEAD(txq, bf_list); +// ATH_TXQ_REMOVE_HEAD(txq, bf_list); ATH_TXQ_UNLOCK_BH(txq); #ifdef AR_DEBUG if (sc->sc_debug & ATH_DEBUG_RESET) @@ -4856,6 +4894,7 @@ ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); dev_kfree_skb(bf->bf_skb); bf->bf_skb = NULL; +#ifdef BLE ni = bf->bf_node; bf->bf_node = NULL; if (ni != NULL) { @@ -4864,8 +4903,9 @@ ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) */ ieee80211_free_node(ni); } +#endif ATH_TXBUF_LOCK_BH(sc); - STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); +// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); ATH_TXBUF_UNLOCK_BH(sc); } } @@ -4878,8 +4918,7 @@ ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) (void) ath_hal_stoptxdma(ah, txq->axq_qnum); DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", __func__, txq->axq_qnum, - (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), - txq->axq_link); + (caddr_t)ath_hal_gettxbuf(ah, txq->axq_qnum), txq->axq_link); } /* @@ -4897,7 +4936,7 @@ ath_draintxq(struct ath_softc *sc) (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %p\n", __func__, - (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); + (caddr_t)ath_hal_gettxbuf(ah, sc->sc_bhalq)); for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) { if (ATH_TXQ_SETUP(sc, i)) ath_tx_stopdma(sc, &sc->sc_txq[i]); @@ -4934,10 +4973,11 @@ ath_stoprecv(struct ath_softc *sc) mdelay(3); /* 3ms is long enough for 1 frame */ #ifdef AR_DEBUG if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow - struct ath_buf *bf; +// struct ath_buf *bf; printk("%s: rx queue %p, link %p\n", __func__, - (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); + (caddr_t)ath_hal_getrxbuf(ah), sc->sc_rxlink); +#ifdef BLE STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { struct ath_desc *ds = bf->bf_desc; AR5K_STATUS status = ath_hal_rxprocdesc(ah, ds, @@ -4945,6 +4985,7 @@ ath_stoprecv(struct ath_softc *sc) if (status == AR5K_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) ath_printrxbuf(bf, status == AR5K_OK); } +#endif } #endif sc->sc_rxlink = NULL; /* just in case */ @@ -4958,8 +4999,7 @@ static int ath_startrecv(struct ath_softc *sc) { struct ath_hal *ah = sc->sc_ah; - struct ieee80211com *ic = &sc->sc_ic; - struct net_device *dev = ic->ic_dev; +// struct net_device *dev = ic->ic_dev; struct ath_buf *bf; /* @@ -4982,6 +5022,7 @@ ath_startrecv(struct ath_softc *sc) #else sc->sc_rxbufsize = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz); #endif +#ifdef BLE DPRINTF(sc, ATH_DEBUG_RESET, "%s: mtu %u cachelsz %u rxbufsize %u\n", __func__, dev->mtu, sc->sc_cachelsz, sc->sc_rxbufsize); @@ -4997,28 +5038,30 @@ ath_startrecv(struct ath_softc *sc) } bf = STAILQ_FIRST(&sc->sc_rxbuf); +#endif + bf = NULL; ath_hal_putrxbuf(ah, bf->bf_daddr); ath_hal_rxena(ah); /* enable recv descriptors */ - ath_mode_init(dev); /* set filters, etc. */ +// ath_mode_init(dev); /* set filters, etc. */ ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ return 0; } +#ifdef BLE /* * Update internal state after a channel change. */ static void ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) { - struct ieee80211com *ic = &sc->sc_ic; - enum ieee80211_phymode mode; - u_int16_t flags; + unsigned int mode; +// u_int16_t flags; /* * Change channels and update the h/w rate map * if we're switching; e.g. 11a to 11b/g. */ - mode = ieee80211_chan2mode(ic, chan); +// mode = ieee80211_chan2mode(ic, chan); if (mode != sc->sc_curmode) ath_setcurmode(sc, mode); /* @@ -5047,20 +5090,20 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) { struct ath_hal *ah = sc->sc_ah; - struct ieee80211com *ic = &sc->sc_ic; AR5K_CHANNEL hchan; - int opmode; /* * Convert to a HAL channel description with * the flags constrained to reflect the current * operating mode. */ +#ifdef BLE if (chan == IEEE80211_CHAN_ANYC) { return 0; } - hchan.freq = chan->ic_freq; + hchan.freq = chan->freq; hchan.channel_flags = ath_chan2flags(ic, chan); +#endif DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", __func__, @@ -5081,11 +5124,11 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) ath_hal_intrset(ah, 0); /* disable interrupts */ ath_draintxq(sc); /* clear pending tx frames */ ath_stoprecv(sc); /* turn off frame recv */ - opmode = (ic->ic_opmode == IEEE80211_M_AHDEMO) ? 0 : ic->ic_opmode; - if (!ath_hal_reset(ah, opmode, &hchan, TRUE, &status)) { - if_printf(ic->ic_dev, "ath_chan_set: unable to reset " - "channel %u (%u Mhz)\n", - ieee80211_chan2ieee(ic, chan), chan->ic_freq); + if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, TRUE, &status)) { + printk(KERN_ERR "ath_chan_set: unable to reset " + "channel %u (%u Mhz)\n", 0, +// ieee80211_chan2ieee(ic, chan), + chan->freq); return EIO; } sc->sc_curchan = hchan; @@ -5096,8 +5139,8 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) * Re-enable rx framework. */ if (ath_startrecv(sc) != 0) { - if_printf(ic->ic_dev, - "ath_chan_set: unable to restart recv logic\n"); + printk(KERN_ERR "ath_chan_set: unable to restart recv " + "logic\n"); return EIO; } @@ -5105,7 +5148,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) * Change channels and update the h/w rate map * if we're switching; e.g. 11a to 11b/g. */ - ic->ic_ibss_chan = chan; +// ic->ic_ibss_chan = chan; ath_chan_change(sc, chan); /* @@ -5115,16 +5158,17 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) } return 0; } - +#endif static void ath_next_scan(unsigned long arg) { +#ifdef BLE struct net_device *dev = (struct net_device *) arg; struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; if (ic->ic_state == IEEE80211_S_SCAN) ieee80211_next_scan(ic); +#endif } /* @@ -5162,7 +5206,7 @@ ath_calibrate(unsigned long arg) sc->sc_cal_ch.expires = jiffies + (ath_calinterval * HZ); add_timer(&sc->sc_cal_ch); } - +#ifdef BLE static int ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) { @@ -5358,26 +5402,25 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) if (isnew && (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, - ("new assoc with a unicast key already setup (keyix %u)", - ni->ni_ucastkey.wk_keyix)); + "new assoc with a unicast key already setup (keyix %u)", + ni->ni_ucastkey.wk_keyix); ath_setup_stationkey(ni); } } - +#endif static int ath_getchannels(struct net_device *dev, u_int cc, AR5K_BOOL outdoor, AR5K_BOOL xchanmode) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; AR5K_CHANNEL *chans; int i, ix; u_int nchan; - +#define IEEE80211_CHAN_MAX 255 chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(AR5K_CHANNEL), GFP_KERNEL); if (chans == NULL) { - if_printf(dev, "unable to allocate channel table\n"); + printk(KERN_ERR "unable to allocate channel table\n"); return ENOMEM; } if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, @@ -5385,7 +5428,7 @@ ath_getchannels(struct net_device *dev, u_int cc, u_int32_t rd; ath_hal_getregdomain(ah, &rd); - if_printf(dev, "unable to collect channel list from hal; " + printk(KERN_ERR "unable to collect channel list from hal; " "regdomain likely %u country code %u\n", rd, cc); kfree(chans); return EINVAL; @@ -5399,10 +5442,11 @@ ath_getchannels(struct net_device *dev, u_int cc, AR5K_CHANNEL *c = &chans[i]; ix = ath_hal_mhz2ieee(c->freq, c->channel_flags); if (ix > IEEE80211_CHAN_MAX) { - if_printf(dev, "bad hal channel %u (%u/%x) ignored\n", + printk(KERN_ERR "bad hal channel %u (%u/%x) ignored\n", ix, c->freq, c->channel_flags); continue; } +#ifdef BLE /* NB: flags are known to be compatible */ if (ic->ic_channels[ix].ic_freq == 0) { ic->ic_channels[ix].ic_freq = c->freq; @@ -5411,9 +5455,11 @@ ath_getchannels(struct net_device *dev, u_int cc, /* channels overlap; e.g. 11g and 11b */ ic->ic_channels[ix].ic_flags |= c->channel_flags; } +#endif } kfree(chans); return 0; +#undef IEEE80211_CHAN_MAX } /* @@ -5434,7 +5480,7 @@ ath_led_off(unsigned long arg) mod_timer(&sc->sc_ledtimer, jiffies + sc->sc_ledoff); } } - +#ifdef BLE /* * Blink the LED according to the specified on/off times. */ @@ -5471,11 +5517,11 @@ ath_led_event(struct ath_softc *sc, int event) break; } } - +#endif static void ath_update_txpow(struct ath_softc *sc) { - struct ieee80211com *ic = &sc->sc_ic; +#ifdef BLE struct ath_hal *ah = sc->sc_ah; u_int32_t txpow; @@ -5490,6 +5536,7 @@ ath_update_txpow(struct ath_softc *sc) */ (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); ic->ic_bss->ni_txpower = txpow; +#endif } static int @@ -5497,25 +5544,24 @@ ath_rate_setup(struct net_device *dev, u_int mode) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - struct ieee80211com *ic = &sc->sc_ic; const AR5K_RATE_TABLE *rt; - struct ieee80211_rateset *rs; - int i, maxrates; +// struct ieee80211_rateset *rs; +// int i, maxrates; switch (mode) { - case IEEE80211_MODE_11A: + case MODE_IEEE80211A: sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_11A); break; - case IEEE80211_MODE_11B: + case MODE_IEEE80211B: sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_11B); break; - case IEEE80211_MODE_11G: + case MODE_IEEE80211G: sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_11G); break; - case IEEE80211_MODE_TURBO_A: + case MODE_ATHEROS_TURBO: sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_TURBO); break; - case IEEE80211_MODE_TURBO_G: + case MODE_ATHEROS_TURBOG: sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_108G); break; default: @@ -5526,6 +5572,7 @@ ath_rate_setup(struct net_device *dev, u_int mode) rt = sc->sc_rates[mode]; if (rt == NULL) return 0; +#ifdef BLE if (rt->rate_count > IEEE80211_RATE_MAXSIZE) { DPRINTF(sc, ATH_DEBUG_ANY, "%s: rate table too small (%u > %u)\n", @@ -5537,14 +5584,16 @@ ath_rate_setup(struct net_device *dev, u_int mode) for (i = 0; i < maxrates; i++) rs->rs_rates[i] = rt->rates[i].dot11_rate; rs->rs_nrates = maxrates; +#endif return 1; } static void -ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) +ath_setcurmode(struct ath_softc *sc, unsigned int mode) { #define N(a) (sizeof(a)/sizeof(a[0])) /* NB: on/off times from the Atheros NDIS driver, w/ permission */ +#ifdef BLE static const struct { u_int rate; /* tx/rx 802.11 rate */ u_int16_t timeOn; /* LED on time (ms) */ @@ -5565,12 +5614,14 @@ ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) { 2, 400, 100 }, { 0, 500, 130 }, }; +#endif const AR5K_RATE_TABLE *rt; - int i, j; +// int i, j; memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); rt = sc->sc_rates[mode]; - KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); + KASSERT(rt != NULL, "no h/w rate set for phy mode %u", mode); +#ifdef BLE for (i = 0; i < rt->rate_count; i++) sc->sc_rixmap[rt->rates[i].dot11_rate & IEEE80211_RATE_VAL] = i; memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); @@ -5599,6 +5650,7 @@ ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * HZ) / 1000; sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * HZ) / 1000; } +#endif sc->sc_currates = rt; sc->sc_curmode = mode; /* @@ -5606,12 +5658,12 @@ ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) * 11g, otherwise at 1Mb/s. * XXX select protection rate index from rate table. */ - sc->sc_protrix = ((mode == IEEE80211_MODE_11G || mode == IEEE80211_MODE_TURBO_G) ? 1 : 0); + sc->sc_protrix = ((mode == MODE_IEEE80211G || mode == MODE_ATHEROS_TURBOG) ? 1 : 0); /* NB: caller is responsible for reseting rate control state */ #undef N } - +#ifdef BLE static int ath_rawdev_attach(struct ath_softc *sc) { @@ -5659,6 +5711,7 @@ ath_rawdev_detach(struct ath_softc *sc) unregister_netdev(&sc->sc_rawdev); } } + #if IEEE80211_VLAN_TAG_USED static void ath_vlan_register(struct net_device *dev, struct vlan_group *grp) @@ -5678,7 +5731,7 @@ ath_vlan_kill_vid(struct net_device *dev, unsigned short vid) ieee80211_vlan_kill_vid(ic, vid); } #endif /* IEEE80211_VLAN_TAG_USED */ - +#endif #ifdef AR_DEBUG static void ath_printrxbuf(struct ath_buf *bf, int done) @@ -5706,7 +5759,7 @@ ath_printtxbuf(struct ath_buf *bf, int done) !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); } #endif /* AR_DEBUG */ - +#ifdef BLE /* * Return netdevice statistics. */ @@ -5742,10 +5795,9 @@ static struct iw_statistics * ath_iw_getstats(struct net_device *dev) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; struct iw_statistics *is = &sc->sc_iwstats; - ieee80211_iw_getstats(ic, is); +// ieee80211_iw_getstats(ic, is); /* add in statistics maintained by the driver */ is->discard.code += sc->sc_stats.ast_rx_badcrypt; is->discard.retries += sc->sc_stats.ast_tx_xretries; @@ -5960,7 +6012,6 @@ static int ath_set_mac_address(struct net_device *dev, void *addr) { struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; struct sockaddr *mac = addr; int error = 0; @@ -5977,8 +6028,8 @@ ath_set_mac_address(struct net_device *dev, void *addr) ATH_LOCK(sc); /* XXX not right for multiple vap's */ - IEEE80211_ADDR_COPY(ic->ic_myaddr, mac->sa_data); - IEEE80211_ADDR_COPY(dev->dev_addr, mac->sa_data); +// IEEE80211_ADDR_COPY(ic->ic_myaddr, mac->sa_data); + memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN); ath_hal_setmac(ah, dev->dev_addr); if ((dev->flags & IFF_RUNNING) && !sc->sc_invalid) { error = -ath_reset(dev); @@ -6082,7 +6133,6 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) #define IS_RUNNING(dev) \ ((dev->flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; int error = 0; ATH_LOCK(sc); @@ -6105,7 +6155,7 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) * torn down much of our state. There's * probably a better way to deal with this. */ - if (!sc->sc_invalid && ic->ic_bss != NULL) +// if (!sc->sc_invalid && ic->ic_bss != NULL) ath_init(dev); /* XXX lose error */ } else ath_stop_locked(dev); @@ -6120,6 +6170,7 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) if (dev->flags & IFF_RUNNING) ath_mode_init(dev); break; +#ifdef BLE case SIOCGATHSTATS: /* NB: embed these numbers to get a consistent view */ sc->sc_stats.ast_tx_packets = ic->ic_devstats->tx_packets; @@ -6132,6 +6183,7 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) else error = 0; break; +#endif case SIOCGATHDIAG: if (!capable(CAP_NET_ADMIN)) error = -EPERM; @@ -6145,6 +6197,7 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) error = ath_ioctl_ethtool(sc, cmd, ifr->ifr_data); break; default: +#ifdef BLE error = ieee80211_ioctlx(ic, ifr, cmd); if (error == -ENETRESET) { if (IS_RUNNING(dev) && @@ -6154,13 +6207,14 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) } if (error == -ERESTART) error = IS_RUNNING(dev) ? ath_reset(dev) : 0; +#endif break; } ATH_UNLOCK(sc); return error; #undef IS_RUNNING } - +#endif /* * Sysctls are split into ``static'' and ``dynamic'' tables. * The former are defined at module load time and are used @@ -6206,7 +6260,6 @@ static int ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) { struct ath_softc *sc = ctl->extra1; - struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; u_int val; int ret; @@ -6273,9 +6326,10 @@ ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) /* XXX validate? */ ath_hal_settpc(ah, val); break; +#ifdef BLE case ATH_TXPOWLIMIT: /* XXX validate? */ - ic->ic_txpowlimit = val; + ic->ic_txpowlimit = val; ath_reset(&sc->sc_dev); break; case ATH_BINTVAL: @@ -6313,6 +6367,7 @@ ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) } ath_reset(&sc->sc_dev); break; +#endif case ATH_RXFILTER: sc->sc_rxfilter = val; ath_reset(&sc->sc_dev); @@ -6378,7 +6433,7 @@ ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) val = sc->sc_hasveol; break; case ATH_BINTVAL: - val = (sc->sc_ic).ic_lintval; +// val = (sc->sc_ic).ic_lintval; break; case ATH_RAWDEV: val = sc->sc_rawdev_enabled; @@ -6561,7 +6616,7 @@ ath_dynamic_sysctl_register(struct ath_softc *sc) for (i = 4; sc->sc_sysctls[i].ctl_name; i++) if (sc->sc_sysctls[i].extra1 == NULL) sc->sc_sysctls[i].extra1 = sc; - +#ifdef BLE /* and register everything */ sc->sc_sysctl_header = ATH_REGISTER_SYSCTL_TABLE(sc->sc_sysctls); if (!sc->sc_sysctl_header) { @@ -6569,7 +6624,7 @@ ath_dynamic_sysctl_register(struct ath_softc *sc) kfree(sc->sc_sysctls); sc->sc_sysctls = NULL; } - +#endif /* initialize values */ #ifdef AR_DEBUG sc->sc_debug = ath_debug; @@ -6599,12 +6654,12 @@ static void ath_announce(struct ath_softc *sc) { #define AR5K_MODE_DUALBAND (AR5K_MODE_11A|AR5K_MODE_11B) - struct net_device *dev = &sc->sc_dev; +// struct net_device *dev = &sc->sc_dev; struct ath_hal *ah = sc->sc_ah; u_int modes, cc; - int i; +// int i; - if_printf(dev, "mac %d.%d phy %d.%d", + printk(KERN_INFO "mac %d.%d phy %d.%d", ah->ah_mac_version, ah->ah_mac_version, ah->ah_phy_revision >> 4, ah->ah_phy_revision & 0xf); /* @@ -6628,14 +6683,16 @@ ath_announce(struct ath_softc *sc) printk(" radio %d.%d", ah->ah_radio_5ghz_revision >> 4, ah->ah_radio_5ghz_revision & 0xf); printk("\n"); +#ifdef BLE for (i = 0; i <= WME_AC_VO; i++) { struct ath_txq *txq = sc->sc_ac2q[i]; - if_printf(dev, "Use hw queue %u for %s traffic\n", - txq->axq_qnum, ieee80211_wme_acnames[i]); + printk(KERN_INFO "Use hw queue %u for %s traffic\n", + txq->axq_qnum, ieee80211_wme_acnames[i]); } - if_printf(dev, "Use hw queue %u for CAB traffic\n", - sc->sc_cabq->axq_qnum); - if_printf(dev, "Use hw queue %u for beacons\n", sc->sc_bhalq); +#endif + printk(KERN_INFO "Use hw queue %u for CAB traffic\n", + sc->sc_cabq->axq_qnum); + printk(KERN_INFO "Use hw queue %u for beacons\n", sc->sc_bhalq); #ifdef AR_DEBUG printk("Debugging version (ATH)\n"); @@ -6731,8 +6788,7 @@ ath_sysctl_register(void) static int initialized = 0; if (!initialized) { - ath_sysctl_header = - ATH_REGISTER_SYSCTL_TABLE(ath_root_table); + ath_sysctl_header = register_sysctl_table(ath_root_table); initialized = 1; } } diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 2bdd297..439749e 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -59,9 +59,6 @@ #include -#include "if_media.h" -#include - #include "if_athvar.h" #include "if_ath_pci.h" diff --git a/ath/if_athioctl.h b/ath/if_athioctl.h index 2b0935f..24ab592 100644 --- a/ath/if_athioctl.h +++ b/ath/if_athioctl.h @@ -42,6 +42,8 @@ #ifndef _DEV_ATH_ATHIOCTL_H #define _DEV_ATH_ATHIOCTL_H +#include + struct ath_stats { u_int32_t ast_watchdog; /* device reset by watchdog */ u_int32_t ast_hardware; /* fatal hardware error interrupts */ diff --git a/ath/if_athrate.h b/ath/if_athrate.h index d8f251c..ff4beaf 100644 --- a/ath/if_athrate.h +++ b/ath/if_athrate.h @@ -110,13 +110,14 @@ void ath_rate_node_cleanup(struct ath_softc *, struct ath_node *); */ void ath_rate_newassoc(struct ath_softc *, struct ath_node *, int isNewAssociation); +#ifdef BLE /* * Update/reset rate control state for 802.11 state transitions. * Important mostly as the analog to ath_rate_newassoc when operating * in station mode. */ void ath_rate_newstate(struct ath_softc *, enum ieee80211_state); - +#endif /* * Transmit handling. */ diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 3320729..16edb96 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -43,11 +43,11 @@ #define _DEV_ATH_ATHVAR_H #include "ah.h" -#include "../net80211/ieee80211_radiotap.h" #include "if_athioctl.h" #include "if_athrate.h" #include +#include #ifndef ARPHRD_IEEE80211_RADIOTAP #define ARPHRD_IEEE80211_RADIOTAP 803 /* IEEE 802.11 + radiotap header */ @@ -153,7 +153,9 @@ typedef void irqreturn_t; /* driver-specific node state */ struct ath_node { +#ifdef BLE struct ieee80211_node an_node; /* base class */ +#endif u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */ u_int32_t an_avgrssi; /* average rssi over all rx frames */ @@ -175,20 +177,20 @@ struct ath_node { } while (0) struct ath_buf { - STAILQ_ENTRY(ath_buf) bf_list; + struct list_head bf_list; //int bf_nseg; int bf_flags; /* tx descriptor flags */ struct ath_desc *bf_desc; /* virtual addr of desc */ dma_addr_t bf_daddr; /* physical addr of desc */ struct sk_buff *bf_skb; /* skbuff for buf */ dma_addr_t bf_skbaddr; /* physical addr of skb data */ +#ifdef BLE struct ieee80211_node *bf_node; /* pointer to the node */ +#endif }; -typedef STAILQ_HEAD(, ath_buf) ath_bufhead; struct ath_hal; struct ath_desc; -struct proc_dir_entry; /* * Data transmit queue state. One of these exists for each @@ -204,7 +206,7 @@ struct ath_txq { u_int axq_depth; /* queue depth (stat only) */ u_int axq_intrcnt; /* interrupt count */ u_int32_t *axq_link; /* link ptr in last TX desc */ - STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ + struct list_head axq_q; /* transmit queue */ spinlock_t axq_lock; /* lock on q and link */ /* * State for patching up CTS when bursting. @@ -246,10 +248,15 @@ struct ath_softc { struct semaphore sc_lock; /* dev-level lock */ struct net_device_stats sc_devstats; /* device statistics */ struct ath_stats sc_stats; /* private statistics */ + struct ieee80211_hw sc_hw; /* IEEE 802.11 common */ +#ifdef BLE struct ieee80211com sc_ic; /* IEEE 802.11 common */ +#endif + enum ieee80211_if_types sc_opmode; int sc_regdomain; int sc_countrycode; int sc_debug; +#ifdef BLE void (*sc_recv_mgmt)(struct ieee80211com *, struct sk_buff *, struct ieee80211_node *, @@ -257,6 +264,7 @@ struct ath_softc { int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); void (*sc_node_free)(struct ieee80211_node *); +#endif void *sc_bdev; /* associated bus device */ struct ath_desc *sc_desc; /* TX/RX descriptors */ size_t sc_desc_len; /* size of TX/RX descriptors */ @@ -280,9 +288,9 @@ struct ath_softc { sc_hasclrkey:1, /* CLR key supported */ sc_rawdev_enabled : 1; /* enable sc_rawdev */ /* rate tables */ - const AR5K_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; + const AR5K_RATE_TABLE *sc_rates[NUM_IEEE80211_MODES]; const AR5K_RATE_TABLE *sc_currates; /* current rate table */ - enum ieee80211_phymode sc_curmode; /* current phy mode */ + unsigned int sc_curmode; /* current phy mode */ u_int16_t sc_curtxpow; /* current tx power limit */ AR5K_CHANNEL sc_curchan; /* current h/w channel */ u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ @@ -297,8 +305,10 @@ struct ath_softc { u_int sc_txantenna; /* tx antenna (fixed or auto) */ AR5K_INT sc_imask; /* interrupt mask copy */ u_int sc_keymax; /* size of key cache */ +#ifdef BLE u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ +#endif u_int sc_ledpin; /* GPIO pin for driving LED */ u_int sc_ledon; /* pin setting for LED on */ @@ -325,14 +335,14 @@ struct ath_softc { struct tq_struct sc_radartq; /* Radar detection */ int sc_rxbufsize; /* rx size based on mtu */ - ath_bufhead sc_rxbuf; /* receive buffer */ + struct list_head *sc_rxbuf; /* receive buffer */ u_int32_t *sc_rxlink; /* link ptr in last RX desc */ struct tq_struct sc_rxtq; /* rx intr tasklet */ struct tq_struct sc_rxorntq; /* rxorn intr tasklet */ u_int8_t sc_defant; /* current default antenna */ u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ - ath_bufhead sc_txbuf; /* transmit buffer */ + struct list_head *sc_txbuf; /* transmit buffer */ spinlock_t sc_txbuflock; /* txbuf lock */ int sc_tx_timer; /* transmit timeout */ u_int sc_txqsetup; /* h/w queues setup */ @@ -341,13 +351,15 @@ struct ath_softc { struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ struct tq_struct sc_txtq; /* tx intr tasklet */ - ath_bufhead sc_bbuf; /* beacon buffers */ + struct list_head *sc_bbuf; /* beacon buffers */ u_int sc_bhalq; /* HAL q for outgoing beacons */ u_int sc_bmisscount; /* missed beacon transmits */ u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ struct ath_txq *sc_cabq; /* tx q for cab frames */ struct ath_buf *sc_bufptr; /* allocated buffer ptr */ +#ifdef BLE struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ +#endif struct tq_struct sc_bmisstq; /* bmiss intr tasklet */ struct tq_struct sc_bstuckq; /* stuck beacon processing */ enum { diff --git a/ath/radar.c b/ath/radar.c index adaffae..1da9edf 100644 --- a/ath/radar.c +++ b/ath/radar.c @@ -8,10 +8,7 @@ #include #include -#include "if_media.h" - -#include -#include "radar.h" +//#include "radar.h" /* diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 444b97f..8fc2ad3 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -33,6 +33,8 @@ #ifndef _AR5K_H #define _AR5K_H +#include + /*Os dependent definitions*/ #include "ah_osdep.h" #include "ath5k_hw.h" @@ -49,14 +51,12 @@ */ #include "translation.h" -/*Use with MadWiFi/net80211*/ -#include "stack_net80211.h" - - /****************************\ GENERIC DRIVER DEFINITIONS \****************************/ +#define howmany(x, y) (((x)+((y)-1))/(y)) + /* * C doesn't support boolean ;-( * TODO: See if there is a bool definition somewere else @@ -195,6 +195,28 @@ struct ath5k_srev_name { #define AR5K_SREV_RAD_UNSUPP 0x50 +/* IEEE defs */ + +#define IEEE80211_MAX_LEN 2500 + +#define MAX_PDU_LENGTH IEEE80211_MAX_LEN +#define MODULATION_CCK IEEE80211_RATE_CCK +#define MODULATION_OFDM IEEE80211_RATE_OFDM +#define MODULATION_TURBO IEEE80211_RATE_TURBO +#define MODULATION_XR 0x00000200 /*XR thingie*/ +#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ + +#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code + enables short preamble, see ar5212_reg.h */ +#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) +#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 + +typedef enum { + AR5K_M_STA = IEEE80211_IF_TYPE_STA, + AR5K_M_IBSS = IEEE80211_IF_TYPE_IBSS, + AR5K_M_HOSTAP = IEEE80211_IF_TYPE_AP, + AR5K_M_MONITOR = IEEE80211_IF_TYPE_MNTR, +} AR5K_OPMODE; /****************\ diff --git a/openhal/stack_d80211.h b/openhal/stack_d80211.h deleted file mode 100644 index fbcde4f..0000000 --- a/openhal/stack_d80211.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/*d80211 definitions needed for use with dadwifi*/ -#include - -#define IEEE80211_MAX_LEN 2500 - -#define MAX_PDU_LENGTH IEEE80211_MAX_LEN -#define MODULATION_CCK IEEE80211_RATE_CCK -#define MODULATION_OFDM IEEE80211_RATE_OFDM -#define MODULATION_TURBO IEEE80211_RATE_TURBO -#define MODULATION_XR 0x00000200 /*XR thingie*/ -#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ - -#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code - enables short preamble, see ar5212_reg.h */ -#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) -#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 - -typedef enum { - AR5K_M_STA = IEEE80211_IF_TYPE_STA, - AR5K_M_IBSS = IEEE80211_IF_TYPE_IBSS, - AR5K_M_HOSTAP = IEEE80211_IF_TYPE_AP, - AR5K_M_MONITOR = IEEE80211_IF_TYPE_MNTR, -}AR5K_OPMODE; diff --git a/openhal/stack_net80211.h b/openhal/stack_net80211.h deleted file mode 100644 index 7c218bf..0000000 --- a/openhal/stack_net80211.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/*net80211 definitions needed for use with madwifi*/ -#include -#include - -#define MAX_PDU_LENGTH IEEE80211_MAX_LEN -#define MODULATION_CCK IEEE80211_T_CCK -#define MODULATION_OFDM IEEE80211_T_OFDM -#define MODULATION_TURBO IEEE80211_T_TURBO -#define MODULATION_XR 7 /*XR thingie*/ -#define MODULATION_CCK_SP 8 /*CCK + Shortpreamble*/ - -#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code - enables short preamble, see ar5212_reg.h */ -#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) -#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 - -typedef enum { - AR5K_M_STA = IEEE80211_M_STA, - AR5K_M_IBSS = IEEE80211_M_IBSS, - AR5K_M_HOSTAP = IEEE80211_M_HOSTAP, - AR5K_M_MONITOR = IEEE80211_M_MONITOR, -}AR5K_OPMODE; commit e3102a95e057f0092cc9408cdbe587787d20cdb0 Author: Jiri Slaby Date: Sun Jun 17 10:02:53 2007 +0200 backport g support diff --git a/ath/if_ath.c b/ath/if_ath.c index 7533e01..eefbbed 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -1026,7 +1026,7 @@ ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 0, /* IEEE80211_MODE_AUTO */ CHANNEL_A, /* IEEE80211_MODE_11A */ CHANNEL_B, /* IEEE80211_MODE_11B */ - CHANNEL_PUREG, /* IEEE80211_MODE_11G */ + CHANNEL_G, /* IEEE80211_MODE_11G */ 0, /* IEEE80211_MODE_FH */ CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 8fc2ad3..153a1fe 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -593,17 +593,12 @@ typedef struct { #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ -#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation)*/ +#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ #define CHANNEL_XR 0x0800 /* XR channel */ #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) -#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) -//#ifdef notdef -#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN) -//#else -//#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) -//#endif +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) #define CHANNEL_108A CHANNEL_T diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index d8caeb5..5ceb363 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -227,14 +227,14 @@ ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates, * Return the supported 802.11 operation modes * TODO:Left here for combatibility, change it in at5k */ -u_int/*TODO:Fix this & fix g support*/ +u_int/*TODO:Fix this */ ath_hal_getwirelessmodes(struct ath_hal *hal, AR5K_CTRY_CODE country) { switch(hal->ah_version){ case AR5K_AR5212: - return (AR5K_MODE_11A|AR5K_MODE_11B); + return (AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G); case AR5K_AR5211: - return (AR5K_MODE_11A|AR5K_MODE_11B); + return (AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G); default : return(AR5K_MODE_11A); } @@ -594,15 +594,15 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, AR5K_BOOL initial) if (flags & CHANNEL_CCK) { mode |= AR5K_PHY_MODE_MOD_CCK; - } else if (flags & CHANNEL_OFDM) { - mode |= AR5K_PHY_MODE_MOD_OFDM; - } else if (flags & CHANNEL_DYN) { + } else if (flags & CHANNEL_G) { /* Dynamic OFDM/CCK is not supported by the AR5211 */ if (hal->ah_version == AR5K_AR5211) { - mode |= AR5K_PHY_MODE_MOD_CCK; + mode |= AR5K_PHY_MODE_MOD_OFDM; } else { mode |= AR5K_PHY_MODE_MOD_DYN; } + } else if (flags & CHANNEL_OFDM) { + mode |= AR5K_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); return (FALSE); @@ -1062,7 +1062,7 @@ ath5k_hw_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { AR5K_REG_WRITE(AR5K_PHY_CCKTXCTL, AR5K_PHY_CCKTXCTL_WORLD); - if (channel->channel_flags & CHANNEL_OFDM) + if (channel->channel_flags & CHANNEL_A) data = 0xffb81020; else data = 0xffb80d20; @@ -1286,7 +1286,7 @@ ath5k_hw_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, return (FALSE); } - /* Wait until the noise floor is calibrated */ + /* Wait until the noise floor is calibrated and read the value */ for (i = 20; i > 0; i--) { udelay(1000); noise_floor = AR5K_REG_READ(AR5K_PHY_NF); @@ -2627,10 +2627,9 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) if (AR5K_EEPROM_HDR_11B(ee_header)) hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; -#if 0 + if (AR5K_EEPROM_HDR_11G(ee_header)) hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; -#endif } } @@ -4816,11 +4815,8 @@ ath_hal_init_channels(struct ath_hal *hal, AR5K_CHANNEL *channels, min = 1; /* 2GHz channel 1 -2412Mhz */ max = 26;/* 2GHz channel 26 (non-ieee) -2732Mhz */ - flags = CHANNEL_B /*| CHANNEL_TG | - (hal->ah_version == AR5K_AR5211 ? - CHANNEL_PUREG : CHANNEL_G)*/; - - debugchan: + flags = CHANNEL_B | CHANNEL_G; +debugchan: for (i = min; (i <= max) && (c < max_channels); i++) { freq = ath_hal_ieee2mhz(i, flags); if (ath5k_check_channel(hal, freq, flags) == FALSE) @@ -4908,12 +4904,10 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11G) && (ath5k_2ghz_channels[i].rc_mode & CHANNEL_OFDM)) { - all_channels[c].channel_flags |= - hal->ah_version == AR5K_AR5211 ? - CHANNEL_PUREG : CHANNEL_G; - if (ath5k_2ghz_channels[i].rc_mode & + all_channels[c].channel_flags |= CHANNEL_G; +/* if (ath5k_2ghz_channels[i].rc_mode & CHANNEL_TURBO) - all_channels[c].channel_flags |= CHANNEL_TG; + all_channels[c].channel_flags |= CHANNEL_TG;*/ } /* Write channel and increment counter */ commit d126a7865370e18c989898c23d7f063203a3c2d9 Author: Jiri Slaby Date: Sun Jun 17 10:05:09 2007 +0200 some openhal/ath5kreg (radar) changes diff --git a/openhal/ath5kreg.h b/openhal/ath5kreg.h index c871df8..d21b057 100644 --- a/openhal/ath5kreg.h +++ b/openhal/ath5kreg.h @@ -1802,11 +1802,48 @@ #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* - * PHY radar detection enable register [5111+] + * PHY radar detection register [5111+] */ #define AR5K_PHY_RADAR 0x9954 -#define AR5K_PHY_RADAR_DISABLE 0x00000000 + +/* Radar enable ........ ........ ........ .......1 */ #define AR5K_PHY_RADAR_ENABLE 0x00000001 +#define AR5K_PHY_RADAR_DISABLE 0x00000000 +#define AR5K_PHY_RADAR_ENABLE_S 0 + +/* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... +at power on. */ +#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 + +/* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1 +after DFS is enabled */ +#define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d + +/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ + * power out threshold. + * 7-bits, standard power range {0..127} in 1/2 dBm units. */ +#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 +#define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24 + +/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ + * 6-bits, dBm range {0..63} in dBm units. */ +#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 +#define AR5K_PHY_RADAR_RADARRSSITHR_S 18 + +/* Pulse height threshold ........ ......11 1111.... ........ + * 6-bits, dBm range {0..63} in dBm units. */ +#define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000 +#define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12 + +/* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... + * 6-bits, dBm range {0..63} in dBm units. */ +#define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0 +#define AR5K_PHY_RADAR_PULSERSSITHR_S 6 + +/* Inband threshold ........ ........ ........ ..11111. + * 5-bits, units unknown {0..31} (? MHz ?) */ +#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e +#define AR5K_PHY_RADAR_INBANDTHR_S 1 /* * PHY antenna switch table registers [5110] commit b7e3495dc0f9a83566bd4bae96af0590944557ea Author: Jiri Slaby Date: Sun Jun 17 10:17:36 2007 +0200 ah_osdep cleanup diff --git a/openhal/ah_osdep.c b/openhal/ah_osdep.c index 0d87d48..1b83167 100644 --- a/openhal/ah_osdep.c +++ b/openhal/ah_osdep.c @@ -9,85 +9,52 @@ * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ */ -#include "ah.h" - -/*Definitions for module loading/unloading - *combatible with 2.4 and 2.6 kernels*/ - -#ifndef __MOD_INC_USE_COUNT -#define AH_MOD_INC_USE_COUNT(_m) \ - if (!try_module_get(_m)) { \ - printk(KERN_WARNING "try_module_get failed\n"); \ - return NULL; \ - } -#define AH_MOD_DEC_USE_COUNT(_m) module_put(_m) -#else -#define AH_MOD_INC_USE_COUNT(_m) MOD_INC_USE_COUNT -#define AH_MOD_DEC_USE_COUNT(_m) MOD_DEC_USE_COUNT -#endif - -static char *dev_info = "ath_hal"; - -MODULE_AUTHOR("Nick Kossifidis"); -MODULE_DESCRIPTION("OpenHAL"); -MODULE_SUPPORTED_DEVICE("Atheros AR5xxx WLAN cards"); -#ifdef MODULE_LICENSE -MODULE_LICENSE("Dual BSD/GPL"); -#endif +#include "ath5k.h" -/*Attach/Dettach to HAL*/ +static char dev_info[] = "ath_hal"; -struct ath_hal * -_ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, - AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void* s) +struct ath_hal *_ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, + AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void *s) { - AR5K_STATUS status; - struct ath_hal *ah = ath5k_hw_init(devid, sc, t, h, &status); + AR5K_STATUS status; + struct ath_hal *ah = ath5k_hw_init(devid, sc, t, h, &status); + + *(AR5K_STATUS *)s = status; + if (ah && !try_module_get(THIS_MODULE)) { + printk(KERN_WARNING "try_module_get failed\n"); + kfree(ah); + return NULL; + } - *(AR5K_STATUS *)s = status; - if (ah) - AH_MOD_INC_USE_COUNT(THIS_MODULE); - return ah; + return ah; } +EXPORT_SYMBOL(_ath_hal_attach); -void -ath_hal_detach(struct ath_hal *ah) +void ath_hal_detach(struct ath_hal *ah) { - (*ah->ah_detach)(ah); - AH_MOD_DEC_USE_COUNT(THIS_MODULE); + ah->ah_detach(ah); + module_put(THIS_MODULE); } - -EXPORT_SYMBOL(ath_hal_probe); -EXPORT_SYMBOL(_ath_hal_attach); EXPORT_SYMBOL(ath_hal_detach); -EXPORT_SYMBOL(ath_hal_init_channels); -EXPORT_SYMBOL(ath_hal_getwirelessmodes); -EXPORT_SYMBOL(ath_hal_computetxtime); -EXPORT_SYMBOL(ath_hal_mhz2ieee); -EXPORT_SYMBOL(ath_hal_ieee2mhz); -static int __init -init_ath_hal(void) +static int __init ath_hal_init(void) { - printk(KERN_INFO "%s: OpenHAL loaded (AR5210, AR5211, AR5212, RF5110/1/2)\n", dev_info); - return (0); + printk(KERN_INFO "%s: OpenHAL loaded (AR5210, AR5211, AR5212, " + "RF5110/1/2)\n", dev_info); + return 0; } -module_init(init_ath_hal); -static void __exit -exit_ath_hal(void) +static void __exit ath_hal_exit(void) { printk(KERN_INFO "%s: driver unloaded\n", dev_info); } -module_exit(exit_ath_hal); + +module_init(ath_hal_init); +module_exit(ath_hal_exit); + +MODULE_AUTHOR("Nick Kossifidis"); +MODULE_DESCRIPTION("OpenHAL"); +MODULE_SUPPORTED_DEVICE("Atheros AR5xxx WLAN cards"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 5ceb363..ee9ba92 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -156,6 +156,7 @@ ath_hal_probe(u_int16_t vendor, u_int16_t device) return (NULL); } +EXPORT_SYMBOL(ath_hal_probe); /* * Calculate transmition time of a frame @@ -222,6 +223,7 @@ ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates, return (value); } +EXPORT_SYMBOL(ath_hal_computetxtime); /* * Return the supported 802.11 operation modes @@ -239,6 +241,7 @@ ath_hal_getwirelessmodes(struct ath_hal *hal, AR5K_CTRY_CODE country) return(AR5K_MODE_11A); } } +EXPORT_SYMBOL(ath_hal_getwirelessmodes); /* * Functions used internaly @@ -4734,6 +4737,7 @@ ath_hal_mhz2ieee(u_int freq, u_int flags) /* something is fishy, don't do anything */ return 0; } +EXPORT_SYMBOL(ath_hal_mhz2ieee); /* * Convert IEEE channel number to MHz frequency. @@ -4760,6 +4764,7 @@ ath_hal_ieee2mhz(u_int chan, u_int flags) return 5000 + (chan * 5); } } +EXPORT_SYMBOL(ath_hal_ieee2mhz); /* * Check if a channel is supported @@ -4920,6 +4925,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ kfree(all_channels); return (TRUE); } +EXPORT_SYMBOL(ath_hal_init_channels); /* * Regdomain stuff, these also don't belong here etc commit f3703cf522ed186e3ef5b1891d954c173d306a9d Author: Jiri Slaby Date: Sun Jun 17 11:48:00 2007 +0200 remove bus typedefs diff --git a/ath/if_ath.c b/ath/if_ath.c index eefbbed..0a76149 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -362,7 +362,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Attach the hal */ - ah = _ath_hal_attach(devid, sc, 0, sc->sc_iobase, &status); + ah = _ath_hal_attach(devid, sc, sc->sc_iobase, &status); if (ah == NULL) { printk(KERN_ERR "%s: unable to attach hardware: '%s' (HAL status %u)\n", __func__, hal_status_desc[status], status); diff --git a/openhal/ah_osdep.c b/openhal/ah_osdep.c index 1b83167..d2a14be 100644 --- a/openhal/ah_osdep.c +++ b/openhal/ah_osdep.c @@ -15,13 +15,11 @@ static char dev_info[] = "ath_hal"; -struct ath_hal *_ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, - AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void *s) +struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, + AR5K_STATUS *s) { - AR5K_STATUS status; - struct ath_hal *ah = ath5k_hw_init(devid, sc, t, h, &status); + struct ath_hal *ah = ath5k_hw_init(devid, sc, h, s); - *(AR5K_STATUS *)s = status; if (ah && !try_module_get(THIS_MODULE)) { printk(KERN_WARNING "try_module_get failed\n"); kfree(ah); diff --git a/openhal/ah_osdep.h b/openhal/ah_osdep.h index 973bcb8..3b0661e 100644 --- a/openhal/ah_osdep.h +++ b/openhal/ah_osdep.h @@ -9,42 +9,9 @@ * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ */ -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -/*For radar functions*/ -//#include - -#include -#include -#include -#include - - -typedef void* AR5K_SOFTC; -typedef int AR5K_BUS_TAG; -typedef __iomem void* AR5K_BUS_HANDLE; -typedef u_int32_t AR5K_BUS_ADDR; -#define bus_space_tag_t AR5K_BUS_TAG -#define bus_space_handle_t AR5K_BUS_HANDLE #define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) #define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 153a1fe..8f78f70 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -957,9 +957,6 @@ typedef enum ieee80211_countrycode AR5K_CTRY_CODE; #define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0])) -typedef struct ath_hal * (ath5k_attach_t) - (u_int16_t, AR5K_SOFTC, AR5K_BUS_TAG, AR5K_BUS_HANDLE, AR5K_STATUS *); - typedef AR5K_BOOL (ath5k_rfgain_t) (struct ath_hal *, AR5K_CHANNEL *, u_int); @@ -1064,7 +1061,7 @@ typedef AR5K_BOOL (ath5k_rfgain_t) _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, u_int32_t intval); \ _t void (_a _n##_set_beacon_timers)(struct ath_hal *, const AR5K_BEACON_STATE *); \ _t void (_a _n##_reset_beacon)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, AR5K_BUS_ADDR); \ + _t AR5K_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, unsigned long); \ /* Interrupt functions */ \ _t AR5K_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \ _t AR5K_BOOL (_a _n##_get_isr)(struct ath_hal *, u_int32_t *); \ @@ -1102,9 +1099,8 @@ struct ath_hal { u_int16_t ah_device; u_int16_t ah_sub_vendor; - AR5K_SOFTC ah_sc; - bus_space_tag_t ah_st; - bus_space_handle_t ah_sh; + void *ah_sc; + void __iomem *ah_sh; AR5K_CTRY_CODE ah_country_code; AR5K_INT ah_imr; @@ -1194,9 +1190,9 @@ struct ath_hal { * Prototypes */ -const char* ath_hal_probe(u_int16_t, u_int16_t); -struct ath_hal* ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG, - AR5K_BUS_HANDLE, AR5K_STATUS *); +const char *ath_hal_probe(u16, u16); +struct ath_hal *ath5k_hw_init(u16, void *, void __iomem *, + AR5K_STATUS *); u_int16_t ath_hal_computetxtime(struct ath_hal *, const AR5K_RATE_TABLE *, u_int32_t, u_int16_t, AR5K_BOOL); u_int ath_hal_mhz2ieee(u_int, u_int); @@ -1248,8 +1244,8 @@ AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); void ath5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); /*added*/ -extern u_int ath_hal_getwirelessmodes(struct ath_hal*, AR5K_CTRY_CODE); +extern u_int ath_hal_getwirelessmodes(struct ath_hal *, AR5K_CTRY_CODE); void ath_hal_detach(struct ath_hal *ah); -struct ath_hal * _ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, AR5K_BUS_TAG t, - AR5K_BUS_HANDLE h, void* s); +struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, + AR5K_STATUS *s); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index ee9ba92..fb59cd3 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -22,6 +22,8 @@ * (Please have a look at ar5xxx.h for further information) */ +#include + #include "ah_devid.h" #include "ath5k.h" #include "ath5kreg.h" @@ -354,8 +356,7 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, * Check if the device is supported and initialize the needed structs */ struct ath_hal * -ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, - AR5K_BUS_HANDLE sh, AR5K_STATUS *status) +ath5k_hw_init(u16 device, void *sc, void __iomem *sh, AR5K_STATUS *status) { struct ath_hal *hal = NULL; u_int8_t mac[ETH_ALEN]; @@ -392,7 +393,6 @@ ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, memset(hal, 0, sizeof(struct ath_hal)); hal->ah_sc = sc; - hal->ah_st = st; hal->ah_sh = sh; hal->ah_device = device; hal->ah_sub_vendor = 0; /* XXX unknown?! */ @@ -3206,7 +3206,7 @@ ath5k_hw_reset_beacon(struct ath_hal *hal) * TODO: This function's name is misleading, rename */ AR5K_BOOL -ath5k_hw_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) +ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) { AR5K_BOOL ret; int i; @@ -3228,7 +3228,7 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) /* * Re-schedule the beacon queue */ - AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, (u_int32_t)phys_addr); + AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, phys_addr); AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE); return (FALSE); commit 864ee6a9607787147044a9067c631ca8c235508c Author: Jiri Slaby Date: Sun Jun 17 11:58:43 2007 +0200 fix sparse warnings diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 8f78f70..7b62b51 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -211,12 +211,12 @@ struct ath5k_srev_name { #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) #define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 -typedef enum { +/*typedef enum { AR5K_M_STA = IEEE80211_IF_TYPE_STA, AR5K_M_IBSS = IEEE80211_IF_TYPE_IBSS, AR5K_M_HOSTAP = IEEE80211_IF_TYPE_AP, AR5K_M_MONITOR = IEEE80211_IF_TYPE_MNTR, -} AR5K_OPMODE; +} AR5K_OPMODE;*/ /****************\ @@ -957,6 +957,8 @@ typedef enum ieee80211_countrycode AR5K_CTRY_CODE; #define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0])) +struct ath_hal; + typedef AR5K_BOOL (ath5k_rfgain_t) (struct ath_hal *, AR5K_CHANNEL *, u_int); @@ -968,7 +970,7 @@ typedef AR5K_BOOL (ath5k_rfgain_t) _t const AR5K_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, u_int mode); \ _t void (_a _n##_detach)(struct ath_hal *); \ /* Reset functions */ \ - _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, AR5K_OPMODE, AR5K_CHANNEL *, \ + _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, enum ieee80211_if_types, AR5K_CHANNEL *, \ AR5K_BOOL change_channel, AR5K_STATUS *status); \ _t void (_a _n##_set_opmode)(struct ath_hal *); \ _t AR5K_BOOL (_a _n##_phy_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ @@ -1105,7 +1107,7 @@ struct ath_hal { AR5K_INT ah_imr; - AR5K_OPMODE ah_op_mode; + enum ieee80211_if_types ah_op_mode; AR5K_POWER_MODE ah_power_mode; AR5K_CHANNEL ah_current_channel; AR5K_BOOL ah_turbo; diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index fb59cd3..17814ca 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -405,7 +405,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, AR5K_STATUS *status) hal->ah_country_code = AR5K_TUNE_CTRY; ath5k_get_regdomain(hal); - hal->ah_op_mode = AR5K_M_STA; + hal->ah_op_mode = IEEE80211_IF_TYPE_STA; hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; hal->ah_turbo = FALSE; hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; @@ -794,8 +794,8 @@ ath5k_hw_detach(struct ath_hal *hal) * Main reset function */ AR5K_BOOL -ath5k_hw_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, - AR5K_BOOL change_channel, AR5K_STATUS *status) +ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, + AR5K_CHANNEL *channel, AR5K_BOOL change_channel, AR5K_STATUS *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int8_t mac[ETH_ALEN]; @@ -2669,7 +2669,7 @@ ath5k_hw_set_opmode(struct ath_hal *hal) AR5K_TRACE; switch (hal->ah_op_mode) { - case AR5K_M_IBSS: + case IEEE80211_IF_TYPE_IBSS: pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA | (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); @@ -2677,7 +2677,7 @@ ath5k_hw_set_opmode(struct ath_hal *hal) beacon_reg |= AR5K_BCR_ADHOC; break; - case AR5K_M_HOSTAP: + case IEEE80211_IF_TYPE_AP: pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA | (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); @@ -2685,10 +2685,10 @@ ath5k_hw_set_opmode(struct ath_hal *hal) beacon_reg |= AR5K_BCR_AP; break; - case AR5K_M_STA: + case IEEE80211_IF_TYPE_STA: pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_PWR_SV :0); - case AR5K_M_MONITOR: + case IEEE80211_IF_TYPE_MNTR: pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); break; @@ -3020,7 +3020,7 @@ ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, * Set the additional timers by mode */ switch (hal->ah_op_mode) { - case AR5K_M_STA: + case IEEE80211_IF_TYPE_STA: if (hal->ah_version == AR5K_AR5210) { timer1 = 0xffffffff; timer2 = 0xffffffff; @@ -3912,7 +3912,7 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) /* * Initialize the 2-word tx descriptor on 5210/5211 */ -AR5K_BOOL +static AR5K_BOOL ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, @@ -4129,7 +4129,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Fill the 2-word tx descriptor on 5210/5211 */ -AR5K_BOOL +static AR5K_BOOL ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) { @@ -4190,7 +4190,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the tx status descriptor on 5210/5211 */ -AR5K_STATUS +static AR5K_STATUS ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; @@ -4378,7 +4378,7 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the rx status descriptor on 5210/5211 */ -AR5K_STATUS +static AR5K_STATUS ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { commit 4815589cf66695bdfb0143b894e98dfd41a66669 Author: Jiri Slaby Date: Sun Jun 17 13:46:31 2007 +0200 pci_ids cleanup diff --git a/openhal/ah_devid.h b/openhal/ah_devid.h index 0bf0dbc..f17813b 100644 --- a/openhal/ah_devid.h +++ b/openhal/ah_devid.h @@ -5,42 +5,37 @@ /* From /dev/pci/pcidevs.h also incudes updates from the binary HAL's ah_devid.h */ -/*Vendors*/ -#define PCI_VENDOR_ATHEROS 0x168c /*Atheros*/ -#define PCI_VENDOR_3COM 0x10b7 /* 3Com */ -#define PCI_VENDOR_3COM2 0xa727 /* 3Com */ - /*Products*/ -#define PCI_PRODUCT_ATHEROS_AR5210 0x0007 /* AR5210 */ -#define PCI_PRODUCT_ATHEROS_AR5311 0x0011 /* AR5311 */ -#define PCI_PRODUCT_ATHEROS_AR5211 0x0012 /* AR5211 */ -#define PCI_PRODUCT_ATHEROS_AR5212 0x0013 /* AR5212 */ -#define PCI_PRODUCT_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ -#define PCI_PRODUCT_3COM2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ -#define PCI_PRODUCT_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ -#define PCI_PRODUCT_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ -#define PCI_PRODUCT_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ -#define PCI_PRODUCT_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ -#define PCI_PRODUCT_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ -#define PCI_PRODUCT_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ -#define PCI_PRODUCT_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ -#define PCI_PRODUCT_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ -#define PCI_PRODUCT_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ -#define PCI_PRODUCT_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -#define PCI_PRODUCT_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ -#define PCI_PRODUCT_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ -#define PCI_PRODUCT_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ -#define PCI_PRODUCT_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ -#define PCI_PRODUCT_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ -#define PCI_PRODUCT_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ -#define PCI_PRODUCT_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ -#define PCI_PRODUCT_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ -#define PCI_PRODUCT_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ -#define PCI_PRODUCT_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ +#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ +#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ +#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ +#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ +#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ +#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ +#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ -#define AR5K_DEVID_AR2413 PCI_PRODUCT_ATHEROS_AR2413 -#define AR5K_DEVID_AR5413 PCI_PRODUCT_ATHEROS_AR5413 -#define AR5K_DEVID_AR5424 PCI_PRODUCT_ATHEROS_AR5424 +#define AR5K_DEVID_AR2413 PCI_DEVICE_ID_ATHEROS_AR2413 +#define AR5K_DEVID_AR5413 PCI_DEVICE_ID_ATHEROS_AR5413 +#define AR5K_DEVID_AR5424 PCI_DEVICE_ID_ATHEROS_AR5424 /*Combatibility with MadWiFi's definitions (bimary HAL)*/ @@ -50,36 +45,36 @@ #define ATHEROS_3COM2_VENDOR_ID PCI_VENDOR_3COM /* 3Com 3CRDAG675 vendor ID */ /* AR5210 (for reference) */ -#define AR5210_DEFAULT PCI_PRODUCT_ATHEROS_AR5210_DEFAULT /* No eeprom HW default */ -#define AR5210_PROD PCI_PRODUCT_ATHEROS_AR5210 /* Final device ID */ -#define AR5210_AP PCI_PRODUCT_ATHEROS_AR5210_AP /* Early AP11s */ +#define AR5210_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT /* No eeprom HW default */ +#define AR5210_PROD PCI_DEVICE_ID_ATHEROS_AR5210 /* Final device ID */ +#define AR5210_AP PCI_DEVICE_ID_ATHEROS_AR5210_AP /* Early AP11s */ /* AR5211 */ -#define AR5211_DEFAULT PCI_PRODUCT_ATHEROS_AR5211_DEFAULT /* No eeprom HW default */ -#define AR5311_DEVID PCI_PRODUCT_ATHEROS_AR5311 /* Final ar5311 devid */ -#define AR5211_DEVID PCI_PRODUCT_ATHEROS_AR5211 /* Final ar5211 devid */ -#define AR5211_LEGACY PCI_PRODUCT_ATHEROS_AR5211_LEGACY /* Original emulation board */ -#define AR5211_FPGA11B PCI_PRODUCT_ATHEROS_AR5211_FPGA11B /* 11b emulation board */ +#define AR5211_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT /* No eeprom HW default */ +#define AR5311_DEVID PCI_DEVICE_ID_ATHEROS_AR5311 /* Final ar5311 devid */ +#define AR5211_DEVID PCI_DEVICE_ID_ATHEROS_AR5211 /* Final ar5211 devid */ +#define AR5211_LEGACY PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY /* Original emulation board */ +#define AR5211_FPGA11B PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B /* 11b emulation board */ /* AR5212 */ -#define AR5212_DEFAULT PCI_PRODUCT_ATHEROS_AR5212_DEFAULT /* No eeprom HW default */ -#define AR5212_DEVID PCI_PRODUCT_ATHEROS_AR5212 /* Final ar5212 devid */ -#define AR5212_FPGA PCI_PRODUCT_ATHEROS_AR5212_FPGA /* Emulation board */ -#define AR5212_DEVID_IBM PCI_PRODUCT_ATHEROS_AR5212_IBM /* IBM minipci ID */ -#define AR5212_AR5312_REV2 PCI_PRODUCT_ATHEROS_AR5212_REV2 /* AR5312 WMAC (AP31) */ -#define AR5212_AR5312_REV7 PCI_PRODUCT_ATHEROS_AR5212_REV7 /* AR5312 WMAC (AP30-040) */ -#define AR5212_AR2313_REV8 PCI_PRODUCT_ATHEROS_AR5212_REV8 /* AR2313 WMAC (AP43-030) */ +#define AR5212_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT /* No eeprom HW default */ +#define AR5212_DEVID PCI_DEVICE_ID_ATHEROS_AR5212 /* Final ar5212 devid */ +#define AR5212_FPGA PCI_DEVICE_ID_ATHEROS_AR5212_FPGA /* Emulation board */ +#define AR5212_DEVID_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM /* IBM minipci ID */ +#define AR5212_AR5312_REV2 PCI_DEVICE_ID_ATHEROS_AR5212_REV2 /* AR5312 WMAC (AP31) */ +#define AR5212_AR5312_REV7 PCI_DEVICE_ID_ATHEROS_AR5212_REV7 /* AR5312 WMAC (AP30-040) */ +#define AR5212_AR2313_REV8 PCI_DEVICE_ID_ATHEROS_AR5212_REV8 /* AR2313 WMAC (AP43-030) */ /* AR5212 compatible devid's also attach to 5212 */ -#define AR5212_DEVID_0014 PCI_PRODUCT_ATHEROS_AR5212_0014 -#define AR5212_DEVID_0015 PCI_PRODUCT_ATHEROS_AR5212_0015 -#define AR5212_DEVID_0016 PCI_PRODUCT_ATHEROS_AR5212_0016 -#define AR5212_DEVID_0017 PCI_PRODUCT_ATHEROS_AR5212_0017 -#define AR5212_DEVID_0018 PCI_PRODUCT_ATHEROS_AR5212_0018 -#define AR5212_DEVID_0019 PCI_PRODUCT_ATHEROS_AR5212_0019 -#define AR5212_AR2413 PCI_PRODUCT_ATHEROS_AR2413 /* AR2413 aka Griffin-lite */ -#define AR5212_AR5413 PCI_PRODUCT_ATHEROS_AR5413 /* Eagle */ -#define AR5212_AR5424 PCI_PRODUCT_ATHEROS_AR5424 /* Condor (PCI express) */ +#define AR5212_DEVID_0014 PCI_DEVICE_ID_ATHEROS_AR5212_0014 +#define AR5212_DEVID_0015 PCI_DEVICE_ID_ATHEROS_AR5212_0015 +#define AR5212_DEVID_0016 PCI_DEVICE_ID_ATHEROS_AR5212_0016 +#define AR5212_DEVID_0017 PCI_DEVICE_ID_ATHEROS_AR5212_0017 +#define AR5212_DEVID_0018 PCI_DEVICE_ID_ATHEROS_AR5212_0018 +#define AR5212_DEVID_0019 PCI_DEVICE_ID_ATHEROS_AR5212_0019 +#define AR5212_AR2413 PCI_DEVICE_ID_ATHEROS_AR2413 /* AR2413 aka Griffin-lite */ +#define AR5212_AR5413 PCI_DEVICE_ID_ATHEROS_AR5413 /* Eagle */ +#define AR5212_AR5424 PCI_DEVICE_ID_ATHEROS_AR5424 /* Condor (PCI express) */ /*Not-supported by OpenHAL*/ /* AR5213 */ commit 730d44a43179f9510e5f17822ce623cddd8f1b06 Author: Jiri Slaby Date: Sun Jun 17 14:12:41 2007 +0200 fix ids in ath5k_hw diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 17814ca..85f4e88 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -22,6 +22,8 @@ * (Please have a look at ar5xxx.h for further information) */ +#include + #include #include "ah_devid.h" @@ -40,32 +42,32 @@ static const struct { /* * From pcidevs_data.h */ - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210, AR5K_AR5210}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP, AR5K_AR5210}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT, AR5K_AR5210}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211, AR5K_AR5211}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT, AR5K_AR5211}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5311, AR5K_AR5211}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_FPGA11B, AR5K_AR5211}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY, AR5K_AR5211}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_IBM, AR5K_AR5212}, - { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675, AR5K_AR5212}, - { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_REV2, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_REV7, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_REV8, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0014, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0015, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0016, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0017, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0018, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0019, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413, AR5K_AR5212}, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210, AR5K_AR5210}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210_AP, AR5K_AR5210}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT, AR5K_AR5210}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211, AR5K_AR5211}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT, AR5K_AR5211}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5311, AR5K_AR5211}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B, AR5K_AR5211}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY, AR5K_AR5211}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_FPGA, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_IBM, AR5K_AR5212}, + { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CRDAG675, AR5K_AR5212}, + { PCI_VENDOR_ID_3COM_2, PCI_DEVICE_ID_3COM_2_3CRPAG175, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV2, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV7, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV8, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0014, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0015, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0016, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0017, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0018, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0019, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR2413, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5413, AR5K_AR5212}, + { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5424, AR5K_AR5212}, }; /*Rate tables*/ @@ -418,9 +420,9 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, AR5K_STATUS *status) hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; switch (device) { - case PCI_PRODUCT_ATHEROS_AR2413: - case PCI_PRODUCT_ATHEROS_AR5413: - case PCI_PRODUCT_ATHEROS_AR5424: + case PCI_DEVICE_ID_ATHEROS_AR2413: + case PCI_DEVICE_ID_ATHEROS_AR5413: + case PCI_DEVICE_ID_ATHEROS_AR5424: /* * Known single chip solutions */ commit caf93d3ffbdc75dbd3dd32712b4749458b4149ea Author: Jiri Slaby Date: Sun Jun 17 14:54:42 2007 +0200 get rid of typedefs, blaah diff --git a/ath/if_ath.c b/ath/if_ath.c index 0a76149..a2f282e 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -181,7 +181,7 @@ static void ath_setup_stationkey(struct ieee80211_node *); static void ath_newassoc(struct ieee80211_node *, int); #endif static int ath_getchannels(struct net_device *, u_int cc, - AR5K_BOOL outdoor, AR5K_BOOL xchanmode); + bool outdoor, bool xchanmode); #ifdef BLE static void ath_led_event(struct ath_softc *, int); #endif @@ -305,29 +305,29 @@ enum { P80211ENUM_truth_true = 0x01 }; -typedef struct { - u_int32_t did; - u_int16_t status; - u_int16_t len; - u_int32_t data; -} p80211item_uint32_t; +struct p80211item_u32 { + u32 did; + u16 status; + u16 len; + u32 data; +}; -typedef struct { - u_int32_t msgcode; - u_int32_t msglen; +struct wlan_ng_prism2_header { + u32 msgcode; + u32 msglen; #define WLAN_DEVNAMELEN_MAX 16 - u_int8_t devname[WLAN_DEVNAMELEN_MAX]; - p80211item_uint32_t hosttime; - p80211item_uint32_t mactime; - p80211item_uint32_t channel; - p80211item_uint32_t rssi; - p80211item_uint32_t sq; - p80211item_uint32_t signal; - p80211item_uint32_t noise; - p80211item_uint32_t rate; - p80211item_uint32_t istx; - p80211item_uint32_t frmlen; -} wlan_ng_prism2_header; + u8 devname[WLAN_DEVNAMELEN_MAX]; + struct p80211item_u32 hosttime; + struct p80211item_u32 mactime; + struct p80211item_u32 channel; + struct p80211item_u32 rssi; + struct p80211item_u32 sq; + struct p80211item_u32 signal; + struct p80211item_u32 noise; + struct p80211item_u32 rate; + struct p80211item_u32 istx; + struct p80211item_u32 frmlen; +}; int ath_attach(u_int16_t devid, struct net_device *dev) @@ -335,7 +335,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) struct ath_softc *sc = dev->priv; // struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah; - AR5K_STATUS status; + enum ath5k_status status; int error = 0, i; u_int8_t csz; @@ -831,7 +831,7 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs) struct net_device *dev = dev_id; struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - AR5K_INT status; + enum ath5k_int status; int needmark; if (sc->sc_invalid) { @@ -1044,7 +1044,7 @@ ath_init(struct net_device *dev) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - AR5K_STATUS status; + enum ath5k_status status; int error = 0; ATH_LOCK(sc); @@ -1252,7 +1252,7 @@ ath_reset(struct net_device *dev) struct ath_softc *sc = dev->priv; // struct ath_hal *ah = sc->sc_ah; // struct ieee80211_channel *c; -// AR5K_STATUS status; +// enum ath5k_status status; // int opmode; DPRINTF(sc, ATH_DEBUG_RESET, "%s: resetting\n", dev->name); @@ -1395,7 +1395,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) u_int flags = 0; struct ieee80211_frame *wh; struct ath_desc *ds; - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; uint8_t testmac[ETH_ALEN]; if ((sc->sc_dev.flags & IFF_RUNNING) == 0 || sc->sc_invalid) { @@ -2430,7 +2430,7 @@ ath_updateslot(struct net_device *dev) static int ath_beaconq_setup(struct ath_hal *ah) { - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; memset(&qi, 0, sizeof(qi)); qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; @@ -2450,7 +2450,7 @@ ath_beaconq_config(struct ath_softc *sc) #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) // struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah = sc->sc_ah; - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); if (sc->sc_opmode == IEEE80211_IF_TYPE_AP) { @@ -3169,9 +3169,9 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) int headroom_needed = 0; if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { - headroom_needed = sizeof(wlan_ng_prism2_header); + headroom_needed = sizeof(struct wlan_ng_prism2_header); } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_PRISM) { - headroom_needed = sizeof(wlan_ng_prism2_header); + headroom_needed = sizeof(struct wlan_ng_prism2_header); } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_RADIOTAP) { headroom_needed = sizeof(struct ath_rx_radiotap_header); } @@ -3684,7 +3684,7 @@ ath_rx_tasklet(TQUEUE_ARG data) // struct ath_node *an; int len;//, type; u_int phyerr; - AR5K_STATUS status; + enum ath5k_status status; DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s\n", __func__); do { @@ -4005,7 +4005,7 @@ ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) { #define N(a) (sizeof(a)/sizeof(a[0])) struct ath_hal *ah = sc->sc_ah; - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; int qnum; memset(&qi, 0, sizeof(qi)); @@ -4095,7 +4095,7 @@ ath_txq_update(struct ath_softc *sc, int ac) struct ath_txq *txq = sc->sc_ac2q[ac]; // struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; struct ath_hal *ah = sc->sc_ah; - AR5K_TXQ_INFO qi; + struct ath5k_txq_info qi; ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); qi.tqi_aifs = wmep->wmep_aifsn; @@ -4181,8 +4181,8 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * struct ieee80211_frame *wh; u_int subtype, flags, ctsduration; AR5K_PKT_TYPE atype; - const AR5K_RATE_TABLE *rt; - AR5K_BOOL short_preamble; + const struct ath5k_rate_table *rt; + bool short_preamble; struct ath_node *an; struct llc *llc; int eapol; @@ -4653,7 +4653,7 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) // struct ieee80211_node *ni; // struct ath_node *an; // int sr, lr, pri; - AR5K_STATUS status; + enum ath5k_status status; DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", __func__, txq->axq_qnum, @@ -4980,7 +4980,7 @@ ath_stoprecv(struct ath_softc *sc) #ifdef BLE STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { struct ath_desc *ds = bf->bf_desc; - AR5K_STATUS status = ath_hal_rxprocdesc(ah, ds, + enum ath5k_status status = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, PA2DESC(sc, ds->ds_link)); if (status == AR5K_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) ath_printrxbuf(bf, status == AR5K_OK); @@ -5090,7 +5090,7 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) { struct ath_hal *ah = sc->sc_ah; - AR5K_CHANNEL hchan; + struct ath5k_channel hchan; /* * Convert to a HAL channel description with @@ -5113,7 +5113,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) ath_hal_mhz2ieee(hchan.freq, hchan.channel_flags), hchan.freq); if (hchan.freq != sc->sc_curchan.freq || hchan.channel_flags != sc->sc_curchan.channel_flags) { - AR5K_STATUS status; + enum ath5k_status status; /* * To switch channels clear any pending DMA operations; @@ -5410,15 +5410,15 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) #endif static int ath_getchannels(struct net_device *dev, u_int cc, - AR5K_BOOL outdoor, AR5K_BOOL xchanmode) + bool outdoor, bool xchanmode) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - AR5K_CHANNEL *chans; + struct ath5k_channel *chans; int i, ix; u_int nchan; #define IEEE80211_CHAN_MAX 255 - chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(AR5K_CHANNEL), GFP_KERNEL); + chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(struct ath5k_channel), GFP_KERNEL); if (chans == NULL) { printk(KERN_ERR "unable to allocate channel table\n"); return ENOMEM; @@ -5439,7 +5439,7 @@ ath_getchannels(struct net_device *dev, u_int cc, * them in the table according to their channel number. */ for (i = 0; i < nchan; i++) { - AR5K_CHANNEL *c = &chans[i]; + struct ath5k_channel *c = &chans[i]; ix = ath_hal_mhz2ieee(c->freq, c->channel_flags); if (ix > IEEE80211_CHAN_MAX) { printk(KERN_ERR "bad hal channel %u (%u/%x) ignored\n", @@ -5544,7 +5544,7 @@ ath_rate_setup(struct net_device *dev, u_int mode) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; // struct ieee80211_rateset *rs; // int i, maxrates; @@ -5615,7 +5615,7 @@ ath_setcurmode(struct ath_softc *sc, unsigned int mode) { 0, 500, 130 }, }; #endif - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; // int i, j; memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 16edb96..8d61385 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -156,10 +156,10 @@ struct ath_node { #ifdef BLE struct ieee80211_node an_node; /* base class */ #endif - u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ - u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */ - u_int32_t an_avgrssi; /* average rssi over all rx frames */ - AR5K_NODE_STATS an_halstats; /* rssi statistics used by hal */ + u8 an_tx_mgtrate; /* h/w rate for management/ctl frames */ + u8 an_tx_mgtratesp;/* short preamble h/w rate for " " */ + u32 an_avgrssi; /* average rssi over all rx frames */ + struct ath5k_node_stats an_halstats; /* rssi statistics used by hal */ /* variable-length rate control state follows */ }; #define ATH_NODE(ni) ((struct ath_node *)(ni)) @@ -205,7 +205,7 @@ struct ath_txq { u_int axq_qnum; /* hardware q number */ u_int axq_depth; /* queue depth (stat only) */ u_int axq_intrcnt; /* interrupt count */ - u_int32_t *axq_link; /* link ptr in last TX desc */ + u32 *axq_link; /* link ptr in last TX desc */ struct list_head axq_q; /* transmit queue */ spinlock_t axq_lock; /* lock on q and link */ /* @@ -260,7 +260,7 @@ struct ath_softc { void (*sc_recv_mgmt)(struct ieee80211com *, struct sk_buff *, struct ieee80211_node *, - int, int, u_int32_t); + int, int, u32); int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); void (*sc_node_free)(struct ieee80211_node *); @@ -268,7 +268,7 @@ struct ath_softc { void *sc_bdev; /* associated bus device */ struct ath_desc *sc_desc; /* TX/RX descriptors */ size_t sc_desc_len; /* size of TX/RX descriptors */ - u_int16_t sc_cachelsz; /* cache line size */ + u16 sc_cachelsz; /* cache line size */ dma_addr_t sc_desc_daddr; /* DMA (physical) address */ struct ath_hal *sc_ah; /* Atheros HAL */ struct ath_ratectrl *sc_rc; /* tx rate control support */ @@ -288,25 +288,25 @@ struct ath_softc { sc_hasclrkey:1, /* CLR key supported */ sc_rawdev_enabled : 1; /* enable sc_rawdev */ /* rate tables */ - const AR5K_RATE_TABLE *sc_rates[NUM_IEEE80211_MODES]; - const AR5K_RATE_TABLE *sc_currates; /* current rate table */ + const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; + const struct ath5k_rate_table *sc_currates; /* current rate table */ unsigned int sc_curmode; /* current phy mode */ - u_int16_t sc_curtxpow; /* current tx power limit */ - AR5K_CHANNEL sc_curchan; /* current h/w channel */ - u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ + u16 sc_curtxpow; /* current tx power limit */ + struct ath5k_channel sc_curchan; /* current h/w channel */ + u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ struct { - u_int8_t ieeerate; /* IEEE rate */ - u_int8_t rxflags; /* radiotap rx flags */ - u_int8_t txflags; /* radiotap tx flags */ - u_int16_t ledon; /* softled on time */ - u_int16_t ledoff; /* softled off time */ + u8 ieeerate; /* IEEE rate */ + u8 rxflags; /* radiotap rx flags */ + u8 txflags; /* radiotap tx flags */ + u16 ledon; /* softled on time */ + u16 ledoff; /* softled off time */ } sc_hwmap[32]; /* h/w rate ix mappings */ - u_int8_t sc_protrix; /* protection rate index */ + u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ - AR5K_INT sc_imask; /* interrupt mask copy */ + enum ath5k_int sc_imask; /* interrupt mask copy */ u_int sc_keymax; /* size of key cache */ #ifdef BLE - u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ + u8 sc_keymap[ATH_KEYBYTES];/* key use bit map */ struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ #endif @@ -314,20 +314,20 @@ struct ath_softc { u_int sc_ledon; /* pin setting for LED on */ u_int sc_ledidle; /* idle polling interval */ int sc_ledevent; /* time of last LED event */ - u_int8_t sc_rxrate; /* current rx rate for LED */ - u_int8_t sc_txrate; /* current tx rate for LED */ - u_int16_t sc_ledoff; /* off time for current blink */ + u8 sc_rxrate; /* current rx rate for LED */ + u8 sc_txrate; /* current tx rate for LED */ + u16 sc_ledoff; /* off time for current blink */ struct timer_list sc_ledtimer; /* led off timer */ - u_int32_t sc_rxfilter; + u32 sc_rxfilter; union { struct ath_tx_radiotap_header th; - u_int8_t pad[64]; + u8 pad[64]; } u_tx_rt; int sc_tx_th_len; union { struct ath_rx_radiotap_header th; - u_int8_t pad[64]; + u8 pad[64]; } u_rx_rt; int sc_rx_th_len; @@ -336,11 +336,11 @@ struct ath_softc { int sc_rxbufsize; /* rx size based on mtu */ struct list_head *sc_rxbuf; /* receive buffer */ - u_int32_t *sc_rxlink; /* link ptr in last RX desc */ + u32 *sc_rxlink; /* link ptr in last RX desc */ struct tq_struct sc_rxtq; /* rx intr tasklet */ struct tq_struct sc_rxorntq; /* rxorn intr tasklet */ - u_int8_t sc_defant; /* current default antenna */ - u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ + u8 sc_defant; /* current default antenna */ + u8 sc_rxotherant; /* rx's on non-default antenna*/ struct list_head *sc_txbuf; /* transmit buffer */ spinlock_t sc_txbuflock; /* txbuf lock */ @@ -354,7 +354,7 @@ struct ath_softc { struct list_head *sc_bbuf; /* beacon buffers */ u_int sc_bhalq; /* HAL q for outgoing beacons */ u_int sc_bmisscount; /* missed beacon transmits */ - u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ + u32 sc_ant_tx[8]; /* recent tx frames/antenna */ struct ath_txq *sc_cabq; /* tx q for cab frames */ struct ath_buf *sc_bufptr; /* allocated buffer ptr */ #ifdef BLE @@ -394,7 +394,7 @@ struct ath_softc { #define ATH_TXBUF_LOCK_ASSERT(_sc) \ KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), ("txbuf not locked!")) -int ath_attach(u_int16_t, struct net_device *); +int ath_attach(u16, struct net_device *); int ath_detach(struct net_device *); void ath_resume(struct net_device *); void ath_suspend(struct net_device *); @@ -407,7 +407,7 @@ irqreturn_t ath_intr(int, void *); #else irqreturn_t ath_intr(int, void *, struct pt_regs *regs); #endif -void bus_read_cachesize(struct ath_softc *, u_int8_t *); +void bus_read_cachesize(struct ath_softc *, u8 *); int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); void ath_sysctl_unregister(void); diff --git a/openhal/ah_osdep.c b/openhal/ah_osdep.c index d2a14be..9f1a7c4 100644 --- a/openhal/ah_osdep.c +++ b/openhal/ah_osdep.c @@ -16,7 +16,7 @@ static char dev_info[] = "ath_hal"; struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, - AR5K_STATUS *s) + enum ath5k_status *s) { struct ath_hal *ah = ath5k_hw_init(devid, sc, h, s); diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 7b62b51..8bf0bb3 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -68,12 +68,11 @@ #ifndef FALSE #define FALSE 0 #endif -typedef u_int8_t AR5K_BOOL; /* * Error codes reported from HAL to the driver */ -typedef enum { +enum ath5k_status { AR5K_OK = 0, /* Everything went O.K.*/ AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/ AR5K_EIO = 2, /* Hardware I/O Error*/ @@ -84,7 +83,7 @@ typedef enum { AR5K_EINVAL = 7, /* Invalid parameter to function */ AR5K_ENOTSUPP = 8, /* Hardware revision not supported */ AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */ -} AR5K_STATUS; +}; /* * Some tuneable values (these should be changeable by the user) @@ -116,7 +115,7 @@ typedef enum { #define AR5K_TUNE_HWTXTRIES 4 /* token to use for aifs, cwmin, cwmax in MadWiFi */ -#define AR5K_TXQ_USEDEFAULT ((u_int32_t) -1) +#define AR5K_TXQ_USEDEFAULT ((u32) -1) /* GENERIC CHIPSET DEFINITIONS */ @@ -211,14 +210,6 @@ struct ath5k_srev_name { #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) #define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 -/*typedef enum { - AR5K_M_STA = IEEE80211_IF_TYPE_STA, - AR5K_M_IBSS = IEEE80211_IF_TYPE_IBSS, - AR5K_M_HOSTAP = IEEE80211_IF_TYPE_AP, - AR5K_M_MONITOR = IEEE80211_IF_TYPE_MNTR, -} AR5K_OPMODE;*/ - - /****************\ TX DEFINITIONS \****************/ @@ -227,15 +218,15 @@ struct ath5k_srev_name { * Tx Descriptor */ struct ath_tx_status { - u_int16_t ts_seqnum; - u_int16_t ts_tstamp; - u_int8_t ts_status; - u_int8_t ts_rate; + u16 ts_seqnum; + u16 ts_tstamp; + u8 ts_status; + u8 ts_rate; int8_t ts_rssi; - u_int8_t ts_shortretry; - u_int8_t ts_longretry; - u_int8_t ts_virtcol; - u_int8_t ts_antenna; + u8 ts_shortretry; + u8 ts_longretry; + u8 ts_virtcol; + u8 ts_antenna; }; #define AR5K_TXSTAT_ALTRATE 0x80 @@ -246,14 +237,14 @@ struct ath_tx_status { /* * Queue types used to classify tx queues. */ -typedef enum { +enum ath5k_tx_queue { AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ AR5K_TX_QUEUE_DATA, /*A normal data queue*/ AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ -} AR5K_TX_QUEUE; +}; #define AR5K_NUM_TX_QUEUES 10 #define AR5K_NUM_TX_QUEUES_NOQCU 2 @@ -265,12 +256,12 @@ typedef enum { * highest. Normal data that hasn't been classified * goes to the Best Effort AC. */ -typedef enum { +enum ath5k_tx_queue_subtype { AR5K_WME_AC_BK = 0, /*Background traffic*/ AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ AR5K_WME_AC_VI, /*Video traffic*/ AR5K_WME_AC_VO, /*Voice traffic*/ -} AR5K_TX_QUEUE_SUBTYPE; +}; /* * Queue ID numbers as returned by the HAL, each number @@ -278,7 +269,7 @@ typedef enum { * (eg 5210) all data goes in one queue. These match * d80211 definitions (net80211/MadWiFi don't use them). */ -typedef enum { +enum ath5k_tx_queue_id { AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ @@ -288,7 +279,7 @@ typedef enum { AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ AR5K_TX_QUEUE_ID_UAPSD = 8, AR5K_TX_QUEUE_ID_XR_DATA = 9, -} AR5K_TX_QUEUE_ID; +}; /* @@ -306,32 +297,32 @@ typedef enum { /* * A struct to hold tx queue's parameters */ -typedef struct { - AR5K_TX_QUEUE tqi_type; /* See AR5K_TX_QUEUE */ - AR5K_TX_QUEUE_SUBTYPE tqi_subtype; /* See AR5K_TX_QUEUE_SUBTYPE */ - u_int16_t tqi_flags; /* Tx queue flags (see above) */ - u_int32_t tqi_aifs; /* Arbitrated Interframe Space */ - int32_t tqi_cw_min; /* Minimum Contention Window */ - int32_t tqi_cw_max; /* Maximum Contention Window */ - u_int32_t tqi_cbr_period; /* Constant bit rate period */ - u_int32_t tqi_cbr_overflow_limit; - u_int32_t tqi_burst_time; - u_int32_t tqi_ready_time; /* Not used */ - u_int32_t tqi_comp_buffer;/* Compression Buffer's phys addr */ -} AR5K_TXQ_INFO; +struct ath5k_txq_info { + enum ath5k_tx_queue tqi_type; + enum ath5k_tx_queue_subtype tqi_subtype; + u16 tqi_flags; /* Tx queue flags (see above) */ + u32 tqi_aifs; /* Arbitrated Interframe Space */ + s32 tqi_cw_min; /* Minimum Contention Window */ + s32 tqi_cw_max; /* Maximum Contention Window */ + u32 tqi_cbr_period; /* Constant bit rate period */ + u32 tqi_cbr_overflow_limit; + u32 tqi_burst_time; + u32 tqi_ready_time; /* Not used */ + u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ +}; /* * Transmit packet types. * These are not fully used inside OpenHAL yet */ -typedef enum { +enum ath5k_pkt_type { AR5K_PKT_TYPE_NORMAL = 0, AR5K_PKT_TYPE_ATIM = 1, AR5K_PKT_TYPE_PSPOLL = 2, AR5K_PKT_TYPE_BEACON = 3, AR5K_PKT_TYPE_PROBE_RESP = 4, AR5K_PKT_TYPE_PIFS = 5, -} AR5K_PKT_TYPE; +}; /* * TX power and TPC settings @@ -427,7 +418,7 @@ typedef enum { /* * DMA size definitions (2^n+2) */ -typedef enum { +enum ath5k_dmasize { AR5K_DMASIZE_4B = 0, AR5K_DMASIZE_8B, AR5K_DMASIZE_16B, @@ -436,7 +427,7 @@ typedef enum { AR5K_DMASIZE_128B, AR5K_DMASIZE_256B, AR5K_DMASIZE_512B -} ath5k_dmasize_t; +}; @@ -448,15 +439,15 @@ typedef enum { * Rx Descriptor */ struct ath_rx_status { - u_int16_t rs_datalen; - u_int16_t rs_tstamp; - u_int8_t rs_status; - u_int8_t rs_phyerr; + u16 rs_datalen; + u16 rs_tstamp; + u8 rs_status; + u8 rs_phyerr; int8_t rs_rssi; - u_int8_t rs_keyix; - u_int8_t rs_rate; - u_int8_t rs_antenna; - u_int8_t rs_more; + u8 rs_keyix; + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; }; #define AR5K_RXERR_CRC 0x01 @@ -464,8 +455,8 @@ struct ath_rx_status { #define AR5K_RXERR_FIFO 0x04 #define AR5K_RXERR_DECRYPT 0x08 #define AR5K_RXERR_MIC 0x10 -#define AR5K_RXKEYIX_INVALID ((u_int8_t) - 1) -#define AR5K_TXKEYIX_INVALID ((u_int32_t) - 1) +#define AR5K_RXKEYIX_INVALID ((u8) - 1) +#define AR5K_TXKEYIX_INVALID ((u32) - 1) /* * RX filters @@ -482,13 +473,13 @@ struct ath_rx_status { #define AR5K_RX_FILTER_PHYERROR 0x00000100 /* Don't filter phy errors */ #define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ -typedef struct { - u_int32_t ackrcv_bad; - u_int32_t rts_bad; - u_int32_t rts_good; - u_int32_t fcs_bad; - u_int32_t beacons; -} AR5K_MIB_STATS; +struct ath5k_mib_stats { + u32 ackrcv_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 beacons; +}; @@ -504,21 +495,21 @@ typedef struct { /* * Per-station beacon timer state. */ -typedef struct { - u_int32_t bs_next_beacon; - u_int32_t bs_next_dtim; - u_int32_t bs_interval; /*in TU's -see net80211/ieee80211_var.h- +struct ath5k_beacon_state { + u32 bs_next_beacon; + u32 bs_next_dtim; + u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- can also include the above flags*/ - u_int8_t bs_dtim_period; - u_int8_t bs_cfp_period; - u_int16_t bs_cfp_max_duration; /*if non-zero hw is setup to coexist with + u8 bs_dtim_period; + u8 bs_cfp_period; + u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with a Point Coordination Function capable AP*/ - u_int16_t bs_cfp_du_remain; - u_int16_t bs_tim_offset; - u_int16_t bs_sleep_duration; - u_int16_t bs_bmiss_threshold; - u_int32_t bs_cfp_next; -} AR5K_BEACON_STATE; + u16 bs_cfp_du_remain; + u16 bs_tim_offset; + u16 bs_sleep_duration; + u16 bs_bmiss_threshold; + u32 bs_cfp_next; +}; @@ -531,11 +522,11 @@ typedef struct { * Atheros descriptor */ struct ath_desc { - u_int32_t ds_link; - u_int32_t ds_data; - u_int32_t ds_ctl0; - u_int32_t ds_ctl1; - u_int32_t ds_hw[4]; + u32 ds_link; + u32 ds_data; + u32 ds_ctl0; + u32 ds_ctl1; + u32 ds_hw[4]; union { struct ath_rx_status rx; @@ -575,11 +566,11 @@ struct ath_desc { /* * Channel definitions */ -typedef struct { - u_int16_t freq; /* setting in Mhz */ - u_int16_t channel_flags; - u_int8_t private_flags; /* not used in OpenHAL yet*/ -} AR5K_CHANNEL; +struct ath5k_channel { + u16 freq; /* setting in Mhz */ + u16 channel_flags; + u8 private_flags; /* not used in OpenHAL yet*/ +}; #define AR5K_SLOT_TIME_9 396 #define AR5K_SLOT_TIME_20 880 @@ -613,7 +604,7 @@ typedef struct { /* * Used internaly in OpenHAL (ar5211.c/ar5212.c - * for reset_tx_queue). Also see struct AR5K_CHANNEL. + * for reset_tx_queue). Also see struct struct ath5k_channel. */ #define IS_CHAN_XR(_c) \ ((_c.channel_flags & CHANNEL_XR) != 0) @@ -621,18 +612,18 @@ typedef struct { #define IS_CHAN_B(_c) \ ((_c.channel_flags & CHANNEL_B) != 0) -typedef enum { +enum ath5k_chip{ AR5K_CHIP_5GHZ = CHANNEL_5GHZ, AR5K_CHIP_2GHZ = CHANNEL_2GHZ, -} AR5K_CHIP; +}; /* * The following structure will be used to map 2GHz channels to * 5GHz Atheros channels. */ struct ath5k_athchan_2ghz { - u_int32_t a2_flags; - u_int16_t a2_athchan; + u32 a2_flags; + u16 a2_athchan; }; /* @@ -641,22 +632,22 @@ struct ath5k_athchan_2ghz { #define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ -typedef struct { - u_int8_t valid; /* Valid for rate control */ - u_int32_t modulation; - u_int16_t rate_kbps; - u_int8_t rate_code; /* Rate mapping for h/w descriptors */ - u_int8_t dot11_rate; - u_int8_t control_rate; - u_int16_t lp_ack_duration;/* long preamble ACK duration */ - u_int16_t sp_ack_duration;/* short preamble ACK duration*/ -} AR5K_RATE; - -typedef struct { - u_int16_t rate_count; - u_int8_t rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ - AR5K_RATE rates[AR5K_MAX_RATES]; -} AR5K_RATE_TABLE; +struct ath5k_rate { + u8 valid; /* Valid for rate control */ + u32 modulation; + u16 rate_kbps; + u8 rate_code; /* Rate mapping for h/w descriptors */ + u8 dot11_rate; + u8 control_rate; + u16 lp_ack_duration;/* long preamble ACK duration */ + u16 sp_ack_duration;/* short preamble ACK duration*/ +}; + +struct ath5k_rate_table { + u16 rate_count; + u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ + struct ath5k_rate rates[AR5K_MAX_RATES]; +}; /* * Rate tables... @@ -740,7 +731,7 @@ typedef struct { */ /* key types */ -typedef enum { +enum ath5k_cipher { AR5K_CIPHER_WEP = 0, AR5K_CIPHER_AES_OCB = 1, AR5K_CIPHER_AES_CCM = 2, @@ -749,21 +740,19 @@ typedef enum { AR5K_CIPHER_CLR = 5, /* no encryption */ AR5K_CIPHER_MIC = 127 /* used for Message Integrity Code */ -} AR5K_CIPHER; +}; #define AR5K_KEYVAL_LENGTH_40 5 #define AR5K_KEYVAL_LENGTH_104 13 #define AR5K_KEYVAL_LENGTH_128 16 #define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128 -typedef struct { +struct ath5k_keyval { int wk_len; /* key's length */ - u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX]; - u_int8_t wk_type; /* see above */ - u_int8_t wk_mic[8]; /* TKIP MIC key */ -} AR5K_KEYVAL; - - + u8 wk_key[AR5K_KEYVAL_LENGTH_MAX]; + u8 wk_type; /* see above */ + u8 wk_mic[8]; /* TKIP MIC key */ +}; /***********************\ HW RELATED DEFINITIONS @@ -780,18 +769,18 @@ typedef struct { } while (0) -typedef struct { - u_int32_t ns_avgbrssi; /* average beacon rssi */ - u_int32_t ns_avgrssi; /* average data rssi */ - u_int32_t ns_avgtxrssi; /* average tx rssi */ -} AR5K_NODE_STATS; +struct ath5k_node_stats { + u32 ns_avgbrssi; /* average beacon rssi */ + u32 ns_avgrssi; /* average data rssi */ + u32 ns_avgtxrssi; /* average tx rssi */ +}; -typedef enum { +enum ath5k_ant_setting { AR5K_ANT_VARIABLE = 0, /* variable by programming */ AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ AR5K_ANT_MAX = 3, -} AR5K_ANT_SETTING; +}; /* * HAL interrupt abstraction @@ -802,7 +791,7 @@ typedef enum { * between the MAC chips, to be able to set intr properties * easier. Some of them are not used yet inside OpenHAL. */ -typedef enum { +enum ath5k_int { AR5K_INT_RX = 0x00000001, AR5K_INT_RXDESC = 0x00000002, AR5K_INT_RXNOFRM = 0x00000008, @@ -836,24 +825,18 @@ typedef enum { | AR5K_INT_GPIO, AR5K_INT_NOCARD = 0xffffffff /*Declare that the card has been removed*/ -} AR5K_INT; +}; /* * Power management */ -typedef enum { +enum ath5k_power_mode { AR5K_PM_UNDEFINED = 0, AR5K_PM_AUTO, AR5K_PM_AWAKE, AR5K_PM_FULL_SLEEP, AR5K_PM_NETWORK_SLEEP, -} AR5K_POWER_MODE; - - -/* - * LED states - */ -typedef int AR5K_LED_STATE; +}; /* * These match net80211 definitions (not used in @@ -875,7 +858,7 @@ typedef int AR5K_LED_STATE; * get_capability function is not yet fully implemented * in OpenHAL so most of these don't work yet... */ -typedef enum { +enum ath5k_capability_type { AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ AR5K_CAP_CIPHER = 1, /* Can handle encryption */ AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ @@ -897,23 +880,23 @@ typedef enum { AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ -} AR5K_CAPABILITY_TYPE; +}; -typedef struct { +struct ath5k_capabilities { /* * Supported PHY modes * (ie. CHANNEL_A, CHANNEL_B, ...) */ - u_int16_t cap_mode; + u16 cap_mode; /* * Frequency range (without regulation restrictions) */ struct { - u_int16_t range_2ghz_min; - u_int16_t range_2ghz_max; - u_int16_t range_5ghz_min; - u_int16_t range_5ghz_max; + u16 range_2ghz_min; + u16 range_2ghz_max; + u16 range_5ghz_min; + u16 range_5ghz_max; } cap_range; /* @@ -933,9 +916,9 @@ typedef struct { * Queue information */ struct { - u_int8_t q_tx_num; + u8 q_tx_num; } cap_queues; -} ath5k_capabilities_t; +}; /***************************************\ @@ -945,7 +928,6 @@ typedef struct { /* * Regulation stuff */ -typedef enum ieee80211_countrycode AR5K_CTRY_CODE; /* Default regulation domain if stored value EEPROM value is invalid */ #define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ @@ -959,295 +941,295 @@ typedef enum ieee80211_countrycode AR5K_CTRY_CODE; struct ath_hal; -typedef AR5K_BOOL (ath5k_rfgain_t) - (struct ath_hal *, AR5K_CHANNEL *, u_int); +typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); /* * HAL Functions that have different implementations for each chipset... */ #define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ath5k_##_n##_##_f #define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ - _t const AR5K_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, u_int mode); \ + _t const struct ath5k_rate_table *(_a _n##_get_rate_table)(struct ath_hal *, \ + u_int mode); \ _t void (_a _n##_detach)(struct ath_hal *); \ /* Reset functions */ \ - _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, enum ieee80211_if_types, AR5K_CHANNEL *, \ - AR5K_BOOL change_channel, AR5K_STATUS *status); \ - _t void (_a _n##_set_opmode)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_phy_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ + _t bool (_a _n##_reset)(struct ath_hal *, enum ieee80211_if_types, \ + struct ath5k_channel *, bool change_channel, enum ath5k_status *status);\ + _t void (_a _n##_set_opmode)(struct ath_hal *); \ + _t bool (_a _n##_phy_calibrate)(struct ath_hal*, struct ath5k_channel *); \ /* Transmit functions */ \ - _t AR5K_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, AR5K_BOOL level); \ - _t int (_a _n##_setup_tx_queue)(struct ath_hal *, AR5K_TX_QUEUE, AR5K_TXQ_INFO *); \ - _t AR5K_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ - const AR5K_TXQ_INFO *); \ - _t AR5K_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ - _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u_int32_t phys_addr); \ - _t AR5K_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, \ - u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index,\ - u_int antenna_mode, u_int flags, u_int rtscts_rate, \ - u_int rtscts_duration); \ - _t AR5K_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ - u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ - _t AR5K_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ - AR5K_BOOL firstSeg, AR5K_BOOL lastSeg, const struct ath_desc *);\ - _t AR5K_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ - _t AR5K_BOOL (_a _n##_has_veol)(struct ath_hal *); \ + _t bool (_a _n##_update_tx_triglevel)(struct ath_hal*, bool level); \ + _t int (_a _n##_setup_tx_queue)(struct ath_hal *, enum ath5k_tx_queue, \ + struct ath5k_txq_info *); \ + _t bool (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ + const struct ath5k_txq_info *); \ + _t bool (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ + _t u32 (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u32 phys_addr); \ + _t bool (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ + _t bool (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int packet_length, u_int header_length, enum ath5k_pkt_type type, \ + u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \ + u_int antenna_mode, u_int flags, u_int rtscts_rate, \ + u_int rtscts_duration); \ + _t bool (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ + u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ + _t bool (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ + bool firstSeg, bool lastSeg, const struct ath_desc *); \ + _t enum ath5k_status (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ + _t bool (_a _n##_has_veol)(struct ath_hal *); \ /* Receive Functions */ \ - _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \ - _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \ + _t u32 (_a _n##_get_rx_buf)(struct ath_hal*); \ + _t void (_a _n##_put_rx_buf)(struct ath_hal*, u32 rxdp); \ _t void (_a _n##_start_rx)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \ + _t bool (_a _n##_stop_rx_dma)(struct ath_hal*); \ _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \ _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \ - _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u_int32_t filter0, \ - u_int32_t filter1); \ - _t AR5K_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, u_int32_t index); \ - _t AR5K_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*,u_int32_t index); \ - _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \ - _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \ - _t AR5K_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t size, u_int flags); \ - _t AR5K_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t phyAddr, struct ath_desc *next); \ - _t void (_a _n##_set_rx_signal)(struct ath_hal *, const AR5K_NODE_STATS *); \ + _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u32 filter0, \ + u32 filter1); \ + _t bool (_a _n##_set_mcast_filterindex)(struct ath_hal*, u32 index); \ + _t bool (_a _n##_clear_mcast_filter_idx)(struct ath_hal*, u32 index); \ + _t u32 (_a _n##_get_rx_filter)(struct ath_hal*); \ + _t void (_a _n##_set_rx_filter)(struct ath_hal*, u32); \ + _t bool (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u32 size, u_int flags); \ + _t enum ath5k_status (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u32 phyAddr, struct ath_desc *next); \ + _t void (_a _n##_set_rx_signal)(struct ath_hal *, const struct ath5k_node_stats *); \ /* Misc Functions */ \ - _t void (_a _n##_dump_state)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ - u_int32_t argsize, void **result, u_int32_t *resultsize); \ - _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \ - _t AR5K_BOOL (_a _n##_set_lladdr)(struct ath_hal *, const u_int8_t*); \ - _t AR5K_BOOL (_a _n##_set_regdomain)(struct ath_hal*, u_int16_t, AR5K_STATUS *); \ - _t void (_a _n##_set_ledstate)(struct ath_hal*, AR5K_LED_STATE); \ - _t void (_a _n##_set_associd)(struct ath_hal*, const u_int8_t *bssid, \ - u_int16_t assocId); \ - _t AR5K_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, u_int32_t gpio); \ - _t AR5K_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, u_int32_t gpio); \ - _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \ - _t AR5K_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, u_int32_t val); \ - _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \ - _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \ - _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \ - _t void (_a _n##_reset_tsf)(struct ath_hal*); \ - _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \ - _t void (_a _n##_update_mib_counters)(struct ath_hal*, AR5K_MIB_STATS*); \ - _t AR5K_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \ - _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ - _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \ - _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \ + _t void (_a _n##_dump_state)(struct ath_hal *); \ + _t bool (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ + u32 argsize, void **result, u32 *resultsize); \ + _t void (_a _n##_get_lladdr)(struct ath_hal *, u8 *); \ + _t bool (_a _n##_set_lladdr)(struct ath_hal *, const u8*); \ + _t bool (_a _n##_set_regdomain)(struct ath_hal*, u16, enum ath5k_status *); \ + _t void (_a _n##_set_ledstate)(struct ath_hal*, unsigned int); \ + _t void (_a _n##_set_associd)(struct ath_hal*, const u8 *bssid, \ + u16 assocId); \ + _t bool (_a _n##_set_gpio_input)(struct ath_hal *, u32 gpio); \ + _t bool (_a _n##_set_gpio_output)(struct ath_hal *, u32 gpio); \ + _t u32 (_a _n##_get_gpio)(struct ath_hal *, u32 gpio); \ + _t bool (_a _n##_set_gpio)(struct ath_hal *, u32 gpio, u32 val); \ + _t void (_a _n##_set_gpio_intr)(struct ath_hal *, u_int, u32); \ + _t u32 (_a _n##_get_tsf32)(struct ath_hal *); \ + _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal *); \ + _t void (_a _n##_reset_tsf)(struct ath_hal *); \ + _t u16 (_a _n##_get_regdomain)(struct ath_hal *); \ + _t bool (_a _n##_detect_card_present)(struct ath_hal *); \ + _t void (_a _n##_update_mib_counters)(struct ath_hal *, struct ath5k_mib_stats *); \ + _t enum ath5k_rfgain (_a _n##_get_rf_gain)(struct ath_hal *); \ + _t bool (_a _n##_set_slot_time)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_slot_time)(struct ath_hal *); \ + _t bool (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_ack_timeout)(struct ath_hal *); \ + _t bool (_a _n##_set_cts_timeout)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_cts_timeout)(struct ath_hal *); \ /* Key Cache Functions */ \ - _t AR5K_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, AR5K_CIPHER); \ - _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_reset_key)(struct ath_hal*, u_int16_t); \ - _t AR5K_BOOL (_a _n##_is_key_valid)(struct ath_hal *, u_int16_t); \ - _t AR5K_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, const AR5K_KEYVAL *, \ - const u_int8_t *, int); \ - _t AR5K_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, u_int16_t, const u_int8_t *); \ + _t bool (_a _n##_is_cipher_supported)(struct ath_hal*, enum ath5k_cipher); \ + _t u32 (_a _n##_get_keycache_size)(struct ath_hal*); \ + _t bool (_a _n##_reset_key)(struct ath_hal*, u16); \ + _t bool (_a _n##_is_key_valid)(struct ath_hal *, u16); \ + _t bool (_a _n##_set_key)(struct ath_hal*, u16, const struct ath5k_keyval *, \ + const u8 *, int); \ + _t bool (_a _n##_set_key_lladdr)(struct ath_hal*, u16, const u8 *); \ /* Power Management Functions */ \ - _t AR5K_BOOL (_a _n##_set_power)(struct ath_hal*, AR5K_POWER_MODE mode, \ - AR5K_BOOL set_chip, u_int16_t sleep_duration); \ - _t AR5K_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, u_int16_t); \ - _t AR5K_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \ + _t bool (_a _n##_set_power)(struct ath_hal*, enum ath5k_power_mode mode, \ + bool set_chip, u16 sleep_duration); \ + _t enum ath5k_power_mode (_a _n##_get_power_mode)(struct ath_hal*); \ + _t bool (_a _n##_query_pspoll_support)(struct ath_hal*); \ + _t bool (_a _n##_init_pspoll)(struct ath_hal*); \ + _t bool (_a _n##_enable_pspoll)(struct ath_hal *, u8 *, u16); \ + _t bool (_a _n##_disable_pspoll)(struct ath_hal *); \ /* Beacon Management Functions */ \ - _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, u_int32_t intval); \ - _t void (_a _n##_set_beacon_timers)(struct ath_hal *, const AR5K_BEACON_STATE *); \ + _t void (_a _n##_init_beacon)(struct ath_hal *, u32 nexttbtt, u32 intval); \ + _t void (_a _n##_set_beacon_timers)(struct ath_hal *, \ + const struct ath5k_beacon_state *); \ _t void (_a _n##_reset_beacon)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, unsigned long); \ + _t bool (_a _n##_wait_for_beacon)(struct ath_hal *, unsigned long); \ /* Interrupt functions */ \ - _t AR5K_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_get_isr)(struct ath_hal *, u_int32_t *); \ - _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \ - _t AR5K_INT (_a _n##_set_intr)(struct ath_hal *, AR5K_INT); \ + _t bool (_a _n##_is_intr_pending)(struct ath_hal *); \ + _t bool (_a _n##_get_isr)(struct ath_hal *, u32 *); \ + _t u32 (_a _n##_get_intr)(struct ath_hal *); \ + _t enum ath5k_int (_a _n##_set_intr)(struct ath_hal *, enum ath5k_int); \ /* Chipset functions (ar5k-specific, non-HAL) */ \ - _t AR5K_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \ - _t void (_a _n##_radar_alert)(struct ath_hal *, AR5K_BOOL enable); \ - _t AR5K_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \ - _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, u_int16_t *data); \ - _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, u_int16_t data); \ + _t bool (_a _n##_get_capabilities)(struct ath_hal *); \ + _t void (_a _n##_radar_alert)(struct ath_hal *, bool enable); \ + _t bool (_a _n##_eeprom_is_busy)(struct ath_hal *); \ + _t int (_a _n##_eeprom_read)(struct ath_hal *, u32 offset, u16 *data); \ + _t int (_a _n##_eeprom_write)(struct ath_hal *, u32 offset, u16 data); \ /* Functions not found in OpenBSD */ \ - _t AR5K_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, AR5K_TXQ_INFO *); \ - _t AR5K_STATUS (_a _n##_get_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, \ - u_int32_t, u_int32_t *); \ - _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ - _t AR5K_BOOL (_a _n##_phy_disable)(struct ath_hal *); \ + _t bool (_a _n##_get_tx_queueprops)(struct ath_hal *, int, struct ath5k_txq_info *); \ + _t enum ath5k_status (_a _n##_get_capability)(struct ath_hal *, \ + enum ath5k_capability_type, u32, u32 *); \ + _t u32 (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ + _t bool (_a _n##_phy_disable)(struct ath_hal *); \ _t void (_a _n##_set_pcu_config)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ + _t bool (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \ _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n ##_set_bssid_mask)(struct ath_hal *, const u_int8_t*); \ + _t bool (_a _n ##_set_bssid_mask)(struct ath_hal *, const u8 *); \ /*Totaly unimplemented*/ \ - _t AR5K_BOOL (_a _n##_set_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, u_int32_t,\ - u_int32_t,AR5K_STATUS *) ; \ - _t void (_a _n##_proc_mib_event)(struct ath_hal *, const AR5K_NODE_STATS *) ; \ - _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *); + _t bool (_a _n##_set_capability)(struct ath_hal *, enum ath5k_capability_type, u32, \ + u32,enum ath5k_status *); \ + _t void (_a _n##_proc_mib_event)(struct ath_hal *, const struct ath5k_node_stats *); \ + _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u32 *); #define AR5K_MAX_GPIO 10 #define AR5K_MAX_RF_BANKS 8 struct ath_hal { - u_int32_t ah_magic; - u_int16_t ah_device; - u_int16_t ah_sub_vendor; + u32 ah_magic; + u16 ah_device; + u16 ah_sub_vendor; void *ah_sc; void __iomem *ah_sh; - AR5K_CTRY_CODE ah_country_code; + enum ieee80211_countrycode ah_country_code; - AR5K_INT ah_imr; + enum ath5k_int ah_imr; enum ieee80211_if_types ah_op_mode; - AR5K_POWER_MODE ah_power_mode; - AR5K_CHANNEL ah_current_channel; - AR5K_BOOL ah_turbo; - AR5K_BOOL ah_calibration; - AR5K_BOOL ah_running; - AR5K_BOOL ah_single_chip; - AR5K_RFGAIN ah_rf_gain; - - AR5K_RATE_TABLE ah_rt_11a; - AR5K_RATE_TABLE ah_rt_11b; - AR5K_RATE_TABLE ah_rt_11g; - AR5K_RATE_TABLE ah_rt_turbo; - AR5K_RATE_TABLE ah_rt_xr; - - u_int32_t ah_mac_srev; - u_int16_t ah_mac_version; - u_int16_t ah_mac_revision; - u_int16_t ah_phy_revision; - u_int16_t ah_radio_5ghz_revision; - u_int16_t ah_radio_2ghz_revision; + enum ath5k_power_mode ah_power_mode; + struct ath5k_channel ah_current_channel; + bool ah_turbo; + bool ah_calibration; + bool ah_running; + bool ah_single_chip; + enum ath5k_rfgain ah_rf_gain; + + struct ath5k_rate_table ah_rt_11a; + struct ath5k_rate_table ah_rt_11b; + struct ath5k_rate_table ah_rt_11g; + struct ath5k_rate_table ah_rt_turbo; + struct ath5k_rate_table ah_rt_xr; + + u32 ah_mac_srev; + u16 ah_mac_version; + u16 ah_mac_revision; + u16 ah_phy_revision; + u16 ah_radio_5ghz_revision; + u16 ah_radio_2ghz_revision; enum ath5k_version ah_version; enum ath5k_radio ah_radio; - u_int32_t ah_phy; + u32 ah_phy; - AR5K_BOOL ah_5ghz; - AR5K_BOOL ah_2ghz; + bool ah_5ghz; + bool ah_2ghz; #define ah_regdomain ah_capabilities.cap_regdomain.reg_current -#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw #define ah_modes ah_capabilities.cap_mode #define ah_ee_version ah_capabilities.cap_eeprom.ee_version - u_int32_t ah_atim_window; - u_int32_t ah_aifs; - u_int32_t ah_cw_min; - u_int32_t ah_cw_max; - AR5K_BOOL ah_software_retry; - u_int32_t ah_limit_tx_retries; + u32 ah_atim_window; + u32 ah_aifs; + u32 ah_cw_min; + u32 ah_cw_max; + bool ah_software_retry; + u32 ah_limit_tx_retries; - u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; - AR5K_BOOL ah_ant_diversity; + u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + bool ah_ant_diversity; - u_int8_t ah_sta_id[ETH_ALEN]; - u_int8_t ah_bssid[ETH_ALEN]; + u8 ah_sta_id[ETH_ALEN]; + u8 ah_bssid[ETH_ALEN]; - u_int32_t ah_gpio[AR5K_MAX_GPIO]; + u32 ah_gpio[AR5K_MAX_GPIO]; int ah_gpio_npins; - ath5k_capabilities_t ah_capabilities; + struct ath5k_capabilities ah_capabilities; - AR5K_TXQ_INFO ah_txq[AR5K_NUM_TX_QUEUES]; - u_int32_t ah_txq_interrupts; + struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; + u32 ah_txq_interrupts; - u_int32_t *ah_rf_banks; + u32 *ah_rf_banks; size_t ah_rf_banks_size; struct ath5k_gain ah_gain; - u_int32_t ah_offset[AR5K_MAX_RF_BANKS]; + u32 ah_offset[AR5K_MAX_RF_BANKS]; struct { - u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; - u_int16_t txp_rates[AR5K_MAX_RATES]; - int16_t txp_min, txp_max; - AR5K_BOOL txp_tpc; - int16_t txp_ofdm; + u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; + u16 txp_rates[AR5K_MAX_RATES]; + s16 txp_min, txp_max; + bool txp_tpc; + s16 txp_ofdm; } ah_txpower; struct { - AR5K_BOOL r_enabled; + bool r_enabled; int r_last_alert; - AR5K_CHANNEL r_last_channel; + struct ath5k_channel r_last_channel; } ah_radar; /* * Function pointers */ AR5K_HAL_FUNCTIONS(, ah, *) - }; /* * Prototypes */ -const char *ath_hal_probe(u16, u16); -struct ath_hal *ath5k_hw_init(u16, void *, void __iomem *, - AR5K_STATUS *); -u_int16_t ath_hal_computetxtime(struct ath_hal *, const AR5K_RATE_TABLE *, - u_int32_t, u_int16_t, AR5K_BOOL); -u_int ath_hal_mhz2ieee(u_int, u_int); -u_int ath_hal_ieee2mhz(u_int, u_int); -AR5K_BOOL ath_hal_init_channels(struct ath_hal *, AR5K_CHANNEL *, - u_int, u_int *, AR5K_CTRY_CODE, u_int16_t, - AR5K_BOOL, AR5K_BOOL); -const char* ath5k_printver(enum ath5k_srev_type, u_int32_t); -void ath5k_radar_alert(struct ath_hal *); -ieee80211_regdomain_t ath5k_regdomain_to_ieee(u_int16_t); -u_int16_t ath5k_regdomain_from_ieee(ieee80211_regdomain_t); -u_int16_t ath5k_get_regdomain(struct ath_hal *); -u_int32_t ath5k_bitswap(u_int32_t, u_int); -inline u_int ath5k_clocktoh(u_int, AR5K_BOOL); -inline u_int ath5k_htoclock(u_int, AR5K_BOOL); -void ath5k_rt_copy(AR5K_RATE_TABLE *, const AR5K_RATE_TABLE *); -AR5K_BOOL ath5k_register_timeout(struct ath_hal *, u_int32_t, u_int32_t, - u_int32_t, AR5K_BOOL); -int ath5k_eeprom_init(struct ath_hal *); -int ath5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); -AR5K_BOOL ath5k_eeprom_regulation_domain(struct ath_hal *, AR5K_BOOL, +const char *ath_hal_probe(u16, u16); +struct ath_hal *ath5k_hw_init(u16, void *, void __iomem *, enum ath5k_status *); +u16 ath_hal_computetxtime(struct ath_hal *, const struct ath5k_rate_table *, + u32, u16, bool); +u_int ath_hal_mhz2ieee(u_int, u_int); +u_int ath_hal_ieee2mhz(u_int, u_int); +bool ath_hal_init_channels(struct ath_hal *, struct ath5k_channel *, + u_int, u_int *, enum ieee80211_countrycode, u16, + bool, bool); +const char *ath5k_printver(enum ath5k_srev_type, u32); +void ath5k_radar_alert(struct ath_hal *); +ieee80211_regdomain_t ath5k_regdomain_to_ieee(u16); +u16 ath5k_regdomain_from_ieee(ieee80211_regdomain_t); +u16 ath5k_get_regdomain(struct ath_hal *); +u32 ath5k_bitswap(u32, u_int); +inline u_int ath5k_clocktoh(u_int, bool); +inline u_int ath5k_htoclock(u_int, bool); +void ath5k_rt_copy(struct ath5k_rate_table *, const struct ath5k_rate_table *); +bool ath5k_register_timeout(struct ath_hal *, u32, u32, + u32, bool); +int ath5k_eeprom_init(struct ath_hal *); +int ath5k_eeprom_read_mac(struct ath_hal *, u8 *); +bool ath5k_eeprom_regulation_domain(struct ath_hal *, bool, ieee80211_regdomain_t *); -int ath5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); -int ath5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); -u_int16_t ath5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); - -AR5K_BOOL ath5k_hw_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_hw_rf5110_channel(struct ath_hal *, AR5K_CHANNEL *); -u_int32_t ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *); -AR5K_BOOL ath5k_hw_rf5111_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_hw_rf5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); -AR5K_BOOL ath5k_hw_rf5112_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); - -AR5K_BOOL ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); -AR5K_BOOL ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); -AR5K_BOOL ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); - -AR5K_BOOL ath5k_hw_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -AR5K_BOOL ath5k_hw_rf5111_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -AR5K_BOOL ath5k_hw_rf5112_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -void ath5k_hw_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int, u_int); -u_int ath5k_hw_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, - u_int32_t, u_int32_t, AR5K_BOOL); -u_int32_t ath5k_hw_rfregs_gainf_corr(struct ath_hal *); -AR5K_BOOL ath5k_hw_rfregs_gain_readback(struct ath_hal *); -int32_t ath5k_hw_rfregs_gain_adjust(struct ath_hal *); -AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); -void ath5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); +int ath5k_eeprom_read_ants(struct ath_hal *, u32 *, u_int); +int ath5k_eeprom_read_modes(struct ath_hal *, u32 *, u_int); +u16 ath5k_eeprom_bin2freq(struct ath_hal *, u16, u_int); + +bool ath5k_hw_channel(struct ath_hal *, struct ath5k_channel *); +bool ath5k_hw_rf5110_channel(struct ath_hal *, struct ath5k_channel *); +u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *); +bool ath5k_hw_rf5111_channel(struct ath_hal *, struct ath5k_channel *); +bool ath5k_hw_rf5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); +bool ath5k_hw_rf5112_channel(struct ath_hal *, struct ath5k_channel *); +bool ath5k_check_channel(struct ath_hal *, u16, u_int flags); + +bool ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); + +bool ath5k_hw_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); +bool ath5k_hw_rf5111_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); +bool ath5k_hw_rf5112_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); +void ath5k_hw_ar5211_rfregs(struct ath_hal *, struct ath5k_channel *, u_int, u_int); +u_int ath5k_hw_rfregs_op(u32 *, u32, u32, u32, + u32, u32, bool); +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *); +bool ath5k_hw_rfregs_gain_readback(struct ath_hal *); +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *); +bool ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); +void ath5k_txpower_table(struct ath_hal *, struct ath5k_channel *, s16); /*added*/ -extern u_int ath_hal_getwirelessmodes(struct ath_hal *, AR5K_CTRY_CODE); +extern u_int ath_hal_getwirelessmodes(struct ath_hal *, enum ieee80211_countrycode); void ath_hal_detach(struct ath_hal *ah); struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, - AR5K_STATUS *s); + enum ath5k_status *s); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 85f4e88..b20bc3d 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -25,6 +25,7 @@ #include #include +#include #include "ah_devid.h" #include "ath5k.h" @@ -71,18 +72,18 @@ static const struct { }; /*Rate tables*/ -static const AR5K_RATE_TABLE ath5k_rt_11a = AR5K_RATES_11A; -static const AR5K_RATE_TABLE ath5k_rt_11b = AR5K_RATES_11B; -static const AR5K_RATE_TABLE ath5k_rt_11g = AR5K_RATES_11G; -static const AR5K_RATE_TABLE ath5k_rt_turbo = AR5K_RATES_TURBO; -static const AR5K_RATE_TABLE ath5k_rt_xr = AR5K_RATES_XR; +static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; +static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; +static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G; +static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; +static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -AR5K_BOOL ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); -AR5K_BOOL ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t, AR5K_BOOL); -u_int16_t ath5k_hw_radio_revision(struct ath_hal *, AR5K_CHIP); +bool ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); +bool ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t, bool); +u_int16_t ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); void ath5k_hw_fill(struct ath_hal *); -AR5K_BOOL ath5k_hw_txpower(struct ath_hal *, AR5K_CHANNEL *, u_int); +bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, u_int); AR5K_HAL_FUNCTIONS(extern, ath5k_hw,); @@ -167,10 +168,10 @@ EXPORT_SYMBOL(ath_hal_probe); * TODO: Left here for combatibility, change it in ath5k */ u_int16_t /*TODO: Is this really hardware dependent ?*/ -ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates, - u_int32_t frame_length, u_int16_t rate_index, AR5K_BOOL short_preamble) +ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, + u_int32_t frame_length, u_int16_t rate_index, bool short_preamble) { - const AR5K_RATE *rate; + const struct ath5k_rate *rate; u_int32_t value; AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); @@ -234,7 +235,7 @@ EXPORT_SYMBOL(ath_hal_computetxtime); * TODO:Left here for combatibility, change it in at5k */ u_int/*TODO:Fix this */ -ath_hal_getwirelessmodes(struct ath_hal *hal, AR5K_CTRY_CODE country) +ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) { switch(hal->ah_version){ case AR5K_AR5212: @@ -265,13 +266,13 @@ ath5k_hw_bitswap(u_int32_t val, u_int bits) } inline u_int -ath5k_hw_htoclock(u_int usec, AR5K_BOOL turbo) +ath5k_hw_htoclock(u_int usec, bool turbo) { return (turbo == TRUE ? (usec * 80) : (usec * 40)); } inline u_int -ath5k_hw_clocktoh(u_int clock, AR5K_BOOL turbo) +ath5k_hw_clocktoh(u_int clock, bool turbo) { return (turbo == TRUE ? (clock / 80) : (clock / 40)); } @@ -280,9 +281,9 @@ ath5k_hw_clocktoh(u_int clock, AR5K_BOOL turbo) * Copy a rate table to a new one */ inline void -ath5k_hw_rtcopy(AR5K_RATE_TABLE *dst, const AR5K_RATE_TABLE *src) +ath5k_hw_rtcopy(struct ath5k_rate_table *dst, const struct ath5k_rate_table *src) { - memset(dst, 0, sizeof(AR5K_RATE_TABLE)); + memset(dst, 0, sizeof(struct ath5k_rate_table)); dst->rate_count = src->rate_count; memcpy(dst->rates, src->rates, sizeof(dst->rates)); } @@ -326,9 +327,9 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) /* * Check if a register write has been completed */ -static AR5K_BOOL +static bool ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, - u_int32_t val, AR5K_BOOL is_set) + u_int32_t val, bool is_set) { int i; u_int32_t data; @@ -358,7 +359,7 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, * Check if the device is supported and initialize the needed structs */ struct ath_hal * -ath5k_hw_init(u16 device, void *sc, void __iomem *sh, AR5K_STATUS *status) +ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) { struct ath_hal *hal = NULL; u_int8_t mac[ETH_ALEN]; @@ -562,8 +563,8 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, AR5K_STATUS *status) /* * Bring up MAC + PHY Chips */ -AR5K_BOOL -ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, AR5K_BOOL initial) +bool +ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) { u_int32_t turbo, mode, clock; @@ -694,7 +695,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, AR5K_BOOL initial) * Get the PHY Chip revision */ u_int16_t -ath5k_hw_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) +ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) { int i; u_int32_t srev; @@ -744,7 +745,7 @@ ath5k_hw_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) * Get the rate table for a specific operation mode * TODO:Limit this per chipset */ -const AR5K_RATE_TABLE * +const struct ath5k_rate_table * ath5k_hw_get_rate_table(struct ath_hal *hal, u_int mode) { @@ -795,15 +796,15 @@ ath5k_hw_detach(struct ath_hal *hal) /* * Main reset function */ -AR5K_BOOL +bool ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, - AR5K_CHANNEL *channel, AR5K_BOOL change_channel, AR5K_STATUS *status) + struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int8_t mac[ETH_ALEN]; u_int32_t data, noise_floor, s_seq, s_ant, s_led[3]; u_int i, phy, mode, freq, off, ee_mode, ant[2]; - const AR5K_RATE_TABLE *rt; + const struct ath5k_rate_table *rt; AR5K_TRACE; @@ -1380,10 +1381,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /* * Reset chipset */ -AR5K_BOOL +bool ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) { - AR5K_BOOL ret = FALSE; + bool ret = FALSE; u_int32_t mask = val ? val : ~0; AR5K_TRACE; @@ -1428,9 +1429,9 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) /* * Sleep control */ -AR5K_BOOL -ath5k_hw_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, - AR5K_BOOL set_chip, u_int16_t sleep_duration) +bool +ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, + bool set_chip, u_int16_t sleep_duration) { u_int32_t staid; int i; @@ -1499,7 +1500,7 @@ ath5k_hw_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, * Get power mode (sleep state) * TODO:Remove ? */ -AR5K_POWER_MODE +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal) { AR5K_TRACE; @@ -1530,7 +1531,7 @@ ath5k_hw_start_rx(struct ath_hal *hal) /* * Stop DMA receive */ -AR5K_BOOL +bool ath5k_hw_stop_rx_dma(struct ath_hal *hal) { int i; @@ -1578,7 +1579,7 @@ ath5k_hw_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) * Start DMA transmit for a specific queue * (see also QCU/DCU functions) */ -AR5K_BOOL +bool ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) { u_int32_t tx_queue; @@ -1635,7 +1636,7 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) * Stop DMA transmit for a specific queue * (see also QCU/DCU functions) */ -AR5K_BOOL +bool ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) { int i = 100, pending; @@ -1729,7 +1730,7 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) * Set the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) */ -AR5K_BOOL +bool ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) { u_int16_t tx_reg; @@ -1773,11 +1774,11 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) /* * Update tx trigger level */ -AR5K_BOOL -ath5k_hw_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) +bool +ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) { u_int32_t trigger_level, imr; - AR5K_BOOL status = FALSE; + bool status = FALSE; AR5K_TRACE; /* @@ -1823,7 +1824,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) /* * Check if we have pending interrupts */ -AR5K_BOOL +bool ath5k_hw_is_intr_pending(struct ath_hal *hal) { AR5K_TRACE; @@ -1833,7 +1834,7 @@ ath5k_hw_is_intr_pending(struct ath_hal *hal) /* * Get interrupt mask (ISR) */ -AR5K_BOOL +bool ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) { u_int32_t data; @@ -1919,10 +1920,10 @@ ath5k_hw_get_intr(struct ath_hal *hal) /* * Set interrupt mask */ -AR5K_INT -ath5k_hw_set_intr(struct ath_hal *hal, AR5K_INT new_mask) +enum ath5k_int +ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) { - AR5K_INT old_mask, int_mask; + enum ath5k_int old_mask, int_mask; /* * Disable card interrupts to prevent any race conditions @@ -1977,7 +1978,7 @@ ath5k_hw_set_intr(struct ath_hal *hal, AR5K_INT new_mask) * Enalbe HW radar detection */ void -ath5k_hw_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) +ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) { AR5K_TRACE; @@ -2029,7 +2030,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) /* * Check if eeprom is busy */ -AR5K_BOOL +bool ath5k_hw_eeprom_is_busy(struct ath_hal *hal) { AR5K_TRACE; @@ -2527,8 +2528,8 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) /* * Read/Write refulatory domain */ -AR5K_BOOL -ath5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, +bool +ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, ieee80211_regdomain_t *regdomain) { u_int16_t ee_regdomain; @@ -2558,9 +2559,9 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, /* * Use the above to write a new regulatory domain */ -AR5K_BOOL +bool ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - AR5K_STATUS *status) + enum ath5k_status *status) { ieee80211_regdomain_t ieee_regdomain; @@ -2580,7 +2581,7 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, /* * Fill the capabilities struct */ -AR5K_BOOL +bool ath5k_hw_get_capabilities(struct ath_hal *hal) { u_int16_t ee_header; @@ -2741,7 +2742,7 @@ ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) /* * Set station id */ -AR5K_BOOL +bool ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) { u_int32_t low_id, high_id; @@ -2801,7 +2802,7 @@ ath5k_hw_set_associd(struct ath_hal *hal, const u_int8_t *bssid, /* * Set BSSID mask on 5212 */ -AR5K_BOOL +bool ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) { u_int32_t low_id, high_id; @@ -2864,7 +2865,7 @@ ath5k_hw_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, /* * Set multicast filter by index */ -AR5K_BOOL +bool ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) { @@ -2884,7 +2885,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) /* * Clear Multicast filter by index */ -AR5K_BOOL +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) { @@ -3060,13 +3061,13 @@ ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, * Set beacon timers */ void -ath5k_hw_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) +ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state) { u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; /* * TODO: should be changed through *state - * review AR5K_BEACON_STATE struct + * review struct ath5k_beacon_state struct * * XXX: These are used for cfp period bellow, are they * ok ? Is it O.K. for tsf here to be 0 or should we use @@ -3207,10 +3208,10 @@ ath5k_hw_reset_beacon(struct ath_hal *hal) * Wait for beacon queue to finish * TODO: This function's name is misleading, rename */ -AR5K_BOOL +bool ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) { - AR5K_BOOL ret; + bool ret; int i; AR5K_TRACE; @@ -3254,7 +3255,7 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) * Update mib counters (statistics) */ void -ath5k_hw_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) +ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statistics) { AR5K_TRACE; /* Read-And-Clear */ @@ -3274,7 +3275,7 @@ ath5k_hw_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) } void /*Unimplemented*/ -ath5k_hw_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) +ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; return; @@ -3287,7 +3288,7 @@ ath5k_hw_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) /* * Set ACK timeout on PCU */ -AR5K_BOOL +bool ath5k_hw_set_ack_timeout(struct ath_hal *hal, u_int timeout) { AR5K_TRACE; @@ -3315,7 +3316,7 @@ ath5k_hw_get_ack_timeout(struct ath_hal *hal) /* * Set CTS timeout on PCU */ -AR5K_BOOL +bool ath5k_hw_set_cts_timeout(struct ath_hal *hal, u_int timeout) { AR5K_TRACE; @@ -3347,8 +3348,8 @@ ath5k_hw_get_cts_timeout(struct ath_hal *hal) /* * Return which ciphers are supported by hw */ -AR5K_BOOL -ath5k_hw_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) +bool +ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) { AR5K_TRACE; /* @@ -3373,7 +3374,7 @@ ath5k_hw_get_keycache_size(struct ath_hal *hal) /* * Reset encryption key */ -AR5K_BOOL +bool ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) { int i; @@ -3395,7 +3396,7 @@ ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) /* * Check if a key entry is valid */ -AR5K_BOOL +bool ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) { AR5K_TRACE; @@ -3414,9 +3415,9 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) /* * Set encryption key */ -AR5K_BOOL +bool ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, - const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) + const struct ath5k_keyval *keyval, const u_int8_t *mac, int xor_notused) { int i; u_int32_t key_v[AR5K_KEYCACHE_SIZE - 2]; @@ -3462,7 +3463,7 @@ ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, return (ath5k_hw_set_key_lladdr(hal, entry, mac)); } -AR5K_BOOL +bool ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, const u_int8_t *mac) { @@ -3500,8 +3501,8 @@ Queue Control Unit, DFS Control Unit Functions * Initialize a transmit queue */ int -ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, - AR5K_TXQ_INFO *queue_info) +ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, + struct ath5k_txq_info *queue_info) { u_int queue; AR5K_TRACE; @@ -3555,7 +3556,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, /* * Setup internal queue structure */ - memset(&hal->ah_txq[queue], 0, sizeof(AR5K_TXQ_INFO)); + memset(&hal->ah_txq[queue], 0, sizeof(struct ath5k_txq_info)); hal->ah_txq[queue].tqi_type = queue_type; if (queue_info != NULL) { @@ -3577,9 +3578,9 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, /* * Setup a transmit queue */ -AR5K_BOOL +bool ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, - const AR5K_TXQ_INFO *queue_info) + const struct ath5k_txq_info *queue_info) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3587,7 +3588,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) return (FALSE); - memcpy(&hal->ah_txq[queue], queue_info, sizeof(AR5K_TXQ_INFO)); + memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); /*XXX: Is this supported on 5210 ?*/ if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && @@ -3603,18 +3604,18 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, /* * Get properties for a specific transmit queue */ -AR5K_BOOL -ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) +bool +ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info *queue_info) { AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); return (TRUE); } /* * Set a transmit queue inactive */ -AR5K_BOOL +bool ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) { AR5K_TRACE; @@ -3631,11 +3632,11 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) /* * Set DFS params for a transmit queue */ -AR5K_BOOL +bool ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) { u_int32_t cw_min, cw_max, retry_lg, retry_sh; - AR5K_TXQ_INFO *tq = &hal->ah_txq[queue]; + struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; struct ath5k_ar5210_ini_mode ar5210_mode[] = AR5K_AR5210_INI_MODE(hal->ah_aifs + tq->tqi_aifs); @@ -3870,7 +3871,7 @@ ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) { /* * Set slot time */ -AR5K_BOOL +bool ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) { AR5K_TRACE; @@ -3914,9 +3915,9 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) /* * Initialize the 2-word tx descriptor on 5210/5211 */ -static AR5K_BOOL +static bool ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, + u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { @@ -4011,9 +4012,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Initialize the 4-word tx descriptor on 5212 */ -static AR5K_BOOL +static bool ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, + u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { @@ -4096,7 +4097,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Initialize a 4-word XR tx descriptor on 5212 */ -static AR5K_BOOL +static bool ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, u_int tx_rate3, u_int tx_tries3) @@ -4131,9 +4132,9 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Fill the 2-word tx descriptor on 5210/5211 */ -static AR5K_BOOL +static bool ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) + u_int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4160,9 +4161,9 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Fill the 4-word tx descriptor on 5212 * XXX: Added an argument *last_desc -need revision */ -static AR5K_BOOL +static bool ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, + u_int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4192,7 +4193,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the tx status descriptor on 5210/5211 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; @@ -4251,7 +4252,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* * Proccess a tx descriptor on 5212 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; @@ -4344,7 +4345,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* * Initialize an rx descriptor */ -AR5K_BOOL +bool ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t size, u_int flags) { @@ -4380,7 +4381,7 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the rx status descriptor on 5210/5211 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { @@ -4455,7 +4456,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, /* * Proccess the rx status descriptor on 5212 */ -static AR5K_STATUS +static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { @@ -4543,7 +4544,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, * Set led state */ void -ath5k_hw_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) +ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) { u_int32_t led; /*5210 has different led mode handling*/ @@ -4601,7 +4602,7 @@ ath5k_hw_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) /* * Set GPIO outputs */ -AR5K_BOOL +bool ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; @@ -4618,7 +4619,7 @@ ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) /* * Set GPIO inputs */ -AR5K_BOOL +bool ath5k_hw_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; @@ -4650,7 +4651,7 @@ ath5k_hw_get_gpio(struct ath_hal *hal, u_int32_t gpio) /* * Set GPIO state */ -AR5K_BOOL +bool ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) { u_int32_t data; @@ -4771,7 +4772,7 @@ EXPORT_SYMBOL(ath_hal_ieee2mhz); /* * Check if a channel is supported */ -AR5K_BOOL +bool ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) { /* Check if the channel is in our supported range */ @@ -4792,18 +4793,18 @@ ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) * TODO: Do this in the driver, only check_channel is hw related * also left here temporarily for combatibility. */ -AR5K_BOOL -ath_hal_init_channels(struct ath_hal *hal, AR5K_CHANNEL *channels, - u_int max_channels, u_int *channels_size, AR5K_CTRY_CODE country, u_int16_t mode, - AR5K_BOOL outdoor, AR5K_BOOL extended) +bool +ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, + u_int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u_int16_t mode, + bool outdoor, bool extended) { u_int i, c; u_int32_t domain_current; u_int domain_5ghz, domain_2ghz; - AR5K_CHANNEL *all_channels; - AR5K_CTRY_CODE country_current; + struct ath5k_channel *all_channels; + enum ieee80211_countrycode country_current; - if ((all_channels = kmalloc(sizeof(AR5K_CHANNEL) * max_channels, + if ((all_channels = kmalloc(sizeof(struct ath5k_channel) * max_channels, GFP_KERNEL)) == NULL) return (FALSE); @@ -4922,7 +4923,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ } done: - memcpy(channels, all_channels, sizeof(AR5K_CHANNEL) * max_channels); + memcpy(channels, all_channels, sizeof(struct ath5k_channel) * max_channels); *channels_size = c; kfree(all_channels); return (TRUE); @@ -5002,10 +5003,10 @@ ath5k_hw_get_regdomain(struct ath_hal *hal) /* * Set a channel on the radio chip */ -AR5K_BOOL -ath5k_hw_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - AR5K_BOOL ret; + bool ret; /* * Check bounds supported by the PHY @@ -5045,7 +5046,7 @@ ath5k_hw_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) * Convertion needed for RF5110 */ u_int32_t -ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *channel) +ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) { u_int32_t athchan; @@ -5065,8 +5066,8 @@ ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *channel) /* * Set channel on RF5110 */ -AR5K_BOOL -ath5k_hw_rf5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) { u_int32_t data; @@ -5084,7 +5085,7 @@ ath5k_hw_rf5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Convertion needed for 5111 */ -AR5K_BOOL +bool ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) { int channel; @@ -5113,8 +5114,8 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) /* * Set channel on 5111 */ -AR5K_BOOL -ath5k_hw_rf5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) { u_int ieee_channel, ath_channel; u_int32_t data0, data1, clock; @@ -5157,8 +5158,8 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Set channel on 5112 */ -AR5K_BOOL -ath5k_hw_rf5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) { u_int32_t data, data0, data1, data2; u_int16_t c; @@ -5205,10 +5206,10 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Perform a PHY calibration */ -AR5K_BOOL -ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel){ +bool +ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ - AR5K_BOOL ret; + bool ret; if (hal->ah_radio == AR5K_RF5110) ret = ath5k_hw_rf5110_calibrate(hal,channel); @@ -5220,10 +5221,10 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel){ /* * Perform a PHY calibration on RF5110 */ -AR5K_BOOL -ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { - AR5K_BOOL ret = TRUE; + bool ret = TRUE; u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor; u_int i; @@ -5369,8 +5370,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) /* * Perform a PHY calibration on RF5111/5112 */ -AR5K_BOOL -ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) +bool +ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { u_int32_t i_pwr, q_pwr; int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; @@ -5417,7 +5418,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) return (TRUE); } -AR5K_BOOL +bool ath5k_hw_phy_disable(struct ath_hal *hal) { AR5K_TRACE; @@ -5450,7 +5451,7 @@ ath5k_hw_get_def_antenna(struct ath_hal *hal) u_int ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, - u_int32_t first, u_int32_t col, AR5K_BOOL set) + u_int32_t first, u_int32_t col, bool set) { u_int32_t mask, entry, last, data, shift, position; int32_t left; @@ -5532,7 +5533,7 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) return (hal->ah_gain.g_f_corr); } -AR5K_BOOL +bool ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) { u_int32_t step, mix, level[4]; @@ -5634,11 +5635,11 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) /* * Initialize RF */ -AR5K_BOOL -ath5k_hw_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +bool +ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) { ath5k_rfgain_t *func = NULL; - AR5K_BOOL ret; + bool ret; if (hal->ah_radio == AR5K_RF5111) { hal->ah_rf_banks_size = sizeof(rf5111_rf); @@ -5672,8 +5673,8 @@ ath5k_hw_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) /* * Initialize RF5111 */ -AR5K_BOOL -ath5k_hw_rf5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +bool +ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; const u_int rf_size = AR5K_ELEMENTS(rf5111_rf); @@ -5770,8 +5771,8 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) /* * Initialize RF5112 */ -AR5K_BOOL -ath5k_hw_rf5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +bool +ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int rf_size; @@ -5867,7 +5868,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) * doesn't ar5k_rfregs work ? */ void -ath5k_hw_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, +ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int freq, u_int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -5925,7 +5926,7 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; } -AR5K_BOOL +bool ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) { int i; @@ -5955,7 +5956,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) return (TRUE); } -AR5K_RFGAIN +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal) { u_int32_t data, type; @@ -6005,7 +6006,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) * Initialize the tx power table (not fully implemented) */ void -ath5k_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t max_power) +ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t max_power) { u_int16_t txpower, *rates; int i, min, max, n; @@ -6042,10 +6043,10 @@ ath5k_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t max_powe /* * Set transmition power */ -AR5K_BOOL /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower) +bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ +ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpower) { - AR5K_BOOL tpc = hal->ah_txpower.txp_tpc; + bool tpc = hal->ah_txpower.txp_tpc; int i; AR5K_TRACE; @@ -6100,11 +6101,11 @@ ath5k_hw_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower) return (TRUE); } -AR5K_BOOL +bool ath5k_hw_set_txpower_limit(struct ath_hal *hal, u_int power) { /*Just a try M.F.*/ - AR5K_CHANNEL *channel = &hal->ah_current_channel; + struct ath5k_channel *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n",power); @@ -6222,7 +6223,7 @@ ath5k_hw_dump_state(struct ath_hal *hal) #endif } -AR5K_BOOL /*what about VEOL cap ?*/ +bool /*what about VEOL cap ?*/ ath5k_hw_has_veol(struct ath_hal *hal) { return (TRUE); @@ -6236,14 +6237,14 @@ ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) return; } -void /*Added AR5K_NODE_STATS argument*/ -ath5k_hw_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) +void /*Added struct ath5k_node_stats argument*/ +ath5k_hw_set_rx_signal(struct ath_hal *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; /* Signal state monitoring is not yet supported */ } -AR5K_BOOL /*Added arguments*/ +bool /*Added arguments*/ ath5k_hw_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) { @@ -6255,7 +6256,7 @@ const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) return (FALSE); } -AR5K_BOOL /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ +bool /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ ath5k_hw_detect_card_present(struct ath_hal *hal) { u_int16_t magic; @@ -6271,8 +6272,8 @@ ath5k_hw_detect_card_present(struct ath_hal *hal) return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); } -AR5K_STATUS -ath5k_hw_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, +enum ath5k_status +ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, u_int32_t capability, u_int32_t *result) { AR5K_TRACE; @@ -6330,11 +6331,12 @@ ath5k_hw_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, } -AR5K_BOOL -ath5k_hw_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) +bool +ath5k_hw_set_capability(struct ath_hal *hal, + enum ath5k_capability_type cap_type, + u_int32_t capability, u_int32_t setting, + enum ath5k_status *status) { - AR5K_TRACE; if (status) *status = AR5K_OK; @@ -6342,7 +6344,7 @@ ath5k_hw_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, return (FALSE); } -AR5K_BOOL +bool ath5k_hw_query_pspoll_support(struct ath_hal *hal) { AR5K_TRACE; @@ -6352,7 +6354,7 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) return (FALSE); } -AR5K_BOOL +bool ath5k_hw_init_pspoll(struct ath_hal *hal) { AR5K_TRACE; @@ -6362,7 +6364,7 @@ ath5k_hw_init_pspoll(struct ath_hal *hal) return (FALSE); } -AR5K_BOOL +bool ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, u_int16_t assoc_id) { @@ -6377,7 +6379,7 @@ ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, return (FALSE); } -AR5K_BOOL +bool ath5k_hw_disable_pspoll(struct ath_hal *hal) { AR5K_TRACE; diff --git a/openhal/ath5k_hw.h b/openhal/ath5k_hw.h index 1458dfe..3b53963 100644 --- a/openhal/ath5k_hw.h +++ b/openhal/ath5k_hw.h @@ -21,11 +21,11 @@ * Gain settings */ -typedef enum { +enum ath5k_rfgain { AR5K_RFGAIN_INACTIVE = 0, AR5K_RFGAIN_READ_REQUESTED, AR5K_RFGAIN_NEED_CHANGE, -} AR5K_RFGAIN; +}; #define AR5K_GAIN_CRN_FIX_BITS_5111 4 #define AR5K_GAIN_CRN_FIX_BITS_5112 7 @@ -55,19 +55,19 @@ struct ath5k_gain_opt_step { }; struct ath5k_gain_opt { - u_int32_t go_default; - u_int32_t go_steps_count; + u32 go_default; + u32 go_steps_count; const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; }; struct ath5k_gain { - u_int32_t g_step_idx; - u_int32_t g_current; - u_int32_t g_target; - u_int32_t g_low; - u_int32_t g_high; - u_int32_t g_f_corr; - u_int32_t g_active; + u32 g_step_idx; + u32 g_current; + u32 g_target; + u32 g_low; + u32 g_high; + u32 g_f_corr; + u32 g_active; const struct ath5k_gain_opt_step *g_step; }; @@ -146,47 +146,47 @@ struct ath5k_gain { #define AR5K_EEPROM_N_IQ_CAL 2 struct ath5k_eeprom_info { - u_int16_t ee_magic; - u_int16_t ee_protect; - u_int16_t ee_regdomain; - u_int16_t ee_version; - u_int16_t ee_header; - u_int16_t ee_ant_gain; - u_int16_t ee_misc0; - u_int16_t ee_misc1; - u_int16_t ee_cck_ofdm_gain_delta; - u_int16_t ee_cck_ofdm_power_delta; - u_int16_t ee_scaled_cck_delta; - u_int16_t ee_tx_clip; - u_int16_t ee_pwd_84; - u_int16_t ee_pwd_90; - u_int16_t ee_gain_select; - - u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES]; - u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES]; - u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES]; - u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES]; - u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES]; - u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; - u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; - u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xpd[AR5K_EEPROM_N_MODES]; - u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; - u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; - u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; - u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; - - u_int16_t ee_ctls; - u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS]; + u16 ee_magic; + u16 ee_protect; + u16 ee_regdomain; + u16 ee_version; + u16 ee_header; + u16 ee_ant_gain; + u16 ee_misc0; + u16 ee_misc1; + u16 ee_cck_ofdm_gain_delta; + u16 ee_cck_ofdm_power_delta; + u16 ee_scaled_cck_delta; + u16 ee_tx_clip; + u16 ee_pwd_84; + u16 ee_pwd_90; + u16 ee_gain_select; + + u16 ee_i_cal[AR5K_EEPROM_N_MODES]; + u16 ee_q_cal[AR5K_EEPROM_N_MODES]; + u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; + u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; + u16 ee_xr_power[AR5K_EEPROM_N_MODES]; + u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; + u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; + u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; + u16 ee_thr_62[AR5K_EEPROM_N_MODES]; + u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; + u16 ee_xpd[AR5K_EEPROM_N_MODES]; + u16 ee_x_gain[AR5K_EEPROM_N_MODES]; + u16 ee_i_gain[AR5K_EEPROM_N_MODES]; + u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_false_detect[AR5K_EEPROM_N_MODES]; + u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; + u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; + + u16 ee_ctls; + u16 ee_ctl[AR5K_EEPROM_MAX_CTLS]; int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; @@ -361,9 +361,9 @@ struct ath5k_eeprom_info { #define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS struct ath5k_ini_rf { - u_int8_t rf_bank; - u_int16_t rf_register; - u_int32_t rf_value[5]; + u8 rf_bank; + u16 rf_register; + u32 rf_value[5]; }; #define AR5K_RF5111_INI_RF { \ @@ -686,8 +686,8 @@ struct ath5k_ini_rf { } struct ath5k_ini_rfgain { - u_int16_t rfg_register; - u_int32_t rfg_value[2][2]; + u16 rfg_register; + u32 rfg_value[2][2]; #define AR5K_INI_RFGAIN_5GHZ 0 #define AR5K_INI_RFGAIN_2GHZ 1 @@ -833,14 +833,14 @@ struct ath5k_rx_desc { /* * RX control word 0 */ - u_int32_t rx_control_0; + u32 rx_control_0; #define AR5K_DESC_RX_CTL0 0x00000000 /* * RX control word 1 */ - u_int32_t rx_control_1; + u32 rx_control_1; #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 @@ -850,7 +850,7 @@ struct ath5k_hw_old_rx_status { /* * RX status word 0 */ - u_int32_t rx_status_0; + u32 rx_status_0; #define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff #define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 @@ -864,7 +864,7 @@ struct ath5k_hw_old_rx_status { /* * RX status word 1 */ - u_int32_t rx_status_1; + u32 rx_status_1; #define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 #define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 @@ -885,7 +885,7 @@ struct ath5k_hw_new_rx_status { /* * RX status word 0 */ - u_int32_t rx_status_0; + u32 rx_status_0; #define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff #define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 @@ -900,7 +900,7 @@ struct ath5k_hw_new_rx_status { /* * RX status word 1 */ - u_int32_t rx_status_1; + u32 rx_status_1; #define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 #define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 @@ -920,14 +920,14 @@ struct ath5k_hw_rx_error { /* * RX error word 0 */ - u_int32_t rx_error_0; + u32 rx_error_0; #define AR5K_RX_DESC_ERROR0 0x00000000 /* * RX error word 1 */ - u_int32_t rx_error_1; + u32 rx_error_1; #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 @@ -946,7 +946,7 @@ struct ath5k_hw_2w_tx_desc { /* * TX control word 0 */ - u_int32_t tx_control_0; + u32 tx_control_0; #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ @@ -971,7 +971,7 @@ struct ath5k_hw_2w_tx_desc { /* * TX control word 1 */ - u_int32_t tx_control_1; + u32 tx_control_1; #define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff #define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 @@ -997,7 +997,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 0 */ - u_int32_t tx_control_0; + u32 tx_control_0; #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 @@ -1014,7 +1014,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 1 */ - u_int32_t tx_control_1; + u32 tx_control_1; #define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff #define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 @@ -1033,7 +1033,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 2 */ - u_int32_t tx_control_2; + u32 tx_control_2; #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff #define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 @@ -1049,7 +1049,7 @@ struct ath5k_hw_4w_tx_desc { /* * TX control word 3 */ - u_int32_t tx_control_3; + u32 tx_control_3; #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 @@ -1066,7 +1066,7 @@ struct ath5k_hw_tx_status { /* * TX status word 0 */ - u_int32_t tx_status_0; + u32 tx_status_0; #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 @@ -1092,7 +1092,7 @@ struct ath5k_hw_tx_status { /* * TX status word 1 */ - u_int32_t tx_status_1; + u32 tx_status_1; #define AR5K_DESC_TX_STATUS1_DONE 0x00000001 #define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe @@ -1112,8 +1112,8 @@ struct ath5k_hw_tx_status { */ struct ath5k_ini { - u_int16_t ini_register; - u_int32_t ini_value; + u16 ini_register; + u32 ini_value; enum { AR5K_INI_WRITE = 0, @@ -1333,8 +1333,8 @@ struct ath5k_ini { } struct ath5k_ar5210_ini_mode{ - u_int16_t mode_register; - u_int32_t mode_base, mode_turbo; + u16 mode_register; + u32 mode_base, mode_turbo; }; #define AR5K_AR5210_INI_MODE(_aifs) { \ @@ -1554,9 +1554,9 @@ struct ath5k_ar5210_ini_mode{ } struct ath5k_ar5212_ini { - u_int8_t ini_flags; - u_int16_t ini_register; - u_int32_t ini_value; + u8 ini_flags; + u16 ini_register; + u32 ini_value; #define AR5K_INI_FLAG_511X 0x00 #define AR5K_INI_FLAG_5111 0x01 @@ -1938,8 +1938,8 @@ struct ath5k_ar5212_ini { } struct ath5k_ar5211_ini_mode { - u_int16_t mode_register; - u_int32_t mode_value[4]; + u16 mode_register; + u32 mode_value[4]; }; #define AR5K_AR5211_INI_MODE { \ @@ -1981,9 +1981,9 @@ struct ath5k_ar5211_ini_mode { } struct ath5k_ar5212_ini_mode { - u_int16_t mode_register; - u_int8_t mode_flags; - u_int32_t mode_value[2][5]; + u16 mode_register; + u8 mode_flags; + u32 mode_value[2][5]; }; #define AR5K_AR5212_INI_MODE { \ @@ -2154,8 +2154,8 @@ struct ath5k_ar5212_ini_mode { } struct ath5k_ar5211_ini_rf { - u_int16_t rf_register; - u_int32_t rf_value[2]; + u16 rf_register; + u32 rf_value[2]; }; #define AR5K_AR5211_INI_RF { \ commit 2ed949ae84a8798cb6275a8630b61afd4421371f Author: Jiri Slaby Date: Sun Jun 17 14:58:58 2007 +0200 use true/false from kernel diff --git a/ath/if_ath.c b/ath/if_ath.c index a2f282e..0403417 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -218,8 +218,8 @@ static int ath_dwelltime = 200; /* 5 channels/second */ static int ath_calinterval = 30; /* calibrate every 30 secs */ static int ath_countrycode = CTRY_DEFAULT; /* country code */ static int ath_regdomain = 0; /* regulatory domain */ -static int ath_outdoor = TRUE; /* enable outdoor use */ -static int ath_xchanmode = TRUE; /* enable extended channels */ +static int ath_outdoor = true; /* enable outdoor use */ +static int ath_xchanmode = true; /* enable extended channels */ #ifdef AR_DEBUG static int ath_debug = 0; @@ -899,7 +899,7 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs) if (status & AR5K_INT_TXURN) { sc->sc_stats.ast_txurn++; /* bump tx trigger level */ - ath_hal_updatetxtriglevel(ah, TRUE); + ath_hal_updatetxtriglevel(ah, true); } if (status & AR5K_INT_RX) ATH_SCHEDULE_TQUEUE(&sc->sc_rxtq, &needmark); @@ -1073,7 +1073,7 @@ ath_init(struct net_device *dev) sc->sc_curchan.freq = ic->ic_ibss_chan->ic_freq; sc->sc_curchan.channel_flags = ath_chan2flags(ic, ic->ic_ibss_chan); #endif - if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, FALSE, &status)) { + if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, false, &status)) { printk(KERN_ERR "unable to reset hardware; hal status %u\n", status); error = -EIO; @@ -1271,7 +1271,7 @@ ath_reset(struct net_device *dev) opmode = (ic->ic_opmode == IEEE80211_M_AHDEMO) ? 0 : ic->ic_opmode; /* NB: indicate channel change so we do a full reset */ - if (!ath_hal_reset(ah, opmode, &sc->sc_curchan, TRUE, &status)) + if (!ath_hal_reset(ah, opmode, &sc->sc_curchan, true, &status)) if_printf(dev, "%s: unable to reset hardware: '%s' (%u)\n", __func__, hal_status_desc[status], status); ath_update_txpow(sc); /* update tx power state */ @@ -1376,7 +1376,7 @@ static int ath_start_raw(struct sk_buff *skb, struct net_device *dev) { #define CTS_DURATION \ - ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, TRUE) + ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, true) /*#define updateCTSForBursting(_ah, _ds, _txq) \ ath_hal_updateCTSForBursting(_ah, _ds, \ _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ @@ -1577,8 +1577,8 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) ds->ds_data = bf->bf_skbaddr; ath_hal_filltxdesc(ah, ds , skb->len /* segment length */ - , TRUE /* first segment */ - , TRUE /* last segment */ + , true /* first segment */ + , true /* last segment */ , ds /* first descriptor */ ); @@ -2601,8 +2601,8 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, /* NB: beacon's BufLen must be a multiple of 4 bytes */ ath_hal_filltxdesc(ah, ds , roundup(skb->len, 4) /* buffer length */ - , TRUE /* first segment */ - , TRUE /* last segment */ + , true /* first segment */ + , true /* last segment */ , ds /* first descriptor */ ); #undef USE_SHPREAMBLE @@ -4163,7 +4163,7 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * struct sk_buff *skb) { #define CTS_DURATION \ - ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, TRUE) + ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, true) /*#define updateCTSForBursting(_ah, _ds, _txq) \ ath_hal_updateCTSForBursting(_ah, _ds, \ _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ @@ -4288,10 +4288,10 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * */ if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { - short_preamble = TRUE; + short_preamble = true; sc->sc_stats.ast_tx_shortpre++; } else { - short_preamble = FALSE; + short_preamble = false; } an = ATH_NODE(ni); @@ -4486,14 +4486,14 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * if (flags & AR5K_TXDESC_RTSENA) /* SIFS + CTS */ ctsduration += rt->rates[cix].sp_ack_duration; ctsduration += ath_hal_computetxtime(ah, - rt, pktlen, rix, TRUE); + rt, pktlen, rix, true); if ((flags & AR5K_TXDESC_NOACK) == 0) /* SIFS + ACK */ ctsduration += rt->rates[cix].sp_ack_duration; } else { if (flags & AR5K_TXDESC_RTSENA) /* SIFS + CTS */ ctsduration += rt->rates[cix].lp_ack_duration; ctsduration += ath_hal_computetxtime(ah, - rt, pktlen, rix, FALSE); + rt, pktlen, rix, false); if ((flags & AR5K_TXDESC_NOACK) == 0) /* SIFS + ACK */ ctsduration += rt->rates[cix].lp_ack_duration; } @@ -4564,8 +4564,8 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * ds->ds_data = bf->bf_skbaddr; ath_hal_filltxdesc(ah, ds , skb->len /* segment length */ - , TRUE /* first segment */ - , TRUE /* last segment */ + , true /* first segment */ + , true /* last segment */ , ds /* first descriptor */ ); DPRINTF(sc, ATH_DEBUG_XMIT, "%s: Q%d: %08x %08x %08x %08x %08x %08x\n", @@ -5124,7 +5124,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) ath_hal_intrset(ah, 0); /* disable interrupts */ ath_draintxq(sc); /* clear pending tx frames */ ath_stoprecv(sc); /* turn off frame recv */ - if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, TRUE, &status)) { + if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, true, &status)) { printk(KERN_ERR "ath_chan_set: unable to reset " "channel %u (%u Mhz)\n", 0, // ieee80211_chan2ieee(ic, chan), diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 8d61385..7689ff5 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -434,7 +434,7 @@ void ath_sysctl_unregister(void); #define ath_hal_updatetxtriglevel(_ah, _inc) \ ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) #define ath_hal_setpower(_ah, _mode, _sleepduration) \ - ((*(_ah)->ah_setPowerMode)((_ah), (_mode), TRUE, (_sleepduration))) + ((*(_ah)->ah_setPowerMode)((_ah), (_mode), true, (_sleepduration))) #define ath_hal_keycachesize(_ah) \ ((*(_ah)->ah_getKeyCacheSize)((_ah))) #define ath_hal_keyreset(_ah, _ix) \ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 8bf0bb3..a3f8980 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -58,18 +58,6 @@ #define howmany(x, y) (((x)+((y)-1))/(y)) /* - * C doesn't support boolean ;-( - * TODO: See if there is a bool definition somewere else - * in the kernel, we shouldn't redefine it if it does... - */ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* * Error codes reported from HAL to the driver */ enum ath5k_status { @@ -91,7 +79,7 @@ enum ath5k_status { #define AR5K_TUNE_DMA_BEACON_RESP 2 #define AR5K_TUNE_SW_BEACON_RESP 10 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 -#define AR5K_TUNE_RADAR_ALERT FALSE +#define AR5K_TUNE_RADAR_ALERT false #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) #define AR5K_TUNE_RSSI_THRES 1792 @@ -110,8 +98,8 @@ enum ath5k_status { #define AR5K_TUNE_NOISE_FLOOR -72 #define AR5K_TUNE_MAX_TXPOWER 60 #define AR5K_TUNE_DEFAULT_TXPOWER 30 -#define AR5K_TUNE_TPC_TXPOWER TRUE -#define AR5K_TUNE_ANT_DIVERSITY TRUE +#define AR5K_TUNE_TPC_TXPOWER true +#define AR5K_TUNE_ANT_DIVERSITY true #define AR5K_TUNE_HWTXTRIES 4 /* token to use for aifs, cwmin, cwmax in MadWiFi */ @@ -765,7 +753,7 @@ struct ath5k_keyval { #define AR5K_ASSERT_ENTRY(_e, _s) do { \ if (_e >= _s) \ - return (FALSE); \ + return (false); \ } while (0) diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index b20bc3d..56962b2 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -268,13 +268,13 @@ ath5k_hw_bitswap(u_int32_t val, u_int bits) inline u_int ath5k_hw_htoclock(u_int usec, bool turbo) { - return (turbo == TRUE ? (usec * 80) : (usec * 40)); + return (turbo == true ? (usec * 80) : (usec * 40)); } inline u_int ath5k_hw_clocktoh(u_int clock, bool turbo) { - return (turbo == TRUE ? (clock / 80) : (clock / 40)); + return (turbo == true ? (clock / 80) : (clock / 40)); } /* @@ -336,7 +336,7 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { data = AR5K_REG_READ(reg); - if ((is_set == TRUE) && (data & flag)) + if ((is_set == true) && (data & flag)) break; else if ((data & flag) == val) break; @@ -344,9 +344,9 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, } if (i <= 0) - return (FALSE); + return (false); - return (TRUE); + return (true); } @@ -410,14 +410,14 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) hal->ah_op_mode = IEEE80211_IF_TYPE_STA; hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; - hal->ah_turbo = FALSE; + hal->ah_turbo = false; hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; hal->ah_imr = 0; hal->ah_atim_window = 0; hal->ah_aifs = AR5K_TUNE_AIFS; hal->ah_cw_min = AR5K_TUNE_CWMIN; hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; - hal->ah_software_retry = FALSE; + hal->ah_software_retry = false; hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; switch (device) { @@ -427,13 +427,13 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /* * Known single chip solutions */ - hal->ah_single_chip = TRUE; + hal->ah_single_chip = true; break; default: /* * Multi chip solutions */ - hal->ah_single_chip = FALSE; + hal->ah_single_chip = false; break; } @@ -446,7 +446,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) ath5k_hw_fill(hal); /* Bring device out of sleep and reset it's units */ - if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, TRUE) != TRUE) + if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true) != true) goto failed; /* Get MAC, PHY and RADIO revisions */ @@ -503,7 +503,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) } /* Get misc capabilities */ - if (hal->ah_get_capabilities(hal) != TRUE) { + if (hal->ah_get_capabilities(hal) != true) { *status = AR5K_EEREAD; AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", device); @@ -595,7 +595,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) clock |= AR5K_PHY_PLL_40MHZ; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); + return (false); } if (flags & CHANNEL_CCK) { @@ -611,7 +611,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) mode |= AR5K_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); + return (false); } if (flags & CHANNEL_TURBO) { @@ -625,12 +625,12 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) */ else { - if (initial == TRUE) { + if (initial == true) { /* ...reset hardware */ if (ath5k_hw_nic_reset(hal, - AR5K_RESET_CTL_PCI) == FALSE) { + AR5K_RESET_CTL_PCI) == false) { AR5K_PRINT("failed to reset the PCI chipset\n"); - return (FALSE); + return (false); } udelay(1000); @@ -638,9 +638,9 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) /* ...wakeup */ if (ath5k_hw_set_power(hal, - AR5K_PM_AWAKE, TRUE, 0) == FALSE) { + AR5K_PM_AWAKE, true, 0) == false) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return (FALSE); + return (false); } /* ...enable Atheros turbo mode if requested */ @@ -648,19 +648,19 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE); /* ...reset chipset */ - if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == FALSE) { + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == false) { AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return (FALSE); + return (false); } udelay(1000); } /* ...reset chipset and PCI device */ - if (hal->ah_single_chip == FALSE && - ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == FALSE) { + if (hal->ah_single_chip == false && + ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == false) { AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); - return (FALSE); + return (false); } if (hal->ah_version == AR5K_AR5210) @@ -668,15 +668,15 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) /* ...wakeup */ if (ath5k_hw_set_power(hal, - AR5K_PM_AWAKE, TRUE, 0) == FALSE) { + AR5K_PM_AWAKE, true, 0) == false) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return (FALSE); + return (false); } /* ...final warm reset */ - if (ath5k_hw_nic_reset(hal, 0) == FALSE) { + if (ath5k_hw_nic_reset(hal, 0) == false) { AR5K_PRINT("failed to warm reset the MAC Chip\n"); - return (FALSE); + return (false); } if (hal->ah_version != AR5K_AR5210){ @@ -688,7 +688,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); } - return (TRUE); + return (true); } /* @@ -821,7 +821,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ /*DCU/Antenna selection not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { - if (change_channel == TRUE) { + if (change_channel == true) { /*Sequence number for queue 0 -do this for all queues ?*/ s_seq = AR5K_REG_READ(AR5K_QUEUE_DFS_SEQNUM(0)); /*Default antenna*/ @@ -834,14 +834,14 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, s_led[1] = AR5K_REG_READ(AR5K_GPIOCR); s_led[2] = AR5K_REG_READ(AR5K_GPIODO); - if (change_channel == TRUE && hal->ah_rf_banks != NULL) + if (change_channel == true && hal->ah_rf_banks != NULL) ath5k_hw_get_rf_gain(hal); /*Wakeup the device*/ - if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, FALSE) == FALSE) { + if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) { *status = AR5K_EIO; - return (FALSE); + return (false); } /* @@ -861,7 +861,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, else { AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); *status = AR5K_EINVAL; - return (FALSE); + return (false); } switch (channel->channel_flags & CHANNEL_MODES) { @@ -894,7 +894,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, case CHANNEL_XR: if (hal->ah_version == AR5K_AR5211) { AR5K_PRINTF("XR mode not available on 5211"); - return (FALSE); + return (false); } mode = AR5K_INI_VAL_XR; freq = AR5K_INI_RFGAIN_5GHZ; @@ -903,7 +903,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, default: AR5K_PRINTF("invalid channel: %d\n", channel->freq); *status = AR5K_EINVAL; - return (FALSE); + return (false); } /* PHY access enable */ @@ -956,7 +956,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) { - if (change_channel == TRUE && + if (change_channel == true && ar5212_ini[i].ini_register >= AR5K_PCU_MIN && ar5212_ini[i].ini_register <= AR5K_PCU_MAX) continue; @@ -974,7 +974,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { - if (change_channel == TRUE && + if (change_channel == true && ar5211_ini[i].ini_register >= AR5K_PCU_MIN && ar5211_ini[i].ini_register <= AR5K_PCU_MAX) continue; @@ -987,7 +987,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /*For 5210*/ if (hal->ah_version == AR5K_AR5210) for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) { - if (change_channel == TRUE && + if (change_channel == true && ar5210_ini[i].ini_register >= AR5K_PCU_MIN && ar5210_ini[i].ini_register <= AR5K_PCU_MAX) continue; @@ -1013,9 +1013,9 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, * Write initial RF gain settings * This should work for both 5111/5112 */ - if (ath5k_hw_rfgain(hal, phy, freq) == FALSE) { + if (ath5k_hw_rfgain(hal, phy, freq) == false) { *status = AR5K_EIO; - return (FALSE); + return (false); } udelay(1000); @@ -1036,12 +1036,12 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, data = AR5K_RATE_DUR(rt->rates[i].rate_code); AR5K_REG_WRITE(data, ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); + rt->rates[i].control_rate, false)); if (HAS_SHPREAMBLE(i)) { AR5K_REG_WRITE(data + (AR5K_SET_SHORT_PREAMBLE << 2), ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); + rt->rates[i].control_rate, false)); } } @@ -1057,7 +1057,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, for (i = 0; i < rt->rate_count; i++) { AR5K_REG_WRITE(AR5K_RATE_DUR(rt->rates[i].rate_code), ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); + rt->rates[i].control_rate, false)); } } @@ -1079,18 +1079,18 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, * Set TX power (XXX use txpower from net80211) */ if (ath5k_hw_txpower(hal, channel, - AR5K_TUNE_DEFAULT_TXPOWER) == FALSE) { + AR5K_TUNE_DEFAULT_TXPOWER) == false) { *status = AR5K_EIO; - return (FALSE); + return (false); } /* * Write RF registers * TODO:Does this work on 5211 (5111) ? */ - if (ath5k_hw_rfregs(hal, channel, mode) == FALSE) { + if (ath5k_hw_rfregs(hal, channel, mode) == false) { *status = AR5K_EINPROGRESS; - return (FALSE); + return (false); } /* @@ -1112,7 +1112,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (!coef_exp) { *status = AR5K_EINVAL; - return (FALSE); + return (false); } coef_exp = 14 - (coef_exp - 24); @@ -1243,9 +1243,9 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /* * Set channel and calibrate the PHY */ - if (ath5k_hw_channel(hal, channel) == FALSE) { + if (ath5k_hw_channel(hal, channel) == false) { *status = AR5K_EIO; - return (FALSE); + return (false); } /* @@ -1273,10 +1273,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) { + AR5K_PHY_AGCCTL_CAL, 0, false) == false) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); - return (FALSE); + return (false); } /* @@ -1286,10 +1286,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, FALSE) == FALSE) { + AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return (FALSE); + return (false); } /* Wait until the noise floor is calibrated and read the value */ @@ -1308,13 +1308,13 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return (FALSE); + return (false); } - hal->ah_calibration = FALSE; + hal->ah_calibration = false; if (!(channel->channel_flags & CHANNEL_B)) { - hal->ah_calibration = TRUE; + hal->ah_calibration = true; AR5K_REG_WRITE_BITS(AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, @@ -1329,10 +1329,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (hal->ah_version != AR5K_AR5210) AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i); - if (ath5k_hw_reset_tx_queue(hal, i) == FALSE) { + if (ath5k_hw_reset_tx_queue(hal, i) == false) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); *status = AR5K_EINVAL; - return (FALSE); + return (false); } } @@ -1375,7 +1375,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_REG_DISABLE_BITS(AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); - return (TRUE); + return (true); } /* @@ -1384,7 +1384,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, bool ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) { - bool ret = FALSE; + bool ret = false; u_int32_t mask = val ? val : ~0; AR5K_TRACE; @@ -1411,7 +1411,7 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; } - ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, FALSE); + ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false); /* * Reset configuration register (for hw byte-swap) @@ -1444,7 +1444,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; /* fallthrough */ case AR5K_PM_NETWORK_SLEEP: - if (set_chip == TRUE) { + if (set_chip == true) { AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE | sleep_duration); } @@ -1452,7 +1452,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, break; case AR5K_PM_FULL_SLEEP: - if (set_chip == TRUE) { + if (set_chip == true) { AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE_SLP); } @@ -1460,7 +1460,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, break; case AR5K_PM_AWAKE: - if (set_chip == FALSE) + if (set_chip == false) goto commit; AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE_WAKE); @@ -1479,13 +1479,13 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, /* Fail if the chip didn't wake up */ if (i <= 0) - return (FALSE); + return (false); staid &= ~AR5K_STA_ID1_PWR_SV; break; default: - return (FALSE); + return (false); } commit: @@ -1493,7 +1493,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, AR5K_REG_WRITE(AR5K_STA_ID1, staid); - return (TRUE); + return (true); } /* @@ -1547,7 +1547,7 @@ ath5k_hw_stop_rx_dma(struct ath_hal *hal) i--) udelay(10); - return (i > 0 ? TRUE : FALSE); + return (i > 0 ? true : false); } /* @@ -1589,7 +1589,7 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (FALSE); + return (false); if (hal->ah_version == AR5K_AR5210) { @@ -1616,20 +1616,20 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) AR5K_BCR_BDMAE); break; default: - return (FALSE); + return (false); } /* Start queue */ AR5K_REG_WRITE(AR5K_CR, tx_queue); } else { /* Return if queue is disabled */ if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) - return (FALSE); + return (false); /* Start queue */ AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); } - return (TRUE); + return (true); } /* @@ -1647,7 +1647,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (FALSE); + return (false); if (hal->ah_version == AR5K_AR5210) { tx_queue = AR5K_REG_READ(AR5K_CR); @@ -1666,7 +1666,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) AR5K_REG_WRITE(AR5K_BSR, 0); break; default: - return (FALSE); + return (false); } /* Stop queue */ @@ -1689,7 +1689,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) } /*TODO: Check for success else return false*/ - return (TRUE); + return (true); } /* @@ -1751,7 +1751,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) tx_reg = AR5K_NOQCU_TXDP1; break; default: - return (FALSE); + return (false); } } else { /* @@ -1760,7 +1760,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) * (this won't work if the queue is still active) */ if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) - return (FALSE); + return (false); tx_reg = AR5K_QUEUE_TXDP(queue); } @@ -1768,7 +1768,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) /* Set descriptor pointer */ AR5K_REG_WRITE(tx_reg, phys_addr); - return (TRUE); + return (true); } /* @@ -1778,7 +1778,7 @@ bool ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) { u_int32_t trigger_level, imr; - bool status = FALSE; + bool status = false; AR5K_TRACE; /* @@ -1790,7 +1790,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_TXCFG), AR5K_TXCFG_TXFULL); - if (increase == FALSE) { + if (increase == false) { if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) goto done; } else @@ -1806,7 +1806,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) AR5K_REG_WRITE_BITS(AR5K_TXCFG, AR5K_TXCFG_TXFULL, trigger_level); - status = TRUE; + status = true; done: /* @@ -1828,7 +1828,7 @@ bool ath5k_hw_is_intr_pending(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_INTPEND) == TRUE ? TRUE : FALSE); + return (AR5K_REG_READ(AR5K_INTPEND) == true ? true : false); } /* @@ -1848,7 +1848,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) if (hal->ah_version == AR5K_AR5210) { if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) { *interrupt_mask = data; - return (FALSE); + return (false); } } @@ -1863,7 +1863,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; if (data == AR5K_INT_NOCARD) - return (FALSE); + return (false); if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) *interrupt_mask |= AR5K_INT_RX; @@ -1885,7 +1885,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) * Special interrupt handling (not caught by the driver) */ if (((*interrupt_mask) & AR5K_ISR_RXPHY) && - hal->ah_radar.r_enabled == TRUE) + hal->ah_radar.r_enabled == true) ath5k_radar_alert(hal); /* @@ -1903,7 +1903,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) if (*interrupt_mask == 0) AR5K_PRINTF("0x%08x\n", data); - return (TRUE); + return (true); } /* @@ -1994,7 +1994,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) * possible radar activity. */ if (hal->ah_version == AR5K_AR5210) { - if (enable == TRUE) { + if (enable == true) { AR5K_REG_ENABLE_BITS(AR5K_IMR, AR5K_IMR_RXPHY); } else { @@ -2003,7 +2003,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) } } else { /*Also set AR5K_PHY_RADAR register on 5111/5112*/ - if (enable == TRUE) { + if (enable == true) { AR5K_REG_WRITE(AR5K_PHY_RADAR, AR5K_PHY_RADAR_ENABLE); AR5K_REG_ENABLE_BITS(AR5K_PIMR, @@ -2035,7 +2035,7 @@ ath5k_hw_eeprom_is_busy(struct ath_hal *hal) { AR5K_TRACE; return (AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? - TRUE : FALSE); + true : false); } /* @@ -2535,10 +2535,10 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, u_int16_t ee_regdomain; /* Read current value */ - if (write != TRUE) { + if (write != true) { ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; *regdomain = ath5k_regdomain_to_ieee(ee_regdomain); - return (TRUE); + return (true); } ee_regdomain = ath5k_regdomain_from_ieee(*regdomain); @@ -2546,14 +2546,14 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, /* Try to write a new value */ if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_EEPROM_PROTECT_WR_128_191) - return (FALSE); + return (false); if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain) != 0) - return (FALSE); + return (false); hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; - return (TRUE); + return (true); } /* @@ -2567,15 +2567,15 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); - if (ath5k_eeprom_regulation_domain(hal, TRUE, - &ieee_regdomain) == TRUE) { + if (ath5k_eeprom_regulation_domain(hal, true, + &ieee_regdomain) == true) { *status = AR5K_OK; - return (TRUE); + return (true); } *status = AR5K_EIO; - return (FALSE); + return (false); } /* @@ -2648,7 +2648,7 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) else hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; - return (TRUE); + return (true); } @@ -2757,7 +2757,7 @@ ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) AR5K_REG_WRITE(AR5K_STA_ID0, low_id); AR5K_REG_WRITE(AR5K_STA_ID1, high_id); - return (TRUE); + return (true); } /* @@ -2816,9 +2816,9 @@ ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) AR5K_REG_WRITE(AR5K_BSS_IDM0, low_id); AR5K_REG_WRITE(AR5K_BSS_IDM1, high_id); - return (TRUE); + return (true); } else - return (FALSE); + return (false); } /* @@ -2871,7 +2871,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) AR5K_TRACE; if (index >= 64) - return (FALSE); + return (false); else if (index >= 32) AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1, (1 << (index - 32))); @@ -2879,7 +2879,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0, (1 << index)); - return (TRUE); + return (true); } /* @@ -2891,7 +2891,7 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) AR5K_TRACE; if (index >= 64) - return (FALSE); + return (false); else if (index >= 32) AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1, (1 << (index - 32))); @@ -2899,7 +2899,7 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0, (1 << index)); - return (TRUE); + return (true); } /* @@ -3234,18 +3234,18 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, phys_addr); AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE); - return (FALSE); + return (false); } - ret= TRUE; + ret= true; } else { /*5211/5212*/ ret = ath5k_hw_register_timeout(hal, AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), - AR5K_QCU_STS_FRMPENDCNT, 0, FALSE); + AR5K_QCU_STS_FRMPENDCNT, 0, false); if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) - return (FALSE); + return (false); } return (ret); @@ -3294,12 +3294,12 @@ ath5k_hw_set_ack_timeout(struct ath_hal *hal, u_int timeout) AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), hal->ah_turbo) <= timeout) - return (FALSE); + return (false); AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_htoclock(timeout, hal->ah_turbo)); - return (TRUE); + return (true); } /* @@ -3322,12 +3322,12 @@ ath5k_hw_set_cts_timeout(struct ath_hal *hal, u_int timeout) AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), hal->ah_turbo) <= timeout) - return (FALSE); + return (false); AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_htoclock(timeout, hal->ah_turbo)); - return (TRUE); + return (true); } /* @@ -3356,9 +3356,9 @@ ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) * Only WEP for now */ if (cipher == AR5K_CIPHER_WEP) - return (TRUE); + return (true); - return (FALSE); + return (false); } /* @@ -3390,7 +3390,7 @@ ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), AR5K_KEYTABLE_TYPE_NULL); - return (FALSE); /*????*/ + return (false); /*????*/ } /* @@ -3407,9 +3407,9 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) */ if (AR5K_REG_READ(AR5K_KEYTABLE_MAC1(entry)) & AR5K_KEYTABLE_VALID) - return (TRUE); + return (true); - return (FALSE); + return (false); } /* @@ -3454,7 +3454,7 @@ ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, default: /* Unsupported key length (not WEP40/104/128) */ - return (FALSE); + return (false); } for (i = 0; i < AR5K_ELEMENTS(key_v); i++) @@ -3487,7 +3487,7 @@ ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id); - return (TRUE); + return (true); } @@ -3562,7 +3562,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, if (queue_info != NULL) { queue_info->tqi_type = queue_type; if (ath5k_hw_setup_tx_queueprops(hal, queue, queue_info) - != TRUE) + != true) return (-1); } /* @@ -3586,7 +3586,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (FALSE); + return (false); memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); @@ -3598,7 +3598,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - return (TRUE); + return (true); } /* @@ -3609,7 +3609,7 @@ ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info { AR5K_TRACE; memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); - return (TRUE); + return (true); } /* @@ -3626,7 +3626,7 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) /*For SIMR setup*/ AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - return (FALSE); /*???*/ + return (false); /*???*/ } /* @@ -3647,19 +3647,19 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) tq = &hal->ah_txq[queue]; if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (TRUE); + return (true); if (hal->ah_version == AR5K_AR5210) { /* Only handle data queues, others will be ignored */ if (tq->tqi_type != AR5K_TX_QUEUE_DATA) - return (TRUE); + return (true); /* * Write initial mode register settings */ for (i = 0; i < AR5K_ELEMENTS(ar5210_mode); i++) AR5K_REG_WRITE((u_int32_t)ar5210_mode[i].mode_register, - hal->ah_turbo == TRUE ? + hal->ah_turbo == true ? ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base); } @@ -3697,7 +3697,7 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) /* * Calculate and set retry limits */ - if (hal->ah_software_retry == TRUE) { + if (hal->ah_software_retry == true) { /* XXX Need to test this */ retry_lg = hal->ah_limit_tx_retries; retry_sh = retry_lg = @@ -3845,7 +3845,7 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); } - return (TRUE); + return (true); } /* @@ -3859,11 +3859,11 @@ ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) { /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (FALSE); + return (false); /* XXX: How about AR5K_CFG_TXCNT ? */ if (hal->ah_version == AR5K_AR5210) - return (FALSE); + return (false); return (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT); } @@ -3876,7 +3876,7 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) { AR5K_TRACE; if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) - return (FALSE); + return (false); if (hal->ah_version == AR5K_AR5210) AR5K_REG_WRITE(AR5K_SLOT_TIME, @@ -3884,7 +3884,7 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) else AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); - return (TRUE); + return (true); } /* @@ -3930,7 +3930,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Validate input */ if (tx_tries0 == 0) - return (FALSE); + return (false); /* Initialize control descriptor */ tx_desc->tx_control_0 = 0; @@ -3941,7 +3941,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /*Verify packet length*/ if ((tx_desc->tx_control_0 = (packet_length & AR5K_2W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return (FALSE); + return (false); /* * Verify header length * XXX: I only found that on 5210 code, does it work on 5211 ? @@ -3949,7 +3949,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (hal->ah_version == AR5K_AR5210) if ((tx_desc->tx_control_0 = (header_length & AR5K_2W_TX_DESC_CTL0_HEADER_LEN)) != header_length) - return (FALSE); + return (false); /*Diferences between 5210-5211*/ if (hal->ah_version == AR5K_AR5210) { @@ -4006,7 +4006,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; } - return (TRUE); + return (true); } /* @@ -4028,7 +4028,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Validate input */ if (tx_tries0 == 0) - return (FALSE); + return (false); /* Initialize status descriptor */ tx_desc->tx_control_0 = 0; @@ -4039,7 +4039,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Setup status descriptor */ if ((tx_desc->tx_control_0 = (packet_length & AR5K_4W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return (FALSE); + return (false); tx_desc->tx_control_0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | @@ -4083,7 +4083,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { if ((flags & AR5K_TXDESC_RTSENA) && (flags & AR5K_TXDESC_CTSENA)) - return (FALSE); + return (false); tx_desc->tx_control_2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION; tx_desc->tx_control_3 |= @@ -4091,7 +4091,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); } - return (TRUE); + return (true); } /* @@ -4123,10 +4123,10 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, #undef _XTX_TRIES - return (TRUE); + return (true); } - return(FALSE); + return(false); } /* @@ -4146,15 +4146,15 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_2W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return (FALSE); + return (false); - if (first_segment != TRUE) + if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN; - if (last_segment != TRUE) + if (last_segment != true) tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE; - return (TRUE); + return (true); } /* @@ -4179,15 +4179,15 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_4W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return (FALSE); + return (false); - if (first_segment != TRUE) + if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN; - if (last_segment != TRUE) + if (last_segment != true) tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE; - return (TRUE); + return (true); } /* @@ -4370,12 +4370,12 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, /*Setup descriptor*/ if ((rx_desc->rx_control_1 = (size & AR5K_DESC_RX_CTL1_BUF_LEN)) != size) - return (FALSE); + return (false); if (flags & AR5K_RXDESC_INTREQ) rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; - return (TRUE); + return (true); } /* @@ -4607,13 +4607,13 @@ ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (FALSE); + return (false); AR5K_REG_WRITE(AR5K_GPIOCR, (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio)); - return (TRUE); + return (true); } /* @@ -4624,13 +4624,13 @@ ath5k_hw_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (FALSE); + return (false); AR5K_REG_WRITE(AR5K_GPIOCR, (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio)); - return (TRUE); + return (true); } /* @@ -4658,7 +4658,7 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (FALSE); + return (false); /* GPIO output magic */ data = AR5K_REG_READ(AR5K_GPIODO); @@ -4668,7 +4668,7 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) AR5K_REG_WRITE(AR5K_GPIODO, data); - return (TRUE); + return (true); } /* @@ -4779,13 +4779,13 @@ ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) if (flags & CHANNEL_2GHZ) { if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) - return (TRUE); + return (true); } else if (flags & CHANNEL_5GHZ) if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) - return (TRUE); + return (true); - return (FALSE); + return (false); } /* @@ -4806,7 +4806,7 @@ ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, if ((all_channels = kmalloc(sizeof(struct ath5k_channel) * max_channels, GFP_KERNEL)) == NULL) - return (FALSE); + return (false); i = c = 0; domain_current = hal->ah_regdomain; @@ -4827,7 +4827,7 @@ ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, debugchan: for (i = min; (i <= max) && (c < max_channels); i++) { freq = ath_hal_ieee2mhz(i, flags); - if (ath5k_check_channel(hal, freq, flags) == FALSE) + if (ath5k_check_channel(hal, freq, flags) == false) continue; all_channels[c].freq = freq; all_channels[c].channel_flags = flags; @@ -4866,7 +4866,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ /* Check if channel is supported by the chipset */ if (ath5k_check_channel(hal, ath5k_5ghz_channels[i].rc_channel, - CHANNEL_5GHZ) == FALSE) + CHANNEL_5GHZ) == false) continue; /* Match regulation domain */ @@ -4897,7 +4897,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ /* Check if channel is supported by the chipset */ if (ath5k_check_channel(hal, ath5k_2ghz_channels[i].rc_channel, - CHANNEL_2GHZ) == FALSE) + CHANNEL_2GHZ) == false) continue; /* Match regulation domain */ @@ -4926,7 +4926,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ memcpy(channels, all_channels, sizeof(struct ath5k_channel) * max_channels); *channels_size = c; kfree(all_channels); - return (TRUE); + return (true); } EXPORT_SYMBOL(ath_hal_init_channels); @@ -4968,7 +4968,7 @@ ath5k_get_regdomain(struct ath_hal *hal) u_int16_t code; #endif - ath5k_eeprom_regulation_domain(hal, FALSE, &ieee_regdomain); + ath5k_eeprom_regulation_domain(hal, false, &ieee_regdomain); hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; #ifdef COUNTRYCODE @@ -5018,7 +5018,7 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { AR5K_PRINTF("channel out of supported range (%u MHz)\n", channel->freq); - return (FALSE); + return (false); } /* @@ -5031,15 +5031,15 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) else ret = ath5k_hw_rf5112_channel(hal, channel); - if (ret == FALSE) + if (ret == false) return (ret); hal->ah_current_channel.freq = channel->freq; hal->ah_current_channel.channel_flags = channel->channel_flags; hal->ah_turbo = channel->channel_flags == CHANNEL_T ? - TRUE : FALSE; + true : false; - return (TRUE); + return (true); } /* @@ -5079,7 +5079,7 @@ ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x30, 0); udelay(1000); - return (TRUE); + return (true); } /* @@ -5106,9 +5106,9 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) athchan->a2_athchan = ((channel - 14) * 4) + 132; athchan->a2_flags = 0x46; } else - return (FALSE); + return (false); - return (TRUE); + return (true); } /* @@ -5131,8 +5131,8 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) if (channel->channel_flags & CHANNEL_2GHZ) { /* Map 2GHz channel to 5GHz Atheros channel ID */ if (ath5k_hw_rf5111_chan2athchan(ieee_channel, - &ath_channel_2ghz) == FALSE) - return (FALSE); + &ath_channel_2ghz) == false) + return (false); ath_channel = ath_channel_2ghz.a2_athchan; data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) @@ -5152,7 +5152,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); - return (TRUE); + return (true); } /* @@ -5178,7 +5178,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) data0 = ((2 * (c - 672)) - 3040) / 10; data1 = 0; } else - return (FALSE); + return (false); data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); } else { @@ -5192,7 +5192,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); data2 = ath5k_hw_bitswap(1, 2); } else - return (FALSE); + return (false); } data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; @@ -5200,7 +5200,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x27, data & 0xff); AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); - return (TRUE); + return (true); } /* @@ -5224,7 +5224,7 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { - bool ret = TRUE; + bool ret = true; u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor; u_int i; @@ -5263,7 +5263,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AGC_ENABLE; - if (ret == FALSE) + if (ret == false) return (ret); /* @@ -5307,10 +5307,10 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) { + AR5K_PHY_AGCCTL_CAL, 0, false) == false) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); - ret = FALSE; + ret = false; } /* Reset to normal state */ @@ -5318,8 +5318,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, phy_agc); AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat); - if (ret == FALSE) - return (FALSE); + if (ret == false) + return (false); /* * Enable noise floor calibration and wait until completion @@ -5328,10 +5328,10 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, FALSE) == FALSE) { + AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return (FALSE); + return (false); } /* Wait until the noise floor is calibrated */ @@ -5350,7 +5350,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return (FALSE); + return (false); } @@ -5364,7 +5364,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) #undef AGC_ENABLE #undef AGC_DISABLE - return (TRUE); + return (true); } /* @@ -5377,11 +5377,11 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; AR5K_TRACE; - if (hal->ah_calibration == FALSE || + if (hal->ah_calibration == false || AR5K_REG_READ(AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) goto done; - hal->ah_calibration = FALSE; + hal->ah_calibration = false; iq_corr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_CORR); i_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_I); @@ -5415,7 +5415,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } - return (TRUE); + return (true); } bool @@ -5424,7 +5424,7 @@ ath5k_hw_phy_disable(struct ath_hal *hal) AR5K_TRACE; /*Just a try M.F.*/ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); - return (TRUE); + return (true); } void /*TODO:Boundary check*/ @@ -5446,7 +5446,7 @@ ath5k_hw_get_def_antenna(struct ath_hal *hal) if (hal->ah_version != AR5K_AR5210) return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); - return (FALSE); /*XXX: What do we return for 5210 ?*/ + return (false); /*XXX: What do we return for 5210 ?*/ } u_int @@ -5471,7 +5471,7 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit entry = ((first - 1) / 8) + offset; position = (first - 1) % 8; - if (set == TRUE) + if (set == true) data = ath5k_hw_bitswap(reg, bits); for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { @@ -5479,7 +5479,7 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8); - if (set == TRUE) { + if (set == true) { rf[entry] &= ~mask; rf[entry] |= ((data << position) << (col * 8)) & mask; data >>= (8 - position); @@ -5492,7 +5492,7 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit left -= 8 - position; } - data = set == TRUE ? 1 : ath5k_hw_bitswap(data, bits); + data = set == true ? 1 : ath5k_hw_bitswap(data, bits); return (data); } @@ -5509,10 +5509,10 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) rf = hal->ah_rf_banks; hal->ah_gain.g_f_corr = 0; - if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1) + if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1) return (0); - step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE); + step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false); mix = hal->ah_gain.g_step->gos_param[0]; switch (mix) { @@ -5546,7 +5546,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) if (hal->ah_radio == AR5K_RF5111) { step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 6, 37, 0, FALSE); + 0, 6, 37, 0, false); level[0] = 0; level[1] = (step == 0x3f) ? 0x32 : step + 4; level[2] = (step != 0x3f) ? 0x40 : level[0]; @@ -5558,7 +5558,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); } else { mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 1, 36, 0, FALSE); + 0, 1, 36, 0, false); level[0] = level[2] = 0; if (mix == 1) { @@ -5651,20 +5651,20 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) hal->ah_rf_banks_size = sizeof(rf5112_rf); func = ath5k_hw_rf5112_rfregs; } else - return (FALSE); + return (false); if (hal->ah_rf_banks == NULL) { /* XXX do extra checks? */ if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, GFP_KERNEL)) == NULL) { AR5K_PRINT("out of memory\n"); - return (FALSE); + return (false); } } ret = (func)(hal, channel, mode); - if (ret == TRUE) + if (ret == true) hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; return (ret); @@ -5691,7 +5691,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (rf5111_rf[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (FALSE); + return (false); } if (bank != rf5111_rf[i].rf_bank) { @@ -5710,12 +5710,12 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int obdb = 0; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 119, 0, TRUE)) - return (FALSE); + ee->ee_ob[ee_mode][obdb], 3, 119, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 122, 0, TRUE)) - return (FALSE); + ee->ee_ob[ee_mode][obdb], 3, 122, 0, true)) + return (false); obdb = 1; } else { @@ -5727,37 +5727,37 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int (channel->freq > 4000 ? 0 : -1))); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_84, 1, 51, 3, TRUE)) - return (FALSE); + ee->ee_pwd_84, 1, 51, 3, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_90, 1, 45, 3, TRUE)) - return (FALSE); + ee->ee_pwd_90, 1, 45, 3, true)) + return (false); } if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - !ee->ee_xpd[ee_mode], 1, 95, 0, TRUE)) - return (FALSE); + !ee->ee_xpd[ee_mode], 1, 95, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 4, 96, 0, TRUE)) - return (FALSE); + ee->ee_x_gain[ee_mode], 4, 96, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, TRUE)) - return (FALSE); + obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE)) - return (FALSE); + obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE)) - return (FALSE); + ee->ee_i_gain[ee_mode], 6, 29, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_xpd[ee_mode], 1, 4, 0, TRUE)) - return (FALSE); + ee->ee_xpd[ee_mode], 1, 4, 0, true)) + return (false); /* Write RF values */ for (i = 0; i < rf_size; i++) { @@ -5765,7 +5765,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]); } - return (TRUE); + return (true); } /* @@ -5798,7 +5798,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (FALSE); + return (false); } if (bank != rf_ini[i].rf_bank) { @@ -5817,12 +5817,12 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int obdb = 0; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 287, 0, TRUE)) - return (FALSE); + ee->ee_ob[ee_mode][obdb], 3, 287, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 290, 0, TRUE)) - return (FALSE); + ee->ee_ob[ee_mode][obdb], 3, 290, 0, true)) + return (false); } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; @@ -5832,34 +5832,34 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int (channel->freq > 4000 ? 0 : -1))); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 279, 0, TRUE)) - return (FALSE); + ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 282, 0, TRUE)) - return (FALSE); + ee->ee_ob[ee_mode][obdb], 3, 282, 0, true)) + return (false); } #ifdef notyet ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 270, 0, TRUE); + ee->ee_x_gain[ee_mode], 2, 270, 0, true); ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 257, 0, TRUE); + ee->ee_x_gain[ee_mode], 2, 257, 0, true); #endif if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_xpd[ee_mode], 1, 302, 0, TRUE)) - return (FALSE); + ee->ee_xpd[ee_mode], 1, 302, 0, true)) + return (false); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE)) - return (FALSE); + ee->ee_i_gain[ee_mode], 6, 14, 0, true)) + return (false); /* Write RF values */ for (i = 0; i < rf_size; i++) AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); - return (TRUE); + return (true); } /* @@ -5936,7 +5936,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) case AR5K_INI_PHY_5112: break; default: - return (FALSE); + return (false); } switch (freq) { @@ -5944,7 +5944,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) case AR5K_INI_RFGAIN_5GHZ: break; default: - return (FALSE); + return (false); } for (i = 0; i < AR5K_ELEMENTS(ath5k_rfg); i++) { @@ -5953,7 +5953,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) ath5k_rfg[i].rfg_value[phy][freq]); } - return (TRUE); + return (true); } enum ath5k_rfgain @@ -6052,7 +6052,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow AR5K_TRACE; if (txpower > AR5K_TUNE_MAX_TXPOWER) { AR5K_PRINTF("invalid tx power: %u\n", txpower); - return (FALSE); + return (false); } /* Reset TX power values */ @@ -6088,7 +6088,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); - if (hal->ah_txpower.txp_tpc == TRUE) { + if (hal->ah_txpower.txp_tpc == true) { AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | AR5K_TUNE_MAX_TXPOWER); @@ -6098,7 +6098,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow AR5K_TUNE_MAX_TXPOWER); } - return (TRUE); + return (true); } bool @@ -6226,7 +6226,7 @@ ath5k_hw_dump_state(struct ath_hal *hal) bool /*what about VEOL cap ?*/ ath5k_hw_has_veol(struct ath_hal *hal) { - return (TRUE); + return (true); } void /*Unimplemented*/ @@ -6253,7 +6253,7 @@ const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) * We'll ignore this right now. This seems to be some kind of an obscure * debugging interface for the binary-only HAL. */ - return (FALSE); + return (false); } bool /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ @@ -6267,9 +6267,9 @@ ath5k_hw_detect_card_present(struct ath_hal *hal) * way to do this. */ if (ath5k_hw_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (FALSE); + return (false); - return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); + return (magic == AR5K_EEPROM_MAGIC_VALUE ? true : false); } enum ath5k_status @@ -6341,7 +6341,7 @@ ath5k_hw_set_capability(struct ath_hal *hal, if (status) *status = AR5K_OK; - return (FALSE); + return (false); } bool @@ -6349,9 +6349,9 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) - return(TRUE); + return(true); - return (FALSE); + return (false); } bool @@ -6361,7 +6361,7 @@ ath5k_hw_init_pspoll(struct ath_hal *hal) /* * Not used */ - return (FALSE); + return (false); } bool @@ -6373,10 +6373,10 @@ ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); - return (TRUE); + return (true); } - return (FALSE); + return (false); } bool @@ -6387,10 +6387,10 @@ ath5k_hw_disable_pspoll(struct ath_hal *hal) AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); - return (TRUE); + return (true); } - return (FALSE); + return (false); } const char * /*O.K. - TODO:Get rid of this*/ commit 52686d9001703b67d734deec39d7cae9d5110765 Author: Jiri Slaby Date: Sun Jun 17 22:24:10 2007 +0200 ath/if_athvar.h cleanup diff --git a/ath/if_ath.c b/ath/if_ath.c index 0403417..ed6de19 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -102,11 +102,11 @@ enum { static int ath_init(struct net_device *); static int ath_reset(struct net_device *); -static void ath_fatal_tasklet(TQUEUE_ARG); -static void ath_bstuck_tasklet(TQUEUE_ARG); -static void ath_rxorn_tasklet(TQUEUE_ARG); -static void ath_bmiss_tasklet(TQUEUE_ARG); -static void ath_radar_tasklet(TQUEUE_ARG); +static void ath_fatal_tasklet(unsigned long); +static void ath_bstuck_tasklet(unsigned long); +static void ath_rxorn_tasklet(unsigned long); +static void ath_bmiss_tasklet(unsigned long); +static void ath_radar_tasklet(unsigned long); static int ath_stop_locked(struct net_device *); static int ath_stop(struct net_device *); #ifdef BLE @@ -146,7 +146,7 @@ static void ath_recv_mgmt(struct ieee80211com *, struct sk_buff *, int subtype, int rssi, u_int32_t rstamp); #endif static void ath_setdefantenna(struct ath_softc *, u_int); -static void ath_rx_tasklet(TQUEUE_ARG data); +static void ath_rx_tasklet(unsigned long data); static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); //static int ath_wme_update(struct ieee80211com *); static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); @@ -156,9 +156,9 @@ static int ath_start(struct sk_buff *, struct net_device *); static int ath_tx_setup(struct ath_softc *, int ac, int txq); static int ath_tx_start(struct net_device *, struct ieee80211_node *, struct ath_buf *, struct sk_buff *); -static void ath_tx_tasklet_q0(TQUEUE_ARG data); -static void ath_tx_tasklet_q0123(TQUEUE_ARG data); -static void ath_tx_tasklet(TQUEUE_ARG data); +static void ath_tx_tasklet_q0(unsigned long data); +static void ath_tx_tasklet_q0123(unsigned long data); +static void ath_tx_tasklet(unsigned long data); static void ath_tx_timeout(struct net_device *); static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); #endif @@ -352,12 +352,12 @@ ath_attach(u_int16_t devid, struct net_device *dev) ATH_LOCK_INIT(sc); ATH_TXBUF_LOCK_INIT(sc); - ATH_INIT_TQUEUE(&sc->sc_rxtq, ath_rx_tasklet, dev); - ATH_INIT_TQUEUE(&sc->sc_rxorntq,ath_rxorn_tasklet, dev); - ATH_INIT_TQUEUE(&sc->sc_fataltq,ath_fatal_tasklet, dev); - ATH_INIT_TQUEUE(&sc->sc_bmisstq,ath_bmiss_tasklet, dev); - ATH_INIT_TQUEUE(&sc->sc_bstuckq,ath_bstuck_tasklet, dev); - ATH_INIT_TQUEUE(&sc->sc_radartq,ath_radar_tasklet, dev); + tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)dev); + tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)dev); + tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)dev); + tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)dev); + tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)dev); + tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)dev); /* * Attach the hal @@ -821,12 +821,7 @@ ath_resume(struct net_device *dev) *Port r1752 - Starting linux kernel v2.6.19 and later *interrupt handlers are not passed. */ -irqreturn_t -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -ath_intr(int irq, void *dev_id) -#else -ath_intr(int irq, void *dev_id, struct pt_regs *regs) -#endif +irqreturn_t ath_intr(int irq, void *dev_id) { struct net_device *dev = dev_id; struct ath_softc *sc = dev->priv; @@ -872,11 +867,11 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs) */ sc->sc_stats.ast_hardware++; ath_hal_intrset(ah, 0); /* disable intr's until reset */ - ATH_SCHEDULE_TQUEUE(&sc->sc_fataltq, &needmark); + tasklet_schedule(&sc->sc_fataltq); } else if (status & AR5K_INT_RXORN) { sc->sc_stats.ast_rxorn++; ath_hal_intrset(ah, 0); /* disable intr's until reset */ - ATH_SCHEDULE_TQUEUE(&sc->sc_rxorntq, &needmark); + tasklet_schedule(&sc->sc_rxorntq); } else { if (status & AR5K_INT_SWBA) { /* @@ -902,12 +897,12 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs) ath_hal_updatetxtriglevel(ah, true); } if (status & AR5K_INT_RX) - ATH_SCHEDULE_TQUEUE(&sc->sc_rxtq, &needmark); + tasklet_schedule(&sc->sc_rxtq); if (status & AR5K_INT_TX) - ATH_SCHEDULE_TQUEUE(&sc->sc_txtq, &needmark); + tasklet_schedule(&sc->sc_txtq); if (status & AR5K_INT_BMISS) { sc->sc_stats.ast_bmiss++; - ATH_SCHEDULE_TQUEUE(&sc->sc_bmisstq, &needmark); + tasklet_schedule(&sc->sc_bmisstq); } if (status & AR5K_INT_MIB) { sc->sc_stats.ast_mib++; @@ -929,14 +924,11 @@ ath_intr(int irq, void *dev_id, struct pt_regs *regs) } } while (ath_hal_intrpend(ah)); - if (needmark) { - mark_bh(IMMEDIATE_BH); - } return IRQ_HANDLED; } static void -ath_fatal_tasklet(TQUEUE_ARG data) +ath_fatal_tasklet(unsigned long data) { struct net_device *dev = (struct net_device *)data; @@ -945,7 +937,7 @@ ath_fatal_tasklet(TQUEUE_ARG data) } static void -ath_radar_tasklet (TQUEUE_ARG data) +ath_radar_tasklet (unsigned long data) { struct net_device *dev = (struct net_device *)data; #ifdef BLE @@ -970,7 +962,7 @@ ath_radar_tasklet (TQUEUE_ARG data) } static void -ath_rxorn_tasklet(TQUEUE_ARG data) +ath_rxorn_tasklet(unsigned long data) { struct net_device *dev = (struct net_device *)data; @@ -979,7 +971,7 @@ ath_rxorn_tasklet(TQUEUE_ARG data) } static void -ath_bmiss_tasklet(TQUEUE_ARG data) +ath_bmiss_tasklet(unsigned long data) { #ifdef BLE struct net_device *dev = (struct net_device *)data; @@ -1630,14 +1622,15 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); DPRINTF(sc, ATH_DEBUG_XMIT, "%s: TXDP[%u] = %llx (%p) depth %d\n", __func__, - txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc, - txq->axq_depth); + txq->axq_qnum, (unsigned long long)bf->bf_daddr, + bf->bf_desc, txq->axq_depth); } else { *txq->axq_link = bf->bf_daddr; DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u](%p)=%llx (%p) depth %d\n", __func__, txq->axq_qnum, txq->axq_link, - ito64(bf->bf_daddr), bf->bf_desc, txq->axq_depth); + (unsigned long long)bf->bf_daddr, bf->bf_desc, + txq->axq_depth); } txq->axq_link = &bf->bf_desc->ds_link; /* @@ -2547,7 +2540,8 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, skb->data, skb->len, BUS_DMA_TODEVICE); DPRINTF(sc, ATH_DEBUG_BEACON, "%s: skb %p [data %p len %u] skbaddr %llx\n", - __func__, skb, skb->data, skb->len, ito64(bf->bf_skbaddr)); + __func__, skb, skb->data, skb->len, + (unsigned long long)bf->bf_skbaddr); if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { printk(KERN_ERR "%s: DMA mapping failed\n", __func__); return; @@ -2652,7 +2646,7 @@ ath_beacon_send(struct net_device *dev) DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: stuck beacon time (%u missed)\n", __func__, sc->sc_bmisscount); - ATH_SCHEDULE_TQUEUE(&sc->sc_bstuckq, &needmark); + tasklet_schedule(&sc->sc_bstuckq); } return; } @@ -2750,7 +2744,7 @@ ath_beacon_send(struct net_device *dev) ath_hal_txstart(ah, sc->sc_bhalq); DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: TXDP[%u] = %llx (%p)\n", __func__, - sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); + sc->sc_bhalq, (unsigned long long)bf->bf_daddr, bf->bf_desc); sc->sc_stats.ast_be_xmit++; } @@ -2759,7 +2753,7 @@ ath_beacon_send(struct net_device *dev) * Reset the hardware after detecting beacons have stopped. */ static void -ath_bstuck_tasklet(TQUEUE_ARG data) +ath_bstuck_tasklet(unsigned long data) { struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; @@ -3043,7 +3037,8 @@ ath_desc_alloc(struct ath_softc *sc) } ds = sc->sc_desc; DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%u) -> %llx\n", - __func__, ds, (unsigned int) sc->sc_desc_len, ito64(sc->sc_desc_daddr)); + __func__, ds, (unsigned int) sc->sc_desc_len, + (unsigned long long)sc->sc_desc_daddr); /* allocate buffers */ bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); @@ -3670,7 +3665,7 @@ ath_setdefantenna(struct ath_softc *sc, u_int antenna) } static void -ath_rx_tasklet(TQUEUE_ARG data) +ath_rx_tasklet(unsigned long data) { #define PA2DESC(_sc, _pa) \ ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ @@ -3755,7 +3750,7 @@ ath_rx_tasklet(TQUEUE_ARG data) /* if (phyerr == AR5K_PHYERR_RADAR && ic->ic_opmode == IEEE80211_M_HOSTAP) { - ATH_SCHEDULE_TQUEUE (&sc->sc_radartq, &needmark); + tasklet_schedule(&sc->sc_radartq); } */ goto rx_next; @@ -4616,14 +4611,15 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); DPRINTF(sc, ATH_DEBUG_XMIT, "%s: TXDP[%u] = %llx (%p) depth %d\n", __func__, - txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc, - txq->axq_depth); + txq->axq_qnum, (unsigned long long)bf->bf_daddr, + bf->bf_desc, txq->axq_depth); } else { *txq->axq_link = bf->bf_daddr; DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u](%p)=%llx (%p) depth %d\n", __func__, txq->axq_qnum, txq->axq_link, - ito64(bf->bf_daddr), bf->bf_desc, txq->axq_depth); + (unsigned long long)bf->bf_daddr, bf->bf_desc, + txq->axq_depth); } txq->axq_link = &bf->bf_desc->ds_link; /* @@ -4752,7 +4748,7 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) * for a single hardware transmit queue (e.g. 5210 and 5211). */ static void -ath_tx_tasklet_q0(TQUEUE_ARG data) +ath_tx_tasklet_q0(unsigned long data) { struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; @@ -4783,7 +4779,7 @@ ath_tx_tasklet_q0(TQUEUE_ARG data) * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). */ static void -ath_tx_tasklet_q0123(TQUEUE_ARG data) +ath_tx_tasklet_q0123(unsigned long data) { struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; @@ -4819,7 +4815,7 @@ ath_tx_tasklet_q0123(TQUEUE_ARG data) * Deferred processing of transmit interrupt. */ static void -ath_tx_tasklet(TQUEUE_ARG data) +ath_tx_tasklet(unsigned long data) { struct net_device *dev = (struct net_device *)data; struct ath_softc *sc = dev->priv; @@ -5739,7 +5735,7 @@ ath_printrxbuf(struct ath_buf *bf, int done) struct ath_desc *ds = bf->bf_desc; printk("R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", - ds, ito64(bf->bf_daddr), + ds, (unsigned long long)bf->bf_daddr, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1], @@ -5752,7 +5748,7 @@ ath_printtxbuf(struct ath_buf *bf, int done) struct ath_desc *ds = bf->bf_desc; printk("T (%p %llx) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", - ds, ito64(bf->bf_daddr), + ds, (unsigned long long)bf->bf_daddr, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], @@ -6257,7 +6253,8 @@ enum { }; static int -ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) +ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ath_softc *sc = ctl->extra1; struct ath_hal *ah = sc->sc_ah; @@ -6267,8 +6264,7 @@ ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) ctl->data = &val; ctl->maxlen = sizeof(val); if (write) { - ret = ATH_SYSCTL_PROC_DOINTVEC(ctl, write, filp, buffer, - lenp, ppos); + ret = proc_dointvec(ctl, write, filp, buffer, lenp, ppos); if (ret == 0) { switch (ctl->ctl_name) { case ATH_SLOTTIME: @@ -6373,7 +6369,7 @@ ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) ath_reset(&sc->sc_dev); break; case ATH_RADARSIM: - ATH_SCHEDULE_TQUEUE (&sc->sc_radartq, &needmark); + tasklet_schedule(&sc->sc_radartq); break; default: return -EINVAL; @@ -6456,8 +6452,7 @@ ATH_SYSCTL_DECL(ath_sysctl_halparam, ctl, write, filp, buffer, lenp, ppos) default: return -EINVAL; } - ret = ATH_SYSCTL_PROC_DOINTVEC(ctl, write, filp, buffer, - lenp, ppos); + ret = proc_dointvec(ctl, write, filp, buffer, lenp, ppos); } return ret; } diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 439749e..c5a7d24 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -305,6 +305,9 @@ ath_pci_resume(struct pci_dev *pdev) return (0); } +#else +#define ath_pci_suspend NULL +#define ath_pci_resume NULL #endif /* CONFIG_PM */ MODULE_DEVICE_TABLE(pci, ath_pci_id_table); @@ -313,12 +316,9 @@ static struct pci_driver ath_pci_drv_id = { .name = "ath_pci", .id_table = ath_pci_id_table, .probe = ath_pci_probe, - .remove = ath_pci_remove, -#ifdef CONFIG_PM + .remove = __devexit_p(ath_pci_remove), .suspend = ath_pci_suspend, .resume = ath_pci_resume, -#endif /* CONFIG_PM */ - /* Linux 2.4.6 has save_state and enable_wake that are not used here */ }; /* diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 7689ff5..cb707cd 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -42,83 +42,18 @@ #ifndef _DEV_ATH_ATHVAR_H #define _DEV_ATH_ATHVAR_H +#include +#include +#include + #include "ah.h" #include "if_athioctl.h" #include "if_athrate.h" -#include -#include - #ifndef ARPHRD_IEEE80211_RADIOTAP #define ARPHRD_IEEE80211_RADIOTAP 803 /* IEEE 802.11 + radiotap header */ #endif /* ARPHRD_IEEE80211_RADIOTAP */ -/* - * Deduce if tasklets are available. If not then - * fall back to using the immediate work queue. - */ -#include -#ifdef DECLARE_TASKLET /* native tasklets */ -#define tq_struct tasklet_struct -#define ATH_INIT_TQUEUE(a,b,c) tasklet_init((a),(b),(unsigned long)(c)) -#define ATH_SCHEDULE_TQUEUE(a,b) tasklet_schedule((a)) -typedef unsigned long TQUEUE_ARG; -#define mark_bh(a) -#else /* immediate work queue */ -#define ATH_INIT_TQUEUE(a,b,c) INIT_TQUEUE(a,b,c) -#define ATH_SCHEDULE_TQUEUE(a,b) do { \ - *(b) |= queue_task((a), &tq_immediate); \ -} while(0) -typedef void *TQUEUE_ARG; -#define tasklet_disable(t) do { (void) t; local_bh_disable(); } while (0) -#define tasklet_enable(t) do { (void) t; local_bh_enable(); } while (0) -#endif /* !DECLARE_TASKLET */ - -/* - * Guess how the interrupt handler should work. - */ -#if !defined(IRQ_NONE) -typedef void irqreturn_t; -#define IRQ_NONE -#define IRQ_HANDLED -#endif /* !defined(IRQ_NONE) */ - -#ifndef SET_MODULE_OWNER -#define SET_MODULE_OWNER(dev) do { \ - dev->owner = THIS_MODULE; \ -} while (0) -#endif - -#ifndef SET_NETDEV_DEV -#define SET_NETDEV_DEV(ndev, pdev) -#endif - - -/* - * Macro to expand scalars to 64-bit objects - */ -#define ito64(x) (sizeof(x)==8) ? (((unsigned long long int)(x)) & (0xff)) : \ - (sizeof(x)==16) ? (((unsigned long long int)(x)) & 0xffff) : \ - ((sizeof(x)==32) ? (((unsigned long long int)(x)) & 0xffffffff): (unsigned long long int)(x)) - - -/* - * Deal with the sysctl handler api changing. - */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) -#define ATH_SYSCTL_DECL(f, ctl, write, filp, buffer, lenp, ppos) \ - f(ctl_table *ctl, int write, struct file *filp, void *buffer, \ - size_t *lenp) -#define ATH_SYSCTL_PROC_DOINTVEC(ctl, write, filp, buffer, lenp, ppos) \ - proc_dointvec(ctl, write, filp, buffer, lenp) -#else /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) */ -#define ATH_SYSCTL_DECL(f, ctl, write, filp, buffer, lenp, ppos) \ - f(ctl_table *ctl, int write, struct file *filp, void __user *buffer,\ - size_t *lenp, loff_t *ppos) -#define ATH_SYSCTL_PROC_DOINTVEC(ctl, write, filp, buffer, lenp, ppos) \ - proc_dointvec(ctl, write, filp, buffer, lenp, ppos) -#endif - #define ATH_TIMEOUT 1000 /* @@ -331,14 +266,14 @@ struct ath_softc { } u_rx_rt; int sc_rx_th_len; - struct tq_struct sc_fataltq; /* fatal int tasklet */ - struct tq_struct sc_radartq; /* Radar detection */ + struct tasklet_struct sc_fataltq; /* fatal int tasklet */ + struct tasklet_struct sc_radartq; /* Radar detection */ int sc_rxbufsize; /* rx size based on mtu */ struct list_head *sc_rxbuf; /* receive buffer */ u32 *sc_rxlink; /* link ptr in last RX desc */ - struct tq_struct sc_rxtq; /* rx intr tasklet */ - struct tq_struct sc_rxorntq; /* rxorn intr tasklet */ + struct tasklet_struct sc_rxtq; /* rx intr tasklet */ + struct tasklet_struct sc_rxorntq; /* rxorn intr tasklet */ u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ @@ -349,7 +284,7 @@ struct ath_softc { u_int sc_txintrperiod;/* tx interrupt batching */ struct ath_txq sc_txq[AR5K_NUM_TX_QUEUES]; struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ - struct tq_struct sc_txtq; /* tx intr tasklet */ + struct tasklet_struct sc_txtq; /* tx intr tasklet */ struct list_head *sc_bbuf; /* beacon buffers */ u_int sc_bhalq; /* HAL q for outgoing beacons */ @@ -360,8 +295,8 @@ struct ath_softc { #ifdef BLE struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ #endif - struct tq_struct sc_bmisstq; /* bmiss intr tasklet */ - struct tq_struct sc_bstuckq; /* stuck beacon processing */ + struct tasklet_struct sc_bmisstq; /* bmiss intr tasklet */ + struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ enum { OK, /* no change needed */ UPDATE, /* update pending */ @@ -402,11 +337,7 @@ void ath_suspend(struct net_device *); *Port r1752 - Starting linux kernel v2.6.19 and later *interrupt handlers are not passed. */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) irqreturn_t ath_intr(int, void *); -#else -irqreturn_t ath_intr(int, void *, struct pt_regs *regs); -#endif void bus_read_cachesize(struct ath_softc *, u8 *); int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); commit 50b76de6e6c38b5bee038446e998aae8a3233df9 Author: Jiri Slaby Date: Sun Jun 17 23:10:44 2007 +0200 openhal/ath5k_hw.c cleanup diff --git a/openhal/ath5k.h b/openhal/ath5k.h index a3f8980..25949f0 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -925,8 +925,6 @@ struct ath5k_capabilities { * Misc defines */ -#define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0])) - struct ath_hal; typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 56962b2..3fd4cc2 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -36,9 +36,9 @@ */ static const struct { - u_int16_t vendor; - u_int16_t device; - u_int8_t mac_version; + u16 vendor; + u16 device; + u8 mac_version; } ath5k_known_products[] = { /* * From pcidevs_data.h @@ -79,11 +79,11 @@ static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -bool ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); -bool ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t, bool); -u_int16_t ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); +bool ath5k_hw_nic_reset(struct ath_hal *, u32); +bool ath5k_hw_nic_wakeup(struct ath_hal *, u16, bool); +u16 ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); void ath5k_hw_fill(struct ath_hal *); -bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, u_int); +bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, unsigned int); AR5K_HAL_FUNCTIONS(extern, ath5k_hw,); @@ -136,14 +136,14 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; * TODO:Left here for combatibility, change it in at5k */ const char * -ath_hal_probe(u_int16_t vendor, u_int16_t device) +ath_hal_probe(u16 vendor, u16 device) { int i; /* * Perform a linear search on the table of supported devices */ - for (i = 0; i < AR5K_ELEMENTS(ath5k_known_products); i++) { + for (i = 0; i < ARRAY_SIZE(ath5k_known_products); i++) { if (vendor == ath5k_known_products[i].vendor && device == ath5k_known_products[i].device){ switch (ath5k_known_products[i].mac_version) { @@ -154,12 +154,12 @@ ath_hal_probe(u_int16_t vendor, u_int16_t device) case AR5K_AR5212: return("AR5212"); default: - return (""); + return ""; } } } - return (NULL); + return NULL; } EXPORT_SYMBOL(ath_hal_probe); @@ -167,12 +167,12 @@ EXPORT_SYMBOL(ath_hal_probe); * Calculate transmition time of a frame * TODO: Left here for combatibility, change it in ath5k */ -u_int16_t /*TODO: Is this really hardware dependent ?*/ +u16 /*TODO: Is this really hardware dependent ?*/ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, - u_int32_t frame_length, u_int16_t rate_index, bool short_preamble) + u32 frame_length, u16 rate_index, bool short_preamble) { const struct ath5k_rate *rate; - u_int32_t value; + u32 value; AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); @@ -198,7 +198,7 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * Orthogonal Frequency Division Multiplexing */ if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); + return 0; value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length); break; @@ -208,7 +208,7 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * Atheros "Turbo Mode" (doubled rates) */ if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); + return 0; value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length); break; @@ -218,15 +218,15 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * Atheros "eXtended Range" (XR) */ if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); + return 0; value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length); break; default: - return (0); + return 0; } - return (value); + return value; } EXPORT_SYMBOL(ath_hal_computetxtime); @@ -234,14 +234,14 @@ EXPORT_SYMBOL(ath_hal_computetxtime); * Return the supported 802.11 operation modes * TODO:Left here for combatibility, change it in at5k */ -u_int/*TODO:Fix this */ +unsigned int/*TODO:Fix this */ ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) { switch(hal->ah_version){ case AR5K_AR5212: - return (AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G); + return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; case AR5K_AR5211: - return (AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G); + return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; default : return(AR5K_MODE_11A); } @@ -252,29 +252,29 @@ EXPORT_SYMBOL(ath_hal_getwirelessmodes); * Functions used internaly */ -static u_int32_t -ath5k_hw_bitswap(u_int32_t val, u_int bits) +static u32 +ath5k_hw_bitswap(u32 val, unsigned int bits) { - u_int32_t retval = 0, bit, i; + u32 retval = 0, bit, i; for (i = 0; i < bits; i++) { bit = (val >> i) & 1; retval = (retval << 1) | bit; } - return (retval); + return retval; } -inline u_int -ath5k_hw_htoclock(u_int usec, bool turbo) +inline unsigned int +ath5k_hw_htoclock(unsigned int usec, bool turbo) { - return (turbo == true ? (usec * 80) : (usec * 40)); + return turbo == true ? (usec * 80) : (usec * 40); } -inline u_int -ath5k_hw_clocktoh(u_int clock, bool turbo) +inline unsigned int +ath5k_hw_clocktoh(unsigned int clock, bool turbo) { - return (turbo == true ? (clock / 80) : (clock / 40)); + return turbo == true ? (clock / 80) : (clock / 40); } /* @@ -328,11 +328,11 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) * Check if a register write has been completed */ static bool -ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, - u_int32_t val, bool is_set) +ath5k_hw_register_timeout(struct ath_hal *hal, u32 reg, u32 flag, + u32 val, bool is_set) { int i; - u_int32_t data; + u32 data; for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { data = AR5K_REG_READ(reg); @@ -344,9 +344,9 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, } if (i <= 0) - return (false); + return false; - return (true); + return true; } @@ -362,10 +362,10 @@ struct ath_hal * ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) { struct ath_hal *hal = NULL; - u_int8_t mac[ETH_ALEN]; - u_int8_t mac_version = 255; /*Initialize this to something else than ath5k_version*/ + u8 mac[ETH_ALEN]; + u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ int i; - u_int32_t srev; + u32 srev; *status = AR5K_EINVAL; /*TODO:Use eeprom_magic to verify chipset*/ @@ -373,7 +373,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /* * Check if device is a known one */ - for (i = 0; i < AR5K_ELEMENTS(ath5k_known_products); i++) { + for (i = 0; i < ARRAY_SIZE(ath5k_known_products); i++) { if (device == ath5k_known_products[i].device) mac_version = ath5k_known_products[i].mac_version; } @@ -382,19 +382,17 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) if (mac_version == 255) { *status = AR5K_ENOTSUPP; AR5K_PRINTF("device not supported: 0x%04x\n", device); - return (NULL); + return NULL; } /*If we passed the test malloc a hal struct*/ - if ((hal = kmalloc(sizeof(struct ath_hal), GFP_KERNEL)) == NULL) { + hal = kzalloc(sizeof(struct ath_hal), GFP_KERNEL); + if (hal == NULL) { *status = AR5K_ENOMEM; AR5K_PRINT("out of memory\n"); - return (NULL); + return NULL; } - /*Initialize it*/ - memset(hal, 0, sizeof(struct ath_hal)); - hal->ah_sc = sc; hal->ah_sh = sh; hal->ah_device = device; @@ -553,20 +551,20 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) *status = AR5K_OK; - return (hal); + return hal; failed: kfree(hal); - return (NULL); + return NULL; } /* * Bring up MAC + PHY Chips */ bool -ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) +ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) { - u_int32_t turbo, mode, clock; + u32 turbo, mode, clock; turbo = 0; mode = 0; @@ -595,7 +593,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) clock |= AR5K_PHY_PLL_40MHZ; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (false); + return false; } if (flags & CHANNEL_CCK) { @@ -611,7 +609,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) mode |= AR5K_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (false); + return false; } if (flags & CHANNEL_TURBO) { @@ -630,17 +628,17 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI) == false) { AR5K_PRINT("failed to reset the PCI chipset\n"); - return (false); + return false; } - udelay(1000); + mdelay(1); } /* ...wakeup */ if (ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0) == false) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return (false); + return false; } /* ...enable Atheros turbo mode if requested */ @@ -650,17 +648,17 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) /* ...reset chipset */ if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == false) { AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return (false); + return false; } - udelay(1000); + mdelay(1); } /* ...reset chipset and PCI device */ if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == false) { AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); - return (false); + return false; } if (hal->ah_version == AR5K_AR5210) @@ -670,13 +668,13 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) if (ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0) == false) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return (false); + return false; } /* ...final warm reset */ if (ath5k_hw_nic_reset(hal, 0) == false) { AR5K_PRINT("failed to warm reset the MAC Chip\n"); - return (false); + return false; } if (hal->ah_version != AR5K_AR5210){ @@ -688,18 +686,18 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); } - return (true); + return true; } /* * Get the PHY Chip revision */ -u_int16_t +u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) { int i; - u_int32_t srev; - u_int16_t ret; + u32 srev; + u16 ret; AR5K_TRACE; @@ -714,10 +712,10 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); break; default: - return (0); + return 0; } - udelay(2000); + mdelay(2); /* ...wait until PHY is ready and read the selected radio revision */ AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16); @@ -728,17 +726,17 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) if (hal->ah_version == AR5K_AR5210) { srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf; - ret = (u_int16_t) ath5k_hw_bitswap(srev, 4) + 1; + ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; } else { srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff; - ret = (u_int16_t) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); } /* Reset to the 5GHz mode */ AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); - return (ret); + return ret; } /* @@ -746,27 +744,26 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) * TODO:Limit this per chipset */ const struct ath5k_rate_table * -ath5k_hw_get_rate_table(struct ath_hal *hal, u_int mode) +ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode) { - AR5K_TRACE; switch (mode) { case AR5K_MODE_11A: - return (&hal->ah_rt_11a); + return &hal->ah_rt_11a; case AR5K_MODE_TURBO: - return (&hal->ah_rt_turbo); + return &hal->ah_rt_turbo; case AR5K_MODE_11B: - return (&hal->ah_rt_11b); + return &hal->ah_rt_11b; case AR5K_MODE_11G: - return (&hal->ah_rt_11g); + return &hal->ah_rt_11g; case AR5K_MODE_XR: - return (&hal->ah_rt_xr); + return &hal->ah_rt_xr; default: - return (NULL); + return NULL; } - return (NULL); + return NULL; } /* @@ -780,9 +777,7 @@ ath5k_hw_detach(struct ath_hal *hal) if (hal->ah_rf_banks != NULL) kfree(hal->ah_rf_banks); - /* - * Free HAL structure, assume interrupts are down - */ + /* assume interrupts are down */ kfree(hal); } @@ -801,9 +796,9 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int8_t mac[ETH_ALEN]; - u_int32_t data, noise_floor, s_seq, s_ant, s_led[3]; - u_int i, phy, mode, freq, off, ee_mode, ant[2]; + u8 mac[ETH_ALEN]; + u32 data, noise_floor, s_seq, s_ant, s_led[3]; + unsigned int i, phy, mode, freq, off, ee_mode, ant[2]; const struct ath5k_rate_table *rt; AR5K_TRACE; @@ -841,7 +836,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /*Wakeup the device*/ if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) { *status = AR5K_EIO; - return (false); + return false; } /* @@ -861,7 +856,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, else { AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); *status = AR5K_EINVAL; - return (false); + return false; } switch (channel->channel_flags & CHANNEL_MODES) { @@ -894,7 +889,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, case CHANNEL_XR: if (hal->ah_version == AR5K_AR5211) { AR5K_PRINTF("XR mode not available on 5211"); - return (false); + return false; } mode = AR5K_INI_VAL_XR; freq = AR5K_INI_RFGAIN_5GHZ; @@ -903,7 +898,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, default: AR5K_PRINTF("invalid channel: %d\n", channel->freq); *status = AR5K_EINVAL; - return (false); + return false; } /* PHY access enable */ @@ -923,7 +918,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < AR5K_ELEMENTS(ar5212_mode); i++) { + for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) { if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) off = AR5K_INI_PHY_511X; else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && @@ -936,15 +931,15 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_mode[i].mode_register, + AR5K_REG_WRITE((u32)ar5212_mode[i].mode_register, ar5212_mode[i].mode_value[off][mode]); } } /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < AR5K_ELEMENTS(ar5211_mode); i++) { + for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, + AR5K_REG_WRITE((u32)ar5211_mode[i].mode_register, ar5211_mode[i].mode_value[mode]); } } @@ -955,7 +950,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) { + for (i = 0; i < ARRAY_SIZE(ar5212_ini); i++) { if (change_channel == true && ar5212_ini[i].ini_register >= AR5K_PCU_MIN && ar5212_ini[i].ini_register <= AR5K_PCU_MAX) @@ -966,27 +961,27 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, (hal->ah_radio == AR5K_RF5112 && ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_ini[i].ini_register, + AR5K_REG_WRITE((u32)ar5212_ini[i].ini_register, ar5212_ini[i].ini_value); } } } /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { + for (i = 0; i < ARRAY_SIZE(ar5211_ini); i++) { if (change_channel == true && ar5211_ini[i].ini_register >= AR5K_PCU_MIN && ar5211_ini[i].ini_register <= AR5K_PCU_MAX) continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, + AR5K_REG_WRITE((u32)ar5211_ini[i].ini_register, ar5211_ini[i].ini_value); } } /*For 5210*/ if (hal->ah_version == AR5K_AR5210) - for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) { + for (i = 0; i < ARRAY_SIZE(ar5210_ini); i++) { if (change_channel == true && ar5210_ini[i].ini_register >= AR5K_PCU_MIN && ar5210_ini[i].ini_register <= AR5K_PCU_MAX) @@ -1015,10 +1010,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_rfgain(hal, phy, freq) == false) { *status = AR5K_EIO; - return (false); + return false; } - udelay(1000); + mdelay(1); /* * Set rate duration table on 5212 @@ -1081,7 +1076,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER) == false) { *status = AR5K_EIO; - return (false); + return false; } /* @@ -1090,7 +1085,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_rfregs(hal, channel, mode) == false) { *status = AR5K_EINPROGRESS; - return (false); + return false; } /* @@ -1100,7 +1095,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /* Write OFDM timings on 5212*/ if (hal->ah_version == AR5K_AR5212) { if (channel->channel_flags & CHANNEL_OFDM) { - u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, + u32 coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man, clock; clock = channel->channel_flags & CHANNEL_T ? 80 : 40; @@ -1112,7 +1107,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (!coef_exp) { *status = AR5K_EINVAL; - return (false); + return false; } coef_exp = 14 - (coef_exp - 24); @@ -1193,10 +1188,10 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, } } else { - udelay(1000); + mdelay(1); /* Disable phy and wait */ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); - udelay(1000); + mdelay(1); } /* @@ -1245,7 +1240,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_channel(hal, channel) == false) { *status = AR5K_EIO; - return (false); + return false; } /* @@ -1263,7 +1258,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, udelay(100 + data); } else { - udelay(1000); + mdelay(1); } /* @@ -1276,7 +1271,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_CAL, 0, false) == false) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); - return (false); + return false; } /* @@ -1289,12 +1284,12 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return (false); + return false; } /* Wait until the noise floor is calibrated and read the value */ for (i = 20; i > 0; i--) { - udelay(1000); + mdelay(1); noise_floor = AR5K_REG_READ(AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & @@ -1308,7 +1303,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return (false); + return false; } hal->ah_calibration = false; @@ -1332,7 +1327,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_reset_tx_queue(hal, i) == false) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); *status = AR5K_EINVAL; - return (false); + return false; } } @@ -1375,17 +1370,17 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, AR5K_REG_DISABLE_BITS(AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); - return (true); + return true; } /* * Reset chipset */ bool -ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) +ath5k_hw_nic_reset(struct ath_hal *hal, u32 val) { bool ret = false; - u_int32_t mask = val ? val : ~0; + u32 mask = val ? val : ~0; AR5K_TRACE; @@ -1419,7 +1414,7 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) if ((val & AR5K_RESET_CTL_PCU) == 0) AR5K_REG_WRITE(AR5K_CFG, AR5K_INIT_CFG); - return (ret); + return ret; } /* @@ -1431,9 +1426,9 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) */ bool ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, - bool set_chip, u_int16_t sleep_duration) + bool set_chip, u16 sleep_duration) { - u_int32_t staid; + u32 staid; int i; AR5K_TRACE; @@ -1479,13 +1474,13 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, /* Fail if the chip didn't wake up */ if (i <= 0) - return (false); + return false; staid &= ~AR5K_STA_ID1_PWR_SV; break; default: - return (false); + return false; } commit: @@ -1493,7 +1488,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, AR5K_REG_WRITE(AR5K_STA_ID1, staid); - return (true); + return true; } /* @@ -1504,7 +1499,7 @@ enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal) { AR5K_TRACE; - return (hal->ah_power_mode); + return hal->ah_power_mode; } @@ -1547,23 +1542,23 @@ ath5k_hw_stop_rx_dma(struct ath_hal *hal) i--) udelay(10); - return (i > 0 ? true : false); + return i > 0 ? true : false; } /* * Get the address of the RX Descriptor */ -u_int32_t +u32 ath5k_hw_get_rx_buf(struct ath_hal *hal) { - return (AR5K_REG_READ(AR5K_RXDP)); + return AR5K_REG_READ(AR5K_RXDP); } /* * Set the address of the RX Descriptor */ void -ath5k_hw_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) +ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr) { AR5K_TRACE; @@ -1580,16 +1575,16 @@ ath5k_hw_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) * (see also QCU/DCU functions) */ bool -ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) +ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue) { - u_int32_t tx_queue; + u32 tx_queue; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; if (hal->ah_version == AR5K_AR5210) { @@ -1616,20 +1611,20 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) AR5K_BCR_BDMAE); break; default: - return (false); + return false; } /* Start queue */ AR5K_REG_WRITE(AR5K_CR, tx_queue); } else { /* Return if queue is disabled */ if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) - return (false); + return false; /* Start queue */ AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); } - return (true); + return true; } /* @@ -1637,17 +1632,17 @@ ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) +ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue) { int i = 100, pending; - u_int32_t tx_queue; + u32 tx_queue; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; if (hal->ah_version == AR5K_AR5210) { tx_queue = AR5K_REG_READ(AR5K_CR); @@ -1666,7 +1661,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) AR5K_REG_WRITE(AR5K_BSR, 0); break; default: - return (false); + return false; } /* Stop queue */ @@ -1689,17 +1684,17 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) } /*TODO: Check for success else return false*/ - return (true); + return true; } /* * Get the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) */ -u_int32_t -ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) +u32 +ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue) { - u_int16_t tx_reg; + u16 tx_reg; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1717,13 +1712,13 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) tx_reg = AR5K_NOQCU_TXDP1; break; default: - return (0xffffffff); + return 0xffffffff; } } else { tx_reg = AR5K_QUEUE_TXDP(queue); } - return (AR5K_REG_READ(tx_reg)); + return AR5K_REG_READ(tx_reg); } /* @@ -1731,9 +1726,9 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) +ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr) { - u_int16_t tx_reg; + u16 tx_reg; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1751,7 +1746,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) tx_reg = AR5K_NOQCU_TXDP1; break; default: - return (false); + return false; } } else { /* @@ -1760,7 +1755,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) * (this won't work if the queue is still active) */ if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) - return (false); + return false; tx_reg = AR5K_QUEUE_TXDP(queue); } @@ -1768,7 +1763,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) /* Set descriptor pointer */ AR5K_REG_WRITE(tx_reg, phys_addr); - return (true); + return true; } /* @@ -1777,7 +1772,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) bool ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) { - u_int32_t trigger_level, imr; + u32 trigger_level, imr; bool status = false; AR5K_TRACE; @@ -1814,7 +1809,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) */ ath5k_hw_set_intr(hal, imr); - return (status); + return status; } /* @@ -1828,16 +1823,16 @@ bool ath5k_hw_is_intr_pending(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_INTPEND) == true ? true : false); + return AR5K_REG_READ(AR5K_INTPEND) == true ? true : false; } /* * Get interrupt mask (ISR) */ bool -ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) +ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask) { - u_int32_t data; + u32 data; AR5K_TRACE; @@ -1848,7 +1843,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) if (hal->ah_version == AR5K_AR5210) { if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) { *interrupt_mask = data; - return (false); + return false; } } @@ -1863,7 +1858,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; if (data == AR5K_INT_NOCARD) - return (false); + return false; if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) *interrupt_mask |= AR5K_INT_RX; @@ -1885,7 +1880,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) * Special interrupt handling (not caught by the driver) */ if (((*interrupt_mask) & AR5K_ISR_RXPHY) && - hal->ah_radar.r_enabled == true) + hal->ah_radar.r_enabled == true) ath5k_radar_alert(hal); /* @@ -1900,21 +1895,21 @@ ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) * In case we didn't handle anything, * print the register value. */ - if (*interrupt_mask == 0) + if (*interrupt_mask == 0 && printk_ratelimit()) AR5K_PRINTF("0x%08x\n", data); - return (true); + return true; } /* * Return the interrupt mask stored previously * TODO: Remove ? */ -u_int32_t +u32 ath5k_hw_get_intr(struct ath_hal *hal) { AR5K_TRACE; - return (hal->ah_imr); + return hal->ah_imr; } /* @@ -1971,7 +1966,7 @@ ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) /* ..re-enable interrupts */ AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); - return (old_mask); + return old_mask; } /* @@ -2034,17 +2029,16 @@ bool ath5k_hw_eeprom_is_busy(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? - true : false); + return AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? true : false; } /* * Read from eeprom */ int -ath5k_hw_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) +ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data) { - u_int32_t status, timeout; + u32 status, timeout; AR5K_TRACE; /* @@ -2063,25 +2057,25 @@ ath5k_hw_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) - return (EIO); - *data = (u_int16_t) + return EIO; + *data = (u16) (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); - return (0); + return 0; } udelay(15); } - return (ETIMEDOUT); + return ETIMEDOUT; } /* * Write to eeprom - currently disabled, use at your own risk */ int -ath5k_hw_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) +ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data) { #if 0 - u_int32_t status, timeout; + u32 status, timeout; AR5K_TRACE; @@ -2115,23 +2109,23 @@ ath5k_hw_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_WRDONE) { if (status & AR5K_EEPROM_STAT_WRERR) - return (EIO); - return (0); + return EIO; + return 0; } udelay(15); } #endif AR5K_PRINTF("EEPROM Write is disabled!"); - return (ETIMEDOUT); + return ETIMEDOUT; } -u_int16_t -ath5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) +u16 +ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode) { - u_int16_t val; + u16 val; if (bin == AR5K_EEPROM_CHANNEL_DIS) - return (bin); + return bin; if (mode == AR5K_EEPROM_MODE_11A) { if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) @@ -2147,18 +2141,18 @@ ath5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) val = bin + 2400; } - return (val); + return val; } /* * Read antenna infos from eeprom */ int -ath5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) +ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t o = *offset; - u_int16_t val; + u32 o = *offset; + u16 val; int ret, i = 0; AR5K_EEPROM_READ(o++, val); @@ -2206,18 +2200,18 @@ ath5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) /* return new offset */ *offset = o; - return (0); + return 0; } /* * Read supported modes from eeprom */ int -ath5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) +ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t o = *offset; - u_int16_t val; + u32 o = *offset; + u16 val; int ret; AR5K_EEPROM_READ(o++, val); @@ -2290,7 +2284,7 @@ ath5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) /* return new offset */ *offset = o; - return (0); + return 0; } /* @@ -2300,10 +2294,10 @@ int ath5k_eeprom_init(struct ath_hal *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t offset; - u_int16_t val; + u32 offset; + u16 val; int ret, i; - u_int mode; + unsigned int mode; /* Initial TX thermal adjustment values */ ee->ee_tx_clip = 4; @@ -2321,7 +2315,7 @@ ath5k_eeprom_init(struct ath_hal *hal) /* Return if we have an old EEPROM */ if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) - return (0); + return 0; #ifdef notyet /* @@ -2334,7 +2328,7 @@ ath5k_eeprom_init(struct ath_hal *hal) } if (cksum != AR5K_EEPROM_INFO_CKSUM) { AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); - return (AR5K_EEBADSUM); + return AR5K_EEBADSUM; } #endif @@ -2379,10 +2373,10 @@ ath5k_eeprom_init(struct ath_hal *hal) offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); + return ret; AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); ee->ee_ob[mode][3] = (val >> 5) & 0x7; ee->ee_db[mode][3] = (val >> 2) & 0x7; ee->ee_ob[mode][2] = (val << 1) & 0x7; @@ -2396,7 +2390,7 @@ ath5k_eeprom_init(struct ath_hal *hal) ee->ee_db[mode][0] = val & 0x7; if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); + return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { AR5K_EEPROM_READ(offset++, val); @@ -2410,15 +2404,15 @@ ath5k_eeprom_init(struct ath_hal *hal) offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); + return ret; AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); + return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); @@ -2443,15 +2437,15 @@ ath5k_eeprom_init(struct ath_hal *hal) offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); + return ret; AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); + return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); @@ -2486,30 +2480,30 @@ ath5k_eeprom_init(struct ath_hal *hal) * Read 5GHz EEPROM channels */ - return (0); + return 0; } /* * Read the MAC address from eeprom */ int -ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) +ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) { - u_int32_t total, offset; - u_int16_t data; + u32 total, offset; + u16 data; int octet; - u_int8_t mac_d[ETH_ALEN]; + u8 mac_d[ETH_ALEN]; memset(mac, 0, ETH_ALEN); memset(&mac_d, 0, ETH_ALEN); if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) - return (AR5K_EIO); + return AR5K_EIO; for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { if (hal->ah_eeprom_read(hal, offset, &data) != 0) - return (AR5K_EIO); + return AR5K_EIO; total += data; mac_d[octet + 1] = data & 0xff; @@ -2520,9 +2514,9 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) memcpy(mac, mac_d, ETH_ALEN); if ((!total) || total == (3 * 0xffff)) - return (AR5K_EINVAL); + return AR5K_EINVAL; - return (0); + return 0; } /* @@ -2532,13 +2526,13 @@ bool ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, ieee80211_regdomain_t *regdomain) { - u_int16_t ee_regdomain; + u16 ee_regdomain; /* Read current value */ if (write != true) { ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; *regdomain = ath5k_regdomain_to_ieee(ee_regdomain); - return (true); + return true; } ee_regdomain = ath5k_regdomain_from_ieee(*regdomain); @@ -2546,36 +2540,35 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, /* Try to write a new value */ if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_EEPROM_PROTECT_WR_128_191) - return (false); + return false; if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain) != 0) - return (false); + return false; hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; - return (true); + return true; } /* * Use the above to write a new regulatory domain */ bool -ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - enum ath5k_status *status) +ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, + enum ath5k_status *status) { ieee80211_regdomain_t ieee_regdomain; ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); - if (ath5k_eeprom_regulation_domain(hal, true, - &ieee_regdomain) == true) { + if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true){ *status = AR5K_OK; - return (true); + return true; } *status = AR5K_EIO; - return (false); + return false; } /* @@ -2584,7 +2577,7 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, bool ath5k_hw_get_capabilities(struct ath_hal *hal) { - u_int16_t ee_header; + u16 ee_header; AR5K_TRACE; /* Capabilities stored in the EEPROM */ @@ -2648,12 +2641,9 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) else hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; - return (true); + return true; } - - - /*********************************\ Protocol Control Unit Functions \*********************************/ @@ -2664,7 +2654,7 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) void ath5k_hw_set_opmode(struct ath_hal *hal) { - u_int32_t pcu_reg, beacon_reg, low_id, high_id; + u32 pcu_reg, beacon_reg, low_id, high_id; pcu_reg = 0; beacon_reg = 0; @@ -2713,8 +2703,6 @@ ath5k_hw_set_opmode(struct ath_hal *hal) */ if (hal->ah_version == AR5K_AR5210) AR5K_REG_WRITE(AR5K_BCR, beacon_reg); - - return; } void /*TODO: Get rid of this, clean up the driver code, only set_opmode is needed*/ @@ -2722,7 +2710,6 @@ ath5k_hw_set_pcu_config(struct ath_hal *hal) { AR5K_TRACE; ath5k_hw_set_opmode(hal); - return; } /* @@ -2733,7 +2720,7 @@ ath5k_hw_set_pcu_config(struct ath_hal *hal) * Get station id */ void -ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) +ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac) { AR5K_TRACE; memcpy(mac, hal->ah_sta_id, ETH_ALEN); @@ -2743,9 +2730,9 @@ ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) * Set station id */ bool -ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) +ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac) { - u_int32_t low_id, high_id; + u32 low_id, high_id; AR5K_TRACE; /* Set new station ID */ @@ -2757,18 +2744,18 @@ ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) AR5K_REG_WRITE(AR5K_STA_ID0, low_id); AR5K_REG_WRITE(AR5K_STA_ID1, high_id); - return (true); + return true; } /* * Set BSSID */ void -ath5k_hw_set_associd(struct ath_hal *hal, const u_int8_t *bssid, - u_int16_t assoc_id) +ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, + u16 assoc_id) { - u_int32_t low_id, high_id; - u_int16_t tim_offset = 0; + u32 low_id, high_id; + u16 tim_offset = 0; /* * Set simple BSSID mask on 5212 @@ -2803,9 +2790,9 @@ ath5k_hw_set_associd(struct ath_hal *hal, const u_int8_t *bssid, * Set BSSID mask on 5212 */ bool -ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) +ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask) { - u_int32_t low_id, high_id; + u32 low_id, high_id; AR5K_TRACE; if (hal->ah_version == AR5K_AR5212) { @@ -2816,9 +2803,9 @@ ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) AR5K_REG_WRITE(AR5K_BSS_IDM0, low_id); AR5K_REG_WRITE(AR5K_BSS_IDM1, high_id); - return (true); + return true; } else - return (false); + return false; } /* @@ -2853,8 +2840,8 @@ ath5k_hw_stop_pcu_recv(struct ath_hal *hal) * Set multicast filter */ void -ath5k_hw_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, - u_int32_t filter1) +ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, + u32 filter1) { AR5K_TRACE; /* Set the multicat filter */ @@ -2866,12 +2853,12 @@ ath5k_hw_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, * Set multicast filter by index */ bool -ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) +ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index) { AR5K_TRACE; if (index >= 64) - return (false); + return false; else if (index >= 32) AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1, (1 << (index - 32))); @@ -2879,19 +2866,19 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0, (1 << index)); - return (true); + return true; } /* * Clear Multicast filter by index */ bool -ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) +ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index) { AR5K_TRACE; if (index >= 64) - return (false); + return false; else if (index >= 32) AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1, (1 << (index - 32))); @@ -2899,16 +2886,16 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0, (1 << index)); - return (true); + return true; } /* * Get current rx filter */ -u_int32_t +u32 ath5k_hw_get_rx_filter(struct ath_hal *hal) { - u_int32_t data, filter = 0; + u32 data, filter = 0; AR5K_TRACE; filter = AR5K_REG_READ(AR5K_RX_FILTER); @@ -2924,16 +2911,16 @@ ath5k_hw_get_rx_filter(struct ath_hal *hal) filter |= AR5K_RX_FILTER_PHYERR; } - return (filter); + return filter; } /* * Set rx filter */ void -ath5k_hw_set_rx_filter(struct ath_hal *hal, u_int32_t filter) +ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter) { - u_int32_t data = 0; + u32 data = 0; AR5K_TRACE; @@ -2979,23 +2966,23 @@ ath5k_hw_set_rx_filter(struct ath_hal *hal, u_int32_t filter) /* * Get a 32bit TSF */ -u_int32_t +u32 ath5k_hw_get_tsf32(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_TSF_L32)); + return AR5K_REG_READ(AR5K_TSF_L32); } /* * Get the full 64bit TSF */ -u_int64_t +u64 ath5k_hw_get_tsf64(struct ath_hal *hal) { - u_int64_t tsf = AR5K_REG_READ(AR5K_TSF_U32); + u64 tsf = AR5K_REG_READ(AR5K_TSF_U32); AR5K_TRACE; - return (AR5K_REG_READ(AR5K_TSF_L32) | (tsf << 32)); + return AR5K_REG_READ(AR5K_TSF_L32) | (tsf << 32); } /* @@ -3013,10 +3000,10 @@ ath5k_hw_reset_tsf(struct ath_hal *hal) * Initialize beacon timers */ void -ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, - u_int32_t interval) +ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, + u32 interval) { - u_int32_t timer1, timer2, timer3; + u32 timer1, timer2, timer3; AR5K_TRACE; /* @@ -3063,7 +3050,7 @@ ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, void ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state) { - u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; + u32 cfp_period, next_cfp, dtim, interval, next_beacon; /* * TODO: should be changed through *state @@ -3073,9 +3060,9 @@ ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state * ok ? Is it O.K. for tsf here to be 0 or should we use * get_tsf ? */ - u_int32_t dtim_count = 0; /* XXX */ - u_int32_t cfp_count = 0; /* XXX */ - u_int32_t tsf = 0; /* XXX */ + u32 dtim_count = 0; /* XXX */ + u32 cfp_count = 0; /* XXX */ + u32 tsf = 0; /* XXX */ AR5K_TRACE; /* Return on an invalid beacon state */ @@ -3234,7 +3221,7 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, phys_addr); AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE); - return (false); + return false; } ret= true; @@ -3245,10 +3232,10 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) AR5K_QCU_STS_FRMPENDCNT, 0, false); if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) - return (false); + return false; } - return (ret); + return ret; } /* @@ -3278,7 +3265,6 @@ void /*Unimplemented*/ ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; - return; } /* @@ -3289,23 +3275,23 @@ ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stat * Set ACK timeout on PCU */ bool -ath5k_hw_set_ack_timeout(struct ath_hal *hal, u_int timeout) +ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), hal->ah_turbo) <= timeout) - return (false); + return false; AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_htoclock(timeout, hal->ah_turbo)); - return (true); + return true; } /* * Read the ACK timeout from PCU */ -u_int +unsigned int ath5k_hw_get_ack_timeout(struct ath_hal *hal) { AR5K_TRACE; @@ -3317,23 +3303,23 @@ ath5k_hw_get_ack_timeout(struct ath_hal *hal) * Set CTS timeout on PCU */ bool -ath5k_hw_set_cts_timeout(struct ath_hal *hal, u_int timeout) +ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), hal->ah_turbo) <= timeout) - return (false); + return false; AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_htoclock(timeout, hal->ah_turbo)); - return (true); + return true; } /* * Read CTS timeout from PCU */ -u_int +unsigned int ath5k_hw_get_cts_timeout(struct ath_hal *hal) { AR5K_TRACE; @@ -3356,26 +3342,26 @@ ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) * Only WEP for now */ if (cipher == AR5K_CIPHER_WEP) - return (true); + return true; - return (false); + return false; } /* * Get key cache size */ -u_int32_t +u32 ath5k_hw_get_keycache_size(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_KEYCACHE_SIZE); + return AR5K_KEYCACHE_SIZE; } /* * Reset encryption key */ bool -ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) +ath5k_hw_reset_key(struct ath_hal *hal, u16 entry) { int i; @@ -3390,14 +3376,14 @@ ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), AR5K_KEYTABLE_TYPE_NULL); - return (false); /*????*/ + return false; /*????*/ } /* * Check if a key entry is valid */ bool -ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) +ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry) { AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); @@ -3407,20 +3393,20 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) */ if (AR5K_REG_READ(AR5K_KEYTABLE_MAC1(entry)) & AR5K_KEYTABLE_VALID) - return (true); + return true; - return (false); + return false; } /* * Set encryption key */ bool -ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, - const struct ath5k_keyval *keyval, const u_int8_t *mac, int xor_notused) +ath5k_hw_set_key(struct ath_hal *hal, u16 entry, + const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused) { int i; - u_int32_t key_v[AR5K_KEYCACHE_SIZE - 2]; + u32 key_v[AR5K_KEYCACHE_SIZE - 2]; AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); @@ -3454,20 +3440,20 @@ ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, default: /* Unsupported key length (not WEP40/104/128) */ - return (false); + return false; } - for (i = 0; i < AR5K_ELEMENTS(key_v); i++) + for (i = 0; i < ARRAY_SIZE(key_v); i++) AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), key_v[i]); - return (ath5k_hw_set_key_lladdr(hal, entry, mac)); + return ath5k_hw_set_key_lladdr(hal, entry, mac); } bool -ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, - const u_int8_t *mac) +ath5k_hw_set_key_lladdr(struct ath_hal *hal, u16 entry, + const u8 *mac) { - u_int32_t low_id, high_id; + u32 low_id, high_id; AR5K_TRACE; /* Invalid entry (key table overflow) */ @@ -3487,7 +3473,7 @@ ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id); - return (true); + return true; } @@ -3504,7 +3490,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info) { - u_int queue; + unsigned int queue; AR5K_TRACE; /* @@ -3521,7 +3507,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; break; default: - return (-1); + return -1; } } else { switch (queue_type) { @@ -3531,7 +3517,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, AR5K_TX_QUEUE_INACTIVE; queue++) { if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) - return (-1); + return -1; } break; case AR5K_TX_QUEUE_UAPSD: @@ -3549,7 +3535,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, queue = AR5K_TX_QUEUE_ID_XR_DATA; break; default: - return (-1); + return -1; } } @@ -3563,7 +3549,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, queue_info->tqi_type = queue_type; if (ath5k_hw_setup_tx_queueprops(hal, queue, queue_info) != true) - return (-1); + return -1; } /* * We use ah_txq_interrupts to hold a temp value for @@ -3572,7 +3558,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, */ AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); - return (queue); + return queue; } /* @@ -3586,7 +3572,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); @@ -3598,7 +3584,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - return (true); + return true; } /* @@ -3609,14 +3595,14 @@ ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info { AR5K_TRACE; memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); - return (true); + return true; } /* * Set a transmit queue inactive */ bool -ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) +ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3626,16 +3612,16 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) /*For SIMR setup*/ AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - return (false); /*???*/ + return false; /*???*/ } /* * Set DFS params for a transmit queue */ bool -ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) +ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue) { - u_int32_t cw_min, cw_max, retry_lg, retry_sh; + u32 cw_min, cw_max, retry_lg, retry_sh; struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; struct ath5k_ar5210_ini_mode ar5210_mode[] = @@ -3647,18 +3633,18 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) tq = &hal->ah_txq[queue]; if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (true); + return true; if (hal->ah_version == AR5K_AR5210) { /* Only handle data queues, others will be ignored */ if (tq->tqi_type != AR5K_TX_QUEUE_DATA) - return (true); + return true; /* * Write initial mode register settings */ - for (i = 0; i < AR5K_ELEMENTS(ar5210_mode); i++) - AR5K_REG_WRITE((u_int32_t)ar5210_mode[i].mode_register, + for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++) + AR5K_REG_WRITE((u32)ar5210_mode[i].mode_register, hal->ah_turbo == true ? ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base); } @@ -3845,38 +3831,38 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); } - return (true); + return true; } /* * Get number of pending frames * for a specific queue [5211+] */ -u_int32_t -ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) { +u32 +ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (false); + return false; /* XXX: How about AR5K_CFG_TXCNT ? */ if (hal->ah_version == AR5K_AR5210) - return (false); + return false; - return (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT); + return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT; } /* * Set slot time */ bool -ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) +ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time) { AR5K_TRACE; if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) - return (false); + return false; if (hal->ah_version == AR5K_AR5210) AR5K_REG_WRITE(AR5K_SLOT_TIME, @@ -3884,13 +3870,13 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) else AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); - return (true); + return true; } /* * Get slot time */ -u_int +unsigned int ath5k_hw_get_slot_time(struct ath_hal *hal) { AR5K_TRACE; @@ -3898,7 +3884,7 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) return (ath5k_hw_clocktoh(AR5K_REG_READ(AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo)); else - return (AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff); + return AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff; } @@ -3917,11 +3903,11 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) */ static bool ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, - u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - u_int flags, u_int rtscts_rate, u_int rtscts_duration) + unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, + unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, + unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) { - u_int32_t frame_type; + u32 frame_type; struct ath5k_hw_2w_tx_desc *tx_desc; tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; @@ -3930,7 +3916,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Validate input */ if (tx_tries0 == 0) - return (false); + return false; /* Initialize control descriptor */ tx_desc->tx_control_0 = 0; @@ -3941,7 +3927,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /*Verify packet length*/ if ((tx_desc->tx_control_0 = (packet_length & AR5K_2W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return (false); + return false; /* * Verify header length * XXX: I only found that on 5210 code, does it work on 5211 ? @@ -3949,7 +3935,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (hal->ah_version == AR5K_AR5210) if ((tx_desc->tx_control_0 = (header_length & AR5K_2W_TX_DESC_CTL0_HEADER_LEN)) != header_length) - return (false); + return false; /*Diferences between 5210-5211*/ if (hal->ah_version == AR5K_AR5210) { @@ -4006,7 +3992,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; } - return (true); + return true; } /* @@ -4014,9 +4000,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, - u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - u_int flags, u_int rtscts_rate, u_int rtscts_duration) + unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, + unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, + unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4028,7 +4014,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Validate input */ if (tx_tries0 == 0) - return (false); + return false; /* Initialize status descriptor */ tx_desc->tx_control_0 = 0; @@ -4039,7 +4025,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Setup status descriptor */ if ((tx_desc->tx_control_0 = (packet_length & AR5K_4W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return (false); + return false; tx_desc->tx_control_0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | @@ -4083,7 +4069,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { if ((flags & AR5K_TXDESC_RTSENA) && (flags & AR5K_TXDESC_CTSENA)) - return (false); + return false; tx_desc->tx_control_2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION; tx_desc->tx_control_3 |= @@ -4091,7 +4077,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); } - return (true); + return true; } /* @@ -4099,8 +4085,8 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - u_int tx_rate3, u_int tx_tries3) + unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, + unsigned int tx_rate3, u_int tx_tries3) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4123,7 +4109,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, #undef _XTX_TRIES - return (true); + return true; } return(false); @@ -4134,7 +4120,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) + unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4146,7 +4132,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_2W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return (false); + return false; if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN; @@ -4154,7 +4140,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (last_segment != true) tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE; - return (true); + return true; } /* @@ -4163,7 +4149,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static bool ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, bool first_segment, bool last_segment, + unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4179,7 +4165,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_4W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return (false); + return false; if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN; @@ -4187,7 +4173,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, if (last_segment != true) tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE; - return (true); + return true; } /* @@ -4204,7 +4190,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Get descriptor status @@ -4246,7 +4232,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return (AR5K_OK); + return AR5K_OK; } /* @@ -4264,7 +4250,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Get descriptor status @@ -4335,7 +4321,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return (AR5K_OK); + return AR5K_OK; } /* @@ -4347,7 +4333,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) */ bool ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t size, u_int flags) + u32 size, unsigned int flags) { struct ath5k_rx_desc *rx_desc; @@ -4370,12 +4356,12 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, /*Setup descriptor*/ if ((rx_desc->rx_control_1 = (size & AR5K_DESC_RX_CTL1_BUF_LEN)) != size) - return (false); + return false; if (flags & AR5K_RXDESC_INTREQ) rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; - return (true); + return true; } /* @@ -4383,7 +4369,7 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, */ static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) + u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_old_rx_status *rx_status; @@ -4391,7 +4377,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Frame receive status @@ -4450,7 +4436,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; } - return (AR5K_OK); + return AR5K_OK; } /* @@ -4458,7 +4444,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, */ static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) + u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_new_rx_status *rx_status; struct ath5k_hw_rx_error *rx_err; @@ -4471,7 +4457,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); + return AR5K_EINPROGRESS; /* * Frame receive status @@ -4530,7 +4516,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } - return (AR5K_OK); + return AR5K_OK; } @@ -4546,9 +4532,9 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, void ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) { - u_int32_t led; + u32 led; /*5210 has different led mode handling*/ - u_int32_t led_5210; + u32 led_5210; AR5K_TRACE; @@ -4603,45 +4589,45 @@ ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) * Set GPIO outputs */ bool -ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) +ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (false); + return false; AR5K_REG_WRITE(AR5K_GPIOCR, (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio)); - return (true); + return true; } /* * Set GPIO inputs */ bool -ath5k_hw_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) +ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (false); + return false; AR5K_REG_WRITE(AR5K_GPIOCR, (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio)); - return (true); + return true; } /* * Get GPIO state */ -u_int32_t -ath5k_hw_get_gpio(struct ath_hal *hal, u_int32_t gpio) +u32 +ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (0xffffffff); + return 0xffffffff; /* GPIO input magic */ return (((AR5K_REG_READ(AR5K_GPIODI) & @@ -4652,13 +4638,13 @@ ath5k_hw_get_gpio(struct ath_hal *hal, u_int32_t gpio) * Set GPIO state */ bool -ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) +ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val) { - u_int32_t data; + u32 data; AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return (false); + return false; /* GPIO output magic */ data = AR5K_REG_READ(AR5K_GPIODO); @@ -4668,17 +4654,17 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) AR5K_REG_WRITE(AR5K_GPIODO, data); - return (true); + return true; } /* * Initialize the GPIO interrupt (RFKill switch) */ void -ath5k_hw_set_gpio_intr(struct ath_hal *hal, u_int gpio, - u_int32_t interrupt_level) +ath5k_hw_set_gpio_intr(struct ath_hal *hal, unsigned int gpio, + u32 interrupt_level) { - u_int32_t data; + u32 data; AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4719,8 +4705,8 @@ ath5k_hw_set_gpio_intr(struct ath_hal *hal, u_int gpio, /* * Convert MHz frequency to IEEE channel number. */ -u_int -ath_hal_mhz2ieee(u_int freq, u_int flags) +unsigned int +ath_hal_mhz2ieee(unsigned int freq, u_int flags) { if (flags & CHANNEL_2GHZ) { /* 2GHz band */ if (freq == 2484) /* Japan */ @@ -4745,8 +4731,8 @@ EXPORT_SYMBOL(ath_hal_mhz2ieee); /* * Convert IEEE channel number to MHz frequency. */ -u_int -ath_hal_ieee2mhz(u_int chan, u_int flags) +unsigned int +ath_hal_ieee2mhz(unsigned int chan, u_int flags) { if (flags & CHANNEL_2GHZ) { /* 2GHz band */ if (chan == 14) @@ -4773,19 +4759,19 @@ EXPORT_SYMBOL(ath_hal_ieee2mhz); * Check if a channel is supported */ bool -ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) +ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags) { /* Check if the channel is in our supported range */ if (flags & CHANNEL_2GHZ) { if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) - return (true); + return true; } else if (flags & CHANNEL_5GHZ) if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) - return (true); + return true; - return (false); + return false; } /* @@ -4795,18 +4781,18 @@ ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) */ bool ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, - u_int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u_int16_t mode, + unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended) { - u_int i, c; - u_int32_t domain_current; - u_int domain_5ghz, domain_2ghz; + unsigned int i, c; + u32 domain_current; + unsigned int domain_5ghz, domain_2ghz; struct ath5k_channel *all_channels; enum ieee80211_countrycode country_current; if ((all_channels = kmalloc(sizeof(struct ath5k_channel) * max_channels, GFP_KERNEL)) == NULL) - return (false); + return false; i = c = 0; domain_current = hal->ah_regdomain; @@ -4818,7 +4804,7 @@ ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, */ if (domain_current == DMN_DEFAULT || CHAN_DEBUG == 1) { int min, max, freq; - u_int flags; + unsigned int flags; min = 1; /* 2GHz channel 1 -2412Mhz */ max = 26;/* 2GHz channel 26 (non-ieee) -2732Mhz */ @@ -4861,7 +4847,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ * and mode. 5GHz... */ for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && - (i < AR5K_ELEMENTS(ath5k_5ghz_channels)) && + (i < ARRAY_SIZE(ath5k_5ghz_channels)) && (c < max_channels); i++) { /* Check if channel is supported by the chipset */ if (ath5k_check_channel(hal, @@ -4891,7 +4877,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ * ...and 2GHz. */ for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && - (i < AR5K_ELEMENTS(ath5k_2ghz_channels)) && + (i < ARRAY_SIZE(ath5k_2ghz_channels)) && (c < max_channels); i++) { /* Check if channel is supported by the chipset */ @@ -4926,7 +4912,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ memcpy(channels, all_channels, sizeof(struct ath5k_channel) * max_channels); *channels_size = c; kfree(all_channels); - return (true); + return true; } EXPORT_SYMBOL(ath_hal_init_channels); @@ -4934,10 +4920,10 @@ EXPORT_SYMBOL(ath_hal_init_channels); * Regdomain stuff, these also don't belong here etc */ -u_int16_t +u16 ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) { - u_int32_t regdomain = (u_int32_t)ieee; + u32 regdomain = (u32)ieee; /* * Use the default regulation domain if the value is empty @@ -4945,27 +4931,27 @@ ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) */ if (ieee80211_regdomain2flag(regdomain, IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) - return ((u_int16_t)AR5K_TUNE_REGDOMAIN); + return (u16)AR5K_TUNE_REGDOMAIN; /* It is supported, just return the value */ - return (regdomain); + return regdomain; } ieee80211_regdomain_t -ath5k_regdomain_to_ieee(u_int16_t regdomain) +ath5k_regdomain_to_ieee(u16 regdomain) { ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; - return (ieee); + return ieee; } -u_int16_t +u16 ath5k_get_regdomain(struct ath_hal *hal) { - u_int16_t regdomain; + u16 regdomain; ieee80211_regdomain_t ieee_regdomain; #ifdef COUNTRYCODE - u_int16_t code; + u16 code; #endif ath5k_eeprom_regulation_domain(hal, false, &ieee_regdomain); @@ -4983,14 +4969,14 @@ ath5k_get_regdomain(struct ath_hal *hal) regdomain = ath5k_regdomain_from_ieee(ieee_regdomain); hal->ah_capabilities.cap_regdomain.reg_current = regdomain; - return (regdomain); + return regdomain; } -u_int16_t /*TODO:Get rid of this*/ +u16 /*TODO:Get rid of this*/ ath5k_hw_get_regdomain(struct ath_hal *hal) { AR5K_TRACE; - return (ath5k_get_regdomain(hal)); + return ath5k_get_regdomain(hal); } @@ -5018,7 +5004,7 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { AR5K_PRINTF("channel out of supported range (%u MHz)\n", channel->freq); - return (false); + return false; } /* @@ -5032,23 +5018,23 @@ ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) ret = ath5k_hw_rf5112_channel(hal, channel); if (ret == false) - return (ret); + return ret; hal->ah_current_channel.freq = channel->freq; hal->ah_current_channel.channel_flags = channel->channel_flags; hal->ah_turbo = channel->channel_flags == CHANNEL_T ? true : false; - return (true); + return true; } /* * Convertion needed for RF5110 */ -u_int32_t +u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) { - u_int32_t athchan; + u32 athchan; /* * Convert IEEE channel/MHz to an internal channel value used @@ -5060,7 +5046,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) channel->channel_flags) - 24) / 2, 5) << 1) | (1 << 6) | 0x1; - return (athchan); + return athchan; } /* @@ -5069,7 +5055,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) bool ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int32_t data; + u32 data; /* * Set the channel and wait @@ -5079,14 +5065,14 @@ ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x30, 0); udelay(1000); - return (true); + return true; } /* * Convertion needed for 5111 */ bool -ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) +ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan) { int channel; @@ -5106,9 +5092,9 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) athchan->a2_athchan = ((channel - 14) * 4) + 132; athchan->a2_flags = 0x46; } else - return (false); + return false; - return (true); + return true; } /* @@ -5117,8 +5103,8 @@ ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) bool ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int ieee_channel, ath_channel; - u_int32_t data0, data1, clock; + unsigned int ieee_channel, ath_channel; + u32 data0, data1, clock; struct ath5k_athchan_2ghz ath_channel_2ghz; /* @@ -5132,7 +5118,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) /* Map 2GHz channel to 5GHz Atheros channel ID */ if (ath5k_hw_rf5111_chan2athchan(ieee_channel, &ath_channel_2ghz) == false) - return (false); + return false; ath_channel = ath_channel_2ghz.a2_athchan; data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) @@ -5152,7 +5138,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); - return (true); + return true; } /* @@ -5161,8 +5147,8 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) bool ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int32_t data, data0, data1, data2; - u_int16_t c; + u32 data, data0, data1, data2; + u16 c; data = data0 = data1 = data2 = 0; c = channel->freq; @@ -5178,7 +5164,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) data0 = ((2 * (c - 672)) - 3040) / 10; data1 = 0; } else - return (false); + return false; data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); } else { @@ -5192,7 +5178,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); data2 = ath5k_hw_bitswap(1, 2); } else - return (false); + return false; } data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; @@ -5200,7 +5186,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_WRITE(0x27, data & 0xff); AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); - return (true); + return true; } /* @@ -5216,7 +5202,7 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ else ret = ath5k_hw_rf511x_calibrate(hal,channel); - return (ret); + return ret; } /* * Perform a PHY calibration on RF5110 @@ -5225,8 +5211,8 @@ bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { bool ret = true; - u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor; - u_int i; + u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; + unsigned int i; #define AGC_DISABLE { \ AR5K_REG_ENABLE_BITS(AR5K_PHY_AGC, \ @@ -5264,7 +5250,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AGC_ENABLE; if (ret == false) - return (ret); + return ret; /* * Calibrate the radio chip @@ -5319,7 +5305,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat); if (ret == false) - return (false); + return false; /* * Enable noise floor calibration and wait until completion @@ -5331,7 +5317,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return (false); + return false; } /* Wait until the noise floor is calibrated */ @@ -5350,7 +5336,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return (false); + return false; } @@ -5364,7 +5350,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) #undef AGC_ENABLE #undef AGC_DISABLE - return (true); + return true; } /* @@ -5373,8 +5359,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) { - u_int32_t i_pwr, q_pwr; - int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; + u32 i_pwr, q_pwr; + s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; AR5K_TRACE; if (hal->ah_calibration == false || @@ -5393,13 +5379,13 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) goto done; i_coff = ((-iq_corr) / i_coffd) & 0x3f; - q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; + q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; /* Commit new IQ value */ AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | - ((u_int32_t)q_coff) | - ((u_int32_t)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + ((u32)q_coff) | + ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); done: /* Start noise floor calibration */ @@ -5415,7 +5401,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } - return (true); + return true; } bool @@ -5424,21 +5410,19 @@ ath5k_hw_phy_disable(struct ath_hal *hal) AR5K_TRACE; /*Just a try M.F.*/ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); - return (true); + return true; } void /*TODO:Boundary check*/ -ath5k_hw_set_def_antenna(struct ath_hal *hal, u_int ant) +ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant) { AR5K_TRACE; /*Just a try M.F.*/ if (hal->ah_version != AR5K_AR5210) AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant); - - return; } -u_int +unsigned int ath5k_hw_get_def_antenna(struct ath_hal *hal) { AR5K_TRACE; @@ -5446,26 +5430,26 @@ ath5k_hw_get_def_antenna(struct ath_hal *hal) if (hal->ah_version != AR5K_AR5210) return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); - return (false); /*XXX: What do we return for 5210 ?*/ + return false; /*XXX: What do we return for 5210 ?*/ } -u_int -ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, - u_int32_t first, u_int32_t col, bool set) +unsigned int +ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, + u32 first, u32 col, bool set) { - u_int32_t mask, entry, last, data, shift, position; - int32_t left; + u32 mask, entry, last, data, shift, position; + s32 left; int i; data = 0; if (rf == NULL) /* should not happen */ - return (0); + return 0; if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { AR5K_PRINTF("invalid values at offset %u\n", offset); - return (0); + return 0; } entry = ((first - 1) / 8) + offset; @@ -5494,23 +5478,23 @@ ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bit data = set == true ? 1 : ath5k_hw_bitswap(data, bits); - return (data); + return data; } -u_int32_t +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) { - u_int32_t mix, step; - u_int32_t *rf; + u32 mix, step; + u32 *rf; if (hal->ah_rf_banks == NULL) - return (0); + return 0; rf = hal->ah_rf_banks; hal->ah_gain.g_f_corr = 0; if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1) - return (0); + return 0; step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false); mix = hal->ah_gain.g_step->gos_param[0]; @@ -5530,17 +5514,17 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) break; } - return (hal->ah_gain.g_f_corr); + return hal->ah_gain.g_f_corr; } bool ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) { - u_int32_t step, mix, level[4]; - u_int32_t *rf; + u32 step, mix, level[4]; + u32 *rf; if (hal->ah_rf_banks == NULL) - return (0); + return 0; rf = hal->ah_rf_banks; @@ -5575,7 +5559,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) hal->ah_gain.g_current <= level[3])); } -int32_t +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) { int ret = 0; @@ -5588,7 +5572,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { if (hal->ah_gain.g_step_idx == 0) - return (-1); + return -1; for (hal->ah_gain.g_target = hal->ah_gain.g_current; hal->ah_gain.g_target >= hal->ah_gain.g_high && hal->ah_gain.g_step_idx > 0; @@ -5605,7 +5589,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) - return (-2); + return -2; for (hal->ah_gain.g_target = hal->ah_gain.g_current; hal->ah_gain.g_target <= hal->ah_gain.g_low && hal->ah_gain.g_step_idx < (go->go_steps_count - 1); @@ -5629,14 +5613,14 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) hal->ah_gain.g_target); #endif - return (ret); + return ret; } /* * Initialize RF */ bool -ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) +ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) { ath5k_rfgain_t *func = NULL; bool ret; @@ -5651,14 +5635,14 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) hal->ah_rf_banks_size = sizeof(rf5112_rf); func = ath5k_hw_rf5112_rfregs; } else - return (false); + return false; if (hal->ah_rf_banks == NULL) { /* XXX do extra checks? */ if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, GFP_KERNEL)) == NULL) { AR5K_PRINT("out of memory\n"); - return (false); + return false; } } @@ -5667,20 +5651,20 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) if (ret == true) hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; - return (ret); + return ret; } /* * Initialize RF5111 */ bool -ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) +ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - const u_int rf_size = AR5K_ELEMENTS(rf5111_rf); - u_int32_t *rf; + const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); + u32 *rf; int i, obdb = -1, bank = -1; - u_int32_t ee_mode; + u32 ee_mode; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5691,7 +5675,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (rf5111_rf[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (false); + return false; } if (bank != rf5111_rf[i].rf_bank) { @@ -5711,11 +5695,11 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], ee->ee_ob[ee_mode][obdb], 3, 119, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], ee->ee_ob[ee_mode][obdb], 3, 122, 0, true)) - return (false); + return false; obdb = 1; } else { @@ -5728,36 +5712,36 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_84, 1, 51, 3, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_90, 1, 45, 3, true)) - return (false); + return false; } if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], !ee->ee_xpd[ee_mode], 1, 95, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_x_gain[ee_mode], 4, 96, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 29, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_xpd[ee_mode], 1, 4, 0, true)) - return (false); + return false; /* Write RF values */ for (i = 0; i < rf_size; i++) { @@ -5765,20 +5749,20 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]); } - return (true); + return true; } /* * Initialize RF5112 */ bool -ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int mode) +ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int rf_size; - u_int32_t *rf; + unsigned int rf_size; + u32 *rf; int i, obdb = -1, bank = -1; - u_int32_t ee_mode; + u32 ee_mode; const struct ath5k_ini_rf *rf_ini; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5787,18 +5771,17 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { rf_ini = rf5112a_rf; - rf_size = AR5K_ELEMENTS(rf5112a_rf); + rf_size = ARRAY_SIZE(rf5112a_rf); } else { rf_ini = rf5112_rf; - rf_size = AR5K_ELEMENTS(rf5112_rf); + rf_size = ARRAY_SIZE(rf5112_rf); } /* Copy values to modify them */ for (i = 0; i < rf_size; i++) { - if (rf_ini[i].rf_bank >= - AR5K_RF5112_INI_RF_MAX_BANKS) { + if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (false); + return false; } if (bank != rf_ini[i].rf_bank) { @@ -5818,11 +5801,11 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 287, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 290, 0, true)) - return (false); + return false; } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; @@ -5833,11 +5816,11 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 282, 0, true)) - return (false); + return false; } #ifdef notyet @@ -5849,17 +5832,17 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_xpd[ee_mode], 1, 302, 0, true)) - return (false); + return false; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 14, 0, true)) - return (false); + return false; /* Write RF values */ for (i = 0; i < rf_size; i++) AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); - return (true); + return true; } /* @@ -5868,13 +5851,13 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int * doesn't ar5k_rfregs work ? */ void -ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int freq, - u_int ee_mode) +ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, + unsigned int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - struct ath5k_ar5211_ini_rf rf[AR5K_ELEMENTS(ar5211_rf)]; - u_int32_t ob, db, obdb, xpds, xpdp, x_gain; - u_int i; + struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)]; + u32 ob, db, obdb, xpds, xpdp, x_gain; + unsigned int i; memcpy(rf, ar5211_rf, sizeof(rf)); obdb = 0; @@ -5917,9 +5900,9 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | ((xpds << 3) & 0x8); - for (i = 0; i < AR5K_ELEMENTS(rf); i++) { + for (i = 0; i < ARRAY_SIZE(rf); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, + AR5K_REG_WRITE((u32)rf[i].rf_register, rf[i].rf_value[freq]); } @@ -5927,7 +5910,7 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, u_int } bool -ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) +ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq) { int i; @@ -5936,7 +5919,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) case AR5K_INI_PHY_5112: break; default: - return (false); + return false; } switch (freq) { @@ -5944,28 +5927,28 @@ ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) case AR5K_INI_RFGAIN_5GHZ: break; default: - return (false); + return false; } - for (i = 0; i < AR5K_ELEMENTS(ath5k_rfg); i++) { + for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ath5k_rfg[i].rfg_register, + AR5K_REG_WRITE((u32)ath5k_rfg[i].rfg_register, ath5k_rfg[i].rfg_value[phy][freq]); } - return (true); + return true; } enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal) { - u_int32_t data, type; + u32 data, type; AR5K_TRACE; - if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active) - || (hal->ah_version <= AR5K_AR5211)) - return (AR5K_RFGAIN_INACTIVE); + if (hal->ah_rf_banks == NULL || !hal->ah_gain.g_active || + hal->ah_version <= AR5K_AR5211) + return AR5K_RFGAIN_INACTIVE; if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) goto done; @@ -5973,8 +5956,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) data = AR5K_REG_READ(AR5K_PHY_PAPD_PROBE); if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { - hal->ah_gain.g_current = - data >> AR5K_PHY_PAPD_PROBE_GAINF_S; + hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) @@ -5995,7 +5977,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) } done: - return (hal->ah_rf_gain); + return hal->ah_rf_gain; } /* @@ -6006,9 +5988,9 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) * Initialize the tx power table (not fully implemented) */ void -ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t max_power) +ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_power) { - u_int16_t txpower, *rates; + u16 txpower, *rates; int i, min, max, n; rates = hal->ah_txpower.txp_rates; @@ -6028,7 +6010,7 @@ ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t hal->ah_txpower.txp_ofdm = rates[0]; /* Calculate the power table */ - n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac); + n = ARRAY_SIZE(hal->ah_txpower.txp_pcdac); min = AR5K_EEPROM_PCDAC_START; max = AR5K_EEPROM_PCDAC_STOP; for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) @@ -6044,7 +6026,7 @@ ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, int16_t * Set transmition power */ bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpower) +ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; int i; @@ -6052,7 +6034,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow AR5K_TRACE; if (txpower > AR5K_TUNE_MAX_TXPOWER) { AR5K_PRINTF("invalid tx power: %u\n", txpower); - return (false); + return false; } /* Reset TX power values */ @@ -6098,18 +6080,18 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, u_int txpow AR5K_TUNE_MAX_TXPOWER); } - return (true); + return true; } bool -ath5k_hw_set_txpower_limit(struct ath_hal *hal, u_int power) +ath5k_hw_set_txpower_limit(struct ath_hal *hal, unsigned int power) { /*Just a try M.F.*/ struct ath5k_channel *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n",power); - return (ath5k_hw_txpower(hal, channel, power)); + return ath5k_hw_txpower(hal, channel, power); } @@ -6226,15 +6208,14 @@ ath5k_hw_dump_state(struct ath_hal *hal) bool /*what about VEOL cap ?*/ ath5k_hw_has_veol(struct ath_hal *hal) { - return (true); + return true; } void /*Unimplemented*/ -ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) +ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u32 *i) { AR5K_TRACE; /* XXX */ - return; } void /*Added struct ath5k_node_stats argument*/ @@ -6246,20 +6227,20 @@ ath5k_hw_set_rx_signal(struct ath_hal *hal, const struct ath5k_node_stats *stats bool /*Added arguments*/ ath5k_hw_get_diag_state(struct ath_hal *hal, int request, -const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) + const void *args, u32 argsize, void **result, u32 *resultsize) { AR5K_TRACE; /* * We'll ignore this right now. This seems to be some kind of an obscure * debugging interface for the binary-only HAL. */ - return (false); + return false; } bool /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ ath5k_hw_detect_card_present(struct ath_hal *hal) { - u_int16_t magic; + u16 magic; AR5K_TRACE; /* * Checking the EEPROM's magic value could be an indication @@ -6267,14 +6248,14 @@ ath5k_hw_detect_card_present(struct ath_hal *hal) * way to do this. */ if (ath5k_hw_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (false); + return false; - return (magic == AR5K_EEPROM_MAGIC_VALUE ? true : false); + return magic == AR5K_EEPROM_MAGIC_VALUE ? true : false; } -enum ath5k_status -ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, - u_int32_t capability, u_int32_t *result) +enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, + enum ath5k_capability_type cap_type, + u32 capability, u32 *result) { AR5K_TRACE; @@ -6325,7 +6306,7 @@ ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type } no: - return (AR5K_EINVAL); + return AR5K_EINVAL; yes: return AR5K_OK; @@ -6334,14 +6315,14 @@ ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type bool ath5k_hw_set_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, - u_int32_t capability, u_int32_t setting, + u32 capability, u32 setting, enum ath5k_status *status) { AR5K_TRACE; if (status) *status = AR5K_OK; - return (false); + return false; } bool @@ -6351,7 +6332,7 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) if (hal->ah_version == AR5K_AR5210) return(true); - return (false); + return false; } bool @@ -6361,22 +6342,22 @@ ath5k_hw_init_pspoll(struct ath_hal *hal) /* * Not used */ - return (false); + return false; } bool -ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, - u_int16_t assoc_id) +ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, + u16 assoc_id) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); - return (true); + return true; } - return (false); + return false; } bool @@ -6387,20 +6368,20 @@ ath5k_hw_disable_pspoll(struct ath_hal *hal) AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); - return (true); + return true; } - return (false); + return false; } const char * /*O.K. - TODO:Get rid of this*/ -ath5k_printver(enum ath5k_srev_type type, u_int32_t val) +ath5k_printver(enum ath5k_srev_type type, u32 val) { struct ath5k_srev_name names[] = AR5K_SREV_NAME; const char *name = "xxxx"; int i; - for (i = 0; i < AR5K_ELEMENTS(names); i++) { + for (i = 0; i < ARRAY_SIZE(names); i++) { if (type == AR5K_VERSION_DEV) { if (names[i].sr_type == type && names[i].sr_val == val) { @@ -6418,7 +6399,7 @@ ath5k_printver(enum ath5k_srev_type type, u_int32_t val) } } - return (name); + return name; } void /*O.K. - TODO: Implement this in if_ath.c (ath_intr)*/ @@ -6484,7 +6465,7 @@ ath5k_hw_fill(struct ath_hal *hal) hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc; hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; - } else if (hal->ah_version != AR5K_AR5212) { + } else { hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc; commit 2022cacb6ad3856315194328e1900d486bad2c1b Author: Jiri Slaby Date: Sun Jun 17 23:23:55 2007 +0200 openhal/ieee80211_regdomain cleanup diff --git a/openhal/ieee80211_regdomain.c b/openhal/ieee80211_regdomain.c index 870e52e..172c0dc 100644 --- a/openhal/ieee80211_regdomain.c +++ b/openhal/ieee80211_regdomain.c @@ -1,19 +1,9 @@ -/* $OpenBSD: ieee80211_regdomain.c,v 1.4 2005/02/17 23:52:05 reyk Exp $ */ - /* * Copyright (c) 2004, 2005 Reyk Floeter * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /* @@ -23,10 +13,6 @@ #include "ah_osdep.h" #include "ieee80211_regdomain.h" - -int ieee80211_regdomain_compare_cn(const void *, const void *); -int ieee80211_regdomain_compare_rn(const void *, const void *); - static const struct ieee80211_regdomainname ieee80211_r_names[] = IEEE80211_REGDOMAIN_NAMES; @@ -37,24 +23,20 @@ static const struct ieee80211_countryname ieee80211_r_ctry[] = IEEE80211_REGDOMAIN_COUNTRY_NAMES; #ifndef bsearch -const void *bsearch(const void *, const void *, size_t, size_t, - int (*)(const void *, const void *)); - -const void * -bsearch(const void *key, const void *base0, size_t nmemb, size_t size, - int (*compar)(const void *, const void *)) +static const void *bsearch(const void *key, const void *base0, size_t nmemb, + size_t size, int (*compar)(const void *, const void *)) { const char *base = base0; int lim, cmp; const void *p; - for (lim = nmemb; lim != 0; lim >>= 1) { - p = base + (lim >> 1) * size; + for (lim = nmemb; lim != 0; lim /= 2) { + p = base + (lim / 2) * size; cmp = (*compar)(key, p); if (cmp == 0) - return ((const void *)p); + return p; if (cmp > 0) { /* key > p: move right */ - base = (const char *)p + size; + base = p + size; lim--; } /* else move left */ } @@ -62,103 +44,92 @@ bsearch(const void *key, const void *base0, size_t nmemb, size_t size, } #endif -int -ieee80211_regdomain_compare_cn(const void *a, const void *b) +static int ieee80211_regdomain_compare_cn(const void *a, const void *b) { - return(strcmp(((const struct ieee80211_countryname*)a)->cn_name, - ((const struct ieee80211_countryname*)b)->cn_name)); + const struct ieee80211_countryname *ca = a, *cb = b; + return strcmp(ca->cn_name, cb->cn_name); } -int -ieee80211_regdomain_compare_rn(const void *a, const void *b) +static int ieee80211_regdomain_compare_rn(const void *a, const void *b) { - return(strcmp(((const struct ieee80211_regdomainname*)a)->rn_name, - ((const struct ieee80211_regdomainname*)b)->rn_name)); + const struct ieee80211_regdomainname *ra = a, *rb = b; + return strcmp(ra->rn_name, rb->rn_name); } -u_int16_t -ieee80211_name2countrycode(const char *name) +u16 ieee80211_name2countrycode(const char *name) { const struct ieee80211_countryname key = { CTRY_DEFAULT, name }, *value; - if((value = bsearch(&key, &ieee80211_r_ctry, - sizeof(ieee80211_r_ctry) / sizeof(ieee80211_r_ctry[0]), + value = bsearch(&key, &ieee80211_r_ctry, ARRAY_SIZE(ieee80211_r_ctry), sizeof(struct ieee80211_countryname), - ieee80211_regdomain_compare_cn)) != 0) - return(value->cn_code); + ieee80211_regdomain_compare_cn); + if (value != 0) + return value->cn_code; - return(CTRY_DEFAULT); + return CTRY_DEFAULT; } -u_int32_t -ieee80211_name2regdomain(const char *name) +u32 ieee80211_name2regdomain(const char *name) { - const struct ieee80211_regdomainname key = { DMN_DEFAULT, name }, *value; + const struct ieee80211_regdomainname key = { DMN_DEFAULT, name },*value; - if((value = bsearch(&key, &ieee80211_r_names, - sizeof(ieee80211_r_names) / sizeof(ieee80211_r_names[0]), + value = bsearch(&key, &ieee80211_r_names, ARRAY_SIZE(ieee80211_r_names), sizeof(struct ieee80211_regdomainname), - ieee80211_regdomain_compare_rn)) != 0) - return((u_int32_t)value->rn_domain); + ieee80211_regdomain_compare_rn); + if (value != 0) + return (u32)value->rn_domain; - return((u_int32_t)DMN_DEFAULT); + return (u32)DMN_DEFAULT; } -const char * -ieee80211_countrycode2name(u_int16_t code) +const char *ieee80211_countrycode2name(u16 code) { - int i; + unsigned int i; /* Linear search over the table */ - for(i = 0; i < (sizeof(ieee80211_r_ctry) / sizeof(ieee80211_r_ctry[0])); i++) - if(ieee80211_r_ctry[i].cn_code == code) - return(ieee80211_r_ctry[i].cn_name); + for (i = 0; i < ARRAY_SIZE(ieee80211_r_ctry); i++) + if (ieee80211_r_ctry[i].cn_code == code) + return ieee80211_r_ctry[i].cn_name; return NULL; } -const char * -ieee80211_regdomain2name(u_int32_t regdomain) +const char *ieee80211_regdomain2name(u_int32_t regdomain) { - int i; + unsigned int i; /* Linear search over the table */ - for(i = 0; i < (sizeof(ieee80211_r_names) / - sizeof(ieee80211_r_names[0])); i++) - if(ieee80211_r_names[i].rn_domain == regdomain) - return(ieee80211_r_names[i].rn_name); + for (i = 0; i < ARRAY_SIZE(ieee80211_r_names); i++) + if (ieee80211_r_names[i].rn_domain == regdomain) + return ieee80211_r_names[i].rn_name; - return(ieee80211_r_names[0].rn_name); + return ieee80211_r_names[0].rn_name; } -u_int32_t -ieee80211_regdomain2flag(u_int16_t regdomain, u_int16_t mhz) +u32 ieee80211_regdomain2flag(u16 regdomain, u16 mhz) { - int i; + unsigned int i; - for(i = 0; i < (sizeof(ieee80211_r_map) / - sizeof(ieee80211_r_map[0])); i++) { - if(ieee80211_r_map[i].rm_domain == regdomain) { - if(mhz >= 2000 && mhz <= 3000) - return((u_int32_t)ieee80211_r_map[i].rm_domain_2ghz); - if(mhz >= IEEE80211_CHANNELS_5GHZ_MIN && - mhz <= IEEE80211_CHANNELS_5GHZ_MAX) - return((u_int32_t)ieee80211_r_map[i].rm_domain_5ghz); + for (i = 0; i < ARRAY_SIZE(ieee80211_r_map); i++) { + if (ieee80211_r_map[i].rm_domain == regdomain) { + if (mhz >= 2000 && mhz <= 3000) + return (u32)ieee80211_r_map[i].rm_domain_2ghz; + if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && + mhz <= IEEE80211_CHANNELS_5GHZ_MAX) + return (u32)ieee80211_r_map[i].rm_domain_5ghz; } } - return((u_int32_t)DMN_DEBUG); + return (u32)DMN_DEBUG; } -u_int32_t -ieee80211_countrycode2regdomain(u_int16_t code) +u32 ieee80211_countrycode2regdomain(u16 code) { - int i; + unsigned int i; - for (i = 0; - i < (sizeof(ieee80211_r_ctry) / sizeof(ieee80211_r_ctry[0])); i++) + for (i = 0; i < ARRAY_SIZE(ieee80211_r_ctry); i++) if (ieee80211_r_ctry[i].cn_code == code) - return (ieee80211_r_ctry[i].cn_domain); + return ieee80211_r_ctry[i].cn_domain; - return((u_int32_t)DMN_DEFAULT); + return (u32)DMN_DEFAULT; } diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 8f2a365..39e07fa 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -19,7 +19,7 @@ #ifndef _NET80211_IEEE80211_REGDOMAIN_H_ #define _NET80211_IEEE80211_REGDOMAIN_H_ -typedef u_int32_t ieee80211_regdomain_t; +typedef u32 ieee80211_regdomain_t; enum ieee80211_regdomain { DMN_DEFAULT = 0x00, @@ -102,7 +102,7 @@ enum ieee80211_regdomain { #define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) struct ieee80211_regdomainname { - u_int32_t rn_domain; + u32 rn_domain; const char *rn_name; }; @@ -184,9 +184,9 @@ struct ieee80211_regdomainname { } struct ieee80211_regdomainmap { - u_int16_t rm_domain; - u_int32_t rm_domain_5ghz; - u_int32_t rm_domain_2ghz; + u16 rm_domain; + u32 rm_domain_5ghz; + u32 rm_domain_2ghz; }; #define IEEE80211_REGDOMAIN_MAP { \ @@ -361,9 +361,9 @@ enum ieee80211_countrycode { }; struct ieee80211_countryname { - u_int16_t cn_code; + u16 cn_code; const char *cn_name; - u_int32_t cn_domain; + u32 cn_domain; }; #define IEEE80211_REGDOMAIN_COUNTRY_NAMES { \ @@ -501,9 +501,9 @@ enum ieee80211_ctl { #define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ struct ieee80211_regchannel { - u_int16_t rc_channel; - u_int32_t rc_domain; - u_int32_t rc_mode; + u16 rc_channel; + u32 rc_domain; + u32 rc_mode; }; #define IEEE80211_CHANNELS_2GHZ { \ @@ -769,12 +769,12 @@ struct ieee80211_regchannel { } -extern u_int16_t ieee80211_name2countrycode(const char *); -extern u_int32_t ieee80211_name2regdomain(const char *); -extern const char *ieee80211_countrycode2name(u_int16_t); -extern const char *ieee80211_regdomain2name(u_int32_t); -extern u_int32_t ieee80211_regdomain2flag(u_int16_t, u_int16_t); -extern u_int32_t ieee80211_countrycode2regdomain(u_int16_t); +extern u16 ieee80211_name2countrycode(const char *); +extern u32 ieee80211_name2regdomain(const char *); +extern const char *ieee80211_countrycode2name(u16); +extern const char *ieee80211_regdomain2name(u32); +extern u32 ieee80211_regdomain2flag(u16, u16); +extern u32 ieee80211_countrycode2regdomain(u16); #endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ commit b1836b874d1fa17b9cdfe470122b5e2b2f9749bf Author: Jiri Slaby Date: Mon Jun 18 09:25:54 2007 +0200 add compat defs diff --git a/ath/if_ath.c b/ath/if_ath.c index ed6de19..81f0ca1 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -362,7 +362,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Attach the hal */ - ah = _ath_hal_attach(devid, sc, sc->sc_iobase, &status); + ah = ath_hal_attach(devid, sc, sc->sc_iobase, &status); if (ah == NULL) { printk(KERN_ERR "%s: unable to attach hardware: '%s' (HAL status %u)\n", __func__, hal_status_desc[status], status); diff --git a/openhal/Makefile b/openhal/Makefile index 9007072..38bb7b8 100644 --- a/openhal/Makefile +++ b/openhal/Makefile @@ -1,2 +1,4 @@ obj-m += ath_hal.o ath_hal-objs := ah_osdep.o ath5k_hw.o ieee80211_regdomain.o + +EXTRA_CFLAGS+=-DCONFIG_OPENHAL_COMPAT diff --git a/openhal/ah_osdep.c b/openhal/ah_osdep.c index 9f1a7c4..f76c0a2 100644 --- a/openhal/ah_osdep.c +++ b/openhal/ah_osdep.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2006-2007 Nick Kossifidis + * Copyright (c) 2007 Jiri Slaby * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -15,7 +16,7 @@ static char dev_info[] = "ath_hal"; -struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, +struct ath_hal *ath_hal_attach(u16 devid, void *sc, void __iomem *h, enum ath5k_status *s) { struct ath_hal *ah = ath5k_hw_init(devid, sc, h, s); @@ -28,7 +29,7 @@ struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, return ah; } -EXPORT_SYMBOL(_ath_hal_attach); +EXPORT_SYMBOL(ath_hal_attach); void ath_hal_detach(struct ath_hal *ah) { diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 25949f0..07a146e 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -891,8 +891,8 @@ struct ath5k_capabilities { * Active regulation domain settings */ struct { - ieee80211_regdomain_t reg_current; - ieee80211_regdomain_t reg_hw; + enum ieee80211_regdomain reg_current; + enum ieee80211_regdomain reg_hw; } cap_regdomain; /* @@ -1172,8 +1172,8 @@ bool ath_hal_init_channels(struct ath_hal *, struct ath5k_channel *, bool, bool); const char *ath5k_printver(enum ath5k_srev_type, u32); void ath5k_radar_alert(struct ath_hal *); -ieee80211_regdomain_t ath5k_regdomain_to_ieee(u16); -u16 ath5k_regdomain_from_ieee(ieee80211_regdomain_t); +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16); +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain); u16 ath5k_get_regdomain(struct ath_hal *); u32 ath5k_bitswap(u32, u_int); inline u_int ath5k_clocktoh(u_int, bool); @@ -1184,7 +1184,7 @@ bool ath5k_register_timeout(struct ath_hal *, u32, u32, int ath5k_eeprom_init(struct ath_hal *); int ath5k_eeprom_read_mac(struct ath_hal *, u8 *); bool ath5k_eeprom_regulation_domain(struct ath_hal *, bool, - ieee80211_regdomain_t *); + enum ieee80211_regdomain *); int ath5k_eeprom_read_ants(struct ath_hal *, u32 *, u_int); int ath5k_eeprom_read_modes(struct ath_hal *, u32 *, u_int); u16 ath5k_eeprom_bin2freq(struct ath_hal *, u16, u_int); @@ -1216,6 +1216,71 @@ void ath5k_txpower_table(struct ath_hal *, struct ath5k_channel *, s16); /*added*/ extern u_int ath_hal_getwirelessmodes(struct ath_hal *, enum ieee80211_countrycode); void ath_hal_detach(struct ath_hal *ah); -struct ath_hal *_ath_hal_attach(u16 devid, void *sc, void __iomem *h, +struct ath_hal *ath_hal_attach(u16 devid, void *sc, void __iomem *h, enum ath5k_status *s); + +/* COMPAT stuff */ + +#ifdef CONFIG_OPENHAL_COMPAT +typedef u32 ieee80211_regdomain_t; + +typedef struct ath5k_node_stats AR5K_NODE_STATS; +typedef struct ath5k_rate_table AR5K_RATE_TABLE; +typedef struct ath5k_channel AR5K_CHANNEL; +typedef struct ath5k_keyval AR5K_KEYVAL; +typedef struct ath5k_txq_info AR5K_TXQ_INFO; + +typedef enum ieee80211_if_types AR5K_OPMODE; +typedef enum ath5k_int AR5K_INT; +typedef enum ath5k_status AR5K_STATUS; +typedef enum ath5k_pkt_type AR5K_PKT_TYPE; + +typedef void *AR5K_SOFTC; +typedef int AR5K_BUS_TAG; +typedef __iomem void *AR5K_BUS_HANDLE; +typedef u_int32_t AR5K_BUS_ADDR; + +typedef bool AR5K_BOOL; + +#define TRUE true +#define FALSE false + +#define AR5K_M_STA IEEE80211_IF_TYPE_STA +#define AR5K_M_IBSS IEEE80211_IF_TYPE_IBSS +#define AR5K_M_HOSTAP IEEE80211_IF_TYPE_AP +#define AR5K_M_MONITOR IEEE80211_IF_TYPE_MNTR + +#define PCI_PRODUCT_ATHEROS_AR5210_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT +#define PCI_PRODUCT_ATHEROS_AR5210 PCI_DEVICE_ID_ATHEROS_AR5210 +#define PCI_PRODUCT_ATHEROS_AR5210_AP PCI_DEVICE_ID_ATHEROS_AR5210_AP +#define PCI_PRODUCT_ATHEROS_AR5212_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM +#define PCI_PRODUCT_ATHEROS_AR5211 PCI_DEVICE_ID_ATHEROS_AR5211 +#define PCI_PRODUCT_ATHEROS_AR5211_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT +#define PCI_PRODUCT_ATHEROS_AR5311 PCI_DEVICE_ID_ATHEROS_AR5311 +#define PCI_PRODUCT_ATHEROS_AR5211_LEGACY PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY +#define PCI_PRODUCT_ATHEROS_AR5211_FPGA11B PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B +#define PCI_PRODUCT_ATHEROS_AR5212_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT +#define PCI_PRODUCT_ATHEROS_AR5212 PCI_DEVICE_ID_ATHEROS_AR5212 +#define PCI_PRODUCT_ATHEROS_AR5212_FPGA PCI_DEVICE_ID_ATHEROS_AR5212_FPGA +#define PCI_PRODUCT_ATHEROS_AR5212_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM +#define PCI_PRODUCT_ATHEROS_AR5212_REV2 PCI_DEVICE_ID_ATHEROS_AR5212_REV2 +#define PCI_PRODUCT_ATHEROS_AR5212_REV7 PCI_DEVICE_ID_ATHEROS_AR5212_REV7 +#define PCI_PRODUCT_ATHEROS_AR5212_REV8 PCI_DEVICE_ID_ATHEROS_AR5212_REV8 +#define PCI_PRODUCT_ATHEROS_AR5212_0014 PCI_DEVICE_ID_ATHEROS_AR5212_0014 +#define PCI_PRODUCT_ATHEROS_AR5212_0015 PCI_DEVICE_ID_ATHEROS_AR5212_0015 +#define PCI_PRODUCT_ATHEROS_AR5212_0016 PCI_DEVICE_ID_ATHEROS_AR5212_0016 +#define PCI_PRODUCT_ATHEROS_AR5212_0017 PCI_DEVICE_ID_ATHEROS_AR5212_0017 +#define PCI_PRODUCT_ATHEROS_AR5212_0018 PCI_DEVICE_ID_ATHEROS_AR5212_0018 +#define PCI_PRODUCT_ATHEROS_AR5212_0019 PCI_DEVICE_ID_ATHEROS_AR5212_0019 +#define PCI_PRODUCT_ATHEROS_AR2413 PCI_DEVICE_ID_ATHEROS_AR2413 +#define PCI_PRODUCT_ATHEROS_AR5413 PCI_DEVICE_ID_ATHEROS_AR5413 +#define PCI_PRODUCT_ATHEROS_AR5424 PCI_DEVICE_ID_ATHEROS_AR5424 + +static inline struct ath_hal *_ath_hal_attach(u16 devid, AR5K_SOFTC sc, + AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void *s) +{ + return ath_hal_attach(devid, sc, h, s); +} +#endif + #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 3fd4cc2..4a1e44c 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -2524,7 +2524,7 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) */ bool ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, - ieee80211_regdomain_t *regdomain) + enum ieee80211_regdomain *regdomain) { u16 ee_regdomain; @@ -2557,7 +2557,7 @@ bool ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, enum ath5k_status *status) { - ieee80211_regdomain_t ieee_regdomain; + enum ieee80211_regdomain ieee_regdomain; ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); @@ -4921,7 +4921,7 @@ EXPORT_SYMBOL(ath_hal_init_channels); */ u16 -ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) +ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) { u32 regdomain = (u32)ieee; @@ -4930,17 +4930,17 @@ ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) * or not supported by the net80211 regulation code. */ if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) return (u16)AR5K_TUNE_REGDOMAIN; /* It is supported, just return the value */ return regdomain; } -ieee80211_regdomain_t +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) { - ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; + enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; return ieee; } @@ -4949,7 +4949,7 @@ u16 ath5k_get_regdomain(struct ath_hal *hal) { u16 regdomain; - ieee80211_regdomain_t ieee_regdomain; + enum ieee80211_regdomain ieee_regdomain; #ifdef COUNTRYCODE u16 code; #endif diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 39e07fa..1c68e8f 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -19,8 +19,6 @@ #ifndef _NET80211_IEEE80211_REGDOMAIN_H_ #define _NET80211_IEEE80211_REGDOMAIN_H_ -typedef u32 ieee80211_regdomain_t; - enum ieee80211_regdomain { DMN_DEFAULT = 0x00, DMN_NULL_WORLD = 0x03, commit b20479460f970d96702a09739edcd2533871728f Author: Jiri Slaby Date: Mon Jun 18 09:46:30 2007 +0200 little ath_pci cleanup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c5a7d24..e946fcf 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -21,41 +21,18 @@ * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $Id: if_ath_pci.c 2408 2007-05-30 22:58:20Z mickflemm $ */ -#include "opt_ah.h" +#define ATH_PCI_VERSION "0.9.5.0-BSD" -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB -#endif +#include "opt_ah.h" -#ifndef AUTOCONF_INCLUDED -#include -#endif #include #include -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) -#include -#endif -#include #include #include #include - #include +#include #include @@ -64,22 +41,9 @@ /* support for module parameters */ static char *ifname = "ath"; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,52)) -MODULE_PARM(ifname, "s"); -#else module_param(ifname, charp, 0); -#endif - MODULE_PARM_DESC(ifname, "Interface name prefix (default: ath)"); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)) -/* - * PCI initialization uses Linux 2.4.x version and - * older kernels do not support this - */ -#error Atheros PCI version requires at least Linux kernel version 2.4.0 -#endif /* kernel < 2.4.0 */ - struct ath_pci_softc { struct ath_softc aps_sc; #ifdef CONFIG_PM @@ -324,12 +288,9 @@ static struct pci_driver ath_pci_drv_id = { /* * Module glue. */ -#include "version.h" static char *version = ATH_PCI_VERSION " (EXPERIMENTAL)"; static char *dev_info = "ath_pci"; -#include - int ath_ioctl_ethtool(struct ath_softc *sc, int cmd, void __user *addr) { diff --git a/ath/version.h b/ath/version.h deleted file mode 100644 index 04b690c..0000000 --- a/ath/version.h +++ /dev/null @@ -1,38 +0,0 @@ -/*- - * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $Id: version.h 844 2005-02-16 14:20:31Z togg $ - */ -#define ATH_PCI_VERSION "0.9.5.0-BSD" commit cfa315c963ba834a30f6699d2dcff460f3fa6547 Author: Jiri Slaby Date: Mon Jun 18 10:35:35 2007 +0200 ath/if_ath_pci cleanup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index e946fcf..2934afd 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -44,57 +44,60 @@ static char *ifname = "ath"; module_param(ifname, charp, 0); MODULE_PARM_DESC(ifname, "Interface name prefix (default: ath)"); -struct ath_pci_softc { - struct ath_softc aps_sc; -#ifdef CONFIG_PM - u32 aps_pmstate[16]; -#endif -}; - /* * User a static table of PCI id's for now. While this is the * "new way" to do things, we may want to switch back to having * the HAL check them by defining a probe method. */ static struct pci_device_id ath_pci_id_table[] __devinitdata = { - { 0x168c, 0x0207, PCI_ANY_ID, PCI_ANY_ID }, /* 5210 early */ - { 0x168c, 0x0007, PCI_ANY_ID, PCI_ANY_ID }, /* 5210 */ - { 0x168c, 0x0011, PCI_ANY_ID, PCI_ANY_ID }, /* 5311 */ - { 0x168c, 0x0012, PCI_ANY_ID, PCI_ANY_ID }, /* 5211 */ - { 0x168c, 0x0013, PCI_ANY_ID, PCI_ANY_ID }, /* 5212 */ - { 0xa727, 0x0013, PCI_ANY_ID, PCI_ANY_ID }, /* 3com 5212 */ - { 0x10b7, 0x0013, PCI_ANY_ID, PCI_ANY_ID }, /* 3com 3CRDAG675 5212 */ - { 0x168c, 0x1014, PCI_ANY_ID, PCI_ANY_ID }, /* IBM minipci 5212 */ - { 0x168c, 0x0014, PCI_ANY_ID, PCI_ANY_ID }, /* 5212 combatible */ - { 0x168c, 0x0015, PCI_ANY_ID, PCI_ANY_ID }, /* 5212 combatible */ - { 0x168c, 0x0016, PCI_ANY_ID, PCI_ANY_ID }, /* 5212 combatible */ - { 0x168c, 0x0017, PCI_ANY_ID, PCI_ANY_ID }, /* 5212 combatible */ - { 0x168c, 0x0018, PCI_ANY_ID, PCI_ANY_ID }, /* 5212 combatible */ - { 0x168c, 0x0019, PCI_ANY_ID, PCI_ANY_ID }, /* 5212 combatible */ - { 0x168c, 0x001a, PCI_ANY_ID, PCI_ANY_ID }, /* 2413 Griffin-lite */ - { 0x168c, 0x001b, PCI_ANY_ID, PCI_ANY_ID }, /* 5413 Eagle */ - { 0x168c, 0x001c, PCI_ANY_ID, PCI_ANY_ID }, /* 5424 Condor (PCI-E)*/ + { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ + { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ + { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 */ + { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ + { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ + { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ + { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ + { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ + { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ + { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ + { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ + { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ + { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ + { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ + { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ + { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ + { PCI_VDEVICE(ATHEROS, 0x001c) }, /* 5424 Condor (PCI-E)*/ { 0 } }; +MODULE_DEVICE_TABLE(pci, ath_pci_id_table); + +/* return bus cachesize in 4B word units */ +void bus_read_cachesize(struct ath_softc *sc, u8 *csz) +{ + pci_read_config_byte(sc->sc_bdev, PCI_CACHE_LINE_SIZE, csz); +} -static int -ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) +static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - unsigned long phymem; void __iomem *mem; - struct ath_pci_softc *sc; + struct ath_softc *sc; struct net_device *dev; const char *athname; - u_int8_t csz; + int retval; u32 val; + u8 csz; - if (pci_enable_device(pdev)) - return (-EIO); + retval = pci_enable_device(pdev); + if (retval) { + dev_err(&pdev->dev, "can't enable device\n"); + goto err; + } /* XXX 32-bit addressing only */ - if (pci_set_dma_mask(pdev, 0xffffffff)) { - printk(KERN_ERR "ath_pci: 32-bit DMA not available\n"); - goto bad; + retval = pci_set_dma_mask(pdev, DMA_32BIT_MASK); + if (retval) { + dev_err(&pdev->dev, "32-bit DMA not available\n"); + goto err_dis; } /* @@ -110,7 +113,7 @@ ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) * DMA to work so force a reasonable value here if it * comes up zero. */ - csz = L1_CACHE_BYTES / sizeof(u_int32_t); + csz = L1_CACHE_BYTES / sizeof(u32); pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); } /* @@ -132,32 +135,31 @@ ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if ((val & 0x0000ff00) != 0) pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); - phymem = pci_resource_start(pdev, 0); - if (!request_mem_region(phymem, pci_resource_len(pdev, 0), "ath")) { - printk(KERN_ERR "ath_pci: cannot reserve PCI memory region\n"); - goto bad; + retval = pci_request_region(pdev, 0, "ath"); + if (retval) { + dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); + goto err_dis; } - mem = ioremap(phymem, pci_resource_len(pdev, 0)); + mem = pci_iomap(pdev, 0, 0); if (!mem) { - printk(KERN_ERR "ath_pci: cannot remap PCI memory region\n") ; - goto bad1; + dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; + goto err_reg; } - sc = kmalloc(sizeof(struct ath_pci_softc), GFP_KERNEL); + sc = kzalloc(sizeof(struct ath_softc), GFP_KERNEL); if (sc == NULL) { - printk(KERN_ERR "ath_pci: no memory for device state\n"); - goto bad2; + dev_err(&pdev->dev, "no memory for device state\n"); + goto err_map; } - memset(sc, 0, sizeof(struct ath_pci_softc)); /* * Mark the device as detached to avoid processing * interrupts until setup is complete. */ - sc->aps_sc.sc_invalid = 1; + sc->sc_invalid = 1; - dev = &sc->aps_sc.sc_dev; /* XXX blech, violate layering */ + dev = &sc->sc_dev; /* use variable interface name prefix */ strncpy(dev->name, ifname, IFNAMSIZ - sizeof("%d") - 1); @@ -165,81 +167,72 @@ ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) dev->irq = pdev->irq; dev->priv = sc; - sc->aps_sc.sc_iobase = mem; + sc->sc_iobase = mem; SET_MODULE_OWNER(dev); SET_NETDEV_DEV(dev, &pdev->dev); - sc->aps_sc.sc_bdev = (void *) pdev; + sc->sc_bdev = pdev; pci_set_drvdata(pdev, dev); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) if (request_irq(dev->irq, ath_intr, IRQF_SHARED, dev->name, dev)) { -#else - if (request_irq(dev->irq, ath_intr, SA_SHIRQ, dev->name, dev)) { -#endif - printk(KERN_WARNING "%s: request_irq failed\n", dev->name); - goto bad3; + dev_err(&pdev->dev, "request_irq failed\n"); + goto err_free; } if (ath_attach(id->device, dev) != 0) - goto bad4; + goto err_irq; athname = ath_hal_probe(id->vendor, id->device); - printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n", - dev->name, athname ? athname : "Atheros ???", phymem, dev->irq); + dev_info(&pdev->dev, "%s: irq=%d\n", + athname ? athname : "Atheros ???", dev->irq); /* ready to process interrupts */ - sc->aps_sc.sc_invalid = 0; + sc->sc_invalid = 0; return 0; -bad4: +err_irq: free_irq(dev->irq, dev); -bad3: +err_free: kfree(sc); -bad2: - iounmap(mem); -bad1: - release_mem_region(phymem, pci_resource_len(pdev, 0)); -bad: +err_map: + pci_iounmap(pdev, mem); +err_reg: + pci_release_region(pdev, 0); +err_dis: pci_disable_device(pdev); - return (-ENODEV); +err: + return retval; } -static void -ath_pci_remove(struct pci_dev *pdev) +static void ath_pci_remove(struct pci_dev *pdev) { struct net_device *dev = pci_get_drvdata(pdev); - struct ath_pci_softc *sc = dev->priv; + struct ath_softc *sc = dev->priv; ath_detach(dev); - if (dev->irq) - free_irq(dev->irq, dev); - iounmap(sc->aps_sc.sc_iobase); - release_mem_region(pci_resource_start(pdev, 0), - pci_resource_len(pdev, 0)); + free_irq(dev->irq, dev); + pci_iounmap(pdev, sc->sc_iobase); + pci_release_region(pdev, 0); pci_disable_device(pdev); free_netdev(dev); } #ifdef CONFIG_PM -static int -ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) +static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) { struct net_device *dev = pci_get_drvdata(pdev); ath_suspend(dev); - PCI_SAVE_STATE(pdev, - ((struct ath_pci_softc *)dev->priv)->aps_pmstate); + pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, PCI_D3hot); - return (0); + return 0; } -static int -ath_pci_resume(struct pci_dev *pdev) +static int ath_pci_resume(struct pci_dev *pdev) { struct net_device *dev = pci_get_drvdata(pdev); u32 val; @@ -253,8 +246,7 @@ ath_pci_resume(struct pci_dev *pdev) if (err) return err; - PCI_RESTORE_STATE(pdev, - ((struct ath_pci_softc *)dev->priv)->aps_pmstate); + pci_restore_state(pdev); /* * Suspend/Resume resets the PCI configuration space, so we have to * re-disable the RETRY_TIMEOUT register (0x41) to keep @@ -267,15 +259,13 @@ ath_pci_resume(struct pci_dev *pdev) pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); ath_resume(dev); - return (0); + return 0; } #else #define ath_pci_suspend NULL #define ath_pci_resume NULL #endif /* CONFIG_PM */ -MODULE_DEVICE_TABLE(pci, ath_pci_id_table); - static struct pci_driver ath_pci_drv_id = { .name = "ath_pci", .id_table = ath_pci_id_table, @@ -288,11 +278,10 @@ static struct pci_driver ath_pci_drv_id = { /* * Module glue. */ -static char *version = ATH_PCI_VERSION " (EXPERIMENTAL)"; -static char *dev_info = "ath_pci"; +static char version[] = ATH_PCI_VERSION " (EXPERIMENTAL)"; +static char dev_info[] = "ath_pci"; -int -ath_ioctl_ethtool(struct ath_softc *sc, int cmd, void __user *addr) +int ath_ioctl_ethtool(struct ath_softc *sc, int cmd, void __user *addr) { struct ethtool_drvinfo info; @@ -302,49 +291,41 @@ ath_ioctl_ethtool(struct ath_softc *sc, int cmd, void __user *addr) info.cmd = cmd; strncpy(info.driver, dev_info, sizeof(info.driver)-1); strncpy(info.version, version, sizeof(info.version)-1); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,22) + /* include the device name so later versions of kudzu DTRT */ - strncpy(info.bus_info, pci_name((struct pci_dev *)sc->sc_bdev), - sizeof(info.bus_info)-1); -#endif + strncpy(info.bus_info, pci_name(sc->sc_bdev), sizeof(info.bus_info)-1); + return copy_to_user(addr, &info, sizeof(info)) ? -EFAULT : 0; } -MODULE_AUTHOR("Errno Consulting, Sam Leffler"); -MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); -MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); -#ifdef MODULE_LICENSE -MODULE_LICENSE("Dual BSD/GPL"); -#endif - -static int __init -init_ath_pci(void) +static int __init init_ath_pci(void) { + int ret; + printk(KERN_INFO "%s: %s\n", dev_info, version); - if (pci_register_driver(&ath_pci_drv_id) < 0) { - printk("ath_pci: No devices found, driver not installed.\n"); - pci_unregister_driver(&ath_pci_drv_id); - return (-ENODEV); + ret = pci_register_driver(&ath_pci_drv_id); + if (ret) { + printk(KERN_ERR "ath_pci: can't register pci driver\n"); + return ret; } ath_sysctl_register(); - return (0); + + return 0; } -module_init(init_ath_pci); -static void __exit -exit_ath_pci(void) +static void __exit exit_ath_pci(void) { ath_sysctl_unregister(); pci_unregister_driver(&ath_pci_drv_id); printk(KERN_INFO "%s: driver unloaded\n", dev_info); } + +module_init(init_ath_pci); module_exit(exit_ath_pci); -/* return bus cachesize in 4B word units */ -void -bus_read_cachesize(struct ath_softc *sc, u_int8_t *csz) -{ - pci_read_config_byte(sc->sc_bdev, PCI_CACHE_LINE_SIZE, csz); -} +MODULE_AUTHOR("Errno Consulting, Sam Leffler"); +MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); +MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/ath/if_ath_pci.h b/ath/if_ath_pci.h index 613d954..1d152bd 100644 --- a/ath/if_ath_pci.h +++ b/ath/if_ath_pci.h @@ -21,55 +21,20 @@ * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $Id: if_ath_pci.h 2046 2007-01-31 06:38:07Z proski $ */ #ifndef _DEV_ATH_PCI_H_ #define _DEV_ATH_PCI_H_ #include + #define bus_map_single pci_map_single #define bus_unmap_single pci_unmap_single -#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9) #define bus_dma_sync_single pci_dma_sync_single_for_cpu #define BUS_DMA_MAP_ERROR(a) pci_dma_mapping_error(a) -#define PCI_SAVE_STATE(a,b) pci_save_state(a) -#define PCI_RESTORE_STATE(a,b) pci_restore_state(a) -#else -#define bus_dma_sync_single pci_dma_sync_single -/* AFAIK we can't reliably check for DMA mapping errors on 2.4 kernels */ -#define BUS_DMA_MAP_ERROR(a) 0 -#define PCI_SAVE_STATE(a,b) pci_save_state(a,b) -#define PCI_RESTORE_STATE(a,b) pci_restore_state(a,b) -#endif #define bus_alloc_consistent pci_alloc_consistent #define bus_free_consistent pci_free_consistent #define BUS_DMA_FROMDEVICE PCI_DMA_FROMDEVICE #define BUS_DMA_TODEVICE PCI_DMA_TODEVICE -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -#define pm_message_t u32 -#endif - -#ifndef PCI_D0 -#define PCI_D0 0 -#endif - -#ifndef PCI_D3hot -#define PCI_D3hot 3 -#endif - #endif /* _DEV_ATH_PCI_H_ */ commit 92403a075407d74b2f95dca7561814f9312f96b3 Author: Jiri Slaby Date: Mon Jun 18 10:35:52 2007 +0200 rename Makefiles to Kbuilds diff --git a/ath/Kbuild b/ath/Kbuild new file mode 100644 index 0000000..808a66b --- /dev/null +++ b/ath/Kbuild @@ -0,0 +1,21 @@ +# +# Copyright (c) 2007 Jiri Slaby +# All rights reserved. +# +# This software may be distributed under the terms of the +# GNU General Public License ("GPL") version 2 as published by the Free +# Software Foundation. + +ifeq ($(strip $(BUS)),AHB) +EXTRA_CFLAGS += -DATH_AHB +bus=ath +else +EXTRA_CFLAGS += -DATH_PCI +bus=pci +endif + +obj-m += ath_$(bus).o +ath_ahb-objs := if_ath.o if_ath_ahb.o #radar.o +ath_pci-objs := if_ath.o if_ath_pci.o #radar.o + +EXTRA_CFLAGS += -I$(src)/../openhal diff --git a/ath/Makefile b/ath/Makefile deleted file mode 100644 index 808a66b..0000000 --- a/ath/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2007 Jiri Slaby -# All rights reserved. -# -# This software may be distributed under the terms of the -# GNU General Public License ("GPL") version 2 as published by the Free -# Software Foundation. - -ifeq ($(strip $(BUS)),AHB) -EXTRA_CFLAGS += -DATH_AHB -bus=ath -else -EXTRA_CFLAGS += -DATH_PCI -bus=pci -endif - -obj-m += ath_$(bus).o -ath_ahb-objs := if_ath.o if_ath_ahb.o #radar.o -ath_pci-objs := if_ath.o if_ath_pci.o #radar.o - -EXTRA_CFLAGS += -I$(src)/../openhal diff --git a/openhal/Kbuild b/openhal/Kbuild new file mode 100644 index 0000000..9007072 --- /dev/null +++ b/openhal/Kbuild @@ -0,0 +1,2 @@ +obj-m += ath_hal.o +ath_hal-objs := ah_osdep.o ath5k_hw.o ieee80211_regdomain.o diff --git a/openhal/Makefile b/openhal/Makefile deleted file mode 100644 index 38bb7b8..0000000 --- a/openhal/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-m += ath_hal.o -ath_hal-objs := ah_osdep.o ath5k_hw.o ieee80211_regdomain.o - -EXTRA_CFLAGS+=-DCONFIG_OPENHAL_COMPAT commit 0d75814f0fadabf669881951da8e7e991ce052a9 Author: Jiri Slaby Date: Mon Jun 18 16:00:00 2007 +0200 get rid of most headers since we will merge the hal and the driver together diff --git a/README b/README new file mode 100644 index 0000000..51b3814 --- /dev/null +++ b/README @@ -0,0 +1,117 @@ +Linux OpenHAL 20072703 +====================== +/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\ + * This is a port of the ar5k hal for atheros device drivers that is * + * source-compatible with the Madwifi driver for linux. * + * * + * Code ported, modified for combatibility and some bugs were fixed by * + * Nick "Mick Flemm" Kossifidis (Athens Wireless Metropolitan Network) * + * and Pavel Roskin so ar5k can work propertly * + * on Linux. * + * * + * Currently only the 5212 code has been tested due to lack of hardware. * + * * + * Some code from John Bicket's port (roofnet project) was taken, you can * + * can find his OpenHAL here -> http://pdos.csail.mit.edu/~jbicket/openhal/ * + * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * +\* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ + + +DEVELOPMENT +=========== + +We are basing our openhal on OpenBSD's ar5k. Because of this and since the GPL does not +allow us to commit changes on the GPL version back to the BSD version please sumbit your +non-linux enhancements to the HAL to "Reyk Floeter" and CC madwifi-devel. + + +About AR5K +================= +ar5k is a free replacement of the binary-only HAL used by some drivers +for Atheros chipsets. While using a different ABI, it tries to be +source-compatible with the original (non-free) HAL interface. + +It is maintained by Reyk Floeter and many others. You can find more +infos at http://team.vantronix.net/ar5k/ or inside ar5k's source. + +The ar5k hal maintained at OpenBSD +http://www.openbsd.org/cgi-bin/cvsweb/src/sys/dev/ic/#dirlist + + +About channels and regulatory domains +===================================== + +Regulatory domain restrictions are enabled by default to follow ETSI and FCC standards. +If you want to be legal you shouldn't disable regdomains, althow if you want to +experiment etc there are 2 ways you can override regdomains: + +a) Change SUPERCHANNEL to 1 (opt_ah.h) +b) Change your card's regulatory domain (EEPROM) to 0x00 + +WARNING: Whatever you do with your hardware is YOUR resposibility, don't blame the developers +if you get caught using your hardware outside legal ranges etc, you 've been warned... + +The goal of this project is to create an open-source free alternative to binary HAL from Atheros, +NOT to allow more channels/frequencies etc. + + +About AWMN +========== +Athens Wireless Metropolitan Network is a community radio network based in Athens, Greece. +Its members are node owners, comprising the Athens metropolitan area network, which at the +moment has roughly 750 active nodes, using 802.11b and 802.11a wireless technology for interconnection. + +Its aims include: + + * The development and use of community wireless network throughout the greater Athens area. + * The development of wireless technology and its implementation. + * Making the public aware of wireless networks and their use. + * Educating it's members and the public on the use and benefits of wireless networks. + +The Athens Wireless Metropolitan Network +http://www.awmn.net + + +Building +======== +To build OpenHAL with MadWiFi, place the OpenHAL source directory in the +MadWiFi directory. Edit Makefile.inc and set the following: + +HAL=${DEPTH}/ +ATH_HAL=${DEPTH}/ + +After that, go to the top directory and build like you normally would. + +WARNING: Don't delete the empty files included (ah_desc.h etc) + +Note: Currenty works for MadWiFi-old + +Use +===== +You 'll have to set everything propertly for things to work +e.g. you 'll first need to set the mode (a/b/g) using + +iwpriv mode X + +Then if you want to use it as an AP you'll have to set channel + +iwconfig athX channel x + +Txpower currently seems to be buggy, in measurements I did it seems that +tx power differs from -56 to -41 dbm, setting txpower does change txpower +but not in a normal way -needs revision. + + +TODO +==== +* Lot's of tests and fixes. +* Make it combatible with newer versions of MadWiFi (after the merge). +* Test 5210/5211 code. diff --git a/ath/if_ath.c b/ath/if_ath.c index 81f0ca1..f2a6748 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -70,9 +70,7 @@ /*#include "radar.h"*/ #include "if_athvar.h" -#include "ah_desc.h" -#include "ah_devid.h" /* XXX to identify IBM cards */ -#include "ah.h" +#include "ath5k.h" #ifdef ATH_PCI /* PCI BUS */ #include "if_ath_pci.h" @@ -555,7 +553,8 @@ ath_attach(u_int16_t devid, struct net_device *dev) * 5211 minipci cards. Users can also manually enable/disable * support with a sysctl. */ - sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); + sc->sc_softled = (devid == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || + devid == PCI_DEVICE_ID_ATHEROS_AR5211); if (sc->sc_softled) { ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); diff --git a/ath/if_athvar.h b/ath/if_athvar.h index cb707cd..0df6d40 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -46,7 +46,7 @@ #include #include -#include "ah.h" +#include "ath5k.h" #include "if_athioctl.h" #include "if_athrate.h" diff --git a/openhal/README b/openhal/README deleted file mode 100644 index 51b3814..0000000 --- a/openhal/README +++ /dev/null @@ -1,117 +0,0 @@ -Linux OpenHAL 20072703 -====================== -/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\ - * This is a port of the ar5k hal for atheros device drivers that is * - * source-compatible with the Madwifi driver for linux. * - * * - * Code ported, modified for combatibility and some bugs were fixed by * - * Nick "Mick Flemm" Kossifidis (Athens Wireless Metropolitan Network) * - * and Pavel Roskin so ar5k can work propertly * - * on Linux. * - * * - * Currently only the 5212 code has been tested due to lack of hardware. * - * * - * Some code from John Bicket's port (roofnet project) was taken, you can * - * can find his OpenHAL here -> http://pdos.csail.mit.edu/~jbicket/openhal/ * - * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * -\* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ - - -DEVELOPMENT -=========== - -We are basing our openhal on OpenBSD's ar5k. Because of this and since the GPL does not -allow us to commit changes on the GPL version back to the BSD version please sumbit your -non-linux enhancements to the HAL to "Reyk Floeter" and CC madwifi-devel. - - -About AR5K -================= -ar5k is a free replacement of the binary-only HAL used by some drivers -for Atheros chipsets. While using a different ABI, it tries to be -source-compatible with the original (non-free) HAL interface. - -It is maintained by Reyk Floeter and many others. You can find more -infos at http://team.vantronix.net/ar5k/ or inside ar5k's source. - -The ar5k hal maintained at OpenBSD -http://www.openbsd.org/cgi-bin/cvsweb/src/sys/dev/ic/#dirlist - - -About channels and regulatory domains -===================================== - -Regulatory domain restrictions are enabled by default to follow ETSI and FCC standards. -If you want to be legal you shouldn't disable regdomains, althow if you want to -experiment etc there are 2 ways you can override regdomains: - -a) Change SUPERCHANNEL to 1 (opt_ah.h) -b) Change your card's regulatory domain (EEPROM) to 0x00 - -WARNING: Whatever you do with your hardware is YOUR resposibility, don't blame the developers -if you get caught using your hardware outside legal ranges etc, you 've been warned... - -The goal of this project is to create an open-source free alternative to binary HAL from Atheros, -NOT to allow more channels/frequencies etc. - - -About AWMN -========== -Athens Wireless Metropolitan Network is a community radio network based in Athens, Greece. -Its members are node owners, comprising the Athens metropolitan area network, which at the -moment has roughly 750 active nodes, using 802.11b and 802.11a wireless technology for interconnection. - -Its aims include: - - * The development and use of community wireless network throughout the greater Athens area. - * The development of wireless technology and its implementation. - * Making the public aware of wireless networks and their use. - * Educating it's members and the public on the use and benefits of wireless networks. - -The Athens Wireless Metropolitan Network -http://www.awmn.net - - -Building -======== -To build OpenHAL with MadWiFi, place the OpenHAL source directory in the -MadWiFi directory. Edit Makefile.inc and set the following: - -HAL=${DEPTH}/ -ATH_HAL=${DEPTH}/ - -After that, go to the top directory and build like you normally would. - -WARNING: Don't delete the empty files included (ah_desc.h etc) - -Note: Currenty works for MadWiFi-old - -Use -===== -You 'll have to set everything propertly for things to work -e.g. you 'll first need to set the mode (a/b/g) using - -iwpriv mode X - -Then if you want to use it as an AP you'll have to set channel - -iwconfig athX channel x - -Txpower currently seems to be buggy, in measurements I did it seems that -tx power differs from -56 to -41 dbm, setting txpower does change txpower -but not in a normal way -needs revision. - - -TODO -==== -* Lot's of tests and fixes. -* Make it combatible with newer versions of MadWiFi (after the merge). -* Test 5210/5211 code. diff --git a/openhal/ah.h b/openhal/ah.h deleted file mode 100644 index f7e2f2b..0000000 --- a/openhal/ah.h +++ /dev/null @@ -1 +0,0 @@ -#include "ath5k.h" diff --git a/openhal/ah_desc.h b/openhal/ah_desc.h deleted file mode 100644 index e69de29..0000000 diff --git a/openhal/ah_devid.h b/openhal/ah_devid.h deleted file mode 100644 index f17813b..0000000 --- a/openhal/ah_devid.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Device IDs... - * - */ - -/* From /dev/pci/pcidevs.h also incudes updates from the binary HAL's ah_devid.h */ - -/*Products*/ -#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ -#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ -#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ -#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ -#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ -#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ -#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ -#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ - -#define AR5K_DEVID_AR2413 PCI_DEVICE_ID_ATHEROS_AR2413 -#define AR5K_DEVID_AR5413 PCI_DEVICE_ID_ATHEROS_AR5413 -#define AR5K_DEVID_AR5424 PCI_DEVICE_ID_ATHEROS_AR5424 - - -/*Combatibility with MadWiFi's definitions (bimary HAL)*/ - -#define ATHEROS_VENDOR_ID PCI_VENDOR_ATHEROS /* Atheros PCI vendor ID */ -#define ATHEROS_3COM_VENDOR_ID PCI_VENDOR_3COM2 /* 3Com 3CRPAG175 vendor ID */ -#define ATHEROS_3COM2_VENDOR_ID PCI_VENDOR_3COM /* 3Com 3CRDAG675 vendor ID */ - -/* AR5210 (for reference) */ -#define AR5210_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT /* No eeprom HW default */ -#define AR5210_PROD PCI_DEVICE_ID_ATHEROS_AR5210 /* Final device ID */ -#define AR5210_AP PCI_DEVICE_ID_ATHEROS_AR5210_AP /* Early AP11s */ - -/* AR5211 */ -#define AR5211_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT /* No eeprom HW default */ -#define AR5311_DEVID PCI_DEVICE_ID_ATHEROS_AR5311 /* Final ar5311 devid */ -#define AR5211_DEVID PCI_DEVICE_ID_ATHEROS_AR5211 /* Final ar5211 devid */ -#define AR5211_LEGACY PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY /* Original emulation board */ -#define AR5211_FPGA11B PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B /* 11b emulation board */ - -/* AR5212 */ -#define AR5212_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT /* No eeprom HW default */ -#define AR5212_DEVID PCI_DEVICE_ID_ATHEROS_AR5212 /* Final ar5212 devid */ -#define AR5212_FPGA PCI_DEVICE_ID_ATHEROS_AR5212_FPGA /* Emulation board */ -#define AR5212_DEVID_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM /* IBM minipci ID */ -#define AR5212_AR5312_REV2 PCI_DEVICE_ID_ATHEROS_AR5212_REV2 /* AR5312 WMAC (AP31) */ -#define AR5212_AR5312_REV7 PCI_DEVICE_ID_ATHEROS_AR5212_REV7 /* AR5312 WMAC (AP30-040) */ -#define AR5212_AR2313_REV8 PCI_DEVICE_ID_ATHEROS_AR5212_REV8 /* AR2313 WMAC (AP43-030) */ - -/* AR5212 compatible devid's also attach to 5212 */ -#define AR5212_DEVID_0014 PCI_DEVICE_ID_ATHEROS_AR5212_0014 -#define AR5212_DEVID_0015 PCI_DEVICE_ID_ATHEROS_AR5212_0015 -#define AR5212_DEVID_0016 PCI_DEVICE_ID_ATHEROS_AR5212_0016 -#define AR5212_DEVID_0017 PCI_DEVICE_ID_ATHEROS_AR5212_0017 -#define AR5212_DEVID_0018 PCI_DEVICE_ID_ATHEROS_AR5212_0018 -#define AR5212_DEVID_0019 PCI_DEVICE_ID_ATHEROS_AR5212_0019 -#define AR5212_AR2413 PCI_DEVICE_ID_ATHEROS_AR2413 /* AR2413 aka Griffin-lite */ -#define AR5212_AR5413 PCI_DEVICE_ID_ATHEROS_AR5413 /* Eagle */ -#define AR5212_AR5424 PCI_DEVICE_ID_ATHEROS_AR5424 /* Condor (PCI express) */ - -/*Not-supported by OpenHAL*/ -/* AR5213 */ -#define AR5213_SREV_1_0 0x0055 -#define AR5213_SREV_REG 0x4020 - -#define AR_SUBVENDOR_ID_NOG 0x0e11 /* No 11G subvendor ID */ -#define AR_SUBVENDOR_ID_NEW_A 0x7065 /* Update device to new RD */ diff --git a/openhal/ah_osdep.h b/openhal/ah_osdep.h deleted file mode 100644 index 3b0661e..0000000 --- a/openhal/ah_osdep.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - */ - -#include - -#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) -#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) -#ifdef AR5K_DEBUG -#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) -#else -#define AR5K_TRACE -#endif diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 07a146e..830612b 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -33,28 +33,60 @@ #ifndef _AR5K_H #define _AR5K_H +/* Set this to 1 to disable regulatory domain restrictions for channel tests. + * WARNING: This is for debuging only and has side effects (eg. scan takes too long + * and results timeouts). It's also illegal to tune to some of the supported frequencies + * in some countries, so use this at your own risk, you 've been warned. */ +#define CHAN_DEBUG 0 + +/* Uncomment this for debuging (warning that results TOO much output) */ +/*#define AR5K_DEBUG 1 */ + #include -/*Os dependent definitions*/ -#include "ah_osdep.h" #include "ath5k_hw.h" - -/*Regulatory domain & Channel definitions*/ #include "ieee80211_regdomain.h" - -/*Options*/ -#include "opt_ah.h" - -/* - *Translation for MadWiFi combatibility - *(damn this is changed AGAIN in if_ath.pci :P) - */ #include "translation.h" +/* PCI IDs */ +#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ +#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ +#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ +#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ +#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ +#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ +#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ +#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ + /****************************\ GENERIC DRIVER DEFINITIONS \****************************/ +#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) +#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) +#ifdef AR5K_DEBUG +#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) +#else +#define AR5K_TRACE +#endif #define howmany(x, y) (((x)+((y)-1))/(y)) /* @@ -154,9 +186,9 @@ struct ath5k_srev_name { { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ - { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \ - { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \ - { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \ + { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ + { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ + { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ } @@ -1218,69 +1250,4 @@ extern u_int ath_hal_getwirelessmodes(struct ath_hal *, enum ieee80211_countryc void ath_hal_detach(struct ath_hal *ah); struct ath_hal *ath_hal_attach(u16 devid, void *sc, void __iomem *h, enum ath5k_status *s); - -/* COMPAT stuff */ - -#ifdef CONFIG_OPENHAL_COMPAT -typedef u32 ieee80211_regdomain_t; - -typedef struct ath5k_node_stats AR5K_NODE_STATS; -typedef struct ath5k_rate_table AR5K_RATE_TABLE; -typedef struct ath5k_channel AR5K_CHANNEL; -typedef struct ath5k_keyval AR5K_KEYVAL; -typedef struct ath5k_txq_info AR5K_TXQ_INFO; - -typedef enum ieee80211_if_types AR5K_OPMODE; -typedef enum ath5k_int AR5K_INT; -typedef enum ath5k_status AR5K_STATUS; -typedef enum ath5k_pkt_type AR5K_PKT_TYPE; - -typedef void *AR5K_SOFTC; -typedef int AR5K_BUS_TAG; -typedef __iomem void *AR5K_BUS_HANDLE; -typedef u_int32_t AR5K_BUS_ADDR; - -typedef bool AR5K_BOOL; - -#define TRUE true -#define FALSE false - -#define AR5K_M_STA IEEE80211_IF_TYPE_STA -#define AR5K_M_IBSS IEEE80211_IF_TYPE_IBSS -#define AR5K_M_HOSTAP IEEE80211_IF_TYPE_AP -#define AR5K_M_MONITOR IEEE80211_IF_TYPE_MNTR - -#define PCI_PRODUCT_ATHEROS_AR5210_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT -#define PCI_PRODUCT_ATHEROS_AR5210 PCI_DEVICE_ID_ATHEROS_AR5210 -#define PCI_PRODUCT_ATHEROS_AR5210_AP PCI_DEVICE_ID_ATHEROS_AR5210_AP -#define PCI_PRODUCT_ATHEROS_AR5212_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM -#define PCI_PRODUCT_ATHEROS_AR5211 PCI_DEVICE_ID_ATHEROS_AR5211 -#define PCI_PRODUCT_ATHEROS_AR5211_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT -#define PCI_PRODUCT_ATHEROS_AR5311 PCI_DEVICE_ID_ATHEROS_AR5311 -#define PCI_PRODUCT_ATHEROS_AR5211_LEGACY PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY -#define PCI_PRODUCT_ATHEROS_AR5211_FPGA11B PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B -#define PCI_PRODUCT_ATHEROS_AR5212_DEFAULT PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT -#define PCI_PRODUCT_ATHEROS_AR5212 PCI_DEVICE_ID_ATHEROS_AR5212 -#define PCI_PRODUCT_ATHEROS_AR5212_FPGA PCI_DEVICE_ID_ATHEROS_AR5212_FPGA -#define PCI_PRODUCT_ATHEROS_AR5212_IBM PCI_DEVICE_ID_ATHEROS_AR5212_IBM -#define PCI_PRODUCT_ATHEROS_AR5212_REV2 PCI_DEVICE_ID_ATHEROS_AR5212_REV2 -#define PCI_PRODUCT_ATHEROS_AR5212_REV7 PCI_DEVICE_ID_ATHEROS_AR5212_REV7 -#define PCI_PRODUCT_ATHEROS_AR5212_REV8 PCI_DEVICE_ID_ATHEROS_AR5212_REV8 -#define PCI_PRODUCT_ATHEROS_AR5212_0014 PCI_DEVICE_ID_ATHEROS_AR5212_0014 -#define PCI_PRODUCT_ATHEROS_AR5212_0015 PCI_DEVICE_ID_ATHEROS_AR5212_0015 -#define PCI_PRODUCT_ATHEROS_AR5212_0016 PCI_DEVICE_ID_ATHEROS_AR5212_0016 -#define PCI_PRODUCT_ATHEROS_AR5212_0017 PCI_DEVICE_ID_ATHEROS_AR5212_0017 -#define PCI_PRODUCT_ATHEROS_AR5212_0018 PCI_DEVICE_ID_ATHEROS_AR5212_0018 -#define PCI_PRODUCT_ATHEROS_AR5212_0019 PCI_DEVICE_ID_ATHEROS_AR5212_0019 -#define PCI_PRODUCT_ATHEROS_AR2413 PCI_DEVICE_ID_ATHEROS_AR2413 -#define PCI_PRODUCT_ATHEROS_AR5413 PCI_DEVICE_ID_ATHEROS_AR5413 -#define PCI_PRODUCT_ATHEROS_AR5424 PCI_DEVICE_ID_ATHEROS_AR5424 - -static inline struct ath_hal *_ath_hal_attach(u16 devid, AR5K_SOFTC sc, - AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void *s) -{ - return ath_hal_attach(devid, sc, h, s); -} -#endif - #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 4a1e44c..df0b1ec 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -27,7 +27,6 @@ #include #include -#include "ah_devid.h" #include "ath5k.h" #include "ath5kreg.h" diff --git a/openhal/ieee80211_regdomain.c b/openhal/ieee80211_regdomain.c index 172c0dc..4c0fd06 100644 --- a/openhal/ieee80211_regdomain.c +++ b/openhal/ieee80211_regdomain.c @@ -10,7 +10,9 @@ * Basic regulation domain extensions for the IEEE 802.11 stack */ -#include "ah_osdep.h" +#include +#include + #include "ieee80211_regdomain.h" static const struct ieee80211_regdomainname diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 1c68e8f..7df7990 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -19,6 +19,8 @@ #ifndef _NET80211_IEEE80211_REGDOMAIN_H_ #define _NET80211_IEEE80211_REGDOMAIN_H_ +#include + enum ieee80211_regdomain { DMN_DEFAULT = 0x00, DMN_NULL_WORLD = 0x03, @@ -766,7 +768,6 @@ struct ieee80211_regchannel { { 5240, DMN_WORLD, CHANNEL_OFDM }, \ } - extern u16 ieee80211_name2countrycode(const char *); extern u32 ieee80211_name2regdomain(const char *); extern const char *ieee80211_countrycode2name(u16); @@ -774,5 +775,4 @@ extern const char *ieee80211_regdomain2name(u32); extern u32 ieee80211_regdomain2flag(u16, u16); extern u32 ieee80211_countrycode2regdomain(u16); - #endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ diff --git a/openhal/opt_ah.h b/openhal/opt_ah.h index b92921a..e69de29 100644 --- a/openhal/opt_ah.h +++ b/openhal/opt_ah.h @@ -1,8 +0,0 @@ -/* Set this to 1 to disable regulatory domain restrictions for channel tests. - * WARNING: This is for debuging only and has side effects (eg. scan takes too long - * and results timeouts). It's also illegal to tune to some of the supported frequencies - * in some countries, so use this at your own risk, you 've been warned. */ -#define CHAN_DEBUG 0 - -/* Uncomment this for debuging (warning that results TOO much output) */ -//#define AR5K_DEBUG 1 commit 4f3d02e4c43a03e7b3c35dbfc5873675013b1445 Author: Jiri Slaby Date: Mon Jun 18 17:11:57 2007 +0200 remove unused functions from ieee80211_regdomain diff --git a/openhal/ieee80211_regdomain.c b/openhal/ieee80211_regdomain.c index 4c0fd06..a2fd25a 100644 --- a/openhal/ieee80211_regdomain.c +++ b/openhal/ieee80211_regdomain.c @@ -15,98 +15,61 @@ #include "ieee80211_regdomain.h" -static const struct ieee80211_regdomainname -ieee80211_r_names[] = IEEE80211_REGDOMAIN_NAMES; - -static const struct ieee80211_regdomainmap -ieee80211_r_map[] = IEEE80211_REGDOMAIN_MAP; - -static const struct ieee80211_countryname -ieee80211_r_ctry[] = IEEE80211_REGDOMAIN_COUNTRY_NAMES; - -#ifndef bsearch -static const void *bsearch(const void *key, const void *base0, size_t nmemb, - size_t size, int (*compar)(const void *, const void *)) -{ - const char *base = base0; - int lim, cmp; - const void *p; - - for (lim = nmemb; lim != 0; lim /= 2) { - p = base + (lim / 2) * size; - cmp = (*compar)(key, p); - if (cmp == 0) - return p; - if (cmp > 0) { /* key > p: move right */ - base = p + size; - lim--; - } /* else move left */ - } - return NULL; -} -#endif - -static int ieee80211_regdomain_compare_cn(const void *a, const void *b) -{ - const struct ieee80211_countryname *ca = a, *cb = b; - return strcmp(ca->cn_name, cb->cn_name); -} - -static int ieee80211_regdomain_compare_rn(const void *a, const void *b) -{ - const struct ieee80211_regdomainname *ra = a, *rb = b; - return strcmp(ra->rn_name, rb->rn_name); -} - -u16 ieee80211_name2countrycode(const char *name) -{ - const struct ieee80211_countryname key = { CTRY_DEFAULT, name }, *value; - - value = bsearch(&key, &ieee80211_r_ctry, ARRAY_SIZE(ieee80211_r_ctry), - sizeof(struct ieee80211_countryname), - ieee80211_regdomain_compare_cn); - if (value != 0) - return value->cn_code; - - return CTRY_DEFAULT; -} - -u32 ieee80211_name2regdomain(const char *name) -{ - const struct ieee80211_regdomainname key = { DMN_DEFAULT, name },*value; - - value = bsearch(&key, &ieee80211_r_names, ARRAY_SIZE(ieee80211_r_names), - sizeof(struct ieee80211_regdomainname), - ieee80211_regdomain_compare_rn); - if (value != 0) - return (u32)value->rn_domain; - - return (u32)DMN_DEFAULT; -} - -const char *ieee80211_countrycode2name(u16 code) -{ - unsigned int i; - - /* Linear search over the table */ - for (i = 0; i < ARRAY_SIZE(ieee80211_r_ctry); i++) - if (ieee80211_r_ctry[i].cn_code == code) - return ieee80211_r_ctry[i].cn_name; - - return NULL; -} - -const char *ieee80211_regdomain2name(u_int32_t regdomain) -{ - unsigned int i; - - /* Linear search over the table */ - for (i = 0; i < ARRAY_SIZE(ieee80211_r_names); i++) - if (ieee80211_r_names[i].rn_domain == regdomain) - return ieee80211_r_names[i].rn_name; - - return ieee80211_r_names[0].rn_name; -} +static const struct ieee80211_regdomainmap { + u16 rm_domain; + u32 rm_domain_5ghz; + u32 rm_domain_2ghz; +} ieee80211_r_map[] = { + { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, + { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, + { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, + { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, + { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, + { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, + { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, + { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, + { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, + { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, + { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, + { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, + { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, + { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, + { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, + { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, + { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, + { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, + { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, + { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, + { DMN_APL_NULL, DMN_APL1, DMN_NULL }, + { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, + { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, + { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, + { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, + { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, + { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, + { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, + { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, + { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, + { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, + { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, + { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, + { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, + { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, +}; u32 ieee80211_regdomain2flag(u16 regdomain, u16 mhz) { @@ -124,14 +87,3 @@ u32 ieee80211_regdomain2flag(u16 regdomain, u16 mhz) return (u32)DMN_DEBUG; } - -u32 ieee80211_countrycode2regdomain(u16 code) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(ieee80211_r_ctry); i++) - if (ieee80211_r_ctry[i].cn_code == code) - return ieee80211_r_ctry[i].cn_domain; - - return (u32)DMN_DEFAULT; -} diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 7df7990..8d9ad74 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -1,19 +1,9 @@ -/* $OpenBSD: ieee80211_regdomain.h,v 1.8 2005/12/18 17:59:59 reyk Exp $ */ - /* * Copyright (c) 2004, 2005 Reyk Floeter * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef _NET80211_IEEE80211_REGDOMAIN_H_ @@ -101,146 +91,6 @@ enum ieee80211_regdomain { #define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) -struct ieee80211_regdomainname { - u32 rn_domain; - const char *rn_name; -}; - -#define IEEE80211_REGDOMAIN_NAMES { \ - { DMN_APL1, "APL1" }, \ - { DMN_APL1_APLA, "APL1A" }, \ - { DMN_APL1_ETSIC, "APL1_ETSIC" }, \ - { DMN_APL1_FCCA, "APL1_FCCA" }, \ - { DMN_APL1_WORLD, "APL1W" }, \ - { DMN_APL2, "APL2" }, \ - { DMN_APL2_APLC, "APL2C" }, \ - { DMN_APL2_APLD, "APL2D" }, \ - { DMN_APL2_ETSIC, "APL2_ETSIC" }, \ - { DMN_APL2_WORLD, "APL2W" }, \ - { DMN_APL3, "APL3" }, \ - { DMN_APL3_WORLD, "APL3W" }, \ - { DMN_APL4, "APL4" }, \ - { DMN_APL4_WORLD, "APL4W" }, \ - { DMN_APL5, "APL5" }, \ - { DMN_APL5_WORLD, "APL5W" }, \ - { DMN_APLD, "APLD" }, \ - { DMN_APL_NULL, "APL" }, \ - { DMN_DEBUG, "DEBUG" }, \ - { DMN_ETSI1, "ETSI1" }, \ - { DMN_ETSI1_WORLD, "ETSI1W" }, \ - { DMN_ETSI2, "ETSI2" }, \ - { DMN_ETSI2_WORLD, "ETSI2W" }, \ - { DMN_ETSI3, "ETSI3" }, \ - { DMN_ETSI3_ETSIA, "ETSI3A" }, \ - { DMN_ETSI3_WORLD, "ETSI3W," }, \ - { DMN_ETSI4, "ETSI4" }, \ - { DMN_ETSI4_ETSIC, "ETSI4C" }, \ - { DMN_ETSI4_WORLD, "ETSI4W" }, \ - { DMN_ETSI5, "ETSI5" }, \ - { DMN_ETSI5_WORLD, "ETSI5W" }, \ - { DMN_ETSI6, "ETSI6" }, \ - { DMN_ETSI6_WORLD, "ETSI6W" }, \ - { DMN_ETSIA, "ETSIA" }, \ - { DMN_ETSIB, "ETSIB" }, \ - { DMN_ETSIC, "ETSIC" }, \ - { DMN_ETSI_NULL, "ETSI" }, \ - { DMN_EU1_WORLD, "EU1W" }, \ - { DMN_FCC1, "FCC1" }, \ - { DMN_FCC1_FCCA, "FCC1A" }, \ - { DMN_FCC1_WORLD, "FCC1W" }, \ - { DMN_FCC2, "FCC2" }, \ - { DMN_FCC2_ETSIC, "FCC2C" }, \ - { DMN_FCC2_FCCA, "FCC2A" }, \ - { DMN_FCC2_WORLD, "FCC2W" }, \ - { DMN_FCC3, "FCC3" }, \ - { DMN_FCC3_FCCA, "FCC3A" }, \ - { DMN_FCCA, "FCCA" }, \ - { DMN_FRANCE_NULL, "FRANCE" }, \ - { DMN_MKK1, "MKK1" }, \ - { DMN_MKK1_FCCA, "MKK1_FCCA" }, \ - { DMN_MKK1_MKKA, "MKK1A" }, \ - { DMN_MKK1_MKKA1, "MKK1A1" }, \ - { DMN_MKK1_MKKA2, "MKK1A2" }, \ - { DMN_MKK1_MKKB, "MKK1B" }, \ - { DMN_MKK2, "MKK2" }, \ - { DMN_MKK2_MKKA, "MKK2A" }, \ - { DMN_MKKA, "MKKA" }, \ - { DMN_DEFAULT, "NONE" }, \ - { DMN_NULL, "NONE" }, \ - { DMN_NULL_ETSIB, "ETSIB" }, \ - { DMN_NULL_ETSIC, "ETSIC" }, \ - { DMN_WOR01_WORLD, "WOR01W" }, \ - { DMN_WOR02_WORLD, "WOR02W" }, \ - { DMN_WOR0_WORLD, "WOR0W" }, \ - { DMN_WOR1_WORLD, "WOR1W" }, \ - { DMN_WOR2_WORLD, "WOR2W" }, \ - { DMN_WOR3_WORLD, "WOR3W" }, \ - { DMN_WOR4_WORLD, "WOR4W" }, \ - { DMN_WOR5_ETSIC, "WOR5_ETSIC" }, \ - { DMN_WOR9_WORLD, "WOR9W" }, \ - { DMN_WORA_WORLD, "WORAW" }, \ - { DMN_NULL_WORLD, "WORLD" }, \ - { DMN_WORLD, "WORLD" } \ -} - -struct ieee80211_regdomainmap { - u16 rm_domain; - u32 rm_domain_5ghz; - u32 rm_domain_2ghz; -}; - -#define IEEE80211_REGDOMAIN_MAP { \ - { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, \ - { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, \ - { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, \ - { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, \ - { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, \ - { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, \ - { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, \ - { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, \ - { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, \ - { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, \ - { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, \ - { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, \ - { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, \ - { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, \ - { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, \ - { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, \ - { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, \ - { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, \ - { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, \ - { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, \ - { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, \ - { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, \ - { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, \ - { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, \ - { DMN_APL_NULL, DMN_APL1, DMN_NULL }, \ - { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, \ - { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, \ - { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, \ - { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, \ - { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, \ - { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, \ - { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, \ - { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, \ - { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, \ - { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, \ - { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, \ - { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, \ - { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, \ - { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, \ - { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, \ -} - enum ieee80211_countrycode { CTRY_DEFAULT = 0, /* Default domain (NA) */ CTRY_ALBANIA = 8, /* Albania */ @@ -360,143 +210,6 @@ enum ieee80211_countrycode { CTRY_ZIMBABWE = 716, /* Zimbabwe */ }; -struct ieee80211_countryname { - u16 cn_code; - const char *cn_name; - u32 cn_domain; -}; - -#define IEEE80211_REGDOMAIN_COUNTRY_NAMES { \ - { CTRY_DEFAULT, "00", DMN_DEFAULT }, \ - { CTRY_UAE, "ae", DMN_NULL_WORLD }, \ - { CTRY_ALBANIA, "al", DMN_NULL_WORLD }, \ - { CTRY_ARMENIA, "am", DMN_ETSI4_WORLD }, \ - { CTRY_ARGENTINA, "ar", DMN_APL3_WORLD }, \ - { CTRY_AUSTRIA, "at", DMN_ETSI5_WORLD }, \ - { CTRY_AUSTRALIA, "au", DMN_FCC2_WORLD }, \ - { CTRY_AZERBAIJAN, "az", DMN_ETSI4_WORLD }, \ - { CTRY_BELGIUM, "be", DMN_ETSI4_WORLD }, \ - { CTRY_BULGARIA, "bg", DMN_ETSI6_WORLD }, \ - { CTRY_BAHRAIN, "bh", DMN_NULL_WORLD }, \ - { CTRY_BRUNEI_DARUSSALAM, "bn", DMN_APL1_WORLD }, \ - { CTRY_BOLIVIA, "bo", DMN_APL1_ETSIC }, \ - { CTRY_BRAZIL, "br", DMN_NULL_ETSIC }, \ - { CTRY_BELARUS, "by", DMN_NULL_WORLD }, \ - { CTRY_BELIZE, "bz", DMN_NULL_ETSIC }, \ - { CTRY_CANADA, "ca", DMN_FCC2_FCCA }, \ - { CTRY_SWITZERLAND, "ch", DMN_ETSI2_WORLD }, \ - { CTRY_CHILE, "cl", DMN_APL5_WORLD }, \ - { CTRY_CHINA, "cn", DMN_APL1_WORLD }, \ - { CTRY_COLOMBIA, "co", DMN_FCC1_FCCA }, \ - { CTRY_COSTA_RICA, "cr", DMN_NULL_WORLD }, \ - { CTRY_CYPRUS, "cy", DMN_ETSI1_WORLD }, \ - { CTRY_CZECH, "cz", DMN_ETSI3_WORLD }, \ - { CTRY_GERMANY, "de", DMN_ETSI1_WORLD }, \ - { CTRY_DENMARK, "dk", DMN_ETSI1_WORLD }, \ - { CTRY_DOMINICAN_REPUBLIC, "do", DMN_FCC1_FCCA }, \ - { CTRY_ALGERIA, "dz", DMN_NULL_WORLD }, \ - { CTRY_ECUADOR, "ec", DMN_NULL_WORLD }, \ - { CTRY_ESTONIA, "ee", DMN_ETSI1_WORLD }, \ - { CTRY_EGYPT, "eg", DMN_NULL_WORLD }, \ - { CTRY_SPAIN, "es", DMN_ETSI1_WORLD }, \ - { CTRY_FRANCE2, "f2", DMN_ETSI3_WORLD }, \ - { CTRY_FINLAND, "fi", DMN_ETSI1_WORLD }, \ - { CTRY_FAEROE_ISLANDS, "fo", DMN_NULL_WORLD }, \ - { CTRY_FRANCE, "fr", DMN_ETSI3_WORLD }, \ - { CTRY_GEORGIA, "ge", DMN_ETSI4_WORLD }, \ - { CTRY_GREECE, "gr", DMN_NULL_WORLD }, \ - { CTRY_GUATEMALA, "gt", DMN_FCC1_FCCA }, \ - { CTRY_HONG_KONG, "hk", DMN_FCC2_WORLD }, \ - { CTRY_HONDURAS, "hn", DMN_NULL_WORLD }, \ - { CTRY_CROATIA, "hr", DMN_ETSI3_WORLD }, \ - { CTRY_HUNGARY, "hu", DMN_ETSI2_WORLD }, \ - { CTRY_INDONESIA, "id", DMN_NULL_WORLD }, \ - { CTRY_IRELAND, "ie", DMN_ETSI1_WORLD }, \ - { CTRY_ISRAEL, "il", DMN_NULL_WORLD }, \ - { CTRY_INDIA, "in", DMN_NULL_WORLD }, \ - { CTRY_IRAQ, "iq", DMN_NULL_WORLD }, \ - { CTRY_IRAN, "ir", DMN_APL1_WORLD }, \ - { CTRY_ICELAND, "is", DMN_ETSI1_WORLD }, \ - { CTRY_ITALY, "it", DMN_ETSI1_WORLD }, \ - { CTRY_JAPAN1, "j1", DMN_MKK1_MKKB }, \ - { CTRY_JAPAN2, "j2", DMN_MKK1_FCCA }, \ - { CTRY_JAPAN3, "j3", DMN_MKK2_MKKA }, \ - { CTRY_JAPAN4, "j4", DMN_MKK1_MKKA1 }, \ - { CTRY_JAPAN5, "j5", DMN_MKK1_MKKA2 }, \ - { CTRY_JAMAICA, "jm", DMN_NULL_WORLD }, \ - { CTRY_JORDAN, "jo", DMN_NULL_WORLD }, \ - { CTRY_JAPAN, "jp", DMN_MKK1_MKKA }, \ - { CTRY_KOREA_ROC2, "k2", DMN_APL2_APLD }, \ - { CTRY_KENYA, "ke", DMN_NULL_WORLD }, \ - { CTRY_KOREA_NORTH, "kp", DMN_APL2_WORLD }, \ - { CTRY_KOREA_ROC, "kr", DMN_APL2_WORLD }, \ - { CTRY_KUWAIT, "kw", DMN_NULL_WORLD }, \ - { CTRY_KAZAKHSTAN, "kz", DMN_NULL_WORLD }, \ - { CTRY_LEBANON, "lb", DMN_NULL_WORLD }, \ - { CTRY_LIECHTENSTEIN, "li", DMN_ETSI2_WORLD }, \ - { CTRY_SRI_LANKA, "lk", DMN_NULL_WORLD }, \ - { CTRY_LITHUANIA, "lt", DMN_ETSI1_WORLD }, \ - { CTRY_LUXEMBOURG, "lu", DMN_ETSI1_WORLD }, \ - { CTRY_LATVIA, "lv", DMN_NULL_WORLD }, \ - { CTRY_LIBYA, "ly", DMN_NULL_WORLD }, \ - { CTRY_MOROCCO, "ma", DMN_NULL_WORLD }, \ - { CTRY_MONACO, "mc", DMN_ETSI4_WORLD }, \ - { CTRY_MACEDONIA, "mk", DMN_NULL_WORLD }, \ - { CTRY_MACAU, "mo", DMN_FCC2_WORLD }, \ - { CTRY_MEXICO, "mx", DMN_FCC1_FCCA }, \ - { CTRY_MALAYSIA, "my", DMN_NULL_WORLD }, \ - { CTRY_NICARAGUA, "ni", DMN_NULL_WORLD }, \ - { CTRY_NETHERLANDS, "nl", DMN_ETSI1_WORLD }, \ - { CTRY_NORWAY, "no", DMN_ETSI1_WORLD }, \ - { CTRY_NEW_ZEALAND, "nz", DMN_FCC2_ETSIC }, \ - { CTRY_OMAN, "om", DMN_NULL_WORLD }, \ - { CTRY_PANAMA, "pa", DMN_FCC1_FCCA }, \ - { CTRY_PERU, "pe", DMN_NULL_WORLD }, \ - { CTRY_PHILIPPINES, "ph", DMN_FCC1_WORLD }, \ - { CTRY_PAKISTAN, "pk", DMN_NULL_WORLD }, \ - { CTRY_POLAND, "pl", DMN_ETSI1_WORLD }, \ - { CTRY_PUERTO_RICO, "pr", DMN_FCC1_FCCA }, \ - { CTRY_PORTUGAL, "pt", DMN_ETSI1_WORLD }, \ - { CTRY_PARAGUAY, "py", DMN_NULL_WORLD }, \ - { CTRY_QATAR, "qa", DMN_NULL_WORLD }, \ - { CTRY_ROMANIA, "ro", DMN_NULL_WORLD }, \ - { CTRY_RUSSIA, "ru", DMN_NULL_WORLD }, \ - { CTRY_SAUDI_ARABIA, "sa", DMN_NULL_WORLD }, \ - { CTRY_SWEDEN, "se", DMN_ETSI1_WORLD }, \ - { CTRY_SINGAPORE, "sg", DMN_APL4_WORLD }, \ - { CTRY_SLOVENIA, "si", DMN_ETSI1_WORLD }, \ - { CTRY_SLOVAKIA, "sk", DMN_ETSI3_WORLD }, \ - { CTRY_EL_SALVADOR, "sv", DMN_NULL_WORLD }, \ - { CTRY_SYRIA, "sy", DMN_NULL_WORLD }, \ - { CTRY_THAILAND, "th", DMN_APL2_WORLD }, \ - { CTRY_TUNISIA, "tn", DMN_ETSI3_WORLD }, \ - { CTRY_TURKEY, "tr", DMN_ETSI3_WORLD }, \ - { CTRY_TRINIDAD_Y_TOBAGO, "tt", DMN_ETSI4_WORLD }, \ - { CTRY_TAIWAN, "tw", DMN_APL3_WORLD }, \ - { CTRY_UKRAINE, "ua", DMN_NULL_WORLD }, \ - { CTRY_UNITED_KINGDOM, "uk", DMN_ETSI1_WORLD }, \ - { CTRY_UNITED_STATES, "us", DMN_FCC1_FCCA }, \ - { CTRY_URUGUAY, "uy", DMN_APL2_WORLD }, \ - { CTRY_UZBEKISTAN, "uz", DMN_FCC3_FCCA }, \ - { CTRY_VENEZUELA, "ve", DMN_APL2_ETSIC }, \ - { CTRY_VIET_NAM, "vn", DMN_NULL_WORLD }, \ - { CTRY_YEMEN, "ye", DMN_NULL_WORLD }, \ - { CTRY_SOUTH_AFRICA, "za", DMN_ETSI1_WORLD }, \ - { CTRY_ZIMBABWE, "zw", DMN_NULL_WORLD }, \ -} - -enum ieee80211_ctl { - CTL_11A = 0x00, - CTL_11B = 0x01, - CTL_11G = 0x02, - CTL_TURBO = 0x03, - CTL_TURBO_G = 0x04, - CTL_FCC = 0x10, - CTL_ETSI = 0x30, - CTL_MKK = 0x40, - CTL_NONEA = 0xff -}; - #define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ #define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ @@ -768,11 +481,6 @@ struct ieee80211_regchannel { { 5240, DMN_WORLD, CHANNEL_OFDM }, \ } -extern u16 ieee80211_name2countrycode(const char *); -extern u32 ieee80211_name2regdomain(const char *); -extern const char *ieee80211_countrycode2name(u16); -extern const char *ieee80211_regdomain2name(u32); -extern u32 ieee80211_regdomain2flag(u16, u16); -extern u32 ieee80211_countrycode2regdomain(u16); +u32 ieee80211_regdomain2flag(u16, u16); #endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ commit 8c248b86f0904bf82b58874a4fa716845ebfe9d0 Author: Jiri Slaby Date: Mon Jun 18 17:26:24 2007 +0200 basic join of the two parts diff --git a/Makefile b/Makefile index ab632e8..e891fe0 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,20 @@ KDIR=/lib/modules/$(shell uname -r)/build KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) -obj-y += openhal/ ath/ +ifeq ($(strip $(BUS)),AHB) +EXTRA_CFLAGS += -DATH_AHB +bus=ath +else +EXTRA_CFLAGS += -DATH_PCI +bus=pci +endif + +EXTRA_CFLAGS += -I$(src)/openhal + +ath5k-objs := ath/if_ath.o ath/if_ath_$(bus).o openhal/ath5k_hw.o \ + openhal/ieee80211_regdomain.o #ath/radar.o + +obj-m += ath5k.o all: $(KBUILD) modules diff --git a/ath/Kbuild b/ath/Kbuild deleted file mode 100644 index 808a66b..0000000 --- a/ath/Kbuild +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2007 Jiri Slaby -# All rights reserved. -# -# This software may be distributed under the terms of the -# GNU General Public License ("GPL") version 2 as published by the Free -# Software Foundation. - -ifeq ($(strip $(BUS)),AHB) -EXTRA_CFLAGS += -DATH_AHB -bus=ath -else -EXTRA_CFLAGS += -DATH_PCI -bus=pci -endif - -obj-m += ath_$(bus).o -ath_ahb-objs := if_ath.o if_ath_ahb.o #radar.o -ath_pci-objs := if_ath.o if_ath_pci.o #radar.o - -EXTRA_CFLAGS += -I$(src)/../openhal diff --git a/ath/if_ath.c b/ath/if_ath.c index f2a6748..53bfe5b 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -360,7 +360,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Attach the hal */ - ah = ath_hal_attach(devid, sc, sc->sc_iobase, &status); + ah = ath5k_hw_init(devid, sc, sc->sc_iobase, &status); if (ah == NULL) { printk(KERN_ERR "%s: unable to attach hardware: '%s' (HAL status %u)\n", __func__, hal_status_desc[status], status); @@ -740,7 +740,7 @@ bad2: ath_desc_free(sc); bad: if (ah) { - ath_hal_detach(ah); + ah->ah_detach(ah); } sc->sc_invalid = 1; return error; @@ -771,7 +771,7 @@ ath_detach(struct net_device *dev) // ath_rate_detach(sc->sc_rc); ath_desc_free(sc); ath_tx_cleanup(sc); - ath_hal_detach(sc->sc_ah); + sc->sc_ah->ah_detach(sc->sc_ah); /* * NB: can't reclaim these until after ieee80211_ifdetach diff --git a/openhal/Kbuild b/openhal/Kbuild deleted file mode 100644 index 9007072..0000000 --- a/openhal/Kbuild +++ /dev/null @@ -1,2 +0,0 @@ -obj-m += ath_hal.o -ath_hal-objs := ah_osdep.o ath5k_hw.o ieee80211_regdomain.o diff --git a/openhal/ah_osdep.c b/openhal/ah_osdep.c deleted file mode 100644 index f76c0a2..0000000 --- a/openhal/ah_osdep.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2006-2007 Nick Kossifidis - * Copyright (c) 2007 Jiri Slaby - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - */ - -#include "ath5k.h" - -static char dev_info[] = "ath_hal"; - -struct ath_hal *ath_hal_attach(u16 devid, void *sc, void __iomem *h, - enum ath5k_status *s) -{ - struct ath_hal *ah = ath5k_hw_init(devid, sc, h, s); - - if (ah && !try_module_get(THIS_MODULE)) { - printk(KERN_WARNING "try_module_get failed\n"); - kfree(ah); - return NULL; - } - - return ah; -} -EXPORT_SYMBOL(ath_hal_attach); - -void ath_hal_detach(struct ath_hal *ah) -{ - ah->ah_detach(ah); - module_put(THIS_MODULE); -} -EXPORT_SYMBOL(ath_hal_detach); - -static int __init ath_hal_init(void) -{ - printk(KERN_INFO "%s: OpenHAL loaded (AR5210, AR5211, AR5212, " - "RF5110/1/2)\n", dev_info); - return 0; -} - -static void __exit ath_hal_exit(void) -{ - printk(KERN_INFO "%s: driver unloaded\n", dev_info); -} - -module_init(ath_hal_init); -module_exit(ath_hal_exit); - -MODULE_AUTHOR("Nick Kossifidis"); -MODULE_DESCRIPTION("OpenHAL"); -MODULE_SUPPORTED_DEVICE("Atheros AR5xxx WLAN cards"); -MODULE_LICENSE("Dual BSD/GPL"); diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 830612b..4fc5efa 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -1247,7 +1247,4 @@ void ath5k_txpower_table(struct ath_hal *, struct ath5k_channel *, s16); /*added*/ extern u_int ath_hal_getwirelessmodes(struct ath_hal *, enum ieee80211_countrycode); -void ath_hal_detach(struct ath_hal *ah); -struct ath_hal *ath_hal_attach(u16 devid, void *sc, void __iomem *h, - enum ath5k_status *s); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index df0b1ec..ea4d086 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -160,7 +160,6 @@ ath_hal_probe(u16 vendor, u16 device) return NULL; } -EXPORT_SYMBOL(ath_hal_probe); /* * Calculate transmition time of a frame @@ -227,7 +226,6 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, return value; } -EXPORT_SYMBOL(ath_hal_computetxtime); /* * Return the supported 802.11 operation modes @@ -245,7 +243,6 @@ ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country return(AR5K_MODE_11A); } } -EXPORT_SYMBOL(ath_hal_getwirelessmodes); /* * Functions used internaly @@ -4725,7 +4722,6 @@ ath_hal_mhz2ieee(unsigned int freq, u_int flags) /* something is fishy, don't do anything */ return 0; } -EXPORT_SYMBOL(ath_hal_mhz2ieee); /* * Convert IEEE channel number to MHz frequency. @@ -4752,7 +4748,6 @@ ath_hal_ieee2mhz(unsigned int chan, u_int flags) return 5000 + (chan * 5); } } -EXPORT_SYMBOL(ath_hal_ieee2mhz); /* * Check if a channel is supported @@ -4913,7 +4908,6 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ kfree(all_channels); return true; } -EXPORT_SYMBOL(ath_hal_init_channels); /* * Regdomain stuff, these also don't belong here etc commit db5ff9a0d954d3507a2307dac1406218e2dde2ce Author: Jiri Slaby Date: Tue Jun 19 14:46:11 2007 +0200 remove translation.h and functions in ath_hal struct diff --git a/ath/if_ath.c b/ath/if_ath.c index 53bfe5b..6841f55 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -376,7 +376,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) * return false w/o doing anything. MAC's that do * support it will return true w/o doing anything. */ - sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); + sc->sc_mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); /* * Check if the device has hardware counters for PHY @@ -389,7 +389,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Get the hardware key cache size. */ - sc->sc_keymax = ath_hal_keycachesize(ah); + sc->sc_keymax = ath5k_hw_get_keycache_size(ah); if (sc->sc_keymax > ATH_KEYMAX) { printk(KERN_WARNING "Warning, using only %u of %u key cache " "slots\n", ATH_KEYMAX, sc->sc_keymax); @@ -401,7 +401,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) * reset the contents on initial power up. */ for (i = 0; i < sc->sc_keymax; i++) - ath_hal_keyreset(ah, i); + ath5k_hw_reset_key(ah, i); /* * Mark key cache slots associated with global keys * as in use. If we knew TKIP was not to be used we @@ -556,8 +556,8 @@ ath_attach(u_int16_t devid, struct net_device *dev) sc->sc_softled = (devid == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || devid == PCI_DEVICE_ID_ATHEROS_AR5211); if (sc->sc_softled) { - ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); - ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); + ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); + ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); } #ifdef BLE @@ -664,7 +664,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Query the hal about antenna support. */ - sc->sc_defant = ath_hal_getdefantenna(ah); + sc->sc_defant = ath5k_hw_get_def_antenna(ah); /* * Not all chips have the VEOL support we want to @@ -740,7 +740,7 @@ bad2: ath_desc_free(sc); bad: if (ah) { - ah->ah_detach(ah); + ath5k_hw_detach(ah); } sc->sc_invalid = 1; return error; @@ -771,7 +771,7 @@ ath_detach(struct net_device *dev) // ath_rate_detach(sc->sc_rc); ath_desc_free(sc); ath_tx_cleanup(sc); - sc->sc_ah->ah_detach(sc->sc_ah); + ath5k_hw_detach(sc->sc_ah); /* * NB: can't reclaim these until after ieee80211_ifdetach @@ -793,7 +793,7 @@ ath_suspend(struct net_device *dev) DPRINTF(sc, ATH_DEBUG_ANY, "%s: flags %x\n", __func__, dev->flags); if (sc->sc_softled) - ath_hal_gpioset(ah, sc->sc_ledpin, 1); + ath5k_hw_set_gpio(ah, sc->sc_ledpin, 1); ath_stop(dev); } @@ -807,8 +807,8 @@ ath_resume(struct net_device *dev) DPRINTF(sc, ATH_DEBUG_ANY, "%s: flags %x\n", __func__, dev->flags); ath_init(dev); if (sc->sc_softled) { - ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); - ath_hal_gpioset(ah, sc->sc_ledpin, 0); + ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); + ath5k_hw_set_gpio(ah, sc->sc_ledpin, 0); } } @@ -841,8 +841,8 @@ irqreturn_t ath_intr(int irq, void *dev_id) if ((dev->flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", __func__, dev->flags); - ath_hal_getisr(ah, &status); /* clear ISR */ - ath_hal_intrset(ah, 0); /* disable further intr's */ + ath5k_hw_get_isr(ah, &status); /* clear ISR */ + ath5k_hw_set_intr(ah, 0); /* disable further intr's */ return IRQ_HANDLED; } needmark = 0; @@ -854,7 +854,7 @@ irqreturn_t ath_intr(int irq, void *dev_id) * bits we haven't explicitly enabled so we mask the * value to insure we only process bits we requested. */ - ath_hal_getisr(ah, &status); /* NB: clears ISR too */ + ath5k_hw_get_isr(ah, &status); /* NB: clears ISR too */ DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); status &= sc->sc_imask; /* discard unasked for bits */ if (status & AR5K_INT_FATAL) { @@ -865,11 +865,11 @@ irqreturn_t ath_intr(int irq, void *dev_id) * by the hal. */ sc->sc_stats.ast_hardware++; - ath_hal_intrset(ah, 0); /* disable intr's until reset */ + ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ tasklet_schedule(&sc->sc_fataltq); } else if (status & AR5K_INT_RXORN) { sc->sc_stats.ast_rxorn++; - ath_hal_intrset(ah, 0); /* disable intr's until reset */ + ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ tasklet_schedule(&sc->sc_rxorntq); } else { if (status & AR5K_INT_SWBA) { @@ -893,7 +893,7 @@ irqreturn_t ath_intr(int irq, void *dev_id) if (status & AR5K_INT_TXURN) { sc->sc_stats.ast_txurn++; /* bump tx trigger level */ - ath_hal_updatetxtriglevel(ah, true); + ath5k_hw_update_tx_triglevel(ah, true); } if (status & AR5K_INT_RX) tasklet_schedule(&sc->sc_rxtq); @@ -909,19 +909,19 @@ irqreturn_t ath_intr(int irq, void *dev_id) * Disable interrupts until we service the MIB * interrupt; otherwise it will continue to fire. */ - ath_hal_intrset(ah, 0); + ath5k_hw_set_intr(ah, 0); /* * Let the hal handle the event. We assume it will * clear whatever condition caused the interrupt. */ #ifdef BLE - ath_hal_mibevent(ah, + ath5k_hw_proc_mib_event(ah, &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); #endif - ath_hal_intrset(ah, sc->sc_imask); + ath5k_hw_set_intr(ah, sc->sc_imask); } } - } while (ath_hal_intrpend(ah)); + } while (ath5k_hw_is_intr_pending(ah)); return IRQ_HANDLED; } @@ -1064,7 +1064,8 @@ ath_init(struct net_device *dev) sc->sc_curchan.freq = ic->ic_ibss_chan->ic_freq; sc->sc_curchan.channel_flags = ath_chan2flags(ic, ic->ic_ibss_chan); #endif - if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, false, &status)) { + if (!ath5k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, false, + &status)) { printk(KERN_ERR "unable to reset hardware; hal status %u\n", status); error = -EIO; @@ -1108,7 +1109,7 @@ ath_init(struct net_device *dev) */ if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) sc->sc_imask |= AR5K_INT_MIB; - ath_hal_intrset(ah, sc->sc_imask); + ath5k_hw_set_intr(ah, sc->sc_imask); dev->flags |= IFF_RUNNING; ic->ic_state = IEEE80211_S_INIT; @@ -1169,16 +1170,16 @@ ath_stop_locked(struct net_device *dev) if (!sc->sc_invalid) { if (sc->sc_softled) { del_timer(&sc->sc_ledtimer); - ath_hal_gpioset(ah, sc->sc_ledpin, + ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); sc->sc_blinking = 0; } - ath_hal_intrset(ah, 0); + ath5k_hw_set_intr(ah, 0); } ath_draintxq(sc); if (!sc->sc_invalid) { ath_stoprecv(sc); - ath_hal_phydisable(ah); + ath5k_hw_phy_disable(ah); } else sc->sc_rxlink = NULL; ath_beacon_free(sc); @@ -1223,7 +1224,8 @@ ath_stop(struct net_device *dev) else { DPRINTF(sc, ATH_DEBUG_RESET, "%s: putting device to full sleep\n", __func__); - ath_hal_setpower(sc->sc_ah, AR5K_PM_FULL_SLEEP, 0); + ath5k_hw_set_power(sc->sc_ah, AR5K_PM_FULL_SLEEP, + true, 0); } } ATH_UNLOCK(sc); @@ -1256,13 +1258,13 @@ ath_reset(struct net_device *dev) sc->sc_curchan.freq = c->ic_freq; sc->sc_curchan.channel_flags = ath_chan2flags(ic, c); - ath_hal_intrset(ah, 0); /* disable interrupts */ + ath5k_hw_set_intr(ah, 0); /* disable interrupts */ ath_draintxq(sc); /* stop xmit side */ ath_stoprecv(sc); /* stop recv side */ opmode = (ic->ic_opmode == IEEE80211_M_AHDEMO) ? 0 : ic->ic_opmode; /* NB: indicate channel change so we do a full reset */ - if (!ath_hal_reset(ah, opmode, &sc->sc_curchan, true, &status)) + if (!ath5k_hw_reset(ah, opmode, &sc->sc_curchan, true, &status)) if_printf(dev, "%s: unable to reset hardware: '%s' (%u)\n", __func__, hal_status_desc[status], status); ath_update_txpow(sc); /* update tx power state */ @@ -1277,7 +1279,7 @@ ath_reset(struct net_device *dev) ath_chan_change(sc, c); if (ic->ic_state == IEEE80211_S_RUN) ath_beacon_config(sc); /* restart beacons */ - ath_hal_intrset(ah, sc->sc_imask); + ath5k_hw_set_intr(ah, sc->sc_imask); if (ic->ic_state == IEEE80211_S_RUN) netif_wake_queue(dev); /* restart xmit */ @@ -1548,7 +1550,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) * Formulate first tx descriptor with tx controls. */ /* XXX check return value? */ - ath_hal_setuptxdesc(ah, ds + ah->ah_setup_tx_desc(ah, ds , pktlen /* packet length */ , hdrlen /* header length */ , atype /* Atheros packet type */ @@ -1566,7 +1568,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) */ ds->ds_link = 0; ds->ds_data = bf->bf_skbaddr; - ath_hal_filltxdesc(ah, ds + ah->ah_fill_tx_desc(ah, ds , skb->len /* segment length */ , true /* first segment */ , true /* last segment */ @@ -1618,7 +1620,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: txq depth = %d\n", __func__, txq->axq_depth); if (txq->axq_link == NULL) { - ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); + ath5k_hw_put_tx_buf(ah, txq->axq_qnum, bf->bf_daddr); DPRINTF(sc, ATH_DEBUG_XMIT, "%s: TXDP[%u] = %llx (%p) depth %d\n", __func__, txq->axq_qnum, (unsigned long long)bf->bf_daddr, @@ -1637,7 +1639,7 @@ ath_start_raw(struct sk_buff *skb, struct net_device *dev) * frames only go out on DTIM and to avoid possible races. */ if (txq != sc->sc_cabq) - ath_hal_txstart(ah, txq->axq_qnum); + ath5k_hw_tx_start(ah, txq->axq_qnum); ATH_TXQ_UNLOCK_BH(txq); sc->sc_devstats.tx_packets++; @@ -1826,7 +1828,7 @@ ath_start(struct sk_buff *skb, struct net_device *dev) u_int64_t tsf; __le32 *tstamp; - tsf = ath_hal_gettsf64(ah); + tsf = ath5k_hw_get_tsf64(ah); /* XXX: adjust 100us delay to xmit */ tsf += 100; tstamp = (__le32 *)&wh[1]; @@ -1927,13 +1929,13 @@ ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, */ memcpy(hk->wk_mic, k->wk_txmic, sizeof(hk->wk_mic)); KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); - if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) + if (!ath5k_hw_set_key(ah, k->wk_keyix, hk, zerobssid)) return 0; memcpy(hk->wk_mic, k->wk_rxmic, sizeof(hk->wk_mic)); KEYPRINTF(sc, k->wk_keyix+32, hk, mac); /* XXX delete tx key on failure? */ - return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); + return ath5k_hw_set_key(ah, k->wk_keyix+32, hk, mac, false); } else if (k->wk_flags & IEEE80211_KEY_XR) { /* * TX/RX key goes at first index. @@ -1942,7 +1944,7 @@ ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, memcpy(hk->wk_mic, k->wk_flags & IEEE80211_KEY_XMIT ? k->wk_txmic : k->wk_rxmic, sizeof(hk->wk_mic)); KEYPRINTF(sc, k->wk_keyix, hk, mac); - return ath_hal_keyset(ah, k->wk_keyix, hk, mac); + return ath5k_hw_set_key(ah, k->wk_keyix, hk, mac, false); } return 0; #undef IEEE80211_KEY_XR @@ -2007,7 +2009,7 @@ ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, return ath_keyset_tkip(sc, k, &hk, mac); } else { KEYPRINTF(sc, k->wk_keyix, &hk, mac); - return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); + return ath5k_hw_set_key(ah, k->wk_keyix, &hk, mac, false); } #undef N } @@ -2171,7 +2173,7 @@ ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); - ath_hal_keyreset(ah, keyix); + ath5k_hw_reset_key(ah, keyix); /* * Check the key->node map and flush any ref. */ @@ -2185,7 +2187,7 @@ ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) */ if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { - ath_hal_keyreset(ah, keyix+32); /* RX key */ + ath5k_hw_reset_key(ah, keyix+32); /* RX key */ ni = sc->sc_keyixmap[keyix+32]; if (ni != NULL) { /* as above... */ ieee80211_free_node(ni); @@ -2299,7 +2301,7 @@ ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) struct net_device *dev = ic->ic_dev; u_int32_t rfilt; - rfilt = (ath_hal_getrxfilter(ah) & AR5K_RX_FILTER_PHYERROR) + rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERROR) | AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_PHYRADAR; if (ic->ic_opmode != IEEE80211_M_STA && ic->ic_opmode != IEEE80211_M_AHDEMO) @@ -2335,10 +2337,10 @@ ath_mode_init(struct net_device *dev) /* configure rx filter */ // rfilt = ath_calcrxfilter(sc, ic->ic_state); -// ath_hal_setrxfilter(ah, rfilt); +// ath5k_hw_set_rx_filter(ah, rfilt); /* configure operational mode */ - ath_hal_setopmode(ah); + ath5k_hw_set_pcu_config(ah); /* * Handle any link-level address change. Note that we only @@ -2349,7 +2351,7 @@ ath_mode_init(struct net_device *dev) * XXX should get from lladdr instead of arpcom but that's more work */ // IEEE80211_ADDR_COPY(ic->ic_myaddr, dev->dev_addr); - ath_hal_setmac(ah, dev->dev_addr); + ath5k_hw_set_lladdr(ah, dev->dev_addr); /* calculate and install multicast filter */ if ((dev->flags & IFF_ALLMULTI) == 0) { @@ -2366,7 +2368,7 @@ ath_mode_init(struct net_device *dev) } else { mfilt[0] = mfilt[1] = ~0; } - ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); + ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", __func__, rfilt, mfilt[0], mfilt[1]); } @@ -2388,9 +2390,9 @@ ath_setslottime(struct ath_softc *sc) */ if (!sc->sc_lockslottime) { // if (ic->ic_flags & IEEE80211_F_SHSLOT) -// ath_hal_setslottime(ah, AR5K_SLOT_TIME_9); +// ath5k_hw_set_slot_time(ah, AR5K_SLOT_TIME_9); // else - ath_hal_setslottime(ah, AR5K_SLOT_TIME_20); + ath5k_hw_set_slot_time(ah, AR5K_SLOT_TIME_20); } sc->sc_updateslot = OK; } @@ -2430,7 +2432,7 @@ ath_beaconq_setup(struct ath_hal *ah) qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; /* NB: for dynamic turbo, don't enable any other interrupts */ qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - return ath_hal_setuptxqueue(ah, AR5K_TX_QUEUE_BEACON, &qi); + return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); } #ifdef BLE /* @@ -2444,7 +2446,7 @@ ath_beaconq_config(struct ath_softc *sc) struct ath_hal *ah = sc->sc_ah; struct ath5k_txq_info qi; - ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); + ath5k_hw_get_tx_queueprops(ah, sc->sc_bhalq, &qi); if (sc->sc_opmode == IEEE80211_IF_TYPE_AP) { /* * Always burst out beacon and CAB traffic. @@ -2465,12 +2467,12 @@ ath_beaconq_config(struct ath_softc *sc) #endif } - if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { + if (!ath5k_hw_setup_tx_queueprops(ah, sc->sc_bhalq, &qi)) { printk("%s: unable to update parameters for " "beacon hardware queue! (%s)\n", __func__, sc->sc_dev.name); return 0; } else { - ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ + ath5k_hw_reset_tx_queue(ah, sc->sc_bhalq); /* push to h/w */ return 1; } #undef ATH_EXPONENT_TO_VALUE @@ -2579,7 +2581,7 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, rate = an->an_tx_mgtrate; #endif rate = 0; - ath_hal_setuptxdesc(ah, ds + ah->ah_setup_tx_desc(ah, ds , skb->len + FCS_LEN /* frame length */ , ieee80211_get_hdrlen_from_skb(skb) /* header length */ , AR5K_PKT_TYPE_BEACON /* Atheros packet type */ @@ -2592,7 +2594,7 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, , 0 /* rts/cts duration */ ); /* NB: beacon's BufLen must be a multiple of 4 bytes */ - ath_hal_filltxdesc(ah, ds + ah->ah_fill_tx_desc(ah, ds , roundup(skb->len, 4) /* buffer length */ , true /* first segment */ , true /* last segment */ @@ -2636,7 +2638,7 @@ ath_beacon_send(struct net_device *dev) * indicate a problem and should not occur. If we * miss too many consecutive beacons reset the device. */ - if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { + if (ath5k_hw_num_tx_pending(ah, sc->sc_bhalq) != 0) { sc->sc_bmisscount++; DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: missed %u consecutive beacons\n", @@ -2717,7 +2719,7 @@ ath_beacon_send(struct net_device *dev) * This should never fail since we check above that no frames * are still pending on the queue. */ - if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { + if (!ath5k_hw_stop_tx_dma(ah, sc->sc_bhalq)) { DPRINTF(sc, ATH_DEBUG_ANY, "%s: beacon queue %u did not stop?\n", __func__, sc->sc_bhalq); @@ -2737,10 +2739,10 @@ ath_beacon_send(struct net_device *dev) #ifdef BLE if (sc->sc_opmode == IEEE80211_IF_TYPE_AP && ncabq > 0 && sc->sc_boff.bo_tim[4] & 1) - ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); + ath5k_hw_tx_start(ah, sc->sc_cabq->axq_qnum); #endif - ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); - ath_hal_txstart(ah, sc->sc_bhalq); + ath5k_hw_put_tx_buf(ah, sc->sc_bhalq, bf->bf_daddr); + ath5k_hw_tx_start(ah, sc->sc_bhalq); DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: TXDP[%u] = %llx (%p)\n", __func__, sc->sc_bhalq, (unsigned long long)bf->bf_daddr, bf->bf_desc); @@ -2818,7 +2820,7 @@ ath_beacon_config(struct ath_softc *sc) /* NB: the beacon interval is kept internally in TU's */ intval = ni->ni_intval & AR5K_BEACON_PERIOD; /* current TSF converted to TU */ - tsf = ath_hal_gettsf64(ah); + tsf = ath5k_hw_get_tsf64(ah); tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf); DPRINTF(sc, ATH_DEBUG_BEACON, "%s: last beacon %u intval %u (%u) hw tsftu %u\n", @@ -2917,13 +2919,13 @@ ath_beacon_config(struct ath_softc *sc) , bs.bs_cfp_next , bs.bs_tim_offset ); - ath_hal_intrset(ah, 0); - ath_hal_beacontimers(ah, &bs); + ath5k_hw_set_intr(ah, 0); + ath5k_hw_set_beacon_timers(ah, &bs); sc->sc_imask |= AR5K_INT_BMISS; sc->sc_bmisscount = 0; - ath_hal_intrset(ah, sc->sc_imask); + ath5k_hw_set_intr(ah, sc->sc_imask); } else { /* IBSS or HOSTAP */ - ath_hal_intrset(ah, 0); + ath5k_hw_set_intr(ah, 0); if (ic->ic_opmode == IEEE80211_M_IBSS) { /* @@ -2970,10 +2972,10 @@ ath_beacon_config(struct ath_softc *sc) intval |= AR5K_BEACON_ENA; ath_beaconq_config(sc); - ath_hal_beaconinit(ah, nexttbtt, intval); + ath5k_hw_init_beacon(ah, nexttbtt, intval); sc->sc_bmisscount = 0; - ath_hal_intrset(ah, sc->sc_imask); + ath5k_hw_set_intr(ah, sc->sc_imask); /* * When using a self-linked beacon descriptor in * ibss mode load it once here. @@ -3248,10 +3250,9 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) ds = bf->bf_desc; ds->ds_link = bf->bf_daddr; /* link to self */ ds->ds_data = bf->bf_skbaddr; - ath_hal_setuprxdesc(ah, ds - , skb_tailroom(skb) /* buffer size */ - , 0 - ); + ath5k_hw_setup_rx_desc(ah, ds, + skb_tailroom(skb), /* buffer size */ + 0); if (sc->sc_rxlink != NULL) *sc->sc_rxlink = bf->bf_daddr; @@ -3322,7 +3323,7 @@ ath_tx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) * the time the frame was received. Use the current * tsf to extend this to 32 bits. */ - tsf = ath_hal_gettsf32(sc->sc_ah); + tsf = ath5k_hw_get_tsf32(sc->sc_ah); if ((tsf & 0x7fff) < ds->ds_rxstat.rs_tstamp) tsf -= 0x8000; ph->mactime.data = ds->ds_rxstat.rs_tstamp | (tsf &~ 0x7fff); @@ -3478,7 +3479,7 @@ ath_rx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) * the time the frame was received. Use the current * tsf to extend this to 32 bits. */ - tsf = ath_hal_gettsf32(sc->sc_ah); + tsf = ath5k_hw_get_tsf32(sc->sc_ah); if ((tsf & 0x7fff) < ds->ds_rxstat.rs_tstamp) tsf -= 0x8000; ph->mactime.data = ds->ds_rxstat.rs_tstamp | (tsf &~ 0x7fff); @@ -3574,7 +3575,7 @@ ath_tsf_extend(struct ath_hal *ah, uint32_t rstamp) { uint64_t tsf; - tsf = ath_hal_gettsf64(ah); + tsf = ath5k_hw_get_tsf64(ah); /* Compensate for rollover. */ if ((tsf & 0x7fff) < rstamp) @@ -3656,7 +3657,7 @@ ath_setdefantenna(struct ath_softc *sc, u_int antenna) struct ath_hal *ah = sc->sc_ah; /* XXX block beacon interrupts */ - ath_hal_setdefantenna(ah, antenna); + ath5k_hw_set_def_antenna(ah, antenna); if (sc->sc_defant != antenna) sc->sc_stats.ast_ant_defswitch++; sc->sc_defant = antenna; @@ -3710,7 +3711,7 @@ ath_rx_tasklet(unsigned long data) * on. All this is necessary because of our use of * a self-linked list to avoid rx overruns. */ - status = ath_hal_rxprocdesc(ah, ds, + status = ah->ah_proc_rx_desc(ah, ds, bf->bf_daddr, PA2DESC(sc, ds->ds_link)); #ifdef AR_DEBUG if (sc->sc_debug & ATH_DEBUG_RECV_DESC) @@ -3986,7 +3987,7 @@ rx_next: } while (ath_rxbuf_init(sc, bf) == 0); /* rx signal state monitoring */ -// ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); +// ath5k_hw_set_rx_signal(ah, &ATH_NODE(ic->ic_bss)->an_halstats); #undef PA2DESC } @@ -4020,7 +4021,7 @@ ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) * due to a lack of tx descriptors. */ qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - qnum = ath_hal_setuptxqueue(ah, qtype, &qi); + qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); if (qnum == -1) { /* * NB: don't print a message, this happens @@ -4031,7 +4032,7 @@ ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) if (qnum >= N(sc->sc_txq)) { printk("%s: hal qnum %u out of range, max %u!\n", sc->sc_dev.name, qnum, (unsigned int) N(sc->sc_txq)); - ath_hal_releasetxqueue(ah, qnum); + ath5k_hw_release_tx_queue(ah, qnum); return NULL; } if (!ATH_TXQ_SETUP(sc, qnum)) { @@ -4091,19 +4092,19 @@ ath_txq_update(struct ath_softc *sc, int ac) struct ath_hal *ah = sc->sc_ah; struct ath5k_txq_info qi; - ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); + ath5k_hw_get_tx_queueprops(ah, txq->axq_qnum, &qi); qi.tqi_aifs = wmep->wmep_aifsn; qi.tqi_cw_min = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); qi.tqi_cw_max = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); qi.tqi_burst_time = ATH_TXOP_TO_US(wmep->wmep_txopLimit); - if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { + if (!ath5k_hw_setup_tx_queueprops(ah, txq->axq_qnum, &qi)) { if_printf(&sc->sc_dev, "unable to update hardware queue " "parameters for %s traffic!\n", ieee80211_wme_acnames[ac]); return 0; } else { - ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ + ath5k_hw_reset_tx_queue(ah, txq->axq_qnum); /* push to h/w */ return 1; } #undef ATH_TXOP_TO_US @@ -4130,8 +4131,7 @@ ath_wme_update(struct ieee80211com *ic) static void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) { - - ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); + ath5k_hw_release_tx_queue(sc->sc_ah, txq->axq_qnum); ATH_TXQ_LOCK_DESTROY(txq); sc->sc_txqsetup &= ~(1<axq_qnum); } @@ -4528,7 +4528,7 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * * Formulate first tx descriptor with tx controls. */ /* XXX check return value? */ - ath_hal_setuptxdesc(ah, ds + ah->ah_setup_tx_desc(ah, ds , pktlen /* packet length */ , hdrlen /* header length */ , atype /* Atheros packet type */ @@ -4556,7 +4556,7 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * */ ds->ds_link = 0; ds->ds_data = bf->bf_skbaddr; - ath_hal_filltxdesc(ah, ds + ah->ah_fill_tx_desc(ah, ds , skb->len /* segment length */ , true /* first segment */ , true /* last segment */ @@ -4607,7 +4607,7 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: txq depth = %d\n", __func__, txq->axq_depth); if (txq->axq_link == NULL) { - ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); + ath5k_hw_put_tx_buf(ah, txq->axq_qnum, bf->bf_daddr); DPRINTF(sc, ATH_DEBUG_XMIT, "%s: TXDP[%u] = %llx (%p) depth %d\n", __func__, txq->axq_qnum, (unsigned long long)bf->bf_daddr, @@ -4626,7 +4626,7 @@ ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf * * frames only go out on DTIM and to avoid possible races. */ if (txq != sc->sc_cabq) - ath_hal_txstart(ah, txq->axq_qnum); + ath5k_hw_tx_start(ah, txq->axq_qnum); ATH_TXQ_UNLOCK_BH(txq); dev->trans_start = jiffies; @@ -4650,10 +4650,9 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) // int sr, lr, pri; enum ath5k_status status; - DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", + DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %x link %p\n", __func__, txq->axq_qnum, - (caddr_t)ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), - txq->axq_link); + ath5k_hw_get_tx_buf(sc->sc_ah, txq->axq_qnum), txq->axq_link); for (;;) { ATH_TXQ_LOCK(txq); txq->axq_intrcnt = 0; /* reset periodic desc intr count */ @@ -4664,7 +4663,7 @@ ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) break; } ds = bf->bf_desc; /* NB: last decriptor */ - status = ath_hal_txprocdesc(ah, ds); + status = ah->ah_proc_tx_desc(ah, ds); #ifdef AR_DEBUG if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) ath_printtxbuf(bf, status == AR5K_OK); @@ -4882,8 +4881,8 @@ ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) ATH_TXQ_UNLOCK_BH(txq); #ifdef AR_DEBUG if (sc->sc_debug & ATH_DEBUG_RESET) - ath_printtxbuf(bf, - ath_hal_txprocdesc(ah, bf->bf_desc) == AR5K_OK); + ath_printtxbuf(bf, ah->ah_proc_tx_desc(ah, + bf->bf_desc) == AR5K_OK); #endif /* AR_DEBUG */ bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); @@ -4910,10 +4909,10 @@ ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) { struct ath_hal *ah = sc->sc_ah; - (void) ath_hal_stoptxdma(ah, txq->axq_qnum); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", - __func__, txq->axq_qnum, - (caddr_t)ath_hal_gettxbuf(ah, txq->axq_qnum), txq->axq_link); + ath5k_hw_stop_tx_dma(ah, txq->axq_qnum); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %x, link %p\n", + __func__, txq->axq_qnum, + ath5k_hw_get_tx_buf(ah, txq->axq_qnum), txq->axq_link); } /* @@ -4928,10 +4927,9 @@ ath_draintxq(struct ath_softc *sc) /* XXX return value */ if (!sc->sc_invalid) { /* don't touch the hardware if marked invalid */ - (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); - DPRINTF(sc, ATH_DEBUG_RESET, - "%s: beacon queue %p\n", __func__, - (caddr_t)ath_hal_gettxbuf(ah, sc->sc_bhalq)); + (void) ath5k_hw_stop_tx_dma(ah, sc->sc_bhalq); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, + ath5k_hw_get_tx_buf(ah, sc->sc_bhalq)); for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) { if (ATH_TXQ_SETUP(sc, i)) ath_tx_stopdma(sc, &sc->sc_txq[i]); @@ -4962,20 +4960,20 @@ ath_stoprecv(struct ath_softc *sc) ((_pa) - (_sc)->sc_desc_daddr))) struct ath_hal *ah = sc->sc_ah; - ath_hal_stoppcurecv(ah); /* disable PCU */ - ath_hal_setrxfilter(ah, 0); /* clear recv filter */ - ath_hal_stopdmarecv(ah); /* disable DMA engine */ + ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ + ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ + ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ mdelay(3); /* 3ms is long enough for 1 frame */ #ifdef AR_DEBUG if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow // struct ath_buf *bf; - printk("%s: rx queue %p, link %p\n", __func__, - (caddr_t)ath_hal_getrxbuf(ah), sc->sc_rxlink); + printk("%s: rx queue %x, link %p\n", __func__, + ath5k_hw_get_rx_buf(ah), sc->sc_rxlink); #ifdef BLE STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { struct ath_desc *ds = bf->bf_desc; - enum ath5k_status status = ath_hal_rxprocdesc(ah, ds, + enum ath5k_status status = ah->ah_proc_rx_desc(ah, ds, bf->bf_daddr, PA2DESC(sc, ds->ds_link)); if (status == AR5K_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) ath_printrxbuf(bf, status == AR5K_OK); @@ -5035,10 +5033,10 @@ ath_startrecv(struct ath_softc *sc) bf = STAILQ_FIRST(&sc->sc_rxbuf); #endif bf = NULL; - ath_hal_putrxbuf(ah, bf->bf_daddr); - ath_hal_rxena(ah); /* enable recv descriptors */ + ath5k_hw_put_rx_buf(ah, bf->bf_daddr); + ath5k_hw_start_rx(ah); /* enable recv descriptors */ // ath_mode_init(dev); /* set filters, etc. */ - ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ + ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ return 0; } @@ -5116,10 +5114,10 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) * hardware at the new frequency, and then re-enable * the relevant bits of the h/w. */ - ath_hal_intrset(ah, 0); /* disable interrupts */ + ath5k_hw_set_intr(ah, 0); /* disable interrupts */ ath_draintxq(sc); /* clear pending tx frames */ ath_stoprecv(sc); /* turn off frame recv */ - if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, true, &status)) { + if (!ath5k_hw_reset(ah, sc->sc_opmode, &hchan, true, &status)) { printk(KERN_ERR "ath_chan_set: unable to reset " "channel %u (%u Mhz)\n", 0, // ieee80211_chan2ieee(ic, chan), @@ -5149,7 +5147,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) /* * Re-enable interrupts. */ - ath_hal_intrset(ah, sc->sc_imask); + ath5k_hw_set_intr(ah, sc->sc_imask); } return 0; } @@ -5182,17 +5180,17 @@ ath_calibrate(unsigned long arg) DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", __func__, sc->sc_curchan.freq, sc->sc_curchan.channel_flags); - if (ath_hal_getrfgain(ah) == AR5K_RFGAIN_NEED_CHANGE) { + if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { /* * Rfgain is out of bounds, reset the chip * to load new gain values. */ sc->sc_stats.ast_per_rfgain++; - DPRINTF(sc, ATH_DEBUG_RESET, - "%s: calibration, resetting\n", dev->name); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: calibration, resetting\n", + dev->name); ath_reset(dev); } - if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { + if (!ath5k_hw_phy_calibrate(ah, &sc->sc_curchan)) { DPRINTF(sc, ATH_DEBUG_ANY, "%s: calibration of channel %u failed\n", __func__, sc->sc_curchan.freq); @@ -5226,7 +5224,7 @@ ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) del_timer(&sc->sc_scan_ch); /* ap/neighbor scan timer */ del_timer(&sc->sc_cal_ch); /* periodic calibration timer */ - ath_hal_setledstate(ah, leds[nstate]); /* set LED */ + ath5k_hw_set_ledstate(ah, leds[nstate]); /* set LED */ netif_stop_queue(dev); /* before we do anything else */ if (sc->sc_rawdev_enabled) netif_stop_queue(&sc->sc_rawdev); @@ -5236,7 +5234,7 @@ ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) /* * NB: disable interrupts so we don't rx frames. */ - ath_hal_intrset(ah, sc->sc_imask &~ AR5K_INT_GLOBAL); + ath5k_hw_set_intr(ah, sc->sc_imask &~ AR5K_INT_GLOBAL); /* * Notify the rate control algorithm. */ @@ -5252,18 +5250,18 @@ ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) bssid = dev->broadcast; else bssid = ni->ni_bssid; - ath_hal_setrxfilter(ah, rfilt); + ath5k_hw_set_rx_filter(ah, rfilt); DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", __func__, rfilt, ether_sprintf(bssid)); if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) - ath_hal_setassocid(ah, bssid, ni->ni_associd); + ath5k_hw_set_associd(ah, bssid, ni->ni_associd); else - ath_hal_setassocid(ah, bssid, 0); + ath5k_hw_set_associd(ah, bssid, 0); if (ic->ic_flags & IEEE80211_F_PRIVACY) { for (i = 0; i < IEEE80211_WEP_NKID; i++) - if (ath_hal_keyisvalid(ah, i)) - ath_hal_keysetmac(ah, i, bssid); + if (ath5k_hw_is_key_valid(ah, i)) + ath5k_hw_set_key_lladdr(ah, i, bssid); } /* @@ -5300,7 +5298,7 @@ ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) * transition from RUN->RUN that means we may * be called with beacon transmission active. */ - ath_hal_stoptxdma(ah, sc->sc_bhalq); + ath5k_hw_stop_tx_dma(ah, sc->sc_bhalq); ath_beacon_free(sc); error = ath_beacon_alloc(sc, ni); if (error != 0) @@ -5324,7 +5322,7 @@ ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) */ ath_beacon_config(sc); } else { - ath_hal_intrset(ah, + ath5k_hw_set_intr(ah, sc->sc_imask &~ (AR5K_INT_SWBA | AR5K_INT_BMISS)); sc->sc_imask &= ~(AR5K_INT_SWBA | AR5K_INT_BMISS); } @@ -5470,7 +5468,7 @@ ath_led_off(unsigned long arg) /* part of ath_led_done() */ sc->sc_blinking = 0; } else{ - ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); + ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); sc->sc_endblink = 1; mod_timer(&sc->sc_ledtimer, jiffies + sc->sc_ledoff); } @@ -5483,7 +5481,7 @@ static void ath_led_blink(struct ath_softc *sc, int on, int off) { DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); - ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); + ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); sc->sc_blinking = 1; sc->sc_endblink = 0; sc->sc_ledoff = off; @@ -5521,7 +5519,7 @@ ath_update_txpow(struct ath_softc *sc) u_int32_t txpow; if (sc->sc_curtxpow != ic->ic_txpowlimit) { - ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); + ath5k_hw_set_txpower_limit(ah, ic->ic_txpowlimit); /* read back in case value is clamped */ (void)ath_hal_gettxpowlimit(ah, &txpow); ic->ic_txpowlimit = sc->sc_curtxpow = txpow; @@ -5545,19 +5543,19 @@ ath_rate_setup(struct net_device *dev, u_int mode) switch (mode) { case MODE_IEEE80211A: - sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_11A); + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A); break; case MODE_IEEE80211B: - sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_11B); + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11B); break; case MODE_IEEE80211G: - sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_11G); + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11G); break; case MODE_ATHEROS_TURBO: - sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_TURBO); + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_TURBO); break; case MODE_ATHEROS_TURBOG: - sc->sc_rates[mode] = ath_hal_getratetable(ah, AR5K_MODE_108G); + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_108G); break; default: DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", @@ -6025,7 +6023,7 @@ ath_set_mac_address(struct net_device *dev, void *addr) /* XXX not right for multiple vap's */ // IEEE80211_ADDR_COPY(ic->ic_myaddr, mac->sa_data); memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN); - ath_hal_setmac(ah, dev->dev_addr); + ath5k_hw_set_lladdr(ah, dev->dev_addr); if ((dev->flags & IFF_RUNNING) && !sc->sc_invalid) { error = -ath_reset(dev); } @@ -6105,7 +6103,7 @@ ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) goto bad; } } - if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { + if (ath5k_hw_get_diag_state(ah, id, indata, insize, &outdata,&outsize)){ if (outsize < ad->ad_out_size) ad->ad_out_size = outsize; if (outdata && @@ -6267,26 +6265,27 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, if (ret == 0) { switch (ctl->ctl_name) { case ATH_SLOTTIME: - if (!ath_hal_setslottime(ah, val)) + if (!ath5k_hw_set_slot_time(ah, val)) ret = -EINVAL; break; case ATH_LOCKSLOTTIME: sc->sc_lockslottime = val != 0; break; case ATH_ACKTIMEOUT: - if (!ath_hal_setacktimeout(ah, val)) + if (!ath5k_hw_set_ack_timeout(ah, val)) ret = -EINVAL; break; case ATH_CTSTIMEOUT: - if (!ath_hal_setctstimeout(ah, val)) + if (!ath5k_hw_set_cts_timeout(ah, val)) ret = -EINVAL; break; case ATH_SOFTLED: if (val != sc->sc_softled) { if (val) - ath_hal_gpioCfgOutput(ah, + ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); - ath_hal_gpioset(ah, sc->sc_ledpin,!val); + ath5k_hw_set_gpio(ah, sc->sc_ledpin, + !val); sc->sc_softled = val; } break; @@ -6377,16 +6376,16 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, } else { switch (ctl->ctl_name) { case ATH_SLOTTIME: - val = ath_hal_getslottime(ah); + val = ath5k_hw_get_slot_time(ah); break; case ATH_LOCKSLOTTIME: val = sc->sc_lockslottime; break; case ATH_ACKTIMEOUT: - val = ath_hal_getacktimeout(ah); + val = ath5k_hw_get_ack_timeout(ah); break; case ATH_CTSTIMEOUT: - val = ath_hal_getctstimeout(ah); + val = ath5k_hw_get_cts_timeout(ah); break; case ATH_SOFTLED: val = sc->sc_softled; @@ -6395,7 +6394,7 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, val = sc->sc_ledpin; break; case ATH_COUNTRYCODE: - ath_hal_getcountrycode(ah, &val); + val = ah->ah_country_code; /* XXX */ break; case ATH_REGDOMAIN: ath_hal_getregdomain(ah, &val); @@ -6407,7 +6406,7 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, val = sc->sc_txantenna; break; case ATH_RXANTENNA: - val = ath_hal_getdefantenna(ah); + val = ath5k_hw_get_def_antenna(ah); break; case ATH_DIVERSITY: val = sc->sc_diversity; @@ -6661,7 +6660,7 @@ ath_announce(struct ath_softc *sc) * to avoid falsely printing revs for inoperable parts. * Dual-band radio revs are returned in the 5Ghz rev number. */ - ath_hal_getcountrycode(ah, &cc); + cc = ah->ah_country_code; modes = ath_hal_getwirelessmodes(ah, cc); if ((modes & AR5K_MODE_DUALBAND) == AR5K_MODE_DUALBAND) { if (ah->ah_radio_5ghz_revision && ah->ah_radio_2ghz_revision) diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 0df6d40..0d3f1d2 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -343,211 +343,57 @@ int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); void ath_sysctl_unregister(void); -/* - * HAL definitions to comply with local coding convention. - */ -#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ - ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) -#define ath_hal_getratetable(_ah, _mode) \ - ((*(_ah)->ah_getRateTable)((_ah), (_mode))) -#define ath_hal_getmac(_ah, _mac) \ - ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) -#define ath_hal_setmac(_ah, _mac) \ - ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) -#define ath_hal_intrset(_ah, _mask) \ - ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) -#define ath_hal_intrget(_ah) \ - ((*(_ah)->ah_getInterrupts)((_ah))) -#define ath_hal_intrpend(_ah) \ - ((*(_ah)->ah_isInterruptPending)((_ah))) -#define ath_hal_getisr(_ah, _pmask) \ - ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) -#define ath_hal_updatetxtriglevel(_ah, _inc) \ - ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) -#define ath_hal_setpower(_ah, _mode, _sleepduration) \ - ((*(_ah)->ah_setPowerMode)((_ah), (_mode), true, (_sleepduration))) -#define ath_hal_keycachesize(_ah) \ - ((*(_ah)->ah_getKeyCacheSize)((_ah))) -#define ath_hal_keyreset(_ah, _ix) \ - ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) -#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ - ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), FALSE)) -#define ath_hal_keyisvalid(_ah, _ix) \ - (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) -#define ath_hal_keysetmac(_ah, _ix, _mac) \ - ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) -#define ath_hal_getrxfilter(_ah) \ - ((*(_ah)->ah_getRxFilter)((_ah))) -#define ath_hal_setrxfilter(_ah, _filter) \ - ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) -#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ - ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) -#define ath_hal_waitforbeacon(_ah, _bf) \ - ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) -#define ath_hal_putrxbuf(_ah, _bufaddr) \ - ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) -#define ath_hal_gettsf32(_ah) \ - ((*(_ah)->ah_getTsf32)((_ah))) -#define ath_hal_gettsf64(_ah) \ - ((*(_ah)->ah_getTsf64)((_ah))) -#define ath_hal_resettsf(_ah) \ - ((*(_ah)->ah_resetTsf)((_ah))) -#define ath_hal_rxena(_ah) \ - ((*(_ah)->ah_enableReceive)((_ah))) -#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ - ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) -#define ath_hal_gettxbuf(_ah, _q) \ - ((*(_ah)->ah_getTxDP)((_ah), (_q))) -#define ath_hal_numtxpending(_ah, _q) \ - ((*(_ah)->ah_numTxPending)((_ah), (_q))) -#define ath_hal_getrxbuf(_ah) \ - ((*(_ah)->ah_getRxDP)((_ah))) -#define ath_hal_txstart(_ah, _q) \ - ((*(_ah)->ah_startTxDma)((_ah), (_q))) -#define ath_hal_setchannel(_ah, _chan) \ - ((*(_ah)->ah_setChannel)((_ah), (_chan))) -#define ath_hal_calibrate(_ah, _chan) \ - ((*(_ah)->ah_perCalibration)((_ah), (_chan))) -#define ath_hal_setledstate(_ah, _state) \ - ((*(_ah)->ah_setLedState)((_ah), (_state))) -#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ - ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) -#define ath_hal_beaconreset(_ah) \ - ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) -#define ath_hal_beacontimers(_ah, _bs) \ - ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) -#define ath_hal_setassocid(_ah, _bss, _associd) \ - ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) -#define ath_hal_phydisable(_ah) \ - ((*(_ah)->ah_phyDisable)((_ah))) -#define ath_hal_setopmode(_ah) \ - ((*(_ah)->ah_setPCUConfig)((_ah))) -#define ath_hal_stoptxdma(_ah, _qnum) \ - ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) -#define ath_hal_stoppcurecv(_ah) \ - ((*(_ah)->ah_stopPcuReceive)((_ah))) -#define ath_hal_startpcurecv(_ah) \ - ((*(_ah)->ah_startPcuReceive)((_ah))) -#define ath_hal_stopdmarecv(_ah) \ - ((*(_ah)->ah_stopDmaReceive)((_ah))) -#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ - ((*(_ah)->ah_getDiagState)((_ah), (_id), \ - (_indata), (_insize), (_outdata), (_outsize))) -#define ath_hal_setuptxqueue(_ah, _type, _irq) \ - ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) -#define ath_hal_resettxqueue(_ah, _q) \ - ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) -#define ath_hal_releasetxqueue(_ah, _q) \ - ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) -#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ - ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) -#define ath_hal_settxqueueprops(_ah, _q, _qi) \ - ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) -#define ath_hal_getrfgain(_ah) \ - ((*(_ah)->ah_getRfGain)((_ah))) -#define ath_hal_getdefantenna(_ah) \ - ((*(_ah)->ah_getDefAntenna)((_ah))) -#define ath_hal_setdefantenna(_ah, _ant) \ - ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) -#define ath_hal_rxmonitor(_ah, _arg) \ - ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) -#define ath_hal_mibevent(_ah, _stats) \ - ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) -#define ath_hal_setslottime(_ah, _us) \ - ((*(_ah)->ah_setSlotTime)((_ah), (_us))) -#define ath_hal_getslottime(_ah) \ - ((*(_ah)->ah_getSlotTime)((_ah))) -#define ath_hal_setacktimeout(_ah, _us) \ - ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) -#define ath_hal_getacktimeout(_ah) \ - ((*(_ah)->ah_getAckTimeout)((_ah))) -#define ath_hal_setctstimeout(_ah, _us) \ - ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) -#define ath_hal_getctstimeout(_ah) \ - ((*(_ah)->ah_getCTSTimeout)((_ah))) -#define ath_hal_getcapability(_ah, _cap, _param, _result) \ - ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) -#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ - ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) #define ath_hal_ciphersupported(_ah, _cipher) \ - (ath_hal_getcapability(_ah, AR5K_CAP_CIPHER, _cipher, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_CIPHER, _cipher, NULL) == AR5K_OK) #define ath_hal_getregdomain(_ah, _prd) \ - ath_hal_getcapability(_ah, AR5K_CAP_REG_DMN, 0, (_prd)) + ath5k_hw_get_capability(_ah, AR5K_CAP_REG_DMN, 0, (_prd)) #define ath_hal_getcountrycode(_ah, _pcc) \ (*(_pcc) = (_ah)->ah_country_code) #define ath_hal_tkipsplit(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == AR5K_OK) #define ath_hal_hwphycounters(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == AR5K_OK) #define ath_hal_hasdiversity(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == AR5K_OK) #define ath_hal_getdiversity(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == AR5K_OK) #define ath_hal_setdiversity(_ah, _v) \ - ath_hal_setcapability(_ah, AR5K_CAP_DIVERSITY, 1, _v, NULL) + ath5k_hw_set_capability(_ah, AR5K_CAP_DIVERSITY, 1, _v, NULL) #define ath_hal_getdiag(_ah, _pv) \ - (ath_hal_getcapability(_ah, AR5K_CAP_DIAG, 0, _pv) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIAG, 0, _pv) == AR5K_OK) #define ath_hal_setdiag(_ah, _v) \ - ath_hal_setcapability(_ah, AR5K_CAP_DIAG, 0, _v, NULL) + ath5k_hw_set_capability(_ah, AR5K_CAP_DIAG, 0, _v, NULL) #define ath_hal_getnumtxqueues(_ah, _pv) \ - (ath_hal_getcapability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == AR5K_OK) #define ath_hal_hasveol(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_VEOL, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == AR5K_OK) #define ath_hal_hastxpowlimit(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_TXPOW, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 0, NULL) == AR5K_OK) #define ath_hal_settxpowlimit(_ah, _pow) \ ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) #define ath_hal_gettxpowlimit(_ah, _ppow) \ - (ath_hal_getcapability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == AR5K_OK) #define ath_hal_getmaxtxpow(_ah, _ppow) \ - (ath_hal_getcapability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == AR5K_OK) #define ath_hal_gettpscale(_ah, _scale) \ - (ath_hal_getcapability(_ah, AR5K_CAP_TXPOW, 3, _scale) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 3, _scale) == AR5K_OK) #define ath_hal_settpscale(_ah, _v) \ - ath_hal_setcapability(_ah, AR5K_CAP_TXPOW, 3, _v, NULL) + ath5k_hw_set_capability(_ah, AR5K_CAP_TXPOW, 3, _v, NULL) #define ath_hal_hastpc(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_TPC, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == AR5K_OK) #define ath_hal_gettpc(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_TPC, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == AR5K_OK) #define ath_hal_settpc(_ah, _v) \ - ath_hal_setcapability(_ah, AR5K_CAP_TPC, 1, _v, NULL) + ath5k_hw_set_capability(_ah, AR5K_CAP_TPC, 1, _v, NULL) #define ath_hal_hasbursting(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_BURST, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == AR5K_OK) #ifdef notyet #define ath_hal_hasmcastkeysearch(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == AR5K_OK) #define ath_hal_getmcastkeysearch(_ah) \ - (ath_hal_getcapability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == AR5K_OK) #else #define ath_hal_getmcastkeysearch(_ah) 0 #endif -#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ - ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) -#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ - ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) -#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ - _txr0, _txtr0, _keyix, _ant, _flags, \ - _rtsrate, _rtsdura) \ - ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ - (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ - (_flags), (_rtsrate), (_rtsdura))) -#define ath_hal_setupxtxdesc(_ah, _ds, \ - _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ - ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ - (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) -#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ - ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) -#define ath_hal_txprocdesc(_ah, _ds) \ - ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) -#define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \ - _gatingds, _txOpLimit, _ctsDuration) \ - ((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \ - (_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration))) - -#define ath_hal_gpioCfgOutput(_ah, _gpio) \ - ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) -#define ath_hal_gpioset(_ah, _gpio, _b) \ - ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) - #endif /* _DEV_ATH_ATHVAR_H */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 4fc5efa..3bf9636 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -46,7 +46,6 @@ #include "ath5k_hw.h" #include "ieee80211_regdomain.h" -#include "translation.h" /* PCI IDs */ #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ @@ -242,7 +241,7 @@ struct ath_tx_status { u16 ts_tstamp; u8 ts_status; u8 ts_rate; - int8_t ts_rssi; + s8 ts_rssi; u8 ts_shortretry; u8 ts_longretry; u8 ts_virtcol; @@ -463,7 +462,7 @@ struct ath_rx_status { u16 rs_tstamp; u8 rs_status; u8 rs_phyerr; - int8_t rs_rssi; + s8 rs_rssi; u8 rs_keyix; u8 rs_rate; u8 rs_antenna; @@ -957,144 +956,6 @@ struct ath5k_capabilities { * Misc defines */ -struct ath_hal; - -typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); - -/* - * HAL Functions that have different implementations for each chipset... - */ -#define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ath5k_##_n##_##_f -#define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ - _t const struct ath5k_rate_table *(_a _n##_get_rate_table)(struct ath_hal *, \ - u_int mode); \ - _t void (_a _n##_detach)(struct ath_hal *); \ - /* Reset functions */ \ - _t bool (_a _n##_reset)(struct ath_hal *, enum ieee80211_if_types, \ - struct ath5k_channel *, bool change_channel, enum ath5k_status *status);\ - _t void (_a _n##_set_opmode)(struct ath_hal *); \ - _t bool (_a _n##_phy_calibrate)(struct ath_hal*, struct ath5k_channel *); \ - /* Transmit functions */ \ - _t bool (_a _n##_update_tx_triglevel)(struct ath_hal*, bool level); \ - _t int (_a _n##_setup_tx_queue)(struct ath_hal *, enum ath5k_tx_queue, \ - struct ath5k_txq_info *); \ - _t bool (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ - const struct ath5k_txq_info *); \ - _t bool (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ - _t bool (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ - _t u32 (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ - _t bool (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u32 phys_addr); \ - _t bool (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ - _t bool (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ - _t bool (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int packet_length, u_int header_length, enum ath5k_pkt_type type, \ - u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \ - u_int antenna_mode, u_int flags, u_int rtscts_rate, \ - u_int rtscts_duration); \ - _t bool (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ - u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ - _t bool (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ - bool firstSeg, bool lastSeg, const struct ath_desc *); \ - _t enum ath5k_status (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ - _t bool (_a _n##_has_veol)(struct ath_hal *); \ - /* Receive Functions */ \ - _t u32 (_a _n##_get_rx_buf)(struct ath_hal*); \ - _t void (_a _n##_put_rx_buf)(struct ath_hal*, u32 rxdp); \ - _t void (_a _n##_start_rx)(struct ath_hal*); \ - _t bool (_a _n##_stop_rx_dma)(struct ath_hal*); \ - _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \ - _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \ - _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u32 filter0, \ - u32 filter1); \ - _t bool (_a _n##_set_mcast_filterindex)(struct ath_hal*, u32 index); \ - _t bool (_a _n##_clear_mcast_filter_idx)(struct ath_hal*, u32 index); \ - _t u32 (_a _n##_get_rx_filter)(struct ath_hal*); \ - _t void (_a _n##_set_rx_filter)(struct ath_hal*, u32); \ - _t bool (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u32 size, u_int flags); \ - _t enum ath5k_status (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u32 phyAddr, struct ath_desc *next); \ - _t void (_a _n##_set_rx_signal)(struct ath_hal *, const struct ath5k_node_stats *); \ - /* Misc Functions */ \ - _t void (_a _n##_dump_state)(struct ath_hal *); \ - _t bool (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ - u32 argsize, void **result, u32 *resultsize); \ - _t void (_a _n##_get_lladdr)(struct ath_hal *, u8 *); \ - _t bool (_a _n##_set_lladdr)(struct ath_hal *, const u8*); \ - _t bool (_a _n##_set_regdomain)(struct ath_hal*, u16, enum ath5k_status *); \ - _t void (_a _n##_set_ledstate)(struct ath_hal*, unsigned int); \ - _t void (_a _n##_set_associd)(struct ath_hal*, const u8 *bssid, \ - u16 assocId); \ - _t bool (_a _n##_set_gpio_input)(struct ath_hal *, u32 gpio); \ - _t bool (_a _n##_set_gpio_output)(struct ath_hal *, u32 gpio); \ - _t u32 (_a _n##_get_gpio)(struct ath_hal *, u32 gpio); \ - _t bool (_a _n##_set_gpio)(struct ath_hal *, u32 gpio, u32 val); \ - _t void (_a _n##_set_gpio_intr)(struct ath_hal *, u_int, u32); \ - _t u32 (_a _n##_get_tsf32)(struct ath_hal *); \ - _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal *); \ - _t void (_a _n##_reset_tsf)(struct ath_hal *); \ - _t u16 (_a _n##_get_regdomain)(struct ath_hal *); \ - _t bool (_a _n##_detect_card_present)(struct ath_hal *); \ - _t void (_a _n##_update_mib_counters)(struct ath_hal *, struct ath5k_mib_stats *); \ - _t enum ath5k_rfgain (_a _n##_get_rf_gain)(struct ath_hal *); \ - _t bool (_a _n##_set_slot_time)(struct ath_hal *, u_int); \ - _t u_int (_a _n##_get_slot_time)(struct ath_hal *); \ - _t bool (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ - _t u_int (_a _n##_get_ack_timeout)(struct ath_hal *); \ - _t bool (_a _n##_set_cts_timeout)(struct ath_hal *, u_int); \ - _t u_int (_a _n##_get_cts_timeout)(struct ath_hal *); \ - /* Key Cache Functions */ \ - _t bool (_a _n##_is_cipher_supported)(struct ath_hal*, enum ath5k_cipher); \ - _t u32 (_a _n##_get_keycache_size)(struct ath_hal*); \ - _t bool (_a _n##_reset_key)(struct ath_hal*, u16); \ - _t bool (_a _n##_is_key_valid)(struct ath_hal *, u16); \ - _t bool (_a _n##_set_key)(struct ath_hal*, u16, const struct ath5k_keyval *, \ - const u8 *, int); \ - _t bool (_a _n##_set_key_lladdr)(struct ath_hal*, u16, const u8 *); \ - /* Power Management Functions */ \ - _t bool (_a _n##_set_power)(struct ath_hal*, enum ath5k_power_mode mode, \ - bool set_chip, u16 sleep_duration); \ - _t enum ath5k_power_mode (_a _n##_get_power_mode)(struct ath_hal*); \ - _t bool (_a _n##_query_pspoll_support)(struct ath_hal*); \ - _t bool (_a _n##_init_pspoll)(struct ath_hal*); \ - _t bool (_a _n##_enable_pspoll)(struct ath_hal *, u8 *, u16); \ - _t bool (_a _n##_disable_pspoll)(struct ath_hal *); \ - /* Beacon Management Functions */ \ - _t void (_a _n##_init_beacon)(struct ath_hal *, u32 nexttbtt, u32 intval); \ - _t void (_a _n##_set_beacon_timers)(struct ath_hal *, \ - const struct ath5k_beacon_state *); \ - _t void (_a _n##_reset_beacon)(struct ath_hal *); \ - _t bool (_a _n##_wait_for_beacon)(struct ath_hal *, unsigned long); \ - /* Interrupt functions */ \ - _t bool (_a _n##_is_intr_pending)(struct ath_hal *); \ - _t bool (_a _n##_get_isr)(struct ath_hal *, u32 *); \ - _t u32 (_a _n##_get_intr)(struct ath_hal *); \ - _t enum ath5k_int (_a _n##_set_intr)(struct ath_hal *, enum ath5k_int); \ - /* Chipset functions (ar5k-specific, non-HAL) */ \ - _t bool (_a _n##_get_capabilities)(struct ath_hal *); \ - _t void (_a _n##_radar_alert)(struct ath_hal *, bool enable); \ - _t bool (_a _n##_eeprom_is_busy)(struct ath_hal *); \ - _t int (_a _n##_eeprom_read)(struct ath_hal *, u32 offset, u16 *data); \ - _t int (_a _n##_eeprom_write)(struct ath_hal *, u32 offset, u16 data); \ - /* Functions not found in OpenBSD */ \ - _t bool (_a _n##_get_tx_queueprops)(struct ath_hal *, int, struct ath5k_txq_info *); \ - _t enum ath5k_status (_a _n##_get_capability)(struct ath_hal *, \ - enum ath5k_capability_type, u32, u32 *); \ - _t u32 (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ - _t bool (_a _n##_phy_disable)(struct ath_hal *); \ - _t void (_a _n##_set_pcu_config)(struct ath_hal *); \ - _t bool (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ - _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \ - _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \ - _t bool (_a _n ##_set_bssid_mask)(struct ath_hal *, const u8 *); \ - /*Totaly unimplemented*/ \ - _t bool (_a _n##_set_capability)(struct ath_hal *, enum ath5k_capability_type, u32, \ - u32,enum ath5k_status *); \ - _t void (_a _n##_proc_mib_event)(struct ath_hal *, const struct ath5k_node_stats *); \ - _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u32 *); - - #define AR5K_MAX_GPIO 10 #define AR5K_MAX_RF_BANKS 8 @@ -1186,65 +1047,175 @@ struct ath_hal { /* * Function pointers */ - AR5K_HAL_FUNCTIONS(, ah, *) + bool (*ah_setup_tx_desc)(struct ath_hal *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int); + bool (*ah_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); + bool (*ah_fill_tx_desc)(struct ath_hal *, struct ath_desc *, + unsigned int, bool, bool, const struct ath_desc *); + enum ath5k_status (*ah_proc_tx_desc)(struct ath_hal *, + struct ath_desc *); + enum ath5k_status (*ah_proc_rx_desc)(struct ath_hal *, + struct ath_desc *, u32, struct ath_desc *); }; /* * Prototypes */ +typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); -const char *ath_hal_probe(u16, u16); -struct ath_hal *ath5k_hw_init(u16, void *, void __iomem *, enum ath5k_status *); -u16 ath_hal_computetxtime(struct ath_hal *, const struct ath5k_rate_table *, - u32, u16, bool); -u_int ath_hal_mhz2ieee(u_int, u_int); -u_int ath_hal_ieee2mhz(u_int, u_int); -bool ath_hal_init_channels(struct ath_hal *, struct ath5k_channel *, - u_int, u_int *, enum ieee80211_countrycode, u16, - bool, bool); -const char *ath5k_printver(enum ath5k_srev_type, u32); -void ath5k_radar_alert(struct ath_hal *); -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16); -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain); -u16 ath5k_get_regdomain(struct ath_hal *); -u32 ath5k_bitswap(u32, u_int); -inline u_int ath5k_clocktoh(u_int, bool); -inline u_int ath5k_htoclock(u_int, bool); -void ath5k_rt_copy(struct ath5k_rate_table *, const struct ath5k_rate_table *); -bool ath5k_register_timeout(struct ath_hal *, u32, u32, - u32, bool); -int ath5k_eeprom_init(struct ath_hal *); -int ath5k_eeprom_read_mac(struct ath_hal *, u8 *); -bool ath5k_eeprom_regulation_domain(struct ath_hal *, bool, - enum ieee80211_regdomain *); -int ath5k_eeprom_read_ants(struct ath_hal *, u32 *, u_int); -int ath5k_eeprom_read_modes(struct ath_hal *, u32 *, u_int); -u16 ath5k_eeprom_bin2freq(struct ath_hal *, u16, u_int); - -bool ath5k_hw_channel(struct ath_hal *, struct ath5k_channel *); -bool ath5k_hw_rf5110_channel(struct ath_hal *, struct ath5k_channel *); -u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *); -bool ath5k_hw_rf5111_channel(struct ath_hal *, struct ath5k_channel *); -bool ath5k_hw_rf5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); -bool ath5k_hw_rf5112_channel(struct ath_hal *, struct ath5k_channel *); -bool ath5k_check_channel(struct ath_hal *, u16, u_int flags); - -bool ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); - -bool ath5k_hw_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); -bool ath5k_hw_rf5111_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); -bool ath5k_hw_rf5112_rfregs(struct ath_hal *, struct ath5k_channel *, u_int); -void ath5k_hw_ar5211_rfregs(struct ath_hal *, struct ath5k_channel *, u_int, u_int); -u_int ath5k_hw_rfregs_op(u32 *, u32, u32, u32, - u32, u32, bool); -u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *); -bool ath5k_hw_rfregs_gain_readback(struct ath_hal *); -s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *); -bool ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); -void ath5k_txpower_table(struct ath_hal *, struct ath5k_channel *, s16); - -/*added*/ -extern u_int ath_hal_getwirelessmodes(struct ath_hal *, enum ieee80211_countrycode); +/* General Functions */ +const char *ath_hal_probe(u16 vendor, u16 device); +u16 ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); +unsigned int ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) ; +/* Attach/Detach Functions */ +struct ath_hal *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); +bool ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial); +u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip); +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode); +void ath5k_hw_detach(struct ath_hal *hal); +/* Reset Functions */ +bool ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); +bool ath5k_hw_nic_reset(struct ath_hal *hal, u32 val); +/* Power management functions */ +bool ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal); +/* DMA Related Functions */ +void ath5k_hw_start_rx(struct ath_hal *hal); +bool ath5k_hw_stop_rx_dma(struct ath_hal *hal); +u32 ath5k_hw_get_rx_buf(struct ath_hal *hal); +void ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr); +bool ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue); +bool ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue); +u32 ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue); +bool ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr); +bool ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase); +/* Interrupt handling */ +bool ath5k_hw_is_intr_pending(struct ath_hal *hal); +bool ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask); +u32 ath5k_hw_get_intr(struct ath_hal *hal); +enum ath5k_int ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask); +void ath5k_hw_radar_alert(struct ath_hal *hal, bool enable); +/* EEPROM access functions */ +bool ath5k_hw_eeprom_is_busy(struct ath_hal *hal); +int ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data); +int ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data); +u16 ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode); +int ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode); +int ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode); +int ath5k_eeprom_init(struct ath_hal *hal); +int ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac); +bool ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, enum ieee80211_regdomain *regdomain); +bool ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, enum ath5k_status *status); +bool ath5k_hw_get_capabilities(struct ath_hal *hal); +/* Protocol Control Unit Functions */ +void ath5k_hw_set_opmode(struct ath_hal *hal); +void ath5k_hw_set_pcu_config(struct ath_hal *hal); +/* BSSID Functions */ +void ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac); +bool ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac); +void ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, u16 assoc_id); +bool ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask); +/* Receive start/stop functions */ +void ath5k_hw_start_rx_pcu(struct ath_hal *hal); +void ath5k_hw_stop_pcu_recv(struct ath_hal *hal); +/* RX Filter functions */ +void ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, u32 filter1); +bool ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index); +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index); +u32 ath5k_hw_get_rx_filter(struct ath_hal *hal); +void ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter); +/* Beacon related functions */ +u32 ath5k_hw_get_tsf32(struct ath_hal *hal); +u64 ath5k_hw_get_tsf64(struct ath_hal *hal); +void ath5k_hw_reset_tsf(struct ath_hal *hal); +void ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, u32 interval); +void ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state); +void ath5k_hw_reset_beacon(struct ath_hal *hal); +bool ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr); +void ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statistics); +void ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) ; +/* ACK/CTS Timeouts */ +bool ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout); +unsigned int ath5k_hw_get_ack_timeout(struct ath_hal *hal); +bool ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout); +unsigned int ath5k_hw_get_cts_timeout(struct ath_hal *hal); +/* Key table (WEP) functions */ +bool ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher); +u32 ath5k_hw_get_keycache_size(struct ath_hal *hal); +bool ath5k_hw_reset_key(struct ath_hal *hal, u16 entry); +bool ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry); +bool ath5k_hw_set_key(struct ath_hal *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused); +bool ath5k_hw_set_key_lladdr(struct ath_hal *hal, u16 entry, const u8 *mac); +/* Queue Control Unit, DFS Control Unit Functions */ +int ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); +bool ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, const struct ath5k_txq_info *queue_info); +bool ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info *queue_info); +bool ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue); +bool ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue); +u32 ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue); +bool ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time); +unsigned int ath5k_hw_get_slot_time(struct ath_hal *hal); +/* Hardware Descriptor Functions */ +/* RX Descriptor */ +bool ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u32 size, unsigned int flags); +/* GPIO Functions */ +void ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state); +bool ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio); +bool ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio); +u32 ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio); +bool ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val); +void ath5k_hw_set_gpio_intr(struct ath_hal *hal, unsigned int gpio, u32 interrupt_level); +/* Regulatory Domain/Channels Setup */ +unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); +unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); +bool ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags); +bool ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); +u16 ath5k_get_regdomain(struct ath_hal *hal); +u16 ath5k_hw_get_regdomain(struct ath_hal *hal); +/* PHY/RF access functions */ +bool ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel); +u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel); +bool ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan); +bool ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_phy_disable(struct ath_hal *hal); +void ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant); +unsigned int ath5k_hw_get_def_antenna(struct ath_hal *hal); +unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 first, u32 col, bool set); +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal); +bool ath5k_hw_rfregs_gain_readback(struct ath_hal *hal); +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal); +bool ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); +bool ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); +bool ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); +void ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode); +bool ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq); +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal); +/* TX power setup */ +/* Misc functions */ +void ath5k_hw_dump_state(struct ath_hal *hal); +bool ath5k_hw_has_veol(struct ath_hal *hal); +void ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u32 *i); +void ath5k_hw_set_rx_signal(struct ath_hal *hal, const struct ath5k_node_stats *stats); +bool ath5k_hw_get_diag_state(struct ath_hal *hal, int request, const void *args, u32 argsize, void **result, u32 *resultsize); +bool ath5k_hw_detect_card_present(struct ath_hal *hal); +enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; +bool ath5k_hw_set_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; +bool ath5k_hw_query_pspoll_support(struct ath_hal *hal); +bool ath5k_hw_init_pspoll(struct ath_hal *hal); +bool ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, u16 assoc_id); +bool ath5k_hw_disable_pspoll(struct ath_hal *hal); +const char *ath5k_printver(enum ath5k_srev_type type, u32 val); +void ath5k_radar_alert(struct ath_hal *hal); +void ath5k_hw_fill(struct ath_hal *hal); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index ea4d086..c384231 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -84,8 +84,6 @@ u16 ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); void ath5k_hw_fill(struct ath_hal *); bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, unsigned int); -AR5K_HAL_FUNCTIONS(extern, ath5k_hw,); - /* * Supported channels */ @@ -497,7 +495,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) } /* Get misc capabilities */ - if (hal->ah_get_capabilities(hal) != true) { + if (ath5k_hw_get_capabilities(hal) != true) { *status = AR5K_EEREAD; AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", device); @@ -512,7 +510,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) goto failed; } - hal->ah_set_lladdr(hal, mac); + ath5k_hw_set_lladdr(hal, mac); /* Get rate tables */ if (hal->ah_capabilities.cap_mode & AR5K_MODE_11A) @@ -2493,12 +2491,12 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) memset(mac, 0, ETH_ALEN); memset(&mac_d, 0, ETH_ALEN); - if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) + if (ath5k_hw_eeprom_read(hal, 0x20, &data) != 0) return AR5K_EIO; for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { - if (hal->ah_eeprom_read(hal, offset, &data) != 0) + if (ath5k_hw_eeprom_read(hal, offset, &data) != 0) return AR5K_EIO; total += data; @@ -2537,7 +2535,7 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_EEPROM_PROTECT_WR_128_191) return false; - if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, + if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain) != 0) return false; @@ -6428,31 +6426,6 @@ ath5k_hw_fill(struct ath_hal *hal) else if (hal->ah_version == AR5K_AR5211) hal->ah_magic = AR5K_EEPROM_MAGIC_5211; - /* - * Init/Exit functions - */ - AR5K_HAL_FUNCTION(hal, hw, get_rate_table); - AR5K_HAL_FUNCTION(hal, hw, detach); - - /* - * Reset functions - */ - AR5K_HAL_FUNCTION(hal, hw, reset); - AR5K_HAL_FUNCTION(hal, hw, set_opmode); - AR5K_HAL_FUNCTION(hal, hw, phy_calibrate); - - /* - * TX functions - */ - AR5K_HAL_FUNCTION(hal, hw, update_tx_triglevel); - AR5K_HAL_FUNCTION(hal, hw, setup_tx_queue); - AR5K_HAL_FUNCTION(hal, hw, setup_tx_queueprops); - AR5K_HAL_FUNCTION(hal, hw, release_tx_queue); - AR5K_HAL_FUNCTION(hal, hw, reset_tx_queue); - AR5K_HAL_FUNCTION(hal, hw, get_tx_buf); - AR5K_HAL_FUNCTION(hal, hw, put_tx_buf); - AR5K_HAL_FUNCTION(hal, hw, tx_start); - AR5K_HAL_FUNCTION(hal, hw, stop_tx_dma); if (hal->ah_version == AR5K_AR5212) { hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; @@ -6464,120 +6437,9 @@ ath5k_hw_fill(struct ath_hal *hal) hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc; hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; } - AR5K_HAL_FUNCTION(hal, hw, has_veol); - /* - * RX functions - */ - AR5K_HAL_FUNCTION(hal, hw, get_rx_buf); - AR5K_HAL_FUNCTION(hal, hw, put_rx_buf); - AR5K_HAL_FUNCTION(hal, hw, start_rx); - AR5K_HAL_FUNCTION(hal, hw, stop_rx_dma); - AR5K_HAL_FUNCTION(hal, hw, start_rx_pcu); - AR5K_HAL_FUNCTION(hal, hw, stop_pcu_recv); - AR5K_HAL_FUNCTION(hal, hw, set_mcast_filter); - AR5K_HAL_FUNCTION(hal, hw, set_mcast_filterindex); - AR5K_HAL_FUNCTION(hal, hw, clear_mcast_filter_idx); - AR5K_HAL_FUNCTION(hal, hw, get_rx_filter); - AR5K_HAL_FUNCTION(hal, hw, set_rx_filter); - AR5K_HAL_FUNCTION(hal, hw, setup_rx_desc); if (hal->ah_version == AR5K_AR5212) hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; else if (hal->ah_version <= AR5K_AR5211) hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; - AR5K_HAL_FUNCTION(hal, hw, set_rx_signal); - - /* - * Misc functions - */ - AR5K_HAL_FUNCTION(hal, hw, dump_state); - AR5K_HAL_FUNCTION(hal, hw, get_diag_state); - AR5K_HAL_FUNCTION(hal, hw, get_lladdr); - AR5K_HAL_FUNCTION(hal, hw, set_lladdr); - AR5K_HAL_FUNCTION(hal, hw, set_regdomain); - AR5K_HAL_FUNCTION(hal, hw, set_ledstate); - AR5K_HAL_FUNCTION(hal, hw, set_associd); - AR5K_HAL_FUNCTION(hal, hw, set_gpio_input); - AR5K_HAL_FUNCTION(hal, hw, set_gpio_output); - AR5K_HAL_FUNCTION(hal, hw, get_gpio); - AR5K_HAL_FUNCTION(hal, hw, set_gpio); - AR5K_HAL_FUNCTION(hal, hw, set_gpio_intr); - AR5K_HAL_FUNCTION(hal, hw, get_tsf32); - AR5K_HAL_FUNCTION(hal, hw, get_tsf64); - AR5K_HAL_FUNCTION(hal, hw, reset_tsf); - AR5K_HAL_FUNCTION(hal, hw, get_regdomain); - AR5K_HAL_FUNCTION(hal, hw, detect_card_present); - AR5K_HAL_FUNCTION(hal, hw, update_mib_counters); - AR5K_HAL_FUNCTION(hal, hw, get_rf_gain); - AR5K_HAL_FUNCTION(hal, hw, set_slot_time); - AR5K_HAL_FUNCTION(hal, hw, get_slot_time); - AR5K_HAL_FUNCTION(hal, hw, set_ack_timeout); - AR5K_HAL_FUNCTION(hal, hw, get_ack_timeout); - AR5K_HAL_FUNCTION(hal, hw, set_cts_timeout); - AR5K_HAL_FUNCTION(hal, hw, get_cts_timeout); - - /* - * Key table (WEP) functions - */ - AR5K_HAL_FUNCTION(hal, hw, is_cipher_supported); - AR5K_HAL_FUNCTION(hal, hw, get_keycache_size); - AR5K_HAL_FUNCTION(hal, hw, reset_key); - AR5K_HAL_FUNCTION(hal, hw, is_key_valid); - AR5K_HAL_FUNCTION(hal, hw, set_key); - AR5K_HAL_FUNCTION(hal, hw, set_key_lladdr); - - /* - * Power management functions - */ - AR5K_HAL_FUNCTION(hal, hw, set_power); - AR5K_HAL_FUNCTION(hal, hw, get_power_mode); - AR5K_HAL_FUNCTION(hal, hw, query_pspoll_support); - AR5K_HAL_FUNCTION(hal, hw, init_pspoll); - AR5K_HAL_FUNCTION(hal, hw, enable_pspoll); - AR5K_HAL_FUNCTION(hal, hw, disable_pspoll); - - /* - * Beacon functions - */ - AR5K_HAL_FUNCTION(hal, hw, init_beacon); - AR5K_HAL_FUNCTION(hal, hw, set_beacon_timers); - AR5K_HAL_FUNCTION(hal, hw, reset_beacon); - AR5K_HAL_FUNCTION(hal, hw, wait_for_beacon); - - /* - * Interrupt functions - */ - AR5K_HAL_FUNCTION(hal, hw, is_intr_pending); - AR5K_HAL_FUNCTION(hal, hw, get_isr); - AR5K_HAL_FUNCTION(hal, hw, get_intr); - AR5K_HAL_FUNCTION(hal, hw, set_intr); - - /* - * Chipset functions (ar5k-specific, non-HAL) - */ - AR5K_HAL_FUNCTION(hal, hw, get_capabilities); - AR5K_HAL_FUNCTION(hal, hw, radar_alert); - - /* - * EEPROM access - */ - AR5K_HAL_FUNCTION(hal, hw, eeprom_is_busy); - AR5K_HAL_FUNCTION(hal, hw, eeprom_read); - AR5K_HAL_FUNCTION(hal, hw, eeprom_write); - - /* Functions not found in OpenBSD */ - AR5K_HAL_FUNCTION(hal, hw, get_tx_queueprops); - AR5K_HAL_FUNCTION(hal, hw, get_capability); - AR5K_HAL_FUNCTION(hal, hw, num_tx_pending); - AR5K_HAL_FUNCTION(hal, hw, phy_disable); - AR5K_HAL_FUNCTION(hal, hw, set_pcu_config); - AR5K_HAL_FUNCTION(hal, hw, set_txpower_limit); - AR5K_HAL_FUNCTION(hal, hw, set_def_antenna); - AR5K_HAL_FUNCTION(hal, hw, get_def_antenna); - AR5K_HAL_FUNCTION(hal, hw, set_bssid_mask); - /*Totaly unimplemented*/ - AR5K_HAL_FUNCTION(hal, hw, set_capability); - AR5K_HAL_FUNCTION(hal, hw, proc_mib_event); - AR5K_HAL_FUNCTION(hal, hw, get_tx_inter_queue); - } diff --git a/openhal/ath5k_hw.h b/openhal/ath5k_hw.h index 3b53963..417812f 100644 --- a/openhal/ath5k_hw.h +++ b/openhal/ath5k_hw.h @@ -245,7 +245,7 @@ struct ath5k_eeprom_info { udelay(1); #define AR5K_EEPROM_READ(_o, _v) { \ - if ((ret = hal->ah_eeprom_read(hal, (_o), \ + if ((ret = ath5k_hw_eeprom_read(hal, (_o), \ &(_v))) != 0) \ return (ret); \ } diff --git a/openhal/translation.h b/openhal/translation.h deleted file mode 100644 index 219a1fc..0000000 --- a/openhal/translation.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * Init/Exit functions - */ -#define ah_getRateTable ah_get_rate_table -//detach - -/* - * Reset functions - */ -//reset -//set_opmode -#define ah_perCalibration ah_phy_calibrate -#define ah_phyDisable ah_phy_disable - -/* - * TX functions - */ -#define ah_updateTxTrigLevel ah_update_tx_triglevel -#define ah_setupTxQueue ah_setup_tx_queue -#define ah_setTxQueueProps ah_setup_tx_queueprops -#define ah_getTxQueueProps ah_get_tx_queueprops -#define ah_releaseTxQueue ah_release_tx_queue -#define ah_resetTxQueue ah_reset_tx_queue -#define ah_getTxDP ah_get_tx_buf -#define ah_setTxDP ah_put_tx_buf -#define ah_numTxPending ah_num_tx_pending -#define ah_startTxDma ah_tx_start -#define ah_stopTxDma ah_stop_tx_dma -#define ah_setupTxDesc ah_setup_tx_desc -#define ah_setupXTxDesc ah_setup_xtx_desc -#define ah_fillTxDesc ah_fill_tx_desc -#define ah_procTxDesc ah_proc_tx_desc -#define ah_getTxIntrQueue ah_get_tx_inter_queue -//has_veol - -/* - * RX functions - */ -#define ah_getRxDP ah_get_rx_buf -#define ah_setRxDP ah_put_rx_buf -#define ah_enableReceive ah_start_rx -#define ah_stopDmaReceive ah_stop_rx_dma -#define ah_startPcuReceive ah_start_rx_pcu -#define ah_stopPcuReceive ah_stop_pcu_recv -#define ah_setMulticastFilter ah_set_mcast_filter -#define ah_setMulticastFilterIndex ah_set_mcast_filterindex -#define ah_clrMulticastFilterIndex ah_clear_mcast_filter_idx -#define ah_getRxFilter ah_get_rx_filter -#define ah_setRxFilter ah_set_rx_filter -#define ah_setupRxDesc ah_setup_rx_desc -#define ah_procRxDesc ah_proc_rx_desc -#define ah_rxMonitor ah_set_rx_signal -#define ah_procMibEvent ah_proc_mib_event - -/* - * Misc functions - */ -#define ah_getCapability ah_get_capability -#define ah_setCapability ah_set_capability -//dump_state -#define ah_getDiagState ah_get_diag_state -#define ah_getMacAddress ah_get_lladdr -#define ah_setMacAddress ah_set_lladdr -#define ah_setBssIdMask ah_set_bssid_mask -//#define ah_getBssIdMask ah_get_bssid_mask -#define ah_setRegulatoryDomain ah_set_regdomain -#define ah_setLedState ah_set_ledstate -#define ah_writeAssocid ah_set_associd -#define ah_gpioCfgInput ah_set_gpio_input -#define ah_gpioCfgOutput ah_set_gpio_output -#define ah_gpioGet ah_get_gpio -#define ah_gpioSet ah_set_gpio -#define ah_gpioSetIntr ah_set_gpio_intr -#define ah_getTsf32 ah_get_tsf32 -#define ah_getTsf64 ah_get_tsf64 -#define ah_resetTsf ah_reset_tsf -//get_regdomain -#define ah_detectCardPresent ah_detect_card_present -#define ah_updateMibCounters ah_update_mib_counters -#define ah_getRfGain ah_get_rf_gain -#define ah_getDefAntenna ah_get_def_antenna -#define ah_setDefAntenna ah_set_def_antenna -#define ah_setSlotTime ah_set_slot_time -#define ah_getSlotTime ah_get_slot_time -#define ah_setAckTimeout ah_set_ack_timeout -#define ah_getAckTimeout ah_get_ack_timeout -#define ah_setCTSTimeout ah_set_cts_timeout -#define ah_getCTSTimeout ah_get_cts_timeout - -/* - * Key table (WEP) functions - */ -//is_cipher_supported -#define ah_getKeyCacheSize ah_get_keycache_size -#define ah_resetKeyCacheEntry ah_reset_key -#define ah_isKeyCacheEntryValid ah_is_key_valid -#define ah_setKeyCacheEntry ah_set_key -#define ah_setKeyCacheEntryMac ah_set_key_lladdr - -/* - * Power management functions - */ -#define ah_setPowerMode ah_set_power -#define ah_getPowerMode ah_get_power_mode -//query_pspoll_support -#define ah_initPSPoll ah_init_pspoll -#define ah_enablePSPoll ah_enable_pspoll -#define ah_disablePSPoll ah_disable_pspoll -#define ah_setTxPowerLimit ah_set_txpower_limit - -/* - * Beacon functions - */ -#define ah_beaconInit ah_init_beacon -#define ah_setStationBeaconTimers ah_set_beacon_timers -#define ah_resetStationBeaconTimers ah_reset_beacon -#define ah_waitForBeaconDone ah_wait_for_beacon - -/* - * Interrupt functions - */ -#define ah_isInterruptPending ah_is_intr_pending -#define ah_getPendingInterrupts ah_get_isr -#define ah_getInterrupts ah_get_intr -#define ah_setInterrupts ah_set_intr - -/* - * Chipset functions (ar5k-specific, non-HAL) - */ -//get_capabilities -#define ah_radarlert ah_radar_alert - -/* - * EEPROM access - */ -//eeprom_is_busy -//eeprom_read -//eeprom_write - -#define ah_setPCUConfig ah_set_pcu_config commit 5b0e4964aac39edbde94b062f649da16eef2b7d5 Author: Jiri Slaby Date: Tue Jun 19 14:49:43 2007 +0200 remove svn Id diff --git a/ath/if_ath.c b/ath/if_ath.c index 6841f55..3de318a 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -32,8 +32,6 @@ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. - * - * $Id: if_ath.c 2408 2007-05-30 22:58:20Z mickflemm $ */ /* commit 2112755f6a1811bdd0b26b8a28c60d89a5a513ed Author: Jiri Slaby Date: Tue Jun 19 14:50:59 2007 +0200 define missing pci ids diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 3bf9636..2b93265 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -48,6 +48,13 @@ #include "ieee80211_regdomain.h" /* PCI IDs */ +#ifndef PCI_VENDOR_ID_ATHEROS +#define PCI_VENDOR_ID_ATHEROS 0x168c +#endif +#ifndef PCI_VENDOR_ID_3COM_2 +#define PCI_VENDOR_ID_3COM_2 0xa727 +#endif + #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ commit 7e43a7f43d522eb484098ea858e0d33eeb4f0d6e Author: Jiri Slaby Date: Tue Jun 19 22:59:46 2007 +0200 functions move and cleanup diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 2b93265..451c3cc 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -456,7 +456,6 @@ enum ath5k_dmasize { }; - /****************\ RX DEFINITIONS \****************/ @@ -952,14 +951,6 @@ struct ath5k_capabilities { \***************************************/ /* - * Regulation stuff - */ - -/* Default regulation domain if stored value EEPROM value is invalid */ -#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ -#define AR5K_TUNE_CTRY CTRY_DEFAULT - -/* * Misc defines */ @@ -1080,13 +1071,13 @@ u16 ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *ra unsigned int ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ struct ath_hal *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); -bool ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial); -u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip); +//bool ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial); +//u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode); void ath5k_hw_detach(struct ath_hal *hal); /* Reset Functions */ bool ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); -bool ath5k_hw_nic_reset(struct ath_hal *hal, u32 val); +//bool ath5k_hw_nic_reset(struct ath_hal *hal, u32 val); /* Power management functions */ bool ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal); @@ -1181,10 +1172,7 @@ unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); bool ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags); bool ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); u16 ath5k_get_regdomain(struct ath_hal *hal); -u16 ath5k_hw_get_regdomain(struct ath_hal *hal); /* PHY/RF access functions */ bool ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel); u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel); @@ -1208,21 +1196,11 @@ bool ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, void ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode); bool ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq); enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal); -/* TX power setup */ /* Misc functions */ void ath5k_hw_dump_state(struct ath_hal *hal); -bool ath5k_hw_has_veol(struct ath_hal *hal); -void ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u32 *i); -void ath5k_hw_set_rx_signal(struct ath_hal *hal, const struct ath5k_node_stats *stats); -bool ath5k_hw_get_diag_state(struct ath_hal *hal, int request, const void *args, u32 argsize, void **result, u32 *resultsize); -bool ath5k_hw_detect_card_present(struct ath_hal *hal); enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; bool ath5k_hw_set_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; bool ath5k_hw_query_pspoll_support(struct ath_hal *hal); -bool ath5k_hw_init_pspoll(struct ath_hal *hal); bool ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, u16 assoc_id); bool ath5k_hw_disable_pspoll(struct ath_hal *hal); -const char *ath5k_printver(enum ath5k_srev_type type, u32 val); -void ath5k_radar_alert(struct ath_hal *hal); -void ath5k_hw_fill(struct ath_hal *hal); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index c384231..a56d14e 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -78,11 +78,34 @@ static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -bool ath5k_hw_nic_reset(struct ath_hal *, u32); -bool ath5k_hw_nic_wakeup(struct ath_hal *, u16, bool); -u16 ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); -void ath5k_hw_fill(struct ath_hal *); -bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, unsigned int); +static bool ath5k_hw_nic_reset(struct ath_hal *, u32); +static bool ath5k_hw_nic_wakeup(struct ath_hal *, u16, bool); +static u16 ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); +static bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, + unsigned int); +static bool ath5k_hw_setup_4word_tx_desc(struct ath_hal *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); +static bool ath5k_hw_setup_xr_tx_desc(struct ath_hal *, struct ath_desc *, + unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int); +static bool ath5k_hw_fill_4word_tx_desc(struct ath_hal *, struct ath_desc *, + unsigned int, bool, bool, const struct ath_desc *); +static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hal *, + struct ath_desc *); +static bool ath5k_hw_setup_2word_tx_desc(struct ath_hal *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); +static bool ath5k_hw_fill_2word_tx_desc(struct ath_hal *, struct ath_desc *, + unsigned int, bool, bool, const struct ath_desc *); +static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hal *, + struct ath_desc *); +static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hal *, + struct ath_desc *, u32, struct ath_desc *); +static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hal *, + struct ath_desc *, u32, struct ath_desc *); /* * Supported channels @@ -435,7 +458,27 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) hal->ah_version = mac_version; /*Fill the hal struct with the needed functions*/ - ath5k_hw_fill(hal); + if (hal->ah_version == AR5K_AR5212) + hal->ah_magic = AR5K_EEPROM_MAGIC_5212; + else if (hal->ah_version == AR5K_AR5211) + hal->ah_magic = AR5K_EEPROM_MAGIC_5211; + + if (hal->ah_version == AR5K_AR5212) { + hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; + hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; + hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc; + hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; + } else { + hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; + hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; + hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc; + hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; + } + + if (hal->ah_version == AR5K_AR5212) + hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; + else if (hal->ah_version <= AR5K_AR5211) + hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; /* Bring device out of sleep and reset it's units */ if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true) != true) @@ -555,7 +598,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /* * Bring up MAC + PHY Chips */ -bool +static bool ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) { u32 turbo, mode, clock; @@ -686,7 +729,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) /* * Get the PHY Chip revision */ -u16 +static u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) { int i; @@ -1370,7 +1413,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, /* * Reset chipset */ -bool +static bool ath5k_hw_nic_reset(struct ath_hal *hal, u32 val) { bool ret = false; @@ -1870,13 +1913,6 @@ ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask) *interrupt_mask |= AR5K_INT_BNR; } - /* - * Special interrupt handling (not caught by the driver) - */ - if (((*interrupt_mask) & AR5K_ISR_RXPHY) && - hal->ah_radar.r_enabled == true) - ath5k_radar_alert(hal); - /* * XXX: BMISS interrupts may occur after association. * I found this on 5210 code but it needs testing @@ -3882,8 +3918,6 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) } - - /******************************\ Hardware Descriptor Functions \******************************/ @@ -4907,35 +4941,6 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ return true; } -/* - * Regdomain stuff, these also don't belong here etc - */ - -u16 -ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) -{ - u32 regdomain = (u32)ieee; - - /* - * Use the default regulation domain if the value is empty - * or not supported by the net80211 regulation code. - */ - if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) - return (u16)AR5K_TUNE_REGDOMAIN; - - /* It is supported, just return the value */ - return regdomain; -} - -enum ieee80211_regdomain -ath5k_regdomain_to_ieee(u16 regdomain) -{ - enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; - - return ieee; -} - u16 ath5k_get_regdomain(struct ath_hal *hal) { @@ -4963,16 +4968,6 @@ ath5k_get_regdomain(struct ath_hal *hal) return regdomain; } -u16 /*TODO:Get rid of this*/ -ath5k_hw_get_regdomain(struct ath_hal *hal) -{ - AR5K_TRACE; - return ath5k_get_regdomain(hal); -} - - - - /*************************\ PHY/RF access functions \*************************/ @@ -5978,7 +5973,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) /* * Initialize the tx power table (not fully implemented) */ -void +static void ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_power) { u16 txpower, *rates; @@ -6016,7 +6011,7 @@ ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_ /* * Set transmition power */ -bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ +static bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; @@ -6196,54 +6191,6 @@ ath5k_hw_dump_state(struct ath_hal *hal) #endif } -bool /*what about VEOL cap ?*/ -ath5k_hw_has_veol(struct ath_hal *hal) -{ - return true; -} - -void /*Unimplemented*/ -ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u32 *i) -{ - AR5K_TRACE; - /* XXX */ -} - -void /*Added struct ath5k_node_stats argument*/ -ath5k_hw_set_rx_signal(struct ath_hal *hal, const struct ath5k_node_stats *stats) -{ - AR5K_TRACE; - /* Signal state monitoring is not yet supported */ -} - -bool /*Added arguments*/ -ath5k_hw_get_diag_state(struct ath_hal *hal, int request, - const void *args, u32 argsize, void **result, u32 *resultsize) -{ - AR5K_TRACE; - /* - * We'll ignore this right now. This seems to be some kind of an obscure - * debugging interface for the binary-only HAL. - */ - return false; -} - -bool /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ -ath5k_hw_detect_card_present(struct ath_hal *hal) -{ - u16 magic; - AR5K_TRACE; - /* - * Checking the EEPROM's magic value could be an indication - * if the card is still present. I didn't find another suitable - * way to do this. - */ - if (ath5k_hw_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return false; - - return magic == AR5K_EEPROM_MAGIC_VALUE ? true : false; -} - enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, u32 capability, u32 *result) @@ -6327,16 +6274,6 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) } bool -ath5k_hw_init_pspoll(struct ath_hal *hal) -{ - AR5K_TRACE; - /* - * Not used - */ - return false; -} - -bool ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, u16 assoc_id) { @@ -6364,82 +6301,3 @@ ath5k_hw_disable_pspoll(struct ath_hal *hal) return false; } - -const char * /*O.K. - TODO:Get rid of this*/ -ath5k_printver(enum ath5k_srev_type type, u32 val) -{ - struct ath5k_srev_name names[] = AR5K_SREV_NAME; - const char *name = "xxxx"; - int i; - - for (i = 0; i < ARRAY_SIZE(names); i++) { - if (type == AR5K_VERSION_DEV) { - if (names[i].sr_type == type && - names[i].sr_val == val) { - name = names[i].sr_name; - break; - } - continue; - } - if (names[i].sr_type != type || - names[i].sr_val == AR5K_SREV_UNKNOWN) - continue; - if ((val & 0xff) < names[i + 1].sr_val) { - name = names[i].sr_name; - break; - } - } - - return name; -} - -void /*O.K. - TODO: Implement this in if_ath.c (ath_intr)*/ -ath5k_radar_alert(struct ath_hal *hal) -{ - /* - * Limit ~1/s - */ - -// if (hal->ah_radar.r_last_channel.freq == -// hal->ah_current_channel.freq && -// tick < (hal->ah_radar.r_last_alert + hz)) - return; - -/* hal->ah_radar.r_last_channel.freq = - hal->ah_current_channel.freq; - hal->ah_radar.r_last_channel.channel_flags = - hal->ah_current_channel.channel_flags; - hal->ah_radar.r_last_alert = tick; - - AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", - hal->ah_radar.r_last_alert, hal->ah_current_channel.freq);*/ -} - -/* - * Fill the hal struct, left here for combatibility - */ -void /*Functions added*/ -ath5k_hw_fill(struct ath_hal *hal) -{ - if (hal->ah_version == AR5K_AR5212) - hal->ah_magic = AR5K_EEPROM_MAGIC_5212; - else if (hal->ah_version == AR5K_AR5211) - hal->ah_magic = AR5K_EEPROM_MAGIC_5211; - - if (hal->ah_version == AR5K_AR5212) { - hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; - hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; - hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc; - hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; - } else { - hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; - hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; - hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc; - hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; - } - - if (hal->ah_version == AR5K_AR5212) - hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; - else if (hal->ah_version <= AR5K_AR5211) - hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; -} diff --git a/openhal/ieee80211_regdomain.c b/openhal/ieee80211_regdomain.c index a2fd25a..f600604 100644 --- a/openhal/ieee80211_regdomain.c +++ b/openhal/ieee80211_regdomain.c @@ -87,3 +87,27 @@ u32 ieee80211_regdomain2flag(u16 regdomain, u16 mhz) return (u32)DMN_DEBUG; } + +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) +{ + u32 regdomain = (u32)ieee; + + /* + * Use the default regulation domain if the value is empty + * or not supported by the net80211 regulation code. + */ + if (ieee80211_regdomain2flag(regdomain, + IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + return (u16)AR5K_TUNE_REGDOMAIN; + + /* It is supported, just return the value */ + return regdomain; +} + +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) +{ + enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; + + return ieee; +} + diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 8d9ad74..1f1ed97 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -6,11 +6,16 @@ * copyright notice and this permission notice appear in all copies. */ -#ifndef _NET80211_IEEE80211_REGDOMAIN_H_ -#define _NET80211_IEEE80211_REGDOMAIN_H_ +#ifndef _IEEE80211_REGDOMAIN_H_ +#define _IEEE80211_REGDOMAIN_H_ #include +/* Default regulation domain if stored value EEPROM value is invalid */ +#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ +#define AR5K_TUNE_CTRY CTRY_DEFAULT + + enum ieee80211_regdomain { DMN_DEFAULT = 0x00, DMN_NULL_WORLD = 0x03, @@ -482,5 +487,7 @@ struct ieee80211_regchannel { } u32 ieee80211_regdomain2flag(u16, u16); +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); #endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ commit e96ad6dbcadd7370c7ba71b20618b0370dc5fa8f Author: Jiri Slaby Date: Tue Jun 19 23:26:30 2007 +0200 remove ahb diff --git a/Makefile b/Makefile index e891fe0..cbd7dfa 100644 --- a/Makefile +++ b/Makefile @@ -1,17 +1,9 @@ KDIR=/lib/modules/$(shell uname -r)/build KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) -ifeq ($(strip $(BUS)),AHB) -EXTRA_CFLAGS += -DATH_AHB -bus=ath -else -EXTRA_CFLAGS += -DATH_PCI -bus=pci -endif - EXTRA_CFLAGS += -I$(src)/openhal -ath5k-objs := ath/if_ath.o ath/if_ath_$(bus).o openhal/ath5k_hw.o \ +ath5k-objs := ath/if_ath.o ath/if_ath_pci.o openhal/ath5k_hw.o \ openhal/ieee80211_regdomain.o #ath/radar.o obj-m += ath5k.o diff --git a/ath/if_ath.c b/ath/if_ath.c index 3de318a..e2dc8ee 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -40,9 +40,6 @@ * This software is derived from work of Atsushi Onoe; his contribution * is greatly appreciated. */ -#ifndef AUTOCONF_INCLUDED -#include -#endif #include #include #include @@ -67,16 +64,9 @@ /*#include "radar.h"*/ +#include "if_ath_pci.h" #include "if_athvar.h" #include "ath5k.h" - -#ifdef ATH_PCI /* PCI BUS */ -#include "if_ath_pci.h" -#endif /* PCI BUS */ -#ifdef ATH_AHB /* AHB BUS */ -#include "if_ath_ahb.h" -#endif /* AHB BUS */ - #include "ath_hw.h" #define KASSERT(exp, msg...) do { \ commit cad85c03520dbd348dbd633e50d1bc8fc2e19587 Author: Jiri Slaby Date: Tue Jun 19 23:32:42 2007 +0200 add devinit and devexit diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 2934afd..6a98a2d 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -77,7 +77,8 @@ void bus_read_cachesize(struct ath_softc *sc, u8 *csz) pci_read_config_byte(sc->sc_bdev, PCI_CACHE_LINE_SIZE, csz); } -static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) +static int __devinit ath_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) { void __iomem *mem; struct ath_softc *sc; @@ -206,7 +207,7 @@ err: return retval; } -static void ath_pci_remove(struct pci_dev *pdev) +static void __devexit ath_pci_remove(struct pci_dev *pdev) { struct net_device *dev = pci_get_drvdata(pdev); struct ath_softc *sc = dev->priv; commit b5617d7a818453cf2f16e35fa97a42d9211c39ef Author: Jiri Slaby Date: Wed Jun 20 10:12:42 2007 +0200 remove opt_ah.h reference diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 6a98a2d..ad78e30 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -24,8 +24,6 @@ */ #define ATH_PCI_VERSION "0.9.5.0-BSD" -#include "opt_ah.h" - #include #include #include commit e3da8ea8c04c123504a0b4fe8cf2cc18447d6799 Author: Jiri Slaby Date: Wed Jun 20 18:22:24 2007 +0200 alloc ieee80211_hw instead of netdev diff --git a/ath/if_ath.c b/ath/if_ath.c index e2dc8ee..f342270 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -86,15 +86,15 @@ enum { ATH_LED_POLL, }; -static int ath_init(struct net_device *); -static int ath_reset(struct net_device *); +static int ath_init(struct ieee80211_hw *); +static int ath_reset(struct ieee80211_hw *); static void ath_fatal_tasklet(unsigned long); static void ath_bstuck_tasklet(unsigned long); static void ath_rxorn_tasklet(unsigned long); static void ath_bmiss_tasklet(unsigned long); static void ath_radar_tasklet(unsigned long); -static int ath_stop_locked(struct net_device *); -static int ath_stop(struct net_device *); +static int ath_stop_locked(struct ieee80211_hw *); +static int ath_stop(struct ieee80211_hw *); #ifdef BLE static int ath_media_change(struct net_device *); static int ath_key_alloc(struct ieee80211com *, @@ -115,7 +115,7 @@ static int ath_beaconq_setup(struct ath_hal *); static void ath_beacon_setup(struct ath_softc *, struct ath_buf *, struct ieee80211_tx_control *); static void ath_beacon_send(struct net_device *); -static void ath_beacon_free(struct ath_softc *); +//static void ath_beacon_free(struct ath_softc *); //static void ath_beacon_config(struct ath_softc *); static void ath_descdma_cleanup(struct ath_softc *sc, struct list_head *); static int ath_desc_alloc(struct ath_softc *); @@ -148,8 +148,8 @@ static void ath_tx_tasklet(unsigned long data); static void ath_tx_timeout(struct net_device *); static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); #endif -static void ath_draintxq(struct ath_softc *); -static void ath_stoprecv(struct ath_softc *); +//static void ath_draintxq(struct ath_softc *); +//static void ath_stoprecv(struct ath_softc *); static int ath_startrecv(struct ath_softc *); //static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); static void ath_next_scan(unsigned long); @@ -166,7 +166,7 @@ static struct iw_handler_def ath_iw_handler_def; static void ath_setup_stationkey(struct ieee80211_node *); static void ath_newassoc(struct ieee80211_node *, int); #endif -static int ath_getchannels(struct net_device *, u_int cc, +static int ath_getchannels(struct ieee80211_hw *, u_int cc, bool outdoor, bool xchanmode); #ifdef BLE static void ath_led_event(struct ath_softc *, int); @@ -178,7 +178,7 @@ static int ath_set_mac_address(struct net_device *, void *); static int ath_change_mtu(struct net_device *, int); static int ath_ioctl(struct net_device *, struct ifreq *, int); #endif -static int ath_rate_setup(struct net_device *, u_int mode); +static int ath_rate_setup(struct ieee80211_hw *, u_int mode); static void ath_setcurmode(struct ath_softc *, unsigned int); //static int ath_rawdev_attach(struct ath_softc *); @@ -233,16 +233,16 @@ enum { ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ ATH_DEBUG_ANY = 0xffffffff }; -#define DPRINTF(sc, _m, _fmt, ...) do { \ - if (sc->sc_debug & (_m)) \ - printk(_fmt, __VA_ARGS__); \ +#define DPRINTF(sc, _m, _fmt...) do { \ + if (sc->sc_debug & (_m)) \ + printk(_fmt); \ } while (0) #define KEYPRINTF(sc, ix, hk, mac) do { \ if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ ath_keyprint(__func__, ix, hk, mac); \ } while (0) static void ath_printrxbuf(struct ath_buf *bf, int); -static void ath_printtxbuf(struct ath_buf *bf, int); +//static void ath_printtxbuf(struct ath_buf *bf, int); #else #define IFF_DUMPPKTS(sc, _m) 0 #define DPRINTF(sc, _m, _fmt, ...) @@ -316,9 +316,9 @@ struct wlan_ng_prism2_header { }; int -ath_attach(u_int16_t devid, struct net_device *dev) +ath_attach(u_int16_t devid, struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = hw->priv; // struct ieee80211com *ic = &sc->sc_ic; struct ath_hal *ah; enum ath5k_status status; @@ -338,12 +338,12 @@ ath_attach(u_int16_t devid, struct net_device *dev) ATH_LOCK_INIT(sc); ATH_TXBUF_LOCK_INIT(sc); - tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)dev); - tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)dev); - tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)dev); - tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)dev); - tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)dev); - tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)dev); + tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)hw); /* * Attach the hal @@ -417,8 +417,7 @@ ath_attach(u_int16_t devid, struct net_device *dev) ath_outdoor = outdoor; if (xchanmode != -1) ath_xchanmode = xchanmode; - error = ath_getchannels(dev, ath_countrycode, - ath_outdoor, ath_xchanmode); + error = ath_getchannels(hw, ath_countrycode, ath_outdoor,ath_xchanmode); if (error != 0) { printk("error! but continuing anyways...\n"); //goto bad; @@ -427,11 +426,11 @@ ath_attach(u_int16_t devid, struct net_device *dev) /* * Setup rate tables for all potential media types. */ - ath_rate_setup(dev, MODE_IEEE80211A); - ath_rate_setup(dev, MODE_IEEE80211B); - ath_rate_setup(dev, MODE_IEEE80211G); - ath_rate_setup(dev, MODE_ATHEROS_TURBO); - ath_rate_setup(dev, MODE_ATHEROS_TURBOG); + ath_rate_setup(hw, MODE_IEEE80211A); + ath_rate_setup(hw, MODE_IEEE80211B); + ath_rate_setup(hw, MODE_IEEE80211G); + ath_rate_setup(hw, MODE_ATHEROS_TURBO); + ath_rate_setup(hw, MODE_ATHEROS_TURBOG); /* NB: setup here so ath_rate_update is happy */ ath_setcurmode(sc, MODE_IEEE80211A); @@ -522,11 +521,11 @@ ath_attach(u_int16_t devid, struct net_device *dev) #endif init_timer(&sc->sc_scan_ch); sc->sc_scan_ch.function = ath_next_scan; - sc->sc_scan_ch.data = (unsigned long) dev; + sc->sc_scan_ch.data = (unsigned long)hw; init_timer(&sc->sc_cal_ch); sc->sc_cal_ch.function = ath_calibrate; - sc->sc_cal_ch.data = (unsigned long) dev; + sc->sc_cal_ch.data = (unsigned long)hw; sc->sc_blinking = 0; sc->sc_ledstate = 1; @@ -661,8 +660,6 @@ ath_attach(u_int16_t devid, struct net_device *dev) sc->sc_hasveol = ath_hal_hasveol(ah); sc->sc_rxfilter = 0; - sc->sc_rawdev_enabled = 0; - sc->sc_rawdev.type = ARPHRD_IEEE80211; /* get mac address from hardware */ // ath_hal_getmac(ah, ic->ic_myaddr); BLEE @@ -735,13 +732,12 @@ bad: } int -ath_detach(struct net_device *dev) +ath_detach(struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = hw->priv; // struct ieee80211com *ic = &sc->sc_ic; - DPRINTF(sc, ATH_DEBUG_ANY, "%s: flags %x\n", __func__, dev->flags); - ath_stop(dev); + ath_stop(hw); sc->sc_invalid = 1; /* * NB: the order of these is important: @@ -774,26 +770,24 @@ ath_detach(struct net_device *dev) } void -ath_suspend(struct net_device *dev) +ath_suspend(struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; - DPRINTF(sc, ATH_DEBUG_ANY, "%s: flags %x\n", __func__, dev->flags); if (sc->sc_softled) ath5k_hw_set_gpio(ah, sc->sc_ledpin, 1); - ath_stop(dev); + ath_stop(hw); } void -ath_resume(struct net_device *dev) +ath_resume(struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; - DPRINTF(sc, ATH_DEBUG_ANY, "%s: flags %x\n", __func__, dev->flags); - ath_init(dev); + ath_init(hw); if (sc->sc_softled) { ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); ath5k_hw_set_gpio(ah, sc->sc_ledpin, 0); @@ -917,16 +911,16 @@ irqreturn_t ath_intr(int irq, void *dev_id) static void ath_fatal_tasklet(unsigned long data) { - struct net_device *dev = (struct net_device *)data; + struct ieee80211_hw *hw = (void *)data; printk(KERN_ERR "hardware error; resetting\n"); - ath_reset(dev); + ath_reset(hw); } static void -ath_radar_tasklet (unsigned long data) +ath_radar_tasklet(unsigned long data) { - struct net_device *dev = (struct net_device *)data; + struct ieee80211_hw *hw = (void *)data; #ifdef BLE struct ath_softc *sc = dev->priv; struct ieee80211com *ic = &sc->sc_ic; @@ -945,23 +939,23 @@ ath_radar_tasklet (unsigned long data) ic->ic_ibss_chan = c; ieee80211_new_state (ic, IEEE80211_S_INIT, -1); #endif - ath_init (dev); + ath_init(hw); } static void ath_rxorn_tasklet(unsigned long data) { - struct net_device *dev = (struct net_device *)data; + struct ieee80211_hw *hw = (void *)data; printk(KERN_WARNING "rx FIFO overrun; resetting\n"); - ath_reset(dev); + ath_reset(hw); } static void ath_bmiss_tasklet(unsigned long data) { #ifdef BLE - struct net_device *dev = (struct net_device *)data; + struct ieee80211_hw *dev = (void *)data; struct ath_softc *sc = dev->priv; struct ieee80211com *ic = &sc->sc_ic; @@ -1019,9 +1013,9 @@ ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) } #endif static int -ath_init(struct net_device *dev) +ath_init(struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; enum ath5k_status status; int error = 0; @@ -1034,7 +1028,7 @@ ath_init(struct net_device *dev) * Stop anything previously setup. This is safe * whether this is the first time through or not. */ - ath_stop_locked(dev); + ath_stop_locked(hw); #ifdef BLE /* * Change our interface type if we are in monitor mode. @@ -1122,14 +1116,14 @@ done: } static int -ath_stop_locked(struct net_device *dev) +ath_stop_locked(struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; -// struct ieee80211com *ic = &sc->sc_ic; +#ifdef BLE + struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; - DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u flags 0x%x\n", - __func__, sc->sc_invalid, dev->flags); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", + __func__, sc->sc_invalid); ATH_LOCK_ASSERT(sc); if (dev->flags & IFF_RUNNING) { @@ -1150,9 +1144,9 @@ ath_stop_locked(struct net_device *dev) * hardware is gone (invalid). */ // ieee80211_new_state(ic, IEEE80211_S_INIT, -1); - netif_stop_queue(dev); - if (sc->sc_rawdev_enabled) - netif_stop_queue(&sc->sc_rawdev); +// netif_stop_queue(dev); +// if (sc->sc_rawdev_enabled) +// netif_stop_queue(&sc->sc_rawdev); dev->flags &= ~IFF_RUNNING; if (!sc->sc_invalid) { @@ -1172,6 +1166,7 @@ ath_stop_locked(struct net_device *dev) sc->sc_rxlink = NULL; ath_beacon_free(sc); } +#endif return 0; } @@ -1182,13 +1177,13 @@ ath_stop_locked(struct net_device *dev) * stop is preempted). */ static int -ath_stop(struct net_device *dev) +ath_stop(struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = hw->priv; int error; ATH_LOCK(sc); - error = ath_stop_locked(dev); + error = ath_stop_locked(hw); if (error == 0 && !sc->sc_invalid) { /* * Set the chip in full sleep mode. Note that we are @@ -1228,16 +1223,16 @@ ath_stop(struct net_device *dev) * to reset or reload hardware state. */ static int -ath_reset(struct net_device *dev) +ath_reset(struct ieee80211_hw *hw) { - struct ath_softc *sc = dev->priv; -// struct ath_hal *ah = sc->sc_ah; -// struct ieee80211_channel *c; -// enum ath5k_status status; -// int opmode; +#ifdef BLE + struct ath_softc *sc = hw->priv; + struct ath_hal *ah = sc->sc_ah; + struct ieee80211_channel *c; + enum ath5k_status status; + int opmode; DPRINTF(sc, ATH_DEBUG_RESET, "%s: resetting\n", dev->name); -#ifdef BLE /* * Convert to a HAL channel description with the flags * constrained to reflect the current operating mode. @@ -1271,9 +1266,10 @@ ath_reset(struct net_device *dev) if (ic->ic_state == IEEE80211_S_RUN) netif_wake_queue(dev); /* restart xmit */ -#endif + if (sc->sc_rawdev_enabled) netif_wake_queue(&sc->sc_rawdev); +#endif return 0; } @@ -2744,14 +2740,14 @@ ath_beacon_send(struct net_device *dev) static void ath_bstuck_tasklet(unsigned long data) { - struct net_device *dev = (struct net_device *)data; - struct ath_softc *sc = dev->priv; + struct ieee80211_hw *hw = (void *)data; + struct ath_softc *sc = hw->priv; printk(KERN_WARNING "stuck beacon; resetting (bmiss count %u)\n", sc->sc_bmisscount); - ath_reset(dev); + ath_reset(hw); } - +#ifdef BLE /* * Reclaim beacon resources. */ @@ -2777,7 +2773,6 @@ ath_beacon_free(struct ath_softc *sc) // } } -#ifdef BLE /* * Configure the beacon and sleep timers. * @@ -3154,11 +3149,14 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { headroom_needed = sizeof(struct wlan_ng_prism2_header); - } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_PRISM) { + } +#ifdef BLE + else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_PRISM) { headroom_needed = sizeof(struct wlan_ng_prism2_header); } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_RADIOTAP) { headroom_needed = sizeof(struct ath_rx_radiotap_header); } +#endif /* * Check if we have enough headroom. If not, just free the skb @@ -3207,7 +3205,7 @@ ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) if (off != 0) skb_reserve(skb, sc->sc_cachelsz - off); - skb->dev = &sc->sc_dev; +// skb->dev = sc->sc_dev; bf->bf_skb = skb; bf->bf_skbaddr = bus_map_single(sc->sc_bdev, skb->data, sc->sc_rxbufsize, BUS_DMA_FROMDEVICE); @@ -3832,7 +3830,7 @@ rx_accept: skb_put(skb, len); skb->protocol = __constant_htons(ETH_P_CONTROL); - +#ifdef BLE if (sc->sc_rawdev_enabled && (sc->sc_rawdev.flags & IFF_UP)) { struct sk_buff *skb2; @@ -3841,7 +3839,7 @@ rx_accept: ath_rx_capture(&sc->sc_rawdev, ds, skb2); } } - +#endif if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { /* * Monitor mode: discard anything shorter than @@ -4019,7 +4017,7 @@ ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) } if (qnum >= N(sc->sc_txq)) { printk("%s: hal qnum %u out of range, max %u!\n", - sc->sc_dev.name, qnum, (unsigned int) N(sc->sc_txq)); + "BLE"/*sc->sc_dev->name*/, qnum, (unsigned int) N(sc->sc_txq)); ath5k_hw_release_tx_queue(ah, qnum); return NULL; } @@ -4842,7 +4840,6 @@ ath_tx_timeout(struct net_device *dev) sc->sc_stats.ast_watchdog++; ath_init(dev); } -#endif static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) @@ -4923,13 +4920,9 @@ ath_draintxq(struct ath_softc *sc) ath_tx_stopdma(sc, &sc->sc_txq[i]); } } - sc->sc_dev.trans_start = jiffies; - sc->sc_rawdev.trans_start = jiffies; - - netif_start_queue(&sc->sc_dev); // TODO: needed here? - if (sc->sc_rawdev_enabled) - netif_start_queue(&sc->sc_rawdev); +// sc->sc_dev->trans_start = jiffies; +// netif_start_queue(sc->sc_dev); // TODO: needed here? for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) { if (ATH_TXQ_SETUP(sc, i)) ath_tx_draintxq(sc, &sc->sc_txq[i]); @@ -4972,7 +4965,7 @@ ath_stoprecv(struct ath_softc *sc) sc->sc_rxlink = NULL; /* just in case */ #undef PA2DESC } - +#endif /* * Enable the receive h/w following a reset. */ @@ -5159,8 +5152,8 @@ ath_next_scan(unsigned long arg) static void ath_calibrate(unsigned long arg) { - struct net_device *dev = (struct net_device *) arg; - struct ath_softc *sc = dev->priv; + struct ieee80211_hw *hw = (void *)arg; + struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; sc->sc_stats.ast_per_cal++; @@ -5174,9 +5167,8 @@ ath_calibrate(unsigned long arg) * to load new gain values. */ sc->sc_stats.ast_per_rfgain++; - DPRINTF(sc, ATH_DEBUG_RESET, "%s: calibration, resetting\n", - dev->name); - ath_reset(dev); + DPRINTF(sc, ATH_DEBUG_RESET, "calibration, resetting\n"); + ath_reset(hw); } if (!ath5k_hw_phy_calibrate(ah, &sc->sc_curchan)) { DPRINTF(sc, ATH_DEBUG_ANY, @@ -5390,10 +5382,10 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) } #endif static int -ath_getchannels(struct net_device *dev, u_int cc, +ath_getchannels(struct ieee80211_hw *hw, u_int cc, bool outdoor, bool xchanmode) { - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; struct ath5k_channel *chans; int i, ix; @@ -5521,7 +5513,7 @@ ath_update_txpow(struct ath_softc *sc) } static int -ath_rate_setup(struct net_device *dev, u_int mode) +ath_rate_setup(struct ieee80211_hw *dev, u_int mode) { struct ath_softc *sc = dev->priv; struct ath_hal *ah = sc->sc_ah; @@ -5726,7 +5718,7 @@ ath_printrxbuf(struct ath_buf *bf, int done) ds->ds_hw[0], ds->ds_hw[1], !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); } - +#ifdef BLE static void ath_printtxbuf(struct ath_buf *bf, int done) { @@ -5739,6 +5731,7 @@ ath_printtxbuf(struct ath_buf *bf, int done) ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); } +#endif #endif /* AR_DEBUG */ #ifdef BLE /* @@ -6352,7 +6345,7 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, #endif case ATH_RXFILTER: sc->sc_rxfilter = val; - ath_reset(&sc->sc_dev); +// ath_reset(sc->sc_dev); break; case ATH_RADARSIM: tasklet_schedule(&sc->sc_radartq); @@ -6417,6 +6410,7 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, case ATH_BINTVAL: // val = (sc->sc_ic).ic_lintval; break; +#ifdef BLE case ATH_RAWDEV: val = sc->sc_rawdev_enabled; break; @@ -6429,6 +6423,7 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, val = 0; } break; +#endif case ATH_RXFILTER: val = sc->sc_rxfilter; break; @@ -6585,7 +6580,7 @@ ath_dynamic_sysctl_register(struct ath_softc *sc) sc->sc_sysctls[0].child = &sc->sc_sysctls[2]; /* [1] is NULL terminator */ sc->sc_sysctls[2].ctl_name = CTL_AUTO; - sc->sc_sysctls[2].procname = sc->sc_dev.name; + sc->sc_sysctls[2].procname = "BLE";//sc->sc_dev->name; sc->sc_sysctls[2].mode = 0555; sc->sc_sysctls[2].child = &sc->sc_sysctls[4]; /* [3] is NULL terminator */ diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index ad78e30..c9c4a4f 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -37,11 +37,6 @@ #include "if_athvar.h" #include "if_ath_pci.h" -/* support for module parameters */ -static char *ifname = "ath"; -module_param(ifname, charp, 0); -MODULE_PARM_DESC(ifname, "Interface name prefix (default: ath)"); - /* * User a static table of PCI id's for now. While this is the * "new way" to do things, we may want to switch back to having @@ -75,12 +70,30 @@ void bus_read_cachesize(struct ath_softc *sc, u8 *csz) pci_read_config_byte(sc->sc_bdev, PCI_CACHE_LINE_SIZE, csz); } +static struct ieee80211_ops ath_hw_ops = { +/* .tx = d_tx, + .open = d_open, + .stop = d_stop, + .add_interface = d_add_interface, + .remove_interface = d_remove_interface, + .config = d_config, + .config_interface = d_config_interface, + .set_key = d_set_key, + .get_stats = d_get_stats, + .get_tx_stats = d_get_tx_stats, + .conf_tx = d_conf_tx, + .get_tsf = d_get_tsf, + .reset_tsf = d_reset_tsf, + .beacon_update = d_beacon_update, + .hw_scan = d_hw_scan*/ +}; + static int __devinit ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { void __iomem *mem; struct ath_softc *sc; - struct net_device *dev; + struct ieee80211_hw *hw; const char *athname; int retval; u32 val; @@ -146,55 +159,46 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, goto err_reg; } - sc = kzalloc(sizeof(struct ath_softc), GFP_KERNEL); - if (sc == NULL) { - dev_err(&pdev->dev, "no memory for device state\n"); + hw = ieee80211_alloc_hw(sizeof(*sc), &ath_hw_ops); + if (hw == NULL) { + dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); goto err_map; } + SET_IEEE80211_DEV(hw, &pdev->dev); + sc = hw->priv; + sc->hw = hw; + /* * Mark the device as detached to avoid processing * interrupts until setup is complete. */ sc->sc_invalid = 1; - - dev = &sc->sc_dev; - - /* use variable interface name prefix */ - strncpy(dev->name, ifname, IFNAMSIZ - sizeof("%d") - 1); - strncat(dev->name, "%d", sizeof("%d")); - - dev->irq = pdev->irq; - dev->priv = sc; sc->sc_iobase = mem; - - SET_MODULE_OWNER(dev); - SET_NETDEV_DEV(dev, &pdev->dev); - sc->sc_bdev = pdev; - pci_set_drvdata(pdev, dev); + pci_set_drvdata(pdev, hw); - if (request_irq(dev->irq, ath_intr, IRQF_SHARED, dev->name, dev)) { + if (request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc)) { dev_err(&pdev->dev, "request_irq failed\n"); goto err_free; } - if (ath_attach(id->device, dev) != 0) + if (ath_attach(id->device, hw) != 0) goto err_irq; athname = ath_hal_probe(id->vendor, id->device); dev_info(&pdev->dev, "%s: irq=%d\n", - athname ? athname : "Atheros ???", dev->irq); + athname ? athname : "Atheros ???", pdev->irq); /* ready to process interrupts */ sc->sc_invalid = 0; return 0; err_irq: - free_irq(dev->irq, dev); + free_irq(pdev->irq, sc); err_free: - kfree(sc); + ieee80211_free_hw(hw); err_map: pci_iounmap(pdev, mem); err_reg: @@ -207,15 +211,15 @@ err: static void __devexit ath_pci_remove(struct pci_dev *pdev) { - struct net_device *dev = pci_get_drvdata(pdev); - struct ath_softc *sc = dev->priv; + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; - ath_detach(dev); - free_irq(dev->irq, dev); + ath_detach(hw); + free_irq(pdev->irq, sc); pci_iounmap(pdev, sc->sc_iobase); pci_release_region(pdev, 0); pci_disable_device(pdev); - free_netdev(dev); + ieee80211_free_hw(hw); } #ifdef CONFIG_PM diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 0d3f1d2..c9685eb 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -177,16 +177,12 @@ struct ath_txq { } while (0) struct ath_softc { - struct net_device sc_dev; /* NB: must be first */ void __iomem *sc_iobase; /* address of the device */ - struct net_device sc_rawdev; /* live monitor device */ struct semaphore sc_lock; /* dev-level lock */ struct net_device_stats sc_devstats; /* device statistics */ struct ath_stats sc_stats; /* private statistics */ - struct ieee80211_hw sc_hw; /* IEEE 802.11 common */ -#ifdef BLE - struct ieee80211com sc_ic; /* IEEE 802.11 common */ -#endif + struct ieee80211_hw *hw; /* IEEE 802.11 common */ + enum ieee80211_if_types sc_opmode; int sc_regdomain; int sc_countrycode; @@ -220,8 +216,7 @@ struct ath_softc { sc_blinking: 1, /* LED blink operation active */ sc_endblink: 1, /* finish LED blink operation */ sc_mcastkey: 1, /* mcast key cache search */ - sc_hasclrkey:1, /* CLR key supported */ - sc_rawdev_enabled : 1; /* enable sc_rawdev */ + sc_hasclrkey:1; /* CLR key supported */ /* rate tables */ const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; const struct ath5k_rate_table *sc_currates; /* current rate table */ @@ -329,10 +324,10 @@ struct ath_softc { #define ATH_TXBUF_LOCK_ASSERT(_sc) \ KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), ("txbuf not locked!")) -int ath_attach(u16, struct net_device *); -int ath_detach(struct net_device *); -void ath_resume(struct net_device *); -void ath_suspend(struct net_device *); +int ath_attach(u16, struct ieee80211_hw *); +int ath_detach(struct ieee80211_hw *); +void ath_resume(struct ieee80211_hw *); +void ath_suspend(struct ieee80211_hw *); /* *Port r1752 - Starting linux kernel v2.6.19 and later *interrupt handlers are not passed. commit fd06b08583b552475389544b3cf2f7f8cdaa5e85 Author: Jiri Slaby Date: Wed Jun 20 23:47:17 2007 +0200 move some stuff to pci (it would be the base) diff --git a/Makefile b/Makefile index cbd7dfa..e71cfe3 100644 --- a/Makefile +++ b/Makefile @@ -3,8 +3,8 @@ KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) EXTRA_CFLAGS += -I$(src)/openhal -ath5k-objs := ath/if_ath.o ath/if_ath_pci.o openhal/ath5k_hw.o \ - openhal/ieee80211_regdomain.o #ath/radar.o +ath5k-objs := ath/if_ath_pci.o openhal/ath5k_hw.o \ + openhal/ieee80211_regdomain.o #ath/radar.o #ath/if_ath.o obj-m += ath5k.o diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c9c4a4f..fbdeb1e 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -37,6 +37,43 @@ #include "if_athvar.h" #include "if_ath_pci.h" +#define DPRINTF(sc, _m, _fmt...) do { \ + if (sc->sc_debug & (_m)) \ + printk(_fmt); \ +} while (0) +enum { + ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ + ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ + ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ + ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ + ATH_DEBUG_RATE = 0x00000010, /* rate control */ + ATH_DEBUG_RESET = 0x00000020, /* reset processing */ + ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ + ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ + ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ + ATH_DEBUG_INTR = 0x00001000, /* ISR */ + ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ + ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ + ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ + ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ + ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ + ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ + ATH_DEBUG_NODE = 0x00080000, /* node management */ + ATH_DEBUG_LED = 0x00100000, /* led management */ + ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ + ATH_DEBUG_ANY = 0xffffffff +}; + +static int countrycode = CTRY_DEFAULT; +static int outdoor = true; +static int xchanmode = true; +module_param(countrycode, int, 0); +MODULE_PARM_DESC(countrycode, "Override default country code"); +module_param(outdoor, int, 0); +MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); +module_param(xchanmode, int, 0); +MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); + /* * User a static table of PCI id's for now. While this is the * "new way" to do things, we may want to switch back to having @@ -64,12 +101,6 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = { }; MODULE_DEVICE_TABLE(pci, ath_pci_id_table); -/* return bus cachesize in 4B word units */ -void bus_read_cachesize(struct ath_softc *sc, u8 *csz) -{ - pci_read_config_byte(sc->sc_bdev, PCI_CACHE_LINE_SIZE, csz); -} - static struct ieee80211_ops ath_hw_ops = { /* .tx = d_tx, .open = d_open, @@ -88,6 +119,587 @@ static struct ieee80211_ops ath_hw_ops = { .hw_scan = d_hw_scan*/ }; +/* + * Read from a device register + */ +static inline u32 ath_hw_reg_read(struct ath_hal *hw, u16 reg) +{ + return readl(hw->ah_sh + reg); +} + +/* + * Write to a device register + */ +static inline void ath_hw_reg_write(struct ath_hal *hw, u32 val, u16 reg) +{ + writel(val, hw->ah_sh + reg); +} + +#define ATH_HW_IRQ_PENDING 0x4008 +# define ATH_HW_IRQ_PENDING_FALSE 0 +# define ATH_HW_IRQ_PENDING_TRUE 1 + +/* + * Check if there is an interrupt waiting to be processed. + * Return 1 if there is an interrupt for us, or 0 if there is none or if + * the device has been removed. + */ +static inline int ath_hw_irq_pending(struct ath_hal *hw) +{ + return ath_hw_reg_read(hw, ATH_HW_IRQ_PENDING) == ATH_HW_IRQ_PENDING_TRUE; +} + +/* + * Interrupt handler. Most of the actual processing is deferred. + */ +static irqreturn_t ath_intr(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct ath_softc *sc = dev->priv; + struct ath_hal *ah = sc->sc_ah; + enum ath5k_int status; + int needmark; + + if (sc->sc_invalid) { + /* + * The hardware is not ready/present, don't touch anything. + * Note this can happen early on if the IRQ is shared. + */ + DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); + return IRQ_NONE; + } + if (!ath_hw_irq_pending(ah)) /* shared irq, not for us */ + return IRQ_NONE; + if ((dev->flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", + __func__, dev->flags); + ath5k_hw_get_isr(ah, &status); /* clear ISR */ + ath5k_hw_set_intr(ah, 0); /* disable further intr's */ + return IRQ_HANDLED; + } + needmark = 0; + + do { + /* + * Figure out the reason(s) for the interrupt. Note + * that the hal returns a pseudo-ISR that may include + * bits we haven't explicitly enabled so we mask the + * value to insure we only process bits we requested. + */ + ath5k_hw_get_isr(ah, &status); /* NB: clears ISR too */ + DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); + status &= sc->sc_imask; /* discard unasked for bits */ + if (status & AR5K_INT_FATAL) { + /* + * Fatal errors are unrecoverable. Typically + * these are caused by DMA errors. Unfortunately + * the exact reason is not (presently) returned + * by the hal. + */ + sc->sc_stats.ast_hardware++; + ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ + tasklet_schedule(&sc->sc_fataltq); + } else if (status & AR5K_INT_RXORN) { + sc->sc_stats.ast_rxorn++; + ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ + tasklet_schedule(&sc->sc_rxorntq); + } else { + if (status & AR5K_INT_SWBA) { + /* + * Software beacon alert--time to send a beacon. + * Handle beacon transmission directly; deferring + * this is too slow to meet timing constraints + * under load. + */ +// ath_beacon_send(dev); + } + if (status & AR5K_INT_RXEOL) { + /* + * NB: the hardware should re-read the link when + * RXE bit is written, but it doesn't work at + * least on older hardware revs. + */ + sc->sc_stats.ast_rxeol++; + sc->sc_rxlink = NULL; + } + if (status & AR5K_INT_TXURN) { + sc->sc_stats.ast_txurn++; + /* bump tx trigger level */ + ath5k_hw_update_tx_triglevel(ah, true); + } + if (status & AR5K_INT_RX) + tasklet_schedule(&sc->sc_rxtq); + if (status & AR5K_INT_TX) + tasklet_schedule(&sc->sc_txtq); + if (status & AR5K_INT_BMISS) { + sc->sc_stats.ast_bmiss++; + tasklet_schedule(&sc->sc_bmisstq); + } + if (status & AR5K_INT_MIB) { + sc->sc_stats.ast_mib++; + /* + * Disable interrupts until we service the MIB + * interrupt; otherwise it will continue to fire. + */ + ath5k_hw_set_intr(ah, 0); + /* + * Let the hal handle the event. We assume it will + * clear whatever condition caused the interrupt. + */ +#ifdef BLE + ath5k_hw_proc_mib_event(ah, + &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); +#endif + ath5k_hw_set_intr(ah, sc->sc_imask); + } + } + } while (ath5k_hw_is_intr_pending(ah)); + + return IRQ_HANDLED; +} + +static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hal *ah; + enum ath5k_status status; + int error = 0, i; + u8 csz; + + DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); + + /* + * Cache line size is used to size and align various + * structures used to communicate with the hardware. + */ + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); + /* XXX assert csz is non-zero */ + sc->sc_cachelsz = csz << 2; /* convert to bytes */ + + ATH_LOCK_INIT(sc); + ATH_TXBUF_LOCK_INIT(sc); + +/* tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)hw);*/ + + /* + * Attach the hal + */ + ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase, &status); + if (ah == NULL) { + error = ENXIO; + goto bad; + } + sc->sc_ah = ah; + + /* + * Check if the MAC has multi-rate retry support. + * We do this by trying to setup a fake extended + * descriptor. MAC's that don't have support will + * return false w/o doing anything. MAC's that do + * support it will return true w/o doing anything. + */ + sc->sc_mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); + + /* + * Check if the device has hardware counters for PHY + * errors. If so we need to enable the MIB interrupt + * so we can act on stat triggers. + */ + if (ath_hal_hwphycounters(ah)) + sc->sc_needmib = 1; + + /* + * Get the hardware key cache size. + */ + sc->sc_keymax = ath5k_hw_get_keycache_size(ah); + if (sc->sc_keymax > ATH_KEYMAX) { + printk(KERN_WARNING "Warning, using only %u of %u key cache " + "slots\n", ATH_KEYMAX, sc->sc_keymax); + sc->sc_keymax = ATH_KEYMAX; + } + + /* + * Reset the key cache since some parts do not + * reset the contents on initial power up. + */ + for (i = 0; i < sc->sc_keymax; i++) + ath5k_hw_reset_key(ah, i); + /* + * Mark key cache slots associated with global keys + * as in use. If we knew TKIP was not to be used we + * could leave the +32, +64, and +32+64 slots free. + * XXX only for splitmic. + */ +#ifdef BLE + for (i = 0; i < IEEE80211_WEP_NKID; i++) { + setbit(sc->sc_keymap, i); + setbit(sc->sc_keymap, i+32); + setbit(sc->sc_keymap, i+64); + setbit(sc->sc_keymap, i+32+64); + } + + /* + * Collect the channel list using the default country + * code and including outdoor channels. The 802.11 layer + * is resposible for filtering this list based on settings + * like the phy mode. + */ + error = ath_getchannels(hw, countrycode, outdoor, xchanmode); + if (error != 0) { + printk("error! but continuing anyways...\n"); + //goto bad; + } + + /* + * Setup rate tables for all potential media types. + */ + ath_rate_setup(hw, MODE_IEEE80211A); + ath_rate_setup(hw, MODE_IEEE80211B); + ath_rate_setup(hw, MODE_IEEE80211G); + ath_rate_setup(hw, MODE_ATHEROS_TURBO); + ath_rate_setup(hw, MODE_ATHEROS_TURBOG); + /* NB: setup here so ath_rate_update is happy */ + ath_setcurmode(sc, MODE_IEEE80211A); + + /* + * Allocate tx+rx descriptors and populate the lists. + */ + error = ath_desc_alloc(sc); + if (error != 0) { + printk(KERN_ERR "failed to allocate descriptors: %d\n", error); + goto bad; + } + + /* + * Allocate hardware transmit queues: one queue for + * beacon frames and one data queue for each QoS + * priority. Note that the hal handles reseting + * these queues at the needed time. + * + * XXX PS-Poll + */ + sc->sc_bhalq = ath_beaconq_setup(ah); + if (sc->sc_bhalq == (u_int) -1) { + printk(KERN_ERR "unable to setup a beacon xmit queue!\n"); + goto bad2; + } + sc->sc_cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); + if (sc->sc_cabq == NULL) { + printk(KERN_ERR "unable to setup CAB xmit queue!\n"); + error = EIO; + goto bad2; + } +#endif +#ifdef BLE + /* NB: insure BK queue is the lowest priority h/w queue */ + if (!ath_tx_setup(sc, WME_AC_BK, AR5K_WME_AC_BK)) { + printk(KERN_ERR "unable to setup xmit queue for %s traffic!\n", + ieee80211_wme_acnames[WME_AC_BK]); + error = EIO; + goto bad2; + } + if (!ath_tx_setup(sc, WME_AC_BE, AR5K_WME_AC_BE) || + !ath_tx_setup(sc, WME_AC_VI, AR5K_WME_AC_VI) || + !ath_tx_setup(sc, WME_AC_VO, AR5K_WME_AC_VO)) { + /* + * Not enough hardware tx queues to properly do WME; + * just punt and assign them all to the same h/w queue. + * We could do a better job of this if, for example, + * we allocate queues when we switch from station to + * AP mode. + */ + if (sc->sc_ac2q[WME_AC_VI] != NULL) + ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); + if (sc->sc_ac2q[WME_AC_BE] != NULL) + ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); + sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; + sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; + sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; + } + + /* + * Special case certain configurations. Note the + * CAB queue is handled by these specially so don't + * include them when checking the txq setup mask. + */ + switch (sc->sc_txqsetup &~ (1<sc_cabq->axq_qnum)) { + case 0x01: + ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet_q0, dev); + break; + case 0x0f: + ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet_q0123, dev); + break; + default: + ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet, dev); + break; + } + + /* + * Setup rate control. Some rate control modules + * call back to change the anntena state so expose + * the necessary entry points. + * XXX maybe belongs in struct ath_ratectrl? + */ + sc->sc_setdefantenna = ath_setdefantenna; + sc->sc_rc = ath_rate_attach(sc); + if (sc->sc_rc == NULL) { + error = EIO; + goto bad2; + } + + init_timer(&sc->sc_scan_ch); + sc->sc_scan_ch.function = ath_next_scan; + sc->sc_scan_ch.data = (unsigned long)hw; + + init_timer(&sc->sc_cal_ch); + sc->sc_cal_ch.function = ath_calibrate; + sc->sc_cal_ch.data = (unsigned long)hw; + + sc->sc_blinking = 0; + sc->sc_ledstate = 1; + sc->sc_ledon = 0; /* low true */ + sc->sc_ledidle = (2700*HZ)/1000; /* 2.7sec */ + + init_timer(&sc->sc_ledtimer); + sc->sc_ledtimer.function = ath_led_off; + sc->sc_ledtimer.data = (unsigned long) sc; + /* + * Auto-enable soft led processing for IBM cards and for + * 5211 minipci cards. Users can also manually enable/disable + * support with a sysctl. + */ + sc->sc_softled = (devid == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || + devid == PCI_DEVICE_ID_ATHEROS_AR5211); + if (sc->sc_softled) { + ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); + ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); + } + + ether_setup(dev); + dev->open = ath_init; + dev->stop = ath_stop; + dev->hard_start_xmit = ath_start; + dev->tx_timeout = ath_tx_timeout; + dev->watchdog_timeo = 5 * HZ; /* XXX */ + dev->set_multicast_list = ath_mode_init; + dev->do_ioctl = ath_ioctl; + dev->get_stats = ath_getstats; + dev->set_mac_address = ath_set_mac_address; + dev->change_mtu = &ath_change_mtu; + dev->tx_queue_len = ATH_TXBUF; /* TODO? 1 for mgmt frame */ +/*get_wireless_stats moved from net_device to iw_handler_def*/ +# if IW_HANDLER_VERSION < 7 + dev->get_wireless_stats = ath_iw_getstats; +# endif + ieee80211_ioctl_iwsetup(&ath_iw_handler_def); + dev->wireless_handlers = &ath_iw_handler_def; +#if IEEE80211_VLAN_TAG_USED + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; + dev->vlan_rx_register = ath_vlan_register; + dev->vlan_rx_kill_vid = ath_vlan_kill_vid; +#endif /* IEEE80211_VLAN_TAG_USED */ + ic->ic_dev = dev; + ic->ic_devstats = &sc->sc_devstats; + ic->ic_init = ath_init; + ic->ic_reset = ath_reset; + ic->ic_newassoc = ath_newassoc; + ic->ic_updateslot = ath_updateslot; + ic->ic_wme.wme_update = ath_wme_update; + /* XXX not right but it's not used anywhere important */ + ic->ic_phytype = MODULATION_OFDM; + ic->ic_opmode = IEEE80211_M_STA; + ic->ic_caps = + IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ + | IEEE80211_C_AHDEMO /* adhoc demo (pseudo_ibss) mode */ + | IEEE80211_C_HOSTAP /* hostap mode */ + | IEEE80211_C_MONITOR /* monitor mode */ + | IEEE80211_C_SHPREAMBLE /* short preamble supported */ + | IEEE80211_C_SHSLOT /* short slot time supported */ + | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ + ; + /* + * initialize management queue + */ + skb_queue_head_init(&ic->ic_mgtq); + + /* + * Query the hal to figure out h/w crypto support. + */ + if (ath_hal_ciphersupported(ah, AR5K_CIPHER_WEP)) + ic->ic_caps |= IEEE80211_C_WEP; + if (ath_hal_ciphersupported(ah, AR5K_CIPHER_AES_OCB)) + ic->ic_caps |= IEEE80211_C_AES; + if (ath_hal_ciphersupported(ah, AR5K_CIPHER_AES_CCM)) + ic->ic_caps |= IEEE80211_C_AES_CCM; + if (ath_hal_ciphersupported(ah, AR5K_CIPHER_CKIP)) + ic->ic_caps |= IEEE80211_C_CKIP; + if (ath_hal_ciphersupported(ah, AR5K_CIPHER_TKIP)) { + ic->ic_caps |= IEEE80211_C_TKIP; + /* + * Check if h/w does the MIC and/or whether the + * separate key cache entries are required to + * handle both tx+rx MIC keys. + */ + if (ath_hal_ciphersupported(ah, AR5K_CIPHER_MIC)) + ic->ic_caps |= IEEE80211_C_TKIPMIC; + if (ath_hal_tkipsplit(ah)) + sc->sc_splitmic = 1; + } + sc->sc_hasclrkey = ath_hal_ciphersupported(ah, AR5K_CIPHER_CLR); + sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); + /* + * TPC support can be done either with a global cap or + * per-packet support. The latter is not available on + * all parts. We're a bit pedantic here as all parts + * support a global cap. + */ + if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) + ic->ic_caps |= IEEE80211_C_TXPMGT; + + /* + * Mark WME capability only if we have sufficient + * hardware queues to do proper priority scheduling. + */ + if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) + ic->ic_caps |= IEEE80211_C_WME; + /* + * Check for misc other capabilities. + */ + if (ath_hal_hasbursting(ah)) + ic->ic_caps |= IEEE80211_C_BURST; + + /* + * Indicate we need the 802.11 header padded to a + * 32-bit boundary for 4-address and QoS frames. + */ + ic->ic_flags |= IEEE80211_F_DATAPAD; +#endif + + /* + * Query the hal about antenna support. + */ + sc->sc_defant = ath5k_hw_get_def_antenna(ah); + + /* + * Not all chips have the VEOL support we want to + * use with IBSS beacons; check here for it. + */ + sc->sc_hasveol = ath_hal_hasveol(ah); + + sc->sc_rxfilter = 0; + + /* get mac address from hardware */ +// ath_hal_getmac(ah, ic->ic_myaddr); BLEE +// IEEE80211_ADDR_COPY(dev->dev_addr, ic->ic_myaddr); +#ifdef BLE + /* call MI attach routine. */ + ieee80211_ifattach(ic); + /* override default methods */ + ic->ic_node_alloc = ath_node_alloc; + sc->sc_node_free = ic->ic_node_free; + ic->ic_node_free = ath_node_free; + ic->ic_node_getrssi = ath_node_getrssi; + sc->sc_recv_mgmt = ic->ic_recv_mgmt; + ic->ic_recv_mgmt = ath_recv_mgmt; + sc->sc_newstate = ic->ic_newstate; + ic->ic_newstate = ath_newstate; + ic->ic_crypto.cs_key_alloc = ath_key_alloc; + ic->ic_crypto.cs_key_delete = ath_key_delete; + ic->ic_crypto.cs_key_set = ath_key_set; + ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; + ic->ic_crypto.cs_key_update_end = ath_key_update_end; + + radar_init(ic); +#endif +#if 0 + /* complete initialization */ + ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); + + if (register_netdev(dev)) { + printk(KERN_ERR "%s: unable to register device\n", dev->name); + goto bad3; + } + +#endif + /* + * Attach dynamic MIB vars and announce support + * now that we have a device name with unit number. + */ +// ath_dynamic_sysctl_register(sc); +// ath_rate_dynamic_sysctl_register(sc); +// ath_announce(sc); + + return 0; +#ifdef BLE +//bad3: +// ieee80211_ifdetach(ic); +// ath_rate_detach(sc->sc_rc); +bad2: + if (sc->sc_txq[WME_AC_BK].axq_qnum != (u_int) -1) { + ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_BK]); + } + if (sc->sc_txq[WME_AC_BE].axq_qnum != (u_int) -1) { + ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_BE]); + } + if (sc->sc_txq[WME_AC_VI].axq_qnum != (u_int) -1) { + ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VI]); + } + if (sc->sc_txq[WME_AC_VO].axq_qnum != (u_int) -1) { + ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VO]); + } + ath_tx_cleanup(sc); + ath_desc_free(sc); +#endif +bad: + if (ah) { + ath5k_hw_detach(ah); + } + sc->sc_invalid = 1; + return error; +} + +static int ath_detach(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; +// struct ieee80211com *ic = &sc->sc_ic; + +// ath_stop(hw); + sc->sc_invalid = 1; + /* + * NB: the order of these is important: + * o call the 802.11 layer before detaching the hal to + * insure callbacks into the driver to delete global + * key cache entries can be handled + * o reclaim the tx queue data structures after calling + * the 802.11 layer as we'll get called back to reclaim + * node state and potentially want to use them + * o to cleanup the tx queues the hal is called, so detach + * it last + * Other than that, it's straightforward... + */ +// ieee80211_ifdetach(ic); +// ath_rate_detach(sc->sc_rc); +// ath_desc_free(sc); +// ath_tx_cleanup(sc); + ath5k_hw_detach(sc->sc_ah); + + /* + * NB: can't reclaim these until after ieee80211_ifdetach + * returns because we'll get called back to reclaim node + * state and potentially want to use them. + */ +// ath_dynamic_sysctl_unregister(sc); +// ath_rawdev_detach(sc); +// unregister_netdev(dev); + + return 0; +} + static int __devinit ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -184,7 +796,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, goto err_free; } - if (ath_attach(id->device, hw) != 0) + if (ath_attach(pdev, hw) != 0) goto err_irq; athname = ath_hal_probe(id->vendor, id->device); @@ -225,9 +837,13 @@ static void __devexit ath_pci_remove(struct pci_dev *pdev) #ifdef CONFIG_PM static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) { - struct net_device *dev = pci_get_drvdata(pdev); + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; - ath_suspend(dev); + if (sc->sc_softled) + ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, 1); + +// ath_stop(hw); pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, PCI_D3hot); @@ -237,7 +853,8 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) static int ath_pci_resume(struct pci_dev *pdev) { - struct net_device *dev = pci_get_drvdata(pdev); + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; u32 val; int err; @@ -260,7 +877,12 @@ static int ath_pci_resume(struct pci_dev *pdev) pci_read_config_dword(pdev, 0x40, &val); if ((val & 0x0000ff00) != 0) pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); - ath_resume(dev); + +// ath_init(hw); + if (sc->sc_softled) { + ath5k_hw_set_gpio_output(sc->sc_ah, sc->sc_ledpin); + ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, 0); + } return 0; } @@ -279,27 +901,94 @@ static struct pci_driver ath_pci_drv_id = { }; /* - * Module glue. + * Static (i.e. global) sysctls. Note that the hal sysctls + * are located under ours by sharing the setting for DEV_ATH. */ -static char version[] = ATH_PCI_VERSION " (EXPERIMENTAL)"; -static char dev_info[] = "ath_pci"; - -int ath_ioctl_ethtool(struct ath_softc *sc, int cmd, void __user *addr) -{ - struct ethtool_drvinfo info; +enum { + DEV_ATH = 9, /* XXX known by hal */ +}; - if (cmd != ETHTOOL_GDRVINFO) - return -EOPNOTSUPP; - memset(&info, 0, sizeof(info)); - info.cmd = cmd; - strncpy(info.driver, dev_info, sizeof(info.driver)-1); - strncpy(info.version, version, sizeof(info.version)-1); +#define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ - /* include the device name so later versions of kudzu DTRT */ - strncpy(info.bus_info, pci_name(sc->sc_bdev), sizeof(info.bus_info)-1); +static ctl_table ath_static_sysctls[] = { +#ifdef AR_DEBUG + { .ctl_name = CTL_AUTO, + .procname = "debug", + .mode = 0644, + .data = &ath_debug, + .maxlen = sizeof(ath_debug), + .proc_handler = proc_dointvec + }, +#endif + { .ctl_name = CTL_AUTO, + .procname = "countrycode", + .mode = 0444, + .data = &countrycode, + .maxlen = sizeof(countrycode), + .proc_handler = proc_dointvec + }, +/* { .ctl_name = CTL_AUTO, + .procname = "regdomain", + .mode = 0444, + .data = &ath_regdomain, + .maxlen = sizeof(ath_regdomain), + .proc_handler = proc_dointvec + },*/ + { .ctl_name = CTL_AUTO, + .procname = "outdoor", + .mode = 0444, + .data = &outdoor, + .maxlen = sizeof(outdoor), + .proc_handler = proc_dointvec + }, + { .ctl_name = CTL_AUTO, + .procname = "xchanmode", + .mode = 0444, + .data = &xchanmode, + .maxlen = sizeof(xchanmode), + .proc_handler = proc_dointvec + }, +/* { .ctl_name = CTL_AUTO, + .procname = "dwelltime", + .mode = 0644, + .data = &ath_dwelltime, + .maxlen = sizeof(ath_dwelltime), + .extra1 = &mindwelltime, + .extra2 = &maxint, + .proc_handler = proc_dointvec_minmax + }, + { .ctl_name = CTL_AUTO, + .procname = "calibrate", + .mode = 0644, + .data = &ath_calinterval, + .maxlen = sizeof(ath_calinterval), + .extra1 = &mincalibrate, + .extra2 = &maxint, + .proc_handler = proc_dointvec_minmax + },*/ + { 0 } +}; +static ctl_table ath_ath_table[] = { + { .ctl_name = DEV_ATH, + .procname = "ath", + .mode = 0555, + .child = ath_static_sysctls + }, { 0 } +}; +static ctl_table ath_root_table[] = { + { .ctl_name = CTL_DEV, + .procname = "dev", + .mode = 0555, + .child = ath_ath_table + }, { 0 } +}; +static struct ctl_table_header *ath_sysctl_header; - return copy_to_user(addr, &info, sizeof(info)) ? -EFAULT : 0; -} +/* + * Module glue. + */ +static char version[] = ATH_PCI_VERSION " (EXPERIMENTAL)"; +static char dev_info[] = "ath_pci"; static int __init init_ath_pci(void) { @@ -312,14 +1001,15 @@ static int __init init_ath_pci(void) printk(KERN_ERR "ath_pci: can't register pci driver\n"); return ret; } - ath_sysctl_register(); + ath_sysctl_header = register_sysctl_table(ath_root_table); return 0; } static void __exit exit_ath_pci(void) { - ath_sysctl_unregister(); + if (ath_sysctl_header) + unregister_sysctl_table(ath_sysctl_header); pci_unregister_driver(&ath_pci_drv_id); printk(KERN_INFO "%s: driver unloaded\n", dev_info); diff --git a/ath/if_athvar.h b/ath/if_athvar.h index c9685eb..2a5aedc 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -324,16 +324,6 @@ struct ath_softc { #define ATH_TXBUF_LOCK_ASSERT(_sc) \ KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), ("txbuf not locked!")) -int ath_attach(u16, struct ieee80211_hw *); -int ath_detach(struct ieee80211_hw *); -void ath_resume(struct ieee80211_hw *); -void ath_suspend(struct ieee80211_hw *); -/* - *Port r1752 - Starting linux kernel v2.6.19 and later - *interrupt handlers are not passed. - */ -irqreturn_t ath_intr(int, void *); -void bus_read_cachesize(struct ath_softc *, u8 *); int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); void ath_sysctl_unregister(void); commit 9f4324c2d79b28d387df32a25fbd192e7ca160cb Author: Jiri Slaby Date: Thu Jun 21 10:52:31 2007 +0200 write byte to pci 0x41, not anded dword diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index fbdeb1e..dc414f1 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -708,7 +708,6 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, struct ieee80211_hw *hw; const char *athname; int retval; - u32 val; u8 csz; retval = pci_enable_device(pdev); @@ -752,12 +751,8 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, /* * Disable the RETRY_TIMEOUT register (0x41) to keep * PCI Tx retries from interfering with C3 CPU state. - * - * Code taken from ipw2100 driver - jg */ - pci_read_config_dword(pdev, 0x40, &val); - if ((val & 0x0000ff00) != 0) - pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); + pci_write_config_byte(pdev, 0x41, 0); retval = pci_request_region(pdev, 0, "ath"); if (retval) { @@ -855,7 +850,6 @@ static int ath_pci_resume(struct pci_dev *pdev) { struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct ath_softc *sc = hw->priv; - u32 val; int err; err = pci_set_power_state(pdev, PCI_D0); @@ -871,12 +865,8 @@ static int ath_pci_resume(struct pci_dev *pdev) * Suspend/Resume resets the PCI configuration space, so we have to * re-disable the RETRY_TIMEOUT register (0x41) to keep * PCI Tx retries from interfering with C3 CPU state - * - * Code taken from ipw2100 driver - jg */ - pci_read_config_dword(pdev, 0x40, &val); - if ((val & 0x0000ff00) != 0) - pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); + pci_write_config_byte(pdev, 0x41, 0); // ath_init(hw); if (sc->sc_softled) { commit 17083477ed4da412daba5fa19db2ede7d8fd28ce Author: Jiri Slaby Date: Thu Jun 21 11:34:27 2007 +0200 insertable module now (basic pci init) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index dc414f1..2a9f98d 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -80,23 +80,23 @@ MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); * the HAL check them by defining a probe method. */ static struct pci_device_id ath_pci_id_table[] __devinitdata = { - { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ - { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ - { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 */ - { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ - { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ - { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ - { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ - { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ - { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ - { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ - { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ - { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ - { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ - { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ - { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ - { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ - { PCI_VDEVICE(ATHEROS, 0x001c) }, /* 5424 Condor (PCI-E)*/ + { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */ + { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */ + { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 */ + { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */ + { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */ + { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */ + { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */ + { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */ + { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ + { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ + { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ { 0 } }; MODULE_DEVICE_TABLE(pci, ath_pci_id_table); @@ -168,6 +168,8 @@ static irqreturn_t ath_intr(int irq, void *dev_id) DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); return IRQ_NONE; } + return IRQ_HANDLED; + if (!ath_hw_irq_pending(ah)) /* shared irq, not for us */ return IRQ_NONE; if ((dev->flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { @@ -264,29 +266,11 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) struct ath_hal *ah; enum ath5k_status status; int error = 0, i; - u8 csz; DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); + return 0; /* - * Cache line size is used to size and align various - * structures used to communicate with the hardware. - */ - pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); - /* XXX assert csz is non-zero */ - sc->sc_cachelsz = csz << 2; /* convert to bytes */ - - ATH_LOCK_INIT(sc); - ATH_TXBUF_LOCK_INIT(sc); - -/* tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)hw);*/ - - /* * Attach the hal */ ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase, &status); @@ -663,13 +647,11 @@ bad: return error; } -static int ath_detach(struct ieee80211_hw *hw) +static void ath_detach(struct ieee80211_hw *hw) { - struct ath_softc *sc = hw->priv; -// struct ieee80211com *ic = &sc->sc_ic; +// struct ath_softc *sc = hw->priv; // ath_stop(hw); - sc->sc_invalid = 1; /* * NB: the order of these is important: * o call the 802.11 layer before detaching the hal to @@ -686,7 +668,7 @@ static int ath_detach(struct ieee80211_hw *hw) // ath_rate_detach(sc->sc_rc); // ath_desc_free(sc); // ath_tx_cleanup(sc); - ath5k_hw_detach(sc->sc_ah); +// ath5k_hw_detach(sc->sc_ah); /* * NB: can't reclaim these until after ieee80211_ifdetach @@ -696,8 +678,19 @@ static int ath_detach(struct ieee80211_hw *hw) // ath_dynamic_sysctl_unregister(sc); // ath_rawdev_detach(sc); // unregister_netdev(dev); +} - return 0; +static const char *ath_chip_name(u8 mac_version) +{ + switch (mac_version) { + case AR5K_AR5210: + return "AR5210"; + case AR5K_AR5211: + return "AR5211"; + case AR5K_AR5212: + return "AR5212"; + } + return "Unknown"; } static int __devinit ath_pci_probe(struct pci_dev *pdev, @@ -706,19 +699,18 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, void __iomem *mem; struct ath_softc *sc; struct ieee80211_hw *hw; - const char *athname; - int retval; + int ret; u8 csz; - retval = pci_enable_device(pdev); - if (retval) { + ret = pci_enable_device(pdev); + if (ret) { dev_err(&pdev->dev, "can't enable device\n"); goto err; } /* XXX 32-bit addressing only */ - retval = pci_set_dma_mask(pdev, DMA_32BIT_MASK); - if (retval) { + ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); + if (ret) { dev_err(&pdev->dev, "32-bit DMA not available\n"); goto err_dis; } @@ -754,8 +746,8 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, */ pci_write_config_byte(pdev, 0x41, 0); - retval = pci_request_region(pdev, 0, "ath"); - if (retval) { + ret = pci_request_region(pdev, 0, "ath"); + if (ret) { dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); goto err_dis; } @@ -763,12 +755,14 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, mem = pci_iomap(pdev, 0, 0); if (!mem) { dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; + ret = -EIO; goto err_reg; } hw = ieee80211_alloc_hw(sizeof(*sc), &ath_hw_ops); if (hw == NULL) { dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); + ret = -ENOMEM; goto err_map; } @@ -782,21 +776,30 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, */ sc->sc_invalid = 1; sc->sc_iobase = mem; - sc->sc_bdev = pdev; + sc->sc_cachelsz = csz * sizeof(u32); /* convert to bytes */ + mutex_init(&sc->lock); + spin_lock_init(&sc->sc_txbuflock); + +/* tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)hw); + tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)hw);*/ pci_set_drvdata(pdev, hw); - if (request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc)) { + ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc); + if (ret) { dev_err(&pdev->dev, "request_irq failed\n"); goto err_free; } - if (ath_attach(pdev, hw) != 0) + ret = ath_attach(pdev, hw); + if (ret) goto err_irq; - athname = ath_hal_probe(id->vendor, id->device); - dev_info(&pdev->dev, "%s: irq=%d\n", - athname ? athname : "Atheros ???", pdev->irq); + dev_info(&pdev->dev, "%s chip found\n", ath_chip_name(id->driver_data)); /* ready to process interrupts */ sc->sc_invalid = 0; @@ -813,7 +816,7 @@ err_reg: err_dis: pci_disable_device(pdev); err: - return retval; + return ret; } static void __devexit ath_pci_remove(struct pci_dev *pdev) @@ -977,15 +980,10 @@ static struct ctl_table_header *ath_sysctl_header; /* * Module glue. */ -static char version[] = ATH_PCI_VERSION " (EXPERIMENTAL)"; -static char dev_info[] = "ath_pci"; - static int __init init_ath_pci(void) { int ret; - printk(KERN_INFO "%s: %s\n", dev_info, version); - ret = pci_register_driver(&ath_pci_drv_id); if (ret) { printk(KERN_ERR "ath_pci: can't register pci driver\n"); @@ -1001,8 +999,6 @@ static void __exit exit_ath_pci(void) if (ath_sysctl_header) unregister_sysctl_table(ath_sysctl_header); pci_unregister_driver(&ath_pci_drv_id); - - printk(KERN_INFO "%s: driver unloaded\n", dev_info); } module_init(init_ath_pci); @@ -1012,3 +1008,4 @@ MODULE_AUTHOR("Errno Consulting, Sam Leffler"); MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION(ATH_PCI_VERSION " (EXPERIMENTAL)"); diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 2a5aedc..55e3df7 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -178,8 +178,8 @@ struct ath_txq { struct ath_softc { void __iomem *sc_iobase; /* address of the device */ - struct semaphore sc_lock; /* dev-level lock */ - struct net_device_stats sc_devstats; /* device statistics */ + struct mutex lock; /* dev-level lock */ +// struct net_device_stats sc_devstats; /* device statistics */ struct ath_stats sc_stats; /* private statistics */ struct ieee80211_hw *hw; /* IEEE 802.11 common */ @@ -196,7 +196,6 @@ struct ath_softc { enum ieee80211_state, int); void (*sc_node_free)(struct ieee80211_node *); #endif - void *sc_bdev; /* associated bus device */ struct ath_desc *sc_desc; /* TX/RX descriptors */ size_t sc_desc_len; /* size of TX/RX descriptors */ u16 sc_cachelsz; /* cache line size */ @@ -305,24 +304,14 @@ struct ath_softc { struct ctl_table *sc_sysctls; }; -#define ATH_LOCK_INIT(_sc) \ - init_MUTEX(&(_sc)->sc_lock) -#define ATH_LOCK_DESTROY(_sc) -#define ATH_LOCK(_sc) down(&(_sc)->sc_lock) -#define ATH_UNLOCK(_sc) up(&(_sc)->sc_lock) -#define ATH_LOCK_ASSERT(_sc) -//TODO: KASSERT(spin_is_locked(&(_sc)->sc_lock), ("buf not locked!")) - #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<sc_txbuflock) -#define ATH_TXBUF_LOCK_DESTROY(_sc) #define ATH_TXBUF_LOCK(_sc) spin_lock(&(_sc)->sc_txbuflock) #define ATH_TXBUF_UNLOCK(_sc) spin_unlock(&(_sc)->sc_txbuflock) #define ATH_TXBUF_LOCK_BH(_sc) spin_lock_bh(&(_sc)->sc_txbuflock) #define ATH_TXBUF_UNLOCK_BH(_sc) spin_unlock_bh(&(_sc)->sc_txbuflock) #define ATH_TXBUF_LOCK_ASSERT(_sc) \ - KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), ("txbuf not locked!")) + KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), "txbuf not locked!") int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 451c3cc..97cc7cc 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -1066,7 +1066,6 @@ struct ath_hal { typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); /* General Functions */ -const char *ath_hal_probe(u16 vendor, u16 device); u16 ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); unsigned int ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index a56d14e..1aba99b 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -150,37 +150,6 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; General Functions \*******************/ -/* - * Perform a lookup if the device is supported by the HAL - * and return the chip name. - * TODO:Left here for combatibility, change it in at5k - */ -const char * -ath_hal_probe(u16 vendor, u16 device) -{ - int i; - - /* - * Perform a linear search on the table of supported devices - */ - for (i = 0; i < ARRAY_SIZE(ath5k_known_products); i++) { - if (vendor == ath5k_known_products[i].vendor && - device == ath5k_known_products[i].device){ - switch (ath5k_known_products[i].mac_version) { - case AR5K_AR5210: - return("AR5210"); - case AR5K_AR5211: - return("AR5211"); - case AR5K_AR5212: - return("AR5212"); - default: - return ""; - } - } - } - - return NULL; -} /* * Calculate transmition time of a frame commit a26f2991cbe2904ae658396caa605a0770091b41 Author: Jiri Slaby Date: Thu Jun 21 11:40:56 2007 +0200 rename ath_hal to ath_hw diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 2a9f98d..935b8fe 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -122,7 +122,7 @@ static struct ieee80211_ops ath_hw_ops = { /* * Read from a device register */ -static inline u32 ath_hw_reg_read(struct ath_hal *hw, u16 reg) +static inline u32 ath_hw_reg_read(struct ath_hw *hw, u16 reg) { return readl(hw->ah_sh + reg); } @@ -130,7 +130,7 @@ static inline u32 ath_hw_reg_read(struct ath_hal *hw, u16 reg) /* * Write to a device register */ -static inline void ath_hw_reg_write(struct ath_hal *hw, u32 val, u16 reg) +static inline void ath_hw_reg_write(struct ath_hw *hw, u32 val, u16 reg) { writel(val, hw->ah_sh + reg); } @@ -144,7 +144,7 @@ static inline void ath_hw_reg_write(struct ath_hal *hw, u32 val, u16 reg) * Return 1 if there is an interrupt for us, or 0 if there is none or if * the device has been removed. */ -static inline int ath_hw_irq_pending(struct ath_hal *hw) +static inline int ath_hw_irq_pending(struct ath_hw *hw) { return ath_hw_reg_read(hw, ATH_HW_IRQ_PENDING) == ATH_HW_IRQ_PENDING_TRUE; } @@ -156,7 +156,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) { struct net_device *dev = dev_id; struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; enum ath5k_int status; int needmark; @@ -263,7 +263,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; - struct ath_hal *ah; + struct ath_hw *ah; enum ath5k_status status; int error = 0, i; diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 97cc7cc..aa3b8c3 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -957,7 +957,7 @@ struct ath5k_capabilities { #define AR5K_MAX_GPIO 10 #define AR5K_MAX_RF_BANKS 8 -struct ath_hal { +struct ath_hw { u32 ah_magic; u16 ah_device; u16 ah_sub_vendor; @@ -1045,161 +1045,161 @@ struct ath_hal { /* * Function pointers */ - bool (*ah_setup_tx_desc)(struct ath_hal *, struct ath_desc *, + bool (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); - bool (*ah_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, + bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); - bool (*ah_fill_tx_desc)(struct ath_hal *, struct ath_desc *, + bool (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); - enum ath5k_status (*ah_proc_tx_desc)(struct ath_hal *, + enum ath5k_status (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); - enum ath5k_status (*ah_proc_rx_desc)(struct ath_hal *, + enum ath5k_status (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); }; /* * Prototypes */ -typedef bool (ath5k_rfgain_t)(struct ath_hal *, struct ath5k_channel *, u_int); +typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ath5k_channel *, u_int); /* General Functions */ -u16 ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); -unsigned int ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) ; +u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); +unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ -struct ath_hal *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); -//bool ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial); -//u16 ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip); -const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode); -void ath5k_hw_detach(struct ath_hal *hal); +struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); +//bool ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial); +//u16 ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip); +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); +void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ -bool ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); -//bool ath5k_hw_nic_reset(struct ath_hal *hal, u32 val); +bool ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); +//bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ -bool ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); -enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hal *hal); +bool ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); /* DMA Related Functions */ -void ath5k_hw_start_rx(struct ath_hal *hal); -bool ath5k_hw_stop_rx_dma(struct ath_hal *hal); -u32 ath5k_hw_get_rx_buf(struct ath_hal *hal); -void ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr); -bool ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue); -u32 ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr); -bool ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase); +void ath5k_hw_start_rx(struct ath_hw *hal); +bool ath5k_hw_stop_rx_dma(struct ath_hw *hal); +u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); +void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); +bool ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); +bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); /* Interrupt handling */ -bool ath5k_hw_is_intr_pending(struct ath_hal *hal); -bool ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask); -u32 ath5k_hw_get_intr(struct ath_hal *hal); -enum ath5k_int ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask); -void ath5k_hw_radar_alert(struct ath_hal *hal, bool enable); +bool ath5k_hw_is_intr_pending(struct ath_hw *hal); +bool ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask); +u32 ath5k_hw_get_intr(struct ath_hw *hal); +enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); +void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ -bool ath5k_hw_eeprom_is_busy(struct ath_hal *hal); -int ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data); -int ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data); -u16 ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode); -int ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_init(struct ath_hal *hal); -int ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac); -bool ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, enum ieee80211_regdomain *regdomain); -bool ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, enum ath5k_status *status); -bool ath5k_hw_get_capabilities(struct ath_hal *hal); +bool ath5k_hw_eeprom_is_busy(struct ath_hw *hal); +int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data); +int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data); +u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); +int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); +int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); +int ath5k_eeprom_init(struct ath_hw *hal); +int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac); +bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain); +bool ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, enum ath5k_status *status); +bool ath5k_hw_get_capabilities(struct ath_hw *hal); /* Protocol Control Unit Functions */ -void ath5k_hw_set_opmode(struct ath_hal *hal); -void ath5k_hw_set_pcu_config(struct ath_hal *hal); +void ath5k_hw_set_opmode(struct ath_hw *hal); +void ath5k_hw_set_pcu_config(struct ath_hw *hal); /* BSSID Functions */ -void ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac); -bool ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac); -void ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, u16 assoc_id); -bool ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask); +void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); +bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); +void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); +bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); /* Receive start/stop functions */ -void ath5k_hw_start_rx_pcu(struct ath_hal *hal); -void ath5k_hw_stop_pcu_recv(struct ath_hal *hal); +void ath5k_hw_start_rx_pcu(struct ath_hw *hal); +void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); /* RX Filter functions */ -void ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, u32 filter1); -bool ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index); -bool ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index); -u32 ath5k_hw_get_rx_filter(struct ath_hal *hal); -void ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter); +void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); +bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); +u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); +void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); /* Beacon related functions */ -u32 ath5k_hw_get_tsf32(struct ath_hal *hal); -u64 ath5k_hw_get_tsf64(struct ath_hal *hal); -void ath5k_hw_reset_tsf(struct ath_hal *hal); -void ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, u32 interval); -void ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state); -void ath5k_hw_reset_beacon(struct ath_hal *hal); -bool ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr); -void ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statistics); -void ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) ; +u32 ath5k_hw_get_tsf32(struct ath_hw *hal); +u64 ath5k_hw_get_tsf64(struct ath_hw *hal); +void ath5k_hw_reset_tsf(struct ath_hw *hal); +void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); +void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); +void ath5k_hw_reset_beacon(struct ath_hw *hal); +bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); +void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); +void ath5k_hw_proc_mib_event(struct ath_hw *hal, const struct ath5k_node_stats *stats) ; /* ACK/CTS Timeouts */ -bool ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout); -unsigned int ath5k_hw_get_ack_timeout(struct ath_hal *hal); -bool ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout); -unsigned int ath5k_hw_get_cts_timeout(struct ath_hal *hal); +bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); +bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); /* Key table (WEP) functions */ -bool ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher); -u32 ath5k_hw_get_keycache_size(struct ath_hal *hal); -bool ath5k_hw_reset_key(struct ath_hal *hal, u16 entry); -bool ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry); -bool ath5k_hw_set_key(struct ath_hal *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused); -bool ath5k_hw_set_key_lladdr(struct ath_hal *hal, u16 entry, const u8 *mac); +bool ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher); +u32 ath5k_hw_get_keycache_size(struct ath_hw *hal); +bool ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); +bool ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); +bool ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused); +bool ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); /* Queue Control Unit, DFS Control Unit Functions */ -int ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); -bool ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, const struct ath5k_txq_info *queue_info); -bool ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info *queue_info); -bool ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue); -u32 ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue); -bool ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time); -unsigned int ath5k_hw_get_slot_time(struct ath_hal *hal); +int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); +bool ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); +bool ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); +bool ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); +unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); /* Hardware Descriptor Functions */ /* RX Descriptor */ -bool ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u32 size, unsigned int flags); +bool ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); /* GPIO Functions */ -void ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state); -bool ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio); -bool ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio); -u32 ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio); -bool ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val); -void ath5k_hw_set_gpio_intr(struct ath_hal *hal, unsigned int gpio, u32 interrupt_level); +void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); +bool ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); +bool ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); +u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); +bool ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); +void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); /* Regulatory Domain/Channels Setup */ unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); -bool ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags); -bool ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); -u16 ath5k_get_regdomain(struct ath_hal *hal); +bool ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags); +bool ath_hal_init_channels(struct ath_hw *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); +u16 ath5k_get_regdomain(struct ath_hw *hal); /* PHY/RF access functions */ -bool ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel); u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel); -bool ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ath5k_channel *channel); bool ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan); -bool ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel); -bool ath5k_hw_phy_disable(struct ath_hal *hal); -void ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant); -unsigned int ath5k_hw_get_def_antenna(struct ath_hal *hal); +bool ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_phy_disable(struct ath_hw *hal); +void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); +unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 first, u32 col, bool set); -u32 ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal); -bool ath5k_hw_rfregs_gain_readback(struct ath_hal *hal); -s32 ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal); -bool ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); -bool ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); -bool ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode); -void ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode); -bool ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq); -enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hal *hal); +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal); +bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal); +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal); +bool ath5k_hw_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); +bool ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); +bool ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); +void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode); +bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ -void ath5k_hw_dump_state(struct ath_hal *hal); -enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; -bool ath5k_hw_set_capability(struct ath_hal *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; -bool ath5k_hw_query_pspoll_support(struct ath_hal *hal); -bool ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, u16 assoc_id); -bool ath5k_hw_disable_pspoll(struct ath_hal *hal); +void ath5k_hw_dump_state(struct ath_hw *hal); +enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; +bool ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; +bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); +bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); +bool ath5k_hw_disable_pspoll(struct ath_hw *hal); #endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 1aba99b..a1473a1 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -78,33 +78,33 @@ static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -static bool ath5k_hw_nic_reset(struct ath_hal *, u32); -static bool ath5k_hw_nic_wakeup(struct ath_hal *, u16, bool); -static u16 ath5k_hw_radio_revision(struct ath_hal *, enum ath5k_chip); -static bool ath5k_hw_txpower(struct ath_hal *, struct ath5k_channel *, +static bool ath5k_hw_nic_reset(struct ath_hw *, u32); +static bool ath5k_hw_nic_wakeup(struct ath_hw *, u16, bool); +static u16 ath5k_hw_radio_revision(struct ath_hw *, enum ath5k_chip); +static bool ath5k_hw_txpower(struct ath_hw *, struct ath5k_channel *, unsigned int); -static bool ath5k_hw_setup_4word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_setup_xr_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_fill_4word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *); -static bool ath5k_hw_setup_2word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_fill_2word_tx_desc(struct ath_hal *, struct ath_desc *, +static bool ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hal *, +static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); /* @@ -156,7 +156,7 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; * TODO: Left here for combatibility, change it in ath5k */ u16 /*TODO: Is this really hardware dependent ?*/ -ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, +ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble) { const struct ath5k_rate *rate; @@ -222,7 +222,7 @@ ath_hal_computetxtime(struct ath_hal *hal, const struct ath5k_rate_table *rates, * TODO:Left here for combatibility, change it in at5k */ unsigned int/*TODO:Fix this */ -ath_hal_getwirelessmodes(struct ath_hal *hal, enum ieee80211_countrycode country) +ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) { switch(hal->ah_version){ case AR5K_AR5212: @@ -277,7 +277,7 @@ ath5k_hw_rtcopy(struct ath5k_rate_table *dst, const struct ath5k_rate_table *src /* * Read from a device register */ -static inline u32 ath5k_hw_reg_read(struct ath_hal *hal, u16 reg) +static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg) { return readl(hal->ah_sh + reg); } @@ -285,7 +285,7 @@ static inline u32 ath5k_hw_reg_read(struct ath_hal *hal, u16 reg) /* * Write to a device register */ -static inline void ath5k_hw_reg_write(struct ath_hal *hal, u32 val, u16 reg) +static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg) { writel(val, hal->ah_sh + reg); } @@ -314,7 +314,7 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) * Check if a register write has been completed */ static bool -ath5k_hw_register_timeout(struct ath_hal *hal, u32 reg, u32 flag, +ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, u32 val, bool is_set) { int i; @@ -344,10 +344,10 @@ ath5k_hw_register_timeout(struct ath_hal *hal, u32 reg, u32 flag, /* * Check if the device is supported and initialize the needed structs */ -struct ath_hal * +struct ath_hw * ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) { - struct ath_hal *hal = NULL; + struct ath_hw *hal = NULL; u8 mac[ETH_ALEN]; u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ int i; @@ -372,7 +372,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) } /*If we passed the test malloc a hal struct*/ - hal = kzalloc(sizeof(struct ath_hal), GFP_KERNEL); + hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); if (hal == NULL) { *status = AR5K_ENOMEM; AR5K_PRINT("out of memory\n"); @@ -568,7 +568,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) * Bring up MAC + PHY Chips */ static bool -ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) +ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) { u32 turbo, mode, clock; @@ -699,7 +699,7 @@ ath5k_hw_nic_wakeup(struct ath_hal *hal, u16 flags, bool initial) * Get the PHY Chip revision */ static u16 -ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) +ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip) { int i; u32 srev; @@ -750,7 +750,7 @@ ath5k_hw_radio_revision(struct ath_hal *hal, enum ath5k_chip chip) * TODO:Limit this per chipset */ const struct ath5k_rate_table * -ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode) +ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) { AR5K_TRACE; @@ -776,7 +776,7 @@ ath5k_hw_get_rate_table(struct ath_hal *hal, unsigned int mode) * Free the hal struct */ void -ath5k_hw_detach(struct ath_hal *hal) +ath5k_hw_detach(struct ath_hw *hal) { AR5K_TRACE; @@ -798,7 +798,7 @@ ath5k_hw_detach(struct ath_hal *hal) * Main reset function */ bool -ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, +ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -1383,7 +1383,7 @@ ath5k_hw_reset(struct ath_hal *hal, enum ieee80211_if_types op_mode, * Reset chipset */ static bool -ath5k_hw_nic_reset(struct ath_hal *hal, u32 val) +ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) { bool ret = false; u32 mask = val ? val : ~0; @@ -1431,7 +1431,7 @@ ath5k_hw_nic_reset(struct ath_hal *hal, u32 val) * Sleep control */ bool -ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, +ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration) { u32 staid; @@ -1502,7 +1502,7 @@ ath5k_hw_set_power(struct ath_hal *hal, enum ath5k_power_mode mode, * TODO:Remove ? */ enum ath5k_power_mode -ath5k_hw_get_power_mode(struct ath_hal *hal) +ath5k_hw_get_power_mode(struct ath_hw *hal) { AR5K_TRACE; return hal->ah_power_mode; @@ -1523,7 +1523,7 @@ ath5k_hw_get_power_mode(struct ath_hal *hal) * Start DMA receive */ void -ath5k_hw_start_rx(struct ath_hal *hal) +ath5k_hw_start_rx(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXE); @@ -1533,7 +1533,7 @@ ath5k_hw_start_rx(struct ath_hal *hal) * Stop DMA receive */ bool -ath5k_hw_stop_rx_dma(struct ath_hal *hal) +ath5k_hw_stop_rx_dma(struct ath_hw *hal) { int i; @@ -1555,7 +1555,7 @@ ath5k_hw_stop_rx_dma(struct ath_hal *hal) * Get the address of the RX Descriptor */ u32 -ath5k_hw_get_rx_buf(struct ath_hal *hal) +ath5k_hw_get_rx_buf(struct ath_hw *hal) { return AR5K_REG_READ(AR5K_RXDP); } @@ -1564,7 +1564,7 @@ ath5k_hw_get_rx_buf(struct ath_hal *hal) * Set the address of the RX Descriptor */ void -ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr) +ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) { AR5K_TRACE; @@ -1581,7 +1581,7 @@ ath5k_hw_put_rx_buf(struct ath_hal *hal, u32 phys_addr) * (see also QCU/DCU functions) */ bool -ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue) +ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) { u32 tx_queue; @@ -1638,7 +1638,7 @@ ath5k_hw_tx_start(struct ath_hal *hal, unsigned int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue) +ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) { int i = 100, pending; u32 tx_queue; @@ -1698,7 +1698,7 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, unsigned int queue) * (see also QCU/DCU functions) */ u32 -ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue) +ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) { u16 tx_reg; AR5K_TRACE; @@ -1732,7 +1732,7 @@ ath5k_hw_get_tx_buf(struct ath_hal *hal, unsigned int queue) * (see also QCU/DCU functions) */ bool -ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr) +ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) { u16 tx_reg; AR5K_TRACE; @@ -1776,7 +1776,7 @@ ath5k_hw_put_tx_buf(struct ath_hal *hal, unsigned int queue, u32 phys_addr) * Update tx trigger level */ bool -ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) +ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) { u32 trigger_level, imr; bool status = false; @@ -1826,7 +1826,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hal *hal, bool increase) * Check if we have pending interrupts */ bool -ath5k_hw_is_intr_pending(struct ath_hal *hal) +ath5k_hw_is_intr_pending(struct ath_hw *hal) { AR5K_TRACE; return AR5K_REG_READ(AR5K_INTPEND) == true ? true : false; @@ -1836,7 +1836,7 @@ ath5k_hw_is_intr_pending(struct ath_hal *hal) * Get interrupt mask (ISR) */ bool -ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask) +ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) { u32 data; @@ -1905,7 +1905,7 @@ ath5k_hw_get_isr(struct ath_hal *hal, u32 *interrupt_mask) * TODO: Remove ? */ u32 -ath5k_hw_get_intr(struct ath_hal *hal) +ath5k_hw_get_intr(struct ath_hw *hal) { AR5K_TRACE; return hal->ah_imr; @@ -1915,7 +1915,7 @@ ath5k_hw_get_intr(struct ath_hal *hal) * Set interrupt mask */ enum ath5k_int -ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) +ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) { enum ath5k_int old_mask, int_mask; @@ -1972,7 +1972,7 @@ ath5k_hw_set_intr(struct ath_hal *hal, enum ath5k_int new_mask) * Enalbe HW radar detection */ void -ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) +ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) { AR5K_TRACE; @@ -2025,7 +2025,7 @@ ath5k_hw_radar_alert(struct ath_hal *hal, bool enable) * Check if eeprom is busy */ bool -ath5k_hw_eeprom_is_busy(struct ath_hal *hal) +ath5k_hw_eeprom_is_busy(struct ath_hw *hal) { AR5K_TRACE; return AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? true : false; @@ -2035,7 +2035,7 @@ ath5k_hw_eeprom_is_busy(struct ath_hal *hal) * Read from eeprom */ int -ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data) +ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) { u32 status, timeout; @@ -2071,7 +2071,7 @@ ath5k_hw_eeprom_read(struct ath_hal *hal, u32 offset, u16 *data) * Write to eeprom - currently disabled, use at your own risk */ int -ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data) +ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) { #if 0 u32 status, timeout; @@ -2119,7 +2119,7 @@ ath5k_hw_eeprom_write(struct ath_hal *hal, u32 offset, u16 data) } u16 -ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode) +ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) { u16 val; @@ -2147,7 +2147,7 @@ ath5k_eeprom_bin2freq(struct ath_hal *hal, u16 bin, unsigned int mode) * Read antenna infos from eeprom */ int -ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode) +ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 o = *offset; @@ -2206,7 +2206,7 @@ ath5k_eeprom_read_ants(struct ath_hal *hal, u32 *offset, unsigned int mode) * Read supported modes from eeprom */ int -ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode) +ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 o = *offset; @@ -2290,7 +2290,7 @@ ath5k_eeprom_read_modes(struct ath_hal *hal, u32 *offset, unsigned int mode) * Initialize eeprom & capabilities structs */ int -ath5k_eeprom_init(struct ath_hal *hal) +ath5k_eeprom_init(struct ath_hw *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 offset; @@ -2486,7 +2486,7 @@ ath5k_eeprom_init(struct ath_hal *hal) * Read the MAC address from eeprom */ int -ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) +ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) { u32 total, offset; u16 data; @@ -2522,7 +2522,7 @@ ath5k_eeprom_read_mac(struct ath_hal *hal, u8 *mac) * Read/Write refulatory domain */ bool -ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, +ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain) { u16 ee_regdomain; @@ -2553,7 +2553,7 @@ ath5k_eeprom_regulation_domain(struct ath_hal *hal, bool write, * Use the above to write a new regulatory domain */ bool -ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, +ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, enum ath5k_status *status) { enum ieee80211_regdomain ieee_regdomain; @@ -2574,7 +2574,7 @@ ath5k_hw_set_regdomain(struct ath_hal *hal, u16 regdomain, * Fill the capabilities struct */ bool -ath5k_hw_get_capabilities(struct ath_hal *hal) +ath5k_hw_get_capabilities(struct ath_hw *hal) { u16 ee_header; @@ -2651,7 +2651,7 @@ ath5k_hw_get_capabilities(struct ath_hal *hal) * Set Operation mode */ void -ath5k_hw_set_opmode(struct ath_hal *hal) +ath5k_hw_set_opmode(struct ath_hw *hal) { u32 pcu_reg, beacon_reg, low_id, high_id; @@ -2705,7 +2705,7 @@ ath5k_hw_set_opmode(struct ath_hal *hal) } void /*TODO: Get rid of this, clean up the driver code, only set_opmode is needed*/ -ath5k_hw_set_pcu_config(struct ath_hal *hal) +ath5k_hw_set_pcu_config(struct ath_hw *hal) { AR5K_TRACE; ath5k_hw_set_opmode(hal); @@ -2719,7 +2719,7 @@ ath5k_hw_set_pcu_config(struct ath_hal *hal) * Get station id */ void -ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac) +ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) { AR5K_TRACE; memcpy(mac, hal->ah_sta_id, ETH_ALEN); @@ -2729,7 +2729,7 @@ ath5k_hw_get_lladdr(struct ath_hal *hal, u8 *mac) * Set station id */ bool -ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac) +ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac) { u32 low_id, high_id; @@ -2750,7 +2750,7 @@ ath5k_hw_set_lladdr(struct ath_hal *hal, const u8 *mac) * Set BSSID */ void -ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, +ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id) { u32 low_id, high_id; @@ -2789,7 +2789,7 @@ ath5k_hw_set_associd(struct ath_hal *hal, const u8 *bssid, * Set BSSID mask on 5212 */ bool -ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask) +ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) { u32 low_id, high_id; AR5K_TRACE; @@ -2815,7 +2815,7 @@ ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u8* mask) * Start receive on PCU */ void -ath5k_hw_start_rx_pcu(struct ath_hal *hal) +ath5k_hw_start_rx_pcu(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); @@ -2825,7 +2825,7 @@ ath5k_hw_start_rx_pcu(struct ath_hal *hal) * Stop receive on PCU */ void -ath5k_hw_stop_pcu_recv(struct ath_hal *hal) +ath5k_hw_stop_pcu_recv(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); @@ -2839,7 +2839,7 @@ ath5k_hw_stop_pcu_recv(struct ath_hal *hal) * Set multicast filter */ void -ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, +ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1) { AR5K_TRACE; @@ -2852,7 +2852,7 @@ ath5k_hw_set_mcast_filter(struct ath_hal *hal, u32 filter0, * Set multicast filter by index */ bool -ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index) +ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) { AR5K_TRACE; @@ -2872,7 +2872,7 @@ ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u32 index) * Clear Multicast filter by index */ bool -ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index) +ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) { AR5K_TRACE; @@ -2892,7 +2892,7 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u32 index) * Get current rx filter */ u32 -ath5k_hw_get_rx_filter(struct ath_hal *hal) +ath5k_hw_get_rx_filter(struct ath_hw *hal) { u32 data, filter = 0; @@ -2917,7 +2917,7 @@ ath5k_hw_get_rx_filter(struct ath_hal *hal) * Set rx filter */ void -ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter) +ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) { u32 data = 0; @@ -2966,7 +2966,7 @@ ath5k_hw_set_rx_filter(struct ath_hal *hal, u32 filter) * Get a 32bit TSF */ u32 -ath5k_hw_get_tsf32(struct ath_hal *hal) +ath5k_hw_get_tsf32(struct ath_hw *hal) { AR5K_TRACE; return AR5K_REG_READ(AR5K_TSF_L32); @@ -2976,7 +2976,7 @@ ath5k_hw_get_tsf32(struct ath_hal *hal) * Get the full 64bit TSF */ u64 -ath5k_hw_get_tsf64(struct ath_hal *hal) +ath5k_hw_get_tsf64(struct ath_hw *hal) { u64 tsf = AR5K_REG_READ(AR5K_TSF_U32); AR5K_TRACE; @@ -2988,7 +2988,7 @@ ath5k_hw_get_tsf64(struct ath_hal *hal) * Force a TSF reset */ void -ath5k_hw_reset_tsf(struct ath_hal *hal) +ath5k_hw_reset_tsf(struct ath_hw *hal) { AR5K_TRACE; AR5K_REG_ENABLE_BITS(AR5K_BEACON, @@ -2999,7 +2999,7 @@ ath5k_hw_reset_tsf(struct ath_hal *hal) * Initialize beacon timers */ void -ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, +ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval) { u32 timer1, timer2, timer3; @@ -3047,7 +3047,7 @@ ath5k_hw_init_beacon(struct ath_hal *hal, u32 next_beacon, * Set beacon timers */ void -ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state *state) +ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state) { u32 cfp_period, next_cfp, dtim, interval, next_beacon; @@ -3173,7 +3173,7 @@ ath5k_hw_set_beacon_timers(struct ath_hal *hal, const struct ath5k_beacon_state * Reset beacon timers */ void -ath5k_hw_reset_beacon(struct ath_hal *hal) +ath5k_hw_reset_beacon(struct ath_hw *hal) { AR5K_TRACE; /* @@ -3195,7 +3195,7 @@ ath5k_hw_reset_beacon(struct ath_hal *hal) * TODO: This function's name is misleading, rename */ bool -ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) +ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) { bool ret; int i; @@ -3241,7 +3241,7 @@ ath5k_hw_wait_for_beacon(struct ath_hal *hal, unsigned long phys_addr) * Update mib counters (statistics) */ void -ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statistics) +ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics) { AR5K_TRACE; /* Read-And-Clear */ @@ -3261,7 +3261,7 @@ ath5k_hw_update_mib_counters(struct ath_hal *hal, struct ath5k_mib_stats *statis } void /*Unimplemented*/ -ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stats) +ath5k_hw_proc_mib_event(struct ath_hw *hal, const struct ath5k_node_stats *stats) { AR5K_TRACE; } @@ -3274,7 +3274,7 @@ ath5k_hw_proc_mib_event(struct ath_hal *hal, const struct ath5k_node_stats *stat * Set ACK timeout on PCU */ bool -ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout) +ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), @@ -3291,7 +3291,7 @@ ath5k_hw_set_ack_timeout(struct ath_hal *hal, unsigned int timeout) * Read the ACK timeout from PCU */ unsigned int -ath5k_hw_get_ack_timeout(struct ath_hal *hal) +ath5k_hw_get_ack_timeout(struct ath_hw *hal) { AR5K_TRACE; return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), @@ -3302,7 +3302,7 @@ ath5k_hw_get_ack_timeout(struct ath_hal *hal) * Set CTS timeout on PCU */ bool -ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout) +ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), @@ -3319,7 +3319,7 @@ ath5k_hw_set_cts_timeout(struct ath_hal *hal, unsigned int timeout) * Read CTS timeout from PCU */ unsigned int -ath5k_hw_get_cts_timeout(struct ath_hal *hal) +ath5k_hw_get_cts_timeout(struct ath_hw *hal) { AR5K_TRACE; return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), @@ -3334,7 +3334,7 @@ ath5k_hw_get_cts_timeout(struct ath_hal *hal) * Return which ciphers are supported by hw */ bool -ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) +ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher) { AR5K_TRACE; /* @@ -3350,7 +3350,7 @@ ath5k_hw_is_cipher_supported(struct ath_hal *hal, enum ath5k_cipher cipher) * Get key cache size */ u32 -ath5k_hw_get_keycache_size(struct ath_hal *hal) +ath5k_hw_get_keycache_size(struct ath_hw *hal) { AR5K_TRACE; return AR5K_KEYCACHE_SIZE; @@ -3360,7 +3360,7 @@ ath5k_hw_get_keycache_size(struct ath_hal *hal) * Reset encryption key */ bool -ath5k_hw_reset_key(struct ath_hal *hal, u16 entry) +ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) { int i; @@ -3382,7 +3382,7 @@ ath5k_hw_reset_key(struct ath_hal *hal, u16 entry) * Check if a key entry is valid */ bool -ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry) +ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) { AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); @@ -3401,7 +3401,7 @@ ath5k_hw_is_key_valid(struct ath_hal *hal, u16 entry) * Set encryption key */ bool -ath5k_hw_set_key(struct ath_hal *hal, u16 entry, +ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused) { int i; @@ -3449,7 +3449,7 @@ ath5k_hw_set_key(struct ath_hal *hal, u16 entry, } bool -ath5k_hw_set_key_lladdr(struct ath_hal *hal, u16 entry, +ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) { u32 low_id, high_id; @@ -3486,7 +3486,7 @@ Queue Control Unit, DFS Control Unit Functions * Initialize a transmit queue */ int -ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, +ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info) { unsigned int queue; @@ -3564,7 +3564,7 @@ ath5k_hw_setup_tx_queue(struct ath_hal *hal, enum ath5k_tx_queue queue_type, * Setup a transmit queue */ bool -ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, +ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info) { AR5K_TRACE; @@ -3590,7 +3590,7 @@ ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, * Get properties for a specific transmit queue */ bool -ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info *queue_info) +ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info) { AR5K_TRACE; memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); @@ -3601,7 +3601,7 @@ ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, struct ath5k_txq_info * Set a transmit queue inactive */ bool -ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue) +ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3618,7 +3618,7 @@ ath5k_hw_release_tx_queue(struct ath_hal *hal, unsigned int queue) * Set DFS params for a transmit queue */ bool -ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue) +ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) { u32 cw_min, cw_max, retry_lg, retry_sh; struct ath5k_txq_info *tq = &hal->ah_txq[queue]; @@ -3838,7 +3838,7 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, unsigned int queue) * for a specific queue [5211+] */ u32 -ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue) { +ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3857,7 +3857,7 @@ ath5k_hw_num_tx_pending(struct ath_hal *hal, unsigned int queue) { * Set slot time */ bool -ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time) +ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time) { AR5K_TRACE; if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) @@ -3876,7 +3876,7 @@ ath5k_hw_set_slot_time(struct ath_hal *hal, unsigned int slot_time) * Get slot time */ unsigned int -ath5k_hw_get_slot_time(struct ath_hal *hal) +ath5k_hw_get_slot_time(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) @@ -3899,7 +3899,7 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) * Initialize the 2-word tx descriptor on 5210/5211 */ static bool -ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) @@ -3996,7 +3996,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Initialize the 4-word tx descriptor on 5212 */ static bool -ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) @@ -4081,7 +4081,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Initialize a 4-word XR tx descriptor on 5212 */ static bool -ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3) { @@ -4116,7 +4116,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Fill the 2-word tx descriptor on 5210/5211 */ static bool -ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4145,7 +4145,7 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * XXX: Added an argument *last_desc -need revision */ static bool -ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) { @@ -4177,7 +4177,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, * Proccess the tx status descriptor on 5210/5211 */ static enum ath5k_status -ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) +ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4236,7 +4236,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) * Proccess a tx descriptor on 5212 */ static enum ath5k_status -ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) +ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4329,7 +4329,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) * Initialize an rx descriptor */ bool -ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags) { struct ath5k_rx_desc *rx_desc; @@ -4365,7 +4365,7 @@ ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, * Proccess the rx status descriptor on 5210/5211 */ static enum ath5k_status -ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_old_rx_status *rx_status; @@ -4440,7 +4440,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, * Proccess the rx status descriptor on 5212 */ static enum ath5k_status -ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_new_rx_status *rx_status; @@ -4527,7 +4527,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, * Set led state */ void -ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) +ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) { u32 led; /*5210 has different led mode handling*/ @@ -4586,7 +4586,7 @@ ath5k_hw_set_ledstate(struct ath_hal *hal, unsigned int state) * Set GPIO outputs */ bool -ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio) +ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4603,7 +4603,7 @@ ath5k_hw_set_gpio_output(struct ath_hal *hal, u32 gpio) * Set GPIO inputs */ bool -ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio) +ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4620,7 +4620,7 @@ ath5k_hw_set_gpio_input(struct ath_hal *hal, u32 gpio) * Get GPIO state */ u32 -ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio) +ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) @@ -4635,7 +4635,7 @@ ath5k_hw_get_gpio(struct ath_hal *hal, u32 gpio) * Set GPIO state */ bool -ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val) +ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) { u32 data; AR5K_TRACE; @@ -4658,7 +4658,7 @@ ath5k_hw_set_gpio(struct ath_hal *hal, u32 gpio, u32 val) * Initialize the GPIO interrupt (RFKill switch) */ void -ath5k_hw_set_gpio_intr(struct ath_hal *hal, unsigned int gpio, +ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level) { u32 data; @@ -4754,7 +4754,7 @@ ath_hal_ieee2mhz(unsigned int chan, u_int flags) * Check if a channel is supported */ bool -ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags) +ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags) { /* Check if the channel is in our supported range */ if (flags & CHANNEL_2GHZ) { @@ -4775,7 +4775,7 @@ ath5k_check_channel(struct ath_hal *hal, u16 freq, unsigned int flags) * also left here temporarily for combatibility. */ bool -ath_hal_init_channels(struct ath_hal *hal, struct ath5k_channel *channels, +ath_hal_init_channels(struct ath_hw *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended) { @@ -4911,7 +4911,7 @@ for loop starts from 1 and all channels are marked as 5GHz M.F.*/ } u16 -ath5k_get_regdomain(struct ath_hal *hal) +ath5k_get_regdomain(struct ath_hw *hal) { u16 regdomain; enum ieee80211_regdomain ieee_regdomain; @@ -4945,7 +4945,7 @@ ath5k_get_regdomain(struct ath_hal *hal) * Set a channel on the radio chip */ bool -ath5k_hw_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel) { bool ret; @@ -5008,7 +5008,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) * Set channel on RF5110 */ bool -ath5k_hw_rf5110_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ath5k_channel *channel) { u32 data; @@ -5056,7 +5056,7 @@ ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athch * Set channel on 5111 */ bool -ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel) { unsigned int ieee_channel, ath_channel; u32 data0, data1, clock; @@ -5100,7 +5100,7 @@ ath5k_hw_rf5111_channel(struct ath_hal *hal, struct ath5k_channel *channel) * Set channel on 5112 */ bool -ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ath5k_channel *channel) { u32 data, data0, data1, data2; u16 c; @@ -5148,7 +5148,7 @@ ath5k_hw_rf5112_channel(struct ath_hal *hal, struct ath5k_channel *channel) * Perform a PHY calibration */ bool -ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ +ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ath5k_channel *channel){ bool ret; @@ -5163,7 +5163,7 @@ ath5k_hw_phy_calibrate(struct ath_hal *hal, struct ath5k_channel *channel){ * Perform a PHY calibration on RF5110 */ bool -ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) { bool ret = true; u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; @@ -5312,7 +5312,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) * Perform a PHY calibration on RF5111/5112 */ bool -ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) +ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) { u32 i_pwr, q_pwr; s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; @@ -5360,7 +5360,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hal *hal, struct ath5k_channel *channel) } bool -ath5k_hw_phy_disable(struct ath_hal *hal) +ath5k_hw_phy_disable(struct ath_hw *hal) { AR5K_TRACE; /*Just a try M.F.*/ @@ -5369,7 +5369,7 @@ ath5k_hw_phy_disable(struct ath_hal *hal) } void /*TODO:Boundary check*/ -ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant) +ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant) { AR5K_TRACE; /*Just a try M.F.*/ @@ -5378,7 +5378,7 @@ ath5k_hw_set_def_antenna(struct ath_hal *hal, unsigned int ant) } unsigned int -ath5k_hw_get_def_antenna(struct ath_hal *hal) +ath5k_hw_get_def_antenna(struct ath_hw *hal) { AR5K_TRACE; /*Just a try M.F.*/ @@ -5437,7 +5437,7 @@ ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, } u32 -ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) +ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal) { u32 mix, step; u32 *rf; @@ -5473,7 +5473,7 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) } bool -ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) +ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) { u32 step, mix, level[4]; u32 *rf; @@ -5515,7 +5515,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) } s32 -ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) +ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) { int ret = 0; const struct ath5k_gain_opt *go; @@ -5575,7 +5575,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) * Initialize RF */ bool -ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) { ath5k_rfgain_t *func = NULL; bool ret; @@ -5613,7 +5613,7 @@ ath5k_hw_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int * Initialize RF5111 */ bool -ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); @@ -5711,7 +5711,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsig * Initialize RF5112 */ bool -ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; unsigned int rf_size; @@ -5806,7 +5806,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsig * doesn't ar5k_rfregs work ? */ void -ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int freq, +ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -5865,7 +5865,7 @@ ath5k_hw_ar5211_rfregs(struct ath_hal *hal, struct ath5k_channel *channel, unsig } bool -ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq) +ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) { int i; @@ -5895,7 +5895,7 @@ ath5k_hw_rfgain(struct ath_hal *hal, unsigned int phy, u_int freq) } enum ath5k_rfgain -ath5k_hw_get_rf_gain(struct ath_hal *hal) +ath5k_hw_get_rf_gain(struct ath_hw *hal) { u32 data, type; @@ -5943,7 +5943,7 @@ ath5k_hw_get_rf_gain(struct ath_hal *hal) * Initialize the tx power table (not fully implemented) */ static void -ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_power) +ath5k_txpower_table(struct ath_hw *hal, struct ath5k_channel *channel, s16 max_power) { u16 txpower, *rates; int i, min, max, n; @@ -5981,7 +5981,7 @@ ath5k_txpower_table(struct ath_hal *hal, struct ath5k_channel *channel, s16 max_ * Set transmition power */ static bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, unsigned int txpower) +ath5k_hw_txpower(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; int i; @@ -6039,7 +6039,7 @@ ath5k_hw_txpower(struct ath_hal *hal, struct ath5k_channel *channel, unsigned in } bool -ath5k_hw_set_txpower_limit(struct ath_hal *hal, unsigned int power) +ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) { /*Just a try M.F.*/ struct ath5k_channel *channel = &hal->ah_current_channel; @@ -6057,7 +6057,7 @@ ath5k_hw_set_txpower_limit(struct ath_hal *hal, unsigned int power) \****************/ void /*O.K.*/ -ath5k_hw_dump_state(struct ath_hal *hal) +ath5k_hw_dump_state(struct ath_hw *hal) { #ifdef AR5K_DEBUG #define AR5K_PRINT_REGISTER(_x) \ @@ -6160,7 +6160,7 @@ ath5k_hw_dump_state(struct ath_hal *hal) #endif } -enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, +enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 *result) { @@ -6220,7 +6220,7 @@ enum ath5k_status ath5k_hw_get_capability(struct ath_hal *hal, } bool -ath5k_hw_set_capability(struct ath_hal *hal, +ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) @@ -6233,7 +6233,7 @@ ath5k_hw_set_capability(struct ath_hal *hal, } bool -ath5k_hw_query_pspoll_support(struct ath_hal *hal) +ath5k_hw_query_pspoll_support(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) @@ -6243,7 +6243,7 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) } bool -ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, +ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id) { AR5K_TRACE; @@ -6258,7 +6258,7 @@ ath5k_hw_enable_pspoll(struct ath_hal *hal, u8 *bssid, } bool -ath5k_hw_disable_pspoll(struct ath_hal *hal) +ath5k_hw_disable_pspoll(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { commit 7c167b519a5822d7df15b612730c515610fcc171 Author: Jiri Slaby Date: Thu Jun 21 12:03:22 2007 +0200 get rid of ath5k_status diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 935b8fe..c37bb0a 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -264,7 +264,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; struct ath_hw *ah; - enum ath5k_status status; int error = 0, i; DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); @@ -273,9 +272,9 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) /* * Attach the hal */ - ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase, &status); - if (ah == NULL) { - error = ENXIO; + ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase); + if (IS_ERR(ah)) { + error = PTR_ERR(ah); goto bad; } sc->sc_ah = ah; diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 55e3df7..01f7d29 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -124,9 +124,6 @@ struct ath_buf { #endif }; -struct ath_hal; -struct ath_desc; - /* * Data transmit queue state. One of these exists for each * hardware transmit queue. Packets sent to us from above @@ -200,7 +197,7 @@ struct ath_softc { size_t sc_desc_len; /* size of TX/RX descriptors */ u16 sc_cachelsz; /* cache line size */ dma_addr_t sc_desc_daddr; /* DMA (physical) address */ - struct ath_hal *sc_ah; /* Atheros HAL */ + struct ath_hw *sc_ah; /* Atheros HAL */ struct ath_ratectrl *sc_rc; /* tx rate control support */ void (*sc_setdefantenna)(struct ath_softc *, u_int); unsigned int sc_invalid : 1, /* disable hardware accesses */ @@ -318,54 +315,54 @@ void ath_sysctl_register(void); void ath_sysctl_unregister(void); #define ath_hal_ciphersupported(_ah, _cipher) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_CIPHER, _cipher, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_CIPHER, _cipher, NULL) == 0) #define ath_hal_getregdomain(_ah, _prd) \ ath5k_hw_get_capability(_ah, AR5K_CAP_REG_DMN, 0, (_prd)) #define ath_hal_getcountrycode(_ah, _pcc) \ (*(_pcc) = (_ah)->ah_country_code) #define ath_hal_tkipsplit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == 0) #define ath_hal_hwphycounters(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == 0) #define ath_hal_hasdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == 0) #define ath_hal_getdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == 0) #define ath_hal_setdiversity(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_DIVERSITY, 1, _v, NULL) #define ath_hal_getdiag(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIAG, 0, _pv) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_DIAG, 0, _pv) == 0) #define ath_hal_setdiag(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_DIAG, 0, _v, NULL) #define ath_hal_getnumtxqueues(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == 0) #define ath_hal_hasveol(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) #define ath_hal_hastxpowlimit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 0, NULL) == 0) #define ath_hal_settxpowlimit(_ah, _pow) \ ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) #define ath_hal_gettxpowlimit(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == 0) #define ath_hal_getmaxtxpow(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == 0) #define ath_hal_gettpscale(_ah, _scale) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 3, _scale) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 3, _scale) == 0) #define ath_hal_settpscale(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_TXPOW, 3, _v, NULL) #define ath_hal_hastpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == 0) #define ath_hal_gettpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == 0) #define ath_hal_settpc(_ah, _v) \ ath5k_hw_set_capability(_ah, AR5K_CAP_TPC, 1, _v, NULL) #define ath_hal_hasbursting(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) #ifdef notyet #define ath_hal_hasmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == 0) #define ath_hal_getmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == AR5K_OK) + (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == 0) #else #define ath_hal_getmcastkeysearch(_ah) 0 #endif diff --git a/openhal/ath5k.h b/openhal/ath5k.h index aa3b8c3..5fe1004 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -96,22 +96,6 @@ #define howmany(x, y) (((x)+((y)-1))/(y)) /* - * Error codes reported from HAL to the driver - */ -enum ath5k_status { - AR5K_OK = 0, /* Everything went O.K.*/ - AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/ - AR5K_EIO = 2, /* Hardware I/O Error*/ - AR5K_EELOCKED = 3, /* Unable to access EEPROM*/ - AR5K_EEBADSUM = 4, /* Invalid EEPROM checksum*/ - AR5K_EEREAD = 5, /* Unable to get device caps from EEPROM */ - AR5K_EEBADMAC = 6, /* Unable to read MAC address from EEPROM */ - AR5K_EINVAL = 7, /* Invalid parameter to function */ - AR5K_ENOTSUPP = 8, /* Hardware revision not supported */ - AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */ -}; - -/* * Some tuneable values (these should be changeable by the user) */ #define AR5K_TUNE_DMA_BEACON_RESP 2 @@ -1054,10 +1038,9 @@ struct ath_hw { unsigned int, unsigned int); bool (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); - enum ath5k_status (*ah_proc_tx_desc)(struct ath_hw *, + int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); + int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); - enum ath5k_status (*ah_proc_rx_desc)(struct ath_hw *, - struct ath_desc *, u32, struct ath_desc *); }; /* @@ -1069,13 +1052,13 @@ typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ath5k_channel *, u_int); u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ -struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status); +struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh); //bool ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial); //u16 ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ -bool ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status); +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel); //bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ bool ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); @@ -1106,7 +1089,7 @@ int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_eeprom_init(struct ath_hw *hal); int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac); bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain); -bool ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, enum ath5k_status *status); +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); bool ath5k_hw_get_capabilities(struct ath_hw *hal); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); @@ -1197,8 +1180,8 @@ bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ void ath5k_hw_dump_state(struct ath_hw *hal); -enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result) ; -bool ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting, enum ath5k_status *status) ; +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); +int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting); bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); bool ath5k_hw_disable_pspoll(struct ath_hw *hal); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index a1473a1..f0e2516 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -92,20 +92,18 @@ static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int); static bool ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_4word_tx_status(struct ath_hw *, - struct ath_desc *); +static int ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *); static bool ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); static bool ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool, const struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_2word_tx_status(struct ath_hw *, +static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); +static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, + struct ath_desc *); +static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_new_rx_status(struct ath_hw *, - struct ath_desc *, u32, struct ath_desc *); -static enum ath5k_status ath5k_hw_proc_old_rx_status(struct ath_hw *, - struct ath_desc *, u32, struct ath_desc *); /* * Supported channels @@ -345,14 +343,13 @@ ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, * Check if the device is supported and initialize the needed structs */ struct ath_hw * -ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) +ath5k_hw_init(u16 device, void *sc, void __iomem *sh) { struct ath_hw *hal = NULL; u8 mac[ETH_ALEN]; u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ - int i; + int i, ret; u32 srev; - *status = AR5K_EINVAL; /*TODO:Use eeprom_magic to verify chipset*/ @@ -366,7 +363,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /*If there wasn't a match, the device is not supported*/ if (mac_version == 255) { - *status = AR5K_ENOTSUPP; + ret = -EOPNOTSUPP; AR5K_PRINTF("device not supported: 0x%04x\n", device); return NULL; } @@ -374,7 +371,7 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) /*If we passed the test malloc a hal struct*/ hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); if (hal == NULL) { - *status = AR5K_ENOMEM; + ret = -ENOMEM; AR5K_PRINT("out of memory\n"); return NULL; } @@ -501,22 +498,22 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) */ if (ath5k_eeprom_init(hal) != 0) { - *status = AR5K_EELOCKED; + ret = -EIO; AR5K_PRINT("unable to init EEPROM\n"); goto failed; } /* Get misc capabilities */ if (ath5k_hw_get_capabilities(hal) != true) { - *status = AR5K_EEREAD; + ret = -EIO; AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", device); goto failed; } /* Get MAC address */ - if ((*status = ath5k_eeprom_read_mac(hal, mac)) != 0) { - *status = AR5K_EEBADMAC; + if (ath5k_eeprom_read_mac(hal, mac)) { + ret = -EIO; AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", device); goto failed; @@ -555,13 +552,11 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh, enum ath5k_status *status) hal->ah_gain.g_active = 1; } - *status = AR5K_OK; - return hal; failed: kfree(hal); - return NULL; + return ERR_PTR(ret); } /* @@ -797,9 +792,8 @@ ath5k_hw_detach(struct ath_hw *hal) /* * Main reset function */ -bool -ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, - struct ath5k_channel *channel, bool change_channel, enum ath5k_status *status) +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, + struct ath5k_channel *channel, bool change_channel) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u8 mac[ETH_ALEN]; @@ -809,7 +803,6 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_TRACE; - *status = AR5K_OK; s_seq = 0; s_ant = 1; ee_mode = 0; @@ -840,10 +833,8 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Wakeup the device*/ - if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) { - *status = AR5K_EIO; - return false; - } + if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) + return -EIO; /* * Initialize operating mode @@ -861,8 +852,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, phy = AR5K_INI_PHY_5112; else { AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); - *status = AR5K_EINVAL; - return false; + return -EINVAL; } switch (channel->channel_flags & CHANNEL_MODES) { @@ -895,7 +885,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, case CHANNEL_XR: if (hal->ah_version == AR5K_AR5211) { AR5K_PRINTF("XR mode not available on 5211"); - return false; + return -EINVAL; } mode = AR5K_INI_VAL_XR; freq = AR5K_INI_RFGAIN_5GHZ; @@ -903,8 +893,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, break; default: AR5K_PRINTF("invalid channel: %d\n", channel->freq); - *status = AR5K_EINVAL; - return false; + return -EINVAL; } /* PHY access enable */ @@ -1015,8 +1004,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * This should work for both 5111/5112 */ if (ath5k_hw_rfgain(hal, phy, freq) == false) { - *status = AR5K_EIO; - return false; + return -EIO; } mdelay(1); @@ -1081,8 +1069,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, */ if (ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER) == false) { - *status = AR5K_EIO; - return false; + return -EIO; } /* @@ -1090,8 +1077,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * TODO:Does this work on 5211 (5111) ? */ if (ath5k_hw_rfregs(hal, channel, mode) == false) { - *status = AR5K_EINPROGRESS; - return false; + return -EINPROGRESS; } /* @@ -1112,8 +1098,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, break; if (!coef_exp) { - *status = AR5K_EINVAL; - return false; + return -EINVAL; } coef_exp = 14 - (coef_exp - 24); @@ -1244,10 +1229,8 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Set channel and calibrate the PHY */ - if (ath5k_hw_channel(hal, channel) == false) { - *status = AR5K_EIO; - return false; - } + if (ath5k_hw_channel(hal, channel) == false) + return -EIO; /* * Enable the PHY and wait until completion @@ -1277,7 +1260,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_CAL, 0, false) == false) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); - return false; + return -EAGAIN; } /* @@ -1290,7 +1273,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_NF, 0, false) == false) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return false; + return -EAGAIN; } /* Wait until the noise floor is calibrated and read the value */ @@ -1309,7 +1292,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return false; + return -EIO; } hal->ah_calibration = false; @@ -1332,8 +1315,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_reset_tx_queue(hal, i) == false) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); - *status = AR5K_EINVAL; - return false; + return -EINVAL; } } @@ -1376,7 +1358,7 @@ ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_REG_DISABLE_BITS(AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); - return true; + return 0; } /* @@ -2497,12 +2479,12 @@ ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) memset(&mac_d, 0, ETH_ALEN); if (ath5k_hw_eeprom_read(hal, 0x20, &data) != 0) - return AR5K_EIO; + return -EIO; for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { if (ath5k_hw_eeprom_read(hal, offset, &data) != 0) - return AR5K_EIO; + return -EIO; total += data; mac_d[octet + 1] = data & 0xff; @@ -2513,7 +2495,7 @@ ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) memcpy(mac, mac_d, ETH_ALEN); if ((!total) || total == (3 * 0xffff)) - return AR5K_EINVAL; + return -EINVAL; return 0; } @@ -2552,22 +2534,16 @@ ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, /* * Use the above to write a new regulatory domain */ -bool -ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain, - enum ath5k_status *status) +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain) { enum ieee80211_regdomain ieee_regdomain; ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); - if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true){ - *status = AR5K_OK; - return true; - } - - *status = AR5K_EIO; + if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true) + return 0; - return false; + return -EIO; } /* @@ -4176,8 +4152,8 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, /* * Proccess the tx status descriptor on 5210/5211 */ -static enum ath5k_status -ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) +static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, + struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_2w_tx_desc *tx_desc; @@ -4187,7 +4163,7 @@ ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Get descriptor status @@ -4229,14 +4205,14 @@ ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return AR5K_OK; + return 0; } /* * Proccess a tx descriptor on 5212 */ -static enum ath5k_status -ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) +static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, + struct ath_desc *desc) { struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4247,7 +4223,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Get descriptor status @@ -4318,7 +4294,7 @@ ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath_desc *desc) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return AR5K_OK; + return 0; } /* @@ -4364,9 +4340,8 @@ ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, /* * Proccess the rx status descriptor on 5210/5211 */ -static enum ath5k_status -ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, - u32 phys_addr, struct ath_desc *next) +static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, + struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_old_rx_status *rx_status; @@ -4374,7 +4349,7 @@ ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Frame receive status @@ -4433,15 +4408,14 @@ ath5k_hw_proc_old_rx_status(struct ath_hw *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; } - return AR5K_OK; + return 0; } /* * Proccess the rx status descriptor on 5212 */ -static enum ath5k_status -ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, - u32 phys_addr, struct ath_desc *next) +static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, + struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) { struct ath5k_hw_new_rx_status *rx_status; struct ath5k_hw_rx_error *rx_err; @@ -4454,7 +4428,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) - return AR5K_EINPROGRESS; + return -EINPROGRESS; /* * Frame receive status @@ -4513,7 +4487,7 @@ ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath_desc *desc, desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } - return AR5K_OK; + return 0; } @@ -6160,9 +6134,9 @@ ath5k_hw_dump_state(struct ath_hw *hal) #endif } -enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, - u32 capability, u32 *result) + u32 capability, u32 *result) { AR5K_TRACE; @@ -6213,23 +6187,19 @@ enum ath5k_status ath5k_hw_get_capability(struct ath_hw *hal, } no: - return AR5K_EINVAL; + return -EINVAL; yes: - return AR5K_OK; + return 0; } -bool -ath5k_hw_set_capability(struct ath_hw *hal, +int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, - u32 capability, u32 setting, - enum ath5k_status *status) + u32 capability, u32 setting) { AR5K_TRACE; - if (status) - *status = AR5K_OK; - return false; + return 0; } bool commit fda53aa14f88128d0be6e79f4b2bcbd0d2efad08 Author: Jiri Slaby Date: Thu Jun 21 12:50:48 2007 +0200 involve hw_attach and detach (i.e. we now inits the card) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c37bb0a..2ec4b0c 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -156,7 +156,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) { struct net_device *dev = dev_id; struct ath_softc *sc = dev->priv; - struct ath_hw *ah = sc->sc_ah; + struct ath_hw *ah = sc->ah; enum ath5k_int status; int needmark; @@ -263,23 +263,13 @@ static irqreturn_t ath_intr(int irq, void *dev_id) static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; - struct ath_hw *ah; + struct ath_hw *ah = sc->ah; int error = 0, i; DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); return 0; /* - * Attach the hal - */ - ah = ath5k_hw_init(pdev->device, sc, sc->sc_iobase); - if (IS_ERR(ah)) { - error = PTR_ERR(ah); - goto bad; - } - sc->sc_ah = ah; - - /* * Check if the MAC has multi-rate retry support. * We do this by trying to setup a fake extended * descriptor. MAC's that don't have support will @@ -638,11 +628,6 @@ bad2: ath_tx_cleanup(sc); ath_desc_free(sc); #endif -bad: - if (ah) { - ath5k_hw_detach(ah); - } - sc->sc_invalid = 1; return error; } @@ -667,7 +652,6 @@ static void ath_detach(struct ieee80211_hw *hw) // ath_rate_detach(sc->sc_rc); // ath_desc_free(sc); // ath_tx_cleanup(sc); -// ath5k_hw_detach(sc->sc_ah); /* * NB: can't reclaim these until after ieee80211_ifdetach @@ -675,7 +659,6 @@ static void ath_detach(struct ieee80211_hw *hw) * state and potentially want to use them. */ // ath_dynamic_sysctl_unregister(sc); -// ath_rawdev_detach(sc); // unregister_netdev(dev); } @@ -774,7 +757,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, * interrupts until setup is complete. */ sc->sc_invalid = 1; - sc->sc_iobase = mem; + sc->iobase = mem; sc->sc_cachelsz = csz * sizeof(u32); /* convert to bytes */ mutex_init(&sc->lock); spin_lock_init(&sc->sc_txbuflock); @@ -794,9 +777,15 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, goto err_free; } + sc->ah = ath5k_hw_attach(pdev->device, id->driver_data, sc, sc->iobase); + if (IS_ERR(sc->ah)) { + ret = PTR_ERR(sc->ah); + goto err_irq; + } + ret = ath_attach(pdev, hw); if (ret) - goto err_irq; + goto err_ah; dev_info(&pdev->dev, "%s chip found\n", ath_chip_name(id->driver_data)); @@ -804,6 +793,8 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, sc->sc_invalid = 0; return 0; +err_ah: + ath5k_hw_detach(sc->ah); err_irq: free_irq(pdev->irq, sc); err_free: @@ -824,8 +815,9 @@ static void __devexit ath_pci_remove(struct pci_dev *pdev) struct ath_softc *sc = hw->priv; ath_detach(hw); + ath5k_hw_detach(sc->ah); free_irq(pdev->irq, sc); - pci_iounmap(pdev, sc->sc_iobase); + pci_iounmap(pdev, sc->iobase); pci_release_region(pdev, 0); pci_disable_device(pdev); ieee80211_free_hw(hw); @@ -838,7 +830,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) struct ath_softc *sc = hw->priv; if (sc->sc_softled) - ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, 1); + ath5k_hw_set_gpio(sc->ah, sc->sc_ledpin, 1); // ath_stop(hw); pci_save_state(pdev); @@ -872,8 +864,8 @@ static int ath_pci_resume(struct pci_dev *pdev) // ath_init(hw); if (sc->sc_softled) { - ath5k_hw_set_gpio_output(sc->sc_ah, sc->sc_ledpin); - ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, 0); + ath5k_hw_set_gpio_output(sc->ah, sc->sc_ledpin); + ath5k_hw_set_gpio(sc->ah, sc->sc_ledpin, 0); } return 0; diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 01f7d29..decb45a 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -174,11 +174,12 @@ struct ath_txq { } while (0) struct ath_softc { - void __iomem *sc_iobase; /* address of the device */ + void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ // struct net_device_stats sc_devstats; /* device statistics */ struct ath_stats sc_stats; /* private statistics */ struct ieee80211_hw *hw; /* IEEE 802.11 common */ + struct ath_hw *ah; /* Atheros HW */ enum ieee80211_if_types sc_opmode; int sc_regdomain; @@ -197,7 +198,6 @@ struct ath_softc { size_t sc_desc_len; /* size of TX/RX descriptors */ u16 sc_cachelsz; /* cache line size */ dma_addr_t sc_desc_daddr; /* DMA (physical) address */ - struct ath_hw *sc_ah; /* Atheros HAL */ struct ath_ratectrl *sc_rc; /* tx rate control support */ void (*sc_setdefantenna)(struct ath_softc *, u_int); unsigned int sc_invalid : 1, /* disable hardware accesses */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 5fe1004..f40d7ec 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -943,8 +943,6 @@ struct ath5k_capabilities { struct ath_hw { u32 ah_magic; - u16 ah_device; - u16 ah_sub_vendor; void *ah_sc; void __iomem *ah_sh; @@ -1052,16 +1050,14 @@ typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ath5k_channel *, u_int); u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ -struct ath_hw *ath5k_hw_init(u16 device, void *sc, void __iomem *sh); -//bool ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial); -//u16 ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip); +struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel); //bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ -bool ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); /* DMA Related Functions */ void ath5k_hw_start_rx(struct ath_hw *hal); @@ -1080,17 +1076,11 @@ u32 ath5k_hw_get_intr(struct ath_hw *hal); enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ -bool ath5k_hw_eeprom_is_busy(struct ath_hw *hal); -int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data); -int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data); u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_init(struct ath_hw *hal); -int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac); bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain); int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); -bool ath5k_hw_get_capabilities(struct ath_hw *hal); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); void ath5k_hw_set_pcu_config(struct ath_hw *hal); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index f0e2516..8318143 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -78,8 +78,8 @@ static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ -static bool ath5k_hw_nic_reset(struct ath_hw *, u32); -static bool ath5k_hw_nic_wakeup(struct ath_hw *, u16, bool); +static int ath5k_hw_nic_reset(struct ath_hw *, u32); +static int ath5k_hw_nic_wakeup(struct ath_hw *, u16, bool); static u16 ath5k_hw_radio_revision(struct ath_hw *, enum ath5k_chip); static bool ath5k_hw_txpower(struct ath_hw *, struct ath5k_channel *, unsigned int); @@ -104,6 +104,10 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); +static int ath5k_hw_get_capabilities(struct ath_hw *); + +static int ath5k_eeprom_init(struct ath_hw *); +static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *); /* * Supported channels @@ -311,9 +315,8 @@ static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) /* * Check if a register write has been completed */ -static bool -ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, - u32 val, bool is_set) +static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, + u32 val, bool is_set) { int i; u32 data; @@ -327,10 +330,7 @@ ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, udelay(15); } - if (i <= 0) - return false; - - return true; + return (i <= 0) ? -EAGAIN : 0; } @@ -342,44 +342,26 @@ ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, /* * Check if the device is supported and initialize the needed structs */ -struct ath_hw * -ath5k_hw_init(u16 device, void *sc, void __iomem *sh) +struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, + void __iomem *sh) { - struct ath_hw *hal = NULL; + struct ath_hw *hal; u8 mac[ETH_ALEN]; - u8 mac_version = 255; /*Initialize this to something else than ath5k_version*/ - int i, ret; + int ret; u32 srev; /*TODO:Use eeprom_magic to verify chipset*/ - /* - * Check if device is a known one - */ - for (i = 0; i < ARRAY_SIZE(ath5k_known_products); i++) { - if (device == ath5k_known_products[i].device) - mac_version = ath5k_known_products[i].mac_version; - } - - /*If there wasn't a match, the device is not supported*/ - if (mac_version == 255) { - ret = -EOPNOTSUPP; - AR5K_PRINTF("device not supported: 0x%04x\n", device); - return NULL; - } - /*If we passed the test malloc a hal struct*/ hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); if (hal == NULL) { ret = -ENOMEM; AR5K_PRINT("out of memory\n"); - return NULL; + goto err; } hal->ah_sc = sc; hal->ah_sh = sh; - hal->ah_device = device; - hal->ah_sub_vendor = 0; /* XXX unknown?! */ /* * HAL information @@ -447,24 +429,24 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; /* Bring device out of sleep and reset it's units */ - if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true) != true) - goto failed; + ret = ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true); + if (ret) + goto err_free; /* Get MAC, PHY and RADIO revisions */ srev = AR5K_REG_READ(AR5K_SREV); hal->ah_mac_srev = srev; hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); - hal->ah_phy_revision = - AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; - hal->ah_radio_5ghz_revision = - ath5k_hw_radio_revision(hal, AR5K_CHIP_5GHZ); + hal->ah_phy_revision = AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; + hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal, + AR5K_CHIP_5GHZ); if (hal->ah_version == AR5K_AR5210) { hal->ah_radio_2ghz_revision = 0; } else { - hal->ah_radio_2ghz_revision = - ath5k_hw_radio_revision(hal, AR5K_CHIP_2GHZ); + hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal, + AR5K_CHIP_2GHZ); } /* Single chip radio */ @@ -475,8 +457,8 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) if (hal->ah_version == AR5K_AR5210) hal->ah_radio = AR5K_RF5110; else - hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ? - AR5K_RF5111 : AR5K_RF5112; + hal->ah_radio = hal->ah_radio_5ghz_revision < + AR5K_SREV_RAD_5112 ? AR5K_RF5111 : AR5K_RF5112; hal->ah_phy = AR5K_PHY(0); @@ -497,26 +479,26 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) * Get card capabilities, values, ... */ - if (ath5k_eeprom_init(hal) != 0) { - ret = -EIO; + ret = ath5k_eeprom_init(hal); + if (ret) { AR5K_PRINT("unable to init EEPROM\n"); - goto failed; + goto err_free; } /* Get misc capabilities */ - if (ath5k_hw_get_capabilities(hal) != true) { - ret = -EIO; + ret = ath5k_hw_get_capabilities(hal); + if (ret) { AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", - device); - goto failed; + device); + goto err_free; } /* Get MAC address */ - if (ath5k_eeprom_read_mac(hal, mac)) { - ret = -EIO; + ret = ath5k_eeprom_read_mac(hal, mac); + if (ret) { AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", - device); - goto failed; + device); + goto err_free; } ath5k_hw_set_lladdr(hal, mac); @@ -553,19 +535,19 @@ ath5k_hw_init(u16 device, void *sc, void __iomem *sh) } return hal; - - failed: +err_free: kfree(hal); +err: return ERR_PTR(ret); } /* * Bring up MAC + PHY Chips */ -static bool -ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) +static int ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) { u32 turbo, mode, clock; + int ret; turbo = 0; mode = 0; @@ -594,7 +576,7 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) clock |= AR5K_PHY_PLL_40MHZ; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return false; + return -EINVAL; } if (flags & CHANNEL_CCK) { @@ -610,7 +592,7 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) mode |= AR5K_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return false; + return -EINVAL; } if (flags & CHANNEL_TURBO) { @@ -626,20 +608,19 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) else { if (initial == true) { /* ...reset hardware */ - if (ath5k_hw_nic_reset(hal, - AR5K_RESET_CTL_PCI) == false) { + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) { AR5K_PRINT("failed to reset the PCI chipset\n"); - return false; + return -EIO; } mdelay(1); } /* ...wakeup */ - if (ath5k_hw_set_power(hal, - AR5K_PM_AWAKE, true, 0) == false) { + ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); + if (ret) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return false; + return ret; } /* ...enable Atheros turbo mode if requested */ @@ -647,35 +628,35 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE); /* ...reset chipset */ - if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == false) { + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) { AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return false; + return -EIO; } mdelay(1); } /* ...reset chipset and PCI device */ - if (hal->ah_single_chip == false && - ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == false) { + if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal, + AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) { AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); - return false; + return -EIO; } if (hal->ah_version == AR5K_AR5210) udelay(2300); /* ...wakeup */ - if (ath5k_hw_set_power(hal, - AR5K_PM_AWAKE, true, 0) == false) { + ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); + if (ret) { AR5K_PRINT("failed to resume the MAC Chip\n"); - return false; + return ret; } /* ...final warm reset */ - if (ath5k_hw_nic_reset(hal, 0) == false) { + if (ath5k_hw_nic_reset(hal, 0)) { AR5K_PRINT("failed to warm reset the MAC Chip\n"); - return false; + return -EIO; } if (hal->ah_version != AR5K_AR5210){ @@ -687,7 +668,7 @@ ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); } - return true; + return 0; } /* @@ -770,8 +751,7 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) /* * Free the hal struct */ -void -ath5k_hw_detach(struct ath_hw *hal) +void ath5k_hw_detach(struct ath_hw *hal) { AR5K_TRACE; @@ -782,9 +762,6 @@ ath5k_hw_detach(struct ath_hw *hal) kfree(hal); } - - - /*******************************\ Reset Functions \*******************************/ @@ -1257,7 +1234,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, false) == false) { + AR5K_PHY_AGCCTL_CAL, 0, false)) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); return -EAGAIN; @@ -1270,7 +1247,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, false) == false) { + AR5K_PHY_AGCCTL_NF, 0, false)) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); return -EAGAIN; @@ -1364,10 +1341,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Reset chipset */ -static bool -ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) +static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) { - bool ret = false; + int ret; u32 mask = val ? val : ~0; AR5K_TRACE; @@ -1412,8 +1388,7 @@ ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) /* * Sleep control */ -bool -ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration) { u32 staid; @@ -1462,21 +1437,20 @@ ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, /* Fail if the chip didn't wake up */ if (i <= 0) - return false; + return -EIO; staid &= ~AR5K_STA_ID1_PWR_SV; break; default: - return false; + return -EINVAL; } - commit: +commit: hal->ah_power_mode = mode; - AR5K_REG_WRITE(AR5K_STA_ID1, staid); - return true; + return 0; } /* @@ -2004,20 +1978,9 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) \*************************/ /* - * Check if eeprom is busy - */ -bool -ath5k_hw_eeprom_is_busy(struct ath_hw *hal) -{ - AR5K_TRACE; - return AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? true : false; -} - -/* * Read from eeprom */ -int -ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) +static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) { u32 status, timeout; @@ -2038,7 +2001,7 @@ ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) - return EIO; + return -EIO; *data = (u16) (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); return 0; @@ -2046,14 +2009,13 @@ ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) udelay(15); } - return ETIMEDOUT; + return -ETIMEDOUT; } /* * Write to eeprom - currently disabled, use at your own risk */ -int -ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) +static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) { #if 0 u32 status, timeout; @@ -2097,7 +2059,7 @@ ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) } #endif AR5K_PRINTF("EEPROM Write is disabled!"); - return ETIMEDOUT; + return -EIO; } u16 @@ -2271,8 +2233,7 @@ ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode) /* * Initialize eeprom & capabilities structs */ -int -ath5k_eeprom_init(struct ath_hw *hal) +static int ath5k_eeprom_init(struct ath_hw *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 offset; @@ -2309,7 +2270,7 @@ ath5k_eeprom_init(struct ath_hw *hal) } if (cksum != AR5K_EEPROM_INFO_CKSUM) { AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); - return AR5K_EEBADSUM; + return -EIO; } #endif @@ -2353,7 +2314,8 @@ ath5k_eeprom_init(struct ath_hw *hal) offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) return ret; AR5K_EEPROM_READ(offset++, val); @@ -2370,7 +2332,8 @@ ath5k_eeprom_init(struct ath_hw *hal) ee->ee_ob[mode][0] = (val >> 3) & 0x7; ee->ee_db[mode][0] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { @@ -2384,7 +2347,8 @@ ath5k_eeprom_init(struct ath_hw *hal) mode = AR5K_EEPROM_MODE_11B; offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) return ret; AR5K_EEPROM_READ(offset++, val); @@ -2392,7 +2356,8 @@ ath5k_eeprom_init(struct ath_hw *hal) ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { @@ -2417,7 +2382,8 @@ ath5k_eeprom_init(struct ath_hw *hal) mode = AR5K_EEPROM_MODE_11G; offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) return ret; AR5K_EEPROM_READ(offset++, val); @@ -2425,7 +2391,8 @@ ath5k_eeprom_init(struct ath_hw *hal) ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) return ret; if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { @@ -2467,24 +2434,25 @@ ath5k_eeprom_init(struct ath_hw *hal) /* * Read the MAC address from eeprom */ -int -ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) +static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) { + u8 mac_d[ETH_ALEN]; u32 total, offset; u16 data; - int octet; - u8 mac_d[ETH_ALEN]; + int octet, ret; memset(mac, 0, ETH_ALEN); memset(&mac_d, 0, ETH_ALEN); - if (ath5k_hw_eeprom_read(hal, 0x20, &data) != 0) - return -EIO; + ret = ath5k_hw_eeprom_read(hal, 0x20, &data); + if (ret) + return ret; for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { - if (ath5k_hw_eeprom_read(hal, offset, &data) != 0) - return -EIO; + ret = ath5k_hw_eeprom_read(hal, offset, &data); + if (ret) + return ret; total += data; mac_d[octet + 1] = data & 0xff; @@ -2494,7 +2462,7 @@ ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) memcpy(mac, mac_d, ETH_ALEN); - if ((!total) || total == (3 * 0xffff)) + if (!total || total == 3 * 0xffff) return -EINVAL; return 0; @@ -2549,8 +2517,7 @@ int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain) /* * Fill the capabilities struct */ -bool -ath5k_hw_get_capabilities(struct ath_hw *hal) +static int ath5k_hw_get_capabilities(struct ath_hw *hal) { u16 ee_header; @@ -2616,7 +2583,7 @@ ath5k_hw_get_capabilities(struct ath_hw *hal) else hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; - return true; + return 0; } /*********************************\ @@ -3204,7 +3171,7 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) /*5211/5212*/ ret = ath5k_hw_register_timeout(hal, AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), - AR5K_QCU_STS_FRMPENDCNT, 0, false); + AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true; if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) return false; @@ -5222,7 +5189,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, false) == false) { + AR5K_PHY_AGCCTL_CAL, 0, false)) { AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); ret = false; @@ -5243,7 +5210,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, false) == false) { + AR5K_PHY_AGCCTL_NF, 0, false)) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); return false; commit ba1084e4fd93cc0089107da702badec88064caaa Author: Jiri Slaby Date: Thu Jun 21 20:25:29 2007 +0200 remove ath/ath_hw.h diff --git a/ath/ath_hw.h b/ath/ath_hw.h deleted file mode 100644 index 9ac6027..0000000 --- a/ath/ath_hw.h +++ /dev/null @@ -1,75 +0,0 @@ -/*- - * Copyright (c) 2007 Pavel Roskin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -#ifndef _ATH_HW_H -#define _ATH_HW_H - -#define ATH_HW_IRQ_PENDING 0x4008 -# define ATH_HW_IRQ_PENDING_FALSE 0 -# define ATH_HW_IRQ_PENDING_TRUE 1 - -struct ath_hal; - -/* - * Read from a device register - */ -static inline u32 ath_hw_reg_read(struct ath_hal *hw, u16 reg) -{ - return readl(hw->ah_sh + reg); -} - -/* - * Write to a device register - */ -static inline void ath_hw_reg_write(struct ath_hal *hw, u32 val, u16 reg) -{ - writel(val, hw->ah_sh + reg); -} - -/* - * Check if there is an interrupt waiting to be processed. - * Return 1 if there is an interrupt for us, or 0 if there is none or if - * the device has been removed. - */ -static inline int ath_hw_irq_pending(struct ath_hal *hw) -{ - if (ath_hw_reg_read(hw, ATH_HW_IRQ_PENDING) == ATH_HW_IRQ_PENDING_TRUE) - return 1; - else - return 0; -} - -#endif /* _ATH_HW_H */ commit ac1bb8018d8c92fec4915055f26a52ce4ac888f4 Author: Jiri Slaby Date: Fri Jun 22 10:54:12 2007 +0200 compute channels. this was hmm hard, very hard. also get rid of ath5k_channel (and use ieee80211_channel) diff --git a/ath/if_ath.c b/ath/if_ath.c index f342270..02518fe 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -69,13 +69,6 @@ #include "ath5k.h" #include "ath_hw.h" -#define KASSERT(exp, msg...) do { \ - if (unlikely(!(exp))) { \ - printk(msg); \ - BUG(); \ - } \ -} while (0) - /* unaligned little endian access */ #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) @@ -2999,84 +2992,6 @@ ath_descdma_cleanup(struct ath_softc *sc, struct list_head *head) #endif } -static int -ath_desc_alloc(struct ath_softc *sc) -{ -#define DS2PHYS(_sc, _ds) \ - ((_sc)->sc_desc_daddr + ((caddr_t)(_ds) - (caddr_t)(_sc)->sc_desc)) - int bsize; - struct ath_desc *ds; - struct ath_buf *bf; - int i; - - /* allocate descriptors */ - sc->sc_desc_len = sizeof(struct ath_desc) * - (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); - barrier(); /* get_order() rounds down constants before Linux 2.6.21 */ - sc->sc_desc = bus_alloc_consistent(sc->sc_bdev, - sc->sc_desc_len, &sc->sc_desc_daddr); - if (sc->sc_desc == NULL) { - printk(KERN_ERR "%s, could not allocate descriptors\n", __func__); - return ENOMEM; - } - ds = sc->sc_desc; - DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%u) -> %llx\n", - __func__, ds, (unsigned int) sc->sc_desc_len, - (unsigned long long)sc->sc_desc_daddr); - - /* allocate buffers */ - bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); - bf = kmalloc(bsize, GFP_KERNEL); - if (bf == NULL) - goto bad; - memset(bf, 0, bsize); - sc->sc_bufptr = bf; - -// STAILQ_INIT(&sc->sc_rxbuf); - for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { - bf->bf_desc = ds; - bf->bf_daddr = DS2PHYS(sc, ds); -// STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); - } - -// STAILQ_INIT(&sc->sc_txbuf); - for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { - bf->bf_desc = ds; - bf->bf_daddr = DS2PHYS(sc, ds); -// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); - } - -// STAILQ_INIT(&sc->sc_bbuf); - for (i = 0; i < ATH_BCBUF; i++, bf++, ds++) { - bf->bf_desc = ds; - bf->bf_daddr = DS2PHYS(sc, ds); -// STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); - } - - return 0; -bad: - bus_free_consistent(sc->sc_bdev, sc->sc_desc_len, - sc->sc_desc, sc->sc_desc_daddr); - sc->sc_desc = NULL; - return ENOMEM; -#undef DS2PHYS -} - -static void -ath_desc_free(struct ath_softc *sc) -{ - ath_descdma_cleanup(sc, sc->sc_bbuf); - ath_descdma_cleanup(sc, sc->sc_txbuf); - ath_descdma_cleanup(sc, sc->sc_rxbuf); - - /* Free memory associated with all descriptors */ - bus_free_consistent(sc->sc_bdev, sc->sc_desc_len, - sc->sc_desc, sc->sc_desc_daddr); - - kfree(sc->sc_bufptr); - sc->sc_bufptr = NULL; -} - #ifdef BLE static struct ieee80211_node * ath_node_alloc(struct ieee80211_node_table *nt) @@ -5381,59 +5296,6 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) } } #endif -static int -ath_getchannels(struct ieee80211_hw *hw, u_int cc, - bool outdoor, bool xchanmode) -{ - struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; - struct ath5k_channel *chans; - int i, ix; - u_int nchan; -#define IEEE80211_CHAN_MAX 255 - chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(struct ath5k_channel), GFP_KERNEL); - if (chans == NULL) { - printk(KERN_ERR "unable to allocate channel table\n"); - return ENOMEM; - } - if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, - cc, AR5K_MODE_ALL, outdoor, xchanmode)) { - u_int32_t rd; - - ath_hal_getregdomain(ah, &rd); - printk(KERN_ERR "unable to collect channel list from hal; " - "regdomain likely %u country code %u\n", rd, cc); - kfree(chans); - return EINVAL; - } - - /* - * Convert HAL channels to ieee80211 ones and insert - * them in the table according to their channel number. - */ - for (i = 0; i < nchan; i++) { - struct ath5k_channel *c = &chans[i]; - ix = ath_hal_mhz2ieee(c->freq, c->channel_flags); - if (ix > IEEE80211_CHAN_MAX) { - printk(KERN_ERR "bad hal channel %u (%u/%x) ignored\n", - ix, c->freq, c->channel_flags); - continue; - } -#ifdef BLE - /* NB: flags are known to be compatible */ - if (ic->ic_channels[ix].ic_freq == 0) { - ic->ic_channels[ix].ic_freq = c->freq; - ic->ic_channels[ix].ic_flags = c->channel_flags; - } else { - /* channels overlap; e.g. 11g and 11b */ - ic->ic_channels[ix].ic_flags |= c->channel_flags; - } -#endif - } - kfree(chans); - return 0; -#undef IEEE80211_CHAN_MAX -} /* * Turn the LED off: flip the pin and then set a timer so no @@ -5512,130 +5374,6 @@ ath_update_txpow(struct ath_softc *sc) #endif } -static int -ath_rate_setup(struct ieee80211_hw *dev, u_int mode) -{ - struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; - const struct ath5k_rate_table *rt; -// struct ieee80211_rateset *rs; -// int i, maxrates; - - switch (mode) { - case MODE_IEEE80211A: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A); - break; - case MODE_IEEE80211B: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11B); - break; - case MODE_IEEE80211G: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11G); - break; - case MODE_ATHEROS_TURBO: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_TURBO); - break; - case MODE_ATHEROS_TURBOG: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_108G); - break; - default: - DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", - __func__, mode); - return 0; - } - rt = sc->sc_rates[mode]; - if (rt == NULL) - return 0; -#ifdef BLE - if (rt->rate_count > IEEE80211_RATE_MAXSIZE) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: rate table too small (%u > %u)\n", - __func__, rt->rate_count, IEEE80211_RATE_MAXSIZE); - maxrates = IEEE80211_RATE_MAXSIZE; - } else - maxrates = rt->rate_count; - rs = &ic->ic_sup_rates[mode]; - for (i = 0; i < maxrates; i++) - rs->rs_rates[i] = rt->rates[i].dot11_rate; - rs->rs_nrates = maxrates; -#endif - return 1; -} - -static void -ath_setcurmode(struct ath_softc *sc, unsigned int mode) -{ -#define N(a) (sizeof(a)/sizeof(a[0])) - /* NB: on/off times from the Atheros NDIS driver, w/ permission */ -#ifdef BLE - static const struct { - u_int rate; /* tx/rx 802.11 rate */ - u_int16_t timeOn; /* LED on time (ms) */ - u_int16_t timeOff; /* LED off time (ms) */ - } blinkrates[] = { - { 108, 40, 10 }, - { 96, 44, 11 }, - { 72, 50, 13 }, - { 48, 57, 14 }, - { 36, 67, 16 }, - { 24, 80, 20 }, - { 22, 100, 25 }, - { 18, 133, 34 }, - { 12, 160, 40 }, - { 10, 200, 50 }, - { 6, 240, 58 }, - { 4, 267, 66 }, - { 2, 400, 100 }, - { 0, 500, 130 }, - }; -#endif - const struct ath5k_rate_table *rt; -// int i, j; - - memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); - rt = sc->sc_rates[mode]; - KASSERT(rt != NULL, "no h/w rate set for phy mode %u", mode); -#ifdef BLE - for (i = 0; i < rt->rate_count; i++) - sc->sc_rixmap[rt->rates[i].dot11_rate & IEEE80211_RATE_VAL] = i; - memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); - for (i = 0; i < 32; i++) { - u_int8_t ix = rt->rate_code_to_index[i]; - if (ix == 0xff) { - sc->sc_hwmap[i].ledon = (500 * HZ) / 1000; - sc->sc_hwmap[i].ledoff = (130 * HZ) / 1000; - continue; - } - sc->sc_hwmap[i].ieeerate = - rt->rates[ix].dot11_rate & IEEE80211_RATE_VAL; - sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; - if (SHPREAMBLE_FLAG(ix) || - rt->rates[ix].modulation == MODULATION_OFDM) - sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; - /* NB: receive frames include FCS */ - sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | - IEEE80211_RADIOTAP_F_FCS; - /* setup blink rate table to avoid per-packet lookup */ - for (j = 0; j < N(blinkrates)-1; j++) - if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) - break; - /* NB: this uses the last entry if the rate isn't found */ - /* XXX beware of overlow */ - sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * HZ) / 1000; - sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * HZ) / 1000; - } -#endif - sc->sc_currates = rt; - sc->sc_curmode = mode; - /* - * All protection frames are transmited at 2Mb/s for - * 11g, otherwise at 1Mb/s. - * XXX select protection rate index from rate table. - */ - sc->sc_protrix = ((mode == MODE_IEEE80211G || mode == MODE_ATHEROS_TURBOG) ? 1 : 0); - /* NB: caller is responsible for reseting rate control state */ -#undef N -} - #ifdef BLE static int ath_rawdev_attach(struct ath_softc *sc) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 2ec4b0c..6a65fe7 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -37,6 +37,15 @@ #include "if_athvar.h" #include "if_ath_pci.h" +#define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ + +#define KASSERT(exp, msg...) do { \ + if (unlikely(!(exp))) { \ + printk(msg); \ + BUG(); \ + } \ +} while (0) + #define DPRINTF(sc, _m, _fmt...) do { \ if (sc->sc_debug & (_m)) \ printk(_fmt); \ @@ -136,18 +145,6 @@ static inline void ath_hw_reg_write(struct ath_hw *hw, u32 val, u16 reg) } #define ATH_HW_IRQ_PENDING 0x4008 -# define ATH_HW_IRQ_PENDING_FALSE 0 -# define ATH_HW_IRQ_PENDING_TRUE 1 - -/* - * Check if there is an interrupt waiting to be processed. - * Return 1 if there is an interrupt for us, or 0 if there is none or if - * the device has been removed. - */ -static inline int ath_hw_irq_pending(struct ath_hw *hw) -{ - return ath_hw_reg_read(hw, ATH_HW_IRQ_PENDING) == ATH_HW_IRQ_PENDING_TRUE; -} /* * Interrupt handler. Most of the actual processing is deferred. @@ -168,10 +165,9 @@ static irqreturn_t ath_intr(int irq, void *dev_id) DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); return IRQ_NONE; } - return IRQ_HANDLED; - - if (!ath_hw_irq_pending(ah)) /* shared irq, not for us */ + if (!ath_hw_reg_read(ah, ATH_HW_IRQ_PENDING)) return IRQ_NONE; +return IRQ_HANDLED; if ((dev->flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", __func__, dev->flags); @@ -260,14 +256,413 @@ static irqreturn_t ath_intr(int irq, void *dev_id) return IRQ_HANDLED; } +/* + * Convert IEEE channel number to MHz frequency. + */ +static inline short ath_ieee2mhz(short chan) +{ + if (chan <= 14 || chan >= 27) + return ieee80211chan2mhz(chan); + else + return 2212 + chan * 20; +} + +static inline unsigned int ath_copy_rates(struct ieee80211_rate *rates, + const struct ath5k_rate_table *rt) +{ + unsigned int i; + + for (i = 0; i < rt->rate_count; i++, rates++) { + rates->rate = rt->rates[i].rate_kbps / 100; + rates->val = rt->rates[i].rate_code; + rates->flags = rt->rates[i].modulation; + } + + return i; +} + +#if ATH_DEBUG_MODES +static void ath_dump_modes(struct ieee80211_hw_mode *modes) +{ + unsigned int m, i; + + for (m = 0; m < NUM_IEEE80211_MODES; m++) { + printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m, + modes[m].num_channels, modes[m].num_rates); + printk(KERN_DEBUG " channels:\n"); + for (i = 0; i < modes[m].num_channels; i++) { + printk(KERN_DEBUG " %3d %d %.4x %.4x\n", + modes[m].channels[i].chan, + modes[m].channels[i].freq, + modes[m].channels[i].val, + modes[m].channels[i].flag); + } + printk(KERN_DEBUG " rates:\n"); + for (i = 0; i < modes[m].num_rates; i++) { + printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n", + modes[m].rates[i].rate, + modes[m].rates[i].val, + modes[m].rates[i].flags, + modes[m].rates[i].val2); + } + } +} +#else +static inline void ath_dump_modes(struct ieee80211_hw_mode *modes) {} +#endif + +static int ath_getchannels(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + struct ieee80211_hw_mode *modes = sc->modes; + u32 domain_current = ah->ah_regdomain; + unsigned int i, c, domain_5ghz, domain_2ghz; + int ret; + enum { + A = 0, + B = 1, + G = 2, + T = 3, + TG = 4, + }; + + ah->ah_country_code = countrycode; + + modes[A].mode = MODE_IEEE80211A; + modes[A].channels = sc->channels; + modes[B].mode = MODE_IEEE80211B; + modes[B].channels = sc->channels; + modes[G].mode = MODE_IEEE80211G; + modes[G].channels = sc->channels; + + modes[A].rates = sc->rates; + modes[A].num_rates = ath_copy_rates(modes[A].rates, + ath5k_hw_get_rate_table(ah, AR5K_MODE_11A)); + modes[B].rates = &modes[A].rates[modes[A].num_rates]; + modes[B].num_rates = ath_copy_rates(modes[B].rates, + ath5k_hw_get_rate_table(ah, AR5K_MODE_11B)); + modes[G].rates = &modes[B].rates[modes[B].num_rates]; + modes[G].num_rates = ath_copy_rates(modes[G].rates, + ath5k_hw_get_rate_table(ah, AR5K_MODE_11G)); + + /* + * In debugging mode, enable all channels supported by the chipset + */ + if (domain_current == DMN_DEFAULT || CHAN_DEBUG == 1) { + short freq; + + /* channel 1 -2412MHz .. channel 26 (non-ieee) -2732MHz */ + for (i = 1, c = 0; i <= 26 && c < ATH_CHAN_MAX; i++) { + freq = ath_ieee2mhz(i); + if (ath5k_check_channel(ah, freq,CHANNEL_2GHZ) == false) + continue; + sc->channels[c].chan = i; + sc->channels[c].freq = freq; + sc->channels[c].val = CHANNEL_B | CHANNEL_G; + c++; + } + modes[B].num_channels = c; + modes[G].num_channels = c; + + for (i = 27; i <= 220 && c < ATH_CHAN_MAX; i++) { + freq = ath_ieee2mhz(i); + if (ath5k_check_channel(ah, freq,CHANNEL_5GHZ) == false) + continue; + sc->channels[c].chan = i; + sc->channels[c].freq = freq; + sc->channels[c].val = CHANNEL_A | CHANNEL_T| CHANNEL_XR; + c++; + } + modes[A].channels += modes[B].num_channels; /* skip B/G chans */ + modes[A].num_channels = c - modes[B].num_channels; + + goto end; + } + + domain_5ghz = ieee80211_regdomain2flag(domain_current, + IEEE80211_CHANNELS_5GHZ_MIN); + domain_2ghz = ieee80211_regdomain2flag(domain_current, + IEEE80211_CHANNELS_2GHZ_MIN); +#if 0 + /* + * Create channel list based on chipset capabilities, regulation domain + * and mode. 5GHz... + */ + for (i = 0; hal->ah_capabilities.cap_range.range_5ghz_max > 0 && + i < ARRAY_SIZE(ath5k_5ghz_channels) && + c < max_channels; i++) { + /* Check if channel is supported by the chipset */ + if (ath5k_check_channel(hal, ath5k_5ghz_channels[i].rc_channel, + CHANNEL_5GHZ) == false) + continue; + + /* Match regulation domain */ + if ((IEEE80211_DMN(ath5k_5ghz_channels[i].rc_domain) & + IEEE80211_DMN(domain_5ghz)) == 0) + continue; + + /* Match modes */ + if (ath5k_5ghz_channels[i].rc_mode & CHANNEL_TURBO) + all_channels[c].channel_flags = CHANNEL_T; + else if (ath5k_5ghz_channels[i].rc_mode & CHANNEL_OFDM) + all_channels[c].channel_flags = CHANNEL_A; + else + continue; + + /* Write channel and increment counter */ + all_channels[c++].freq = ath5k_5ghz_channels[i].rc_channel; + } + + /* + * ...and 2GHz. + */ + for (i = 0; hal->ah_capabilities.cap_range.range_2ghz_max > 0 && + i < ARRAY_SIZE(ath5k_2ghz_channels) && + c < max_channels; i++) { + /* Check if channel is supported by the chipset */ + if (ath5k_check_channel(hal, ath5k_2ghz_channels[i].rc_channel, + CHANNEL_2GHZ) == false) + continue; + + /* Match regulation domain */ + if ((IEEE80211_DMN(ath5k_2ghz_channels[i].rc_domain) & + IEEE80211_DMN(domain_2ghz)) == 0) + continue; + + /* Match modes */ + if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11B) && + (ath5k_2ghz_channels[i].rc_mode & CHANNEL_CCK)) + all_channels[c].channel_flags = CHANNEL_B; + + if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11G) && + (ath5k_2ghz_channels[i].rc_mode &CHANNEL_OFDM)){ + all_channels[c].channel_flags |= CHANNEL_G; +/* if (ath5k_2ghz_channels[i].rc_mode & CHANNEL_TURBO) + all_channels[c].channel_flags |= CHANNEL_TG;*/ + } + + /* Write channel and increment counter */ + all_channels[c++].freq = ath5k_2ghz_channels[i].rc_channel; + } +#endif +end: + ret = ieee80211_register_hwmode(hw, modes); + if (ret) { + printk(KERN_ERR "can't register hwmodes\n"); + goto err; + } + ath_dump_modes(modes); + + return 0; +err: + return ret; +} +#if 0 +static int ath_rate_setup(struct ieee80211_hw *dev, u_int mode) +{ + struct ath_softc *sc = dev->priv; + struct ath_hw *ah = sc->ah; + const struct ath5k_rate_table *rt; +// struct ieee80211_rateset *rs; +// int i, maxrates; + + switch (mode) { + case MODE_IEEE80211A: + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A); + break; + case MODE_IEEE80211B: + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11B); + break; + case MODE_IEEE80211G: + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11G); + break; + case MODE_ATHEROS_TURBO: + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_TURBO); + break; + case MODE_ATHEROS_TURBOG: + sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_108G); + break; + default: + DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", + __func__, mode); + return 0; + } + rt = sc->sc_rates[mode]; + if (rt == NULL) + return 0; +#ifdef BLE + if (rt->rate_count > IEEE80211_RATE_MAXSIZE) { + DPRINTF(sc, ATH_DEBUG_ANY, + "%s: rate table too small (%u > %u)\n", + __func__, rt->rate_count, IEEE80211_RATE_MAXSIZE); + maxrates = IEEE80211_RATE_MAXSIZE; + } else + maxrates = rt->rate_count; + rs = &ic->ic_sup_rates[mode]; + for (i = 0; i < maxrates; i++) + rs->rs_rates[i] = rt->rates[i].dot11_rate; + rs->rs_nrates = maxrates; +#endif + return 1; +} + +static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) +{ + /* NB: on/off times from the Atheros NDIS driver, w/ permission */ +#ifdef BLE + static const struct { + u_int rate; /* tx/rx 802.11 rate */ + u_int16_t timeOn; /* LED on time (ms) */ + u_int16_t timeOff; /* LED off time (ms) */ + } blinkrates[] = { + { 108, 40, 10 }, + { 96, 44, 11 }, + { 72, 50, 13 }, + { 48, 57, 14 }, + { 36, 67, 16 }, + { 24, 80, 20 }, + { 22, 100, 25 }, + { 18, 133, 34 }, + { 12, 160, 40 }, + { 10, 200, 50 }, + { 6, 240, 58 }, + { 4, 267, 66 }, + { 2, 400, 100 }, + { 0, 500, 130 }, + }; +#endif + const struct ath5k_rate_table *rt; +// int i, j; + + memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); + rt = sc->sc_rates[mode]; + KASSERT(rt != NULL, "no h/w rate set for phy mode %u", mode); +#ifdef BLE + for (i = 0; i < rt->rate_count; i++) + sc->sc_rixmap[rt->rates[i].dot11_rate & IEEE80211_RATE_VAL] = i; + memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); + for (i = 0; i < 32; i++) { + u_int8_t ix = rt->rate_code_to_index[i]; + if (ix == 0xff) { + sc->sc_hwmap[i].ledon = (500 * HZ) / 1000; + sc->sc_hwmap[i].ledoff = (130 * HZ) / 1000; + continue; + } + sc->sc_hwmap[i].ieeerate = + rt->rates[ix].dot11_rate & IEEE80211_RATE_VAL; + sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; + if (SHPREAMBLE_FLAG(ix) || + rt->rates[ix].modulation == MODULATION_OFDM) + sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; + /* NB: receive frames include FCS */ + sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | + IEEE80211_RADIOTAP_F_FCS; + /* setup blink rate table to avoid per-packet lookup */ + for (j = 0; j < N(blinkrates)-1; j++) + if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) + break; + /* NB: this uses the last entry if the rate isn't found */ + /* XXX beware of overlow */ + sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * HZ) / 1000; + sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * HZ) / 1000; + } +#endif + sc->sc_currates = rt; + sc->sc_curmode = mode; + /* + * All protection frames are transmited at 2Mb/s for + * 11g, otherwise at 1Mb/s. + * XXX select protection rate index from rate table. + */ + sc->sc_protrix = ((mode == MODE_IEEE80211G || mode == MODE_ATHEROS_TURBOG) ? 1 : 0); + /* NB: caller is responsible for reseting rate control state */ +} + +static int ath_desc_alloc(struct ath_softc *sc) +{ +#define DS2PHYS(_sc, _ds) \ + ((_sc)->sc_desc_daddr + ((caddr_t)(_ds) - (caddr_t)(_sc)->sc_desc)) + int bsize; + struct ath_desc *ds; + struct ath_buf *bf; + int i; + + /* allocate descriptors */ + sc->sc_desc_len = sizeof(struct ath_desc) * + (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); + barrier(); /* get_order() rounds down constants before Linux 2.6.21 */ + sc->sc_desc = bus_alloc_consistent(sc->sc_bdev, + sc->sc_desc_len, &sc->sc_desc_daddr); + if (sc->sc_desc == NULL) { + printk(KERN_ERR "%s, could not allocate descriptors\n", __func__); + return ENOMEM; + } + ds = sc->sc_desc; + DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%u) -> %llx\n", + __func__, ds, (unsigned int) sc->sc_desc_len, + (unsigned long long)sc->sc_desc_daddr); + + /* allocate buffers */ + bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); + bf = kmalloc(bsize, GFP_KERNEL); + if (bf == NULL) + goto bad; + memset(bf, 0, bsize); + sc->sc_bufptr = bf; + +// STAILQ_INIT(&sc->sc_rxbuf); + for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { + bf->bf_desc = ds; + bf->bf_daddr = DS2PHYS(sc, ds); +// STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); + } + +// STAILQ_INIT(&sc->sc_txbuf); + for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { + bf->bf_desc = ds; + bf->bf_daddr = DS2PHYS(sc, ds); +// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); + } + +// STAILQ_INIT(&sc->sc_bbuf); + for (i = 0; i < ATH_BCBUF; i++, bf++, ds++) { + bf->bf_desc = ds; + bf->bf_daddr = DS2PHYS(sc, ds); +// STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); + } + + return 0; +bad: + bus_free_consistent(sc->sc_bdev, sc->sc_desc_len, + sc->sc_desc, sc->sc_desc_daddr); + sc->sc_desc = NULL; + return -ENOMEM; +#undef DS2PHYS +} + +static void ath_desc_free(struct ath_softc *sc) +{ + ath_descdma_cleanup(sc, sc->sc_bbuf); + ath_descdma_cleanup(sc, sc->sc_txbuf); + ath_descdma_cleanup(sc, sc->sc_rxbuf); + + /* Free memory associated with all descriptors */ + bus_free_consistent(sc->sc_bdev, sc->sc_desc_len, + sc->sc_desc, sc->sc_desc_daddr); + + kfree(sc->sc_bufptr); + sc->sc_bufptr = NULL; +} +#endif static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; struct ath_hw *ah = sc->ah; - int error = 0, i; + unsigned int i; + int ret; DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); - return 0; /* * Check if the MAC has multi-rate retry support. @@ -279,22 +674,9 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) sc->sc_mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); /* - * Check if the device has hardware counters for PHY - * errors. If so we need to enable the MIB interrupt - * so we can act on stat triggers. - */ - if (ath_hal_hwphycounters(ah)) - sc->sc_needmib = 1; - - /* * Get the hardware key cache size. */ - sc->sc_keymax = ath5k_hw_get_keycache_size(ah); - if (sc->sc_keymax > ATH_KEYMAX) { - printk(KERN_WARNING "Warning, using only %u of %u key cache " - "slots\n", ATH_KEYMAX, sc->sc_keymax); - sc->sc_keymax = ATH_KEYMAX; - } + sc->sc_keymax = AR5K_KEYCACHE_SIZE; /* * Reset the key cache since some parts do not @@ -315,19 +697,19 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) setbit(sc->sc_keymap, i+64); setbit(sc->sc_keymap, i+32+64); } - +#endif /* * Collect the channel list using the default country * code and including outdoor channels. The 802.11 layer * is resposible for filtering this list based on settings * like the phy mode. */ - error = ath_getchannels(hw, countrycode, outdoor, xchanmode); - if (error != 0) { - printk("error! but continuing anyways...\n"); - //goto bad; + ret = ath_getchannels(hw); + if (ret) { + dev_err(&pdev->dev, "can't get channels\n"); + goto err; } - +#ifdef BLE /* * Setup rate tables for all potential media types. */ @@ -342,8 +724,8 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) /* * Allocate tx+rx descriptors and populate the lists. */ - error = ath_desc_alloc(sc); - if (error != 0) { + ret = ath_desc_alloc(sc); + if (ret) { printk(KERN_ERR "failed to allocate descriptors: %d\n", error); goto bad; } @@ -367,8 +749,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) error = EIO; goto bad2; } -#endif -#ifdef BLE + /* NB: insure BK queue is the lowest priority h/w queue */ if (!ath_tx_setup(sc, WME_AC_BK, AR5K_WME_AC_BK)) { printk(KERN_ERR "unable to setup xmit queue for %s traffic!\n", @@ -551,7 +932,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) * 32-bit boundary for 4-address and QoS frames. */ ic->ic_flags |= IEEE80211_F_DATAPAD; -#endif /* * Query the hal about antenna support. @@ -569,7 +949,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) /* get mac address from hardware */ // ath_hal_getmac(ah, ic->ic_myaddr); BLEE // IEEE80211_ADDR_COPY(dev->dev_addr, ic->ic_myaddr); -#ifdef BLE + /* call MI attach routine. */ ieee80211_ifattach(ic); /* override default methods */ @@ -588,8 +968,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ic->ic_crypto.cs_key_update_end = ath_key_update_end; radar_init(ic); -#endif -#if 0 + /* complete initialization */ ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); @@ -598,14 +977,14 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto bad3; } -#endif /* * Attach dynamic MIB vars and announce support * now that we have a device name with unit number. */ -// ath_dynamic_sysctl_register(sc); -// ath_rate_dynamic_sysctl_register(sc); -// ath_announce(sc); + ath_dynamic_sysctl_register(sc); + ath_rate_dynamic_sysctl_register(sc); + ath_announce(sc); +#endif return 0; #ifdef BLE @@ -628,7 +1007,8 @@ bad2: ath_tx_cleanup(sc); ath_desc_free(sc); #endif - return error; +err: + return ret; } static void ath_detach(struct ieee80211_hw *hw) diff --git a/ath/if_athvar.h b/ath/if_athvar.h index decb45a..7260f79 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -50,10 +50,6 @@ #include "if_athioctl.h" #include "if_athrate.h" -#ifndef ARPHRD_IEEE80211_RADIOTAP -#define ARPHRD_IEEE80211_RADIOTAP 803 /* IEEE 802.11 + radiotap header */ -#endif /* ARPHRD_IEEE80211_RADIOTAP */ - #define ATH_TIMEOUT 1000 /* @@ -83,8 +79,8 @@ * Different parts have different size key caches. We handle * up to ATH_KEYMAX entries (could dynamically allocate state). */ -#define ATH_KEYMAX 128 /* max key cache size we handle */ -#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ +#define ATH_KEYMAX AR5K_KEYCACHE_SIZE /* max key cache size we handle */ +#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ /* driver-specific node state */ struct ath_node { @@ -173,18 +169,25 @@ struct ath_txq { (_tq)->axq_depth--; \ } while (0) +#define ATH_CHAN_MAX 255 /* XXX what's the max? */ + struct ath_softc { void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ // struct net_device_stats sc_devstats; /* device statistics */ struct ath_stats sc_stats; /* private statistics */ struct ieee80211_hw *hw; /* IEEE 802.11 common */ + struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; + struct ieee80211_channel channels[ATH_CHAN_MAX]; + struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_IEEE80211_MODES]; struct ath_hw *ah; /* Atheros HW */ - +#ifdef BLE enum ieee80211_if_types sc_opmode; int sc_regdomain; int sc_countrycode; +#endif int sc_debug; + #ifdef BLE void (*sc_recv_mgmt)(struct ieee80211com *, struct sk_buff *, @@ -193,16 +196,20 @@ struct ath_softc { int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); void (*sc_node_free)(struct ieee80211_node *); -#endif struct ath_desc *sc_desc; /* TX/RX descriptors */ size_t sc_desc_len; /* size of TX/RX descriptors */ +#endif u16 sc_cachelsz; /* cache line size */ +#ifdef BLE dma_addr_t sc_desc_daddr; /* DMA (physical) address */ struct ath_ratectrl *sc_rc; /* tx rate control support */ void (*sc_setdefantenna)(struct ath_softc *, u_int); +#endif unsigned int sc_invalid : 1, /* disable hardware accesses */ sc_mrretry : 1, /* multi-rate retry support */ sc_softled : 1, /* enable LED gpio status */ + xxx:1; +#ifdef BLE sc_splitmic: 1, /* split TKIP MIC keys */ sc_needmib : 1, /* enable MIB stats intr */ sc_diversity : 1,/* enable rx diversity */ @@ -218,7 +225,7 @@ struct ath_softc { const struct ath5k_rate_table *sc_currates; /* current rate table */ unsigned int sc_curmode; /* current phy mode */ u16 sc_curtxpow; /* current tx power limit */ - struct ath5k_channel sc_curchan; /* current h/w channel */ + struct ieee80211_channel sc_curchan; /* current h/w channel */ u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ struct { u8 ieeerate; /* IEEE rate */ @@ -229,14 +236,15 @@ struct ath_softc { } sc_hwmap[32]; /* h/w rate ix mappings */ u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ +#endif enum ath5k_int sc_imask; /* interrupt mask copy */ u_int sc_keymax; /* size of key cache */ #ifdef BLE u8 sc_keymap[ATH_KEYBYTES];/* key use bit map */ struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ #endif - u_int sc_ledpin; /* GPIO pin for driving LED */ +#ifdef BLE u_int sc_ledon; /* pin setting for LED on */ u_int sc_ledidle; /* idle polling interval */ int sc_ledevent; /* time of last LED event */ @@ -256,26 +264,33 @@ struct ath_softc { u8 pad[64]; } u_rx_rt; int sc_rx_th_len; - +#endif struct tasklet_struct sc_fataltq; /* fatal int tasklet */ +#ifdef BLE struct tasklet_struct sc_radartq; /* Radar detection */ int sc_rxbufsize; /* rx size based on mtu */ struct list_head *sc_rxbuf; /* receive buffer */ - u32 *sc_rxlink; /* link ptr in last RX desc */ +#endif struct tasklet_struct sc_rxtq; /* rx intr tasklet */ struct tasklet_struct sc_rxorntq; /* rxorn intr tasklet */ + u32 *sc_rxlink; /* link ptr in last RX desc */ +#ifdef BLE u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ struct list_head *sc_txbuf; /* transmit buffer */ +#endif spinlock_t sc_txbuflock; /* txbuf lock */ +#ifdef BLE int sc_tx_timer; /* transmit timeout */ u_int sc_txqsetup; /* h/w queues setup */ u_int sc_txintrperiod;/* tx interrupt batching */ struct ath_txq sc_txq[AR5K_NUM_TX_QUEUES]; struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ +#endif struct tasklet_struct sc_txtq; /* tx intr tasklet */ +#ifdef BLE struct list_head *sc_bbuf; /* beacon buffers */ u_int sc_bhalq; /* HAL q for outgoing beacons */ @@ -286,7 +301,9 @@ struct ath_softc { #ifdef BLE struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ #endif +#endif struct tasklet_struct sc_bmisstq; /* bmiss intr tasklet */ +#ifdef BLE struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ enum { OK, /* no change needed */ @@ -299,6 +316,7 @@ struct ath_softc { struct iw_statistics sc_iwstats; /* wireless statistics block */ struct ctl_table_header *sc_sysctl_header; struct ctl_table *sc_sysctls; +#endif }; #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<ah_country_code) #define ath_hal_tkipsplit(_ah) \ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index f40d7ec..731f5a8 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -37,7 +37,7 @@ * WARNING: This is for debuging only and has side effects (eg. scan takes too long * and results timeouts). It's also illegal to tune to some of the supported frequencies * in some countries, so use this at your own risk, you 've been warned. */ -#define CHAN_DEBUG 0 +#define CHAN_DEBUG 1 /* Uncomment this for debuging (warning that results TOO much output) */ /*#define AR5K_DEBUG 1 */ @@ -572,15 +572,6 @@ struct ath_desc { AR5K_MODE_108G | \ AR5K_MODE_XR) -/* - * Channel definitions - */ -struct ath5k_channel { - u16 freq; /* setting in Mhz */ - u16 channel_flags; - u8 private_flags; /* not used in OpenHAL yet*/ -}; - #define AR5K_SLOT_TIME_9 396 #define AR5K_SLOT_TIME_20 880 #define AR5K_SLOT_TIME_MAX 0xffff @@ -613,13 +604,13 @@ struct ath5k_channel { /* * Used internaly in OpenHAL (ar5211.c/ar5212.c - * for reset_tx_queue). Also see struct struct ath5k_channel. + * for reset_tx_queue). Also see struct struct ieee80211_channel. */ #define IS_CHAN_XR(_c) \ - ((_c.channel_flags & CHANNEL_XR) != 0) + ((_c.val & CHANNEL_XR) != 0) #define IS_CHAN_B(_c) \ - ((_c.channel_flags & CHANNEL_B) != 0) + ((_c.val & CHANNEL_B) != 0) enum ath5k_chip{ AR5K_CHIP_5GHZ = CHANNEL_5GHZ, @@ -763,6 +754,8 @@ struct ath5k_keyval { u8 wk_mic[8]; /* TKIP MIC key */ }; +#define AR5K_KEYCACHE_SIZE 8 + /***********************\ HW RELATED DEFINITIONS \***********************/ @@ -952,7 +945,7 @@ struct ath_hw { enum ieee80211_if_types ah_op_mode; enum ath5k_power_mode ah_power_mode; - struct ath5k_channel ah_current_channel; + struct ieee80211_channel ah_current_channel; bool ah_turbo; bool ah_calibration; bool ah_running; @@ -1021,7 +1014,7 @@ struct ath_hw { struct { bool r_enabled; int r_last_alert; - struct ath5k_channel r_last_channel; + struct ieee80211_channel r_last_channel; } ah_radar; /* @@ -1044,7 +1037,8 @@ struct ath_hw { /* * Prototypes */ -typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ath5k_channel *, u_int); +typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ieee80211_channel *, + unsigned int); /* General Functions */ u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); @@ -1054,7 +1048,7 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ -int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ath5k_channel *channel, bool change_channel); +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); //bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); @@ -1079,7 +1073,6 @@ void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); -bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain); int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); @@ -1115,7 +1108,6 @@ bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); /* Key table (WEP) functions */ bool ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher); -u32 ath5k_hw_get_keycache_size(struct ath_hw *hal); bool ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); bool ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); bool ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused); @@ -1143,18 +1135,18 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); bool ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags); -bool ath_hal_init_channels(struct ath_hw *hal, struct ath5k_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); +bool ath_hal_init_channels(struct ath_hw *hal, struct ieee80211_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); u16 ath5k_get_regdomain(struct ath_hw *hal); /* PHY/RF access functions */ -bool ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel); -u32 ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel); -bool ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel); +u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel); +bool ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel); bool ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan); -bool ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ath5k_channel *channel); -bool ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); -bool ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ath5k_channel *channel); +bool ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); bool ath5k_hw_phy_disable(struct ath_hw *hal); void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); @@ -1162,10 +1154,10 @@ unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 firs u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal); bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal); s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal); -bool ath5k_hw_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); -bool ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); -bool ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode); -void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int freq, unsigned int ee_mode); +bool ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); +bool ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); +bool ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); +void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, unsigned int ee_mode); bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 8318143..d941be3 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -79,9 +79,9 @@ static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ static int ath5k_hw_nic_reset(struct ath_hw *, u32); -static int ath5k_hw_nic_wakeup(struct ath_hw *, u16, bool); +static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool); static u16 ath5k_hw_radio_revision(struct ath_hw *, enum ath5k_chip); -static bool ath5k_hw_txpower(struct ath_hw *, struct ath5k_channel *, +static bool ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int); static bool ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, @@ -544,7 +544,7 @@ err: /* * Bring up MAC + PHY Chips */ -static int ath5k_hw_nic_wakeup(struct ath_hw *hal, u16 flags, bool initial) +static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) { u32 turbo, mode, clock; int ret; @@ -770,7 +770,7 @@ void ath5k_hw_detach(struct ath_hw *hal) * Main reset function */ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, - struct ath5k_channel *channel, bool change_channel) + struct ieee80211_channel *channel, bool change_channel) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u8 mac[ETH_ALEN]; @@ -810,7 +810,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Wakeup the device*/ - if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, false) == false) + if (ath5k_hw_nic_wakeup(hal, channel->val, false) == false) return -EIO; /* @@ -832,7 +832,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, return -EINVAL; } - switch (channel->channel_flags & CHANNEL_MODES) { + switch (channel->val & CHANNEL_MODES) { case CHANNEL_A: mode = AR5K_INI_VAL_11A; freq = AR5K_INI_RFGAIN_5GHZ; @@ -992,7 +992,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (hal->ah_version == AR5K_AR5212) { /*For 802.11b*/ - if (!(channel->channel_flags & CHANNEL_B)) { + if (!(channel->val & CHANNEL_B)) { /*Get rate table for this operation mode*/ rt = ath5k_hw_get_rate_table(hal, AR5K_MODE_11B); @@ -1016,7 +1016,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Get rate table for this operation mode*/ rt = ath5k_hw_get_rate_table(hal, - channel->channel_flags & CHANNEL_TURBO ? + channel->val & CHANNEL_TURBO ? AR5K_MODE_TURBO : AR5K_MODE_XR); /*Write rate duration table*/ @@ -1034,7 +1034,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { AR5K_REG_WRITE(AR5K_PHY_CCKTXCTL, AR5K_PHY_CCKTXCTL_WORLD); - if (channel->channel_flags & CHANNEL_A) + if (channel->val & CHANNEL_A) data = 0xffb81020; else data = 0xffb80d20; @@ -1063,11 +1063,11 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* Write OFDM timings on 5212*/ if (hal->ah_version == AR5K_AR5212) { - if (channel->channel_flags & CHANNEL_OFDM) { + if (channel->val & CHANNEL_OFDM) { u32 coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man, clock; - clock = channel->channel_flags & CHANNEL_T ? 80 : 40; + clock = channel->val & CHANNEL_T ? 80 : 40; coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; for (coef_exp = 31; coef_exp > 0; coef_exp--) @@ -1093,7 +1093,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Enable/disable 802.11b mode on 5111 (enable 2111 frequency converter + CCK)*/ if (hal->ah_radio == AR5K_RF5111) { - if (channel->channel_flags & CHANNEL_B) + if (channel->val & CHANNEL_B) AR5K_REG_ENABLE_BITS(AR5K_TXCFG, AR5K_TXCFG_B_MODE); else @@ -1219,7 +1219,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, */ if (hal->ah_version != AR5K_AR5210) { data = AR5K_REG_READ(AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; - data = (channel->channel_flags & CHANNEL_CCK) ? + data = (channel->val & CHANNEL_CCK) ? ((data << 2) / 22) : (data / 10); udelay(100 + data); @@ -1274,7 +1274,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, hal->ah_calibration = false; - if (!(channel->channel_flags & CHANNEL_B)) { + if (!(channel->val & CHANNEL_B)) { hal->ah_calibration = true; AR5K_REG_WRITE_BITS(AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); @@ -2469,10 +2469,9 @@ static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) } /* - * Read/Write refulatory domain + * Read/Write regulatory domain */ -bool -ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, +static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, enum ieee80211_regdomain *regdomain) { u16 ee_regdomain; @@ -3290,16 +3289,6 @@ ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher) } /* - * Get key cache size - */ -u32 -ath5k_hw_get_keycache_size(struct ath_hw *hal) -{ - AR5K_TRACE; - return AR5K_KEYCACHE_SIZE; -} - -/* * Reset encryption key */ bool @@ -4666,32 +4655,6 @@ ath_hal_mhz2ieee(unsigned int freq, u_int flags) } /* - * Convert IEEE channel number to MHz frequency. - */ -unsigned int -ath_hal_ieee2mhz(unsigned int chan, u_int flags) -{ - if (flags & CHANNEL_2GHZ) { /* 2GHz band */ - if (chan == 14) - return 2484; - if (chan < 14) - return 2407 + chan * 5; - else - return 2512 + ((chan - 15) * 20); - } else if (flags & CHANNEL_5GHZ) /* 5Ghz band */ - return 5000 + (chan * 5); - else { /* either, guess */ - if (chan == 14) - return 2484; - if (chan < 14) /* 0-13 */ - return 2407 + chan * 5; - if (chan < 27) /* 15-26 */ - return 2512 + ((chan - 15) * 20); - return 5000 + (chan * 5); - } -} - -/* * Check if a channel is supported */ bool @@ -4710,147 +4673,6 @@ ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags) return false; } -/* - * Initialize channels array - * TODO: Do this in the driver, only check_channel is hw related - * also left here temporarily for combatibility. - */ -bool -ath_hal_init_channels(struct ath_hw *hal, struct ath5k_channel *channels, - unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, - bool outdoor, bool extended) -{ - unsigned int i, c; - u32 domain_current; - unsigned int domain_5ghz, domain_2ghz; - struct ath5k_channel *all_channels; - enum ieee80211_countrycode country_current; - - if ((all_channels = kmalloc(sizeof(struct ath5k_channel) * max_channels, - GFP_KERNEL)) == NULL) - return false; - - i = c = 0; - domain_current = hal->ah_regdomain; - hal->ah_country_code = country; - country_current = hal->ah_country_code; - - /* - * In debugging mode, enable all channels supported by the chipset - */ - if (domain_current == DMN_DEFAULT || CHAN_DEBUG == 1) { - int min, max, freq; - unsigned int flags; - - min = 1; /* 2GHz channel 1 -2412Mhz */ - max = 26;/* 2GHz channel 26 (non-ieee) -2732Mhz */ - - flags = CHANNEL_B | CHANNEL_G; -debugchan: - for (i = min; (i <= max) && (c < max_channels); i++) { - freq = ath_hal_ieee2mhz(i, flags); - if (ath5k_check_channel(hal, freq, flags) == false) - continue; - all_channels[c].freq = freq; - all_channels[c].channel_flags = flags; - c++; - } - - /* If is there to protect from infinite loop */ - if (flags & CHANNEL_2GHZ) { -/* ath_hal_mhz2ieee returns 1 for IEEE80211_CHANNELS_5GHZ_MIN -for loop starts from 1 and all channels are marked as 5GHz M.F.*/ -// min = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, -// CHANNEL_5GHZ); -/* Continue from where we stoped, skip last 2GHz channel */ - min = max + 1; - max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, - CHANNEL_5GHZ); - flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR; - goto debugchan; - } - - goto done; - } - - domain_5ghz = ieee80211_regdomain2flag(domain_current, - IEEE80211_CHANNELS_5GHZ_MIN); - domain_2ghz = ieee80211_regdomain2flag(domain_current, - IEEE80211_CHANNELS_2GHZ_MIN); - - /* - * Create channel list based on chipset capabilities, regulation domain - * and mode. 5GHz... - */ - for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && - (i < ARRAY_SIZE(ath5k_5ghz_channels)) && - (c < max_channels); i++) { - /* Check if channel is supported by the chipset */ - if (ath5k_check_channel(hal, - ath5k_5ghz_channels[i].rc_channel, - CHANNEL_5GHZ) == false) - continue; - - /* Match regulation domain */ - if ((IEEE80211_DMN(ath5k_5ghz_channels[i].rc_domain) & - IEEE80211_DMN(domain_5ghz)) == 0) - continue; - - /* Match modes */ - if (ath5k_5ghz_channels[i].rc_mode & CHANNEL_TURBO) - all_channels[c].channel_flags = CHANNEL_T; - else if (ath5k_5ghz_channels[i].rc_mode & - CHANNEL_OFDM) - all_channels[c].channel_flags = CHANNEL_A; - else - continue; - - /* Write channel and increment counter */ - all_channels[c++].freq = ath5k_5ghz_channels[i].rc_channel; - } - - /* - * ...and 2GHz. - */ - for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && - (i < ARRAY_SIZE(ath5k_2ghz_channels)) && - (c < max_channels); i++) { - - /* Check if channel is supported by the chipset */ - if (ath5k_check_channel(hal, - ath5k_2ghz_channels[i].rc_channel, - CHANNEL_2GHZ) == false) - continue; - - /* Match regulation domain */ - if ((IEEE80211_DMN(ath5k_2ghz_channels[i].rc_domain) & - IEEE80211_DMN(domain_2ghz)) == 0) - continue; - - /* Match modes */ - if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11B) && - (ath5k_2ghz_channels[i].rc_mode & CHANNEL_CCK)) - all_channels[c].channel_flags = CHANNEL_B; - - if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11G) && - (ath5k_2ghz_channels[i].rc_mode & CHANNEL_OFDM)) { - all_channels[c].channel_flags |= CHANNEL_G; -/* if (ath5k_2ghz_channels[i].rc_mode & - CHANNEL_TURBO) - all_channels[c].channel_flags |= CHANNEL_TG;*/ - } - - /* Write channel and increment counter */ - all_channels[c++].freq = ath5k_2ghz_channels[i].rc_channel; - } - - done: - memcpy(channels, all_channels, sizeof(struct ath5k_channel) * max_channels); - *channels_size = c; - kfree(all_channels); - return true; -} - u16 ath5k_get_regdomain(struct ath_hw *hal) { @@ -4886,7 +4708,7 @@ ath5k_get_regdomain(struct ath_hw *hal) * Set a channel on the radio chip */ bool -ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel) +ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel) { bool ret; @@ -4917,9 +4739,8 @@ ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel) return ret; hal->ah_current_channel.freq = channel->freq; - hal->ah_current_channel.channel_flags = channel->channel_flags; - hal->ah_turbo = channel->channel_flags == CHANNEL_T ? - true : false; + hal->ah_current_channel.val = channel->val; + hal->ah_turbo = channel->val == CHANNEL_T ? true : false; return true; } @@ -4928,7 +4749,7 @@ ath5k_hw_channel(struct ath_hw *hal, struct ath5k_channel *channel) * Convertion needed for RF5110 */ u32 -ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) +ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) { u32 athchan; @@ -4939,7 +4760,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) * different RF/PHY part. */ athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq, - channel->channel_flags) - 24) / 2, 5) << 1) | + channel->val) - 24) / 2, 5) << 1) | (1 << 6) | 0x1; return athchan; @@ -4949,7 +4770,7 @@ ath5k_hw_rf5110_chan2athchan(struct ath5k_channel *channel) * Set channel on RF5110 */ bool -ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ath5k_channel *channel) +ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) { u32 data; @@ -4997,7 +4818,7 @@ ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athch * Set channel on 5111 */ bool -ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel) +ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) { unsigned int ieee_channel, ath_channel; u32 data0, data1, clock; @@ -5008,9 +4829,9 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel) */ data0 = data1 = 0; ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, - channel->channel_flags); + channel->val); - if (channel->channel_flags & CHANNEL_2GHZ) { + if (channel->val & CHANNEL_2GHZ) { /* Map 2GHz channel to 5GHz Atheros channel ID */ if (ath5k_hw_rf5111_chan2athchan(ieee_channel, &ath_channel_2ghz) == false) @@ -5041,7 +4862,7 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ath5k_channel *channel) * Set channel on 5112 */ bool -ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ath5k_channel *channel) +ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) { u32 data, data0, data1, data2; u16 c; @@ -5089,7 +4910,7 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ath5k_channel *channel) * Perform a PHY calibration */ bool -ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ath5k_channel *channel){ +ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel){ bool ret; @@ -5104,7 +4925,7 @@ ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ath5k_channel *channel){ * Perform a PHY calibration on RF5110 */ bool -ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) +ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) { bool ret = true; u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; @@ -5253,7 +5074,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) * Perform a PHY calibration on RF5111/5112 */ bool -ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) +ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) { u32 i_pwr, q_pwr; s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; @@ -5289,7 +5110,7 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ath5k_channel *channel) AR5K_PHY_AGCCTL_NF); /* Request RF gain */ - if (channel->channel_flags & CHANNEL_5GHZ) { + if (channel->val & CHANNEL_5GHZ) { AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE, AR5K_REG_SM(hal->ah_txpower.txp_max, AR5K_PHY_PAPD_PROBE_TXPOWER) | @@ -5516,7 +5337,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) * Initialize RF */ bool -ath5k_hw_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) { ath5k_rfgain_t *func = NULL; bool ret; @@ -5554,7 +5375,7 @@ ath5k_hw_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int * Initialize RF5111 */ bool -ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); @@ -5582,8 +5403,8 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsign rf[i] = rf5111_rf[i].rf_value[mode]; } - if (channel->channel_flags & CHANNEL_2GHZ) { - if (channel->channel_flags & CHANNEL_B) + if (channel->val & CHANNEL_2GHZ) { + if (channel->val & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; else ee_mode = AR5K_EEPROM_MODE_11G; @@ -5652,7 +5473,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsign * Initialize RF5112 */ bool -ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int mode) +ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; unsigned int rf_size; @@ -5688,8 +5509,8 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsign rf[i] = rf_ini[i].rf_value[mode]; } - if (channel->channel_flags & CHANNEL_2GHZ) { - if (channel->channel_flags & CHANNEL_B) + if (channel->val & CHANNEL_2GHZ) { + if (channel->val & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; else ee_mode = AR5K_EEPROM_MODE_11G; @@ -5747,7 +5568,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsign * doesn't ar5k_rfregs work ? */ void -ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int freq, +ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, unsigned int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -5884,7 +5705,7 @@ ath5k_hw_get_rf_gain(struct ath_hw *hal) * Initialize the tx power table (not fully implemented) */ static void -ath5k_txpower_table(struct ath_hw *hal, struct ath5k_channel *channel, s16 max_power) +ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power) { u16 txpower, *rates; int i, min, max, n; @@ -5922,7 +5743,7 @@ ath5k_txpower_table(struct ath_hw *hal, struct ath5k_channel *channel, s16 max_p * Set transmition power */ static bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hw *hal, struct ath5k_channel *channel, unsigned int txpower) +ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; int i; @@ -5983,7 +5804,7 @@ bool ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) { /*Just a try M.F.*/ - struct ath5k_channel *channel = &hal->ah_current_channel; + struct ieee80211_channel *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n",power); diff --git a/openhal/ath5kreg.h b/openhal/ath5kreg.h index d21b057..05c0b88 100644 --- a/openhal/ath5kreg.h +++ b/openhal/ath5kreg.h @@ -1607,8 +1607,6 @@ #define AR5K_KEYTABLE_SIZE_5211 128 #define AR5K_KEYTABLE_SIZE (hal->ah_version == AR5K_AR5210 ? \ AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) -#define AR5K_KEYCACHE_SIZE 8 - /*===PHY REGISTERS===*/ commit 5c4375df170ac3e4fdd971bdac02a919881fea50 Author: Jiri Slaby Date: Fri Jun 22 11:02:46 2007 +0200 remove ath5k_known_products diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index d941be3..99e5982 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -30,46 +30,6 @@ #include "ath5k.h" #include "ath5kreg.h" -/* - * Known pci ids - */ - -static const struct { - u16 vendor; - u16 device; - u8 mac_version; -} ath5k_known_products[] = { - /* - * From pcidevs_data.h - */ - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210, AR5K_AR5210}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210_AP, AR5K_AR5210}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT, AR5K_AR5210}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5311, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_FPGA, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_IBM, AR5K_AR5212}, - { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CRDAG675, AR5K_AR5212}, - { PCI_VENDOR_ID_3COM_2, PCI_DEVICE_ID_3COM_2_3CRPAG175, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV2, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV7, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV8, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0014, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0015, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0016, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0017, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0018, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0019, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR2413, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5413, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5424, AR5K_AR5212}, -}; - /*Rate tables*/ static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; commit e868e1e53256928c50c67fa0331073a6f8f48eb1 Author: Jiri Slaby Date: Fri Jun 22 11:11:25 2007 +0200 several cleanups diff --git a/ath/if_ath.c b/ath/if_ath.c index 02518fe..ed978b0 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -2317,7 +2317,7 @@ ath_mode_init(struct net_device *dev) // ath5k_hw_set_rx_filter(ah, rfilt); /* configure operational mode */ - ath5k_hw_set_pcu_config(ah); + ath5k_hw_set_opmode(ah); /* * Handle any link-level address change. Note that we only diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 731f5a8..6de3c16 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -1042,7 +1042,6 @@ typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ieee80211_channel *, /* General Functions */ u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); -unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); @@ -1066,7 +1065,6 @@ bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); /* Interrupt handling */ bool ath5k_hw_is_intr_pending(struct ath_hw *hal); bool ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask); -u32 ath5k_hw_get_intr(struct ath_hw *hal); enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ @@ -1076,7 +1074,6 @@ int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); -void ath5k_hw_set_pcu_config(struct ath_hw *hal); /* BSSID Functions */ void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 99e5982..4bf7c42 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -180,23 +180,6 @@ ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, } /* - * Return the supported 802.11 operation modes - * TODO:Left here for combatibility, change it in at5k - */ -unsigned int/*TODO:Fix this */ -ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) -{ - switch(hal->ah_version){ - case AR5K_AR5212: - return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; - case AR5K_AR5211: - return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; - default : - return(AR5K_MODE_11A); - } -} - -/* * Functions used internaly */ @@ -213,14 +196,12 @@ ath5k_hw_bitswap(u32 val, unsigned int bits) return retval; } -inline unsigned int -ath5k_hw_htoclock(unsigned int usec, bool turbo) +static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) { return turbo == true ? (usec * 80) : (usec * 40); } -inline unsigned int -ath5k_hw_clocktoh(unsigned int clock, bool turbo) +static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) { return turbo == true ? (clock / 80) : (clock / 40); } @@ -228,7 +209,7 @@ ath5k_hw_clocktoh(unsigned int clock, bool turbo) /* * Copy a rate table to a new one */ -inline void +static inline void ath5k_hw_rtcopy(struct ath5k_rate_table *dst, const struct ath5k_rate_table *src) { memset(dst, 0, sizeof(struct ath5k_rate_table)); @@ -1817,17 +1798,6 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) } /* - * Return the interrupt mask stored previously - * TODO: Remove ? - */ -u32 -ath5k_hw_get_intr(struct ath_hw *hal) -{ - AR5K_TRACE; - return hal->ah_imr; -} - -/* * Set interrupt mask */ enum ath5k_int @@ -2606,13 +2576,6 @@ ath5k_hw_set_opmode(struct ath_hw *hal) AR5K_REG_WRITE(AR5K_BCR, beacon_reg); } -void /*TODO: Get rid of this, clean up the driver code, only set_opmode is needed*/ -ath5k_hw_set_pcu_config(struct ath_hw *hal) -{ - AR5K_TRACE; - ath5k_hw_set_opmode(hal); -} - /* * BSSID Functions */ commit e84295c46eb56b29f8abb6d07f27c53cc2a74a32 Author: Jiri Slaby Date: Fri Jun 22 14:53:57 2007 +0200 check for null rates diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 6a65fe7..4c6bfcc 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -272,6 +272,9 @@ static inline unsigned int ath_copy_rates(struct ieee80211_rate *rates, { unsigned int i; + if (rt == NULL) + return 0; + for (i = 0; i < rt->rate_count; i++, rates++) { rates->rate = rt->rates[i].rate_kbps / 100; rates->val = rt->rates[i].rate_code; commit 17de3041208847d9ed076824cf0eccb5635ce913 Merge: ba1084e... ac1bb80... Author: Jiri Slaby Date: Fri Jun 22 22:54:28 2007 +0200 Merge with git+ssh://decibel/home/xslaby/public_html/git/madwifi-openhal2 commit ba1084e4fd93cc0089107da702badec88064caaa Author: Jiri Slaby Date: Thu Jun 21 20:25:29 2007 +0200 remove ath/ath_hw.h diff --git a/ath/ath_hw.h b/ath/ath_hw.h deleted file mode 100644 index 9ac6027..0000000 --- a/ath/ath_hw.h +++ /dev/null @@ -1,75 +0,0 @@ -/*- - * Copyright (c) 2007 Pavel Roskin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -#ifndef _ATH_HW_H -#define _ATH_HW_H - -#define ATH_HW_IRQ_PENDING 0x4008 -# define ATH_HW_IRQ_PENDING_FALSE 0 -# define ATH_HW_IRQ_PENDING_TRUE 1 - -struct ath_hal; - -/* - * Read from a device register - */ -static inline u32 ath_hw_reg_read(struct ath_hal *hw, u16 reg) -{ - return readl(hw->ah_sh + reg); -} - -/* - * Write to a device register - */ -static inline void ath_hw_reg_write(struct ath_hal *hw, u32 val, u16 reg) -{ - writel(val, hw->ah_sh + reg); -} - -/* - * Check if there is an interrupt waiting to be processed. - * Return 1 if there is an interrupt for us, or 0 if there is none or if - * the device has been removed. - */ -static inline int ath_hw_irq_pending(struct ath_hal *hw) -{ - if (ath_hw_reg_read(hw, ATH_HW_IRQ_PENDING) == ATH_HW_IRQ_PENDING_TRUE) - return 1; - else - return 0; -} - -#endif /* _ATH_HW_H */ commit ebfde874c8c9e895ee86e9c8a3e223bdfdfba5a6 Merge: e84295c... 17de304... Author: Jiri Slaby Date: Sat Jun 23 12:53:48 2007 +0200 Merge with git+ssh://xslaby@decibel/home/xslaby/public_html/git/madwifi-openhal2 commit e84295c46eb56b29f8abb6d07f27c53cc2a74a32 Author: Jiri Slaby Date: Fri Jun 22 14:53:57 2007 +0200 check for null rates diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 6a65fe7..4c6bfcc 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -272,6 +272,9 @@ static inline unsigned int ath_copy_rates(struct ieee80211_rate *rates, { unsigned int i; + if (rt == NULL) + return 0; + for (i = 0; i < rt->rate_count; i++, rates++) { rates->rate = rt->rates[i].rate_kbps / 100; rates->val = rt->rates[i].rate_code; commit e868e1e53256928c50c67fa0331073a6f8f48eb1 Author: Jiri Slaby Date: Fri Jun 22 11:11:25 2007 +0200 several cleanups diff --git a/ath/if_ath.c b/ath/if_ath.c index 02518fe..ed978b0 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -2317,7 +2317,7 @@ ath_mode_init(struct net_device *dev) // ath5k_hw_set_rx_filter(ah, rfilt); /* configure operational mode */ - ath5k_hw_set_pcu_config(ah); + ath5k_hw_set_opmode(ah); /* * Handle any link-level address change. Note that we only diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 731f5a8..6de3c16 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -1042,7 +1042,6 @@ typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ieee80211_channel *, /* General Functions */ u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); -unsigned int ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) ; /* Attach/Detach Functions */ struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); @@ -1066,7 +1065,6 @@ bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); /* Interrupt handling */ bool ath5k_hw_is_intr_pending(struct ath_hw *hal); bool ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask); -u32 ath5k_hw_get_intr(struct ath_hw *hal); enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ @@ -1076,7 +1074,6 @@ int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); -void ath5k_hw_set_pcu_config(struct ath_hw *hal); /* BSSID Functions */ void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 99e5982..4bf7c42 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -180,23 +180,6 @@ ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, } /* - * Return the supported 802.11 operation modes - * TODO:Left here for combatibility, change it in at5k - */ -unsigned int/*TODO:Fix this */ -ath_hal_getwirelessmodes(struct ath_hw *hal, enum ieee80211_countrycode country) -{ - switch(hal->ah_version){ - case AR5K_AR5212: - return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; - case AR5K_AR5211: - return AR5K_MODE_11A|AR5K_MODE_11B|AR5K_MODE_11G; - default : - return(AR5K_MODE_11A); - } -} - -/* * Functions used internaly */ @@ -213,14 +196,12 @@ ath5k_hw_bitswap(u32 val, unsigned int bits) return retval; } -inline unsigned int -ath5k_hw_htoclock(unsigned int usec, bool turbo) +static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) { return turbo == true ? (usec * 80) : (usec * 40); } -inline unsigned int -ath5k_hw_clocktoh(unsigned int clock, bool turbo) +static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) { return turbo == true ? (clock / 80) : (clock / 40); } @@ -228,7 +209,7 @@ ath5k_hw_clocktoh(unsigned int clock, bool turbo) /* * Copy a rate table to a new one */ -inline void +static inline void ath5k_hw_rtcopy(struct ath5k_rate_table *dst, const struct ath5k_rate_table *src) { memset(dst, 0, sizeof(struct ath5k_rate_table)); @@ -1817,17 +1798,6 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) } /* - * Return the interrupt mask stored previously - * TODO: Remove ? - */ -u32 -ath5k_hw_get_intr(struct ath_hw *hal) -{ - AR5K_TRACE; - return hal->ah_imr; -} - -/* * Set interrupt mask */ enum ath5k_int @@ -2606,13 +2576,6 @@ ath5k_hw_set_opmode(struct ath_hw *hal) AR5K_REG_WRITE(AR5K_BCR, beacon_reg); } -void /*TODO: Get rid of this, clean up the driver code, only set_opmode is needed*/ -ath5k_hw_set_pcu_config(struct ath_hw *hal) -{ - AR5K_TRACE; - ath5k_hw_set_opmode(hal); -} - /* * BSSID Functions */ commit 5c4375df170ac3e4fdd971bdac02a919881fea50 Author: Jiri Slaby Date: Fri Jun 22 11:02:46 2007 +0200 remove ath5k_known_products diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index d941be3..99e5982 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -30,46 +30,6 @@ #include "ath5k.h" #include "ath5kreg.h" -/* - * Known pci ids - */ - -static const struct { - u16 vendor; - u16 device; - u8 mac_version; -} ath5k_known_products[] = { - /* - * From pcidevs_data.h - */ - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210, AR5K_AR5210}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210_AP, AR5K_AR5210}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT, AR5K_AR5210}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5311, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY, AR5K_AR5211}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_FPGA, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_IBM, AR5K_AR5212}, - { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CRDAG675, AR5K_AR5212}, - { PCI_VENDOR_ID_3COM_2, PCI_DEVICE_ID_3COM_2_3CRPAG175, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV2, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV7, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_REV8, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0014, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0015, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0016, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0017, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0018, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_0019, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR2413, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5413, AR5K_AR5212}, - { PCI_VENDOR_ID_ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5424, AR5K_AR5212}, -}; - /*Rate tables*/ static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; commit 6c6240b10efc54eb3e867dbc1fd90accaebbb8fd Author: Jiri Slaby Date: Sat Jun 23 13:01:45 2007 +0200 don't copy and store rates in ath_hw diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 6de3c16..1aa8e37 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -952,12 +952,6 @@ struct ath_hw { bool ah_single_chip; enum ath5k_rfgain ah_rf_gain; - struct ath5k_rate_table ah_rt_11a; - struct ath5k_rate_table ah_rt_11b; - struct ath5k_rate_table ah_rt_11g; - struct ath5k_rate_table ah_rt_turbo; - struct ath5k_rate_table ah_rt_xr; - u32 ah_mac_srev; u16 ah_mac_version; u16 ah_mac_revision; diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 4bf7c42..6826e9c 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -207,17 +207,6 @@ static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) } /* - * Copy a rate table to a new one - */ -static inline void -ath5k_hw_rtcopy(struct ath5k_rate_table *dst, const struct ath5k_rate_table *src) -{ - memset(dst, 0, sizeof(struct ath5k_rate_table)); - dst->rate_count = src->rate_count; - memcpy(dst->rates, src->rates, sizeof(dst->rates)); -} - -/* * Read from a device register */ static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg) @@ -444,18 +433,6 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, ath5k_hw_set_lladdr(hal, mac); - /* Get rate tables */ - if (hal->ah_capabilities.cap_mode & AR5K_MODE_11A) - ath5k_hw_rtcopy(&hal->ah_rt_11a, &ath5k_rt_11a); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_11B) - ath5k_hw_rtcopy(&hal->ah_rt_11b, &ath5k_rt_11b); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_11G) - ath5k_hw_rtcopy(&hal->ah_rt_11g, &ath5k_rt_11g); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_TURBO) - ath5k_hw_rtcopy(&hal->ah_rt_turbo, &ath5k_rt_turbo); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_XR) - ath5k_hw_rtcopy(&hal->ah_rt_xr, &ath5k_rt_xr); - /* Initialize the gain optimization values */ /*For RF5111*/ if (hal->ah_radio == AR5K_RF5111) { @@ -671,17 +648,21 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) { AR5K_TRACE; + /* Get rate tables */ + if (!(hal->ah_capabilities.cap_mode & mode)) + return NULL; + switch (mode) { case AR5K_MODE_11A: - return &hal->ah_rt_11a; + return &ath5k_rt_11a; case AR5K_MODE_TURBO: - return &hal->ah_rt_turbo; + return &ath5k_rt_turbo; case AR5K_MODE_11B: - return &hal->ah_rt_11b; + return &ath5k_rt_11b; case AR5K_MODE_11G: - return &hal->ah_rt_11g; + return &ath5k_rt_11g; case AR5K_MODE_XR: - return &hal->ah_rt_xr; + return &ath5k_rt_xr; default: return NULL; } commit c7386335a5a34b03530adba5f07b2571f23b5f2b Author: Jiri Slaby Date: Sat Jun 23 13:51:55 2007 +0200 remove AR5K_MODEs and AR5K_CHIPs diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 4c6bfcc..08ae745 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -341,13 +341,13 @@ static int ath_getchannels(struct ieee80211_hw *hw) modes[A].rates = sc->rates; modes[A].num_rates = ath_copy_rates(modes[A].rates, - ath5k_hw_get_rate_table(ah, AR5K_MODE_11A)); + ath5k_hw_get_rate_table(ah, MODE_IEEE80211A)); modes[B].rates = &modes[A].rates[modes[A].num_rates]; modes[B].num_rates = ath_copy_rates(modes[B].rates, - ath5k_hw_get_rate_table(ah, AR5K_MODE_11B)); + ath5k_hw_get_rate_table(ah, MODE_IEEE80211B)); modes[G].rates = &modes[B].rates[modes[B].num_rates]; modes[G].num_rates = ath_copy_rates(modes[G].rates, - ath5k_hw_get_rate_table(ah, AR5K_MODE_11G)); + ath5k_hw_get_rate_table(ah, MODE_IEEE80211G)); /* * In debugging mode, enable all channels supported by the chipset diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 1aa8e37..54c1a78 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -13,35 +13,22 @@ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for Atheros Wireless LAN devices. - * - * ar5k is a free replacement of the binary-only HAL used by some drivers - * for Atheros chipsets. While using a different ABI, it tries to be - * source-compatible with the original (non-free) HAL interface. - * - * Many thanks to various contributors who supported the development of - * ar5k with hard work and useful information. And, of course, for all the - * people who encouraged me to continue this work which has been based - * on my initial approach found on http://team.vantronix.net/ar5k/. */ #ifndef _AR5K_H #define _AR5K_H /* Set this to 1 to disable regulatory domain restrictions for channel tests. - * WARNING: This is for debuging only and has side effects (eg. scan takes too long - * and results timeouts). It's also illegal to tune to some of the supported frequencies - * in some countries, so use this at your own risk, you 've been warned. */ + * WARNING: This is for debuging only and has side effects (eg. scan takes too + * long and results timeouts). It's also illegal to tune to some of the + * supported frequencies in some countries, so use this at your own risk, + * you've been warned. */ #define CHAN_DEBUG 1 -/* Uncomment this for debuging (warning that results TOO much output) */ +/* Uncomment this for debuging (warning that it results in TOO much output) */ /*#define AR5K_DEBUG 1 */ +#include #include #include "ath5k_hw.h" @@ -556,22 +543,6 @@ struct ath_desc { #define AR5K_TXDESC_INTREQ 0x0010 #define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ -/* - * 802.11 operating modes... - */ -#define AR5K_MODE_11A 0x01 -#define AR5K_MODE_11B 0x02 -#define AR5K_MODE_11G 0x04 -#define AR5K_MODE_TURBO 0x08 -#define AR5K_MODE_108G 0x10 -#define AR5K_MODE_XR 0x20 -#define AR5K_MODE_ALL (AR5K_MODE_11A | \ - AR5K_MODE_11B | \ - AR5K_MODE_11G | \ - AR5K_MODE_TURBO | \ - AR5K_MODE_108G | \ - AR5K_MODE_XR) - #define AR5K_SLOT_TIME_9 396 #define AR5K_SLOT_TIME_20 880 #define AR5K_SLOT_TIME_MAX 0xffff @@ -606,16 +577,8 @@ struct ath_desc { * Used internaly in OpenHAL (ar5211.c/ar5212.c * for reset_tx_queue). Also see struct struct ieee80211_channel. */ -#define IS_CHAN_XR(_c) \ - ((_c.val & CHANNEL_XR) != 0) - -#define IS_CHAN_B(_c) \ - ((_c.val & CHANNEL_B) != 0) - -enum ath5k_chip{ - AR5K_CHIP_5GHZ = CHANNEL_5GHZ, - AR5K_CHIP_2GHZ = CHANNEL_2GHZ, -}; +#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) +#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) /* * The following structure will be used to map 2GHz channels to @@ -789,7 +752,7 @@ enum ath5k_ant_setting { */ /* - * These are maped to take advantage of some common bits + * These are mapped to take advantage of some common bits * between the MAC chips, to be able to set intr properties * easier. Some of them are not used yet inside OpenHAL. */ @@ -889,7 +852,7 @@ struct ath5k_capabilities { * Supported PHY modes * (ie. CHANNEL_A, CHANNEL_B, ...) */ - u16 cap_mode; + DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); /* * Frequency range (without regulation restrictions) diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 6826e9c..091010b 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -40,7 +40,7 @@ static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; /*Prototypes*/ static int ath5k_hw_nic_reset(struct ath_hw *, u32); static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool); -static u16 ath5k_hw_radio_revision(struct ath_hw *, enum ath5k_chip); +static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int); static bool ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int); static bool ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, @@ -369,14 +369,13 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); hal->ah_phy_revision = AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; - hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal, - AR5K_CHIP_5GHZ); + hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ); if (hal->ah_version == AR5K_AR5210) { hal->ah_radio_2ghz_revision = 0; } else { hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal, - AR5K_CHIP_2GHZ); + CHANNEL_2GHZ); } /* Single chip radio */ @@ -593,7 +592,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) * Get the PHY Chip revision */ static u16 -ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip) +ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) { int i; u32 srev; @@ -604,11 +603,11 @@ ath5k_hw_radio_revision(struct ath_hw *hal, enum ath5k_chip chip) /* * Set the radio chip access register */ - switch (chip) { - case AR5K_CHIP_2GHZ: + switch (chan) { + case CHANNEL_2GHZ: AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_2GHZ); break; - case AR5K_CHIP_5GHZ: + case CHANNEL_5GHZ: AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); break; default: @@ -649,19 +648,19 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) AR5K_TRACE; /* Get rate tables */ - if (!(hal->ah_capabilities.cap_mode & mode)) + if (!test_bit(mode, hal->ah_capabilities.cap_mode)) return NULL; switch (mode) { - case AR5K_MODE_11A: + case MODE_IEEE80211A: return &ath5k_rt_11a; - case AR5K_MODE_TURBO: + case MODE_ATHEROS_TURBO: return &ath5k_rt_turbo; - case AR5K_MODE_11B: + case MODE_IEEE80211B: return &ath5k_rt_11b; - case AR5K_MODE_11G: + case MODE_IEEE80211G: return &ath5k_rt_11g; - case AR5K_MODE_XR: + case MODE_ATHEROS_TURBOG: return &ath5k_rt_xr; default: return NULL; @@ -917,7 +916,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (!(channel->val & CHANNEL_B)) { /*Get rate table for this operation mode*/ - rt = ath5k_hw_get_rate_table(hal, AR5K_MODE_11B); + rt = ath5k_hw_get_rate_table(hal, + MODE_IEEE80211B); /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { @@ -939,7 +939,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Get rate table for this operation mode*/ rt = ath5k_hw_get_rate_table(hal, channel->val & CHANNEL_TURBO ? - AR5K_MODE_TURBO : AR5K_MODE_XR); + MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG); /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { @@ -2446,7 +2446,8 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) hal->ah_capabilities.cap_range.range_2ghz_max = 0; /* Set supported modes */ - hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO; + set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); + set_bit(MODE_ATHEROS_TURBO, hal->ah_capabilities.cap_mode); } else { /* * XXX The tranceiver supports frequencies from 4920 to 6100GHz @@ -2467,8 +2468,12 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) hal->ah_capabilities.cap_range.range_5ghz_max = 6100; /* Set supported modes */ - hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO | - (hal->ah_version == AR5K_AR5212 ? AR5K_MODE_XR : 0); + set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); + set_bit(MODE_ATHEROS_TURBO, + hal->ah_capabilities.cap_mode); + if (hal->ah_version == AR5K_AR5212) + set_bit(MODE_ATHEROS_TURBOG, + hal->ah_capabilities.cap_mode); } /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ @@ -2477,10 +2482,12 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) hal->ah_capabilities.cap_range.range_2ghz_max = 2732; if (AR5K_EEPROM_HDR_11B(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; + set_bit(MODE_IEEE80211B, + hal->ah_capabilities.cap_mode); if (AR5K_EEPROM_HDR_11G(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; + set_bit(MODE_IEEE80211G, + hal->ah_capabilities.cap_mode); } } commit a5df5c89bcd6974f7c4ee2bed89bedd5189ee8d7 Author: Jiri Slaby Date: Sat Jun 23 13:53:11 2007 +0200 remove useless comments diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 08ae745..a2962ca 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -128,17 +128,11 @@ static struct ieee80211_ops ath_hw_ops = { .hw_scan = d_hw_scan*/ }; -/* - * Read from a device register - */ static inline u32 ath_hw_reg_read(struct ath_hw *hw, u16 reg) { return readl(hw->ah_sh + reg); } -/* - * Write to a device register - */ static inline void ath_hw_reg_write(struct ath_hw *hw, u32 val, u16 reg) { writel(val, hw->ah_sh + reg); @@ -146,9 +140,6 @@ static inline void ath_hw_reg_write(struct ath_hw *hw, u32 val, u16 reg) #define ATH_HW_IRQ_PENDING 0x4008 -/* - * Interrupt handler. Most of the actual processing is deferred. - */ static irqreturn_t ath_intr(int irq, void *dev_id) { struct net_device *dev = dev_id; commit d824e5bcfec6e1f475be2b740219811313fea2a1 Author: Jiri Slaby Date: Sat Jun 23 14:07:48 2007 +0200 isr cleanup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index a2962ca..3c789bf 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -46,9 +46,9 @@ } \ } while (0) -#define DPRINTF(sc, _m, _fmt...) do { \ - if (sc->sc_debug & (_m)) \ - printk(_fmt); \ +#define DPRINTF(sc, _m, _fmt...) do { \ + if (sc->sc_debug & (_m) && printk_ratelimit()) \ + printk(_fmt); \ } while (0) enum { ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ @@ -128,45 +128,16 @@ static struct ieee80211_ops ath_hw_ops = { .hw_scan = d_hw_scan*/ }; -static inline u32 ath_hw_reg_read(struct ath_hw *hw, u16 reg) -{ - return readl(hw->ah_sh + reg); -} - -static inline void ath_hw_reg_write(struct ath_hw *hw, u32 val, u16 reg) -{ - writel(val, hw->ah_sh + reg); -} - -#define ATH_HW_IRQ_PENDING 0x4008 - static irqreturn_t ath_intr(int irq, void *dev_id) { - struct net_device *dev = dev_id; - struct ath_softc *sc = dev->priv; + struct ath_softc *sc = dev_id; struct ath_hw *ah = sc->ah; enum ath5k_int status; - int needmark; + unsigned int counter = 1000; - if (sc->sc_invalid) { - /* - * The hardware is not ready/present, don't touch anything. - * Note this can happen early on if the IRQ is shared. - */ - DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); - return IRQ_NONE; - } - if (!ath_hw_reg_read(ah, ATH_HW_IRQ_PENDING)) + if (sc->sc_invalid || !ath5k_hw_is_intr_pending(ah)) return IRQ_NONE; return IRQ_HANDLED; - if ((dev->flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", - __func__, dev->flags); - ath5k_hw_get_isr(ah, &status); /* clear ISR */ - ath5k_hw_set_intr(ah, 0); /* disable further intr's */ - return IRQ_HANDLED; - } - needmark = 0; do { /* @@ -186,11 +157,11 @@ return IRQ_HANDLED; * by the hal. */ sc->sc_stats.ast_hardware++; - ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ + ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ tasklet_schedule(&sc->sc_fataltq); } else if (status & AR5K_INT_RXORN) { sc->sc_stats.ast_rxorn++; - ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ + ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ tasklet_schedule(&sc->sc_rxorntq); } else { if (status & AR5K_INT_SWBA) { @@ -242,7 +213,11 @@ return IRQ_HANDLED; ath5k_hw_set_intr(ah, sc->sc_imask); } } - } while (ath5k_hw_is_intr_pending(ah)); + } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); + + if (!counter) + printk(KERN_WARNING "ath: too much interrupts, giving up for " + "now\n"); return IRQ_HANDLED; } diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 091010b..df71d23 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -1703,11 +1703,10 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) /* * Check if we have pending interrupts */ -bool -ath5k_hw_is_intr_pending(struct ath_hw *hal) +bool ath5k_hw_is_intr_pending(struct ath_hw *hal) { AR5K_TRACE; - return AR5K_REG_READ(AR5K_INTPEND) == true ? true : false; + return AR5K_REG_READ(AR5K_INTPEND); } /* commit 251729806f557f9fbf5b6aa3e4762fca31cfe10e Author: Jiri Slaby Date: Sat Jun 23 15:01:12 2007 +0200 get rid of AR5K_REG_READ/WRITE macros. add hw as parameter to other macros diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index df71d23..9d0e883 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -252,7 +252,7 @@ static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, u32 data; for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { - data = AR5K_REG_READ(reg); + data = ath5k_hw_reg_read(hal, reg); if ((is_set == true) && (data & flag)) break; else if ((data & flag) == val) @@ -364,11 +364,11 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, goto err_free; /* Get MAC, PHY and RADIO revisions */ - srev = AR5K_REG_READ(AR5K_SREV); + srev = ath5k_hw_reg_read(hal, AR5K_SREV); hal->ah_mac_srev = srev; hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); - hal->ah_phy_revision = AR5K_REG_READ(AR5K_PHY_CHIP_ID) & 0x00ffffffff; + hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff; hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ); if (hal->ah_version == AR5K_AR5210) { @@ -542,7 +542,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) /* ...enable Atheros turbo mode if requested */ if (flags & CHANNEL_TURBO) - AR5K_REG_WRITE(AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE); + ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO); /* ...reset chipset */ if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) { @@ -578,11 +578,11 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) if (hal->ah_version != AR5K_AR5210){ /* ...set the PHY operating mode */ - AR5K_REG_WRITE(AR5K_PHY_PLL, clock); + ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL); udelay(300); - AR5K_REG_WRITE(AR5K_PHY_MODE, mode); - AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); + ath5k_hw_reg_write(hal, mode, AR5K_PHY_MODE); + ath5k_hw_reg_write(hal, turbo, AR5K_PHY_TURBO); } return 0; @@ -605,10 +605,10 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) */ switch (chan) { case CHANNEL_2GHZ: - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_2GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); break; case CHANNEL_5GHZ: - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); break; default: return 0; @@ -617,23 +617,23 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) mdelay(2); /* ...wait until PHY is ready and read the selected radio revision */ - AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16); + ath5k_hw_reg_write(hal, 0x00001c16, AR5K_PHY(0x34)); for (i = 0; i < 8; i++) - AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000); + ath5k_hw_reg_write(hal, 0x00010000, AR5K_PHY(0x20)); if (hal->ah_version == AR5K_AR5210) { - srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf; + srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf; ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; } else { - srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff; + srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff; ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); } /* Reset to the 5GHz mode */ - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); return ret; } @@ -715,16 +715,16 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (hal->ah_version != AR5K_AR5210) { if (change_channel == true) { /*Sequence number for queue 0 -do this for all queues ?*/ - s_seq = AR5K_REG_READ(AR5K_QUEUE_DFS_SEQNUM(0)); + s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0)); /*Default antenna*/ - s_ant = AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); } } /*GPIOs*/ - s_led[0] = AR5K_REG_READ(AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; - s_led[1] = AR5K_REG_READ(AR5K_GPIOCR); - s_led[2] = AR5K_REG_READ(AR5K_GPIODO); + s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; + s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR); + s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO); if (change_channel == true && hal->ah_rf_banks != NULL) ath5k_hw_get_rf_gain(hal); @@ -795,7 +795,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, } /* PHY access enable */ - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); /* * Write initial RF registers on 5211 @@ -824,16 +824,18 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5212_mode[i].mode_register, - ar5212_mode[i].mode_value[off][mode]); + ath5k_hw_reg_write(hal, + ar5212_mode[i].mode_value[off][mode], + (u32)ar5212_mode[i].mode_register); } } /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5211_mode[i].mode_register, - ar5211_mode[i].mode_value[mode]); + ath5k_hw_reg_write(hal, + ar5211_mode[i].mode_value[mode], + (u32)ar5211_mode[i].mode_register); } } @@ -854,8 +856,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (hal->ah_radio == AR5K_RF5112 && ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5212_ini[i].ini_register, - ar5212_ini[i].ini_value); + ath5k_hw_reg_write(hal, + ar5212_ini[i].ini_value, + (u32)ar5212_ini[i].ini_register); } } } @@ -868,8 +871,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, continue; AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ar5211_ini[i].ini_register, - ar5211_ini[i].ini_value); + ath5k_hw_reg_write(hal, + ar5211_ini[i].ini_value, + (u32)ar5211_ini[i].ini_register); } } /*For 5210*/ @@ -883,13 +887,13 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, switch (ar5210_ini[i].ini_mode) { case AR5K_INI_READ: /* Cleared on read */ - AR5K_REG_READ(ar5210_ini[i].ini_register); + ath5k_hw_reg_read(hal, ar5210_ini[i].ini_register); break; case AR5K_INI_WRITE: default: - AR5K_REG_WRITE(ar5210_ini[i].ini_register, - ar5210_ini[i].ini_value); + ath5k_hw_reg_write(hal, ar5210_ini[i].ini_value, + ar5210_ini[i].ini_register); } } @@ -922,14 +926,16 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { data = AR5K_RATE_DUR(rt->rates[i].rate_code); - AR5K_REG_WRITE(data, - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false)); + ath5k_hw_reg_write(hal, + ath_hal_computetxtime(hal, rt, + 14, rt->rates[i].control_rate, + false), data); if (HAS_SHPREAMBLE(i)) { - AR5K_REG_WRITE(data + - (AR5K_SET_SHORT_PREAMBLE << 2), + ath5k_hw_reg_write(hal, ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false)); + rt->rates[i].control_rate, false), + data + + (AR5K_SET_SHORT_PREAMBLE << 2)); } } @@ -943,24 +949,26 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Write rate duration table*/ for (i = 0; i < rt->rate_count; i++) { - AR5K_REG_WRITE(AR5K_RATE_DUR(rt->rates[i].rate_code), - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false)); + ath5k_hw_reg_write(hal, + ath_hal_computetxtime(hal, rt, + 14, rt->rates[i].control_rate, + false), + AR5K_RATE_DUR(rt->rates[i].rate_code)); } } } /* Fix for first revision of the RF5112 RF chipset */ - if (hal->ah_radio >= AR5K_RF5112 && - hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { - AR5K_REG_WRITE(AR5K_PHY_CCKTXCTL, - AR5K_PHY_CCKTXCTL_WORLD); + if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision< + AR5K_SREV_RAD_5112A) { + ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD, + AR5K_PHY_CCKTXCTL); if (channel->val & CHANNEL_A) data = 0xffb81020; else data = 0xffb80d20; - AR5K_REG_WRITE(AR5K_PHY_FRAME_CTL, data); + ath5k_hw_reg_write(hal, data, AR5K_PHY_FRAME_CTL); } /* @@ -1005,9 +1013,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ds_coef_man = coef_man >> (24 - coef_exp); ds_coef_exp = coef_exp - 16; - AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); - AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); } } @@ -1016,15 +1024,15 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (enable 2111 frequency converter + CCK)*/ if (hal->ah_radio == AR5K_RF5111) { if (channel->val & CHANNEL_B) - AR5K_REG_ENABLE_BITS(AR5K_TXCFG, + AR5K_REG_ENABLE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_B_MODE); else - AR5K_REG_DISABLE_BITS(AR5K_TXCFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_B_MODE); } /* Set antenna mode */ - AR5K_REG_MASKED_BITS(AR5K_PHY(0x44), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44), hal->ah_antenna[ee_mode][0], 0xfffffc06); if (freq == AR5K_INI_RFGAIN_2GHZ) @@ -1033,46 +1041,47 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ant[0] = ant[1] = AR5K_ANT_FIXED_A; - AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_0, - hal->ah_antenna[ee_mode][ant[0]]); - AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_1, - hal->ah_antenna[ee_mode][ant[1]]); + ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]], + AR5K_PHY_ANT_SWITCH_TABLE_0); + ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[1]], + AR5K_PHY_ANT_SWITCH_TABLE_1); /* Commit values from EEPROM */ if (hal->ah_radio == AR5K_RF5111) - AR5K_REG_WRITE_BITS(AR5K_PHY_FRAME_CTL, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_FRAME_CTL, AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); - AR5K_REG_WRITE(AR5K_PHY(0x5a), - AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); + ath5k_hw_reg_write(hal, + AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), + AR5K_PHY(0x5a)); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x11), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11), (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x12), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12), (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x14), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14), (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); - AR5K_REG_WRITE(AR5K_PHY(0x0d), - (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | - (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | - (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | - (ee->ee_tx_frm2xpa_enable[ee_mode])); + ath5k_hw_reg_write(hal, + (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | + (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | + (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | + (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x0a), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a), ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x19), + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19), (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x49), 4, 0xffffff01); + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01); - AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | ee->ee_q_cal[ee_mode]); if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - AR5K_REG_WRITE_BITS(AR5K_PHY_GAIN_2GHZ, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ, AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, ee->ee_margin_tx_rx[ee_mode]); } @@ -1080,7 +1089,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, } else { mdelay(1); /* Disable phy and wait */ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); mdelay(1); } @@ -1089,12 +1098,12 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, */ /*DCU/Antenna selection not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_SEQNUM(0), s_seq); - AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, s_ant); + ath5k_hw_reg_write(hal, s_seq, AR5K_QUEUE_DFS_SEQNUM(0)); + ath5k_hw_reg_write(hal, s_ant, AR5K_DEFAULT_ANTENNA); } - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, s_led[0]); - AR5K_REG_WRITE(AR5K_GPIOCR, s_led[1]); - AR5K_REG_WRITE(AR5K_GPIODO, s_led[2]); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, s_led[0]); + ath5k_hw_reg_write(hal, s_led[1], AR5K_GPIOCR); + ath5k_hw_reg_write(hal, s_led[2], AR5K_GPIODO); /* * Misc @@ -1104,14 +1113,14 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ath5k_hw_set_opmode(hal); /*PISR/SISR Not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_PISR, 0xffffffff); + ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR); /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so - * direct write using AR5K_REG_WRITE seems wrong. Test with: - * AR5K_REG_WRITE_BITS(AR5K_RSSI_THR, + * direct write using ath5k_hw_reg_write seems wrong. Test with: + * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); * with different variables and check results compared - * to AR5K_REG_WRITE() */ - AR5K_REG_WRITE(AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES); + * to ath5k_hw_reg_write(hal, ) */ + ath5k_hw_reg_write(hal, AR5K_TUNE_RSSI_THRES, AR5K_RSSI_THR); } /* @@ -1119,9 +1128,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, *(passing dma size not available on 5210) */ if (hal->ah_version != AR5K_AR5210) { - AR5K_REG_WRITE_BITS(AR5K_TXCFG, AR5K_TXCFG_SDMAMR, + AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); - AR5K_REG_WRITE_BITS(AR5K_RXCFG, AR5K_RXCFG_SDMAMW, + AR5K_REG_WRITE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_512B); } @@ -1134,13 +1143,13 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Enable the PHY and wait until completion */ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); /* * 5111/5112 Specific */ if (hal->ah_version != AR5K_AR5210) { - data = AR5K_REG_READ(AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; + data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; data = (channel->val & CHANNEL_CCK) ? ((data << 2) / 22) : (data / 10); @@ -1152,7 +1161,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Enable calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -1165,7 +1174,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Enable noise floor calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -1178,7 +1187,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* Wait until the noise floor is calibrated and read the value */ for (i = 20; i > 0; i--) { mdelay(1); - noise_floor = AR5K_REG_READ(AR5K_PHY_NF); + noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) @@ -1198,9 +1207,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (!(channel->val & CHANNEL_B)) { hal->ah_calibration = true; - AR5K_REG_WRITE_BITS(AR5K_PHY_IQ, + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); - AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); } @@ -1210,7 +1219,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { /*No QCU on 5210*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i); + AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i); if (ath5k_hw_reset_tx_queue(hal, i) == false) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); @@ -1242,19 +1251,20 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * Set the 32MHz reference clock on 5212 phy clock sleep register */ if (hal->ah_version == AR5K_AR5212) { - AR5K_REG_WRITE(AR5K_PHY_SCR, AR5K_PHY_SCR_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SLMT, AR5K_PHY_SLMT_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SCAL, AR5K_PHY_SCAL_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SCLOCK, AR5K_PHY_SCLOCK_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SDELAY, AR5K_PHY_SDELAY_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SPENDING, hal->ah_radio == AR5K_RF5111 ? - AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112); + ath5k_hw_reg_write(hal, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR); + ath5k_hw_reg_write(hal, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); + ath5k_hw_reg_write(hal, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL); + ath5k_hw_reg_write(hal, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); + ath5k_hw_reg_write(hal, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); + ath5k_hw_reg_write(hal, hal->ah_radio == AR5K_RF5111 ? + AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112, + AR5K_PHY_SPENDING); } /* * Disable beacons and reset the register */ - AR5K_REG_DISABLE_BITS(AR5K_BEACON, + AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); return 0; @@ -1271,12 +1281,12 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) AR5K_TRACE; /* Read-and-clear RX Descriptor Pointer*/ - AR5K_REG_READ(AR5K_RXDP); + ath5k_hw_reg_read(hal, AR5K_RXDP); /* * Reset the device and wait until success */ - AR5K_REG_WRITE(AR5K_RESET_CTL, val); + ath5k_hw_reg_write(hal, val, AR5K_RESET_CTL); /* Wait at least 128 PCI clocks */ udelay(15); @@ -1298,7 +1308,7 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) * Reset configuration register (for hw byte-swap) */ if ((val & AR5K_RESET_CTL_PCU) == 0) - AR5K_REG_WRITE(AR5K_CFG, AR5K_INIT_CFG); + ath5k_hw_reg_write(hal, AR5K_INIT_CFG, AR5K_CFG); return ret; } @@ -1317,7 +1327,7 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, int i; AR5K_TRACE; - staid = AR5K_REG_READ(AR5K_STA_ID1); + staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1); switch (mode) { case AR5K_PM_AUTO: @@ -1325,16 +1335,17 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, /* fallthrough */ case AR5K_PM_NETWORK_SLEEP: if (set_chip == true) { - AR5K_REG_WRITE(AR5K_SLEEP_CTL, - AR5K_SLEEP_CTL_SLE | sleep_duration); + ath5k_hw_reg_write(hal, + AR5K_SLEEP_CTL_SLE | sleep_duration, + AR5K_SLEEP_CTL); } staid |= AR5K_STA_ID1_PWR_SV; break; case AR5K_PM_FULL_SLEEP: if (set_chip == true) { - AR5K_REG_WRITE(AR5K_SLEEP_CTL, - AR5K_SLEEP_CTL_SLE_SLP); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP, + AR5K_SLEEP_CTL); } staid |= AR5K_STA_ID1_PWR_SV; break; @@ -1343,18 +1354,18 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, if (set_chip == false) goto commit; - AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE_WAKE); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL); for (i = 5000; i > 0; i--) { /* Check if the chip did wake up */ - if ((AR5K_REG_READ(AR5K_PCICFG) & + if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_SPWR_DN) == 0) break; /* Wait a bit and retry */ udelay(200); - AR5K_REG_WRITE(AR5K_SLEEP_CTL, - AR5K_SLEEP_CTL_SLE_WAKE); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, + AR5K_SLEEP_CTL); } /* Fail if the chip didn't wake up */ @@ -1370,7 +1381,7 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, commit: hal->ah_power_mode = mode; - AR5K_REG_WRITE(AR5K_STA_ID1, staid); + ath5k_hw_reg_write(hal, staid, AR5K_STA_ID1); return 0; } @@ -1404,7 +1415,7 @@ void ath5k_hw_start_rx(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXE); + ath5k_hw_reg_write(hal, AR5K_CR_RXE, AR5K_CR); } /* @@ -1416,13 +1427,13 @@ ath5k_hw_stop_rx_dma(struct ath_hw *hal) int i; AR5K_TRACE; - AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXD); + ath5k_hw_reg_write(hal, AR5K_CR_RXD, AR5K_CR); /* * It may take some time to disable the DMA receive unit */ for (i = 2000; - i > 0 && (AR5K_REG_READ(AR5K_CR) & AR5K_CR_RXE) != 0; + i > 0 && (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_RXE) != 0; i--) udelay(10); @@ -1435,7 +1446,7 @@ ath5k_hw_stop_rx_dma(struct ath_hw *hal) u32 ath5k_hw_get_rx_buf(struct ath_hw *hal) { - return AR5K_REG_READ(AR5K_RXDP); + return ath5k_hw_reg_read(hal, AR5K_RXDP); } /* @@ -1447,7 +1458,7 @@ ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) AR5K_TRACE; /*TODO:Shouldn't we check if RX is enabled first ?*/ - AR5K_REG_WRITE(AR5K_RXDP, phys_addr); + ath5k_hw_reg_write(hal, phys_addr, AR5K_RXDP); } /* @@ -1472,7 +1483,7 @@ ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) if (hal->ah_version == AR5K_AR5210) { - tx_queue = AR5K_REG_READ(AR5K_CR); + tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); /* * Set the queue by type on 5210 @@ -1483,29 +1494,27 @@ ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) break; case AR5K_TX_QUEUE_BEACON: tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - AR5K_REG_WRITE(AR5K_BSR, - AR5K_BCR_TQ1V | - AR5K_BCR_BDMAE); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | + AR5K_BCR_BDMAE, AR5K_BSR); break; case AR5K_TX_QUEUE_CAB: tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - AR5K_REG_WRITE(AR5K_BSR, - AR5K_BCR_TQ1FV | - AR5K_BCR_TQ1V | - AR5K_BCR_BDMAE); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | + AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, + AR5K_BSR); break; default: return false; } /* Start queue */ - AR5K_REG_WRITE(AR5K_CR, tx_queue); + ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); } else { /* Return if queue is disabled */ - if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXD, queue)) return false; /* Start queue */ - AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); + AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXE, queue); } return true; @@ -1529,7 +1538,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) return false; if (hal->ah_version == AR5K_AR5210) { - tx_queue = AR5K_REG_READ(AR5K_CR); + tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); /* * Set by queue type @@ -1542,29 +1551,29 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) case AR5K_TX_QUEUE_CAB: /* XXX Fix me... */ tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; - AR5K_REG_WRITE(AR5K_BSR, 0); + ath5k_hw_reg_write(hal, 0, AR5K_BSR); break; default: return false; } /* Stop queue */ - AR5K_REG_WRITE(AR5K_CR, tx_queue); + ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); } else { /* * Schedule TX disable and wait until queue is empty */ - AR5K_REG_WRITE_Q(AR5K_QCU_TXD, queue); + AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXD, queue); /*Check for pending frames*/ do { - pending = AR5K_REG_READ(AR5K_QUEUE_STATUS(queue)) & + pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) & AR5K_QCU_STS_FRMPENDCNT; udelay(100); } while (--i && pending); /* Clear register */ - AR5K_REG_WRITE(AR5K_QCU_TXD, 0); + ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD); } /*TODO: Check for success else return false*/ @@ -1602,7 +1611,7 @@ ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) tx_reg = AR5K_QUEUE_TXDP(queue); } - return AR5K_REG_READ(tx_reg); + return ath5k_hw_reg_read(hal, tx_reg); } /* @@ -1638,14 +1647,14 @@ ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) * the selected queue on QCU for 5211+ * (this won't work if the queue is still active) */ - if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, queue)) return false; tx_reg = AR5K_QUEUE_TXDP(queue); } /* Set descriptor pointer */ - AR5K_REG_WRITE(tx_reg, phys_addr); + ath5k_hw_reg_write(hal, phys_addr, tx_reg); return true; } @@ -1666,7 +1675,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) imr = ath5k_hw_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); /*TODO: Boundary check on trigger_level*/ - trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_TXCFG), + trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TXCFG), AR5K_TXCFG_TXFULL); if (increase == false) { @@ -1680,9 +1689,9 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) * Update trigger level on success */ if (hal->ah_version == AR5K_AR5210) - AR5K_REG_WRITE(AR5K_TRIG_LVL, trigger_level); + ath5k_hw_reg_write(hal, trigger_level, AR5K_TRIG_LVL); else - AR5K_REG_WRITE_BITS(AR5K_TXCFG, + AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_TXFULL, trigger_level); status = true; @@ -1706,7 +1715,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) bool ath5k_hw_is_intr_pending(struct ath_hw *hal) { AR5K_TRACE; - return AR5K_REG_READ(AR5K_INTPEND); + return ath5k_hw_reg_read(hal, AR5K_INTPEND); } /* @@ -1724,7 +1733,7 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) * on 5210 */ if (hal->ah_version == AR5K_AR5210) { - if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) { + if ((data = ath5k_hw_reg_read(hal, AR5K_ISR)) == AR5K_INT_NOCARD) { *interrupt_mask = data; return false; } @@ -1733,7 +1742,7 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) /* * Read interrupt status from the Read-And-Clear shadow register */ - data = AR5K_REG_READ(AR5K_RAC_PISR); + data = ath5k_hw_reg_read(hal, AR5K_RAC_PISR); /* * Get abstract interrupt mask (HAL-compatible) @@ -1789,7 +1798,7 @@ ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) * Disable card interrupts to prevent any race conditions * (they will be re-enabled afterwards). */ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_DISABLE); + ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); old_mask = hal->ah_imr; @@ -1816,20 +1825,20 @@ ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) if (hal->ah_version != AR5K_AR5210) { if (new_mask & AR5K_INT_FATAL) { int_mask |= AR5K_IMR_HIUERR; - AR5K_REG_ENABLE_BITS(AR5K_SIMR2, + AR5K_REG_ENABLE_BITS(hal, AR5K_SIMR2, AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR); } } - AR5K_REG_WRITE(AR5K_PIMR, int_mask); + ath5k_hw_reg_write(hal, int_mask, AR5K_PIMR); /* Store new interrupt mask */ hal->ah_imr = new_mask; /* ..re-enable interrupts */ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); + ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); return old_mask; } @@ -1847,7 +1856,7 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) */ /*Disable interupts*/ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_DISABLE); + ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); /* * Set the RXPHY interrupt to be able to detect @@ -1855,29 +1864,29 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) */ if (hal->ah_version == AR5K_AR5210) { if (enable == true) { - AR5K_REG_ENABLE_BITS(AR5K_IMR, + AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); } else { - AR5K_REG_DISABLE_BITS(AR5K_IMR, + AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); } } else { /*Also set AR5K_PHY_RADAR register on 5111/5112*/ if (enable == true) { - AR5K_REG_WRITE(AR5K_PHY_RADAR, - AR5K_PHY_RADAR_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_PIMR, - AR5K_IMR_RXPHY); + ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_ENABLE, + AR5K_PHY_RADAR); + AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, + AR5K_IMR_RXPHY); } else { - AR5K_REG_WRITE(AR5K_PHY_RADAR, - AR5K_PHY_RADAR_DISABLE); - AR5K_REG_DISABLE_BITS(AR5K_PIMR, - AR5K_IMR_RXPHY); + ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_DISABLE, + AR5K_PHY_RADAR); + AR5K_REG_DISABLE_BITS(hal, AR5K_PIMR, + AR5K_IMR_RXPHY); } } /*Re-enable interrupts*/ - AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); + ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); } @@ -1899,21 +1908,21 @@ static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) * Initialize EEPROM access */ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE); - (void)AR5K_REG_READ(AR5K_EEPROM_BASE + (4 * offset)); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); + (void)ath5k_hw_reg_read(hal, AR5K_EEPROM_BASE + (4 * offset)); } else { - AR5K_REG_WRITE(AR5K_EEPROM_BASE, offset); - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, + ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_READ); } for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { - status = AR5K_REG_READ(AR5K_EEPROM_STATUS); + status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) return -EIO; *data = (u16) - (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); + (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff); return 0; } udelay(15); @@ -1937,9 +1946,9 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) */ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); } else { - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); } /* @@ -1947,11 +1956,11 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) */ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_EEPROM_BASE + (4 * offset), data); + ath5k_hw_reg_write(hal, data, AR5K_EEPROM_BASE + (4 * offset)); } else { - AR5K_REG_WRITE(AR5K_EEPROM_BASE, offset); - AR5K_REG_WRITE(AR5K_EEPROM_DATA, data); - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); + ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); + ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); } /* @@ -1959,7 +1968,7 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) */ for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { - status = AR5K_REG_READ(AR5K_EEPROM_STATUS); + status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_WRDONE) { if (status & AR5K_EEPROM_STAT_WRERR) return EIO; @@ -2553,14 +2562,14 @@ ath5k_hw_set_opmode(struct ath_hw *hal) */ low_id = AR5K_LOW_ID(hal->ah_sta_id); high_id = AR5K_HIGH_ID(hal->ah_sta_id); - AR5K_REG_WRITE(AR5K_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_STA_ID1, pcu_reg | high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(hal, pcu_reg | high_id, AR5K_STA_ID1); /* * Set Beacon Control Register on 5210 */ if (hal->ah_version == AR5K_AR5210) - AR5K_REG_WRITE(AR5K_BCR, beacon_reg); + ath5k_hw_reg_write(hal, beacon_reg, AR5K_BCR); } /* @@ -2592,8 +2601,8 @@ ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac) low_id = AR5K_LOW_ID(mac); high_id = AR5K_HIGH_ID(mac); - AR5K_REG_WRITE(AR5K_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_STA_ID1, high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(hal, high_id, AR5K_STA_ID1); return true; } @@ -2612,8 +2621,8 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, * Set simple BSSID mask on 5212 */ if (hal->ah_version == AR5K_AR5212) { - AR5K_REG_WRITE(AR5K_BSS_IDM0, 0xfffffff); - AR5K_REG_WRITE(AR5K_BSS_IDM1, 0xfffffff); + ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM1); } /* @@ -2621,9 +2630,9 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, */ low_id = AR5K_LOW_ID(bssid); high_id = AR5K_HIGH_ID(bssid); - AR5K_REG_WRITE(AR5K_BSS_ID0, low_id); - AR5K_REG_WRITE(AR5K_BSS_ID1, high_id | - ((assoc_id & 0x3fff) << AR5K_BSS_ID1_AID_S)); + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_ID0); + ath5k_hw_reg_write(hal, high_id | ((assoc_id & 0x3fff) << + AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); memcpy(&hal->ah_bssid, bssid, ETH_ALEN); if (assoc_id == 0) { @@ -2631,7 +2640,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, return; } - AR5K_REG_WRITE_BITS(AR5K_BEACON, AR5K_BEACON_TIM, + AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM, tim_offset ? tim_offset + 4 : 0); ath5k_hw_enable_pspoll(hal, NULL, 0); @@ -2651,8 +2660,8 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) low_id = AR5K_LOW_ID(mask); high_id = AR5K_HIGH_ID(mask); - AR5K_REG_WRITE(AR5K_BSS_IDM0, low_id); - AR5K_REG_WRITE(AR5K_BSS_IDM1, high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); return true; } else @@ -2670,7 +2679,7 @@ void ath5k_hw_start_rx_pcu(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); + AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); } /* @@ -2680,7 +2689,7 @@ void ath5k_hw_stop_pcu_recv(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); + AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); } /* @@ -2696,8 +2705,8 @@ ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, { AR5K_TRACE; /* Set the multicat filter */ - AR5K_REG_WRITE(AR5K_MCAST_FILTER0, filter0); - AR5K_REG_WRITE(AR5K_MCAST_FILTER1, filter1); + ath5k_hw_reg_write(hal, filter0, AR5K_MCAST_FILTER0); + ath5k_hw_reg_write(hal, filter1, AR5K_MCAST_FILTER1); } /* @@ -2711,10 +2720,10 @@ ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) if (index >= 64) return false; else if (index >= 32) - AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1, + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, (1 << (index - 32))); else - AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0, + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; @@ -2731,10 +2740,10 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) if (index >= 64) return false; else if (index >= 32) - AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1, + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, (1 << (index - 32))); else - AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0, + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; @@ -2749,11 +2758,11 @@ ath5k_hw_get_rx_filter(struct ath_hw *hal) u32 data, filter = 0; AR5K_TRACE; - filter = AR5K_REG_READ(AR5K_RX_FILTER); + filter = ath5k_hw_reg_read(hal, AR5K_RX_FILTER); /*Radar detection for 5212*/ if (hal->ah_version == AR5K_AR5212) { - data = AR5K_REG_READ(AR5K_PHY_ERR_FIL); + data = ath5k_hw_reg_read(hal, AR5K_PHY_ERR_FIL); if (data & AR5K_PHY_ERR_FIL_RADAR) filter |= AR5K_RX_FILTER_PHYRADAR; @@ -2795,18 +2804,18 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) /*Zero length DMA*/ if (data) - AR5K_REG_ENABLE_BITS(AR5K_RXCFG, + AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); else - AR5K_REG_DISABLE_BITS(AR5K_RXCFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); /*Write RX Filter register*/ - AR5K_REG_WRITE(AR5K_RX_FILTER, filter & 0xff); + ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER); /*Write PHY error filter register on 5212*/ if (hal->ah_version == AR5K_AR5212) - AR5K_REG_WRITE(AR5K_PHY_ERR_FIL, data); + ath5k_hw_reg_write(hal, data, AR5K_PHY_ERR_FIL); } @@ -2821,7 +2830,7 @@ u32 ath5k_hw_get_tsf32(struct ath_hw *hal) { AR5K_TRACE; - return AR5K_REG_READ(AR5K_TSF_L32); + return ath5k_hw_reg_read(hal, AR5K_TSF_L32); } /* @@ -2830,10 +2839,10 @@ ath5k_hw_get_tsf32(struct ath_hw *hal) u64 ath5k_hw_get_tsf64(struct ath_hw *hal) { - u64 tsf = AR5K_REG_READ(AR5K_TSF_U32); + u64 tsf = ath5k_hw_reg_read(hal, AR5K_TSF_U32); AR5K_TRACE; - return AR5K_REG_READ(AR5K_TSF_L32) | (tsf << 32); + return ath5k_hw_reg_read(hal, AR5K_TSF_L32) | (tsf << 32); } /* @@ -2843,7 +2852,7 @@ void ath5k_hw_reset_tsf(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_ENABLE_BITS(AR5K_BEACON, + AR5K_REG_ENABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_RESET_TSF); } @@ -2885,14 +2894,14 @@ ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, * Set the beacon register and enable all timers. * (next beacon, DMA beacon, software beacon, ATIM window time) */ - AR5K_REG_WRITE(AR5K_TIMER0, next_beacon); - AR5K_REG_WRITE(AR5K_TIMER1, timer1); - AR5K_REG_WRITE(AR5K_TIMER2, timer2); - AR5K_REG_WRITE(AR5K_TIMER3, timer3); + ath5k_hw_reg_write(hal, next_beacon, AR5K_TIMER0); + ath5k_hw_reg_write(hal, timer1, AR5K_TIMER1); + ath5k_hw_reg_write(hal, timer2, AR5K_TIMER2); + ath5k_hw_reg_write(hal, timer3, AR5K_TIMER3); - AR5K_REG_WRITE(AR5K_BEACON, interval & - (AR5K_BEACON_PERIOD | AR5K_BEACON_RESET_TSF | - AR5K_BEACON_ENABLE)); + ath5k_hw_reg_write(hal, interval & (AR5K_BEACON_PERIOD | + AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE), + AR5K_BEACON); } /* @@ -2936,16 +2945,16 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * state->bs_interval; - AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, + AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_CFP_PERIOD, cfp_period); - AR5K_REG_WRITE(AR5K_CFP_DUR, state->bs_cfp_max_duration); - AR5K_REG_WRITE(AR5K_TIMER2, - (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); + ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD); + ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR); + ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period : + next_cfp)) << 3, AR5K_TIMER2); } else { /* Disable PCF mode */ - AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); } @@ -2953,17 +2962,16 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * /* * Enable the beacon timer register */ - AR5K_REG_WRITE(AR5K_TIMER0, state->bs_next_beacon); + ath5k_hw_reg_write(hal, state->bs_next_beacon, AR5K_TIMER0); /* * Start the beacon timers */ - AR5K_REG_WRITE(AR5K_BEACON, - (AR5K_REG_READ(AR5K_BEACON) &~ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_BEACON) &~ (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, - AR5K_BEACON_PERIOD)); + AR5K_BEACON_PERIOD), AR5K_BEACON); /* * Write new beacon miss threshold, if it appears to be valid @@ -2972,7 +2980,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * setting value to a largest value and seeing which values register. */ - AR5K_REG_WRITE_BITS(AR5K_RSSI_THR, + AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); /* @@ -2980,7 +2988,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * XXX: Didn't find this in 5210 code but since this register * exists also in ar5k's 5210 headers i leave it as common code. */ - AR5K_REG_WRITE_BITS(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, + AR5K_REG_WRITE_BITS(hal, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, (state->bs_sleep_duration - 3) << 3); /* @@ -3003,21 +3011,20 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * next_beacon = interval == dtim ? state->bs_next_dtim: state->bs_next_beacon; - AR5K_REG_WRITE(AR5K_SLEEP0, + ath5k_hw_reg_write(hal, AR5K_REG_SM((state->bs_next_dtim - 3) << 3, AR5K_SLEEP0_NEXT_DTIM) | AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | AR5K_SLEEP0_ENH_SLEEP_EN | - AR5K_SLEEP0_ASSUME_DTIM); + AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); - AR5K_REG_WRITE(AR5K_SLEEP1, - AR5K_REG_SM((next_beacon - 3) << 3, + ath5k_hw_reg_write(hal, AR5K_REG_SM((next_beacon - 3) << 3, AR5K_SLEEP1_NEXT_TIM) | - AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO)); + AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); - AR5K_REG_WRITE(AR5K_SLEEP2, + ath5k_hw_reg_write(hal, AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | - AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER)); + AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); } } @@ -3031,15 +3038,15 @@ ath5k_hw_reset_beacon(struct ath_hw *hal) /* * Disable beacon timer */ - AR5K_REG_WRITE(AR5K_TIMER0, 0); + ath5k_hw_reg_write(hal, 0, AR5K_TIMER0); /* * Disable some beacon register values */ - AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_BEACON, AR5K_BEACON_PERIOD); + ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON); } /* @@ -3061,16 +3068,16 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) * Control Register and Beacon Status Register. */ for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && - (AR5K_REG_READ(AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && - (AR5K_REG_READ(AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); + (ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && + (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); /* Timeout... */ if (i <= 0) { /* * Re-schedule the beacon queue */ - AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, phys_addr); - AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE); + ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR); return false; } @@ -3082,7 +3089,7 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true; - if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) return false; } @@ -3097,18 +3104,18 @@ ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statist { AR5K_TRACE; /* Read-And-Clear */ - statistics->ackrcv_bad += AR5K_REG_READ(AR5K_ACK_FAIL); - statistics->rts_bad += AR5K_REG_READ(AR5K_RTS_FAIL); - statistics->rts_good += AR5K_REG_READ(AR5K_RTS_OK); - statistics->fcs_bad += AR5K_REG_READ(AR5K_FCS_FAIL); - statistics->beacons += AR5K_REG_READ(AR5K_BEACON_CNT); + statistics->ackrcv_bad += ath5k_hw_reg_read(hal, AR5K_ACK_FAIL); + statistics->rts_bad += ath5k_hw_reg_read(hal, AR5K_RTS_FAIL); + statistics->rts_good += ath5k_hw_reg_read(hal, AR5K_RTS_OK); + statistics->fcs_bad += ath5k_hw_reg_read(hal, AR5K_FCS_FAIL); + statistics->beacons += ath5k_hw_reg_read(hal, AR5K_BEACON_CNT); /* Reset profile count registers on 5212*/ if (hal->ah_version == AR5K_AR5212) { - AR5K_REG_WRITE(AR5K_PROFCNT_TX, 0); - AR5K_REG_WRITE(AR5K_PROFCNT_RX, 0); - AR5K_REG_WRITE(AR5K_PROFCNT_RXCLR, 0); - AR5K_REG_WRITE(AR5K_PROFCNT_CYCLE, 0); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_TX); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RX); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RXCLR); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_CYCLE); } } @@ -3133,7 +3140,7 @@ ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) hal->ah_turbo) <= timeout) return false; - AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, + AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; @@ -3146,7 +3153,7 @@ unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), hal->ah_turbo)); } @@ -3161,7 +3168,7 @@ ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) hal->ah_turbo) <= timeout) return false; - AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, + AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; @@ -3174,7 +3181,7 @@ unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), hal->ah_turbo)); } @@ -3210,12 +3217,12 @@ ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) - AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), 0); + ath5k_hw_reg_write(hal, 0, AR5K_KEYTABLE_OFF(entry, i)); /* Set NULL encryption on non-5210*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), - AR5K_KEYTABLE_TYPE_NULL); + ath5k_hw_reg_write(hal, AR5K_KEYTABLE_TYPE_NULL, + AR5K_KEYTABLE_TYPE(entry)); return false; /*????*/ } @@ -3232,7 +3239,7 @@ ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) /* * Check the validation flag at the end of the entry */ - if (AR5K_REG_READ(AR5K_KEYTABLE_MAC1(entry)) & + if (ath5k_hw_reg_read(hal, AR5K_KEYTABLE_MAC1(entry)) & AR5K_KEYTABLE_VALID) return true; @@ -3285,7 +3292,7 @@ ath5k_hw_set_key(struct ath_hw *hal, u16 entry, } for (i = 0; i < ARRAY_SIZE(key_v); i++) - AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), key_v[i]); + ath5k_hw_reg_write(hal, key_v[i], AR5K_KEYTABLE_OFF(entry, i)); return ath5k_hw_set_key_lladdr(hal, entry, mac); } @@ -3311,8 +3318,8 @@ ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID; } - AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id); - AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id); + ath5k_hw_reg_write(hal, low_id, AR5K_KEYTABLE_MAC0(entry)); + ath5k_hw_reg_write(hal, high_id, AR5K_KEYTABLE_MAC1(entry)); return true; } @@ -3466,7 +3473,7 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; struct ath5k_ar5210_ini_mode ar5210_mode[] = - AR5K_AR5210_INI_MODE(hal->ah_aifs + tq->tqi_aifs); + AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs); AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3485,9 +3492,10 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) * Write initial mode register settings */ for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++) - AR5K_REG_WRITE((u32)ar5210_mode[i].mode_register, - hal->ah_turbo == true ? - ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base); + ath5k_hw_reg_write(hal, hal->ah_turbo == true ? + ar5210_mode[i].mode_turbo : + ar5210_mode[i].mode_base, + (u32)ar5210_mode[i].mode_register); } /* @@ -3537,23 +3545,25 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) /*No QCU/DCU [5210]*/ if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_WRITE(AR5K_NODCU_RETRY_LMT, + ath5k_hw_reg_write(hal, (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_NODCU_RETRY_LMT_SLG_RETRY) | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_NODCU_RETRY_LMT_SSH_RETRY) | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) - | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY)); + | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), + AR5K_NODCU_RETRY_LMT); } else { /*QCU/DCU [5211+]*/ - AR5K_REG_WRITE(AR5K_QUEUE_DFS_RETRY_LIMIT(queue), + ath5k_hw_reg_write(hal, AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_DCU_RETRY_LMT_SLG_RETRY) | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_DCU_RETRY_LMT_SSH_RETRY) | AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | - AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY)); + AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), + AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); /*===Rest is also for QCU/DCU only [5211+]===*/ @@ -3561,58 +3571,58 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) * Set initial content window (cw_min/cw_max) * and arbitrated interframe space (aifs)... */ - AR5K_REG_WRITE(AR5K_QUEUE_DFS_LOCAL_IFS(queue), + ath5k_hw_reg_write(hal, AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, - AR5K_DCU_LCL_IFS_AIFS)); + AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue)); /* * Set misc registers */ - AR5K_REG_WRITE(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_DCU_EARLY); + ath5k_hw_reg_write(hal, AR5K_QCU_MISC_DCU_EARLY, + AR5K_QUEUE_MISC(queue)); if (tq->tqi_cbr_period) { - AR5K_REG_WRITE(AR5K_QUEUE_CBRCFG(queue), - AR5K_REG_SM(tq->tqi_cbr_period, - AR5K_QCU_CBRCFG_INTVAL) | + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_cbr_period, + AR5K_QCU_CBRCFG_INTVAL) | AR5K_REG_SM(tq->tqi_cbr_overflow_limit, - AR5K_QCU_CBRCFG_ORN_THRES)); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_CBRCFG_ORN_THRES), + AR5K_QUEUE_CBRCFG(queue)); + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_CBR); if (tq->tqi_cbr_overflow_limit) - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_CBR_THRES_ENABLE); } if (tq->tqi_ready_time) { - AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), - AR5K_REG_SM(tq->tqi_ready_time, - AR5K_QCU_RDYTIMECFG_INTVAL) | - AR5K_QCU_RDYTIMECFG_ENABLE); + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time, + AR5K_QCU_RDYTIMECFG_INTVAL) | + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); } if (tq->tqi_burst_time) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_CHANNEL_TIME(queue), - AR5K_REG_SM(tq->tqi_burst_time, + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time, AR5K_DCU_CHAN_TIME_DUR) | - AR5K_DCU_CHAN_TIME_ENABLE); + AR5K_DCU_CHAN_TIME_ENABLE, + AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_TXE); } } if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), - AR5K_DCU_MISC_POST_FR_BKOFF_DIS); + ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, + AR5K_QUEUE_DFS_MISC(queue)); } if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), - AR5K_DCU_MISC_BACKOFF_FRAG); + ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG, + AR5K_QUEUE_DFS_MISC(queue)); } /* @@ -3620,38 +3630,39 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) */ switch (tq->tqi_type) { case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_DBA_GT | AR5K_QCU_MISC_CBREXP_BCN | AR5K_QCU_MISC_BCN_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << AR5K_DCU_MISC_ARBLOCK_CTL_S) | AR5K_DCU_MISC_POST_FR_BKOFF_DIS | AR5K_DCU_MISC_BCN_ENABLE); - AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), + ath5k_hw_reg_write(hal, ((AR5K_TUNE_BEACON_INTERVAL - (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | - AR5K_QCU_RDYTIMECFG_ENABLE); + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); break; case AR5K_TX_QUEUE_CAB: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_DBA_GT | AR5K_QCU_MISC_CBREXP | AR5K_QCU_MISC_CBREXP_BCN); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << AR5K_DCU_MISC_ARBLOCK_CTL_S)); break; case AR5K_TX_QUEUE_UAPSD: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_CBREXP); break; @@ -3663,13 +3674,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) /* * Enable tx queue in the secondary interrupt mask registers */ - AR5K_REG_WRITE(AR5K_SIMR0, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXOK) | - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXDESC)); - AR5K_REG_WRITE(AR5K_SIMR1, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR1_QCU_TXERR)); - AR5K_REG_WRITE(AR5K_SIMR2, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR0_QCU_TXOK) | + AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); } return true; @@ -3706,10 +3718,10 @@ ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time) return false; if (hal->ah_version == AR5K_AR5210) - AR5K_REG_WRITE(AR5K_SLOT_TIME, - ath5k_hw_htoclock(slot_time, hal->ah_turbo)); + ath5k_hw_reg_write(hal, ath5k_hw_htoclock(slot_time, + hal->ah_turbo), AR5K_SLOT_TIME); else - AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); + ath5k_hw_reg_write(hal, slot_time, AR5K_DCU_GBL_IFS_SLOT); return true; } @@ -3722,10 +3734,10 @@ ath5k_hw_get_slot_time(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) - return (ath5k_hw_clocktoh(AR5K_REG_READ(AR5K_SLOT_TIME) & + return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo)); else - return AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff; + return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff; } @@ -4377,10 +4389,10 @@ ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) /*Reset led status*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_DISABLE_BITS(AR5K_PCICFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); else - AR5K_REG_DISABLE_BITS(AR5K_PCICFG, + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LED); /* @@ -4417,9 +4429,9 @@ ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) /*Write new status to the register*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led); else - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led_5210); + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led_5210); } /* @@ -4432,9 +4444,8 @@ ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) if (gpio > AR5K_NUM_GPIO) return false; - AR5K_REG_WRITE(AR5K_GPIOCR, - (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) - | AR5K_GPIOCR_OUT(gpio)); + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ + AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); return true; } @@ -4449,9 +4460,8 @@ ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) if (gpio > AR5K_NUM_GPIO) return false; - AR5K_REG_WRITE(AR5K_GPIOCR, - (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) - | AR5K_GPIOCR_IN(gpio)); + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ + AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); return true; } @@ -4467,7 +4477,7 @@ ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) return 0xffffffff; /* GPIO input magic */ - return (((AR5K_REG_READ(AR5K_GPIODI) & + return (((ath5k_hw_reg_read(hal, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) & 0x1); } @@ -4484,12 +4494,12 @@ ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) return false; /* GPIO output magic */ - data = AR5K_REG_READ(AR5K_GPIODO); + data = ath5k_hw_reg_read(hal, AR5K_GPIODO); data &= ~(1 << gpio); data |= (val&1) << gpio; - AR5K_REG_WRITE(AR5K_GPIODO, data); + ath5k_hw_reg_write(hal, data, AR5K_GPIODO); return true; } @@ -4510,18 +4520,18 @@ ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, /* * Set the GPIO interrupt */ - data = (AR5K_REG_READ(AR5K_GPIOCR) & + data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) & ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); - AR5K_REG_WRITE(AR5K_GPIOCR, - interrupt_level ? data : (data | AR5K_GPIOCR_INT_SELH)); + ath5k_hw_reg_write(hal, interrupt_level ? data : + (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); hal->ah_imr |= AR5K_IMR_GPIO; /* Enable GPIO interrupts */ - AR5K_REG_ENABLE_BITS(AR5K_PIMR, AR5K_IMR_GPIO); + AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, AR5K_IMR_GPIO); } @@ -4688,8 +4698,8 @@ ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) * Set the channel and wait */ data = ath5k_hw_rf5110_chan2athchan(channel); - AR5K_PHY_WRITE(0x27, data); - AR5K_PHY_WRITE(0x30, 0); + AR5K_PHY_WRITE(hal, 0x27, data); + AR5K_PHY_WRITE(hal, 0x30, 0); udelay(1000); return true; @@ -4762,8 +4772,8 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) | (clock << 1) | (1 << 10) | 1; } - AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); - AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); + AR5K_PHY_WRITE(hal, 0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); + AR5K_PHY_WRITE(hal, 0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); return true; } @@ -4810,8 +4820,8 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; - AR5K_PHY_WRITE(0x27, data & 0xff); - AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); + AR5K_PHY_WRITE(hal, 0x27, data & 0xff); + AR5K_PHY_WRITE(hal, 0x36, (data >> 8) & 0x7f); return true; } @@ -4842,23 +4852,23 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) unsigned int i; #define AGC_DISABLE { \ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGC, \ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, \ AR5K_PHY_AGC_DISABLE); \ udelay(10); \ } #define AGC_ENABLE { \ - AR5K_REG_DISABLE_BITS(AR5K_PHY_AGC, \ + AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, \ AR5K_PHY_AGC_DISABLE); \ } /* * Disable beacons and RX/TX queues, wait */ - AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW_5210, + AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210, AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); - beacon = AR5K_REG_READ(AR5K_BEACON_5210); - AR5K_REG_WRITE(AR5K_BEACON_5210, beacon & ~AR5K_BEACON_ENABLE); + beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210); + ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); udelay(2300); @@ -4871,7 +4881,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Activate PHY and wait */ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); udelay(1000); AGC_ENABLE; @@ -4884,31 +4894,28 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) */ /* Remember normal state */ - phy_sig = AR5K_REG_READ(AR5K_PHY_SIG); - phy_agc = AR5K_REG_READ(AR5K_PHY_AGCCOARSE); - phy_sat = AR5K_REG_READ(AR5K_PHY_ADCSAT); + phy_sig = ath5k_hw_reg_read(hal, AR5K_PHY_SIG); + phy_agc = ath5k_hw_reg_read(hal, AR5K_PHY_AGCCOARSE); + phy_sat = ath5k_hw_reg_read(hal, AR5K_PHY_ADCSAT); /* Update radio registers */ - AR5K_REG_WRITE(AR5K_PHY_SIG, - (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | - AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR)); + ath5k_hw_reg_write(hal, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | + AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); - AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, - (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | + ath5k_hw_reg_write(hal, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | AR5K_PHY_AGCCOARSE_LO)) | AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | - AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO)); + AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); - AR5K_REG_WRITE(AR5K_PHY_ADCSAT, - (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | + ath5k_hw_reg_write(hal, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | AR5K_PHY_ADCSAT_THR)) | AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | - AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR)); + AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); udelay(20); AGC_DISABLE; - AR5K_REG_WRITE(AR5K_PHY_RFSTG, AR5K_PHY_RFSTG_DISABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); AGC_ENABLE; udelay(1000); @@ -4916,7 +4923,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Enable calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -4927,9 +4934,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) } /* Reset to normal state */ - AR5K_REG_WRITE(AR5K_PHY_SIG, phy_sig); - AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, phy_agc); - AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat); + ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG); + ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE); + ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT); if (ret == false) return false; @@ -4937,7 +4944,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Enable noise floor calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -4950,7 +4957,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* Wait until the noise floor is calibrated */ for (i = 20; i > 0; i--) { udelay(1000); - noise_floor = AR5K_REG_READ(AR5K_PHY_NF); + noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) @@ -4970,9 +4977,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Re-enable RX/TX and beacons */ - AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW_5210, + AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW_5210, AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); - AR5K_REG_WRITE(AR5K_BEACON_5210, beacon); + ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210); #undef AGC_ENABLE #undef AGC_DISABLE @@ -4991,14 +4998,14 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) AR5K_TRACE; if (hal->ah_calibration == false || - AR5K_REG_READ(AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) + ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) goto done; hal->ah_calibration = false; - iq_corr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_CORR); - i_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_I); - q_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_Q); + iq_corr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_CORR); + i_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_I); + q_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_Q); i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; q_coffd = q_pwr >> 6; @@ -5009,22 +5016,21 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; /* Commit new IQ value */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); done: /* Start noise floor calibration */ - AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); /* Request RF gain */ if (channel->val & CHANNEL_5GHZ) { - AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE, - AR5K_REG_SM(hal->ah_txpower.txp_max, + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txpower.txp_max, AR5K_PHY_PAPD_PROBE_TXPOWER) | - AR5K_PHY_PAPD_PROBE_TX_NEXT); + AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } @@ -5036,7 +5042,7 @@ ath5k_hw_phy_disable(struct ath_hw *hal) { AR5K_TRACE; /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); return true; } @@ -5046,7 +5052,7 @@ ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant) AR5K_TRACE; /*Just a try M.F.*/ if (hal->ah_version != AR5K_AR5210) - AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant); + ath5k_hw_reg_write(hal, ant, AR5K_DEFAULT_ANTENNA); } unsigned int @@ -5055,7 +5061,7 @@ ath5k_hw_get_def_antenna(struct ath_hw *hal) AR5K_TRACE; /*Just a try M.F.*/ if (hal->ah_version != AR5K_AR5210) - return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + return ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); return false; /*XXX: What do we return for 5210 ?*/ } @@ -5373,7 +5379,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un /* Write RF values */ for (i = 0; i < rf_size; i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]); + ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register); } return true; @@ -5467,7 +5473,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un /* Write RF values */ for (i = 0; i < rf_size; i++) - AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); + ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register); return true; } @@ -5529,8 +5535,8 @@ ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un for (i = 0; i < ARRAY_SIZE(rf); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)rf[i].rf_register, - rf[i].rf_value[freq]); + ath5k_hw_reg_write(hal, rf[i].rf_value[freq], + (u32)rf[i].rf_register); } hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; @@ -5559,8 +5565,8 @@ ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u32)ath5k_rfg[i].rfg_register, - ath5k_rfg[i].rfg_value[phy][freq]); + ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[phy][freq], + (u32)ath5k_rfg[i].rfg_register); } return true; @@ -5580,7 +5586,7 @@ ath5k_hw_get_rf_gain(struct ath_hw *hal) if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) goto done; - data = AR5K_REG_READ(AR5K_PHY_PAPD_PROBE); + data = ath5k_hw_reg_read(hal, AR5K_PHY_PAPD_PROBE); if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; @@ -5675,36 +5681,34 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned * Write TX power values */ for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { - AR5K_REG_WRITE(AR5K_PHY_PCDAC_TXPOWER(i), - ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) - | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ) - ); + ath5k_hw_reg_write(hal, + ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) + | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ), + AR5K_PHY_PCDAC_TXPOWER(i)); } - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE1, - AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16) - | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(3, 24) | + AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | + AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE2, - AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16) - | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(7, 24) | + AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | + AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE3, - AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16) - | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(10, 24) | + AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | + AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE4, - AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) - | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); + ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(14, 24) | + AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | + AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); if (hal->ah_txpower.txp_tpc == true) { - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX, - AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | - AR5K_TUNE_MAX_TXPOWER); + ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); } else { - AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX, - AR5K_PHY_TXPOWER_RATE_MAX | - AR5K_TUNE_MAX_TXPOWER); + ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); } return true; @@ -5733,7 +5737,7 @@ ath5k_hw_dump_state(struct ath_hw *hal) { #ifdef AR5K_DEBUG #define AR5K_PRINT_REGISTER(_x) \ - AR5K_PRINTF("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_##_x)); + AR5K_PRINTF("(%s: %08x) ", #_x, ath5k_hw_reg_read(hal, AR5K_##_x)); AR5K_PRINT("MAC registers:\n"); AR5K_PRINT_REGISTER(CR); @@ -5916,7 +5920,7 @@ ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; @@ -5930,7 +5934,7 @@ ath5k_hw_disable_pspoll(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, + AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; diff --git a/openhal/ath5k_hw.h b/openhal/ath5k_hw.h index 417812f..92ff4cf 100644 --- a/openhal/ath5k_hw.h +++ b/openhal/ath5k_hw.h @@ -206,9 +206,9 @@ struct ath5k_eeprom_info { #define AR5K_INIT_CFG 0x00000000 #endif -#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg) +/*#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg) -#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg) +#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg)*/ #define AR5K_REG_SM(_val, _flags) \ (((_val) << _flags##_S) & (_flags)) @@ -221,32 +221,32 @@ struct ath5k_eeprom_info { * retrieve the values which we do not want to clear (lets call this * old_data) and then set the register with this and our new_value: * ( old_data | new_value) */ -#define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ - AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ - (((_val) << _flags##_S) & (_flags))) +#define AR5K_REG_WRITE_BITS(hal, _reg, _flags, _val) \ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & ~(_flags)) | \ + (((_val) << _flags##_S) & (_flags)), _reg) -#define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \ - AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags)) +#define AR5K_REG_MASKED_BITS(hal, _reg, _flags, _mask) \ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & \ + (_mask)) | (_flags), _reg) -#define AR5K_REG_ENABLE_BITS(_reg, _flags) \ - AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) +#define AR5K_REG_ENABLE_BITS(hal, _reg, _flags) \ + ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) | (_flags), _reg) -#define AR5K_REG_DISABLE_BITS(_reg, _flags) \ - AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) +#define AR5K_REG_DISABLE_BITS(hal, _reg, _flags) \ + ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) & ~(_flags), _reg) -#define AR5K_PHY_WRITE(_reg, _val) \ - AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val) +#define AR5K_PHY_WRITE(hal, _reg, _val) \ + ath5k_hw_reg_write(hal, _val, (hal)->ah_phy + ((_reg) << 2)) -#define AR5K_PHY_READ(_reg) \ - AR5K_REG_READ(hal->ah_phy + ((_reg) << 2)) +#define AR5K_PHY_READ(hal, _reg) \ + ath5k_hw_reg_read(hal, (hal)->ah_phy + ((_reg) << 2)) #define AR5K_REG_WAIT(_i) \ if (_i % 64) \ udelay(1); #define AR5K_EEPROM_READ(_o, _v) { \ - if ((ret = ath5k_hw_eeprom_read(hal, (_o), \ - &(_v))) != 0) \ + if ((ret = ath5k_hw_eeprom_read(hal, (_o), &(_v))) != 0) \ return (ret); \ } @@ -254,11 +254,11 @@ struct ath5k_eeprom_info { AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ /* Read status of selected queue */ -#define AR5K_REG_READ_Q(_reg, _queue) \ - (AR5K_REG_READ(_reg) & (1 << _queue)) \ +#define AR5K_REG_READ_Q(hal, _reg, _queue) \ + (ath5k_hw_reg_read(hal, _reg) & (1 << _queue)) \ -#define AR5K_REG_WRITE_Q(_reg, _queue) \ - AR5K_REG_WRITE(_reg, (1 << _queue)) +#define AR5K_REG_WRITE_Q(hal, _reg, _queue) \ + ath5k_hw_reg_write(hal, (1 << _queue), _reg) #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ _reg |= 1 << _queue; \ @@ -1337,7 +1337,7 @@ struct ath5k_ar5210_ini_mode{ u32 mode_base, mode_turbo; }; -#define AR5K_AR5210_INI_MODE(_aifs) { \ +#define AR5K_AR5210_INI_MODE(hal, _aifs) { \ { AR5K_SLOT_TIME, \ AR5K_INIT_SLOT_TIME, \ AR5K_INIT_SLOT_TIME_TURBO }, \ @@ -1356,8 +1356,8 @@ struct ath5k_ar5210_ini_mode{ AR5K_INIT_PROTO_TIME_CNTRL, \ AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ { AR5K_PHY(17), \ - (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x1C, \ - (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ + (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x1C, \ + (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ { AR5K_PHY_FRAME_CTL_5210, \ AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ AR5K_PHY_FRAME_CTL_TXURN_ERR | \ commit 4e0919538e6d196584ec425483f06374f2c9f1db Author: Jiri Slaby Date: Sat Jun 23 15:01:49 2007 +0200 use mdelay diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 9d0e883..2e88557 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -4700,7 +4700,7 @@ ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) data = ath5k_hw_rf5110_chan2athchan(channel); AR5K_PHY_WRITE(hal, 0x27, data); AR5K_PHY_WRITE(hal, 0x30, 0); - udelay(1000); + mdelay(1); return true; } @@ -4882,7 +4882,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) * Activate PHY and wait */ ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); - udelay(1000); + mdelay(1); AGC_ENABLE; @@ -4918,7 +4918,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); AGC_ENABLE; - udelay(1000); + mdelay(1); /* * Enable calibration and wait until completion @@ -4956,7 +4956,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* Wait until the noise floor is calibrated */ for (i = 20; i > 0; i--) { - udelay(1000); + mdelay(1); noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & commit 5559d6c12b928fd46d444911a4695989f0419dac Author: Jiri Slaby Date: Sat Jun 23 15:06:57 2007 +0200 remove ath_rate_setup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 3c789bf..1246b12 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -428,54 +428,6 @@ err: return ret; } #if 0 -static int ath_rate_setup(struct ieee80211_hw *dev, u_int mode) -{ - struct ath_softc *sc = dev->priv; - struct ath_hw *ah = sc->ah; - const struct ath5k_rate_table *rt; -// struct ieee80211_rateset *rs; -// int i, maxrates; - - switch (mode) { - case MODE_IEEE80211A: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A); - break; - case MODE_IEEE80211B: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11B); - break; - case MODE_IEEE80211G: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_11G); - break; - case MODE_ATHEROS_TURBO: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_TURBO); - break; - case MODE_ATHEROS_TURBOG: - sc->sc_rates[mode] = ath5k_hw_get_rate_table(ah, AR5K_MODE_108G); - break; - default: - DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", - __func__, mode); - return 0; - } - rt = sc->sc_rates[mode]; - if (rt == NULL) - return 0; -#ifdef BLE - if (rt->rate_count > IEEE80211_RATE_MAXSIZE) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: rate table too small (%u > %u)\n", - __func__, rt->rate_count, IEEE80211_RATE_MAXSIZE); - maxrates = IEEE80211_RATE_MAXSIZE; - } else - maxrates = rt->rate_count; - rs = &ic->ic_sup_rates[mode]; - for (i = 0; i < maxrates; i++) - rs->rs_rates[i] = rt->rates[i].dot11_rate; - rs->rs_nrates = maxrates; -#endif - return 1; -} - static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) { /* NB: on/off times from the Atheros NDIS driver, w/ permission */ @@ -679,14 +631,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto err; } #ifdef BLE - /* - * Setup rate tables for all potential media types. - */ - ath_rate_setup(hw, MODE_IEEE80211A); - ath_rate_setup(hw, MODE_IEEE80211B); - ath_rate_setup(hw, MODE_IEEE80211G); - ath_rate_setup(hw, MODE_ATHEROS_TURBO); - ath_rate_setup(hw, MODE_ATHEROS_TURBOG); /* NB: setup here so ath_rate_update is happy */ ath_setcurmode(sc, MODE_IEEE80211A); commit e5a81de8e556c104aacffb9ce3d15241a2b55ca9 Author: Jiri Slaby Date: Mon Jun 25 00:09:07 2007 +0200 regdomain cleanup diff --git a/openhal/ieee80211_regdomain.c b/openhal/ieee80211_regdomain.c index f600604..f5da7cf 100644 --- a/openhal/ieee80211_regdomain.c +++ b/openhal/ieee80211_regdomain.c @@ -16,10 +16,10 @@ #include "ieee80211_regdomain.h" static const struct ieee80211_regdomainmap { - u16 rm_domain; - u32 rm_domain_5ghz; - u32 rm_domain_2ghz; -} ieee80211_r_map[] = { + enum ieee80211_regdomain dmn; + enum ieee80211_regdomain dmn5; + enum ieee80211_regdomain dmn2; +} r_map[] = { { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, @@ -71,21 +71,22 @@ static const struct ieee80211_regdomainmap { { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, }; -u32 ieee80211_regdomain2flag(u16 regdomain, u16 mhz) +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, + u16 mhz) { unsigned int i; - for (i = 0; i < ARRAY_SIZE(ieee80211_r_map); i++) { - if (ieee80211_r_map[i].rm_domain == regdomain) { + for (i = 0; i < ARRAY_SIZE(r_map); i++) { + if (r_map[i].dmn == dmn) { if (mhz >= 2000 && mhz <= 3000) - return (u32)ieee80211_r_map[i].rm_domain_2ghz; + return r_map[i].dmn2; if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && mhz <= IEEE80211_CHANNELS_5GHZ_MAX) - return (u32)ieee80211_r_map[i].rm_domain_5ghz; + return r_map[i].dmn5; } } - return (u32)DMN_DEBUG; + return DMN_DEBUG; } u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 1f1ed97..14dc84d 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -219,9 +219,9 @@ enum ieee80211_countrycode { #define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ struct ieee80211_regchannel { - u16 rc_channel; - u32 rc_domain; - u32 rc_mode; + u16 chan; + enum ieee80211_regdomain domain; + u32 mode; }; #define IEEE80211_CHANNELS_2GHZ { \ @@ -486,7 +486,7 @@ struct ieee80211_regchannel { { 5240, DMN_WORLD, CHANNEL_OFDM }, \ } -u32 ieee80211_regdomain2flag(u16, u16); +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); commit d6ad0bbbece16d10bc0adef0eeb04d6eff4b4ed5 Author: Jiri Slaby Date: Mon Jun 25 00:09:40 2007 +0200 regdomains are clean as heaven from now :) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 1246b12..337c724 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -233,15 +233,15 @@ static inline short ath_ieee2mhz(short chan) return 2212 + chan * 20; } -static inline unsigned int ath_copy_rates(struct ieee80211_rate *rates, - const struct ath5k_rate_table *rt) +static unsigned int ath_copy_rates(struct ieee80211_rate *rates, + const struct ath5k_rate_table *rt, unsigned int max) { unsigned int i; if (rt == NULL) return 0; - for (i = 0; i < rt->rate_count; i++, rates++) { + for (i = 0; i < rt->rate_count && max > 0; i++, rates++, max--) { rates->rate = rt->rates[i].rate_kbps / 100; rates->val = rt->rates[i].rate_code; rates->flags = rt->rates[i].modulation; @@ -250,6 +250,80 @@ static inline unsigned int ath_copy_rates(struct ieee80211_rate *rates, return i; } +static unsigned int ath_copy_channels(struct ath_hw *ah, + struct ieee80211_channel *channels, unsigned int mode, + unsigned int max) +{ + static const struct { unsigned int mode, mask, chan; } map[] = { + [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A }, + [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T }, + [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B }, + [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G }, + [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG }, + }; + static const struct ieee80211_regchannel chans_2ghz[] = + IEEE80211_CHANNELS_2GHZ; + static const struct ieee80211_regchannel chans_5ghz[] = + IEEE80211_CHANNELS_5GHZ; + const struct ieee80211_regchannel *chans; + enum ieee80211_regdomain dmn; + unsigned int i, count, size, chfreq, all, f; + + if (!test_bit(mode, ah->ah_modes)) + return 0; + + all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1; + + switch (mode) { + case MODE_IEEE80211A: + case MODE_ATHEROS_TURBO: + /* 1..220, but 2GHz frequencies are filtered by check_channel */ + size = all ? 220 : ARRAY_SIZE(chans_5ghz); + chans = chans_5ghz; + dmn = ieee80211_regdomain2flag(ah->ah_regdomain, + IEEE80211_CHANNELS_5GHZ_MIN); + chfreq = CHANNEL_5GHZ; + break; + case MODE_IEEE80211B: + case MODE_IEEE80211G: + case MODE_ATHEROS_TURBOG: + size = all ? 26 : ARRAY_SIZE(chans_2ghz); + chans = chans_2ghz; + dmn = ieee80211_regdomain2flag(ah->ah_regdomain, + IEEE80211_CHANNELS_2GHZ_MIN); + chfreq = CHANNEL_2GHZ; + break; + default: + printk(KERN_WARNING "bad mode, not copying channels\n"); + return 0; + } + + for (i = 0, count = 0; i < size && max > 0; i++) { + f = all ? ath_ieee2mhz(i + 1) : chans[i].chan; + /* Check if channel is supported by the chipset */ + if (ath5k_check_channel(ah, f, chfreq) == false) + continue; + + /* Match regulation domain */ + if (!all && !(IEEE80211_DMN(chans[i].domain) & + IEEE80211_DMN(dmn))) + continue; + + if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode) + continue; + + /* Write channel and increment counter */ +// channels->chan = i; + channels->freq = f; + channels->val = map[mode].chan; + channels++; + count++; + max--; + } + + return count; +} + #if ATH_DEBUG_MODES static void ath_dump_modes(struct ieee80211_hw_mode *modes) { @@ -285,8 +359,7 @@ static int ath_getchannels(struct ieee80211_hw *hw) struct ath_softc *sc = hw->priv; struct ath_hw *ah = sc->ah; struct ieee80211_hw_mode *modes = sc->modes; - u32 domain_current = ah->ah_regdomain; - unsigned int i, c, domain_5ghz, domain_2ghz; + unsigned int i, max; int ret; enum { A = 0, @@ -296,131 +369,52 @@ static int ath_getchannels(struct ieee80211_hw *hw) TG = 4, }; + BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 5); + ah->ah_country_code = countrycode; modes[A].mode = MODE_IEEE80211A; - modes[A].channels = sc->channels; modes[B].mode = MODE_IEEE80211B; - modes[B].channels = sc->channels; modes[G].mode = MODE_IEEE80211G; - modes[G].channels = sc->channels; + max = ARRAY_SIZE(sc->rates); modes[A].rates = sc->rates; - modes[A].num_rates = ath_copy_rates(modes[A].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211A)); + max -= modes[A].num_rates = ath_copy_rates(modes[A].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211A), max); modes[B].rates = &modes[A].rates[modes[A].num_rates]; - modes[B].num_rates = ath_copy_rates(modes[B].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211B)); + max -= modes[B].num_rates = ath_copy_rates(modes[B].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211B), max); modes[G].rates = &modes[B].rates[modes[B].num_rates]; - modes[G].num_rates = ath_copy_rates(modes[G].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211G)); - - /* - * In debugging mode, enable all channels supported by the chipset - */ - if (domain_current == DMN_DEFAULT || CHAN_DEBUG == 1) { - short freq; - - /* channel 1 -2412MHz .. channel 26 (non-ieee) -2732MHz */ - for (i = 1, c = 0; i <= 26 && c < ATH_CHAN_MAX; i++) { - freq = ath_ieee2mhz(i); - if (ath5k_check_channel(ah, freq,CHANNEL_2GHZ) == false) - continue; - sc->channels[c].chan = i; - sc->channels[c].freq = freq; - sc->channels[c].val = CHANNEL_B | CHANNEL_G; - c++; - } - modes[B].num_channels = c; - modes[G].num_channels = c; - - for (i = 27; i <= 220 && c < ATH_CHAN_MAX; i++) { - freq = ath_ieee2mhz(i); - if (ath5k_check_channel(ah, freq,CHANNEL_5GHZ) == false) - continue; - sc->channels[c].chan = i; - sc->channels[c].freq = freq; - sc->channels[c].val = CHANNEL_A | CHANNEL_T| CHANNEL_XR; - c++; - } - modes[A].channels += modes[B].num_channels; /* skip B/G chans */ - modes[A].num_channels = c - modes[B].num_channels; + max -= modes[G].num_rates = ath_copy_rates(modes[G].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211G), max); - goto end; - } + if (!max) + printk(KERN_WARNING "yet another rates found, but there is not " + "sufficient space to store them\n"); - domain_5ghz = ieee80211_regdomain2flag(domain_current, - IEEE80211_CHANNELS_5GHZ_MIN); - domain_2ghz = ieee80211_regdomain2flag(domain_current, - IEEE80211_CHANNELS_2GHZ_MIN); -#if 0 - /* - * Create channel list based on chipset capabilities, regulation domain - * and mode. 5GHz... - */ - for (i = 0; hal->ah_capabilities.cap_range.range_5ghz_max > 0 && - i < ARRAY_SIZE(ath5k_5ghz_channels) && - c < max_channels; i++) { - /* Check if channel is supported by the chipset */ - if (ath5k_check_channel(hal, ath5k_5ghz_channels[i].rc_channel, - CHANNEL_5GHZ) == false) - continue; - - /* Match regulation domain */ - if ((IEEE80211_DMN(ath5k_5ghz_channels[i].rc_domain) & - IEEE80211_DMN(domain_5ghz)) == 0) - continue; - - /* Match modes */ - if (ath5k_5ghz_channels[i].rc_mode & CHANNEL_TURBO) - all_channels[c].channel_flags = CHANNEL_T; - else if (ath5k_5ghz_channels[i].rc_mode & CHANNEL_OFDM) - all_channels[c].channel_flags = CHANNEL_A; - else - continue; - - /* Write channel and increment counter */ - all_channels[c++].freq = ath5k_5ghz_channels[i].rc_channel; - } - - /* - * ...and 2GHz. - */ - for (i = 0; hal->ah_capabilities.cap_range.range_2ghz_max > 0 && - i < ARRAY_SIZE(ath5k_2ghz_channels) && - c < max_channels; i++) { - /* Check if channel is supported by the chipset */ - if (ath5k_check_channel(hal, ath5k_2ghz_channels[i].rc_channel, - CHANNEL_2GHZ) == false) - continue; - - /* Match regulation domain */ - if ((IEEE80211_DMN(ath5k_2ghz_channels[i].rc_domain) & - IEEE80211_DMN(domain_2ghz)) == 0) - continue; - - /* Match modes */ - if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11B) && - (ath5k_2ghz_channels[i].rc_mode & CHANNEL_CCK)) - all_channels[c].channel_flags = CHANNEL_B; - - if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11G) && - (ath5k_2ghz_channels[i].rc_mode &CHANNEL_OFDM)){ - all_channels[c].channel_flags |= CHANNEL_G; -/* if (ath5k_2ghz_channels[i].rc_mode & CHANNEL_TURBO) - all_channels[c].channel_flags |= CHANNEL_TG;*/ + max = ARRAY_SIZE(sc->channels); + modes[A].channels = sc->channels; + max -= modes[A].num_channels = ath_copy_channels(ah, modes[A].channels, + MODE_IEEE80211A, max); + modes[B].channels = &modes[A].channels[modes[A].num_channels]; + max -= modes[B].num_channels = ath_copy_channels(ah, modes[B].channels, + MODE_IEEE80211B, max); + modes[G].channels = &modes[B].channels[modes[B].num_channels]; + max -= modes[G].num_channels = ath_copy_channels(ah, modes[G].channels, + MODE_IEEE80211G, max); + + if (!max) + printk(KERN_WARNING "yet another modes found, but there is not " + "sufficient space to store them\n"); + + for (i = 0; i < ARRAY_SIZE(sc->modes); i++) + if (modes[i].num_channels) { + ret = ieee80211_register_hwmode(hw, &modes[i]); + if (ret) { + printk(KERN_ERR "can't register hwmode %u\n",i); + goto err; + } } - - /* Write channel and increment counter */ - all_channels[c++].freq = ath5k_2ghz_channels[i].rc_channel; - } -#endif -end: - ret = ieee80211_register_hwmode(hw, modes); - if (ret) { - printk(KERN_ERR "can't register hwmodes\n"); - goto err; - } ath_dump_modes(modes); return 0; diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 7260f79..6e84246 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -169,7 +169,11 @@ struct ath_txq { (_tq)->axq_depth--; \ } while (0) -#define ATH_CHAN_MAX 255 /* XXX what's the max? */ +#if CHAN_DEBUG +#define ATH_CHAN_MAX (26+26+26+200+200) +#else +#define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */ +#endif struct ath_softc { void __iomem *iobase; /* address of the device */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 2e88557..660c295 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -70,14 +70,6 @@ static int ath5k_eeprom_init(struct ath_hw *); static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *); /* - * Supported channels - */ -static const struct -ieee80211_regchannel ath5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; -static const struct -ieee80211_regchannel ath5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; - -/* * Initial register dumps */ static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI; commit 40a937fb2ca1d864263d659bcb87817ef0a976e9 Author: Jiri Slaby Date: Mon Jun 25 10:17:56 2007 +0200 fill also channel (this means rewrite regdomain structure to contain channels instead of freq, awk rulez) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 337c724..c09c0cb 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -267,7 +267,7 @@ static unsigned int ath_copy_channels(struct ath_hw *ah, IEEE80211_CHANNELS_5GHZ; const struct ieee80211_regchannel *chans; enum ieee80211_regdomain dmn; - unsigned int i, count, size, chfreq, all, f; + unsigned int i, count, size, chfreq, all, f, ch; if (!test_bit(mode, ah->ah_modes)) return 0; @@ -299,7 +299,8 @@ static unsigned int ath_copy_channels(struct ath_hw *ah, } for (i = 0, count = 0; i < size && max > 0; i++) { - f = all ? ath_ieee2mhz(i + 1) : chans[i].chan; + ch = all ? i + 1 : chans[i].chan; + f = ath_ieee2mhz(ch); /* Check if channel is supported by the chipset */ if (ath5k_check_channel(ah, f, chfreq) == false) continue; @@ -313,7 +314,7 @@ static unsigned int ath_copy_channels(struct ath_hw *ah, continue; /* Write channel and increment counter */ -// channels->chan = i; + channels->chan = ch; channels->freq = f; channels->val = map[mode].chan; channels++; diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h index 14dc84d..b5f67f3 100644 --- a/openhal/ieee80211_regdomain.h +++ b/openhal/ieee80211_regdomain.h @@ -217,6 +217,8 @@ enum ieee80211_countrycode { #define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ #define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ +#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ +#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ struct ieee80211_regchannel { u16 chan; @@ -225,265 +227,262 @@ struct ieee80211_regchannel { }; #define IEEE80211_CHANNELS_2GHZ { \ - { 2412, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2417, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2422, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2427, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2432, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2437, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2442, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2447, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2452, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2457, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2462, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2467, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2472, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2432, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2437, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 2442, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2412, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2417, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2422, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2427, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2432, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2437, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 2442, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2447, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2452, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2457, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2462, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2467, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2472, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2412, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2417, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2422, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2427, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2432, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2437, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 2442, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2447, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2452, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2457, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2462, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2412, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2417, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2422, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2427, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2432, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2437, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2442, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2447, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2452, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2457, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2462, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2467, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2472, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2484, DMN_MKKA, CHANNEL_CCK }, \ +/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \ \ - { 2412, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2417, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2422, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2427, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2432, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2437, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 2442, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2447, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2452, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2457, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2462, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2467, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - { 2472, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ } -#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ -#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ - #define IEEE80211_CHANNELS_5GHZ { \ - { 5745, DMN_APL1, CHANNEL_OFDM }, \ - { 5765, DMN_APL1, CHANNEL_OFDM }, \ - { 5785, DMN_APL1, CHANNEL_OFDM }, \ - { 5805, DMN_APL1, CHANNEL_OFDM }, \ - { 5825, DMN_APL1, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \ \ - { 5745, DMN_APL2, CHANNEL_OFDM }, \ - { 5765, DMN_APL2, CHANNEL_OFDM }, \ - { 5785, DMN_APL2, CHANNEL_OFDM }, \ - { 5805, DMN_APL2, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \ \ - { 5280, DMN_APL3, CHANNEL_OFDM }, \ - { 5300, DMN_APL3, CHANNEL_OFDM }, \ - { 5320, DMN_APL3, CHANNEL_OFDM }, \ - { 5745, DMN_APL3, CHANNEL_OFDM }, \ - { 5765, DMN_APL3, CHANNEL_OFDM }, \ - { 5785, DMN_APL3, CHANNEL_OFDM }, \ - { 5805, DMN_APL3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \ \ - { 5180, DMN_APL4, CHANNEL_OFDM }, \ - { 5200, DMN_APL4, CHANNEL_OFDM }, \ - { 5220, DMN_APL4, CHANNEL_OFDM }, \ - { 5240, DMN_APL4, CHANNEL_OFDM }, \ - { 5745, DMN_APL4, CHANNEL_OFDM }, \ - { 5765, DMN_APL4, CHANNEL_OFDM }, \ - { 5785, DMN_APL4, CHANNEL_OFDM }, \ - { 5805, DMN_APL4, CHANNEL_OFDM }, \ - { 5825, DMN_APL4, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \ \ - { 5745, DMN_APL5, CHANNEL_OFDM }, \ - { 5765, DMN_APL5, CHANNEL_OFDM }, \ - { 5785, DMN_APL5, CHANNEL_OFDM }, \ - { 5805, DMN_APL5, CHANNEL_OFDM }, \ - { 5825, DMN_APL5, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \ \ - { 5180, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5200, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5220, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5240, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5260, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5280, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5300, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5320, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5500, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5520, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5540, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5560, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5580, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5600, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5620, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5640, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5660, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5680, DMN_ETSI1, CHANNEL_OFDM }, \ - { 5700, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \ \ - { 5180, DMN_ETSI2, CHANNEL_OFDM }, \ - { 5200, DMN_ETSI2, CHANNEL_OFDM }, \ - { 5220, DMN_ETSI2, CHANNEL_OFDM }, \ - { 5240, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \ \ - { 5180, DMN_ETSI3, CHANNEL_OFDM }, \ - { 5200, DMN_ETSI3, CHANNEL_OFDM }, \ - { 5220, DMN_ETSI3, CHANNEL_OFDM }, \ - { 5240, DMN_ETSI3, CHANNEL_OFDM }, \ - { 5260, DMN_ETSI3, CHANNEL_OFDM }, \ - { 5280, DMN_ETSI3, CHANNEL_OFDM }, \ - { 5300, DMN_ETSI3, CHANNEL_OFDM }, \ - { 5320, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \ \ - { 5180, DMN_ETSI4, CHANNEL_OFDM }, \ - { 5200, DMN_ETSI4, CHANNEL_OFDM }, \ - { 5220, DMN_ETSI4, CHANNEL_OFDM }, \ - { 5240, DMN_ETSI4, CHANNEL_OFDM }, \ - { 5260, DMN_ETSI4, CHANNEL_OFDM }, \ - { 5280, DMN_ETSI4, CHANNEL_OFDM }, \ - { 5300, DMN_ETSI4, CHANNEL_OFDM }, \ - { 5320, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \ \ - { 5180, DMN_ETSI5, CHANNEL_OFDM }, \ - { 5200, DMN_ETSI5, CHANNEL_OFDM }, \ - { 5220, DMN_ETSI5, CHANNEL_OFDM }, \ - { 5240, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \ \ - { 5180, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5200, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5220, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5240, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5260, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5280, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5500, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5520, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5540, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5560, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5580, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5600, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5620, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5640, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5660, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5680, DMN_ETSI6, CHANNEL_OFDM }, \ - { 5700, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \ \ - { 5180, DMN_FCC1, CHANNEL_OFDM }, \ - { 5200, DMN_FCC1, CHANNEL_OFDM }, \ - { 5210, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5220, DMN_FCC1, CHANNEL_OFDM }, \ - { 5240, DMN_FCC1, CHANNEL_OFDM }, \ - { 5250, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5260, DMN_FCC1, CHANNEL_OFDM }, \ - { 5280, DMN_FCC1, CHANNEL_OFDM }, \ - { 5290, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5300, DMN_FCC1, CHANNEL_OFDM }, \ - { 5320, DMN_FCC1, CHANNEL_OFDM }, \ - { 5745, DMN_FCC1, CHANNEL_OFDM }, \ - { 5760, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5765, DMN_FCC1, CHANNEL_OFDM }, \ - { 5785, DMN_FCC1, CHANNEL_OFDM }, \ - { 5800, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5805, DMN_FCC1, CHANNEL_OFDM }, \ - { 5825, DMN_FCC1, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \ \ - { 5180, DMN_FCC2, CHANNEL_OFDM }, \ - { 5200, DMN_FCC2, CHANNEL_OFDM }, \ - { 5220, DMN_FCC2, CHANNEL_OFDM }, \ - { 5240, DMN_FCC2, CHANNEL_OFDM }, \ - { 5260, DMN_FCC2, CHANNEL_OFDM }, \ - { 5280, DMN_FCC2, CHANNEL_OFDM }, \ - { 5300, DMN_FCC2, CHANNEL_OFDM }, \ - { 5320, DMN_FCC2, CHANNEL_OFDM }, \ - { 5745, DMN_FCC2, CHANNEL_OFDM }, \ - { 5765, DMN_FCC2, CHANNEL_OFDM }, \ - { 5785, DMN_FCC2, CHANNEL_OFDM }, \ - { 5805, DMN_FCC2, CHANNEL_OFDM }, \ - { 5825, DMN_FCC2, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \ \ - { 5180, DMN_FCC3, CHANNEL_OFDM }, \ - { 5200, DMN_FCC3, CHANNEL_OFDM }, \ - { 5210, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5220, DMN_FCC3, CHANNEL_OFDM }, \ - { 5240, DMN_FCC3, CHANNEL_OFDM }, \ - { 5250, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5260, DMN_FCC3, CHANNEL_OFDM }, \ - { 5280, DMN_FCC3, CHANNEL_OFDM }, \ - { 5290, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5300, DMN_FCC3, CHANNEL_OFDM }, \ - { 5320, DMN_FCC3, CHANNEL_OFDM }, \ - { 5500, DMN_FCC3, CHANNEL_OFDM }, \ - { 5520, DMN_FCC3, CHANNEL_OFDM }, \ - { 5540, DMN_FCC3, CHANNEL_OFDM }, \ - { 5560, DMN_FCC3, CHANNEL_OFDM }, \ - { 5580, DMN_FCC3, CHANNEL_OFDM }, \ - { 5600, DMN_FCC3, CHANNEL_OFDM }, \ - { 5620, DMN_FCC3, CHANNEL_OFDM }, \ - { 5640, DMN_FCC3, CHANNEL_OFDM }, \ - { 5660, DMN_FCC3, CHANNEL_OFDM }, \ - { 5680, DMN_FCC3, CHANNEL_OFDM }, \ - { 5700, DMN_FCC3, CHANNEL_OFDM }, \ - { 5745, DMN_FCC3, CHANNEL_OFDM }, \ - { 5760, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5765, DMN_FCC3, CHANNEL_OFDM }, \ - { 5785, DMN_FCC3, CHANNEL_OFDM }, \ - { 5800, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ - { 5805, DMN_FCC3, CHANNEL_OFDM }, \ - { 5825, DMN_FCC3, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \ \ - { 5170, DMN_MKK1, CHANNEL_OFDM }, \ - { 5190, DMN_MKK1, CHANNEL_OFDM }, \ - { 5210, DMN_MKK1, CHANNEL_OFDM }, \ - { 5230, DMN_MKK1, CHANNEL_OFDM }, \ +/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \ \ - { 5040, DMN_MKK2, CHANNEL_OFDM }, \ - { 5060, DMN_MKK2, CHANNEL_OFDM }, \ - { 5080, DMN_MKK2, CHANNEL_OFDM }, \ - { 5170, DMN_MKK2, CHANNEL_OFDM }, \ - { 5190, DMN_MKK2, CHANNEL_OFDM }, \ - { 5210, DMN_MKK2, CHANNEL_OFDM }, \ - { 5230, DMN_MKK2, CHANNEL_OFDM }, \ +/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \ +/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \ +/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \ +/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \ \ - { 5180, DMN_WORLD, CHANNEL_OFDM }, \ - { 5200, DMN_WORLD, CHANNEL_OFDM }, \ - { 5220, DMN_WORLD, CHANNEL_OFDM }, \ - { 5240, DMN_WORLD, CHANNEL_OFDM }, \ +/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ } enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); commit 3dd1938aedb4be5a83572038a17bcdc4c1dce83f Author: Jiri Slaby Date: Mon Jun 25 11:01:57 2007 +0200 set_curmode diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c09c0cb..6435a29 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -363,11 +363,11 @@ static int ath_getchannels(struct ieee80211_hw *hw) unsigned int i, max; int ret; enum { - A = 0, - B = 1, - G = 2, - T = 3, - TG = 4, + A = MODE_IEEE80211A, + B = MODE_IEEE80211B, + G = MODE_IEEE80211G, + T = MODE_ATHEROS_TURBO, + TG = MODE_ATHEROS_TURBOG, }; BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 5); @@ -422,15 +422,14 @@ static int ath_getchannels(struct ieee80211_hw *hw) err: return ret; } -#if 0 + static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) { - /* NB: on/off times from the Atheros NDIS driver, w/ permission */ -#ifdef BLE + /* from Atheros NDIS driver, w/ permission */ static const struct { - u_int rate; /* tx/rx 802.11 rate */ - u_int16_t timeOn; /* LED on time (ms) */ - u_int16_t timeOff; /* LED off time (ms) */ + u16 rate; /* tx/rx 802.11 rate */ + u16 timeOn; /* LED on time (ms) */ + u16 timeOff; /* LED off time (ms) */ } blinkrates[] = { { 108, 40, 10 }, { 96, 44, 11 }, @@ -445,56 +444,42 @@ static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) { 6, 240, 58 }, { 4, 267, 66 }, { 2, 400, 100 }, - { 0, 500, 130 }, + { 0, 500, 130 } }; -#endif - const struct ath5k_rate_table *rt; -// int i, j; - memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); - rt = sc->sc_rates[mode]; + const struct ath5k_rate_table* rt=ath5k_hw_get_rate_table(sc->ah, mode); + unsigned int i, j; + KASSERT(rt != NULL, "no h/w rate set for phy mode %u", mode); -#ifdef BLE - for (i = 0; i < rt->rate_count; i++) - sc->sc_rixmap[rt->rates[i].dot11_rate & IEEE80211_RATE_VAL] = i; - memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); + + memset(sc->hwmap, 0, sizeof(sc->hwmap)); for (i = 0; i < 32; i++) { - u_int8_t ix = rt->rate_code_to_index[i]; + u8 ix = rt->rate_code_to_index[i]; if (ix == 0xff) { - sc->sc_hwmap[i].ledon = (500 * HZ) / 1000; - sc->sc_hwmap[i].ledoff = (130 * HZ) / 1000; + sc->hwmap[i].ledon = msecs_to_jiffies(500); + sc->hwmap[i].ledoff = msecs_to_jiffies(130); continue; } - sc->sc_hwmap[i].ieeerate = - rt->rates[ix].dot11_rate & IEEE80211_RATE_VAL; - sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; - if (SHPREAMBLE_FLAG(ix) || - rt->rates[ix].modulation == MODULATION_OFDM) - sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; - /* NB: receive frames include FCS */ - sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | - IEEE80211_RADIOTAP_F_FCS; + sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; + if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == + MODULATION_OFDM) + sc->hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; + /* receive frames include FCS */ + sc->hwmap[i].rxflags = sc->hwmap[i].txflags | + IEEE80211_RADIOTAP_F_FCS; /* setup blink rate table to avoid per-packet lookup */ - for (j = 0; j < N(blinkrates)-1; j++) - if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) + for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) + if (blinkrates[j].rate == /* XXX why 7f? */ + (rt->rates[ix].dot11_rate & 0x7f)) break; - /* NB: this uses the last entry if the rate isn't found */ - /* XXX beware of overlow */ - sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * HZ) / 1000; - sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * HZ) / 1000; + + sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].timeOn); + sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].timeOff); } -#endif - sc->sc_currates = rt; - sc->sc_curmode = mode; - /* - * All protection frames are transmited at 2Mb/s for - * 11g, otherwise at 1Mb/s. - * XXX select protection rate index from rate table. - */ - sc->sc_protrix = ((mode == MODE_IEEE80211G || mode == MODE_ATHEROS_TURBOG) ? 1 : 0); - /* NB: caller is responsible for reseting rate control state */ -} + sc->curmode = mode; +} +#if 0 static int ath_desc_alloc(struct ath_softc *sc) { #define DS2PHYS(_sc, _ds) \ @@ -625,9 +610,13 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) dev_err(&pdev->dev, "can't get channels\n"); goto err; } -#ifdef BLE + /* NB: setup here so ath_rate_update is happy */ - ath_setcurmode(sc, MODE_IEEE80211A); + if (test_bit(MODE_IEEE80211A, ah->ah_modes)) + ath_setcurmode(sc, MODE_IEEE80211A); + else + ath_setcurmode(sc, MODE_IEEE80211B); +#ifdef BLE /* * Allocate tx+rx descriptors and populate the lists. diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 6e84246..1f15e18 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -227,17 +227,21 @@ struct ath_softc { /* rate tables */ const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; const struct ath5k_rate_table *sc_currates; /* current rate table */ - unsigned int sc_curmode; /* current phy mode */ +#endif + unsigned int curmode; /* current phy mode */ +#ifdef BLE u16 sc_curtxpow; /* current tx power limit */ struct ieee80211_channel sc_curchan; /* current h/w channel */ u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ +#endif struct { - u8 ieeerate; /* IEEE rate */ +// int ieeerate; /* IEEE rate */ u8 rxflags; /* radiotap rx flags */ u8 txflags; /* radiotap tx flags */ u16 ledon; /* softled on time */ u16 ledoff; /* softled off time */ - } sc_hwmap[32]; /* h/w rate ix mappings */ + } hwmap[32]; /* h/w rate ix mappings */ +#ifdef BLE u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ #endif commit 673bad75e34fec11259a42bccb1cc7e0a2d575a3 Author: Jiri Slaby Date: Mon Jun 25 12:26:16 2007 +0200 alloc dma_descs diff --git a/ath/if_ath.c b/ath/if_ath.c index ed978b0..f8bb32a 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -2963,35 +2963,6 @@ ath_beacon_config(struct ath_softc *sc) } #endif -static void -ath_descdma_cleanup(struct ath_softc *sc, struct list_head *head) -{ -#ifdef BLE - struct ath_buf *bf; - struct ieee80211_node *ni; - - STAILQ_FOREACH(bf, head, bf_list){ - if (bf->bf_skb) { - bus_unmap_single(sc->sc_bdev, - bf->bf_skbaddr, sc->sc_rxbufsize, - BUS_DMA_FROMDEVICE); - dev_kfree_skb(bf->bf_skb); - bf->bf_skb = NULL; - } - ni = bf->bf_node; - bf->bf_node = NULL; - if (ni != NULL) { - /* - * Reclaim node reference. - */ - ieee80211_free_node(ni); - } - } - - STAILQ_INIT(head); -#endif -} - #ifdef BLE static struct ieee80211_node * ath_node_alloc(struct ieee80211_node_table *nt) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 6435a29..e32e3eb 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -35,7 +35,6 @@ #include #include "if_athvar.h" -#include "if_ath_pci.h" #define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ @@ -47,7 +46,7 @@ } while (0) #define DPRINTF(sc, _m, _fmt...) do { \ - if (sc->sc_debug & (_m) && printk_ratelimit()) \ + if (sc->debug & (_m) && printk_ratelimit()) \ printk(_fmt); \ } while (0) enum { @@ -135,7 +134,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) enum ath5k_int status; unsigned int counter = 1000; - if (sc->sc_invalid || !ath5k_hw_is_intr_pending(ah)) + if (sc->invalid || !ath5k_hw_is_intr_pending(ah)) return IRQ_NONE; return IRQ_HANDLED; @@ -148,7 +147,7 @@ return IRQ_HANDLED; */ ath5k_hw_get_isr(ah, &status); /* NB: clears ISR too */ DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); - status &= sc->sc_imask; /* discard unasked for bits */ + status &= sc->imask; /* discard unasked for bits */ if (status & AR5K_INT_FATAL) { /* * Fatal errors are unrecoverable. Typically @@ -156,13 +155,13 @@ return IRQ_HANDLED; * the exact reason is not (presently) returned * by the hal. */ - sc->sc_stats.ast_hardware++; + sc->stats.ast_hardware++; ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ - tasklet_schedule(&sc->sc_fataltq); + tasklet_schedule(&sc->fataltq); } else if (status & AR5K_INT_RXORN) { - sc->sc_stats.ast_rxorn++; + sc->stats.ast_rxorn++; ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ - tasklet_schedule(&sc->sc_rxorntq); + tasklet_schedule(&sc->rxorntq); } else { if (status & AR5K_INT_SWBA) { /* @@ -179,24 +178,24 @@ return IRQ_HANDLED; * RXE bit is written, but it doesn't work at * least on older hardware revs. */ - sc->sc_stats.ast_rxeol++; - sc->sc_rxlink = NULL; + sc->stats.ast_rxeol++; + sc->rxlink = NULL; } if (status & AR5K_INT_TXURN) { - sc->sc_stats.ast_txurn++; + sc->stats.ast_txurn++; /* bump tx trigger level */ ath5k_hw_update_tx_triglevel(ah, true); } if (status & AR5K_INT_RX) - tasklet_schedule(&sc->sc_rxtq); + tasklet_schedule(&sc->rxtq); if (status & AR5K_INT_TX) - tasklet_schedule(&sc->sc_txtq); + tasklet_schedule(&sc->txtq); if (status & AR5K_INT_BMISS) { - sc->sc_stats.ast_bmiss++; - tasklet_schedule(&sc->sc_bmisstq); + sc->stats.ast_bmiss++; + tasklet_schedule(&sc->bmisstq); } if (status & AR5K_INT_MIB) { - sc->sc_stats.ast_mib++; + sc->stats.ast_mib++; /* * Disable interrupts until we service the MIB * interrupt; otherwise it will continue to fire. @@ -210,7 +209,7 @@ return IRQ_HANDLED; ath5k_hw_proc_mib_event(ah, &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); #endif - ath5k_hw_set_intr(ah, sc->sc_imask); + ath5k_hw_set_intr(ah, sc->imask); } } } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); @@ -479,83 +478,101 @@ static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) sc->curmode = mode; } -#if 0 -static int ath_desc_alloc(struct ath_softc *sc) + +static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) { -#define DS2PHYS(_sc, _ds) \ - ((_sc)->sc_desc_daddr + ((caddr_t)(_ds) - (caddr_t)(_sc)->sc_desc)) - int bsize; struct ath_desc *ds; struct ath_buf *bf; - int i; + dma_addr_t da; + unsigned int i; + int ret; /* allocate descriptors */ - sc->sc_desc_len = sizeof(struct ath_desc) * - (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); - barrier(); /* get_order() rounds down constants before Linux 2.6.21 */ - sc->sc_desc = bus_alloc_consistent(sc->sc_bdev, - sc->sc_desc_len, &sc->sc_desc_daddr); - if (sc->sc_desc == NULL) { - printk(KERN_ERR "%s, could not allocate descriptors\n", __func__); - return ENOMEM; + sc->desc_len = sizeof(struct ath_desc) * + (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); + sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); + if (sc->desc == NULL) { + dev_err(&pdev->dev, "can't allocate descriptors\n"); + ret = -ENOMEM; + goto err; + } + ds = sc->desc; + da = sc->desc_daddr; + DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", + __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); + + bf = kcalloc(ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1, + sizeof(struct ath_buf), GFP_KERNEL); + if (bf == NULL) { + dev_err(&pdev->dev, "can't allocate bufptr\n"); + ret = -ENOMEM; + goto err_free; } - ds = sc->sc_desc; - DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%u) -> %llx\n", - __func__, ds, (unsigned int) sc->sc_desc_len, - (unsigned long long)sc->sc_desc_daddr); - - /* allocate buffers */ - bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); - bf = kmalloc(bsize, GFP_KERNEL); - if (bf == NULL) - goto bad; - memset(bf, 0, bsize); - sc->sc_bufptr = bf; - -// STAILQ_INIT(&sc->sc_rxbuf); - for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { - bf->bf_desc = ds; - bf->bf_daddr = DS2PHYS(sc, ds); -// STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); + sc->bufptr = bf; + + INIT_LIST_HEAD(&sc->rxbuf); + for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->rxbuf); } -// STAILQ_INIT(&sc->sc_txbuf); - for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { - bf->bf_desc = ds; - bf->bf_daddr = DS2PHYS(sc, ds); -// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); + INIT_LIST_HEAD(&sc->txbuf); + for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC, + da += ATH_TXDESC * sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->txbuf); } -// STAILQ_INIT(&sc->sc_bbuf); - for (i = 0; i < ATH_BCBUF; i++, bf++, ds++) { - bf->bf_desc = ds; - bf->bf_daddr = DS2PHYS(sc, ds); -// STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); + INIT_LIST_HEAD(&sc->bbuf); + for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->bbuf); } return 0; -bad: - bus_free_consistent(sc->sc_bdev, sc->sc_desc_len, - sc->sc_desc, sc->sc_desc_daddr); - sc->sc_desc = NULL; - return -ENOMEM; -#undef DS2PHYS +err_free: + pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); +err: + sc->desc = NULL; + return ret; } - -static void ath_desc_free(struct ath_softc *sc) +#if 0 +static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, + struct list_head *head) { - ath_descdma_cleanup(sc, sc->sc_bbuf); - ath_descdma_cleanup(sc, sc->sc_txbuf); - ath_descdma_cleanup(sc, sc->sc_rxbuf); + struct list_head *pos; + struct ath_buf *bf; - /* Free memory associated with all descriptors */ - bus_free_consistent(sc->sc_bdev, sc->sc_desc_len, - sc->sc_desc, sc->sc_desc_daddr); + list_for_each(pos, head, bf_list){ + bf = list_entry(pos, struct ath_buf, list); + if (bf->skb) { + pci_unmap_single(pdev, bf->skbaddr, sc->rxbufsize, + PCI_DMA_FROMDEVICE); + dev_kfree_skb(bf->skb); + bf->skb = NULL; + } + } - kfree(sc->sc_bufptr); - sc->sc_bufptr = NULL; + INIT_LIST_HEAD(head); } #endif +static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) +{ +#ifdef BLE + ath_descdma_cleanup(sc, pdev, sc->bbuf); + ath_descdma_cleanup(sc, pdev, sc->txbuf); + ath_descdma_cleanup(sc, pdev, sc->rxbuf); +#endif + /* Free memory associated with all descriptors */ + pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); + + kfree(sc->bufptr); + sc->bufptr = NULL; +} + static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; @@ -572,18 +589,18 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) * return false w/o doing anything. MAC's that do * support it will return true w/o doing anything. */ - sc->sc_mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); + sc->mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); /* * Get the hardware key cache size. */ - sc->sc_keymax = AR5K_KEYCACHE_SIZE; + sc->keymax = AR5K_KEYCACHE_SIZE; /* * Reset the key cache since some parts do not * reset the contents on initial power up. */ - for (i = 0; i < sc->sc_keymax; i++) + for (i = 0; i < sc->keymax; i++) ath5k_hw_reset_key(ah, i); /* * Mark key cache slots associated with global keys @@ -616,16 +633,16 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ath_setcurmode(sc, MODE_IEEE80211A); else ath_setcurmode(sc, MODE_IEEE80211B); -#ifdef BLE /* * Allocate tx+rx descriptors and populate the lists. */ - ret = ath_desc_alloc(sc); + ret = ath_desc_alloc(sc, pdev); if (ret) { - printk(KERN_ERR "failed to allocate descriptors: %d\n", error); - goto bad; + dev_err(&pdev->dev, "can't allocate descriptors\n"); + goto err; } +#ifdef BLE /* * Allocate hardware transmit queues: one queue for @@ -908,9 +925,9 @@ err: return ret; } -static void ath_detach(struct ieee80211_hw *hw) +static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) { -// struct ath_softc *sc = hw->priv; + struct ath_softc *sc = hw->priv; // ath_stop(hw); /* @@ -927,7 +944,7 @@ static void ath_detach(struct ieee80211_hw *hw) */ // ieee80211_ifdetach(ic); // ath_rate_detach(sc->sc_rc); -// ath_desc_free(sc); + ath_desc_free(sc, pdev); // ath_tx_cleanup(sc); /* @@ -1033,11 +1050,11 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, * Mark the device as detached to avoid processing * interrupts until setup is complete. */ - sc->sc_invalid = 1; + sc->invalid = 1; sc->iobase = mem; - sc->sc_cachelsz = csz * sizeof(u32); /* convert to bytes */ + sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ mutex_init(&sc->lock); - spin_lock_init(&sc->sc_txbuflock); + spin_lock_init(&sc->txbuflock); /* tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)hw); @@ -1067,7 +1084,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, dev_info(&pdev->dev, "%s chip found\n", ath_chip_name(id->driver_data)); /* ready to process interrupts */ - sc->sc_invalid = 0; + sc->invalid = 0; return 0; err_ah: @@ -1091,7 +1108,7 @@ static void __devexit ath_pci_remove(struct pci_dev *pdev) struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct ath_softc *sc = hw->priv; - ath_detach(hw); + ath_detach(pdev, hw); ath5k_hw_detach(sc->ah); free_irq(pdev->irq, sc); pci_iounmap(pdev, sc->iobase); @@ -1106,8 +1123,8 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct ath_softc *sc = hw->priv; - if (sc->sc_softled) - ath5k_hw_set_gpio(sc->ah, sc->sc_ledpin, 1); + if (sc->softled) + ath5k_hw_set_gpio(sc->ah, sc->ledpin, 1); // ath_stop(hw); pci_save_state(pdev); @@ -1140,9 +1157,9 @@ static int ath_pci_resume(struct pci_dev *pdev) pci_write_config_byte(pdev, 0x41, 0); // ath_init(hw); - if (sc->sc_softled) { - ath5k_hw_set_gpio_output(sc->ah, sc->sc_ledpin); - ath5k_hw_set_gpio(sc->ah, sc->sc_ledpin, 0); + if (sc->softled) { + ath5k_hw_set_gpio_output(sc->ah, sc->ledpin); + ath5k_hw_set_gpio(sc->ah, sc->ledpin, 0); } return 0; diff --git a/ath/if_ath_pci.h b/ath/if_ath_pci.h deleted file mode 100644 index 1d152bd..0000000 --- a/ath/if_ath_pci.h +++ /dev/null @@ -1,40 +0,0 @@ -/*- - * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting - * Copyright (c) 2004-2005 Atheros Communications, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - */ - -#ifndef _DEV_ATH_PCI_H_ -#define _DEV_ATH_PCI_H_ - -#include - -#define bus_map_single pci_map_single -#define bus_unmap_single pci_unmap_single -#define bus_dma_sync_single pci_dma_sync_single_for_cpu -#define BUS_DMA_MAP_ERROR(a) pci_dma_mapping_error(a) -#define bus_alloc_consistent pci_alloc_consistent -#define bus_free_consistent pci_free_consistent -#define BUS_DMA_FROMDEVICE PCI_DMA_FROMDEVICE -#define BUS_DMA_TODEVICE PCI_DMA_TODEVICE - -#endif /* _DEV_ATH_PCI_H_ */ diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 1f15e18..14b5564 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -108,13 +108,13 @@ struct ath_node { } while (0) struct ath_buf { - struct list_head bf_list; - //int bf_nseg; - int bf_flags; /* tx descriptor flags */ - struct ath_desc *bf_desc; /* virtual addr of desc */ - dma_addr_t bf_daddr; /* physical addr of desc */ - struct sk_buff *bf_skb; /* skbuff for buf */ - dma_addr_t bf_skbaddr; /* physical addr of skb data */ + struct list_head list; + //int nseg; + int flags; /* tx descriptor flags */ + struct ath_desc *desc; /* virtual addr of desc */ + dma_addr_t daddr; /* physical addr of desc */ + struct sk_buff *skb; /* skbuff for buf */ + dma_addr_t skbaddr; /* physical addr of skb data */ #ifdef BLE struct ieee80211_node *bf_node; /* pointer to the node */ #endif @@ -179,7 +179,7 @@ struct ath_softc { void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ // struct net_device_stats sc_devstats; /* device statistics */ - struct ath_stats sc_stats; /* private statistics */ + struct ath_stats stats; /* private statistics */ struct ieee80211_hw *hw; /* IEEE 802.11 common */ struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; struct ieee80211_channel channels[ATH_CHAN_MAX]; @@ -190,7 +190,7 @@ struct ath_softc { int sc_regdomain; int sc_countrycode; #endif - int sc_debug; + int debug; #ifdef BLE void (*sc_recv_mgmt)(struct ieee80211com *, @@ -200,18 +200,19 @@ struct ath_softc { int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); void (*sc_node_free)(struct ieee80211_node *); - struct ath_desc *sc_desc; /* TX/RX descriptors */ - size_t sc_desc_len; /* size of TX/RX descriptors */ #endif - u16 sc_cachelsz; /* cache line size */ + struct ath_buf *bufptr; /* allocated buffer ptr */ + struct ath_desc *desc; /* TX/RX descriptors */ + dma_addr_t desc_daddr; /* DMA (physical) address */ + size_t desc_len; /* size of TX/RX descriptors */ + u16 cachelsz; /* cache line size */ #ifdef BLE - dma_addr_t sc_desc_daddr; /* DMA (physical) address */ struct ath_ratectrl *sc_rc; /* tx rate control support */ void (*sc_setdefantenna)(struct ath_softc *, u_int); #endif - unsigned int sc_invalid : 1, /* disable hardware accesses */ - sc_mrretry : 1, /* multi-rate retry support */ - sc_softled : 1, /* enable LED gpio status */ + unsigned int invalid : 1, /* disable hardware accesses */ + mrretry : 1, /* multi-rate retry support */ + softled : 1, /* enable LED gpio status */ xxx:1; #ifdef BLE sc_splitmic: 1, /* split TKIP MIC keys */ @@ -245,13 +246,13 @@ struct ath_softc { u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ #endif - enum ath5k_int sc_imask; /* interrupt mask copy */ - u_int sc_keymax; /* size of key cache */ + enum ath5k_int imask; /* interrupt mask copy */ + u_int keymax; /* size of key cache */ #ifdef BLE u8 sc_keymap[ATH_KEYBYTES];/* key use bit map */ struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ #endif - u_int sc_ledpin; /* GPIO pin for driving LED */ + u_int ledpin; /* GPIO pin for driving LED */ #ifdef BLE u_int sc_ledon; /* pin setting for LED on */ u_int sc_ledidle; /* idle polling interval */ @@ -273,23 +274,23 @@ struct ath_softc { } u_rx_rt; int sc_rx_th_len; #endif - struct tasklet_struct sc_fataltq; /* fatal int tasklet */ + struct tasklet_struct fataltq; /* fatal int tasklet */ #ifdef BLE struct tasklet_struct sc_radartq; /* Radar detection */ int sc_rxbufsize; /* rx size based on mtu */ - struct list_head *sc_rxbuf; /* receive buffer */ #endif - struct tasklet_struct sc_rxtq; /* rx intr tasklet */ - struct tasklet_struct sc_rxorntq; /* rxorn intr tasklet */ - u32 *sc_rxlink; /* link ptr in last RX desc */ + struct list_head rxbuf; /* receive buffer */ + struct tasklet_struct rxtq; /* rx intr tasklet */ + struct tasklet_struct rxorntq; /* rxorn intr tasklet */ + u32 *rxlink; /* link ptr in last RX desc */ #ifdef BLE u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ - struct list_head *sc_txbuf; /* transmit buffer */ #endif - spinlock_t sc_txbuflock; /* txbuf lock */ + struct list_head txbuf; /* transmit buffer */ + spinlock_t txbuflock; /* txbuf lock */ #ifdef BLE int sc_tx_timer; /* transmit timeout */ u_int sc_txqsetup; /* h/w queues setup */ @@ -297,20 +298,19 @@ struct ath_softc { struct ath_txq sc_txq[AR5K_NUM_TX_QUEUES]; struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ #endif - struct tasklet_struct sc_txtq; /* tx intr tasklet */ -#ifdef BLE + struct tasklet_struct txtq; /* tx intr tasklet */ - struct list_head *sc_bbuf; /* beacon buffers */ + struct list_head bbuf; /* beacon buffers */ +#ifdef BLE u_int sc_bhalq; /* HAL q for outgoing beacons */ u_int sc_bmisscount; /* missed beacon transmits */ u32 sc_ant_tx[8]; /* recent tx frames/antenna */ struct ath_txq *sc_cabq; /* tx q for cab frames */ - struct ath_buf *sc_bufptr; /* allocated buffer ptr */ #ifdef BLE - struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ + struct ieee80211_beacon_offsets boff; /* dynamic update state */ #endif #endif - struct tasklet_struct sc_bmisstq; /* bmiss intr tasklet */ + struct tasklet_struct bmisstq; /* bmiss intr tasklet */ #ifdef BLE struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ enum { commit 74e0e3d12265fc676fa9e77b957f5595f7efd785 Author: Jiri Slaby Date: Mon Jun 25 12:33:08 2007 +0200 timers cleanup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index e32e3eb..6fffdbd 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -720,22 +720,15 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto bad2; } - init_timer(&sc->sc_scan_ch); - sc->sc_scan_ch.function = ath_next_scan; - sc->sc_scan_ch.data = (unsigned long)hw; - - init_timer(&sc->sc_cal_ch); - sc->sc_cal_ch.function = ath_calibrate; - sc->sc_cal_ch.data = (unsigned long)hw; - - sc->sc_blinking = 0; - sc->sc_ledstate = 1; - sc->sc_ledon = 0; /* low true */ - sc->sc_ledidle = (2700*HZ)/1000; /* 2.7sec */ - - init_timer(&sc->sc_ledtimer); - sc->sc_ledtimer.function = ath_led_off; - sc->sc_ledtimer.data = (unsigned long) sc; + setup_timer(&sc->scan_ch, ath_next_scan, (unsigned long)hw); + setup_timer(&sc->cal_ch, ath_calibrate, (unsigned long)hw); + + sc->blinking = 0; + sc->ledstate = 1; + sc->ledon = 0; /* low true */ + sc->ledidle = (2700*HZ)/1000; /* 2.7sec */ + + setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); /* * Auto-enable soft led processing for IBM cards and for * 5211 minipci cards. Users can also manually enable/disable commit af21a9c0abb3644869fe5890b87acb9963d9a6f1 Author: Jiri Slaby Date: Mon Jun 25 14:34:31 2007 +0200 remove yet copied stuff from if_ath.c diff --git a/ath/if_ath.c b/ath/if_ath.c index f8bb32a..beae81d 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -1,74 +1,9 @@ -/*- - * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -/* - * Driver for the Atheros Wireless LAN controller. - * - * This software is derived from work of Atsushi Onoe; his contribution - * is greatly appreciated. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - /* * #define AR_DEBUG here if you need to debug the ath_pci module (athdebug) * disable this if not needed because it adds an amount of load */ #define AR_DEBUG -/*#include "radar.h"*/ - -#include "if_ath_pci.h" -#include "if_athvar.h" -#include "ath5k.h" -#include "ath_hw.h" - /* unaligned little endian access */ #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) @@ -79,107 +14,6 @@ enum { ATH_LED_POLL, }; -static int ath_init(struct ieee80211_hw *); -static int ath_reset(struct ieee80211_hw *); -static void ath_fatal_tasklet(unsigned long); -static void ath_bstuck_tasklet(unsigned long); -static void ath_rxorn_tasklet(unsigned long); -static void ath_bmiss_tasklet(unsigned long); -static void ath_radar_tasklet(unsigned long); -static int ath_stop_locked(struct ieee80211_hw *); -static int ath_stop(struct ieee80211_hw *); -#ifdef BLE -static int ath_media_change(struct net_device *); -static int ath_key_alloc(struct ieee80211com *, - const struct ieee80211_key_conf *); -static int ath_key_delete(struct ieee80211com *, - const struct ieee80211_key_conf *); -static int ath_key_set(struct ieee80211com *, - const struct ieee80211_key_conf *, - const u_int8_t mac[IEEE80211_ADDR_LEN]); -static void ath_key_update_begin(struct ieee80211com *); -static void ath_key_update_end(struct ieee80211com *); -static void ath_mode_init(struct net_device *); -#endif -static void ath_setslottime(struct ath_softc *); -//static void ath_updateslot(struct net_device *); -static int ath_beaconq_setup(struct ath_hal *); -//static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); -static void ath_beacon_setup(struct ath_softc *, struct ath_buf *, - struct ieee80211_tx_control *); -static void ath_beacon_send(struct net_device *); -//static void ath_beacon_free(struct ath_softc *); -//static void ath_beacon_config(struct ath_softc *); -static void ath_descdma_cleanup(struct ath_softc *sc, struct list_head *); -static int ath_desc_alloc(struct ath_softc *); -static void ath_desc_free(struct ath_softc *); -#ifdef BLE -static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); -static void ath_node_free(struct ieee80211_node *); -static u_int8_t ath_node_getrssi(const struct ieee80211_node *); -#endif -static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); -#ifdef BLE -static void ath_recv_mgmt(struct ieee80211com *, struct sk_buff *, - struct ieee80211_node *, - int subtype, int rssi, u_int32_t rstamp); -#endif -static void ath_setdefantenna(struct ath_softc *, u_int); -static void ath_rx_tasklet(unsigned long data); -static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); -//static int ath_wme_update(struct ieee80211com *); -static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); -static void ath_tx_cleanup(struct ath_softc *); -#ifdef BLE -static int ath_start(struct sk_buff *, struct net_device *); -static int ath_tx_setup(struct ath_softc *, int ac, int txq); -static int ath_tx_start(struct net_device *, struct ieee80211_node *, - struct ath_buf *, struct sk_buff *); -static void ath_tx_tasklet_q0(unsigned long data); -static void ath_tx_tasklet_q0123(unsigned long data); -static void ath_tx_tasklet(unsigned long data); -static void ath_tx_timeout(struct net_device *); -static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); -#endif -//static void ath_draintxq(struct ath_softc *); -//static void ath_stoprecv(struct ath_softc *); -static int ath_startrecv(struct ath_softc *); -//static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); -static void ath_next_scan(unsigned long); -static void ath_calibrate(unsigned long); -#ifdef BLE -static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); -#if IEEE80211_VLAN_TAG_USED -static void ath_vlan_register(struct net_device *, struct vlan_group *); -static void ath_vlan_kill_vid(struct net_device *, unsigned short ); -#endif -static struct net_device_stats *ath_getstats(struct net_device *); -static struct iw_statistics *ath_iw_getstats(struct net_device *); -static struct iw_handler_def ath_iw_handler_def; -static void ath_setup_stationkey(struct ieee80211_node *); -static void ath_newassoc(struct ieee80211_node *, int); -#endif -static int ath_getchannels(struct ieee80211_hw *, u_int cc, - bool outdoor, bool xchanmode); -#ifdef BLE -static void ath_led_event(struct ath_softc *, int); -#endif -static void ath_led_off(unsigned long arg); -static void ath_update_txpow(struct ath_softc *); -#ifdef BLE -static int ath_set_mac_address(struct net_device *, void *); -static int ath_change_mtu(struct net_device *, int); -static int ath_ioctl(struct net_device *, struct ifreq *, int); -#endif -static int ath_rate_setup(struct ieee80211_hw *, u_int mode); -static void ath_setcurmode(struct ath_softc *, unsigned int); - -//static int ath_rawdev_attach(struct ath_softc *); -//static void ath_rawdev_detach(struct ath_softc *); -static void ath_dynamic_sysctl_register(struct ath_softc *); -static void ath_dynamic_sysctl_unregister(struct ath_softc *); -static void ath_announce(struct ath_softc *); - static const char *hal_status_desc[] = { "Everything went O.K.", "Unable to allocate memory for ath_hal", @@ -204,32 +38,6 @@ static int ath_xchanmode = true; /* enable extended channels */ static int ath_debug = 0; #define IFF_DUMPPKTS(sc, _m) \ ((sc->sc_debug & _m) || ieee80211_msg_dumppkts(&sc->sc_ic)) -enum { - ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ - ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ - ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ - ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ - ATH_DEBUG_RATE = 0x00000010, /* rate control */ - ATH_DEBUG_RESET = 0x00000020, /* reset processing */ - ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ - ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ - ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ - ATH_DEBUG_INTR = 0x00001000, /* ISR */ - ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ - ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ - ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ - ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ - ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ - ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ - ATH_DEBUG_NODE = 0x00080000, /* node management */ - ATH_DEBUG_LED = 0x00100000, /* led management */ - ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ - ATH_DEBUG_ANY = 0xffffffff -}; -#define DPRINTF(sc, _m, _fmt...) do { \ - if (sc->sc_debug & (_m)) \ - printk(_fmt); \ -} while (0) #define KEYPRINTF(sc, ix, hk, mac) do { \ if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ ath_keyprint(__func__, ix, hk, mac); \ @@ -308,599 +116,6 @@ struct wlan_ng_prism2_header { struct p80211item_u32 frmlen; }; -int -ath_attach(u_int16_t devid, struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; -// struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah; - enum ath5k_status status; - int error = 0, i; - u_int8_t csz; - - DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); - - /* - * Cache line size is used to size and align various - * structures used to communicate with the hardware. - */ - bus_read_cachesize(sc, &csz); - /* XXX assert csz is non-zero */ - sc->sc_cachelsz = csz << 2; /* convert to bytes */ - - ATH_LOCK_INIT(sc); - ATH_TXBUF_LOCK_INIT(sc); - - tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)hw); - - /* - * Attach the hal - */ - ah = ath5k_hw_init(devid, sc, sc->sc_iobase, &status); - if (ah == NULL) { - printk(KERN_ERR "%s: unable to attach hardware: '%s' (HAL status %u)\n", - __func__, hal_status_desc[status], status); - error = ENXIO; - goto bad; - } - sc->sc_ah = ah; - - /* - * Check if the MAC has multi-rate retry support. - * We do this by trying to setup a fake extended - * descriptor. MAC's that don't have support will - * return false w/o doing anything. MAC's that do - * support it will return true w/o doing anything. - */ - sc->sc_mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); - - /* - * Check if the device has hardware counters for PHY - * errors. If so we need to enable the MIB interrupt - * so we can act on stat triggers. - */ - if (ath_hal_hwphycounters(ah)) - sc->sc_needmib = 1; - - /* - * Get the hardware key cache size. - */ - sc->sc_keymax = ath5k_hw_get_keycache_size(ah); - if (sc->sc_keymax > ATH_KEYMAX) { - printk(KERN_WARNING "Warning, using only %u of %u key cache " - "slots\n", ATH_KEYMAX, sc->sc_keymax); - sc->sc_keymax = ATH_KEYMAX; - } - - /* - * Reset the key cache since some parts do not - * reset the contents on initial power up. - */ - for (i = 0; i < sc->sc_keymax; i++) - ath5k_hw_reset_key(ah, i); - /* - * Mark key cache slots associated with global keys - * as in use. If we knew TKIP was not to be used we - * could leave the +32, +64, and +32+64 slots free. - * XXX only for splitmic. - */ -#ifdef BLE - for (i = 0; i < IEEE80211_WEP_NKID; i++) { - setbit(sc->sc_keymap, i); - setbit(sc->sc_keymap, i+32); - setbit(sc->sc_keymap, i+64); - setbit(sc->sc_keymap, i+32+64); - } -#endif - - /* - * Collect the channel list using the default country - * code and including outdoor channels. The 802.11 layer - * is resposible for filtering this list based on settings - * like the phy mode. - */ - if (countrycode != -1) - ath_countrycode = countrycode; - if (outdoor != -1) - ath_outdoor = outdoor; - if (xchanmode != -1) - ath_xchanmode = xchanmode; - error = ath_getchannels(hw, ath_countrycode, ath_outdoor,ath_xchanmode); - if (error != 0) { - printk("error! but continuing anyways...\n"); - //goto bad; - } - - /* - * Setup rate tables for all potential media types. - */ - ath_rate_setup(hw, MODE_IEEE80211A); - ath_rate_setup(hw, MODE_IEEE80211B); - ath_rate_setup(hw, MODE_IEEE80211G); - ath_rate_setup(hw, MODE_ATHEROS_TURBO); - ath_rate_setup(hw, MODE_ATHEROS_TURBOG); - /* NB: setup here so ath_rate_update is happy */ - ath_setcurmode(sc, MODE_IEEE80211A); - - /* - * Allocate tx+rx descriptors and populate the lists. - */ - error = ath_desc_alloc(sc); - if (error != 0) { - printk(KERN_ERR "failed to allocate descriptors: %d\n", error); - goto bad; - } - - /* - * Allocate hardware transmit queues: one queue for - * beacon frames and one data queue for each QoS - * priority. Note that the hal handles reseting - * these queues at the needed time. - * - * XXX PS-Poll - */ - sc->sc_bhalq = ath_beaconq_setup(ah); - if (sc->sc_bhalq == (u_int) -1) { - printk(KERN_ERR "unable to setup a beacon xmit queue!\n"); - goto bad2; - } - sc->sc_cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); - if (sc->sc_cabq == NULL) { - printk(KERN_ERR "unable to setup CAB xmit queue!\n"); - error = EIO; - goto bad2; - } -#ifdef BLE - /* NB: insure BK queue is the lowest priority h/w queue */ - if (!ath_tx_setup(sc, WME_AC_BK, AR5K_WME_AC_BK)) { - printk(KERN_ERR "unable to setup xmit queue for %s traffic!\n", - ieee80211_wme_acnames[WME_AC_BK]); - error = EIO; - goto bad2; - } - if (!ath_tx_setup(sc, WME_AC_BE, AR5K_WME_AC_BE) || - !ath_tx_setup(sc, WME_AC_VI, AR5K_WME_AC_VI) || - !ath_tx_setup(sc, WME_AC_VO, AR5K_WME_AC_VO)) { - /* - * Not enough hardware tx queues to properly do WME; - * just punt and assign them all to the same h/w queue. - * We could do a better job of this if, for example, - * we allocate queues when we switch from station to - * AP mode. - */ - if (sc->sc_ac2q[WME_AC_VI] != NULL) - ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); - if (sc->sc_ac2q[WME_AC_BE] != NULL) - ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); - sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; - sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; - sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; - } - - /* - * Special case certain configurations. Note the - * CAB queue is handled by these specially so don't - * include them when checking the txq setup mask. - */ - switch (sc->sc_txqsetup &~ (1<sc_cabq->axq_qnum)) { - case 0x01: - ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet_q0, dev); - break; - case 0x0f: - ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet_q0123, dev); - break; - default: - ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet, dev); - break; - } - - /* - * Setup rate control. Some rate control modules - * call back to change the anntena state so expose - * the necessary entry points. - * XXX maybe belongs in struct ath_ratectrl? - */ - sc->sc_setdefantenna = ath_setdefantenna; - sc->sc_rc = ath_rate_attach(sc); - if (sc->sc_rc == NULL) { - error = EIO; - goto bad2; - } -#endif - init_timer(&sc->sc_scan_ch); - sc->sc_scan_ch.function = ath_next_scan; - sc->sc_scan_ch.data = (unsigned long)hw; - - init_timer(&sc->sc_cal_ch); - sc->sc_cal_ch.function = ath_calibrate; - sc->sc_cal_ch.data = (unsigned long)hw; - - sc->sc_blinking = 0; - sc->sc_ledstate = 1; - sc->sc_ledon = 0; /* low true */ - sc->sc_ledidle = (2700*HZ)/1000; /* 2.7sec */ - - init_timer(&sc->sc_ledtimer); - sc->sc_ledtimer.function = ath_led_off; - sc->sc_ledtimer.data = (unsigned long) sc; - /* - * Auto-enable soft led processing for IBM cards and for - * 5211 minipci cards. Users can also manually enable/disable - * support with a sysctl. - */ - sc->sc_softled = (devid == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || - devid == PCI_DEVICE_ID_ATHEROS_AR5211); - if (sc->sc_softled) { - ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); - ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); - } - -#ifdef BLE - ether_setup(dev); - dev->open = ath_init; - dev->stop = ath_stop; - dev->hard_start_xmit = ath_start; - dev->tx_timeout = ath_tx_timeout; - dev->watchdog_timeo = 5 * HZ; /* XXX */ - dev->set_multicast_list = ath_mode_init; - dev->do_ioctl = ath_ioctl; - dev->get_stats = ath_getstats; - dev->set_mac_address = ath_set_mac_address; - dev->change_mtu = &ath_change_mtu; - dev->tx_queue_len = ATH_TXBUF; /* TODO? 1 for mgmt frame */ -/*get_wireless_stats moved from net_device to iw_handler_def*/ -# if IW_HANDLER_VERSION < 7 - dev->get_wireless_stats = ath_iw_getstats; -# endif - ieee80211_ioctl_iwsetup(&ath_iw_handler_def); - dev->wireless_handlers = &ath_iw_handler_def; -#if IEEE80211_VLAN_TAG_USED - dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; - dev->vlan_rx_register = ath_vlan_register; - dev->vlan_rx_kill_vid = ath_vlan_kill_vid; -#endif /* IEEE80211_VLAN_TAG_USED */ - ic->ic_dev = dev; - ic->ic_devstats = &sc->sc_devstats; - ic->ic_init = ath_init; - ic->ic_reset = ath_reset; - ic->ic_newassoc = ath_newassoc; - ic->ic_updateslot = ath_updateslot; - ic->ic_wme.wme_update = ath_wme_update; - /* XXX not right but it's not used anywhere important */ - ic->ic_phytype = MODULATION_OFDM; - ic->ic_opmode = IEEE80211_M_STA; - ic->ic_caps = - IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ - | IEEE80211_C_AHDEMO /* adhoc demo (pseudo_ibss) mode */ - | IEEE80211_C_HOSTAP /* hostap mode */ - | IEEE80211_C_MONITOR /* monitor mode */ - | IEEE80211_C_SHPREAMBLE /* short preamble supported */ - | IEEE80211_C_SHSLOT /* short slot time supported */ - | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ - ; - /* - * initialize management queue - */ - skb_queue_head_init(&ic->ic_mgtq); - - /* - * Query the hal to figure out h/w crypto support. - */ - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_WEP)) - ic->ic_caps |= IEEE80211_C_WEP; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_AES_OCB)) - ic->ic_caps |= IEEE80211_C_AES; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_AES_CCM)) - ic->ic_caps |= IEEE80211_C_AES_CCM; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_CKIP)) - ic->ic_caps |= IEEE80211_C_CKIP; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_TKIP)) { - ic->ic_caps |= IEEE80211_C_TKIP; - /* - * Check if h/w does the MIC and/or whether the - * separate key cache entries are required to - * handle both tx+rx MIC keys. - */ - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_MIC)) - ic->ic_caps |= IEEE80211_C_TKIPMIC; - if (ath_hal_tkipsplit(ah)) - sc->sc_splitmic = 1; - } - sc->sc_hasclrkey = ath_hal_ciphersupported(ah, AR5K_CIPHER_CLR); - sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); - /* - * TPC support can be done either with a global cap or - * per-packet support. The latter is not available on - * all parts. We're a bit pedantic here as all parts - * support a global cap. - */ - if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) - ic->ic_caps |= IEEE80211_C_TXPMGT; - - /* - * Mark WME capability only if we have sufficient - * hardware queues to do proper priority scheduling. - */ - if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) - ic->ic_caps |= IEEE80211_C_WME; - /* - * Check for misc other capabilities. - */ - if (ath_hal_hasbursting(ah)) - ic->ic_caps |= IEEE80211_C_BURST; - - /* - * Indicate we need the 802.11 header padded to a - * 32-bit boundary for 4-address and QoS frames. - */ - ic->ic_flags |= IEEE80211_F_DATAPAD; -#endif - - /* - * Query the hal about antenna support. - */ - sc->sc_defant = ath5k_hw_get_def_antenna(ah); - - /* - * Not all chips have the VEOL support we want to - * use with IBSS beacons; check here for it. - */ - sc->sc_hasveol = ath_hal_hasveol(ah); - - sc->sc_rxfilter = 0; - - /* get mac address from hardware */ -// ath_hal_getmac(ah, ic->ic_myaddr); BLEE -// IEEE80211_ADDR_COPY(dev->dev_addr, ic->ic_myaddr); -#ifdef BLE - /* call MI attach routine. */ - ieee80211_ifattach(ic); - /* override default methods */ - ic->ic_node_alloc = ath_node_alloc; - sc->sc_node_free = ic->ic_node_free; - ic->ic_node_free = ath_node_free; - ic->ic_node_getrssi = ath_node_getrssi; - sc->sc_recv_mgmt = ic->ic_recv_mgmt; - ic->ic_recv_mgmt = ath_recv_mgmt; - sc->sc_newstate = ic->ic_newstate; - ic->ic_newstate = ath_newstate; - ic->ic_crypto.cs_key_alloc = ath_key_alloc; - ic->ic_crypto.cs_key_delete = ath_key_delete; - ic->ic_crypto.cs_key_set = ath_key_set; - ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; - ic->ic_crypto.cs_key_update_end = ath_key_update_end; - - radar_init(ic); -#endif -#if 0 - /* complete initialization */ - ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); - - if (register_netdev(dev)) { - printk(KERN_ERR "%s: unable to register device\n", dev->name); - goto bad3; - } - -#endif - /* - * Attach dynamic MIB vars and announce support - * now that we have a device name with unit number. - */ - ath_dynamic_sysctl_register(sc); -// ath_rate_dynamic_sysctl_register(sc); - ath_announce(sc); - - return 0; -//bad3: -// ieee80211_ifdetach(ic); -// ath_rate_detach(sc->sc_rc); -bad2: -#ifdef BLE - if (sc->sc_txq[WME_AC_BK].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_BK]); - } - if (sc->sc_txq[WME_AC_BE].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_BE]); - } - if (sc->sc_txq[WME_AC_VI].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VI]); - } - if (sc->sc_txq[WME_AC_VO].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VO]); - } -#endif - ath_tx_cleanup(sc); - ath_desc_free(sc); -bad: - if (ah) { - ath5k_hw_detach(ah); - } - sc->sc_invalid = 1; - return error; -} - -int -ath_detach(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; -// struct ieee80211com *ic = &sc->sc_ic; - - ath_stop(hw); - sc->sc_invalid = 1; - /* - * NB: the order of these is important: - * o call the 802.11 layer before detaching the hal to - * insure callbacks into the driver to delete global - * key cache entries can be handled - * o reclaim the tx queue data structures after calling - * the 802.11 layer as we'll get called back to reclaim - * node state and potentially want to use them - * o to cleanup the tx queues the hal is called, so detach - * it last - * Other than that, it's straightforward... - */ -// ieee80211_ifdetach(ic); -// ath_rate_detach(sc->sc_rc); - ath_desc_free(sc); - ath_tx_cleanup(sc); - ath5k_hw_detach(sc->sc_ah); - - /* - * NB: can't reclaim these until after ieee80211_ifdetach - * returns because we'll get called back to reclaim node - * state and potentially want to use them. - */ - ath_dynamic_sysctl_unregister(sc); -// ath_rawdev_detach(sc); -// unregister_netdev(dev); - - return 0; -} - -void -ath_suspend(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; - - if (sc->sc_softled) - ath5k_hw_set_gpio(ah, sc->sc_ledpin, 1); - - ath_stop(hw); -} - -void -ath_resume(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; - - ath_init(hw); - if (sc->sc_softled) { - ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); - ath5k_hw_set_gpio(ah, sc->sc_ledpin, 0); - } -} - -/* - * Interrupt handler. Most of the actual processing is deferred. - */ - -/* - *Port r1752 - Starting linux kernel v2.6.19 and later - *interrupt handlers are not passed. - */ -irqreturn_t ath_intr(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; - enum ath5k_int status; - int needmark; - - if (sc->sc_invalid) { - /* - * The hardware is not ready/present, don't touch anything. - * Note this can happen early on if the IRQ is shared. - */ - DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); - return IRQ_NONE; - } - if (!ath_hw_irq_pending(ah)) /* shared irq, not for us */ - return IRQ_NONE; - if ((dev->flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", - __func__, dev->flags); - ath5k_hw_get_isr(ah, &status); /* clear ISR */ - ath5k_hw_set_intr(ah, 0); /* disable further intr's */ - return IRQ_HANDLED; - } - needmark = 0; - - do { - /* - * Figure out the reason(s) for the interrupt. Note - * that the hal returns a pseudo-ISR that may include - * bits we haven't explicitly enabled so we mask the - * value to insure we only process bits we requested. - */ - ath5k_hw_get_isr(ah, &status); /* NB: clears ISR too */ - DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); - status &= sc->sc_imask; /* discard unasked for bits */ - if (status & AR5K_INT_FATAL) { - /* - * Fatal errors are unrecoverable. Typically - * these are caused by DMA errors. Unfortunately - * the exact reason is not (presently) returned - * by the hal. - */ - sc->sc_stats.ast_hardware++; - ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ - tasklet_schedule(&sc->sc_fataltq); - } else if (status & AR5K_INT_RXORN) { - sc->sc_stats.ast_rxorn++; - ath5k_hw_set_intr(ah, 0); /* disable intr's until reset */ - tasklet_schedule(&sc->sc_rxorntq); - } else { - if (status & AR5K_INT_SWBA) { - /* - * Software beacon alert--time to send a beacon. - * Handle beacon transmission directly; deferring - * this is too slow to meet timing constraints - * under load. - */ - ath_beacon_send(dev); - } - if (status & AR5K_INT_RXEOL) { - /* - * NB: the hardware should re-read the link when - * RXE bit is written, but it doesn't work at - * least on older hardware revs. - */ - sc->sc_stats.ast_rxeol++; - sc->sc_rxlink = NULL; - } - if (status & AR5K_INT_TXURN) { - sc->sc_stats.ast_txurn++; - /* bump tx trigger level */ - ath5k_hw_update_tx_triglevel(ah, true); - } - if (status & AR5K_INT_RX) - tasklet_schedule(&sc->sc_rxtq); - if (status & AR5K_INT_TX) - tasklet_schedule(&sc->sc_txtq); - if (status & AR5K_INT_BMISS) { - sc->sc_stats.ast_bmiss++; - tasklet_schedule(&sc->sc_bmisstq); - } - if (status & AR5K_INT_MIB) { - sc->sc_stats.ast_mib++; - /* - * Disable interrupts until we service the MIB - * interrupt; otherwise it will continue to fire. - */ - ath5k_hw_set_intr(ah, 0); - /* - * Let the hal handle the event. We assume it will - * clear whatever condition caused the interrupt. - */ -#ifdef BLE - ath5k_hw_proc_mib_event(ah, - &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); -#endif - ath5k_hw_set_intr(ah, sc->sc_imask); - } - } - } while (ath5k_hw_is_intr_pending(ah)); - - return IRQ_HANDLED; -} - static void ath_fatal_tasklet(unsigned long data) { @@ -6384,103 +5599,3 @@ ath_announce(struct ath_softc *sc) #endif #undef AR5K_MODE_DUALBAND } - -/* - * Static (i.e. global) sysctls. Note that the hal sysctls - * are located under ours by sharing the setting for DEV_ATH. - */ -enum { - DEV_ATH = 9, /* XXX known by hal */ -}; - -static ctl_table ath_static_sysctls[] = { -#ifdef AR_DEBUG - { .ctl_name = CTL_AUTO, - .procname = "debug", - .mode = 0644, - .data = &ath_debug, - .maxlen = sizeof(ath_debug), - .proc_handler = proc_dointvec - }, -#endif - { .ctl_name = CTL_AUTO, - .procname = "countrycode", - .mode = 0444, - .data = &ath_countrycode, - .maxlen = sizeof(ath_countrycode), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "regdomain", - .mode = 0444, - .data = &ath_regdomain, - .maxlen = sizeof(ath_regdomain), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "outdoor", - .mode = 0444, - .data = &ath_outdoor, - .maxlen = sizeof(ath_outdoor), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "xchanmode", - .mode = 0444, - .data = &ath_xchanmode, - .maxlen = sizeof(ath_xchanmode), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "dwelltime", - .mode = 0644, - .data = &ath_dwelltime, - .maxlen = sizeof(ath_dwelltime), - .extra1 = &mindwelltime, - .extra2 = &maxint, - .proc_handler = proc_dointvec_minmax - }, - { .ctl_name = CTL_AUTO, - .procname = "calibrate", - .mode = 0644, - .data = &ath_calinterval, - .maxlen = sizeof(ath_calinterval), - .extra1 = &mincalibrate, - .extra2 = &maxint, - .proc_handler = proc_dointvec_minmax - }, - { 0 } -}; -static ctl_table ath_ath_table[] = { - { .ctl_name = DEV_ATH, - .procname = "ath", - .mode = 0555, - .child = ath_static_sysctls - }, { 0 } -}; -static ctl_table ath_root_table[] = { - { .ctl_name = CTL_DEV, - .procname = "dev", - .mode = 0555, - .child = ath_ath_table - }, { 0 } -}; -static struct ctl_table_header *ath_sysctl_header; - -void -ath_sysctl_register(void) -{ - static int initialized = 0; - - if (!initialized) { - ath_sysctl_header = register_sysctl_table(ath_root_table); - initialized = 1; - } -} - -void -ath_sysctl_unregister(void) -{ - if (ath_sysctl_header) - unregister_sysctl_table(ath_sysctl_header); -} commit 96a208deb4846346d326359c5bc4ed750245c4af Author: Jiri Slaby Date: Mon Jun 25 14:36:16 2007 +0200 remove empty or unused files diff --git a/Makefile b/Makefile index e71cfe3..bcb2589 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,7 @@ KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) EXTRA_CFLAGS += -I$(src)/openhal ath5k-objs := ath/if_ath_pci.o openhal/ath5k_hw.o \ - openhal/ieee80211_regdomain.o #ath/radar.o #ath/if_ath.o + openhal/ieee80211_regdomain.o obj-m += ath5k.o diff --git a/ath/if_athrate.h b/ath/if_athrate.h deleted file mode 100644 index ff4beaf..0000000 --- a/ath/if_athrate.h +++ /dev/null @@ -1,147 +0,0 @@ -/*- - * Copyright (c) 2004-2005 Sam Leffler, Errno Consulting - * Copyright (c) 2004-2005 Video54 Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD: src/sys/dev/ath/if_athrate.h,v 1.2 2004/12/31 22:41:45 sam Exp $ - */ -#ifndef _ATH_RATECTRL_H_ -#define _ATH_RATECTRL_H_ - -/* - * Interface definitions for transmit rate control modules for the - * Atheros driver. - * - * A rate control module is responsible for choosing the transmit rate - * for each data frame. Management+control frames are always sent at - * a fixed rate. - * - * Only one module may be present at a time; the driver references - * rate control interfaces by symbol name. If multiple modules are - * to be supported we'll need to switch to a registration-based scheme - * as is currently done, for example, for authentication modules. - * - * An instance of the rate control module is attached to each device - * at attach time and detached when the device is destroyed. The module - * may associate data with each device and each node (station). Both - * sets of storage are opaque except for the size of the per-node storage - * which must be provided when the module is attached. - * - * The rate control module is notified for each state transition and - * station association/reassociation. Otherwise it is queried for a - * rate for each outgoing frame and provided status from each transmitted - * frame. Any ancillary processing is the responsibility of the module - * (e.g. if periodic processing is required then the module should setup - * it's own timer). - * - * In addition to the transmit rate for each frame the module must also - * indicate the number of attempts to make at the specified rate. If this - * number is != ATH_TXMAXTRY then an additional callback is made to setup - * additional transmit state. The rate control code is assumed to write - * this additional data directly to the transmit descriptor. - */ -struct ath_softc; -struct ath_node; -struct ath_desc; - -struct ath_ratectrl { - size_t arc_space; /* space required for per-node state */ -}; -/* - * Attach/detach a rate control module. - */ -struct ath_ratectrl *ath_rate_attach(struct ath_softc *); -void ath_rate_detach(struct ath_ratectrl *); - -/* - * Allow rate control module to register dynamic sysctls, after - * dev->name is filled in; Modules are expected to unregister dynamic - * sysctls in ath_rate_detach(). - */ -void ath_rate_dynamic_sysctl_register(struct ath_softc *); - -/* - * State storage handling. - */ -/* - * Initialize per-node state already allocated for the specified - * node; this space can be assumed initialized to zero. - */ -void ath_rate_node_init(struct ath_softc *, struct ath_node *); -/* - * Cleanup any per-node state prior to the node being reclaimed. - */ -void ath_rate_node_cleanup(struct ath_softc *, struct ath_node *); -/* - * Update rate control state on station associate/reassociate - * (when operating as an ap or for nodes discovered when operating - * in ibss mode). - */ -void ath_rate_newassoc(struct ath_softc *, struct ath_node *, - int isNewAssociation); -#ifdef BLE -/* - * Update/reset rate control state for 802.11 state transitions. - * Important mostly as the analog to ath_rate_newassoc when operating - * in station mode. - */ -void ath_rate_newstate(struct ath_softc *, enum ieee80211_state); -#endif -/* - * Transmit handling. - */ -/* - * Return the transmit info for a data packet. If multi-rate state - * is to be setup then try0 should contain a value other than ATH_TXMATRY - * and ath_rate_setupxtxdesc will be called after deciding if the frame - * can be transmitted with multi-rate retry. - */ -void ath_rate_findrate(struct ath_softc *, struct ath_node *, - int shortPreamble, size_t frameLen, - u_int8_t *rix, int *try0, u_int8_t *txrate); -/* - * Setup any extended (multi-rate) descriptor state for a data packet. - * The rate index returned by ath_rate_findrate is passed back in. - */ -void ath_rate_setupxtxdesc(struct ath_softc *, struct ath_node *, - struct ath_desc *, int shortPreamble, u_int8_t rix); -/* - * Update rate control state for a packet associated with the - * supplied transmit descriptor. The routine is invoked both - * for packets that were successfully sent and for those that - * failed (consult the descriptor for details). - */ -void ath_rate_tx_complete(struct ath_softc *, struct ath_node *, - const struct ath_desc *); -#endif /* _ATH_RATECTRL_H_ */ diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 14b5564..0b85915 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -48,7 +48,6 @@ #include "ath5k.h" #include "if_athioctl.h" -#include "if_athrate.h" #define ATH_TIMEOUT 1000 diff --git a/ath/radar.c b/ath/radar.c deleted file mode 100644 index 1da9edf..0000000 --- a/ath/radar.c +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef AUTOCONF_INCLUDED -#include -#endif -#include -#include -#include -#include -#include -#include - -//#include "radar.h" - - -/* - Upon "in-service" radar detection, this code handles the frequency hopping - by finding a new channel where we haven't detected any radar or have not - tried to use for 30 minutes -*/ - -/* 30 minutes */ -#define RADAR_CHANNEL_REUSE_LIMIT (HZ * 60 * 30) - -static void -radar_device_reanimate(unsigned long arg) -{ - struct ieee80211com *ic = (struct ieee80211com *)arg; - struct net_device *dev = ic->ic_dev; - - del_timer(&ic->ic_radar_reanimate); - - printk("%s: reanimating device after radar disturbance\n", dev->name); - ic->ic_init(dev); -} - -void -radar_init(struct ieee80211com *ic) -{ - memset (ic->ic_channelList, 0, sizeof (ic->ic_channelList)); - init_timer(&ic->ic_radar_reanimate); - ic->ic_radar_reanimate.function = radar_device_reanimate; - ic->ic_radar_reanimate.data = (unsigned long) ic; -} - -struct ieee80211_channel * -radar_handle_interference(struct ieee80211com *ic) -{ - struct ieee80211_channel *c; - - int index = 0; - int chan; - u_int32_t firstTimeout = jiffies;; - - /* Mark current channel as having radar on it */ - chan = ic->ic_ibss_chan - ic->ic_channels; - - printk ("%s: Marking channel %d as radar disturbed, time=%lu.\n", __func__, chan, jiffies); - - if (ic->ic_ibss_chan != NULL) - ic->ic_channelList[chan] = jiffies; - - /* Find next appropriate channel */ - while (index < IEEE80211_CHAN_MAX) { - if (!isclr(ic->ic_chan_active, index) && - (ic->ic_channelList[index] == 0 || - (jiffies - ic->ic_channelList[index]) > RADAR_CHANNEL_REUSE_LIMIT)) { - printk ("%s: Hopping to channel %d (%u).\n", - ic->ic_dev->name, index, ic->ic_channelList[index]); - break; - } - /* channel blocked */ - if((ic->ic_channelList[index] != 0) && - (ic->ic_channelList[index] < firstTimeout)){ - firstTimeout = ic->ic_channelList[index]; - } - index ++; - } - if (index == IEEE80211_CHAN_MAX) { - /* No channels are availiable */ - printk("%s: all channels blocked, first timeout=%i\n", - ic->ic_dev->name, firstTimeout + RADAR_CHANNEL_REUSE_LIMIT); - ic->ic_radar_reanimate.expires = firstTimeout + RADAR_CHANNEL_REUSE_LIMIT; - add_timer(&ic->ic_radar_reanimate); - return NULL; - } - c = &ic->ic_channels[index]; - - return c; -} diff --git a/openhal/opt_ah.h b/openhal/opt_ah.h deleted file mode 100644 index e69de29..0000000 commit c33809f844e5aa429e1d6f9c581a0fc7bf965b3c Author: Jiri Slaby Date: Mon Jun 25 14:39:38 2007 +0200 add cscope target to maekfile diff --git a/Makefile b/Makefile index bcb2589..1aec332 100644 --- a/Makefile +++ b/Makefile @@ -14,4 +14,7 @@ all: clean: $(KBUILD) clean -.PHONY: all clean +cscope: + cscope -b `find $(src) -type f -name '*.[ch]'` + +.PHONY: all clean cscope commit dc7a6dfc4fd7ebc75e3a01e3462be9a3ce74dbda Author: Jiri Slaby Date: Mon Jun 25 14:41:27 2007 +0200 i'm the module author diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 6fffdbd..d62bf6f 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1282,7 +1282,7 @@ static void __exit exit_ath_pci(void) module_init(init_ath_pci); module_exit(exit_ath_pci); -MODULE_AUTHOR("Errno Consulting, Sam Leffler"); +MODULE_AUTHOR("Jiri Slaby"); MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); MODULE_LICENSE("Dual BSD/GPL"); commit 50519d604a0638bfa5fe2519b1f45ea147e7a331 Author: Jiri Slaby Date: Mon Jun 25 16:02:02 2007 +0200 setup queues diff --git a/ath/if_ath.c b/ath/if_ath.c index beae81d..44628a9 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -1609,24 +1609,6 @@ ath_updateslot(struct net_device *dev) else ath_setslottime(sc); } -#endif -/* - * Setup a h/w transmit queue for beacons. - */ -static int -ath_beaconq_setup(struct ath_hal *ah) -{ - struct ath5k_txq_info qi; - - memset(&qi, 0, sizeof(qi)); - qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; - /* NB: for dynamic turbo, don't enable any other interrupts */ - qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); -} -#ifdef BLE /* * Setup the transmit queue parameters for the beacon queue. */ @@ -3079,63 +3061,6 @@ rx_next: #undef PA2DESC } -/* - * Setup a h/w transmit queue. - */ -static struct ath_txq * -ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) -{ -#define N(a) (sizeof(a)/sizeof(a[0])) - struct ath_hal *ah = sc->sc_ah; - struct ath5k_txq_info qi; - int qnum; - - memset(&qi, 0, sizeof(qi)); - qi.tqi_subtype = subtype; - qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; - /* - * Enable interrupts only for EOL and DESC conditions. - * We mark tx descriptors to receive a DESC interrupt - * when a tx queue gets deep; otherwise waiting for the - * EOL to reap descriptors. Note that this is done to - * reduce interrupt load and this only defers reaping - * descriptors, never transmitting frames. Aside from - * reducing interrupts this also permits more concurrency. - * The only potential downside is if the tx queue backs - * up in which case the top half of the kernel may backup - * due to a lack of tx descriptors. - */ - qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); - if (qnum == -1) { - /* - * NB: don't print a message, this happens - * normally on parts with too few tx queues - */ - return NULL; - } - if (qnum >= N(sc->sc_txq)) { - printk("%s: hal qnum %u out of range, max %u!\n", - "BLE"/*sc->sc_dev->name*/, qnum, (unsigned int) N(sc->sc_txq)); - ath5k_hw_release_tx_queue(ah, qnum); - return NULL; - } - if (!ATH_TXQ_SETUP(sc, qnum)) { - struct ath_txq *txq = &sc->sc_txq[qnum]; - - txq->axq_qnum = qnum; - txq->axq_depth = 0; - txq->axq_intrcnt = 0; - txq->axq_link = NULL; -// STAILQ_INIT(&txq->axq_q); - ATH_TXQ_LOCK_INIT(sc, txq); - sc->sc_txqsetup |= 1<sc_txq[qnum]; -#undef N -} #ifdef BLE /* * Setup a hardware data transmit queue for the specified @@ -3211,34 +3136,7 @@ ath_wme_update(struct ieee80211com *ic) !ath_txq_update(sc, WME_AC_VI) || !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; } -#endif -/* - * Reclaim resources for a setup queue. - */ -static void -ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) -{ - ath5k_hw_release_tx_queue(sc->sc_ah, txq->axq_qnum); - ATH_TXQ_LOCK_DESTROY(txq); - sc->sc_txqsetup &= ~(1<axq_qnum); -} -/* - * Reclaim all tx queue resources. - */ -static void -ath_tx_cleanup(struct ath_softc *sc) -{ - int i; - - ATH_LOCK_DESTROY(sc); - ATH_TXBUF_LOCK_DESTROY(sc); - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) { - if (ATH_TXQ_SETUP(sc, i)) - ath_tx_cleanupq(sc, &sc->sc_txq[i]); - } -} -#ifdef BLE static int ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf *bf, struct sk_buff *skb) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index d62bf6f..6faf778 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -573,6 +573,85 @@ static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) sc->bufptr = NULL; } +static int ath_beaconq_setup(struct ath_hw *ah) +{ + struct ath5k_txq_info qi; + + memset(&qi, 0, sizeof(qi)); + qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; + /* NB: for dynamic turbo, don't enable any other interrupts */ + qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + + return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); +} + +static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, + int subtype) +{ + struct ath_hw *ah = sc->ah; + struct ath5k_txq_info qi; + int qnum; + + memset(&qi, 0, sizeof(qi)); + qi.tqi_subtype = subtype; + qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; + /* + * Enable interrupts only for EOL and DESC conditions. + * We mark tx descriptors to receive a DESC interrupt + * when a tx queue gets deep; otherwise waiting for the + * EOL to reap descriptors. Note that this is done to + * reduce interrupt load and this only defers reaping + * descriptors, never transmitting frames. Aside from + * reducing interrupts this also permits more concurrency. + * The only potential downside is if the tx queue backs + * up in which case the top half of the kernel may backup + * due to a lack of tx descriptors. + */ + qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | + AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); + if (qnum < 0) { + /* + * NB: don't print a message, this happens + * normally on parts with too few tx queues + */ + return ERR_PTR(qnum); + } + if (qnum >= ARRAY_SIZE(sc->txq)) { + printk(KERN_ERR "hal qnum %u out of range, max %u!\n", + qnum, ARRAY_SIZE(sc->txq)); + ath5k_hw_release_tx_queue(ah, qnum); + return ERR_PTR(-EINVAL); + } + if (!test_bit(qnum, sc->txqsetup)) { + struct ath_txq *txq = &sc->txq[qnum]; + + txq->axq_qnum = qnum; + txq->axq_depth = 0; + txq->axq_intrcnt = 0; + txq->axq_link = NULL; + INIT_LIST_HEAD(&txq->axq_q); + spin_lock_init(&txq->axq_lock); + set_bit(qnum, sc->txqsetup); + } + return &sc->txq[qnum]; +} + +static void ath_tx_cleanup(struct ath_softc *sc) +{ + unsigned int i; + + for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) + if (test_bit(i, sc->txqsetup)) { + ath5k_hw_release_tx_queue(sc->ah, sc->txq[i].axq_qnum); + clear_bit(i, sc->txqsetup); + } +} + static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; @@ -642,7 +721,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) dev_err(&pdev->dev, "can't allocate descriptors\n"); goto err; } -#ifdef BLE /* * Allocate hardware transmit queues: one queue for @@ -652,18 +730,22 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) * * XXX PS-Poll */ - sc->sc_bhalq = ath_beaconq_setup(ah); - if (sc->sc_bhalq == (u_int) -1) { - printk(KERN_ERR "unable to setup a beacon xmit queue!\n"); - goto bad2; + ret = ath_beaconq_setup(ah); + if (ret < 0) { + dev_err(&pdev->dev, "can't setup a beacon xmit queue\n"); + goto err_desc; } - sc->sc_cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); - if (sc->sc_cabq == NULL) { - printk(KERN_ERR "unable to setup CAB xmit queue!\n"); - error = EIO; - goto bad2; + sc->bhalq = ret; + + sc->cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); + if (IS_ERR(sc->cabq)) { + dev_err(&pdev->dev, "can't setup CAB xmit queue\n"); + ret = PTR_ERR(sc->cabq); + sc->cabq = NULL; + goto err_queues; } +#ifdef BLE /* NB: insure BK queue is the lowest priority h/w queue */ if (!ath_tx_setup(sc, WME_AC_BK, AR5K_WME_AC_BK)) { printk(KERN_ERR "unable to setup xmit queue for %s traffic!\n", @@ -911,9 +993,11 @@ bad2: if (sc->sc_txq[WME_AC_VO].axq_qnum != (u_int) -1) { ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VO]); } - ath_tx_cleanup(sc); - ath_desc_free(sc); #endif +err_queues: + ath_tx_cleanup(sc); +err_desc: + ath_desc_free(sc, pdev); err: return ret; } @@ -938,7 +1022,7 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) // ieee80211_ifdetach(ic); // ath_rate_detach(sc->sc_rc); ath_desc_free(sc, pdev); -// ath_tx_cleanup(sc); + ath_tx_cleanup(sc); /* * NB: can't reclaim these until after ieee80211_ifdetach diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 0b85915..fce6a97 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -290,25 +290,23 @@ struct ath_softc { #endif struct list_head txbuf; /* transmit buffer */ spinlock_t txbuflock; /* txbuf lock */ + struct ath_txq txq[AR5K_NUM_TX_QUEUES]; + DECLARE_BITMAP(txqsetup, AR5K_NUM_TX_QUEUES); /* h/w queues setup */ #ifdef BLE int sc_tx_timer; /* transmit timeout */ - u_int sc_txqsetup; /* h/w queues setup */ u_int sc_txintrperiod;/* tx interrupt batching */ - struct ath_txq sc_txq[AR5K_NUM_TX_QUEUES]; struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ #endif struct tasklet_struct txtq; /* tx intr tasklet */ struct list_head bbuf; /* beacon buffers */ + unsigned int bhalq; /* HAL q for outgoing beacons */ #ifdef BLE - u_int sc_bhalq; /* HAL q for outgoing beacons */ u_int sc_bmisscount; /* missed beacon transmits */ u32 sc_ant_tx[8]; /* recent tx frames/antenna */ - struct ath_txq *sc_cabq; /* tx q for cab frames */ -#ifdef BLE struct ieee80211_beacon_offsets boff; /* dynamic update state */ #endif -#endif + struct ath_txq *cabq; /* tx q for cab frames */ struct tasklet_struct bmisstq; /* bmiss intr tasklet */ #ifdef BLE struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ @@ -326,12 +324,10 @@ struct ath_softc { #endif }; -#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<sc_txbuflock) +/*#define ATH_TXBUF_LOCK(_sc) spin_lock(&(_sc)->sc_txbuflock) #define ATH_TXBUF_UNLOCK(_sc) spin_unlock(&(_sc)->sc_txbuflock) #define ATH_TXBUF_LOCK_BH(_sc) spin_lock_bh(&(_sc)->sc_txbuflock) -#define ATH_TXBUF_UNLOCK_BH(_sc) spin_unlock_bh(&(_sc)->sc_txbuflock) +#define ATH_TXBUF_UNLOCK_BH(_sc) spin_unlock_bh(&(_sc)->sc_txbuflock)*/ #define ATH_TXBUF_LOCK_ASSERT(_sc) \ KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), "txbuf not locked!") diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 54c1a78..4364949 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -1068,9 +1068,9 @@ bool ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval * bool ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); /* Queue Control Unit, DFS Control Unit Functions */ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); -bool ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); +int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); bool ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); -bool ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); +void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); bool ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 660c295..56761ca 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -3326,11 +3326,12 @@ Queue Control Unit, DFS Control Unit Functions /* * Initialize a transmit queue */ -int -ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, - struct ath5k_txq_info *queue_info) +int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, + struct ath5k_txq_info *queue_info) { unsigned int queue; + int ret; + AR5K_TRACE; /* @@ -3347,7 +3348,7 @@ ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; break; default: - return -1; + return -EINVAL; } } else { switch (queue_type) { @@ -3357,7 +3358,7 @@ ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, AR5K_TX_QUEUE_INACTIVE; queue++) { if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) - return -1; + return -EINVAL; } break; case AR5K_TX_QUEUE_UAPSD: @@ -3371,11 +3372,12 @@ ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, break; case AR5K_TX_QUEUE_XR_DATA: if (hal->ah_version != AR5K_AR5212) - AR5K_PRINTF("XR data queues only supported in 5212!"); + AR5K_PRINTF("XR data queues only " + "supported in 5212!"); queue = AR5K_TX_QUEUE_ID_XR_DATA; break; default: - return -1; + return -EINVAL; } } @@ -3387,9 +3389,9 @@ ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, if (queue_info != NULL) { queue_info->tqi_type = queue_type; - if (ath5k_hw_setup_tx_queueprops(hal, queue, queue_info) - != true) - return -1; + ret = ath5k_hw_setup_tx_queueprops(hal, queue, queue_info); + if (ret) + return ret; } /* * We use ah_txq_interrupts to hold a temp value for @@ -3404,27 +3406,25 @@ ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, /* * Setup a transmit queue */ -bool -ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, +int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return false; + return -EIO; memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); /*XXX: Is this supported on 5210 ?*/ if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && - ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || - (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || - queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) - hal->ah_txq[queue].tqi_flags |= - AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; + ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || + (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || + queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) + hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - return true; + return 0; } /* @@ -3441,18 +3441,18 @@ ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info /* * Set a transmit queue inactive */ -bool -ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) +void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) { AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + if (queue >= hal->ah_capabilities.cap_queues.q_tx_num) { + WARN_ON(1); + return; + } /* This queue will be skipped in further operations */ hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; /*For SIMR setup*/ AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - - return false; /*???*/ } /* commit c42b2eb9711d74c467f30dc022bd2ffd64b54b1f Author: Jiri Slaby Date: Wed Jun 27 20:41:10 2007 +0200 register_hw, ops are empty routines so far diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 6faf778..b2fcefe 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -109,22 +109,54 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = { }; MODULE_DEVICE_TABLE(pci, ath_pci_id_table); +static int ath_open(struct ieee80211_hw *hw) +{ + printk("%s\n", __FUNCTION__); + return 0; +} + +static int ath_stop(struct ieee80211_hw *hw) +{ + printk("%s\n", __FUNCTION__); + return 0; +} + +static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) +{ + printk("%s\n", __FUNCTION__); + return 0; +} + +static int ath_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) +{ + printk("%s\n", __FUNCTION__); + return 0; +} + +static int ath_conf_tx(struct ieee80211_hw *hw, int queue, + const struct ieee80211_tx_queue_params *params) +{ + printk("%s\n", __FUNCTION__); + return 0; +} + static struct ieee80211_ops ath_hw_ops = { -/* .tx = d_tx, - .open = d_open, - .stop = d_stop, - .add_interface = d_add_interface, - .remove_interface = d_remove_interface, - .config = d_config, - .config_interface = d_config_interface, - .set_key = d_set_key, - .get_stats = d_get_stats, - .get_tx_stats = d_get_tx_stats, - .conf_tx = d_conf_tx, - .get_tsf = d_get_tsf, - .reset_tsf = d_reset_tsf, - .beacon_update = d_beacon_update, - .hw_scan = d_hw_scan*/ + .tx = NULL, + .reset = NULL, + .open = ath_open, + .stop = ath_stop, + .add_interface = NULL, + .remove_interface = NULL, + .config = ath_config, + .config_interface = NULL, + .set_key = NULL, + .hw_scan = ath_hw_scan, + .get_stats = NULL, + .conf_tx = ath_conf_tx, +/* .get_tx_stats = , + .get_tsf = , + .reset_tsf = , + .beacon_update = ,*/ }; static irqreturn_t ath_intr(int irq, void *dev_id) @@ -656,6 +688,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; struct ath_hw *ah = sc->ah; + u8 mac[ETH_ALEN]; unsigned int i; int ret; @@ -808,7 +841,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) sc->blinking = 0; sc->ledstate = 1; sc->ledon = 0; /* low true */ - sc->ledidle = (2700*HZ)/1000; /* 2.7sec */ + sc->ledidle = msecs_to_jiffies(2700); /* 2.7sec */ setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); /* @@ -823,104 +856,8 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); } - ether_setup(dev); - dev->open = ath_init; - dev->stop = ath_stop; - dev->hard_start_xmit = ath_start; - dev->tx_timeout = ath_tx_timeout; - dev->watchdog_timeo = 5 * HZ; /* XXX */ - dev->set_multicast_list = ath_mode_init; - dev->do_ioctl = ath_ioctl; - dev->get_stats = ath_getstats; - dev->set_mac_address = ath_set_mac_address; - dev->change_mtu = &ath_change_mtu; - dev->tx_queue_len = ATH_TXBUF; /* TODO? 1 for mgmt frame */ -/*get_wireless_stats moved from net_device to iw_handler_def*/ -# if IW_HANDLER_VERSION < 7 - dev->get_wireless_stats = ath_iw_getstats; -# endif - ieee80211_ioctl_iwsetup(&ath_iw_handler_def); - dev->wireless_handlers = &ath_iw_handler_def; -#if IEEE80211_VLAN_TAG_USED - dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; - dev->vlan_rx_register = ath_vlan_register; - dev->vlan_rx_kill_vid = ath_vlan_kill_vid; -#endif /* IEEE80211_VLAN_TAG_USED */ - ic->ic_dev = dev; - ic->ic_devstats = &sc->sc_devstats; - ic->ic_init = ath_init; - ic->ic_reset = ath_reset; - ic->ic_newassoc = ath_newassoc; - ic->ic_updateslot = ath_updateslot; - ic->ic_wme.wme_update = ath_wme_update; - /* XXX not right but it's not used anywhere important */ - ic->ic_phytype = MODULATION_OFDM; - ic->ic_opmode = IEEE80211_M_STA; - ic->ic_caps = - IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ - | IEEE80211_C_AHDEMO /* adhoc demo (pseudo_ibss) mode */ - | IEEE80211_C_HOSTAP /* hostap mode */ - | IEEE80211_C_MONITOR /* monitor mode */ - | IEEE80211_C_SHPREAMBLE /* short preamble supported */ - | IEEE80211_C_SHSLOT /* short slot time supported */ - | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ - ; - /* - * initialize management queue - */ - skb_queue_head_init(&ic->ic_mgtq); - - /* - * Query the hal to figure out h/w crypto support. - */ - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_WEP)) - ic->ic_caps |= IEEE80211_C_WEP; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_AES_OCB)) - ic->ic_caps |= IEEE80211_C_AES; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_AES_CCM)) - ic->ic_caps |= IEEE80211_C_AES_CCM; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_CKIP)) - ic->ic_caps |= IEEE80211_C_CKIP; - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_TKIP)) { - ic->ic_caps |= IEEE80211_C_TKIP; - /* - * Check if h/w does the MIC and/or whether the - * separate key cache entries are required to - * handle both tx+rx MIC keys. - */ - if (ath_hal_ciphersupported(ah, AR5K_CIPHER_MIC)) - ic->ic_caps |= IEEE80211_C_TKIPMIC; - if (ath_hal_tkipsplit(ah)) - sc->sc_splitmic = 1; - } sc->sc_hasclrkey = ath_hal_ciphersupported(ah, AR5K_CIPHER_CLR); sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); - /* - * TPC support can be done either with a global cap or - * per-packet support. The latter is not available on - * all parts. We're a bit pedantic here as all parts - * support a global cap. - */ - if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) - ic->ic_caps |= IEEE80211_C_TXPMGT; - - /* - * Mark WME capability only if we have sufficient - * hardware queues to do proper priority scheduling. - */ - if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) - ic->ic_caps |= IEEE80211_C_WME; - /* - * Check for misc other capabilities. - */ - if (ath_hal_hasbursting(ah)) - ic->ic_caps |= IEEE80211_C_BURST; - - /* - * Indicate we need the 802.11 header padded to a - * 32-bit boundary for 4-address and QoS frames. - */ - ic->ic_flags |= IEEE80211_F_DATAPAD; /* * Query the hal about antenna support. @@ -934,66 +871,21 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) sc->sc_hasveol = ath_hal_hasveol(ah); sc->sc_rxfilter = 0; +#endif - /* get mac address from hardware */ -// ath_hal_getmac(ah, ic->ic_myaddr); BLEE -// IEEE80211_ADDR_COPY(dev->dev_addr, ic->ic_myaddr); - - /* call MI attach routine. */ - ieee80211_ifattach(ic); - /* override default methods */ - ic->ic_node_alloc = ath_node_alloc; - sc->sc_node_free = ic->ic_node_free; - ic->ic_node_free = ath_node_free; - ic->ic_node_getrssi = ath_node_getrssi; - sc->sc_recv_mgmt = ic->ic_recv_mgmt; - ic->ic_recv_mgmt = ath_recv_mgmt; - sc->sc_newstate = ic->ic_newstate; - ic->ic_newstate = ath_newstate; - ic->ic_crypto.cs_key_alloc = ath_key_alloc; - ic->ic_crypto.cs_key_delete = ath_key_delete; - ic->ic_crypto.cs_key_set = ath_key_set; - ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; - ic->ic_crypto.cs_key_update_end = ath_key_update_end; - - radar_init(ic); - - /* complete initialization */ - ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); - - if (register_netdev(dev)) { - printk(KERN_ERR "%s: unable to register device\n", dev->name); - goto bad3; + ath5k_hw_get_lladdr(ah, mac); + SET_IEEE80211_PERM_ADDR(hw, mac); + + ret = ieee80211_register_hw(hw); + if (ret) { + dev_err(&pdev->dev, "can't register ieee80211 hw\n"); + goto err_queues; } - /* - * Attach dynamic MIB vars and announce support - * now that we have a device name with unit number. - */ - ath_dynamic_sysctl_register(sc); - ath_rate_dynamic_sysctl_register(sc); - ath_announce(sc); -#endif +// ath_dynamic_sysctl_register(sc); +// ath_announce(sc); return 0; -#ifdef BLE -//bad3: -// ieee80211_ifdetach(ic); -// ath_rate_detach(sc->sc_rc); -bad2: - if (sc->sc_txq[WME_AC_BK].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_BK]); - } - if (sc->sc_txq[WME_AC_BE].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_BE]); - } - if (sc->sc_txq[WME_AC_VI].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VI]); - } - if (sc->sc_txq[WME_AC_VO].axq_qnum != (u_int) -1) { - ATH_TXQ_LOCK_DESTROY(&sc->sc_txq[WME_AC_VO]); - } -#endif err_queues: ath_tx_cleanup(sc); err_desc: @@ -1019,8 +911,7 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) * it last * Other than that, it's straightforward... */ -// ieee80211_ifdetach(ic); -// ath_rate_detach(sc->sc_rc); + ieee80211_unregister_hw(hw); ath_desc_free(sc, pdev); ath_tx_cleanup(sc); @@ -1030,7 +921,6 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) * state and potentially want to use them. */ // ath_dynamic_sysctl_unregister(sc); -// unregister_netdev(dev); } static const char *ath_chip_name(u8 mac_version) @@ -1158,7 +1048,10 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, if (ret) goto err_ah; - dev_info(&pdev->dev, "%s chip found\n", ath_chip_name(id->driver_data)); + dev_info(&pdev->dev, "%s chip found: mac %d.%d phy %d.%d\n", + ath_chip_name(id->driver_data), sc->ah->ah_mac_version, + sc->ah->ah_mac_version, sc->ah->ah_phy_revision >> 4, + sc->ah->ah_phy_revision & 0xf); /* ready to process interrupts */ sc->invalid = 0; diff --git a/ath/if_athvar.h b/ath/if_athvar.h index fce6a97..c58286c 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -335,8 +335,6 @@ int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); void ath_sysctl_unregister(void); -#define ath_hal_ciphersupported(_ah, _cipher) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_CIPHER, _cipher, NULL) == 0) #define ath_hal_getcountrycode(_ah, _pcc) \ (*(_pcc) = (_ah)->ah_country_code) #define ath_hal_tkipsplit(_ah) \ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 4364949..8339bfc 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -825,7 +825,6 @@ enum ath5k_power_mode { */ enum ath5k_capability_type { AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ - AR5K_CAP_CIPHER = 1, /* Can handle encryption */ AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 56761ca..34133a1 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -2353,7 +2353,7 @@ static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) int octet, ret; memset(mac, 0, ETH_ALEN); - memset(&mac_d, 0, ETH_ALEN); + memset(mac_d, 0, ETH_ALEN); ret = ath5k_hw_eeprom_read(hal, 0x20, &data); if (ret) @@ -5840,13 +5840,6 @@ int ath5k_hw_get_capability(struct ath_hw *hal, *result = ath5k_get_regdomain(hal); goto yes; } - case AR5K_CAP_CIPHER: - switch (capability) { - case AR5K_CIPHER_WEP: - goto yes; - default: - goto no; - } case AR5K_CAP_NUM_TXQUEUES: if (result) { if (hal->ah_version == AR5K_AR5210) commit c95f835dea4e38b428cca7b61bcd8f28f932d4dc Author: Jiri Slaby Date: Sun Jul 1 11:28:19 2007 +0200 start, stop, config and empty tx diff --git a/ath/if_ath.c b/ath/if_ath.c index 44628a9..0ba0492 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -1,9 +1,3 @@ -/* - * #define AR_DEBUG here if you need to debug the ath_pci module (athdebug) - * disable this if not needed because it adds an amount of load - */ -#define AR_DEBUG - /* unaligned little endian access */ #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) @@ -198,230 +192,6 @@ ath_bmiss_tasklet(unsigned long data) } #endif } -#ifdef BLE -static u_int -ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) -{ -#define N(a) (sizeof(a) / sizeof(a[0])) - static const u_int modeflags[] = { - 0, /* IEEE80211_MODE_AUTO */ - CHANNEL_A, /* IEEE80211_MODE_11A */ - CHANNEL_B, /* IEEE80211_MODE_11B */ - CHANNEL_G, /* IEEE80211_MODE_11G */ - 0, /* IEEE80211_MODE_FH */ - CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ - CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ - }; - enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); - - KASSERT(mode < N(modeflags), "unexpected phy mode %u", mode); - KASSERT(modeflags[mode] != 0, "mode %u undefined", mode); - return modeflags[mode]; -#undef N -} -#endif -static int -ath_init(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; - enum ath5k_status status; - int error = 0; - - ATH_LOCK(sc); - -// DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, ic->ic_opmode); - - /* - * Stop anything previously setup. This is safe - * whether this is the first time through or not. - */ - ath_stop_locked(hw); -#ifdef BLE - /* - * Change our interface type if we are in monitor mode. - */ - dev->type = (ic->ic_opmode == IEEE80211_M_MONITOR) ? - ARPHRD_IEEE80211_RADIOTAP : ARPHRD_ETHER; - - /* - * The basic interface to setting the hardware in a good - * state is ``reset''. On return the hardware is known to - * be powered up and with interrupts disabled. This must - * be followed by initialization of the appropriate bits - * and then setup of the interrupt mask. - */ - sc->sc_curchan.freq = ic->ic_ibss_chan->ic_freq; - sc->sc_curchan.channel_flags = ath_chan2flags(ic, ic->ic_ibss_chan); -#endif - if (!ath5k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, false, - &status)) { - printk(KERN_ERR "unable to reset hardware; hal status %u\n", - status); - error = -EIO; - goto done; - } - /* - * This is needed only to setup initial state - * but it's best done after a reset. - */ - ath_update_txpow(sc); - - /* - * Likewise this is set during reset so update - * state cached in the driver. - */ - sc->sc_diversity = ath_hal_getdiversity(ah); - - /* - * Setup the hardware after reset: the key cache - * is filled as needed and the receive engine is - * set going. Frame transmit is handled entirely - * in the frame output path; there's nothing to do - * here except setup the interrupt mask. - */ - if (ath_startrecv(sc) != 0) { - printk(KERN_ERR "unable to start recv logic\n"); - error = -EIO; - goto done; - } - - /* - * Enable interrupts. - */ - sc->sc_imask = AR5K_INT_RX | AR5K_INT_TX - | AR5K_INT_RXEOL | AR5K_INT_RXORN - | AR5K_INT_FATAL | AR5K_INT_GLOBAL; // TODO: compiler warning integer overflow in expression -#ifdef BLE - /* - * Enable MIB interrupts when there are hardware phy counters. - * Note we only do this (at the moment) for station mode. - */ - if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) - sc->sc_imask |= AR5K_INT_MIB; - ath5k_hw_set_intr(ah, sc->sc_imask); - - dev->flags |= IFF_RUNNING; - ic->ic_state = IEEE80211_S_INIT; - - /* - * The hardware should be ready to go now so it's safe - * to kick the 802.11 state machine as it's likely to - * immediately call back to us to send mgmt frames. - */ - ni = ic->ic_bss; - ni->ni_chan = ic->ic_ibss_chan; - ath_chan_change(sc, ni->ni_chan); - if (ic->ic_opmode != IEEE80211_M_MONITOR) { - if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) - ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); - } else - ieee80211_new_state(ic, IEEE80211_S_RUN, -1); -#endif -done: - ATH_UNLOCK(sc); - return error; -} - -static int -ath_stop_locked(struct ieee80211_hw *hw) -{ -#ifdef BLE - struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", - __func__, sc->sc_invalid); - - ATH_LOCK_ASSERT(sc); - if (dev->flags & IFF_RUNNING) { - /* - * Shutdown the hardware and driver: - * reset 802.11 state machine - * stop output from above - * disable interrupts - * turn off timers - * turn off the radio - * clear transmit machinery - * clear receive machinery - * drain and release tx queues - * reclaim beacon resources - * power down hardware - * - * Note that some of this work is not possible if the - * hardware is gone (invalid). - */ -// ieee80211_new_state(ic, IEEE80211_S_INIT, -1); -// netif_stop_queue(dev); -// if (sc->sc_rawdev_enabled) -// netif_stop_queue(&sc->sc_rawdev); - - dev->flags &= ~IFF_RUNNING; - if (!sc->sc_invalid) { - if (sc->sc_softled) { - del_timer(&sc->sc_ledtimer); - ath5k_hw_set_gpio(ah, sc->sc_ledpin, - !sc->sc_ledon); - sc->sc_blinking = 0; - } - ath5k_hw_set_intr(ah, 0); - } - ath_draintxq(sc); - if (!sc->sc_invalid) { - ath_stoprecv(sc); - ath5k_hw_phy_disable(ah); - } else - sc->sc_rxlink = NULL; - ath_beacon_free(sc); - } -#endif - return 0; -} - -/* - * Stop the device, grabbing the top-level lock to protect - * against concurrent entry through ath_init (which can happen - * if another thread does a system call and the thread doing the - * stop is preempted). - */ -static int -ath_stop(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - int error; - - ATH_LOCK(sc); - error = ath_stop_locked(hw); - if (error == 0 && !sc->sc_invalid) { - /* - * Set the chip in full sleep mode. Note that we are - * careful to do this only when bringing the interface - * completely to a stop. When the chip is in this state - * it must be carefully woken up or references to - * registers in the PCI clock domain may freeze the bus - * (and system). This varies by chip and is mostly an - * issue with newer parts that go to sleep more quickly. - */ - if (sc->sc_ah->ah_mac_version >= 7 && sc->sc_ah->ah_mac_revision >= 8) { - /* - * XXX - * don't put newer MAC revisions > 7.8 to sleep because - * of the above mentioned problems - */ - DPRINTF(sc, ATH_DEBUG_RESET, - "%s: mac version > 7.8, not putting device to sleep\n", - __func__); - } - else { - DPRINTF(sc, ATH_DEBUG_RESET, - "%s: putting device to full sleep\n", __func__); - ath5k_hw_set_power(sc->sc_ah, AR5K_PM_FULL_SLEEP, - true, 0); - } - } - ATH_UNLOCK(sc); - return error; -} /* * Reset the hardware w/o losing operational state. This is @@ -1467,103 +1237,7 @@ ath_key_update_end(struct ieee80211com *ic) #endif } -/* - * Calculate the receive filter according to the - * operating mode and state: - * - * o always accept unicast, broadcast, and multicast traffic - * o maintain current state of phy error reception (the hal - * may enable phy error frames for noise immunity work) - * o probe request frames are accepted only when operating in - * hostap, adhoc, or monitor modes - * o enable promiscuous mode according to the interface state - * o accept beacons: - * - when operating in adhoc mode so the 802.11 layer creates - * node table entries for peers, - * - when operating in station mode for collecting rssi data when - * the station is otherwise quiet, or - * - when scanning - * o accept any additional packets specified by sc_rxfilter - */ -static u_int32_t -ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) -{ - struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah = sc->sc_ah; - struct net_device *dev = ic->ic_dev; - u_int32_t rfilt; - - rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERROR) - | AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_PHYRADAR; - if (ic->ic_opmode != IEEE80211_M_STA && - ic->ic_opmode != IEEE80211_M_AHDEMO) - rfilt |= AR5K_RX_FILTER_PROBEREQ; - if (ic->ic_opmode != IEEE80211_M_HOSTAP && - (dev->flags & IFF_PROMISC)) - rfilt |= AR5K_RX_FILTER_PROM; - if (ic->ic_opmode == IEEE80211_M_STA || - ic->ic_opmode == IEEE80211_M_IBSS || - state == IEEE80211_S_SCAN) - rfilt |= AR5K_RX_FILTER_BEACON; - - if (sc->sc_rawdev_enabled && (sc->sc_rawdev.flags & IFF_UP)) { - /* if the rawdev is up, accept all normal packets */ - rfilt |= (AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROM | - AR5K_RX_FILTER_PROBEREQ); - } - - rfilt |= sc->sc_rxfilter; - - return rfilt; -} - -static void -ath_mode_init(struct net_device *dev) -{ - struct ath_softc *sc = dev->priv; -// struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah = sc->sc_ah; - u_int32_t rfilt, mfilt[2], val; - u_int8_t pos; - struct dev_mc_list *mc; - /* configure rx filter */ -// rfilt = ath_calcrxfilter(sc, ic->ic_state); -// ath5k_hw_set_rx_filter(ah, rfilt); - - /* configure operational mode */ - ath5k_hw_set_opmode(ah); - - /* - * Handle any link-level address change. Note that we only - * need to force ic_myaddr; any other addresses are handled - * as a byproduct of the ifnet code marking the interface - * down then up. - * - * XXX should get from lladdr instead of arpcom but that's more work - */ -// IEEE80211_ADDR_COPY(ic->ic_myaddr, dev->dev_addr); - ath5k_hw_set_lladdr(ah, dev->dev_addr); - - /* calculate and install multicast filter */ - if ((dev->flags & IFF_ALLMULTI) == 0) { - mfilt[0] = mfilt[1] = 0; - for (mc = dev->mc_list; mc; mc = mc->next) { - /* calculate XOR of eight 6bit values */ - val = LE_READ_4(mc->dmi_addr + 0); - pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; - val = LE_READ_4(mc->dmi_addr + 3); - pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; - pos &= 0x3f; - mfilt[pos / 32] |= (1 << (pos % 32)); - } - } else { - mfilt[0] = mfilt[1] = ~0; - } - ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); - DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", - __func__, rfilt, mfilt[0], mfilt[1]); -} #endif /* * Set the slot time based on the current setting. @@ -2222,113 +1896,6 @@ ath_node_getrssi(const struct ieee80211_node *ni) } #endif -static int -ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) -{ - struct ath_hal *ah = sc->sc_ah; - struct sk_buff *skb; - struct ath_desc *ds; - int headroom_needed = 0; - - if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { - headroom_needed = sizeof(struct wlan_ng_prism2_header); - } -#ifdef BLE - else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_PRISM) { - headroom_needed = sizeof(struct wlan_ng_prism2_header); - } else if (sc->sc_rawdev.type == ARPHRD_IEEE80211_RADIOTAP) { - headroom_needed = sizeof(struct ath_rx_radiotap_header); - } -#endif - - /* - * Check if we have enough headroom. If not, just free the skb - * and we'll alloc another one below. - */ - if (bf->bf_skb && skb_headroom(bf->bf_skb) < headroom_needed) { - bus_unmap_single(sc->sc_bdev, - bf->bf_skbaddr, sc->sc_rxbufsize, - BUS_DMA_FROMDEVICE); - dev_kfree_skb(bf->bf_skb); - bf->bf_skb = NULL; - } - - skb = bf->bf_skb; - - if (skb == NULL) { - u_int off; - - /* - * Allocate buffer with headroom_needed space for the - * fake physical layer header at the start. - */ - skb = dev_alloc_skb(sc->sc_rxbufsize + - headroom_needed + - sc->sc_cachelsz - 1); - if (skb == NULL) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: skbuff alloc of size %d failed\n", - __func__, - (int)(sc->sc_rxbufsize - + headroom_needed - + sc->sc_cachelsz - 1)); - sc->sc_stats.ast_rx_nobuf++; - return ENOMEM; - } - /* - * Reserve space for the fake physical layer header. - */ - skb_reserve(skb, headroom_needed); - /* - * Cache-line-align. This is important (for the - * 5210 at least) as not doing so causes bogus data - * in rx'd frames. - */ - off = ((unsigned long) skb->data) % sc->sc_cachelsz; - if (off != 0) - skb_reserve(skb, sc->sc_cachelsz - off); - -// skb->dev = sc->sc_dev; - bf->bf_skb = skb; - bf->bf_skbaddr = bus_map_single(sc->sc_bdev, - skb->data, sc->sc_rxbufsize, BUS_DMA_FROMDEVICE); - if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { - printk(KERN_ERR "%s: DMA mapping failed\n", __func__); - dev_kfree_skb(skb); - bf->bf_skb = NULL; - sc->sc_stats.ast_rx_busdma++; - return ENOMEM; - } - } - - /* - * Setup descriptors. For receive we always terminate - * the descriptor list with a self-linked entry so we'll - * not get overrun under high load (as can happen with a - * 5212 when ANI processing enables PHY error frames). - * - * To insure the last descriptor is self-linked we create - * each descriptor as self-linked and add it to the end. As - * each additional descriptor is added the previous self-linked - * entry is ``fixed'' naturally. This should be safe even - * if DMA is happening. When processing RX interrupts we - * never remove/process the last, self-linked, entry on the - * descriptor list. This insures the hardware always has - * someplace to write a new frame. - */ - ds = bf->bf_desc; - ds->ds_link = bf->bf_daddr; /* link to self */ - ds->ds_data = bf->bf_skbaddr; - ath5k_hw_setup_rx_desc(ah, ds, - skb_tailroom(skb), /* buffer size */ - 0); - - if (sc->sc_rxlink != NULL) - *sc->sc_rxlink = bf->bf_daddr; - sc->sc_rxlink = &ds->ds_link; - return 0; -} - #ifdef BLE /* * Add additional headers to a transmitted frame and netif_rx it on @@ -3840,297 +3407,8 @@ ath_tx_timeout(struct net_device *dev) ath_init(dev); } -static void -ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) -{ -#ifdef AR_DEBUG - struct ath_hal *ah = sc->sc_ah; -#endif - struct ath_buf *bf; - - /* - * NB: this assumes output has been stopped and - * we do not need to block ath_tx_tasklet - */ - for (;;) { - ATH_TXQ_LOCK_BH(txq); -// bf = STAILQ_FIRST(&txq->axq_q); - bf = NULL; - if (bf == NULL) { - txq->axq_link = NULL; - ATH_TXQ_UNLOCK_BH(txq); - break; - } -// ATH_TXQ_REMOVE_HEAD(txq, bf_list); - ATH_TXQ_UNLOCK_BH(txq); -#ifdef AR_DEBUG - if (sc->sc_debug & ATH_DEBUG_RESET) - ath_printtxbuf(bf, ah->ah_proc_tx_desc(ah, - bf->bf_desc) == AR5K_OK); -#endif /* AR_DEBUG */ - bus_unmap_single(sc->sc_bdev, - bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); - dev_kfree_skb(bf->bf_skb); - bf->bf_skb = NULL; -#ifdef BLE - ni = bf->bf_node; - bf->bf_node = NULL; - if (ni != NULL) { - /* - * Reclaim node reference. - */ - ieee80211_free_node(ni); - } -#endif - ATH_TXBUF_LOCK_BH(sc); -// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); - ATH_TXBUF_UNLOCK_BH(sc); - } -} - -static void -ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) -{ - struct ath_hal *ah = sc->sc_ah; - - ath5k_hw_stop_tx_dma(ah, txq->axq_qnum); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %x, link %p\n", - __func__, txq->axq_qnum, - ath5k_hw_get_tx_buf(ah, txq->axq_qnum), txq->axq_link); -} - -/* - * Drain the transmit queues and reclaim resources. - */ -static void -ath_draintxq(struct ath_softc *sc) -{ - struct ath_hal *ah = sc->sc_ah; - int i; - - /* XXX return value */ - if (!sc->sc_invalid) { - /* don't touch the hardware if marked invalid */ - (void) ath5k_hw_stop_tx_dma(ah, sc->sc_bhalq); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, - ath5k_hw_get_tx_buf(ah, sc->sc_bhalq)); - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) { - if (ATH_TXQ_SETUP(sc, i)) - ath_tx_stopdma(sc, &sc->sc_txq[i]); - } - } -// sc->sc_dev->trans_start = jiffies; - -// netif_start_queue(sc->sc_dev); // TODO: needed here? - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) { - if (ATH_TXQ_SETUP(sc, i)) - ath_tx_draintxq(sc, &sc->sc_txq[i]); - } - sc->sc_tx_timer = 0; -} - -/* - * Disable the receive h/w in preparation for a reset. - */ -static void -ath_stoprecv(struct ath_softc *sc) -{ -#define PA2DESC(_sc, _pa) \ - ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ - ((_pa) - (_sc)->sc_desc_daddr))) - struct ath_hal *ah = sc->sc_ah; - - ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ - ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ - ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ - mdelay(3); /* 3ms is long enough for 1 frame */ -#ifdef AR_DEBUG - if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow -// struct ath_buf *bf; - - printk("%s: rx queue %x, link %p\n", __func__, - ath5k_hw_get_rx_buf(ah), sc->sc_rxlink); -#ifdef BLE - STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { - struct ath_desc *ds = bf->bf_desc; - enum ath5k_status status = ah->ah_proc_rx_desc(ah, ds, - bf->bf_daddr, PA2DESC(sc, ds->ds_link)); - if (status == AR5K_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) - ath_printrxbuf(bf, status == AR5K_OK); - } -#endif - } -#endif - sc->sc_rxlink = NULL; /* just in case */ -#undef PA2DESC -} -#endif -/* - * Enable the receive h/w following a reset. - */ -static int -ath_startrecv(struct ath_softc *sc) -{ - struct ath_hal *ah = sc->sc_ah; -// struct net_device *dev = ic->ic_dev; - struct ath_buf *bf; - - /* - * Cisco's VPN software requires that drivers be able to - * receive encapsulated frames that are larger than the MTU. - * Since we can't be sure how large a frame we'll get, setup - * to handle the larges on possible. If you're not using the - * VPN driver and want to save memory, define ATH_ENFORCE_MTU - * and you'll allocate only what you really need. - */ -#ifdef ATH_ENFORCE_MTU - if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) { - sc->sc_rxbufsize = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz); - } else { - sc->sc_rxbufsize = roundup(sizeof(struct ieee80211_frame) + - dev->mtu + IEEE80211_CRC_LEN + - (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + - IEEE80211_WEP_CRCLEN), sc->sc_cachelsz); - } -#else - sc->sc_rxbufsize = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz); #endif #ifdef BLE - DPRINTF(sc, ATH_DEBUG_RESET, "%s: mtu %u cachelsz %u rxbufsize %u\n", - __func__, dev->mtu, sc->sc_cachelsz, sc->sc_rxbufsize); - - sc->sc_rxlink = NULL; - STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { - int error = ath_rxbuf_init(sc, bf); - if (error != 0) { - DPRINTF(sc, ATH_DEBUG_RECV, - "%s: ath_rxbuf_init failed %d\n", - __func__, error); - return error; - } - } - - bf = STAILQ_FIRST(&sc->sc_rxbuf); -#endif - bf = NULL; - ath5k_hw_put_rx_buf(ah, bf->bf_daddr); - ath5k_hw_start_rx(ah); /* enable recv descriptors */ -// ath_mode_init(dev); /* set filters, etc. */ - ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ - return 0; -} - -#ifdef BLE -/* - * Update internal state after a channel change. - */ -static void -ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) -{ - unsigned int mode; -// u_int16_t flags; - - /* - * Change channels and update the h/w rate map - * if we're switching; e.g. 11a to 11b/g. - */ -// mode = ieee80211_chan2mode(ic, chan); - if (mode != sc->sc_curmode) - ath_setcurmode(sc, mode); - /* - * Update BPF state. NB: ethereal et. al. don't handle - * merged flags well so pick a unique mode for their use. - */ - if (IEEE80211_IS_CHAN_A(chan)) - flags = IEEE80211_CHAN_A; - /* XXX 11g schizophrenia */ - else if (IEEE80211_IS_CHAN_G(chan) || - IEEE80211_IS_CHAN_PUREG(chan)) - flags = IEEE80211_CHAN_G; - else - flags = IEEE80211_CHAN_B; - if (IEEE80211_IS_CHAN_T(chan)) - flags |= CHANNEL_TURBO; -} - -/* - * Set/change channels. If the channel is really being changed, - * it's done by reseting the chip. To accomplish this we must - * first cleanup any pending DMA, then restart stuff after a la - * ath_init. - */ -static int -ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) -{ - struct ath_hal *ah = sc->sc_ah; - struct ath5k_channel hchan; - - /* - * Convert to a HAL channel description with - * the flags constrained to reflect the current - * operating mode. - */ -#ifdef BLE - if (chan == IEEE80211_CHAN_ANYC) { - return 0; - } - hchan.freq = chan->freq; - hchan.channel_flags = ath_chan2flags(ic, chan); -#endif - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", - __func__, - ath_hal_mhz2ieee(sc->sc_curchan.freq, - sc->sc_curchan.channel_flags), - sc->sc_curchan.freq, - ath_hal_mhz2ieee(hchan.freq, hchan.channel_flags), hchan.freq); - if (hchan.freq != sc->sc_curchan.freq || - hchan.channel_flags != sc->sc_curchan.channel_flags) { - enum ath5k_status status; - - /* - * To switch channels clear any pending DMA operations; - * wait long enough for the RX fifo to drain, reset the - * hardware at the new frequency, and then re-enable - * the relevant bits of the h/w. - */ - ath5k_hw_set_intr(ah, 0); /* disable interrupts */ - ath_draintxq(sc); /* clear pending tx frames */ - ath_stoprecv(sc); /* turn off frame recv */ - if (!ath5k_hw_reset(ah, sc->sc_opmode, &hchan, true, &status)) { - printk(KERN_ERR "ath_chan_set: unable to reset " - "channel %u (%u Mhz)\n", 0, -// ieee80211_chan2ieee(ic, chan), - chan->freq); - return EIO; - } - sc->sc_curchan = hchan; - ath_update_txpow(sc); /* update tx power state */ - sc->sc_diversity = ath_hal_getdiversity(ah); - - /* - * Re-enable rx framework. - */ - if (ath_startrecv(sc) != 0) { - printk(KERN_ERR "ath_chan_set: unable to restart recv " - "logic\n"); - return EIO; - } - - /* - * Change channels and update the h/w rate map - * if we're switching; e.g. 11a to 11b/g. - */ -// ic->ic_ibss_chan = chan; - ath_chan_change(sc, chan); - - /* - * Re-enable interrupts. - */ - ath5k_hw_set_intr(ah, sc->sc_imask); - } - return 0; -} #endif static void ath_next_scan(unsigned long arg) @@ -4437,26 +3715,6 @@ ath_led_event(struct ath_softc *sc, int event) } } #endif -static void -ath_update_txpow(struct ath_softc *sc) -{ -#ifdef BLE - struct ath_hal *ah = sc->sc_ah; - u_int32_t txpow; - - if (sc->sc_curtxpow != ic->ic_txpowlimit) { - ath5k_hw_set_txpower_limit(ah, ic->ic_txpowlimit); - /* read back in case value is clamped */ - (void)ath_hal_gettxpowlimit(ah, &txpow); - ic->ic_txpowlimit = sc->sc_curtxpow = txpow; - } - /* - * Fetch max tx power level for status requests. - */ - (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); - ic->ic_bss->ni_txpower = txpow; -#endif -} #ifdef BLE static int @@ -4527,34 +3785,6 @@ ath_vlan_kill_vid(struct net_device *dev, unsigned short vid) } #endif /* IEEE80211_VLAN_TAG_USED */ #endif -#ifdef AR_DEBUG -static void -ath_printrxbuf(struct ath_buf *bf, int done) -{ - struct ath_desc *ds = bf->bf_desc; - - printk("R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", - ds, (unsigned long long)bf->bf_daddr, - ds->ds_link, ds->ds_data, - ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], - !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); -} -#ifdef BLE -static void -ath_printtxbuf(struct ath_buf *bf, int done) -{ - struct ath_desc *ds = bf->bf_desc; - - printk("T (%p %llx) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", - ds, (unsigned long long)bf->bf_daddr, - ds->ds_link, ds->ds_data, - ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], - !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); -} -#endif -#endif /* AR_DEBUG */ #ifdef BLE /* * Return netdevice statistics. diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index b2fcefe..0fc213e 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -37,6 +37,7 @@ #include "if_athvar.h" #define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ +#define AR_DEBUG 1 #define KASSERT(exp, msg...) do { \ if (unlikely(!(exp))) { \ @@ -82,6 +83,11 @@ MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); module_param(xchanmode, int, 0); MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); +#ifdef AR_DEBUG +static unsigned int ath_debug; +module_param_named(debug, ath_debug, uint, 0); +#endif + /* * User a static table of PCI id's for now. While this is the * "new way" to do things, we may want to switch back to having @@ -109,30 +115,544 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = { }; MODULE_DEVICE_TABLE(pci, ath_pci_id_table); -static int ath_open(struct ieee80211_hw *hw) +#ifdef AR_DEBUG +static void ath_printrxbuf(struct ath_buf *bf, int done) { - printk("%s\n", __FUNCTION__); + struct ath_desc *ds = bf->desc; + + printk("R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", + ds, (unsigned long long)bf->daddr, + ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], + !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); +} + +static void ath_printtxbuf(struct ath_buf *bf, int done) +{ + struct ath_desc *ds = bf->desc; + + printk("T (%p %llx) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", + ds, (unsigned long long)bf->daddr, + ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], + !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); +} +#endif + +static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) +{ + struct ath_hw *ah = sc->ah; + struct sk_buff *skb = bf->skb; + struct ath_desc *ds; + + if (skb == NULL) { + unsigned int off; + + /* + * Allocate buffer with headroom_needed space for the + * fake physical layer header at the start. + */ + skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); + if (skb == NULL) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " + "size %u failed\n", __func__, + sc->rxbufsize + sc->cachelsz - 1); + sc->stats.ast_rx_nobuf++; + return -ENOMEM; + } + /* + * Cache-line-align. This is important (for the + * 5210 at least) as not doing so causes bogus data + * in rx'd frames. + */ + off = ((unsigned long)skb->data) % sc->cachelsz; + if (off != 0) + skb_reserve(skb, sc->cachelsz - off); + + bf->skb = skb; + bf->skbaddr = pci_map_single(sc->pdev, + skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); + if (pci_dma_mapping_error(bf->skbaddr)) { + printk(KERN_ERR "%s: DMA mapping failed\n", __func__); + dev_kfree_skb(skb); + bf->skb = NULL; + sc->stats.ast_rx_busdma++; + return -ENOMEM; + } + } + + /* + * Setup descriptors. For receive we always terminate + * the descriptor list with a self-linked entry so we'll + * not get overrun under high load (as can happen with a + * 5212 when ANI processing enables PHY error frames). + * + * To insure the last descriptor is self-linked we create + * each descriptor as self-linked and add it to the end. As + * each additional descriptor is added the previous self-linked + * entry is ``fixed'' naturally. This should be safe even + * if DMA is happening. When processing RX interrupts we + * never remove/process the last, self-linked, entry on the + * descriptor list. This insures the hardware always has + * someplace to write a new frame. + */ + ds = bf->desc; + ds->ds_link = bf->daddr; /* link to self */ + ds->ds_data = bf->skbaddr; + ath5k_hw_setup_rx_desc(ah, ds, + skb_tailroom(skb), /* buffer size */ + 0); + + if (sc->rxlink != NULL) + *sc->rxlink = bf->daddr; + sc->rxlink = &ds->ds_link; return 0; } -static int ath_stop(struct ieee80211_hw *hw) +/* + * Calculate the receive filter according to the + * operating mode and state: + * + * o always accept unicast, broadcast, and multicast traffic + * o maintain current state of phy error reception (the hal + * may enable phy error frames for noise immunity work) + * o probe request frames are accepted only when operating in + * hostap, adhoc, or monitor modes + * o enable promiscuous mode according to the interface state + * o accept beacons: + * - when operating in adhoc mode so the 802.11 layer creates + * node table entries for peers, + * - when operating in station mode for collecting rssi data when + * the station is otherwise quiet, or + * - when scanning + * o accept any additional packets specified by sc_rxfilter + */ +static u32 ath_calcrxfilter(struct ath_softc *sc) { - printk("%s\n", __FUNCTION__); + struct ath_hw *ah = sc->ah; + u32 rfilt; + + rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERROR) | + AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | + AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_PHYRADAR; +#ifdef BLE + if (ic->ic_opmode != IEEE80211_M_STA && + ic->ic_opmode != IEEE80211_M_AHDEMO) + rfilt |= AR5K_RX_FILTER_PROBEREQ; + if (ic->ic_opmode != IEEE80211_M_HOSTAP && + (dev->flags & IFF_PROMISC)) + rfilt |= AR5K_RX_FILTER_PROM; + if (ic->ic_opmode == IEEE80211_M_STA || + ic->ic_opmode == IEEE80211_M_IBSS || + state == IEEE80211_S_SCAN) +#endif + rfilt |= AR5K_RX_FILTER_BEACON; + + return rfilt; +} + +static void ath_mode_init(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + u32 rfilt; + + /* configure rx filter */ + rfilt = ath_calcrxfilter(sc); + ath5k_hw_set_rx_filter(ah, rfilt); + + if (ath_hal_hasbssidmask(ah)) + ath5k_hw_set_bssid_mask(ah, sc->bssidmask); + + /* configure operational mode */ + ath5k_hw_set_opmode(ah); + + ath5k_hw_set_mcast_filter(ah, 0, 0); + DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); +} + +/* + * Enable the receive h/w following a reset. + */ +static int ath_startrecv(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + struct list_head *pos; + struct ath_buf *bf; + int ret; + + sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz); + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: cachelsz %u rxbufsize %u\n", + __func__, sc->cachelsz, sc->rxbufsize); + + sc->rxlink = NULL; + list_for_each(pos, &sc->rxbuf) { + bf = list_entry(pos, struct ath_buf, list); + ret = ath_rxbuf_init(sc, bf); + if (ret != 0) + goto err; + } + + bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); + ath5k_hw_put_rx_buf(ah, bf->daddr); + ath5k_hw_start_rx(ah); /* enable recv descriptors */ + ath_mode_init(sc); /* set filters, etc. */ + ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ + return 0; +err: + return ret; } -static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) +static inline void ath_update_txpow(struct ath_softc *sc) { - printk("%s\n", __FUNCTION__); + ath5k_hw_set_txpower_limit(sc->ah, 0); +} + +static int ath_stop_locked(struct ath_softc *); + +static int ath_init(struct ath_softc *sc) +{ + int ret; + + mutex_lock(&sc->lock); + +// DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); + + /* + * Stop anything previously setup. This is safe + * no matter this is the first time through or not. + */ + ath_stop_locked(sc); + + /* + * The basic interface to setting the hardware in a good + * state is ``reset''. On return the hardware is known to + * be powered up and with interrupts disabled. This must + * be followed by initialization of the appropriate bits + * and then setup of the interrupt mask. + */ + sc->curchan = sc->hw->conf.chan; + ret = ath5k_hw_reset(sc->ah, IEEE80211_IF_TYPE_STA, sc->curchan, false); + if (ret) { + printk(KERN_ERR "unable to reset hardware: %d\n", ret); + goto done; + } + /* + * This is needed only to setup initial state + * but it's best done after a reset. + */ + ath_update_txpow(sc); + + /* + * Setup the hardware after reset: the key cache + * is filled as needed and the receive engine is + * set going. Frame transmit is handled entirely + * in the frame output path; there's nothing to do + * here except setup the interrupt mask. + */ + ret = ath_startrecv(sc); + if (ret) + goto done; + + /* + * Enable interrupts. + */ + sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN + | AR5K_INT_FATAL | AR5K_INT_GLOBAL; + + ath5k_hw_set_intr(sc->ah, sc->imask); + + ret = 0; +done: + mutex_unlock(&sc->lock); + return ret; +} + +/* + * Disable the receive h/w in preparation for a reset. + */ +static void ath_stoprecv(struct ath_softc *sc) +{ +#define PA2DESC(_sc, _pa) ((struct ath_desc *)((caddr_t)(_sc)->desc + \ + ((_pa) - (_sc)->desc_daddr))) + struct ath_hw *ah = sc->ah; + + ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ + ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ + ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ + mdelay(3); /* 3ms is long enough for 1 frame */ +#ifdef AR_DEBUG + if (sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow + struct list_head *pos; + struct ath_desc *ds; + struct ath_buf *bf; + int status; + + printk(KERN_DEBUG "%s: rx queue %x, link %p\n", __func__, + ath5k_hw_get_rx_buf(ah), sc->rxlink); + + list_for_each(pos, &sc->rxbuf) { + bf = list_entry(pos, struct ath_buf, list); + ds = bf->desc; + status = ah->ah_proc_rx_desc(ah, ds, bf->daddr, + PA2DESC(sc, ds->ds_link)); + if (!status || (sc->debug & ATH_DEBUG_FATAL)) + ath_printrxbuf(bf, status == 0); + } + } +#endif + sc->rxlink = NULL; /* just in case */ +#undef PA2DESC +} + +static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) +{ +#ifdef AR_DEBUG + struct ath_hw *ah = sc->ah; +#endif + struct ath_buf *bf; + + /* + * NB: this assumes output has been stopped and + * we do not need to block ath_tx_tasklet + */ + for (;;) { + spin_lock_bh(&txq->axq_lock); + if (list_empty(&txq->axq_q)) { + txq->axq_link = NULL; + spin_unlock_bh(&txq->axq_lock); + break; + } + bf = list_first_entry(&txq->axq_q, struct ath_buf, list); + list_del(&bf->list); + spin_unlock_bh(&txq->axq_lock); +#ifdef AR_DEBUG + if (sc->debug & ATH_DEBUG_RESET) + ath_printtxbuf(bf, !ah->ah_proc_tx_desc(ah, bf->desc)); +#endif + pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, + PCI_DMA_TODEVICE); + dev_kfree_skb(bf->skb); + bf->skb = NULL; + + spin_lock_bh(&sc->txbuflock); + list_add_tail(&bf->list, &sc->txbuf); + spin_unlock_bh(&sc->txbuflock); + } +} + +/* + * Drain the transmit queues and reclaim resources. + */ +static void ath_draintxq(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + int i; + + /* XXX return value */ + if (!sc->invalid) { + /* don't touch the hardware if marked invalid */ + (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, + ath5k_hw_get_tx_buf(ah, sc->bhalq)); + for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) + if (test_bit(i, sc->txqsetup)) { + ath5k_hw_stop_tx_dma(ah, sc->txq[i].axq_qnum); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: txq [%u] %x, " + "link %p\n", __func__, + sc->txq[i].axq_qnum, + ath5k_hw_get_tx_buf(ah, + sc->txq[i].axq_qnum), + sc->txq[i].axq_link); + } + } + ieee80211_start_queues(sc->hw); /* XXX move to callers */ + + for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) + if (test_bit(i, sc->txqsetup)) + ath_tx_draintxq(sc, &sc->txq[i]); + +// sc->tx_timer = 0; +} + +static int ath_stop_locked(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__, sc->invalid); + + /* + * Shutdown the hardware and driver: + * stop output from above + * disable interrupts + * turn off timers + * turn off the radio + * clear transmit machinery + * clear receive machinery + * drain and release tx queues + * reclaim beacon resources + * power down hardware + * + * Note that some of this work is not possible if the + * hardware is gone (invalid). + */ + ieee80211_stop_queues(sc->hw); + + if (!sc->invalid) { + if (sc->softled) { +#ifdef BLE + del_timer(&sc->ledtimer); + ath5k_hw_set_gpio(ah, sc->ledpin, !sc->ledon); + sc->blinking = 0; +#endif + } + ath5k_hw_set_intr(ah, 0); + } + ath_draintxq(sc); + if (!sc->invalid) { + ath_stoprecv(sc); + ath5k_hw_phy_disable(ah); + } else + sc->rxlink = NULL; +// ath_beacon_free(sc); + return 0; } -static int ath_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) +/* + * Stop the device, grabbing the top-level lock to protect + * against concurrent entry through ath_init (which can happen + * if another thread does a system call and the thread doing the + * stop is preempted). + */ +static int ath_stop_hw(struct ath_softc *sc) +{ + int ret; + + mutex_lock(&sc->lock); + ret = ath_stop_locked(sc); + if (ret == 0 && !sc->invalid) { + /* + * Set the chip in full sleep mode. Note that we are + * careful to do this only when bringing the interface + * completely to a stop. When the chip is in this state + * it must be carefully woken up or references to + * registers in the PCI clock domain may freeze the bus + * (and system). This varies by chip and is mostly an + * issue with newer parts that go to sleep more quickly. + */ + if (sc->ah->ah_mac_version >= 7 && sc->ah->ah_mac_revision >= 8) { + /* + * XXX + * don't put newer MAC revisions > 7.8 to sleep because + * of the above mentioned problems + */ + DPRINTF(sc, ATH_DEBUG_RESET, "%s: mac version > 7.8, " + "not putting device to sleep\n", __func__); + } + else { + DPRINTF(sc, ATH_DEBUG_RESET, + "%s: putting device to full sleep\n", __func__); + ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); + } + } + mutex_unlock(&sc->lock); + return ret; +} + +/* + * Set/change channels. If the channel is really being changed, + * it's done by reseting the chip. To accomplish this we must + * first cleanup any pending DMA, then restart stuff after a la + * ath_init. + */ +static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) +{ + struct ath_hw *ah = sc->ah; + int ret; + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", + __func__, sc->curchan->chan, sc->curchan->freq, + chan->chan, chan->freq); + + if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) { + /* + * To switch channels clear any pending DMA operations; + * wait long enough for the RX fifo to drain, reset the + * hardware at the new frequency, and then re-enable + * the relevant bits of the h/w. + */ + ath5k_hw_set_intr(ah, 0); /* disable interrupts */ + ath_draintxq(sc); /* clear pending tx frames */ + ath_stoprecv(sc); /* turn off frame recv */ + ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, chan, true); + if (ret) { + printk(KERN_ERR "%s: unable to reset channel %u " + "(%u Mhz)\n", __func__, chan->chan, chan->freq); + return ret; + } + sc->curchan = chan; + ath_update_txpow(sc); + + /* + * Re-enable rx framework. + */ + ret = ath_startrecv(sc); + if (ret) { + printk(KERN_ERR "%s: unable to restart recv logic\n", + __func__); + return ret; + } + + /* + * Change channels and update the h/w rate map + * if we're switching; e.g. 11a to 11b/g. + */ +// ath_chan_change(sc, chan); + + /* + * Re-enable interrupts. + */ + ath5k_hw_set_intr(ah, sc->imask); + } + + return 0; +} + +static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, + struct ieee80211_tx_control *control) { printk("%s\n", __FUNCTION__); + + dev_kfree_skb_any(skb); + return 0; } +static int ath_open(struct ieee80211_hw *hw) +{ + printk("%s\n", __FUNCTION__); + + return ath_init(hw->priv); +} + +static int ath_stop(struct ieee80211_hw *hw) +{ + printk("%s\n", __FUNCTION__); + + return ath_stop_hw(hw->priv); +} + +static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) +{ + struct ath_softc *sc = hw->priv; + + sc->curmode = conf->phymode; + + return ath_chan_set(sc, conf->chan); +} + static int ath_conf_tx(struct ieee80211_hw *hw, int queue, const struct ieee80211_tx_queue_params *params) { @@ -141,7 +661,7 @@ static int ath_conf_tx(struct ieee80211_hw *hw, int queue, } static struct ieee80211_ops ath_hw_ops = { - .tx = NULL, + .tx = ath_tx, .reset = NULL, .open = ath_open, .stop = ath_stop, @@ -150,7 +670,6 @@ static struct ieee80211_ops ath_hw_ops = { .config = ath_config, .config_interface = NULL, .set_key = NULL, - .hw_scan = ath_hw_scan, .get_stats = NULL, .conf_tx = ath_conf_tx, /* .get_tx_stats = , @@ -168,7 +687,6 @@ static irqreturn_t ath_intr(int irq, void *dev_id) if (sc->invalid || !ath5k_hw_is_intr_pending(ah)) return IRQ_NONE; -return IRQ_HANDLED; do { /* @@ -177,8 +695,9 @@ return IRQ_HANDLED; * bits we haven't explicitly enabled so we mask the * value to insure we only process bits we requested. */ - ath5k_hw_get_isr(ah, &status); /* NB: clears ISR too */ - DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); + ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ + DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x/0x%x\n", __func__, + status, sc->imask); status &= sc->imask; /* discard unasked for bits */ if (status & AR5K_INT_FATAL) { /* @@ -189,11 +708,11 @@ return IRQ_HANDLED; */ sc->stats.ast_hardware++; ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ - tasklet_schedule(&sc->fataltq); +// tasklet_schedule(&sc->fataltq); } else if (status & AR5K_INT_RXORN) { sc->stats.ast_rxorn++; ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ - tasklet_schedule(&sc->rxorntq); +// tasklet_schedule(&sc->rxorntq); } else { if (status & AR5K_INT_SWBA) { /* @@ -218,36 +737,23 @@ return IRQ_HANDLED; /* bump tx trigger level */ ath5k_hw_update_tx_triglevel(ah, true); } - if (status & AR5K_INT_RX) +/* if (status & AR5K_INT_RX) tasklet_schedule(&sc->rxtq); if (status & AR5K_INT_TX) tasklet_schedule(&sc->txtq); if (status & AR5K_INT_BMISS) { sc->stats.ast_bmiss++; tasklet_schedule(&sc->bmisstq); - } + }*/ if (status & AR5K_INT_MIB) { sc->stats.ast_mib++; - /* - * Disable interrupts until we service the MIB - * interrupt; otherwise it will continue to fire. - */ - ath5k_hw_set_intr(ah, 0); - /* - * Let the hal handle the event. We assume it will - * clear whatever condition caused the interrupt. - */ -#ifdef BLE - ath5k_hw_proc_mib_event(ah, - &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); -#endif - ath5k_hw_set_intr(ah, sc->imask); + /* TODO */ } } } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); - if (!counter) - printk(KERN_WARNING "ath: too much interrupts, giving up for " + if (!counter && printk_ratelimit()) + printk(KERN_WARNING "ath: too many interrupts, giving up for " "now\n"); return IRQ_HANDLED; @@ -571,14 +1077,14 @@ err: sc->desc = NULL; return ret; } -#if 0 + static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, struct list_head *head) { struct list_head *pos; struct ath_buf *bf; - list_for_each(pos, head, bf_list){ + list_for_each(pos, head) { bf = list_entry(pos, struct ath_buf, list); if (bf->skb) { pci_unmap_single(pdev, bf->skbaddr, sc->rxbufsize, @@ -590,14 +1096,13 @@ static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, INIT_LIST_HEAD(head); } -#endif + static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) { -#ifdef BLE - ath_descdma_cleanup(sc, pdev, sc->bbuf); - ath_descdma_cleanup(sc, pdev, sc->txbuf); - ath_descdma_cleanup(sc, pdev, sc->rxbuf); -#endif + ath_descdma_cleanup(sc, pdev, &sc->bbuf); + ath_descdma_cleanup(sc, pdev, &sc->txbuf); + ath_descdma_cleanup(sc, pdev, &sc->rxbuf); + /* Free memory associated with all descriptors */ pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); @@ -875,6 +1380,10 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ath5k_hw_get_lladdr(ah, mac); SET_IEEE80211_PERM_ADDR(hw, mac); + if (ath_hal_hasbssidmask(ah)) { + memset(sc->bssidmask, 0xff, ETH_ALEN); + ath5k_hw_set_bssid_mask(ah, sc->bssidmask); + } ret = ieee80211_register_hw(hw); if (ret) { @@ -898,7 +1407,7 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; -// ath_stop(hw); + ath_stop_hw(sc); /* XXX needed? */ /* * NB: the order of these is important: * o call the 802.11 layer before detaching the hal to @@ -1017,6 +1526,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, * Mark the device as detached to avoid processing * interrupts until setup is complete. */ + sc->debug = ath_debug; sc->invalid = 1; sc->iobase = mem; sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ @@ -1096,7 +1606,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) if (sc->softled) ath5k_hw_set_gpio(sc->ah, sc->ledpin, 1); -// ath_stop(hw); + ath_stop_hw(sc); pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, PCI_D3hot); @@ -1126,7 +1636,7 @@ static int ath_pci_resume(struct pci_dev *pdev) */ pci_write_config_byte(pdev, 0x41, 0); -// ath_init(hw); + ath_init(sc); if (sc->softled) { ath5k_hw_set_gpio_output(sc->ah, sc->ledpin); ath5k_hw_set_gpio(sc->ah, sc->ledpin, 0); diff --git a/ath/if_athvar.h b/ath/if_athvar.h index c58286c..1b7d2c5 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -45,6 +45,7 @@ #include #include #include +#include #include "ath5k.h" #include "if_athioctl.h" @@ -132,7 +133,7 @@ struct ath_txq { u_int axq_qnum; /* hardware q number */ u_int axq_depth; /* queue depth (stat only) */ u_int axq_intrcnt; /* interrupt count */ - u32 *axq_link; /* link ptr in last TX desc */ + u32 *axq_link; /* link ptr in last TX desc */ struct list_head axq_q; /* transmit queue */ spinlock_t axq_lock; /* lock on q and link */ /* @@ -150,15 +151,6 @@ struct ath_txq { */ }; -#define ATH_TXQ_LOCK_INIT(_sc, _tq) spin_lock_init(&(_tq)->axq_lock) -#define ATH_TXQ_LOCK_DESTROY(_tq) -#define ATH_TXQ_LOCK(_tq) spin_lock(&(_tq)->axq_lock) -#define ATH_TXQ_UNLOCK(_tq) spin_unlock(&(_tq)->axq_lock) -#define ATH_TXQ_LOCK_BH(_tq) spin_lock_bh(&(_tq)->axq_lock) -#define ATH_TXQ_UNLOCK_BH(_tq) spin_unlock_bh(&(_tq)->axq_lock) -#define ATH_TXQ_LOCK_ASSERT(_tq) \ - KASSERT(spin_is_locked(&(_tq)->axq_lock), ("txq not locked!")) - #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ (_tq)->axq_depth++; \ @@ -175,6 +167,7 @@ struct ath_txq { #endif struct ath_softc { + struct pci_dev *pdev; /* for dma mapping */ void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ // struct net_device_stats sc_devstats; /* device statistics */ @@ -228,10 +221,10 @@ struct ath_softc { const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; const struct ath5k_rate_table *sc_currates; /* current rate table */ #endif - unsigned int curmode; /* current phy mode */ + unsigned int curmode; /* current phy mode */ + struct ieee80211_channel *curchan; /* current h/w channel */ #ifdef BLE u16 sc_curtxpow; /* current tx power limit */ - struct ieee80211_channel sc_curchan; /* current h/w channel */ u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ #endif struct { @@ -251,6 +244,7 @@ struct ath_softc { u8 sc_keymap[ATH_KEYBYTES];/* key use bit map */ struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ #endif + u8 bssidmask[ETH_ALEN]; u_int ledpin; /* GPIO pin for driving LED */ #ifdef BLE u_int sc_ledon; /* pin setting for LED on */ @@ -260,7 +254,6 @@ struct ath_softc { u8 sc_txrate; /* current tx rate for LED */ u16 sc_ledoff; /* off time for current blink */ struct timer_list sc_ledtimer; /* led off timer */ - u32 sc_rxfilter; union { struct ath_tx_radiotap_header th; @@ -276,9 +269,8 @@ struct ath_softc { struct tasklet_struct fataltq; /* fatal int tasklet */ #ifdef BLE struct tasklet_struct sc_radartq; /* Radar detection */ - - int sc_rxbufsize; /* rx size based on mtu */ #endif + unsigned int rxbufsize; /* rx size based on mtu */ struct list_head rxbuf; /* receive buffer */ struct tasklet_struct rxtq; /* rx intr tasklet */ struct tasklet_struct rxorntq; /* rxorn intr tasklet */ @@ -375,6 +367,8 @@ void ath_sysctl_unregister(void); ath5k_hw_set_capability(_ah, AR5K_CAP_TPC, 1, _v, NULL) #define ath_hal_hasbursting(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) +#define ath_hal_hasbssidmask(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) #ifdef notyet #define ath_hal_hasmcastkeysearch(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == 0) diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 8339bfc..6f8f180 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -1004,13 +1004,12 @@ const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsig void ath5k_hw_detach(struct ath_hw *hal); /* Reset Functions */ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); -//bool ath5k_hw_nic_reset(struct ath_hw *hal, u32 val); /* Power management functions */ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); /* DMA Related Functions */ void ath5k_hw_start_rx(struct ath_hw *hal); -bool ath5k_hw_stop_rx_dma(struct ath_hw *hal); +int ath5k_hw_stop_rx_dma(struct ath_hw *hal); u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); bool ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); @@ -1020,7 +1019,7 @@ bool ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); /* Interrupt handling */ bool ath5k_hw_is_intr_pending(struct ath_hw *hal); -bool ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask); +int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ @@ -1053,7 +1052,6 @@ void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_st void ath5k_hw_reset_beacon(struct ath_hw *hal); bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); -void ath5k_hw_proc_mib_event(struct ath_hw *hal, const struct ath5k_node_stats *stats) ; /* ACK/CTS Timeouts */ bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); @@ -1114,6 +1112,7 @@ void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channe bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ +int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); void ath5k_hw_dump_state(struct ath_hw *hal); int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 34133a1..0fef518 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -41,8 +41,7 @@ static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; static int ath5k_hw_nic_reset(struct ath_hw *, u32); static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool); static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int); -static bool ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, - unsigned int); +static int ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int); static bool ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, @@ -685,11 +684,12 @@ void ath5k_hw_detach(struct ath_hw *hal) int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel) { + const struct ath5k_rate_table *rt; struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u8 mac[ETH_ALEN]; u32 data, noise_floor, s_seq, s_ant, s_led[3]; + u8 mac[ETH_ALEN]; unsigned int i, phy, mode, freq, off, ee_mode, ant[2]; - const struct ath5k_rate_table *rt; + int ret; AR5K_TRACE; @@ -723,8 +723,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*Wakeup the device*/ - if (ath5k_hw_nic_wakeup(hal, channel->val, false) == false) - return -EIO; + ret = ath5k_hw_nic_wakeup(hal, channel->val, false); + if (ret) + return ret; /* * Initialize operating mode @@ -966,10 +967,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Set TX power (XXX use txpower from net80211) */ - if (ath5k_hw_txpower(hal, channel, - AR5K_TUNE_DEFAULT_TXPOWER) == false) { - return -EIO; - } + ret = ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER); + if (ret) + return ret; /* * Write RF registers @@ -1403,8 +1403,7 @@ ath5k_hw_get_power_mode(struct ath_hw *hal) /* * Start DMA receive */ -void -ath5k_hw_start_rx(struct ath_hw *hal) +void ath5k_hw_start_rx(struct ath_hw *hal) { AR5K_TRACE; ath5k_hw_reg_write(hal, AR5K_CR_RXE, AR5K_CR); @@ -1413,10 +1412,9 @@ ath5k_hw_start_rx(struct ath_hw *hal) /* * Stop DMA receive */ -bool -ath5k_hw_stop_rx_dma(struct ath_hw *hal) +int ath5k_hw_stop_rx_dma(struct ath_hw *hal) { - int i; + unsigned int i; AR5K_TRACE; ath5k_hw_reg_write(hal, AR5K_CR_RXD, AR5K_CR); @@ -1424,19 +1422,18 @@ ath5k_hw_stop_rx_dma(struct ath_hw *hal) /* * It may take some time to disable the DMA receive unit */ - for (i = 2000; - i > 0 && (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_RXE) != 0; - i--) + for (i = 2000; i > 0 && + (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_RXE) != 0; + i--) udelay(10); - return i > 0 ? true : false; + return i ? 0 : -EBUSY; } /* * Get the address of the RX Descriptor */ -u32 -ath5k_hw_get_rx_buf(struct ath_hw *hal) +u32 ath5k_hw_get_rx_buf(struct ath_hw *hal) { return ath5k_hw_reg_read(hal, AR5K_RXDP); } @@ -1444,8 +1441,7 @@ ath5k_hw_get_rx_buf(struct ath_hw *hal) /* * Set the address of the RX Descriptor */ -void -ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) +void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) { AR5K_TRACE; @@ -1713,8 +1709,7 @@ bool ath5k_hw_is_intr_pending(struct ath_hw *hal) /* * Get interrupt mask (ISR) */ -bool -ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) +int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) { u32 data; @@ -1725,9 +1720,10 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) * on 5210 */ if (hal->ah_version == AR5K_AR5210) { - if ((data = ath5k_hw_reg_read(hal, AR5K_ISR)) == AR5K_INT_NOCARD) { + data = ath5k_hw_reg_read(hal, AR5K_ISR); + if (data == AR5K_INT_NOCARD) { *interrupt_mask = data; - return false; + return -ENODEV; } } @@ -1742,7 +1738,7 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; if (data == AR5K_INT_NOCARD) - return false; + return -ENODEV; if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) *interrupt_mask |= AR5K_INT_RX; @@ -1775,14 +1771,13 @@ ath5k_hw_get_isr(struct ath_hw *hal, u32 *interrupt_mask) if (*interrupt_mask == 0 && printk_ratelimit()) AR5K_PRINTF("0x%08x\n", data); - return true; + return 0; } /* * Set interrupt mask */ -enum ath5k_int -ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) +enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) { enum ath5k_int old_mask, int_mask; @@ -1801,26 +1796,18 @@ ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) int_mask = new_mask & AR5K_INT_COMMON; if (new_mask & AR5K_INT_RX) - int_mask |= - AR5K_IMR_RXOK | - AR5K_IMR_RXERR | - AR5K_IMR_RXORN | + int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN | AR5K_IMR_RXDESC; if (new_mask & AR5K_INT_TX) - int_mask |= - AR5K_IMR_TXOK | - AR5K_IMR_TXERR | - AR5K_IMR_TXDESC | + int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC | AR5K_IMR_TXURN; if (hal->ah_version != AR5K_AR5210) { if (new_mask & AR5K_INT_FATAL) { int_mask |= AR5K_IMR_HIUERR; - AR5K_REG_ENABLE_BITS(hal, AR5K_SIMR2, - AR5K_SIMR2_MCABT | - AR5K_SIMR2_SSERR | - AR5K_SIMR2_DPERR); + AR5K_REG_ENABLE_BITS(hal, AR5K_SIMR2, AR5K_SIMR2_MCABT | + AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR); } } @@ -3111,12 +3098,6 @@ ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statist } } -void /*Unimplemented*/ -ath5k_hw_proc_mib_event(struct ath_hw *hal, const struct ath5k_node_stats *stats) -{ - AR5K_TRACE; -} - /* * ACK/CTS Timeouts */ @@ -5612,11 +5593,10 @@ ath5k_hw_get_rf_gain(struct ath_hw *hal) /* * Initialize the tx power table (not fully implemented) */ -static void -ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power) +static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power) { u16 txpower, *rates; - int i, min, max, n; + unsigned int i, min, max, n; rates = hal->ah_txpower.txp_rates; @@ -5650,16 +5630,16 @@ ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 m /* * Set transmition power */ -static bool /*O.K. - txpower_table is unimplemented so this doesn't work*/ +static int /*O.K. - txpower_table is unimplemented so this doesn't work*/ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; - int i; + unsigned int i; AR5K_TRACE; if (txpower > AR5K_TUNE_MAX_TXPOWER) { AR5K_PRINTF("invalid tx power: %u\n", txpower); - return false; + return -EINVAL; } /* Reset TX power values */ @@ -5703,11 +5683,10 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); } - return true; + return 0; } -bool -ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) +int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) { /*Just a try M.F.*/ struct ieee80211_channel *channel = &hal->ah_current_channel; commit d225a4499b88a844d00790a2f4c339b13643c124 Author: Jiri Slaby Date: Fri Jul 6 23:07:36 2007 +0200 implement tx diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 0fc213e..cf6b618 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -47,7 +47,7 @@ } while (0) #define DPRINTF(sc, _m, _fmt...) do { \ - if (sc->debug & (_m) && printk_ratelimit()) \ + if ((sc->debug & (_m)) && net_ratelimit()) \ printk(_fmt); \ } while (0) enum { @@ -209,6 +209,68 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) return 0; } +static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) +{ + struct ieee80211_tx_status txs = {}; + struct ath_buf *bf, *bf0; + struct ath_desc *ds; + struct sk_buff *skb; + int ret; + + spin_lock(&txq->lock); + list_for_each_entry_safe(bf, bf0, &txq->q, list) { + ds = bf->desc; + + ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); + if (ret == -EINPROGRESS) + break; + else if (ret) { + printk(KERN_ERR "ath: error %d while processing " + "queue %u\n", ret, txq->qnum); + break; + } + + skb = bf->skb; + bf->skb = NULL; + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, + PCI_DMA_TODEVICE); + + txs.control = bf->ctl; + txs.retry_count = ds->ds_txstat.ts_shortretry + + ds->ds_txstat.ts_longretry; + if (ds->ds_txstat.ts_status) { + if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { + txs.excessive_retries = 1; + } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { + txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; + } + } else { + txs.flags |= IEEE80211_TX_STATUS_ACK; + txs.ack_signal = ds->ds_txstat.ts_rssi; + } + + ieee80211_tx_status(sc->hw, skb, &txs); + + printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); + + spin_lock(&sc->txbuflock); + list_move_tail(&bf->list, &sc->txbuf); + spin_unlock(&sc->txbuflock); + } + if (list_empty(&txq->q)) + txq->link = NULL; + spin_unlock(&txq->lock); +} + +static void ath_tasklet_tx(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + ath_tx_processq(sc, sc->txq); + + ieee80211_wake_queue(sc->hw, 0); +} + /* * Calculate the receive filter according to the * operating mode and state: @@ -411,22 +473,14 @@ static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) #ifdef AR_DEBUG struct ath_hw *ah = sc->ah; #endif - struct ath_buf *bf; + struct ath_buf *bf, *bf0; /* * NB: this assumes output has been stopped and * we do not need to block ath_tx_tasklet */ - for (;;) { - spin_lock_bh(&txq->axq_lock); - if (list_empty(&txq->axq_q)) { - txq->axq_link = NULL; - spin_unlock_bh(&txq->axq_lock); - break; - } - bf = list_first_entry(&txq->axq_q, struct ath_buf, list); - list_del(&bf->list); - spin_unlock_bh(&txq->axq_lock); + spin_lock_bh(&txq->lock); + list_for_each_entry_safe(bf, bf0, &txq->q, list) { #ifdef AR_DEBUG if (sc->debug & ATH_DEBUG_RESET) ath_printtxbuf(bf, !ah->ah_proc_tx_desc(ah, bf->desc)); @@ -437,9 +491,11 @@ static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) bf->skb = NULL; spin_lock_bh(&sc->txbuflock); - list_add_tail(&bf->list, &sc->txbuf); + list_move_tail(&bf->list, &sc->txbuf); spin_unlock_bh(&sc->txbuflock); } + txq->link = NULL; + spin_unlock_bh(&txq->lock); } /* @@ -452,28 +508,28 @@ static void ath_draintxq(struct ath_softc *sc) /* XXX return value */ if (!sc->invalid) { +#ifdef BLE /* don't touch the hardware if marked invalid */ (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, ath5k_hw_get_tx_buf(ah, sc->bhalq)); - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) - if (test_bit(i, sc->txqsetup)) { - ath5k_hw_stop_tx_dma(ah, sc->txq[i].axq_qnum); +#endif + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) + if (sc->txqs[i].setup) { + ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); DPRINTF(sc, ATH_DEBUG_RESET, "%s: txq [%u] %x, " "link %p\n", __func__, - sc->txq[i].axq_qnum, + sc->txqs[i].qnum, ath5k_hw_get_tx_buf(ah, - sc->txq[i].axq_qnum), - sc->txq[i].axq_link); + sc->txqs[i].qnum), + sc->txqs[i].link); } } ieee80211_start_queues(sc->hw); /* XXX move to callers */ - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) - if (test_bit(i, sc->txqsetup)) - ath_tx_draintxq(sc, &sc->txq[i]); - -// sc->tx_timer = 0; + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) + if (sc->txqs[i].setup) + ath_tx_draintxq(sc, &sc->txqs[i]); } static int ath_stop_locked(struct ath_softc *sc) @@ -583,7 +639,7 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) * hardware at the new frequency, and then re-enable * the relevant bits of the h/w. */ - ath5k_hw_set_intr(ah, 0); /* disable interrupts */ + ath5k_hw_set_intr(ah, 0); /* disable interrupts */ ath_draintxq(sc); /* clear pending tx frames */ ath_stoprecv(sc); /* turn off frame recv */ ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, chan, true); @@ -620,27 +676,118 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) return 0; } +static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, + struct ieee80211_tx_control *ctl) +{ + struct ath_hw *ah = sc->ah; + struct ath_txq *txq = sc->txq; + struct ath_desc *ds = bf->desc; + struct sk_buff *skb = bf->skb; + unsigned int hdrpad, pktlen, flags; + int ret; + + flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; + bf->ctl = *ctl; + /* XXX endianness */ + bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); + + if (ctl->flags & IEEE80211_TXCTL_NO_ACK) + flags |= AR5K_TXDESC_NOACK; + + if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) { + printk(KERN_DEBUG "len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + } + hdrpad = 0; + pktlen = skb->len - hdrpad + FCS_LEN; + ret = ah->ah_setup_tx_desc(ah, ds, pktlen, + ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, + ctl->power_level > 60 ? 60 : ctl->power_level, ctl->tx_rate, + ctl->retry_limit, AR5K_TXKEYIX_INVALID, 0, flags, 0, 0); + if (ret) + goto err_unmap; + + ds->ds_link = 0; + ds->ds_data = bf->skbaddr; + + ret = ah->ah_fill_tx_desc(ah, ds, skb->len, true, true); + if (ret) + goto err_unmap; + + spin_lock_bh(&txq->lock); + list_add_tail(&bf->list, &txq->q); + if (txq->link == NULL) /* is this first packet? */ + ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); + else /* no, so only link it */ + *txq->link = bf->daddr; + + txq->link = &ds->ds_link; + ath5k_hw_tx_start(ah, txq->qnum); + spin_unlock_bh(&txq->lock); + + printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); + + return 0; +err_unmap: + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); + return ret; +} + static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, - struct ieee80211_tx_control *control) + struct ieee80211_tx_control *ctl) { - printk("%s\n", __FUNCTION__); + struct ath_softc *sc = hw->priv; + struct ath_buf *bf; + unsigned long flags; +// unsigned int a; + +/* skb_pad(skb, 4); + printk(KERN_DEBUG "%p/%p, %p/%p, %u, %u\n" KERN_DEBUG, skb->head, skb->data, skb->tail, skb->end, skb->len, skb->data_len); + for (a = 0; a < min(200U, skb->len) + 4; a++) { + printk("%.2x %s", skb->data[a], ((a+1) % 8) ? "" : " "); + if (!((a+1) % 16)) + printk("\n" KERN_DEBUG); + } + printk("\n");*/ + + spin_lock_irqsave(&sc->txbuflock, flags); + if (list_empty(&sc->txbuf)) { + if (net_ratelimit()) + printk(KERN_ERR "ath: no further txbuf available, " + "dropping packet\n"); + sc->stats.ast_tx_nobuf++; + spin_unlock_irqrestore(&sc->txbuflock, flags); + return -1; + } + bf = list_first_entry(&sc->txbuf, struct ath_buf, list); + list_del(&bf->list); + if (list_empty(&sc->txbuf)) { + sc->stats.ast_tx_qstop++; + ieee80211_stop_queues(hw); + } + spin_unlock_irqrestore(&sc->txbuflock, flags); + + bf->skb = skb; - dev_kfree_skb_any(skb); + if (ath_tx_bf(sc, bf, ctl)) { + bf->skb = NULL; + spin_lock_irqsave(&sc->txbuflock, flags); + list_add_tail(&bf->list, &sc->txbuf); + spin_unlock_irqrestore(&sc->txbuflock, flags); + dev_kfree_skb_any(skb); + return 0; + } return 0; } static int ath_open(struct ieee80211_hw *hw) { - printk("%s\n", __FUNCTION__); - return ath_init(hw->priv); } static int ath_stop(struct ieee80211_hw *hw) { - printk("%s\n", __FUNCTION__); - return ath_stop_hw(hw->priv); } @@ -738,10 +885,10 @@ static irqreturn_t ath_intr(int irq, void *dev_id) ath5k_hw_update_tx_triglevel(ah, true); } /* if (status & AR5K_INT_RX) - tasklet_schedule(&sc->rxtq); + tasklet_schedule(&sc->rxtq);*/ if (status & AR5K_INT_TX) tasklet_schedule(&sc->txtq); - if (status & AR5K_INT_BMISS) { +/* if (status & AR5K_INT_BMISS) { sc->stats.ast_bmiss++; tasklet_schedule(&sc->bmisstq); }*/ @@ -752,7 +899,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) } } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); - if (!counter && printk_ratelimit()) + if (!counter && net_ratelimit()) printk(KERN_WARNING "ath: too many interrupts, giving up for " "now\n"); @@ -1062,13 +1209,14 @@ static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) bf->daddr = da; list_add_tail(&bf->list, &sc->txbuf); } - +#ifdef BLE INIT_LIST_HEAD(&sc->bbuf); for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { bf->desc = ds; bf->daddr = da; list_add_tail(&bf->list, &sc->bbuf); } +#endif return 0; err_free: @@ -1099,7 +1247,7 @@ static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) { - ath_descdma_cleanup(sc, pdev, &sc->bbuf); +// ath_descdma_cleanup(sc, pdev, &sc->bbuf); ath_descdma_cleanup(sc, pdev, &sc->txbuf); ath_descdma_cleanup(sc, pdev, &sc->rxbuf); @@ -1109,7 +1257,7 @@ static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) kfree(sc->bufptr); sc->bufptr = NULL; } - +#ifdef BLE static int ath_beaconq_setup(struct ath_hw *ah) { struct ath5k_txq_info qi; @@ -1123,11 +1271,12 @@ static int ath_beaconq_setup(struct ath_hw *ah) return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); } - +#endif static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) { struct ath_hw *ah = sc->ah; + struct ath_txq *txq; struct ath5k_txq_info qi; int qnum; @@ -1158,34 +1307,34 @@ static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, */ return ERR_PTR(qnum); } - if (qnum >= ARRAY_SIZE(sc->txq)) { + if (qnum >= ARRAY_SIZE(sc->txqs)) { printk(KERN_ERR "hal qnum %u out of range, max %u!\n", - qnum, ARRAY_SIZE(sc->txq)); + qnum, ARRAY_SIZE(sc->txqs)); ath5k_hw_release_tx_queue(ah, qnum); return ERR_PTR(-EINVAL); } - if (!test_bit(qnum, sc->txqsetup)) { - struct ath_txq *txq = &sc->txq[qnum]; - - txq->axq_qnum = qnum; - txq->axq_depth = 0; - txq->axq_intrcnt = 0; - txq->axq_link = NULL; - INIT_LIST_HEAD(&txq->axq_q); - spin_lock_init(&txq->axq_lock); - set_bit(qnum, sc->txqsetup); + printk(KERN_DEBUG "QNUM: %d\n", qnum); + txq = &sc->txqs[qnum]; + if (!txq->setup) { + txq->qnum = qnum; + txq->intrcnt = 0; + txq->link = NULL; + INIT_LIST_HEAD(&txq->q); + spin_lock_init(&txq->lock); + txq->setup = true; } - return &sc->txq[qnum]; + return &sc->txqs[qnum]; } static void ath_tx_cleanup(struct ath_softc *sc) { + struct ath_txq *txq = sc->txqs; unsigned int i; - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) - if (test_bit(i, sc->txqsetup)) { - ath5k_hw_release_tx_queue(sc->ah, sc->txq[i].axq_qnum); - clear_bit(i, sc->txqsetup); + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) + if (txq->setup) { + ath5k_hw_release_tx_queue(sc->ah, txq->qnum); + txq->setup = false; } } @@ -1260,6 +1409,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto err; } +#ifdef BLE /* * Allocate hardware transmit queues: one queue for * beacon frames and one data queue for each QoS @@ -1282,15 +1432,15 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) sc->cabq = NULL; goto err_queues; } - -#ifdef BLE - /* NB: insure BK queue is the lowest priority h/w queue */ - if (!ath_tx_setup(sc, WME_AC_BK, AR5K_WME_AC_BK)) { - printk(KERN_ERR "unable to setup xmit queue for %s traffic!\n", - ieee80211_wme_acnames[WME_AC_BK]); - error = EIO; - goto bad2; +#endif + tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); + sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); + if (IS_ERR(sc->txq)) { + dev_err(&pdev->dev, "can't setup xmit queue\n"); + ret = PTR_ERR(sc->txq); + goto err_queues; } +#ifdef BLE if (!ath_tx_setup(sc, WME_AC_BE, AR5K_WME_AC_BE) || !ath_tx_setup(sc, WME_AC_VI, AR5K_WME_AC_VI) || !ath_tx_setup(sc, WME_AC_VO, AR5K_WME_AC_VO)) { @@ -1397,7 +1547,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) return 0; err_queues: ath_tx_cleanup(sc); -err_desc: +//err_desc: ath_desc_free(sc, pdev); err: return ret; diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 1b7d2c5..9439994 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -109,15 +109,12 @@ struct ath_node { struct ath_buf { struct list_head list; - //int nseg; - int flags; /* tx descriptor flags */ + unsigned int flags; /* tx descriptor flags */ struct ath_desc *desc; /* virtual addr of desc */ dma_addr_t daddr; /* physical addr of desc */ struct sk_buff *skb; /* skbuff for buf */ - dma_addr_t skbaddr; /* physical addr of skb data */ -#ifdef BLE - struct ieee80211_node *bf_node; /* pointer to the node */ -#endif + dma_addr_t skbaddr;/* physical addr of skb data */ + struct ieee80211_tx_control ctl; }; /* @@ -130,36 +127,23 @@ struct ath_buf { * hardware queue). */ struct ath_txq { - u_int axq_qnum; /* hardware q number */ - u_int axq_depth; /* queue depth (stat only) */ - u_int axq_intrcnt; /* interrupt count */ - u32 *axq_link; /* link ptr in last TX desc */ - struct list_head axq_q; /* transmit queue */ - spinlock_t axq_lock; /* lock on q and link */ + unsigned int qnum; /* hardware q number */ + unsigned int intrcnt; /* interrupt count */ + u32 *link; /* link ptr in last TX desc */ + struct list_head q; /* transmit queue */ + spinlock_t lock; /* lock on q and link */ /* * State for patching up CTS when bursting. */ - struct ath_buf *axq_linkbuf; /* va of last buffer */ - struct ath_desc *axq_lastdsWithCTS; - /* first desc of last descriptor - * that contains CTS - */ - struct ath_desc *axq_gatingds; /* final desc of the gating desc - * that determines whether - * lastdsWithCTS has been DMA'ed - * or not - */ + struct ath_buf *linkbuf; /* va of last buffer */ + struct ath_desc *lastdsWithCTS; /* first desc of last descriptor that + * contains CTS */ + struct ath_desc *gatingds; /* final desc of the gating desc that + * determines whether lastdsWithCTS has + * been DMA'ed or not */ + bool setup; }; -#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ - STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ - (_tq)->axq_depth++; \ -} while (0) -#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ - STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ - (_tq)->axq_depth--; \ -} while (0) - #if CHAN_DEBUG #define ATH_CHAN_MAX (26+26+26+200+200) #else @@ -170,7 +154,6 @@ struct ath_softc { struct pci_dev *pdev; /* for dma mapping */ void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ -// struct net_device_stats sc_devstats; /* device statistics */ struct ath_stats stats; /* private statistics */ struct ieee80211_hw *hw; /* IEEE 802.11 common */ struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; @@ -265,40 +248,39 @@ struct ath_softc { u8 pad[64]; } u_rx_rt; int sc_rx_th_len; -#endif struct tasklet_struct fataltq; /* fatal int tasklet */ -#ifdef BLE struct tasklet_struct sc_radartq; /* Radar detection */ #endif unsigned int rxbufsize; /* rx size based on mtu */ struct list_head rxbuf; /* receive buffer */ - struct tasklet_struct rxtq; /* rx intr tasklet */ - struct tasklet_struct rxorntq; /* rxorn intr tasklet */ u32 *rxlink; /* link ptr in last RX desc */ #ifdef BLE + struct tasklet_struct rxtq; /* rx intr tasklet */ + struct tasklet_struct rxorntq; /* rxorn intr tasklet */ +//#ifdef BLE u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ #endif struct list_head txbuf; /* transmit buffer */ spinlock_t txbuflock; /* txbuf lock */ - struct ath_txq txq[AR5K_NUM_TX_QUEUES]; - DECLARE_BITMAP(txqsetup, AR5K_NUM_TX_QUEUES); /* h/w queues setup */ + struct ath_txq txqs[2]; /* beacon and tx*/ #ifdef BLE int sc_tx_timer; /* transmit timeout */ u_int sc_txintrperiod;/* tx interrupt batching */ struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ #endif + struct ath_txq *txq; /* beacon and tx*/ struct tasklet_struct txtq; /* tx intr tasklet */ +#ifdef BLE struct list_head bbuf; /* beacon buffers */ unsigned int bhalq; /* HAL q for outgoing beacons */ -#ifdef BLE u_int sc_bmisscount; /* missed beacon transmits */ u32 sc_ant_tx[8]; /* recent tx frames/antenna */ struct ieee80211_beacon_offsets boff; /* dynamic update state */ -#endif struct ath_txq *cabq; /* tx q for cab frames */ +#endif struct tasklet_struct bmisstq; /* bmiss intr tasklet */ #ifdef BLE struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 6f8f180..c2a109e 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -976,15 +976,15 @@ struct ath_hw { /* * Function pointers */ - bool (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, + int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); - bool (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool, const struct ath_desc *); + int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); @@ -1012,10 +1012,10 @@ void ath5k_hw_start_rx(struct ath_hw *hal); int ath5k_hw_stop_rx_dma(struct ath_hw *hal); u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); -bool ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); +int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); +int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); /* Interrupt handling */ bool ath5k_hw_is_intr_pending(struct ath_hw *hal); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 0fef518..6232ce0 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -42,22 +42,22 @@ static int ath5k_hw_nic_reset(struct ath_hw *, u32); static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool); static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int); static int ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int); -static bool ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, +static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool, const struct ath_desc *); +static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); static int ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *); -static bool ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, +static int ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); -static bool ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool, const struct ath_desc *); +static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, struct ath_desc *); @@ -1457,8 +1457,7 @@ void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) * Start DMA transmit for a specific queue * (see also QCU/DCU functions) */ -bool -ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) +int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) { u32 tx_queue; @@ -1467,10 +1466,9 @@ ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) /* Return if queue is declared inactive */ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return false; + return -EIO; if (hal->ah_version == AR5K_AR5210) { - tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); /* @@ -1492,20 +1490,20 @@ ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) AR5K_BSR); break; default: - return false; + return -EINVAL; } /* Start queue */ ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); } else { /* Return if queue is disabled */ if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXD, queue)) - return false; + return -EIO; /* Start queue */ AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXE, queue); } - return true; + return 0; } /* @@ -1606,8 +1604,7 @@ ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) * Set the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) */ -bool -ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) +int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) { u16 tx_reg; AR5K_TRACE; @@ -1627,7 +1624,7 @@ ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) tx_reg = AR5K_NOQCU_TXDP1; break; default: - return false; + return -EINVAL; } } else { /* @@ -1636,7 +1633,7 @@ ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) * (this won't work if the queue is still active) */ if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, queue)) - return false; + return -EIO; tx_reg = AR5K_QUEUE_TXDP(queue); } @@ -1644,7 +1641,7 @@ ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) /* Set descriptor pointer */ ath5k_hw_reg_write(hal, phys_addr, tx_reg); - return true; + return 0; } /* @@ -3725,22 +3722,20 @@ ath5k_hw_get_slot_time(struct ath_hw *hal) /* * Initialize the 2-word tx descriptor on 5210/5211 */ -static bool +static int ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, - unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, - unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) + unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, + unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, + unsigned int key_index, unsigned int antenna_mode, unsigned int flags, + unsigned int rtscts_rate, unsigned int rtscts_duration) { u32 frame_type; struct ath5k_hw_2w_tx_desc *tx_desc; tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; - /* - * Validate input - */ if (tx_tries0 == 0) - return false; + return -EINVAL; /* Initialize control descriptor */ tx_desc->tx_control_0 = 0; @@ -3749,17 +3744,18 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, /* Setup control descriptor */ /*Verify packet length*/ - if ((tx_desc->tx_control_0 = (packet_length & - AR5K_2W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return false; + tx_desc->tx_control_0 = pkt_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; + if (tx_desc->tx_control_0 != pkt_len) + return -EINVAL; /* * Verify header length * XXX: I only found that on 5210 code, does it work on 5211 ? */ - if (hal->ah_version == AR5K_AR5210) - if ((tx_desc->tx_control_0 = (header_length & - AR5K_2W_TX_DESC_CTL0_HEADER_LEN)) != header_length) - return false; + if (hal->ah_version == AR5K_AR5210) { + tx_desc->tx_control_0 = hdr_len & AR5K_2W_TX_DESC_CTL0_HEADER_LEN; + if (tx_desc->tx_control_0 != hdr_len) + return -EINVAL; + } /*Diferences between 5210-5211*/ if (hal->ah_version == AR5K_AR5210) { @@ -3816,17 +3812,18 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; } - return true; + return 0; } /* * Initialize the 4-word tx descriptor on 5212 */ -static bool -ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, - unsigned int packet_length, u_int header_length, enum ath5k_pkt_type type, u_int tx_power, - unsigned int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - unsigned int flags, u_int rtscts_rate, u_int rtscts_duration) +static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, + struct ath_desc *desc, unsigned int pkt_len, unsigned int hdr_len, + enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, + unsigned int tx_tries0, unsigned int key_index, + unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate, + unsigned int rtscts_duration) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -3838,7 +3835,7 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, * Validate input */ if (tx_tries0 == 0) - return false; + return -EINVAL; /* Initialize status descriptor */ tx_desc->tx_control_0 = 0; @@ -3847,20 +3844,18 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, tx_desc->tx_control_3 = 0; /* Setup status descriptor */ - if ((tx_desc->tx_control_0 = (packet_length & - AR5K_4W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) - return false; + tx_desc->tx_control_0 = pkt_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN; + if (tx_desc->tx_control_0 != pkt_len) + return -EINVAL; tx_desc->tx_control_0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); - tx_desc->tx_control_1 = - AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); - tx_desc->tx_control_2 = - AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); - tx_desc->tx_control_3 = - tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; + tx_desc->tx_control_1 = AR5K_REG_SM(type, + AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); + tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); + tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; #define _TX_FLAGS(_c, _flag) \ if (flags & AR5K_TXDESC_##_flag) \ @@ -3880,28 +3875,24 @@ ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, * WEP crap */ if (key_index != AR5K_TXKEYIX_INVALID) { - tx_desc->tx_control_0 |= - AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; - tx_desc->tx_control_1 |= - AR5K_REG_SM(key_index, - AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); + tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; + tx_desc->tx_control_1 |= AR5K_REG_SM(key_index, + AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); } /* * RTS/CTS */ if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { - if ((flags & AR5K_TXDESC_RTSENA) && - (flags & AR5K_TXDESC_CTSENA)) - return false; - tx_desc->tx_control_2 |= - rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION; - tx_desc->tx_control_3 |= - AR5K_REG_SM(rtscts_rate, - AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); + if ((flags & AR5K_TXDESC_RTSENA) &&(flags & AR5K_TXDESC_CTSENA)) + return -EINVAL; + tx_desc->tx_control_2 |= rtscts_duration & + AR5K_4W_TX_DESC_CTL2_RTS_DURATION; + tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate, + AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); } - return true; + return 0; } /* @@ -3942,9 +3933,9 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, /* * Fill the 2-word tx descriptor on 5210/5211 */ -static bool -ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, - unsigned int segment_length, bool first_segment, bool last_segment, const struct ath_desc *last_desc) +static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, + struct ath_desc *desc, unsigned int segment_length, + bool first_segment, bool last_segment) { struct ath5k_hw_2w_tx_desc *tx_desc; @@ -3954,9 +3945,9 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); /* Validate segment length and initialize the descriptor */ - if ((tx_desc->tx_control_1 = (segment_length & - AR5K_2W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return false; + tx_desc->tx_control_1 = segment_length & AR5K_2W_TX_DESC_CTL1_BUF_LEN; + if (tx_desc->tx_control_1 != segment_length) + return -EINVAL; if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN; @@ -3964,17 +3955,16 @@ ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, if (last_segment != true) tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE; - return true; + return 0; } /* * Fill the 4-word tx descriptor on 5212 * XXX: Added an argument *last_desc -need revision */ -static bool -ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, - unsigned int segment_length, bool first_segment, bool last_segment, - const struct ath_desc *last_desc) +static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, + struct ath_desc *desc, unsigned int segment_length, + bool first_segment, bool last_segment) { struct ath5k_hw_4w_tx_desc *tx_desc; struct ath5k_hw_tx_status *tx_status; @@ -3987,9 +3977,9 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status)); /* Validate segment length and initialize the descriptor */ - if ((tx_desc->tx_control_1 = (segment_length & - AR5K_4W_TX_DESC_CTL1_BUF_LEN)) != segment_length) - return false; + tx_desc->tx_control_1 = segment_length & AR5K_4W_TX_DESC_CTL1_BUF_LEN; + if (tx_desc->tx_control_1 != segment_length) + return -EINVAL; if (first_segment != true) tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN; @@ -3997,7 +3987,7 @@ ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, if (last_segment != true) tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE; - return true; + return 0; } /* @@ -4019,40 +4009,31 @@ static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, /* * Get descriptor status */ - desc->ds_us.tx.ts_tstamp = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); - desc->ds_us.tx.ts_shortretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); - desc->ds_us.tx.ts_longretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); + desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); + desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); /*TODO: desc->ds_us.tx.ts_virtcol + test*/ - desc->ds_us.tx.ts_seqnum = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_SEQ_NUM); - desc->ds_us.tx.ts_rssi = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); desc->ds_us.tx.ts_antenna = 1; desc->ds_us.tx.ts_status = 0; - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_0, - AR5K_2W_TX_DESC_CTL0_XMIT_RATE); + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0, + AR5K_2W_TX_DESC_CTL0_XMIT_RATE); - if ((tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { + if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; - if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; - if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FILTERED) + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } @@ -4079,69 +4060,55 @@ static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, /* * Get descriptor status */ - desc->ds_us.tx.ts_tstamp = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); - desc->ds_us.tx.ts_shortretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); - desc->ds_us.tx.ts_longretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); - desc->ds_us.tx.ts_seqnum = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_SEQ_NUM); - desc->ds_us.tx.ts_rssi = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); + desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); + desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & - AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; + AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; desc->ds_us.tx.ts_status = 0; switch (AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { + AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { case 0: desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & - AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; + AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; break; case 1: - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); - desc->ds_us.tx.ts_longretry += - AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); + desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); break; case 2: - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); - desc->ds_us.tx.ts_longretry += - AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); + desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); break; case 3: - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); - desc->ds_us.tx.ts_longretry += - AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); + desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); break; } - if ((tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { + if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; - if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; - if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FILTERED) + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } commit c1efdcfb9aa0337cb811b419b2c05100112aaf23 Author: Jiri Slaby Date: Fri Jul 6 23:08:00 2007 +0200 remove QNUM printk diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index cf6b618..4844e21 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1313,7 +1313,6 @@ static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, ath5k_hw_release_tx_queue(ah, qnum); return ERR_PTR(-EINVAL); } - printk(KERN_DEBUG "QNUM: %d\n", qnum); txq = &sc->txqs[qnum]; if (!txq->setup) { txq->qnum = qnum; commit 1775e4b72abfcf03894a6c64d811fc6bc456f065 Author: Jiri Slaby Date: Fri Jul 6 23:17:40 2007 +0200 remove other tx setups diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 4844e21..b93d0ed 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1440,42 +1440,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto err_queues; } #ifdef BLE - if (!ath_tx_setup(sc, WME_AC_BE, AR5K_WME_AC_BE) || - !ath_tx_setup(sc, WME_AC_VI, AR5K_WME_AC_VI) || - !ath_tx_setup(sc, WME_AC_VO, AR5K_WME_AC_VO)) { - /* - * Not enough hardware tx queues to properly do WME; - * just punt and assign them all to the same h/w queue. - * We could do a better job of this if, for example, - * we allocate queues when we switch from station to - * AP mode. - */ - if (sc->sc_ac2q[WME_AC_VI] != NULL) - ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); - if (sc->sc_ac2q[WME_AC_BE] != NULL) - ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); - sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; - sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; - sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; - } - - /* - * Special case certain configurations. Note the - * CAB queue is handled by these specially so don't - * include them when checking the txq setup mask. - */ - switch (sc->sc_txqsetup &~ (1<sc_cabq->axq_qnum)) { - case 0x01: - ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet_q0, dev); - break; - case 0x0f: - ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet_q0123, dev); - break; - default: - ATH_INIT_TQUEUE(&sc->sc_txtq, ath_tx_tasklet, dev); - break; - } - /* * Setup rate control. Some rate control modules * call back to change the anntena state so expose commit 07c9738dcc3090d264fe80b81d842c730e701067 Author: Jiri Slaby Date: Fri Jul 6 23:20:47 2007 +0200 move ath_rxbuf_init after tasklets diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index b93d0ed..4665fa4 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -139,6 +139,68 @@ static void ath_printtxbuf(struct ath_buf *bf, int done) } #endif +static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) +{ + struct ieee80211_tx_status txs = {}; + struct ath_buf *bf, *bf0; + struct ath_desc *ds; + struct sk_buff *skb; + int ret; + + spin_lock(&txq->lock); + list_for_each_entry_safe(bf, bf0, &txq->q, list) { + ds = bf->desc; + + ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); + if (ret == -EINPROGRESS) + break; + else if (ret) { + printk(KERN_ERR "ath: error %d while processing " + "queue %u\n", ret, txq->qnum); + break; + } + + skb = bf->skb; + bf->skb = NULL; + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, + PCI_DMA_TODEVICE); + + txs.control = bf->ctl; + txs.retry_count = ds->ds_txstat.ts_shortretry + + ds->ds_txstat.ts_longretry; + if (ds->ds_txstat.ts_status) { + if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { + txs.excessive_retries = 1; + } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { + txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; + } + } else { + txs.flags |= IEEE80211_TX_STATUS_ACK; + txs.ack_signal = ds->ds_txstat.ts_rssi; + } + + ieee80211_tx_status(sc->hw, skb, &txs); + + printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); + + spin_lock(&sc->txbuflock); + list_move_tail(&bf->list, &sc->txbuf); + spin_unlock(&sc->txbuflock); + } + if (list_empty(&txq->q)) + txq->link = NULL; + spin_unlock(&txq->lock); +} + +static void ath_tasklet_tx(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + ath_tx_processq(sc, sc->txq); + + ieee80211_wake_queue(sc->hw, 0); +} + static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) { struct ath_hw *ah = sc->ah; @@ -209,68 +271,6 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) return 0; } -static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) -{ - struct ieee80211_tx_status txs = {}; - struct ath_buf *bf, *bf0; - struct ath_desc *ds; - struct sk_buff *skb; - int ret; - - spin_lock(&txq->lock); - list_for_each_entry_safe(bf, bf0, &txq->q, list) { - ds = bf->desc; - - ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); - if (ret == -EINPROGRESS) - break; - else if (ret) { - printk(KERN_ERR "ath: error %d while processing " - "queue %u\n", ret, txq->qnum); - break; - } - - skb = bf->skb; - bf->skb = NULL; - pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, - PCI_DMA_TODEVICE); - - txs.control = bf->ctl; - txs.retry_count = ds->ds_txstat.ts_shortretry + - ds->ds_txstat.ts_longretry; - if (ds->ds_txstat.ts_status) { - if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { - txs.excessive_retries = 1; - } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { - txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; - } - } else { - txs.flags |= IEEE80211_TX_STATUS_ACK; - txs.ack_signal = ds->ds_txstat.ts_rssi; - } - - ieee80211_tx_status(sc->hw, skb, &txs); - - printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); - - spin_lock(&sc->txbuflock); - list_move_tail(&bf->list, &sc->txbuf); - spin_unlock(&sc->txbuflock); - } - if (list_empty(&txq->q)) - txq->link = NULL; - spin_unlock(&txq->lock); -} - -static void ath_tasklet_tx(unsigned long data) -{ - struct ath_softc *sc = (void *)data; - - ath_tx_processq(sc, sc->txq); - - ieee80211_wake_queue(sc->hw, 0); -} - /* * Calculate the receive filter according to the * operating mode and state: commit e01d05d5015d1324379bc7e47f9cda524d753605 Author: Jiri Slaby Date: Fri Jul 6 23:23:59 2007 +0200 make "changing txpower to" DEBUG dependent diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 6232ce0..a8dd473 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -5659,7 +5659,9 @@ int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) struct ieee80211_channel *channel = &hal->ah_current_channel; AR5K_TRACE; +#ifdef AR5K_DEBUG AR5K_PRINTF("changing txpower to %d\n",power); +#endif return ath5k_hw_txpower(hal, channel, power); } commit 09f4238c9cd1b7460cd615a659f78acdf086f094 Author: Jiri Slaby Date: Sat Jul 7 11:49:51 2007 +0200 implement rx diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 4665fa4..534b868 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -181,7 +181,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) ieee80211_tx_status(sc->hw, skb, &txs); - printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); +// printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); spin_lock(&sc->txbuflock); list_move_tail(&bf->list, &sc->txbuf); @@ -271,6 +271,113 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) return 0; } +static void ath_tasklet_rx(unsigned long data) +{ + struct ieee80211_rx_status rxs = {}; + struct sk_buff *skb; + struct ath_softc *sc = (void *)data; + struct ath_buf *bf; + struct ath_desc *ds; + u16 len; + u8 stat; + int ret; + + spin_lock(&sc->rxbuflock); + do { + if (list_empty(&sc->rxbuf)) { + if (net_ratelimit()) + printk(KERN_WARNING "ath: empty rx buf pool\n"); + break; + } + bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); + BUG_ON(bf->skb == NULL); + skb = bf->skb; + ds = bf->desc; + if (ds->ds_link == bf->daddr) /* this is the end */ + break; + + ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); + if (ret == -EINPROGRESS) + break; + else if (ret) { + if (net_ratelimit()) + printk(KERN_ERR "ath: error in processing rx " + "descriptor\n"); + return; + } + + if (ds->ds_rxstat.rs_more) { + if (net_ratelimit()) + printk(KERN_INFO "ath: unsupported jumbo\n"); + goto next; + } + + stat = ds->ds_rxstat.rs_status; + if (stat) { + if (stat & AR5K_RXERR_CRC) + sc->stats.ast_rx_crcerr++; + if (stat & AR5K_RXERR_FIFO) + sc->stats.ast_rx_fifoerr++; + if (stat & AR5K_RXERR_PHY) { + sc->stats.ast_rx_phyerr++; + sc->stats.ast_rx_phy + [ds->ds_rxstat.rs_phyerr & 0x1f]++; + goto next; + } + if (stat & AR5K_RXERR_DECRYPT) { + /* + * Decrypt error. If the error occurred + * because there was no hardware key, then + * let the frame through so the upper layers + * can process it. This is necessary for 5210 + * parts which have no way to setup a ``clear'' + * key cache entry. + * + * XXX do key cache faulting + */ + if (ds->ds_rxstat.rs_keyix == + AR5K_RXKEYIX_INVALID) + goto accept; + sc->stats.ast_rx_badcrypt++; + } + if (stat & AR5K_RXERR_MIC) { + rxs.flag |= RX_FLAG_MMIC_ERROR; + sc->stats.ast_rx_badmic++; + goto accept; + } + + printk(KERN_DEBUG "throwing away: %x\n", stat); + goto next; + } +accept: + len = ds->ds_rxstat.rs_datalen; + pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len, + PCI_DMA_FROMDEVICE); + pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, + PCI_DMA_FROMDEVICE); + bf->skb = NULL; + + skb_put(skb, len); + + sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; + + rxs.mactime = ds->ds_rxstat.rs_tstamp; + rxs.freq = sc->curchan->freq; + rxs.channel = sc->curchan->chan; + rxs.phymode = sc->curmode; + rxs.ssi = ds->ds_rxstat.rs_rssi; + rxs.antenna = ds->ds_rxstat.rs_antenna; + rxs.rate = ds->ds_rxstat.rs_rate; + rxs.flag |= RX_FLAG_DECRYPTED; + +// printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); + __ieee80211_rx(sc->hw, skb, &rxs); +next: + list_move_tail(&bf->list, &sc->rxbuf); + } while (ath_rxbuf_init(sc, bf) == 0); + spin_unlock(&sc->rxbuflock); +} + /* * Calculate the receive filter according to the * operating mode and state: @@ -338,7 +445,6 @@ static void ath_mode_init(struct ath_softc *sc) static int ath_startrecv(struct ath_softc *sc) { struct ath_hw *ah = sc->ah; - struct list_head *pos; struct ath_buf *bf; int ret; @@ -348,14 +454,18 @@ static int ath_startrecv(struct ath_softc *sc) __func__, sc->cachelsz, sc->rxbufsize); sc->rxlink = NULL; - list_for_each(pos, &sc->rxbuf) { - bf = list_entry(pos, struct ath_buf, list); + + spin_lock_bh(&sc->rxbuflock); + list_for_each_entry(bf, &sc->rxbuf, list) { ret = ath_rxbuf_init(sc, bf); - if (ret != 0) + if (ret != 0) { + spin_unlock_bh(&sc->rxbuflock); goto err; + } } - bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); + spin_unlock_bh(&sc->rxbuflock); + ath5k_hw_put_rx_buf(ah, bf->daddr); ath5k_hw_start_rx(ah); /* enable recv descriptors */ ath_mode_init(sc); /* set filters, etc. */ @@ -436,8 +546,6 @@ done: */ static void ath_stoprecv(struct ath_softc *sc) { -#define PA2DESC(_sc, _pa) ((struct ath_desc *)((caddr_t)(_sc)->desc + \ - ((_pa) - (_sc)->desc_daddr))) struct ath_hw *ah = sc->ah; ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ @@ -446,7 +554,6 @@ static void ath_stoprecv(struct ath_softc *sc) mdelay(3); /* 3ms is long enough for 1 frame */ #ifdef AR_DEBUG if (sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow - struct list_head *pos; struct ath_desc *ds; struct ath_buf *bf; int status; @@ -454,18 +561,17 @@ static void ath_stoprecv(struct ath_softc *sc) printk(KERN_DEBUG "%s: rx queue %x, link %p\n", __func__, ath5k_hw_get_rx_buf(ah), sc->rxlink); - list_for_each(pos, &sc->rxbuf) { - bf = list_entry(pos, struct ath_buf, list); + spin_lock_bh(&sc->rxbuflock); + list_for_each_entry(bf, &sc->rxbuf, list) { ds = bf->desc; - status = ah->ah_proc_rx_desc(ah, ds, bf->daddr, - PA2DESC(sc, ds->ds_link)); + status = ah->ah_proc_rx_desc(ah, ds); if (!status || (sc->debug & ATH_DEBUG_FATAL)) ath_printrxbuf(bf, status == 0); } + spin_unlock_bh(&sc->rxbuflock); } #endif sc->rxlink = NULL; /* just in case */ -#undef PA2DESC } static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) @@ -725,7 +831,7 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, ath5k_hw_tx_start(ah, txq->qnum); spin_unlock_bh(&txq->lock); - printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); +// printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); return 0; err_unmap: @@ -884,8 +990,8 @@ static irqreturn_t ath_intr(int irq, void *dev_id) /* bump tx trigger level */ ath5k_hw_update_tx_triglevel(ah, true); } -/* if (status & AR5K_INT_RX) - tasklet_schedule(&sc->rxtq);*/ + if (status & AR5K_INT_RX) + tasklet_schedule(&sc->rxtq); if (status & AR5K_INT_TX) tasklet_schedule(&sc->txtq); /* if (status & AR5K_INT_BMISS) { @@ -1229,11 +1335,9 @@ err: static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, struct list_head *head) { - struct list_head *pos; struct ath_buf *bf; - list_for_each(pos, head) { - bf = list_entry(pos, struct ath_buf, list); + list_for_each_entry(bf, head, list) { if (bf->skb) { pci_unmap_single(pdev, bf->skbaddr, sc->rxbufsize, PCI_DMA_FROMDEVICE); @@ -1241,8 +1345,6 @@ static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, bf->skb = NULL; } } - - INIT_LIST_HEAD(head); } static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) @@ -1432,13 +1534,15 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto err_queues; } #endif - tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); if (IS_ERR(sc->txq)) { dev_err(&pdev->dev, "can't setup xmit queue\n"); ret = PTR_ERR(sc->txq); goto err_queues; } + + tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); + tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); #ifdef BLE /* * Setup rate control. Some rate control modules @@ -1644,6 +1748,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, sc->iobase = mem; sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ mutex_init(&sc->lock); + spin_lock_init(&sc->rxbuflock); spin_lock_init(&sc->txbuflock); /* tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 9439994..5bacf0f 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -253,9 +253,10 @@ struct ath_softc { #endif unsigned int rxbufsize; /* rx size based on mtu */ struct list_head rxbuf; /* receive buffer */ + spinlock_t rxbuflock; u32 *rxlink; /* link ptr in last RX desc */ -#ifdef BLE struct tasklet_struct rxtq; /* rx intr tasklet */ +#ifdef BLE struct tasklet_struct rxorntq; /* rxorn intr tasklet */ //#ifdef BLE u8 sc_defant; /* current default antenna */ @@ -263,8 +264,8 @@ struct ath_softc { #endif struct list_head txbuf; /* transmit buffer */ - spinlock_t txbuflock; /* txbuf lock */ - struct ath_txq txqs[2]; /* beacon and tx*/ + spinlock_t txbuflock; + struct ath_txq txqs[2]; /* beacon and tx */ #ifdef BLE int sc_tx_timer; /* transmit timeout */ u_int sc_txintrperiod;/* tx interrupt batching */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index c2a109e..c24480b 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -986,8 +986,7 @@ struct ath_hw { int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool); int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); - int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *, u32, - struct ath_desc *); + int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *); }; /* @@ -1074,7 +1073,7 @@ bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); /* Hardware Descriptor Functions */ /* RX Descriptor */ -bool ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); +int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); /* GPIO Functions */ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); bool ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index a8dd473..7d246e0 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -59,10 +59,8 @@ static int ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, unsigned int, bool, bool); static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); -static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *, u32, - struct ath_desc *); -static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *, u32, - struct ath_desc *); +static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *); +static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *); static int ath5k_hw_get_capabilities(struct ath_hw *); static int ath5k_eeprom_init(struct ath_hw *); @@ -4122,8 +4120,7 @@ static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, /* * Initialize an rx descriptor */ -bool -ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, +int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags) { struct ath5k_rx_desc *rx_desc; @@ -4144,22 +4141,22 @@ ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, rx_desc->rx_control_0 = 0; rx_desc->rx_control_1 = 0; - /*Setup descriptor*/ - if ((rx_desc->rx_control_1 = (size & - AR5K_DESC_RX_CTL1_BUF_LEN)) != size) - return false; + /* Setup descriptor */ + rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; + if (rx_desc->rx_control_1 != size) + return -EINVAL; if (flags & AR5K_RXDESC_INTREQ) rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; - return true; + return 0; } /* * Proccess the rx status descriptor on 5210/5211 */ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, - struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) + struct ath_desc *desc) { struct ath5k_hw_old_rx_status *rx_status; @@ -4233,7 +4230,7 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, * Proccess the rx status descriptor on 5212 */ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, - struct ath_desc *desc, u32 phys_addr, struct ath_desc *next) + struct ath_desc *desc) { struct ath5k_hw_new_rx_status *rx_status; struct ath5k_hw_rx_error *rx_err; @@ -4271,10 +4268,8 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, /* * Key table status */ - if (rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID) - desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, + if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID) + desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX); else desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; @@ -4284,12 +4279,10 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, */ if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) + if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; - if (rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) { + if (rx_status->rx_status_1 &AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR){ desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; desc->ds_us.rx.rs_phyerr = AR5K_REG_MS(rx_err->rx_error_1, commit 7d9ef476cd315bf2a767a763f605ba3c3599dbe4 Author: Jiri Slaby Date: Sat Jul 7 11:53:05 2007 +0200 no conf_tx diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 534b868..fbe5e30 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -906,13 +906,6 @@ static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) return ath_chan_set(sc, conf->chan); } -static int ath_conf_tx(struct ieee80211_hw *hw, int queue, - const struct ieee80211_tx_queue_params *params) -{ - printk("%s\n", __FUNCTION__); - return 0; -} - static struct ieee80211_ops ath_hw_ops = { .tx = ath_tx, .reset = NULL, @@ -921,11 +914,11 @@ static struct ieee80211_ops ath_hw_ops = { .add_interface = NULL, .remove_interface = NULL, .config = ath_config, - .config_interface = NULL, - .set_key = NULL, - .get_stats = NULL, - .conf_tx = ath_conf_tx, -/* .get_tx_stats = , +/* .config_interface = , + .set_key = , + .get_stats = , + .conf_tx = , + .get_tx_stats = , .get_tsf = , .reset_tsf = , .beacon_update = ,*/ commit 7754c3e70bda57a852286efb9ec8ca518a4efb05 Author: Jiri Slaby Date: Sat Jul 7 11:53:41 2007 +0200 remove debug printk diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index fbe5e30..81bf2e3 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -346,7 +346,6 @@ static void ath_tasklet_rx(unsigned long data) goto accept; } - printk(KERN_DEBUG "throwing away: %x\n", stat); goto next; } accept: commit d521d76d4f18edbb6bf3044fded693ed6075e2c4 Author: Jiri Slaby Date: Sat Jul 7 14:13:27 2007 +0200 set ieee80211_hw flags (FCS included in RX) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 81bf2e3..1783a84 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1728,6 +1728,8 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, } SET_IEEE80211_DEV(hw, &pdev->dev); + hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_WEP_INCLUDE_IV | + IEEE80211_HW_DATA_NULLFUNC_ACK; sc = hw->priv; sc->hw = hw; commit ac7f2c9e146f130b45c32c2496274fbd79e6006c Author: Jiri Slaby Date: Sat Jul 7 14:13:57 2007 +0200 remove tasklets init diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 1783a84..dc4dba6 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1745,13 +1745,6 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, spin_lock_init(&sc->rxbuflock); spin_lock_init(&sc->txbuflock); -/* tasklet_init(&sc->sc_rxtq, ath_rx_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_rxorntq, ath_rxorn_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_fataltq, ath_fatal_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_bmisstq, ath_bmiss_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_bstuckq, ath_bstuck_tasklet, (unsigned long)hw); - tasklet_init(&sc->sc_radartq, ath_radar_tasklet, (unsigned long)hw);*/ - pci_set_drvdata(pdev, hw); ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc); commit f167369d2b67f13e50488b87a06eac9da35bfe18 Author: Jiri Slaby Date: Sat Jul 7 14:15:05 2007 +0200 hdrlen & 3 test add and cleanup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index dc4dba6..4614cb1 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -356,6 +356,9 @@ accept: PCI_DMA_FROMDEVICE); bf->skb = NULL; + if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) + printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + skb_put(skb, len); sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; @@ -800,9 +803,9 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, if (ctl->flags & IEEE80211_TXCTL_NO_ACK) flags |= AR5K_TXDESC_NOACK; - if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) { - printk(KERN_DEBUG "len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); - } + if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) + printk(KERN_DEBUG "tx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + hdrpad = 0; pktlen = skb->len - hdrpad + FCS_LEN; ret = ah->ah_setup_tx_desc(ah, ds, pktlen, commit 69950ecb93318b4a887a1e493db8c48e238bd908 Author: Jiri Slaby Date: Sat Jul 7 14:16:05 2007 +0200 remove RX_FLAG_DECRYPTED diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 4614cb1..086d5aa 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -370,7 +370,7 @@ accept: rxs.ssi = ds->ds_rxstat.rs_rssi; rxs.antenna = ds->ds_rxstat.rs_antenna; rxs.rate = ds->ds_rxstat.rs_rate; - rxs.flag |= RX_FLAG_DECRYPTED; +// rxs.flag |= RX_FLAG_DECRYPTED; // printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); __ieee80211_rx(sc->hw, skb, &rxs); commit a2af4e7b6948a9a6647ff59e84ba16da1de2e1d5 Author: Jiri Slaby Date: Sat Jul 7 14:22:37 2007 +0200 ath_dump_skb diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 086d5aa..9047f78 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -37,6 +37,7 @@ #include "if_athvar.h" #define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ +#define ATH_DUMP_SKB 0 /* show skb contents */ #define AR_DEBUG 1 #define KASSERT(exp, msg...) do { \ @@ -139,6 +140,23 @@ static void ath_printtxbuf(struct ath_buf *bf, int done) } #endif +#ifdef ATH_DUMP_SKB +static void ath_dump_skb(struct sk_buff *skb, unsigned int rx) +{ + unsigned int a; + + printk(KERN_DEBUG "%c", rx ? 'r' : 't'); + for (a = 0; a < min(200U, skb->len) + 4; a++) { + printk("%.2x %s", skb->data[a], ((a+1) % 8) ? "" : " "); + if (!((a+1) % 16)) + printk("\n" KERN_DEBUG " "); + } + printk("\n"); +} +#else +static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) {} +#endif + static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) { struct ieee80211_tx_status txs = {}; @@ -373,6 +391,8 @@ accept: // rxs.flag |= RX_FLAG_DECRYPTED; // printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); + ath_dump_skb(skb, 1); + __ieee80211_rx(sc->hw, skb, &rxs); next: list_move_tail(&bf->list, &sc->rxbuf); @@ -847,16 +867,8 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, struct ath_softc *sc = hw->priv; struct ath_buf *bf; unsigned long flags; -// unsigned int a; -/* skb_pad(skb, 4); - printk(KERN_DEBUG "%p/%p, %p/%p, %u, %u\n" KERN_DEBUG, skb->head, skb->data, skb->tail, skb->end, skb->len, skb->data_len); - for (a = 0; a < min(200U, skb->len) + 4; a++) { - printk("%.2x %s", skb->data[a], ((a+1) % 8) ? "" : " "); - if (!((a+1) % 16)) - printk("\n" KERN_DEBUG); - } - printk("\n");*/ + ath_dump_skb(skb, 0); spin_lock_irqsave(&sc->txbuflock, flags); if (list_empty(&sc->txbuf)) { commit 222faca822a3b79fa1da46e147f744d7718dd310 Author: Jiri Slaby Date: Sat Jul 7 14:23:09 2007 +0200 remove kassert diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 9047f78..c26e765 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -40,13 +40,6 @@ #define ATH_DUMP_SKB 0 /* show skb contents */ #define AR_DEBUG 1 -#define KASSERT(exp, msg...) do { \ - if (unlikely(!(exp))) { \ - printk(msg); \ - BUG(); \ - } \ -} while (0) - #define DPRINTF(sc, _m, _fmt...) do { \ if ((sc->debug & (_m)) && net_ratelimit()) \ printk(_fmt); \ @@ -1247,7 +1240,7 @@ static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) const struct ath5k_rate_table* rt=ath5k_hw_get_rate_table(sc->ah, mode); unsigned int i, j; - KASSERT(rt != NULL, "no h/w rate set for phy mode %u", mode); + BUG_ON(rt == NULL); memset(sc->hwmap, 0, sizeof(sc->hwmap)); for (i = 0; i < 32; i++) { commit 05dba3f9c7511adbabc68b16e86514f04c28be26 Author: Jiri Slaby Date: Sat Jul 7 14:26:11 2007 +0200 #ifdef DUMP_SKB -> #if ... diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c26e765..c81b161 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -133,7 +133,7 @@ static void ath_printtxbuf(struct ath_buf *bf, int done) } #endif -#ifdef ATH_DUMP_SKB +#if ATH_DUMP_SKB static void ath_dump_skb(struct sk_buff *skb, unsigned int rx) { unsigned int a; commit 5ba0537c5f3b8d42ac18fffc6e204e5d02a824e3 Author: Jiri Slaby Date: Sat Jul 7 14:32:43 2007 +0200 add another struct hw values diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c81b161..c7d6a9e 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1738,6 +1738,9 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, SET_IEEE80211_DEV(hw, &pdev->dev); hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_WEP_INCLUDE_IV | IEEE80211_HW_DATA_NULLFUNC_ACK; + hw->extra_tx_headroom = 2; + hw->channel_change_time = 5000; + hw->max_rssi = 127; /* FIXME: get a real value for this. */ sc = hw->priv; sc->hw = hw; commit 9079f2d51a912eb00c698b4e2341c04df75f2332 Author: Jiri Slaby Date: Sun Jul 8 10:09:07 2007 +0200 turn CHAN_DEBUG off diff --git a/openhal/ath5k.h b/openhal/ath5k.h index c24480b..e0cc2c4 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -23,7 +23,7 @@ * long and results timeouts). It's also illegal to tune to some of the * supported frequencies in some countries, so use this at your own risk, * you've been warned. */ -#define CHAN_DEBUG 1 +#define CHAN_DEBUG 0 /* Uncomment this for debuging (warning that it results in TOO much output) */ /*#define AR5K_DEBUG 1 */ commit 64c2d04412281088407bfc614502a61ae5cc9124 Author: Jiri Slaby Date: Wed Jul 11 22:00:19 2007 +0200 set_curmode instead of setting only the sc->curmode diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index c7d6a9e..69bc89a 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -738,6 +738,64 @@ static int ath_stop_hw(struct ath_softc *sc) return ret; } +static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) +{ +#ifdef BLE + /* from Atheros NDIS driver, w/ permission */ + static const struct { + u16 rate; /* tx/rx 802.11 rate */ + u16 timeOn; /* LED on time (ms) */ + u16 timeOff; /* LED off time (ms) */ + } blinkrates[] = { + { 108, 40, 10 }, + { 96, 44, 11 }, + { 72, 50, 13 }, + { 48, 57, 14 }, + { 36, 67, 16 }, + { 24, 80, 20 }, + { 22, 100, 25 }, + { 18, 133, 34 }, + { 12, 160, 40 }, + { 10, 200, 50 }, + { 6, 240, 58 }, + { 4, 267, 66 }, + { 2, 400, 100 }, + { 0, 500, 130 } + }; +#endif + const struct ath5k_rate_table* rt=ath5k_hw_get_rate_table(sc->ah, mode); +// unsigned int i, j; + + BUG_ON(rt == NULL); +#ifdef BLE + memset(sc->hwmap, 0, sizeof(sc->hwmap)); + for (i = 0; i < 32; i++) { + u8 ix = rt->rate_code_to_index[i]; + if (ix == 0xff) { + sc->hwmap[i].ledon = msecs_to_jiffies(500); + sc->hwmap[i].ledoff = msecs_to_jiffies(130); + continue; + } + sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; + if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == + MODULATION_OFDM) + sc->hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; + /* receive frames include FCS */ + sc->hwmap[i].rxflags = sc->hwmap[i].txflags | + IEEE80211_RADIOTAP_F_FCS; + /* setup blink rate table to avoid per-packet lookup */ + for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) + if (blinkrates[j].rate == /* XXX why 7f? */ + (rt->rates[ix].dot11_rate & 0x7f)) + break; + + sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].timeOn); + sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].timeOff); + } +#endif + sc->curmode = mode; +} + /* * Set/change channels. If the channel is really being changed, * it's done by reseting the chip. To accomplish this we must @@ -908,7 +966,7 @@ static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) { struct ath_softc *sc = hw->priv; - sc->curmode = conf->phymode; + ath_setcurmode(sc, conf->phymode); return ath_chan_set(sc, conf->chan); } @@ -1213,63 +1271,6 @@ err: return ret; } -static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) -{ - /* from Atheros NDIS driver, w/ permission */ - static const struct { - u16 rate; /* tx/rx 802.11 rate */ - u16 timeOn; /* LED on time (ms) */ - u16 timeOff; /* LED off time (ms) */ - } blinkrates[] = { - { 108, 40, 10 }, - { 96, 44, 11 }, - { 72, 50, 13 }, - { 48, 57, 14 }, - { 36, 67, 16 }, - { 24, 80, 20 }, - { 22, 100, 25 }, - { 18, 133, 34 }, - { 12, 160, 40 }, - { 10, 200, 50 }, - { 6, 240, 58 }, - { 4, 267, 66 }, - { 2, 400, 100 }, - { 0, 500, 130 } - }; - - const struct ath5k_rate_table* rt=ath5k_hw_get_rate_table(sc->ah, mode); - unsigned int i, j; - - BUG_ON(rt == NULL); - - memset(sc->hwmap, 0, sizeof(sc->hwmap)); - for (i = 0; i < 32; i++) { - u8 ix = rt->rate_code_to_index[i]; - if (ix == 0xff) { - sc->hwmap[i].ledon = msecs_to_jiffies(500); - sc->hwmap[i].ledoff = msecs_to_jiffies(130); - continue; - } - sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; - if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == - MODULATION_OFDM) - sc->hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; - /* receive frames include FCS */ - sc->hwmap[i].rxflags = sc->hwmap[i].txflags | - IEEE80211_RADIOTAP_F_FCS; - /* setup blink rate table to avoid per-packet lookup */ - for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) - if (blinkrates[j].rate == /* XXX why 7f? */ - (rt->rates[ix].dot11_rate & 0x7f)) - break; - - sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].timeOn); - sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].timeOff); - } - - sc->curmode = mode; -} - static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) { struct ath_desc *ds; commit 533d1724955064881e0b3e0b0c503babf5b99dea Author: Jiri Slaby Date: Wed Jul 11 22:01:17 2007 +0200 pass 0xffff as power level (the same as madwifi-old-openhal) diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 69bc89a..7eb8d87 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -881,8 +881,8 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, pktlen = skb->len - hdrpad + FCS_LEN; ret = ah->ah_setup_tx_desc(ah, ds, pktlen, ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, - ctl->power_level > 60 ? 60 : ctl->power_level, ctl->tx_rate, - ctl->retry_limit, AR5K_TXKEYIX_INVALID, 0, flags, 0, 0); + 0xffff, ctl->tx_rate, ctl->retry_limit, AR5K_TXKEYIX_INVALID, 0, + flags, 0, 0); if (ret) goto err_unmap; commit 4814dd766324af7e58e10bb2e4e8ea1da555cf98 Author: Jiri Slaby Date: Wed Jul 11 22:03:03 2007 +0200 comment hwmap in softc diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 5bacf0f..2f58793 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -209,7 +209,7 @@ struct ath_softc { #ifdef BLE u16 sc_curtxpow; /* current tx power limit */ u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ -#endif + struct { // int ieeerate; /* IEEE rate */ u8 rxflags; /* radiotap rx flags */ @@ -217,7 +217,7 @@ struct ath_softc { u16 ledon; /* softled on time */ u16 ledoff; /* softled off time */ } hwmap[32]; /* h/w rate ix mappings */ -#ifdef BLE + u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ #endif commit 504565a760085ed9f2fef9e326cf98871be0c2ca Author: Jiri Slaby Date: Thu Jul 12 18:25:43 2007 +0200 div long retries by 6 diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 7eb8d87..90deebb 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -178,7 +178,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) txs.control = bf->ctl; txs.retry_count = ds->ds_txstat.ts_shortretry + - ds->ds_txstat.ts_longretry; + ds->ds_txstat.ts_longretry / 6; if (ds->ds_txstat.ts_status) { if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { txs.excessive_retries = 1; commit 65a3c32acf5d5fcf5177de9d8f552fe0705f0d1e Author: Jiri Slaby Date: Fri Jul 13 08:18:45 2007 +0200 cleanup hal's key functions diff --git a/openhal/ath5k.h b/openhal/ath5k.h index e0cc2c4..3ca9468 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -1057,11 +1057,10 @@ unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); /* Key table (WEP) functions */ -bool ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher); -bool ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); -bool ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); -bool ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused); -bool ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); +int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); +int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); +int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac); +int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); /* Queue Control Unit, DFS Control Unit Functions */ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 7d246e0..dbee59a 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -3157,29 +3157,9 @@ ath5k_hw_get_cts_timeout(struct ath_hw *hal) * Key table (WEP) functions */ -/* - * Return which ciphers are supported by hw - */ -bool -ath5k_hw_is_cipher_supported(struct ath_hw *hal, enum ath5k_cipher cipher) +int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) { - AR5K_TRACE; - /* - * Only WEP for now - */ - if (cipher == AR5K_CIPHER_WEP) - return true; - - return false; -} - -/* - * Reset encryption key - */ -bool -ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) -{ - int i; + unsigned int i; AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); @@ -3192,43 +3172,28 @@ ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) ath5k_hw_reg_write(hal, AR5K_KEYTABLE_TYPE_NULL, AR5K_KEYTABLE_TYPE(entry)); - return false; /*????*/ + return 0; } -/* - * Check if a key entry is valid - */ -bool -ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) +int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) { AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - /* - * Check the validation flag at the end of the entry - */ - if (ath5k_hw_reg_read(hal, AR5K_KEYTABLE_MAC1(entry)) & - AR5K_KEYTABLE_VALID) - return true; - - return false; + /* Check the validation flag at the end of the entry */ + return ath5k_hw_reg_read(hal, AR5K_KEYTABLE_MAC1(entry)) & + AR5K_KEYTABLE_VALID; } -/* - * Set encryption key - */ -bool -ath5k_hw_set_key(struct ath_hw *hal, u16 entry, - const struct ath5k_keyval *keyval, const u8 *mac, int xor_notused) +int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, + const struct ath5k_keyval *keyval, const u8 *mac) { - int i; - u32 key_v[AR5K_KEYCACHE_SIZE - 2]; + unsigned int i; + u32 key_v[AR5K_KEYCACHE_SIZE - 2] = {}; AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - memset(&key_v, 0, sizeof(key_v)); - switch (keyval->wk_len) { case AR5K_KEYVAL_LENGTH_40: memcpy(&key_v[0], keyval->wk_key, 4); @@ -3255,8 +3220,7 @@ ath5k_hw_set_key(struct ath_hw *hal, u16 entry, break; default: - /* Unsupported key length (not WEP40/104/128) */ - return false; + return -EINVAL; } for (i = 0; i < ARRAY_SIZE(key_v); i++) @@ -3265,9 +3229,7 @@ ath5k_hw_set_key(struct ath_hw *hal, u16 entry, return ath5k_hw_set_key_lladdr(hal, entry, mac); } -bool -ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, - const u8 *mac) +int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) { u32 low_id, high_id; @@ -3277,11 +3239,10 @@ ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, /* MAC may be NULL if it's a broadcast key. In this case no need to * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ - if(unlikely(mac == NULL)) { + if (unlikely(mac == NULL)) { low_id = 0xffffffff; high_id = 0xffff | AR5K_KEYTABLE_VALID; - } - else { + } else { low_id = AR5K_LOW_ID(mac); high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID; } @@ -3289,12 +3250,10 @@ ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, ath5k_hw_reg_write(hal, low_id, AR5K_KEYTABLE_MAC0(entry)); ath5k_hw_reg_write(hal, high_id, AR5K_KEYTABLE_MAC1(entry)); - return true; + return 0; } - - /********************************************\ Queue Control Unit, DFS Control Unit Functions \********************************************/ commit 5ad4eee7a69f66ac8767ed1b919af78c76389101 Author: Jiri Slaby Date: Sat Jul 14 13:17:26 2007 +0200 hw wep diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 90deebb..91e884f 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -282,6 +282,31 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) return 0; } +static unsigned int ath_rx_decrypted(struct ath_softc *sc, + struct ath_desc *ds, struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (void *)skb->data; + unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); + + if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && + ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID) + return RX_FLAG_DECRYPTED; + + /* Apparently when a default key is used to decrypt the packet + the hal does not set the index used to decrypt. In such cases + get the index from the packet. */ + if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && + !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && + skb->len >= hlen + 4) { + keyix = skb->data[hlen + 3] >> 6; + + if (test_bit(keyix, sc->keymap)) + return RX_FLAG_DECRYPTED; + } + + return 0; +} + static void ath_tasklet_rx(unsigned long data) { struct ieee80211_rx_status rxs = {}; @@ -381,7 +406,7 @@ accept: rxs.ssi = ds->ds_rxstat.rs_rssi; rxs.antenna = ds->ds_rxstat.rs_antenna; rxs.rate = ds->ds_rxstat.rs_rate; -// rxs.flag |= RX_FLAG_DECRYPTED; + rxs.flag |= ath_rx_decrypted(sc, ds, skb); // printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); ath_dump_skb(skb, 1); @@ -862,7 +887,7 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, struct ath_txq *txq = sc->txq; struct ath_desc *ds = bf->desc; struct sk_buff *skb = bf->skb; - unsigned int hdrpad, pktlen, flags; + unsigned int hdrpad, pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; int ret; flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; @@ -879,10 +904,15 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, hdrpad = 0; pktlen = skb->len - hdrpad + FCS_LEN; + + if (ctl->key_idx != HW_KEY_IDX_INVALID) { + keyidx = ctl->key_idx; + pktlen += ctl->icv_len; + } + ret = ah->ah_setup_tx_desc(ah, ds, pktlen, ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, - 0xffff, ctl->tx_rate, ctl->retry_limit, AR5K_TXKEYIX_INVALID, 0, - flags, 0, 0); + 0xffff, ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0); if (ret) goto err_unmap; @@ -971,6 +1001,54 @@ static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) return ath_chan_set(sc, conf->chan); } +static int ath_set_key(struct ieee80211_hw *hw, set_key_cmd cmd, + u8 *addr, struct ieee80211_key_conf *key, int aid) +{ + struct ath_softc *sc = hw->priv; + int ret = 0; + + mutex_lock(&sc->lock); + + switch (cmd) { + case SET_KEY: + if (key->alg != ALG_WEP && key->alg != ALG_NONE && + key->alg != ALG_NULL) { + ret = -EINVAL; + goto unlock; + } + + ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr); + if (ret) { + printk(KERN_ERR "ath: can't set the key\n"); + goto unlock; + } + + set_bit(key->keyidx, sc->keymap); + key->hw_key_idx = key->keyidx; + key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT; + break; + case DISABLE_KEY: + ath5k_hw_reset_key(sc->ah, key->keyidx); + clear_bit(key->keyidx, sc->keymap); + break; + case REMOVE_ALL_KEYS: { + unsigned int i; + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) { + ath5k_hw_reset_key(sc->ah, i); + clear_bit(i, sc->keymap); + } + break; + } + default: + ret = -EINVAL; + goto unlock; + } + +unlock: + mutex_unlock(&sc->lock); + return ret; +} + static struct ieee80211_ops ath_hw_ops = { .tx = ath_tx, .reset = NULL, @@ -979,9 +1057,9 @@ static struct ieee80211_ops ath_hw_ops = { .add_interface = NULL, .remove_interface = NULL, .config = ath_config, -/* .config_interface = , - .set_key = , - .get_stats = , +/* .config_interface = ,*/ + .set_key = ath_set_key, +/* .get_stats = , .conf_tx = , .get_tx_stats = , .get_tsf = , @@ -1460,30 +1538,12 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) sc->mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); /* - * Get the hardware key cache size. - */ - sc->keymax = AR5K_KEYCACHE_SIZE; - - /* * Reset the key cache since some parts do not * reset the contents on initial power up. */ - for (i = 0; i < sc->keymax; i++) + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) ath5k_hw_reset_key(ah, i); - /* - * Mark key cache slots associated with global keys - * as in use. If we knew TKIP was not to be used we - * could leave the +32, +64, and +32+64 slots free. - * XXX only for splitmic. - */ -#ifdef BLE - for (i = 0; i < IEEE80211_WEP_NKID; i++) { - setbit(sc->sc_keymap, i); - setbit(sc->sc_keymap, i+32); - setbit(sc->sc_keymap, i+64); - setbit(sc->sc_keymap, i+32+64); - } -#endif + /* * Collect the channel list using the default country * code and including outdoor channels. The 802.11 layer diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 2f58793..92445c7 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -71,17 +71,6 @@ #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ -/* - * The key cache is used for h/w cipher state and also for - * tracking station state such as the current tx antenna. - * We also setup a mapping table between key cache slot indices - * and station state to short-circuit node lookups on rx. - * Different parts have different size key caches. We handle - * up to ATH_KEYMAX entries (could dynamically allocate state). - */ -#define ATH_KEYMAX AR5K_KEYCACHE_SIZE /* max key cache size we handle */ -#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ - /* driver-specific node state */ struct ath_node { #ifdef BLE @@ -222,13 +211,11 @@ struct ath_softc { u_int sc_txantenna; /* tx antenna (fixed or auto) */ #endif enum ath5k_int imask; /* interrupt mask copy */ - u_int keymax; /* size of key cache */ -#ifdef BLE - u8 sc_keymap[ATH_KEYBYTES];/* key use bit map */ - struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */ -#endif + + DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ + u8 bssidmask[ETH_ALEN]; - u_int ledpin; /* GPIO pin for driving LED */ + unsigned int ledpin; /* GPIO pin for driving LED */ #ifdef BLE u_int sc_ledon; /* pin setting for LED on */ u_int sc_ledidle; /* idle polling interval */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h index 3ca9468..012bb46 100644 --- a/openhal/ath5k.h +++ b/openhal/ath5k.h @@ -693,30 +693,6 @@ struct ath5k_rate_table { * Crypto definitions */ -/* key types */ -enum ath5k_cipher { - AR5K_CIPHER_WEP = 0, - AR5K_CIPHER_AES_OCB = 1, - AR5K_CIPHER_AES_CCM = 2, - AR5K_CIPHER_CKIP = 3, - AR5K_CIPHER_TKIP = 4, - AR5K_CIPHER_CLR = 5, /* no encryption */ - AR5K_CIPHER_MIC = 127 /* used for Message - Integrity Code */ -}; - -#define AR5K_KEYVAL_LENGTH_40 5 -#define AR5K_KEYVAL_LENGTH_104 13 -#define AR5K_KEYVAL_LENGTH_128 16 -#define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128 - -struct ath5k_keyval { - int wk_len; /* key's length */ - u8 wk_key[AR5K_KEYVAL_LENGTH_MAX]; - u8 wk_type; /* see above */ - u8 wk_mic[8]; /* TKIP MIC key */ -}; - #define AR5K_KEYCACHE_SIZE 8 /***********************\ @@ -1059,7 +1035,7 @@ unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); /* Key table (WEP) functions */ int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); -int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ath5k_keyval *keyval, const u8 *mac); +int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); /* Queue Control Unit, DFS Control Unit Functions */ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index dbee59a..5791170 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -3186,7 +3186,7 @@ int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) } int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, - const struct ath5k_keyval *keyval, const u8 *mac) + const struct ieee80211_key_conf *key, const u8 *mac) { unsigned int i; u32 key_v[AR5K_KEYCACHE_SIZE - 2] = {}; @@ -3194,28 +3194,28 @@ int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - switch (keyval->wk_len) { - case AR5K_KEYVAL_LENGTH_40: - memcpy(&key_v[0], keyval->wk_key, 4); - memcpy(&key_v[1], keyval->wk_key + 4, 1); + switch (key->keylen) { + case 40 / 8: + memcpy(&key_v[0], key->key, 4); + memcpy(&key_v[1], key->key + 4, 1); key_v[5] = AR5K_KEYTABLE_TYPE_40; break; - case AR5K_KEYVAL_LENGTH_104: - memcpy(&key_v[0], keyval->wk_key, 4); - memcpy(&key_v[1], keyval->wk_key + 4, 2); - memcpy(&key_v[2], keyval->wk_key + 6, 4); - memcpy(&key_v[3], keyval->wk_key + 10, 2); - memcpy(&key_v[4], keyval->wk_key + 12, 1); + case 104 / 8: + memcpy(&key_v[0], key->key, 4); + memcpy(&key_v[1], key->key + 4, 2); + memcpy(&key_v[2], key->key + 6, 4); + memcpy(&key_v[3], key->key + 10, 2); + memcpy(&key_v[4], key->key + 12, 1); key_v[5] = AR5K_KEYTABLE_TYPE_104; break; - case AR5K_KEYVAL_LENGTH_128: - memcpy(&key_v[0], keyval->wk_key, 4); - memcpy(&key_v[1], keyval->wk_key + 4, 2); - memcpy(&key_v[2], keyval->wk_key + 6, 4); - memcpy(&key_v[3], keyval->wk_key + 10, 2); - memcpy(&key_v[4], keyval->wk_key + 12, 4); + case 128 / 8: + memcpy(&key_v[0], key->key, 4); + memcpy(&key_v[1], key->key + 4, 2); + memcpy(&key_v[2], key->key + 6, 4); + memcpy(&key_v[3], key->key + 10, 2); + memcpy(&key_v[4], key->key + 12, 4); key_v[5] = AR5K_KEYTABLE_TYPE_128; break; commit 99200dfda61a570a57514443ead80093dfb0da24 Author: Jiri Slaby Date: Sat Jul 14 13:33:25 2007 +0200 implement reset diff --git a/ath/if_ath.c b/ath/if_ath.c index 0ba0492..794df8a 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -193,64 +193,6 @@ ath_bmiss_tasklet(unsigned long data) #endif } -/* - * Reset the hardware w/o losing operational state. This is - * basically a more efficient way of doing ath_stop, ath_init, - * followed by state transitions to the current 802.11 - * operational state. Used to recover from various errors and - * to reset or reload hardware state. - */ -static int -ath_reset(struct ieee80211_hw *hw) -{ -#ifdef BLE - struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; - struct ieee80211_channel *c; - enum ath5k_status status; - int opmode; - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: resetting\n", dev->name); - /* - * Convert to a HAL channel description with the flags - * constrained to reflect the current operating mode. - */ - c = ic->ic_ibss_chan; - sc->sc_curchan.freq = c->ic_freq; - sc->sc_curchan.channel_flags = ath_chan2flags(ic, c); - - ath5k_hw_set_intr(ah, 0); /* disable interrupts */ - ath_draintxq(sc); /* stop xmit side */ - ath_stoprecv(sc); /* stop recv side */ - - opmode = (ic->ic_opmode == IEEE80211_M_AHDEMO) ? 0 : ic->ic_opmode; - /* NB: indicate channel change so we do a full reset */ - if (!ath5k_hw_reset(ah, opmode, &sc->sc_curchan, true, &status)) - if_printf(dev, "%s: unable to reset hardware: '%s' (%u)\n", - __func__, hal_status_desc[status], status); - ath_update_txpow(sc); /* update tx power state */ - sc->sc_diversity = ath_hal_getdiversity(ah); /*get diversity status*/ - if (ath_startrecv(sc) != 0) /* restart recv */ - if_printf(dev, "%s: unable to start recv logic\n", __func__); - /* - * We may be doing a reset in response to an ioctl - * that changes the channel so update any state that - * might change as a result. - */ - ath_chan_change(sc, c); - if (ic->ic_state == IEEE80211_S_RUN) - ath_beacon_config(sc); /* restart beacons */ - ath5k_hw_set_intr(ah, sc->sc_imask); - - if (ic->ic_state == IEEE80211_S_RUN) - netif_wake_queue(dev); /* restart xmit */ - - if (sc->sc_rawdev_enabled) - netif_wake_queue(&sc->sc_rawdev); -#endif - return 0; -} - #define NUM_RADIOTAP_ELEMENTS 18 diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 91e884f..d877636 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -982,6 +982,50 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, return 0; } +static int ath_reset(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + int ret; + + DPRINTF(sc, ATH_DEBUG_RESET, "resetting\n"); + /* + * Convert to a HAL channel description with the flags + * constrained to reflect the current operating mode. + */ + sc->curchan = hw->conf.chan; + + ath5k_hw_set_intr(ah, 0); + ath_draintxq(sc); + ath_stoprecv(sc); + + ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, sc->curchan, true); + if (ret) { + printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); + goto err; + } + ath_update_txpow(sc); + + ret = ath_startrecv(sc); + if (ret) { + printk(KERN_ERR "ath: can't start recv logic\n"); + goto err; + } + /* + * We may be doing a reset in response to an ioctl + * that changes the channel so update any state that + * might change as a result. + */ +// ath_chan_change(sc, c); + ath5k_hw_set_intr(ah, sc->imask); + + ieee80211_wake_queues(hw); + + return 0; +err: + return ret; +} + static int ath_open(struct ieee80211_hw *hw) { return ath_init(hw->priv); @@ -1051,13 +1095,13 @@ unlock: static struct ieee80211_ops ath_hw_ops = { .tx = ath_tx, - .reset = NULL, + .reset = ath_reset, .open = ath_open, .stop = ath_stop, .add_interface = NULL, .remove_interface = NULL, .config = ath_config, -/* .config_interface = ,*/ + .config_interface = NULL, .set_key = ath_set_key, /* .get_stats = , .conf_tx = , commit 1b6d6e26678e785cbb2b107079bc45e8b367fed8 Author: Jiri Slaby Date: Sat Jul 14 13:45:20 2007 +0200 headers cleanup diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index d877636..5b39237 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1541,7 +1541,6 @@ static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, txq = &sc->txqs[qnum]; if (!txq->setup) { txq->qnum = qnum; - txq->intrcnt = 0; txq->link = NULL; INIT_LIST_HEAD(&txq->q); spin_lock_init(&txq->lock); diff --git a/ath/if_athioctl.h b/ath/if_athioctl.h index 24ab592..6359248 100644 --- a/ath/if_athioctl.h +++ b/ath/if_athioctl.h @@ -45,83 +45,82 @@ #include struct ath_stats { - u_int32_t ast_watchdog; /* device reset by watchdog */ - u_int32_t ast_hardware; /* fatal hardware error interrupts */ - u_int32_t ast_bmiss; /* beacon miss interrupts */ - u_int32_t ast_bstuck; /* beacon stuck interrupts */ - u_int32_t ast_rxorn; /* rx overrun interrupts */ - u_int32_t ast_rxeol; /* rx eol interrupts */ - u_int32_t ast_txurn; /* tx underrun interrupts */ - u_int32_t ast_mib; /* mib interrupts */ - u_int32_t ast_intrcoal; /* interrupts coalesced */ - u_int32_t ast_tx_packets; /* packet sent on the interface */ - u_int32_t ast_tx_mgmt; /* management frames transmitted */ - u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ - u_int32_t ast_tx_invalid; /* frames discarded 'cuz device gone */ - u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ - u_int32_t ast_tx_encap; /* tx encapsulation failed */ - u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ - u_int32_t ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ - u_int32_t ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ - u_int32_t ast_tx_linear; /* tx linearized to cluster */ - u_int32_t ast_tx_nodata; /* tx discarded empty frame */ - u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ - u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ - u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ - u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ - u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ - u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ - u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ - u_int32_t ast_tx_noack; /* tx frames with no ack marked */ - u_int32_t ast_tx_rts; /* tx frames with rts enabled */ - u_int32_t ast_tx_cts; /* tx frames with cts enabled */ - u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ - u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ - u_int32_t ast_tx_protect; /* tx frames with protection */ - u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ - u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ - u_int32_t ast_rx_nobuf; /* rx setup failed 'cuz no skb */ - u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ - u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ - u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ - u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ - u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ - u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ - u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ - u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ - u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ - u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ - u_int32_t ast_rx_packets; /* packet recv on the interface */ - u_int32_t ast_rx_mgt; /* management frames received */ - u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ - int8_t ast_tx_rssi; /* tx rssi of last ack */ - int8_t ast_rx_rssi; /* rx rssi from histogram */ - u_int32_t ast_be_xmit; /* beacons transmitted */ - u_int32_t ast_be_nobuf; /* beacon setup failed 'cuz no skb */ - u_int32_t ast_per_cal; /* periodic calibration calls */ - u_int32_t ast_per_calfail;/* periodic calibration failed */ - u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ - u_int32_t ast_rate_calls; /* rate control checks */ - u_int32_t ast_rate_raise; /* rate control raised xmit rate */ - u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ - u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ - u_int32_t ast_ant_txswitch;/* tx antenna switches */ - u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ - u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ + __u32 ast_watchdog; /* device reset by watchdog */ + __u32 ast_hardware; /* fatal hardware error interrupts */ + __u32 ast_bmiss; /* beacon miss interrupts */ + __u32 ast_bstuck; /* beacon stuck interrupts */ + __u32 ast_rxorn; /* rx overrun interrupts */ + __u32 ast_rxeol; /* rx eol interrupts */ + __u32 ast_txurn; /* tx underrun interrupts */ + __u32 ast_mib; /* mib interrupts */ + __u32 ast_intrcoal; /* interrupts coalesced */ + __u32 ast_tx_packets; /* packet sent on the interface */ + __u32 ast_tx_mgmt; /* management frames transmitted */ + __u32 ast_tx_discard; /* frames discarded prior to assoc */ + __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ + __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ + __u32 ast_tx_encap; /* tx encapsulation failed */ + __u32 ast_tx_nonode; /* tx failed 'cuz no node */ + __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ + __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ + __u32 ast_tx_linear; /* tx linearized to cluster */ + __u32 ast_tx_nodata; /* tx discarded empty frame */ + __u32 ast_tx_busdma; /* tx failed for dma resrcs */ + __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ + __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ + __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ + __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ + __u32 ast_tx_longretry;/* tx on-chip retries (long) */ + __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ + __u32 ast_tx_noack; /* tx frames with no ack marked */ + __u32 ast_tx_rts; /* tx frames with rts enabled */ + __u32 ast_tx_cts; /* tx frames with cts enabled */ + __u32 ast_tx_shortpre;/* tx frames with short preamble */ + __u32 ast_tx_altrate; /* tx frames with alternate rate */ + __u32 ast_tx_protect; /* tx frames with protection */ + __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ + __u32 ast_tx_ctsext; /* tx frames with cts extension */ + __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ + __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ + __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ + __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ + __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ + __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ + __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ + __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ + __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ + __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ + __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ + __u32 ast_rx_packets; /* packet recv on the interface */ + __u32 ast_rx_mgt; /* management frames received */ + __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ + __s8 ast_tx_rssi; /* tx rssi of last ack */ + __s8 ast_rx_rssi; /* rx rssi from histogram */ + __u32 ast_be_xmit; /* beacons transmitted */ + __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ + __u32 ast_per_cal; /* periodic calibration calls */ + __u32 ast_per_calfail;/* periodic calibration failed */ + __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ + __u32 ast_rate_calls; /* rate control checks */ + __u32 ast_rate_raise; /* rate control raised xmit rate */ + __u32 ast_rate_drop; /* rate control dropped xmit rate */ + __u32 ast_ant_defswitch;/* rx/default antenna switches */ + __u32 ast_ant_txswitch;/* tx antenna switches */ + __u32 ast_ant_rx[8]; /* rx frames with antenna */ + __u32 ast_ant_tx[8]; /* tx frames with antenna */ }; struct ath_diag { char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ - u_int16_t ad_id; + __u16 ad_id; #define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ #define ATH_DIAG_IN 0x4000 /* copy in parameters */ #define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ #define ATH_DIAG_ID 0x0fff - u_int16_t ad_in_size; /* pack to fit, yech */ + __u16 ad_in_size; /* pack to fit, yech */ void __user *ad_in_data; void __user *ad_out_data; u_int ad_out_size; - }; /* @@ -137,12 +136,12 @@ struct ath_diag { struct ath_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; - u_int8_t wr_flags; /* XXX for padding */ - u_int8_t wr_rate; + __u8 wr_flags; /* XXX for padding */ + __u8 wr_rate; __le16 wr_chan_freq; __le16 wr_chan_flags; - u_int8_t wr_antenna; - u_int8_t wr_antsignal; + __u8 wr_antenna; + __u8 wr_antsignal; }; #define ATH_TX_RADIOTAP_PRESENT ( \ @@ -157,22 +156,17 @@ struct ath_rx_radiotap_header { struct ath_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; - u_int8_t wt_flags; /* XXX for padding */ - u_int8_t wt_rate; - u_int8_t wt_txpower; - u_int8_t wt_antenna; + __u8 wt_flags; /* XXX for padding */ + __u8 wt_rate; + __u8 wt_txpower; + __u8 wt_antenna; __le16 wt_tx_flags; - u_int8_t wt_rts_retries; - u_int8_t wt_data_retries; + __u8 wt_rts_retries; + __u8 wt_data_retries; }; - -#ifdef __linux__ #define SIOCGATHSTATS (SIOCDEVPRIVATE+0) #define SIOCGATHDIAG (SIOCDEVPRIVATE+1) -#else -#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) -#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) + #endif -#endif /* _DEV_ATH_ATHIOCTL_H */ diff --git a/ath/if_athvar.h b/ath/if_athvar.h index 92445c7..f44464b 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -57,33 +57,19 @@ * MAXFRAMEBODY - WEP - QOS - RSN/WPA: * 2312 - 8 - 2 - 12 = 2290 */ -#define ATH_MAX_MTU 2290 -#define ATH_MIN_MTU 32 +#define ATH_MAX_MTU 2290 +#define ATH_MIN_MTU 32 #define ATH_RXBUF 40 /* number of RX buffers */ #define ATH_TXBUF 200 /* number of TX buffers */ #define ATH_TXDESC 1 /* number of descriptors per buffer */ -#define ATH_BCBUF 1 /* number of beacon buffers */ +#define ATH_BCBUF 1 /* number of beacon buffers */ #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ -#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ -#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ -#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ - -/* driver-specific node state */ -struct ath_node { -#ifdef BLE - struct ieee80211_node an_node; /* base class */ -#endif - u8 an_tx_mgtrate; /* h/w rate for management/ctl frames */ - u8 an_tx_mgtratesp;/* short preamble h/w rate for " " */ - u32 an_avgrssi; /* average rssi over all rx frames */ - struct ath5k_node_stats an_halstats; /* rssi statistics used by hal */ - /* variable-length rate control state follows */ -}; -#define ATH_NODE(ni) ((struct ath_node *)(ni)) -#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) +#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ +#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ +#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ #define ATH_RSSI_LPF_LEN 10 #define ATH_RSSI_DUMMY_MARKER 0x127 @@ -117,20 +103,10 @@ struct ath_buf { */ struct ath_txq { unsigned int qnum; /* hardware q number */ - unsigned int intrcnt; /* interrupt count */ u32 *link; /* link ptr in last TX desc */ struct list_head q; /* transmit queue */ spinlock_t lock; /* lock on q and link */ - /* - * State for patching up CTS when bursting. - */ - struct ath_buf *linkbuf; /* va of last buffer */ - struct ath_desc *lastdsWithCTS; /* first desc of last descriptor that - * contains CTS */ - struct ath_desc *gatingds; /* final desc of the gating desc that - * determines whether lastdsWithCTS has - * been DMA'ed or not */ - bool setup; + bool setup; }; #if CHAN_DEBUG @@ -156,15 +132,6 @@ struct ath_softc { #endif int debug; -#ifdef BLE - void (*sc_recv_mgmt)(struct ieee80211com *, - struct sk_buff *, - struct ieee80211_node *, - int, int, u32); - int (*sc_newstate)(struct ieee80211com *, - enum ieee80211_state, int); - void (*sc_node_free)(struct ieee80211_node *); -#endif struct ath_buf *bufptr; /* allocated buffer ptr */ struct ath_desc *desc; /* TX/RX descriptors */ dma_addr_t desc_daddr; /* DMA (physical) address */ @@ -245,7 +212,6 @@ struct ath_softc { struct tasklet_struct rxtq; /* rx intr tasklet */ #ifdef BLE struct tasklet_struct rxorntq; /* rxorn intr tasklet */ -//#ifdef BLE u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ @@ -286,14 +252,6 @@ struct ath_softc { #endif }; -/*#define ATH_TXBUF_LOCK(_sc) spin_lock(&(_sc)->sc_txbuflock) -#define ATH_TXBUF_UNLOCK(_sc) spin_unlock(&(_sc)->sc_txbuflock) -#define ATH_TXBUF_LOCK_BH(_sc) spin_lock_bh(&(_sc)->sc_txbuflock) -#define ATH_TXBUF_UNLOCK_BH(_sc) spin_unlock_bh(&(_sc)->sc_txbuflock)*/ -#define ATH_TXBUF_LOCK_ASSERT(_sc) \ - KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), "txbuf not locked!") - -int ath_ioctl_ethtool(struct ath_softc *, int, void __user *); void ath_sysctl_register(void); void ath_sysctl_unregister(void); @@ -303,32 +261,10 @@ void ath_sysctl_unregister(void); (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == 0) #define ath_hal_hwphycounters(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == 0) -#define ath_hal_hasdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 0, NULL) == 0) -#define ath_hal_getdiversity(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIVERSITY, 1, NULL) == 0) -#define ath_hal_setdiversity(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_DIVERSITY, 1, _v, NULL) -#define ath_hal_getdiag(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_DIAG, 0, _pv) == 0) -#define ath_hal_setdiag(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_DIAG, 0, _v, NULL) #define ath_hal_getnumtxqueues(_ah, _pv) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == 0) #define ath_hal_hasveol(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) -#define ath_hal_hastxpowlimit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 0, NULL) == 0) -#define ath_hal_settxpowlimit(_ah, _pow) \ - ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) -#define ath_hal_gettxpowlimit(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 1, _ppow) == 0) -#define ath_hal_getmaxtxpow(_ah, _ppow) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 2, _ppow) == 0) -#define ath_hal_gettpscale(_ah, _scale) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TXPOW, 3, _scale) == 0) -#define ath_hal_settpscale(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_TXPOW, 3, _v, NULL) #define ath_hal_hastpc(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == 0) #define ath_hal_gettpc(_ah) \ @@ -339,13 +275,5 @@ void ath_sysctl_unregister(void); (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) #define ath_hal_hasbssidmask(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) -#ifdef notyet -#define ath_hal_hasmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 0, NULL) == 0) -#define ath_hal_getmcastkeysearch(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_MCAST_KEYSRCH, 1, NULL) == 0) -#else -#define ath_hal_getmcastkeysearch(_ah) 0 -#endif -#endif /* _DEV_ATH_ATHVAR_H */ +#endif commit 73f3c89ee0e4ac99a4373067614c23fd71f7221e Author: Jiri Slaby Date: Sun Jul 15 09:26:12 2007 +0200 get/reset_tsf diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 5b39237..5a1bdab 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1093,6 +1093,20 @@ unlock: return ret; } +static u64 ath_get_tsf(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + return ath5k_hw_get_tsf64(sc->ah); +} + +static void ath_reset_tsf(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + ath5k_hw_reset_tsf(sc->ah); +} + static struct ieee80211_ops ath_hw_ops = { .tx = ath_tx, .reset = ath_reset, @@ -1105,10 +1119,10 @@ static struct ieee80211_ops ath_hw_ops = { .set_key = ath_set_key, /* .get_stats = , .conf_tx = , - .get_tx_stats = , - .get_tsf = , - .reset_tsf = , - .beacon_update = ,*/ + .get_tx_stats = ,*/ + .get_tsf = ath_get_tsf, + .reset_tsf = ath_reset_tsf, + .beacon_update = NULL, }; static irqreturn_t ath_intr(int irq, void *dev_id) diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c index 5791170..db1d888 100644 --- a/openhal/ath5k_hw.c +++ b/openhal/ath5k_hw.c @@ -2800,8 +2800,7 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) /* * Get a 32bit TSF */ -u32 -ath5k_hw_get_tsf32(struct ath_hw *hal) +u32 ath5k_hw_get_tsf32(struct ath_hw *hal) { AR5K_TRACE; return ath5k_hw_reg_read(hal, AR5K_TSF_L32); @@ -2810,8 +2809,7 @@ ath5k_hw_get_tsf32(struct ath_hw *hal) /* * Get the full 64bit TSF */ -u64 -ath5k_hw_get_tsf64(struct ath_hw *hal) +u64 ath5k_hw_get_tsf64(struct ath_hw *hal) { u64 tsf = ath5k_hw_reg_read(hal, AR5K_TSF_U32); AR5K_TRACE; @@ -2822,12 +2820,10 @@ ath5k_hw_get_tsf64(struct ath_hw *hal) /* * Force a TSF reset */ -void -ath5k_hw_reset_tsf(struct ath_hw *hal) +void ath5k_hw_reset_tsf(struct ath_hw *hal) { AR5K_TRACE; - AR5K_REG_ENABLE_BITS(hal, AR5K_BEACON, - AR5K_BEACON_RESET_TSF); + AR5K_REG_ENABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_RESET_TSF); } /* commit 42b6382a39fe6bfb329007477fb6e17db6b33d3f Author: Jiri Slaby Date: Sun Jul 15 09:38:31 2007 +0200 stats diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 5a1bdab..2d9794c 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -180,6 +180,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) txs.retry_count = ds->ds_txstat.ts_shortretry + ds->ds_txstat.ts_longretry / 6; if (ds->ds_txstat.ts_status) { + sc->ll_stats.dot11ACKFailureCount++; if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { txs.excessive_retries = 1; } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { @@ -191,10 +192,12 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) } ieee80211_tx_status(sc->hw, skb, &txs); + sc->tx_stats.data[txq->qnum].count++; // printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); spin_lock(&sc->txbuflock); + sc->tx_stats.data[txq->qnum].len--; list_move_tail(&bf->list, &sc->txbuf); spin_unlock(&sc->txbuflock); } @@ -637,6 +640,7 @@ static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) bf->skb = NULL; spin_lock_bh(&sc->txbuflock); + sc->tx_stats.data[txq->qnum].len--; list_move_tail(&bf->list, &sc->txbuf); spin_unlock_bh(&sc->txbuflock); } @@ -925,6 +929,7 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, spin_lock_bh(&txq->lock); list_add_tail(&bf->list, &txq->q); + sc->tx_stats.data[txq->qnum].len++; if (txq->link == NULL) /* is this first packet? */ ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); else /* no, so only link it */ @@ -1093,6 +1098,26 @@ unlock: return ret; } +static int ath_get_stats(struct ieee80211_hw *hw, + struct ieee80211_low_level_stats *stats) +{ + struct ath_softc *sc = hw->priv; + + memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); + + return 0; +} + +static int ath_get_tx_stats(struct ieee80211_hw *hw, + struct ieee80211_tx_queue_stats *stats) +{ + struct ath_softc *sc = hw->priv; + + memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); + + return 0; +} + static u64 ath_get_tsf(struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; @@ -1117,9 +1142,9 @@ static struct ieee80211_ops ath_hw_ops = { .config = ath_config, .config_interface = NULL, .set_key = ath_set_key, -/* .get_stats = , - .conf_tx = , - .get_tx_stats = ,*/ + .get_stats = ath_get_stats, + .conf_tx = NULL, + .get_tx_stats = ath_get_tx_stats, .get_tsf = ath_get_tsf, .reset_tsf = ath_reset_tsf, .beacon_update = NULL, diff --git a/ath/if_athvar.h b/ath/if_athvar.h index f44464b..b884d06 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -120,6 +120,8 @@ struct ath_softc { void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ struct ath_stats stats; /* private statistics */ + struct ieee80211_tx_queue_stats tx_stats; + struct ieee80211_low_level_stats ll_stats; struct ieee80211_hw *hw; /* IEEE 802.11 common */ struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; struct ieee80211_channel channels[ATH_CHAN_MAX]; commit 4b5e57a08f700b3dbf682947b445aa03026e9522 Author: Jiri Slaby Date: Sun Jul 15 09:44:23 2007 +0200 fatal and rxorn diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c index 2d9794c..2a672c0 100644 --- a/ath/if_ath_pci.c +++ b/ath/if_ath_pci.c @@ -1179,12 +1179,10 @@ static irqreturn_t ath_intr(int irq, void *dev_id) * by the hal. */ sc->stats.ast_hardware++; - ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ -// tasklet_schedule(&sc->fataltq); + ath_reset(sc->hw); } else if (status & AR5K_INT_RXORN) { sc->stats.ast_rxorn++; - ath5k_hw_set_intr(ah, 0); /* disable intrs until rst */ -// tasklet_schedule(&sc->rxorntq); + ath_reset(sc->hw); } else { if (status & AR5K_INT_SWBA) { /* diff --git a/ath/if_athvar.h b/ath/if_athvar.h index b884d06..a587302 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -204,7 +204,6 @@ struct ath_softc { u8 pad[64]; } u_rx_rt; int sc_rx_th_len; - struct tasklet_struct fataltq; /* fatal int tasklet */ struct tasklet_struct sc_radartq; /* Radar detection */ #endif unsigned int rxbufsize; /* rx size based on mtu */ @@ -213,10 +212,8 @@ struct ath_softc { u32 *rxlink; /* link ptr in last RX desc */ struct tasklet_struct rxtq; /* rx intr tasklet */ #ifdef BLE - struct tasklet_struct rxorntq; /* rxorn intr tasklet */ u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ - #endif struct list_head txbuf; /* transmit buffer */ spinlock_t txbuflock; commit 6199bbcc1a0cb74b0e4194b349c690d34d1f284c Author: Jiri Slaby Date: Sun Jul 15 09:45:29 2007 +0200 comment bmisstq diff --git a/ath/if_athvar.h b/ath/if_athvar.h index a587302..a753e1f 100644 --- a/ath/if_athvar.h +++ b/ath/if_athvar.h @@ -233,9 +233,9 @@ struct ath_softc { u32 sc_ant_tx[8]; /* recent tx frames/antenna */ struct ieee80211_beacon_offsets boff; /* dynamic update state */ struct ath_txq *cabq; /* tx q for cab frames */ -#endif + struct tasklet_struct bmisstq; /* bmiss intr tasklet */ -#ifdef BLE + struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ enum { OK, /* no change needed */ commit f6fd65e1294437465f031aaae968dd7bd3cb3277 Author: Jiri Slaby Date: Sun Jul 15 13:49:07 2007 +0200 one (top) dir with all files diff --git a/Makefile b/Makefile index 1aec332..877d718 100644 --- a/Makefile +++ b/Makefile @@ -1,10 +1,7 @@ KDIR=/lib/modules/$(shell uname -r)/build KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) -EXTRA_CFLAGS += -I$(src)/openhal - -ath5k-objs := ath/if_ath_pci.o openhal/ath5k_hw.o \ - openhal/ieee80211_regdomain.o +ath5k-objs := ath.o ath5k_hw.o ieee80211_regdomain.o obj-m += ath5k.o diff --git a/ath.c b/ath.c new file mode 100644 index 0000000..970b625 --- /dev/null +++ b/ath.c @@ -0,0 +1,2135 @@ +/*- + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2004-2005 Atheros Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + */ +#define ATH_PCI_VERSION "0.9.5.0-BSD" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "ath.h" + +#define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ +#define ATH_DUMP_SKB 0 /* show skb contents */ +#define AR_DEBUG 1 + +#define DPRINTF(sc, _m, _fmt...) do { \ + if ((sc->debug & (_m)) && net_ratelimit()) \ + printk(_fmt); \ +} while (0) +enum { + ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ + ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ + ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ + ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ + ATH_DEBUG_RATE = 0x00000010, /* rate control */ + ATH_DEBUG_RESET = 0x00000020, /* reset processing */ + ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ + ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ + ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ + ATH_DEBUG_INTR = 0x00001000, /* ISR */ + ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ + ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ + ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ + ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ + ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ + ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ + ATH_DEBUG_NODE = 0x00080000, /* node management */ + ATH_DEBUG_LED = 0x00100000, /* led management */ + ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ + ATH_DEBUG_ANY = 0xffffffff +}; + +static int countrycode = CTRY_DEFAULT; +static int outdoor = true; +static int xchanmode = true; +module_param(countrycode, int, 0); +MODULE_PARM_DESC(countrycode, "Override default country code"); +module_param(outdoor, int, 0); +MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); +module_param(xchanmode, int, 0); +MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); + +#ifdef AR_DEBUG +static unsigned int ath_debug; +module_param_named(debug, ath_debug, uint, 0); +#endif + +/* + * User a static table of PCI id's for now. While this is the + * "new way" to do things, we may want to switch back to having + * the HAL check them by defining a probe method. + */ +static struct pci_device_id ath_pci_id_table[] __devinitdata = { + { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */ + { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */ + { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 */ + { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */ + { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */ + { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */ + { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */ + { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */ + { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ + { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ + { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ + { 0 } +}; +MODULE_DEVICE_TABLE(pci, ath_pci_id_table); + +#ifdef AR_DEBUG +static void ath_printrxbuf(struct ath_buf *bf, int done) +{ + struct ath_desc *ds = bf->desc; + + printk("R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", + ds, (unsigned long long)bf->daddr, + ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], + !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); +} + +static void ath_printtxbuf(struct ath_buf *bf, int done) +{ + struct ath_desc *ds = bf->desc; + + printk("T (%p %llx) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", + ds, (unsigned long long)bf->daddr, + ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], + !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); +} +#endif + +#if ATH_DUMP_SKB +static void ath_dump_skb(struct sk_buff *skb, unsigned int rx) +{ + unsigned int a; + + printk(KERN_DEBUG "%c", rx ? 'r' : 't'); + for (a = 0; a < min(200U, skb->len) + 4; a++) { + printk("%.2x %s", skb->data[a], ((a+1) % 8) ? "" : " "); + if (!((a+1) % 16)) + printk("\n" KERN_DEBUG " "); + } + printk("\n"); +} +#else +static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) {} +#endif + +static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) +{ + struct ieee80211_tx_status txs = {}; + struct ath_buf *bf, *bf0; + struct ath_desc *ds; + struct sk_buff *skb; + int ret; + + spin_lock(&txq->lock); + list_for_each_entry_safe(bf, bf0, &txq->q, list) { + ds = bf->desc; + + ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); + if (ret == -EINPROGRESS) + break; + else if (ret) { + printk(KERN_ERR "ath: error %d while processing " + "queue %u\n", ret, txq->qnum); + break; + } + + skb = bf->skb; + bf->skb = NULL; + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, + PCI_DMA_TODEVICE); + + txs.control = bf->ctl; + txs.retry_count = ds->ds_txstat.ts_shortretry + + ds->ds_txstat.ts_longretry / 6; + if (ds->ds_txstat.ts_status) { + sc->ll_stats.dot11ACKFailureCount++; + if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { + txs.excessive_retries = 1; + } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { + txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; + } + } else { + txs.flags |= IEEE80211_TX_STATUS_ACK; + txs.ack_signal = ds->ds_txstat.ts_rssi; + } + + ieee80211_tx_status(sc->hw, skb, &txs); + sc->tx_stats.data[txq->qnum].count++; + +// printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); + + spin_lock(&sc->txbuflock); + sc->tx_stats.data[txq->qnum].len--; + list_move_tail(&bf->list, &sc->txbuf); + spin_unlock(&sc->txbuflock); + } + if (list_empty(&txq->q)) + txq->link = NULL; + spin_unlock(&txq->lock); +} + +static void ath_tasklet_tx(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + ath_tx_processq(sc, sc->txq); + + ieee80211_wake_queue(sc->hw, 0); +} + +static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) +{ + struct ath_hw *ah = sc->ah; + struct sk_buff *skb = bf->skb; + struct ath_desc *ds; + + if (skb == NULL) { + unsigned int off; + + /* + * Allocate buffer with headroom_needed space for the + * fake physical layer header at the start. + */ + skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); + if (skb == NULL) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " + "size %u failed\n", __func__, + sc->rxbufsize + sc->cachelsz - 1); + sc->stats.ast_rx_nobuf++; + return -ENOMEM; + } + /* + * Cache-line-align. This is important (for the + * 5210 at least) as not doing so causes bogus data + * in rx'd frames. + */ + off = ((unsigned long)skb->data) % sc->cachelsz; + if (off != 0) + skb_reserve(skb, sc->cachelsz - off); + + bf->skb = skb; + bf->skbaddr = pci_map_single(sc->pdev, + skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); + if (pci_dma_mapping_error(bf->skbaddr)) { + printk(KERN_ERR "%s: DMA mapping failed\n", __func__); + dev_kfree_skb(skb); + bf->skb = NULL; + sc->stats.ast_rx_busdma++; + return -ENOMEM; + } + } + + /* + * Setup descriptors. For receive we always terminate + * the descriptor list with a self-linked entry so we'll + * not get overrun under high load (as can happen with a + * 5212 when ANI processing enables PHY error frames). + * + * To insure the last descriptor is self-linked we create + * each descriptor as self-linked and add it to the end. As + * each additional descriptor is added the previous self-linked + * entry is ``fixed'' naturally. This should be safe even + * if DMA is happening. When processing RX interrupts we + * never remove/process the last, self-linked, entry on the + * descriptor list. This insures the hardware always has + * someplace to write a new frame. + */ + ds = bf->desc; + ds->ds_link = bf->daddr; /* link to self */ + ds->ds_data = bf->skbaddr; + ath5k_hw_setup_rx_desc(ah, ds, + skb_tailroom(skb), /* buffer size */ + 0); + + if (sc->rxlink != NULL) + *sc->rxlink = bf->daddr; + sc->rxlink = &ds->ds_link; + return 0; +} + +static unsigned int ath_rx_decrypted(struct ath_softc *sc, + struct ath_desc *ds, struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (void *)skb->data; + unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); + + if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && + ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID) + return RX_FLAG_DECRYPTED; + + /* Apparently when a default key is used to decrypt the packet + the hal does not set the index used to decrypt. In such cases + get the index from the packet. */ + if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && + !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && + skb->len >= hlen + 4) { + keyix = skb->data[hlen + 3] >> 6; + + if (test_bit(keyix, sc->keymap)) + return RX_FLAG_DECRYPTED; + } + + return 0; +} + +static void ath_tasklet_rx(unsigned long data) +{ + struct ieee80211_rx_status rxs = {}; + struct sk_buff *skb; + struct ath_softc *sc = (void *)data; + struct ath_buf *bf; + struct ath_desc *ds; + u16 len; + u8 stat; + int ret; + + spin_lock(&sc->rxbuflock); + do { + if (list_empty(&sc->rxbuf)) { + if (net_ratelimit()) + printk(KERN_WARNING "ath: empty rx buf pool\n"); + break; + } + bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); + BUG_ON(bf->skb == NULL); + skb = bf->skb; + ds = bf->desc; + if (ds->ds_link == bf->daddr) /* this is the end */ + break; + + ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); + if (ret == -EINPROGRESS) + break; + else if (ret) { + if (net_ratelimit()) + printk(KERN_ERR "ath: error in processing rx " + "descriptor\n"); + return; + } + + if (ds->ds_rxstat.rs_more) { + if (net_ratelimit()) + printk(KERN_INFO "ath: unsupported jumbo\n"); + goto next; + } + + stat = ds->ds_rxstat.rs_status; + if (stat) { + if (stat & AR5K_RXERR_CRC) + sc->stats.ast_rx_crcerr++; + if (stat & AR5K_RXERR_FIFO) + sc->stats.ast_rx_fifoerr++; + if (stat & AR5K_RXERR_PHY) { + sc->stats.ast_rx_phyerr++; + sc->stats.ast_rx_phy + [ds->ds_rxstat.rs_phyerr & 0x1f]++; + goto next; + } + if (stat & AR5K_RXERR_DECRYPT) { + /* + * Decrypt error. If the error occurred + * because there was no hardware key, then + * let the frame through so the upper layers + * can process it. This is necessary for 5210 + * parts which have no way to setup a ``clear'' + * key cache entry. + * + * XXX do key cache faulting + */ + if (ds->ds_rxstat.rs_keyix == + AR5K_RXKEYIX_INVALID) + goto accept; + sc->stats.ast_rx_badcrypt++; + } + if (stat & AR5K_RXERR_MIC) { + rxs.flag |= RX_FLAG_MMIC_ERROR; + sc->stats.ast_rx_badmic++; + goto accept; + } + + goto next; + } +accept: + len = ds->ds_rxstat.rs_datalen; + pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len, + PCI_DMA_FROMDEVICE); + pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, + PCI_DMA_FROMDEVICE); + bf->skb = NULL; + + if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) + printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + + skb_put(skb, len); + + sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; + + rxs.mactime = ds->ds_rxstat.rs_tstamp; + rxs.freq = sc->curchan->freq; + rxs.channel = sc->curchan->chan; + rxs.phymode = sc->curmode; + rxs.ssi = ds->ds_rxstat.rs_rssi; + rxs.antenna = ds->ds_rxstat.rs_antenna; + rxs.rate = ds->ds_rxstat.rs_rate; + rxs.flag |= ath_rx_decrypted(sc, ds, skb); + +// printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); + ath_dump_skb(skb, 1); + + __ieee80211_rx(sc->hw, skb, &rxs); +next: + list_move_tail(&bf->list, &sc->rxbuf); + } while (ath_rxbuf_init(sc, bf) == 0); + spin_unlock(&sc->rxbuflock); +} + +/* + * Calculate the receive filter according to the + * operating mode and state: + * + * o always accept unicast, broadcast, and multicast traffic + * o maintain current state of phy error reception (the hal + * may enable phy error frames for noise immunity work) + * o probe request frames are accepted only when operating in + * hostap, adhoc, or monitor modes + * o enable promiscuous mode according to the interface state + * o accept beacons: + * - when operating in adhoc mode so the 802.11 layer creates + * node table entries for peers, + * - when operating in station mode for collecting rssi data when + * the station is otherwise quiet, or + * - when scanning + * o accept any additional packets specified by sc_rxfilter + */ +static u32 ath_calcrxfilter(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + u32 rfilt; + + rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERROR) | + AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | + AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_PHYRADAR; +#ifdef BLE + if (ic->ic_opmode != IEEE80211_M_STA && + ic->ic_opmode != IEEE80211_M_AHDEMO) + rfilt |= AR5K_RX_FILTER_PROBEREQ; + if (ic->ic_opmode != IEEE80211_M_HOSTAP && + (dev->flags & IFF_PROMISC)) + rfilt |= AR5K_RX_FILTER_PROM; + if (ic->ic_opmode == IEEE80211_M_STA || + ic->ic_opmode == IEEE80211_M_IBSS || + state == IEEE80211_S_SCAN) +#endif + rfilt |= AR5K_RX_FILTER_BEACON; + + return rfilt; +} + +static void ath_mode_init(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + u32 rfilt; + + /* configure rx filter */ + rfilt = ath_calcrxfilter(sc); + ath5k_hw_set_rx_filter(ah, rfilt); + + if (ath_hal_hasbssidmask(ah)) + ath5k_hw_set_bssid_mask(ah, sc->bssidmask); + + /* configure operational mode */ + ath5k_hw_set_opmode(ah); + + ath5k_hw_set_mcast_filter(ah, 0, 0); + DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); +} + +/* + * Enable the receive h/w following a reset. + */ +static int ath_startrecv(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + struct ath_buf *bf; + int ret; + + sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz); + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: cachelsz %u rxbufsize %u\n", + __func__, sc->cachelsz, sc->rxbufsize); + + sc->rxlink = NULL; + + spin_lock_bh(&sc->rxbuflock); + list_for_each_entry(bf, &sc->rxbuf, list) { + ret = ath_rxbuf_init(sc, bf); + if (ret != 0) { + spin_unlock_bh(&sc->rxbuflock); + goto err; + } + } + bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); + spin_unlock_bh(&sc->rxbuflock); + + ath5k_hw_put_rx_buf(ah, bf->daddr); + ath5k_hw_start_rx(ah); /* enable recv descriptors */ + ath_mode_init(sc); /* set filters, etc. */ + ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ + + return 0; +err: + return ret; +} + +static inline void ath_update_txpow(struct ath_softc *sc) +{ + ath5k_hw_set_txpower_limit(sc->ah, 0); +} + +static int ath_stop_locked(struct ath_softc *); + +static int ath_init(struct ath_softc *sc) +{ + int ret; + + mutex_lock(&sc->lock); + +// DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); + + /* + * Stop anything previously setup. This is safe + * no matter this is the first time through or not. + */ + ath_stop_locked(sc); + + /* + * The basic interface to setting the hardware in a good + * state is ``reset''. On return the hardware is known to + * be powered up and with interrupts disabled. This must + * be followed by initialization of the appropriate bits + * and then setup of the interrupt mask. + */ + sc->curchan = sc->hw->conf.chan; + ret = ath5k_hw_reset(sc->ah, IEEE80211_IF_TYPE_STA, sc->curchan, false); + if (ret) { + printk(KERN_ERR "unable to reset hardware: %d\n", ret); + goto done; + } + /* + * This is needed only to setup initial state + * but it's best done after a reset. + */ + ath_update_txpow(sc); + + /* + * Setup the hardware after reset: the key cache + * is filled as needed and the receive engine is + * set going. Frame transmit is handled entirely + * in the frame output path; there's nothing to do + * here except setup the interrupt mask. + */ + ret = ath_startrecv(sc); + if (ret) + goto done; + + /* + * Enable interrupts. + */ + sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN + | AR5K_INT_FATAL | AR5K_INT_GLOBAL; + + ath5k_hw_set_intr(sc->ah, sc->imask); + + ret = 0; +done: + mutex_unlock(&sc->lock); + return ret; +} + +/* + * Disable the receive h/w in preparation for a reset. + */ +static void ath_stoprecv(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + + ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ + ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ + ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ + mdelay(3); /* 3ms is long enough for 1 frame */ +#ifdef AR_DEBUG + if (sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow + struct ath_desc *ds; + struct ath_buf *bf; + int status; + + printk(KERN_DEBUG "%s: rx queue %x, link %p\n", __func__, + ath5k_hw_get_rx_buf(ah), sc->rxlink); + + spin_lock_bh(&sc->rxbuflock); + list_for_each_entry(bf, &sc->rxbuf, list) { + ds = bf->desc; + status = ah->ah_proc_rx_desc(ah, ds); + if (!status || (sc->debug & ATH_DEBUG_FATAL)) + ath_printrxbuf(bf, status == 0); + } + spin_unlock_bh(&sc->rxbuflock); + } +#endif + sc->rxlink = NULL; /* just in case */ +} + +static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) +{ +#ifdef AR_DEBUG + struct ath_hw *ah = sc->ah; +#endif + struct ath_buf *bf, *bf0; + + /* + * NB: this assumes output has been stopped and + * we do not need to block ath_tx_tasklet + */ + spin_lock_bh(&txq->lock); + list_for_each_entry_safe(bf, bf0, &txq->q, list) { +#ifdef AR_DEBUG + if (sc->debug & ATH_DEBUG_RESET) + ath_printtxbuf(bf, !ah->ah_proc_tx_desc(ah, bf->desc)); +#endif + pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, + PCI_DMA_TODEVICE); + dev_kfree_skb(bf->skb); + bf->skb = NULL; + + spin_lock_bh(&sc->txbuflock); + sc->tx_stats.data[txq->qnum].len--; + list_move_tail(&bf->list, &sc->txbuf); + spin_unlock_bh(&sc->txbuflock); + } + txq->link = NULL; + spin_unlock_bh(&txq->lock); +} + +/* + * Drain the transmit queues and reclaim resources. + */ +static void ath_draintxq(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + int i; + + /* XXX return value */ + if (!sc->invalid) { +#ifdef BLE + /* don't touch the hardware if marked invalid */ + (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, + ath5k_hw_get_tx_buf(ah, sc->bhalq)); +#endif + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) + if (sc->txqs[i].setup) { + ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: txq [%u] %x, " + "link %p\n", __func__, + sc->txqs[i].qnum, + ath5k_hw_get_tx_buf(ah, + sc->txqs[i].qnum), + sc->txqs[i].link); + } + } + ieee80211_start_queues(sc->hw); /* XXX move to callers */ + + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) + if (sc->txqs[i].setup) + ath_tx_draintxq(sc, &sc->txqs[i]); +} + +static int ath_stop_locked(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__, sc->invalid); + + /* + * Shutdown the hardware and driver: + * stop output from above + * disable interrupts + * turn off timers + * turn off the radio + * clear transmit machinery + * clear receive machinery + * drain and release tx queues + * reclaim beacon resources + * power down hardware + * + * Note that some of this work is not possible if the + * hardware is gone (invalid). + */ + ieee80211_stop_queues(sc->hw); + + if (!sc->invalid) { + if (sc->softled) { +#ifdef BLE + del_timer(&sc->ledtimer); + ath5k_hw_set_gpio(ah, sc->ledpin, !sc->ledon); + sc->blinking = 0; +#endif + } + ath5k_hw_set_intr(ah, 0); + } + ath_draintxq(sc); + if (!sc->invalid) { + ath_stoprecv(sc); + ath5k_hw_phy_disable(ah); + } else + sc->rxlink = NULL; +// ath_beacon_free(sc); + + return 0; +} + +/* + * Stop the device, grabbing the top-level lock to protect + * against concurrent entry through ath_init (which can happen + * if another thread does a system call and the thread doing the + * stop is preempted). + */ +static int ath_stop_hw(struct ath_softc *sc) +{ + int ret; + + mutex_lock(&sc->lock); + ret = ath_stop_locked(sc); + if (ret == 0 && !sc->invalid) { + /* + * Set the chip in full sleep mode. Note that we are + * careful to do this only when bringing the interface + * completely to a stop. When the chip is in this state + * it must be carefully woken up or references to + * registers in the PCI clock domain may freeze the bus + * (and system). This varies by chip and is mostly an + * issue with newer parts that go to sleep more quickly. + */ + if (sc->ah->ah_mac_version >= 7 && sc->ah->ah_mac_revision >= 8) { + /* + * XXX + * don't put newer MAC revisions > 7.8 to sleep because + * of the above mentioned problems + */ + DPRINTF(sc, ATH_DEBUG_RESET, "%s: mac version > 7.8, " + "not putting device to sleep\n", __func__); + } + else { + DPRINTF(sc, ATH_DEBUG_RESET, + "%s: putting device to full sleep\n", __func__); + ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); + } + } + mutex_unlock(&sc->lock); + return ret; +} + +static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) +{ +#ifdef BLE + /* from Atheros NDIS driver, w/ permission */ + static const struct { + u16 rate; /* tx/rx 802.11 rate */ + u16 timeOn; /* LED on time (ms) */ + u16 timeOff; /* LED off time (ms) */ + } blinkrates[] = { + { 108, 40, 10 }, + { 96, 44, 11 }, + { 72, 50, 13 }, + { 48, 57, 14 }, + { 36, 67, 16 }, + { 24, 80, 20 }, + { 22, 100, 25 }, + { 18, 133, 34 }, + { 12, 160, 40 }, + { 10, 200, 50 }, + { 6, 240, 58 }, + { 4, 267, 66 }, + { 2, 400, 100 }, + { 0, 500, 130 } + }; +#endif + const struct ath5k_rate_table* rt=ath5k_hw_get_rate_table(sc->ah, mode); +// unsigned int i, j; + + BUG_ON(rt == NULL); +#ifdef BLE + memset(sc->hwmap, 0, sizeof(sc->hwmap)); + for (i = 0; i < 32; i++) { + u8 ix = rt->rate_code_to_index[i]; + if (ix == 0xff) { + sc->hwmap[i].ledon = msecs_to_jiffies(500); + sc->hwmap[i].ledoff = msecs_to_jiffies(130); + continue; + } + sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; + if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == + MODULATION_OFDM) + sc->hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; + /* receive frames include FCS */ + sc->hwmap[i].rxflags = sc->hwmap[i].txflags | + IEEE80211_RADIOTAP_F_FCS; + /* setup blink rate table to avoid per-packet lookup */ + for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) + if (blinkrates[j].rate == /* XXX why 7f? */ + (rt->rates[ix].dot11_rate & 0x7f)) + break; + + sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].timeOn); + sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].timeOff); + } +#endif + sc->curmode = mode; +} + +/* + * Set/change channels. If the channel is really being changed, + * it's done by reseting the chip. To accomplish this we must + * first cleanup any pending DMA, then restart stuff after a la + * ath_init. + */ +static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) +{ + struct ath_hw *ah = sc->ah; + int ret; + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", + __func__, sc->curchan->chan, sc->curchan->freq, + chan->chan, chan->freq); + + if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) { + /* + * To switch channels clear any pending DMA operations; + * wait long enough for the RX fifo to drain, reset the + * hardware at the new frequency, and then re-enable + * the relevant bits of the h/w. + */ + ath5k_hw_set_intr(ah, 0); /* disable interrupts */ + ath_draintxq(sc); /* clear pending tx frames */ + ath_stoprecv(sc); /* turn off frame recv */ + ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, chan, true); + if (ret) { + printk(KERN_ERR "%s: unable to reset channel %u " + "(%u Mhz)\n", __func__, chan->chan, chan->freq); + return ret; + } + sc->curchan = chan; + ath_update_txpow(sc); + + /* + * Re-enable rx framework. + */ + ret = ath_startrecv(sc); + if (ret) { + printk(KERN_ERR "%s: unable to restart recv logic\n", + __func__); + return ret; + } + + /* + * Change channels and update the h/w rate map + * if we're switching; e.g. 11a to 11b/g. + */ +// ath_chan_change(sc, chan); + + /* + * Re-enable interrupts. + */ + ath5k_hw_set_intr(ah, sc->imask); + } + + return 0; +} + +static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, + struct ieee80211_tx_control *ctl) +{ + struct ath_hw *ah = sc->ah; + struct ath_txq *txq = sc->txq; + struct ath_desc *ds = bf->desc; + struct sk_buff *skb = bf->skb; + unsigned int hdrpad, pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; + int ret; + + flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; + bf->ctl = *ctl; + /* XXX endianness */ + bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); + + if (ctl->flags & IEEE80211_TXCTL_NO_ACK) + flags |= AR5K_TXDESC_NOACK; + + if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) + printk(KERN_DEBUG "tx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + + hdrpad = 0; + pktlen = skb->len - hdrpad + FCS_LEN; + + if (ctl->key_idx != HW_KEY_IDX_INVALID) { + keyidx = ctl->key_idx; + pktlen += ctl->icv_len; + } + + ret = ah->ah_setup_tx_desc(ah, ds, pktlen, + ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, + 0xffff, ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0); + if (ret) + goto err_unmap; + + ds->ds_link = 0; + ds->ds_data = bf->skbaddr; + + ret = ah->ah_fill_tx_desc(ah, ds, skb->len, true, true); + if (ret) + goto err_unmap; + + spin_lock_bh(&txq->lock); + list_add_tail(&bf->list, &txq->q); + sc->tx_stats.data[txq->qnum].len++; + if (txq->link == NULL) /* is this first packet? */ + ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); + else /* no, so only link it */ + *txq->link = bf->daddr; + + txq->link = &ds->ds_link; + ath5k_hw_tx_start(ah, txq->qnum); + spin_unlock_bh(&txq->lock); + +// printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); + + return 0; +err_unmap: + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); + return ret; +} + +static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, + struct ieee80211_tx_control *ctl) +{ + struct ath_softc *sc = hw->priv; + struct ath_buf *bf; + unsigned long flags; + + ath_dump_skb(skb, 0); + + spin_lock_irqsave(&sc->txbuflock, flags); + if (list_empty(&sc->txbuf)) { + if (net_ratelimit()) + printk(KERN_ERR "ath: no further txbuf available, " + "dropping packet\n"); + sc->stats.ast_tx_nobuf++; + spin_unlock_irqrestore(&sc->txbuflock, flags); + return -1; + } + bf = list_first_entry(&sc->txbuf, struct ath_buf, list); + list_del(&bf->list); + if (list_empty(&sc->txbuf)) { + sc->stats.ast_tx_qstop++; + ieee80211_stop_queues(hw); + } + spin_unlock_irqrestore(&sc->txbuflock, flags); + + bf->skb = skb; + + if (ath_tx_bf(sc, bf, ctl)) { + bf->skb = NULL; + spin_lock_irqsave(&sc->txbuflock, flags); + list_add_tail(&bf->list, &sc->txbuf); + spin_unlock_irqrestore(&sc->txbuflock, flags); + dev_kfree_skb_any(skb); + return 0; + } + + return 0; +} + +static int ath_reset(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + int ret; + + DPRINTF(sc, ATH_DEBUG_RESET, "resetting\n"); + /* + * Convert to a HAL channel description with the flags + * constrained to reflect the current operating mode. + */ + sc->curchan = hw->conf.chan; + + ath5k_hw_set_intr(ah, 0); + ath_draintxq(sc); + ath_stoprecv(sc); + + ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, sc->curchan, true); + if (ret) { + printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); + goto err; + } + ath_update_txpow(sc); + + ret = ath_startrecv(sc); + if (ret) { + printk(KERN_ERR "ath: can't start recv logic\n"); + goto err; + } + /* + * We may be doing a reset in response to an ioctl + * that changes the channel so update any state that + * might change as a result. + */ +// ath_chan_change(sc, c); + ath5k_hw_set_intr(ah, sc->imask); + + ieee80211_wake_queues(hw); + + return 0; +err: + return ret; +} + +static int ath_open(struct ieee80211_hw *hw) +{ + return ath_init(hw->priv); +} + +static int ath_stop(struct ieee80211_hw *hw) +{ + return ath_stop_hw(hw->priv); +} + +static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) +{ + struct ath_softc *sc = hw->priv; + + ath_setcurmode(sc, conf->phymode); + + return ath_chan_set(sc, conf->chan); +} + +static int ath_set_key(struct ieee80211_hw *hw, set_key_cmd cmd, + u8 *addr, struct ieee80211_key_conf *key, int aid) +{ + struct ath_softc *sc = hw->priv; + int ret = 0; + + mutex_lock(&sc->lock); + + switch (cmd) { + case SET_KEY: + if (key->alg != ALG_WEP && key->alg != ALG_NONE && + key->alg != ALG_NULL) { + ret = -EINVAL; + goto unlock; + } + + ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr); + if (ret) { + printk(KERN_ERR "ath: can't set the key\n"); + goto unlock; + } + + set_bit(key->keyidx, sc->keymap); + key->hw_key_idx = key->keyidx; + key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT; + break; + case DISABLE_KEY: + ath5k_hw_reset_key(sc->ah, key->keyidx); + clear_bit(key->keyidx, sc->keymap); + break; + case REMOVE_ALL_KEYS: { + unsigned int i; + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) { + ath5k_hw_reset_key(sc->ah, i); + clear_bit(i, sc->keymap); + } + break; + } + default: + ret = -EINVAL; + goto unlock; + } + +unlock: + mutex_unlock(&sc->lock); + return ret; +} + +static int ath_get_stats(struct ieee80211_hw *hw, + struct ieee80211_low_level_stats *stats) +{ + struct ath_softc *sc = hw->priv; + + memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); + + return 0; +} + +static int ath_get_tx_stats(struct ieee80211_hw *hw, + struct ieee80211_tx_queue_stats *stats) +{ + struct ath_softc *sc = hw->priv; + + memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); + + return 0; +} + +static u64 ath_get_tsf(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + return ath5k_hw_get_tsf64(sc->ah); +} + +static void ath_reset_tsf(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + ath5k_hw_reset_tsf(sc->ah); +} + +static struct ieee80211_ops ath_hw_ops = { + .tx = ath_tx, + .reset = ath_reset, + .open = ath_open, + .stop = ath_stop, + .add_interface = NULL, + .remove_interface = NULL, + .config = ath_config, + .config_interface = NULL, + .set_key = ath_set_key, + .get_stats = ath_get_stats, + .conf_tx = NULL, + .get_tx_stats = ath_get_tx_stats, + .get_tsf = ath_get_tsf, + .reset_tsf = ath_reset_tsf, + .beacon_update = NULL, +}; + +static irqreturn_t ath_intr(int irq, void *dev_id) +{ + struct ath_softc *sc = dev_id; + struct ath_hw *ah = sc->ah; + enum ath5k_int status; + unsigned int counter = 1000; + + if (sc->invalid || !ath5k_hw_is_intr_pending(ah)) + return IRQ_NONE; + + do { + /* + * Figure out the reason(s) for the interrupt. Note + * that the hal returns a pseudo-ISR that may include + * bits we haven't explicitly enabled so we mask the + * value to insure we only process bits we requested. + */ + ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ + DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x/0x%x\n", __func__, + status, sc->imask); + status &= sc->imask; /* discard unasked for bits */ + if (status & AR5K_INT_FATAL) { + /* + * Fatal errors are unrecoverable. Typically + * these are caused by DMA errors. Unfortunately + * the exact reason is not (presently) returned + * by the hal. + */ + sc->stats.ast_hardware++; + ath_reset(sc->hw); + } else if (status & AR5K_INT_RXORN) { + sc->stats.ast_rxorn++; + ath_reset(sc->hw); + } else { + if (status & AR5K_INT_SWBA) { + /* + * Software beacon alert--time to send a beacon. + * Handle beacon transmission directly; deferring + * this is too slow to meet timing constraints + * under load. + */ +// ath_beacon_send(dev); + } + if (status & AR5K_INT_RXEOL) { + /* + * NB: the hardware should re-read the link when + * RXE bit is written, but it doesn't work at + * least on older hardware revs. + */ + sc->stats.ast_rxeol++; + sc->rxlink = NULL; + } + if (status & AR5K_INT_TXURN) { + sc->stats.ast_txurn++; + /* bump tx trigger level */ + ath5k_hw_update_tx_triglevel(ah, true); + } + if (status & AR5K_INT_RX) + tasklet_schedule(&sc->rxtq); + if (status & AR5K_INT_TX) + tasklet_schedule(&sc->txtq); +/* if (status & AR5K_INT_BMISS) { + sc->stats.ast_bmiss++; + tasklet_schedule(&sc->bmisstq); + }*/ + if (status & AR5K_INT_MIB) { + sc->stats.ast_mib++; + /* TODO */ + } + } + } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); + + if (!counter && net_ratelimit()) + printk(KERN_WARNING "ath: too many interrupts, giving up for " + "now\n"); + + return IRQ_HANDLED; +} + +/* + * Convert IEEE channel number to MHz frequency. + */ +static inline short ath_ieee2mhz(short chan) +{ + if (chan <= 14 || chan >= 27) + return ieee80211chan2mhz(chan); + else + return 2212 + chan * 20; +} + +static unsigned int ath_copy_rates(struct ieee80211_rate *rates, + const struct ath5k_rate_table *rt, unsigned int max) +{ + unsigned int i; + + if (rt == NULL) + return 0; + + for (i = 0; i < rt->rate_count && max > 0; i++, rates++, max--) { + rates->rate = rt->rates[i].rate_kbps / 100; + rates->val = rt->rates[i].rate_code; + rates->flags = rt->rates[i].modulation; + } + + return i; +} + +static unsigned int ath_copy_channels(struct ath_hw *ah, + struct ieee80211_channel *channels, unsigned int mode, + unsigned int max) +{ + static const struct { unsigned int mode, mask, chan; } map[] = { + [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A }, + [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T }, + [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B }, + [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G }, + [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG }, + }; + static const struct ieee80211_regchannel chans_2ghz[] = + IEEE80211_CHANNELS_2GHZ; + static const struct ieee80211_regchannel chans_5ghz[] = + IEEE80211_CHANNELS_5GHZ; + const struct ieee80211_regchannel *chans; + enum ieee80211_regdomain dmn; + unsigned int i, count, size, chfreq, all, f, ch; + + if (!test_bit(mode, ah->ah_modes)) + return 0; + + all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1; + + switch (mode) { + case MODE_IEEE80211A: + case MODE_ATHEROS_TURBO: + /* 1..220, but 2GHz frequencies are filtered by check_channel */ + size = all ? 220 : ARRAY_SIZE(chans_5ghz); + chans = chans_5ghz; + dmn = ieee80211_regdomain2flag(ah->ah_regdomain, + IEEE80211_CHANNELS_5GHZ_MIN); + chfreq = CHANNEL_5GHZ; + break; + case MODE_IEEE80211B: + case MODE_IEEE80211G: + case MODE_ATHEROS_TURBOG: + size = all ? 26 : ARRAY_SIZE(chans_2ghz); + chans = chans_2ghz; + dmn = ieee80211_regdomain2flag(ah->ah_regdomain, + IEEE80211_CHANNELS_2GHZ_MIN); + chfreq = CHANNEL_2GHZ; + break; + default: + printk(KERN_WARNING "bad mode, not copying channels\n"); + return 0; + } + + for (i = 0, count = 0; i < size && max > 0; i++) { + ch = all ? i + 1 : chans[i].chan; + f = ath_ieee2mhz(ch); + /* Check if channel is supported by the chipset */ + if (ath5k_check_channel(ah, f, chfreq) == false) + continue; + + /* Match regulation domain */ + if (!all && !(IEEE80211_DMN(chans[i].domain) & + IEEE80211_DMN(dmn))) + continue; + + if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode) + continue; + + /* Write channel and increment counter */ + channels->chan = ch; + channels->freq = f; + channels->val = map[mode].chan; + channels++; + count++; + max--; + } + + return count; +} + +#if ATH_DEBUG_MODES +static void ath_dump_modes(struct ieee80211_hw_mode *modes) +{ + unsigned int m, i; + + for (m = 0; m < NUM_IEEE80211_MODES; m++) { + printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m, + modes[m].num_channels, modes[m].num_rates); + printk(KERN_DEBUG " channels:\n"); + for (i = 0; i < modes[m].num_channels; i++) { + printk(KERN_DEBUG " %3d %d %.4x %.4x\n", + modes[m].channels[i].chan, + modes[m].channels[i].freq, + modes[m].channels[i].val, + modes[m].channels[i].flag); + } + printk(KERN_DEBUG " rates:\n"); + for (i = 0; i < modes[m].num_rates; i++) { + printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n", + modes[m].rates[i].rate, + modes[m].rates[i].val, + modes[m].rates[i].flags, + modes[m].rates[i].val2); + } + } +} +#else +static inline void ath_dump_modes(struct ieee80211_hw_mode *modes) {} +#endif + +static int ath_getchannels(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + struct ieee80211_hw_mode *modes = sc->modes; + unsigned int i, max; + int ret; + enum { + A = MODE_IEEE80211A, + B = MODE_IEEE80211B, + G = MODE_IEEE80211G, + T = MODE_ATHEROS_TURBO, + TG = MODE_ATHEROS_TURBOG, + }; + + BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 5); + + ah->ah_country_code = countrycode; + + modes[A].mode = MODE_IEEE80211A; + modes[B].mode = MODE_IEEE80211B; + modes[G].mode = MODE_IEEE80211G; + + max = ARRAY_SIZE(sc->rates); + modes[A].rates = sc->rates; + max -= modes[A].num_rates = ath_copy_rates(modes[A].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211A), max); + modes[B].rates = &modes[A].rates[modes[A].num_rates]; + max -= modes[B].num_rates = ath_copy_rates(modes[B].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211B), max); + modes[G].rates = &modes[B].rates[modes[B].num_rates]; + max -= modes[G].num_rates = ath_copy_rates(modes[G].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211G), max); + + if (!max) + printk(KERN_WARNING "yet another rates found, but there is not " + "sufficient space to store them\n"); + + max = ARRAY_SIZE(sc->channels); + modes[A].channels = sc->channels; + max -= modes[A].num_channels = ath_copy_channels(ah, modes[A].channels, + MODE_IEEE80211A, max); + modes[B].channels = &modes[A].channels[modes[A].num_channels]; + max -= modes[B].num_channels = ath_copy_channels(ah, modes[B].channels, + MODE_IEEE80211B, max); + modes[G].channels = &modes[B].channels[modes[B].num_channels]; + max -= modes[G].num_channels = ath_copy_channels(ah, modes[G].channels, + MODE_IEEE80211G, max); + + if (!max) + printk(KERN_WARNING "yet another modes found, but there is not " + "sufficient space to store them\n"); + + for (i = 0; i < ARRAY_SIZE(sc->modes); i++) + if (modes[i].num_channels) { + ret = ieee80211_register_hwmode(hw, &modes[i]); + if (ret) { + printk(KERN_ERR "can't register hwmode %u\n",i); + goto err; + } + } + ath_dump_modes(modes); + + return 0; +err: + return ret; +} + +static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) +{ + struct ath_desc *ds; + struct ath_buf *bf; + dma_addr_t da; + unsigned int i; + int ret; + + /* allocate descriptors */ + sc->desc_len = sizeof(struct ath_desc) * + (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); + sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); + if (sc->desc == NULL) { + dev_err(&pdev->dev, "can't allocate descriptors\n"); + ret = -ENOMEM; + goto err; + } + ds = sc->desc; + da = sc->desc_daddr; + DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", + __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); + + bf = kcalloc(ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1, + sizeof(struct ath_buf), GFP_KERNEL); + if (bf == NULL) { + dev_err(&pdev->dev, "can't allocate bufptr\n"); + ret = -ENOMEM; + goto err_free; + } + sc->bufptr = bf; + + INIT_LIST_HEAD(&sc->rxbuf); + for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->rxbuf); + } + + INIT_LIST_HEAD(&sc->txbuf); + for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC, + da += ATH_TXDESC * sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->txbuf); + } +#ifdef BLE + INIT_LIST_HEAD(&sc->bbuf); + for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->bbuf); + } +#endif + + return 0; +err_free: + pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); +err: + sc->desc = NULL; + return ret; +} + +static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, + struct list_head *head) +{ + struct ath_buf *bf; + + list_for_each_entry(bf, head, list) { + if (bf->skb) { + pci_unmap_single(pdev, bf->skbaddr, sc->rxbufsize, + PCI_DMA_FROMDEVICE); + dev_kfree_skb(bf->skb); + bf->skb = NULL; + } + } +} + +static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) +{ +// ath_descdma_cleanup(sc, pdev, &sc->bbuf); + ath_descdma_cleanup(sc, pdev, &sc->txbuf); + ath_descdma_cleanup(sc, pdev, &sc->rxbuf); + + /* Free memory associated with all descriptors */ + pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); + + kfree(sc->bufptr); + sc->bufptr = NULL; +} +#ifdef BLE +static int ath_beaconq_setup(struct ath_hw *ah) +{ + struct ath5k_txq_info qi; + + memset(&qi, 0, sizeof(qi)); + qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; + /* NB: for dynamic turbo, don't enable any other interrupts */ + qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + + return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); +} +#endif +static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, + int subtype) +{ + struct ath_hw *ah = sc->ah; + struct ath_txq *txq; + struct ath5k_txq_info qi; + int qnum; + + memset(&qi, 0, sizeof(qi)); + qi.tqi_subtype = subtype; + qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; + qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; + /* + * Enable interrupts only for EOL and DESC conditions. + * We mark tx descriptors to receive a DESC interrupt + * when a tx queue gets deep; otherwise waiting for the + * EOL to reap descriptors. Note that this is done to + * reduce interrupt load and this only defers reaping + * descriptors, never transmitting frames. Aside from + * reducing interrupts this also permits more concurrency. + * The only potential downside is if the tx queue backs + * up in which case the top half of the kernel may backup + * due to a lack of tx descriptors. + */ + qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | + AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); + if (qnum < 0) { + /* + * NB: don't print a message, this happens + * normally on parts with too few tx queues + */ + return ERR_PTR(qnum); + } + if (qnum >= ARRAY_SIZE(sc->txqs)) { + printk(KERN_ERR "hal qnum %u out of range, max %u!\n", + qnum, ARRAY_SIZE(sc->txqs)); + ath5k_hw_release_tx_queue(ah, qnum); + return ERR_PTR(-EINVAL); + } + txq = &sc->txqs[qnum]; + if (!txq->setup) { + txq->qnum = qnum; + txq->link = NULL; + INIT_LIST_HEAD(&txq->q); + spin_lock_init(&txq->lock); + txq->setup = true; + } + return &sc->txqs[qnum]; +} + +static void ath_tx_cleanup(struct ath_softc *sc) +{ + struct ath_txq *txq = sc->txqs; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) + if (txq->setup) { + ath5k_hw_release_tx_queue(sc->ah, txq->qnum); + txq->setup = false; + } +} + +static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + u8 mac[ETH_ALEN]; + unsigned int i; + int ret; + + DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); + + /* + * Check if the MAC has multi-rate retry support. + * We do this by trying to setup a fake extended + * descriptor. MAC's that don't have support will + * return false w/o doing anything. MAC's that do + * support it will return true w/o doing anything. + */ + sc->mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); + + /* + * Reset the key cache since some parts do not + * reset the contents on initial power up. + */ + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) + ath5k_hw_reset_key(ah, i); + + /* + * Collect the channel list using the default country + * code and including outdoor channels. The 802.11 layer + * is resposible for filtering this list based on settings + * like the phy mode. + */ + ret = ath_getchannels(hw); + if (ret) { + dev_err(&pdev->dev, "can't get channels\n"); + goto err; + } + + /* NB: setup here so ath_rate_update is happy */ + if (test_bit(MODE_IEEE80211A, ah->ah_modes)) + ath_setcurmode(sc, MODE_IEEE80211A); + else + ath_setcurmode(sc, MODE_IEEE80211B); + + /* + * Allocate tx+rx descriptors and populate the lists. + */ + ret = ath_desc_alloc(sc, pdev); + if (ret) { + dev_err(&pdev->dev, "can't allocate descriptors\n"); + goto err; + } + +#ifdef BLE + /* + * Allocate hardware transmit queues: one queue for + * beacon frames and one data queue for each QoS + * priority. Note that the hal handles reseting + * these queues at the needed time. + * + * XXX PS-Poll + */ + ret = ath_beaconq_setup(ah); + if (ret < 0) { + dev_err(&pdev->dev, "can't setup a beacon xmit queue\n"); + goto err_desc; + } + sc->bhalq = ret; + + sc->cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); + if (IS_ERR(sc->cabq)) { + dev_err(&pdev->dev, "can't setup CAB xmit queue\n"); + ret = PTR_ERR(sc->cabq); + sc->cabq = NULL; + goto err_queues; + } +#endif + sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); + if (IS_ERR(sc->txq)) { + dev_err(&pdev->dev, "can't setup xmit queue\n"); + ret = PTR_ERR(sc->txq); + goto err_queues; + } + + tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); + tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); +#ifdef BLE + /* + * Setup rate control. Some rate control modules + * call back to change the anntena state so expose + * the necessary entry points. + * XXX maybe belongs in struct ath_ratectrl? + */ + sc->sc_setdefantenna = ath_setdefantenna; + sc->sc_rc = ath_rate_attach(sc); + if (sc->sc_rc == NULL) { + error = EIO; + goto bad2; + } + + setup_timer(&sc->scan_ch, ath_next_scan, (unsigned long)hw); + setup_timer(&sc->cal_ch, ath_calibrate, (unsigned long)hw); + + sc->blinking = 0; + sc->ledstate = 1; + sc->ledon = 0; /* low true */ + sc->ledidle = msecs_to_jiffies(2700); /* 2.7sec */ + + setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); + /* + * Auto-enable soft led processing for IBM cards and for + * 5211 minipci cards. Users can also manually enable/disable + * support with a sysctl. + */ + sc->sc_softled = (devid == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || + devid == PCI_DEVICE_ID_ATHEROS_AR5211); + if (sc->sc_softled) { + ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); + ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); + } + + sc->sc_hasclrkey = ath_hal_ciphersupported(ah, AR5K_CIPHER_CLR); + sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); + + /* + * Query the hal about antenna support. + */ + sc->sc_defant = ath5k_hw_get_def_antenna(ah); + + /* + * Not all chips have the VEOL support we want to + * use with IBSS beacons; check here for it. + */ + sc->sc_hasveol = ath_hal_hasveol(ah); + + sc->sc_rxfilter = 0; +#endif + + ath5k_hw_get_lladdr(ah, mac); + SET_IEEE80211_PERM_ADDR(hw, mac); + if (ath_hal_hasbssidmask(ah)) { + memset(sc->bssidmask, 0xff, ETH_ALEN); + ath5k_hw_set_bssid_mask(ah, sc->bssidmask); + } + + ret = ieee80211_register_hw(hw); + if (ret) { + dev_err(&pdev->dev, "can't register ieee80211 hw\n"); + goto err_queues; + } + +// ath_dynamic_sysctl_register(sc); +// ath_announce(sc); + + return 0; +err_queues: + ath_tx_cleanup(sc); +//err_desc: + ath_desc_free(sc, pdev); +err: + return ret; +} + +static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + ath_stop_hw(sc); /* XXX needed? */ + /* + * NB: the order of these is important: + * o call the 802.11 layer before detaching the hal to + * insure callbacks into the driver to delete global + * key cache entries can be handled + * o reclaim the tx queue data structures after calling + * the 802.11 layer as we'll get called back to reclaim + * node state and potentially want to use them + * o to cleanup the tx queues the hal is called, so detach + * it last + * Other than that, it's straightforward... + */ + ieee80211_unregister_hw(hw); + ath_desc_free(sc, pdev); + ath_tx_cleanup(sc); + + /* + * NB: can't reclaim these until after ieee80211_ifdetach + * returns because we'll get called back to reclaim node + * state and potentially want to use them. + */ +// ath_dynamic_sysctl_unregister(sc); +} + +static const char *ath_chip_name(u8 mac_version) +{ + switch (mac_version) { + case AR5K_AR5210: + return "AR5210"; + case AR5K_AR5211: + return "AR5211"; + case AR5K_AR5212: + return "AR5212"; + } + return "Unknown"; +} + +static int __devinit ath_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + void __iomem *mem; + struct ath_softc *sc; + struct ieee80211_hw *hw; + int ret; + u8 csz; + + ret = pci_enable_device(pdev); + if (ret) { + dev_err(&pdev->dev, "can't enable device\n"); + goto err; + } + + /* XXX 32-bit addressing only */ + ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); + if (ret) { + dev_err(&pdev->dev, "32-bit DMA not available\n"); + goto err_dis; + } + + /* + * Cache line size is used to size and align various + * structures used to communicate with the hardware. + */ + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); + if (csz == 0) { + /* + * Linux 2.4.18 (at least) writes the cache line size + * register as a 16-bit wide register which is wrong. + * We must have this setup properly for rx buffer + * DMA to work so force a reasonable value here if it + * comes up zero. + */ + csz = L1_CACHE_BYTES / sizeof(u32); + pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); + } + /* + * The default setting of latency timer yields poor results, + * set it to the value used by other systems. It may be worth + * tweaking this setting more. + */ + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); + + pci_set_master(pdev); + + /* + * Disable the RETRY_TIMEOUT register (0x41) to keep + * PCI Tx retries from interfering with C3 CPU state. + */ + pci_write_config_byte(pdev, 0x41, 0); + + ret = pci_request_region(pdev, 0, "ath"); + if (ret) { + dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); + goto err_dis; + } + + mem = pci_iomap(pdev, 0, 0); + if (!mem) { + dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; + ret = -EIO; + goto err_reg; + } + + hw = ieee80211_alloc_hw(sizeof(*sc), &ath_hw_ops); + if (hw == NULL) { + dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); + ret = -ENOMEM; + goto err_map; + } + + SET_IEEE80211_DEV(hw, &pdev->dev); + hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_WEP_INCLUDE_IV | + IEEE80211_HW_DATA_NULLFUNC_ACK; + hw->extra_tx_headroom = 2; + hw->channel_change_time = 5000; + hw->max_rssi = 127; /* FIXME: get a real value for this. */ + sc = hw->priv; + sc->hw = hw; + + /* + * Mark the device as detached to avoid processing + * interrupts until setup is complete. + */ + sc->debug = ath_debug; + sc->invalid = 1; + sc->iobase = mem; + sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ + mutex_init(&sc->lock); + spin_lock_init(&sc->rxbuflock); + spin_lock_init(&sc->txbuflock); + + pci_set_drvdata(pdev, hw); + + ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc); + if (ret) { + dev_err(&pdev->dev, "request_irq failed\n"); + goto err_free; + } + + sc->ah = ath5k_hw_attach(pdev->device, id->driver_data, sc, sc->iobase); + if (IS_ERR(sc->ah)) { + ret = PTR_ERR(sc->ah); + goto err_irq; + } + + ret = ath_attach(pdev, hw); + if (ret) + goto err_ah; + + dev_info(&pdev->dev, "%s chip found: mac %d.%d phy %d.%d\n", + ath_chip_name(id->driver_data), sc->ah->ah_mac_version, + sc->ah->ah_mac_version, sc->ah->ah_phy_revision >> 4, + sc->ah->ah_phy_revision & 0xf); + + /* ready to process interrupts */ + sc->invalid = 0; + + return 0; +err_ah: + ath5k_hw_detach(sc->ah); +err_irq: + free_irq(pdev->irq, sc); +err_free: + ieee80211_free_hw(hw); +err_map: + pci_iounmap(pdev, mem); +err_reg: + pci_release_region(pdev, 0); +err_dis: + pci_disable_device(pdev); +err: + return ret; +} + +static void __devexit ath_pci_remove(struct pci_dev *pdev) +{ + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; + + ath_detach(pdev, hw); + ath5k_hw_detach(sc->ah); + free_irq(pdev->irq, sc); + pci_iounmap(pdev, sc->iobase); + pci_release_region(pdev, 0); + pci_disable_device(pdev); + ieee80211_free_hw(hw); +} + +#ifdef CONFIG_PM +static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) +{ + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; + + if (sc->softled) + ath5k_hw_set_gpio(sc->ah, sc->ledpin, 1); + + ath_stop_hw(sc); + pci_save_state(pdev); + pci_disable_device(pdev); + pci_set_power_state(pdev, PCI_D3hot); + + return 0; +} + +static int ath_pci_resume(struct pci_dev *pdev) +{ + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; + int err; + + err = pci_set_power_state(pdev, PCI_D0); + if (err) + return err; + + err = pci_enable_device(pdev); + if (err) + return err; + + pci_restore_state(pdev); + /* + * Suspend/Resume resets the PCI configuration space, so we have to + * re-disable the RETRY_TIMEOUT register (0x41) to keep + * PCI Tx retries from interfering with C3 CPU state + */ + pci_write_config_byte(pdev, 0x41, 0); + + ath_init(sc); + if (sc->softled) { + ath5k_hw_set_gpio_output(sc->ah, sc->ledpin); + ath5k_hw_set_gpio(sc->ah, sc->ledpin, 0); + } + + return 0; +} +#else +#define ath_pci_suspend NULL +#define ath_pci_resume NULL +#endif /* CONFIG_PM */ + +static struct pci_driver ath_pci_drv_id = { + .name = "ath_pci", + .id_table = ath_pci_id_table, + .probe = ath_pci_probe, + .remove = __devexit_p(ath_pci_remove), + .suspend = ath_pci_suspend, + .resume = ath_pci_resume, +}; + +/* + * Static (i.e. global) sysctls. Note that the hal sysctls + * are located under ours by sharing the setting for DEV_ATH. + */ +enum { + DEV_ATH = 9, /* XXX known by hal */ +}; + +#define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ + +static ctl_table ath_static_sysctls[] = { +#ifdef AR_DEBUG + { .ctl_name = CTL_AUTO, + .procname = "debug", + .mode = 0644, + .data = &ath_debug, + .maxlen = sizeof(ath_debug), + .proc_handler = proc_dointvec + }, +#endif + { .ctl_name = CTL_AUTO, + .procname = "countrycode", + .mode = 0444, + .data = &countrycode, + .maxlen = sizeof(countrycode), + .proc_handler = proc_dointvec + }, +/* { .ctl_name = CTL_AUTO, + .procname = "regdomain", + .mode = 0444, + .data = &ath_regdomain, + .maxlen = sizeof(ath_regdomain), + .proc_handler = proc_dointvec + },*/ + { .ctl_name = CTL_AUTO, + .procname = "outdoor", + .mode = 0444, + .data = &outdoor, + .maxlen = sizeof(outdoor), + .proc_handler = proc_dointvec + }, + { .ctl_name = CTL_AUTO, + .procname = "xchanmode", + .mode = 0444, + .data = &xchanmode, + .maxlen = sizeof(xchanmode), + .proc_handler = proc_dointvec + }, +/* { .ctl_name = CTL_AUTO, + .procname = "dwelltime", + .mode = 0644, + .data = &ath_dwelltime, + .maxlen = sizeof(ath_dwelltime), + .extra1 = &mindwelltime, + .extra2 = &maxint, + .proc_handler = proc_dointvec_minmax + }, + { .ctl_name = CTL_AUTO, + .procname = "calibrate", + .mode = 0644, + .data = &ath_calinterval, + .maxlen = sizeof(ath_calinterval), + .extra1 = &mincalibrate, + .extra2 = &maxint, + .proc_handler = proc_dointvec_minmax + },*/ + { 0 } +}; +static ctl_table ath_ath_table[] = { + { .ctl_name = DEV_ATH, + .procname = "ath", + .mode = 0555, + .child = ath_static_sysctls + }, { 0 } +}; +static ctl_table ath_root_table[] = { + { .ctl_name = CTL_DEV, + .procname = "dev", + .mode = 0555, + .child = ath_ath_table + }, { 0 } +}; +static struct ctl_table_header *ath_sysctl_header; + +/* + * Module glue. + */ +static int __init init_ath_pci(void) +{ + int ret; + + ret = pci_register_driver(&ath_pci_drv_id); + if (ret) { + printk(KERN_ERR "ath_pci: can't register pci driver\n"); + return ret; + } + ath_sysctl_header = register_sysctl_table(ath_root_table); + + return 0; +} + +static void __exit exit_ath_pci(void) +{ + if (ath_sysctl_header) + unregister_sysctl_table(ath_sysctl_header); + pci_unregister_driver(&ath_pci_drv_id); +} + +module_init(init_ath_pci); +module_exit(exit_ath_pci); + +MODULE_AUTHOR("Jiri Slaby"); +MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); +MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION(ATH_PCI_VERSION " (EXPERIMENTAL)"); diff --git a/ath.h b/ath.h new file mode 100644 index 0000000..a085294 --- /dev/null +++ b/ath.h @@ -0,0 +1,278 @@ +/*- + * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.20 2005/01/24 20:31:24 sam Exp $ + */ + +/* + * Defintions for the Atheros Wireless LAN controller driver. + */ +#ifndef _DEV_ATH_ATHVAR_H +#define _DEV_ATH_ATHVAR_H + +#include +#include +#include +#include + +#include "ath5k.h" +#include "ath_ioctl.h" + +#define ATH_TIMEOUT 1000 + +/* + * Maximum acceptable MTU + * MAXFRAMEBODY - WEP - QOS - RSN/WPA: + * 2312 - 8 - 2 - 12 = 2290 + */ +#define ATH_MAX_MTU 2290 +#define ATH_MIN_MTU 32 + +#define ATH_RXBUF 40 /* number of RX buffers */ +#define ATH_TXBUF 200 /* number of TX buffers */ +#define ATH_TXDESC 1 /* number of descriptors per buffer */ +#define ATH_BCBUF 1 /* number of beacon buffers */ +#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ +#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ + +#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ +#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ +#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ + +#define ATH_RSSI_LPF_LEN 10 +#define ATH_RSSI_DUMMY_MARKER 0x127 +#define ATH_EP_MUL(x, mul) ((x) * (mul)) +#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), AR5K_RSSI_EP_MULTIPLIER)) +#define ATH_LPF_RSSI(x, y, len) \ + ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) +#define ATH_RSSI_LPF(x, y) do { \ + if ((y) >= -20) \ + x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ +} while (0) + +struct ath_buf { + struct list_head list; + unsigned int flags; /* tx descriptor flags */ + struct ath_desc *desc; /* virtual addr of desc */ + dma_addr_t daddr; /* physical addr of desc */ + struct sk_buff *skb; /* skbuff for buf */ + dma_addr_t skbaddr;/* physical addr of skb data */ + struct ieee80211_tx_control ctl; +}; + +/* + * Data transmit queue state. One of these exists for each + * hardware transmit queue. Packets sent to us from above + * are assigned to queues based on their priority. Not all + * devices support a complete set of hardware transmit queues. + * For those devices the array sc_ac2q will map multiple + * priorities to fewer hardware queues (typically all to one + * hardware queue). + */ +struct ath_txq { + unsigned int qnum; /* hardware q number */ + u32 *link; /* link ptr in last TX desc */ + struct list_head q; /* transmit queue */ + spinlock_t lock; /* lock on q and link */ + bool setup; +}; + +#if CHAN_DEBUG +#define ATH_CHAN_MAX (26+26+26+200+200) +#else +#define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */ +#endif + +struct ath_softc { + struct pci_dev *pdev; /* for dma mapping */ + void __iomem *iobase; /* address of the device */ + struct mutex lock; /* dev-level lock */ + struct ath_stats stats; /* private statistics */ + struct ieee80211_tx_queue_stats tx_stats; + struct ieee80211_low_level_stats ll_stats; + struct ieee80211_hw *hw; /* IEEE 802.11 common */ + struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; + struct ieee80211_channel channels[ATH_CHAN_MAX]; + struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_IEEE80211_MODES]; + struct ath_hw *ah; /* Atheros HW */ +#ifdef BLE + enum ieee80211_if_types sc_opmode; + int sc_regdomain; + int sc_countrycode; +#endif + int debug; + + struct ath_buf *bufptr; /* allocated buffer ptr */ + struct ath_desc *desc; /* TX/RX descriptors */ + dma_addr_t desc_daddr; /* DMA (physical) address */ + size_t desc_len; /* size of TX/RX descriptors */ + u16 cachelsz; /* cache line size */ +#ifdef BLE + struct ath_ratectrl *sc_rc; /* tx rate control support */ + void (*sc_setdefantenna)(struct ath_softc *, u_int); +#endif + unsigned int invalid : 1, /* disable hardware accesses */ + mrretry : 1, /* multi-rate retry support */ + softled : 1, /* enable LED gpio status */ + xxx:1; +#ifdef BLE + sc_splitmic: 1, /* split TKIP MIC keys */ + sc_needmib : 1, /* enable MIB stats intr */ + sc_diversity : 1,/* enable rx diversity */ + sc_lockslottime : 1,/* lock slot time value */ + sc_hasveol : 1, /* tx VEOL support */ + sc_ledstate: 1, /* LED on/off state */ + sc_blinking: 1, /* LED blink operation active */ + sc_endblink: 1, /* finish LED blink operation */ + sc_mcastkey: 1, /* mcast key cache search */ + sc_hasclrkey:1; /* CLR key supported */ + /* rate tables */ + const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; + const struct ath5k_rate_table *sc_currates; /* current rate table */ +#endif + unsigned int curmode; /* current phy mode */ + struct ieee80211_channel *curchan; /* current h/w channel */ +#ifdef BLE + u16 sc_curtxpow; /* current tx power limit */ + u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ + + struct { +// int ieeerate; /* IEEE rate */ + u8 rxflags; /* radiotap rx flags */ + u8 txflags; /* radiotap tx flags */ + u16 ledon; /* softled on time */ + u16 ledoff; /* softled off time */ + } hwmap[32]; /* h/w rate ix mappings */ + + u8 sc_protrix; /* protection rate index */ + u_int sc_txantenna; /* tx antenna (fixed or auto) */ +#endif + enum ath5k_int imask; /* interrupt mask copy */ + + DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ + + u8 bssidmask[ETH_ALEN]; + unsigned int ledpin; /* GPIO pin for driving LED */ +#ifdef BLE + u_int sc_ledon; /* pin setting for LED on */ + u_int sc_ledidle; /* idle polling interval */ + int sc_ledevent; /* time of last LED event */ + u8 sc_rxrate; /* current rx rate for LED */ + u8 sc_txrate; /* current tx rate for LED */ + u16 sc_ledoff; /* off time for current blink */ + struct timer_list sc_ledtimer; /* led off timer */ + + union { + struct ath_tx_radiotap_header th; + u8 pad[64]; + } u_tx_rt; + int sc_tx_th_len; + union { + struct ath_rx_radiotap_header th; + u8 pad[64]; + } u_rx_rt; + int sc_rx_th_len; + struct tasklet_struct sc_radartq; /* Radar detection */ +#endif + unsigned int rxbufsize; /* rx size based on mtu */ + struct list_head rxbuf; /* receive buffer */ + spinlock_t rxbuflock; + u32 *rxlink; /* link ptr in last RX desc */ + struct tasklet_struct rxtq; /* rx intr tasklet */ +#ifdef BLE + u8 sc_defant; /* current default antenna */ + u8 sc_rxotherant; /* rx's on non-default antenna*/ +#endif + struct list_head txbuf; /* transmit buffer */ + spinlock_t txbuflock; + struct ath_txq txqs[2]; /* beacon and tx */ +#ifdef BLE + int sc_tx_timer; /* transmit timeout */ + u_int sc_txintrperiod;/* tx interrupt batching */ + struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ +#endif + struct ath_txq *txq; /* beacon and tx*/ + struct tasklet_struct txtq; /* tx intr tasklet */ + +#ifdef BLE + struct list_head bbuf; /* beacon buffers */ + unsigned int bhalq; /* HAL q for outgoing beacons */ + u_int sc_bmisscount; /* missed beacon transmits */ + u32 sc_ant_tx[8]; /* recent tx frames/antenna */ + struct ieee80211_beacon_offsets boff; /* dynamic update state */ + struct ath_txq *cabq; /* tx q for cab frames */ + + struct tasklet_struct bmisstq; /* bmiss intr tasklet */ + + struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ + enum { + OK, /* no change needed */ + UPDATE, /* update pending */ + COMMIT /* beacon sent, commit change */ + } sc_updateslot; /* slot time update fsm */ + + struct timer_list sc_cal_ch; /* calibration timer */ + struct timer_list sc_scan_ch; /* AP scan timer */ + struct iw_statistics sc_iwstats; /* wireless statistics block */ + struct ctl_table_header *sc_sysctl_header; + struct ctl_table *sc_sysctls; +#endif +}; + +void ath_sysctl_register(void); +void ath_sysctl_unregister(void); + +#define ath_hal_getcountrycode(_ah, _pcc) \ + (*(_pcc) = (_ah)->ah_country_code) +#define ath_hal_tkipsplit(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == 0) +#define ath_hal_hwphycounters(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == 0) +#define ath_hal_getnumtxqueues(_ah, _pv) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == 0) +#define ath_hal_hasveol(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) +#define ath_hal_hastpc(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == 0) +#define ath_hal_gettpc(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == 0) +#define ath_hal_settpc(_ah, _v) \ + ath5k_hw_set_capability(_ah, AR5K_CAP_TPC, 1, _v, NULL) +#define ath_hal_hasbursting(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) +#define ath_hal_hasbssidmask(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) + +#endif diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c deleted file mode 100644 index 2a672c0..0000000 --- a/ath/if_ath_pci.c +++ /dev/null @@ -1,2133 +0,0 @@ -/*- - * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting - * Copyright (c) 2004-2005 Atheros Communications, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - */ -#define ATH_PCI_VERSION "0.9.5.0-BSD" - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "if_athvar.h" - -#define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ -#define ATH_DUMP_SKB 0 /* show skb contents */ -#define AR_DEBUG 1 - -#define DPRINTF(sc, _m, _fmt...) do { \ - if ((sc->debug & (_m)) && net_ratelimit()) \ - printk(_fmt); \ -} while (0) -enum { - ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ - ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ - ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ - ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ - ATH_DEBUG_RATE = 0x00000010, /* rate control */ - ATH_DEBUG_RESET = 0x00000020, /* reset processing */ - ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ - ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ - ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ - ATH_DEBUG_INTR = 0x00001000, /* ISR */ - ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ - ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ - ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ - ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ - ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ - ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ - ATH_DEBUG_NODE = 0x00080000, /* node management */ - ATH_DEBUG_LED = 0x00100000, /* led management */ - ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ - ATH_DEBUG_ANY = 0xffffffff -}; - -static int countrycode = CTRY_DEFAULT; -static int outdoor = true; -static int xchanmode = true; -module_param(countrycode, int, 0); -MODULE_PARM_DESC(countrycode, "Override default country code"); -module_param(outdoor, int, 0); -MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); -module_param(xchanmode, int, 0); -MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); - -#ifdef AR_DEBUG -static unsigned int ath_debug; -module_param_named(debug, ath_debug, uint, 0); -#endif - -/* - * User a static table of PCI id's for now. While this is the - * "new way" to do things, we may want to switch back to having - * the HAL check them by defining a probe method. - */ -static struct pci_device_id ath_pci_id_table[] __devinitdata = { - { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */ - { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */ - { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 */ - { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */ - { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */ - { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */ - { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */ - { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */ - { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ - { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ - { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ - { 0 } -}; -MODULE_DEVICE_TABLE(pci, ath_pci_id_table); - -#ifdef AR_DEBUG -static void ath_printrxbuf(struct ath_buf *bf, int done) -{ - struct ath_desc *ds = bf->desc; - - printk("R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", - ds, (unsigned long long)bf->daddr, - ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], - !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); -} - -static void ath_printtxbuf(struct ath_buf *bf, int done) -{ - struct ath_desc *ds = bf->desc; - - printk("T (%p %llx) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", - ds, (unsigned long long)bf->daddr, - ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], - !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); -} -#endif - -#if ATH_DUMP_SKB -static void ath_dump_skb(struct sk_buff *skb, unsigned int rx) -{ - unsigned int a; - - printk(KERN_DEBUG "%c", rx ? 'r' : 't'); - for (a = 0; a < min(200U, skb->len) + 4; a++) { - printk("%.2x %s", skb->data[a], ((a+1) % 8) ? "" : " "); - if (!((a+1) % 16)) - printk("\n" KERN_DEBUG " "); - } - printk("\n"); -} -#else -static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) {} -#endif - -static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) -{ - struct ieee80211_tx_status txs = {}; - struct ath_buf *bf, *bf0; - struct ath_desc *ds; - struct sk_buff *skb; - int ret; - - spin_lock(&txq->lock); - list_for_each_entry_safe(bf, bf0, &txq->q, list) { - ds = bf->desc; - - ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); - if (ret == -EINPROGRESS) - break; - else if (ret) { - printk(KERN_ERR "ath: error %d while processing " - "queue %u\n", ret, txq->qnum); - break; - } - - skb = bf->skb; - bf->skb = NULL; - pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, - PCI_DMA_TODEVICE); - - txs.control = bf->ctl; - txs.retry_count = ds->ds_txstat.ts_shortretry + - ds->ds_txstat.ts_longretry / 6; - if (ds->ds_txstat.ts_status) { - sc->ll_stats.dot11ACKFailureCount++; - if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { - txs.excessive_retries = 1; - } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { - txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; - } - } else { - txs.flags |= IEEE80211_TX_STATUS_ACK; - txs.ack_signal = ds->ds_txstat.ts_rssi; - } - - ieee80211_tx_status(sc->hw, skb, &txs); - sc->tx_stats.data[txq->qnum].count++; - -// printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); - - spin_lock(&sc->txbuflock); - sc->tx_stats.data[txq->qnum].len--; - list_move_tail(&bf->list, &sc->txbuf); - spin_unlock(&sc->txbuflock); - } - if (list_empty(&txq->q)) - txq->link = NULL; - spin_unlock(&txq->lock); -} - -static void ath_tasklet_tx(unsigned long data) -{ - struct ath_softc *sc = (void *)data; - - ath_tx_processq(sc, sc->txq); - - ieee80211_wake_queue(sc->hw, 0); -} - -static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) -{ - struct ath_hw *ah = sc->ah; - struct sk_buff *skb = bf->skb; - struct ath_desc *ds; - - if (skb == NULL) { - unsigned int off; - - /* - * Allocate buffer with headroom_needed space for the - * fake physical layer header at the start. - */ - skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); - if (skb == NULL) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " - "size %u failed\n", __func__, - sc->rxbufsize + sc->cachelsz - 1); - sc->stats.ast_rx_nobuf++; - return -ENOMEM; - } - /* - * Cache-line-align. This is important (for the - * 5210 at least) as not doing so causes bogus data - * in rx'd frames. - */ - off = ((unsigned long)skb->data) % sc->cachelsz; - if (off != 0) - skb_reserve(skb, sc->cachelsz - off); - - bf->skb = skb; - bf->skbaddr = pci_map_single(sc->pdev, - skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(bf->skbaddr)) { - printk(KERN_ERR "%s: DMA mapping failed\n", __func__); - dev_kfree_skb(skb); - bf->skb = NULL; - sc->stats.ast_rx_busdma++; - return -ENOMEM; - } - } - - /* - * Setup descriptors. For receive we always terminate - * the descriptor list with a self-linked entry so we'll - * not get overrun under high load (as can happen with a - * 5212 when ANI processing enables PHY error frames). - * - * To insure the last descriptor is self-linked we create - * each descriptor as self-linked and add it to the end. As - * each additional descriptor is added the previous self-linked - * entry is ``fixed'' naturally. This should be safe even - * if DMA is happening. When processing RX interrupts we - * never remove/process the last, self-linked, entry on the - * descriptor list. This insures the hardware always has - * someplace to write a new frame. - */ - ds = bf->desc; - ds->ds_link = bf->daddr; /* link to self */ - ds->ds_data = bf->skbaddr; - ath5k_hw_setup_rx_desc(ah, ds, - skb_tailroom(skb), /* buffer size */ - 0); - - if (sc->rxlink != NULL) - *sc->rxlink = bf->daddr; - sc->rxlink = &ds->ds_link; - return 0; -} - -static unsigned int ath_rx_decrypted(struct ath_softc *sc, - struct ath_desc *ds, struct sk_buff *skb) -{ - struct ieee80211_hdr *hdr = (void *)skb->data; - unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); - - if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && - ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID) - return RX_FLAG_DECRYPTED; - - /* Apparently when a default key is used to decrypt the packet - the hal does not set the index used to decrypt. In such cases - get the index from the packet. */ - if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && - !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && - skb->len >= hlen + 4) { - keyix = skb->data[hlen + 3] >> 6; - - if (test_bit(keyix, sc->keymap)) - return RX_FLAG_DECRYPTED; - } - - return 0; -} - -static void ath_tasklet_rx(unsigned long data) -{ - struct ieee80211_rx_status rxs = {}; - struct sk_buff *skb; - struct ath_softc *sc = (void *)data; - struct ath_buf *bf; - struct ath_desc *ds; - u16 len; - u8 stat; - int ret; - - spin_lock(&sc->rxbuflock); - do { - if (list_empty(&sc->rxbuf)) { - if (net_ratelimit()) - printk(KERN_WARNING "ath: empty rx buf pool\n"); - break; - } - bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); - BUG_ON(bf->skb == NULL); - skb = bf->skb; - ds = bf->desc; - if (ds->ds_link == bf->daddr) /* this is the end */ - break; - - ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); - if (ret == -EINPROGRESS) - break; - else if (ret) { - if (net_ratelimit()) - printk(KERN_ERR "ath: error in processing rx " - "descriptor\n"); - return; - } - - if (ds->ds_rxstat.rs_more) { - if (net_ratelimit()) - printk(KERN_INFO "ath: unsupported jumbo\n"); - goto next; - } - - stat = ds->ds_rxstat.rs_status; - if (stat) { - if (stat & AR5K_RXERR_CRC) - sc->stats.ast_rx_crcerr++; - if (stat & AR5K_RXERR_FIFO) - sc->stats.ast_rx_fifoerr++; - if (stat & AR5K_RXERR_PHY) { - sc->stats.ast_rx_phyerr++; - sc->stats.ast_rx_phy - [ds->ds_rxstat.rs_phyerr & 0x1f]++; - goto next; - } - if (stat & AR5K_RXERR_DECRYPT) { - /* - * Decrypt error. If the error occurred - * because there was no hardware key, then - * let the frame through so the upper layers - * can process it. This is necessary for 5210 - * parts which have no way to setup a ``clear'' - * key cache entry. - * - * XXX do key cache faulting - */ - if (ds->ds_rxstat.rs_keyix == - AR5K_RXKEYIX_INVALID) - goto accept; - sc->stats.ast_rx_badcrypt++; - } - if (stat & AR5K_RXERR_MIC) { - rxs.flag |= RX_FLAG_MMIC_ERROR; - sc->stats.ast_rx_badmic++; - goto accept; - } - - goto next; - } -accept: - len = ds->ds_rxstat.rs_datalen; - pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len, - PCI_DMA_FROMDEVICE); - pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, - PCI_DMA_FROMDEVICE); - bf->skb = NULL; - - if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) - printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); - - skb_put(skb, len); - - sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; - - rxs.mactime = ds->ds_rxstat.rs_tstamp; - rxs.freq = sc->curchan->freq; - rxs.channel = sc->curchan->chan; - rxs.phymode = sc->curmode; - rxs.ssi = ds->ds_rxstat.rs_rssi; - rxs.antenna = ds->ds_rxstat.rs_antenna; - rxs.rate = ds->ds_rxstat.rs_rate; - rxs.flag |= ath_rx_decrypted(sc, ds, skb); - -// printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); - ath_dump_skb(skb, 1); - - __ieee80211_rx(sc->hw, skb, &rxs); -next: - list_move_tail(&bf->list, &sc->rxbuf); - } while (ath_rxbuf_init(sc, bf) == 0); - spin_unlock(&sc->rxbuflock); -} - -/* - * Calculate the receive filter according to the - * operating mode and state: - * - * o always accept unicast, broadcast, and multicast traffic - * o maintain current state of phy error reception (the hal - * may enable phy error frames for noise immunity work) - * o probe request frames are accepted only when operating in - * hostap, adhoc, or monitor modes - * o enable promiscuous mode according to the interface state - * o accept beacons: - * - when operating in adhoc mode so the 802.11 layer creates - * node table entries for peers, - * - when operating in station mode for collecting rssi data when - * the station is otherwise quiet, or - * - when scanning - * o accept any additional packets specified by sc_rxfilter - */ -static u32 ath_calcrxfilter(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - u32 rfilt; - - rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERROR) | - AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | - AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_PHYRADAR; -#ifdef BLE - if (ic->ic_opmode != IEEE80211_M_STA && - ic->ic_opmode != IEEE80211_M_AHDEMO) - rfilt |= AR5K_RX_FILTER_PROBEREQ; - if (ic->ic_opmode != IEEE80211_M_HOSTAP && - (dev->flags & IFF_PROMISC)) - rfilt |= AR5K_RX_FILTER_PROM; - if (ic->ic_opmode == IEEE80211_M_STA || - ic->ic_opmode == IEEE80211_M_IBSS || - state == IEEE80211_S_SCAN) -#endif - rfilt |= AR5K_RX_FILTER_BEACON; - - return rfilt; -} - -static void ath_mode_init(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - u32 rfilt; - - /* configure rx filter */ - rfilt = ath_calcrxfilter(sc); - ath5k_hw_set_rx_filter(ah, rfilt); - - if (ath_hal_hasbssidmask(ah)) - ath5k_hw_set_bssid_mask(ah, sc->bssidmask); - - /* configure operational mode */ - ath5k_hw_set_opmode(ah); - - ath5k_hw_set_mcast_filter(ah, 0, 0); - DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); -} - -/* - * Enable the receive h/w following a reset. - */ -static int ath_startrecv(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - struct ath_buf *bf; - int ret; - - sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz); - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: cachelsz %u rxbufsize %u\n", - __func__, sc->cachelsz, sc->rxbufsize); - - sc->rxlink = NULL; - - spin_lock_bh(&sc->rxbuflock); - list_for_each_entry(bf, &sc->rxbuf, list) { - ret = ath_rxbuf_init(sc, bf); - if (ret != 0) { - spin_unlock_bh(&sc->rxbuflock); - goto err; - } - } - bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); - spin_unlock_bh(&sc->rxbuflock); - - ath5k_hw_put_rx_buf(ah, bf->daddr); - ath5k_hw_start_rx(ah); /* enable recv descriptors */ - ath_mode_init(sc); /* set filters, etc. */ - ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ - - return 0; -err: - return ret; -} - -static inline void ath_update_txpow(struct ath_softc *sc) -{ - ath5k_hw_set_txpower_limit(sc->ah, 0); -} - -static int ath_stop_locked(struct ath_softc *); - -static int ath_init(struct ath_softc *sc) -{ - int ret; - - mutex_lock(&sc->lock); - -// DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); - - /* - * Stop anything previously setup. This is safe - * no matter this is the first time through or not. - */ - ath_stop_locked(sc); - - /* - * The basic interface to setting the hardware in a good - * state is ``reset''. On return the hardware is known to - * be powered up and with interrupts disabled. This must - * be followed by initialization of the appropriate bits - * and then setup of the interrupt mask. - */ - sc->curchan = sc->hw->conf.chan; - ret = ath5k_hw_reset(sc->ah, IEEE80211_IF_TYPE_STA, sc->curchan, false); - if (ret) { - printk(KERN_ERR "unable to reset hardware: %d\n", ret); - goto done; - } - /* - * This is needed only to setup initial state - * but it's best done after a reset. - */ - ath_update_txpow(sc); - - /* - * Setup the hardware after reset: the key cache - * is filled as needed and the receive engine is - * set going. Frame transmit is handled entirely - * in the frame output path; there's nothing to do - * here except setup the interrupt mask. - */ - ret = ath_startrecv(sc); - if (ret) - goto done; - - /* - * Enable interrupts. - */ - sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN - | AR5K_INT_FATAL | AR5K_INT_GLOBAL; - - ath5k_hw_set_intr(sc->ah, sc->imask); - - ret = 0; -done: - mutex_unlock(&sc->lock); - return ret; -} - -/* - * Disable the receive h/w in preparation for a reset. - */ -static void ath_stoprecv(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - - ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ - ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ - ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ - mdelay(3); /* 3ms is long enough for 1 frame */ -#ifdef AR_DEBUG - if (sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow - struct ath_desc *ds; - struct ath_buf *bf; - int status; - - printk(KERN_DEBUG "%s: rx queue %x, link %p\n", __func__, - ath5k_hw_get_rx_buf(ah), sc->rxlink); - - spin_lock_bh(&sc->rxbuflock); - list_for_each_entry(bf, &sc->rxbuf, list) { - ds = bf->desc; - status = ah->ah_proc_rx_desc(ah, ds); - if (!status || (sc->debug & ATH_DEBUG_FATAL)) - ath_printrxbuf(bf, status == 0); - } - spin_unlock_bh(&sc->rxbuflock); - } -#endif - sc->rxlink = NULL; /* just in case */ -} - -static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) -{ -#ifdef AR_DEBUG - struct ath_hw *ah = sc->ah; -#endif - struct ath_buf *bf, *bf0; - - /* - * NB: this assumes output has been stopped and - * we do not need to block ath_tx_tasklet - */ - spin_lock_bh(&txq->lock); - list_for_each_entry_safe(bf, bf0, &txq->q, list) { -#ifdef AR_DEBUG - if (sc->debug & ATH_DEBUG_RESET) - ath_printtxbuf(bf, !ah->ah_proc_tx_desc(ah, bf->desc)); -#endif - pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, - PCI_DMA_TODEVICE); - dev_kfree_skb(bf->skb); - bf->skb = NULL; - - spin_lock_bh(&sc->txbuflock); - sc->tx_stats.data[txq->qnum].len--; - list_move_tail(&bf->list, &sc->txbuf); - spin_unlock_bh(&sc->txbuflock); - } - txq->link = NULL; - spin_unlock_bh(&txq->lock); -} - -/* - * Drain the transmit queues and reclaim resources. - */ -static void ath_draintxq(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - int i; - - /* XXX return value */ - if (!sc->invalid) { -#ifdef BLE - /* don't touch the hardware if marked invalid */ - (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, - ath5k_hw_get_tx_buf(ah, sc->bhalq)); -#endif - for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) - if (sc->txqs[i].setup) { - ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: txq [%u] %x, " - "link %p\n", __func__, - sc->txqs[i].qnum, - ath5k_hw_get_tx_buf(ah, - sc->txqs[i].qnum), - sc->txqs[i].link); - } - } - ieee80211_start_queues(sc->hw); /* XXX move to callers */ - - for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) - if (sc->txqs[i].setup) - ath_tx_draintxq(sc, &sc->txqs[i]); -} - -static int ath_stop_locked(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__, sc->invalid); - - /* - * Shutdown the hardware and driver: - * stop output from above - * disable interrupts - * turn off timers - * turn off the radio - * clear transmit machinery - * clear receive machinery - * drain and release tx queues - * reclaim beacon resources - * power down hardware - * - * Note that some of this work is not possible if the - * hardware is gone (invalid). - */ - ieee80211_stop_queues(sc->hw); - - if (!sc->invalid) { - if (sc->softled) { -#ifdef BLE - del_timer(&sc->ledtimer); - ath5k_hw_set_gpio(ah, sc->ledpin, !sc->ledon); - sc->blinking = 0; -#endif - } - ath5k_hw_set_intr(ah, 0); - } - ath_draintxq(sc); - if (!sc->invalid) { - ath_stoprecv(sc); - ath5k_hw_phy_disable(ah); - } else - sc->rxlink = NULL; -// ath_beacon_free(sc); - - return 0; -} - -/* - * Stop the device, grabbing the top-level lock to protect - * against concurrent entry through ath_init (which can happen - * if another thread does a system call and the thread doing the - * stop is preempted). - */ -static int ath_stop_hw(struct ath_softc *sc) -{ - int ret; - - mutex_lock(&sc->lock); - ret = ath_stop_locked(sc); - if (ret == 0 && !sc->invalid) { - /* - * Set the chip in full sleep mode. Note that we are - * careful to do this only when bringing the interface - * completely to a stop. When the chip is in this state - * it must be carefully woken up or references to - * registers in the PCI clock domain may freeze the bus - * (and system). This varies by chip and is mostly an - * issue with newer parts that go to sleep more quickly. - */ - if (sc->ah->ah_mac_version >= 7 && sc->ah->ah_mac_revision >= 8) { - /* - * XXX - * don't put newer MAC revisions > 7.8 to sleep because - * of the above mentioned problems - */ - DPRINTF(sc, ATH_DEBUG_RESET, "%s: mac version > 7.8, " - "not putting device to sleep\n", __func__); - } - else { - DPRINTF(sc, ATH_DEBUG_RESET, - "%s: putting device to full sleep\n", __func__); - ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); - } - } - mutex_unlock(&sc->lock); - return ret; -} - -static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) -{ -#ifdef BLE - /* from Atheros NDIS driver, w/ permission */ - static const struct { - u16 rate; /* tx/rx 802.11 rate */ - u16 timeOn; /* LED on time (ms) */ - u16 timeOff; /* LED off time (ms) */ - } blinkrates[] = { - { 108, 40, 10 }, - { 96, 44, 11 }, - { 72, 50, 13 }, - { 48, 57, 14 }, - { 36, 67, 16 }, - { 24, 80, 20 }, - { 22, 100, 25 }, - { 18, 133, 34 }, - { 12, 160, 40 }, - { 10, 200, 50 }, - { 6, 240, 58 }, - { 4, 267, 66 }, - { 2, 400, 100 }, - { 0, 500, 130 } - }; -#endif - const struct ath5k_rate_table* rt=ath5k_hw_get_rate_table(sc->ah, mode); -// unsigned int i, j; - - BUG_ON(rt == NULL); -#ifdef BLE - memset(sc->hwmap, 0, sizeof(sc->hwmap)); - for (i = 0; i < 32; i++) { - u8 ix = rt->rate_code_to_index[i]; - if (ix == 0xff) { - sc->hwmap[i].ledon = msecs_to_jiffies(500); - sc->hwmap[i].ledoff = msecs_to_jiffies(130); - continue; - } - sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; - if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == - MODULATION_OFDM) - sc->hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; - /* receive frames include FCS */ - sc->hwmap[i].rxflags = sc->hwmap[i].txflags | - IEEE80211_RADIOTAP_F_FCS; - /* setup blink rate table to avoid per-packet lookup */ - for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) - if (blinkrates[j].rate == /* XXX why 7f? */ - (rt->rates[ix].dot11_rate & 0x7f)) - break; - - sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].timeOn); - sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].timeOff); - } -#endif - sc->curmode = mode; -} - -/* - * Set/change channels. If the channel is really being changed, - * it's done by reseting the chip. To accomplish this we must - * first cleanup any pending DMA, then restart stuff after a la - * ath_init. - */ -static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) -{ - struct ath_hw *ah = sc->ah; - int ret; - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", - __func__, sc->curchan->chan, sc->curchan->freq, - chan->chan, chan->freq); - - if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) { - /* - * To switch channels clear any pending DMA operations; - * wait long enough for the RX fifo to drain, reset the - * hardware at the new frequency, and then re-enable - * the relevant bits of the h/w. - */ - ath5k_hw_set_intr(ah, 0); /* disable interrupts */ - ath_draintxq(sc); /* clear pending tx frames */ - ath_stoprecv(sc); /* turn off frame recv */ - ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, chan, true); - if (ret) { - printk(KERN_ERR "%s: unable to reset channel %u " - "(%u Mhz)\n", __func__, chan->chan, chan->freq); - return ret; - } - sc->curchan = chan; - ath_update_txpow(sc); - - /* - * Re-enable rx framework. - */ - ret = ath_startrecv(sc); - if (ret) { - printk(KERN_ERR "%s: unable to restart recv logic\n", - __func__); - return ret; - } - - /* - * Change channels and update the h/w rate map - * if we're switching; e.g. 11a to 11b/g. - */ -// ath_chan_change(sc, chan); - - /* - * Re-enable interrupts. - */ - ath5k_hw_set_intr(ah, sc->imask); - } - - return 0; -} - -static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, - struct ieee80211_tx_control *ctl) -{ - struct ath_hw *ah = sc->ah; - struct ath_txq *txq = sc->txq; - struct ath_desc *ds = bf->desc; - struct sk_buff *skb = bf->skb; - unsigned int hdrpad, pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; - int ret; - - flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; - bf->ctl = *ctl; - /* XXX endianness */ - bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, - PCI_DMA_TODEVICE); - - if (ctl->flags & IEEE80211_TXCTL_NO_ACK) - flags |= AR5K_TXDESC_NOACK; - - if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) - printk(KERN_DEBUG "tx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); - - hdrpad = 0; - pktlen = skb->len - hdrpad + FCS_LEN; - - if (ctl->key_idx != HW_KEY_IDX_INVALID) { - keyidx = ctl->key_idx; - pktlen += ctl->icv_len; - } - - ret = ah->ah_setup_tx_desc(ah, ds, pktlen, - ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, - 0xffff, ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0); - if (ret) - goto err_unmap; - - ds->ds_link = 0; - ds->ds_data = bf->skbaddr; - - ret = ah->ah_fill_tx_desc(ah, ds, skb->len, true, true); - if (ret) - goto err_unmap; - - spin_lock_bh(&txq->lock); - list_add_tail(&bf->list, &txq->q); - sc->tx_stats.data[txq->qnum].len++; - if (txq->link == NULL) /* is this first packet? */ - ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); - else /* no, so only link it */ - *txq->link = bf->daddr; - - txq->link = &ds->ds_link; - ath5k_hw_tx_start(ah, txq->qnum); - spin_unlock_bh(&txq->lock); - -// printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); - - return 0; -err_unmap: - pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); - return ret; -} - -static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, - struct ieee80211_tx_control *ctl) -{ - struct ath_softc *sc = hw->priv; - struct ath_buf *bf; - unsigned long flags; - - ath_dump_skb(skb, 0); - - spin_lock_irqsave(&sc->txbuflock, flags); - if (list_empty(&sc->txbuf)) { - if (net_ratelimit()) - printk(KERN_ERR "ath: no further txbuf available, " - "dropping packet\n"); - sc->stats.ast_tx_nobuf++; - spin_unlock_irqrestore(&sc->txbuflock, flags); - return -1; - } - bf = list_first_entry(&sc->txbuf, struct ath_buf, list); - list_del(&bf->list); - if (list_empty(&sc->txbuf)) { - sc->stats.ast_tx_qstop++; - ieee80211_stop_queues(hw); - } - spin_unlock_irqrestore(&sc->txbuflock, flags); - - bf->skb = skb; - - if (ath_tx_bf(sc, bf, ctl)) { - bf->skb = NULL; - spin_lock_irqsave(&sc->txbuflock, flags); - list_add_tail(&bf->list, &sc->txbuf); - spin_unlock_irqrestore(&sc->txbuflock, flags); - dev_kfree_skb_any(skb); - return 0; - } - - return 0; -} - -static int ath_reset(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hw *ah = sc->ah; - int ret; - - DPRINTF(sc, ATH_DEBUG_RESET, "resetting\n"); - /* - * Convert to a HAL channel description with the flags - * constrained to reflect the current operating mode. - */ - sc->curchan = hw->conf.chan; - - ath5k_hw_set_intr(ah, 0); - ath_draintxq(sc); - ath_stoprecv(sc); - - ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, sc->curchan, true); - if (ret) { - printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); - goto err; - } - ath_update_txpow(sc); - - ret = ath_startrecv(sc); - if (ret) { - printk(KERN_ERR "ath: can't start recv logic\n"); - goto err; - } - /* - * We may be doing a reset in response to an ioctl - * that changes the channel so update any state that - * might change as a result. - */ -// ath_chan_change(sc, c); - ath5k_hw_set_intr(ah, sc->imask); - - ieee80211_wake_queues(hw); - - return 0; -err: - return ret; -} - -static int ath_open(struct ieee80211_hw *hw) -{ - return ath_init(hw->priv); -} - -static int ath_stop(struct ieee80211_hw *hw) -{ - return ath_stop_hw(hw->priv); -} - -static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) -{ - struct ath_softc *sc = hw->priv; - - ath_setcurmode(sc, conf->phymode); - - return ath_chan_set(sc, conf->chan); -} - -static int ath_set_key(struct ieee80211_hw *hw, set_key_cmd cmd, - u8 *addr, struct ieee80211_key_conf *key, int aid) -{ - struct ath_softc *sc = hw->priv; - int ret = 0; - - mutex_lock(&sc->lock); - - switch (cmd) { - case SET_KEY: - if (key->alg != ALG_WEP && key->alg != ALG_NONE && - key->alg != ALG_NULL) { - ret = -EINVAL; - goto unlock; - } - - ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr); - if (ret) { - printk(KERN_ERR "ath: can't set the key\n"); - goto unlock; - } - - set_bit(key->keyidx, sc->keymap); - key->hw_key_idx = key->keyidx; - key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT; - break; - case DISABLE_KEY: - ath5k_hw_reset_key(sc->ah, key->keyidx); - clear_bit(key->keyidx, sc->keymap); - break; - case REMOVE_ALL_KEYS: { - unsigned int i; - for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) { - ath5k_hw_reset_key(sc->ah, i); - clear_bit(i, sc->keymap); - } - break; - } - default: - ret = -EINVAL; - goto unlock; - } - -unlock: - mutex_unlock(&sc->lock); - return ret; -} - -static int ath_get_stats(struct ieee80211_hw *hw, - struct ieee80211_low_level_stats *stats) -{ - struct ath_softc *sc = hw->priv; - - memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); - - return 0; -} - -static int ath_get_tx_stats(struct ieee80211_hw *hw, - struct ieee80211_tx_queue_stats *stats) -{ - struct ath_softc *sc = hw->priv; - - memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); - - return 0; -} - -static u64 ath_get_tsf(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - - return ath5k_hw_get_tsf64(sc->ah); -} - -static void ath_reset_tsf(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - - ath5k_hw_reset_tsf(sc->ah); -} - -static struct ieee80211_ops ath_hw_ops = { - .tx = ath_tx, - .reset = ath_reset, - .open = ath_open, - .stop = ath_stop, - .add_interface = NULL, - .remove_interface = NULL, - .config = ath_config, - .config_interface = NULL, - .set_key = ath_set_key, - .get_stats = ath_get_stats, - .conf_tx = NULL, - .get_tx_stats = ath_get_tx_stats, - .get_tsf = ath_get_tsf, - .reset_tsf = ath_reset_tsf, - .beacon_update = NULL, -}; - -static irqreturn_t ath_intr(int irq, void *dev_id) -{ - struct ath_softc *sc = dev_id; - struct ath_hw *ah = sc->ah; - enum ath5k_int status; - unsigned int counter = 1000; - - if (sc->invalid || !ath5k_hw_is_intr_pending(ah)) - return IRQ_NONE; - - do { - /* - * Figure out the reason(s) for the interrupt. Note - * that the hal returns a pseudo-ISR that may include - * bits we haven't explicitly enabled so we mask the - * value to insure we only process bits we requested. - */ - ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ - DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x/0x%x\n", __func__, - status, sc->imask); - status &= sc->imask; /* discard unasked for bits */ - if (status & AR5K_INT_FATAL) { - /* - * Fatal errors are unrecoverable. Typically - * these are caused by DMA errors. Unfortunately - * the exact reason is not (presently) returned - * by the hal. - */ - sc->stats.ast_hardware++; - ath_reset(sc->hw); - } else if (status & AR5K_INT_RXORN) { - sc->stats.ast_rxorn++; - ath_reset(sc->hw); - } else { - if (status & AR5K_INT_SWBA) { - /* - * Software beacon alert--time to send a beacon. - * Handle beacon transmission directly; deferring - * this is too slow to meet timing constraints - * under load. - */ -// ath_beacon_send(dev); - } - if (status & AR5K_INT_RXEOL) { - /* - * NB: the hardware should re-read the link when - * RXE bit is written, but it doesn't work at - * least on older hardware revs. - */ - sc->stats.ast_rxeol++; - sc->rxlink = NULL; - } - if (status & AR5K_INT_TXURN) { - sc->stats.ast_txurn++; - /* bump tx trigger level */ - ath5k_hw_update_tx_triglevel(ah, true); - } - if (status & AR5K_INT_RX) - tasklet_schedule(&sc->rxtq); - if (status & AR5K_INT_TX) - tasklet_schedule(&sc->txtq); -/* if (status & AR5K_INT_BMISS) { - sc->stats.ast_bmiss++; - tasklet_schedule(&sc->bmisstq); - }*/ - if (status & AR5K_INT_MIB) { - sc->stats.ast_mib++; - /* TODO */ - } - } - } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); - - if (!counter && net_ratelimit()) - printk(KERN_WARNING "ath: too many interrupts, giving up for " - "now\n"); - - return IRQ_HANDLED; -} - -/* - * Convert IEEE channel number to MHz frequency. - */ -static inline short ath_ieee2mhz(short chan) -{ - if (chan <= 14 || chan >= 27) - return ieee80211chan2mhz(chan); - else - return 2212 + chan * 20; -} - -static unsigned int ath_copy_rates(struct ieee80211_rate *rates, - const struct ath5k_rate_table *rt, unsigned int max) -{ - unsigned int i; - - if (rt == NULL) - return 0; - - for (i = 0; i < rt->rate_count && max > 0; i++, rates++, max--) { - rates->rate = rt->rates[i].rate_kbps / 100; - rates->val = rt->rates[i].rate_code; - rates->flags = rt->rates[i].modulation; - } - - return i; -} - -static unsigned int ath_copy_channels(struct ath_hw *ah, - struct ieee80211_channel *channels, unsigned int mode, - unsigned int max) -{ - static const struct { unsigned int mode, mask, chan; } map[] = { - [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A }, - [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T }, - [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B }, - [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G }, - [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG }, - }; - static const struct ieee80211_regchannel chans_2ghz[] = - IEEE80211_CHANNELS_2GHZ; - static const struct ieee80211_regchannel chans_5ghz[] = - IEEE80211_CHANNELS_5GHZ; - const struct ieee80211_regchannel *chans; - enum ieee80211_regdomain dmn; - unsigned int i, count, size, chfreq, all, f, ch; - - if (!test_bit(mode, ah->ah_modes)) - return 0; - - all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1; - - switch (mode) { - case MODE_IEEE80211A: - case MODE_ATHEROS_TURBO: - /* 1..220, but 2GHz frequencies are filtered by check_channel */ - size = all ? 220 : ARRAY_SIZE(chans_5ghz); - chans = chans_5ghz; - dmn = ieee80211_regdomain2flag(ah->ah_regdomain, - IEEE80211_CHANNELS_5GHZ_MIN); - chfreq = CHANNEL_5GHZ; - break; - case MODE_IEEE80211B: - case MODE_IEEE80211G: - case MODE_ATHEROS_TURBOG: - size = all ? 26 : ARRAY_SIZE(chans_2ghz); - chans = chans_2ghz; - dmn = ieee80211_regdomain2flag(ah->ah_regdomain, - IEEE80211_CHANNELS_2GHZ_MIN); - chfreq = CHANNEL_2GHZ; - break; - default: - printk(KERN_WARNING "bad mode, not copying channels\n"); - return 0; - } - - for (i = 0, count = 0; i < size && max > 0; i++) { - ch = all ? i + 1 : chans[i].chan; - f = ath_ieee2mhz(ch); - /* Check if channel is supported by the chipset */ - if (ath5k_check_channel(ah, f, chfreq) == false) - continue; - - /* Match regulation domain */ - if (!all && !(IEEE80211_DMN(chans[i].domain) & - IEEE80211_DMN(dmn))) - continue; - - if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode) - continue; - - /* Write channel and increment counter */ - channels->chan = ch; - channels->freq = f; - channels->val = map[mode].chan; - channels++; - count++; - max--; - } - - return count; -} - -#if ATH_DEBUG_MODES -static void ath_dump_modes(struct ieee80211_hw_mode *modes) -{ - unsigned int m, i; - - for (m = 0; m < NUM_IEEE80211_MODES; m++) { - printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m, - modes[m].num_channels, modes[m].num_rates); - printk(KERN_DEBUG " channels:\n"); - for (i = 0; i < modes[m].num_channels; i++) { - printk(KERN_DEBUG " %3d %d %.4x %.4x\n", - modes[m].channels[i].chan, - modes[m].channels[i].freq, - modes[m].channels[i].val, - modes[m].channels[i].flag); - } - printk(KERN_DEBUG " rates:\n"); - for (i = 0; i < modes[m].num_rates; i++) { - printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n", - modes[m].rates[i].rate, - modes[m].rates[i].val, - modes[m].rates[i].flags, - modes[m].rates[i].val2); - } - } -} -#else -static inline void ath_dump_modes(struct ieee80211_hw_mode *modes) {} -#endif - -static int ath_getchannels(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hw *ah = sc->ah; - struct ieee80211_hw_mode *modes = sc->modes; - unsigned int i, max; - int ret; - enum { - A = MODE_IEEE80211A, - B = MODE_IEEE80211B, - G = MODE_IEEE80211G, - T = MODE_ATHEROS_TURBO, - TG = MODE_ATHEROS_TURBOG, - }; - - BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 5); - - ah->ah_country_code = countrycode; - - modes[A].mode = MODE_IEEE80211A; - modes[B].mode = MODE_IEEE80211B; - modes[G].mode = MODE_IEEE80211G; - - max = ARRAY_SIZE(sc->rates); - modes[A].rates = sc->rates; - max -= modes[A].num_rates = ath_copy_rates(modes[A].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211A), max); - modes[B].rates = &modes[A].rates[modes[A].num_rates]; - max -= modes[B].num_rates = ath_copy_rates(modes[B].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211B), max); - modes[G].rates = &modes[B].rates[modes[B].num_rates]; - max -= modes[G].num_rates = ath_copy_rates(modes[G].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211G), max); - - if (!max) - printk(KERN_WARNING "yet another rates found, but there is not " - "sufficient space to store them\n"); - - max = ARRAY_SIZE(sc->channels); - modes[A].channels = sc->channels; - max -= modes[A].num_channels = ath_copy_channels(ah, modes[A].channels, - MODE_IEEE80211A, max); - modes[B].channels = &modes[A].channels[modes[A].num_channels]; - max -= modes[B].num_channels = ath_copy_channels(ah, modes[B].channels, - MODE_IEEE80211B, max); - modes[G].channels = &modes[B].channels[modes[B].num_channels]; - max -= modes[G].num_channels = ath_copy_channels(ah, modes[G].channels, - MODE_IEEE80211G, max); - - if (!max) - printk(KERN_WARNING "yet another modes found, but there is not " - "sufficient space to store them\n"); - - for (i = 0; i < ARRAY_SIZE(sc->modes); i++) - if (modes[i].num_channels) { - ret = ieee80211_register_hwmode(hw, &modes[i]); - if (ret) { - printk(KERN_ERR "can't register hwmode %u\n",i); - goto err; - } - } - ath_dump_modes(modes); - - return 0; -err: - return ret; -} - -static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) -{ - struct ath_desc *ds; - struct ath_buf *bf; - dma_addr_t da; - unsigned int i; - int ret; - - /* allocate descriptors */ - sc->desc_len = sizeof(struct ath_desc) * - (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); - sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); - if (sc->desc == NULL) { - dev_err(&pdev->dev, "can't allocate descriptors\n"); - ret = -ENOMEM; - goto err; - } - ds = sc->desc; - da = sc->desc_daddr; - DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", - __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); - - bf = kcalloc(ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1, - sizeof(struct ath_buf), GFP_KERNEL); - if (bf == NULL) { - dev_err(&pdev->dev, "can't allocate bufptr\n"); - ret = -ENOMEM; - goto err_free; - } - sc->bufptr = bf; - - INIT_LIST_HEAD(&sc->rxbuf); - for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { - bf->desc = ds; - bf->daddr = da; - list_add_tail(&bf->list, &sc->rxbuf); - } - - INIT_LIST_HEAD(&sc->txbuf); - for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC, - da += ATH_TXDESC * sizeof(*ds)) { - bf->desc = ds; - bf->daddr = da; - list_add_tail(&bf->list, &sc->txbuf); - } -#ifdef BLE - INIT_LIST_HEAD(&sc->bbuf); - for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { - bf->desc = ds; - bf->daddr = da; - list_add_tail(&bf->list, &sc->bbuf); - } -#endif - - return 0; -err_free: - pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); -err: - sc->desc = NULL; - return ret; -} - -static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, - struct list_head *head) -{ - struct ath_buf *bf; - - list_for_each_entry(bf, head, list) { - if (bf->skb) { - pci_unmap_single(pdev, bf->skbaddr, sc->rxbufsize, - PCI_DMA_FROMDEVICE); - dev_kfree_skb(bf->skb); - bf->skb = NULL; - } - } -} - -static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) -{ -// ath_descdma_cleanup(sc, pdev, &sc->bbuf); - ath_descdma_cleanup(sc, pdev, &sc->txbuf); - ath_descdma_cleanup(sc, pdev, &sc->rxbuf); - - /* Free memory associated with all descriptors */ - pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); - - kfree(sc->bufptr); - sc->bufptr = NULL; -} -#ifdef BLE -static int ath_beaconq_setup(struct ath_hw *ah) -{ - struct ath5k_txq_info qi; - - memset(&qi, 0, sizeof(qi)); - qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; - /* NB: for dynamic turbo, don't enable any other interrupts */ - qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - - return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); -} -#endif -static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, - int subtype) -{ - struct ath_hw *ah = sc->ah; - struct ath_txq *txq; - struct ath5k_txq_info qi; - int qnum; - - memset(&qi, 0, sizeof(qi)); - qi.tqi_subtype = subtype; - qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; - /* - * Enable interrupts only for EOL and DESC conditions. - * We mark tx descriptors to receive a DESC interrupt - * when a tx queue gets deep; otherwise waiting for the - * EOL to reap descriptors. Note that this is done to - * reduce interrupt load and this only defers reaping - * descriptors, never transmitting frames. Aside from - * reducing interrupts this also permits more concurrency. - * The only potential downside is if the tx queue backs - * up in which case the top half of the kernel may backup - * due to a lack of tx descriptors. - */ - qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | - AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); - if (qnum < 0) { - /* - * NB: don't print a message, this happens - * normally on parts with too few tx queues - */ - return ERR_PTR(qnum); - } - if (qnum >= ARRAY_SIZE(sc->txqs)) { - printk(KERN_ERR "hal qnum %u out of range, max %u!\n", - qnum, ARRAY_SIZE(sc->txqs)); - ath5k_hw_release_tx_queue(ah, qnum); - return ERR_PTR(-EINVAL); - } - txq = &sc->txqs[qnum]; - if (!txq->setup) { - txq->qnum = qnum; - txq->link = NULL; - INIT_LIST_HEAD(&txq->q); - spin_lock_init(&txq->lock); - txq->setup = true; - } - return &sc->txqs[qnum]; -} - -static void ath_tx_cleanup(struct ath_softc *sc) -{ - struct ath_txq *txq = sc->txqs; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) - if (txq->setup) { - ath5k_hw_release_tx_queue(sc->ah, txq->qnum); - txq->setup = false; - } -} - -static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hw *ah = sc->ah; - u8 mac[ETH_ALEN]; - unsigned int i; - int ret; - - DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); - - /* - * Check if the MAC has multi-rate retry support. - * We do this by trying to setup a fake extended - * descriptor. MAC's that don't have support will - * return false w/o doing anything. MAC's that do - * support it will return true w/o doing anything. - */ - sc->mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); - - /* - * Reset the key cache since some parts do not - * reset the contents on initial power up. - */ - for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) - ath5k_hw_reset_key(ah, i); - - /* - * Collect the channel list using the default country - * code and including outdoor channels. The 802.11 layer - * is resposible for filtering this list based on settings - * like the phy mode. - */ - ret = ath_getchannels(hw); - if (ret) { - dev_err(&pdev->dev, "can't get channels\n"); - goto err; - } - - /* NB: setup here so ath_rate_update is happy */ - if (test_bit(MODE_IEEE80211A, ah->ah_modes)) - ath_setcurmode(sc, MODE_IEEE80211A); - else - ath_setcurmode(sc, MODE_IEEE80211B); - - /* - * Allocate tx+rx descriptors and populate the lists. - */ - ret = ath_desc_alloc(sc, pdev); - if (ret) { - dev_err(&pdev->dev, "can't allocate descriptors\n"); - goto err; - } - -#ifdef BLE - /* - * Allocate hardware transmit queues: one queue for - * beacon frames and one data queue for each QoS - * priority. Note that the hal handles reseting - * these queues at the needed time. - * - * XXX PS-Poll - */ - ret = ath_beaconq_setup(ah); - if (ret < 0) { - dev_err(&pdev->dev, "can't setup a beacon xmit queue\n"); - goto err_desc; - } - sc->bhalq = ret; - - sc->cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); - if (IS_ERR(sc->cabq)) { - dev_err(&pdev->dev, "can't setup CAB xmit queue\n"); - ret = PTR_ERR(sc->cabq); - sc->cabq = NULL; - goto err_queues; - } -#endif - sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); - if (IS_ERR(sc->txq)) { - dev_err(&pdev->dev, "can't setup xmit queue\n"); - ret = PTR_ERR(sc->txq); - goto err_queues; - } - - tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); - tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); -#ifdef BLE - /* - * Setup rate control. Some rate control modules - * call back to change the anntena state so expose - * the necessary entry points. - * XXX maybe belongs in struct ath_ratectrl? - */ - sc->sc_setdefantenna = ath_setdefantenna; - sc->sc_rc = ath_rate_attach(sc); - if (sc->sc_rc == NULL) { - error = EIO; - goto bad2; - } - - setup_timer(&sc->scan_ch, ath_next_scan, (unsigned long)hw); - setup_timer(&sc->cal_ch, ath_calibrate, (unsigned long)hw); - - sc->blinking = 0; - sc->ledstate = 1; - sc->ledon = 0; /* low true */ - sc->ledidle = msecs_to_jiffies(2700); /* 2.7sec */ - - setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); - /* - * Auto-enable soft led processing for IBM cards and for - * 5211 minipci cards. Users can also manually enable/disable - * support with a sysctl. - */ - sc->sc_softled = (devid == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || - devid == PCI_DEVICE_ID_ATHEROS_AR5211); - if (sc->sc_softled) { - ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); - ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); - } - - sc->sc_hasclrkey = ath_hal_ciphersupported(ah, AR5K_CIPHER_CLR); - sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); - - /* - * Query the hal about antenna support. - */ - sc->sc_defant = ath5k_hw_get_def_antenna(ah); - - /* - * Not all chips have the VEOL support we want to - * use with IBSS beacons; check here for it. - */ - sc->sc_hasveol = ath_hal_hasveol(ah); - - sc->sc_rxfilter = 0; -#endif - - ath5k_hw_get_lladdr(ah, mac); - SET_IEEE80211_PERM_ADDR(hw, mac); - if (ath_hal_hasbssidmask(ah)) { - memset(sc->bssidmask, 0xff, ETH_ALEN); - ath5k_hw_set_bssid_mask(ah, sc->bssidmask); - } - - ret = ieee80211_register_hw(hw); - if (ret) { - dev_err(&pdev->dev, "can't register ieee80211 hw\n"); - goto err_queues; - } - -// ath_dynamic_sysctl_register(sc); -// ath_announce(sc); - - return 0; -err_queues: - ath_tx_cleanup(sc); -//err_desc: - ath_desc_free(sc, pdev); -err: - return ret; -} - -static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - - ath_stop_hw(sc); /* XXX needed? */ - /* - * NB: the order of these is important: - * o call the 802.11 layer before detaching the hal to - * insure callbacks into the driver to delete global - * key cache entries can be handled - * o reclaim the tx queue data structures after calling - * the 802.11 layer as we'll get called back to reclaim - * node state and potentially want to use them - * o to cleanup the tx queues the hal is called, so detach - * it last - * Other than that, it's straightforward... - */ - ieee80211_unregister_hw(hw); - ath_desc_free(sc, pdev); - ath_tx_cleanup(sc); - - /* - * NB: can't reclaim these until after ieee80211_ifdetach - * returns because we'll get called back to reclaim node - * state and potentially want to use them. - */ -// ath_dynamic_sysctl_unregister(sc); -} - -static const char *ath_chip_name(u8 mac_version) -{ - switch (mac_version) { - case AR5K_AR5210: - return "AR5210"; - case AR5K_AR5211: - return "AR5211"; - case AR5K_AR5212: - return "AR5212"; - } - return "Unknown"; -} - -static int __devinit ath_pci_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - void __iomem *mem; - struct ath_softc *sc; - struct ieee80211_hw *hw; - int ret; - u8 csz; - - ret = pci_enable_device(pdev); - if (ret) { - dev_err(&pdev->dev, "can't enable device\n"); - goto err; - } - - /* XXX 32-bit addressing only */ - ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); - if (ret) { - dev_err(&pdev->dev, "32-bit DMA not available\n"); - goto err_dis; - } - - /* - * Cache line size is used to size and align various - * structures used to communicate with the hardware. - */ - pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); - if (csz == 0) { - /* - * Linux 2.4.18 (at least) writes the cache line size - * register as a 16-bit wide register which is wrong. - * We must have this setup properly for rx buffer - * DMA to work so force a reasonable value here if it - * comes up zero. - */ - csz = L1_CACHE_BYTES / sizeof(u32); - pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); - } - /* - * The default setting of latency timer yields poor results, - * set it to the value used by other systems. It may be worth - * tweaking this setting more. - */ - pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); - - pci_set_master(pdev); - - /* - * Disable the RETRY_TIMEOUT register (0x41) to keep - * PCI Tx retries from interfering with C3 CPU state. - */ - pci_write_config_byte(pdev, 0x41, 0); - - ret = pci_request_region(pdev, 0, "ath"); - if (ret) { - dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); - goto err_dis; - } - - mem = pci_iomap(pdev, 0, 0); - if (!mem) { - dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; - ret = -EIO; - goto err_reg; - } - - hw = ieee80211_alloc_hw(sizeof(*sc), &ath_hw_ops); - if (hw == NULL) { - dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); - ret = -ENOMEM; - goto err_map; - } - - SET_IEEE80211_DEV(hw, &pdev->dev); - hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_WEP_INCLUDE_IV | - IEEE80211_HW_DATA_NULLFUNC_ACK; - hw->extra_tx_headroom = 2; - hw->channel_change_time = 5000; - hw->max_rssi = 127; /* FIXME: get a real value for this. */ - sc = hw->priv; - sc->hw = hw; - - /* - * Mark the device as detached to avoid processing - * interrupts until setup is complete. - */ - sc->debug = ath_debug; - sc->invalid = 1; - sc->iobase = mem; - sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ - mutex_init(&sc->lock); - spin_lock_init(&sc->rxbuflock); - spin_lock_init(&sc->txbuflock); - - pci_set_drvdata(pdev, hw); - - ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc); - if (ret) { - dev_err(&pdev->dev, "request_irq failed\n"); - goto err_free; - } - - sc->ah = ath5k_hw_attach(pdev->device, id->driver_data, sc, sc->iobase); - if (IS_ERR(sc->ah)) { - ret = PTR_ERR(sc->ah); - goto err_irq; - } - - ret = ath_attach(pdev, hw); - if (ret) - goto err_ah; - - dev_info(&pdev->dev, "%s chip found: mac %d.%d phy %d.%d\n", - ath_chip_name(id->driver_data), sc->ah->ah_mac_version, - sc->ah->ah_mac_version, sc->ah->ah_phy_revision >> 4, - sc->ah->ah_phy_revision & 0xf); - - /* ready to process interrupts */ - sc->invalid = 0; - - return 0; -err_ah: - ath5k_hw_detach(sc->ah); -err_irq: - free_irq(pdev->irq, sc); -err_free: - ieee80211_free_hw(hw); -err_map: - pci_iounmap(pdev, mem); -err_reg: - pci_release_region(pdev, 0); -err_dis: - pci_disable_device(pdev); -err: - return ret; -} - -static void __devexit ath_pci_remove(struct pci_dev *pdev) -{ - struct ieee80211_hw *hw = pci_get_drvdata(pdev); - struct ath_softc *sc = hw->priv; - - ath_detach(pdev, hw); - ath5k_hw_detach(sc->ah); - free_irq(pdev->irq, sc); - pci_iounmap(pdev, sc->iobase); - pci_release_region(pdev, 0); - pci_disable_device(pdev); - ieee80211_free_hw(hw); -} - -#ifdef CONFIG_PM -static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) -{ - struct ieee80211_hw *hw = pci_get_drvdata(pdev); - struct ath_softc *sc = hw->priv; - - if (sc->softled) - ath5k_hw_set_gpio(sc->ah, sc->ledpin, 1); - - ath_stop_hw(sc); - pci_save_state(pdev); - pci_disable_device(pdev); - pci_set_power_state(pdev, PCI_D3hot); - - return 0; -} - -static int ath_pci_resume(struct pci_dev *pdev) -{ - struct ieee80211_hw *hw = pci_get_drvdata(pdev); - struct ath_softc *sc = hw->priv; - int err; - - err = pci_set_power_state(pdev, PCI_D0); - if (err) - return err; - - err = pci_enable_device(pdev); - if (err) - return err; - - pci_restore_state(pdev); - /* - * Suspend/Resume resets the PCI configuration space, so we have to - * re-disable the RETRY_TIMEOUT register (0x41) to keep - * PCI Tx retries from interfering with C3 CPU state - */ - pci_write_config_byte(pdev, 0x41, 0); - - ath_init(sc); - if (sc->softled) { - ath5k_hw_set_gpio_output(sc->ah, sc->ledpin); - ath5k_hw_set_gpio(sc->ah, sc->ledpin, 0); - } - - return 0; -} -#else -#define ath_pci_suspend NULL -#define ath_pci_resume NULL -#endif /* CONFIG_PM */ - -static struct pci_driver ath_pci_drv_id = { - .name = "ath_pci", - .id_table = ath_pci_id_table, - .probe = ath_pci_probe, - .remove = __devexit_p(ath_pci_remove), - .suspend = ath_pci_suspend, - .resume = ath_pci_resume, -}; - -/* - * Static (i.e. global) sysctls. Note that the hal sysctls - * are located under ours by sharing the setting for DEV_ATH. - */ -enum { - DEV_ATH = 9, /* XXX known by hal */ -}; - -#define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ - -static ctl_table ath_static_sysctls[] = { -#ifdef AR_DEBUG - { .ctl_name = CTL_AUTO, - .procname = "debug", - .mode = 0644, - .data = &ath_debug, - .maxlen = sizeof(ath_debug), - .proc_handler = proc_dointvec - }, -#endif - { .ctl_name = CTL_AUTO, - .procname = "countrycode", - .mode = 0444, - .data = &countrycode, - .maxlen = sizeof(countrycode), - .proc_handler = proc_dointvec - }, -/* { .ctl_name = CTL_AUTO, - .procname = "regdomain", - .mode = 0444, - .data = &ath_regdomain, - .maxlen = sizeof(ath_regdomain), - .proc_handler = proc_dointvec - },*/ - { .ctl_name = CTL_AUTO, - .procname = "outdoor", - .mode = 0444, - .data = &outdoor, - .maxlen = sizeof(outdoor), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "xchanmode", - .mode = 0444, - .data = &xchanmode, - .maxlen = sizeof(xchanmode), - .proc_handler = proc_dointvec - }, -/* { .ctl_name = CTL_AUTO, - .procname = "dwelltime", - .mode = 0644, - .data = &ath_dwelltime, - .maxlen = sizeof(ath_dwelltime), - .extra1 = &mindwelltime, - .extra2 = &maxint, - .proc_handler = proc_dointvec_minmax - }, - { .ctl_name = CTL_AUTO, - .procname = "calibrate", - .mode = 0644, - .data = &ath_calinterval, - .maxlen = sizeof(ath_calinterval), - .extra1 = &mincalibrate, - .extra2 = &maxint, - .proc_handler = proc_dointvec_minmax - },*/ - { 0 } -}; -static ctl_table ath_ath_table[] = { - { .ctl_name = DEV_ATH, - .procname = "ath", - .mode = 0555, - .child = ath_static_sysctls - }, { 0 } -}; -static ctl_table ath_root_table[] = { - { .ctl_name = CTL_DEV, - .procname = "dev", - .mode = 0555, - .child = ath_ath_table - }, { 0 } -}; -static struct ctl_table_header *ath_sysctl_header; - -/* - * Module glue. - */ -static int __init init_ath_pci(void) -{ - int ret; - - ret = pci_register_driver(&ath_pci_drv_id); - if (ret) { - printk(KERN_ERR "ath_pci: can't register pci driver\n"); - return ret; - } - ath_sysctl_header = register_sysctl_table(ath_root_table); - - return 0; -} - -static void __exit exit_ath_pci(void) -{ - if (ath_sysctl_header) - unregister_sysctl_table(ath_sysctl_header); - pci_unregister_driver(&ath_pci_drv_id); -} - -module_init(init_ath_pci); -module_exit(exit_ath_pci); - -MODULE_AUTHOR("Jiri Slaby"); -MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); -MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); -MODULE_LICENSE("Dual BSD/GPL"); -MODULE_VERSION(ATH_PCI_VERSION " (EXPERIMENTAL)"); diff --git a/ath/if_athioctl.h b/ath/if_athioctl.h deleted file mode 100644 index 6359248..0000000 --- a/ath/if_athioctl.h +++ /dev/null @@ -1,172 +0,0 @@ -/*- - * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD: src/sys/dev/ath/if_athioctl.h,v 1.9 2004/12/31 22:41:45 sam Exp $ - */ - -/* - * Ioctl-related defintions for the Atheros Wireless LAN controller driver. - */ -#ifndef _DEV_ATH_ATHIOCTL_H -#define _DEV_ATH_ATHIOCTL_H - -#include - -struct ath_stats { - __u32 ast_watchdog; /* device reset by watchdog */ - __u32 ast_hardware; /* fatal hardware error interrupts */ - __u32 ast_bmiss; /* beacon miss interrupts */ - __u32 ast_bstuck; /* beacon stuck interrupts */ - __u32 ast_rxorn; /* rx overrun interrupts */ - __u32 ast_rxeol; /* rx eol interrupts */ - __u32 ast_txurn; /* tx underrun interrupts */ - __u32 ast_mib; /* mib interrupts */ - __u32 ast_intrcoal; /* interrupts coalesced */ - __u32 ast_tx_packets; /* packet sent on the interface */ - __u32 ast_tx_mgmt; /* management frames transmitted */ - __u32 ast_tx_discard; /* frames discarded prior to assoc */ - __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ - __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ - __u32 ast_tx_encap; /* tx encapsulation failed */ - __u32 ast_tx_nonode; /* tx failed 'cuz no node */ - __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ - __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ - __u32 ast_tx_linear; /* tx linearized to cluster */ - __u32 ast_tx_nodata; /* tx discarded empty frame */ - __u32 ast_tx_busdma; /* tx failed for dma resrcs */ - __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ - __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ - __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ - __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ - __u32 ast_tx_longretry;/* tx on-chip retries (long) */ - __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ - __u32 ast_tx_noack; /* tx frames with no ack marked */ - __u32 ast_tx_rts; /* tx frames with rts enabled */ - __u32 ast_tx_cts; /* tx frames with cts enabled */ - __u32 ast_tx_shortpre;/* tx frames with short preamble */ - __u32 ast_tx_altrate; /* tx frames with alternate rate */ - __u32 ast_tx_protect; /* tx frames with protection */ - __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ - __u32 ast_tx_ctsext; /* tx frames with cts extension */ - __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ - __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ - __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ - __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ - __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ - __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ - __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ - __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ - __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ - __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ - __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ - __u32 ast_rx_packets; /* packet recv on the interface */ - __u32 ast_rx_mgt; /* management frames received */ - __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ - __s8 ast_tx_rssi; /* tx rssi of last ack */ - __s8 ast_rx_rssi; /* rx rssi from histogram */ - __u32 ast_be_xmit; /* beacons transmitted */ - __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ - __u32 ast_per_cal; /* periodic calibration calls */ - __u32 ast_per_calfail;/* periodic calibration failed */ - __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ - __u32 ast_rate_calls; /* rate control checks */ - __u32 ast_rate_raise; /* rate control raised xmit rate */ - __u32 ast_rate_drop; /* rate control dropped xmit rate */ - __u32 ast_ant_defswitch;/* rx/default antenna switches */ - __u32 ast_ant_txswitch;/* tx antenna switches */ - __u32 ast_ant_rx[8]; /* rx frames with antenna */ - __u32 ast_ant_tx[8]; /* tx frames with antenna */ -}; - -struct ath_diag { - char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ - __u16 ad_id; -#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ -#define ATH_DIAG_IN 0x4000 /* copy in parameters */ -#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ -#define ATH_DIAG_ID 0x0fff - __u16 ad_in_size; /* pack to fit, yech */ - void __user *ad_in_data; - void __user *ad_out_data; - u_int ad_out_size; -}; - -/* - * Radio capture format. - */ -#define ATH_RX_RADIOTAP_PRESENT ( \ - (1 << IEEE80211_RADIOTAP_FLAGS) | \ - (1 << IEEE80211_RADIOTAP_RATE) | \ - (1 << IEEE80211_RADIOTAP_CHANNEL) | \ - (1 << IEEE80211_RADIOTAP_ANTENNA) | \ - (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ - 0) - -struct ath_rx_radiotap_header { - struct ieee80211_radiotap_header wr_ihdr; - __u8 wr_flags; /* XXX for padding */ - __u8 wr_rate; - __le16 wr_chan_freq; - __le16 wr_chan_flags; - __u8 wr_antenna; - __u8 wr_antsignal; -}; - -#define ATH_TX_RADIOTAP_PRESENT ( \ - (1 << IEEE80211_RADIOTAP_FLAGS) | \ - (1 << IEEE80211_RADIOTAP_RATE) | \ - (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ - (1 << IEEE80211_RADIOTAP_ANTENNA) | \ - (1 << IEEE80211_RADIOTAP_TX_FLAGS) | \ - (1 << IEEE80211_RADIOTAP_RTS_RETRIES) | \ - (1 << IEEE80211_RADIOTAP_DATA_RETRIES) | \ - 0) - -struct ath_tx_radiotap_header { - struct ieee80211_radiotap_header wt_ihdr; - __u8 wt_flags; /* XXX for padding */ - __u8 wt_rate; - __u8 wt_txpower; - __u8 wt_antenna; - __le16 wt_tx_flags; - __u8 wt_rts_retries; - __u8 wt_data_retries; - -}; - -#define SIOCGATHSTATS (SIOCDEVPRIVATE+0) -#define SIOCGATHDIAG (SIOCDEVPRIVATE+1) - -#endif diff --git a/ath/if_athvar.h b/ath/if_athvar.h deleted file mode 100644 index a753e1f..0000000 --- a/ath/if_athvar.h +++ /dev/null @@ -1,278 +0,0 @@ -/*- - * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.20 2005/01/24 20:31:24 sam Exp $ - */ - -/* - * Defintions for the Atheros Wireless LAN controller driver. - */ -#ifndef _DEV_ATH_ATHVAR_H -#define _DEV_ATH_ATHVAR_H - -#include -#include -#include -#include - -#include "ath5k.h" -#include "if_athioctl.h" - -#define ATH_TIMEOUT 1000 - -/* - * Maximum acceptable MTU - * MAXFRAMEBODY - WEP - QOS - RSN/WPA: - * 2312 - 8 - 2 - 12 = 2290 - */ -#define ATH_MAX_MTU 2290 -#define ATH_MIN_MTU 32 - -#define ATH_RXBUF 40 /* number of RX buffers */ -#define ATH_TXBUF 200 /* number of TX buffers */ -#define ATH_TXDESC 1 /* number of descriptors per buffer */ -#define ATH_BCBUF 1 /* number of beacon buffers */ -#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ -#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ - -#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ -#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ -#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ - -#define ATH_RSSI_LPF_LEN 10 -#define ATH_RSSI_DUMMY_MARKER 0x127 -#define ATH_EP_MUL(x, mul) ((x) * (mul)) -#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), AR5K_RSSI_EP_MULTIPLIER)) -#define ATH_LPF_RSSI(x, y, len) \ - ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) -#define ATH_RSSI_LPF(x, y) do { \ - if ((y) >= -20) \ - x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ -} while (0) - -struct ath_buf { - struct list_head list; - unsigned int flags; /* tx descriptor flags */ - struct ath_desc *desc; /* virtual addr of desc */ - dma_addr_t daddr; /* physical addr of desc */ - struct sk_buff *skb; /* skbuff for buf */ - dma_addr_t skbaddr;/* physical addr of skb data */ - struct ieee80211_tx_control ctl; -}; - -/* - * Data transmit queue state. One of these exists for each - * hardware transmit queue. Packets sent to us from above - * are assigned to queues based on their priority. Not all - * devices support a complete set of hardware transmit queues. - * For those devices the array sc_ac2q will map multiple - * priorities to fewer hardware queues (typically all to one - * hardware queue). - */ -struct ath_txq { - unsigned int qnum; /* hardware q number */ - u32 *link; /* link ptr in last TX desc */ - struct list_head q; /* transmit queue */ - spinlock_t lock; /* lock on q and link */ - bool setup; -}; - -#if CHAN_DEBUG -#define ATH_CHAN_MAX (26+26+26+200+200) -#else -#define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */ -#endif - -struct ath_softc { - struct pci_dev *pdev; /* for dma mapping */ - void __iomem *iobase; /* address of the device */ - struct mutex lock; /* dev-level lock */ - struct ath_stats stats; /* private statistics */ - struct ieee80211_tx_queue_stats tx_stats; - struct ieee80211_low_level_stats ll_stats; - struct ieee80211_hw *hw; /* IEEE 802.11 common */ - struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; - struct ieee80211_channel channels[ATH_CHAN_MAX]; - struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_IEEE80211_MODES]; - struct ath_hw *ah; /* Atheros HW */ -#ifdef BLE - enum ieee80211_if_types sc_opmode; - int sc_regdomain; - int sc_countrycode; -#endif - int debug; - - struct ath_buf *bufptr; /* allocated buffer ptr */ - struct ath_desc *desc; /* TX/RX descriptors */ - dma_addr_t desc_daddr; /* DMA (physical) address */ - size_t desc_len; /* size of TX/RX descriptors */ - u16 cachelsz; /* cache line size */ -#ifdef BLE - struct ath_ratectrl *sc_rc; /* tx rate control support */ - void (*sc_setdefantenna)(struct ath_softc *, u_int); -#endif - unsigned int invalid : 1, /* disable hardware accesses */ - mrretry : 1, /* multi-rate retry support */ - softled : 1, /* enable LED gpio status */ - xxx:1; -#ifdef BLE - sc_splitmic: 1, /* split TKIP MIC keys */ - sc_needmib : 1, /* enable MIB stats intr */ - sc_diversity : 1,/* enable rx diversity */ - sc_lockslottime : 1,/* lock slot time value */ - sc_hasveol : 1, /* tx VEOL support */ - sc_ledstate: 1, /* LED on/off state */ - sc_blinking: 1, /* LED blink operation active */ - sc_endblink: 1, /* finish LED blink operation */ - sc_mcastkey: 1, /* mcast key cache search */ - sc_hasclrkey:1; /* CLR key supported */ - /* rate tables */ - const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; - const struct ath5k_rate_table *sc_currates; /* current rate table */ -#endif - unsigned int curmode; /* current phy mode */ - struct ieee80211_channel *curchan; /* current h/w channel */ -#ifdef BLE - u16 sc_curtxpow; /* current tx power limit */ - u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ - - struct { -// int ieeerate; /* IEEE rate */ - u8 rxflags; /* radiotap rx flags */ - u8 txflags; /* radiotap tx flags */ - u16 ledon; /* softled on time */ - u16 ledoff; /* softled off time */ - } hwmap[32]; /* h/w rate ix mappings */ - - u8 sc_protrix; /* protection rate index */ - u_int sc_txantenna; /* tx antenna (fixed or auto) */ -#endif - enum ath5k_int imask; /* interrupt mask copy */ - - DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ - - u8 bssidmask[ETH_ALEN]; - unsigned int ledpin; /* GPIO pin for driving LED */ -#ifdef BLE - u_int sc_ledon; /* pin setting for LED on */ - u_int sc_ledidle; /* idle polling interval */ - int sc_ledevent; /* time of last LED event */ - u8 sc_rxrate; /* current rx rate for LED */ - u8 sc_txrate; /* current tx rate for LED */ - u16 sc_ledoff; /* off time for current blink */ - struct timer_list sc_ledtimer; /* led off timer */ - - union { - struct ath_tx_radiotap_header th; - u8 pad[64]; - } u_tx_rt; - int sc_tx_th_len; - union { - struct ath_rx_radiotap_header th; - u8 pad[64]; - } u_rx_rt; - int sc_rx_th_len; - struct tasklet_struct sc_radartq; /* Radar detection */ -#endif - unsigned int rxbufsize; /* rx size based on mtu */ - struct list_head rxbuf; /* receive buffer */ - spinlock_t rxbuflock; - u32 *rxlink; /* link ptr in last RX desc */ - struct tasklet_struct rxtq; /* rx intr tasklet */ -#ifdef BLE - u8 sc_defant; /* current default antenna */ - u8 sc_rxotherant; /* rx's on non-default antenna*/ -#endif - struct list_head txbuf; /* transmit buffer */ - spinlock_t txbuflock; - struct ath_txq txqs[2]; /* beacon and tx */ -#ifdef BLE - int sc_tx_timer; /* transmit timeout */ - u_int sc_txintrperiod;/* tx interrupt batching */ - struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ -#endif - struct ath_txq *txq; /* beacon and tx*/ - struct tasklet_struct txtq; /* tx intr tasklet */ - -#ifdef BLE - struct list_head bbuf; /* beacon buffers */ - unsigned int bhalq; /* HAL q for outgoing beacons */ - u_int sc_bmisscount; /* missed beacon transmits */ - u32 sc_ant_tx[8]; /* recent tx frames/antenna */ - struct ieee80211_beacon_offsets boff; /* dynamic update state */ - struct ath_txq *cabq; /* tx q for cab frames */ - - struct tasklet_struct bmisstq; /* bmiss intr tasklet */ - - struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ - enum { - OK, /* no change needed */ - UPDATE, /* update pending */ - COMMIT /* beacon sent, commit change */ - } sc_updateslot; /* slot time update fsm */ - - struct timer_list sc_cal_ch; /* calibration timer */ - struct timer_list sc_scan_ch; /* AP scan timer */ - struct iw_statistics sc_iwstats; /* wireless statistics block */ - struct ctl_table_header *sc_sysctl_header; - struct ctl_table *sc_sysctls; -#endif -}; - -void ath_sysctl_register(void); -void ath_sysctl_unregister(void); - -#define ath_hal_getcountrycode(_ah, _pcc) \ - (*(_pcc) = (_ah)->ah_country_code) -#define ath_hal_tkipsplit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == 0) -#define ath_hal_hwphycounters(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == 0) -#define ath_hal_getnumtxqueues(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == 0) -#define ath_hal_hasveol(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) -#define ath_hal_hastpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == 0) -#define ath_hal_gettpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == 0) -#define ath_hal_settpc(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_TPC, 1, _v, NULL) -#define ath_hal_hasbursting(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) -#define ath_hal_hasbssidmask(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) - -#endif diff --git a/ath/radar.h b/ath/radar.h deleted file mode 100644 index 6d28190..0000000 --- a/ath/radar.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __RADAR_H__ -#define __RADAR_H__ - -extern struct ieee80211_channel *radar_handle_interference(struct ieee80211com *ic); -extern void radar_init(struct ieee80211com *ic); - -#endif - diff --git a/ath5k.h b/ath5k.h new file mode 100644 index 0000000..012bb46 --- /dev/null +++ b/ath5k.h @@ -0,0 +1,1096 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _AR5K_H +#define _AR5K_H + +/* Set this to 1 to disable regulatory domain restrictions for channel tests. + * WARNING: This is for debuging only and has side effects (eg. scan takes too + * long and results timeouts). It's also illegal to tune to some of the + * supported frequencies in some countries, so use this at your own risk, + * you've been warned. */ +#define CHAN_DEBUG 0 + +/* Uncomment this for debuging (warning that it results in TOO much output) */ +/*#define AR5K_DEBUG 1 */ + +#include +#include + +#include "ath5k_hw.h" +#include "ieee80211_regdomain.h" + +/* PCI IDs */ +#ifndef PCI_VENDOR_ID_ATHEROS +#define PCI_VENDOR_ID_ATHEROS 0x168c +#endif +#ifndef PCI_VENDOR_ID_3COM_2 +#define PCI_VENDOR_ID_3COM_2 0xa727 +#endif + +#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ +#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ +#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ +#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ +#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ +#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ +#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ +#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ + +/****************************\ + GENERIC DRIVER DEFINITIONS +\****************************/ + +#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) +#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) +#ifdef AR5K_DEBUG +#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) +#else +#define AR5K_TRACE +#endif +#define howmany(x, y) (((x)+((y)-1))/(y)) + +/* + * Some tuneable values (these should be changeable by the user) + */ +#define AR5K_TUNE_DMA_BEACON_RESP 2 +#define AR5K_TUNE_SW_BEACON_RESP 10 +#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 +#define AR5K_TUNE_RADAR_ALERT false +#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 +#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) +#define AR5K_TUNE_RSSI_THRES 1792 +#define AR5K_TUNE_REGISTER_TIMEOUT 20000 +#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 +#define AR5K_TUNE_BEACON_INTERVAL 100 +#define AR5K_TUNE_AIFS 2 +#define AR5K_TUNE_AIFS_11B 2 +#define AR5K_TUNE_AIFS_XR 0 +#define AR5K_TUNE_CWMIN 15 +#define AR5K_TUNE_CWMIN_11B 31 +#define AR5K_TUNE_CWMIN_XR 3 +#define AR5K_TUNE_CWMAX 1023 +#define AR5K_TUNE_CWMAX_11B 1023 +#define AR5K_TUNE_CWMAX_XR 7 +#define AR5K_TUNE_NOISE_FLOOR -72 +#define AR5K_TUNE_MAX_TXPOWER 60 +#define AR5K_TUNE_DEFAULT_TXPOWER 30 +#define AR5K_TUNE_TPC_TXPOWER true +#define AR5K_TUNE_ANT_DIVERSITY true +#define AR5K_TUNE_HWTXTRIES 4 + +/* token to use for aifs, cwmin, cwmax in MadWiFi */ +#define AR5K_TXQ_USEDEFAULT ((u32) -1) + +/* GENERIC CHIPSET DEFINITIONS */ + +/* MAC Chips */ +enum ath5k_version { + AR5K_AR5210 = 0, + AR5K_AR5211 = 1, + AR5K_AR5212 = 2, +}; + +/* PHY Chips */ +enum ath5k_radio { + AR5K_RF5110 = 0, + AR5K_RF5111 = 1, + AR5K_RF5112 = 2, +}; + +/* + * Common silicon revision/version values + */ +enum ath5k_srev_type { + AR5K_VERSION_VER, + AR5K_VERSION_REV, + AR5K_VERSION_RAD, + AR5K_VERSION_DEV +}; + +struct ath5k_srev_name { + const char *sr_name; + enum ath5k_srev_type sr_type; + u_int sr_val; +}; + +#define AR5K_SREV_NAME { \ + { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ + { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ + { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ + { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ + { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ + { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ + { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ + { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ + { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ + { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ + { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ + { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ + { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ + { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ + { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ + { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ + { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ + { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ + { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ + { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ +} + +#define AR5K_SREV_UNKNOWN 0xffff + +#define AR5K_SREV_VER_AR5210 0x00 +#define AR5K_SREV_VER_AR5311 0x10 +#define AR5K_SREV_VER_AR5311A 0x20 +#define AR5K_SREV_VER_AR5311B 0x30 +#define AR5K_SREV_VER_AR5211 0x40 +#define AR5K_SREV_VER_AR5212 0x50 +#define AR5K_SREV_VER_AR5213 0x55 +#define AR5K_SREV_VER_UNSUPP 0x60 + +#define AR5K_SREV_RAD_5110 0x00 +#define AR5K_SREV_RAD_5111 0x10 +#define AR5K_SREV_RAD_5111A 0x15 +#define AR5K_SREV_RAD_2111 0x20 +#define AR5K_SREV_RAD_5112 0x30 +#define AR5K_SREV_RAD_5112A 0x35 +#define AR5K_SREV_RAD_2112 0x40 +#define AR5K_SREV_RAD_2112A 0x45 +#define AR5K_SREV_RAD_UNSUPP 0x50 + + +/* IEEE defs */ + +#define IEEE80211_MAX_LEN 2500 + +#define MAX_PDU_LENGTH IEEE80211_MAX_LEN +#define MODULATION_CCK IEEE80211_RATE_CCK +#define MODULATION_OFDM IEEE80211_RATE_OFDM +#define MODULATION_TURBO IEEE80211_RATE_TURBO +#define MODULATION_XR 0x00000200 /*XR thingie*/ +#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ + +#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code + enables short preamble, see ar5212_reg.h */ +#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) +#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 + +/****************\ + TX DEFINITIONS +\****************/ + +/* + * Tx Descriptor + */ +struct ath_tx_status { + u16 ts_seqnum; + u16 ts_tstamp; + u8 ts_status; + u8 ts_rate; + s8 ts_rssi; + u8 ts_shortretry; + u8 ts_longretry; + u8 ts_virtcol; + u8 ts_antenna; +}; + +#define AR5K_TXSTAT_ALTRATE 0x80 +#define AR5K_TXERR_XRETRY 0x01 +#define AR5K_TXERR_FILT 0x02 +#define AR5K_TXERR_FIFO 0x04 + +/* + * Queue types used to classify tx queues. + */ +enum ath5k_tx_queue { + AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ + AR5K_TX_QUEUE_DATA, /*A normal data queue*/ + AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ + AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ + AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ + AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ +}; + +#define AR5K_NUM_TX_QUEUES 10 +#define AR5K_NUM_TX_QUEUES_NOQCU 2 + +/* + * Queue syb-types to classify normal data queues. + * These are the 4 Access Categories as defined in + * WME spec. 0 is the lowest priority and 4 is the + * highest. Normal data that hasn't been classified + * goes to the Best Effort AC. + */ +enum ath5k_tx_queue_subtype { + AR5K_WME_AC_BK = 0, /*Background traffic*/ + AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ + AR5K_WME_AC_VI, /*Video traffic*/ + AR5K_WME_AC_VO, /*Voice traffic*/ +}; + +/* + * Queue ID numbers as returned by the HAL, each number + * represents a hw queue. If hw does not support hw queues + * (eg 5210) all data goes in one queue. These match + * d80211 definitions (net80211/MadWiFi don't use them). + */ +enum ath5k_tx_queue_id { + AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, + AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, + AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ + AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ + AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ + AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ + AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ + AR5K_TX_QUEUE_ID_UAPSD = 8, + AR5K_TX_QUEUE_ID_XR_DATA = 9, +}; + + +/* + * Flags to set hw queue's parameters... + */ +#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ +#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ +#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ +#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ +#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ +#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ +#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ +#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ + +/* + * A struct to hold tx queue's parameters + */ +struct ath5k_txq_info { + enum ath5k_tx_queue tqi_type; + enum ath5k_tx_queue_subtype tqi_subtype; + u16 tqi_flags; /* Tx queue flags (see above) */ + u32 tqi_aifs; /* Arbitrated Interframe Space */ + s32 tqi_cw_min; /* Minimum Contention Window */ + s32 tqi_cw_max; /* Maximum Contention Window */ + u32 tqi_cbr_period; /* Constant bit rate period */ + u32 tqi_cbr_overflow_limit; + u32 tqi_burst_time; + u32 tqi_ready_time; /* Not used */ + u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ +}; + +/* + * Transmit packet types. + * These are not fully used inside OpenHAL yet + */ +enum ath5k_pkt_type { + AR5K_PKT_TYPE_NORMAL = 0, + AR5K_PKT_TYPE_ATIM = 1, + AR5K_PKT_TYPE_PSPOLL = 2, + AR5K_PKT_TYPE_BEACON = 3, + AR5K_PKT_TYPE_PROBE_RESP = 4, + AR5K_PKT_TYPE_PIFS = 5, +}; + +/* + * TX power and TPC settings + */ +#define AR5K_TXPOWER_OFDM(_r, _v) ( \ + ((0 & 1) << ((_v) + 6)) | \ + (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ +) + +#define AR5K_TXPOWER_CCK(_r, _v) ( \ + (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ +) + +/* + * Used to compute TX times + */ +#define AR5K_CCK_SIFS_TIME 10 +#define AR5K_CCK_PREAMBLE_BITS 144 +#define AR5K_CCK_PLCP_BITS 48 + +#define AR5K_OFDM_SIFS_TIME 16 +#define AR5K_OFDM_PREAMBLE_TIME 20 +#define AR5K_OFDM_PLCP_BITS 22 +#define AR5K_OFDM_SYMBOL_TIME 4 + +#define AR5K_TURBO_SIFS_TIME 8 +#define AR5K_TURBO_PREAMBLE_TIME 14 +#define AR5K_TURBO_PLCP_BITS 22 +#define AR5K_TURBO_SYMBOL_TIME 4 + +#define AR5K_XR_SIFS_TIME 16 +#define AR5K_XR_PLCP_BITS 22 +#define AR5K_XR_SYMBOL_TIME 4 + +/* CCK */ +#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) + +#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ + ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ + (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) + +#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ + AR5K_CCK_PHY_TIME(_sp) + \ + ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ + AR5K_CCK_SIFS_TIME + +/* OFDM */ +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_OFDM_SYMBOL_TIME) / 1000) + +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ + AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ + (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) + +/* TURBO */ +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ + AR5K_TURBO_SYMBOL_TIME) / 1000) + +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ + AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ + AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ + (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) + +/* eXtendent Range (?)*/ +#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) + +#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_XR_SYMBOL_TIME) / 1000) + +#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ + AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ + (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) + +/* + * DMA size definitions (2^n+2) + */ +enum ath5k_dmasize { + AR5K_DMASIZE_4B = 0, + AR5K_DMASIZE_8B, + AR5K_DMASIZE_16B, + AR5K_DMASIZE_32B, + AR5K_DMASIZE_64B, + AR5K_DMASIZE_128B, + AR5K_DMASIZE_256B, + AR5K_DMASIZE_512B +}; + + +/****************\ + RX DEFINITIONS +\****************/ + +/* + * Rx Descriptor + */ +struct ath_rx_status { + u16 rs_datalen; + u16 rs_tstamp; + u8 rs_status; + u8 rs_phyerr; + s8 rs_rssi; + u8 rs_keyix; + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; +}; + +#define AR5K_RXERR_CRC 0x01 +#define AR5K_RXERR_PHY 0x02 +#define AR5K_RXERR_FIFO 0x04 +#define AR5K_RXERR_DECRYPT 0x08 +#define AR5K_RXERR_MIC 0x10 +#define AR5K_RXKEYIX_INVALID ((u8) - 1) +#define AR5K_TXKEYIX_INVALID ((u32) - 1) + +/* + * RX filters + * Most of them are not yet used inside OpenHAL + */ +#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ +#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ +#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ +#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ +#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ +#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ +#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame */ +#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests */ +#define AR5K_RX_FILTER_PHYERROR 0x00000100 /* Don't filter phy errors */ +#define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ + +struct ath5k_mib_stats { + u32 ackrcv_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 beacons; +}; + + + + +/**************************\ + BEACON TIMERS DEFINITIONS +\**************************/ + +#define AR5K_BEACON_PERIOD 0x0000ffff +#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ +#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ + +/* + * Per-station beacon timer state. + */ +struct ath5k_beacon_state { + u32 bs_next_beacon; + u32 bs_next_dtim; + u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- + can also include the above flags*/ + u8 bs_dtim_period; + u8 bs_cfp_period; + u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with + a Point Coordination Function capable AP*/ + u16 bs_cfp_du_remain; + u16 bs_tim_offset; + u16 bs_sleep_duration; + u16 bs_bmiss_threshold; + u32 bs_cfp_next; +}; + + + + +/********************\ + COMMON DEFINITIONS +\********************/ + +/* + * Atheros descriptor + */ +struct ath_desc { + u32 ds_link; + u32 ds_data; + u32 ds_ctl0; + u32 ds_ctl1; + u32 ds_hw[4]; + + union { + struct ath_rx_status rx; + struct ath_tx_status tx; + } ds_us; + +#define ds_rxstat ds_us.rx +#define ds_txstat ds_us.tx + +} __packed; + +#define AR5K_RXDESC_INTREQ 0x0020 + +#define AR5K_TXDESC_CLRDMASK 0x0001 +#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ +#define AR5K_TXDESC_RTSENA 0x0004 +#define AR5K_TXDESC_CTSENA 0x0008 +#define AR5K_TXDESC_INTREQ 0x0010 +#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ + +#define AR5K_SLOT_TIME_9 396 +#define AR5K_SLOT_TIME_20 880 +#define AR5K_SLOT_TIME_MAX 0xffff + +/* channel_flags */ +#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ +#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ +#define CHANNEL_XR 0x0800 /* XR channel */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_108G CHANNEL_TG +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) + +#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ + CHANNEL_5GHZ | CHANNEL_TURBO) + +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) +#define CHANNEL_MODES CHANNEL_ALL + +/* + * Used internaly in OpenHAL (ar5211.c/ar5212.c + * for reset_tx_queue). Also see struct struct ieee80211_channel. + */ +#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) +#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) + +/* + * The following structure will be used to map 2GHz channels to + * 5GHz Atheros channels. + */ +struct ath5k_athchan_2ghz { + u32 a2_flags; + u16 a2_athchan; +}; + +/* + * Rate definitions + */ + +#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ + +struct ath5k_rate { + u8 valid; /* Valid for rate control */ + u32 modulation; + u16 rate_kbps; + u8 rate_code; /* Rate mapping for h/w descriptors */ + u8 dot11_rate; + u8 control_rate; + u16 lp_ack_duration;/* long preamble ACK duration */ + u16 sp_ack_duration;/* short preamble ACK duration*/ +}; + +struct ath5k_rate_table { + u16 rate_count; + u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ + struct ath5k_rate rates[AR5K_MAX_RATES]; +}; + +/* + * Rate tables... + */ +#define AR5K_RATES_11A { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_11B { 4, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ +} + +#define AR5K_RATES_11G { 12, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ + { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ + { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +#define AR5K_RATES_TURBO { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ + { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ + { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ + { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ + { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ + { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ + { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ + { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_XR { 12, { \ + 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_XR, 500, 7, 129, 0 }, \ + { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ + { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ + { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ + { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +/* + * Crypto definitions + */ + +#define AR5K_KEYCACHE_SIZE 8 + +/***********************\ + HW RELATED DEFINITIONS +\***********************/ + +/* + * Misc definitions + */ +#define AR5K_RSSI_EP_MULTIPLIER (1<<7) + +#define AR5K_ASSERT_ENTRY(_e, _s) do { \ + if (_e >= _s) \ + return (false); \ +} while (0) + + +struct ath5k_node_stats { + u32 ns_avgbrssi; /* average beacon rssi */ + u32 ns_avgrssi; /* average data rssi */ + u32 ns_avgtxrssi; /* average tx rssi */ +}; + +enum ath5k_ant_setting { + AR5K_ANT_VARIABLE = 0, /* variable by programming */ + AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ + AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ + AR5K_ANT_MAX = 3, +}; + +/* + * HAL interrupt abstraction + */ + +/* + * These are mapped to take advantage of some common bits + * between the MAC chips, to be able to set intr properties + * easier. Some of them are not used yet inside OpenHAL. + */ +enum ath5k_int { + AR5K_INT_RX = 0x00000001, + AR5K_INT_RXDESC = 0x00000002, + AR5K_INT_RXNOFRM = 0x00000008, + AR5K_INT_RXEOL = 0x00000010, + AR5K_INT_RXORN = 0x00000020, + AR5K_INT_TX = 0x00000040, + AR5K_INT_TXDESC = 0x00000080, + AR5K_INT_TXURN = 0x00000800, + AR5K_INT_MIB = 0x00001000, + AR5K_INT_RXPHY = 0x00004000, + AR5K_INT_RXKCM = 0x00008000, + AR5K_INT_SWBA = 0x00010000, + AR5K_INT_BMISS = 0x00040000, + AR5K_INT_BNR = 0x00100000, + AR5K_INT_GPIO = 0x01000000, + AR5K_INT_FATAL = 0x40000000, + AR5K_INT_GLOBAL = 0x80000000, + + /*A sum of all the common bits*/ + AR5K_INT_COMMON = AR5K_INT_RXNOFRM + | AR5K_INT_RXDESC + | AR5K_INT_RXEOL + | AR5K_INT_RXORN + | AR5K_INT_TXURN + | AR5K_INT_TXDESC + | AR5K_INT_MIB + | AR5K_INT_RXPHY + | AR5K_INT_RXKCM + | AR5K_INT_SWBA + | AR5K_INT_BMISS + | AR5K_INT_GPIO, + AR5K_INT_NOCARD = 0xffffffff /*Declare that the card + has been removed*/ +}; + +/* + * Power management + */ +enum ath5k_power_mode { + AR5K_PM_UNDEFINED = 0, + AR5K_PM_AUTO, + AR5K_PM_AWAKE, + AR5K_PM_FULL_SLEEP, + AR5K_PM_NETWORK_SLEEP, +}; + +/* + * These match net80211 definitions (not used in + * d80211). + */ +#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ +#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ +#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ +#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ +#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ + +/* GPIO-controlled software LED */ +#define AR5K_SOFTLED_PIN 0 +#define AR5K_SOFTLED_ON 0 +#define AR5K_SOFTLED_OFF 1 + +/* + * Chipset capabilities -see ath_hal_getcapability- + * get_capability function is not yet fully implemented + * in OpenHAL so most of these don't work yet... + */ +enum ath5k_capability_type { + AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ + AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ + AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ + AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ + AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ + AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ + AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ + AR5K_CAP_COMPRESSION = 8, /* Supports compression */ + AR5K_CAP_BURST = 9, /* Supports packet bursting */ + AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ + AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ + AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ + AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ + AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ + AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ + AR5K_CAP_XR = 16, /* Supports XR mode */ + AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ + AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ + AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ + AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ +}; + +struct ath5k_capabilities { + /* + * Supported PHY modes + * (ie. CHANNEL_A, CHANNEL_B, ...) + */ + DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); + + /* + * Frequency range (without regulation restrictions) + */ + struct { + u16 range_2ghz_min; + u16 range_2ghz_max; + u16 range_5ghz_min; + u16 range_5ghz_max; + } cap_range; + + /* + * Active regulation domain settings + */ + struct { + enum ieee80211_regdomain reg_current; + enum ieee80211_regdomain reg_hw; + } cap_regdomain; + + /* + * Values stored in the EEPROM (some of them...) + */ + struct ath5k_eeprom_info cap_eeprom; + + /* + * Queue information + */ + struct { + u8 q_tx_num; + } cap_queues; +}; + + +/***************************************\ + HARDWARE ABSTRACTION LAYER STRUCTURE +\***************************************/ + +/* + * Misc defines + */ + +#define AR5K_MAX_GPIO 10 +#define AR5K_MAX_RF_BANKS 8 + +struct ath_hw { + u32 ah_magic; + + void *ah_sc; + void __iomem *ah_sh; + enum ieee80211_countrycode ah_country_code; + + enum ath5k_int ah_imr; + + enum ieee80211_if_types ah_op_mode; + enum ath5k_power_mode ah_power_mode; + struct ieee80211_channel ah_current_channel; + bool ah_turbo; + bool ah_calibration; + bool ah_running; + bool ah_single_chip; + enum ath5k_rfgain ah_rf_gain; + + u32 ah_mac_srev; + u16 ah_mac_version; + u16 ah_mac_revision; + u16 ah_phy_revision; + u16 ah_radio_5ghz_revision; + u16 ah_radio_2ghz_revision; + + enum ath5k_version ah_version; + enum ath5k_radio ah_radio; + u32 ah_phy; + + bool ah_5ghz; + bool ah_2ghz; + +#define ah_regdomain ah_capabilities.cap_regdomain.reg_current +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_modes ah_capabilities.cap_mode +#define ah_ee_version ah_capabilities.cap_eeprom.ee_version + + u32 ah_atim_window; + u32 ah_aifs; + u32 ah_cw_min; + u32 ah_cw_max; + bool ah_software_retry; + u32 ah_limit_tx_retries; + + u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + bool ah_ant_diversity; + + u8 ah_sta_id[ETH_ALEN]; + u8 ah_bssid[ETH_ALEN]; + + u32 ah_gpio[AR5K_MAX_GPIO]; + int ah_gpio_npins; + + struct ath5k_capabilities ah_capabilities; + + struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; + u32 ah_txq_interrupts; + + u32 *ah_rf_banks; + size_t ah_rf_banks_size; + struct ath5k_gain ah_gain; + u32 ah_offset[AR5K_MAX_RF_BANKS]; + + struct { + u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; + u16 txp_rates[AR5K_MAX_RATES]; + s16 txp_min, txp_max; + bool txp_tpc; + s16 txp_ofdm; + } ah_txpower; + + struct { + bool r_enabled; + int r_last_alert; + struct ieee80211_channel r_last_channel; + } ah_radar; + + /* + * Function pointers + */ + int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int); + bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); + int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); + int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); + int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *); +}; + +/* + * Prototypes + */ +typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ieee80211_channel *, + unsigned int); + +/* General Functions */ +u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); +/* Attach/Detach Functions */ +struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); +void ath5k_hw_detach(struct ath_hw *hal); +/* Reset Functions */ +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); +/* Power management functions */ +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); +/* DMA Related Functions */ +void ath5k_hw_start_rx(struct ath_hw *hal); +int ath5k_hw_stop_rx_dma(struct ath_hw *hal); +u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); +void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); +int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); +int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); +bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); +/* Interrupt handling */ +bool ath5k_hw_is_intr_pending(struct ath_hw *hal); +int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); +enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); +void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); +/* EEPROM access functions */ +u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); +int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); +int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); +/* Protocol Control Unit Functions */ +void ath5k_hw_set_opmode(struct ath_hw *hal); +/* BSSID Functions */ +void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); +bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); +void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); +bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); +/* Receive start/stop functions */ +void ath5k_hw_start_rx_pcu(struct ath_hw *hal); +void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); +/* RX Filter functions */ +void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); +bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); +u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); +void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); +/* Beacon related functions */ +u32 ath5k_hw_get_tsf32(struct ath_hw *hal); +u64 ath5k_hw_get_tsf64(struct ath_hw *hal); +void ath5k_hw_reset_tsf(struct ath_hw *hal); +void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); +void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); +void ath5k_hw_reset_beacon(struct ath_hw *hal); +bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); +void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); +/* ACK/CTS Timeouts */ +bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); +bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); +/* Key table (WEP) functions */ +int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); +int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); +int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); +int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); +/* Queue Control Unit, DFS Control Unit Functions */ +int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); +int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); +bool ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); +void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); +unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); +/* Hardware Descriptor Functions */ +/* RX Descriptor */ +int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); +/* GPIO Functions */ +void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); +bool ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); +bool ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); +u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); +bool ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); +void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); +/* Regulatory Domain/Channels Setup */ +unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); +unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); +bool ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags); +bool ath_hal_init_channels(struct ath_hw *hal, struct ieee80211_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); +u16 ath5k_get_regdomain(struct ath_hw *hal); +/* PHY/RF access functions */ +bool ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel); +u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel); +bool ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan); +bool ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_phy_disable(struct ath_hw *hal); +void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); +unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); +unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 first, u32 col, bool set); +u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal); +bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal); +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal); +bool ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); +bool ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); +bool ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); +void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, unsigned int ee_mode); +bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); +/* Misc functions */ +int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); +void ath5k_hw_dump_state(struct ath_hw *hal); +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); +int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting); +bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); +bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); +bool ath5k_hw_disable_pspoll(struct ath_hw *hal); +#endif /* _AR5K_H */ diff --git a/ath5k_hw.c b/ath5k_hw.c new file mode 100644 index 0000000..a96053f --- /dev/null +++ b/ath5k_hw.c @@ -0,0 +1,5825 @@ + /* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + +/* + * HAL interface for Atheros Wireless LAN devices. + * (Please have a look at ar5xxx.h for further information) + */ + +#include + +#include +#include + +#include "ath5k.h" +#include "ath5k_reg.h" + +/*Rate tables*/ +static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; +static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; +static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G; +static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; +static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; + +/*Prototypes*/ +static int ath5k_hw_nic_reset(struct ath_hw *, u32); +static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool); +static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int); +static int ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int); +static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); +static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int); +static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); +static int ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *); +static int ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); +static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); +static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); +static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *); +static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *); +static int ath5k_hw_get_capabilities(struct ath_hw *); + +static int ath5k_eeprom_init(struct ath_hw *); +static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *); + +/* + * Initial register dumps + */ +static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI; +static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE; +static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI; +static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE; +static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF; +static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI; + +/* + * Initial gain optimization values + */ +static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT; +static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT; + +/* + * Initial register for the radio chipsets + */ +static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF; +static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF; +static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF; +static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; + +/* + * Enable to overwrite the country code (use "00" for debug) + */ +#if 0 +#define COUNTRYCODE "00" +#endif + +/*******************\ + General Functions +\*******************/ + + +/* + * Calculate transmition time of a frame + * TODO: Left here for combatibility, change it in ath5k + */ +u16 /*TODO: Is this really hardware dependent ?*/ +ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, + u32 frame_length, u16 rate_index, bool short_preamble) +{ + const struct ath5k_rate *rate; + u32 value; + + AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); + + /* + * Get rate by index + */ + rate = &rates->rates[rate_index]; + + /* + * Calculate the transmission time by operation (PHY) mode + */ + switch (rate->modulation) { + case MODULATION_CCK: + /* + * CCK / DS mode (802.11b) + */ + value = AR5K_CCK_TX_TIME(rate->rate_kbps, frame_length, + (short_preamble && (rate->modulation == MODULATION_CCK_SP))); + break; + + case MODULATION_OFDM: + /* + * Orthogonal Frequency Division Multiplexing + */ + if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) + return 0; + value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length); + break; + + case MODULATION_TURBO: + /* + * Orthogonal Frequency Division Multiplexing + * Atheros "Turbo Mode" (doubled rates) + */ + if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) + return 0; + value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length); + break; + + case MODULATION_XR: + /* + * Orthogonal Frequency Division Multiplexing + * Atheros "eXtended Range" (XR) + */ + if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) + return 0; + value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length); + break; + + default: + return 0; + } + + return value; +} + +/* + * Functions used internaly + */ + +static u32 +ath5k_hw_bitswap(u32 val, unsigned int bits) +{ + u32 retval = 0, bit, i; + + for (i = 0; i < bits; i++) { + bit = (val >> i) & 1; + retval = (retval << 1) | bit; + } + + return retval; +} + +static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) +{ + return turbo == true ? (usec * 80) : (usec * 40); +} + +static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) +{ + return turbo == true ? (clock / 80) : (clock / 40); +} + +/* + * Read from a device register + */ +static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg) +{ + return readl(hal->ah_sh + reg); +} + +/* + * Write to a device register + */ +static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg) +{ + writel(val, hal->ah_sh + reg); +} + +static inline __u16 ath5k_hw_unaligned_read_16(__le16 *p) +{ + return le16_to_cpu(get_unaligned(p)); +} + +static inline void ath5k_hw_unaligned_write_16(__u16 v, __le16* p) +{ + put_unaligned(cpu_to_le16(v), p); +} + +static inline __u32 ath5k_hw_unaligned_read_32(__le32 *p) +{ + return le32_to_cpu(get_unaligned(p)); +} + +static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) +{ + put_unaligned(cpu_to_le32(v), p); +} + +/* + * Check if a register write has been completed + */ +static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, + u32 val, bool is_set) +{ + int i; + u32 data; + + for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { + data = ath5k_hw_reg_read(hal, reg); + if ((is_set == true) && (data & flag)) + break; + else if ((data & flag) == val) + break; + udelay(15); + } + + return (i <= 0) ? -EAGAIN : 0; +} + + + +/***************************************\ + Attach/Detach Functions +\***************************************/ + +/* + * Check if the device is supported and initialize the needed structs + */ +struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, + void __iomem *sh) +{ + struct ath_hw *hal; + u8 mac[ETH_ALEN]; + int ret; + u32 srev; + + /*TODO:Use eeprom_magic to verify chipset*/ + + /*If we passed the test malloc a hal struct*/ + hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); + if (hal == NULL) { + ret = -ENOMEM; + AR5K_PRINT("out of memory\n"); + goto err; + } + + hal->ah_sc = sc; + hal->ah_sh = sh; + + /* + * HAL information + */ + + /* Regulation Stuff */ + hal->ah_country_code = AR5K_TUNE_CTRY; + ath5k_get_regdomain(hal); + + hal->ah_op_mode = IEEE80211_IF_TYPE_STA; + hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; + hal->ah_turbo = false; + hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; + hal->ah_imr = 0; + hal->ah_atim_window = 0; + hal->ah_aifs = AR5K_TUNE_AIFS; + hal->ah_cw_min = AR5K_TUNE_CWMIN; + hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; + hal->ah_software_retry = false; + hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; + + switch (device) { + case PCI_DEVICE_ID_ATHEROS_AR2413: + case PCI_DEVICE_ID_ATHEROS_AR5413: + case PCI_DEVICE_ID_ATHEROS_AR5424: + /* + * Known single chip solutions + */ + hal->ah_single_chip = true; + break; + default: + /* + * Multi chip solutions + */ + hal->ah_single_chip = false; + break; + } + + /* + * Set the mac revision based on the pci id + */ + hal->ah_version = mac_version; + + /*Fill the hal struct with the needed functions*/ + if (hal->ah_version == AR5K_AR5212) + hal->ah_magic = AR5K_EEPROM_MAGIC_5212; + else if (hal->ah_version == AR5K_AR5211) + hal->ah_magic = AR5K_EEPROM_MAGIC_5211; + + if (hal->ah_version == AR5K_AR5212) { + hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; + hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; + hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc; + hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; + } else { + hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; + hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; + hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc; + hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; + } + + if (hal->ah_version == AR5K_AR5212) + hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; + else if (hal->ah_version <= AR5K_AR5211) + hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; + + /* Bring device out of sleep and reset it's units */ + ret = ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true); + if (ret) + goto err_free; + + /* Get MAC, PHY and RADIO revisions */ + srev = ath5k_hw_reg_read(hal, AR5K_SREV); + hal->ah_mac_srev = srev; + hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); + hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); + hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff; + hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ); + + if (hal->ah_version == AR5K_AR5210) { + hal->ah_radio_2ghz_revision = 0; + } else { + hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal, + CHANNEL_2GHZ); + } + + /* Single chip radio */ + if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) + hal->ah_radio_2ghz_revision = 0; + + /* Identify the radio chip*/ + if (hal->ah_version == AR5K_AR5210) + hal->ah_radio = AR5K_RF5110; + else + hal->ah_radio = hal->ah_radio_5ghz_revision < + AR5K_SREV_RAD_5112 ? AR5K_RF5111 : AR5K_RF5112; + + hal->ah_phy = AR5K_PHY(0); + + /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a + * temporary variable for setting our BSSID. Right bellow we update + * it with ath5k_hw_get_lladdr() */ + memset(mac, 0xff, ETH_ALEN); + ath5k_hw_set_associd(hal, mac, 0); + + ath5k_hw_get_lladdr(hal, mac); + ath5k_hw_set_opmode(hal); + +#ifdef AR5K_DEBUG + hal->ah_dump_state(hal); +#endif + + /* + * Get card capabilities, values, ... + */ + + ret = ath5k_eeprom_init(hal); + if (ret) { + AR5K_PRINT("unable to init EEPROM\n"); + goto err_free; + } + + /* Get misc capabilities */ + ret = ath5k_hw_get_capabilities(hal); + if (ret) { + AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", + device); + goto err_free; + } + + /* Get MAC address */ + ret = ath5k_eeprom_read_mac(hal, mac); + if (ret) { + AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", + device); + goto err_free; + } + + ath5k_hw_set_lladdr(hal, mac); + + /* Initialize the gain optimization values */ + /*For RF5111*/ + if (hal->ah_radio == AR5K_RF5111) { + hal->ah_gain.g_step_idx = rf5111_gain_opt.go_default; + hal->ah_gain.g_step = + &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; + hal->ah_gain.g_low = 20; + hal->ah_gain.g_high = 35; + hal->ah_gain.g_active = 1; + /*For RF5112*/ + } else if (hal->ah_radio == AR5K_RF5112) { + hal->ah_gain.g_step_idx = rf5112_gain_opt.go_default; + hal->ah_gain.g_step = + &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; + hal->ah_gain.g_low = 20; + hal->ah_gain.g_high = 85; + hal->ah_gain.g_active = 1; + } + + return hal; +err_free: + kfree(hal); +err: + return ERR_PTR(ret); +} + +/* + * Bring up MAC + PHY Chips + */ +static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) +{ + u32 turbo, mode, clock; + int ret; + + turbo = 0; + mode = 0; + clock = 0; + + AR5K_TRACE; + + if (hal->ah_version != AR5K_AR5210) { + /* + * Get channel mode flags + */ + + if (hal->ah_radio >= AR5K_RF5112) { + mode = AR5K_PHY_MODE_RAD_RF5112; + clock = AR5K_PHY_PLL_RF5112; + } else { + mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ + clock = AR5K_PHY_PLL_RF5111; /*Zero*/ + } + + if (flags & CHANNEL_2GHZ) { + mode |= AR5K_PHY_MODE_FREQ_2GHZ; + clock |= AR5K_PHY_PLL_44MHZ; + } else if (flags & CHANNEL_5GHZ) { + mode |= AR5K_PHY_MODE_FREQ_5GHZ; + clock |= AR5K_PHY_PLL_40MHZ; + } else { + AR5K_PRINT("invalid radio frequency mode\n"); + return -EINVAL; + } + + if (flags & CHANNEL_CCK) { + mode |= AR5K_PHY_MODE_MOD_CCK; + } else if (flags & CHANNEL_G) { + /* Dynamic OFDM/CCK is not supported by the AR5211 */ + if (hal->ah_version == AR5K_AR5211) { + mode |= AR5K_PHY_MODE_MOD_OFDM; + } else { + mode |= AR5K_PHY_MODE_MOD_DYN; + } + } else if (flags & CHANNEL_OFDM) { + mode |= AR5K_PHY_MODE_MOD_OFDM; + } else { + AR5K_PRINT("invalid radio frequency mode\n"); + return -EINVAL; + } + + if (flags & CHANNEL_TURBO) { + turbo = AR5K_PHY_TURBO_MODE | + AR5K_PHY_TURBO_SHORT; + } + } + + /* + * Reset and wakeup the device + */ + + else { + if (initial == true) { + /* ...reset hardware */ + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) { + AR5K_PRINT("failed to reset the PCI chipset\n"); + return -EIO; + } + + mdelay(1); + } + + /* ...wakeup */ + ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); + if (ret) { + AR5K_PRINT("failed to resume the MAC Chip\n"); + return ret; + } + + /* ...enable Atheros turbo mode if requested */ + if (flags & CHANNEL_TURBO) + ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO); + + /* ...reset chipset */ + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) { + AR5K_PRINT("failed to reset the AR5210 chipset\n"); + return -EIO; + } + + mdelay(1); + } + + /* ...reset chipset and PCI device */ + if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal, + AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) { + AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); + return -EIO; + } + + if (hal->ah_version == AR5K_AR5210) + udelay(2300); + + /* ...wakeup */ + ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); + if (ret) { + AR5K_PRINT("failed to resume the MAC Chip\n"); + return ret; + } + + /* ...final warm reset */ + if (ath5k_hw_nic_reset(hal, 0)) { + AR5K_PRINT("failed to warm reset the MAC Chip\n"); + return -EIO; + } + + if (hal->ah_version != AR5K_AR5210){ + /* ...set the PHY operating mode */ + ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL); + udelay(300); + + ath5k_hw_reg_write(hal, mode, AR5K_PHY_MODE); + ath5k_hw_reg_write(hal, turbo, AR5K_PHY_TURBO); + } + + return 0; +} + +/* + * Get the PHY Chip revision + */ +static u16 +ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) +{ + int i; + u32 srev; + u16 ret; + + AR5K_TRACE; + + /* + * Set the radio chip access register + */ + switch (chan) { + case CHANNEL_2GHZ: + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); + break; + case CHANNEL_5GHZ: + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); + break; + default: + return 0; + } + + mdelay(2); + + /* ...wait until PHY is ready and read the selected radio revision */ + ath5k_hw_reg_write(hal, 0x00001c16, AR5K_PHY(0x34)); + + for (i = 0; i < 8; i++) + ath5k_hw_reg_write(hal, 0x00010000, AR5K_PHY(0x20)); + + if (hal->ah_version == AR5K_AR5210) { + srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf; + + ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; + } else { + srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff; + + ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + } + + /* Reset to the 5GHz mode */ + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); + + return ret; +} + +/* + * Get the rate table for a specific operation mode + * TODO:Limit this per chipset + */ +const struct ath5k_rate_table * +ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) +{ + AR5K_TRACE; + + /* Get rate tables */ + if (!test_bit(mode, hal->ah_capabilities.cap_mode)) + return NULL; + + switch (mode) { + case MODE_IEEE80211A: + return &ath5k_rt_11a; + case MODE_ATHEROS_TURBO: + return &ath5k_rt_turbo; + case MODE_IEEE80211B: + return &ath5k_rt_11b; + case MODE_IEEE80211G: + return &ath5k_rt_11g; + case MODE_ATHEROS_TURBOG: + return &ath5k_rt_xr; + default: + return NULL; + } + + return NULL; +} + +/* + * Free the hal struct + */ +void ath5k_hw_detach(struct ath_hw *hal) +{ + AR5K_TRACE; + + if (hal->ah_rf_banks != NULL) + kfree(hal->ah_rf_banks); + + /* assume interrupts are down */ + kfree(hal); +} + +/*******************************\ + Reset Functions +\*******************************/ + +/* + * Main reset function + */ +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, + struct ieee80211_channel *channel, bool change_channel) +{ + const struct ath5k_rate_table *rt; + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u32 data, noise_floor, s_seq, s_ant, s_led[3]; + u8 mac[ETH_ALEN]; + unsigned int i, phy, mode, freq, off, ee_mode, ant[2]; + int ret; + + AR5K_TRACE; + + s_seq = 0; + s_ant = 1; + ee_mode = 0; + freq = 0; + mode = 0; + phy = 0; + + /* + * Save some registers before a reset + */ + /*DCU/Antenna selection not available on 5210*/ + if (hal->ah_version != AR5K_AR5210) { + if (change_channel == true) { + /*Sequence number for queue 0 -do this for all queues ?*/ + s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0)); + /*Default antenna*/ + s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); + } + } + + /*GPIOs*/ + s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; + s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR); + s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO); + + if (change_channel == true && hal->ah_rf_banks != NULL) + ath5k_hw_get_rf_gain(hal); + + + /*Wakeup the device*/ + ret = ath5k_hw_nic_wakeup(hal, channel->val, false); + if (ret) + return ret; + + /* + * Initialize operating mode + */ + hal->ah_op_mode = op_mode; + + /* + * 5111/5112 Settings + * 5210 only comes with RF5110 + */ + if (hal->ah_version != AR5K_AR5210) { + if (hal->ah_radio == AR5K_RF5111) + phy = AR5K_INI_PHY_5111; + else if (hal->ah_radio == AR5K_RF5112) + phy = AR5K_INI_PHY_5112; + else { + AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); + return -EINVAL; + } + + switch (channel->val & CHANNEL_MODES) { + case CHANNEL_A: + mode = AR5K_INI_VAL_11A; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + case CHANNEL_B: + mode = AR5K_INI_VAL_11B; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11B; + break; + case CHANNEL_G: + mode = AR5K_INI_VAL_11G; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_T: + mode = AR5K_INI_VAL_11A_TURBO; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + /*Is this ok on 5211 too ?*/ + case CHANNEL_TG: + mode = AR5K_INI_VAL_11G_TURBO; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_XR: + if (hal->ah_version == AR5K_AR5211) { + AR5K_PRINTF("XR mode not available on 5211"); + return -EINVAL; + } + mode = AR5K_INI_VAL_XR; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + default: + AR5K_PRINTF("invalid channel: %d\n", channel->freq); + return -EINVAL; + } + + /* PHY access enable */ + ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); + + /* + * Write initial RF registers on 5211 + * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ? + */ + if (hal->ah_version == AR5K_AR5211) + ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode); + } + + /* + * Write initial mode settings + * TODO:Do this in a common way + */ + /*For 5212*/ + if (hal->ah_version == AR5K_AR5212) { + for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) { + if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) + off = AR5K_INI_PHY_511X; + else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && + hal->ah_radio == AR5K_RF5111) + off = AR5K_INI_PHY_5111; + else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 && + hal->ah_radio == AR5K_RF5112) + off = AR5K_INI_PHY_5112; + else + continue; + + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, + ar5212_mode[i].mode_value[off][mode], + (u32)ar5212_mode[i].mode_register); + } + } + /*For 5211*/ + if (hal->ah_version == AR5K_AR5211) { + for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, + ar5211_mode[i].mode_value[mode], + (u32)ar5211_mode[i].mode_register); + } + } + + /* + * Write initial register settings + * TODO:Do this in a common way + */ + /*For 5212*/ + if (hal->ah_version == AR5K_AR5212) { + for (i = 0; i < ARRAY_SIZE(ar5212_ini); i++) { + if (change_channel == true && + ar5212_ini[i].ini_register >= AR5K_PCU_MIN && + ar5212_ini[i].ini_register <= AR5K_PCU_MAX) + continue; + + if ((hal->ah_radio == AR5K_RF5111 && + ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) || + (hal->ah_radio == AR5K_RF5112 && + ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, + ar5212_ini[i].ini_value, + (u32)ar5212_ini[i].ini_register); + } + } + } + /*For 5211*/ + if (hal->ah_version == AR5K_AR5211) { + for (i = 0; i < ARRAY_SIZE(ar5211_ini); i++) { + if (change_channel == true && + ar5211_ini[i].ini_register >= AR5K_PCU_MIN && + ar5211_ini[i].ini_register <= AR5K_PCU_MAX) + continue; + + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, + ar5211_ini[i].ini_value, + (u32)ar5211_ini[i].ini_register); + } + } + /*For 5210*/ + if (hal->ah_version == AR5K_AR5210) + for (i = 0; i < ARRAY_SIZE(ar5210_ini); i++) { + if (change_channel == true && + ar5210_ini[i].ini_register >= AR5K_PCU_MIN && + ar5210_ini[i].ini_register <= AR5K_PCU_MAX) + continue; + + switch (ar5210_ini[i].ini_mode) { + case AR5K_INI_READ: + /* Cleared on read */ + ath5k_hw_reg_read(hal, ar5210_ini[i].ini_register); + break; + + case AR5K_INI_WRITE: + default: + ath5k_hw_reg_write(hal, ar5210_ini[i].ini_value, + ar5210_ini[i].ini_register); + } + } + + /* + * 5211/5212 Specific + */ + if (hal->ah_version != AR5K_AR5210) { + /* + * Write initial RF gain settings + * This should work for both 5111/5112 + */ + if (ath5k_hw_rfgain(hal, phy, freq) == false) { + return -EIO; + } + + mdelay(1); + + /* + * Set rate duration table on 5212 + */ + if (hal->ah_version == AR5K_AR5212) { + + /*For 802.11b*/ + if (!(channel->val & CHANNEL_B)) { + + /*Get rate table for this operation mode*/ + rt = ath5k_hw_get_rate_table(hal, + MODE_IEEE80211B); + + /*Write rate duration table*/ + for (i = 0; i < rt->rate_count; i++) { + data = AR5K_RATE_DUR(rt->rates[i].rate_code); + ath5k_hw_reg_write(hal, + ath_hal_computetxtime(hal, rt, + 14, rt->rates[i].control_rate, + false), data); + if (HAS_SHPREAMBLE(i)) { + ath5k_hw_reg_write(hal, + ath_hal_computetxtime(hal, rt, 14, + rt->rates[i].control_rate, false), + data + + (AR5K_SET_SHORT_PREAMBLE << 2)); + } + } + + } else { + /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ + + /*Get rate table for this operation mode*/ + rt = ath5k_hw_get_rate_table(hal, + channel->val & CHANNEL_TURBO ? + MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG); + + /*Write rate duration table*/ + for (i = 0; i < rt->rate_count; i++) { + ath5k_hw_reg_write(hal, + ath_hal_computetxtime(hal, rt, + 14, rt->rates[i].control_rate, + false), + AR5K_RATE_DUR(rt->rates[i].rate_code)); + } + + } + } + + /* Fix for first revision of the RF5112 RF chipset */ + if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision< + AR5K_SREV_RAD_5112A) { + ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD, + AR5K_PHY_CCKTXCTL); + if (channel->val & CHANNEL_A) + data = 0xffb81020; + else + data = 0xffb80d20; + ath5k_hw_reg_write(hal, data, AR5K_PHY_FRAME_CTL); + } + + /* + * Set TX power (XXX use txpower from net80211) + */ + ret = ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER); + if (ret) + return ret; + + /* + * Write RF registers + * TODO:Does this work on 5211 (5111) ? + */ + if (ath5k_hw_rfregs(hal, channel, mode) == false) { + return -EINPROGRESS; + } + + /* + * Configure additional registers + */ + + /* Write OFDM timings on 5212*/ + if (hal->ah_version == AR5K_AR5212) { + if (channel->val & CHANNEL_OFDM) { + u32 coef_scaled, coef_exp, coef_man, ds_coef_exp, + ds_coef_man, clock; + + clock = channel->val & CHANNEL_T ? 80 : 40; + coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; + + for (coef_exp = 31; coef_exp > 0; coef_exp--) + if ((coef_scaled >> coef_exp) & 0x1) + break; + + if (!coef_exp) { + return -EINVAL; + } + + coef_exp = 14 - (coef_exp - 24); + coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); + ds_coef_man = coef_man >> (24 - coef_exp); + ds_coef_exp = coef_exp - 16; + + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); + } + } + + /*Enable/disable 802.11b mode on 5111 + (enable 2111 frequency converter + CCK)*/ + if (hal->ah_radio == AR5K_RF5111) { + if (channel->val & CHANNEL_B) + AR5K_REG_ENABLE_BITS(hal, AR5K_TXCFG, + AR5K_TXCFG_B_MODE); + else + AR5K_REG_DISABLE_BITS(hal, AR5K_TXCFG, + AR5K_TXCFG_B_MODE); + } + + /* Set antenna mode */ + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44), + hal->ah_antenna[ee_mode][0], 0xfffffc06); + + if (freq == AR5K_INI_RFGAIN_2GHZ) + ant[0] = ant[1] = AR5K_ANT_FIXED_B; + else + ant[0] = ant[1] = AR5K_ANT_FIXED_A; + + + ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]], + AR5K_PHY_ANT_SWITCH_TABLE_0); + ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[1]], + AR5K_PHY_ANT_SWITCH_TABLE_1); + + /* Commit values from EEPROM */ + if (hal->ah_radio == AR5K_RF5111) + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_FRAME_CTL, + AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); + + ath5k_hw_reg_write(hal, + AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), + AR5K_PHY(0x5a)); + + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11), + (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12), + (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14), + (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | + ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); + + ath5k_hw_reg_write(hal, + (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | + (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | + (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | + (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); + + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a), + ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19), + (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); + AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01); + + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, + AR5K_PHY_IQ_CORR_ENABLE | + (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | + ee->ee_q_cal[ee_mode]); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ, + AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, + ee->ee_margin_tx_rx[ee_mode]); + } + + } else { + mdelay(1); + /* Disable phy and wait */ + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); + mdelay(1); + } + + /* + * Restore saved values + */ + /*DCU/Antenna selection not available on 5210*/ + if (hal->ah_version != AR5K_AR5210) { + ath5k_hw_reg_write(hal, s_seq, AR5K_QUEUE_DFS_SEQNUM(0)); + ath5k_hw_reg_write(hal, s_ant, AR5K_DEFAULT_ANTENNA); + } + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, s_led[0]); + ath5k_hw_reg_write(hal, s_led[1], AR5K_GPIOCR); + ath5k_hw_reg_write(hal, s_led[2], AR5K_GPIODO); + + /* + * Misc + */ + memset(mac, 0xff, ETH_ALEN); + ath5k_hw_set_associd(hal, mac, 0); + ath5k_hw_set_opmode(hal); + /*PISR/SISR Not available on 5210*/ + if (hal->ah_version != AR5K_AR5210) { + ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR); + /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so + * direct write using ath5k_hw_reg_write seems wrong. Test with: + * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, + * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); + * with different variables and check results compared + * to ath5k_hw_reg_write(hal, ) */ + ath5k_hw_reg_write(hal, AR5K_TUNE_RSSI_THRES, AR5K_RSSI_THR); + } + + /* + * Set Rx/Tx DMA Configuration + *(passing dma size not available on 5210) + */ + if (hal->ah_version != AR5K_AR5210) { + AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, + AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); + AR5K_REG_WRITE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, + AR5K_DMASIZE_512B); + } + + /* + * Set channel and calibrate the PHY + */ + if (ath5k_hw_channel(hal, channel) == false) + return -EIO; + + /* + * Enable the PHY and wait until completion + */ + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); + + /* + * 5111/5112 Specific + */ + if (hal->ah_version != AR5K_AR5210) { + data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; + data = (channel->val & CHANNEL_CCK) ? + ((data << 2) / 22) : (data / 10); + + udelay(100 + data); + } else { + mdelay(1); + } + + /* + * Enable calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL); + + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL, 0, false)) { + AR5K_PRINTF("calibration timeout (%uMHz)\n", + channel->freq); + return -EAGAIN; + } + + /* + * Enable noise floor calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF); + + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF, 0, false)) { + AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", + channel->freq); + return -EAGAIN; + } + + /* Wait until the noise floor is calibrated and read the value */ + for (i = 20; i > 0; i--) { + mdelay(1); + noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); + + if (AR5K_PHY_NF_RVAL(noise_floor) & + AR5K_PHY_NF_ACTIVE) + noise_floor = AR5K_PHY_NF_AVAL(noise_floor); + + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) + break; + } + + if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { + AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", + channel->freq); + return -EIO; + } + + hal->ah_calibration = false; + + if (!(channel->val & CHANNEL_B)) { + hal->ah_calibration = true; + AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ, + AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, + AR5K_PHY_IQ_RUN); + } + + /* + * Reset queues and start beacon timers at the end of the reset routine + */ + for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { + /*No QCU on 5210*/ + if (hal->ah_version != AR5K_AR5210) + AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i); + + if (ath5k_hw_reset_tx_queue(hal, i) == false) { + AR5K_PRINTF("failed to reset TX queue #%d\n", i); + return -EINVAL; + } + } + + /* Pre-enable interrupts on 5211/5212*/ + if (hal->ah_version != AR5K_AR5210) { + ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); + } + + /* + * Set RF kill flags if supported by the device (read from the EEPROM) + * Disable gpio_intr for now since it results system hang. + * TODO: Handle this in ath_intr + */ +#if 0 + if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { + ath5k_hw_set_gpio_input(hal, 0); + if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0) + ath5k_hw_set_gpio_intr(hal, 0, 1); + else + ath5k_hw_set_gpio_intr(hal, 0, 0); + } +#endif + + /* + * Set the 32MHz reference clock on 5212 phy clock sleep register + */ + if (hal->ah_version == AR5K_AR5212) { + ath5k_hw_reg_write(hal, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR); + ath5k_hw_reg_write(hal, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); + ath5k_hw_reg_write(hal, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL); + ath5k_hw_reg_write(hal, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); + ath5k_hw_reg_write(hal, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); + ath5k_hw_reg_write(hal, hal->ah_radio == AR5K_RF5111 ? + AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112, + AR5K_PHY_SPENDING); + } + + /* + * Disable beacons and reset the register + */ + AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, + AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); + + return 0; +} + +/* + * Reset chipset + */ +static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) +{ + int ret; + u32 mask = val ? val : ~0; + + AR5K_TRACE; + + /* Read-and-clear RX Descriptor Pointer*/ + ath5k_hw_reg_read(hal, AR5K_RXDP); + + /* + * Reset the device and wait until success + */ + ath5k_hw_reg_write(hal, val, AR5K_RESET_CTL); + + /* Wait at least 128 PCI clocks */ + udelay(15); + + if (hal->ah_version == AR5K_AR5210) { + val &= AR5K_RESET_CTL_CHIP; + mask &= AR5K_RESET_CTL_CHIP; + } else { + val &= + AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + + mask &= + AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + } + + ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false); + + /* + * Reset configuration register (for hw byte-swap) + */ + if ((val & AR5K_RESET_CTL_PCU) == 0) + ath5k_hw_reg_write(hal, AR5K_INIT_CFG, AR5K_CFG); + + return ret; +} + +/* + * Power management functions + */ + +/* + * Sleep control + */ +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, + bool set_chip, u16 sleep_duration) +{ + u32 staid; + int i; + + AR5K_TRACE; + staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1); + + switch (mode) { + case AR5K_PM_AUTO: + staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; + /* fallthrough */ + case AR5K_PM_NETWORK_SLEEP: + if (set_chip == true) { + ath5k_hw_reg_write(hal, + AR5K_SLEEP_CTL_SLE | sleep_duration, + AR5K_SLEEP_CTL); + } + staid |= AR5K_STA_ID1_PWR_SV; + break; + + case AR5K_PM_FULL_SLEEP: + if (set_chip == true) { + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP, + AR5K_SLEEP_CTL); + } + staid |= AR5K_STA_ID1_PWR_SV; + break; + + case AR5K_PM_AWAKE: + if (set_chip == false) + goto commit; + + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL); + + for (i = 5000; i > 0; i--) { + /* Check if the chip did wake up */ + if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) & + AR5K_PCICFG_SPWR_DN) == 0) + break; + + /* Wait a bit and retry */ + udelay(200); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, + AR5K_SLEEP_CTL); + } + + /* Fail if the chip didn't wake up */ + if (i <= 0) + return -EIO; + + staid &= ~AR5K_STA_ID1_PWR_SV; + break; + + default: + return -EINVAL; + } + +commit: + hal->ah_power_mode = mode; + ath5k_hw_reg_write(hal, staid, AR5K_STA_ID1); + + return 0; +} + +/* + * Get power mode (sleep state) + * TODO:Remove ? + */ +enum ath5k_power_mode +ath5k_hw_get_power_mode(struct ath_hw *hal) +{ + AR5K_TRACE; + return hal->ah_power_mode; +} + + + + +/***********************\ + DMA Related Functions +\***********************/ + +/* + * Receive functions + */ + +/* + * Start DMA receive + */ +void ath5k_hw_start_rx(struct ath_hw *hal) +{ + AR5K_TRACE; + ath5k_hw_reg_write(hal, AR5K_CR_RXE, AR5K_CR); +} + +/* + * Stop DMA receive + */ +int ath5k_hw_stop_rx_dma(struct ath_hw *hal) +{ + unsigned int i; + + AR5K_TRACE; + ath5k_hw_reg_write(hal, AR5K_CR_RXD, AR5K_CR); + + /* + * It may take some time to disable the DMA receive unit + */ + for (i = 2000; i > 0 && + (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_RXE) != 0; + i--) + udelay(10); + + return i ? 0 : -EBUSY; +} + +/* + * Get the address of the RX Descriptor + */ +u32 ath5k_hw_get_rx_buf(struct ath_hw *hal) +{ + return ath5k_hw_reg_read(hal, AR5K_RXDP); +} + +/* + * Set the address of the RX Descriptor + */ +void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) +{ + AR5K_TRACE; + + /*TODO:Shouldn't we check if RX is enabled first ?*/ + ath5k_hw_reg_write(hal, phys_addr, AR5K_RXDP); +} + +/* + * Transmit functions + */ + +/* + * Start DMA transmit for a specific queue + * (see also QCU/DCU functions) + */ +int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) +{ + u32 tx_queue; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* Return if queue is declared inactive */ + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return -EIO; + + if (hal->ah_version == AR5K_AR5210) { + tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); + + /* + * Set the queue by type on 5210 + */ + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; + break; + case AR5K_TX_QUEUE_BEACON: + tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | + AR5K_BCR_BDMAE, AR5K_BSR); + break; + case AR5K_TX_QUEUE_CAB: + tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | + AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, + AR5K_BSR); + break; + default: + return -EINVAL; + } + /* Start queue */ + ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); + } else { + /* Return if queue is disabled */ + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXD, queue)) + return -EIO; + + /* Start queue */ + AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXE, queue); + } + + return 0; +} + +/* + * Stop DMA transmit for a specific queue + * (see also QCU/DCU functions) + */ +bool +ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) +{ + int i = 100, pending; + u32 tx_queue; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* Return if queue is declared inactive */ + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return false; + + if (hal->ah_version == AR5K_AR5210) { + tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); + + /* + * Set by queue type + */ + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + /* XXX Fix me... */ + tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; + ath5k_hw_reg_write(hal, 0, AR5K_BSR); + break; + default: + return false; + } + + /* Stop queue */ + ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); + } else { + /* + * Schedule TX disable and wait until queue is empty + */ + AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXD, queue); + + /*Check for pending frames*/ + do { + pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) & + AR5K_QCU_STS_FRMPENDCNT; + udelay(100); + } while (--i && pending); + + /* Clear register */ + ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD); + } + + /*TODO: Check for success else return false*/ + return true; +} + +/* + * Get the address of the TX Descriptor for a specific queue + * (see also QCU/DCU functions) + */ +u32 +ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) +{ + u16 tx_reg; + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* + * Get the transmit queue descriptor pointer from the selected queue + */ + /*5210 doesn't have QCU*/ + if (hal->ah_version == AR5K_AR5210) { + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_reg = AR5K_NOQCU_TXDP0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + tx_reg = AR5K_NOQCU_TXDP1; + break; + default: + return 0xffffffff; + } + } else { + tx_reg = AR5K_QUEUE_TXDP(queue); + } + + return ath5k_hw_reg_read(hal, tx_reg); +} + +/* + * Set the address of the TX Descriptor for a specific queue + * (see also QCU/DCU functions) + */ +int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) +{ + u16 tx_reg; + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* + * Set the transmit queue descriptor pointer register by type + * on 5210 + */ + if (hal->ah_version == AR5K_AR5210) { + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_reg = AR5K_NOQCU_TXDP0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + tx_reg = AR5K_NOQCU_TXDP1; + break; + default: + return -EINVAL; + } + } else { + /* + * Set the transmit queue descriptor pointer for + * the selected queue on QCU for 5211+ + * (this won't work if the queue is still active) + */ + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, queue)) + return -EIO; + + tx_reg = AR5K_QUEUE_TXDP(queue); + } + + /* Set descriptor pointer */ + ath5k_hw_reg_write(hal, phys_addr, tx_reg); + + return 0; +} + +/* + * Update tx trigger level + */ +bool +ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) +{ + u32 trigger_level, imr; + bool status = false; + AR5K_TRACE; + + /* + * Disable interrupts by setting the mask + */ + imr = ath5k_hw_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); + + /*TODO: Boundary check on trigger_level*/ + trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TXCFG), + AR5K_TXCFG_TXFULL); + + if (increase == false) { + if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) + goto done; + } else + trigger_level += + ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); + + /* + * Update trigger level on success + */ + if (hal->ah_version == AR5K_AR5210) + ath5k_hw_reg_write(hal, trigger_level, AR5K_TRIG_LVL); + else + AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, + AR5K_TXCFG_TXFULL, trigger_level); + + status = true; + + done: + /* + * Restore interrupt mask + */ + ath5k_hw_set_intr(hal, imr); + + return status; +} + +/* + * Interrupt handling + */ + +/* + * Check if we have pending interrupts + */ +bool ath5k_hw_is_intr_pending(struct ath_hw *hal) +{ + AR5K_TRACE; + return ath5k_hw_reg_read(hal, AR5K_INTPEND); +} + +/* + * Get interrupt mask (ISR) + */ +int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) +{ + u32 data; + + AR5K_TRACE; + + /* + * Read interrupt status from the Interrupt Status register + * on 5210 + */ + if (hal->ah_version == AR5K_AR5210) { + data = ath5k_hw_reg_read(hal, AR5K_ISR); + if (data == AR5K_INT_NOCARD) { + *interrupt_mask = data; + return -ENODEV; + } + } + + /* + * Read interrupt status from the Read-And-Clear shadow register + */ + data = ath5k_hw_reg_read(hal, AR5K_RAC_PISR); + + /* + * Get abstract interrupt mask (HAL-compatible) + */ + *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; + + if (data == AR5K_INT_NOCARD) + return -ENODEV; + + if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) + *interrupt_mask |= AR5K_INT_RX; + + if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR)) + *interrupt_mask |= AR5K_INT_TX; + + if (hal->ah_version != AR5K_AR5210) { + /*HIU = Host Interface Unit (PCI etc)*/ + if (data & (AR5K_ISR_HIUERR)) + *interrupt_mask |= AR5K_INT_FATAL; + + /*Beacon Not Ready*/ + if (data & (AR5K_ISR_BNR)) + *interrupt_mask |= AR5K_INT_BNR; + } + + /* + * XXX: BMISS interrupts may occur after association. + * I found this on 5210 code but it needs testing + */ +#if 0 + interrupt_mask &= ~AR5K_INT_BMISS; +#endif + + /* + * In case we didn't handle anything, + * print the register value. + */ + if (*interrupt_mask == 0 && printk_ratelimit()) + AR5K_PRINTF("0x%08x\n", data); + + return 0; +} + +/* + * Set interrupt mask + */ +enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) +{ + enum ath5k_int old_mask, int_mask; + + /* + * Disable card interrupts to prevent any race conditions + * (they will be re-enabled afterwards). + */ + ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); + + old_mask = hal->ah_imr; + + /* + * Add additional, chipset-dependent interrupt mask flags + * and write them to the IMR (interrupt mask register). + */ + int_mask = new_mask & AR5K_INT_COMMON; + + if (new_mask & AR5K_INT_RX) + int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN | + AR5K_IMR_RXDESC; + + if (new_mask & AR5K_INT_TX) + int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC | + AR5K_IMR_TXURN; + + if (hal->ah_version != AR5K_AR5210) { + if (new_mask & AR5K_INT_FATAL) { + int_mask |= AR5K_IMR_HIUERR; + AR5K_REG_ENABLE_BITS(hal, AR5K_SIMR2, AR5K_SIMR2_MCABT | + AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR); + } + } + + ath5k_hw_reg_write(hal, int_mask, AR5K_PIMR); + + /* Store new interrupt mask */ + hal->ah_imr = new_mask; + + /* ..re-enable interrupts */ + ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); + + return old_mask; +} + +/* + * Enalbe HW radar detection + */ +void +ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) +{ + + AR5K_TRACE; + /* + * Enable radar detection + */ + + /*Disable interupts*/ + ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); + + /* + * Set the RXPHY interrupt to be able to detect + * possible radar activity. + */ + if (hal->ah_version == AR5K_AR5210) { + if (enable == true) { + AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, + AR5K_IMR_RXPHY); + } else { + AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, + AR5K_IMR_RXPHY); + } + } else { + /*Also set AR5K_PHY_RADAR register on 5111/5112*/ + if (enable == true) { + ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_ENABLE, + AR5K_PHY_RADAR); + AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, + AR5K_IMR_RXPHY); + } else { + ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_DISABLE, + AR5K_PHY_RADAR); + AR5K_REG_DISABLE_BITS(hal, AR5K_PIMR, + AR5K_IMR_RXPHY); + } + } + + /*Re-enable interrupts*/ + ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); +} + + + + +/*************************\ + EEPROM access functions +\*************************/ + +/* + * Read from eeprom + */ +static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) +{ + u32 status, timeout; + + AR5K_TRACE; + /* + * Initialize EEPROM access + */ + if (hal->ah_version == AR5K_AR5210) { + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); + (void)ath5k_hw_reg_read(hal, AR5K_EEPROM_BASE + (4 * offset)); + } else { + ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_READ); + } + + for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { + status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); + if (status & AR5K_EEPROM_STAT_RDDONE) { + if (status & AR5K_EEPROM_STAT_RDERR) + return -EIO; + *data = (u16) + (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff); + return 0; + } + udelay(15); + } + + return -ETIMEDOUT; +} + +/* + * Write to eeprom - currently disabled, use at your own risk + */ +static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) +{ +#if 0 + u32 status, timeout; + + AR5K_TRACE; + + /* + * Initialize eeprom access + */ + + if (hal->ah_version == AR5K_AR5210) { + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); + } else { + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); + } + + /* + * Write data to data register + */ + + if (hal->ah_version == AR5K_AR5210) { + ath5k_hw_reg_write(hal, data, AR5K_EEPROM_BASE + (4 * offset)); + } else { + ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); + ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); + } + + /* + * Check status + */ + + for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { + status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); + if (status & AR5K_EEPROM_STAT_WRDONE) { + if (status & AR5K_EEPROM_STAT_WRERR) + return EIO; + return 0; + } + udelay(15); + } +#endif + AR5K_PRINTF("EEPROM Write is disabled!"); + return -EIO; +} + +u16 +ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) +{ + u16 val; + + if (bin == AR5K_EEPROM_CHANNEL_DIS) + return bin; + + if (mode == AR5K_EEPROM_MODE_11A) { + if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) + val = (5 * bin) + 4800; + else + val = bin > 62 ? + (10 * 62) + (5 * (bin - 62)) + 5100 : + (bin * 10) + 5100; + } else { + if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) + val = bin + 2300; + else + val = bin + 2400; + } + + return val; +} + +/* + * Read antenna infos from eeprom + */ +int +ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u32 o = *offset; + u16 val; + int ret, i = 0; + + AR5K_EEPROM_READ(o++, val); + ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; + ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; + ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; + ee->ee_ant_control[mode][i++] = val & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; + ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; + ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; + ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; + ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; + ee->ee_ant_control[mode][i++] = val & 0x3f; + + /* Get antenna modes */ + hal->ah_antenna[mode][0] = + (ee->ee_ant_control[mode][0] << 4) | 0x1; + hal->ah_antenna[mode][AR5K_ANT_FIXED_A] = + ee->ee_ant_control[mode][1] | + (ee->ee_ant_control[mode][2] << 6) | + (ee->ee_ant_control[mode][3] << 12) | + (ee->ee_ant_control[mode][4] << 18) | + (ee->ee_ant_control[mode][5] << 24); + hal->ah_antenna[mode][AR5K_ANT_FIXED_B] = + ee->ee_ant_control[mode][6] | + (ee->ee_ant_control[mode][7] << 6) | + (ee->ee_ant_control[mode][8] << 12) | + (ee->ee_ant_control[mode][9] << 18) | + (ee->ee_ant_control[mode][10] << 24); + + /* return new offset */ + *offset = o; + + return 0; +} + +/* + * Read supported modes from eeprom + */ +int +ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u32 o = *offset; + u16 val; + int ret; + + AR5K_EEPROM_READ(o++, val); + ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; + ee->ee_thr_62[mode] = val & 0xff; + + if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) + ee->ee_thr_62[mode] = + mode == AR5K_EEPROM_MODE_11A ? 15 : 28; + + AR5K_EEPROM_READ(o++, val); + ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; + ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; + + AR5K_EEPROM_READ(o++, val); + ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; + + if ((val & 0xff) & 0x80) + ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); + else + ee->ee_noise_floor_thr[mode] = val & 0xff; + + if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) + ee->ee_noise_floor_thr[mode] = + mode == AR5K_EEPROM_MODE_11A ? -54 : -1; + + AR5K_EEPROM_READ(o++, val); + ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; + ee->ee_x_gain[mode] = (val >> 1) & 0xf; + ee->ee_xpd[mode] = val & 0x1; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) + ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { + AR5K_EEPROM_READ(o++, val); + ee->ee_false_detect[mode] = (val >> 6) & 0x7f; + + if (mode == AR5K_EEPROM_MODE_11A) + ee->ee_xr_power[mode] = val & 0x3f; + else { + ee->ee_ob[mode][0] = val & 0x7; + ee->ee_db[mode][0] = (val >> 3) & 0x7; + } + } + + if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { + ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; + ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; + } else { + ee->ee_i_gain[mode] = (val >> 13) & 0x7; + + AR5K_EEPROM_READ(o++, val); + ee->ee_i_gain[mode] |= (val << 3) & 0x38; + + if (mode == AR5K_EEPROM_MODE_11G) + ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; + } + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && + mode == AR5K_EEPROM_MODE_11A) { + ee->ee_i_cal[mode] = (val >> 8) & 0x3f; + ee->ee_q_cal[mode] = (val >> 3) & 0x1f; + } + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && + mode == AR5K_EEPROM_MODE_11G) + ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; + + /* return new offset */ + *offset = o; + + return 0; +} + +/* + * Initialize eeprom & capabilities structs + */ +static int ath5k_eeprom_init(struct ath_hw *hal) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u32 offset; + u16 val; + int ret, i; + unsigned int mode; + + /* Initial TX thermal adjustment values */ + ee->ee_tx_clip = 4; + ee->ee_pwd_84 = ee->ee_pwd_90 = 1; + ee->ee_gain_select = 1; + + /* + * Read values from EEPROM and store them in the capability structure + */ + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); + + /* Return if we have an old EEPROM */ + if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) + return 0; + +#ifdef notyet + /* + * Validate the checksum of the EEPROM date. There are some + * devices with invalid EEPROMs. + */ + for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { + AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); + cksum ^= val; + } + if (cksum != AR5K_EEPROM_INFO_CKSUM) { + AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); + return -EIO; + } +#endif + + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), + ee_ant_gain); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); + } + + if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { + AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); + ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; + ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; + + AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); + ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; + ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; + } + + /* + * Get conformance test limit values + */ + offset = AR5K_EEPROM_CTL(hal->ah_ee_version); + ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); + + for (i = 0; i < ee->ee_ctls; i++) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_ctl[i] = (val >> 8) & 0xff; + ee->ee_ctl[i + 1] = val & 0xff; + } + + /* + * Get values for 802.11a (5GHz) + */ + mode = AR5K_EEPROM_MODE_11A; + + ee->ee_turbo_max_power[mode] = + AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); + + offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); + + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) + return ret; + + AR5K_EEPROM_READ(offset++, val); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); + ee->ee_ob[mode][3] = (val >> 5) & 0x7; + ee->ee_db[mode][3] = (val >> 2) & 0x7; + ee->ee_ob[mode][2] = (val << 1) & 0x7; + + AR5K_EEPROM_READ(offset++, val); + ee->ee_ob[mode][2] |= (val >> 15) & 0x1; + ee->ee_db[mode][2] = (val >> 12) & 0x7; + ee->ee_ob[mode][1] = (val >> 9) & 0x7; + ee->ee_db[mode][1] = (val >> 6) & 0x7; + ee->ee_ob[mode][0] = (val >> 3) & 0x7; + ee->ee_db[mode][0] = val & 0x7; + + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) + return ret; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_margin_tx_rx[mode] = val & 0x3f; + } + + /* + * Get values for 802.11b (2.4GHz) + */ + mode = AR5K_EEPROM_MODE_11B; + offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); + + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) + return ret; + + AR5K_EEPROM_READ(offset++, val); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); + ee->ee_ob[mode][1] = (val >> 4) & 0x7; + ee->ee_db[mode][1] = val & 0x7; + + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) + return ret; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][0] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ee->ee_cal_pier[mode][1] = + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][2] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + } + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; + } + + /* + * Get values for 802.11g (2.4GHz) + */ + mode = AR5K_EEPROM_MODE_11G; + offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); + + ret = ath5k_eeprom_read_ants(hal, &offset, mode); + if (ret) + return ret; + + AR5K_EEPROM_READ(offset++, val); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); + ee->ee_ob[mode][1] = (val >> 4) & 0x7; + ee->ee_db[mode][1] = val & 0x7; + + ret = ath5k_eeprom_read_modes(hal, &offset, mode); + if (ret) + return ret; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][0] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ee->ee_cal_pier[mode][1] = + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + + AR5K_EEPROM_READ(offset++, val); + ee->ee_turbo_max_power[mode] = val & 0x7f; + ee->ee_xr_power[mode] = (val >> 7) & 0x3f; + + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][2] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; + } + + AR5K_EEPROM_READ(offset++, val); + ee->ee_i_cal[mode] = (val >> 8) & 0x3f; + ee->ee_q_cal[mode] = (val >> 3) & 0x1f; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_cck_ofdm_gain_delta = val & 0xff; + } + } + + /* + * Read 5GHz EEPROM channels + */ + + return 0; +} + +/* + * Read the MAC address from eeprom + */ +static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) +{ + u8 mac_d[ETH_ALEN]; + u32 total, offset; + u16 data; + int octet, ret; + + memset(mac, 0, ETH_ALEN); + memset(mac_d, 0, ETH_ALEN); + + ret = ath5k_hw_eeprom_read(hal, 0x20, &data); + if (ret) + return ret; + + for (offset = 0x1f, octet = 0, total = 0; + offset >= 0x1d; offset--) { + ret = ath5k_hw_eeprom_read(hal, offset, &data); + if (ret) + return ret; + + total += data; + mac_d[octet + 1] = data & 0xff; + mac_d[octet] = data >> 8; + octet += 2; + } + + memcpy(mac, mac_d, ETH_ALEN); + + if (!total || total == 3 * 0xffff) + return -EINVAL; + + return 0; +} + +/* + * Read/Write regulatory domain + */ +static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, + enum ieee80211_regdomain *regdomain) +{ + u16 ee_regdomain; + + /* Read current value */ + if (write != true) { + ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; + *regdomain = ath5k_regdomain_to_ieee(ee_regdomain); + return true; + } + + ee_regdomain = ath5k_regdomain_from_ieee(*regdomain); + + /* Try to write a new value */ + if (hal->ah_capabilities.cap_eeprom.ee_protect & + AR5K_EEPROM_PROTECT_WR_128_191) + return false; + if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, + ee_regdomain) != 0) + return false; + + hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; + + return true; +} + +/* + * Use the above to write a new regulatory domain + */ +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain) +{ + enum ieee80211_regdomain ieee_regdomain; + + ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); + + if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true) + return 0; + + return -EIO; +} + +/* + * Fill the capabilities struct + */ +static int ath5k_hw_get_capabilities(struct ath_hw *hal) +{ + u16 ee_header; + + AR5K_TRACE; + /* Capabilities stored in the EEPROM */ + ee_header = hal->ah_capabilities.cap_eeprom.ee_header; + + if (hal->ah_version == AR5K_AR5210) { + /* + * Set radio capabilities + * (The AR5110 only supports the middle 5GHz band) + */ + hal->ah_capabilities.cap_range.range_5ghz_min = 5120; + hal->ah_capabilities.cap_range.range_5ghz_max = 5430; + hal->ah_capabilities.cap_range.range_2ghz_min = 0; + hal->ah_capabilities.cap_range.range_2ghz_max = 0; + + /* Set supported modes */ + set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); + set_bit(MODE_ATHEROS_TURBO, hal->ah_capabilities.cap_mode); + } else { + /* + * XXX The tranceiver supports frequencies from 4920 to 6100GHz + * XXX and from 2312 to 2732GHz. There are problems with the current + * XXX ieee80211 implementation because the IEEE channel mapping + * XXX does not support negative channel numbers (2312MHz is channel + * XXX -19). Of course, this doesn't matter because these channels + * XXX are out of range but some regulation domains like MKK (Japan) + * XXX will support frequencies somewhere around 4.8GHz. + */ + + /* + * Set radio capabilities + */ + + if (AR5K_EEPROM_HDR_11A(ee_header)) { + hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ + hal->ah_capabilities.cap_range.range_5ghz_max = 6100; + + /* Set supported modes */ + set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); + set_bit(MODE_ATHEROS_TURBO, + hal->ah_capabilities.cap_mode); + if (hal->ah_version == AR5K_AR5212) + set_bit(MODE_ATHEROS_TURBOG, + hal->ah_capabilities.cap_mode); + } + + /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ + if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { + hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ + hal->ah_capabilities.cap_range.range_2ghz_max = 2732; + + if (AR5K_EEPROM_HDR_11B(ee_header)) + set_bit(MODE_IEEE80211B, + hal->ah_capabilities.cap_mode); + + if (AR5K_EEPROM_HDR_11G(ee_header)) + set_bit(MODE_IEEE80211G, + hal->ah_capabilities.cap_mode); + } + } + + /* GPIO */ + hal->ah_gpio_npins = AR5K_NUM_GPIO; + + /* Set number of supported TX queues */ + if (hal->ah_version == AR5K_AR5210) + hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU; + else + hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; + + return 0; +} + +/*********************************\ + Protocol Control Unit Functions +\*********************************/ + +/* + * Set Operation mode + */ +void +ath5k_hw_set_opmode(struct ath_hw *hal) +{ + u32 pcu_reg, beacon_reg, low_id, high_id; + + pcu_reg = 0; + beacon_reg = 0; + + AR5K_TRACE; + + switch (hal->ah_op_mode) { + case IEEE80211_IF_TYPE_IBSS: + pcu_reg |= AR5K_STA_ID1_ADHOC | + AR5K_STA_ID1_DESC_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); + + beacon_reg |= AR5K_BCR_ADHOC; + break; + + case IEEE80211_IF_TYPE_AP: + pcu_reg |= AR5K_STA_ID1_AP | + AR5K_STA_ID1_RTS_DEF_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); + + beacon_reg |= AR5K_BCR_AP; + break; + + case IEEE80211_IF_TYPE_STA: + pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_PWR_SV :0); + case IEEE80211_IF_TYPE_MNTR: + pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); + break; + + default: + return; + } + + /* + * Set PCU registers + */ + low_id = AR5K_LOW_ID(hal->ah_sta_id); + high_id = AR5K_HIGH_ID(hal->ah_sta_id); + ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(hal, pcu_reg | high_id, AR5K_STA_ID1); + + /* + * Set Beacon Control Register on 5210 + */ + if (hal->ah_version == AR5K_AR5210) + ath5k_hw_reg_write(hal, beacon_reg, AR5K_BCR); +} + +/* + * BSSID Functions + */ + +/* + * Get station id + */ +void +ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) +{ + AR5K_TRACE; + memcpy(mac, hal->ah_sta_id, ETH_ALEN); +} + +/* + * Set station id + */ +bool +ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac) +{ + u32 low_id, high_id; + + AR5K_TRACE; + /* Set new station ID */ + memcpy(hal->ah_sta_id, mac, ETH_ALEN); + + low_id = AR5K_LOW_ID(mac); + high_id = AR5K_HIGH_ID(mac); + + ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(hal, high_id, AR5K_STA_ID1); + + return true; +} + +/* + * Set BSSID + */ +void +ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, + u16 assoc_id) +{ + u32 low_id, high_id; + u16 tim_offset = 0; + + /* + * Set simple BSSID mask on 5212 + */ + if (hal->ah_version == AR5K_AR5212) { + ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM1); + } + + /* + * Set BSSID which triggers the "SME Join" operation + */ + low_id = AR5K_LOW_ID(bssid); + high_id = AR5K_HIGH_ID(bssid); + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_ID0); + ath5k_hw_reg_write(hal, high_id | ((assoc_id & 0x3fff) << + AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); + memcpy(&hal->ah_bssid, bssid, ETH_ALEN); + + if (assoc_id == 0) { + ath5k_hw_disable_pspoll(hal); + return; + } + + AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM, + tim_offset ? tim_offset + 4 : 0); + + ath5k_hw_enable_pspoll(hal, NULL, 0); +} + +/* + * Set BSSID mask on 5212 + */ +bool +ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) +{ + u32 low_id, high_id; + AR5K_TRACE; + + if (hal->ah_version == AR5K_AR5212) { + + low_id = AR5K_LOW_ID(mask); + high_id = AR5K_HIGH_ID(mask); + + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); + + return true; + } else + return false; +} + +/* + * Receive start/stop functions + */ + +/* + * Start receive on PCU + */ +void +ath5k_hw_start_rx_pcu(struct ath_hw *hal) +{ + AR5K_TRACE; + AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); +} + +/* + * Stop receive on PCU + */ +void +ath5k_hw_stop_pcu_recv(struct ath_hw *hal) +{ + AR5K_TRACE; + AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); +} + +/* + * RX Filter functions + */ + +/* + * Set multicast filter + */ +void +ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, + u32 filter1) +{ + AR5K_TRACE; + /* Set the multicat filter */ + ath5k_hw_reg_write(hal, filter0, AR5K_MCAST_FILTER0); + ath5k_hw_reg_write(hal, filter1, AR5K_MCAST_FILTER1); +} + +/* + * Set multicast filter by index + */ +bool +ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) +{ + + AR5K_TRACE; + if (index >= 64) + return false; + else if (index >= 32) + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, + (1 << (index - 32))); + else + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, + (1 << index)); + + return true; +} + +/* + * Clear Multicast filter by index + */ +bool +ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) +{ + + AR5K_TRACE; + if (index >= 64) + return false; + else if (index >= 32) + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, + (1 << (index - 32))); + else + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, + (1 << index)); + + return true; +} + +/* + * Get current rx filter + */ +u32 +ath5k_hw_get_rx_filter(struct ath_hw *hal) +{ + u32 data, filter = 0; + + AR5K_TRACE; + filter = ath5k_hw_reg_read(hal, AR5K_RX_FILTER); + + /*Radar detection for 5212*/ + if (hal->ah_version == AR5K_AR5212) { + data = ath5k_hw_reg_read(hal, AR5K_PHY_ERR_FIL); + + if (data & AR5K_PHY_ERR_FIL_RADAR) + filter |= AR5K_RX_FILTER_PHYRADAR; + if (data & (AR5K_PHY_ERR_FIL_OFDM | + AR5K_PHY_ERR_FIL_CCK)) + filter |= AR5K_RX_FILTER_PHYERR; + } + + return filter; +} + +/* + * Set rx filter + */ +void +ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) +{ + u32 data = 0; + + AR5K_TRACE; + + /* Set PHY error filter register on 5212*/ + if (hal->ah_version == AR5K_AR5212) { + if (filter & AR5K_RX_FILTER_PHYRADAR) + data |= AR5K_PHY_ERR_FIL_RADAR; + if (filter & AR5K_RX_FILTER_PHYERR) + data |= AR5K_PHY_ERR_FIL_OFDM | + AR5K_PHY_ERR_FIL_CCK; + } + + /* + * The AR5210 uses promiscous mode to detect radar activity + */ + if ((hal->ah_version == AR5K_AR5210) && + (filter & AR5K_RX_FILTER_PHYRADAR)) { + filter &= ~AR5K_RX_FILTER_PHYRADAR; + filter |= AR5K_RX_FILTER_PROM; + } + + /*Zero length DMA*/ + if (data) + AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, + AR5K_RXCFG_ZLFDMA); + else + AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, + AR5K_RXCFG_ZLFDMA); + + /*Write RX Filter register*/ + ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER); + + /*Write PHY error filter register on 5212*/ + if (hal->ah_version == AR5K_AR5212) + ath5k_hw_reg_write(hal, data, AR5K_PHY_ERR_FIL); + +} + +/* + * Beacon related functions + */ + +/* + * Get a 32bit TSF + */ +u32 ath5k_hw_get_tsf32(struct ath_hw *hal) +{ + AR5K_TRACE; + return ath5k_hw_reg_read(hal, AR5K_TSF_L32); +} + +/* + * Get the full 64bit TSF + */ +u64 ath5k_hw_get_tsf64(struct ath_hw *hal) +{ + u64 tsf = ath5k_hw_reg_read(hal, AR5K_TSF_U32); + AR5K_TRACE; + + return ath5k_hw_reg_read(hal, AR5K_TSF_L32) | (tsf << 32); +} + +/* + * Force a TSF reset + */ +void ath5k_hw_reset_tsf(struct ath_hw *hal) +{ + AR5K_TRACE; + AR5K_REG_ENABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_RESET_TSF); +} + +/* + * Initialize beacon timers + */ +void +ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, + u32 interval) +{ + u32 timer1, timer2, timer3; + + AR5K_TRACE; + /* + * Set the additional timers by mode + */ + switch (hal->ah_op_mode) { + case IEEE80211_IF_TYPE_STA: + if (hal->ah_version == AR5K_AR5210) { + timer1 = 0xffffffff; + timer2 = 0xffffffff; + } else { + timer1 = 0x0000ffff; + timer2 = 0x0007ffff; + } + break; + + default: + timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << + 0x00000003; + timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << + 0x00000003; + } + + timer3 = next_beacon + + (hal->ah_atim_window ? hal->ah_atim_window : 1); + + /* + * Set the beacon register and enable all timers. + * (next beacon, DMA beacon, software beacon, ATIM window time) + */ + ath5k_hw_reg_write(hal, next_beacon, AR5K_TIMER0); + ath5k_hw_reg_write(hal, timer1, AR5K_TIMER1); + ath5k_hw_reg_write(hal, timer2, AR5K_TIMER2); + ath5k_hw_reg_write(hal, timer3, AR5K_TIMER3); + + ath5k_hw_reg_write(hal, interval & (AR5K_BEACON_PERIOD | + AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE), + AR5K_BEACON); +} + +/* + * Set beacon timers + */ +void +ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state) +{ + u32 cfp_period, next_cfp, dtim, interval, next_beacon; + + /* + * TODO: should be changed through *state + * review struct ath5k_beacon_state struct + * + * XXX: These are used for cfp period bellow, are they + * ok ? Is it O.K. for tsf here to be 0 or should we use + * get_tsf ? + */ + u32 dtim_count = 0; /* XXX */ + u32 cfp_count = 0; /* XXX */ + u32 tsf = 0; /* XXX */ + + AR5K_TRACE; + /* Return on an invalid beacon state */ + if (state->bs_interval < 1) + return; + + interval = state->bs_interval; + dtim = state->bs_dtim_period; + + /* + * PCF support? + */ + if (state->bs_cfp_period > 0) { + /* + * Enable PCF mode and set the CFP + * (Contention Free Period) and timer registers + */ + cfp_period = state->bs_cfp_period * state->bs_dtim_period * + state->bs_interval; + next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * + state->bs_interval; + + AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, + AR5K_STA_ID1_DEFAULT_ANTENNA | + AR5K_STA_ID1_PCF); + ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD); + ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR); + ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period : + next_cfp)) << 3, AR5K_TIMER2); + } else { + /* Disable PCF mode */ + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, + AR5K_STA_ID1_DEFAULT_ANTENNA | + AR5K_STA_ID1_PCF); + } + + /* + * Enable the beacon timer register + */ + ath5k_hw_reg_write(hal, state->bs_next_beacon, AR5K_TIMER0); + + /* + * Start the beacon timers + */ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_BEACON) &~ + (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | + AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, + AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, + AR5K_BEACON_PERIOD), AR5K_BEACON); + + /* + * Write new beacon miss threshold, if it appears to be valid + * XXX: Figure out right values for min <= bs_bmiss_threshold <= max + * and return if its not in range. We can test this by reading value and + * setting value to a largest value and seeing which values register. + */ + + AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, + AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); + + /* + * Set sleep control register + * XXX: Didn't find this in 5210 code but since this register + * exists also in ar5k's 5210 headers i leave it as common code. + */ + AR5K_REG_WRITE_BITS(hal, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, + (state->bs_sleep_duration - 3) << 3); + + /* + * Set enhanced sleep registers on 5212 + */ + if (hal->ah_version == AR5K_AR5212) { + if ((state->bs_sleep_duration > state->bs_interval) && + (roundup(state->bs_sleep_duration, interval) == + state->bs_sleep_duration)) + interval = state->bs_sleep_duration; + + if (state->bs_sleep_duration > dtim && + (dtim == 0 || roundup(state->bs_sleep_duration, dtim) == + state->bs_sleep_duration)) + dtim = state->bs_sleep_duration; + + if (interval > dtim) + return; + + next_beacon = interval == dtim ? + state->bs_next_dtim: state->bs_next_beacon; + + ath5k_hw_reg_write(hal, + AR5K_REG_SM((state->bs_next_dtim - 3) << 3, + AR5K_SLEEP0_NEXT_DTIM) | + AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | + AR5K_SLEEP0_ENH_SLEEP_EN | + AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); + + ath5k_hw_reg_write(hal, AR5K_REG_SM((next_beacon - 3) << 3, + AR5K_SLEEP1_NEXT_TIM) | + AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); + + ath5k_hw_reg_write(hal, + AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | + AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); + } +} + +/* + * Reset beacon timers + */ +void +ath5k_hw_reset_beacon(struct ath_hw *hal) +{ + AR5K_TRACE; + /* + * Disable beacon timer + */ + ath5k_hw_reg_write(hal, 0, AR5K_TIMER0); + + /* + * Disable some beacon register values + */ + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, + AR5K_STA_ID1_DEFAULT_ANTENNA | + AR5K_STA_ID1_PCF); + ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON); +} + +/* + * Wait for beacon queue to finish + * TODO: This function's name is misleading, rename + */ +bool +ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) +{ + bool ret; + int i; + + AR5K_TRACE; + + /* 5210 doesn't have QCU*/ + if (hal->ah_version == AR5K_AR5210) { + /* + * Wait for beaconn queue to finish by checking + * Control Register and Beacon Status Register. + */ + for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && + (ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && + (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); + + /* Timeout... */ + if (i <= 0) { + /* + * Re-schedule the beacon queue + */ + ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR); + + return false; + } + ret= true; + + } else { + /*5211/5212*/ + ret = ath5k_hw_register_timeout(hal, + AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), + AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true; + + if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) + return false; + } + + return ret; +} + +/* + * Update mib counters (statistics) + */ +void +ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics) +{ + AR5K_TRACE; + /* Read-And-Clear */ + statistics->ackrcv_bad += ath5k_hw_reg_read(hal, AR5K_ACK_FAIL); + statistics->rts_bad += ath5k_hw_reg_read(hal, AR5K_RTS_FAIL); + statistics->rts_good += ath5k_hw_reg_read(hal, AR5K_RTS_OK); + statistics->fcs_bad += ath5k_hw_reg_read(hal, AR5K_FCS_FAIL); + statistics->beacons += ath5k_hw_reg_read(hal, AR5K_BEACON_CNT); + + /* Reset profile count registers on 5212*/ + if (hal->ah_version == AR5K_AR5212) { + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_TX); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RX); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RXCLR); + ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_CYCLE); + } +} + +/* + * ACK/CTS Timeouts + */ + +/* + * Set ACK timeout on PCU + */ +bool +ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) +{ + AR5K_TRACE; + if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), + hal->ah_turbo) <= timeout) + return false; + + AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, + ath5k_hw_htoclock(timeout, hal->ah_turbo)); + + return true; +} + +/* + * Read the ACK timeout from PCU + */ +unsigned int +ath5k_hw_get_ack_timeout(struct ath_hw *hal) +{ + AR5K_TRACE; + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), + AR5K_TIME_OUT_ACK), hal->ah_turbo)); +} + +/* + * Set CTS timeout on PCU + */ +bool +ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) +{ + AR5K_TRACE; + if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), + hal->ah_turbo) <= timeout) + return false; + + AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, + ath5k_hw_htoclock(timeout, hal->ah_turbo)); + + return true; +} + +/* + * Read CTS timeout from PCU + */ +unsigned int +ath5k_hw_get_cts_timeout(struct ath_hw *hal) +{ + AR5K_TRACE; + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), + AR5K_TIME_OUT_CTS), hal->ah_turbo)); +} + +/* + * Key table (WEP) functions + */ + +int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) +{ + unsigned int i; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) + ath5k_hw_reg_write(hal, 0, AR5K_KEYTABLE_OFF(entry, i)); + + /* Set NULL encryption on non-5210*/ + if (hal->ah_version != AR5K_AR5210) + ath5k_hw_reg_write(hal, AR5K_KEYTABLE_TYPE_NULL, + AR5K_KEYTABLE_TYPE(entry)); + + return 0; +} + +int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + /* Check the validation flag at the end of the entry */ + return ath5k_hw_reg_read(hal, AR5K_KEYTABLE_MAC1(entry)) & + AR5K_KEYTABLE_VALID; +} + +int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, + const struct ieee80211_key_conf *key, const u8 *mac) +{ + unsigned int i; + u32 key_v[AR5K_KEYCACHE_SIZE - 2] = {}; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + switch (key->keylen) { + case 40 / 8: + memcpy(&key_v[0], key->key, 4); + memcpy(&key_v[1], key->key + 4, 1); + key_v[5] = AR5K_KEYTABLE_TYPE_40; + break; + + case 104 / 8: + memcpy(&key_v[0], key->key, 4); + memcpy(&key_v[1], key->key + 4, 2); + memcpy(&key_v[2], key->key + 6, 4); + memcpy(&key_v[3], key->key + 10, 2); + memcpy(&key_v[4], key->key + 12, 1); + key_v[5] = AR5K_KEYTABLE_TYPE_104; + break; + + case 128 / 8: + memcpy(&key_v[0], key->key, 4); + memcpy(&key_v[1], key->key + 4, 2); + memcpy(&key_v[2], key->key + 6, 4); + memcpy(&key_v[3], key->key + 10, 2); + memcpy(&key_v[4], key->key + 12, 4); + key_v[5] = AR5K_KEYTABLE_TYPE_128; + break; + + default: + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(key_v); i++) + ath5k_hw_reg_write(hal, key_v[i], AR5K_KEYTABLE_OFF(entry, i)); + + return ath5k_hw_set_key_lladdr(hal, entry, mac); +} + +int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) +{ + u32 low_id, high_id; + + AR5K_TRACE; + /* Invalid entry (key table overflow) */ + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + /* MAC may be NULL if it's a broadcast key. In this case no need to + * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ + if (unlikely(mac == NULL)) { + low_id = 0xffffffff; + high_id = 0xffff | AR5K_KEYTABLE_VALID; + } else { + low_id = AR5K_LOW_ID(mac); + high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID; + } + + ath5k_hw_reg_write(hal, low_id, AR5K_KEYTABLE_MAC0(entry)); + ath5k_hw_reg_write(hal, high_id, AR5K_KEYTABLE_MAC1(entry)); + + return 0; +} + + +/********************************************\ +Queue Control Unit, DFS Control Unit Functions +\********************************************/ + +/* + * Initialize a transmit queue + */ +int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, + struct ath5k_txq_info *queue_info) +{ + unsigned int queue; + int ret; + + AR5K_TRACE; + + /* + * Get queue by type + */ + /*5210 only has 2 queues*/ + if (hal->ah_version == AR5K_AR5210) { + switch (queue_type) { + case AR5K_TX_QUEUE_DATA: + queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; + break; + default: + return -EINVAL; + } + } else { + switch (queue_type) { + case AR5K_TX_QUEUE_DATA: + for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; + hal->ah_txq[queue].tqi_type != + AR5K_TX_QUEUE_INACTIVE; queue++) { + + if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) + return -EINVAL; + } + break; + case AR5K_TX_QUEUE_UAPSD: + queue = AR5K_TX_QUEUE_ID_UAPSD; + break; + case AR5K_TX_QUEUE_BEACON: + queue = AR5K_TX_QUEUE_ID_BEACON; + break; + case AR5K_TX_QUEUE_CAB: + queue = AR5K_TX_QUEUE_ID_CAB; + break; + case AR5K_TX_QUEUE_XR_DATA: + if (hal->ah_version != AR5K_AR5212) + AR5K_PRINTF("XR data queues only " + "supported in 5212!"); + queue = AR5K_TX_QUEUE_ID_XR_DATA; + break; + default: + return -EINVAL; + } + } + + /* + * Setup internal queue structure + */ + memset(&hal->ah_txq[queue], 0, sizeof(struct ath5k_txq_info)); + hal->ah_txq[queue].tqi_type = queue_type; + + if (queue_info != NULL) { + queue_info->tqi_type = queue_type; + ret = ath5k_hw_setup_tx_queueprops(hal, queue, queue_info); + if (ret) + return ret; + } + /* + * We use ah_txq_interrupts to hold a temp value for + * the Secondary interrupt mask registers on 5211+ + * check out ath5k_hw_reset_tx_queue + */ + AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); + + return queue; +} + +/* + * Setup a transmit queue + */ +int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, + const struct ath5k_txq_info *queue_info) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return -EIO; + + memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); + + /*XXX: Is this supported on 5210 ?*/ + if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && + ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || + (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || + queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) + hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; + + return 0; +} + +/* + * Get properties for a specific transmit queue + */ +bool +ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info) +{ + AR5K_TRACE; + memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); + return true; +} + +/* + * Set a transmit queue inactive + */ +void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) +{ + AR5K_TRACE; + if (queue >= hal->ah_capabilities.cap_queues.q_tx_num) { + WARN_ON(1); + return; + } + + /* This queue will be skipped in further operations */ + hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; + /*For SIMR setup*/ + AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); +} + +/* + * Set DFS params for a transmit queue + */ +bool +ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) +{ + u32 cw_min, cw_max, retry_lg, retry_sh; + struct ath5k_txq_info *tq = &hal->ah_txq[queue]; + int i; + struct ath5k_ar5210_ini_mode ar5210_mode[] = + AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs); + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + tq = &hal->ah_txq[queue]; + + if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) + return true; + + if (hal->ah_version == AR5K_AR5210) { + /* Only handle data queues, others will be ignored */ + if (tq->tqi_type != AR5K_TX_QUEUE_DATA) + return true; + + /* + * Write initial mode register settings + */ + for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++) + ath5k_hw_reg_write(hal, hal->ah_turbo == true ? + ar5210_mode[i].mode_turbo : + ar5210_mode[i].mode_base, + (u32)ar5210_mode[i].mode_register); + } + + /* + * Calculate cwmin/max by channel mode + */ + cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; + cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; + hal->ah_aifs = AR5K_TUNE_AIFS; + /*XR is only supported on 5212*/ + if (IS_CHAN_XR(hal->ah_current_channel) + && (hal->ah_version == AR5K_AR5212)) { + cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; + cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; + hal->ah_aifs = AR5K_TUNE_AIFS_XR; + /*B mode is not supported on 5210*/ + } else if (IS_CHAN_B(hal->ah_current_channel) + && (hal->ah_version != AR5K_AR5210)) { + cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; + cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; + hal->ah_aifs = AR5K_TUNE_AIFS_11B; + } + + cw_min = 1; + while (cw_min < hal->ah_cw_min) + cw_min = (cw_min << 1) | 1; + + cw_min = tq->tqi_cw_min < 0 ? + (cw_min >> (-tq->tqi_cw_min)) : + ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); + cw_max = tq->tqi_cw_max < 0 ? + (cw_max >> (-tq->tqi_cw_max)) : + ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); + + /* + * Calculate and set retry limits + */ + if (hal->ah_software_retry == true) { + /* XXX Need to test this */ + retry_lg = hal->ah_limit_tx_retries; + retry_sh = retry_lg = + retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? + AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; + } else { + retry_lg = AR5K_INIT_LG_RETRY; + retry_sh = AR5K_INIT_SH_RETRY; + } + + /*No QCU/DCU [5210]*/ + if (hal->ah_version == AR5K_AR5210) { + ath5k_hw_reg_write(hal, + (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) + | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, + AR5K_NODCU_RETRY_LMT_SLG_RETRY) + | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, + AR5K_NODCU_RETRY_LMT_SSH_RETRY) + | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) + | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), + AR5K_NODCU_RETRY_LMT); + } else { + /*QCU/DCU [5211+]*/ + ath5k_hw_reg_write(hal, + AR5K_REG_SM(AR5K_INIT_SLG_RETRY, + AR5K_DCU_RETRY_LMT_SLG_RETRY) | + AR5K_REG_SM(AR5K_INIT_SSH_RETRY, + AR5K_DCU_RETRY_LMT_SSH_RETRY) | + AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | + AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), + AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); + + /*===Rest is also for QCU/DCU only [5211+]===*/ + + /* + * Set initial content window (cw_min/cw_max) + * and arbitrated interframe space (aifs)... + */ + ath5k_hw_reg_write(hal, + AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | + AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | + AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, + AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue)); + + /* + * Set misc registers + */ + ath5k_hw_reg_write(hal, AR5K_QCU_MISC_DCU_EARLY, + AR5K_QUEUE_MISC(queue)); + + if (tq->tqi_cbr_period) { + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_cbr_period, + AR5K_QCU_CBRCFG_INTVAL) | + AR5K_REG_SM(tq->tqi_cbr_overflow_limit, + AR5K_QCU_CBRCFG_ORN_THRES), + AR5K_QUEUE_CBRCFG(queue)); + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_CBR); + if (tq->tqi_cbr_overflow_limit) + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_CBR_THRES_ENABLE); + } + + if (tq->tqi_ready_time) { + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time, + AR5K_QCU_RDYTIMECFG_INTVAL) | + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); + } + + if (tq->tqi_burst_time) { + ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time, + AR5K_DCU_CHAN_TIME_DUR) | + AR5K_DCU_CHAN_TIME_ENABLE, + AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_TXE); + } + } + + if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { + ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, + AR5K_QUEUE_DFS_MISC(queue)); + } + + if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { + ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG, + AR5K_QUEUE_DFS_MISC(queue)); + } + + /* + * Set registers by queue type + */ + switch (tq->tqi_type) { + case AR5K_TX_QUEUE_BEACON: + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_DBA_GT | + AR5K_QCU_MISC_CBREXP_BCN | + AR5K_QCU_MISC_BCN_ENABLE); + + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), + (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << + AR5K_DCU_MISC_ARBLOCK_CTL_S) | + AR5K_DCU_MISC_POST_FR_BKOFF_DIS | + AR5K_DCU_MISC_BCN_ENABLE); + + ath5k_hw_reg_write(hal, + ((AR5K_TUNE_BEACON_INTERVAL - + (AR5K_TUNE_SW_BEACON_RESP - + AR5K_TUNE_DMA_BEACON_RESP) - + AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); + break; + + case AR5K_TX_QUEUE_CAB: + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_DBA_GT | + AR5K_QCU_MISC_CBREXP | + AR5K_QCU_MISC_CBREXP_BCN); + + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), + (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << + AR5K_DCU_MISC_ARBLOCK_CTL_S)); + break; + + case AR5K_TX_QUEUE_UAPSD: + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_CBREXP); + break; + + case AR5K_TX_QUEUE_DATA: + default: + break; + } + + /* + * Enable tx queue in the secondary interrupt mask registers + */ + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR0_QCU_TXOK) | + AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, + AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); + } + + return true; +} + +/* + * Get number of pending frames + * for a specific queue [5211+] + */ +u32 +ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) { + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* Return if queue is declared inactive */ + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return false; + + /* XXX: How about AR5K_CFG_TXCNT ? */ + if (hal->ah_version == AR5K_AR5210) + return false; + + return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT; +} + +/* + * Set slot time + */ +bool +ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time) +{ + AR5K_TRACE; + if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) + return false; + + if (hal->ah_version == AR5K_AR5210) + ath5k_hw_reg_write(hal, ath5k_hw_htoclock(slot_time, + hal->ah_turbo), AR5K_SLOT_TIME); + else + ath5k_hw_reg_write(hal, slot_time, AR5K_DCU_GBL_IFS_SLOT); + + return true; +} + +/* + * Get slot time + */ +unsigned int +ath5k_hw_get_slot_time(struct ath_hw *hal) +{ + AR5K_TRACE; + if (hal->ah_version == AR5K_AR5210) + return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) & + 0xffff, hal->ah_turbo)); + else + return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff; +} + + +/******************************\ + Hardware Descriptor Functions +\******************************/ + +/* + * TX Descriptor + */ + +/* + * Initialize the 2-word tx descriptor on 5210/5211 + */ +static int +ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, + unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, + unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, + unsigned int key_index, unsigned int antenna_mode, unsigned int flags, + unsigned int rtscts_rate, unsigned int rtscts_duration) +{ + u32 frame_type; + struct ath5k_hw_2w_tx_desc *tx_desc; + + tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; + + if (tx_tries0 == 0) + return -EINVAL; + + /* Initialize control descriptor */ + tx_desc->tx_control_0 = 0; + tx_desc->tx_control_1 = 0; + + /* Setup control descriptor */ + + /*Verify packet length*/ + tx_desc->tx_control_0 = pkt_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; + if (tx_desc->tx_control_0 != pkt_len) + return -EINVAL; + /* + * Verify header length + * XXX: I only found that on 5210 code, does it work on 5211 ? + */ + if (hal->ah_version == AR5K_AR5210) { + tx_desc->tx_control_0 = hdr_len & AR5K_2W_TX_DESC_CTL0_HEADER_LEN; + if (tx_desc->tx_control_0 != hdr_len) + return -EINVAL; + } + + /*Diferences between 5210-5211*/ + if (hal->ah_version == AR5K_AR5210) { + switch (type) { + case AR5K_PKT_TYPE_BEACON: + case AR5K_PKT_TYPE_PROBE_RESP: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; + case AR5K_PKT_TYPE_PIFS: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; + default: + frame_type = type /*<< 2 ?*/; + } + + tx_desc->tx_control_0 = + AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE)| + AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); + } else { + tx_desc->tx_control_0 |= + AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | + AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT); + tx_desc->tx_control_1 = + AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE); + } +#define _TX_FLAGS(_c, _flag) \ + if (flags & AR5K_TXDESC_##_flag) \ + tx_desc->tx_control_##_c |= \ + AR5K_2W_TX_DESC_CTL##_c##_##_flag + + _TX_FLAGS(0, CLRDMASK); + _TX_FLAGS(0, VEOL); + _TX_FLAGS(0, INTREQ); + _TX_FLAGS(0, RTSENA); + _TX_FLAGS(1, NOACK); + +#undef _TX_FLAGS + + /* + * WEP crap + */ + if (key_index != AR5K_TXKEYIX_INVALID) { + tx_desc->tx_control_0 |= + AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; + tx_desc->tx_control_1 |= + AR5K_REG_SM(key_index, + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); + } + + /* + * RTS/CTS Duration [5210 ?] + */ + if ((hal->ah_version == AR5K_AR5210) && + (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) { + tx_desc->tx_control_1 |= + rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; + } + + return 0; +} + +/* + * Initialize the 4-word tx descriptor on 5212 + */ +static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, + struct ath_desc *desc, unsigned int pkt_len, unsigned int hdr_len, + enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, + unsigned int tx_tries0, unsigned int key_index, + unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate, + unsigned int rtscts_duration) +{ + struct ath5k_hw_4w_tx_desc *tx_desc; + + AR5K_TRACE; + + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + + /* + * Validate input + */ + if (tx_tries0 == 0) + return -EINVAL; + + /* Initialize status descriptor */ + tx_desc->tx_control_0 = 0; + tx_desc->tx_control_1 = 0; + tx_desc->tx_control_2 = 0; + tx_desc->tx_control_3 = 0; + + /* Setup status descriptor */ + tx_desc->tx_control_0 = pkt_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN; + if (tx_desc->tx_control_0 != pkt_len) + return -EINVAL; + + tx_desc->tx_control_0 |= + AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | + AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); + tx_desc->tx_control_1 = AR5K_REG_SM(type, + AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); + tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); + tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; + +#define _TX_FLAGS(_c, _flag) \ + if (flags & AR5K_TXDESC_##_flag) \ + tx_desc->tx_control_##_c |= \ + AR5K_4W_TX_DESC_CTL##_c##_##_flag + + _TX_FLAGS(0, CLRDMASK); + _TX_FLAGS(0, VEOL); + _TX_FLAGS(0, INTREQ); + _TX_FLAGS(0, RTSENA); + _TX_FLAGS(0, CTSENA); + _TX_FLAGS(1, NOACK); + +#undef _TX_FLAGS + + /* + * WEP crap + */ + if (key_index != AR5K_TXKEYIX_INVALID) { + tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; + tx_desc->tx_control_1 |= AR5K_REG_SM(key_index, + AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); + } + + /* + * RTS/CTS + */ + if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { + if ((flags & AR5K_TXDESC_RTSENA) &&(flags & AR5K_TXDESC_CTSENA)) + return -EINVAL; + tx_desc->tx_control_2 |= rtscts_duration & + AR5K_4W_TX_DESC_CTL2_RTS_DURATION; + tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate, + AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); + } + + return 0; +} + +/* + * Initialize a 4-word XR tx descriptor on 5212 + */ +static bool +ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, + unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, + unsigned int tx_rate3, u_int tx_tries3) +{ + struct ath5k_hw_4w_tx_desc *tx_desc; + + if (hal->ah_version == AR5K_AR5212) { + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + +#define _XTX_TRIES(_n) \ + if (tx_tries##_n) { \ + tx_desc->tx_control_2 |= \ + AR5K_REG_SM(tx_tries##_n, \ + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \ + tx_desc->tx_control_3 |= \ + AR5K_REG_SM(tx_rate##_n, \ + AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \ + } + + _XTX_TRIES(1); + _XTX_TRIES(2); + _XTX_TRIES(3); + +#undef _XTX_TRIES + + return true; + } + + return(false); +} + +/* + * Fill the 2-word tx descriptor on 5210/5211 + */ +static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, + struct ath_desc *desc, unsigned int segment_length, + bool first_segment, bool last_segment) +{ + struct ath5k_hw_2w_tx_desc *tx_desc; + + tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; + + /* Clear status descriptor */ + memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); + + /* Validate segment length and initialize the descriptor */ + tx_desc->tx_control_1 = segment_length & AR5K_2W_TX_DESC_CTL1_BUF_LEN; + if (tx_desc->tx_control_1 != segment_length) + return -EINVAL; + + if (first_segment != true) + tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN; + + if (last_segment != true) + tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE; + + return 0; +} + +/* + * Fill the 4-word tx descriptor on 5212 + * XXX: Added an argument *last_desc -need revision + */ +static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, + struct ath_desc *desc, unsigned int segment_length, + bool first_segment, bool last_segment) +{ + struct ath5k_hw_4w_tx_desc *tx_desc; + struct ath5k_hw_tx_status *tx_status; + + AR5K_TRACE; + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; + + /* Clear status descriptor */ + memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status)); + + /* Validate segment length and initialize the descriptor */ + tx_desc->tx_control_1 = segment_length & AR5K_4W_TX_DESC_CTL1_BUF_LEN; + if (tx_desc->tx_control_1 != segment_length) + return -EINVAL; + + if (first_segment != true) + tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN; + + if (last_segment != true) + tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE; + + return 0; +} + +/* + * Proccess the tx status descriptor on 5210/5211 + */ +static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, + struct ath_desc *desc) +{ + struct ath5k_hw_tx_status *tx_status; + struct ath5k_hw_2w_tx_desc *tx_desc; + + tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0]; + + /* No frame has been send or error */ + if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) + return -EINPROGRESS; + + /* + * Get descriptor status + */ + desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); + desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); + /*TODO: desc->ds_us.tx.ts_virtcol + test*/ + desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + desc->ds_us.tx.ts_antenna = 1; + desc->ds_us.tx.ts_status = 0; + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0, + AR5K_2W_TX_DESC_CTL0_XMIT_RATE); + + if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; + } + + return 0; +} + +/* + * Proccess a tx descriptor on 5212 + */ +static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, + struct ath_desc *desc) +{ + struct ath5k_hw_tx_status *tx_status; + struct ath5k_hw_4w_tx_desc *tx_desc; + + AR5K_TRACE; + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; + + /* No frame has been send or error */ + if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) + return -EINPROGRESS; + + /* + * Get descriptor status + */ + desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); + desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); + desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & + AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; + desc->ds_us.tx.ts_status = 0; + + switch (AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { + case 0: + desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & + AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; + break; + case 1: + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); + desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); + break; + case 2: + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); + desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); + break; + case 3: + desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); + desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); + break; + } + + if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; + } + + return 0; +} + +/* + * RX Descriptor + */ + +/* + * Initialize an rx descriptor + */ +int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, + u32 size, unsigned int flags) +{ + struct ath5k_rx_desc *rx_desc; + + AR5K_TRACE; + rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0; + + /* + *Clear ds_hw + * If we don't clean the status descriptor, + * while scanning we get too many results, + * most of them virtual, after some secs + * of scanning system hangs. M.F. + */ + memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); + + /*Initialize rx descriptor*/ + rx_desc->rx_control_0 = 0; + rx_desc->rx_control_1 = 0; + + /* Setup descriptor */ + rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; + if (rx_desc->rx_control_1 != size) + return -EINVAL; + + if (flags & AR5K_RXDESC_INTREQ) + rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; + + return 0; +} + +/* + * Proccess the rx status descriptor on 5210/5211 + */ +static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, + struct ath_desc *desc) +{ + struct ath5k_hw_old_rx_status *rx_status; + + rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0]; + + /* No frame received / not ready */ + if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) + return -EINPROGRESS; + + /* + * Frame receive status + */ + desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & + AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; + desc->ds_us.rx.rs_rssi = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); + desc->ds_us.rx.rs_rate = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); + desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; + desc->ds_us.rx.rs_more = rx_status->rx_status_0 & + AR5K_OLD_RX_DESC_STATUS0_MORE; + desc->ds_us.rx.rs_tstamp = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); + desc->ds_us.rx.rs_status = 0; + + /* + * Key table status + */ + if (rx_status->rx_status_1 & + AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) + desc->ds_us.rx.rs_keyix = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); + else + desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; + + /* + * Receive/descriptor errors + */ + if ((rx_status->rx_status_1 & + AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { + if (rx_status->rx_status_1 & + AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; + + if (rx_status->rx_status_1 & + AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN) + desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; + + if (rx_status->rx_status_1 & + AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) { + desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; + desc->ds_us.rx.rs_phyerr = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR); + } + + if (rx_status->rx_status_1 & + AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; + } + + return 0; +} + +/* + * Proccess the rx status descriptor on 5212 + */ +static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, + struct ath_desc *desc) +{ + struct ath5k_hw_new_rx_status *rx_status; + struct ath5k_hw_rx_error *rx_err; + + AR5K_TRACE; + rx_status = (struct ath5k_hw_new_rx_status*)&desc->ds_hw[0]; + + /* Overlay on error */ + rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0]; + + /* No frame received / not ready */ + if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) + return -EINPROGRESS; + + /* + * Frame receive status + */ + desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & + AR5K_NEW_RX_DESC_STATUS0_DATA_LEN; + desc->ds_us.rx.rs_rssi = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); + desc->ds_us.rx.rs_rate = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); + desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA; + desc->ds_us.rx.rs_more = rx_status->rx_status_0 & + AR5K_NEW_RX_DESC_STATUS0_MORE; + desc->ds_us.rx.rs_tstamp = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); + desc->ds_us.rx.rs_status = 0; + + /* + * Key table status + */ + if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID) + desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, + AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX); + else + desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; + + /* + * Receive/descriptor errors + */ + if ((rx_status->rx_status_1 & + AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { + if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; + + if (rx_status->rx_status_1 &AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR){ + desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; + desc->ds_us.rx.rs_phyerr = + AR5K_REG_MS(rx_err->rx_error_1, + AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE); + } + + if (rx_status->rx_status_1 & + AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; + + if (rx_status->rx_status_1 & + AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; + } + + return 0; +} + + + + +/****************\ + GPIO Functions +\****************/ + +/* + * Set led state + */ +void +ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) +{ + u32 led; + /*5210 has different led mode handling*/ + u32 led_5210; + + AR5K_TRACE; + + /*Reset led status*/ + if (hal->ah_version != AR5K_AR5210) + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, + AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); + else + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, + AR5K_PCICFG_LED); + + /* + * Some blinking values, define at your wish + */ + switch (state) { + case AR5K_LED_SCAN: + case AR5K_LED_AUTH: + led = AR5K_PCICFG_LEDMODE_PROP | + AR5K_PCICFG_LED_PEND; + led_5210 = AR5K_PCICFG_LED_PEND| + AR5K_PCICFG_LED_BCTL; + break; + + case AR5K_LED_INIT: + led = AR5K_PCICFG_LEDMODE_PROP | + AR5K_PCICFG_LED_NONE; + led_5210 = AR5K_PCICFG_LED_PEND; + break; + + case AR5K_LED_ASSOC: + case AR5K_LED_RUN: + led = AR5K_PCICFG_LEDMODE_PROP | + AR5K_PCICFG_LED_ASSOC; + led_5210 = AR5K_PCICFG_LED_ASSOC; + break; + + default: + led = AR5K_PCICFG_LEDMODE_PROM | + AR5K_PCICFG_LED_NONE; + led_5210 = AR5K_PCICFG_LED_PEND; + break; + } + + /*Write new status to the register*/ + if (hal->ah_version != AR5K_AR5210) + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led); + else + AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led_5210); +} + +/* + * Set GPIO outputs + */ +bool +ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) +{ + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return false; + + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ + AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); + + return true; +} + +/* + * Set GPIO inputs + */ +bool +ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) +{ + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return false; + + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ + AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); + + return true; +} + +/* + * Get GPIO state + */ +u32 +ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) +{ + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return 0xffffffff; + + /* GPIO input magic */ + return (((ath5k_hw_reg_read(hal, AR5K_GPIODI) & + AR5K_GPIODI_M) >> gpio) & 0x1); +} + +/* + * Set GPIO state + */ +bool +ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) +{ + u32 data; + AR5K_TRACE; + + if (gpio > AR5K_NUM_GPIO) + return false; + + /* GPIO output magic */ + data = ath5k_hw_reg_read(hal, AR5K_GPIODO); + + data &= ~(1 << gpio); + data |= (val&1) << gpio; + + ath5k_hw_reg_write(hal, data, AR5K_GPIODO); + + return true; +} + +/* + * Initialize the GPIO interrupt (RFKill switch) + */ +void +ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, + u32 interrupt_level) +{ + u32 data; + + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return; + + /* + * Set the GPIO interrupt + */ + data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) & + ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | + AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | + (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); + + ath5k_hw_reg_write(hal, interrupt_level ? data : + (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); + + hal->ah_imr |= AR5K_IMR_GPIO; + + /* Enable GPIO interrupts */ + AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, AR5K_IMR_GPIO); +} + + + + +/*********************************\ + Regulatory Domain/Channels Setup +\*********************************/ + +/* + * Following 2 functions come from net80211 + * TODO: These do not belong here, they have nothing + * to do with hw. I left them here temporarily for + * combatibility. + * M.F. + */ + +/* + * Convert MHz frequency to IEEE channel number. + */ +unsigned int +ath_hal_mhz2ieee(unsigned int freq, u_int flags) +{ + if (flags & CHANNEL_2GHZ) { /* 2GHz band */ + if (freq == 2484) /* Japan */ + return 14; + /* don't number non-IEEE channels unless we do channel tests */ + if ((freq >= 2412) && (freq < 2484)) + return (freq - 2407) / 5; + if (CHAN_DEBUG == 1) /* 15-26 */ + return ((freq - 2512)/20) + 15; + return 0; + } else if (flags & CHANNEL_5GHZ) { /* 5Ghz band */ + /* don't number non-IEEE channels unless we do channel tests */ + if (((freq >= 5150) && (freq <= 5825))|| CHAN_DEBUG == 1) + return (freq - 5000) / 5; + return 0; + } else + /* something is fishy, don't do anything */ + return 0; +} + +/* + * Check if a channel is supported + */ +bool +ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags) +{ + /* Check if the channel is in our supported range */ + if (flags & CHANNEL_2GHZ) { + if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && + (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) + return true; + } else if (flags & CHANNEL_5GHZ) + if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && + (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) + return true; + + return false; +} + +u16 +ath5k_get_regdomain(struct ath_hw *hal) +{ + u16 regdomain; + enum ieee80211_regdomain ieee_regdomain; +#ifdef COUNTRYCODE + u16 code; +#endif + + ath5k_eeprom_regulation_domain(hal, false, &ieee_regdomain); + hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; + +#ifdef COUNTRYCODE + /* + * Get the regulation domain by country code. This will ignore + * the settings found in the EEPROM. + */ + code = ieee80211_name2countrycode(COUNTRYCODE); + ieee_regdomain = ieee80211_countrycode2regdomain(code); +#endif + + regdomain = ath5k_regdomain_from_ieee(ieee_regdomain); + hal->ah_capabilities.cap_regdomain.reg_current = regdomain; + + return regdomain; +} + +/*************************\ + PHY/RF access functions +\*************************/ + +/* + * Set a channel on the radio chip + */ +bool +ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +{ + bool ret; + + /* + * Check bounds supported by the PHY + * (don't care about regulation restrictions at this point) + */ + if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) && + (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { + AR5K_PRINTF("channel out of supported range (%u MHz)\n", + channel->freq); + return false; + } + + /* + * Set the channel and wait + */ + if (hal->ah_radio == AR5K_RF5110) + ret = ath5k_hw_rf5110_channel(hal, channel); + else if (hal->ah_radio == AR5K_RF5111) + ret = ath5k_hw_rf5111_channel(hal, channel); + else + ret = ath5k_hw_rf5112_channel(hal, channel); + + if (ret == false) + return ret; + + hal->ah_current_channel.freq = channel->freq; + hal->ah_current_channel.val = channel->val; + hal->ah_turbo = channel->val == CHANNEL_T ? true : false; + + return true; +} + +/* + * Convertion needed for RF5110 + */ +u32 +ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) +{ + u32 athchan; + + /* + * Convert IEEE channel/MHz to an internal channel value used + * by the AR5210 chipset. This has not been verified with + * newer chipsets like the AR5212A who have a completely + * different RF/PHY part. + */ + athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq, + channel->val) - 24) / 2, 5) << 1) | + (1 << 6) | 0x1; + + return athchan; +} + +/* + * Set channel on RF5110 + */ +bool +ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +{ + u32 data; + + /* + * Set the channel and wait + */ + data = ath5k_hw_rf5110_chan2athchan(channel); + AR5K_PHY_WRITE(hal, 0x27, data); + AR5K_PHY_WRITE(hal, 0x30, 0); + mdelay(1); + + return true; +} + +/* + * Convertion needed for 5111 + */ +bool +ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan) +{ + int channel; + + /* Cast this value to catch negative channel numbers (>= -19) */ + channel = (int)ieee; + + /* + * Map 2GHz IEEE channel to 5GHz Atheros channel + */ + if (channel <= 13) { + athchan->a2_athchan = 115 + channel; + athchan->a2_flags = 0x46; + } else if (channel == 14) { + athchan->a2_athchan = 124; + athchan->a2_flags = 0x44; + } else if (channel >= 15 && channel <= 26) { + athchan->a2_athchan = ((channel - 14) * 4) + 132; + athchan->a2_flags = 0x46; + } else + return false; + + return true; +} + +/* + * Set channel on 5111 + */ +bool +ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +{ + unsigned int ieee_channel, ath_channel; + u32 data0, data1, clock; + struct ath5k_athchan_2ghz ath_channel_2ghz; + + /* + * Set the channel on the RF5111 radio + */ + data0 = data1 = 0; + ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, + channel->val); + + if (channel->val & CHANNEL_2GHZ) { + /* Map 2GHz channel to 5GHz Atheros channel ID */ + if (ath5k_hw_rf5111_chan2athchan(ieee_channel, + &ath_channel_2ghz) == false) + return false; + + ath_channel = ath_channel_2ghz.a2_athchan; + data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) + << 5) | (1 << 4); + } + + if (ath_channel < 145 || !(ath_channel & 1)) { + clock = 1; + data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) + | (clock << 1) | (1 << 10) | 1; + } else { + clock = 0; + data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) + | (clock << 1) | (1 << 10) | 1; + } + + AR5K_PHY_WRITE(hal, 0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); + AR5K_PHY_WRITE(hal, 0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); + + return true; +} + +/* + * Set channel on 5112 + */ +bool +ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +{ + u32 data, data0, data1, data2; + u16 c; + + data = data0 = data1 = data2 = 0; + c = channel->freq; + + /* + * Set the channel on the RF5112 or newer + */ + if (c < 4800) { + if (!((c - 2224) % 5)) { + data0 = ((2 * (c - 704)) - 3040) / 10; + data1 = 1; + } else if (!((c - 2192) % 5)) { + data0 = ((2 * (c - 672)) - 3040) / 10; + data1 = 0; + } else + return false; + + data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); + } else { + if (!(c % 20) && c >= 5120) { + data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); + data2 = ath5k_hw_bitswap(3, 2); + } else if (!(c % 10)) { + data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); + data2 = ath5k_hw_bitswap(2, 2); + } else if (!(c % 5)) { + data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); + data2 = ath5k_hw_bitswap(1, 2); + } else + return false; + } + + data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; + + AR5K_PHY_WRITE(hal, 0x27, data & 0xff); + AR5K_PHY_WRITE(hal, 0x36, (data >> 8) & 0x7f); + + return true; +} + +/* + * Perform a PHY calibration + */ +bool +ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel){ + + bool ret; + + if (hal->ah_radio == AR5K_RF5110) + ret = ath5k_hw_rf5110_calibrate(hal,channel); + else + ret = ath5k_hw_rf511x_calibrate(hal,channel); + + return ret; +} +/* + * Perform a PHY calibration on RF5110 + */ +bool +ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) +{ + bool ret = true; + u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; + unsigned int i; + +#define AGC_DISABLE { \ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, \ + AR5K_PHY_AGC_DISABLE); \ + udelay(10); \ +} + +#define AGC_ENABLE { \ + AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, \ + AR5K_PHY_AGC_DISABLE); \ +} + + /* + * Disable beacons and RX/TX queues, wait + */ + AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210, + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210); + ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); + + udelay(2300); + + /* + * Set the channel (with AGC turned off) + */ + AGC_DISABLE; + ret = ath5k_hw_channel(hal, channel); + + /* + * Activate PHY and wait + */ + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); + mdelay(1); + + AGC_ENABLE; + + if (ret == false) + return ret; + + /* + * Calibrate the radio chip + */ + + /* Remember normal state */ + phy_sig = ath5k_hw_reg_read(hal, AR5K_PHY_SIG); + phy_agc = ath5k_hw_reg_read(hal, AR5K_PHY_AGCCOARSE); + phy_sat = ath5k_hw_reg_read(hal, AR5K_PHY_ADCSAT); + + /* Update radio registers */ + ath5k_hw_reg_write(hal, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | + AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); + + ath5k_hw_reg_write(hal, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | + AR5K_PHY_AGCCOARSE_LO)) | + AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | + AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); + + ath5k_hw_reg_write(hal, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | + AR5K_PHY_ADCSAT_THR)) | + AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | + AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); + + udelay(20); + + AGC_DISABLE; + ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); + AGC_ENABLE; + + mdelay(1); + + /* + * Enable calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL); + + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL, 0, false)) { + AR5K_PRINTF("calibration timeout (%uMHz)\n", + channel->freq); + ret = false; + } + + /* Reset to normal state */ + ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG); + ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE); + ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT); + + if (ret == false) + return false; + + /* + * Enable noise floor calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF); + + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF, 0, false)) { + AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", + channel->freq); + return false; + } + + /* Wait until the noise floor is calibrated */ + for (i = 20; i > 0; i--) { + mdelay(1); + noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); + + if (AR5K_PHY_NF_RVAL(noise_floor) & + AR5K_PHY_NF_ACTIVE) + noise_floor = AR5K_PHY_NF_AVAL(noise_floor); + + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) + break; + } + + if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { + AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", + channel->freq); + return false; + } + + + /* + * Re-enable RX/TX and beacons + */ + AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW_5210, + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210); + +#undef AGC_ENABLE +#undef AGC_DISABLE + + return true; +} + +/* + * Perform a PHY calibration on RF5111/5112 + */ +bool +ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) +{ + u32 i_pwr, q_pwr; + s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; + AR5K_TRACE; + + if (hal->ah_calibration == false || + ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) + goto done; + + hal->ah_calibration = false; + + iq_corr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_CORR); + i_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_I); + q_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_Q); + i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; + q_coffd = q_pwr >> 6; + + if (i_coffd == 0 || q_coffd == 0) + goto done; + + i_coff = ((-iq_corr) / i_coffd) & 0x3f; + q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; + + /* Commit new IQ value */ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, + AR5K_PHY_IQ_CORR_ENABLE | + ((u32)q_coff) | + ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + + done: + /* Start noise floor calibration */ + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF); + + /* Request RF gain */ + if (channel->val & CHANNEL_5GHZ) { + ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txpower.txp_max, + AR5K_PHY_PAPD_PROBE_TXPOWER) | + AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); + hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; + } + + return true; +} + +bool +ath5k_hw_phy_disable(struct ath_hw *hal) +{ + AR5K_TRACE; + /*Just a try M.F.*/ + ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); + return true; +} + +void /*TODO:Boundary check*/ +ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant) +{ + AR5K_TRACE; + /*Just a try M.F.*/ + if (hal->ah_version != AR5K_AR5210) + ath5k_hw_reg_write(hal, ant, AR5K_DEFAULT_ANTENNA); +} + +unsigned int +ath5k_hw_get_def_antenna(struct ath_hw *hal) +{ + AR5K_TRACE; + /*Just a try M.F.*/ + if (hal->ah_version != AR5K_AR5210) + return ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); + + return false; /*XXX: What do we return for 5210 ?*/ +} + +unsigned int +ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, + u32 first, u32 col, bool set) +{ + u32 mask, entry, last, data, shift, position; + s32 left; + int i; + + data = 0; + + if (rf == NULL) + /* should not happen */ + return 0; + + if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { + AR5K_PRINTF("invalid values at offset %u\n", offset); + return 0; + } + + entry = ((first - 1) / 8) + offset; + position = (first - 1) % 8; + + if (set == true) + data = ath5k_hw_bitswap(reg, bits); + + for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { + last = (position + left > 8) ? 8 : position + left; + mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << + (col * 8); + + if (set == true) { + rf[entry] &= ~mask; + rf[entry] |= ((data << position) << (col * 8)) & mask; + data >>= (8 - position); + } else { + data = (((rf[entry] & mask) >> (col * 8)) >> + position) << shift; + shift += last - position; + } + + left -= 8 - position; + } + + data = set == true ? 1 : ath5k_hw_bitswap(data, bits); + + return data; +} + +u32 +ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal) +{ + u32 mix, step; + u32 *rf; + + if (hal->ah_rf_banks == NULL) + return 0; + + rf = hal->ah_rf_banks; + hal->ah_gain.g_f_corr = 0; + + if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1) + return 0; + + step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false); + mix = hal->ah_gain.g_step->gos_param[0]; + + switch (mix) { + case 3: + hal->ah_gain.g_f_corr = step * 2; + break; + case 2: + hal->ah_gain.g_f_corr = (step - 5) * 2; + break; + case 1: + hal->ah_gain.g_f_corr = step; + break; + default: + hal->ah_gain.g_f_corr = 0; + break; + } + + return hal->ah_gain.g_f_corr; +} + +bool +ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) +{ + u32 step, mix, level[4]; + u32 *rf; + + if (hal->ah_rf_banks == NULL) + return 0; + + rf = hal->ah_rf_banks; + + if (hal->ah_radio == AR5K_RF5111) { + step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], + 0, 6, 37, 0, false); + level[0] = 0; + level[1] = (step == 0x3f) ? 0x32 : step + 4; + level[2] = (step != 0x3f) ? 0x40 : level[0]; + level[3] = level[2] + 0x32; + + hal->ah_gain.g_high = level[3] - + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); + hal->ah_gain.g_low = level[0] + + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); + } else { + mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], + 0, 1, 36, 0, false); + level[0] = level[2] = 0; + + if (mix == 1) { + level[1] = level[3] = 83; + } else { + level[1] = level[3] = 107; + hal->ah_gain.g_high = 55; + } + } + + return ((hal->ah_gain.g_current >= level[0] && + hal->ah_gain.g_current <= level[1]) || + (hal->ah_gain.g_current >= level[2] && + hal->ah_gain.g_current <= level[3])); +} + +s32 +ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) +{ + int ret = 0; + const struct ath5k_gain_opt *go; + + go = hal->ah_radio == AR5K_RF5111 ? + &rf5111_gain_opt : &rf5112_gain_opt; + + hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; + + if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { + if (hal->ah_gain.g_step_idx == 0) + return -1; + for (hal->ah_gain.g_target = hal->ah_gain.g_current; + hal->ah_gain.g_target >= hal->ah_gain.g_high && + hal->ah_gain.g_step_idx > 0; + hal->ah_gain.g_step = + &go->go_step[hal->ah_gain.g_step_idx]) { + hal->ah_gain.g_target -= 2 * + (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - + hal->ah_gain.g_step->gos_gain); + } + + ret = 1; + goto done; + } + + if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { + if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) + return -2; + for (hal->ah_gain.g_target = hal->ah_gain.g_current; + hal->ah_gain.g_target <= hal->ah_gain.g_low && + hal->ah_gain.g_step_idx < (go->go_steps_count - 1); + hal->ah_gain.g_step = + &go->go_step[hal->ah_gain.g_step_idx]) { + hal->ah_gain.g_target -= 2 * + (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - + hal->ah_gain.g_step->gos_gain); + } + + ret = 2; + goto done; + } + + done: +#ifdef AR5K_DEBUG + AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", + ret, + hal->ah_gain.g_step_idx, + hal->ah_gain.g_current, + hal->ah_gain.g_target); +#endif + + return ret; +} + +/* + * Initialize RF + */ +bool +ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) +{ + ath5k_rfgain_t *func = NULL; + bool ret; + + if (hal->ah_radio == AR5K_RF5111) { + hal->ah_rf_banks_size = sizeof(rf5111_rf); + func = ath5k_hw_rf5111_rfregs; + } else if (hal->ah_radio == AR5K_RF5112) { + if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) + hal->ah_rf_banks_size = sizeof(rf5112a_rf); + else + hal->ah_rf_banks_size = sizeof(rf5112_rf); + func = ath5k_hw_rf5112_rfregs; + } else + return false; + + if (hal->ah_rf_banks == NULL) { + /* XXX do extra checks? */ + if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, + GFP_KERNEL)) == NULL) { + AR5K_PRINT("out of memory\n"); + return false; + } + } + + ret = (func)(hal, channel, mode); + + if (ret == true) + hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; + + return ret; +} + +/* + * Initialize RF5111 + */ +bool +ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); + u32 *rf; + int i, obdb = -1, bank = -1; + u32 ee_mode; + + AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); + + rf = hal->ah_rf_banks; + + /* Copy values to modify them */ + for (i = 0; i < rf_size; i++) { + if (rf5111_rf[i].rf_bank >= + AR5K_RF5111_INI_RF_MAX_BANKS) { + AR5K_PRINT("invalid bank\n"); + return false; + } + + if (bank != rf5111_rf[i].rf_bank) { + bank = rf5111_rf[i].rf_bank; + hal->ah_offset[bank] = i; + } + + rf[i] = rf5111_rf[i].rf_value[mode]; + } + + if (channel->val & CHANNEL_2GHZ) { + if (channel->val & CHANNEL_B) + ee_mode = AR5K_EEPROM_MODE_11B; + else + ee_mode = AR5K_EEPROM_MODE_11G; + obdb = 0; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], + ee->ee_ob[ee_mode][obdb], 3, 119, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], + ee->ee_ob[ee_mode][obdb], 3, 122, 0, true)) + return false; + + obdb = 1; + } else { + /* For 11a, Turbo and XR */ + ee_mode = AR5K_EEPROM_MODE_11A; + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_pwd_84, 1, 51, 3, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_pwd_90, 1, 45, 3, true)) + return false; + } + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + !ee->ee_xpd[ee_mode], 1, 95, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_x_gain[ee_mode], 4, 96, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], + ee->ee_i_gain[ee_mode], 6, 29, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], + ee->ee_xpd[ee_mode], 1, 4, 0, true)) + return false; + + /* Write RF values */ + for (i = 0; i < rf_size; i++) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register); + } + + return true; +} + +/* + * Initialize RF5112 + */ +bool +ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + unsigned int rf_size; + u32 *rf; + int i, obdb = -1, bank = -1; + u32 ee_mode; + const struct ath5k_ini_rf *rf_ini; + + AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); + + rf = hal->ah_rf_banks; + + if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { + rf_ini = rf5112a_rf; + rf_size = ARRAY_SIZE(rf5112a_rf); + } else { + rf_ini = rf5112_rf; + rf_size = ARRAY_SIZE(rf5112_rf); + } + + /* Copy values to modify them */ + for (i = 0; i < rf_size; i++) { + if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { + AR5K_PRINT("invalid bank\n"); + return false; + } + + if (bank != rf_ini[i].rf_bank) { + bank = rf_ini[i].rf_bank; + hal->ah_offset[bank] = i; + } + + rf[i] = rf_ini[i].rf_value[mode]; + } + + if (channel->val & CHANNEL_2GHZ) { + if (channel->val & CHANNEL_B) + ee_mode = AR5K_EEPROM_MODE_11B; + else + ee_mode = AR5K_EEPROM_MODE_11G; + obdb = 0; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 287, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 290, 0, true)) + return false; + } else { + /* For 11a, Turbo and XR */ + ee_mode = AR5K_EEPROM_MODE_11A; + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 282, 0, true)) + return false; + } + +#ifdef notyet + ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_x_gain[ee_mode], 2, 270, 0, true); + ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_x_gain[ee_mode], 2, 257, 0, true); +#endif + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], + ee->ee_xpd[ee_mode], 1, 302, 0, true)) + return false; + + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], + ee->ee_i_gain[ee_mode], 6, 14, 0, true)) + return false; + + /* Write RF values */ + for (i = 0; i < rf_size; i++) + ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register); + + return true; +} + +/* + * Initialize 5211 RF + * TODO: is this needed ? i mean 5211 has a 5111 RF + * doesn't ar5k_rfregs work ? + */ +void +ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, + unsigned int ee_mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)]; + u32 ob, db, obdb, xpds, xpdp, x_gain; + unsigned int i; + + memcpy(rf, ar5211_rf, sizeof(rf)); + obdb = 0; + + if (freq == AR5K_INI_RFGAIN_2GHZ && + hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { + ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3); + db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3); + rf[25].rf_value[freq] = + ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); + rf[26].rf_value[freq] = + (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | + (rf[26].rf_value[freq] & ~0xf); + } + + if (freq == AR5K_INI_RFGAIN_5GHZ) { + /* For 11a and Turbo */ + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); + } + + ob = ee->ee_ob[ee_mode][obdb]; + db = ee->ee_db[ee_mode][obdb]; + x_gain = ee->ee_x_gain[ee_mode]; + xpds = ee->ee_xpd[ee_mode]; + xpdp = !xpds; + + rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | + (((ath5k_hw_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); + rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | + ((ath5k_hw_bitswap(x_gain, 4) >> 1) & 0x7); + rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | + ((ath5k_hw_bitswap(ob, 3) << 7) & 0x80); + rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | + ((ath5k_hw_bitswap(ob, 3) >> 1) & 0x3); + rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | + ((ath5k_hw_bitswap(db, 3) << 2) & 0x1c); + rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | + ((xpds << 3) & 0x8); + + for (i = 0; i < ARRAY_SIZE(rf); i++) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, rf[i].rf_value[freq], + (u32)rf[i].rf_register); + } + + hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; +} + +bool +ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) +{ + int i; + + switch (phy) { + case AR5K_INI_PHY_5111: + case AR5K_INI_PHY_5112: + break; + default: + return false; + } + + switch (freq) { + case AR5K_INI_RFGAIN_2GHZ: + case AR5K_INI_RFGAIN_5GHZ: + break; + default: + return false; + } + + for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[phy][freq], + (u32)ath5k_rfg[i].rfg_register); + } + + return true; +} + +enum ath5k_rfgain +ath5k_hw_get_rf_gain(struct ath_hw *hal) +{ + u32 data, type; + + AR5K_TRACE; + + if (hal->ah_rf_banks == NULL || !hal->ah_gain.g_active || + hal->ah_version <= AR5K_AR5211) + return AR5K_RFGAIN_INACTIVE; + + if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) + goto done; + + data = ath5k_hw_reg_read(hal, AR5K_PHY_PAPD_PROBE); + + if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { + hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; + type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); + + if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) + hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR; + + if (hal->ah_radio == AR5K_RF5112) { + ath5k_hw_rfregs_gainf_corr(hal); + hal->ah_gain.g_current = + hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? + (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : + 0; + } + + if (ath5k_hw_rfregs_gain_readback(hal) && + AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && + ath5k_hw_rfregs_gain_adjust(hal)) + hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE; + } + + done: + return hal->ah_rf_gain; +} + +/* + * TX power setup + */ + +/* + * Initialize the tx power table (not fully implemented) + */ +static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power) +{ + u16 txpower, *rates; + unsigned int i, min, max, n; + + rates = hal->ah_txpower.txp_rates; + + txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; + if (max_power > txpower) + txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? + AR5K_TUNE_MAX_TXPOWER : max_power; + + for (i = 0; i < AR5K_MAX_RATES; i++) + rates[i] = txpower; + + /* XXX setup target powers by rate */ + + hal->ah_txpower.txp_min = rates[7]; + hal->ah_txpower.txp_max = rates[0]; + hal->ah_txpower.txp_ofdm = rates[0]; + + /* Calculate the power table */ + n = ARRAY_SIZE(hal->ah_txpower.txp_pcdac); + min = AR5K_EEPROM_PCDAC_START; + max = AR5K_EEPROM_PCDAC_STOP; + for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) + hal->ah_txpower.txp_pcdac[i] = +#ifdef notyet + min + ((i * (max - min)) / n); +#else + min; +#endif +} + +/* + * Set transmition power + */ +static int /*O.K. - txpower_table is unimplemented so this doesn't work*/ +ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower) +{ + bool tpc = hal->ah_txpower.txp_tpc; + unsigned int i; + + AR5K_TRACE; + if (txpower > AR5K_TUNE_MAX_TXPOWER) { + AR5K_PRINTF("invalid tx power: %u\n", txpower); + return -EINVAL; + } + + /* Reset TX power values */ + memset(&hal->ah_txpower, 0, sizeof(hal->ah_txpower)); + hal->ah_txpower.txp_tpc = tpc; + + /* Initialize TX power table */ + ath5k_txpower_table(hal, channel, txpower); + + /* + * Write TX power values + */ + for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { + ath5k_hw_reg_write(hal, + ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) + | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ), + AR5K_PHY_PCDAC_TXPOWER(i)); + } + + ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(3, 24) | + AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | + AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); + + ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(7, 24) | + AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | + AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); + + ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(10, 24) | + AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | + AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); + + ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(14, 24) | + AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | + AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); + + if (hal->ah_txpower.txp_tpc == true) { + ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); + } else { + ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); + } + + return 0; +} + +int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) +{ + /*Just a try M.F.*/ + struct ieee80211_channel *channel = &hal->ah_current_channel; + + AR5K_TRACE; +#ifdef AR5K_DEBUG + AR5K_PRINTF("changing txpower to %d\n",power); +#endif + return ath5k_hw_txpower(hal, channel, power); +} + + + + +/****************\ + Misc functions +\****************/ + +void /*O.K.*/ +ath5k_hw_dump_state(struct ath_hw *hal) +{ +#ifdef AR5K_DEBUG +#define AR5K_PRINT_REGISTER(_x) \ + AR5K_PRINTF("(%s: %08x) ", #_x, ath5k_hw_reg_read(hal, AR5K_##_x)); + + AR5K_PRINT("MAC registers:\n"); + AR5K_PRINT_REGISTER(CR); + AR5K_PRINT_REGISTER(CFG); + AR5K_PRINT_REGISTER(IER); + AR5K_PRINT_REGISTER(TXCFG); + AR5K_PRINT_REGISTER(RXCFG); + AR5K_PRINT_REGISTER(MIBC); + AR5K_PRINT_REGISTER(TOPS); + AR5K_PRINT_REGISTER(RXNOFRM); + AR5K_PRINT_REGISTER(RPGTO); + AR5K_PRINT_REGISTER(RFCNT); + AR5K_PRINT_REGISTER(MISC); + AR5K_PRINT_REGISTER(PISR); + AR5K_PRINT_REGISTER(SISR0); + AR5K_PRINT_REGISTER(SISR1); + AR5K_PRINT_REGISTER(SISR3); + AR5K_PRINT_REGISTER(SISR4); + AR5K_PRINT_REGISTER(DCM_ADDR); + AR5K_PRINT_REGISTER(DCM_DATA); + AR5K_PRINT_REGISTER(DCCFG); + AR5K_PRINT_REGISTER(CCFG); + AR5K_PRINT_REGISTER(CCFG_CUP); + AR5K_PRINT_REGISTER(CPC0); + AR5K_PRINT_REGISTER(CPC1); + AR5K_PRINT_REGISTER(CPC2); + AR5K_PRINT_REGISTER(CPCORN); + AR5K_PRINT_REGISTER(QCU_TXE); + AR5K_PRINT_REGISTER(QCU_TXD); + AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); + AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); + AR5K_PRINT_REGISTER(DCU_FP); + AR5K_PRINT_REGISTER(DCU_TXP); + AR5K_PRINT_REGISTER(DCU_TX_FILTER); + AR5K_PRINT_REGISTER(RC); + AR5K_PRINT_REGISTER(SCR); + AR5K_PRINT_REGISTER(INTPEND); + AR5K_PRINT_REGISTER(PCICFG); + AR5K_PRINT_REGISTER(GPIOCR); + AR5K_PRINT_REGISTER(GPIODO); + AR5K_PRINT_REGISTER(SREV); + AR5K_PRINT_REGISTER(EEPROM_BASE); + AR5K_PRINT_REGISTER(EEPROM_DATA); + AR5K_PRINT_REGISTER(EEPROM_CMD); + AR5K_PRINT_REGISTER(EEPROM_CFG); + AR5K_PRINT_REGISTER(PCU_MIN); + AR5K_PRINT_REGISTER(STA_ID0); + AR5K_PRINT_REGISTER(STA_ID1); + AR5K_PRINT_REGISTER(BSS_ID0); + AR5K_PRINT_REGISTER(SLOT_TIME); + AR5K_PRINT_REGISTER(TIME_OUT); + AR5K_PRINT_REGISTER(RSSI_THR); + AR5K_PRINT_REGISTER(BEACON); + AR5K_PRINT_REGISTER(CFP_PERIOD); + AR5K_PRINT_REGISTER(TIMER0); + AR5K_PRINT_REGISTER(TIMER2); + AR5K_PRINT_REGISTER(TIMER3); + AR5K_PRINT_REGISTER(CFP_DUR); + AR5K_PRINT_REGISTER(MCAST_FILTER0); + AR5K_PRINT_REGISTER(MCAST_FILTER1); + AR5K_PRINT_REGISTER(DIAG_SW); + AR5K_PRINT_REGISTER(TSF_U32); + AR5K_PRINT_REGISTER(ADDAC_TEST); + AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); + AR5K_PRINT_REGISTER(LAST_TSTP); + AR5K_PRINT_REGISTER(NAV); + AR5K_PRINT_REGISTER(RTS_OK); + AR5K_PRINT_REGISTER(ACK_FAIL); + AR5K_PRINT_REGISTER(FCS_FAIL); + AR5K_PRINT_REGISTER(BEACON_CNT); + AR5K_PRINT_REGISTER(TSF_PARM); + AR5K_PRINT_REGISTER(RATE_DUR_0); + AR5K_PRINT_REGISTER(KEYTABLE_0); + AR5K_PRINT("\n"); + + AR5K_PRINT("PHY registers:\n"); + AR5K_PRINT_REGISTER(PHY_TURBO); + AR5K_PRINT_REGISTER(PHY_AGC); + AR5K_PRINT_REGISTER(PHY_TIMING_3); + AR5K_PRINT_REGISTER(PHY_CHIP_ID); + AR5K_PRINT_REGISTER(PHY_AGCCTL); + AR5K_PRINT_REGISTER(PHY_NF); + AR5K_PRINT_REGISTER(PHY_SCR); + AR5K_PRINT_REGISTER(PHY_SLMT); + AR5K_PRINT_REGISTER(PHY_SCAL); + AR5K_PRINT_REGISTER(PHY_RX_DELAY); + AR5K_PRINT_REGISTER(PHY_IQ); + AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); + AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1); + AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2); + AR5K_PRINT_REGISTER(PHY_FC); + AR5K_PRINT_REGISTER(PHY_RADAR); + AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); + AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); + AR5K_PRINT("\n"); +#endif +} + +int ath5k_hw_get_capability(struct ath_hw *hal, + enum ath5k_capability_type cap_type, + u32 capability, u32 *result) +{ + AR5K_TRACE; + + switch (cap_type) { + case AR5K_CAP_REG_DMN: + if (result){ + *result = ath5k_get_regdomain(hal); + goto yes; + } + case AR5K_CAP_NUM_TXQUEUES: + if (result) { + if (hal->ah_version == AR5K_AR5210) + *result = AR5K_NUM_TX_QUEUES_NOQCU; + else + *result = AR5K_NUM_TX_QUEUES; + goto yes; + } + case AR5K_CAP_VEOL: + goto yes; + case AR5K_CAP_COMPRESSION: + if (hal->ah_version == AR5K_AR5212) + goto yes; + else + goto no; + case AR5K_CAP_BURST: + goto yes; + case AR5K_CAP_TPC: + goto yes; + case AR5K_CAP_BSSIDMASK: + if (hal->ah_version == AR5K_AR5212) + goto yes; + else + goto no; + case AR5K_CAP_XR: + if (hal->ah_version == AR5K_AR5212) + goto yes; + else + goto no; + default: + goto no; + } + + no: + return -EINVAL; + yes: + return 0; + +} + +int ath5k_hw_set_capability(struct ath_hw *hal, + enum ath5k_capability_type cap_type, + u32 capability, u32 setting) +{ + AR5K_TRACE; + + return 0; +} + +bool +ath5k_hw_query_pspoll_support(struct ath_hw *hal) +{ + AR5K_TRACE; + if (hal->ah_version == AR5K_AR5210) + return(true); + + return false; +} + +bool +ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, + u16 assoc_id) +{ + AR5K_TRACE; + if (hal->ah_version == AR5K_AR5210) { + AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, + AR5K_STA_ID1_NO_PSPOLL | + AR5K_STA_ID1_DEFAULT_ANTENNA); + return true; + } + + return false; +} + +bool +ath5k_hw_disable_pspoll(struct ath_hw *hal) +{ + AR5K_TRACE; + if (hal->ah_version == AR5K_AR5210) { + AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, + AR5K_STA_ID1_NO_PSPOLL | + AR5K_STA_ID1_DEFAULT_ANTENNA); + return true; + } + + return false; +} diff --git a/ath5k_hw.h b/ath5k_hw.h new file mode 100644 index 0000000..92ff4cf --- /dev/null +++ b/ath5k_hw.h @@ -0,0 +1,2216 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + +/* + * Gain settings + */ + +enum ath5k_rfgain { + AR5K_RFGAIN_INACTIVE = 0, + AR5K_RFGAIN_READ_REQUESTED, + AR5K_RFGAIN_NEED_CHANGE, +}; + +#define AR5K_GAIN_CRN_FIX_BITS_5111 4 +#define AR5K_GAIN_CRN_FIX_BITS_5112 7 +#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 +#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 +#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 +#define AR5K_GAIN_CCK_PROBE_CORR 5 +#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 +#define AR5K_GAIN_STEP_COUNT 10 +#define AR5K_GAIN_PARAM_TX_CLIP 0 +#define AR5K_GAIN_PARAM_PD_90 1 +#define AR5K_GAIN_PARAM_PD_84 2 +#define AR5K_GAIN_PARAM_GAIN_SEL 3 +#define AR5K_GAIN_PARAM_MIX_ORN 0 +#define AR5K_GAIN_PARAM_PD_138 1 +#define AR5K_GAIN_PARAM_PD_137 2 +#define AR5K_GAIN_PARAM_PD_136 3 +#define AR5K_GAIN_PARAM_PD_132 4 +#define AR5K_GAIN_PARAM_PD_131 5 +#define AR5K_GAIN_PARAM_PD_130 6 +#define AR5K_GAIN_CHECK_ADJUST(_g) \ + ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) + +struct ath5k_gain_opt_step { + int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; + int32_t gos_gain; +}; + +struct ath5k_gain_opt { + u32 go_default; + u32 go_steps_count; + const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; +}; + +struct ath5k_gain { + u32 g_step_idx; + u32 g_current; + u32 g_target; + u32 g_low; + u32 g_high; + u32 g_f_corr; + u32 g_active; + const struct ath5k_gain_opt_step *g_step; +}; + +/* + * Gain optimization tables... + */ +#define AR5K_RF5111_GAIN_OPT { \ + 4, \ + 9, \ + { \ + { { 4, 1, 1, 1 }, 6 }, \ + { { 4, 0, 1, 1 }, 4 }, \ + { { 3, 1, 1, 1 }, 3 }, \ + { { 4, 0, 0, 1 }, 1 }, \ + { { 4, 1, 1, 0 }, 0 }, \ + { { 4, 0, 1, 0 }, -2 }, \ + { { 3, 1, 1, 0 }, -3 }, \ + { { 4, 0, 0, 0 }, -4 }, \ + { { 2, 1, 1, 0 }, -6 } \ + } \ +} + +#define AR5K_RF5112_GAIN_OPT { \ + 1, \ + 8, \ + { \ + { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \ + { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \ + { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \ + { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \ + { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \ + { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \ + { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \ + { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \ + } \ +} + +/* Some EEPROM defines */ +#define AR5K_EEPROM_EEP_SCALE 100 +#define AR5K_EEPROM_EEP_DELTA 10 +#define AR5K_EEPROM_N_MODES 3 +#define AR5K_EEPROM_N_5GHZ_CHAN 10 +#define AR5K_EEPROM_N_2GHZ_CHAN 3 +#define AR5K_EEPROM_MAX_CHAN 10 +#define AR5K_EEPROM_N_PCDAC 11 +#define AR5K_EEPROM_N_TEST_FREQ 8 +#define AR5K_EEPROM_N_EDGES 8 +#define AR5K_EEPROM_N_INTERCEPTS 11 +#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) +#define AR5K_EEPROM_PCDAC_M 0x3f +#define AR5K_EEPROM_PCDAC_START 1 +#define AR5K_EEPROM_PCDAC_STOP 63 +#define AR5K_EEPROM_PCDAC_STEP 1 +#define AR5K_EEPROM_NON_EDGE_M 0x40 +#define AR5K_EEPROM_CHANNEL_POWER 8 +#define AR5K_EEPROM_N_OBDB 4 +#define AR5K_EEPROM_OBDB_DIS 0xffff +#define AR5K_EEPROM_CHANNEL_DIS 0xff +#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) +#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) +#define AR5K_EEPROM_MAX_CTLS 32 +#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 +#define AR5K_EEPROM_N_XPD0_POINTS 4 +#define AR5K_EEPROM_N_XPD3_POINTS 3 +#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 +#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 +#define AR5K_EEPROM_POWER_M 0x3f +#define AR5K_EEPROM_POWER_MIN 0 +#define AR5K_EEPROM_POWER_MAX 3150 +#define AR5K_EEPROM_POWER_STEP 50 +#define AR5K_EEPROM_POWER_TABLE_SIZE 64 +#define AR5K_EEPROM_N_POWER_LOC_11B 4 +#define AR5K_EEPROM_N_POWER_LOC_11G 6 +#define AR5K_EEPROM_I_GAIN 10 +#define AR5K_EEPROM_CCK_OFDM_DELTA 15 +#define AR5K_EEPROM_N_IQ_CAL 2 + +struct ath5k_eeprom_info { + u16 ee_magic; + u16 ee_protect; + u16 ee_regdomain; + u16 ee_version; + u16 ee_header; + u16 ee_ant_gain; + u16 ee_misc0; + u16 ee_misc1; + u16 ee_cck_ofdm_gain_delta; + u16 ee_cck_ofdm_power_delta; + u16 ee_scaled_cck_delta; + u16 ee_tx_clip; + u16 ee_pwd_84; + u16 ee_pwd_90; + u16 ee_gain_select; + + u16 ee_i_cal[AR5K_EEPROM_N_MODES]; + u16 ee_q_cal[AR5K_EEPROM_N_MODES]; + u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; + u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; + u16 ee_xr_power[AR5K_EEPROM_N_MODES]; + u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; + u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; + u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; + u16 ee_thr_62[AR5K_EEPROM_N_MODES]; + u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; + u16 ee_xpd[AR5K_EEPROM_N_MODES]; + u16 ee_x_gain[AR5K_EEPROM_N_MODES]; + u16 ee_i_gain[AR5K_EEPROM_N_MODES]; + u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_false_detect[AR5K_EEPROM_N_MODES]; + u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; + u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; + + u16 ee_ctls; + u16 ee_ctl[AR5K_EEPROM_MAX_CTLS]; + + int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; + int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; + int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; +}; + +/* + * AR5k register access + */ + +/*Swap RX/TX Descriptor for big endian archs*/ +#if defined(__BIG_ENDIAN) +#define AR5K_INIT_CFG ( \ + AR5K_CFG_SWTD | AR5K_CFG_SWRD \ +) +#else +#define AR5K_INIT_CFG 0x00000000 +#endif + +/*#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg) + +#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg)*/ + +#define AR5K_REG_SM(_val, _flags) \ + (((_val) << _flags##_S) & (_flags)) + +#define AR5K_REG_MS(_val, _flags) \ + (((_val) & (_flags)) >> _flags##_S) + +/* Some registers can hold multiple values of interest. For this + * reason when we want to write to these registers we must first + * retrieve the values which we do not want to clear (lets call this + * old_data) and then set the register with this and our new_value: + * ( old_data | new_value) */ +#define AR5K_REG_WRITE_BITS(hal, _reg, _flags, _val) \ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & ~(_flags)) | \ + (((_val) << _flags##_S) & (_flags)), _reg) + +#define AR5K_REG_MASKED_BITS(hal, _reg, _flags, _mask) \ + ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & \ + (_mask)) | (_flags), _reg) + +#define AR5K_REG_ENABLE_BITS(hal, _reg, _flags) \ + ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) | (_flags), _reg) + +#define AR5K_REG_DISABLE_BITS(hal, _reg, _flags) \ + ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) & ~(_flags), _reg) + +#define AR5K_PHY_WRITE(hal, _reg, _val) \ + ath5k_hw_reg_write(hal, _val, (hal)->ah_phy + ((_reg) << 2)) + +#define AR5K_PHY_READ(hal, _reg) \ + ath5k_hw_reg_read(hal, (hal)->ah_phy + ((_reg) << 2)) + +#define AR5K_REG_WAIT(_i) \ + if (_i % 64) \ + udelay(1); + +#define AR5K_EEPROM_READ(_o, _v) { \ + if ((ret = ath5k_hw_eeprom_read(hal, (_o), &(_v))) != 0) \ + return (ret); \ +} + +#define AR5K_EEPROM_READ_HDR(_o, _v) \ + AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ + +/* Read status of selected queue */ +#define AR5K_REG_READ_Q(hal, _reg, _queue) \ + (ath5k_hw_reg_read(hal, _reg) & (1 << _queue)) \ + +#define AR5K_REG_WRITE_Q(hal, _reg, _queue) \ + ath5k_hw_reg_write(hal, (1 << _queue), _reg) + +#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ + _reg |= 1 << _queue; \ +} while (0) + +#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ + _reg &= ~(1 << _queue); \ +} while (0) + +/* + * Unaligned little endian access + */ +#define AR5K_LE_READ_2 ath5k_hw_read_unaligned_16 +#define AR5K_LE_READ_4 ath5k_hw_read_unaligned_32 +#define AR5K_LE_WRITE_2 ath5k_hw_write_unaligned_16 +#define AR5K_LE_WRITE_4 ath5k_hw_write_unaligned_32 + +#define AR5K_LOW_ID(_a)( \ +(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ +) + +#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) + +/* + * Initial register values + */ + +/* + * Common initial register values + */ +#define AR5K_INIT_MODE CHANNEL_B + +#define AR5K_INIT_TX_LATENCY 502 +#define AR5K_INIT_USEC 39 +#define AR5K_INIT_USEC_TURBO 79 +#define AR5K_INIT_USEC_32 31 +#define AR5K_INIT_CARR_SENSE_EN 1 +#define AR5K_INIT_PROG_IFS 920 +#define AR5K_INIT_PROG_IFS_TURBO 960 +#define AR5K_INIT_EIFS 3440 +#define AR5K_INIT_EIFS_TURBO 6880 +#define AR5K_INIT_SLOT_TIME 396 +#define AR5K_INIT_SLOT_TIME_TURBO 480 +#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 +#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 +#define AR5K_INIT_SIFS 560 +#define AR5K_INIT_SIFS_TURBO 480 +#define AR5K_INIT_SH_RETRY 10 +#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY +#define AR5K_INIT_SSH_RETRY 32 +#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY +#define AR5K_INIT_TX_RETRY 10 +#define AR5K_INIT_TOPS 8 +#define AR5K_INIT_RXNOFRM 8 +#define AR5K_INIT_RPGTO 0 +#define AR5K_INIT_TXNOFRM 0 +#define AR5K_INIT_BEACON_PERIOD 65535 +#define AR5K_INIT_TIM_OFFSET 0 +#define AR5K_INIT_BEACON_EN 0 +#define AR5K_INIT_RESET_TSF 0 + +#define AR5K_INIT_TRANSMIT_LATENCY ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC) \ +) +#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC_TURBO) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ + (AR5K_INIT_PROG_IFS) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ + (AR5K_INIT_PROG_IFS_TURBO) \ +) +#define AR5K_INIT_BEACON_CONTROL ( \ + (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ + (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ +) + +/* + * Non - common initial register values + */ + +#define AR5K_INI_VAL_11A 0 +#define AR5K_INI_VAL_11A_TURBO 1 +#define AR5K_INI_VAL_11B 2 +#define AR5K_INI_VAL_11G 3 +#define AR5K_INI_VAL_11G_TURBO 4 +#define AR5K_INI_VAL_XR 0 +#define AR5K_INI_VAL_MAX 5 + +#define AR5K_INI_PHY_5111 0 +#define AR5K_INI_PHY_5112 1 +#define AR5K_INI_PHY_511X 1 + +#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS +#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS + +struct ath5k_ini_rf { + u8 rf_bank; + u16 rf_register; + u32 rf_value[5]; +}; + +#define AR5K_RF5111_INI_RF { \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ + { 0, 0x989c, \ + { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ + { 0, 0x98d4, \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d4, \ + { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ + { 3, 0x98d8, \ + { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ + { 6, 0x989c, \ + { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ + { 6, 0x989c, \ + { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ + { 6, 0x989c, \ + { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ + { 6, 0x989c, \ + { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ + { 6, 0x989c, \ + { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ + { 6, 0x98d4, \ + { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ + { 7, 0x989c, \ + { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ + { 7, 0x989c, \ + { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ + { 7, 0x989c, \ + { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ + { 7, 0x989c, \ + { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ + { 7, 0x989c, \ + { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ + { 7, 0x989c, \ + { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ + { 7, 0x989c, \ + { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ + { 7, 0x98cc, \ + { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ +} + +#define AR5K_RF5112_INI_RF { \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ + { 6, 0x989c, \ + { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ + { 6, 0x989c, \ + { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ + { 6, 0x989c, \ + { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ + { 6, 0x989c, \ + { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ + { 6, 0x989c, \ + { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ + { 6, 0x989c, \ + { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ + { 6, 0x989c, \ + { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ + { 6, 0x989c, \ + { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ + { 6, 0x989c, \ + { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ + { 6, 0x989c, \ + { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ + { 6, 0x989c, \ + { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ + { 6, 0x989c, \ + { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ + { 6, 0x989c, \ + { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ + { 6, 0x989c, \ + { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ + { 6, 0x98d0, \ + { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ + { 7, 0x989c, \ + { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ + } + +#define AR5K_RF5112A_INI_RF { \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ + { 6, 0x989c, \ + { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ + { 6, 0x989c, \ + { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ + { 6, 0x989c, \ + { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ + { 6, 0x989c, \ + { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ + { 6, 0x989c, \ + { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ + { 6, 0x989c, \ + { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ + { 6, 0x989c, \ + { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ + { 6, 0x989c, \ + { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ + { 6, 0x989c, \ + { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ + { 6, 0x989c, \ + { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ + { 6, 0x989c, \ + { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ + { 6, 0x989c, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ + { 6, 0x989c, \ + { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ + { 6, 0x989c, \ + { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ + { 6, 0x989c, \ + { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ + { 6, 0x989c, \ + { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ + { 6, 0x98d8, \ + { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ + { 7, 0x989c, \ + { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ +} + +struct ath5k_ini_rfgain { + u16 rfg_register; + u32 rfg_value[2][2]; + +#define AR5K_INI_RFGAIN_5GHZ 0 +#define AR5K_INI_RFGAIN_2GHZ 1 +}; + +#define AR5K_INI_RFGAIN { \ + { 0x9a00, { \ + { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ + { 0x9a04, { \ + { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ + { 0x9a08, { \ + { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ + { 0x9a0c, { \ + { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ + { 0x9a10, { \ + { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ + { 0x9a14, { \ + { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ + { 0x9a18, { \ + { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ + { 0x9a1c, { \ + { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ + { 0x9a20, { \ + { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ + { 0x9a24, { \ + { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ + { 0x9a28, { \ + { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ + { 0x9a2c, { \ + { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ + { 0x9a30, { \ + { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ + { 0x9a34, { \ + { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ + { 0x9a38, { \ + { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ + { 0x9a3c, { \ + { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ + { 0x9a40, { \ + { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ + { 0x9a44, { \ + { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ + { 0x9a48, { \ + { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ + { 0x9a4c, { \ + { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ + { 0x9a50, { \ + { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ + { 0x9a54, { \ + { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ + { 0x9a58, { \ + { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ + { 0x9a5c, { \ + { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ + { 0x9a60, { \ + { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ + { 0x9a64, { \ + { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ + { 0x9a68, { \ + { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ + { 0x9a6c, { \ + { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ + { 0x9a70, { \ + { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ + { 0x9a74, { \ + { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ + { 0x9a78, { \ + { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ + { 0x9a7c, { \ + { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ + { 0x9a80, { \ + { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ + { 0x9a84, { \ + { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ + { 0x9a88, { \ + { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ + { 0x9a8c, { \ + { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ + { 0x9a90, { \ + { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ + { 0x9a94, { \ + { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ + { 0x9a98, { \ + { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ + { 0x9a9c, { \ + { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ + { 0x9aa0, { \ + { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ + { 0x9aa4, { \ + { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ + { 0x9aa8, { \ + { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ + { 0x9aac, { \ + { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ + { 0x9ab0, { \ + { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ + { 0x9ab4, { \ + { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ + { 0x9ab8, { \ + { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ + { 0x9abc, { \ + { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ + { 0x9ac0, { \ + { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ + { 0x9ac4, { \ + { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ + { 0x9ac8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ + { 0x9acc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ + { 0x9ad0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ + { 0x9ad4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ + { 0x9ad8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9adc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9aec, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9afc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ +} + +/* + * Internal RX/TX descriptor structures + * (rX: reserved fields possibily used by future versions of the ar5k chipset) + */ + +struct ath5k_rx_desc { + /* + * RX control word 0 + */ + u32 rx_control_0; + +#define AR5K_DESC_RX_CTL0 0x00000000 + + /* + * RX control word 1 + */ + u32 rx_control_1; + +#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff +#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 +} __packed; + +struct ath5k_hw_old_rx_status { + /* + * RX status word 0 + */ + u32 rx_status_0; + +#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 + + /* + * RX status word 1 + */ + u32 rx_status_1; + +#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 +#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 +} __packed; + +struct ath5k_hw_new_rx_status { + /* + * RX status word 0 + */ + u32 rx_status_0; + +#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 + + /* + * RX status word 1 + */ + u32 rx_status_1; + +#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 +#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010 +#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 +} __packed; + +struct ath5k_hw_rx_error { + /* + * RX error word 0 + */ + u32 rx_error_0; + +#define AR5K_RX_DESC_ERROR0 0x00000000 + + /* + * RX error word 1 + */ + u32 rx_error_1; + +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 +} __packed; + +#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 +#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 +#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 +#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 +#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 +#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 +#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 +#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 + +struct ath5k_hw_2w_tx_desc { + /* + * TX control word 0 + */ + u32 tx_control_0; + +#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 +#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 + + /* + * TX control word 1 + */ + u32 tx_control_1; + +#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ +} __packed; + +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 + +struct ath5k_hw_4w_tx_desc { + /* + * TX control word 0 + */ + u32 tx_control_0; + +#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 +#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 +#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 +#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 + + /* + * TX control word 1 + */ + u32 tx_control_1; + +#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 + + /* + * TX control word 2 + */ + u32 tx_control_2; + +#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff +#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 + + /* + * TX control word 3 + */ + u32 tx_control_3; + +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 +} __packed; + +struct ath5k_hw_tx_status { + /* + * TX status word 0 + */ + u32 tx_status_0; + +#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 +#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 +#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 +#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 +/*??? +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 +*/ +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 +/*??? +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 +*/ +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 + + /* + * TX status word 1 + */ + u32 tx_status_1; + +#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 +#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe +#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 +#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 +#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 +} __packed; + + +/* + * Initial register values which have to be loaded into the + * card at boot time and after each reset. + */ + +struct ath5k_ini { + u16 ini_register; + u32 ini_value; + + enum { + AR5K_INI_WRITE = 0, + AR5K_INI_READ = 1, + } ini_mode; +}; + +#define AR5K_AR5210_INI { \ + /* PCU and MAC registers */ \ + { AR5K_NOQCU_TXDP0, 0 }, \ + { AR5K_NOQCU_TXDP1, 0 }, \ + { AR5K_RXDP, 0 }, \ + { AR5K_CR, 0 }, \ + { AR5K_ISR, 0, AR5K_INI_READ }, \ + { AR5K_IMR, 0 }, \ + { AR5K_IER, AR5K_IER_DISABLE }, \ + { AR5K_BSR, 0, AR5K_INI_READ }, \ + { AR5K_TXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_RXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_CFG, AR5K_INIT_CFG }, \ + { AR5K_TOPS, AR5K_INIT_TOPS }, \ + { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \ + { AR5K_RPGTO, AR5K_INIT_RPGTO }, \ + { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \ + { AR5K_SFR, 0 }, \ + { AR5K_MIBC, 0 }, \ + { AR5K_MISC, 0 }, \ + { AR5K_RX_FILTER_5210, 0 }, \ + { AR5K_MCAST_FILTER0_5210, 0 }, \ + { AR5K_MCAST_FILTER1_5210, 0 }, \ + { AR5K_TX_MASK0, 0 }, \ + { AR5K_TX_MASK1, 0 }, \ + { AR5K_CLR_TMASK, 0 }, \ + { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ + { AR5K_DIAG_SW_5210, 0 }, \ + { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ + { AR5K_TSF_L32_5210, 0 }, \ + { AR5K_TIMER0_5210, 0 }, \ + { AR5K_TIMER1_5210, 0xffffffff }, \ + { AR5K_TIMER2_5210, 0xffffffff }, \ + { AR5K_TIMER3_5210, 1 }, \ + { AR5K_CFP_DUR_5210, 0 }, \ + { AR5K_CFP_PERIOD_5210, 0 }, \ + /* PHY registers */ \ + { AR5K_PHY(0), 0x00000047 }, \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0x09848ea6 }, \ + { AR5K_PHY(4), 0x3d32e000 }, \ + { AR5K_PHY(5), 0x0000076b }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \ + { AR5K_PHY(8), 0x02020200 }, \ + { AR5K_PHY(9), 0x00000e0e }, \ + { AR5K_PHY(10), 0x0a020201 }, \ + { AR5K_PHY(11), 0x00036ffc }, \ + { AR5K_PHY(12), 0x00000000 }, \ + { AR5K_PHY(13), 0x00000e0e }, \ + { AR5K_PHY(14), 0x00000007 }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x89630000 }, \ + { AR5K_PHY(17), 0x1372169c }, \ + { AR5K_PHY(18), 0x0018b633 }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(20), 0x0de8b8e0 }, \ + { AR5K_PHY(21), 0x00074859 }, \ + { AR5K_PHY(22), 0x7e80beba }, \ + { AR5K_PHY(23), 0x313a665e }, \ + { AR5K_PHY_AGCCTL, 0x00001d08 }, \ + { AR5K_PHY(25), 0x0001ce00 }, \ + { AR5K_PHY(26), 0x409a4190 }, \ + { AR5K_PHY(28), 0x0000000f }, \ + { AR5K_PHY(29), 0x00000080 }, \ + { AR5K_PHY(30), 0x00000004 }, \ + { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \ + { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000003 }, \ + /* BB gain table (64bytes) */ \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(0x01), 0x00000020 }, \ + { AR5K_BB_GAIN(0x02), 0x00000010 }, \ + { AR5K_BB_GAIN(0x03), 0x00000030 }, \ + { AR5K_BB_GAIN(0x04), 0x00000008 }, \ + { AR5K_BB_GAIN(0x05), 0x00000028 }, \ + { AR5K_BB_GAIN(0x06), 0x00000028 }, \ + { AR5K_BB_GAIN(0x07), 0x00000004 }, \ + { AR5K_BB_GAIN(0x08), 0x00000024 }, \ + { AR5K_BB_GAIN(0x09), 0x00000014 }, \ + { AR5K_BB_GAIN(0x0a), 0x00000034 }, \ + { AR5K_BB_GAIN(0x0b), 0x0000000c }, \ + { AR5K_BB_GAIN(0x0c), 0x0000002c }, \ + { AR5K_BB_GAIN(0x0d), 0x00000002 }, \ + { AR5K_BB_GAIN(0x0e), 0x00000022 }, \ + { AR5K_BB_GAIN(0x0f), 0x00000012 }, \ + { AR5K_BB_GAIN(0x10), 0x00000032 }, \ + { AR5K_BB_GAIN(0x11), 0x0000000a }, \ + { AR5K_BB_GAIN(0x12), 0x0000002a }, \ + { AR5K_BB_GAIN(0x13), 0x00000001 }, \ + { AR5K_BB_GAIN(0x14), 0x00000021 }, \ + { AR5K_BB_GAIN(0x15), 0x00000011 }, \ + { AR5K_BB_GAIN(0x16), 0x00000031 }, \ + { AR5K_BB_GAIN(0x17), 0x00000009 }, \ + { AR5K_BB_GAIN(0x18), 0x00000029 }, \ + { AR5K_BB_GAIN(0x19), 0x00000005 }, \ + { AR5K_BB_GAIN(0x1a), 0x00000025 }, \ + { AR5K_BB_GAIN(0x1b), 0x00000015 }, \ + { AR5K_BB_GAIN(0x1c), 0x00000035 }, \ + { AR5K_BB_GAIN(0x1d), 0x0000000d }, \ + { AR5K_BB_GAIN(0x1e), 0x0000002d }, \ + { AR5K_BB_GAIN(0x1f), 0x00000003 }, \ + { AR5K_BB_GAIN(0x20), 0x00000023 }, \ + { AR5K_BB_GAIN(0x21), 0x00000013 }, \ + { AR5K_BB_GAIN(0x22), 0x00000033 }, \ + { AR5K_BB_GAIN(0x23), 0x0000000b }, \ + { AR5K_BB_GAIN(0x24), 0x0000002b }, \ + { AR5K_BB_GAIN(0x25), 0x00000007 }, \ + { AR5K_BB_GAIN(0x26), 0x00000027 }, \ + { AR5K_BB_GAIN(0x27), 0x00000017 }, \ + { AR5K_BB_GAIN(0x28), 0x00000037 }, \ + { AR5K_BB_GAIN(0x29), 0x0000000f }, \ + { AR5K_BB_GAIN(0x2a), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2b), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2c), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2d), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2e), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2f), 0x0000002f }, \ + { AR5K_BB_GAIN(0x30), 0x0000002f }, \ + { AR5K_BB_GAIN(0x31), 0x0000002f }, \ + { AR5K_BB_GAIN(0x32), 0x0000002f }, \ + { AR5K_BB_GAIN(0x33), 0x0000002f }, \ + { AR5K_BB_GAIN(0x34), 0x0000002f }, \ + { AR5K_BB_GAIN(0x35), 0x0000002f }, \ + { AR5K_BB_GAIN(0x36), 0x0000002f }, \ + { AR5K_BB_GAIN(0x37), 0x0000002f }, \ + { AR5K_BB_GAIN(0x38), 0x0000002f }, \ + { AR5K_BB_GAIN(0x39), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3a), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3b), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3c), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3d), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3e), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3f), 0x0000002f }, \ + /* RF gain table (64bytes) */ \ + { AR5K_RF_GAIN(0), 0x0000001d }, \ + { AR5K_RF_GAIN(0x01), 0x0000005d }, \ + { AR5K_RF_GAIN(0x02), 0x0000009d }, \ + { AR5K_RF_GAIN(0x03), 0x000000dd }, \ + { AR5K_RF_GAIN(0x04), 0x0000011d }, \ + { AR5K_RF_GAIN(0x05), 0x00000021 }, \ + { AR5K_RF_GAIN(0x06), 0x00000061 }, \ + { AR5K_RF_GAIN(0x07), 0x000000a1 }, \ + { AR5K_RF_GAIN(0x08), 0x000000e1 }, \ + { AR5K_RF_GAIN(0x09), 0x00000031 }, \ + { AR5K_RF_GAIN(0x0a), 0x00000071 }, \ + { AR5K_RF_GAIN(0x0b), 0x000000b1 }, \ + { AR5K_RF_GAIN(0x0c), 0x0000001c }, \ + { AR5K_RF_GAIN(0x0d), 0x0000005c }, \ + { AR5K_RF_GAIN(0x0e), 0x00000029 }, \ + { AR5K_RF_GAIN(0x0f), 0x00000069 }, \ + { AR5K_RF_GAIN(0x10), 0x000000a9 }, \ + { AR5K_RF_GAIN(0x11), 0x00000020 }, \ + { AR5K_RF_GAIN(0x12), 0x00000019 }, \ + { AR5K_RF_GAIN(0x13), 0x00000059 }, \ + { AR5K_RF_GAIN(0x14), 0x00000099 }, \ + { AR5K_RF_GAIN(0x15), 0x00000030 }, \ + { AR5K_RF_GAIN(0x16), 0x00000005 }, \ + { AR5K_RF_GAIN(0x17), 0x00000025 }, \ + { AR5K_RF_GAIN(0x18), 0x00000065 }, \ + { AR5K_RF_GAIN(0x19), 0x000000a5 }, \ + { AR5K_RF_GAIN(0x1a), 0x00000028 }, \ + { AR5K_RF_GAIN(0x1b), 0x00000068 }, \ + { AR5K_RF_GAIN(0x1c), 0x0000001f }, \ + { AR5K_RF_GAIN(0x1d), 0x0000001e }, \ + { AR5K_RF_GAIN(0x1e), 0x00000018 }, \ + { AR5K_RF_GAIN(0x1f), 0x00000058 }, \ + { AR5K_RF_GAIN(0x20), 0x00000098 }, \ + { AR5K_RF_GAIN(0x21), 0x00000003 }, \ + { AR5K_RF_GAIN(0x22), 0x00000004 }, \ + { AR5K_RF_GAIN(0x23), 0x00000044 }, \ + { AR5K_RF_GAIN(0x24), 0x00000084 }, \ + { AR5K_RF_GAIN(0x25), 0x00000013 }, \ + { AR5K_RF_GAIN(0x26), 0x00000012 }, \ + { AR5K_RF_GAIN(0x27), 0x00000052 }, \ + { AR5K_RF_GAIN(0x28), 0x00000092 }, \ + { AR5K_RF_GAIN(0x29), 0x000000d2 }, \ + { AR5K_RF_GAIN(0x2a), 0x0000002b }, \ + { AR5K_RF_GAIN(0x2b), 0x0000002a }, \ + { AR5K_RF_GAIN(0x2c), 0x0000006a }, \ + { AR5K_RF_GAIN(0x2d), 0x000000aa }, \ + { AR5K_RF_GAIN(0x2e), 0x0000001b }, \ + { AR5K_RF_GAIN(0x2f), 0x0000001a }, \ + { AR5K_RF_GAIN(0x30), 0x0000005a }, \ + { AR5K_RF_GAIN(0x31), 0x0000009a }, \ + { AR5K_RF_GAIN(0x32), 0x000000da }, \ + { AR5K_RF_GAIN(0x33), 0x00000006 }, \ + { AR5K_RF_GAIN(0x34), 0x00000006 }, \ + { AR5K_RF_GAIN(0x35), 0x00000006 }, \ + { AR5K_RF_GAIN(0x36), 0x00000006 }, \ + { AR5K_RF_GAIN(0x37), 0x00000006 }, \ + { AR5K_RF_GAIN(0x38), 0x00000006 }, \ + { AR5K_RF_GAIN(0x39), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3a), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3b), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3c), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3d), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3e), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3f), 0x00000006 }, \ + /* PHY activation */ \ + { AR5K_PHY(53), 0x00000020 }, \ + { AR5K_PHY(51), 0x00000004 }, \ + { AR5K_PHY(50), 0x00060106 }, \ + { AR5K_PHY(39), 0x0000006d }, \ + { AR5K_PHY(48), 0x00000000 }, \ + { AR5K_PHY(52), 0x00000014 }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \ +} + +struct ath5k_ar5210_ini_mode{ + u16 mode_register; + u32 mode_base, mode_turbo; +}; + +#define AR5K_AR5210_INI_MODE(hal, _aifs) { \ + { AR5K_SLOT_TIME, \ + AR5K_INIT_SLOT_TIME, \ + AR5K_INIT_SLOT_TIME_TURBO }, \ + { AR5K_SLOT_TIME, \ + AR5K_INIT_ACK_CTS_TIMEOUT, \ + AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \ + { AR5K_USEC_5210, \ + AR5K_INIT_TRANSMIT_LATENCY, \ + AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \ + { AR5K_IFS0, \ + ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ + << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS, \ + ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \ + << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \ + { AR5K_IFS1, \ + AR5K_INIT_PROTO_TIME_CNTRL, \ + AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ + { AR5K_PHY(17), \ + (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x1C, \ + (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ + { AR5K_PHY_FRAME_CTL_5210, \ + AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ + AR5K_PHY_FRAME_CTL_TXURN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ + AR5K_PHY_FRAME_CTL_PARITY_ERR | \ + AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x1020, \ + AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ + AR5K_PHY_FRAME_CTL_TXURN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ + AR5K_PHY_FRAME_CTL_PARITY_ERR | \ + /*PHY_TURBO is PHY_FRAME_CTL on 5210*/ \ + AR5K_PHY_TURBO_MODE | \ + AR5K_PHY_TURBO_SHORT | \ + AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x2020 }, \ +} + +#define AR5K_AR5211_INI { \ + { 0x000c, 0x00000000 }, \ + { 0x0028, 0x84849c9c }, \ + { 0x002c, 0x7c7c7c7c }, \ + { 0x0034, 0x00000005 }, \ + { 0x0040, 0x00000000 }, \ + { 0x0044, 0x00000008 }, \ + { 0x0048, 0x00000008 }, \ + { 0x004c, 0x00000010 }, \ + { 0x0050, 0x00000000 }, \ + { 0x0054, 0x0000001f }, \ + { 0x0800, 0x00000000 }, \ + { 0x0804, 0x00000000 }, \ + { 0x0808, 0x00000000 }, \ + { 0x080c, 0x00000000 }, \ + { 0x0810, 0x00000000 }, \ + { 0x0814, 0x00000000 }, \ + { 0x0818, 0x00000000 }, \ + { 0x081c, 0x00000000 }, \ + { 0x0820, 0x00000000 }, \ + { 0x0824, 0x00000000 }, \ + { 0x1230, 0x00000000 }, \ + { 0x8004, 0x00000000 }, \ + { 0x8008, 0x00000000 }, \ + { 0x800c, 0x00000000 }, \ + { 0x8018, 0x00000000 }, \ + { 0x8024, 0x00000000 }, \ + { 0x8028, 0x00000030 }, \ + { 0x802c, 0x0007ffff }, \ + { 0x8030, 0x01ffffff }, \ + { 0x8034, 0x00000031 }, \ + { 0x8038, 0x00000000 }, \ + { 0x803c, 0x00000000 }, \ + { 0x8040, 0x00000000 }, \ + { 0x8044, 0x00000002 }, \ + { 0x8048, 0x00000000 }, \ + { 0x8054, 0x00000000 }, \ + { 0x8058, 0x00000000 }, \ + /* PHY registers */ \ + { 0x9808, 0x00000000 }, \ + { 0x980c, 0x2d849093 }, \ + { 0x9810, 0x7d32e000 }, \ + { 0x9814, 0x00000f6b }, \ + { 0x981c, 0x00000000 }, \ + { 0x982c, 0x00026ffe }, \ + { 0x9830, 0x00000000 }, \ + { 0x983c, 0x00020100 }, \ + { 0x9840, 0x206a017a }, \ + { 0x984c, 0x1284613c }, \ + { 0x9854, 0x00000859 }, \ + { 0x9868, 0x409a4190 }, \ + { 0x986c, 0x050cb081 }, \ + { 0x9870, 0x0000000f }, \ + { 0x9874, 0x00000080 }, \ + { 0x9878, 0x0000000c }, \ + { 0x9900, 0x00000000 }, \ + { 0x9904, 0x00000000 }, \ + { 0x9908, 0x00000000 }, \ + { 0x990c, 0x00800000 }, \ + { 0x9910, 0x00000001 }, \ + { 0x991c, 0x0000092a }, \ + { 0x9920, 0x00000000 }, \ + { 0x9924, 0x00058a05 }, \ + { 0x9928, 0x00000001 }, \ + { 0x992c, 0x00000000 }, \ + { 0x9930, 0x00000000 }, \ + { 0x9934, 0x00000000 }, \ + { 0x9938, 0x00000000 }, \ + { 0x993c, 0x0000003f }, \ + { 0x9940, 0x00000004 }, \ + { 0x9948, 0x00000000 }, \ + { 0x994c, 0x00000000 }, \ + { 0x9950, 0x00000000 }, \ + { 0x9954, 0x5d50f14c }, \ + { 0x9958, 0x00000018 }, \ + { 0x995c, 0x004b6a8e }, \ + { 0xa184, 0x06ff05ff }, \ + { 0xa188, 0x07ff07ff }, \ + { 0xa18c, 0x08ff08ff }, \ + { 0xa190, 0x09ff09ff }, \ + { 0xa194, 0x0aff0aff }, \ + { 0xa198, 0x0bff0bff }, \ + { 0xa19c, 0x0cff0cff }, \ + { 0xa1a0, 0x0dff0dff }, \ + { 0xa1a4, 0x0fff0eff }, \ + { 0xa1a8, 0x12ff12ff }, \ + { 0xa1ac, 0x14ff13ff }, \ + { 0xa1b0, 0x16ff15ff }, \ + { 0xa1b4, 0x19ff17ff }, \ + { 0xa1b8, 0x1bff1aff }, \ + { 0xa1bc, 0x1eff1dff }, \ + { 0xa1c0, 0x23ff20ff }, \ + { 0xa1c4, 0x27ff25ff }, \ + { 0xa1c8, 0x2cff29ff }, \ + { 0xa1cc, 0x31ff2fff }, \ + { 0xa1d0, 0x37ff34ff }, \ + { 0xa1d4, 0x3aff3aff }, \ + { 0xa1d8, 0x3aff3aff }, \ + { 0xa1dc, 0x3aff3aff }, \ + { 0xa1e0, 0x3aff3aff }, \ + { 0xa1e4, 0x3aff3aff }, \ + { 0xa1e8, 0x3aff3aff }, \ + { 0xa1ec, 0x3aff3aff }, \ + { 0xa1f0, 0x3aff3aff }, \ + { 0xa1f4, 0x3aff3aff }, \ + { 0xa1f8, 0x3aff3aff }, \ + { 0xa1fc, 0x3aff3aff }, \ + /* BB gain table (64bytes) */ \ + { 0x9b00, 0x00000000 }, \ + { 0x9b04, 0x00000020 }, \ + { 0x9b08, 0x00000010 }, \ + { 0x9b0c, 0x00000030 }, \ + { 0x9b10, 0x00000008 }, \ + { 0x9b14, 0x00000028 }, \ + { 0x9b18, 0x00000004 }, \ + { 0x9b1c, 0x00000024 }, \ + { 0x9b20, 0x00000014 }, \ + { 0x9b24, 0x00000034 }, \ + { 0x9b28, 0x0000000c }, \ + { 0x9b2c, 0x0000002c }, \ + { 0x9b30, 0x00000002 }, \ + { 0x9b34, 0x00000022 }, \ + { 0x9b38, 0x00000012 }, \ + { 0x9b3c, 0x00000032 }, \ + { 0x9b40, 0x0000000a }, \ + { 0x9b44, 0x0000002a }, \ + { 0x9b48, 0x00000006 }, \ + { 0x9b4c, 0x00000026 }, \ + { 0x9b50, 0x00000016 }, \ + { 0x9b54, 0x00000036 }, \ + { 0x9b58, 0x0000000e }, \ + { 0x9b5c, 0x0000002e }, \ + { 0x9b60, 0x00000001 }, \ + { 0x9b64, 0x00000021 }, \ + { 0x9b68, 0x00000011 }, \ + { 0x9b6c, 0x00000031 }, \ + { 0x9b70, 0x00000009 }, \ + { 0x9b74, 0x00000029 }, \ + { 0x9b78, 0x00000005 }, \ + { 0x9b7c, 0x00000025 }, \ + { 0x9b80, 0x00000015 }, \ + { 0x9b84, 0x00000035 }, \ + { 0x9b88, 0x0000000d }, \ + { 0x9b8c, 0x0000002d }, \ + { 0x9b90, 0x00000003 }, \ + { 0x9b94, 0x00000023 }, \ + { 0x9b98, 0x00000013 }, \ + { 0x9b9c, 0x00000033 }, \ + { 0x9ba0, 0x0000000b }, \ + { 0x9ba4, 0x0000002b }, \ + { 0x9ba8, 0x0000002b }, \ + { 0x9bac, 0x0000002b }, \ + { 0x9bb0, 0x0000002b }, \ + { 0x9bb4, 0x0000002b }, \ + { 0x9bb8, 0x0000002b }, \ + { 0x9bbc, 0x0000002b }, \ + { 0x9bc0, 0x0000002b }, \ + { 0x9bc4, 0x0000002b }, \ + { 0x9bc8, 0x0000002b }, \ + { 0x9bcc, 0x0000002b }, \ + { 0x9bd0, 0x0000002b }, \ + { 0x9bd4, 0x0000002b }, \ + { 0x9bd8, 0x0000002b }, \ + { 0x9bdc, 0x0000002b }, \ + { 0x9be0, 0x0000002b }, \ + { 0x9be4, 0x0000002b }, \ + { 0x9be8, 0x0000002b }, \ + { 0x9bec, 0x0000002b }, \ + { 0x9bf0, 0x0000002b }, \ + { 0x9bf4, 0x0000002b }, \ + { 0x9bf8, 0x00000002 }, \ + { 0x9bfc, 0x00000016 }, \ + /* PHY activation */ \ + { 0x98d4, 0x00000020 }, \ + { 0x98d8, 0x00601068 }, \ +} + +struct ath5k_ar5212_ini { + u8 ini_flags; + u16 ini_register; + u32 ini_value; + +#define AR5K_INI_FLAG_511X 0x00 +#define AR5K_INI_FLAG_5111 0x01 +#define AR5K_INI_FLAG_5112 0x02 +#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) +}; + +#define AR5K_AR5212_INI { \ + { AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 }, \ + { AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 }, \ + { AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 }, \ + { AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 }, \ + { AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f }, \ + { AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x081c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0820, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0824, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1230, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1270, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1038, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1078, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1138, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1178, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1238, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1278, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1338, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1378, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1438, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1478, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x14b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x14f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1538, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1578, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x15b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x15f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1638, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1678, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x16b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x16f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1738, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1778, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x17b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x17f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x103c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x107c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x113c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x117c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x123c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x127c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x133c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x137c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x143c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x147c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8004, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8008, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x800c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8018, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8020, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8024, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8028, 0x00000030 }, \ + { AR5K_INI_FLAG_BOTH, 0x802c, 0x0007ffff }, \ + { AR5K_INI_FLAG_BOTH, 0x8030, 0x01ffffff }, \ + { AR5K_INI_FLAG_BOTH, 0x8034, 0x00000031 }, \ + { AR5K_INI_FLAG_BOTH, 0x8038, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x803c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8048, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8054, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8058, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x805c, 0xffffc7ff }, \ + { AR5K_INI_FLAG_BOTH, 0x8080, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8084, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8088, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x808c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8090, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8094, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8098, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80c0, 0x2a82301a }, \ + { AR5K_INI_FLAG_BOTH, 0x80c4, 0x05dc01e0 }, \ + { AR5K_INI_FLAG_BOTH, 0x80c8, 0x1f402710 }, \ + { AR5K_INI_FLAG_BOTH, 0x80cc, 0x01f40000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80d0, 0x00001e1c }, \ + { AR5K_INI_FLAG_BOTH, 0x80d4, 0x0002aaaa }, \ + { AR5K_INI_FLAG_BOTH, 0x80d8, 0x02005555 }, \ + { AR5K_INI_FLAG_BOTH, 0x80dc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80e0, 0xffffffff }, \ + { AR5K_INI_FLAG_BOTH, 0x80e4, 0x0000ffff }, \ + { AR5K_INI_FLAG_BOTH, 0x80e8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80ec, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80f0, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80f4, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80fc, 0x00000088 }, \ + { AR5K_INI_FLAG_BOTH, 0x8700, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8704, 0x0000008c }, \ + { AR5K_INI_FLAG_BOTH, 0x8708, 0x000000e4 }, \ + { AR5K_INI_FLAG_BOTH, 0x870c, 0x000002d5 }, \ + { AR5K_INI_FLAG_BOTH, 0x8710, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8714, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8718, 0x000000a0 }, \ + { AR5K_INI_FLAG_BOTH, 0x871c, 0x000001c9 }, \ + { AR5K_INI_FLAG_BOTH, 0x8720, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8724, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8728, 0x00000030 }, \ + { AR5K_INI_FLAG_BOTH, 0x872c, 0x0000003c }, \ + { AR5K_INI_FLAG_BOTH, 0x8730, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8734, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8738, 0x00000030 }, \ + { AR5K_INI_FLAG_BOTH, 0x873c, 0x0000003c }, \ + { AR5K_INI_FLAG_BOTH, 0x8740, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8744, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8748, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x874c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8750, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8754, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8758, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x875c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8760, 0x000000d5 }, \ + { AR5K_INI_FLAG_BOTH, 0x8764, 0x000000df }, \ + { AR5K_INI_FLAG_BOTH, 0x8768, 0x00000102 }, \ + { AR5K_INI_FLAG_BOTH, 0x876c, 0x0000013a }, \ + { AR5K_INI_FLAG_BOTH, 0x8770, 0x00000075 }, \ + { AR5K_INI_FLAG_BOTH, 0x8774, 0x0000007f }, \ + { AR5K_INI_FLAG_BOTH, 0x8778, 0x000000a2 }, \ + { AR5K_INI_FLAG_BOTH, 0x877c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8100, 0x00010002 }, \ + { AR5K_INI_FLAG_BOTH, 0x8104, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x8108, 0x000000c0 }, \ + { AR5K_INI_FLAG_BOTH, 0x810c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8110, 0x00000168 }, \ + { AR5K_INI_FLAG_BOTH, 0x8114, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x87c0, 0x03020100 }, \ + { AR5K_INI_FLAG_BOTH, 0x87c4, 0x07060504 }, \ + { AR5K_INI_FLAG_BOTH, 0x87c8, 0x0b0a0908 }, \ + { AR5K_INI_FLAG_BOTH, 0x87cc, 0x0f0e0d0c }, \ + { AR5K_INI_FLAG_BOTH, 0x87d0, 0x13121110 }, \ + { AR5K_INI_FLAG_BOTH, 0x87d4, 0x17161514 }, \ + { AR5K_INI_FLAG_BOTH, 0x87d8, 0x1b1a1918 }, \ + { AR5K_INI_FLAG_BOTH, 0x87dc, 0x1f1e1d1c }, \ + { AR5K_INI_FLAG_BOTH, 0x87e0, 0x03020100 }, \ + { AR5K_INI_FLAG_BOTH, 0x87e4, 0x07060504 }, \ + { AR5K_INI_FLAG_BOTH, 0x87e8, 0x0b0a0908 }, \ + { AR5K_INI_FLAG_BOTH, 0x87ec, 0x0f0e0d0c }, \ + { AR5K_INI_FLAG_BOTH, 0x87f0, 0x13121110 }, \ + { AR5K_INI_FLAG_BOTH, 0x87f4, 0x17161514 }, \ + { AR5K_INI_FLAG_BOTH, 0x87f8, 0x1b1a1918 }, \ + { AR5K_INI_FLAG_BOTH, 0x87fc, 0x1f1e1d1c }, \ + /* PHY registers */ \ + { AR5K_INI_FLAG_BOTH, 0x9808, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x980c, 0xad848e19 }, \ + { AR5K_INI_FLAG_BOTH, 0x9810, 0x7d28e000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9814, 0x9c0a9f6b }, \ + { AR5K_INI_FLAG_BOTH, 0x981c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x982c, 0x00022ffe }, \ + { AR5K_INI_FLAG_BOTH, 0x983c, 0x00020100 }, \ + { AR5K_INI_FLAG_BOTH, 0x9840, 0x206a017a }, \ + { AR5K_INI_FLAG_BOTH, 0x984c, 0x1284613c }, \ + { AR5K_INI_FLAG_BOTH, 0x9854, 0x00000859 }, \ + { AR5K_INI_FLAG_BOTH, 0x9900, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9904, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a }, \ + { AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 }, \ + { AR5K_INI_FLAG_BOTH, 0x9934, 0x1e1f2022 }, \ + { AR5K_INI_FLAG_BOTH, 0x9938, 0x0a0b0c0d }, \ + { AR5K_INI_FLAG_BOTH, 0x993c, 0x0000003f }, \ + { AR5K_INI_FLAG_BOTH, 0x9940, 0x00000004 }, \ + { AR5K_INI_FLAG_BOTH, 0x9948, 0x9280b212 }, \ + { AR5K_INI_FLAG_BOTH, 0x9954, 0x5d50e188 }, \ + { AR5K_INI_FLAG_BOTH, 0x9958, 0x000000ff }, \ + { AR5K_INI_FLAG_BOTH, 0x995c, 0x004b6a8e }, \ + { AR5K_INI_FLAG_BOTH, 0x9968, 0x000003ce }, \ + { AR5K_INI_FLAG_BOTH, 0x9970, 0x192fb515 }, \ + { AR5K_INI_FLAG_BOTH, 0x9974, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9978, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x997c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0xa184, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa188, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa18c, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa190, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa194, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa198, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa19c, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1a0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1a4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1a8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1ac, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1b0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1b4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1b8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1bc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1c0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1c4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1c8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1cc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1d0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1d4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1d8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1dc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1e0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1e4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1e8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1ec, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1f0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 }, \ + { AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 }, \ + { AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 }, \ + { AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a }, \ + { AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 }, \ + { AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 }, \ + { AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 }, \ + { AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0xa234, 0x20202020 }, \ + { AR5K_INI_FLAG_BOTH, 0xa238, 0x20202020 }, \ + { AR5K_INI_FLAG_BOTH, 0xa23c, 0x13c889af }, \ + { AR5K_INI_FLAG_BOTH, 0xa240, 0x38490a20 }, \ + { AR5K_INI_FLAG_BOTH, 0xa244, 0x00007bb6 }, \ + { AR5K_INI_FLAG_BOTH, 0xa248, 0x0fff3ffc }, \ + { AR5K_INI_FLAG_BOTH, 0x9b00, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9b28, 0x0000000c }, \ + { AR5K_INI_FLAG_BOTH, 0x9b38, 0x00000012 }, \ + { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \ + { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \ + { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \ + /* RF5111 specific */ \ + { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \ + { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \ + { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \ + { AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a }, \ + { AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 }, \ + { AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 }, \ + { AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 }, \ + { AR5K_INI_FLAG_5111, 0x9b10, 0x00000008 }, \ + { AR5K_INI_FLAG_5111, 0x9b14, 0x00000028 }, \ + { AR5K_INI_FLAG_5111, 0x9b18, 0x00000004 }, \ + { AR5K_INI_FLAG_5111, 0x9b1c, 0x00000024 }, \ + { AR5K_INI_FLAG_5111, 0x9b20, 0x00000014 }, \ + { AR5K_INI_FLAG_5111, 0x9b24, 0x00000034 }, \ + { AR5K_INI_FLAG_5111, 0x9b2c, 0x0000002c }, \ + { AR5K_INI_FLAG_5111, 0x9b30, 0x00000002 }, \ + { AR5K_INI_FLAG_5111, 0x9b34, 0x00000022 }, \ + { AR5K_INI_FLAG_5111, 0x9b3c, 0x00000032 }, \ + { AR5K_INI_FLAG_5111, 0x9b40, 0x0000000a }, \ + { AR5K_INI_FLAG_5111, 0x9b44, 0x0000002a }, \ + { AR5K_INI_FLAG_5111, 0x9b48, 0x00000006 }, \ + { AR5K_INI_FLAG_5111, 0x9b4c, 0x00000026 }, \ + { AR5K_INI_FLAG_5111, 0x9b50, 0x00000016 }, \ + { AR5K_INI_FLAG_5111, 0x9b54, 0x00000036 }, \ + { AR5K_INI_FLAG_5111, 0x9b58, 0x0000000e }, \ + { AR5K_INI_FLAG_5111, 0x9b5c, 0x0000002e }, \ + { AR5K_INI_FLAG_5111, 0x9b60, 0x00000001 }, \ + { AR5K_INI_FLAG_5111, 0x9b68, 0x00000011 }, \ + { AR5K_INI_FLAG_5111, 0x9b6c, 0x00000031 }, \ + { AR5K_INI_FLAG_5111, 0x9b70, 0x00000009 }, \ + { AR5K_INI_FLAG_5111, 0x9b74, 0x00000029 }, \ + { AR5K_INI_FLAG_5111, 0x9b78, 0x00000005 }, \ + { AR5K_INI_FLAG_5111, 0x9b7c, 0x00000025 }, \ + { AR5K_INI_FLAG_5111, 0x9b80, 0x00000015 }, \ + { AR5K_INI_FLAG_5111, 0x9b84, 0x00000035 }, \ + { AR5K_INI_FLAG_5111, 0x9b88, 0x0000000d }, \ + { AR5K_INI_FLAG_5111, 0x9b90, 0x00000003 }, \ + { AR5K_INI_FLAG_5111, 0x9b94, 0x00000023 }, \ + { AR5K_INI_FLAG_5111, 0x9b98, 0x00000013 }, \ + { AR5K_INI_FLAG_5111, 0x9ba0, 0x0000000b }, \ + { AR5K_INI_FLAG_5111, 0x9ba4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9ba8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bac, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bb0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bb4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bb8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bbc, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bc0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bc4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bc8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bcc, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bd0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bd4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bd8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bdc, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9be0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9be4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9be8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bec, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bf0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \ + { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \ + /* RF5112 specific */ \ + { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \ + { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \ + { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \ + { AR5K_INI_FLAG_5112, 0x9b0c, 0x00000003 }, \ + { AR5K_INI_FLAG_5112, 0x9b10, 0x00000004 }, \ + { AR5K_INI_FLAG_5112, 0x9b14, 0x00000005 }, \ + { AR5K_INI_FLAG_5112, 0x9b18, 0x00000008 }, \ + { AR5K_INI_FLAG_5112, 0x9b1c, 0x00000009 }, \ + { AR5K_INI_FLAG_5112, 0x9b20, 0x0000000a }, \ + { AR5K_INI_FLAG_5112, 0x9b24, 0x0000000b }, \ + { AR5K_INI_FLAG_5112, 0x9b2c, 0x0000000d }, \ + { AR5K_INI_FLAG_5112, 0x9b30, 0x00000010 }, \ + { AR5K_INI_FLAG_5112, 0x9b34, 0x00000011 }, \ + { AR5K_INI_FLAG_5112, 0x9b3c, 0x00000013 }, \ + { AR5K_INI_FLAG_5112, 0x9b40, 0x00000014 }, \ + { AR5K_INI_FLAG_5112, 0x9b44, 0x00000015 }, \ + { AR5K_INI_FLAG_5112, 0x9b48, 0x00000018 }, \ + { AR5K_INI_FLAG_5112, 0x9b4c, 0x00000019 }, \ + { AR5K_INI_FLAG_5112, 0x9b50, 0x0000001a }, \ + { AR5K_INI_FLAG_5112, 0x9b54, 0x0000001b }, \ + { AR5K_INI_FLAG_5112, 0x9b58, 0x0000001c }, \ + { AR5K_INI_FLAG_5112, 0x9b5c, 0x0000001d }, \ + { AR5K_INI_FLAG_5112, 0x9b60, 0x00000020 }, \ + { AR5K_INI_FLAG_5112, 0x9b68, 0x00000022 }, \ + { AR5K_INI_FLAG_5112, 0x9b6c, 0x00000023 }, \ + { AR5K_INI_FLAG_5112, 0x9b70, 0x00000024 }, \ + { AR5K_INI_FLAG_5112, 0x9b74, 0x00000025 }, \ + { AR5K_INI_FLAG_5112, 0x9b78, 0x00000028 }, \ + { AR5K_INI_FLAG_5112, 0x9b7c, 0x00000029 }, \ + { AR5K_INI_FLAG_5112, 0x9b80, 0x0000002a }, \ + { AR5K_INI_FLAG_5112, 0x9b84, 0x0000002b }, \ + { AR5K_INI_FLAG_5112, 0x9b88, 0x0000002c }, \ + { AR5K_INI_FLAG_5112, 0x9b90, 0x00000030 }, \ + { AR5K_INI_FLAG_5112, 0x9b94, 0x00000031 }, \ + { AR5K_INI_FLAG_5112, 0x9b98, 0x00000032 }, \ + { AR5K_INI_FLAG_5112, 0x9ba0, 0x00000034 }, \ + { AR5K_INI_FLAG_5112, 0x9ba4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9ba8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bac, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bb0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bb4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bb8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bbc, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bc0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bc4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bc8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bcc, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bd0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bd4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bd8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bdc, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9be0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9be4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9be8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bec, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bf0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bf4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bf8, 0x00000010 }, \ + { AR5K_INI_FLAG_5112, 0x9bfc, 0x0000001a }, \ +} + +struct ath5k_ar5211_ini_mode { + u16 mode_register; + u32 mode_value[4]; +}; + +#define AR5K_AR5211_INI_MODE { \ + { 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \ + { 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, \ + { 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, \ + { 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, \ + { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, \ + { 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, \ + { 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, \ + { 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, \ + { 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, \ + { 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, \ + { 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, \ + { 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ + { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, \ + { 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, \ + { 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, \ + { 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \ + { 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, \ + { 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, \ + { 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, \ + { 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ + { 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, \ + { 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, \ + { 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, \ + { 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, \ + { 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, \ +} + +struct ath5k_ar5212_ini_mode { + u16 mode_register; + u8 mode_flags; + u32 mode_value[2][5]; +}; + +#define AR5K_AR5212_INI_MODE { \ + { 0x0030, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \ + } }, \ + { 0x1040, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1044, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1048, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x104c, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1050, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1054, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1058, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x105c, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1060, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1064, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1030, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } \ + } }, \ + { 0x1070, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } \ + } }, \ + { 0x10b0, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } \ + } }, \ + { 0x10f0, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } \ + } }, \ + { 0x8014, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } \ + } }, \ + { 0x9804, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } \ + } }, \ + { 0x9820, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } \ + } }, \ + { 0x9834, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ + } }, \ + { 0x9838, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } \ + } }, \ + { 0x9844, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 } \ + } }, \ + { 0x9850, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } \ + } }, \ + { 0x9858, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } \ + } }, \ + { 0x9860, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 } \ + } }, \ + { 0x9864, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } \ + } }, \ + { 0x9868, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } \ + } }, \ + { 0x9918, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } \ + } }, \ + { 0x9924, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } \ + } }, \ + { 0xa180, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff } \ + } }, \ + { 0xa230, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } \ + } }, \ + { 0x801c, AR5K_INI_FLAG_BOTH, { \ + { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x128d8fab, 0x09880fcf }, \ + { 0x128d93a7, 0x098813cf, 0x04e01395, 0x128d93ab, 0x098813cf } \ + } }, \ + { 0x9824, AR5K_INI_FLAG_BOTH, { \ + { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e }, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ + } }, \ + { 0x9828, AR5K_INI_FLAG_BOTH, { \ + { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 }, \ + { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } \ + } }, \ + { 0x9848, AR5K_INI_FLAG_BOTH, { \ + { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 }, \ + { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } \ + } }, \ + { 0x985c, AR5K_INI_FLAG_BOTH, { \ + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e }, \ + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } \ + } }, \ + { 0x986c, AR5K_INI_FLAG_BOTH, { \ + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 }, \ + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } \ + } }, \ + { 0x9914, AR5K_INI_FLAG_BOTH, { \ + { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 }, \ + { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } \ + } }, \ + { 0x9944, AR5K_INI_FLAG_BOTH, { \ + { 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 }, \ + { 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 } \ + } }, \ + { 0xa204, AR5K_INI_FLAG_5112, { \ + { 0, }, \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } \ + } }, \ + { 0xa208, AR5K_INI_FLAG_5112, { \ + { 0, }, \ + { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } \ + } }, \ + { 0xa20c, AR5K_INI_FLAG_5112, { \ + { 0, }, \ + { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } \ + } }, \ +} + +struct ath5k_ar5211_ini_rf { + u16 rf_register; + u32 rf_value[2]; +}; + +#define AR5K_AR5211_INI_RF { \ + { 0x0000a204, { 0x00000000, 0x00000000 } }, \ + { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \ + { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \ + { 0x0000a210, { 0x0199a003, 0x0199a003 } }, \ + { 0x0000a214, { 0x044cd610, 0x044cd610 } }, \ + { 0x0000a218, { 0x13800040, 0x13800040 } }, \ + { 0x0000a21c, { 0x1be00060, 0x1be00060 } }, \ + { 0x0000a220, { 0x0c53800a, 0x0c53800a } }, \ + { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \ + { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \ + { 0x0000a22c, { 0x00000020, 0x00000020 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00380000, 0x00380000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \ + { 0x000098d4, { 0x00000000, 0x00000004 } }, \ + \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x10000000, 0x10000000 } }, \ + { 0x0000989c, { 0x04000000, 0x04000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x0a000000 } }, \ + { 0x0000989c, { 0x00380080, 0x02380080 } }, \ + { 0x0000989c, { 0x00020006, 0x00000006 } }, \ + { 0x0000989c, { 0x00000092, 0x00000092 } }, \ + { 0x0000989c, { 0x000000a0, 0x000000a0 } }, \ + { 0x0000989c, { 0x00040007, 0x00040007 } }, \ + { 0x000098d4, { 0x0000001a, 0x0000001a } }, \ + { 0x0000989c, { 0x00000048, 0x00000048 } }, \ + { 0x0000989c, { 0x00000010, 0x00000010 } }, \ + { 0x0000989c, { 0x00000008, 0x00000008 } }, \ + { 0x0000989c, { 0x0000000f, 0x0000000f } }, \ + { 0x0000989c, { 0x000000f2, 0x00000062 } }, \ + { 0x0000989c, { 0x0000904f, 0x0000904c } }, \ + { 0x0000989c, { 0x0000125a, 0x0000129a } }, \ + { 0x000098cc, { 0x0000000e, 0x0000000f } }, \ +} diff --git a/ath5k_reg.h b/ath5k_reg.h new file mode 100644 index 0000000..05c0b88 --- /dev/null +++ b/ath5k_reg.h @@ -0,0 +1,1917 @@ +/*- + * Copyright (c) 2007 Nick Kossifidis + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +/* + * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k + * maintained by Reyk Floeter + * + * I tried to document those registers by looking at ar5k code, some + * 802.11 (802.11e mostly) papers and by reading various public available + * Atheros presentations and papers like these: + * + * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf + * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf + * + * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf + */ + + + +/*====MAC DMA REGISTERS====*/ + +/* + * AR5210-Specific TXDP registers + * 5210 has only 2 transmit queues so no DCU/QCU, just + * 2 transmit descriptor pointers... + */ +#define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ +#define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ + +/* + * Mac Control Register + */ +#define AR5K_CR 0x0008 /* Register Address */ +#define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ +#define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ +#define AR5K_CR_RXE 0x00000004 /* RX Enable */ +#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ +#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ +#define AR5K_CR_RXD 0x00000020 /* RX Disable */ +#define AR5K_CR_SWI 0x00000040 + +/* + * RX Descriptor Pointer register + */ +#define AR5K_RXDP 0x000c + +/* + * Configuration and status register + */ +#define AR5K_CFG 0x0014 /* Register Address */ +#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ +#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer (?) */ +#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ +#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer (?) */ +#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register values (?) */ +#define AR5K_CFG_ADHOC 0x00000020 /* [5211+] */ +#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ +#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ +#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (?) */ +#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ +#define AR5K_CFG_TXCNT_S 11 +#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ +#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ +#define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ +#define AR5K_CFG_PCI_THRES_S 17 + +/* + * Interrupt enable register + */ +#define AR5K_IER 0x0024 /* Register Address */ +#define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ +#define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ + + +/* + * 0x0028 is Beacon Control Register on 5210 + * and first RTS duration register on 5211 + */ + +/* + * Beacon control register [5210] + */ +#define AR5K_BCR 0x0028 /* Register Address */ +#define AR5K_BCR_AP 0x00000000 /* AP mode */ +#define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ +#define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ +#define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ +#define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ +#define AR5K_BCR_BCGET 0x00000010 + +/* + * First RTS duration register [5211] + */ +#define AR5K_RTSD0 0x0028 /* Register Address */ +#define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ +#define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ +#define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ +#define AR5K_RTSD0_9_S 8 +#define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ +#define AR5K_RTSD0_12_S 16 +#define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ +#define AR5K_RTSD0_18_S 24 + + +/* + * 0x002c is Beacon Status Register on 5210 + * and second RTS duration register on 5211 + */ + +/* + * Beacon status register [5210] + * + * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR + * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning + * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). + * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i + * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what + * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. + */ +#define AR5K_BSR 0x002c /* Register Address */ +#define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ +#define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ +#define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ +#define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ +#define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ +#define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ +#define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ +#define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ +#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ +#define AR5K_BSR_SWBA_CNT 0x00ff0000 + +/* + * Second RTS duration register [5211] + */ +#define AR5K_RTSD1 0x002c /* Register Address */ +#define AR5K_RTSD1_24 0x000000ff /* 24Mb */ +#define AR5K_RTSD1_24_S 0 +#define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ +#define AR5K_RTSD1_36_S 8 +#define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ +#define AR5K_RTSD1_48_S 16 +#define AR5K_RTSD1_54 0xff000000 /* 54Mb */ +#define AR5K_RTSD1_54_S 24 + + +/* + * Transmit configuration register + */ +#define AR5K_TXCFG 0x0030 /* Register Address */ +#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */ +#define AR5K_TXCFG_SDMAMR_S 0 +#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ +#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ +#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ +#define AR5K_TXCFG_TXFULL_S 4 +#define AR5K_TXCFG_TXFULL_0B 0x00000000 +#define AR5K_TXCFG_TXFULL_64B 0x00000010 +#define AR5K_TXCFG_TXFULL_128B 0x00000020 +#define AR5K_TXCFG_TXFULL_192B 0x00000030 +#define AR5K_TXCFG_TXFULL_256B 0x00000040 +#define AR5K_TXCFG_TXCONT_EN 0x00000080 +#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ +#define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ +#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ +#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ +#define AR5K_TXCFG_RDY_DIS 0x00004000 /* [5211+] */ + +/* + * Receive configuration register + */ +#define AR5K_RXCFG 0x0034 /* Register Address */ +#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */ +#define AR5K_RXCFG_SDMAMW_S 0 +#define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /* Default antenna */ +#define AR5K_RXCFG_ZLFDMA 0x00000010 /* Zero-length DMA */ +#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo frames reception (?) [5211+] */ +#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames (?) [5211+] */ + +/* + * Receive jumbo descriptor last address register + * Only found in 5211 (?) + */ +#define AR5K_RXJLA 0x0038 + +/* + * MIB control register + */ +#define AR5K_MIBC 0x0040 /* Register Address */ +#define AR5K_MIBC_COW 0x00000001 +#define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ +#define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ +#define AR5K_MIBC_MCS 0x00000008 + +/* + * Timeout prescale register + */ +#define AR5K_TOPS 0x0044 +#define AR5K_TOPS_M 0x0000ffff /* [5211+] (?) */ + +/* + * Receive timeout register (no frame received) + */ +#define AR5K_RXNOFRM 0x0048 +#define AR5K_RXNOFRM_M 0x000003ff /* [5211+] (?) */ + +/* + * Transmit timeout register (no frame sent) + */ +#define AR5K_TXNOFRM 0x004c +#define AR5K_TXNOFRM_M 0x000003ff /* [5211+] (?) */ +#define AR5K_TXNOFRM_QCU 0x000ffc00 /* [5211+] (?) */ + +/* + * Receive frame gap timeout register + */ +#define AR5K_RPGTO 0x0050 +#define AR5K_RPGTO_M 0x000003ff /* [5211+] (?) */ + +/* + * Receive frame count limit register + */ +#define AR5K_RFCNT 0x0054 +#define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ +#define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ + +/* + * Misc settings register + */ +#define AR5K_MISC 0x0058 /* Register Address */ +#define AR5K_MISC_DMA_OBS_M 0x000001e0 +#define AR5K_MISC_DMA_OBS_S 5 +#define AR5K_MISC_MISC_OBS_M 0x00000e00 +#define AR5K_MISC_MISC_OBS_S 9 +#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 +#define AR5K_MISC_MAC_OBS_LSB_S 12 +#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 +#define AR5K_MISC_MAC_OBS_MSB_S 15 +#define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ +#define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ + +/* + * QCU/DCU clock gating register (5311) + */ +#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ +#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ +#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ + +/* + * Interrupt Status Registers + * + * For 5210 there is only one status register but for + * 5211/5212 we have one primary and 4 secondary registers. + * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. + * Most of these bits are common for all chipsets. + */ +#define AR5K_ISR 0x001c /* Register Address [5210] */ +#define AR5K_PISR 0x0080 /* Register Address [5211+] */ +#define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ +#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ +#define AR5K_ISR_RXERR 0x00000004 /* Receive error */ +#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ +#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ +#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ +#define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ +#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ +#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ +#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ +#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ +#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ +#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ +#define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ +#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ +#define AR5K_ISR_RXKCM 0x00008000 +#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ +#define AR5K_ISR_BRSSI 0x00020000 +#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ +#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ +#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ +#define AR5K_ISR_MCABT 0x00100000 /* [5210] */ +#define AR5K_ISR_RXCHIRP 0x00200000 /* [5212+] */ +#define AR5K_ISR_SSERR 0x00200000 /* [5210] */ +#define AR5K_ISR_DPERR 0x00400000 /* [5210] */ +#define AR5K_ISR_TIM 0x00800000 /* [5210] */ +#define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ +#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ +#define AR5K_ISR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ +#define AR5K_ISR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ +#define AR5K_ISR_QTRIG 0x08000000 /* [5211+] */ + +/* + * Secondary status registers [5211+] (0 - 4) + * + * I guess from the names that these give the status for each + * queue, that's why only masks are defined here, haven't got + * any info about them (couldn't find them anywhere in ar5k code). + */ +#define AR5K_SISR0 0x0084 /* Register Address [5211+] */ +#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ +#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ + +#define AR5K_SISR1 0x0088 /* Register Address [5211+] */ +#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ +#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ + +#define AR5K_SISR2 0x008c /* Register Address [5211+] */ +#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ +#define AR5K_SISR2_MCABT 0x00100000 +#define AR5K_SISR2_SSERR 0x00200000 +#define AR5K_SISR2_DPERR 0x00400000 +#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ +#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ +#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ +#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ +#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ +#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ + +#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ +#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ +#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ + +#define AR5K_SISR4 0x0094 /* Register Address [5211+] */ +#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ + +/* + * Shadow read-and-clear interrupt status registers [5211+] + */ +#define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ +#define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ +#define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ +#define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ +#define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ +#define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ + +/* + * Interrupt Mask Registers + * + * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary + * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. + */ +#define AR5K_IMR 0x0020 /* Register Address [5210] */ +#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ +#define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ +#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ +#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ +#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ +#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ +#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ +#define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ +#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ +#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ +#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ +#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ +#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ +#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ +#define AR5K_IMR_SWI 0x00002000 +#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ +#define AR5K_IMR_RXKCM 0x00008000 +#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ +#define AR5K_IMR_BRSSI 0x00020000 +#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ +#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ +#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ +#define AR5K_IMR_MCABT 0x00100000 /* [5210] */ +#define AR5K_IMR_RXCHIRP 0x00200000 /* [5212+]*/ +#define AR5K_IMR_SSERR 0x00200000 /* [5210] */ +#define AR5K_IMR_DPERR 0x00400000 /* [5210] */ +#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ +#define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ +#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ +#define AR5K_IMR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ +#define AR5K_IMR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ +#define AR5K_IMR_QTRIG 0x08000000 /* [5211+] */ + +/* + * Secondary interrupt mask registers [5211+] (0 - 4) + */ +#define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ +#define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ +#define AR5K_SIMR0_QCU_TXOK_S 0 +#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ +#define AR5K_SIMR0_QCU_TXDESC_S 16 + +#define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ +#define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ +#define AR5K_SIMR1_QCU_TXERR_S 0 +#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ +#define AR5K_SIMR1_QCU_TXEOL_S 16 + +#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ +#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ +#define AR5K_SIMR2_QCU_TXURN_S 0 +#define AR5K_SIMR2_MCABT 0x00100000 +#define AR5K_SIMR2_SSERR 0x00200000 +#define AR5K_SIMR2_DPERR 0x00400000 +#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ +#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ +#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ +#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ +#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ +#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ + +#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ +#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ +#define AR5K_SIMR3_QCBRORN_S 0 +#define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ +#define AR5K_SIMR3_QCBRURN_S 16 + +#define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ +#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ +#define AR5K_SIMR4_QTRIG_S 0 + + +/* + * Decompression mask registers [5212+] + */ +#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (?)*/ +#define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/ + +/* + * Decompression configuration registers [5212+] + */ +#define AR5K_DCCFG 0x0420 + +/* + * Compression configuration registers [5212+] + */ +#define AR5K_CCFG 0x0600 +#define AR5K_CCFG_CUP 0x0604 + +/* + * Compression performance counter registers [5212+] + */ +#define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ +#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ +#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ +#define AR5K_CPC3 0x061c /* Compression performance counter 3 */ +#define AR5K_CPCORN 0x0620 /* Compression performance overrun (?) */ + + +/* + * Queue control unit (QCU) registers [5211+] + * + * Card has 12 TX Queues but i see that only 0-9 are used (?) + * both in binary HAL (see ah.h) and ar5k. Each queue has it's own + * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) + * configuration register (0x08c0 - 0x08ec), a ready time configuration + * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - + * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some + * global registers, QCU transmit enable/disable and "one shot arm (?)" + * set/clear, which contain status for all queues (we shift by 1 for each + * queue). To access these registers easily we define some macros here + * that are used inside HAL. For more infos check out *_tx_queue functs. + * + * TODO: Boundary checking on macros (here?) + */ + +/* + * Generic QCU Register access macros + */ +#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) +#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) +#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) + +/* + * QCU Transmit descriptor pointer registers + */ +#define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ +#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) + +/* + * QCU Transmit enable register + */ +#define AR5K_QCU_TXE 0x0840 +#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) +#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) + +/* + * QCU Transmit disable register + */ +#define AR5K_QCU_TXD 0x0880 +#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) +#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) + +/* + * QCU Constant Bit Rate configuration registers + */ +#define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ +#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ +#define AR5K_QCU_CBRCFG_INTVAL_S 0 +#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ +#define AR5K_QCU_CBRCFG_ORN_THRES_S 24 +#define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) + +/* + * QCU Ready time configuration registers + */ +#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ +#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ +#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 +#define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /* Ready time duration mask */ +#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ +#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) + +/* + * QCU one shot arm set registers + */ +#define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ +#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff + +/* + * QCU one shot arm clear registers + */ +#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ +#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff + +/* + * QCU misc registers + */ +#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ +#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ +#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ +#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ +#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ +#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ +#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ +#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ +#define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ +#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ +#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Beacons enabled */ +#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled (?) */ +#define AR5K_QCU_MISC_TXE 0x00000200 /* TXE reset when RDYTIME enalbed (?) */ +#define AR5K_QCU_MISC_CBR 0x00000400 /* CBR threshold reset (?) */ +#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU reset (?) */ +#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) + + +/* + * QCU status registers + */ +#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ +#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ +#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter (?) */ +#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) + +/* + * QCU ready time shutdown register + */ +#define AR5K_QCU_RDYTIMESHDN 0x0a40 +#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff + +/* + * QCU compression buffer base registers [5212+] + */ +#define AR5K_QCU_CBB_SELECT 0x0b00 +#define AR5K_QCU_CBB_ADDR 0x0b04 + +/* + * QCU compression buffer configuration register [5212+] + */ +#define AR5K_QCU_CBCFG 0x0b08 + + + +/* + * Distributed Coordination Function (DCF) control unit (DCU) + * registers [5211+] + * + * These registers control the various characteristics of each queue + * for 802.11e (WME) combatibility so they go together with + * QCU registers in pairs. For each queue we have a QCU mask register, + * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), + * a retry limit register (0x1080 - 0x10ac), a channel time register + * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and + * a sequence number register (0x1140 - 0x116c). It seems that "global" + * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). + * We use the same macros here for easier register access. + * + */ + +/* + * DCU QCU mask registers + */ +#define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ +#define AR5K_DCU_QCUMASK_M 0x000003ff +#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) + +/* + * DCU local Inter Frame Space settings register + */ +#define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ +#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ +#define AR5K_DCU_LCL_IFS_CW_MIN_S 0 +#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ +#define AR5K_DCU_LCL_IFS_CW_MAX_S 10 +#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ +#define AR5K_DCU_LCL_IFS_AIFS_S 20 +#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) + +/* + * DCU retry limit registers + */ +#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ +#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ +#define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 +#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ +#define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 +#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ +#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 +#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ +#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 +#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) + +/* + * DCU channel time registers + */ +#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ +#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ +#define AR5K_DCU_CHAN_TIME_DUR_S 0 +#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ +#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) + +/* + * DCU misc registers [5211+] + * + * For some of the registers i couldn't find in the code + * (only backoff stuff is there realy) i tried to match the + * names with 802.11e parameters etc, so i guess VIRTCOL here + * means Virtual Collision and HCFPOLL means Hybrid Coordination + * factor Poll (CF- Poll). Arbiter lockout control controls the + * behaviour on low priority queues when we have multiple queues + * with pending frames. Intra-frame lockout means we wait until + * the queue's current frame transmits (with post frame backoff and bursting) + * before we transmit anything else and global lockout means we + * wait for the whole queue to finish before higher priority queues + * can transmit (this is used on beacon and CAB queues). + * No lockout means there is no special handling. + */ +#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ +#define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff setting (?) */ +#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ +#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll (?) */ +#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff (?) */ +#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch (?) */ +#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ +#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 +#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 +#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 +#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Beacon enable (?) */ +#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 +#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ +#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 +#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ +#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ +#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ +#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 +#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ +#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) + +/* + * DCU frame sequence number registers + */ +#define AR5K_DCU_SEQNUM_BASE 0x1140 +#define AR5K_DCU_SEQNUM_M 0x00000fff +#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) + +/* + * DCU global IFS SIFS registers + */ +#define AR5K_DCU_GBL_IFS_SIFS 0x1030 +#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff + +/* + * DCU global IFS slot interval registers + */ +#define AR5K_DCU_GBL_IFS_SLOT 0x1070 +#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff + +/* + * DCU global IFS EIFS registers + */ +#define AR5K_DCU_GBL_IFS_EIFS 0x10b0 +#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff + +/* + * DCU global IFS misc registers + */ +#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ +#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 +#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ +#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ +#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 +#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 + +/* + * DCU frame prefetch control register + */ +#define AR5K_DCU_FP 0x1230 + +/* + * DCU transmit pause control/status register + */ +#define AR5K_DCU_TXP 0x1270 /* Register Address */ +#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask (?) */ +#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status (?) */ + +/* + * DCU transmit filter register + */ +#define AR5K_DCU_TX_FILTER 0x1038 + +/* + * DCU clear transmit filter register + */ +#define AR5K_DCU_TX_FILTER_CLR 0x143c + +/* + * DCU set transmit filter register + */ +#define AR5K_DCU_TX_FILTER_SET 0x147c + +/* + * Reset control register + * + * 4 and 8 are not used in 5211/5212 and + * 2 means "baseband reset" on 5211/5212. + */ +#define AR5K_RESET_CTL 0x4000 /* Register Address */ +#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ +#define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ +#define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ +#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ +#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ +#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ +#define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \ + AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY) + +/* + * Sleep control register + */ +#define AR5K_SLEEP_CTL 0x4004 /* Register Address */ +#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ +#define AR5K_SLEEP_CTL_SLDUR_S 0 +#define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ +#define AR5K_SLEEP_CTL_SLE_S 16 +#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ +#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ +#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 +#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ + +/* + * Interrupt pending register + */ +#define AR5K_INTPEND 0x4008 +#define AR5K_INTPEND_M 0x00000001 + +/* + * Sleep force register + */ +#define AR5K_SFR 0x400c +#define AR5K_SFR_M 0x00000001 + +/* + * PCI configuration register + */ +#define AR5K_PCICFG 0x4010 /* Register Address */ +#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ +#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ +#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ +#define AR5K_PCICFG_EESIZE_S 3 +#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ +#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ +#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ +#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size (?) [5211+] */ +#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ +#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ +#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ +#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ +#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ +#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ +#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ +#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ +#define AR5K_PCICFG_SL_INPEN 0x00002800 /* Sleep even whith pending interrupts (?) */ +#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ +#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ +#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ +#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ +#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ +#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ +#define AR5K_PCICFG_LEDBLINK 0x00700000 +#define AR5K_PCICFG_LEDBLINK_S 20 +#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ +#define AR5K_PCICFG_LEDSTATE \ + (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ + AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) + +/* + * "General Purpose Input/Output" (GPIO) control register + * + * I'm not sure about this but after looking at the code + * for all chipsets here is what i got. + * + * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) + * Mode 0 -> always input + * Mode 1 -> output when GPIODO for this GPIO is set to 0 + * Mode 2 -> output when GPIODO for this GPIO is set to 1 + * Mode 3 -> always output + * + * For more infos check out get_gpio/set_gpio and + * set_gpio_input/set_gpio_output functs. + * For more infos on gpio interrupt check out set_gpio_intr. + */ +#define AR5K_NUM_GPIO 6 + +#define AR5K_GPIOCR 0x4014 /* Register Address */ +#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ +#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is off (?) */ +#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is on */ +#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ +#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ +#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ +#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ +#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ + +/* + * "General Purpose Input/Output" (GPIO) data output register + */ +#define AR5K_GPIODO 0x4018 + +/* + * "General Purpose Input/Output" (GPIO) data input register + */ +#define AR5K_GPIODI 0x401c +#define AR5K_GPIODI_M 0x0000002f + + +/* + * Silicon revision register + */ +#define AR5K_SREV 0x4020 /* Register Address */ +#define AR5K_SREV_REV 0x0000000f /* Mask for revision */ +#define AR5K_SREV_REV_S 0 +#define AR5K_SREV_VER 0x000000ff /* Mask for version */ +#define AR5K_SREV_VER_S 4 + + + +/*====EEPROM REGISTERS====*/ + +/* + * EEPROM access registers + * + * Here we got a difference between 5210/5211-12 + * read data register for 5210 is at 0x6800 and + * status register is at 0x6c00. There is also + * no eeprom command register on 5210 and the + * offsets are different. + * + * To read eeprom data for a specific offset: + * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) + * read AR5K_EEPROM_BASE +(4 * offset) + * check the eeprom status register + * and read eeprom data register. + * + * 5211 - write offset to AR5K_EEPROM_BASE + * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD + * check the eeprom status register + * and read eeprom data register. + * + * To write eeprom data for a specific offset: + * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) + * write data to AR5K_EEPROM_BASE +(4 * offset) + * check the eeprom status register + * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD + * 5212 write offset to AR5K_EEPROM_BASE + * write data to data register + * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD + * check the eeprom status register + * + * For more infos check eeprom_* functs and the ar5k.c + * file posted in madwifi-devel mailing list. + * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 + * + */ +#define AR5K_EEPROM_BASE 0x6000 + +/* + * Common ar5xxx EEPROM data offset (set these on AR5K_EEPROM_BASE) + */ +#define AR5K_EEPROM_MAGIC 0x003d +#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 +#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ +#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ +#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ + +#define AR5K_EEPROM_PROTECT 0x003f +#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 +#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 +#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 +#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 +#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 +#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 +#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 +#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 +#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 +#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 +#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 +#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 +#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 +#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 +#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 +#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 +#define AR5K_EEPROM_REG_DOMAIN 0x00bf +#define AR5K_EEPROM_INFO_BASE 0x00c0 +#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) +#define AR5K_EEPROM_INFO_CKSUM 0xffff +#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) + +#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) +#define AR5K_EEPROM_VERSION_3_0 0x3000 +#define AR5K_EEPROM_VERSION_3_1 0x3001 +#define AR5K_EEPROM_VERSION_3_2 0x3002 +#define AR5K_EEPROM_VERSION_3_3 0x3003 +#define AR5K_EEPROM_VERSION_3_4 0x3004 +#define AR5K_EEPROM_VERSION_4_0 0x4000 +#define AR5K_EEPROM_VERSION_4_1 0x4001 +#define AR5K_EEPROM_VERSION_4_2 0x4002 +#define AR5K_EEPROM_VERSION_4_3 0x4003 +#define AR5K_EEPROM_VERSION_4_6 0x4006 +#define AR5K_EEPROM_VERSION_4_7 0x3007 + +#define AR5K_EEPROM_MODE_11A 0 +#define AR5K_EEPROM_MODE_11B 1 +#define AR5K_EEPROM_MODE_11G 2 + +#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) +#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) +#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) +#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) +#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) +#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) +#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) +#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) +#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) + +#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c +#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 +#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 +#define AR5K_EEPROM_RFKILL_POLARITY_S 1 + +/* Newer EEPROMs are using a different offset */ +#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ + (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) + +#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) +#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) +#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) + +#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) +#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) +#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) +#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) + +/* Since 3.1 */ +#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec +#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed + +/* Misc values available since EEPROM 4.0 */ +#define AR5K_EEPROM_MISC0 0x00c4 +#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) +#define AR5K_EEPROM_MISC1 0x00c5 +#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) + +/* + * EEPROM data register + */ +#define AR5K_EEPROM_DATA_5211 0x6004 +#define AR5K_EEPROM_DATA_5210 0x6800 +#define AR5K_EEPROM_DATA (hal->ah_version == AR5K_AR5210 ? \ + AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) + +/* + * EEPROM command register + */ +#define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ +#define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ +#define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ +#define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ + +/* + * EEPROM status register + */ +#define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ +#define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ +#define AR5K_EEPROM_STATUS (hal->ah_version == AR5K_AR5210 ? \ + AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) +#define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ +#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ +#define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ +#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ + +/* + * EEPROM config register (?) + */ +#define AR5K_EEPROM_CFG 0x6010 + + + +/* + * Protocol Control Unit (PCU) registers + */ +/* + * Used for checking initial register writes + * during channel reset (see reset func) + */ +#define AR5K_PCU_MIN 0x8000 +#define AR5K_PCU_MAX 0x8fff + +/* + * First station id register (MAC address in lower 32 bits) + */ +#define AR5K_STA_ID0 0x8000 + +/* + * Second station id register (MAC address in upper 16 bits) + */ +#define AR5K_STA_ID1 0x8004 /* Register Address */ +#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ +#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ +#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */ +#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ +#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ +#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ +#define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ +#define AR5K_STA_ID1_PCF (hal->ah_version == AR5K_AR5210 ? \ + AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) +#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ +#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ +#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */ +#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */ +#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ + +/* + * First BSSID register (MAC address, lower 32bits) + */ +#define AR5K_BSS_ID0 0x8008 + +/* + * Second BSSID register (MAC address in upper 16 bits) + * + * AID: Association ID + */ +#define AR5K_BSS_ID1 0x800c +#define AR5K_BSS_ID1_AID 0xffff0000 +#define AR5K_BSS_ID1_AID_S 16 + +/* + * Backoff slot time register + */ +#define AR5K_SLOT_TIME 0x8010 + +/* + * ACK/CTS timeout register + */ +#define AR5K_TIME_OUT 0x8014 /* Register Address */ +#define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ +#define AR5K_TIME_OUT_ACK_S 0 +#define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ +#define AR5K_TIME_OUT_CTS_S 16 + +/* + * RSSI threshold register + */ +#define AR5K_RSSI_THR 0x8018 /* Register Address */ +#define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ +#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ +#define AR5K_RSSI_THR_BMISS_5210_S 8 +#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ +#define AR5K_RSSI_THR_BMISS_5211_S 8 +#define AR5K_RSSI_THR_BMISS (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) +#define AR5K_RSSI_THR_BMISS_S 8 + +/* + * 5210 has more PCU registers because there is no QCU/DCU + * so queue parameters are set here, this way a lot common + * registers have different address for 5210. To make things + * easier we define a macro based on hal->ah_version for common + * registers with different addresses and common flags. + */ + +/* + * Retry limit register + * + * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) + */ +#define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address */ +#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ +#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 +#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ +#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 +#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ +#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 +#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ +#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 +#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ +#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 + +/* + * Transmit latency register + */ +#define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ +#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ +#define AR5K_USEC (hal->ah_version == AR5K_AR5210 ? \ + AR5K_USEC_5210 : AR5K_USEC_5211) +#define AR5K_USEC_1 0x0000007f +#define AR5K_USEC_1_S 0 +#define AR5K_USEC_32 0x00003f80 +#define AR5K_USEC_32_S 7 +#define AR5K_USEC_TX_LATENCY_5211 0x007fc000 +#define AR5K_USEC_TX_LATENCY_5211_S 14 +#define AR5K_USEC_RX_LATENCY_5211 0x1f800000 +#define AR5K_USEC_RX_LATENCY_5211_S 23 +#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ +#define AR5K_USEC_TX_LATENCY_5210_S 14 +#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ +#define AR5K_USEC_RX_LATENCY_5210_S 20 + +/* + * PCU beacon control register + */ +#define AR5K_BEACON_5210 0x8024 +#define AR5K_BEACON_5211 0x8020 +#define AR5K_BEACON (hal->ah_version == AR5K_AR5210 ? \ + AR5K_BEACON_5210 : AR5K_BEACON_5211) +#define AR5K_BEACON_PERIOD 0x0000ffff +#define AR5K_BEACON_PERIOD_S 0 +#define AR5K_BEACON_TIM 0x007f0000 +#define AR5K_BEACON_TIM_S 16 +#define AR5K_BEACON_ENABLE 0x00800000 +#define AR5K_BEACON_RESET_TSF 0x01000000 + +/* + * CFP period register + */ +#define AR5K_CFP_PERIOD_5210 0x8028 +#define AR5K_CFP_PERIOD_5211 0x8024 +#define AR5K_CFP_PERIOD (hal->ah_version == AR5K_AR5210 ? \ + AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) + +/* + * Next beacon time register + */ +#define AR5K_TIMER0_5210 0x802c +#define AR5K_TIMER0_5211 0x8028 +#define AR5K_TIMER0 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER0_5210 : AR5K_TIMER0_5211) + +/* + * Next DMA beacon alert register + */ +#define AR5K_TIMER1_5210 0x8030 +#define AR5K_TIMER1_5211 0x802c +#define AR5K_TIMER1 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER1_5210 : AR5K_TIMER1_5211) + +/* + * Next software beacon alert register + */ +#define AR5K_TIMER2_5210 0x8034 +#define AR5K_TIMER2_5211 0x8030 +#define AR5K_TIMER2 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER2_5210 : AR5K_TIMER2_5211) + +/* + * Next ATIM window time register + */ +#define AR5K_TIMER3_5210 0x8038 +#define AR5K_TIMER3_5211 0x8034 +#define AR5K_TIMER3 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER3_5210 : AR5K_TIMER3_5211) + + +/* + * 5210 First inter frame spacing register (IFS) + */ +#define AR5K_IFS0 0x8040 +#define AR5K_IFS0_SIFS 0x000007ff +#define AR5K_IFS0_SIFS_S 0 +#define AR5K_IFS0_DIFS 0x007ff800 +#define AR5K_IFS0_DIFS_S 11 + +/* + * 5210 Second inter frame spacing register (IFS) + */ +#define AR5K_IFS1 0x8044 +#define AR5K_IFS1_PIFS 0x00000fff +#define AR5K_IFS1_PIFS_S 0 +#define AR5K_IFS1_EIFS 0x03fff000 +#define AR5K_IFS1_EIFS_S 12 +#define AR5K_IFS1_CS_EN 0x04000000 + + +/* + * CFP duration register + */ +#define AR5K_CFP_DUR_5210 0x8048 +#define AR5K_CFP_DUR_5211 0x8038 +#define AR5K_CFP_DUR (hal->ah_version == AR5K_AR5210 ? \ + AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) + +/* + * Receive filter register + * TODO: Get these out of ar5xxx.h on ath5k + */ +#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ +#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ +#define AR5K_RX_FILTER (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) +#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ +#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ +#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ +#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ +#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ +#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ +#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ +#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ +#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ +#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ +#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ +#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ +#define AR5K_RX_FILTER_PHYERR (hal->ah_version == AR5K_AR5211 ? \ + AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212) +#define AR5K_RX_FILTER_RADARERR (hal->ah_version == AR5K_AR5211 ? \ + AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212) +/* + * Multicast filter register (lower 32 bits) + */ +#define AR5K_MCAST_FILTER0_5210 0x8050 +#define AR5K_MCAST_FILTER0_5211 0x8040 +#define AR5K_MCAST_FILTER0 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) + +/* + * Multicast filter register (higher 16 bits) + */ +#define AR5K_MCAST_FILTER1_5210 0x8054 +#define AR5K_MCAST_FILTER1_5211 0x8044 +#define AR5K_MCAST_FILTER1 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) + + +/* + * Transmit mask register (lower 32 bits) [5210] + */ +#define AR5K_TX_MASK0 0x8058 + +/* + * Transmit mask register (higher 16 bits) [5210] + */ +#define AR5K_TX_MASK1 0x805c + +/* + * Clear transmit mask [5210] + */ +#define AR5K_CLR_TMASK 0x8060 + +/* + * Trigger level register (before transmission) [5210] + */ +#define AR5K_TRIG_LVL 0x8064 + + +/* + * PCU control register + * + * Only DIS_RX is used in the code, the rest i guess are + * for tweaking/diagnostics. + */ +#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ +#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ +#define AR5K_DIAG_SW (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) +#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 +#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ +#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ +#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ +#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption (?) */ +#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ +#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ +#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 +#define AR5K_DIAG_SW_DIS_RX (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) +#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ +#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 +#define AR5K_DIAG_SW_LOOP_BACK (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) +#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 +#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 +#define AR5K_DIAG_SW_CORR_FCS (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) +#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 +#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 +#define AR5K_DIAG_SW_CHAN_INFO (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) +#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Scrambler seed (?) */ +#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 +#define AR5K_DIAG_SW_EN_SCRAM_SEED (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) +#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ +#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ +#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ +#define AR5K_DIAG_SW_SCRAM_SEED_S 10 +#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ +#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 +#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 +#define AR5K_DIAG_SW_FRAME_NV0 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) +#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 +#define AR5K_DIAG_SW_OBSPT_S 18 + +/* + * TSF (clock) register (lower 32 bits) + */ +#define AR5K_TSF_L32_5210 0x806c +#define AR5K_TSF_L32_5211 0x804c +#define AR5K_TSF_L32 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) + +/* + * TSF (clock) register (higher 32 bits) + */ +#define AR5K_TSF_U32_5210 0x8070 +#define AR5K_TSF_U32_5211 0x8050 +#define AR5K_TSF_U32 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) + +/* + * Last beacon timestamp register + */ +#define AR5K_LAST_TSTP 0x8080 + +/* + * ADDAC test register [5211+] + */ +#define AR5K_ADDAC_TEST 0x8054 +#define AR5K_ADDAC_TEST_TXCONT 0x00000001 + +/* + * Default antenna register [5211+] + */ +#define AR5K_DEFAULT_ANTENNA 0x8058 + + + +/* + * Retry count register [5210] + */ +#define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ +#define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ +#define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ + +/* + * Back-off status register [5210] + */ +#define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ +#define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ +#define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ + + + +/* + * NAV register (current) + */ +#define AR5K_NAV_5210 0x808c +#define AR5K_NAV_5211 0x8084 +#define AR5K_NAV (hal->ah_version == AR5K_AR5210 ? \ + AR5K_NAV_5210 : AR5K_NAV_5211) + +/* + * RTS success register + */ +#define AR5K_RTS_OK_5210 0x8090 +#define AR5K_RTS_OK_5211 0x8088 +#define AR5K_RTS_OK (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) + +/* + * RTS failure register + */ +#define AR5K_RTS_FAIL_5210 0x8094 +#define AR5K_RTS_FAIL_5211 0x808c +#define AR5K_RTS_FAIL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) + +/* + * ACK failure register + */ +#define AR5K_ACK_FAIL_5210 0x8098 +#define AR5K_ACK_FAIL_5211 0x8090 +#define AR5K_ACK_FAIL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) + +/* + * FCS failure register + */ +#define AR5K_FCS_FAIL_5210 0x809c +#define AR5K_FCS_FAIL_5211 0x8094 +#define AR5K_FCS_FAIL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) + +/* + * Beacon count register + */ +#define AR5K_BEACON_CNT_5210 0x80a0 +#define AR5K_BEACON_CNT_5211 0x8098 +#define AR5K_BEACON_CNT (hal->ah_version == AR5K_AR5210 ? \ + AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) + + +/*===5212 Specific PCU registers===*/ + +/* + * XR (eXtended Range) mode register + */ +#define AR5K_XRMODE 0x80c0 +#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f +#define AR5K_XRMODE_POLL_TYPE_S 0 +#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c +#define AR5K_XRMODE_POLL_SUBTYPE_S 2 +#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 +#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 +#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 +#define AR5K_XRMODE_FRAME_HOLD_S 20 + +/* + * XR delay register + */ +#define AR5K_XRDELAY 0x80c4 +#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff +#define AR5K_XRDELAY_SLOT_DELAY_S 0 +#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 +#define AR5K_XRDELAY_CHIRP_DELAY_S 16 + +/* + * XR timeout register + */ +#define AR5K_XRTIMEOUT 0x80c8 +#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff +#define AR5K_XRTIMEOUT_CHIRP_S 0 +#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 +#define AR5K_XRTIMEOUT_POLL_S 16 + +/* + * XR chirp register + */ +#define AR5K_XRCHIRP 0x80cc +#define AR5K_XRCHIRP_SEND 0x00000001 +#define AR5K_XRCHIRP_GAP 0xffff0000 + +/* + * XR stomp register + */ +#define AR5K_XRSTOMP 0x80d0 +#define AR5K_XRSTOMP_TX 0x00000001 +#define AR5K_XRSTOMP_RX_ABORT 0x00000002 +#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 + +/* + * First enhanced sleep register + */ +#define AR5K_SLEEP0 0x80d4 +#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff +#define AR5K_SLEEP0_NEXT_DTIM_S 0 +#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 +#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 +#define AR5K_SLEEP0_CABTO 0xff000000 +#define AR5K_SLEEP0_CABTO_S 24 + +/* + * Second enhanced sleep register + */ +#define AR5K_SLEEP1 0x80d8 +#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff +#define AR5K_SLEEP1_NEXT_TIM_S 0 +#define AR5K_SLEEP1_BEACON_TO 0xff000000 +#define AR5K_SLEEP1_BEACON_TO_S 24 + +/* + * Third enhanced sleep register + */ +#define AR5K_SLEEP2 0x80dc +#define AR5K_SLEEP2_TIM_PER 0x0000ffff +#define AR5K_SLEEP2_TIM_PER_S 0 +#define AR5K_SLEEP2_DTIM_PER 0xffff0000 +#define AR5K_SLEEP2_DTIM_PER_S 16 + +/* + * BSSID mask registers + */ +#define AR5K_BSS_IDM0 0x80e0 +#define AR5K_BSS_IDM1 0x80e4 + +/* + * TX power control (TPC) register + */ +#define AR5K_TXPC 0x80e8 +#define AR5K_TXPC_ACK_M 0x0000003f +#define AR5K_TXPC_ACK_S 0 +#define AR5K_TXPC_CTS_M 0x00003f00 +#define AR5K_TXPC_CTS_S 8 +#define AR5K_TXPC_CHIRP_M 0x003f0000 +#define AR5K_TXPC_CHIRP_S 22 + +/* + * Profile count registers + */ +#define AR5K_PROFCNT_TX 0x80ec +#define AR5K_PROFCNT_RX 0x80f0 +#define AR5K_PROFCNT_RXCLR 0x80f4 +#define AR5K_PROFCNT_CYCLE 0x80f8 + +/* + * TSF parameter register + */ +#define AR5K_TSF_PARM 0x8104 +#define AR5K_TSF_PARM_INC_M 0x000000ff +#define AR5K_TSF_PARM_INC_S 0 + +/* + * PHY error filter register + */ +#define AR5K_PHY_ERR_FIL 0x810c +#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 +#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 +#define AR5K_PHY_ERR_FIL_CCK 0x02000000 + +/* + * Rate duration register + */ +#define AR5K_RATE_DUR_BASE 0x8700 +#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) + +/*===5212 end===*/ + +/* + * Key table (WEP) register + */ +#define AR5K_KEYTABLE_0_5210 0x9000 +#define AR5K_KEYTABLE_0_5211 0x8800 +#define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) +#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) * 32)) +#define AR5K_KEYTABLE(_n) (hal->ah_version == AR5K_AR5210 ? \ + AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) +#define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) +#define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5) +#define AR5K_KEYTABLE_TYPE_40 0x00000000 +#define AR5K_KEYTABLE_TYPE_104 0x00000001 +#define AR5K_KEYTABLE_TYPE_128 0x00000003 +#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */ +#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */ +#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */ +#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */ +#define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */ +#define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) +#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) +#define AR5K_KEYTABLE_VALID 0x00008000 + +#define AR5K_KEYTABLE_SIZE_5210 64 +#define AR5K_KEYTABLE_SIZE_5211 128 +#define AR5K_KEYTABLE_SIZE (hal->ah_version == AR5K_AR5210 ? \ + AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) + + +/*===PHY REGISTERS===*/ + +/* + * PHY register + */ +#define AR5K_PHY_BASE 0x9800 +#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) +#define AR5K_PHY_SHIFT_2GHZ 0x00004007 +#define AR5K_PHY_SHIFT_5GHZ 0x00000007 + +/* + * PHY frame control register [5110] /turbo mode register [5111+] + * + * There is another frame control register for [5111+] + * at address 0x9944 (see below) but the 2 first flags + * are common here between 5110 frame control register + * and [5111+] turbo mode register, so this also works as + * a "turbo mode register" for 5110. We treat this one as + * a frame control register for 5110 below. + */ +#define AR5K_PHY_TURBO 0x9804 +#define AR5K_PHY_TURBO_MODE 0x00000001 +#define AR5K_PHY_TURBO_SHORT 0x00000002 + +/* + * PHY agility command register + */ +#define AR5K_PHY_AGC 0x9808 +#define AR5K_PHY_AGC_DISABLE 0x08000000 + +/* + * PHY timing register [5112+] + */ +#define AR5K_PHY_TIMING_3 0x9814 +#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 +#define AR5K_PHY_TIMING_3_DSC_MAN_S 17 +#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 +#define AR5K_PHY_TIMING_3_DSC_EXP_S 13 + +/* + * PHY chip revision register + */ +#define AR5K_PHY_CHIP_ID 0x9818 + +/* + * PHY activation register + */ +#define AR5K_PHY_ACT 0x981c +#define AR5K_PHY_ACT_ENABLE 0x00000001 +#define AR5K_PHY_ACT_DISABLE 0x00000002 + +/* + * PHY signal register [5110] + */ +#define AR5K_PHY_SIG 0x9858 +#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 +#define AR5K_PHY_SIG_FIRSTEP_S 12 +#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 +#define AR5K_PHY_SIG_FIRPWR_S 18 + +/* + * PHY coarse agility control register [5110] + */ +#define AR5K_PHY_AGCCOARSE 0x985c +#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 +#define AR5K_PHY_AGCCOARSE_LO_S 7 +#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 +#define AR5K_PHY_AGCCOARSE_HI_S 15 + +/* + * PHY agility control register + */ +#define AR5K_PHY_AGCCTL 0x9860 /* Register address */ +#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ +#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ + +/* + * PHY noise floor status register + */ +#define AR5K_PHY_NF 0x9864 +#define AR5K_PHY_NF_M 0x000001ff +#define AR5K_PHY_NF_ACTIVE 0x00000100 +#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) +#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) +#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) + +/* + * PHY ADC saturation register [5110] + */ +#define AR5K_PHY_ADCSAT 0x9868 +#define AR5K_PHY_ADCSAT_ICNT 0x0001f800 +#define AR5K_PHY_ADCSAT_ICNT_S 11 +#define AR5K_PHY_ADCSAT_THR 0x000007e0 +#define AR5K_PHY_ADCSAT_THR_S 5 + +/* + * PHY sleep registers [5112+] + */ +#define AR5K_PHY_SCR 0x9870 +#define AR5K_PHY_SCR_32MHZ 0x0000001f +#define AR5K_PHY_SLMT 0x9874 +#define AR5K_PHY_SLMT_32MHZ 0x0000007f +#define AR5K_PHY_SCAL 0x9878 +#define AR5K_PHY_SCAL_32MHZ 0x0000000e + +/* + * PHY PLL control register [5111+] + */ +#define AR5K_PHY_PLL 0x987c +#define AR5K_PHY_PLL_20MHZ 0x13 /* [5111] */ +#define AR5K_PHY_PLL_40MHZ_5211 0x18 +#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa +#define AR5K_PHY_PLL_40MHZ (hal->ah_version == AR5K_AR5211 ? \ + AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) +#define AR5K_PHY_PLL_44MHZ_5211 0x19 +#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab +#define AR5K_PHY_PLL_44MHZ (hal->ah_version == AR5K_AR5211 ? \ + AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) +#define AR5K_PHY_PLL_RF5111 0x00000000 +#define AR5K_PHY_PLL_RF5112 0x00000040 + +/* + * PHY RF stage register [5110] + */ +#define AR5K_PHY_RFSTG 0x98d4 +#define AR5K_PHY_RFSTG_DISABLE 0x00000021 + +/* + * PHY receiver delay register [5111+] + */ +#define AR5K_PHY_RX_DELAY 0x9914 +#define AR5K_PHY_RX_DELAY_M 0x00003fff + +/* + * PHY timing IQ control register [5111+] + */ +#define AR5K_PHY_IQ 0x9920 +#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f +#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 +#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 +#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 +#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 +#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 +#define AR5K_PHY_IQ_RUN 0x00010000 + + +/* + * PHY PAPD probe register [5111+] + */ +#define AR5K_PHY_PAPD_PROBE 0x9930 +#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 +#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 +#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 +#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ +#define AR5K_PHY_PAPD_PROBE_TYPE_S 23 +#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 +#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 +#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 +#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 +#define AR5K_PHY_PAPD_PROBE_GAINF_S 25 + + +/* + * PHY TX power registers [5112+] + */ +#define AR5K_PHY_TXPOWER_RATE1 0x9934 +#define AR5K_PHY_TXPOWER_RATE2 0x9938 +#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c +#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 +#define AR5K_PHY_TXPOWER_RATE3 0xa234 +#define AR5K_PHY_TXPOWER_RATE4 0xa238 + +/* + * PHY frame control register [5111+] + */ +#define AR5K_PHY_FRAME_CTL_5210 0x9804 +#define AR5K_PHY_FRAME_CTL_5211 0x9944 +#define AR5K_PHY_FRAME_CTL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) +/*---[5111+]---*/ +#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 +#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 +/*---[5110]---*/ +#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 +#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 +#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 +#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 +#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 +#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 + +/* + * PHY radar detection register [5111+] + */ +#define AR5K_PHY_RADAR 0x9954 + +/* Radar enable ........ ........ ........ .......1 */ +#define AR5K_PHY_RADAR_ENABLE 0x00000001 +#define AR5K_PHY_RADAR_DISABLE 0x00000000 +#define AR5K_PHY_RADAR_ENABLE_S 0 + +/* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... +at power on. */ +#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 + +/* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1 +after DFS is enabled */ +#define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d + +/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ + * power out threshold. + * 7-bits, standard power range {0..127} in 1/2 dBm units. */ +#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 +#define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24 + +/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ + * 6-bits, dBm range {0..63} in dBm units. */ +#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 +#define AR5K_PHY_RADAR_RADARRSSITHR_S 18 + +/* Pulse height threshold ........ ......11 1111.... ........ + * 6-bits, dBm range {0..63} in dBm units. */ +#define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000 +#define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12 + +/* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... + * 6-bits, dBm range {0..63} in dBm units. */ +#define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0 +#define AR5K_PHY_RADAR_PULSERSSITHR_S 6 + +/* Inband threshold ........ ........ ........ ..11111. + * 5-bits, units unknown {0..31} (? MHz ?) */ +#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e +#define AR5K_PHY_RADAR_INBANDTHR_S 1 + +/* + * PHY antenna switch table registers [5110] + */ +#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 +#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 + +/* + * PHY clock sleep registers [5112+] + */ +#define AR5K_PHY_SCLOCK 0x99f0 +#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c +#define AR5K_PHY_SDELAY 0x99f4 +#define AR5K_PHY_SDELAY_32MHZ 0x000000ff +#define AR5K_PHY_SPENDING 0x99f8 +#define AR5K_PHY_SPENDING_RF5111 0x00000018 +#define AR5K_PHY_SPENDING_RF5112 0x00000014 + +/* + * Misc PHY/radio registers [5110 - 5111] + */ +#define AR5K_BB_GAIN_BASE 0x9b00 +#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) +#define AR5K_RF_GAIN_BASE 0x9a00 +#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) + +/* + * PHY timing IQ calibration result register [5111+] + */ +#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 +#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 +#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 + +/* + * PHY current RSSI register [5111+] + */ +#define AR5K_PHY_CURRENT_RSSI 0x9c1c + +/* + * PHY PCDAC TX power register [5112+] + */ +#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 +#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) + +/* + * PHY mode register [5111+] + */ +#define AR5K_PHY_MODE 0x0a200 +#define AR5K_PHY_MODE_MOD 0x00000001 +#define AR5K_PHY_MODE_MOD_OFDM 0 +#define AR5K_PHY_MODE_MOD_CCK 1 +#define AR5K_PHY_MODE_FREQ 0x00000002 +#define AR5K_PHY_MODE_FREQ_5GHZ 0 +#define AR5K_PHY_MODE_FREQ_2GHZ 2 +#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* [5112+] */ +#define AR5K_PHY_MODE_RAD 0x00000008 /* [5112+] */ +#define AR5K_PHY_MODE_RAD_RF5111 0 +#define AR5K_PHY_MODE_RAD_RF5112 8 +#define AR5K_PHY_MODE_XR 0x00000010 /* [5112+] */ + +/* + * PHY CCK transmit control register [5112+] + */ +#define AR5K_PHY_CCKTXCTL 0xa204 +#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 +#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 + +/* + * PHY 2GHz gain register [5112+] + */ +#define AR5K_PHY_GAIN_2GHZ 0xa20c +#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 +#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 diff --git a/ath_ioctl.h b/ath_ioctl.h new file mode 100644 index 0000000..6359248 --- /dev/null +++ b/ath_ioctl.h @@ -0,0 +1,172 @@ +/*- + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD: src/sys/dev/ath/if_athioctl.h,v 1.9 2004/12/31 22:41:45 sam Exp $ + */ + +/* + * Ioctl-related defintions for the Atheros Wireless LAN controller driver. + */ +#ifndef _DEV_ATH_ATHIOCTL_H +#define _DEV_ATH_ATHIOCTL_H + +#include + +struct ath_stats { + __u32 ast_watchdog; /* device reset by watchdog */ + __u32 ast_hardware; /* fatal hardware error interrupts */ + __u32 ast_bmiss; /* beacon miss interrupts */ + __u32 ast_bstuck; /* beacon stuck interrupts */ + __u32 ast_rxorn; /* rx overrun interrupts */ + __u32 ast_rxeol; /* rx eol interrupts */ + __u32 ast_txurn; /* tx underrun interrupts */ + __u32 ast_mib; /* mib interrupts */ + __u32 ast_intrcoal; /* interrupts coalesced */ + __u32 ast_tx_packets; /* packet sent on the interface */ + __u32 ast_tx_mgmt; /* management frames transmitted */ + __u32 ast_tx_discard; /* frames discarded prior to assoc */ + __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ + __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ + __u32 ast_tx_encap; /* tx encapsulation failed */ + __u32 ast_tx_nonode; /* tx failed 'cuz no node */ + __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ + __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ + __u32 ast_tx_linear; /* tx linearized to cluster */ + __u32 ast_tx_nodata; /* tx discarded empty frame */ + __u32 ast_tx_busdma; /* tx failed for dma resrcs */ + __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ + __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ + __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ + __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ + __u32 ast_tx_longretry;/* tx on-chip retries (long) */ + __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ + __u32 ast_tx_noack; /* tx frames with no ack marked */ + __u32 ast_tx_rts; /* tx frames with rts enabled */ + __u32 ast_tx_cts; /* tx frames with cts enabled */ + __u32 ast_tx_shortpre;/* tx frames with short preamble */ + __u32 ast_tx_altrate; /* tx frames with alternate rate */ + __u32 ast_tx_protect; /* tx frames with protection */ + __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ + __u32 ast_tx_ctsext; /* tx frames with cts extension */ + __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ + __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ + __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ + __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ + __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ + __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ + __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ + __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ + __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ + __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ + __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ + __u32 ast_rx_packets; /* packet recv on the interface */ + __u32 ast_rx_mgt; /* management frames received */ + __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ + __s8 ast_tx_rssi; /* tx rssi of last ack */ + __s8 ast_rx_rssi; /* rx rssi from histogram */ + __u32 ast_be_xmit; /* beacons transmitted */ + __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ + __u32 ast_per_cal; /* periodic calibration calls */ + __u32 ast_per_calfail;/* periodic calibration failed */ + __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ + __u32 ast_rate_calls; /* rate control checks */ + __u32 ast_rate_raise; /* rate control raised xmit rate */ + __u32 ast_rate_drop; /* rate control dropped xmit rate */ + __u32 ast_ant_defswitch;/* rx/default antenna switches */ + __u32 ast_ant_txswitch;/* tx antenna switches */ + __u32 ast_ant_rx[8]; /* rx frames with antenna */ + __u32 ast_ant_tx[8]; /* tx frames with antenna */ +}; + +struct ath_diag { + char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ + __u16 ad_id; +#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ +#define ATH_DIAG_IN 0x4000 /* copy in parameters */ +#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ +#define ATH_DIAG_ID 0x0fff + __u16 ad_in_size; /* pack to fit, yech */ + void __user *ad_in_data; + void __user *ad_out_data; + u_int ad_out_size; +}; + +/* + * Radio capture format. + */ +#define ATH_RX_RADIOTAP_PRESENT ( \ + (1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA) | \ + (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ + 0) + +struct ath_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + __u8 wr_flags; /* XXX for padding */ + __u8 wr_rate; + __le16 wr_chan_freq; + __le16 wr_chan_flags; + __u8 wr_antenna; + __u8 wr_antsignal; +}; + +#define ATH_TX_RADIOTAP_PRESENT ( \ + (1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA) | \ + (1 << IEEE80211_RADIOTAP_TX_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RTS_RETRIES) | \ + (1 << IEEE80211_RADIOTAP_DATA_RETRIES) | \ + 0) + +struct ath_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + __u8 wt_flags; /* XXX for padding */ + __u8 wt_rate; + __u8 wt_txpower; + __u8 wt_antenna; + __le16 wt_tx_flags; + __u8 wt_rts_retries; + __u8 wt_data_retries; + +}; + +#define SIOCGATHSTATS (SIOCDEVPRIVATE+0) +#define SIOCGATHDIAG (SIOCDEVPRIVATE+1) + +#endif diff --git a/ieee80211_regdomain.c b/ieee80211_regdomain.c new file mode 100644 index 0000000..f5da7cf --- /dev/null +++ b/ieee80211_regdomain.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2004, 2005 Reyk Floeter + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + */ + +/* + * Basic regulation domain extensions for the IEEE 802.11 stack + */ + +#include +#include + +#include "ieee80211_regdomain.h" + +static const struct ieee80211_regdomainmap { + enum ieee80211_regdomain dmn; + enum ieee80211_regdomain dmn5; + enum ieee80211_regdomain dmn2; +} r_map[] = { + { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, + { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, + { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, + { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, + { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, + { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, + { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, + { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, + { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, + { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, + { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, + { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, + { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, + { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, + { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, + { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, + { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, + { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, + { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, + { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, + { DMN_APL_NULL, DMN_APL1, DMN_NULL }, + { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, + { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, + { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, + { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, + { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, + { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, + { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, + { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, + { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, + { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, + { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, + { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, + { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, + { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, +}; + +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, + u16 mhz) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(r_map); i++) { + if (r_map[i].dmn == dmn) { + if (mhz >= 2000 && mhz <= 3000) + return r_map[i].dmn2; + if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && + mhz <= IEEE80211_CHANNELS_5GHZ_MAX) + return r_map[i].dmn5; + } + } + + return DMN_DEBUG; +} + +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) +{ + u32 regdomain = (u32)ieee; + + /* + * Use the default regulation domain if the value is empty + * or not supported by the net80211 regulation code. + */ + if (ieee80211_regdomain2flag(regdomain, + IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + return (u16)AR5K_TUNE_REGDOMAIN; + + /* It is supported, just return the value */ + return regdomain; +} + +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) +{ + enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; + + return ieee; +} + diff --git a/ieee80211_regdomain.h b/ieee80211_regdomain.h new file mode 100644 index 0000000..b5f67f3 --- /dev/null +++ b/ieee80211_regdomain.h @@ -0,0 +1,492 @@ +/* + * Copyright (c) 2004, 2005 Reyk Floeter + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + */ + +#ifndef _IEEE80211_REGDOMAIN_H_ +#define _IEEE80211_REGDOMAIN_H_ + +#include + +/* Default regulation domain if stored value EEPROM value is invalid */ +#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ +#define AR5K_TUNE_CTRY CTRY_DEFAULT + + +enum ieee80211_regdomain { + DMN_DEFAULT = 0x00, + DMN_NULL_WORLD = 0x03, + DMN_NULL_ETSIB = 0x07, + DMN_NULL_ETSIC = 0x08, + DMN_FCC1_FCCA = 0x10, + DMN_FCC1_WORLD = 0x11, + DMN_FCC2_FCCA = 0x20, + DMN_FCC2_WORLD = 0x21, + DMN_FCC2_ETSIC = 0x22, + DMN_FRANCE_NULL = 0x31, + DMN_FCC3_FCCA = 0x3A, + DMN_ETSI1_WORLD = 0x37, + DMN_ETSI3_ETSIA = 0x32, + DMN_ETSI2_WORLD = 0x35, + DMN_ETSI3_WORLD = 0x36, + DMN_ETSI4_WORLD = 0x30, + DMN_ETSI4_ETSIC = 0x38, + DMN_ETSI5_WORLD = 0x39, + DMN_ETSI6_WORLD = 0x34, + DMN_ETSI_NULL = 0x33, + DMN_MKK1_MKKA = 0x40, + DMN_MKK1_MKKB = 0x41, + DMN_APL4_WORLD = 0x42, + DMN_MKK2_MKKA = 0x43, + DMN_APL_NULL = 0x44, + DMN_APL2_WORLD = 0x45, + DMN_APL2_APLC = 0x46, + DMN_APL3_WORLD = 0x47, + DMN_MKK1_FCCA = 0x48, + DMN_APL2_APLD = 0x49, + DMN_MKK1_MKKA1 = 0x4A, + DMN_MKK1_MKKA2 = 0x4B, + DMN_APL1_WORLD = 0x52, + DMN_APL1_FCCA = 0x53, + DMN_APL1_APLA = 0x54, + DMN_APL1_ETSIC = 0x55, + DMN_APL2_ETSIC = 0x56, + DMN_APL5_WORLD = 0x58, + DMN_WOR0_WORLD = 0x60, + DMN_WOR1_WORLD = 0x61, + DMN_WOR2_WORLD = 0x62, + DMN_WOR3_WORLD = 0x63, + DMN_WOR4_WORLD = 0x64, + DMN_WOR5_ETSIC = 0x65, + DMN_WOR01_WORLD = 0x66, + DMN_WOR02_WORLD = 0x67, + DMN_EU1_WORLD = 0x68, + DMN_WOR9_WORLD = 0x69, + DMN_WORA_WORLD = 0x6A, + + DMN_APL1 = 0xf0000001, + DMN_APL2 = 0xf0000002, + DMN_APL3 = 0xf0000004, + DMN_APL4 = 0xf0000008, + DMN_APL5 = 0xf0000010, + DMN_ETSI1 = 0xf0000020, + DMN_ETSI2 = 0xf0000040, + DMN_ETSI3 = 0xf0000080, + DMN_ETSI4 = 0xf0000100, + DMN_ETSI5 = 0xf0000200, + DMN_ETSI6 = 0xf0000400, + DMN_ETSIA = 0xf0000800, + DMN_ETSIB = 0xf0001000, + DMN_ETSIC = 0xf0002000, + DMN_FCC1 = 0xf0004000, + DMN_FCC2 = 0xf0008000, + DMN_FCC3 = 0xf0010000, + DMN_FCCA = 0xf0020000, + DMN_APLD = 0xf0040000, + DMN_MKK1 = 0xf0080000, + DMN_MKK2 = 0xf0100000, + DMN_MKKA = 0xf0200000, + DMN_NULL = 0xf0400000, + DMN_WORLD = 0xf0800000, + DMN_DEBUG = 0xf1000000 /* used for debugging */ +}; + +#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) + +enum ieee80211_countrycode { + CTRY_DEFAULT = 0, /* Default domain (NA) */ + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_AUSTRALIA = 36, /* Australia */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CANADA = 124, /* Canada */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, /* Cyprus */ + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRI_LANKA = 728, /* Sri Lanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States */ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716, /* Zimbabwe */ +}; + +#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ +#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ +#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ +#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ + +struct ieee80211_regchannel { + u16 chan; + enum ieee80211_regdomain domain; + u32 mode; +}; + +#define IEEE80211_CHANNELS_2GHZ { \ +/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \ + \ +/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +} + +#define IEEE80211_CHANNELS_5GHZ { \ +/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \ + \ +/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \ + \ +/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \ + \ +/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \ + \ +/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \ + \ +/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \ +/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \ +/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \ +/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ +} + +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); + +#endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ diff --git a/openhal/ath5k.h b/openhal/ath5k.h deleted file mode 100644 index 012bb46..0000000 --- a/openhal/ath5k.h +++ /dev/null @@ -1,1096 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AR5K_H -#define _AR5K_H - -/* Set this to 1 to disable regulatory domain restrictions for channel tests. - * WARNING: This is for debuging only and has side effects (eg. scan takes too - * long and results timeouts). It's also illegal to tune to some of the - * supported frequencies in some countries, so use this at your own risk, - * you've been warned. */ -#define CHAN_DEBUG 0 - -/* Uncomment this for debuging (warning that it results in TOO much output) */ -/*#define AR5K_DEBUG 1 */ - -#include -#include - -#include "ath5k_hw.h" -#include "ieee80211_regdomain.h" - -/* PCI IDs */ -#ifndef PCI_VENDOR_ID_ATHEROS -#define PCI_VENDOR_ID_ATHEROS 0x168c -#endif -#ifndef PCI_VENDOR_ID_3COM_2 -#define PCI_VENDOR_ID_3COM_2 0xa727 -#endif - -#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ -#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ -#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ -#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ -#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ -#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ -#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ -#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ - -/****************************\ - GENERIC DRIVER DEFINITIONS -\****************************/ - -#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) -#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) -#ifdef AR5K_DEBUG -#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) -#else -#define AR5K_TRACE -#endif -#define howmany(x, y) (((x)+((y)-1))/(y)) - -/* - * Some tuneable values (these should be changeable by the user) - */ -#define AR5K_TUNE_DMA_BEACON_RESP 2 -#define AR5K_TUNE_SW_BEACON_RESP 10 -#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 -#define AR5K_TUNE_RADAR_ALERT false -#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 -#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) -#define AR5K_TUNE_RSSI_THRES 1792 -#define AR5K_TUNE_REGISTER_TIMEOUT 20000 -#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 -#define AR5K_TUNE_BEACON_INTERVAL 100 -#define AR5K_TUNE_AIFS 2 -#define AR5K_TUNE_AIFS_11B 2 -#define AR5K_TUNE_AIFS_XR 0 -#define AR5K_TUNE_CWMIN 15 -#define AR5K_TUNE_CWMIN_11B 31 -#define AR5K_TUNE_CWMIN_XR 3 -#define AR5K_TUNE_CWMAX 1023 -#define AR5K_TUNE_CWMAX_11B 1023 -#define AR5K_TUNE_CWMAX_XR 7 -#define AR5K_TUNE_NOISE_FLOOR -72 -#define AR5K_TUNE_MAX_TXPOWER 60 -#define AR5K_TUNE_DEFAULT_TXPOWER 30 -#define AR5K_TUNE_TPC_TXPOWER true -#define AR5K_TUNE_ANT_DIVERSITY true -#define AR5K_TUNE_HWTXTRIES 4 - -/* token to use for aifs, cwmin, cwmax in MadWiFi */ -#define AR5K_TXQ_USEDEFAULT ((u32) -1) - -/* GENERIC CHIPSET DEFINITIONS */ - -/* MAC Chips */ -enum ath5k_version { - AR5K_AR5210 = 0, - AR5K_AR5211 = 1, - AR5K_AR5212 = 2, -}; - -/* PHY Chips */ -enum ath5k_radio { - AR5K_RF5110 = 0, - AR5K_RF5111 = 1, - AR5K_RF5112 = 2, -}; - -/* - * Common silicon revision/version values - */ -enum ath5k_srev_type { - AR5K_VERSION_VER, - AR5K_VERSION_REV, - AR5K_VERSION_RAD, - AR5K_VERSION_DEV -}; - -struct ath5k_srev_name { - const char *sr_name; - enum ath5k_srev_type sr_type; - u_int sr_val; -}; - -#define AR5K_SREV_NAME { \ - { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ - { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ - { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ - { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ - { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ - { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ - { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ - { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ - { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ - { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ - { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ - { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ - { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ - { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ - { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ - { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ - { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ - { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ - { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ - { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ -} - -#define AR5K_SREV_UNKNOWN 0xffff - -#define AR5K_SREV_VER_AR5210 0x00 -#define AR5K_SREV_VER_AR5311 0x10 -#define AR5K_SREV_VER_AR5311A 0x20 -#define AR5K_SREV_VER_AR5311B 0x30 -#define AR5K_SREV_VER_AR5211 0x40 -#define AR5K_SREV_VER_AR5212 0x50 -#define AR5K_SREV_VER_AR5213 0x55 -#define AR5K_SREV_VER_UNSUPP 0x60 - -#define AR5K_SREV_RAD_5110 0x00 -#define AR5K_SREV_RAD_5111 0x10 -#define AR5K_SREV_RAD_5111A 0x15 -#define AR5K_SREV_RAD_2111 0x20 -#define AR5K_SREV_RAD_5112 0x30 -#define AR5K_SREV_RAD_5112A 0x35 -#define AR5K_SREV_RAD_2112 0x40 -#define AR5K_SREV_RAD_2112A 0x45 -#define AR5K_SREV_RAD_UNSUPP 0x50 - - -/* IEEE defs */ - -#define IEEE80211_MAX_LEN 2500 - -#define MAX_PDU_LENGTH IEEE80211_MAX_LEN -#define MODULATION_CCK IEEE80211_RATE_CCK -#define MODULATION_OFDM IEEE80211_RATE_OFDM -#define MODULATION_TURBO IEEE80211_RATE_TURBO -#define MODULATION_XR 0x00000200 /*XR thingie*/ -#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ - -#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code - enables short preamble, see ar5212_reg.h */ -#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) -#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 - -/****************\ - TX DEFINITIONS -\****************/ - -/* - * Tx Descriptor - */ -struct ath_tx_status { - u16 ts_seqnum; - u16 ts_tstamp; - u8 ts_status; - u8 ts_rate; - s8 ts_rssi; - u8 ts_shortretry; - u8 ts_longretry; - u8 ts_virtcol; - u8 ts_antenna; -}; - -#define AR5K_TXSTAT_ALTRATE 0x80 -#define AR5K_TXERR_XRETRY 0x01 -#define AR5K_TXERR_FILT 0x02 -#define AR5K_TXERR_FIFO 0x04 - -/* - * Queue types used to classify tx queues. - */ -enum ath5k_tx_queue { - AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ - AR5K_TX_QUEUE_DATA, /*A normal data queue*/ - AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ - AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ - AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ - AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ -}; - -#define AR5K_NUM_TX_QUEUES 10 -#define AR5K_NUM_TX_QUEUES_NOQCU 2 - -/* - * Queue syb-types to classify normal data queues. - * These are the 4 Access Categories as defined in - * WME spec. 0 is the lowest priority and 4 is the - * highest. Normal data that hasn't been classified - * goes to the Best Effort AC. - */ -enum ath5k_tx_queue_subtype { - AR5K_WME_AC_BK = 0, /*Background traffic*/ - AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ - AR5K_WME_AC_VI, /*Video traffic*/ - AR5K_WME_AC_VO, /*Voice traffic*/ -}; - -/* - * Queue ID numbers as returned by the HAL, each number - * represents a hw queue. If hw does not support hw queues - * (eg 5210) all data goes in one queue. These match - * d80211 definitions (net80211/MadWiFi don't use them). - */ -enum ath5k_tx_queue_id { - AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, - AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, - AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ - AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ - AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ - AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ - AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ - AR5K_TX_QUEUE_ID_UAPSD = 8, - AR5K_TX_QUEUE_ID_XR_DATA = 9, -}; - - -/* - * Flags to set hw queue's parameters... - */ -#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ -#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ -#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ -#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ -#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ -#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ -#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ -#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ - -/* - * A struct to hold tx queue's parameters - */ -struct ath5k_txq_info { - enum ath5k_tx_queue tqi_type; - enum ath5k_tx_queue_subtype tqi_subtype; - u16 tqi_flags; /* Tx queue flags (see above) */ - u32 tqi_aifs; /* Arbitrated Interframe Space */ - s32 tqi_cw_min; /* Minimum Contention Window */ - s32 tqi_cw_max; /* Maximum Contention Window */ - u32 tqi_cbr_period; /* Constant bit rate period */ - u32 tqi_cbr_overflow_limit; - u32 tqi_burst_time; - u32 tqi_ready_time; /* Not used */ - u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ -}; - -/* - * Transmit packet types. - * These are not fully used inside OpenHAL yet - */ -enum ath5k_pkt_type { - AR5K_PKT_TYPE_NORMAL = 0, - AR5K_PKT_TYPE_ATIM = 1, - AR5K_PKT_TYPE_PSPOLL = 2, - AR5K_PKT_TYPE_BEACON = 3, - AR5K_PKT_TYPE_PROBE_RESP = 4, - AR5K_PKT_TYPE_PIFS = 5, -}; - -/* - * TX power and TPC settings - */ -#define AR5K_TXPOWER_OFDM(_r, _v) ( \ - ((0 & 1) << ((_v) + 6)) | \ - (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ -) - -#define AR5K_TXPOWER_CCK(_r, _v) ( \ - (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ -) - -/* - * Used to compute TX times - */ -#define AR5K_CCK_SIFS_TIME 10 -#define AR5K_CCK_PREAMBLE_BITS 144 -#define AR5K_CCK_PLCP_BITS 48 - -#define AR5K_OFDM_SIFS_TIME 16 -#define AR5K_OFDM_PREAMBLE_TIME 20 -#define AR5K_OFDM_PLCP_BITS 22 -#define AR5K_OFDM_SYMBOL_TIME 4 - -#define AR5K_TURBO_SIFS_TIME 8 -#define AR5K_TURBO_PREAMBLE_TIME 14 -#define AR5K_TURBO_PLCP_BITS 22 -#define AR5K_TURBO_SYMBOL_TIME 4 - -#define AR5K_XR_SIFS_TIME 16 -#define AR5K_XR_PLCP_BITS 22 -#define AR5K_XR_SYMBOL_TIME 4 - -/* CCK */ -#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) - -#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ - ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ - (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) - -#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ - AR5K_CCK_PHY_TIME(_sp) + \ - ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ - AR5K_CCK_SIFS_TIME - -/* OFDM */ -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_OFDM_SYMBOL_TIME) / 1000) - -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ - AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ - (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) - -/* TURBO */ -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ - AR5K_TURBO_SYMBOL_TIME) / 1000) - -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ - AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ - AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ - (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) - -/* eXtendent Range (?)*/ -#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) - -#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_XR_SYMBOL_TIME) / 1000) - -#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ - AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ - (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) - -/* - * DMA size definitions (2^n+2) - */ -enum ath5k_dmasize { - AR5K_DMASIZE_4B = 0, - AR5K_DMASIZE_8B, - AR5K_DMASIZE_16B, - AR5K_DMASIZE_32B, - AR5K_DMASIZE_64B, - AR5K_DMASIZE_128B, - AR5K_DMASIZE_256B, - AR5K_DMASIZE_512B -}; - - -/****************\ - RX DEFINITIONS -\****************/ - -/* - * Rx Descriptor - */ -struct ath_rx_status { - u16 rs_datalen; - u16 rs_tstamp; - u8 rs_status; - u8 rs_phyerr; - s8 rs_rssi; - u8 rs_keyix; - u8 rs_rate; - u8 rs_antenna; - u8 rs_more; -}; - -#define AR5K_RXERR_CRC 0x01 -#define AR5K_RXERR_PHY 0x02 -#define AR5K_RXERR_FIFO 0x04 -#define AR5K_RXERR_DECRYPT 0x08 -#define AR5K_RXERR_MIC 0x10 -#define AR5K_RXKEYIX_INVALID ((u8) - 1) -#define AR5K_TXKEYIX_INVALID ((u32) - 1) - -/* - * RX filters - * Most of them are not yet used inside OpenHAL - */ -#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ -#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ -#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ -#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ -#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ -#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ -#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame */ -#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests */ -#define AR5K_RX_FILTER_PHYERROR 0x00000100 /* Don't filter phy errors */ -#define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ - -struct ath5k_mib_stats { - u32 ackrcv_bad; - u32 rts_bad; - u32 rts_good; - u32 fcs_bad; - u32 beacons; -}; - - - - -/**************************\ - BEACON TIMERS DEFINITIONS -\**************************/ - -#define AR5K_BEACON_PERIOD 0x0000ffff -#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ -#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ - -/* - * Per-station beacon timer state. - */ -struct ath5k_beacon_state { - u32 bs_next_beacon; - u32 bs_next_dtim; - u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- - can also include the above flags*/ - u8 bs_dtim_period; - u8 bs_cfp_period; - u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with - a Point Coordination Function capable AP*/ - u16 bs_cfp_du_remain; - u16 bs_tim_offset; - u16 bs_sleep_duration; - u16 bs_bmiss_threshold; - u32 bs_cfp_next; -}; - - - - -/********************\ - COMMON DEFINITIONS -\********************/ - -/* - * Atheros descriptor - */ -struct ath_desc { - u32 ds_link; - u32 ds_data; - u32 ds_ctl0; - u32 ds_ctl1; - u32 ds_hw[4]; - - union { - struct ath_rx_status rx; - struct ath_tx_status tx; - } ds_us; - -#define ds_rxstat ds_us.rx -#define ds_txstat ds_us.tx - -} __packed; - -#define AR5K_RXDESC_INTREQ 0x0020 - -#define AR5K_TXDESC_CLRDMASK 0x0001 -#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ -#define AR5K_TXDESC_RTSENA 0x0004 -#define AR5K_TXDESC_CTSENA 0x0008 -#define AR5K_TXDESC_INTREQ 0x0010 -#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ - -#define AR5K_SLOT_TIME_9 396 -#define AR5K_SLOT_TIME_20 880 -#define AR5K_SLOT_TIME_MAX 0xffff - -/* channel_flags */ -#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ -#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ -#define CHANNEL_CCK 0x0020 /* CCK channel */ -#define CHANNEL_OFDM 0x0040 /* OFDM channel */ -#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ -#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ -#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ -#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ -#define CHANNEL_XR 0x0800 /* XR channel */ - -#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) -#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) -#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) -#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_108A CHANNEL_T -#define CHANNEL_108G CHANNEL_TG -#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) - -#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ - CHANNEL_5GHZ | CHANNEL_TURBO) - -#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) -#define CHANNEL_MODES CHANNEL_ALL - -/* - * Used internaly in OpenHAL (ar5211.c/ar5212.c - * for reset_tx_queue). Also see struct struct ieee80211_channel. - */ -#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) -#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) - -/* - * The following structure will be used to map 2GHz channels to - * 5GHz Atheros channels. - */ -struct ath5k_athchan_2ghz { - u32 a2_flags; - u16 a2_athchan; -}; - -/* - * Rate definitions - */ - -#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ - -struct ath5k_rate { - u8 valid; /* Valid for rate control */ - u32 modulation; - u16 rate_kbps; - u8 rate_code; /* Rate mapping for h/w descriptors */ - u8 dot11_rate; - u8 control_rate; - u16 lp_ack_duration;/* long preamble ACK duration */ - u16 sp_ack_duration;/* short preamble ACK duration*/ -}; - -struct ath5k_rate_table { - u16 rate_count; - u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ - struct ath5k_rate rates[AR5K_MAX_RATES]; -}; - -/* - * Rate tables... - */ -#define AR5K_RATES_11A { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_11B { 4, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ -} - -#define AR5K_RATES_11G { 12, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ - { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ - { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -#define AR5K_RATES_TURBO { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ - { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ - { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ - { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ - { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ - { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ - { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ - { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_XR { 12, { \ - 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_XR, 500, 7, 129, 0 }, \ - { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ - { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ - { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ - { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -/* - * Crypto definitions - */ - -#define AR5K_KEYCACHE_SIZE 8 - -/***********************\ - HW RELATED DEFINITIONS -\***********************/ - -/* - * Misc definitions - */ -#define AR5K_RSSI_EP_MULTIPLIER (1<<7) - -#define AR5K_ASSERT_ENTRY(_e, _s) do { \ - if (_e >= _s) \ - return (false); \ -} while (0) - - -struct ath5k_node_stats { - u32 ns_avgbrssi; /* average beacon rssi */ - u32 ns_avgrssi; /* average data rssi */ - u32 ns_avgtxrssi; /* average tx rssi */ -}; - -enum ath5k_ant_setting { - AR5K_ANT_VARIABLE = 0, /* variable by programming */ - AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ - AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ - AR5K_ANT_MAX = 3, -}; - -/* - * HAL interrupt abstraction - */ - -/* - * These are mapped to take advantage of some common bits - * between the MAC chips, to be able to set intr properties - * easier. Some of them are not used yet inside OpenHAL. - */ -enum ath5k_int { - AR5K_INT_RX = 0x00000001, - AR5K_INT_RXDESC = 0x00000002, - AR5K_INT_RXNOFRM = 0x00000008, - AR5K_INT_RXEOL = 0x00000010, - AR5K_INT_RXORN = 0x00000020, - AR5K_INT_TX = 0x00000040, - AR5K_INT_TXDESC = 0x00000080, - AR5K_INT_TXURN = 0x00000800, - AR5K_INT_MIB = 0x00001000, - AR5K_INT_RXPHY = 0x00004000, - AR5K_INT_RXKCM = 0x00008000, - AR5K_INT_SWBA = 0x00010000, - AR5K_INT_BMISS = 0x00040000, - AR5K_INT_BNR = 0x00100000, - AR5K_INT_GPIO = 0x01000000, - AR5K_INT_FATAL = 0x40000000, - AR5K_INT_GLOBAL = 0x80000000, - - /*A sum of all the common bits*/ - AR5K_INT_COMMON = AR5K_INT_RXNOFRM - | AR5K_INT_RXDESC - | AR5K_INT_RXEOL - | AR5K_INT_RXORN - | AR5K_INT_TXURN - | AR5K_INT_TXDESC - | AR5K_INT_MIB - | AR5K_INT_RXPHY - | AR5K_INT_RXKCM - | AR5K_INT_SWBA - | AR5K_INT_BMISS - | AR5K_INT_GPIO, - AR5K_INT_NOCARD = 0xffffffff /*Declare that the card - has been removed*/ -}; - -/* - * Power management - */ -enum ath5k_power_mode { - AR5K_PM_UNDEFINED = 0, - AR5K_PM_AUTO, - AR5K_PM_AWAKE, - AR5K_PM_FULL_SLEEP, - AR5K_PM_NETWORK_SLEEP, -}; - -/* - * These match net80211 definitions (not used in - * d80211). - */ -#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ -#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ -#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ -#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ -#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ - -/* GPIO-controlled software LED */ -#define AR5K_SOFTLED_PIN 0 -#define AR5K_SOFTLED_ON 0 -#define AR5K_SOFTLED_OFF 1 - -/* - * Chipset capabilities -see ath_hal_getcapability- - * get_capability function is not yet fully implemented - * in OpenHAL so most of these don't work yet... - */ -enum ath5k_capability_type { - AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ - AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ - AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ - AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ - AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ - AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ - AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ - AR5K_CAP_COMPRESSION = 8, /* Supports compression */ - AR5K_CAP_BURST = 9, /* Supports packet bursting */ - AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ - AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ - AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ - AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ - AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ - AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ - AR5K_CAP_XR = 16, /* Supports XR mode */ - AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ - AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ - AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ - AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ -}; - -struct ath5k_capabilities { - /* - * Supported PHY modes - * (ie. CHANNEL_A, CHANNEL_B, ...) - */ - DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); - - /* - * Frequency range (without regulation restrictions) - */ - struct { - u16 range_2ghz_min; - u16 range_2ghz_max; - u16 range_5ghz_min; - u16 range_5ghz_max; - } cap_range; - - /* - * Active regulation domain settings - */ - struct { - enum ieee80211_regdomain reg_current; - enum ieee80211_regdomain reg_hw; - } cap_regdomain; - - /* - * Values stored in the EEPROM (some of them...) - */ - struct ath5k_eeprom_info cap_eeprom; - - /* - * Queue information - */ - struct { - u8 q_tx_num; - } cap_queues; -}; - - -/***************************************\ - HARDWARE ABSTRACTION LAYER STRUCTURE -\***************************************/ - -/* - * Misc defines - */ - -#define AR5K_MAX_GPIO 10 -#define AR5K_MAX_RF_BANKS 8 - -struct ath_hw { - u32 ah_magic; - - void *ah_sc; - void __iomem *ah_sh; - enum ieee80211_countrycode ah_country_code; - - enum ath5k_int ah_imr; - - enum ieee80211_if_types ah_op_mode; - enum ath5k_power_mode ah_power_mode; - struct ieee80211_channel ah_current_channel; - bool ah_turbo; - bool ah_calibration; - bool ah_running; - bool ah_single_chip; - enum ath5k_rfgain ah_rf_gain; - - u32 ah_mac_srev; - u16 ah_mac_version; - u16 ah_mac_revision; - u16 ah_phy_revision; - u16 ah_radio_5ghz_revision; - u16 ah_radio_2ghz_revision; - - enum ath5k_version ah_version; - enum ath5k_radio ah_radio; - u32 ah_phy; - - bool ah_5ghz; - bool ah_2ghz; - -#define ah_regdomain ah_capabilities.cap_regdomain.reg_current -#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw -#define ah_modes ah_capabilities.cap_mode -#define ah_ee_version ah_capabilities.cap_eeprom.ee_version - - u32 ah_atim_window; - u32 ah_aifs; - u32 ah_cw_min; - u32 ah_cw_max; - bool ah_software_retry; - u32 ah_limit_tx_retries; - - u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; - bool ah_ant_diversity; - - u8 ah_sta_id[ETH_ALEN]; - u8 ah_bssid[ETH_ALEN]; - - u32 ah_gpio[AR5K_MAX_GPIO]; - int ah_gpio_npins; - - struct ath5k_capabilities ah_capabilities; - - struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; - u32 ah_txq_interrupts; - - u32 *ah_rf_banks; - size_t ah_rf_banks_size; - struct ath5k_gain ah_gain; - u32 ah_offset[AR5K_MAX_RF_BANKS]; - - struct { - u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; - u16 txp_rates[AR5K_MAX_RATES]; - s16 txp_min, txp_max; - bool txp_tpc; - s16 txp_ofdm; - } ah_txpower; - - struct { - bool r_enabled; - int r_last_alert; - struct ieee80211_channel r_last_channel; - } ah_radar; - - /* - * Function pointers - */ - int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int); - bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int); - int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool); - int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); - int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *); -}; - -/* - * Prototypes - */ -typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ieee80211_channel *, - unsigned int); - -/* General Functions */ -u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); -/* Attach/Detach Functions */ -struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); -const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); -void ath5k_hw_detach(struct ath_hw *hal); -/* Reset Functions */ -int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); -/* Power management functions */ -int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); -enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); -/* DMA Related Functions */ -void ath5k_hw_start_rx(struct ath_hw *hal); -int ath5k_hw_stop_rx_dma(struct ath_hw *hal); -u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); -void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); -int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); -u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); -int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); -bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); -/* Interrupt handling */ -bool ath5k_hw_is_intr_pending(struct ath_hw *hal); -int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); -enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); -void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); -/* EEPROM access functions */ -u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); -int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); -int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); -/* Protocol Control Unit Functions */ -void ath5k_hw_set_opmode(struct ath_hw *hal); -/* BSSID Functions */ -void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); -bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); -void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); -bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); -/* Receive start/stop functions */ -void ath5k_hw_start_rx_pcu(struct ath_hw *hal); -void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); -/* RX Filter functions */ -void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); -bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); -bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); -u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); -void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); -/* Beacon related functions */ -u32 ath5k_hw_get_tsf32(struct ath_hw *hal); -u64 ath5k_hw_get_tsf64(struct ath_hw *hal); -void ath5k_hw_reset_tsf(struct ath_hw *hal); -void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); -void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); -void ath5k_hw_reset_beacon(struct ath_hw *hal); -bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); -void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); -/* ACK/CTS Timeouts */ -bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); -unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); -bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); -unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); -/* Key table (WEP) functions */ -int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); -int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); -int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); -int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); -/* Queue Control Unit, DFS Control Unit Functions */ -int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); -int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); -bool ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); -void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); -u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); -unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); -/* Hardware Descriptor Functions */ -/* RX Descriptor */ -int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); -/* GPIO Functions */ -void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); -bool ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); -bool ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); -u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); -bool ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); -void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); -/* Regulatory Domain/Channels Setup */ -unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); -unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); -bool ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags); -bool ath_hal_init_channels(struct ath_hw *hal, struct ieee80211_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); -u16 ath5k_get_regdomain(struct ath_hw *hal); -/* PHY/RF access functions */ -bool ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel); -bool ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan); -bool ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_phy_disable(struct ath_hw *hal); -void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); -unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); -unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 first, u32 col, bool set); -u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal); -bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal); -s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal); -bool ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); -bool ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); -bool ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); -void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, unsigned int ee_mode); -bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); -enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); -/* Misc functions */ -int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); -void ath5k_hw_dump_state(struct ath_hw *hal); -int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); -int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting); -bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); -bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); -bool ath5k_hw_disable_pspoll(struct ath_hw *hal); -#endif /* _AR5K_H */ diff --git a/openhal/ath5k_hw.c b/openhal/ath5k_hw.c deleted file mode 100644 index db1d888..0000000 --- a/openhal/ath5k_hw.c +++ /dev/null @@ -1,5825 +0,0 @@ - /* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for Atheros Wireless LAN devices. - * (Please have a look at ar5xxx.h for further information) - */ - -#include - -#include -#include - -#include "ath5k.h" -#include "ath5kreg.h" - -/*Rate tables*/ -static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; -static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; -static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G; -static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; -static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; - -/*Prototypes*/ -static int ath5k_hw_nic_reset(struct ath_hw *, u32); -static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool); -static u16 ath5k_hw_radio_revision(struct ath_hw *, unsigned int); -static int ath5k_hw_txpower(struct ath_hw *, struct ieee80211_channel *, unsigned int); -static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, - unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int); -static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int); -static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool); -static int ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *); -static int ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, - unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int); -static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool); -static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *); -static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *); -static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *); -static int ath5k_hw_get_capabilities(struct ath_hw *); - -static int ath5k_eeprom_init(struct ath_hw *); -static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *); - -/* - * Initial register dumps - */ -static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI; -static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE; -static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI; -static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE; -static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF; -static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI; - -/* - * Initial gain optimization values - */ -static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT; -static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT; - -/* - * Initial register for the radio chipsets - */ -static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF; -static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF; -static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF; -static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; - -/* - * Enable to overwrite the country code (use "00" for debug) - */ -#if 0 -#define COUNTRYCODE "00" -#endif - -/*******************\ - General Functions -\*******************/ - - -/* - * Calculate transmition time of a frame - * TODO: Left here for combatibility, change it in ath5k - */ -u16 /*TODO: Is this really hardware dependent ?*/ -ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, - u32 frame_length, u16 rate_index, bool short_preamble) -{ - const struct ath5k_rate *rate; - u32 value; - - AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); - - /* - * Get rate by index - */ - rate = &rates->rates[rate_index]; - - /* - * Calculate the transmission time by operation (PHY) mode - */ - switch (rate->modulation) { - case MODULATION_CCK: - /* - * CCK / DS mode (802.11b) - */ - value = AR5K_CCK_TX_TIME(rate->rate_kbps, frame_length, - (short_preamble && (rate->modulation == MODULATION_CCK_SP))); - break; - - case MODULATION_OFDM: - /* - * Orthogonal Frequency Division Multiplexing - */ - if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return 0; - value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length); - break; - - case MODULATION_TURBO: - /* - * Orthogonal Frequency Division Multiplexing - * Atheros "Turbo Mode" (doubled rates) - */ - if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return 0; - value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length); - break; - - case MODULATION_XR: - /* - * Orthogonal Frequency Division Multiplexing - * Atheros "eXtended Range" (XR) - */ - if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return 0; - value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length); - break; - - default: - return 0; - } - - return value; -} - -/* - * Functions used internaly - */ - -static u32 -ath5k_hw_bitswap(u32 val, unsigned int bits) -{ - u32 retval = 0, bit, i; - - for (i = 0; i < bits; i++) { - bit = (val >> i) & 1; - retval = (retval << 1) | bit; - } - - return retval; -} - -static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) -{ - return turbo == true ? (usec * 80) : (usec * 40); -} - -static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) -{ - return turbo == true ? (clock / 80) : (clock / 40); -} - -/* - * Read from a device register - */ -static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg) -{ - return readl(hal->ah_sh + reg); -} - -/* - * Write to a device register - */ -static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg) -{ - writel(val, hal->ah_sh + reg); -} - -static inline __u16 ath5k_hw_unaligned_read_16(__le16 *p) -{ - return le16_to_cpu(get_unaligned(p)); -} - -static inline void ath5k_hw_unaligned_write_16(__u16 v, __le16* p) -{ - put_unaligned(cpu_to_le16(v), p); -} - -static inline __u32 ath5k_hw_unaligned_read_32(__le32 *p) -{ - return le32_to_cpu(get_unaligned(p)); -} - -static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) -{ - put_unaligned(cpu_to_le32(v), p); -} - -/* - * Check if a register write has been completed - */ -static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, - u32 val, bool is_set) -{ - int i; - u32 data; - - for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { - data = ath5k_hw_reg_read(hal, reg); - if ((is_set == true) && (data & flag)) - break; - else if ((data & flag) == val) - break; - udelay(15); - } - - return (i <= 0) ? -EAGAIN : 0; -} - - - -/***************************************\ - Attach/Detach Functions -\***************************************/ - -/* - * Check if the device is supported and initialize the needed structs - */ -struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, - void __iomem *sh) -{ - struct ath_hw *hal; - u8 mac[ETH_ALEN]; - int ret; - u32 srev; - - /*TODO:Use eeprom_magic to verify chipset*/ - - /*If we passed the test malloc a hal struct*/ - hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); - if (hal == NULL) { - ret = -ENOMEM; - AR5K_PRINT("out of memory\n"); - goto err; - } - - hal->ah_sc = sc; - hal->ah_sh = sh; - - /* - * HAL information - */ - - /* Regulation Stuff */ - hal->ah_country_code = AR5K_TUNE_CTRY; - ath5k_get_regdomain(hal); - - hal->ah_op_mode = IEEE80211_IF_TYPE_STA; - hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; - hal->ah_turbo = false; - hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; - hal->ah_imr = 0; - hal->ah_atim_window = 0; - hal->ah_aifs = AR5K_TUNE_AIFS; - hal->ah_cw_min = AR5K_TUNE_CWMIN; - hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; - hal->ah_software_retry = false; - hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; - - switch (device) { - case PCI_DEVICE_ID_ATHEROS_AR2413: - case PCI_DEVICE_ID_ATHEROS_AR5413: - case PCI_DEVICE_ID_ATHEROS_AR5424: - /* - * Known single chip solutions - */ - hal->ah_single_chip = true; - break; - default: - /* - * Multi chip solutions - */ - hal->ah_single_chip = false; - break; - } - - /* - * Set the mac revision based on the pci id - */ - hal->ah_version = mac_version; - - /*Fill the hal struct with the needed functions*/ - if (hal->ah_version == AR5K_AR5212) - hal->ah_magic = AR5K_EEPROM_MAGIC_5212; - else if (hal->ah_version == AR5K_AR5211) - hal->ah_magic = AR5K_EEPROM_MAGIC_5211; - - if (hal->ah_version == AR5K_AR5212) { - hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; - hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; - hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc; - hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; - } else { - hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; - hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; - hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc; - hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; - } - - if (hal->ah_version == AR5K_AR5212) - hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; - else if (hal->ah_version <= AR5K_AR5211) - hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; - - /* Bring device out of sleep and reset it's units */ - ret = ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true); - if (ret) - goto err_free; - - /* Get MAC, PHY and RADIO revisions */ - srev = ath5k_hw_reg_read(hal, AR5K_SREV); - hal->ah_mac_srev = srev; - hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); - hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); - hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff; - hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ); - - if (hal->ah_version == AR5K_AR5210) { - hal->ah_radio_2ghz_revision = 0; - } else { - hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal, - CHANNEL_2GHZ); - } - - /* Single chip radio */ - if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) - hal->ah_radio_2ghz_revision = 0; - - /* Identify the radio chip*/ - if (hal->ah_version == AR5K_AR5210) - hal->ah_radio = AR5K_RF5110; - else - hal->ah_radio = hal->ah_radio_5ghz_revision < - AR5K_SREV_RAD_5112 ? AR5K_RF5111 : AR5K_RF5112; - - hal->ah_phy = AR5K_PHY(0); - - /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a - * temporary variable for setting our BSSID. Right bellow we update - * it with ath5k_hw_get_lladdr() */ - memset(mac, 0xff, ETH_ALEN); - ath5k_hw_set_associd(hal, mac, 0); - - ath5k_hw_get_lladdr(hal, mac); - ath5k_hw_set_opmode(hal); - -#ifdef AR5K_DEBUG - hal->ah_dump_state(hal); -#endif - - /* - * Get card capabilities, values, ... - */ - - ret = ath5k_eeprom_init(hal); - if (ret) { - AR5K_PRINT("unable to init EEPROM\n"); - goto err_free; - } - - /* Get misc capabilities */ - ret = ath5k_hw_get_capabilities(hal); - if (ret) { - AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", - device); - goto err_free; - } - - /* Get MAC address */ - ret = ath5k_eeprom_read_mac(hal, mac); - if (ret) { - AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", - device); - goto err_free; - } - - ath5k_hw_set_lladdr(hal, mac); - - /* Initialize the gain optimization values */ - /*For RF5111*/ - if (hal->ah_radio == AR5K_RF5111) { - hal->ah_gain.g_step_idx = rf5111_gain_opt.go_default; - hal->ah_gain.g_step = - &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; - hal->ah_gain.g_low = 20; - hal->ah_gain.g_high = 35; - hal->ah_gain.g_active = 1; - /*For RF5112*/ - } else if (hal->ah_radio == AR5K_RF5112) { - hal->ah_gain.g_step_idx = rf5112_gain_opt.go_default; - hal->ah_gain.g_step = - &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; - hal->ah_gain.g_low = 20; - hal->ah_gain.g_high = 85; - hal->ah_gain.g_active = 1; - } - - return hal; -err_free: - kfree(hal); -err: - return ERR_PTR(ret); -} - -/* - * Bring up MAC + PHY Chips - */ -static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) -{ - u32 turbo, mode, clock; - int ret; - - turbo = 0; - mode = 0; - clock = 0; - - AR5K_TRACE; - - if (hal->ah_version != AR5K_AR5210) { - /* - * Get channel mode flags - */ - - if (hal->ah_radio >= AR5K_RF5112) { - mode = AR5K_PHY_MODE_RAD_RF5112; - clock = AR5K_PHY_PLL_RF5112; - } else { - mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ - clock = AR5K_PHY_PLL_RF5111; /*Zero*/ - } - - if (flags & CHANNEL_2GHZ) { - mode |= AR5K_PHY_MODE_FREQ_2GHZ; - clock |= AR5K_PHY_PLL_44MHZ; - } else if (flags & CHANNEL_5GHZ) { - mode |= AR5K_PHY_MODE_FREQ_5GHZ; - clock |= AR5K_PHY_PLL_40MHZ; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return -EINVAL; - } - - if (flags & CHANNEL_CCK) { - mode |= AR5K_PHY_MODE_MOD_CCK; - } else if (flags & CHANNEL_G) { - /* Dynamic OFDM/CCK is not supported by the AR5211 */ - if (hal->ah_version == AR5K_AR5211) { - mode |= AR5K_PHY_MODE_MOD_OFDM; - } else { - mode |= AR5K_PHY_MODE_MOD_DYN; - } - } else if (flags & CHANNEL_OFDM) { - mode |= AR5K_PHY_MODE_MOD_OFDM; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return -EINVAL; - } - - if (flags & CHANNEL_TURBO) { - turbo = AR5K_PHY_TURBO_MODE | - AR5K_PHY_TURBO_SHORT; - } - } - - /* - * Reset and wakeup the device - */ - - else { - if (initial == true) { - /* ...reset hardware */ - if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) { - AR5K_PRINT("failed to reset the PCI chipset\n"); - return -EIO; - } - - mdelay(1); - } - - /* ...wakeup */ - ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); - if (ret) { - AR5K_PRINT("failed to resume the MAC Chip\n"); - return ret; - } - - /* ...enable Atheros turbo mode if requested */ - if (flags & CHANNEL_TURBO) - ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO); - - /* ...reset chipset */ - if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) { - AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return -EIO; - } - - mdelay(1); - } - - /* ...reset chipset and PCI device */ - if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal, - AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) { - AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); - return -EIO; - } - - if (hal->ah_version == AR5K_AR5210) - udelay(2300); - - /* ...wakeup */ - ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0); - if (ret) { - AR5K_PRINT("failed to resume the MAC Chip\n"); - return ret; - } - - /* ...final warm reset */ - if (ath5k_hw_nic_reset(hal, 0)) { - AR5K_PRINT("failed to warm reset the MAC Chip\n"); - return -EIO; - } - - if (hal->ah_version != AR5K_AR5210){ - /* ...set the PHY operating mode */ - ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL); - udelay(300); - - ath5k_hw_reg_write(hal, mode, AR5K_PHY_MODE); - ath5k_hw_reg_write(hal, turbo, AR5K_PHY_TURBO); - } - - return 0; -} - -/* - * Get the PHY Chip revision - */ -static u16 -ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) -{ - int i; - u32 srev; - u16 ret; - - AR5K_TRACE; - - /* - * Set the radio chip access register - */ - switch (chan) { - case CHANNEL_2GHZ: - ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); - break; - case CHANNEL_5GHZ: - ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); - break; - default: - return 0; - } - - mdelay(2); - - /* ...wait until PHY is ready and read the selected radio revision */ - ath5k_hw_reg_write(hal, 0x00001c16, AR5K_PHY(0x34)); - - for (i = 0; i < 8; i++) - ath5k_hw_reg_write(hal, 0x00010000, AR5K_PHY(0x20)); - - if (hal->ah_version == AR5K_AR5210) { - srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf; - - ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; - } else { - srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff; - - ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); - } - - /* Reset to the 5GHz mode */ - ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); - - return ret; -} - -/* - * Get the rate table for a specific operation mode - * TODO:Limit this per chipset - */ -const struct ath5k_rate_table * -ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) -{ - AR5K_TRACE; - - /* Get rate tables */ - if (!test_bit(mode, hal->ah_capabilities.cap_mode)) - return NULL; - - switch (mode) { - case MODE_IEEE80211A: - return &ath5k_rt_11a; - case MODE_ATHEROS_TURBO: - return &ath5k_rt_turbo; - case MODE_IEEE80211B: - return &ath5k_rt_11b; - case MODE_IEEE80211G: - return &ath5k_rt_11g; - case MODE_ATHEROS_TURBOG: - return &ath5k_rt_xr; - default: - return NULL; - } - - return NULL; -} - -/* - * Free the hal struct - */ -void ath5k_hw_detach(struct ath_hw *hal) -{ - AR5K_TRACE; - - if (hal->ah_rf_banks != NULL) - kfree(hal->ah_rf_banks); - - /* assume interrupts are down */ - kfree(hal); -} - -/*******************************\ - Reset Functions -\*******************************/ - -/* - * Main reset function - */ -int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, - struct ieee80211_channel *channel, bool change_channel) -{ - const struct ath5k_rate_table *rt; - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u32 data, noise_floor, s_seq, s_ant, s_led[3]; - u8 mac[ETH_ALEN]; - unsigned int i, phy, mode, freq, off, ee_mode, ant[2]; - int ret; - - AR5K_TRACE; - - s_seq = 0; - s_ant = 1; - ee_mode = 0; - freq = 0; - mode = 0; - phy = 0; - - /* - * Save some registers before a reset - */ - /*DCU/Antenna selection not available on 5210*/ - if (hal->ah_version != AR5K_AR5210) { - if (change_channel == true) { - /*Sequence number for queue 0 -do this for all queues ?*/ - s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0)); - /*Default antenna*/ - s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); - } - } - - /*GPIOs*/ - s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; - s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR); - s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO); - - if (change_channel == true && hal->ah_rf_banks != NULL) - ath5k_hw_get_rf_gain(hal); - - - /*Wakeup the device*/ - ret = ath5k_hw_nic_wakeup(hal, channel->val, false); - if (ret) - return ret; - - /* - * Initialize operating mode - */ - hal->ah_op_mode = op_mode; - - /* - * 5111/5112 Settings - * 5210 only comes with RF5110 - */ - if (hal->ah_version != AR5K_AR5210) { - if (hal->ah_radio == AR5K_RF5111) - phy = AR5K_INI_PHY_5111; - else if (hal->ah_radio == AR5K_RF5112) - phy = AR5K_INI_PHY_5112; - else { - AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); - return -EINVAL; - } - - switch (channel->val & CHANNEL_MODES) { - case CHANNEL_A: - mode = AR5K_INI_VAL_11A; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - case CHANNEL_B: - mode = AR5K_INI_VAL_11B; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11B; - break; - case CHANNEL_G: - mode = AR5K_INI_VAL_11G; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11G; - break; - case CHANNEL_T: - mode = AR5K_INI_VAL_11A_TURBO; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - /*Is this ok on 5211 too ?*/ - case CHANNEL_TG: - mode = AR5K_INI_VAL_11G_TURBO; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11G; - break; - case CHANNEL_XR: - if (hal->ah_version == AR5K_AR5211) { - AR5K_PRINTF("XR mode not available on 5211"); - return -EINVAL; - } - mode = AR5K_INI_VAL_XR; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - default: - AR5K_PRINTF("invalid channel: %d\n", channel->freq); - return -EINVAL; - } - - /* PHY access enable */ - ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); - - /* - * Write initial RF registers on 5211 - * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ? - */ - if (hal->ah_version == AR5K_AR5211) - ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode); - } - - /* - * Write initial mode settings - * TODO:Do this in a common way - */ - /*For 5212*/ - if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) { - if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) - off = AR5K_INI_PHY_511X; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && - hal->ah_radio == AR5K_RF5111) - off = AR5K_INI_PHY_5111; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 && - hal->ah_radio == AR5K_RF5112) - off = AR5K_INI_PHY_5112; - else - continue; - - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, - ar5212_mode[i].mode_value[off][mode], - (u32)ar5212_mode[i].mode_register); - } - } - /*For 5211*/ - if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < ARRAY_SIZE(ar5211_mode); i++) { - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, - ar5211_mode[i].mode_value[mode], - (u32)ar5211_mode[i].mode_register); - } - } - - /* - * Write initial register settings - * TODO:Do this in a common way - */ - /*For 5212*/ - if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < ARRAY_SIZE(ar5212_ini); i++) { - if (change_channel == true && - ar5212_ini[i].ini_register >= AR5K_PCU_MIN && - ar5212_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - - if ((hal->ah_radio == AR5K_RF5111 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) || - (hal->ah_radio == AR5K_RF5112 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, - ar5212_ini[i].ini_value, - (u32)ar5212_ini[i].ini_register); - } - } - } - /*For 5211*/ - if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < ARRAY_SIZE(ar5211_ini); i++) { - if (change_channel == true && - ar5211_ini[i].ini_register >= AR5K_PCU_MIN && - ar5211_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, - ar5211_ini[i].ini_value, - (u32)ar5211_ini[i].ini_register); - } - } - /*For 5210*/ - if (hal->ah_version == AR5K_AR5210) - for (i = 0; i < ARRAY_SIZE(ar5210_ini); i++) { - if (change_channel == true && - ar5210_ini[i].ini_register >= AR5K_PCU_MIN && - ar5210_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - - switch (ar5210_ini[i].ini_mode) { - case AR5K_INI_READ: - /* Cleared on read */ - ath5k_hw_reg_read(hal, ar5210_ini[i].ini_register); - break; - - case AR5K_INI_WRITE: - default: - ath5k_hw_reg_write(hal, ar5210_ini[i].ini_value, - ar5210_ini[i].ini_register); - } - } - - /* - * 5211/5212 Specific - */ - if (hal->ah_version != AR5K_AR5210) { - /* - * Write initial RF gain settings - * This should work for both 5111/5112 - */ - if (ath5k_hw_rfgain(hal, phy, freq) == false) { - return -EIO; - } - - mdelay(1); - - /* - * Set rate duration table on 5212 - */ - if (hal->ah_version == AR5K_AR5212) { - - /*For 802.11b*/ - if (!(channel->val & CHANNEL_B)) { - - /*Get rate table for this operation mode*/ - rt = ath5k_hw_get_rate_table(hal, - MODE_IEEE80211B); - - /*Write rate duration table*/ - for (i = 0; i < rt->rate_count; i++) { - data = AR5K_RATE_DUR(rt->rates[i].rate_code); - ath5k_hw_reg_write(hal, - ath_hal_computetxtime(hal, rt, - 14, rt->rates[i].control_rate, - false), data); - if (HAS_SHPREAMBLE(i)) { - ath5k_hw_reg_write(hal, - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false), - data + - (AR5K_SET_SHORT_PREAMBLE << 2)); - } - } - - } else { - /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ - - /*Get rate table for this operation mode*/ - rt = ath5k_hw_get_rate_table(hal, - channel->val & CHANNEL_TURBO ? - MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG); - - /*Write rate duration table*/ - for (i = 0; i < rt->rate_count; i++) { - ath5k_hw_reg_write(hal, - ath_hal_computetxtime(hal, rt, - 14, rt->rates[i].control_rate, - false), - AR5K_RATE_DUR(rt->rates[i].rate_code)); - } - - } - } - - /* Fix for first revision of the RF5112 RF chipset */ - if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision< - AR5K_SREV_RAD_5112A) { - ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD, - AR5K_PHY_CCKTXCTL); - if (channel->val & CHANNEL_A) - data = 0xffb81020; - else - data = 0xffb80d20; - ath5k_hw_reg_write(hal, data, AR5K_PHY_FRAME_CTL); - } - - /* - * Set TX power (XXX use txpower from net80211) - */ - ret = ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER); - if (ret) - return ret; - - /* - * Write RF registers - * TODO:Does this work on 5211 (5111) ? - */ - if (ath5k_hw_rfregs(hal, channel, mode) == false) { - return -EINPROGRESS; - } - - /* - * Configure additional registers - */ - - /* Write OFDM timings on 5212*/ - if (hal->ah_version == AR5K_AR5212) { - if (channel->val & CHANNEL_OFDM) { - u32 coef_scaled, coef_exp, coef_man, ds_coef_exp, - ds_coef_man, clock; - - clock = channel->val & CHANNEL_T ? 80 : 40; - coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; - - for (coef_exp = 31; coef_exp > 0; coef_exp--) - if ((coef_scaled >> coef_exp) & 0x1) - break; - - if (!coef_exp) { - return -EINVAL; - } - - coef_exp = 14 - (coef_exp - 24); - coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); - ds_coef_man = coef_man >> (24 - coef_exp); - ds_coef_exp = coef_exp - 16; - - AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, - AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); - AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3, - AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); - } - } - - /*Enable/disable 802.11b mode on 5111 - (enable 2111 frequency converter + CCK)*/ - if (hal->ah_radio == AR5K_RF5111) { - if (channel->val & CHANNEL_B) - AR5K_REG_ENABLE_BITS(hal, AR5K_TXCFG, - AR5K_TXCFG_B_MODE); - else - AR5K_REG_DISABLE_BITS(hal, AR5K_TXCFG, - AR5K_TXCFG_B_MODE); - } - - /* Set antenna mode */ - AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44), - hal->ah_antenna[ee_mode][0], 0xfffffc06); - - if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] = AR5K_ANT_FIXED_B; - else - ant[0] = ant[1] = AR5K_ANT_FIXED_A; - - - ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]], - AR5K_PHY_ANT_SWITCH_TABLE_0); - ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[1]], - AR5K_PHY_ANT_SWITCH_TABLE_1); - - /* Commit values from EEPROM */ - if (hal->ah_radio == AR5K_RF5111) - AR5K_REG_WRITE_BITS(hal, AR5K_PHY_FRAME_CTL, - AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); - - ath5k_hw_reg_write(hal, - AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), - AR5K_PHY(0x5a)); - - AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11), - (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); - AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12), - (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); - AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14), - (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | - ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); - - ath5k_hw_reg_write(hal, - (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | - (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | - (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | - (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); - - AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a), - ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); - AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19), - (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); - AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01); - - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_CORR_ENABLE | - (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | - ee->ee_q_cal[ee_mode]); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ, - AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, - ee->ee_margin_tx_rx[ee_mode]); - } - - } else { - mdelay(1); - /* Disable phy and wait */ - ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); - mdelay(1); - } - - /* - * Restore saved values - */ - /*DCU/Antenna selection not available on 5210*/ - if (hal->ah_version != AR5K_AR5210) { - ath5k_hw_reg_write(hal, s_seq, AR5K_QUEUE_DFS_SEQNUM(0)); - ath5k_hw_reg_write(hal, s_ant, AR5K_DEFAULT_ANTENNA); - } - AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, s_led[0]); - ath5k_hw_reg_write(hal, s_led[1], AR5K_GPIOCR); - ath5k_hw_reg_write(hal, s_led[2], AR5K_GPIODO); - - /* - * Misc - */ - memset(mac, 0xff, ETH_ALEN); - ath5k_hw_set_associd(hal, mac, 0); - ath5k_hw_set_opmode(hal); - /*PISR/SISR Not available on 5210*/ - if (hal->ah_version != AR5K_AR5210) { - ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR); - /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so - * direct write using ath5k_hw_reg_write seems wrong. Test with: - * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, - * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); - * with different variables and check results compared - * to ath5k_hw_reg_write(hal, ) */ - ath5k_hw_reg_write(hal, AR5K_TUNE_RSSI_THRES, AR5K_RSSI_THR); - } - - /* - * Set Rx/Tx DMA Configuration - *(passing dma size not available on 5210) - */ - if (hal->ah_version != AR5K_AR5210) { - AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, - AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); - AR5K_REG_WRITE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, - AR5K_DMASIZE_512B); - } - - /* - * Set channel and calibrate the PHY - */ - if (ath5k_hw_channel(hal, channel) == false) - return -EIO; - - /* - * Enable the PHY and wait until completion - */ - ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); - - /* - * 5111/5112 Specific - */ - if (hal->ah_version != AR5K_AR5210) { - data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; - data = (channel->val & CHANNEL_CCK) ? - ((data << 2) / 22) : (data / 10); - - udelay(100 + data); - } else { - mdelay(1); - } - - /* - * Enable calibration and wait until completion - */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL); - - if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, false)) { - AR5K_PRINTF("calibration timeout (%uMHz)\n", - channel->freq); - return -EAGAIN; - } - - /* - * Enable noise floor calibration and wait until completion - */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF); - - if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, false)) { - AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", - channel->freq); - return -EAGAIN; - } - - /* Wait until the noise floor is calibrated and read the value */ - for (i = 20; i > 0; i--) { - mdelay(1); - noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); - - if (AR5K_PHY_NF_RVAL(noise_floor) & - AR5K_PHY_NF_ACTIVE) - noise_floor = AR5K_PHY_NF_AVAL(noise_floor); - - if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) - break; - } - - if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { - AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", - channel->freq); - return -EIO; - } - - hal->ah_calibration = false; - - if (!(channel->val & CHANNEL_B)) { - hal->ah_calibration = true; - AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_RUN); - } - - /* - * Reset queues and start beacon timers at the end of the reset routine - */ - for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { - /*No QCU on 5210*/ - if (hal->ah_version != AR5K_AR5210) - AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i); - - if (ath5k_hw_reset_tx_queue(hal, i) == false) { - AR5K_PRINTF("failed to reset TX queue #%d\n", i); - return -EINVAL; - } - } - - /* Pre-enable interrupts on 5211/5212*/ - if (hal->ah_version != AR5K_AR5210) { - ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); - } - - /* - * Set RF kill flags if supported by the device (read from the EEPROM) - * Disable gpio_intr for now since it results system hang. - * TODO: Handle this in ath_intr - */ -#if 0 - if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { - ath5k_hw_set_gpio_input(hal, 0); - if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0) - ath5k_hw_set_gpio_intr(hal, 0, 1); - else - ath5k_hw_set_gpio_intr(hal, 0, 0); - } -#endif - - /* - * Set the 32MHz reference clock on 5212 phy clock sleep register - */ - if (hal->ah_version == AR5K_AR5212) { - ath5k_hw_reg_write(hal, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR); - ath5k_hw_reg_write(hal, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); - ath5k_hw_reg_write(hal, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL); - ath5k_hw_reg_write(hal, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); - ath5k_hw_reg_write(hal, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); - ath5k_hw_reg_write(hal, hal->ah_radio == AR5K_RF5111 ? - AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112, - AR5K_PHY_SPENDING); - } - - /* - * Disable beacons and reset the register - */ - AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, - AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); - - return 0; -} - -/* - * Reset chipset - */ -static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) -{ - int ret; - u32 mask = val ? val : ~0; - - AR5K_TRACE; - - /* Read-and-clear RX Descriptor Pointer*/ - ath5k_hw_reg_read(hal, AR5K_RXDP); - - /* - * Reset the device and wait until success - */ - ath5k_hw_reg_write(hal, val, AR5K_RESET_CTL); - - /* Wait at least 128 PCI clocks */ - udelay(15); - - if (hal->ah_version == AR5K_AR5210) { - val &= AR5K_RESET_CTL_CHIP; - mask &= AR5K_RESET_CTL_CHIP; - } else { - val &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; - - mask &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; - } - - ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false); - - /* - * Reset configuration register (for hw byte-swap) - */ - if ((val & AR5K_RESET_CTL_PCU) == 0) - ath5k_hw_reg_write(hal, AR5K_INIT_CFG, AR5K_CFG); - - return ret; -} - -/* - * Power management functions - */ - -/* - * Sleep control - */ -int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, - bool set_chip, u16 sleep_duration) -{ - u32 staid; - int i; - - AR5K_TRACE; - staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1); - - switch (mode) { - case AR5K_PM_AUTO: - staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; - /* fallthrough */ - case AR5K_PM_NETWORK_SLEEP: - if (set_chip == true) { - ath5k_hw_reg_write(hal, - AR5K_SLEEP_CTL_SLE | sleep_duration, - AR5K_SLEEP_CTL); - } - staid |= AR5K_STA_ID1_PWR_SV; - break; - - case AR5K_PM_FULL_SLEEP: - if (set_chip == true) { - ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP, - AR5K_SLEEP_CTL); - } - staid |= AR5K_STA_ID1_PWR_SV; - break; - - case AR5K_PM_AWAKE: - if (set_chip == false) - goto commit; - - ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL); - - for (i = 5000; i > 0; i--) { - /* Check if the chip did wake up */ - if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) & - AR5K_PCICFG_SPWR_DN) == 0) - break; - - /* Wait a bit and retry */ - udelay(200); - ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, - AR5K_SLEEP_CTL); - } - - /* Fail if the chip didn't wake up */ - if (i <= 0) - return -EIO; - - staid &= ~AR5K_STA_ID1_PWR_SV; - break; - - default: - return -EINVAL; - } - -commit: - hal->ah_power_mode = mode; - ath5k_hw_reg_write(hal, staid, AR5K_STA_ID1); - - return 0; -} - -/* - * Get power mode (sleep state) - * TODO:Remove ? - */ -enum ath5k_power_mode -ath5k_hw_get_power_mode(struct ath_hw *hal) -{ - AR5K_TRACE; - return hal->ah_power_mode; -} - - - - -/***********************\ - DMA Related Functions -\***********************/ - -/* - * Receive functions - */ - -/* - * Start DMA receive - */ -void ath5k_hw_start_rx(struct ath_hw *hal) -{ - AR5K_TRACE; - ath5k_hw_reg_write(hal, AR5K_CR_RXE, AR5K_CR); -} - -/* - * Stop DMA receive - */ -int ath5k_hw_stop_rx_dma(struct ath_hw *hal) -{ - unsigned int i; - - AR5K_TRACE; - ath5k_hw_reg_write(hal, AR5K_CR_RXD, AR5K_CR); - - /* - * It may take some time to disable the DMA receive unit - */ - for (i = 2000; i > 0 && - (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_RXE) != 0; - i--) - udelay(10); - - return i ? 0 : -EBUSY; -} - -/* - * Get the address of the RX Descriptor - */ -u32 ath5k_hw_get_rx_buf(struct ath_hw *hal) -{ - return ath5k_hw_reg_read(hal, AR5K_RXDP); -} - -/* - * Set the address of the RX Descriptor - */ -void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr) -{ - AR5K_TRACE; - - /*TODO:Shouldn't we check if RX is enabled first ?*/ - ath5k_hw_reg_write(hal, phys_addr, AR5K_RXDP); -} - -/* - * Transmit functions - */ - -/* - * Start DMA transmit for a specific queue - * (see also QCU/DCU functions) - */ -int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) -{ - u32 tx_queue; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* Return if queue is declared inactive */ - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return -EIO; - - if (hal->ah_version == AR5K_AR5210) { - tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); - - /* - * Set the queue by type on 5210 - */ - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; - break; - case AR5K_TX_QUEUE_BEACON: - tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | - AR5K_BCR_BDMAE, AR5K_BSR); - break; - case AR5K_TX_QUEUE_CAB: - tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | - AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, - AR5K_BSR); - break; - default: - return -EINVAL; - } - /* Start queue */ - ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); - } else { - /* Return if queue is disabled */ - if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXD, queue)) - return -EIO; - - /* Start queue */ - AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXE, queue); - } - - return 0; -} - -/* - * Stop DMA transmit for a specific queue - * (see also QCU/DCU functions) - */ -bool -ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) -{ - int i = 100, pending; - u32 tx_queue; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* Return if queue is declared inactive */ - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return false; - - if (hal->ah_version == AR5K_AR5210) { - tx_queue = ath5k_hw_reg_read(hal, AR5K_CR); - - /* - * Set by queue type - */ - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - /* XXX Fix me... */ - tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, 0, AR5K_BSR); - break; - default: - return false; - } - - /* Stop queue */ - ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); - } else { - /* - * Schedule TX disable and wait until queue is empty - */ - AR5K_REG_WRITE_Q(hal, AR5K_QCU_TXD, queue); - - /*Check for pending frames*/ - do { - pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) & - AR5K_QCU_STS_FRMPENDCNT; - udelay(100); - } while (--i && pending); - - /* Clear register */ - ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD); - } - - /*TODO: Check for success else return false*/ - return true; -} - -/* - * Get the address of the TX Descriptor for a specific queue - * (see also QCU/DCU functions) - */ -u32 -ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) -{ - u16 tx_reg; - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Get the transmit queue descriptor pointer from the selected queue - */ - /*5210 doesn't have QCU*/ - if (hal->ah_version == AR5K_AR5210) { - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_reg = AR5K_NOQCU_TXDP0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - tx_reg = AR5K_NOQCU_TXDP1; - break; - default: - return 0xffffffff; - } - } else { - tx_reg = AR5K_QUEUE_TXDP(queue); - } - - return ath5k_hw_reg_read(hal, tx_reg); -} - -/* - * Set the address of the TX Descriptor for a specific queue - * (see also QCU/DCU functions) - */ -int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) -{ - u16 tx_reg; - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Set the transmit queue descriptor pointer register by type - * on 5210 - */ - if (hal->ah_version == AR5K_AR5210) { - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_reg = AR5K_NOQCU_TXDP0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - tx_reg = AR5K_NOQCU_TXDP1; - break; - default: - return -EINVAL; - } - } else { - /* - * Set the transmit queue descriptor pointer for - * the selected queue on QCU for 5211+ - * (this won't work if the queue is still active) - */ - if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, queue)) - return -EIO; - - tx_reg = AR5K_QUEUE_TXDP(queue); - } - - /* Set descriptor pointer */ - ath5k_hw_reg_write(hal, phys_addr, tx_reg); - - return 0; -} - -/* - * Update tx trigger level - */ -bool -ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) -{ - u32 trigger_level, imr; - bool status = false; - AR5K_TRACE; - - /* - * Disable interrupts by setting the mask - */ - imr = ath5k_hw_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); - - /*TODO: Boundary check on trigger_level*/ - trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TXCFG), - AR5K_TXCFG_TXFULL); - - if (increase == false) { - if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) - goto done; - } else - trigger_level += - ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); - - /* - * Update trigger level on success - */ - if (hal->ah_version == AR5K_AR5210) - ath5k_hw_reg_write(hal, trigger_level, AR5K_TRIG_LVL); - else - AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, - AR5K_TXCFG_TXFULL, trigger_level); - - status = true; - - done: - /* - * Restore interrupt mask - */ - ath5k_hw_set_intr(hal, imr); - - return status; -} - -/* - * Interrupt handling - */ - -/* - * Check if we have pending interrupts - */ -bool ath5k_hw_is_intr_pending(struct ath_hw *hal) -{ - AR5K_TRACE; - return ath5k_hw_reg_read(hal, AR5K_INTPEND); -} - -/* - * Get interrupt mask (ISR) - */ -int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) -{ - u32 data; - - AR5K_TRACE; - - /* - * Read interrupt status from the Interrupt Status register - * on 5210 - */ - if (hal->ah_version == AR5K_AR5210) { - data = ath5k_hw_reg_read(hal, AR5K_ISR); - if (data == AR5K_INT_NOCARD) { - *interrupt_mask = data; - return -ENODEV; - } - } - - /* - * Read interrupt status from the Read-And-Clear shadow register - */ - data = ath5k_hw_reg_read(hal, AR5K_RAC_PISR); - - /* - * Get abstract interrupt mask (HAL-compatible) - */ - *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; - - if (data == AR5K_INT_NOCARD) - return -ENODEV; - - if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) - *interrupt_mask |= AR5K_INT_RX; - - if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR)) - *interrupt_mask |= AR5K_INT_TX; - - if (hal->ah_version != AR5K_AR5210) { - /*HIU = Host Interface Unit (PCI etc)*/ - if (data & (AR5K_ISR_HIUERR)) - *interrupt_mask |= AR5K_INT_FATAL; - - /*Beacon Not Ready*/ - if (data & (AR5K_ISR_BNR)) - *interrupt_mask |= AR5K_INT_BNR; - } - - /* - * XXX: BMISS interrupts may occur after association. - * I found this on 5210 code but it needs testing - */ -#if 0 - interrupt_mask &= ~AR5K_INT_BMISS; -#endif - - /* - * In case we didn't handle anything, - * print the register value. - */ - if (*interrupt_mask == 0 && printk_ratelimit()) - AR5K_PRINTF("0x%08x\n", data); - - return 0; -} - -/* - * Set interrupt mask - */ -enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) -{ - enum ath5k_int old_mask, int_mask; - - /* - * Disable card interrupts to prevent any race conditions - * (they will be re-enabled afterwards). - */ - ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); - - old_mask = hal->ah_imr; - - /* - * Add additional, chipset-dependent interrupt mask flags - * and write them to the IMR (interrupt mask register). - */ - int_mask = new_mask & AR5K_INT_COMMON; - - if (new_mask & AR5K_INT_RX) - int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN | - AR5K_IMR_RXDESC; - - if (new_mask & AR5K_INT_TX) - int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC | - AR5K_IMR_TXURN; - - if (hal->ah_version != AR5K_AR5210) { - if (new_mask & AR5K_INT_FATAL) { - int_mask |= AR5K_IMR_HIUERR; - AR5K_REG_ENABLE_BITS(hal, AR5K_SIMR2, AR5K_SIMR2_MCABT | - AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR); - } - } - - ath5k_hw_reg_write(hal, int_mask, AR5K_PIMR); - - /* Store new interrupt mask */ - hal->ah_imr = new_mask; - - /* ..re-enable interrupts */ - ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); - - return old_mask; -} - -/* - * Enalbe HW radar detection - */ -void -ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) -{ - - AR5K_TRACE; - /* - * Enable radar detection - */ - - /*Disable interupts*/ - ath5k_hw_reg_write(hal, AR5K_IER_DISABLE, AR5K_IER); - - /* - * Set the RXPHY interrupt to be able to detect - * possible radar activity. - */ - if (hal->ah_version == AR5K_AR5210) { - if (enable == true) { - AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, - AR5K_IMR_RXPHY); - } else { - AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, - AR5K_IMR_RXPHY); - } - } else { - /*Also set AR5K_PHY_RADAR register on 5111/5112*/ - if (enable == true) { - ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_ENABLE, - AR5K_PHY_RADAR); - AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, - AR5K_IMR_RXPHY); - } else { - ath5k_hw_reg_write(hal, AR5K_PHY_RADAR_DISABLE, - AR5K_PHY_RADAR); - AR5K_REG_DISABLE_BITS(hal, AR5K_PIMR, - AR5K_IMR_RXPHY); - } - } - - /*Re-enable interrupts*/ - ath5k_hw_reg_write(hal, AR5K_IER_ENABLE, AR5K_IER); -} - - - - -/*************************\ - EEPROM access functions -\*************************/ - -/* - * Read from eeprom - */ -static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) -{ - u32 status, timeout; - - AR5K_TRACE; - /* - * Initialize EEPROM access - */ - if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); - (void)ath5k_hw_reg_read(hal, AR5K_EEPROM_BASE + (4 * offset)); - } else { - ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); - AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, - AR5K_EEPROM_CMD_READ); - } - - for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { - status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); - if (status & AR5K_EEPROM_STAT_RDDONE) { - if (status & AR5K_EEPROM_STAT_RDERR) - return -EIO; - *data = (u16) - (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff); - return 0; - } - udelay(15); - } - - return -ETIMEDOUT; -} - -/* - * Write to eeprom - currently disabled, use at your own risk - */ -static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) -{ -#if 0 - u32 status, timeout; - - AR5K_TRACE; - - /* - * Initialize eeprom access - */ - - if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); - } else { - AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); - } - - /* - * Write data to data register - */ - - if (hal->ah_version == AR5K_AR5210) { - ath5k_hw_reg_write(hal, data, AR5K_EEPROM_BASE + (4 * offset)); - } else { - ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); - ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA); - AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); - } - - /* - * Check status - */ - - for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { - status = ath5k_hw_reg_read(hal, AR5K_EEPROM_STATUS); - if (status & AR5K_EEPROM_STAT_WRDONE) { - if (status & AR5K_EEPROM_STAT_WRERR) - return EIO; - return 0; - } - udelay(15); - } -#endif - AR5K_PRINTF("EEPROM Write is disabled!"); - return -EIO; -} - -u16 -ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) -{ - u16 val; - - if (bin == AR5K_EEPROM_CHANNEL_DIS) - return bin; - - if (mode == AR5K_EEPROM_MODE_11A) { - if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) - val = (5 * bin) + 4800; - else - val = bin > 62 ? - (10 * 62) + (5 * (bin - 62)) + 5100 : - (bin * 10) + 5100; - } else { - if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) - val = bin + 2300; - else - val = bin + 2400; - } - - return val; -} - -/* - * Read antenna infos from eeprom - */ -int -ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode) -{ - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u32 o = *offset; - u16 val; - int ret, i = 0; - - AR5K_EEPROM_READ(o++, val); - ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; - ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; - ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; - ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; - ee->ee_ant_control[mode][i++] = val & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; - ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; - ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; - ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; - ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; - ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; - ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; - ee->ee_ant_control[mode][i++] = val & 0x3f; - - /* Get antenna modes */ - hal->ah_antenna[mode][0] = - (ee->ee_ant_control[mode][0] << 4) | 0x1; - hal->ah_antenna[mode][AR5K_ANT_FIXED_A] = - ee->ee_ant_control[mode][1] | - (ee->ee_ant_control[mode][2] << 6) | - (ee->ee_ant_control[mode][3] << 12) | - (ee->ee_ant_control[mode][4] << 18) | - (ee->ee_ant_control[mode][5] << 24); - hal->ah_antenna[mode][AR5K_ANT_FIXED_B] = - ee->ee_ant_control[mode][6] | - (ee->ee_ant_control[mode][7] << 6) | - (ee->ee_ant_control[mode][8] << 12) | - (ee->ee_ant_control[mode][9] << 18) | - (ee->ee_ant_control[mode][10] << 24); - - /* return new offset */ - *offset = o; - - return 0; -} - -/* - * Read supported modes from eeprom - */ -int -ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode) -{ - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u32 o = *offset; - u16 val; - int ret; - - AR5K_EEPROM_READ(o++, val); - ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; - ee->ee_thr_62[mode] = val & 0xff; - - if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) - ee->ee_thr_62[mode] = - mode == AR5K_EEPROM_MODE_11A ? 15 : 28; - - AR5K_EEPROM_READ(o++, val); - ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; - ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; - - AR5K_EEPROM_READ(o++, val); - ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; - - if ((val & 0xff) & 0x80) - ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); - else - ee->ee_noise_floor_thr[mode] = val & 0xff; - - if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) - ee->ee_noise_floor_thr[mode] = - mode == AR5K_EEPROM_MODE_11A ? -54 : -1; - - AR5K_EEPROM_READ(o++, val); - ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; - ee->ee_x_gain[mode] = (val >> 1) & 0xf; - ee->ee_xpd[mode] = val & 0x1; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) - ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { - AR5K_EEPROM_READ(o++, val); - ee->ee_false_detect[mode] = (val >> 6) & 0x7f; - - if (mode == AR5K_EEPROM_MODE_11A) - ee->ee_xr_power[mode] = val & 0x3f; - else { - ee->ee_ob[mode][0] = val & 0x7; - ee->ee_db[mode][0] = (val >> 3) & 0x7; - } - } - - if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { - ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; - ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; - } else { - ee->ee_i_gain[mode] = (val >> 13) & 0x7; - - AR5K_EEPROM_READ(o++, val); - ee->ee_i_gain[mode] |= (val << 3) & 0x38; - - if (mode == AR5K_EEPROM_MODE_11G) - ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; - } - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && - mode == AR5K_EEPROM_MODE_11A) { - ee->ee_i_cal[mode] = (val >> 8) & 0x3f; - ee->ee_q_cal[mode] = (val >> 3) & 0x1f; - } - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && - mode == AR5K_EEPROM_MODE_11G) - ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; - - /* return new offset */ - *offset = o; - - return 0; -} - -/* - * Initialize eeprom & capabilities structs - */ -static int ath5k_eeprom_init(struct ath_hw *hal) -{ - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u32 offset; - u16 val; - int ret, i; - unsigned int mode; - - /* Initial TX thermal adjustment values */ - ee->ee_tx_clip = 4; - ee->ee_pwd_84 = ee->ee_pwd_90 = 1; - ee->ee_gain_select = 1; - - /* - * Read values from EEPROM and store them in the capability structure - */ - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); - - /* Return if we have an old EEPROM */ - if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) - return 0; - -#ifdef notyet - /* - * Validate the checksum of the EEPROM date. There are some - * devices with invalid EEPROMs. - */ - for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { - AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); - cksum ^= val; - } - if (cksum != AR5K_EEPROM_INFO_CKSUM) { - AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); - return -EIO; - } -#endif - - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), - ee_ant_gain); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); - } - - if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { - AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); - ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; - ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; - - AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); - ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; - ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; - } - - /* - * Get conformance test limit values - */ - offset = AR5K_EEPROM_CTL(hal->ah_ee_version); - ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); - - for (i = 0; i < ee->ee_ctls; i++) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_ctl[i] = (val >> 8) & 0xff; - ee->ee_ctl[i + 1] = val & 0xff; - } - - /* - * Get values for 802.11a (5GHz) - */ - mode = AR5K_EEPROM_MODE_11A; - - ee->ee_turbo_max_power[mode] = - AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); - - offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); - - ret = ath5k_eeprom_read_ants(hal, &offset, mode); - if (ret) - return ret; - - AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); - ee->ee_ob[mode][3] = (val >> 5) & 0x7; - ee->ee_db[mode][3] = (val >> 2) & 0x7; - ee->ee_ob[mode][2] = (val << 1) & 0x7; - - AR5K_EEPROM_READ(offset++, val); - ee->ee_ob[mode][2] |= (val >> 15) & 0x1; - ee->ee_db[mode][2] = (val >> 12) & 0x7; - ee->ee_ob[mode][1] = (val >> 9) & 0x7; - ee->ee_db[mode][1] = (val >> 6) & 0x7; - ee->ee_ob[mode][0] = (val >> 3) & 0x7; - ee->ee_db[mode][0] = val & 0x7; - - ret = ath5k_eeprom_read_modes(hal, &offset, mode); - if (ret) - return ret; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_margin_tx_rx[mode] = val & 0x3f; - } - - /* - * Get values for 802.11b (2.4GHz) - */ - mode = AR5K_EEPROM_MODE_11B; - offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); - - ret = ath5k_eeprom_read_ants(hal, &offset, mode); - if (ret) - return ret; - - AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); - ee->ee_ob[mode][1] = (val >> 4) & 0x7; - ee->ee_db[mode][1] = val & 0x7; - - ret = ath5k_eeprom_read_modes(hal, &offset, mode); - if (ret) - return ret; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); - ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); - - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); - } - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; - } - - /* - * Get values for 802.11g (2.4GHz) - */ - mode = AR5K_EEPROM_MODE_11G; - offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); - - ret = ath5k_eeprom_read_ants(hal, &offset, mode); - if (ret) - return ret; - - AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); - ee->ee_ob[mode][1] = (val >> 4) & 0x7; - ee->ee_db[mode][1] = val & 0x7; - - ret = ath5k_eeprom_read_modes(hal, &offset, mode); - if (ret) - return ret; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); - ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); - - AR5K_EEPROM_READ(offset++, val); - ee->ee_turbo_max_power[mode] = val & 0x7f; - ee->ee_xr_power[mode] = (val >> 7) & 0x3f; - - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; - } - - AR5K_EEPROM_READ(offset++, val); - ee->ee_i_cal[mode] = (val >> 8) & 0x3f; - ee->ee_q_cal[mode] = (val >> 3) & 0x1f; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_cck_ofdm_gain_delta = val & 0xff; - } - } - - /* - * Read 5GHz EEPROM channels - */ - - return 0; -} - -/* - * Read the MAC address from eeprom - */ -static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) -{ - u8 mac_d[ETH_ALEN]; - u32 total, offset; - u16 data; - int octet, ret; - - memset(mac, 0, ETH_ALEN); - memset(mac_d, 0, ETH_ALEN); - - ret = ath5k_hw_eeprom_read(hal, 0x20, &data); - if (ret) - return ret; - - for (offset = 0x1f, octet = 0, total = 0; - offset >= 0x1d; offset--) { - ret = ath5k_hw_eeprom_read(hal, offset, &data); - if (ret) - return ret; - - total += data; - mac_d[octet + 1] = data & 0xff; - mac_d[octet] = data >> 8; - octet += 2; - } - - memcpy(mac, mac_d, ETH_ALEN); - - if (!total || total == 3 * 0xffff) - return -EINVAL; - - return 0; -} - -/* - * Read/Write regulatory domain - */ -static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, - enum ieee80211_regdomain *regdomain) -{ - u16 ee_regdomain; - - /* Read current value */ - if (write != true) { - ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; - *regdomain = ath5k_regdomain_to_ieee(ee_regdomain); - return true; - } - - ee_regdomain = ath5k_regdomain_from_ieee(*regdomain); - - /* Try to write a new value */ - if (hal->ah_capabilities.cap_eeprom.ee_protect & - AR5K_EEPROM_PROTECT_WR_128_191) - return false; - if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, - ee_regdomain) != 0) - return false; - - hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; - - return true; -} - -/* - * Use the above to write a new regulatory domain - */ -int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain) -{ - enum ieee80211_regdomain ieee_regdomain; - - ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); - - if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true) - return 0; - - return -EIO; -} - -/* - * Fill the capabilities struct - */ -static int ath5k_hw_get_capabilities(struct ath_hw *hal) -{ - u16 ee_header; - - AR5K_TRACE; - /* Capabilities stored in the EEPROM */ - ee_header = hal->ah_capabilities.cap_eeprom.ee_header; - - if (hal->ah_version == AR5K_AR5210) { - /* - * Set radio capabilities - * (The AR5110 only supports the middle 5GHz band) - */ - hal->ah_capabilities.cap_range.range_5ghz_min = 5120; - hal->ah_capabilities.cap_range.range_5ghz_max = 5430; - hal->ah_capabilities.cap_range.range_2ghz_min = 0; - hal->ah_capabilities.cap_range.range_2ghz_max = 0; - - /* Set supported modes */ - set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); - set_bit(MODE_ATHEROS_TURBO, hal->ah_capabilities.cap_mode); - } else { - /* - * XXX The tranceiver supports frequencies from 4920 to 6100GHz - * XXX and from 2312 to 2732GHz. There are problems with the current - * XXX ieee80211 implementation because the IEEE channel mapping - * XXX does not support negative channel numbers (2312MHz is channel - * XXX -19). Of course, this doesn't matter because these channels - * XXX are out of range but some regulation domains like MKK (Japan) - * XXX will support frequencies somewhere around 4.8GHz. - */ - - /* - * Set radio capabilities - */ - - if (AR5K_EEPROM_HDR_11A(ee_header)) { - hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ - hal->ah_capabilities.cap_range.range_5ghz_max = 6100; - - /* Set supported modes */ - set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); - set_bit(MODE_ATHEROS_TURBO, - hal->ah_capabilities.cap_mode); - if (hal->ah_version == AR5K_AR5212) - set_bit(MODE_ATHEROS_TURBOG, - hal->ah_capabilities.cap_mode); - } - - /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ - if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { - hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ - hal->ah_capabilities.cap_range.range_2ghz_max = 2732; - - if (AR5K_EEPROM_HDR_11B(ee_header)) - set_bit(MODE_IEEE80211B, - hal->ah_capabilities.cap_mode); - - if (AR5K_EEPROM_HDR_11G(ee_header)) - set_bit(MODE_IEEE80211G, - hal->ah_capabilities.cap_mode); - } - } - - /* GPIO */ - hal->ah_gpio_npins = AR5K_NUM_GPIO; - - /* Set number of supported TX queues */ - if (hal->ah_version == AR5K_AR5210) - hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU; - else - hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; - - return 0; -} - -/*********************************\ - Protocol Control Unit Functions -\*********************************/ - -/* - * Set Operation mode - */ -void -ath5k_hw_set_opmode(struct ath_hw *hal) -{ - u32 pcu_reg, beacon_reg, low_id, high_id; - - pcu_reg = 0; - beacon_reg = 0; - - AR5K_TRACE; - - switch (hal->ah_op_mode) { - case IEEE80211_IF_TYPE_IBSS: - pcu_reg |= AR5K_STA_ID1_ADHOC | - AR5K_STA_ID1_DESC_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); - - beacon_reg |= AR5K_BCR_ADHOC; - break; - - case IEEE80211_IF_TYPE_AP: - pcu_reg |= AR5K_STA_ID1_AP | - AR5K_STA_ID1_RTS_DEF_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); - - beacon_reg |= AR5K_BCR_AP; - break; - - case IEEE80211_IF_TYPE_STA: - pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_PWR_SV :0); - case IEEE80211_IF_TYPE_MNTR: - pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); - break; - - default: - return; - } - - /* - * Set PCU registers - */ - low_id = AR5K_LOW_ID(hal->ah_sta_id); - high_id = AR5K_HIGH_ID(hal->ah_sta_id); - ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); - ath5k_hw_reg_write(hal, pcu_reg | high_id, AR5K_STA_ID1); - - /* - * Set Beacon Control Register on 5210 - */ - if (hal->ah_version == AR5K_AR5210) - ath5k_hw_reg_write(hal, beacon_reg, AR5K_BCR); -} - -/* - * BSSID Functions - */ - -/* - * Get station id - */ -void -ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) -{ - AR5K_TRACE; - memcpy(mac, hal->ah_sta_id, ETH_ALEN); -} - -/* - * Set station id - */ -bool -ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac) -{ - u32 low_id, high_id; - - AR5K_TRACE; - /* Set new station ID */ - memcpy(hal->ah_sta_id, mac, ETH_ALEN); - - low_id = AR5K_LOW_ID(mac); - high_id = AR5K_HIGH_ID(mac); - - ath5k_hw_reg_write(hal, low_id, AR5K_STA_ID0); - ath5k_hw_reg_write(hal, high_id, AR5K_STA_ID1); - - return true; -} - -/* - * Set BSSID - */ -void -ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, - u16 assoc_id) -{ - u32 low_id, high_id; - u16 tim_offset = 0; - - /* - * Set simple BSSID mask on 5212 - */ - if (hal->ah_version == AR5K_AR5212) { - ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM0); - ath5k_hw_reg_write(hal, 0xfffffff, AR5K_BSS_IDM1); - } - - /* - * Set BSSID which triggers the "SME Join" operation - */ - low_id = AR5K_LOW_ID(bssid); - high_id = AR5K_HIGH_ID(bssid); - ath5k_hw_reg_write(hal, low_id, AR5K_BSS_ID0); - ath5k_hw_reg_write(hal, high_id | ((assoc_id & 0x3fff) << - AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); - memcpy(&hal->ah_bssid, bssid, ETH_ALEN); - - if (assoc_id == 0) { - ath5k_hw_disable_pspoll(hal); - return; - } - - AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM, - tim_offset ? tim_offset + 4 : 0); - - ath5k_hw_enable_pspoll(hal, NULL, 0); -} - -/* - * Set BSSID mask on 5212 - */ -bool -ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) -{ - u32 low_id, high_id; - AR5K_TRACE; - - if (hal->ah_version == AR5K_AR5212) { - - low_id = AR5K_LOW_ID(mask); - high_id = AR5K_HIGH_ID(mask); - - ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); - ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); - - return true; - } else - return false; -} - -/* - * Receive start/stop functions - */ - -/* - * Start receive on PCU - */ -void -ath5k_hw_start_rx_pcu(struct ath_hw *hal) -{ - AR5K_TRACE; - AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); -} - -/* - * Stop receive on PCU - */ -void -ath5k_hw_stop_pcu_recv(struct ath_hw *hal) -{ - AR5K_TRACE; - AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); -} - -/* - * RX Filter functions - */ - -/* - * Set multicast filter - */ -void -ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, - u32 filter1) -{ - AR5K_TRACE; - /* Set the multicat filter */ - ath5k_hw_reg_write(hal, filter0, AR5K_MCAST_FILTER0); - ath5k_hw_reg_write(hal, filter1, AR5K_MCAST_FILTER1); -} - -/* - * Set multicast filter by index - */ -bool -ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) -{ - - AR5K_TRACE; - if (index >= 64) - return false; - else if (index >= 32) - AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, - (1 << (index - 32))); - else - AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, - (1 << index)); - - return true; -} - -/* - * Clear Multicast filter by index - */ -bool -ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) -{ - - AR5K_TRACE; - if (index >= 64) - return false; - else if (index >= 32) - AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, - (1 << (index - 32))); - else - AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, - (1 << index)); - - return true; -} - -/* - * Get current rx filter - */ -u32 -ath5k_hw_get_rx_filter(struct ath_hw *hal) -{ - u32 data, filter = 0; - - AR5K_TRACE; - filter = ath5k_hw_reg_read(hal, AR5K_RX_FILTER); - - /*Radar detection for 5212*/ - if (hal->ah_version == AR5K_AR5212) { - data = ath5k_hw_reg_read(hal, AR5K_PHY_ERR_FIL); - - if (data & AR5K_PHY_ERR_FIL_RADAR) - filter |= AR5K_RX_FILTER_PHYRADAR; - if (data & (AR5K_PHY_ERR_FIL_OFDM | - AR5K_PHY_ERR_FIL_CCK)) - filter |= AR5K_RX_FILTER_PHYERR; - } - - return filter; -} - -/* - * Set rx filter - */ -void -ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) -{ - u32 data = 0; - - AR5K_TRACE; - - /* Set PHY error filter register on 5212*/ - if (hal->ah_version == AR5K_AR5212) { - if (filter & AR5K_RX_FILTER_PHYRADAR) - data |= AR5K_PHY_ERR_FIL_RADAR; - if (filter & AR5K_RX_FILTER_PHYERR) - data |= AR5K_PHY_ERR_FIL_OFDM | - AR5K_PHY_ERR_FIL_CCK; - } - - /* - * The AR5210 uses promiscous mode to detect radar activity - */ - if ((hal->ah_version == AR5K_AR5210) && - (filter & AR5K_RX_FILTER_PHYRADAR)) { - filter &= ~AR5K_RX_FILTER_PHYRADAR; - filter |= AR5K_RX_FILTER_PROM; - } - - /*Zero length DMA*/ - if (data) - AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, - AR5K_RXCFG_ZLFDMA); - else - AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, - AR5K_RXCFG_ZLFDMA); - - /*Write RX Filter register*/ - ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER); - - /*Write PHY error filter register on 5212*/ - if (hal->ah_version == AR5K_AR5212) - ath5k_hw_reg_write(hal, data, AR5K_PHY_ERR_FIL); - -} - -/* - * Beacon related functions - */ - -/* - * Get a 32bit TSF - */ -u32 ath5k_hw_get_tsf32(struct ath_hw *hal) -{ - AR5K_TRACE; - return ath5k_hw_reg_read(hal, AR5K_TSF_L32); -} - -/* - * Get the full 64bit TSF - */ -u64 ath5k_hw_get_tsf64(struct ath_hw *hal) -{ - u64 tsf = ath5k_hw_reg_read(hal, AR5K_TSF_U32); - AR5K_TRACE; - - return ath5k_hw_reg_read(hal, AR5K_TSF_L32) | (tsf << 32); -} - -/* - * Force a TSF reset - */ -void ath5k_hw_reset_tsf(struct ath_hw *hal) -{ - AR5K_TRACE; - AR5K_REG_ENABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_RESET_TSF); -} - -/* - * Initialize beacon timers - */ -void -ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, - u32 interval) -{ - u32 timer1, timer2, timer3; - - AR5K_TRACE; - /* - * Set the additional timers by mode - */ - switch (hal->ah_op_mode) { - case IEEE80211_IF_TYPE_STA: - if (hal->ah_version == AR5K_AR5210) { - timer1 = 0xffffffff; - timer2 = 0xffffffff; - } else { - timer1 = 0x0000ffff; - timer2 = 0x0007ffff; - } - break; - - default: - timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << - 0x00000003; - timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << - 0x00000003; - } - - timer3 = next_beacon + - (hal->ah_atim_window ? hal->ah_atim_window : 1); - - /* - * Set the beacon register and enable all timers. - * (next beacon, DMA beacon, software beacon, ATIM window time) - */ - ath5k_hw_reg_write(hal, next_beacon, AR5K_TIMER0); - ath5k_hw_reg_write(hal, timer1, AR5K_TIMER1); - ath5k_hw_reg_write(hal, timer2, AR5K_TIMER2); - ath5k_hw_reg_write(hal, timer3, AR5K_TIMER3); - - ath5k_hw_reg_write(hal, interval & (AR5K_BEACON_PERIOD | - AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE), - AR5K_BEACON); -} - -/* - * Set beacon timers - */ -void -ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state) -{ - u32 cfp_period, next_cfp, dtim, interval, next_beacon; - - /* - * TODO: should be changed through *state - * review struct ath5k_beacon_state struct - * - * XXX: These are used for cfp period bellow, are they - * ok ? Is it O.K. for tsf here to be 0 or should we use - * get_tsf ? - */ - u32 dtim_count = 0; /* XXX */ - u32 cfp_count = 0; /* XXX */ - u32 tsf = 0; /* XXX */ - - AR5K_TRACE; - /* Return on an invalid beacon state */ - if (state->bs_interval < 1) - return; - - interval = state->bs_interval; - dtim = state->bs_dtim_period; - - /* - * PCF support? - */ - if (state->bs_cfp_period > 0) { - /* - * Enable PCF mode and set the CFP - * (Contention Free Period) and timer registers - */ - cfp_period = state->bs_cfp_period * state->bs_dtim_period * - state->bs_interval; - next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * - state->bs_interval; - - AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_DEFAULT_ANTENNA | - AR5K_STA_ID1_PCF); - ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD); - ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR); - ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period : - next_cfp)) << 3, AR5K_TIMER2); - } else { - /* Disable PCF mode */ - AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_DEFAULT_ANTENNA | - AR5K_STA_ID1_PCF); - } - - /* - * Enable the beacon timer register - */ - ath5k_hw_reg_write(hal, state->bs_next_beacon, AR5K_TIMER0); - - /* - * Start the beacon timers - */ - ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_BEACON) &~ - (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | - AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, - AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, - AR5K_BEACON_PERIOD), AR5K_BEACON); - - /* - * Write new beacon miss threshold, if it appears to be valid - * XXX: Figure out right values for min <= bs_bmiss_threshold <= max - * and return if its not in range. We can test this by reading value and - * setting value to a largest value and seeing which values register. - */ - - AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, - AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); - - /* - * Set sleep control register - * XXX: Didn't find this in 5210 code but since this register - * exists also in ar5k's 5210 headers i leave it as common code. - */ - AR5K_REG_WRITE_BITS(hal, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, - (state->bs_sleep_duration - 3) << 3); - - /* - * Set enhanced sleep registers on 5212 - */ - if (hal->ah_version == AR5K_AR5212) { - if ((state->bs_sleep_duration > state->bs_interval) && - (roundup(state->bs_sleep_duration, interval) == - state->bs_sleep_duration)) - interval = state->bs_sleep_duration; - - if (state->bs_sleep_duration > dtim && - (dtim == 0 || roundup(state->bs_sleep_duration, dtim) == - state->bs_sleep_duration)) - dtim = state->bs_sleep_duration; - - if (interval > dtim) - return; - - next_beacon = interval == dtim ? - state->bs_next_dtim: state->bs_next_beacon; - - ath5k_hw_reg_write(hal, - AR5K_REG_SM((state->bs_next_dtim - 3) << 3, - AR5K_SLEEP0_NEXT_DTIM) | - AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | - AR5K_SLEEP0_ENH_SLEEP_EN | - AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); - - ath5k_hw_reg_write(hal, AR5K_REG_SM((next_beacon - 3) << 3, - AR5K_SLEEP1_NEXT_TIM) | - AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); - - ath5k_hw_reg_write(hal, - AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | - AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); - } -} - -/* - * Reset beacon timers - */ -void -ath5k_hw_reset_beacon(struct ath_hw *hal) -{ - AR5K_TRACE; - /* - * Disable beacon timer - */ - ath5k_hw_reg_write(hal, 0, AR5K_TIMER0); - - /* - * Disable some beacon register values - */ - AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_DEFAULT_ANTENNA | - AR5K_STA_ID1_PCF); - ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON); -} - -/* - * Wait for beacon queue to finish - * TODO: This function's name is misleading, rename - */ -bool -ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) -{ - bool ret; - int i; - - AR5K_TRACE; - - /* 5210 doesn't have QCU*/ - if (hal->ah_version == AR5K_AR5210) { - /* - * Wait for beaconn queue to finish by checking - * Control Register and Beacon Status Register. - */ - for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && - (ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && - (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); - - /* Timeout... */ - if (i <= 0) { - /* - * Re-schedule the beacon queue - */ - ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1); - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR); - - return false; - } - ret= true; - - } else { - /*5211/5212*/ - ret = ath5k_hw_register_timeout(hal, - AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), - AR5K_QCU_STS_FRMPENDCNT, 0, false) ? false : true; - - if (AR5K_REG_READ_Q(hal, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) - return false; - } - - return ret; -} - -/* - * Update mib counters (statistics) - */ -void -ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics) -{ - AR5K_TRACE; - /* Read-And-Clear */ - statistics->ackrcv_bad += ath5k_hw_reg_read(hal, AR5K_ACK_FAIL); - statistics->rts_bad += ath5k_hw_reg_read(hal, AR5K_RTS_FAIL); - statistics->rts_good += ath5k_hw_reg_read(hal, AR5K_RTS_OK); - statistics->fcs_bad += ath5k_hw_reg_read(hal, AR5K_FCS_FAIL); - statistics->beacons += ath5k_hw_reg_read(hal, AR5K_BEACON_CNT); - - /* Reset profile count registers on 5212*/ - if (hal->ah_version == AR5K_AR5212) { - ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_TX); - ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RX); - ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_RXCLR); - ath5k_hw_reg_write(hal, 0, AR5K_PROFCNT_CYCLE); - } -} - -/* - * ACK/CTS Timeouts - */ - -/* - * Set ACK timeout on PCU - */ -bool -ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) -{ - AR5K_TRACE; - if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), - hal->ah_turbo) <= timeout) - return false; - - AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, - ath5k_hw_htoclock(timeout, hal->ah_turbo)); - - return true; -} - -/* - * Read the ACK timeout from PCU - */ -unsigned int -ath5k_hw_get_ack_timeout(struct ath_hw *hal) -{ - AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), - AR5K_TIME_OUT_ACK), hal->ah_turbo)); -} - -/* - * Set CTS timeout on PCU - */ -bool -ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) -{ - AR5K_TRACE; - if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), - hal->ah_turbo) <= timeout) - return false; - - AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, - ath5k_hw_htoclock(timeout, hal->ah_turbo)); - - return true; -} - -/* - * Read CTS timeout from PCU - */ -unsigned int -ath5k_hw_get_cts_timeout(struct ath_hw *hal) -{ - AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), - AR5K_TIME_OUT_CTS), hal->ah_turbo)); -} - -/* - * Key table (WEP) functions - */ - -int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry) -{ - unsigned int i; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - - for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) - ath5k_hw_reg_write(hal, 0, AR5K_KEYTABLE_OFF(entry, i)); - - /* Set NULL encryption on non-5210*/ - if (hal->ah_version != AR5K_AR5210) - ath5k_hw_reg_write(hal, AR5K_KEYTABLE_TYPE_NULL, - AR5K_KEYTABLE_TYPE(entry)); - - return 0; -} - -int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - - /* Check the validation flag at the end of the entry */ - return ath5k_hw_reg_read(hal, AR5K_KEYTABLE_MAC1(entry)) & - AR5K_KEYTABLE_VALID; -} - -int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, - const struct ieee80211_key_conf *key, const u8 *mac) -{ - unsigned int i; - u32 key_v[AR5K_KEYCACHE_SIZE - 2] = {}; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - - switch (key->keylen) { - case 40 / 8: - memcpy(&key_v[0], key->key, 4); - memcpy(&key_v[1], key->key + 4, 1); - key_v[5] = AR5K_KEYTABLE_TYPE_40; - break; - - case 104 / 8: - memcpy(&key_v[0], key->key, 4); - memcpy(&key_v[1], key->key + 4, 2); - memcpy(&key_v[2], key->key + 6, 4); - memcpy(&key_v[3], key->key + 10, 2); - memcpy(&key_v[4], key->key + 12, 1); - key_v[5] = AR5K_KEYTABLE_TYPE_104; - break; - - case 128 / 8: - memcpy(&key_v[0], key->key, 4); - memcpy(&key_v[1], key->key + 4, 2); - memcpy(&key_v[2], key->key + 6, 4); - memcpy(&key_v[3], key->key + 10, 2); - memcpy(&key_v[4], key->key + 12, 4); - key_v[5] = AR5K_KEYTABLE_TYPE_128; - break; - - default: - return -EINVAL; - } - - for (i = 0; i < ARRAY_SIZE(key_v); i++) - ath5k_hw_reg_write(hal, key_v[i], AR5K_KEYTABLE_OFF(entry, i)); - - return ath5k_hw_set_key_lladdr(hal, entry, mac); -} - -int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) -{ - u32 low_id, high_id; - - AR5K_TRACE; - /* Invalid entry (key table overflow) */ - AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - - /* MAC may be NULL if it's a broadcast key. In this case no need to - * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ - if (unlikely(mac == NULL)) { - low_id = 0xffffffff; - high_id = 0xffff | AR5K_KEYTABLE_VALID; - } else { - low_id = AR5K_LOW_ID(mac); - high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID; - } - - ath5k_hw_reg_write(hal, low_id, AR5K_KEYTABLE_MAC0(entry)); - ath5k_hw_reg_write(hal, high_id, AR5K_KEYTABLE_MAC1(entry)); - - return 0; -} - - -/********************************************\ -Queue Control Unit, DFS Control Unit Functions -\********************************************/ - -/* - * Initialize a transmit queue - */ -int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, - struct ath5k_txq_info *queue_info) -{ - unsigned int queue; - int ret; - - AR5K_TRACE; - - /* - * Get queue by type - */ - /*5210 only has 2 queues*/ - if (hal->ah_version == AR5K_AR5210) { - switch (queue_type) { - case AR5K_TX_QUEUE_DATA: - queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; - break; - default: - return -EINVAL; - } - } else { - switch (queue_type) { - case AR5K_TX_QUEUE_DATA: - for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != - AR5K_TX_QUEUE_INACTIVE; queue++) { - - if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) - return -EINVAL; - } - break; - case AR5K_TX_QUEUE_UAPSD: - queue = AR5K_TX_QUEUE_ID_UAPSD; - break; - case AR5K_TX_QUEUE_BEACON: - queue = AR5K_TX_QUEUE_ID_BEACON; - break; - case AR5K_TX_QUEUE_CAB: - queue = AR5K_TX_QUEUE_ID_CAB; - break; - case AR5K_TX_QUEUE_XR_DATA: - if (hal->ah_version != AR5K_AR5212) - AR5K_PRINTF("XR data queues only " - "supported in 5212!"); - queue = AR5K_TX_QUEUE_ID_XR_DATA; - break; - default: - return -EINVAL; - } - } - - /* - * Setup internal queue structure - */ - memset(&hal->ah_txq[queue], 0, sizeof(struct ath5k_txq_info)); - hal->ah_txq[queue].tqi_type = queue_type; - - if (queue_info != NULL) { - queue_info->tqi_type = queue_type; - ret = ath5k_hw_setup_tx_queueprops(hal, queue, queue_info); - if (ret) - return ret; - } - /* - * We use ah_txq_interrupts to hold a temp value for - * the Secondary interrupt mask registers on 5211+ - * check out ath5k_hw_reset_tx_queue - */ - AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); - - return queue; -} - -/* - * Setup a transmit queue - */ -int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, - const struct ath5k_txq_info *queue_info) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return -EIO; - - memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); - - /*XXX: Is this supported on 5210 ?*/ - if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && - ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || - (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || - queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) - hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - - return 0; -} - -/* - * Get properties for a specific transmit queue - */ -bool -ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info) -{ - AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); - return true; -} - -/* - * Set a transmit queue inactive - */ -void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) -{ - AR5K_TRACE; - if (queue >= hal->ah_capabilities.cap_queues.q_tx_num) { - WARN_ON(1); - return; - } - - /* This queue will be skipped in further operations */ - hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; - /*For SIMR setup*/ - AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); -} - -/* - * Set DFS params for a transmit queue - */ -bool -ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) -{ - u32 cw_min, cw_max, retry_lg, retry_sh; - struct ath5k_txq_info *tq = &hal->ah_txq[queue]; - int i; - struct ath5k_ar5210_ini_mode ar5210_mode[] = - AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs); - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - tq = &hal->ah_txq[queue]; - - if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) - return true; - - if (hal->ah_version == AR5K_AR5210) { - /* Only handle data queues, others will be ignored */ - if (tq->tqi_type != AR5K_TX_QUEUE_DATA) - return true; - - /* - * Write initial mode register settings - */ - for (i = 0; i < ARRAY_SIZE(ar5210_mode); i++) - ath5k_hw_reg_write(hal, hal->ah_turbo == true ? - ar5210_mode[i].mode_turbo : - ar5210_mode[i].mode_base, - (u32)ar5210_mode[i].mode_register); - } - - /* - * Calculate cwmin/max by channel mode - */ - cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; - hal->ah_aifs = AR5K_TUNE_AIFS; - /*XR is only supported on 5212*/ - if (IS_CHAN_XR(hal->ah_current_channel) - && (hal->ah_version == AR5K_AR5212)) { - cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; - hal->ah_aifs = AR5K_TUNE_AIFS_XR; - /*B mode is not supported on 5210*/ - } else if (IS_CHAN_B(hal->ah_current_channel) - && (hal->ah_version != AR5K_AR5210)) { - cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; - hal->ah_aifs = AR5K_TUNE_AIFS_11B; - } - - cw_min = 1; - while (cw_min < hal->ah_cw_min) - cw_min = (cw_min << 1) | 1; - - cw_min = tq->tqi_cw_min < 0 ? - (cw_min >> (-tq->tqi_cw_min)) : - ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); - cw_max = tq->tqi_cw_max < 0 ? - (cw_max >> (-tq->tqi_cw_max)) : - ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); - - /* - * Calculate and set retry limits - */ - if (hal->ah_software_retry == true) { - /* XXX Need to test this */ - retry_lg = hal->ah_limit_tx_retries; - retry_sh = retry_lg = - retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? - AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; - } else { - retry_lg = AR5K_INIT_LG_RETRY; - retry_sh = AR5K_INIT_SH_RETRY; - } - - /*No QCU/DCU [5210]*/ - if (hal->ah_version == AR5K_AR5210) { - ath5k_hw_reg_write(hal, - (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) - | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, - AR5K_NODCU_RETRY_LMT_SLG_RETRY) - | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, - AR5K_NODCU_RETRY_LMT_SSH_RETRY) - | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) - | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), - AR5K_NODCU_RETRY_LMT); - } else { - /*QCU/DCU [5211+]*/ - ath5k_hw_reg_write(hal, - AR5K_REG_SM(AR5K_INIT_SLG_RETRY, - AR5K_DCU_RETRY_LMT_SLG_RETRY) | - AR5K_REG_SM(AR5K_INIT_SSH_RETRY, - AR5K_DCU_RETRY_LMT_SSH_RETRY) | - AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | - AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), - AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); - - /*===Rest is also for QCU/DCU only [5211+]===*/ - - /* - * Set initial content window (cw_min/cw_max) - * and arbitrated interframe space (aifs)... - */ - ath5k_hw_reg_write(hal, - AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | - AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | - AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, - AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue)); - - /* - * Set misc registers - */ - ath5k_hw_reg_write(hal, AR5K_QCU_MISC_DCU_EARLY, - AR5K_QUEUE_MISC(queue)); - - if (tq->tqi_cbr_period) { - ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_cbr_period, - AR5K_QCU_CBRCFG_INTVAL) | - AR5K_REG_SM(tq->tqi_cbr_overflow_limit, - AR5K_QCU_CBRCFG_ORN_THRES), - AR5K_QUEUE_CBRCFG(queue)); - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_FRSHED_CBR); - if (tq->tqi_cbr_overflow_limit) - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_CBR_THRES_ENABLE); - } - - if (tq->tqi_ready_time) { - ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time, - AR5K_QCU_RDYTIMECFG_INTVAL) | - AR5K_QCU_RDYTIMECFG_ENABLE, - AR5K_QUEUE_RDYTIMECFG(queue)); - } - - if (tq->tqi_burst_time) { - ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time, - AR5K_DCU_CHAN_TIME_DUR) | - AR5K_DCU_CHAN_TIME_ENABLE, - AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); - - if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_TXE); - } - } - - if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { - ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, - AR5K_QUEUE_DFS_MISC(queue)); - } - - if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { - ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG, - AR5K_QUEUE_DFS_MISC(queue)); - } - - /* - * Set registers by queue type - */ - switch (tq->tqi_type) { - case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_FRSHED_DBA_GT | - AR5K_QCU_MISC_CBREXP_BCN | - AR5K_QCU_MISC_BCN_ENABLE); - - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), - (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_DCU_MISC_ARBLOCK_CTL_S) | - AR5K_DCU_MISC_POST_FR_BKOFF_DIS | - AR5K_DCU_MISC_BCN_ENABLE); - - ath5k_hw_reg_write(hal, - ((AR5K_TUNE_BEACON_INTERVAL - - (AR5K_TUNE_SW_BEACON_RESP - - AR5K_TUNE_DMA_BEACON_RESP) - - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | - AR5K_QCU_RDYTIMECFG_ENABLE, - AR5K_QUEUE_RDYTIMECFG(queue)); - break; - - case AR5K_TX_QUEUE_CAB: - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_FRSHED_DBA_GT | - AR5K_QCU_MISC_CBREXP | - AR5K_QCU_MISC_CBREXP_BCN); - - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), - (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_DCU_MISC_ARBLOCK_CTL_S)); - break; - - case AR5K_TX_QUEUE_UAPSD: - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_CBREXP); - break; - - case AR5K_TX_QUEUE_DATA: - default: - break; - } - - /* - * Enable tx queue in the secondary interrupt mask registers - */ - ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, - AR5K_SIMR0_QCU_TXOK) | - AR5K_REG_SM(hal->ah_txq_interrupts, - AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); - ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, - AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); - ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, - AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); - } - - return true; -} - -/* - * Get number of pending frames - * for a specific queue [5211+] - */ -u32 -ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue) { - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* Return if queue is declared inactive */ - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return false; - - /* XXX: How about AR5K_CFG_TXCNT ? */ - if (hal->ah_version == AR5K_AR5210) - return false; - - return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT; -} - -/* - * Set slot time - */ -bool -ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time) -{ - AR5K_TRACE; - if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) - return false; - - if (hal->ah_version == AR5K_AR5210) - ath5k_hw_reg_write(hal, ath5k_hw_htoclock(slot_time, - hal->ah_turbo), AR5K_SLOT_TIME); - else - ath5k_hw_reg_write(hal, slot_time, AR5K_DCU_GBL_IFS_SLOT); - - return true; -} - -/* - * Get slot time - */ -unsigned int -ath5k_hw_get_slot_time(struct ath_hw *hal) -{ - AR5K_TRACE; - if (hal->ah_version == AR5K_AR5210) - return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) & - 0xffff, hal->ah_turbo)); - else - return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff; -} - - -/******************************\ - Hardware Descriptor Functions -\******************************/ - -/* - * TX Descriptor - */ - -/* - * Initialize the 2-word tx descriptor on 5210/5211 - */ -static int -ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, - unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, - unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, - unsigned int key_index, unsigned int antenna_mode, unsigned int flags, - unsigned int rtscts_rate, unsigned int rtscts_duration) -{ - u32 frame_type; - struct ath5k_hw_2w_tx_desc *tx_desc; - - tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; - - if (tx_tries0 == 0) - return -EINVAL; - - /* Initialize control descriptor */ - tx_desc->tx_control_0 = 0; - tx_desc->tx_control_1 = 0; - - /* Setup control descriptor */ - - /*Verify packet length*/ - tx_desc->tx_control_0 = pkt_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; - if (tx_desc->tx_control_0 != pkt_len) - return -EINVAL; - /* - * Verify header length - * XXX: I only found that on 5210 code, does it work on 5211 ? - */ - if (hal->ah_version == AR5K_AR5210) { - tx_desc->tx_control_0 = hdr_len & AR5K_2W_TX_DESC_CTL0_HEADER_LEN; - if (tx_desc->tx_control_0 != hdr_len) - return -EINVAL; - } - - /*Diferences between 5210-5211*/ - if (hal->ah_version == AR5K_AR5210) { - switch (type) { - case AR5K_PKT_TYPE_BEACON: - case AR5K_PKT_TYPE_PROBE_RESP: - frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; - case AR5K_PKT_TYPE_PIFS: - frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; - default: - frame_type = type /*<< 2 ?*/; - } - - tx_desc->tx_control_0 = - AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE)| - AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); - } else { - tx_desc->tx_control_0 |= - AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | - AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT); - tx_desc->tx_control_1 = - AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE); - } -#define _TX_FLAGS(_c, _flag) \ - if (flags & AR5K_TXDESC_##_flag) \ - tx_desc->tx_control_##_c |= \ - AR5K_2W_TX_DESC_CTL##_c##_##_flag - - _TX_FLAGS(0, CLRDMASK); - _TX_FLAGS(0, VEOL); - _TX_FLAGS(0, INTREQ); - _TX_FLAGS(0, RTSENA); - _TX_FLAGS(1, NOACK); - -#undef _TX_FLAGS - - /* - * WEP crap - */ - if (key_index != AR5K_TXKEYIX_INVALID) { - tx_desc->tx_control_0 |= - AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; - tx_desc->tx_control_1 |= - AR5K_REG_SM(key_index, - AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); - } - - /* - * RTS/CTS Duration [5210 ?] - */ - if ((hal->ah_version == AR5K_AR5210) && - (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) { - tx_desc->tx_control_1 |= - rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; - } - - return 0; -} - -/* - * Initialize the 4-word tx descriptor on 5212 - */ -static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, - struct ath_desc *desc, unsigned int pkt_len, unsigned int hdr_len, - enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, - unsigned int tx_tries0, unsigned int key_index, - unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate, - unsigned int rtscts_duration) -{ - struct ath5k_hw_4w_tx_desc *tx_desc; - - AR5K_TRACE; - - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; - - /* - * Validate input - */ - if (tx_tries0 == 0) - return -EINVAL; - - /* Initialize status descriptor */ - tx_desc->tx_control_0 = 0; - tx_desc->tx_control_1 = 0; - tx_desc->tx_control_2 = 0; - tx_desc->tx_control_3 = 0; - - /* Setup status descriptor */ - tx_desc->tx_control_0 = pkt_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN; - if (tx_desc->tx_control_0 != pkt_len) - return -EINVAL; - - tx_desc->tx_control_0 |= - AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | - AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); - tx_desc->tx_control_1 = AR5K_REG_SM(type, - AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); - tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); - tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; - -#define _TX_FLAGS(_c, _flag) \ - if (flags & AR5K_TXDESC_##_flag) \ - tx_desc->tx_control_##_c |= \ - AR5K_4W_TX_DESC_CTL##_c##_##_flag - - _TX_FLAGS(0, CLRDMASK); - _TX_FLAGS(0, VEOL); - _TX_FLAGS(0, INTREQ); - _TX_FLAGS(0, RTSENA); - _TX_FLAGS(0, CTSENA); - _TX_FLAGS(1, NOACK); - -#undef _TX_FLAGS - - /* - * WEP crap - */ - if (key_index != AR5K_TXKEYIX_INVALID) { - tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; - tx_desc->tx_control_1 |= AR5K_REG_SM(key_index, - AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); - } - - /* - * RTS/CTS - */ - if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { - if ((flags & AR5K_TXDESC_RTSENA) &&(flags & AR5K_TXDESC_CTSENA)) - return -EINVAL; - tx_desc->tx_control_2 |= rtscts_duration & - AR5K_4W_TX_DESC_CTL2_RTS_DURATION; - tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate, - AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); - } - - return 0; -} - -/* - * Initialize a 4-word XR tx descriptor on 5212 - */ -static bool -ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, - unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - unsigned int tx_rate3, u_int tx_tries3) -{ - struct ath5k_hw_4w_tx_desc *tx_desc; - - if (hal->ah_version == AR5K_AR5212) { - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; - -#define _XTX_TRIES(_n) \ - if (tx_tries##_n) { \ - tx_desc->tx_control_2 |= \ - AR5K_REG_SM(tx_tries##_n, \ - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \ - tx_desc->tx_control_3 |= \ - AR5K_REG_SM(tx_rate##_n, \ - AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \ - } - - _XTX_TRIES(1); - _XTX_TRIES(2); - _XTX_TRIES(3); - -#undef _XTX_TRIES - - return true; - } - - return(false); -} - -/* - * Fill the 2-word tx descriptor on 5210/5211 - */ -static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, - struct ath_desc *desc, unsigned int segment_length, - bool first_segment, bool last_segment) -{ - struct ath5k_hw_2w_tx_desc *tx_desc; - - tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; - - /* Clear status descriptor */ - memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); - - /* Validate segment length and initialize the descriptor */ - tx_desc->tx_control_1 = segment_length & AR5K_2W_TX_DESC_CTL1_BUF_LEN; - if (tx_desc->tx_control_1 != segment_length) - return -EINVAL; - - if (first_segment != true) - tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN; - - if (last_segment != true) - tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE; - - return 0; -} - -/* - * Fill the 4-word tx descriptor on 5212 - * XXX: Added an argument *last_desc -need revision - */ -static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, - struct ath_desc *desc, unsigned int segment_length, - bool first_segment, bool last_segment) -{ - struct ath5k_hw_4w_tx_desc *tx_desc; - struct ath5k_hw_tx_status *tx_status; - - AR5K_TRACE; - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; - - /* Clear status descriptor */ - memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status)); - - /* Validate segment length and initialize the descriptor */ - tx_desc->tx_control_1 = segment_length & AR5K_4W_TX_DESC_CTL1_BUF_LEN; - if (tx_desc->tx_control_1 != segment_length) - return -EINVAL; - - if (first_segment != true) - tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN; - - if (last_segment != true) - tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE; - - return 0; -} - -/* - * Proccess the tx status descriptor on 5210/5211 - */ -static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, - struct ath_desc *desc) -{ - struct ath5k_hw_tx_status *tx_status; - struct ath5k_hw_2w_tx_desc *tx_desc; - - tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0]; - - /* No frame has been send or error */ - if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return -EINPROGRESS; - - /* - * Get descriptor status - */ - desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); - desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); - desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); - /*TODO: desc->ds_us.tx.ts_virtcol + test*/ - desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_SEQ_NUM); - desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); - desc->ds_us.tx.ts_antenna = 1; - desc->ds_us.tx.ts_status = 0; - desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0, - AR5K_2W_TX_DESC_CTL0_XMIT_RATE); - - if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ - if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; - - if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; - - if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; - } - - return 0; -} - -/* - * Proccess a tx descriptor on 5212 - */ -static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, - struct ath_desc *desc) -{ - struct ath5k_hw_tx_status *tx_status; - struct ath5k_hw_4w_tx_desc *tx_desc; - - AR5K_TRACE; - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; - - /* No frame has been send or error */ - if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) - return -EINPROGRESS; - - /* - * Get descriptor status - */ - desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); - desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); - desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); - desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_SEQ_NUM); - desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); - desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & - AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; - desc->ds_us.tx.ts_status = 0; - - switch (AR5K_REG_MS(tx_status->tx_status_1, - AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { - case 0: - desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & - AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; - break; - case 1: - desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); - desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); - break; - case 2: - desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); - desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); - break; - case 3: - desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); - desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); - break; - } - - if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ - if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; - - if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; - - if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; - } - - return 0; -} - -/* - * RX Descriptor - */ - -/* - * Initialize an rx descriptor - */ -int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, - u32 size, unsigned int flags) -{ - struct ath5k_rx_desc *rx_desc; - - AR5K_TRACE; - rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0; - - /* - *Clear ds_hw - * If we don't clean the status descriptor, - * while scanning we get too many results, - * most of them virtual, after some secs - * of scanning system hangs. M.F. - */ - memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); - - /*Initialize rx descriptor*/ - rx_desc->rx_control_0 = 0; - rx_desc->rx_control_1 = 0; - - /* Setup descriptor */ - rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; - if (rx_desc->rx_control_1 != size) - return -EINVAL; - - if (flags & AR5K_RXDESC_INTREQ) - rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; - - return 0; -} - -/* - * Proccess the rx status descriptor on 5210/5211 - */ -static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, - struct ath_desc *desc) -{ - struct ath5k_hw_old_rx_status *rx_status; - - rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0]; - - /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) - return -EINPROGRESS; - - /* - * Frame receive status - */ - desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); - desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; - desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); - desc->ds_us.rx.rs_status = 0; - - /* - * Key table status - */ - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) - desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); - else - desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; - - /* - * Receive/descriptor errors - */ - if ((rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; - - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN) - desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; - - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) { - desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; - desc->ds_us.rx.rs_phyerr = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR); - } - - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; - } - - return 0; -} - -/* - * Proccess the rx status descriptor on 5212 - */ -static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, - struct ath_desc *desc) -{ - struct ath5k_hw_new_rx_status *rx_status; - struct ath5k_hw_rx_error *rx_err; - - AR5K_TRACE; - rx_status = (struct ath5k_hw_new_rx_status*)&desc->ds_hw[0]; - - /* Overlay on error */ - rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0]; - - /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) - return -EINPROGRESS; - - /* - * Frame receive status - */ - desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_NEW_RX_DESC_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); - desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA; - desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_NEW_RX_DESC_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); - desc->ds_us.rx.rs_status = 0; - - /* - * Key table status - */ - if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID) - desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, - AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX); - else - desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; - - /* - * Receive/descriptor errors - */ - if ((rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; - - if (rx_status->rx_status_1 &AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR){ - desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; - desc->ds_us.rx.rs_phyerr = - AR5K_REG_MS(rx_err->rx_error_1, - AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE); - } - - if (rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; - - if (rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; - } - - return 0; -} - - - - -/****************\ - GPIO Functions -\****************/ - -/* - * Set led state - */ -void -ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) -{ - u32 led; - /*5210 has different led mode handling*/ - u32 led_5210; - - AR5K_TRACE; - - /*Reset led status*/ - if (hal->ah_version != AR5K_AR5210) - AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, - AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); - else - AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, - AR5K_PCICFG_LED); - - /* - * Some blinking values, define at your wish - */ - switch (state) { - case AR5K_LED_SCAN: - case AR5K_LED_AUTH: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_PEND; - led_5210 = AR5K_PCICFG_LED_PEND| - AR5K_PCICFG_LED_BCTL; - break; - - case AR5K_LED_INIT: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_NONE; - led_5210 = AR5K_PCICFG_LED_PEND; - break; - - case AR5K_LED_ASSOC: - case AR5K_LED_RUN: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_ASSOC; - led_5210 = AR5K_PCICFG_LED_ASSOC; - break; - - default: - led = AR5K_PCICFG_LEDMODE_PROM | - AR5K_PCICFG_LED_NONE; - led_5210 = AR5K_PCICFG_LED_PEND; - break; - } - - /*Write new status to the register*/ - if (hal->ah_version != AR5K_AR5210) - AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led); - else - AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, led_5210); -} - -/* - * Set GPIO outputs - */ -bool -ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) -{ - AR5K_TRACE; - if (gpio > AR5K_NUM_GPIO) - return false; - - ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ - AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); - - return true; -} - -/* - * Set GPIO inputs - */ -bool -ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) -{ - AR5K_TRACE; - if (gpio > AR5K_NUM_GPIO) - return false; - - ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ - AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); - - return true; -} - -/* - * Get GPIO state - */ -u32 -ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) -{ - AR5K_TRACE; - if (gpio > AR5K_NUM_GPIO) - return 0xffffffff; - - /* GPIO input magic */ - return (((ath5k_hw_reg_read(hal, AR5K_GPIODI) & - AR5K_GPIODI_M) >> gpio) & 0x1); -} - -/* - * Set GPIO state - */ -bool -ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) -{ - u32 data; - AR5K_TRACE; - - if (gpio > AR5K_NUM_GPIO) - return false; - - /* GPIO output magic */ - data = ath5k_hw_reg_read(hal, AR5K_GPIODO); - - data &= ~(1 << gpio); - data |= (val&1) << gpio; - - ath5k_hw_reg_write(hal, data, AR5K_GPIODO); - - return true; -} - -/* - * Initialize the GPIO interrupt (RFKill switch) - */ -void -ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, - u32 interrupt_level) -{ - u32 data; - - AR5K_TRACE; - if (gpio > AR5K_NUM_GPIO) - return; - - /* - * Set the GPIO interrupt - */ - data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) & - ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | - AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | - (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); - - ath5k_hw_reg_write(hal, interrupt_level ? data : - (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); - - hal->ah_imr |= AR5K_IMR_GPIO; - - /* Enable GPIO interrupts */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PIMR, AR5K_IMR_GPIO); -} - - - - -/*********************************\ - Regulatory Domain/Channels Setup -\*********************************/ - -/* - * Following 2 functions come from net80211 - * TODO: These do not belong here, they have nothing - * to do with hw. I left them here temporarily for - * combatibility. - * M.F. - */ - -/* - * Convert MHz frequency to IEEE channel number. - */ -unsigned int -ath_hal_mhz2ieee(unsigned int freq, u_int flags) -{ - if (flags & CHANNEL_2GHZ) { /* 2GHz band */ - if (freq == 2484) /* Japan */ - return 14; - /* don't number non-IEEE channels unless we do channel tests */ - if ((freq >= 2412) && (freq < 2484)) - return (freq - 2407) / 5; - if (CHAN_DEBUG == 1) /* 15-26 */ - return ((freq - 2512)/20) + 15; - return 0; - } else if (flags & CHANNEL_5GHZ) { /* 5Ghz band */ - /* don't number non-IEEE channels unless we do channel tests */ - if (((freq >= 5150) && (freq <= 5825))|| CHAN_DEBUG == 1) - return (freq - 5000) / 5; - return 0; - } else - /* something is fishy, don't do anything */ - return 0; -} - -/* - * Check if a channel is supported - */ -bool -ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags) -{ - /* Check if the channel is in our supported range */ - if (flags & CHANNEL_2GHZ) { - if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && - (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) - return true; - } else if (flags & CHANNEL_5GHZ) - if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && - (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) - return true; - - return false; -} - -u16 -ath5k_get_regdomain(struct ath_hw *hal) -{ - u16 regdomain; - enum ieee80211_regdomain ieee_regdomain; -#ifdef COUNTRYCODE - u16 code; -#endif - - ath5k_eeprom_regulation_domain(hal, false, &ieee_regdomain); - hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; - -#ifdef COUNTRYCODE - /* - * Get the regulation domain by country code. This will ignore - * the settings found in the EEPROM. - */ - code = ieee80211_name2countrycode(COUNTRYCODE); - ieee_regdomain = ieee80211_countrycode2regdomain(code); -#endif - - regdomain = ath5k_regdomain_from_ieee(ieee_regdomain); - hal->ah_capabilities.cap_regdomain.reg_current = regdomain; - - return regdomain; -} - -/*************************\ - PHY/RF access functions -\*************************/ - -/* - * Set a channel on the radio chip - */ -bool -ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel) -{ - bool ret; - - /* - * Check bounds supported by the PHY - * (don't care about regulation restrictions at this point) - */ - if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min || - channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) && - (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min || - channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { - AR5K_PRINTF("channel out of supported range (%u MHz)\n", - channel->freq); - return false; - } - - /* - * Set the channel and wait - */ - if (hal->ah_radio == AR5K_RF5110) - ret = ath5k_hw_rf5110_channel(hal, channel); - else if (hal->ah_radio == AR5K_RF5111) - ret = ath5k_hw_rf5111_channel(hal, channel); - else - ret = ath5k_hw_rf5112_channel(hal, channel); - - if (ret == false) - return ret; - - hal->ah_current_channel.freq = channel->freq; - hal->ah_current_channel.val = channel->val; - hal->ah_turbo = channel->val == CHANNEL_T ? true : false; - - return true; -} - -/* - * Convertion needed for RF5110 - */ -u32 -ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) -{ - u32 athchan; - - /* - * Convert IEEE channel/MHz to an internal channel value used - * by the AR5210 chipset. This has not been verified with - * newer chipsets like the AR5212A who have a completely - * different RF/PHY part. - */ - athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq, - channel->val) - 24) / 2, 5) << 1) | - (1 << 6) | 0x1; - - return athchan; -} - -/* - * Set channel on RF5110 - */ -bool -ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) -{ - u32 data; - - /* - * Set the channel and wait - */ - data = ath5k_hw_rf5110_chan2athchan(channel); - AR5K_PHY_WRITE(hal, 0x27, data); - AR5K_PHY_WRITE(hal, 0x30, 0); - mdelay(1); - - return true; -} - -/* - * Convertion needed for 5111 - */ -bool -ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan) -{ - int channel; - - /* Cast this value to catch negative channel numbers (>= -19) */ - channel = (int)ieee; - - /* - * Map 2GHz IEEE channel to 5GHz Atheros channel - */ - if (channel <= 13) { - athchan->a2_athchan = 115 + channel; - athchan->a2_flags = 0x46; - } else if (channel == 14) { - athchan->a2_athchan = 124; - athchan->a2_flags = 0x44; - } else if (channel >= 15 && channel <= 26) { - athchan->a2_athchan = ((channel - 14) * 4) + 132; - athchan->a2_flags = 0x46; - } else - return false; - - return true; -} - -/* - * Set channel on 5111 - */ -bool -ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) -{ - unsigned int ieee_channel, ath_channel; - u32 data0, data1, clock; - struct ath5k_athchan_2ghz ath_channel_2ghz; - - /* - * Set the channel on the RF5111 radio - */ - data0 = data1 = 0; - ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, - channel->val); - - if (channel->val & CHANNEL_2GHZ) { - /* Map 2GHz channel to 5GHz Atheros channel ID */ - if (ath5k_hw_rf5111_chan2athchan(ieee_channel, - &ath_channel_2ghz) == false) - return false; - - ath_channel = ath_channel_2ghz.a2_athchan; - data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) - << 5) | (1 << 4); - } - - if (ath_channel < 145 || !(ath_channel & 1)) { - clock = 1; - data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) - | (clock << 1) | (1 << 10) | 1; - } else { - clock = 0; - data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) - | (clock << 1) | (1 << 10) | 1; - } - - AR5K_PHY_WRITE(hal, 0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); - AR5K_PHY_WRITE(hal, 0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); - - return true; -} - -/* - * Set channel on 5112 - */ -bool -ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) -{ - u32 data, data0, data1, data2; - u16 c; - - data = data0 = data1 = data2 = 0; - c = channel->freq; - - /* - * Set the channel on the RF5112 or newer - */ - if (c < 4800) { - if (!((c - 2224) % 5)) { - data0 = ((2 * (c - 704)) - 3040) / 10; - data1 = 1; - } else if (!((c - 2192) % 5)) { - data0 = ((2 * (c - 672)) - 3040) / 10; - data1 = 0; - } else - return false; - - data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); - } else { - if (!(c % 20) && c >= 5120) { - data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); - data2 = ath5k_hw_bitswap(3, 2); - } else if (!(c % 10)) { - data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); - data2 = ath5k_hw_bitswap(2, 2); - } else if (!(c % 5)) { - data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); - data2 = ath5k_hw_bitswap(1, 2); - } else - return false; - } - - data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; - - AR5K_PHY_WRITE(hal, 0x27, data & 0xff); - AR5K_PHY_WRITE(hal, 0x36, (data >> 8) & 0x7f); - - return true; -} - -/* - * Perform a PHY calibration - */ -bool -ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel){ - - bool ret; - - if (hal->ah_radio == AR5K_RF5110) - ret = ath5k_hw_rf5110_calibrate(hal,channel); - else - ret = ath5k_hw_rf511x_calibrate(hal,channel); - - return ret; -} -/* - * Perform a PHY calibration on RF5110 - */ -bool -ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) -{ - bool ret = true; - u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; - unsigned int i; - -#define AGC_DISABLE { \ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, \ - AR5K_PHY_AGC_DISABLE); \ - udelay(10); \ -} - -#define AGC_ENABLE { \ - AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, \ - AR5K_PHY_AGC_DISABLE); \ -} - - /* - * Disable beacons and RX/TX queues, wait - */ - AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210, - AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); - beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210); - ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); - - udelay(2300); - - /* - * Set the channel (with AGC turned off) - */ - AGC_DISABLE; - ret = ath5k_hw_channel(hal, channel); - - /* - * Activate PHY and wait - */ - ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); - mdelay(1); - - AGC_ENABLE; - - if (ret == false) - return ret; - - /* - * Calibrate the radio chip - */ - - /* Remember normal state */ - phy_sig = ath5k_hw_reg_read(hal, AR5K_PHY_SIG); - phy_agc = ath5k_hw_reg_read(hal, AR5K_PHY_AGCCOARSE); - phy_sat = ath5k_hw_reg_read(hal, AR5K_PHY_ADCSAT); - - /* Update radio registers */ - ath5k_hw_reg_write(hal, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | - AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); - - ath5k_hw_reg_write(hal, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | - AR5K_PHY_AGCCOARSE_LO)) | - AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | - AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); - - ath5k_hw_reg_write(hal, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | - AR5K_PHY_ADCSAT_THR)) | - AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | - AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); - - udelay(20); - - AGC_DISABLE; - ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); - AGC_ENABLE; - - mdelay(1); - - /* - * Enable calibration and wait until completion - */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL); - - if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, false)) { - AR5K_PRINTF("calibration timeout (%uMHz)\n", - channel->freq); - ret = false; - } - - /* Reset to normal state */ - ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG); - ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE); - ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT); - - if (ret == false) - return false; - - /* - * Enable noise floor calibration and wait until completion - */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF); - - if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, false)) { - AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", - channel->freq); - return false; - } - - /* Wait until the noise floor is calibrated */ - for (i = 20; i > 0; i--) { - mdelay(1); - noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); - - if (AR5K_PHY_NF_RVAL(noise_floor) & - AR5K_PHY_NF_ACTIVE) - noise_floor = AR5K_PHY_NF_AVAL(noise_floor); - - if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) - break; - } - - if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { - AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", - channel->freq); - return false; - } - - - /* - * Re-enable RX/TX and beacons - */ - AR5K_REG_DISABLE_BITS(hal, AR5K_DIAG_SW_5210, - AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); - ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210); - -#undef AGC_ENABLE -#undef AGC_DISABLE - - return true; -} - -/* - * Perform a PHY calibration on RF5111/5112 - */ -bool -ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) -{ - u32 i_pwr, q_pwr; - s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; - AR5K_TRACE; - - if (hal->ah_calibration == false || - ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) - goto done; - - hal->ah_calibration = false; - - iq_corr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_CORR); - i_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_I); - q_pwr = ath5k_hw_reg_read(hal, AR5K_PHY_IQRES_CAL_PWR_Q); - i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; - q_coffd = q_pwr >> 6; - - if (i_coffd == 0 || q_coffd == 0) - goto done; - - i_coff = ((-iq_corr) / i_coffd) & 0x3f; - q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; - - /* Commit new IQ value */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_CORR_ENABLE | - ((u32)q_coff) | - ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); - - done: - /* Start noise floor calibration */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF); - - /* Request RF gain */ - if (channel->val & CHANNEL_5GHZ) { - ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txpower.txp_max, - AR5K_PHY_PAPD_PROBE_TXPOWER) | - AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); - hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; - } - - return true; -} - -bool -ath5k_hw_phy_disable(struct ath_hw *hal) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); - return true; -} - -void /*TODO:Boundary check*/ -ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - if (hal->ah_version != AR5K_AR5210) - ath5k_hw_reg_write(hal, ant, AR5K_DEFAULT_ANTENNA); -} - -unsigned int -ath5k_hw_get_def_antenna(struct ath_hw *hal) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - if (hal->ah_version != AR5K_AR5210) - return ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); - - return false; /*XXX: What do we return for 5210 ?*/ -} - -unsigned int -ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, - u32 first, u32 col, bool set) -{ - u32 mask, entry, last, data, shift, position; - s32 left; - int i; - - data = 0; - - if (rf == NULL) - /* should not happen */ - return 0; - - if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { - AR5K_PRINTF("invalid values at offset %u\n", offset); - return 0; - } - - entry = ((first - 1) / 8) + offset; - position = (first - 1) % 8; - - if (set == true) - data = ath5k_hw_bitswap(reg, bits); - - for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { - last = (position + left > 8) ? 8 : position + left; - mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << - (col * 8); - - if (set == true) { - rf[entry] &= ~mask; - rf[entry] |= ((data << position) << (col * 8)) & mask; - data >>= (8 - position); - } else { - data = (((rf[entry] & mask) >> (col * 8)) >> - position) << shift; - shift += last - position; - } - - left -= 8 - position; - } - - data = set == true ? 1 : ath5k_hw_bitswap(data, bits); - - return data; -} - -u32 -ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal) -{ - u32 mix, step; - u32 *rf; - - if (hal->ah_rf_banks == NULL) - return 0; - - rf = hal->ah_rf_banks; - hal->ah_gain.g_f_corr = 0; - - if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, false) != 1) - return 0; - - step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, false); - mix = hal->ah_gain.g_step->gos_param[0]; - - switch (mix) { - case 3: - hal->ah_gain.g_f_corr = step * 2; - break; - case 2: - hal->ah_gain.g_f_corr = (step - 5) * 2; - break; - case 1: - hal->ah_gain.g_f_corr = step; - break; - default: - hal->ah_gain.g_f_corr = 0; - break; - } - - return hal->ah_gain.g_f_corr; -} - -bool -ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) -{ - u32 step, mix, level[4]; - u32 *rf; - - if (hal->ah_rf_banks == NULL) - return 0; - - rf = hal->ah_rf_banks; - - if (hal->ah_radio == AR5K_RF5111) { - step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 6, 37, 0, false); - level[0] = 0; - level[1] = (step == 0x3f) ? 0x32 : step + 4; - level[2] = (step != 0x3f) ? 0x40 : level[0]; - level[3] = level[2] + 0x32; - - hal->ah_gain.g_high = level[3] - - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); - hal->ah_gain.g_low = level[0] + - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); - } else { - mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 1, 36, 0, false); - level[0] = level[2] = 0; - - if (mix == 1) { - level[1] = level[3] = 83; - } else { - level[1] = level[3] = 107; - hal->ah_gain.g_high = 55; - } - } - - return ((hal->ah_gain.g_current >= level[0] && - hal->ah_gain.g_current <= level[1]) || - (hal->ah_gain.g_current >= level[2] && - hal->ah_gain.g_current <= level[3])); -} - -s32 -ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) -{ - int ret = 0; - const struct ath5k_gain_opt *go; - - go = hal->ah_radio == AR5K_RF5111 ? - &rf5111_gain_opt : &rf5112_gain_opt; - - hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; - - if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { - if (hal->ah_gain.g_step_idx == 0) - return -1; - for (hal->ah_gain.g_target = hal->ah_gain.g_current; - hal->ah_gain.g_target >= hal->ah_gain.g_high && - hal->ah_gain.g_step_idx > 0; - hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { - hal->ah_gain.g_target -= 2 * - (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - - hal->ah_gain.g_step->gos_gain); - } - - ret = 1; - goto done; - } - - if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { - if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) - return -2; - for (hal->ah_gain.g_target = hal->ah_gain.g_current; - hal->ah_gain.g_target <= hal->ah_gain.g_low && - hal->ah_gain.g_step_idx < (go->go_steps_count - 1); - hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { - hal->ah_gain.g_target -= 2 * - (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - - hal->ah_gain.g_step->gos_gain); - } - - ret = 2; - goto done; - } - - done: -#ifdef AR5K_DEBUG - AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", - ret, - hal->ah_gain.g_step_idx, - hal->ah_gain.g_current, - hal->ah_gain.g_target); -#endif - - return ret; -} - -/* - * Initialize RF - */ -bool -ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) -{ - ath5k_rfgain_t *func = NULL; - bool ret; - - if (hal->ah_radio == AR5K_RF5111) { - hal->ah_rf_banks_size = sizeof(rf5111_rf); - func = ath5k_hw_rf5111_rfregs; - } else if (hal->ah_radio == AR5K_RF5112) { - if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) - hal->ah_rf_banks_size = sizeof(rf5112a_rf); - else - hal->ah_rf_banks_size = sizeof(rf5112_rf); - func = ath5k_hw_rf5112_rfregs; - } else - return false; - - if (hal->ah_rf_banks == NULL) { - /* XXX do extra checks? */ - if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, - GFP_KERNEL)) == NULL) { - AR5K_PRINT("out of memory\n"); - return false; - } - } - - ret = (func)(hal, channel, mode); - - if (ret == true) - hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; - - return ret; -} - -/* - * Initialize RF5111 - */ -bool -ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) -{ - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); - u32 *rf; - int i, obdb = -1, bank = -1; - u32 ee_mode; - - AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); - - rf = hal->ah_rf_banks; - - /* Copy values to modify them */ - for (i = 0; i < rf_size; i++) { - if (rf5111_rf[i].rf_bank >= - AR5K_RF5111_INI_RF_MAX_BANKS) { - AR5K_PRINT("invalid bank\n"); - return false; - } - - if (bank != rf5111_rf[i].rf_bank) { - bank = rf5111_rf[i].rf_bank; - hal->ah_offset[bank] = i; - } - - rf[i] = rf5111_rf[i].rf_value[mode]; - } - - if (channel->val & CHANNEL_2GHZ) { - if (channel->val & CHANNEL_B) - ee_mode = AR5K_EEPROM_MODE_11B; - else - ee_mode = AR5K_EEPROM_MODE_11G; - obdb = 0; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 119, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 122, 0, true)) - return false; - - obdb = 1; - } else { - /* For 11a, Turbo and XR */ - ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_84, 1, 51, 3, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_90, 1, 45, 3, true)) - return false; - } - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - !ee->ee_xpd[ee_mode], 1, 95, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 4, 96, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 29, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_xpd[ee_mode], 1, 4, 0, true)) - return false; - - /* Write RF values */ - for (i = 0; i < rf_size; i++) { - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register); - } - - return true; -} - -/* - * Initialize RF5112 - */ -bool -ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) -{ - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - unsigned int rf_size; - u32 *rf; - int i, obdb = -1, bank = -1; - u32 ee_mode; - const struct ath5k_ini_rf *rf_ini; - - AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); - - rf = hal->ah_rf_banks; - - if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { - rf_ini = rf5112a_rf; - rf_size = ARRAY_SIZE(rf5112a_rf); - } else { - rf_ini = rf5112_rf; - rf_size = ARRAY_SIZE(rf5112_rf); - } - - /* Copy values to modify them */ - for (i = 0; i < rf_size; i++) { - if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { - AR5K_PRINT("invalid bank\n"); - return false; - } - - if (bank != rf_ini[i].rf_bank) { - bank = rf_ini[i].rf_bank; - hal->ah_offset[bank] = i; - } - - rf[i] = rf_ini[i].rf_value[mode]; - } - - if (channel->val & CHANNEL_2GHZ) { - if (channel->val & CHANNEL_B) - ee_mode = AR5K_EEPROM_MODE_11B; - else - ee_mode = AR5K_EEPROM_MODE_11G; - obdb = 0; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 287, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 290, 0, true)) - return false; - } else { - /* For 11a, Turbo and XR */ - ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 282, 0, true)) - return false; - } - -#ifdef notyet - ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 270, 0, true); - ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 257, 0, true); -#endif - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_xpd[ee_mode], 1, 302, 0, true)) - return false; - - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 14, 0, true)) - return false; - - /* Write RF values */ - for (i = 0; i < rf_size; i++) - ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register); - - return true; -} - -/* - * Initialize 5211 RF - * TODO: is this needed ? i mean 5211 has a 5111 RF - * doesn't ar5k_rfregs work ? - */ -void -ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, - unsigned int ee_mode) -{ - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)]; - u32 ob, db, obdb, xpds, xpdp, x_gain; - unsigned int i; - - memcpy(rf, ar5211_rf, sizeof(rf)); - obdb = 0; - - if (freq == AR5K_INI_RFGAIN_2GHZ && - hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { - ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3); - db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3); - rf[25].rf_value[freq] = - ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); - rf[26].rf_value[freq] = - (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | - (rf[26].rf_value[freq] & ~0xf); - } - - if (freq == AR5K_INI_RFGAIN_5GHZ) { - /* For 11a and Turbo */ - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); - } - - ob = ee->ee_ob[ee_mode][obdb]; - db = ee->ee_db[ee_mode][obdb]; - x_gain = ee->ee_x_gain[ee_mode]; - xpds = ee->ee_xpd[ee_mode]; - xpdp = !xpds; - - rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | - (((ath5k_hw_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); - rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | - ((ath5k_hw_bitswap(x_gain, 4) >> 1) & 0x7); - rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | - ((ath5k_hw_bitswap(ob, 3) << 7) & 0x80); - rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | - ((ath5k_hw_bitswap(ob, 3) >> 1) & 0x3); - rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | - ((ath5k_hw_bitswap(db, 3) << 2) & 0x1c); - rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | - ((xpds << 3) & 0x8); - - for (i = 0; i < ARRAY_SIZE(rf); i++) { - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, rf[i].rf_value[freq], - (u32)rf[i].rf_register); - } - - hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; -} - -bool -ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) -{ - int i; - - switch (phy) { - case AR5K_INI_PHY_5111: - case AR5K_INI_PHY_5112: - break; - default: - return false; - } - - switch (freq) { - case AR5K_INI_RFGAIN_2GHZ: - case AR5K_INI_RFGAIN_5GHZ: - break; - default: - return false; - } - - for (i = 0; i < ARRAY_SIZE(ath5k_rfg); i++) { - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, ath5k_rfg[i].rfg_value[phy][freq], - (u32)ath5k_rfg[i].rfg_register); - } - - return true; -} - -enum ath5k_rfgain -ath5k_hw_get_rf_gain(struct ath_hw *hal) -{ - u32 data, type; - - AR5K_TRACE; - - if (hal->ah_rf_banks == NULL || !hal->ah_gain.g_active || - hal->ah_version <= AR5K_AR5211) - return AR5K_RFGAIN_INACTIVE; - - if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) - goto done; - - data = ath5k_hw_reg_read(hal, AR5K_PHY_PAPD_PROBE); - - if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { - hal->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; - type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); - - if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) - hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR; - - if (hal->ah_radio == AR5K_RF5112) { - ath5k_hw_rfregs_gainf_corr(hal); - hal->ah_gain.g_current = - hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? - (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : - 0; - } - - if (ath5k_hw_rfregs_gain_readback(hal) && - AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && - ath5k_hw_rfregs_gain_adjust(hal)) - hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE; - } - - done: - return hal->ah_rf_gain; -} - -/* - * TX power setup - */ - -/* - * Initialize the tx power table (not fully implemented) - */ -static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power) -{ - u16 txpower, *rates; - unsigned int i, min, max, n; - - rates = hal->ah_txpower.txp_rates; - - txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; - if (max_power > txpower) - txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? - AR5K_TUNE_MAX_TXPOWER : max_power; - - for (i = 0; i < AR5K_MAX_RATES; i++) - rates[i] = txpower; - - /* XXX setup target powers by rate */ - - hal->ah_txpower.txp_min = rates[7]; - hal->ah_txpower.txp_max = rates[0]; - hal->ah_txpower.txp_ofdm = rates[0]; - - /* Calculate the power table */ - n = ARRAY_SIZE(hal->ah_txpower.txp_pcdac); - min = AR5K_EEPROM_PCDAC_START; - max = AR5K_EEPROM_PCDAC_STOP; - for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) - hal->ah_txpower.txp_pcdac[i] = -#ifdef notyet - min + ((i * (max - min)) / n); -#else - min; -#endif -} - -/* - * Set transmition power - */ -static int /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower) -{ - bool tpc = hal->ah_txpower.txp_tpc; - unsigned int i; - - AR5K_TRACE; - if (txpower > AR5K_TUNE_MAX_TXPOWER) { - AR5K_PRINTF("invalid tx power: %u\n", txpower); - return -EINVAL; - } - - /* Reset TX power values */ - memset(&hal->ah_txpower, 0, sizeof(hal->ah_txpower)); - hal->ah_txpower.txp_tpc = tpc; - - /* Initialize TX power table */ - ath5k_txpower_table(hal, channel, txpower); - - /* - * Write TX power values - */ - for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { - ath5k_hw_reg_write(hal, - ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) - | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ), - AR5K_PHY_PCDAC_TXPOWER(i)); - } - - ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(3, 24) | - AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | - AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); - - ath5k_hw_reg_write(hal, AR5K_TXPOWER_OFDM(7, 24) | - AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | - AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); - - ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(10, 24) | - AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | - AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); - - ath5k_hw_reg_write(hal, AR5K_TXPOWER_CCK(14, 24) | - AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | - AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); - - if (hal->ah_txpower.txp_tpc == true) { - ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | - AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); - } else { - ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX | - AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); - } - - return 0; -} - -int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) -{ - /*Just a try M.F.*/ - struct ieee80211_channel *channel = &hal->ah_current_channel; - - AR5K_TRACE; -#ifdef AR5K_DEBUG - AR5K_PRINTF("changing txpower to %d\n",power); -#endif - return ath5k_hw_txpower(hal, channel, power); -} - - - - -/****************\ - Misc functions -\****************/ - -void /*O.K.*/ -ath5k_hw_dump_state(struct ath_hw *hal) -{ -#ifdef AR5K_DEBUG -#define AR5K_PRINT_REGISTER(_x) \ - AR5K_PRINTF("(%s: %08x) ", #_x, ath5k_hw_reg_read(hal, AR5K_##_x)); - - AR5K_PRINT("MAC registers:\n"); - AR5K_PRINT_REGISTER(CR); - AR5K_PRINT_REGISTER(CFG); - AR5K_PRINT_REGISTER(IER); - AR5K_PRINT_REGISTER(TXCFG); - AR5K_PRINT_REGISTER(RXCFG); - AR5K_PRINT_REGISTER(MIBC); - AR5K_PRINT_REGISTER(TOPS); - AR5K_PRINT_REGISTER(RXNOFRM); - AR5K_PRINT_REGISTER(RPGTO); - AR5K_PRINT_REGISTER(RFCNT); - AR5K_PRINT_REGISTER(MISC); - AR5K_PRINT_REGISTER(PISR); - AR5K_PRINT_REGISTER(SISR0); - AR5K_PRINT_REGISTER(SISR1); - AR5K_PRINT_REGISTER(SISR3); - AR5K_PRINT_REGISTER(SISR4); - AR5K_PRINT_REGISTER(DCM_ADDR); - AR5K_PRINT_REGISTER(DCM_DATA); - AR5K_PRINT_REGISTER(DCCFG); - AR5K_PRINT_REGISTER(CCFG); - AR5K_PRINT_REGISTER(CCFG_CUP); - AR5K_PRINT_REGISTER(CPC0); - AR5K_PRINT_REGISTER(CPC1); - AR5K_PRINT_REGISTER(CPC2); - AR5K_PRINT_REGISTER(CPCORN); - AR5K_PRINT_REGISTER(QCU_TXE); - AR5K_PRINT_REGISTER(QCU_TXD); - AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); - AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); - AR5K_PRINT_REGISTER(DCU_FP); - AR5K_PRINT_REGISTER(DCU_TXP); - AR5K_PRINT_REGISTER(DCU_TX_FILTER); - AR5K_PRINT_REGISTER(RC); - AR5K_PRINT_REGISTER(SCR); - AR5K_PRINT_REGISTER(INTPEND); - AR5K_PRINT_REGISTER(PCICFG); - AR5K_PRINT_REGISTER(GPIOCR); - AR5K_PRINT_REGISTER(GPIODO); - AR5K_PRINT_REGISTER(SREV); - AR5K_PRINT_REGISTER(EEPROM_BASE); - AR5K_PRINT_REGISTER(EEPROM_DATA); - AR5K_PRINT_REGISTER(EEPROM_CMD); - AR5K_PRINT_REGISTER(EEPROM_CFG); - AR5K_PRINT_REGISTER(PCU_MIN); - AR5K_PRINT_REGISTER(STA_ID0); - AR5K_PRINT_REGISTER(STA_ID1); - AR5K_PRINT_REGISTER(BSS_ID0); - AR5K_PRINT_REGISTER(SLOT_TIME); - AR5K_PRINT_REGISTER(TIME_OUT); - AR5K_PRINT_REGISTER(RSSI_THR); - AR5K_PRINT_REGISTER(BEACON); - AR5K_PRINT_REGISTER(CFP_PERIOD); - AR5K_PRINT_REGISTER(TIMER0); - AR5K_PRINT_REGISTER(TIMER2); - AR5K_PRINT_REGISTER(TIMER3); - AR5K_PRINT_REGISTER(CFP_DUR); - AR5K_PRINT_REGISTER(MCAST_FILTER0); - AR5K_PRINT_REGISTER(MCAST_FILTER1); - AR5K_PRINT_REGISTER(DIAG_SW); - AR5K_PRINT_REGISTER(TSF_U32); - AR5K_PRINT_REGISTER(ADDAC_TEST); - AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); - AR5K_PRINT_REGISTER(LAST_TSTP); - AR5K_PRINT_REGISTER(NAV); - AR5K_PRINT_REGISTER(RTS_OK); - AR5K_PRINT_REGISTER(ACK_FAIL); - AR5K_PRINT_REGISTER(FCS_FAIL); - AR5K_PRINT_REGISTER(BEACON_CNT); - AR5K_PRINT_REGISTER(TSF_PARM); - AR5K_PRINT_REGISTER(RATE_DUR_0); - AR5K_PRINT_REGISTER(KEYTABLE_0); - AR5K_PRINT("\n"); - - AR5K_PRINT("PHY registers:\n"); - AR5K_PRINT_REGISTER(PHY_TURBO); - AR5K_PRINT_REGISTER(PHY_AGC); - AR5K_PRINT_REGISTER(PHY_TIMING_3); - AR5K_PRINT_REGISTER(PHY_CHIP_ID); - AR5K_PRINT_REGISTER(PHY_AGCCTL); - AR5K_PRINT_REGISTER(PHY_NF); - AR5K_PRINT_REGISTER(PHY_SCR); - AR5K_PRINT_REGISTER(PHY_SLMT); - AR5K_PRINT_REGISTER(PHY_SCAL); - AR5K_PRINT_REGISTER(PHY_RX_DELAY); - AR5K_PRINT_REGISTER(PHY_IQ); - AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); - AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1); - AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2); - AR5K_PRINT_REGISTER(PHY_FC); - AR5K_PRINT_REGISTER(PHY_RADAR); - AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); - AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); - AR5K_PRINT("\n"); -#endif -} - -int ath5k_hw_get_capability(struct ath_hw *hal, - enum ath5k_capability_type cap_type, - u32 capability, u32 *result) -{ - AR5K_TRACE; - - switch (cap_type) { - case AR5K_CAP_REG_DMN: - if (result){ - *result = ath5k_get_regdomain(hal); - goto yes; - } - case AR5K_CAP_NUM_TXQUEUES: - if (result) { - if (hal->ah_version == AR5K_AR5210) - *result = AR5K_NUM_TX_QUEUES_NOQCU; - else - *result = AR5K_NUM_TX_QUEUES; - goto yes; - } - case AR5K_CAP_VEOL: - goto yes; - case AR5K_CAP_COMPRESSION: - if (hal->ah_version == AR5K_AR5212) - goto yes; - else - goto no; - case AR5K_CAP_BURST: - goto yes; - case AR5K_CAP_TPC: - goto yes; - case AR5K_CAP_BSSIDMASK: - if (hal->ah_version == AR5K_AR5212) - goto yes; - else - goto no; - case AR5K_CAP_XR: - if (hal->ah_version == AR5K_AR5212) - goto yes; - else - goto no; - default: - goto no; - } - - no: - return -EINVAL; - yes: - return 0; - -} - -int ath5k_hw_set_capability(struct ath_hw *hal, - enum ath5k_capability_type cap_type, - u32 capability, u32 setting) -{ - AR5K_TRACE; - - return 0; -} - -bool -ath5k_hw_query_pspoll_support(struct ath_hw *hal) -{ - AR5K_TRACE; - if (hal->ah_version == AR5K_AR5210) - return(true); - - return false; -} - -bool -ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, - u16 assoc_id) -{ - AR5K_TRACE; - if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_NO_PSPOLL | - AR5K_STA_ID1_DEFAULT_ANTENNA); - return true; - } - - return false; -} - -bool -ath5k_hw_disable_pspoll(struct ath_hw *hal) -{ - AR5K_TRACE; - if (hal->ah_version == AR5K_AR5210) { - AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_NO_PSPOLL | - AR5K_STA_ID1_DEFAULT_ANTENNA); - return true; - } - - return false; -} diff --git a/openhal/ath5k_hw.h b/openhal/ath5k_hw.h deleted file mode 100644 index 92ff4cf..0000000 --- a/openhal/ath5k_hw.h +++ /dev/null @@ -1,2216 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * Gain settings - */ - -enum ath5k_rfgain { - AR5K_RFGAIN_INACTIVE = 0, - AR5K_RFGAIN_READ_REQUESTED, - AR5K_RFGAIN_NEED_CHANGE, -}; - -#define AR5K_GAIN_CRN_FIX_BITS_5111 4 -#define AR5K_GAIN_CRN_FIX_BITS_5112 7 -#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 -#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 -#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 -#define AR5K_GAIN_CCK_PROBE_CORR 5 -#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 -#define AR5K_GAIN_STEP_COUNT 10 -#define AR5K_GAIN_PARAM_TX_CLIP 0 -#define AR5K_GAIN_PARAM_PD_90 1 -#define AR5K_GAIN_PARAM_PD_84 2 -#define AR5K_GAIN_PARAM_GAIN_SEL 3 -#define AR5K_GAIN_PARAM_MIX_ORN 0 -#define AR5K_GAIN_PARAM_PD_138 1 -#define AR5K_GAIN_PARAM_PD_137 2 -#define AR5K_GAIN_PARAM_PD_136 3 -#define AR5K_GAIN_PARAM_PD_132 4 -#define AR5K_GAIN_PARAM_PD_131 5 -#define AR5K_GAIN_PARAM_PD_130 6 -#define AR5K_GAIN_CHECK_ADJUST(_g) \ - ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) - -struct ath5k_gain_opt_step { - int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; - int32_t gos_gain; -}; - -struct ath5k_gain_opt { - u32 go_default; - u32 go_steps_count; - const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; -}; - -struct ath5k_gain { - u32 g_step_idx; - u32 g_current; - u32 g_target; - u32 g_low; - u32 g_high; - u32 g_f_corr; - u32 g_active; - const struct ath5k_gain_opt_step *g_step; -}; - -/* - * Gain optimization tables... - */ -#define AR5K_RF5111_GAIN_OPT { \ - 4, \ - 9, \ - { \ - { { 4, 1, 1, 1 }, 6 }, \ - { { 4, 0, 1, 1 }, 4 }, \ - { { 3, 1, 1, 1 }, 3 }, \ - { { 4, 0, 0, 1 }, 1 }, \ - { { 4, 1, 1, 0 }, 0 }, \ - { { 4, 0, 1, 0 }, -2 }, \ - { { 3, 1, 1, 0 }, -3 }, \ - { { 4, 0, 0, 0 }, -4 }, \ - { { 2, 1, 1, 0 }, -6 } \ - } \ -} - -#define AR5K_RF5112_GAIN_OPT { \ - 1, \ - 8, \ - { \ - { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \ - { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \ - { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \ - { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \ - { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \ - { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \ - { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \ - { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \ - } \ -} - -/* Some EEPROM defines */ -#define AR5K_EEPROM_EEP_SCALE 100 -#define AR5K_EEPROM_EEP_DELTA 10 -#define AR5K_EEPROM_N_MODES 3 -#define AR5K_EEPROM_N_5GHZ_CHAN 10 -#define AR5K_EEPROM_N_2GHZ_CHAN 3 -#define AR5K_EEPROM_MAX_CHAN 10 -#define AR5K_EEPROM_N_PCDAC 11 -#define AR5K_EEPROM_N_TEST_FREQ 8 -#define AR5K_EEPROM_N_EDGES 8 -#define AR5K_EEPROM_N_INTERCEPTS 11 -#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) -#define AR5K_EEPROM_PCDAC_M 0x3f -#define AR5K_EEPROM_PCDAC_START 1 -#define AR5K_EEPROM_PCDAC_STOP 63 -#define AR5K_EEPROM_PCDAC_STEP 1 -#define AR5K_EEPROM_NON_EDGE_M 0x40 -#define AR5K_EEPROM_CHANNEL_POWER 8 -#define AR5K_EEPROM_N_OBDB 4 -#define AR5K_EEPROM_OBDB_DIS 0xffff -#define AR5K_EEPROM_CHANNEL_DIS 0xff -#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) -#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) -#define AR5K_EEPROM_MAX_CTLS 32 -#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 -#define AR5K_EEPROM_N_XPD0_POINTS 4 -#define AR5K_EEPROM_N_XPD3_POINTS 3 -#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 -#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 -#define AR5K_EEPROM_POWER_M 0x3f -#define AR5K_EEPROM_POWER_MIN 0 -#define AR5K_EEPROM_POWER_MAX 3150 -#define AR5K_EEPROM_POWER_STEP 50 -#define AR5K_EEPROM_POWER_TABLE_SIZE 64 -#define AR5K_EEPROM_N_POWER_LOC_11B 4 -#define AR5K_EEPROM_N_POWER_LOC_11G 6 -#define AR5K_EEPROM_I_GAIN 10 -#define AR5K_EEPROM_CCK_OFDM_DELTA 15 -#define AR5K_EEPROM_N_IQ_CAL 2 - -struct ath5k_eeprom_info { - u16 ee_magic; - u16 ee_protect; - u16 ee_regdomain; - u16 ee_version; - u16 ee_header; - u16 ee_ant_gain; - u16 ee_misc0; - u16 ee_misc1; - u16 ee_cck_ofdm_gain_delta; - u16 ee_cck_ofdm_power_delta; - u16 ee_scaled_cck_delta; - u16 ee_tx_clip; - u16 ee_pwd_84; - u16 ee_pwd_90; - u16 ee_gain_select; - - u16 ee_i_cal[AR5K_EEPROM_N_MODES]; - u16 ee_q_cal[AR5K_EEPROM_N_MODES]; - u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; - u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; - u16 ee_xr_power[AR5K_EEPROM_N_MODES]; - u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; - u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; - u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; - u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; - u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; - u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; - u16 ee_thr_62[AR5K_EEPROM_N_MODES]; - u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; - u16 ee_xpd[AR5K_EEPROM_N_MODES]; - u16 ee_x_gain[AR5K_EEPROM_N_MODES]; - u16 ee_i_gain[AR5K_EEPROM_N_MODES]; - u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; - u16 ee_false_detect[AR5K_EEPROM_N_MODES]; - u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; - u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; - - u16 ee_ctls; - u16 ee_ctl[AR5K_EEPROM_MAX_CTLS]; - - int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; - int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; - int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; -}; - -/* - * AR5k register access - */ - -/*Swap RX/TX Descriptor for big endian archs*/ -#if defined(__BIG_ENDIAN) -#define AR5K_INIT_CFG ( \ - AR5K_CFG_SWTD | AR5K_CFG_SWRD \ -) -#else -#define AR5K_INIT_CFG 0x00000000 -#endif - -/*#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg) - -#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg)*/ - -#define AR5K_REG_SM(_val, _flags) \ - (((_val) << _flags##_S) & (_flags)) - -#define AR5K_REG_MS(_val, _flags) \ - (((_val) & (_flags)) >> _flags##_S) - -/* Some registers can hold multiple values of interest. For this - * reason when we want to write to these registers we must first - * retrieve the values which we do not want to clear (lets call this - * old_data) and then set the register with this and our new_value: - * ( old_data | new_value) */ -#define AR5K_REG_WRITE_BITS(hal, _reg, _flags, _val) \ - ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & ~(_flags)) | \ - (((_val) << _flags##_S) & (_flags)), _reg) - -#define AR5K_REG_MASKED_BITS(hal, _reg, _flags, _mask) \ - ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & \ - (_mask)) | (_flags), _reg) - -#define AR5K_REG_ENABLE_BITS(hal, _reg, _flags) \ - ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) | (_flags), _reg) - -#define AR5K_REG_DISABLE_BITS(hal, _reg, _flags) \ - ath5k_hw_reg_write(hal, ath5k_hw_reg_read(hal, _reg) & ~(_flags), _reg) - -#define AR5K_PHY_WRITE(hal, _reg, _val) \ - ath5k_hw_reg_write(hal, _val, (hal)->ah_phy + ((_reg) << 2)) - -#define AR5K_PHY_READ(hal, _reg) \ - ath5k_hw_reg_read(hal, (hal)->ah_phy + ((_reg) << 2)) - -#define AR5K_REG_WAIT(_i) \ - if (_i % 64) \ - udelay(1); - -#define AR5K_EEPROM_READ(_o, _v) { \ - if ((ret = ath5k_hw_eeprom_read(hal, (_o), &(_v))) != 0) \ - return (ret); \ -} - -#define AR5K_EEPROM_READ_HDR(_o, _v) \ - AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ - -/* Read status of selected queue */ -#define AR5K_REG_READ_Q(hal, _reg, _queue) \ - (ath5k_hw_reg_read(hal, _reg) & (1 << _queue)) \ - -#define AR5K_REG_WRITE_Q(hal, _reg, _queue) \ - ath5k_hw_reg_write(hal, (1 << _queue), _reg) - -#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ - _reg |= 1 << _queue; \ -} while (0) - -#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ - _reg &= ~(1 << _queue); \ -} while (0) - -/* - * Unaligned little endian access - */ -#define AR5K_LE_READ_2 ath5k_hw_read_unaligned_16 -#define AR5K_LE_READ_4 ath5k_hw_read_unaligned_32 -#define AR5K_LE_WRITE_2 ath5k_hw_write_unaligned_16 -#define AR5K_LE_WRITE_4 ath5k_hw_write_unaligned_32 - -#define AR5K_LOW_ID(_a)( \ -(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ -) - -#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) - -/* - * Initial register values - */ - -/* - * Common initial register values - */ -#define AR5K_INIT_MODE CHANNEL_B - -#define AR5K_INIT_TX_LATENCY 502 -#define AR5K_INIT_USEC 39 -#define AR5K_INIT_USEC_TURBO 79 -#define AR5K_INIT_USEC_32 31 -#define AR5K_INIT_CARR_SENSE_EN 1 -#define AR5K_INIT_PROG_IFS 920 -#define AR5K_INIT_PROG_IFS_TURBO 960 -#define AR5K_INIT_EIFS 3440 -#define AR5K_INIT_EIFS_TURBO 6880 -#define AR5K_INIT_SLOT_TIME 396 -#define AR5K_INIT_SLOT_TIME_TURBO 480 -#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 -#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 -#define AR5K_INIT_SIFS 560 -#define AR5K_INIT_SIFS_TURBO 480 -#define AR5K_INIT_SH_RETRY 10 -#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY -#define AR5K_INIT_SSH_RETRY 32 -#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY -#define AR5K_INIT_TX_RETRY 10 -#define AR5K_INIT_TOPS 8 -#define AR5K_INIT_RXNOFRM 8 -#define AR5K_INIT_RPGTO 0 -#define AR5K_INIT_TXNOFRM 0 -#define AR5K_INIT_BEACON_PERIOD 65535 -#define AR5K_INIT_TIM_OFFSET 0 -#define AR5K_INIT_BEACON_EN 0 -#define AR5K_INIT_RESET_TSF 0 - -#define AR5K_INIT_TRANSMIT_LATENCY ( \ - (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ - (AR5K_INIT_USEC) \ -) -#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ - (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ - (AR5K_INIT_USEC_TURBO) \ -) -#define AR5K_INIT_PROTO_TIME_CNTRL ( \ - (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ - (AR5K_INIT_PROG_IFS) \ -) -#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ - (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ - (AR5K_INIT_PROG_IFS_TURBO) \ -) -#define AR5K_INIT_BEACON_CONTROL ( \ - (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ - (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ -) - -/* - * Non - common initial register values - */ - -#define AR5K_INI_VAL_11A 0 -#define AR5K_INI_VAL_11A_TURBO 1 -#define AR5K_INI_VAL_11B 2 -#define AR5K_INI_VAL_11G 3 -#define AR5K_INI_VAL_11G_TURBO 4 -#define AR5K_INI_VAL_XR 0 -#define AR5K_INI_VAL_MAX 5 - -#define AR5K_INI_PHY_5111 0 -#define AR5K_INI_PHY_5112 1 -#define AR5K_INI_PHY_511X 1 - -#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS -#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS - -struct ath5k_ini_rf { - u8 rf_bank; - u16 rf_register; - u32 rf_value[5]; -}; - -#define AR5K_RF5111_INI_RF { \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ - { 0, 0x989c, \ - { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ - { 0, 0x98d4, \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ - { 1, 0x98d4, \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d4, \ - { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ - { 3, 0x98d8, \ - { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ - { 6, 0x989c, \ - { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ - { 6, 0x989c, \ - { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ - { 6, 0x989c, \ - { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ - { 6, 0x989c, \ - { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ - { 6, 0x989c, \ - { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ - { 6, 0x98d4, \ - { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ - { 7, 0x989c, \ - { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ - { 7, 0x989c, \ - { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ - { 7, 0x989c, \ - { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ - { 7, 0x989c, \ - { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ - { 7, 0x989c, \ - { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ - { 7, 0x989c, \ - { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ - { 7, 0x989c, \ - { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ - { 7, 0x98cc, \ - { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ -} - -#define AR5K_RF5112_INI_RF { \ - { 1, 0x98d4, \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d0, \ - { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ - { 3, 0x98dc, \ - { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ - { 6, 0x989c, \ - { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ - { 6, 0x989c, \ - { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ - { 6, 0x989c, \ - { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ - { 6, 0x989c, \ - { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ - { 6, 0x989c, \ - { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ - { 6, 0x989c, \ - { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ - { 6, 0x989c, \ - { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ - { 6, 0x989c, \ - { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ - { 6, 0x989c, \ - { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ - { 6, 0x989c, \ - { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ - { 6, 0x989c, \ - { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ - { 6, 0x989c, \ - { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ - { 6, 0x989c, \ - { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ - { 6, 0x989c, \ - { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ - { 6, 0x989c, \ - { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ - { 6, 0x989c, \ - { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ - { 6, 0x989c, \ - { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ - { 6, 0x989c, \ - { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ - { 6, 0x989c, \ - { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ - { 6, 0x989c, \ - { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ - { 6, 0x989c, \ - { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ - { 6, 0x98d0, \ - { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ - { 7, 0x989c, \ - { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ - { 7, 0x989c, \ - { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ - { 7, 0x989c, \ - { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ - { 7, 0x989c, \ - { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ - { 7, 0x989c, \ - { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ - { 7, 0x989c, \ - { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ - { 7, 0x989c, \ - { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ - { 7, 0x989c, \ - { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ - { 7, 0x989c, \ - { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ - { 7, 0x989c, \ - { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ - { 7, 0x989c, \ - { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ - { 7, 0x989c, \ - { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ - { 7, 0x98c4, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ - } - -#define AR5K_RF5112A_INI_RF { \ - { 1, 0x98d4, \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d0, \ - { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ - { 3, 0x98dc, \ - { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ - { 6, 0x989c, \ - { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ - { 6, 0x989c, \ - { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ - { 6, 0x989c, \ - { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ - { 6, 0x989c, \ - { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ - { 6, 0x989c, \ - { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ - { 6, 0x989c, \ - { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ - { 6, 0x989c, \ - { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ - { 6, 0x989c, \ - { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ - { 6, 0x989c, \ - { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ - { 6, 0x989c, \ - { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ - { 6, 0x989c, \ - { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ - { 6, 0x989c, \ - { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ - { 6, 0x989c, \ - { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ - { 6, 0x989c, \ - { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ - { 6, 0x989c, \ - { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ - { 6, 0x989c, \ - { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ - { 6, 0x989c, \ - { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ - { 6, 0x989c, \ - { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ - { 6, 0x989c, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ - { 6, 0x989c, \ - { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ - { 6, 0x989c, \ - { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ - { 6, 0x989c, \ - { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ - { 6, 0x989c, \ - { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ - { 6, 0x98d8, \ - { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ - { 7, 0x989c, \ - { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ - { 7, 0x989c, \ - { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ - { 7, 0x989c, \ - { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ - { 7, 0x989c, \ - { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ - { 7, 0x989c, \ - { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ - { 7, 0x989c, \ - { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ - { 7, 0x989c, \ - { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ - { 7, 0x989c, \ - { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ - { 7, 0x989c, \ - { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ - { 7, 0x989c, \ - { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ - { 7, 0x989c, \ - { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ - { 7, 0x989c, \ - { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ - { 7, 0x98c4, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ -} - -struct ath5k_ini_rfgain { - u16 rfg_register; - u32 rfg_value[2][2]; - -#define AR5K_INI_RFGAIN_5GHZ 0 -#define AR5K_INI_RFGAIN_2GHZ 1 -}; - -#define AR5K_INI_RFGAIN { \ - { 0x9a00, { \ - { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ - { 0x9a04, { \ - { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ - { 0x9a08, { \ - { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ - { 0x9a0c, { \ - { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ - { 0x9a10, { \ - { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ - { 0x9a14, { \ - { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ - { 0x9a18, { \ - { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ - { 0x9a1c, { \ - { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ - { 0x9a20, { \ - { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ - { 0x9a24, { \ - { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ - { 0x9a28, { \ - { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ - { 0x9a2c, { \ - { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ - { 0x9a30, { \ - { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ - { 0x9a34, { \ - { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ - { 0x9a38, { \ - { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ - { 0x9a3c, { \ - { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ - { 0x9a40, { \ - { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ - { 0x9a44, { \ - { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ - { 0x9a48, { \ - { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ - { 0x9a4c, { \ - { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ - { 0x9a50, { \ - { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ - { 0x9a54, { \ - { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ - { 0x9a58, { \ - { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ - { 0x9a5c, { \ - { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ - { 0x9a60, { \ - { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ - { 0x9a64, { \ - { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ - { 0x9a68, { \ - { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ - { 0x9a6c, { \ - { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ - { 0x9a70, { \ - { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ - { 0x9a74, { \ - { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ - { 0x9a78, { \ - { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ - { 0x9a7c, { \ - { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ - { 0x9a80, { \ - { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ - { 0x9a84, { \ - { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ - { 0x9a88, { \ - { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ - { 0x9a8c, { \ - { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ - { 0x9a90, { \ - { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ - { 0x9a94, { \ - { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ - { 0x9a98, { \ - { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ - { 0x9a9c, { \ - { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ - { 0x9aa0, { \ - { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ - { 0x9aa4, { \ - { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ - { 0x9aa8, { \ - { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ - { 0x9aac, { \ - { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ - { 0x9ab0, { \ - { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ - { 0x9ab4, { \ - { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ - { 0x9ab8, { \ - { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ - { 0x9abc, { \ - { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ - { 0x9ac0, { \ - { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ - { 0x9ac4, { \ - { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ - { 0x9ac8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ - { 0x9acc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ - { 0x9ad0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ - { 0x9ad4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ - { 0x9ad8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9adc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9aec, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9afc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ -} - -/* - * Internal RX/TX descriptor structures - * (rX: reserved fields possibily used by future versions of the ar5k chipset) - */ - -struct ath5k_rx_desc { - /* - * RX control word 0 - */ - u32 rx_control_0; - -#define AR5K_DESC_RX_CTL0 0x00000000 - - /* - * RX control word 1 - */ - u32 rx_control_1; - -#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff -#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 -} __packed; - -struct ath5k_hw_old_rx_status { - /* - * RX status word 0 - */ - u32 rx_status_0; - -#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff -#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 - - /* - * RX status word 1 - */ - u32 rx_status_1; - -#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 -#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 -#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 -#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 -#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9 -#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 -#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 -} __packed; - -struct ath5k_hw_new_rx_status { - /* - * RX status word 0 - */ - u32 rx_status_0; - -#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff -#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 -#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 - - /* - * RX status word 1 - */ - u32 rx_status_1; - -#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 -#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 -#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010 -#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9 -#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 -#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 -} __packed; - -struct ath5k_hw_rx_error { - /* - * RX error word 0 - */ - u32 rx_error_0; - -#define AR5K_RX_DESC_ERROR0 0x00000000 - - /* - * RX error word 1 - */ - u32 rx_error_1; - -#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 -#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 -} __packed; - -#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 -#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 -#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 -#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 -#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 -#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 -#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 -#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 - -struct ath5k_hw_2w_tx_desc { - /* - * TX control word 0 - */ - u32 tx_control_0; - -#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff -#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ -#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 -#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 -#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 -#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 -#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 -#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ -#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ -#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (hal->ah_version == AR5K_AR5210 ? \ - AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ - AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 -#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 - - /* - * TX control word 1 - */ - u32 tx_control_1; - -#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff -#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (hal->ah_version == AR5K_AR5210 ? \ - AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ - AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 -#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ -} __packed; - -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 - -struct ath5k_hw_4w_tx_desc { - /* - * TX control word 0 - */ - u32 tx_control_0; - -#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff -#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 -#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 -#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 -#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 -#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 -#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 -#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 -#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 -#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 - - /* - * TX control word 1 - */ - u32 tx_control_1; - -#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff -#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 -#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 -#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 -#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 -#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 -#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 -#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 - - /* - * TX control word 2 - */ - u32 tx_control_2; - -#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff -#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 - - /* - * TX control word 3 - */ - u32 tx_control_3; - -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 -#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 -#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 -} __packed; - -struct ath5k_hw_tx_status { - /* - * TX status word 0 - */ - u32 tx_status_0; - -#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 -#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 -#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 -#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 -/*??? -#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 -#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 -*/ -#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 -#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 -/*??? -#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 -#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 -*/ -#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 -#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 -#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 -#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 -#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 -#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 - - /* - * TX status word 1 - */ - u32 tx_status_1; - -#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 -#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe -#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 -#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 -#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 -#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 -#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 -#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 -#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 -} __packed; - - -/* - * Initial register values which have to be loaded into the - * card at boot time and after each reset. - */ - -struct ath5k_ini { - u16 ini_register; - u32 ini_value; - - enum { - AR5K_INI_WRITE = 0, - AR5K_INI_READ = 1, - } ini_mode; -}; - -#define AR5K_AR5210_INI { \ - /* PCU and MAC registers */ \ - { AR5K_NOQCU_TXDP0, 0 }, \ - { AR5K_NOQCU_TXDP1, 0 }, \ - { AR5K_RXDP, 0 }, \ - { AR5K_CR, 0 }, \ - { AR5K_ISR, 0, AR5K_INI_READ }, \ - { AR5K_IMR, 0 }, \ - { AR5K_IER, AR5K_IER_DISABLE }, \ - { AR5K_BSR, 0, AR5K_INI_READ }, \ - { AR5K_TXCFG, AR5K_DMASIZE_128B }, \ - { AR5K_RXCFG, AR5K_DMASIZE_128B }, \ - { AR5K_CFG, AR5K_INIT_CFG }, \ - { AR5K_TOPS, AR5K_INIT_TOPS }, \ - { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \ - { AR5K_RPGTO, AR5K_INIT_RPGTO }, \ - { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \ - { AR5K_SFR, 0 }, \ - { AR5K_MIBC, 0 }, \ - { AR5K_MISC, 0 }, \ - { AR5K_RX_FILTER_5210, 0 }, \ - { AR5K_MCAST_FILTER0_5210, 0 }, \ - { AR5K_MCAST_FILTER1_5210, 0 }, \ - { AR5K_TX_MASK0, 0 }, \ - { AR5K_TX_MASK1, 0 }, \ - { AR5K_CLR_TMASK, 0 }, \ - { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ - { AR5K_DIAG_SW_5210, 0 }, \ - { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ - { AR5K_TSF_L32_5210, 0 }, \ - { AR5K_TIMER0_5210, 0 }, \ - { AR5K_TIMER1_5210, 0xffffffff }, \ - { AR5K_TIMER2_5210, 0xffffffff }, \ - { AR5K_TIMER3_5210, 1 }, \ - { AR5K_CFP_DUR_5210, 0 }, \ - { AR5K_CFP_PERIOD_5210, 0 }, \ - /* PHY registers */ \ - { AR5K_PHY(0), 0x00000047 }, \ - { AR5K_PHY_AGC, 0x00000000 }, \ - { AR5K_PHY(3), 0x09848ea6 }, \ - { AR5K_PHY(4), 0x3d32e000 }, \ - { AR5K_PHY(5), 0x0000076b }, \ - { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \ - { AR5K_PHY(8), 0x02020200 }, \ - { AR5K_PHY(9), 0x00000e0e }, \ - { AR5K_PHY(10), 0x0a020201 }, \ - { AR5K_PHY(11), 0x00036ffc }, \ - { AR5K_PHY(12), 0x00000000 }, \ - { AR5K_PHY(13), 0x00000e0e }, \ - { AR5K_PHY(14), 0x00000007 }, \ - { AR5K_PHY(15), 0x00020100 }, \ - { AR5K_PHY(16), 0x89630000 }, \ - { AR5K_PHY(17), 0x1372169c }, \ - { AR5K_PHY(18), 0x0018b633 }, \ - { AR5K_PHY(19), 0x1284613c }, \ - { AR5K_PHY(20), 0x0de8b8e0 }, \ - { AR5K_PHY(21), 0x00074859 }, \ - { AR5K_PHY(22), 0x7e80beba }, \ - { AR5K_PHY(23), 0x313a665e }, \ - { AR5K_PHY_AGCCTL, 0x00001d08 }, \ - { AR5K_PHY(25), 0x0001ce00 }, \ - { AR5K_PHY(26), 0x409a4190 }, \ - { AR5K_PHY(28), 0x0000000f }, \ - { AR5K_PHY(29), 0x00000080 }, \ - { AR5K_PHY(30), 0x00000004 }, \ - { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \ - { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \ - { AR5K_PHY(65), 0x00000000 }, \ - { AR5K_PHY(66), 0x00000000 }, \ - { AR5K_PHY(67), 0x00800000 }, \ - { AR5K_PHY(68), 0x00000003 }, \ - /* BB gain table (64bytes) */ \ - { AR5K_BB_GAIN(0), 0x00000000 }, \ - { AR5K_BB_GAIN(0x01), 0x00000020 }, \ - { AR5K_BB_GAIN(0x02), 0x00000010 }, \ - { AR5K_BB_GAIN(0x03), 0x00000030 }, \ - { AR5K_BB_GAIN(0x04), 0x00000008 }, \ - { AR5K_BB_GAIN(0x05), 0x00000028 }, \ - { AR5K_BB_GAIN(0x06), 0x00000028 }, \ - { AR5K_BB_GAIN(0x07), 0x00000004 }, \ - { AR5K_BB_GAIN(0x08), 0x00000024 }, \ - { AR5K_BB_GAIN(0x09), 0x00000014 }, \ - { AR5K_BB_GAIN(0x0a), 0x00000034 }, \ - { AR5K_BB_GAIN(0x0b), 0x0000000c }, \ - { AR5K_BB_GAIN(0x0c), 0x0000002c }, \ - { AR5K_BB_GAIN(0x0d), 0x00000002 }, \ - { AR5K_BB_GAIN(0x0e), 0x00000022 }, \ - { AR5K_BB_GAIN(0x0f), 0x00000012 }, \ - { AR5K_BB_GAIN(0x10), 0x00000032 }, \ - { AR5K_BB_GAIN(0x11), 0x0000000a }, \ - { AR5K_BB_GAIN(0x12), 0x0000002a }, \ - { AR5K_BB_GAIN(0x13), 0x00000001 }, \ - { AR5K_BB_GAIN(0x14), 0x00000021 }, \ - { AR5K_BB_GAIN(0x15), 0x00000011 }, \ - { AR5K_BB_GAIN(0x16), 0x00000031 }, \ - { AR5K_BB_GAIN(0x17), 0x00000009 }, \ - { AR5K_BB_GAIN(0x18), 0x00000029 }, \ - { AR5K_BB_GAIN(0x19), 0x00000005 }, \ - { AR5K_BB_GAIN(0x1a), 0x00000025 }, \ - { AR5K_BB_GAIN(0x1b), 0x00000015 }, \ - { AR5K_BB_GAIN(0x1c), 0x00000035 }, \ - { AR5K_BB_GAIN(0x1d), 0x0000000d }, \ - { AR5K_BB_GAIN(0x1e), 0x0000002d }, \ - { AR5K_BB_GAIN(0x1f), 0x00000003 }, \ - { AR5K_BB_GAIN(0x20), 0x00000023 }, \ - { AR5K_BB_GAIN(0x21), 0x00000013 }, \ - { AR5K_BB_GAIN(0x22), 0x00000033 }, \ - { AR5K_BB_GAIN(0x23), 0x0000000b }, \ - { AR5K_BB_GAIN(0x24), 0x0000002b }, \ - { AR5K_BB_GAIN(0x25), 0x00000007 }, \ - { AR5K_BB_GAIN(0x26), 0x00000027 }, \ - { AR5K_BB_GAIN(0x27), 0x00000017 }, \ - { AR5K_BB_GAIN(0x28), 0x00000037 }, \ - { AR5K_BB_GAIN(0x29), 0x0000000f }, \ - { AR5K_BB_GAIN(0x2a), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2b), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2c), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2d), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2e), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2f), 0x0000002f }, \ - { AR5K_BB_GAIN(0x30), 0x0000002f }, \ - { AR5K_BB_GAIN(0x31), 0x0000002f }, \ - { AR5K_BB_GAIN(0x32), 0x0000002f }, \ - { AR5K_BB_GAIN(0x33), 0x0000002f }, \ - { AR5K_BB_GAIN(0x34), 0x0000002f }, \ - { AR5K_BB_GAIN(0x35), 0x0000002f }, \ - { AR5K_BB_GAIN(0x36), 0x0000002f }, \ - { AR5K_BB_GAIN(0x37), 0x0000002f }, \ - { AR5K_BB_GAIN(0x38), 0x0000002f }, \ - { AR5K_BB_GAIN(0x39), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3a), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3b), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3c), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3d), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3e), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3f), 0x0000002f }, \ - /* RF gain table (64bytes) */ \ - { AR5K_RF_GAIN(0), 0x0000001d }, \ - { AR5K_RF_GAIN(0x01), 0x0000005d }, \ - { AR5K_RF_GAIN(0x02), 0x0000009d }, \ - { AR5K_RF_GAIN(0x03), 0x000000dd }, \ - { AR5K_RF_GAIN(0x04), 0x0000011d }, \ - { AR5K_RF_GAIN(0x05), 0x00000021 }, \ - { AR5K_RF_GAIN(0x06), 0x00000061 }, \ - { AR5K_RF_GAIN(0x07), 0x000000a1 }, \ - { AR5K_RF_GAIN(0x08), 0x000000e1 }, \ - { AR5K_RF_GAIN(0x09), 0x00000031 }, \ - { AR5K_RF_GAIN(0x0a), 0x00000071 }, \ - { AR5K_RF_GAIN(0x0b), 0x000000b1 }, \ - { AR5K_RF_GAIN(0x0c), 0x0000001c }, \ - { AR5K_RF_GAIN(0x0d), 0x0000005c }, \ - { AR5K_RF_GAIN(0x0e), 0x00000029 }, \ - { AR5K_RF_GAIN(0x0f), 0x00000069 }, \ - { AR5K_RF_GAIN(0x10), 0x000000a9 }, \ - { AR5K_RF_GAIN(0x11), 0x00000020 }, \ - { AR5K_RF_GAIN(0x12), 0x00000019 }, \ - { AR5K_RF_GAIN(0x13), 0x00000059 }, \ - { AR5K_RF_GAIN(0x14), 0x00000099 }, \ - { AR5K_RF_GAIN(0x15), 0x00000030 }, \ - { AR5K_RF_GAIN(0x16), 0x00000005 }, \ - { AR5K_RF_GAIN(0x17), 0x00000025 }, \ - { AR5K_RF_GAIN(0x18), 0x00000065 }, \ - { AR5K_RF_GAIN(0x19), 0x000000a5 }, \ - { AR5K_RF_GAIN(0x1a), 0x00000028 }, \ - { AR5K_RF_GAIN(0x1b), 0x00000068 }, \ - { AR5K_RF_GAIN(0x1c), 0x0000001f }, \ - { AR5K_RF_GAIN(0x1d), 0x0000001e }, \ - { AR5K_RF_GAIN(0x1e), 0x00000018 }, \ - { AR5K_RF_GAIN(0x1f), 0x00000058 }, \ - { AR5K_RF_GAIN(0x20), 0x00000098 }, \ - { AR5K_RF_GAIN(0x21), 0x00000003 }, \ - { AR5K_RF_GAIN(0x22), 0x00000004 }, \ - { AR5K_RF_GAIN(0x23), 0x00000044 }, \ - { AR5K_RF_GAIN(0x24), 0x00000084 }, \ - { AR5K_RF_GAIN(0x25), 0x00000013 }, \ - { AR5K_RF_GAIN(0x26), 0x00000012 }, \ - { AR5K_RF_GAIN(0x27), 0x00000052 }, \ - { AR5K_RF_GAIN(0x28), 0x00000092 }, \ - { AR5K_RF_GAIN(0x29), 0x000000d2 }, \ - { AR5K_RF_GAIN(0x2a), 0x0000002b }, \ - { AR5K_RF_GAIN(0x2b), 0x0000002a }, \ - { AR5K_RF_GAIN(0x2c), 0x0000006a }, \ - { AR5K_RF_GAIN(0x2d), 0x000000aa }, \ - { AR5K_RF_GAIN(0x2e), 0x0000001b }, \ - { AR5K_RF_GAIN(0x2f), 0x0000001a }, \ - { AR5K_RF_GAIN(0x30), 0x0000005a }, \ - { AR5K_RF_GAIN(0x31), 0x0000009a }, \ - { AR5K_RF_GAIN(0x32), 0x000000da }, \ - { AR5K_RF_GAIN(0x33), 0x00000006 }, \ - { AR5K_RF_GAIN(0x34), 0x00000006 }, \ - { AR5K_RF_GAIN(0x35), 0x00000006 }, \ - { AR5K_RF_GAIN(0x36), 0x00000006 }, \ - { AR5K_RF_GAIN(0x37), 0x00000006 }, \ - { AR5K_RF_GAIN(0x38), 0x00000006 }, \ - { AR5K_RF_GAIN(0x39), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3a), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3b), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3c), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3d), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3e), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3f), 0x00000006 }, \ - /* PHY activation */ \ - { AR5K_PHY(53), 0x00000020 }, \ - { AR5K_PHY(51), 0x00000004 }, \ - { AR5K_PHY(50), 0x00060106 }, \ - { AR5K_PHY(39), 0x0000006d }, \ - { AR5K_PHY(48), 0x00000000 }, \ - { AR5K_PHY(52), 0x00000014 }, \ - { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \ -} - -struct ath5k_ar5210_ini_mode{ - u16 mode_register; - u32 mode_base, mode_turbo; -}; - -#define AR5K_AR5210_INI_MODE(hal, _aifs) { \ - { AR5K_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME_TURBO }, \ - { AR5K_SLOT_TIME, \ - AR5K_INIT_ACK_CTS_TIMEOUT, \ - AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \ - { AR5K_USEC_5210, \ - AR5K_INIT_TRANSMIT_LATENCY, \ - AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \ - { AR5K_IFS0, \ - ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ - << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS, \ - ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \ - << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \ - { AR5K_IFS1, \ - AR5K_INIT_PROTO_TIME_CNTRL, \ - AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ - { AR5K_PHY(17), \ - (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x1C, \ - (ath5k_hw_reg_read(hal, AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ - { AR5K_PHY_FRAME_CTL_5210, \ - AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ - AR5K_PHY_FRAME_CTL_TXURN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ - AR5K_PHY_FRAME_CTL_PARITY_ERR | \ - AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x1020, \ - AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ - AR5K_PHY_FRAME_CTL_TXURN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ - AR5K_PHY_FRAME_CTL_PARITY_ERR | \ - /*PHY_TURBO is PHY_FRAME_CTL on 5210*/ \ - AR5K_PHY_TURBO_MODE | \ - AR5K_PHY_TURBO_SHORT | \ - AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x2020 }, \ -} - -#define AR5K_AR5211_INI { \ - { 0x000c, 0x00000000 }, \ - { 0x0028, 0x84849c9c }, \ - { 0x002c, 0x7c7c7c7c }, \ - { 0x0034, 0x00000005 }, \ - { 0x0040, 0x00000000 }, \ - { 0x0044, 0x00000008 }, \ - { 0x0048, 0x00000008 }, \ - { 0x004c, 0x00000010 }, \ - { 0x0050, 0x00000000 }, \ - { 0x0054, 0x0000001f }, \ - { 0x0800, 0x00000000 }, \ - { 0x0804, 0x00000000 }, \ - { 0x0808, 0x00000000 }, \ - { 0x080c, 0x00000000 }, \ - { 0x0810, 0x00000000 }, \ - { 0x0814, 0x00000000 }, \ - { 0x0818, 0x00000000 }, \ - { 0x081c, 0x00000000 }, \ - { 0x0820, 0x00000000 }, \ - { 0x0824, 0x00000000 }, \ - { 0x1230, 0x00000000 }, \ - { 0x8004, 0x00000000 }, \ - { 0x8008, 0x00000000 }, \ - { 0x800c, 0x00000000 }, \ - { 0x8018, 0x00000000 }, \ - { 0x8024, 0x00000000 }, \ - { 0x8028, 0x00000030 }, \ - { 0x802c, 0x0007ffff }, \ - { 0x8030, 0x01ffffff }, \ - { 0x8034, 0x00000031 }, \ - { 0x8038, 0x00000000 }, \ - { 0x803c, 0x00000000 }, \ - { 0x8040, 0x00000000 }, \ - { 0x8044, 0x00000002 }, \ - { 0x8048, 0x00000000 }, \ - { 0x8054, 0x00000000 }, \ - { 0x8058, 0x00000000 }, \ - /* PHY registers */ \ - { 0x9808, 0x00000000 }, \ - { 0x980c, 0x2d849093 }, \ - { 0x9810, 0x7d32e000 }, \ - { 0x9814, 0x00000f6b }, \ - { 0x981c, 0x00000000 }, \ - { 0x982c, 0x00026ffe }, \ - { 0x9830, 0x00000000 }, \ - { 0x983c, 0x00020100 }, \ - { 0x9840, 0x206a017a }, \ - { 0x984c, 0x1284613c }, \ - { 0x9854, 0x00000859 }, \ - { 0x9868, 0x409a4190 }, \ - { 0x986c, 0x050cb081 }, \ - { 0x9870, 0x0000000f }, \ - { 0x9874, 0x00000080 }, \ - { 0x9878, 0x0000000c }, \ - { 0x9900, 0x00000000 }, \ - { 0x9904, 0x00000000 }, \ - { 0x9908, 0x00000000 }, \ - { 0x990c, 0x00800000 }, \ - { 0x9910, 0x00000001 }, \ - { 0x991c, 0x0000092a }, \ - { 0x9920, 0x00000000 }, \ - { 0x9924, 0x00058a05 }, \ - { 0x9928, 0x00000001 }, \ - { 0x992c, 0x00000000 }, \ - { 0x9930, 0x00000000 }, \ - { 0x9934, 0x00000000 }, \ - { 0x9938, 0x00000000 }, \ - { 0x993c, 0x0000003f }, \ - { 0x9940, 0x00000004 }, \ - { 0x9948, 0x00000000 }, \ - { 0x994c, 0x00000000 }, \ - { 0x9950, 0x00000000 }, \ - { 0x9954, 0x5d50f14c }, \ - { 0x9958, 0x00000018 }, \ - { 0x995c, 0x004b6a8e }, \ - { 0xa184, 0x06ff05ff }, \ - { 0xa188, 0x07ff07ff }, \ - { 0xa18c, 0x08ff08ff }, \ - { 0xa190, 0x09ff09ff }, \ - { 0xa194, 0x0aff0aff }, \ - { 0xa198, 0x0bff0bff }, \ - { 0xa19c, 0x0cff0cff }, \ - { 0xa1a0, 0x0dff0dff }, \ - { 0xa1a4, 0x0fff0eff }, \ - { 0xa1a8, 0x12ff12ff }, \ - { 0xa1ac, 0x14ff13ff }, \ - { 0xa1b0, 0x16ff15ff }, \ - { 0xa1b4, 0x19ff17ff }, \ - { 0xa1b8, 0x1bff1aff }, \ - { 0xa1bc, 0x1eff1dff }, \ - { 0xa1c0, 0x23ff20ff }, \ - { 0xa1c4, 0x27ff25ff }, \ - { 0xa1c8, 0x2cff29ff }, \ - { 0xa1cc, 0x31ff2fff }, \ - { 0xa1d0, 0x37ff34ff }, \ - { 0xa1d4, 0x3aff3aff }, \ - { 0xa1d8, 0x3aff3aff }, \ - { 0xa1dc, 0x3aff3aff }, \ - { 0xa1e0, 0x3aff3aff }, \ - { 0xa1e4, 0x3aff3aff }, \ - { 0xa1e8, 0x3aff3aff }, \ - { 0xa1ec, 0x3aff3aff }, \ - { 0xa1f0, 0x3aff3aff }, \ - { 0xa1f4, 0x3aff3aff }, \ - { 0xa1f8, 0x3aff3aff }, \ - { 0xa1fc, 0x3aff3aff }, \ - /* BB gain table (64bytes) */ \ - { 0x9b00, 0x00000000 }, \ - { 0x9b04, 0x00000020 }, \ - { 0x9b08, 0x00000010 }, \ - { 0x9b0c, 0x00000030 }, \ - { 0x9b10, 0x00000008 }, \ - { 0x9b14, 0x00000028 }, \ - { 0x9b18, 0x00000004 }, \ - { 0x9b1c, 0x00000024 }, \ - { 0x9b20, 0x00000014 }, \ - { 0x9b24, 0x00000034 }, \ - { 0x9b28, 0x0000000c }, \ - { 0x9b2c, 0x0000002c }, \ - { 0x9b30, 0x00000002 }, \ - { 0x9b34, 0x00000022 }, \ - { 0x9b38, 0x00000012 }, \ - { 0x9b3c, 0x00000032 }, \ - { 0x9b40, 0x0000000a }, \ - { 0x9b44, 0x0000002a }, \ - { 0x9b48, 0x00000006 }, \ - { 0x9b4c, 0x00000026 }, \ - { 0x9b50, 0x00000016 }, \ - { 0x9b54, 0x00000036 }, \ - { 0x9b58, 0x0000000e }, \ - { 0x9b5c, 0x0000002e }, \ - { 0x9b60, 0x00000001 }, \ - { 0x9b64, 0x00000021 }, \ - { 0x9b68, 0x00000011 }, \ - { 0x9b6c, 0x00000031 }, \ - { 0x9b70, 0x00000009 }, \ - { 0x9b74, 0x00000029 }, \ - { 0x9b78, 0x00000005 }, \ - { 0x9b7c, 0x00000025 }, \ - { 0x9b80, 0x00000015 }, \ - { 0x9b84, 0x00000035 }, \ - { 0x9b88, 0x0000000d }, \ - { 0x9b8c, 0x0000002d }, \ - { 0x9b90, 0x00000003 }, \ - { 0x9b94, 0x00000023 }, \ - { 0x9b98, 0x00000013 }, \ - { 0x9b9c, 0x00000033 }, \ - { 0x9ba0, 0x0000000b }, \ - { 0x9ba4, 0x0000002b }, \ - { 0x9ba8, 0x0000002b }, \ - { 0x9bac, 0x0000002b }, \ - { 0x9bb0, 0x0000002b }, \ - { 0x9bb4, 0x0000002b }, \ - { 0x9bb8, 0x0000002b }, \ - { 0x9bbc, 0x0000002b }, \ - { 0x9bc0, 0x0000002b }, \ - { 0x9bc4, 0x0000002b }, \ - { 0x9bc8, 0x0000002b }, \ - { 0x9bcc, 0x0000002b }, \ - { 0x9bd0, 0x0000002b }, \ - { 0x9bd4, 0x0000002b }, \ - { 0x9bd8, 0x0000002b }, \ - { 0x9bdc, 0x0000002b }, \ - { 0x9be0, 0x0000002b }, \ - { 0x9be4, 0x0000002b }, \ - { 0x9be8, 0x0000002b }, \ - { 0x9bec, 0x0000002b }, \ - { 0x9bf0, 0x0000002b }, \ - { 0x9bf4, 0x0000002b }, \ - { 0x9bf8, 0x00000002 }, \ - { 0x9bfc, 0x00000016 }, \ - /* PHY activation */ \ - { 0x98d4, 0x00000020 }, \ - { 0x98d8, 0x00601068 }, \ -} - -struct ath5k_ar5212_ini { - u8 ini_flags; - u16 ini_register; - u32 ini_value; - -#define AR5K_INI_FLAG_511X 0x00 -#define AR5K_INI_FLAG_5111 0x01 -#define AR5K_INI_FLAG_5112 0x02 -#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) -}; - -#define AR5K_AR5212_INI { \ - { AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 }, \ - { AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 }, \ - { AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f }, \ - { AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x081c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0820, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0824, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1230, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1270, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1078, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1138, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1178, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1238, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1278, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1338, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1378, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1438, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1478, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1538, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1578, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1638, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1678, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1738, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1778, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x103c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x107c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x113c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x117c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x123c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x127c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x133c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x137c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x143c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x147c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8004, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8008, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x800c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8018, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8020, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8024, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8028, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x802c, 0x0007ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8030, 0x01ffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8034, 0x00000031 }, \ - { AR5K_INI_FLAG_BOTH, 0x8038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x803c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8048, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8054, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8058, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x805c, 0xffffc7ff }, \ - { AR5K_INI_FLAG_BOTH, 0x8080, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8084, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8088, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x808c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8090, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8094, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8098, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c0, 0x2a82301a }, \ - { AR5K_INI_FLAG_BOTH, 0x80c4, 0x05dc01e0 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c8, 0x1f402710 }, \ - { AR5K_INI_FLAG_BOTH, 0x80cc, 0x01f40000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80d0, 0x00001e1c }, \ - { AR5K_INI_FLAG_BOTH, 0x80d4, 0x0002aaaa }, \ - { AR5K_INI_FLAG_BOTH, 0x80d8, 0x02005555 }, \ - { AR5K_INI_FLAG_BOTH, 0x80dc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80e0, 0xffffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e4, 0x0000ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80ec, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f0, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f4, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80fc, 0x00000088 }, \ - { AR5K_INI_FLAG_BOTH, 0x8700, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8704, 0x0000008c }, \ - { AR5K_INI_FLAG_BOTH, 0x8708, 0x000000e4 }, \ - { AR5K_INI_FLAG_BOTH, 0x870c, 0x000002d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8710, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8714, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8718, 0x000000a0 }, \ - { AR5K_INI_FLAG_BOTH, 0x871c, 0x000001c9 }, \ - { AR5K_INI_FLAG_BOTH, 0x8720, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8724, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8728, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x872c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8730, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8734, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8738, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x873c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8740, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8744, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8748, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x874c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8750, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8754, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8758, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x875c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8760, 0x000000d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8764, 0x000000df }, \ - { AR5K_INI_FLAG_BOTH, 0x8768, 0x00000102 }, \ - { AR5K_INI_FLAG_BOTH, 0x876c, 0x0000013a }, \ - { AR5K_INI_FLAG_BOTH, 0x8770, 0x00000075 }, \ - { AR5K_INI_FLAG_BOTH, 0x8774, 0x0000007f }, \ - { AR5K_INI_FLAG_BOTH, 0x8778, 0x000000a2 }, \ - { AR5K_INI_FLAG_BOTH, 0x877c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8100, 0x00010002 }, \ - { AR5K_INI_FLAG_BOTH, 0x8104, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x8108, 0x000000c0 }, \ - { AR5K_INI_FLAG_BOTH, 0x810c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8110, 0x00000168 }, \ - { AR5K_INI_FLAG_BOTH, 0x8114, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87cc, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87d0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87dc, 0x1f1e1d1c }, \ - { AR5K_INI_FLAG_BOTH, 0x87e0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87ec, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87f0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87fc, 0x1f1e1d1c }, \ - /* PHY registers */ \ - { AR5K_INI_FLAG_BOTH, 0x9808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x980c, 0xad848e19 }, \ - { AR5K_INI_FLAG_BOTH, 0x9810, 0x7d28e000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9814, 0x9c0a9f6b }, \ - { AR5K_INI_FLAG_BOTH, 0x981c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x982c, 0x00022ffe }, \ - { AR5K_INI_FLAG_BOTH, 0x983c, 0x00020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x9840, 0x206a017a }, \ - { AR5K_INI_FLAG_BOTH, 0x984c, 0x1284613c }, \ - { AR5K_INI_FLAG_BOTH, 0x9854, 0x00000859 }, \ - { AR5K_INI_FLAG_BOTH, 0x9900, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9904, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a }, \ - { AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9934, 0x1e1f2022 }, \ - { AR5K_INI_FLAG_BOTH, 0x9938, 0x0a0b0c0d }, \ - { AR5K_INI_FLAG_BOTH, 0x993c, 0x0000003f }, \ - { AR5K_INI_FLAG_BOTH, 0x9940, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9948, 0x9280b212 }, \ - { AR5K_INI_FLAG_BOTH, 0x9954, 0x5d50e188 }, \ - { AR5K_INI_FLAG_BOTH, 0x9958, 0x000000ff }, \ - { AR5K_INI_FLAG_BOTH, 0x995c, 0x004b6a8e }, \ - { AR5K_INI_FLAG_BOTH, 0x9968, 0x000003ce }, \ - { AR5K_INI_FLAG_BOTH, 0x9970, 0x192fb515 }, \ - { AR5K_INI_FLAG_BOTH, 0x9974, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9978, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x997c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa184, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa188, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa18c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa190, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa194, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa198, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa19c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ac, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1bc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1cc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1dc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ec, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 }, \ - { AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 }, \ - { AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 }, \ - { AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a }, \ - { AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 }, \ - { AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 }, \ - { AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 }, \ - { AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa234, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa238, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa23c, 0x13c889af }, \ - { AR5K_INI_FLAG_BOTH, 0xa240, 0x38490a20 }, \ - { AR5K_INI_FLAG_BOTH, 0xa244, 0x00007bb6 }, \ - { AR5K_INI_FLAG_BOTH, 0xa248, 0x0fff3ffc }, \ - { AR5K_INI_FLAG_BOTH, 0x9b00, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b28, 0x0000000c }, \ - { AR5K_INI_FLAG_BOTH, 0x9b38, 0x00000012 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \ - { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \ - /* RF5111 specific */ \ - { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \ - { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \ - { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \ - { AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a }, \ - { AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 }, \ - { AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 }, \ - { AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 }, \ - { AR5K_INI_FLAG_5111, 0x9b10, 0x00000008 }, \ - { AR5K_INI_FLAG_5111, 0x9b14, 0x00000028 }, \ - { AR5K_INI_FLAG_5111, 0x9b18, 0x00000004 }, \ - { AR5K_INI_FLAG_5111, 0x9b1c, 0x00000024 }, \ - { AR5K_INI_FLAG_5111, 0x9b20, 0x00000014 }, \ - { AR5K_INI_FLAG_5111, 0x9b24, 0x00000034 }, \ - { AR5K_INI_FLAG_5111, 0x9b2c, 0x0000002c }, \ - { AR5K_INI_FLAG_5111, 0x9b30, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9b34, 0x00000022 }, \ - { AR5K_INI_FLAG_5111, 0x9b3c, 0x00000032 }, \ - { AR5K_INI_FLAG_5111, 0x9b40, 0x0000000a }, \ - { AR5K_INI_FLAG_5111, 0x9b44, 0x0000002a }, \ - { AR5K_INI_FLAG_5111, 0x9b48, 0x00000006 }, \ - { AR5K_INI_FLAG_5111, 0x9b4c, 0x00000026 }, \ - { AR5K_INI_FLAG_5111, 0x9b50, 0x00000016 }, \ - { AR5K_INI_FLAG_5111, 0x9b54, 0x00000036 }, \ - { AR5K_INI_FLAG_5111, 0x9b58, 0x0000000e }, \ - { AR5K_INI_FLAG_5111, 0x9b5c, 0x0000002e }, \ - { AR5K_INI_FLAG_5111, 0x9b60, 0x00000001 }, \ - { AR5K_INI_FLAG_5111, 0x9b68, 0x00000011 }, \ - { AR5K_INI_FLAG_5111, 0x9b6c, 0x00000031 }, \ - { AR5K_INI_FLAG_5111, 0x9b70, 0x00000009 }, \ - { AR5K_INI_FLAG_5111, 0x9b74, 0x00000029 }, \ - { AR5K_INI_FLAG_5111, 0x9b78, 0x00000005 }, \ - { AR5K_INI_FLAG_5111, 0x9b7c, 0x00000025 }, \ - { AR5K_INI_FLAG_5111, 0x9b80, 0x00000015 }, \ - { AR5K_INI_FLAG_5111, 0x9b84, 0x00000035 }, \ - { AR5K_INI_FLAG_5111, 0x9b88, 0x0000000d }, \ - { AR5K_INI_FLAG_5111, 0x9b90, 0x00000003 }, \ - { AR5K_INI_FLAG_5111, 0x9b94, 0x00000023 }, \ - { AR5K_INI_FLAG_5111, 0x9b98, 0x00000013 }, \ - { AR5K_INI_FLAG_5111, 0x9ba0, 0x0000000b }, \ - { AR5K_INI_FLAG_5111, 0x9ba4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9ba8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bac, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bbc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bcc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bdc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bec, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \ - /* RF5112 specific */ \ - { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \ - { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \ - { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \ - { AR5K_INI_FLAG_5112, 0x9b0c, 0x00000003 }, \ - { AR5K_INI_FLAG_5112, 0x9b10, 0x00000004 }, \ - { AR5K_INI_FLAG_5112, 0x9b14, 0x00000005 }, \ - { AR5K_INI_FLAG_5112, 0x9b18, 0x00000008 }, \ - { AR5K_INI_FLAG_5112, 0x9b1c, 0x00000009 }, \ - { AR5K_INI_FLAG_5112, 0x9b20, 0x0000000a }, \ - { AR5K_INI_FLAG_5112, 0x9b24, 0x0000000b }, \ - { AR5K_INI_FLAG_5112, 0x9b2c, 0x0000000d }, \ - { AR5K_INI_FLAG_5112, 0x9b30, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9b34, 0x00000011 }, \ - { AR5K_INI_FLAG_5112, 0x9b3c, 0x00000013 }, \ - { AR5K_INI_FLAG_5112, 0x9b40, 0x00000014 }, \ - { AR5K_INI_FLAG_5112, 0x9b44, 0x00000015 }, \ - { AR5K_INI_FLAG_5112, 0x9b48, 0x00000018 }, \ - { AR5K_INI_FLAG_5112, 0x9b4c, 0x00000019 }, \ - { AR5K_INI_FLAG_5112, 0x9b50, 0x0000001a }, \ - { AR5K_INI_FLAG_5112, 0x9b54, 0x0000001b }, \ - { AR5K_INI_FLAG_5112, 0x9b58, 0x0000001c }, \ - { AR5K_INI_FLAG_5112, 0x9b5c, 0x0000001d }, \ - { AR5K_INI_FLAG_5112, 0x9b60, 0x00000020 }, \ - { AR5K_INI_FLAG_5112, 0x9b68, 0x00000022 }, \ - { AR5K_INI_FLAG_5112, 0x9b6c, 0x00000023 }, \ - { AR5K_INI_FLAG_5112, 0x9b70, 0x00000024 }, \ - { AR5K_INI_FLAG_5112, 0x9b74, 0x00000025 }, \ - { AR5K_INI_FLAG_5112, 0x9b78, 0x00000028 }, \ - { AR5K_INI_FLAG_5112, 0x9b7c, 0x00000029 }, \ - { AR5K_INI_FLAG_5112, 0x9b80, 0x0000002a }, \ - { AR5K_INI_FLAG_5112, 0x9b84, 0x0000002b }, \ - { AR5K_INI_FLAG_5112, 0x9b88, 0x0000002c }, \ - { AR5K_INI_FLAG_5112, 0x9b90, 0x00000030 }, \ - { AR5K_INI_FLAG_5112, 0x9b94, 0x00000031 }, \ - { AR5K_INI_FLAG_5112, 0x9b98, 0x00000032 }, \ - { AR5K_INI_FLAG_5112, 0x9ba0, 0x00000034 }, \ - { AR5K_INI_FLAG_5112, 0x9ba4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9ba8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bac, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bbc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bcc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bdc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bec, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf8, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9bfc, 0x0000001a }, \ -} - -struct ath5k_ar5211_ini_mode { - u16 mode_register; - u32 mode_value[4]; -}; - -#define AR5K_AR5211_INI_MODE { \ - { 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \ - { 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, \ - { 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, \ - { 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, \ - { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, \ - { 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, \ - { 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, \ - { 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, \ - { 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, \ - { 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, \ - { 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, \ - { 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ - { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, \ - { 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, \ - { 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, \ - { 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \ - { 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, \ - { 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, \ - { 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, \ - { 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ - { 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, \ - { 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, \ - { 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, \ - { 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, \ - { 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, \ -} - -struct ath5k_ar5212_ini_mode { - u16 mode_register; - u8 mode_flags; - u32 mode_value[2][5]; -}; - -#define AR5K_AR5212_INI_MODE { \ - { 0x0030, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \ - } }, \ - { 0x1040, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1044, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1048, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x104c, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1050, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1054, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1058, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x105c, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1060, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1064, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1030, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } \ - } }, \ - { 0x1070, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } \ - } }, \ - { 0x10b0, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } \ - } }, \ - { 0x10f0, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } \ - } }, \ - { 0x8014, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } \ - } }, \ - { 0x9804, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } \ - } }, \ - { 0x9820, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } \ - } }, \ - { 0x9834, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ - } }, \ - { 0x9838, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } \ - } }, \ - { 0x9844, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 } \ - } }, \ - { 0x9850, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } \ - } }, \ - { 0x9858, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } \ - } }, \ - { 0x9860, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 } \ - } }, \ - { 0x9864, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } \ - } }, \ - { 0x9868, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } \ - } }, \ - { 0x9918, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } \ - } }, \ - { 0x9924, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } \ - } }, \ - { 0xa180, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff } \ - } }, \ - { 0xa230, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } \ - } }, \ - { 0x801c, AR5K_INI_FLAG_BOTH, { \ - { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x128d8fab, 0x09880fcf }, \ - { 0x128d93a7, 0x098813cf, 0x04e01395, 0x128d93ab, 0x098813cf } \ - } }, \ - { 0x9824, AR5K_INI_FLAG_BOTH, { \ - { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e }, \ - { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ - } }, \ - { 0x9828, AR5K_INI_FLAG_BOTH, { \ - { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 }, \ - { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } \ - } }, \ - { 0x9848, AR5K_INI_FLAG_BOTH, { \ - { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 }, \ - { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } \ - } }, \ - { 0x985c, AR5K_INI_FLAG_BOTH, { \ - { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e }, \ - { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } \ - } }, \ - { 0x986c, AR5K_INI_FLAG_BOTH, { \ - { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 }, \ - { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } \ - } }, \ - { 0x9914, AR5K_INI_FLAG_BOTH, { \ - { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 }, \ - { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } \ - } }, \ - { 0x9944, AR5K_INI_FLAG_BOTH, { \ - { 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 }, \ - { 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 } \ - } }, \ - { 0xa204, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } \ - } }, \ - { 0xa208, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } \ - } }, \ - { 0xa20c, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } \ - } }, \ -} - -struct ath5k_ar5211_ini_rf { - u16 rf_register; - u32 rf_value[2]; -}; - -#define AR5K_AR5211_INI_RF { \ - { 0x0000a204, { 0x00000000, 0x00000000 } }, \ - { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \ - { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \ - { 0x0000a210, { 0x0199a003, 0x0199a003 } }, \ - { 0x0000a214, { 0x044cd610, 0x044cd610 } }, \ - { 0x0000a218, { 0x13800040, 0x13800040 } }, \ - { 0x0000a21c, { 0x1be00060, 0x1be00060 } }, \ - { 0x0000a220, { 0x0c53800a, 0x0c53800a } }, \ - { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \ - { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \ - { 0x0000a22c, { 0x00000020, 0x00000020 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00380000, 0x00380000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \ - { 0x000098d4, { 0x00000000, 0x00000004 } }, \ - \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x10000000, 0x10000000 } }, \ - { 0x0000989c, { 0x04000000, 0x04000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x0a000000 } }, \ - { 0x0000989c, { 0x00380080, 0x02380080 } }, \ - { 0x0000989c, { 0x00020006, 0x00000006 } }, \ - { 0x0000989c, { 0x00000092, 0x00000092 } }, \ - { 0x0000989c, { 0x000000a0, 0x000000a0 } }, \ - { 0x0000989c, { 0x00040007, 0x00040007 } }, \ - { 0x000098d4, { 0x0000001a, 0x0000001a } }, \ - { 0x0000989c, { 0x00000048, 0x00000048 } }, \ - { 0x0000989c, { 0x00000010, 0x00000010 } }, \ - { 0x0000989c, { 0x00000008, 0x00000008 } }, \ - { 0x0000989c, { 0x0000000f, 0x0000000f } }, \ - { 0x0000989c, { 0x000000f2, 0x00000062 } }, \ - { 0x0000989c, { 0x0000904f, 0x0000904c } }, \ - { 0x0000989c, { 0x0000125a, 0x0000129a } }, \ - { 0x000098cc, { 0x0000000e, 0x0000000f } }, \ -} diff --git a/openhal/ath5kreg.h b/openhal/ath5kreg.h deleted file mode 100644 index 05c0b88..0000000 --- a/openhal/ath5kreg.h +++ /dev/null @@ -1,1917 +0,0 @@ -/*- - * Copyright (c) 2007 Nick Kossifidis - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -/* - * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k - * maintained by Reyk Floeter - * - * I tried to document those registers by looking at ar5k code, some - * 802.11 (802.11e mostly) papers and by reading various public available - * Atheros presentations and papers like these: - * - * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf - * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf - * - * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf - */ - - - -/*====MAC DMA REGISTERS====*/ - -/* - * AR5210-Specific TXDP registers - * 5210 has only 2 transmit queues so no DCU/QCU, just - * 2 transmit descriptor pointers... - */ -#define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ -#define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ - -/* - * Mac Control Register - */ -#define AR5K_CR 0x0008 /* Register Address */ -#define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ -#define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ -#define AR5K_CR_RXE 0x00000004 /* RX Enable */ -#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ -#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ -#define AR5K_CR_RXD 0x00000020 /* RX Disable */ -#define AR5K_CR_SWI 0x00000040 - -/* - * RX Descriptor Pointer register - */ -#define AR5K_RXDP 0x000c - -/* - * Configuration and status register - */ -#define AR5K_CFG 0x0014 /* Register Address */ -#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ -#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer (?) */ -#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ -#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer (?) */ -#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register values (?) */ -#define AR5K_CFG_ADHOC 0x00000020 /* [5211+] */ -#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ -#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ -#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (?) */ -#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ -#define AR5K_CFG_TXCNT_S 11 -#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ -#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ -#define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ -#define AR5K_CFG_PCI_THRES_S 17 - -/* - * Interrupt enable register - */ -#define AR5K_IER 0x0024 /* Register Address */ -#define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ -#define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ - - -/* - * 0x0028 is Beacon Control Register on 5210 - * and first RTS duration register on 5211 - */ - -/* - * Beacon control register [5210] - */ -#define AR5K_BCR 0x0028 /* Register Address */ -#define AR5K_BCR_AP 0x00000000 /* AP mode */ -#define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ -#define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ -#define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ -#define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ -#define AR5K_BCR_BCGET 0x00000010 - -/* - * First RTS duration register [5211] - */ -#define AR5K_RTSD0 0x0028 /* Register Address */ -#define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ -#define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ -#define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ -#define AR5K_RTSD0_9_S 8 -#define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ -#define AR5K_RTSD0_12_S 16 -#define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ -#define AR5K_RTSD0_18_S 24 - - -/* - * 0x002c is Beacon Status Register on 5210 - * and second RTS duration register on 5211 - */ - -/* - * Beacon status register [5210] - * - * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR - * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning - * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). - * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i - * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what - * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. - */ -#define AR5K_BSR 0x002c /* Register Address */ -#define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ -#define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ -#define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ -#define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ -#define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ -#define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ -#define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ -#define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ -#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ -#define AR5K_BSR_SWBA_CNT 0x00ff0000 - -/* - * Second RTS duration register [5211] - */ -#define AR5K_RTSD1 0x002c /* Register Address */ -#define AR5K_RTSD1_24 0x000000ff /* 24Mb */ -#define AR5K_RTSD1_24_S 0 -#define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ -#define AR5K_RTSD1_36_S 8 -#define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ -#define AR5K_RTSD1_48_S 16 -#define AR5K_RTSD1_54 0xff000000 /* 54Mb */ -#define AR5K_RTSD1_54_S 24 - - -/* - * Transmit configuration register - */ -#define AR5K_TXCFG 0x0030 /* Register Address */ -#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */ -#define AR5K_TXCFG_SDMAMR_S 0 -#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ -#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ -#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ -#define AR5K_TXCFG_TXFULL_S 4 -#define AR5K_TXCFG_TXFULL_0B 0x00000000 -#define AR5K_TXCFG_TXFULL_64B 0x00000010 -#define AR5K_TXCFG_TXFULL_128B 0x00000020 -#define AR5K_TXCFG_TXFULL_192B 0x00000030 -#define AR5K_TXCFG_TXFULL_256B 0x00000040 -#define AR5K_TXCFG_TXCONT_EN 0x00000080 -#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ -#define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ -#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ -#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ -#define AR5K_TXCFG_RDY_DIS 0x00004000 /* [5211+] */ - -/* - * Receive configuration register - */ -#define AR5K_RXCFG 0x0034 /* Register Address */ -#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */ -#define AR5K_RXCFG_SDMAMW_S 0 -#define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /* Default antenna */ -#define AR5K_RXCFG_ZLFDMA 0x00000010 /* Zero-length DMA */ -#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo frames reception (?) [5211+] */ -#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames (?) [5211+] */ - -/* - * Receive jumbo descriptor last address register - * Only found in 5211 (?) - */ -#define AR5K_RXJLA 0x0038 - -/* - * MIB control register - */ -#define AR5K_MIBC 0x0040 /* Register Address */ -#define AR5K_MIBC_COW 0x00000001 -#define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ -#define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ -#define AR5K_MIBC_MCS 0x00000008 - -/* - * Timeout prescale register - */ -#define AR5K_TOPS 0x0044 -#define AR5K_TOPS_M 0x0000ffff /* [5211+] (?) */ - -/* - * Receive timeout register (no frame received) - */ -#define AR5K_RXNOFRM 0x0048 -#define AR5K_RXNOFRM_M 0x000003ff /* [5211+] (?) */ - -/* - * Transmit timeout register (no frame sent) - */ -#define AR5K_TXNOFRM 0x004c -#define AR5K_TXNOFRM_M 0x000003ff /* [5211+] (?) */ -#define AR5K_TXNOFRM_QCU 0x000ffc00 /* [5211+] (?) */ - -/* - * Receive frame gap timeout register - */ -#define AR5K_RPGTO 0x0050 -#define AR5K_RPGTO_M 0x000003ff /* [5211+] (?) */ - -/* - * Receive frame count limit register - */ -#define AR5K_RFCNT 0x0054 -#define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ -#define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ - -/* - * Misc settings register - */ -#define AR5K_MISC 0x0058 /* Register Address */ -#define AR5K_MISC_DMA_OBS_M 0x000001e0 -#define AR5K_MISC_DMA_OBS_S 5 -#define AR5K_MISC_MISC_OBS_M 0x00000e00 -#define AR5K_MISC_MISC_OBS_S 9 -#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 -#define AR5K_MISC_MAC_OBS_LSB_S 12 -#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 -#define AR5K_MISC_MAC_OBS_MSB_S 15 -#define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ -#define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ - -/* - * QCU/DCU clock gating register (5311) - */ -#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ -#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ -#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ - -/* - * Interrupt Status Registers - * - * For 5210 there is only one status register but for - * 5211/5212 we have one primary and 4 secondary registers. - * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. - * Most of these bits are common for all chipsets. - */ -#define AR5K_ISR 0x001c /* Register Address [5210] */ -#define AR5K_PISR 0x0080 /* Register Address [5211+] */ -#define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ -#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ -#define AR5K_ISR_RXERR 0x00000004 /* Receive error */ -#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ -#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ -#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ -#define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ -#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ -#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ -#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ -#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ -#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ -#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ -#define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ -#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ -#define AR5K_ISR_RXKCM 0x00008000 -#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ -#define AR5K_ISR_BRSSI 0x00020000 -#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ -#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ -#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ -#define AR5K_ISR_MCABT 0x00100000 /* [5210] */ -#define AR5K_ISR_RXCHIRP 0x00200000 /* [5212+] */ -#define AR5K_ISR_SSERR 0x00200000 /* [5210] */ -#define AR5K_ISR_DPERR 0x00400000 /* [5210] */ -#define AR5K_ISR_TIM 0x00800000 /* [5210] */ -#define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ -#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ -#define AR5K_ISR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ -#define AR5K_ISR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ -#define AR5K_ISR_QTRIG 0x08000000 /* [5211+] */ - -/* - * Secondary status registers [5211+] (0 - 4) - * - * I guess from the names that these give the status for each - * queue, that's why only masks are defined here, haven't got - * any info about them (couldn't find them anywhere in ar5k code). - */ -#define AR5K_SISR0 0x0084 /* Register Address [5211+] */ -#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ -#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ - -#define AR5K_SISR1 0x0088 /* Register Address [5211+] */ -#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ -#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ - -#define AR5K_SISR2 0x008c /* Register Address [5211+] */ -#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ -#define AR5K_SISR2_MCABT 0x00100000 -#define AR5K_SISR2_SSERR 0x00200000 -#define AR5K_SISR2_DPERR 0x00400000 -#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ -#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ -#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ -#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ -#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ -#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ - -#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ -#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ -#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ - -#define AR5K_SISR4 0x0094 /* Register Address [5211+] */ -#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ - -/* - * Shadow read-and-clear interrupt status registers [5211+] - */ -#define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ -#define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ -#define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ -#define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ -#define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ -#define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ - -/* - * Interrupt Mask Registers - * - * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary - * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. - */ -#define AR5K_IMR 0x0020 /* Register Address [5210] */ -#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ -#define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ -#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ -#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ -#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ -#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ -#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ -#define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ -#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ -#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ -#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ -#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ -#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ -#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ -#define AR5K_IMR_SWI 0x00002000 -#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ -#define AR5K_IMR_RXKCM 0x00008000 -#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ -#define AR5K_IMR_BRSSI 0x00020000 -#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ -#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ -#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ -#define AR5K_IMR_MCABT 0x00100000 /* [5210] */ -#define AR5K_IMR_RXCHIRP 0x00200000 /* [5212+]*/ -#define AR5K_IMR_SSERR 0x00200000 /* [5210] */ -#define AR5K_IMR_DPERR 0x00400000 /* [5210] */ -#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ -#define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ -#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ -#define AR5K_IMR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ -#define AR5K_IMR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ -#define AR5K_IMR_QTRIG 0x08000000 /* [5211+] */ - -/* - * Secondary interrupt mask registers [5211+] (0 - 4) - */ -#define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ -#define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ -#define AR5K_SIMR0_QCU_TXOK_S 0 -#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ -#define AR5K_SIMR0_QCU_TXDESC_S 16 - -#define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ -#define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ -#define AR5K_SIMR1_QCU_TXERR_S 0 -#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ -#define AR5K_SIMR1_QCU_TXEOL_S 16 - -#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ -#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ -#define AR5K_SIMR2_QCU_TXURN_S 0 -#define AR5K_SIMR2_MCABT 0x00100000 -#define AR5K_SIMR2_SSERR 0x00200000 -#define AR5K_SIMR2_DPERR 0x00400000 -#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ -#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ -#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ -#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ -#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ -#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ - -#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ -#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ -#define AR5K_SIMR3_QCBRORN_S 0 -#define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ -#define AR5K_SIMR3_QCBRURN_S 16 - -#define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ -#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ -#define AR5K_SIMR4_QTRIG_S 0 - - -/* - * Decompression mask registers [5212+] - */ -#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (?)*/ -#define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/ - -/* - * Decompression configuration registers [5212+] - */ -#define AR5K_DCCFG 0x0420 - -/* - * Compression configuration registers [5212+] - */ -#define AR5K_CCFG 0x0600 -#define AR5K_CCFG_CUP 0x0604 - -/* - * Compression performance counter registers [5212+] - */ -#define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ -#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ -#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ -#define AR5K_CPC3 0x061c /* Compression performance counter 3 */ -#define AR5K_CPCORN 0x0620 /* Compression performance overrun (?) */ - - -/* - * Queue control unit (QCU) registers [5211+] - * - * Card has 12 TX Queues but i see that only 0-9 are used (?) - * both in binary HAL (see ah.h) and ar5k. Each queue has it's own - * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) - * configuration register (0x08c0 - 0x08ec), a ready time configuration - * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - - * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some - * global registers, QCU transmit enable/disable and "one shot arm (?)" - * set/clear, which contain status for all queues (we shift by 1 for each - * queue). To access these registers easily we define some macros here - * that are used inside HAL. For more infos check out *_tx_queue functs. - * - * TODO: Boundary checking on macros (here?) - */ - -/* - * Generic QCU Register access macros - */ -#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) -#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) -#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) - -/* - * QCU Transmit descriptor pointer registers - */ -#define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ -#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) - -/* - * QCU Transmit enable register - */ -#define AR5K_QCU_TXE 0x0840 -#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) -#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) - -/* - * QCU Transmit disable register - */ -#define AR5K_QCU_TXD 0x0880 -#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) -#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) - -/* - * QCU Constant Bit Rate configuration registers - */ -#define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ -#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ -#define AR5K_QCU_CBRCFG_INTVAL_S 0 -#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ -#define AR5K_QCU_CBRCFG_ORN_THRES_S 24 -#define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) - -/* - * QCU Ready time configuration registers - */ -#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ -#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ -#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 -#define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /* Ready time duration mask */ -#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ -#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) - -/* - * QCU one shot arm set registers - */ -#define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ -#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff - -/* - * QCU one shot arm clear registers - */ -#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ -#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff - -/* - * QCU misc registers - */ -#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ -#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ -#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ -#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ -#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ -#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ -#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ -#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ -#define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ -#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ -#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Beacons enabled */ -#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled (?) */ -#define AR5K_QCU_MISC_TXE 0x00000200 /* TXE reset when RDYTIME enalbed (?) */ -#define AR5K_QCU_MISC_CBR 0x00000400 /* CBR threshold reset (?) */ -#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU reset (?) */ -#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) - - -/* - * QCU status registers - */ -#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ -#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ -#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter (?) */ -#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) - -/* - * QCU ready time shutdown register - */ -#define AR5K_QCU_RDYTIMESHDN 0x0a40 -#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff - -/* - * QCU compression buffer base registers [5212+] - */ -#define AR5K_QCU_CBB_SELECT 0x0b00 -#define AR5K_QCU_CBB_ADDR 0x0b04 - -/* - * QCU compression buffer configuration register [5212+] - */ -#define AR5K_QCU_CBCFG 0x0b08 - - - -/* - * Distributed Coordination Function (DCF) control unit (DCU) - * registers [5211+] - * - * These registers control the various characteristics of each queue - * for 802.11e (WME) combatibility so they go together with - * QCU registers in pairs. For each queue we have a QCU mask register, - * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), - * a retry limit register (0x1080 - 0x10ac), a channel time register - * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and - * a sequence number register (0x1140 - 0x116c). It seems that "global" - * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). - * We use the same macros here for easier register access. - * - */ - -/* - * DCU QCU mask registers - */ -#define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ -#define AR5K_DCU_QCUMASK_M 0x000003ff -#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) - -/* - * DCU local Inter Frame Space settings register - */ -#define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ -#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ -#define AR5K_DCU_LCL_IFS_CW_MIN_S 0 -#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ -#define AR5K_DCU_LCL_IFS_CW_MAX_S 10 -#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ -#define AR5K_DCU_LCL_IFS_AIFS_S 20 -#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) - -/* - * DCU retry limit registers - */ -#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ -#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ -#define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ -#define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ -#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ -#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 -#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) - -/* - * DCU channel time registers - */ -#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ -#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ -#define AR5K_DCU_CHAN_TIME_DUR_S 0 -#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ -#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) - -/* - * DCU misc registers [5211+] - * - * For some of the registers i couldn't find in the code - * (only backoff stuff is there realy) i tried to match the - * names with 802.11e parameters etc, so i guess VIRTCOL here - * means Virtual Collision and HCFPOLL means Hybrid Coordination - * factor Poll (CF- Poll). Arbiter lockout control controls the - * behaviour on low priority queues when we have multiple queues - * with pending frames. Intra-frame lockout means we wait until - * the queue's current frame transmits (with post frame backoff and bursting) - * before we transmit anything else and global lockout means we - * wait for the whole queue to finish before higher priority queues - * can transmit (this is used on beacon and CAB queues). - * No lockout means there is no special handling. - */ -#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ -#define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff setting (?) */ -#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ -#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll (?) */ -#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff (?) */ -#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch (?) */ -#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ -#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 -#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 -#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 -#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Beacon enable (?) */ -#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ -#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 -#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ -#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ -#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ -#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 -#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ -#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ -#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ -#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 -#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ -#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) - -/* - * DCU frame sequence number registers - */ -#define AR5K_DCU_SEQNUM_BASE 0x1140 -#define AR5K_DCU_SEQNUM_M 0x00000fff -#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) - -/* - * DCU global IFS SIFS registers - */ -#define AR5K_DCU_GBL_IFS_SIFS 0x1030 -#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff - -/* - * DCU global IFS slot interval registers - */ -#define AR5K_DCU_GBL_IFS_SLOT 0x1070 -#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff - -/* - * DCU global IFS EIFS registers - */ -#define AR5K_DCU_GBL_IFS_EIFS 0x10b0 -#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff - -/* - * DCU global IFS misc registers - */ -#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ -#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 -#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ -#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ -#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 -#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 - -/* - * DCU frame prefetch control register - */ -#define AR5K_DCU_FP 0x1230 - -/* - * DCU transmit pause control/status register - */ -#define AR5K_DCU_TXP 0x1270 /* Register Address */ -#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask (?) */ -#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status (?) */ - -/* - * DCU transmit filter register - */ -#define AR5K_DCU_TX_FILTER 0x1038 - -/* - * DCU clear transmit filter register - */ -#define AR5K_DCU_TX_FILTER_CLR 0x143c - -/* - * DCU set transmit filter register - */ -#define AR5K_DCU_TX_FILTER_SET 0x147c - -/* - * Reset control register - * - * 4 and 8 are not used in 5211/5212 and - * 2 means "baseband reset" on 5211/5212. - */ -#define AR5K_RESET_CTL 0x4000 /* Register Address */ -#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ -#define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ -#define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ -#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ -#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ -#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ -#define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \ - AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY) - -/* - * Sleep control register - */ -#define AR5K_SLEEP_CTL 0x4004 /* Register Address */ -#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ -#define AR5K_SLEEP_CTL_SLDUR_S 0 -#define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ -#define AR5K_SLEEP_CTL_SLE_S 16 -#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ -#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ -#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 -#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ - -/* - * Interrupt pending register - */ -#define AR5K_INTPEND 0x4008 -#define AR5K_INTPEND_M 0x00000001 - -/* - * Sleep force register - */ -#define AR5K_SFR 0x400c -#define AR5K_SFR_M 0x00000001 - -/* - * PCI configuration register - */ -#define AR5K_PCICFG 0x4010 /* Register Address */ -#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ -#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ -#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ -#define AR5K_PCICFG_EESIZE_S 3 -#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ -#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ -#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ -#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size (?) [5211+] */ -#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ -#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ -#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ -#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ -#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ -#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ -#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ -#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ -#define AR5K_PCICFG_SL_INPEN 0x00002800 /* Sleep even whith pending interrupts (?) */ -#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ -#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ -#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ -#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ -#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ -#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ -#define AR5K_PCICFG_LEDBLINK 0x00700000 -#define AR5K_PCICFG_LEDBLINK_S 20 -#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ -#define AR5K_PCICFG_LEDSTATE \ - (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ - AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) - -/* - * "General Purpose Input/Output" (GPIO) control register - * - * I'm not sure about this but after looking at the code - * for all chipsets here is what i got. - * - * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) - * Mode 0 -> always input - * Mode 1 -> output when GPIODO for this GPIO is set to 0 - * Mode 2 -> output when GPIODO for this GPIO is set to 1 - * Mode 3 -> always output - * - * For more infos check out get_gpio/set_gpio and - * set_gpio_input/set_gpio_output functs. - * For more infos on gpio interrupt check out set_gpio_intr. - */ -#define AR5K_NUM_GPIO 6 - -#define AR5K_GPIOCR 0x4014 /* Register Address */ -#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ -#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is off (?) */ -#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is on */ -#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ -#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ -#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ -#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ -#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ - -/* - * "General Purpose Input/Output" (GPIO) data output register - */ -#define AR5K_GPIODO 0x4018 - -/* - * "General Purpose Input/Output" (GPIO) data input register - */ -#define AR5K_GPIODI 0x401c -#define AR5K_GPIODI_M 0x0000002f - - -/* - * Silicon revision register - */ -#define AR5K_SREV 0x4020 /* Register Address */ -#define AR5K_SREV_REV 0x0000000f /* Mask for revision */ -#define AR5K_SREV_REV_S 0 -#define AR5K_SREV_VER 0x000000ff /* Mask for version */ -#define AR5K_SREV_VER_S 4 - - - -/*====EEPROM REGISTERS====*/ - -/* - * EEPROM access registers - * - * Here we got a difference between 5210/5211-12 - * read data register for 5210 is at 0x6800 and - * status register is at 0x6c00. There is also - * no eeprom command register on 5210 and the - * offsets are different. - * - * To read eeprom data for a specific offset: - * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) - * read AR5K_EEPROM_BASE +(4 * offset) - * check the eeprom status register - * and read eeprom data register. - * - * 5211 - write offset to AR5K_EEPROM_BASE - * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD - * check the eeprom status register - * and read eeprom data register. - * - * To write eeprom data for a specific offset: - * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) - * write data to AR5K_EEPROM_BASE +(4 * offset) - * check the eeprom status register - * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD - * 5212 write offset to AR5K_EEPROM_BASE - * write data to data register - * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD - * check the eeprom status register - * - * For more infos check eeprom_* functs and the ar5k.c - * file posted in madwifi-devel mailing list. - * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 - * - */ -#define AR5K_EEPROM_BASE 0x6000 - -/* - * Common ar5xxx EEPROM data offset (set these on AR5K_EEPROM_BASE) - */ -#define AR5K_EEPROM_MAGIC 0x003d -#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 -#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ -#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ -#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ - -#define AR5K_EEPROM_PROTECT 0x003f -#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 -#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 -#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 -#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 -#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 -#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 -#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 -#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 -#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 -#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 -#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 -#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 -#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 -#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 -#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 -#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 -#define AR5K_EEPROM_REG_DOMAIN 0x00bf -#define AR5K_EEPROM_INFO_BASE 0x00c0 -#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) -#define AR5K_EEPROM_INFO_CKSUM 0xffff -#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) - -#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) -#define AR5K_EEPROM_VERSION_3_0 0x3000 -#define AR5K_EEPROM_VERSION_3_1 0x3001 -#define AR5K_EEPROM_VERSION_3_2 0x3002 -#define AR5K_EEPROM_VERSION_3_3 0x3003 -#define AR5K_EEPROM_VERSION_3_4 0x3004 -#define AR5K_EEPROM_VERSION_4_0 0x4000 -#define AR5K_EEPROM_VERSION_4_1 0x4001 -#define AR5K_EEPROM_VERSION_4_2 0x4002 -#define AR5K_EEPROM_VERSION_4_3 0x4003 -#define AR5K_EEPROM_VERSION_4_6 0x4006 -#define AR5K_EEPROM_VERSION_4_7 0x3007 - -#define AR5K_EEPROM_MODE_11A 0 -#define AR5K_EEPROM_MODE_11B 1 -#define AR5K_EEPROM_MODE_11G 2 - -#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) -#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) -#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) -#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) -#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) -#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) -#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) -#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) -#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) - -#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c -#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 -#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 -#define AR5K_EEPROM_RFKILL_POLARITY_S 1 - -/* Newer EEPROMs are using a different offset */ -#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ - (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) - -#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) -#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) -#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) - -#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) -#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) -#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) -#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) - -/* Since 3.1 */ -#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec -#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed - -/* Misc values available since EEPROM 4.0 */ -#define AR5K_EEPROM_MISC0 0x00c4 -#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) -#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) -#define AR5K_EEPROM_MISC1 0x00c5 -#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) -#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) - -/* - * EEPROM data register - */ -#define AR5K_EEPROM_DATA_5211 0x6004 -#define AR5K_EEPROM_DATA_5210 0x6800 -#define AR5K_EEPROM_DATA (hal->ah_version == AR5K_AR5210 ? \ - AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) - -/* - * EEPROM command register - */ -#define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ -#define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ -#define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ -#define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ - -/* - * EEPROM status register - */ -#define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ -#define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ -#define AR5K_EEPROM_STATUS (hal->ah_version == AR5K_AR5210 ? \ - AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) -#define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ -#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ -#define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ -#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ - -/* - * EEPROM config register (?) - */ -#define AR5K_EEPROM_CFG 0x6010 - - - -/* - * Protocol Control Unit (PCU) registers - */ -/* - * Used for checking initial register writes - * during channel reset (see reset func) - */ -#define AR5K_PCU_MIN 0x8000 -#define AR5K_PCU_MAX 0x8fff - -/* - * First station id register (MAC address in lower 32 bits) - */ -#define AR5K_STA_ID0 0x8000 - -/* - * Second station id register (MAC address in upper 16 bits) - */ -#define AR5K_STA_ID1 0x8004 /* Register Address */ -#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ -#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ -#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */ -#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ -#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ -#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ -#define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ -#define AR5K_STA_ID1_PCF (hal->ah_version == AR5K_AR5210 ? \ - AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) -#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ -#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ -#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */ -#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */ -#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ - -/* - * First BSSID register (MAC address, lower 32bits) - */ -#define AR5K_BSS_ID0 0x8008 - -/* - * Second BSSID register (MAC address in upper 16 bits) - * - * AID: Association ID - */ -#define AR5K_BSS_ID1 0x800c -#define AR5K_BSS_ID1_AID 0xffff0000 -#define AR5K_BSS_ID1_AID_S 16 - -/* - * Backoff slot time register - */ -#define AR5K_SLOT_TIME 0x8010 - -/* - * ACK/CTS timeout register - */ -#define AR5K_TIME_OUT 0x8014 /* Register Address */ -#define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ -#define AR5K_TIME_OUT_ACK_S 0 -#define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ -#define AR5K_TIME_OUT_CTS_S 16 - -/* - * RSSI threshold register - */ -#define AR5K_RSSI_THR 0x8018 /* Register Address */ -#define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ -#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ -#define AR5K_RSSI_THR_BMISS_5210_S 8 -#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ -#define AR5K_RSSI_THR_BMISS_5211_S 8 -#define AR5K_RSSI_THR_BMISS (hal->ah_version == AR5K_AR5210 ? \ - AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) -#define AR5K_RSSI_THR_BMISS_S 8 - -/* - * 5210 has more PCU registers because there is no QCU/DCU - * so queue parameters are set here, this way a lot common - * registers have different address for 5210. To make things - * easier we define a macro based on hal->ah_version for common - * registers with different addresses and common flags. - */ - -/* - * Retry limit register - * - * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) - */ -#define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address */ -#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ -#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ -#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ -#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ -#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 -#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ -#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 - -/* - * Transmit latency register - */ -#define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ -#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ -#define AR5K_USEC (hal->ah_version == AR5K_AR5210 ? \ - AR5K_USEC_5210 : AR5K_USEC_5211) -#define AR5K_USEC_1 0x0000007f -#define AR5K_USEC_1_S 0 -#define AR5K_USEC_32 0x00003f80 -#define AR5K_USEC_32_S 7 -#define AR5K_USEC_TX_LATENCY_5211 0x007fc000 -#define AR5K_USEC_TX_LATENCY_5211_S 14 -#define AR5K_USEC_RX_LATENCY_5211 0x1f800000 -#define AR5K_USEC_RX_LATENCY_5211_S 23 -#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ -#define AR5K_USEC_TX_LATENCY_5210_S 14 -#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ -#define AR5K_USEC_RX_LATENCY_5210_S 20 - -/* - * PCU beacon control register - */ -#define AR5K_BEACON_5210 0x8024 -#define AR5K_BEACON_5211 0x8020 -#define AR5K_BEACON (hal->ah_version == AR5K_AR5210 ? \ - AR5K_BEACON_5210 : AR5K_BEACON_5211) -#define AR5K_BEACON_PERIOD 0x0000ffff -#define AR5K_BEACON_PERIOD_S 0 -#define AR5K_BEACON_TIM 0x007f0000 -#define AR5K_BEACON_TIM_S 16 -#define AR5K_BEACON_ENABLE 0x00800000 -#define AR5K_BEACON_RESET_TSF 0x01000000 - -/* - * CFP period register - */ -#define AR5K_CFP_PERIOD_5210 0x8028 -#define AR5K_CFP_PERIOD_5211 0x8024 -#define AR5K_CFP_PERIOD (hal->ah_version == AR5K_AR5210 ? \ - AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) - -/* - * Next beacon time register - */ -#define AR5K_TIMER0_5210 0x802c -#define AR5K_TIMER0_5211 0x8028 -#define AR5K_TIMER0 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_TIMER0_5210 : AR5K_TIMER0_5211) - -/* - * Next DMA beacon alert register - */ -#define AR5K_TIMER1_5210 0x8030 -#define AR5K_TIMER1_5211 0x802c -#define AR5K_TIMER1 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_TIMER1_5210 : AR5K_TIMER1_5211) - -/* - * Next software beacon alert register - */ -#define AR5K_TIMER2_5210 0x8034 -#define AR5K_TIMER2_5211 0x8030 -#define AR5K_TIMER2 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_TIMER2_5210 : AR5K_TIMER2_5211) - -/* - * Next ATIM window time register - */ -#define AR5K_TIMER3_5210 0x8038 -#define AR5K_TIMER3_5211 0x8034 -#define AR5K_TIMER3 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_TIMER3_5210 : AR5K_TIMER3_5211) - - -/* - * 5210 First inter frame spacing register (IFS) - */ -#define AR5K_IFS0 0x8040 -#define AR5K_IFS0_SIFS 0x000007ff -#define AR5K_IFS0_SIFS_S 0 -#define AR5K_IFS0_DIFS 0x007ff800 -#define AR5K_IFS0_DIFS_S 11 - -/* - * 5210 Second inter frame spacing register (IFS) - */ -#define AR5K_IFS1 0x8044 -#define AR5K_IFS1_PIFS 0x00000fff -#define AR5K_IFS1_PIFS_S 0 -#define AR5K_IFS1_EIFS 0x03fff000 -#define AR5K_IFS1_EIFS_S 12 -#define AR5K_IFS1_CS_EN 0x04000000 - - -/* - * CFP duration register - */ -#define AR5K_CFP_DUR_5210 0x8048 -#define AR5K_CFP_DUR_5211 0x8038 -#define AR5K_CFP_DUR (hal->ah_version == AR5K_AR5210 ? \ - AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) - -/* - * Receive filter register - * TODO: Get these out of ar5xxx.h on ath5k - */ -#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ -#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ -#define AR5K_RX_FILTER (hal->ah_version == AR5K_AR5210 ? \ - AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) -#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ -#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ -#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ -#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ -#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ -#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ -#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ -#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ -#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ -#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ -#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ -#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ -#define AR5K_RX_FILTER_PHYERR (hal->ah_version == AR5K_AR5211 ? \ - AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212) -#define AR5K_RX_FILTER_RADARERR (hal->ah_version == AR5K_AR5211 ? \ - AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212) -/* - * Multicast filter register (lower 32 bits) - */ -#define AR5K_MCAST_FILTER0_5210 0x8050 -#define AR5K_MCAST_FILTER0_5211 0x8040 -#define AR5K_MCAST_FILTER0 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) - -/* - * Multicast filter register (higher 16 bits) - */ -#define AR5K_MCAST_FILTER1_5210 0x8054 -#define AR5K_MCAST_FILTER1_5211 0x8044 -#define AR5K_MCAST_FILTER1 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) - - -/* - * Transmit mask register (lower 32 bits) [5210] - */ -#define AR5K_TX_MASK0 0x8058 - -/* - * Transmit mask register (higher 16 bits) [5210] - */ -#define AR5K_TX_MASK1 0x805c - -/* - * Clear transmit mask [5210] - */ -#define AR5K_CLR_TMASK 0x8060 - -/* - * Trigger level register (before transmission) [5210] - */ -#define AR5K_TRIG_LVL 0x8064 - - -/* - * PCU control register - * - * Only DIS_RX is used in the code, the rest i guess are - * for tweaking/diagnostics. - */ -#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ -#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ -#define AR5K_DIAG_SW (hal->ah_version == AR5K_AR5210 ? \ - AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) -#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 -#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ -#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ -#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ -#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption (?) */ -#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ -#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ -#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 -#define AR5K_DIAG_SW_DIS_RX (hal->ah_version == AR5K_AR5210 ? \ - AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) -#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ -#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 -#define AR5K_DIAG_SW_LOOP_BACK (hal->ah_version == AR5K_AR5210 ? \ - AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) -#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 -#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 -#define AR5K_DIAG_SW_CORR_FCS (hal->ah_version == AR5K_AR5210 ? \ - AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) -#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 -#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 -#define AR5K_DIAG_SW_CHAN_INFO (hal->ah_version == AR5K_AR5210 ? \ - AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) -#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Scrambler seed (?) */ -#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 -#define AR5K_DIAG_SW_EN_SCRAM_SEED (hal->ah_version == AR5K_AR5210 ? \ - AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) -#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ -#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ -#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ -#define AR5K_DIAG_SW_SCRAM_SEED_S 10 -#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ -#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 -#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 -#define AR5K_DIAG_SW_FRAME_NV0 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) -#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 -#define AR5K_DIAG_SW_OBSPT_S 18 - -/* - * TSF (clock) register (lower 32 bits) - */ -#define AR5K_TSF_L32_5210 0x806c -#define AR5K_TSF_L32_5211 0x804c -#define AR5K_TSF_L32 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) - -/* - * TSF (clock) register (higher 32 bits) - */ -#define AR5K_TSF_U32_5210 0x8070 -#define AR5K_TSF_U32_5211 0x8050 -#define AR5K_TSF_U32 (hal->ah_version == AR5K_AR5210 ? \ - AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) - -/* - * Last beacon timestamp register - */ -#define AR5K_LAST_TSTP 0x8080 - -/* - * ADDAC test register [5211+] - */ -#define AR5K_ADDAC_TEST 0x8054 -#define AR5K_ADDAC_TEST_TXCONT 0x00000001 - -/* - * Default antenna register [5211+] - */ -#define AR5K_DEFAULT_ANTENNA 0x8058 - - - -/* - * Retry count register [5210] - */ -#define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ -#define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ -#define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ - -/* - * Back-off status register [5210] - */ -#define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ -#define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ -#define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ - - - -/* - * NAV register (current) - */ -#define AR5K_NAV_5210 0x808c -#define AR5K_NAV_5211 0x8084 -#define AR5K_NAV (hal->ah_version == AR5K_AR5210 ? \ - AR5K_NAV_5210 : AR5K_NAV_5211) - -/* - * RTS success register - */ -#define AR5K_RTS_OK_5210 0x8090 -#define AR5K_RTS_OK_5211 0x8088 -#define AR5K_RTS_OK (hal->ah_version == AR5K_AR5210 ? \ - AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) - -/* - * RTS failure register - */ -#define AR5K_RTS_FAIL_5210 0x8094 -#define AR5K_RTS_FAIL_5211 0x808c -#define AR5K_RTS_FAIL (hal->ah_version == AR5K_AR5210 ? \ - AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) - -/* - * ACK failure register - */ -#define AR5K_ACK_FAIL_5210 0x8098 -#define AR5K_ACK_FAIL_5211 0x8090 -#define AR5K_ACK_FAIL (hal->ah_version == AR5K_AR5210 ? \ - AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) - -/* - * FCS failure register - */ -#define AR5K_FCS_FAIL_5210 0x809c -#define AR5K_FCS_FAIL_5211 0x8094 -#define AR5K_FCS_FAIL (hal->ah_version == AR5K_AR5210 ? \ - AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) - -/* - * Beacon count register - */ -#define AR5K_BEACON_CNT_5210 0x80a0 -#define AR5K_BEACON_CNT_5211 0x8098 -#define AR5K_BEACON_CNT (hal->ah_version == AR5K_AR5210 ? \ - AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) - - -/*===5212 Specific PCU registers===*/ - -/* - * XR (eXtended Range) mode register - */ -#define AR5K_XRMODE 0x80c0 -#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f -#define AR5K_XRMODE_POLL_TYPE_S 0 -#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c -#define AR5K_XRMODE_POLL_SUBTYPE_S 2 -#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 -#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 -#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 -#define AR5K_XRMODE_FRAME_HOLD_S 20 - -/* - * XR delay register - */ -#define AR5K_XRDELAY 0x80c4 -#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff -#define AR5K_XRDELAY_SLOT_DELAY_S 0 -#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 -#define AR5K_XRDELAY_CHIRP_DELAY_S 16 - -/* - * XR timeout register - */ -#define AR5K_XRTIMEOUT 0x80c8 -#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff -#define AR5K_XRTIMEOUT_CHIRP_S 0 -#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 -#define AR5K_XRTIMEOUT_POLL_S 16 - -/* - * XR chirp register - */ -#define AR5K_XRCHIRP 0x80cc -#define AR5K_XRCHIRP_SEND 0x00000001 -#define AR5K_XRCHIRP_GAP 0xffff0000 - -/* - * XR stomp register - */ -#define AR5K_XRSTOMP 0x80d0 -#define AR5K_XRSTOMP_TX 0x00000001 -#define AR5K_XRSTOMP_RX_ABORT 0x00000002 -#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 - -/* - * First enhanced sleep register - */ -#define AR5K_SLEEP0 0x80d4 -#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff -#define AR5K_SLEEP0_NEXT_DTIM_S 0 -#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 -#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 -#define AR5K_SLEEP0_CABTO 0xff000000 -#define AR5K_SLEEP0_CABTO_S 24 - -/* - * Second enhanced sleep register - */ -#define AR5K_SLEEP1 0x80d8 -#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff -#define AR5K_SLEEP1_NEXT_TIM_S 0 -#define AR5K_SLEEP1_BEACON_TO 0xff000000 -#define AR5K_SLEEP1_BEACON_TO_S 24 - -/* - * Third enhanced sleep register - */ -#define AR5K_SLEEP2 0x80dc -#define AR5K_SLEEP2_TIM_PER 0x0000ffff -#define AR5K_SLEEP2_TIM_PER_S 0 -#define AR5K_SLEEP2_DTIM_PER 0xffff0000 -#define AR5K_SLEEP2_DTIM_PER_S 16 - -/* - * BSSID mask registers - */ -#define AR5K_BSS_IDM0 0x80e0 -#define AR5K_BSS_IDM1 0x80e4 - -/* - * TX power control (TPC) register - */ -#define AR5K_TXPC 0x80e8 -#define AR5K_TXPC_ACK_M 0x0000003f -#define AR5K_TXPC_ACK_S 0 -#define AR5K_TXPC_CTS_M 0x00003f00 -#define AR5K_TXPC_CTS_S 8 -#define AR5K_TXPC_CHIRP_M 0x003f0000 -#define AR5K_TXPC_CHIRP_S 22 - -/* - * Profile count registers - */ -#define AR5K_PROFCNT_TX 0x80ec -#define AR5K_PROFCNT_RX 0x80f0 -#define AR5K_PROFCNT_RXCLR 0x80f4 -#define AR5K_PROFCNT_CYCLE 0x80f8 - -/* - * TSF parameter register - */ -#define AR5K_TSF_PARM 0x8104 -#define AR5K_TSF_PARM_INC_M 0x000000ff -#define AR5K_TSF_PARM_INC_S 0 - -/* - * PHY error filter register - */ -#define AR5K_PHY_ERR_FIL 0x810c -#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 -#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 -#define AR5K_PHY_ERR_FIL_CCK 0x02000000 - -/* - * Rate duration register - */ -#define AR5K_RATE_DUR_BASE 0x8700 -#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) - -/*===5212 end===*/ - -/* - * Key table (WEP) register - */ -#define AR5K_KEYTABLE_0_5210 0x9000 -#define AR5K_KEYTABLE_0_5211 0x8800 -#define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) -#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) * 32)) -#define AR5K_KEYTABLE(_n) (hal->ah_version == AR5K_AR5210 ? \ - AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) -#define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) -#define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5) -#define AR5K_KEYTABLE_TYPE_40 0x00000000 -#define AR5K_KEYTABLE_TYPE_104 0x00000001 -#define AR5K_KEYTABLE_TYPE_128 0x00000003 -#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */ -#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */ -#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */ -#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */ -#define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */ -#define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) -#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) -#define AR5K_KEYTABLE_VALID 0x00008000 - -#define AR5K_KEYTABLE_SIZE_5210 64 -#define AR5K_KEYTABLE_SIZE_5211 128 -#define AR5K_KEYTABLE_SIZE (hal->ah_version == AR5K_AR5210 ? \ - AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) - - -/*===PHY REGISTERS===*/ - -/* - * PHY register - */ -#define AR5K_PHY_BASE 0x9800 -#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) -#define AR5K_PHY_SHIFT_2GHZ 0x00004007 -#define AR5K_PHY_SHIFT_5GHZ 0x00000007 - -/* - * PHY frame control register [5110] /turbo mode register [5111+] - * - * There is another frame control register for [5111+] - * at address 0x9944 (see below) but the 2 first flags - * are common here between 5110 frame control register - * and [5111+] turbo mode register, so this also works as - * a "turbo mode register" for 5110. We treat this one as - * a frame control register for 5110 below. - */ -#define AR5K_PHY_TURBO 0x9804 -#define AR5K_PHY_TURBO_MODE 0x00000001 -#define AR5K_PHY_TURBO_SHORT 0x00000002 - -/* - * PHY agility command register - */ -#define AR5K_PHY_AGC 0x9808 -#define AR5K_PHY_AGC_DISABLE 0x08000000 - -/* - * PHY timing register [5112+] - */ -#define AR5K_PHY_TIMING_3 0x9814 -#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 -#define AR5K_PHY_TIMING_3_DSC_MAN_S 17 -#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 -#define AR5K_PHY_TIMING_3_DSC_EXP_S 13 - -/* - * PHY chip revision register - */ -#define AR5K_PHY_CHIP_ID 0x9818 - -/* - * PHY activation register - */ -#define AR5K_PHY_ACT 0x981c -#define AR5K_PHY_ACT_ENABLE 0x00000001 -#define AR5K_PHY_ACT_DISABLE 0x00000002 - -/* - * PHY signal register [5110] - */ -#define AR5K_PHY_SIG 0x9858 -#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 -#define AR5K_PHY_SIG_FIRSTEP_S 12 -#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 -#define AR5K_PHY_SIG_FIRPWR_S 18 - -/* - * PHY coarse agility control register [5110] - */ -#define AR5K_PHY_AGCCOARSE 0x985c -#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 -#define AR5K_PHY_AGCCOARSE_LO_S 7 -#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 -#define AR5K_PHY_AGCCOARSE_HI_S 15 - -/* - * PHY agility control register - */ -#define AR5K_PHY_AGCCTL 0x9860 /* Register address */ -#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ -#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ - -/* - * PHY noise floor status register - */ -#define AR5K_PHY_NF 0x9864 -#define AR5K_PHY_NF_M 0x000001ff -#define AR5K_PHY_NF_ACTIVE 0x00000100 -#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) -#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) -#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) - -/* - * PHY ADC saturation register [5110] - */ -#define AR5K_PHY_ADCSAT 0x9868 -#define AR5K_PHY_ADCSAT_ICNT 0x0001f800 -#define AR5K_PHY_ADCSAT_ICNT_S 11 -#define AR5K_PHY_ADCSAT_THR 0x000007e0 -#define AR5K_PHY_ADCSAT_THR_S 5 - -/* - * PHY sleep registers [5112+] - */ -#define AR5K_PHY_SCR 0x9870 -#define AR5K_PHY_SCR_32MHZ 0x0000001f -#define AR5K_PHY_SLMT 0x9874 -#define AR5K_PHY_SLMT_32MHZ 0x0000007f -#define AR5K_PHY_SCAL 0x9878 -#define AR5K_PHY_SCAL_32MHZ 0x0000000e - -/* - * PHY PLL control register [5111+] - */ -#define AR5K_PHY_PLL 0x987c -#define AR5K_PHY_PLL_20MHZ 0x13 /* [5111] */ -#define AR5K_PHY_PLL_40MHZ_5211 0x18 -#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa -#define AR5K_PHY_PLL_40MHZ (hal->ah_version == AR5K_AR5211 ? \ - AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) -#define AR5K_PHY_PLL_44MHZ_5211 0x19 -#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab -#define AR5K_PHY_PLL_44MHZ (hal->ah_version == AR5K_AR5211 ? \ - AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) -#define AR5K_PHY_PLL_RF5111 0x00000000 -#define AR5K_PHY_PLL_RF5112 0x00000040 - -/* - * PHY RF stage register [5110] - */ -#define AR5K_PHY_RFSTG 0x98d4 -#define AR5K_PHY_RFSTG_DISABLE 0x00000021 - -/* - * PHY receiver delay register [5111+] - */ -#define AR5K_PHY_RX_DELAY 0x9914 -#define AR5K_PHY_RX_DELAY_M 0x00003fff - -/* - * PHY timing IQ control register [5111+] - */ -#define AR5K_PHY_IQ 0x9920 -#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f -#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 -#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 -#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 -#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 -#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 -#define AR5K_PHY_IQ_RUN 0x00010000 - - -/* - * PHY PAPD probe register [5111+] - */ -#define AR5K_PHY_PAPD_PROBE 0x9930 -#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 -#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 -#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 -#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ -#define AR5K_PHY_PAPD_PROBE_TYPE_S 23 -#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 -#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 -#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 -#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 -#define AR5K_PHY_PAPD_PROBE_GAINF_S 25 - - -/* - * PHY TX power registers [5112+] - */ -#define AR5K_PHY_TXPOWER_RATE1 0x9934 -#define AR5K_PHY_TXPOWER_RATE2 0x9938 -#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c -#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 -#define AR5K_PHY_TXPOWER_RATE3 0xa234 -#define AR5K_PHY_TXPOWER_RATE4 0xa238 - -/* - * PHY frame control register [5111+] - */ -#define AR5K_PHY_FRAME_CTL_5210 0x9804 -#define AR5K_PHY_FRAME_CTL_5211 0x9944 -#define AR5K_PHY_FRAME_CTL (hal->ah_version == AR5K_AR5210 ? \ - AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) -/*---[5111+]---*/ -#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 -#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 -/*---[5110]---*/ -#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 -#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 -#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 -#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 -#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 -#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 - -/* - * PHY radar detection register [5111+] - */ -#define AR5K_PHY_RADAR 0x9954 - -/* Radar enable ........ ........ ........ .......1 */ -#define AR5K_PHY_RADAR_ENABLE 0x00000001 -#define AR5K_PHY_RADAR_DISABLE 0x00000000 -#define AR5K_PHY_RADAR_ENABLE_S 0 - -/* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... -at power on. */ -#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 - -/* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1 -after DFS is enabled */ -#define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d - -/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ - * power out threshold. - * 7-bits, standard power range {0..127} in 1/2 dBm units. */ -#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 -#define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24 - -/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ - * 6-bits, dBm range {0..63} in dBm units. */ -#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 -#define AR5K_PHY_RADAR_RADARRSSITHR_S 18 - -/* Pulse height threshold ........ ......11 1111.... ........ - * 6-bits, dBm range {0..63} in dBm units. */ -#define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000 -#define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12 - -/* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... - * 6-bits, dBm range {0..63} in dBm units. */ -#define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0 -#define AR5K_PHY_RADAR_PULSERSSITHR_S 6 - -/* Inband threshold ........ ........ ........ ..11111. - * 5-bits, units unknown {0..31} (? MHz ?) */ -#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e -#define AR5K_PHY_RADAR_INBANDTHR_S 1 - -/* - * PHY antenna switch table registers [5110] - */ -#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 -#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 - -/* - * PHY clock sleep registers [5112+] - */ -#define AR5K_PHY_SCLOCK 0x99f0 -#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c -#define AR5K_PHY_SDELAY 0x99f4 -#define AR5K_PHY_SDELAY_32MHZ 0x000000ff -#define AR5K_PHY_SPENDING 0x99f8 -#define AR5K_PHY_SPENDING_RF5111 0x00000018 -#define AR5K_PHY_SPENDING_RF5112 0x00000014 - -/* - * Misc PHY/radio registers [5110 - 5111] - */ -#define AR5K_BB_GAIN_BASE 0x9b00 -#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) -#define AR5K_RF_GAIN_BASE 0x9a00 -#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) - -/* - * PHY timing IQ calibration result register [5111+] - */ -#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 -#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 -#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 - -/* - * PHY current RSSI register [5111+] - */ -#define AR5K_PHY_CURRENT_RSSI 0x9c1c - -/* - * PHY PCDAC TX power register [5112+] - */ -#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 -#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) - -/* - * PHY mode register [5111+] - */ -#define AR5K_PHY_MODE 0x0a200 -#define AR5K_PHY_MODE_MOD 0x00000001 -#define AR5K_PHY_MODE_MOD_OFDM 0 -#define AR5K_PHY_MODE_MOD_CCK 1 -#define AR5K_PHY_MODE_FREQ 0x00000002 -#define AR5K_PHY_MODE_FREQ_5GHZ 0 -#define AR5K_PHY_MODE_FREQ_2GHZ 2 -#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* [5112+] */ -#define AR5K_PHY_MODE_RAD 0x00000008 /* [5112+] */ -#define AR5K_PHY_MODE_RAD_RF5111 0 -#define AR5K_PHY_MODE_RAD_RF5112 8 -#define AR5K_PHY_MODE_XR 0x00000010 /* [5112+] */ - -/* - * PHY CCK transmit control register [5112+] - */ -#define AR5K_PHY_CCKTXCTL 0xa204 -#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 -#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 - -/* - * PHY 2GHz gain register [5112+] - */ -#define AR5K_PHY_GAIN_2GHZ 0xa20c -#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 -#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 diff --git a/openhal/ieee80211_regdomain.c b/openhal/ieee80211_regdomain.c deleted file mode 100644 index f5da7cf..0000000 --- a/openhal/ieee80211_regdomain.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - */ - -/* - * Basic regulation domain extensions for the IEEE 802.11 stack - */ - -#include -#include - -#include "ieee80211_regdomain.h" - -static const struct ieee80211_regdomainmap { - enum ieee80211_regdomain dmn; - enum ieee80211_regdomain dmn5; - enum ieee80211_regdomain dmn2; -} r_map[] = { - { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, - { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, - { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, - { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, - { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, - { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, - { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, - { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, - { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, - { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, - { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, - { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, - { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, - { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, - { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, - { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, - { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, - { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, - { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, - { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, - { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, - { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, - { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, - { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, - { DMN_APL_NULL, DMN_APL1, DMN_NULL }, - { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, - { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, - { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, - { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, - { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, - { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, - { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, - { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, - { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, - { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, - { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, - { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, - { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, - { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, - { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, - { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, -}; - -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, - u16 mhz) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(r_map); i++) { - if (r_map[i].dmn == dmn) { - if (mhz >= 2000 && mhz <= 3000) - return r_map[i].dmn2; - if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && - mhz <= IEEE80211_CHANNELS_5GHZ_MAX) - return r_map[i].dmn5; - } - } - - return DMN_DEBUG; -} - -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) -{ - u32 regdomain = (u32)ieee; - - /* - * Use the default regulation domain if the value is empty - * or not supported by the net80211 regulation code. - */ - if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) - return (u16)AR5K_TUNE_REGDOMAIN; - - /* It is supported, just return the value */ - return regdomain; -} - -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) -{ - enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; - - return ieee; -} - diff --git a/openhal/ieee80211_regdomain.h b/openhal/ieee80211_regdomain.h deleted file mode 100644 index b5f67f3..0000000 --- a/openhal/ieee80211_regdomain.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - */ - -#ifndef _IEEE80211_REGDOMAIN_H_ -#define _IEEE80211_REGDOMAIN_H_ - -#include - -/* Default regulation domain if stored value EEPROM value is invalid */ -#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ -#define AR5K_TUNE_CTRY CTRY_DEFAULT - - -enum ieee80211_regdomain { - DMN_DEFAULT = 0x00, - DMN_NULL_WORLD = 0x03, - DMN_NULL_ETSIB = 0x07, - DMN_NULL_ETSIC = 0x08, - DMN_FCC1_FCCA = 0x10, - DMN_FCC1_WORLD = 0x11, - DMN_FCC2_FCCA = 0x20, - DMN_FCC2_WORLD = 0x21, - DMN_FCC2_ETSIC = 0x22, - DMN_FRANCE_NULL = 0x31, - DMN_FCC3_FCCA = 0x3A, - DMN_ETSI1_WORLD = 0x37, - DMN_ETSI3_ETSIA = 0x32, - DMN_ETSI2_WORLD = 0x35, - DMN_ETSI3_WORLD = 0x36, - DMN_ETSI4_WORLD = 0x30, - DMN_ETSI4_ETSIC = 0x38, - DMN_ETSI5_WORLD = 0x39, - DMN_ETSI6_WORLD = 0x34, - DMN_ETSI_NULL = 0x33, - DMN_MKK1_MKKA = 0x40, - DMN_MKK1_MKKB = 0x41, - DMN_APL4_WORLD = 0x42, - DMN_MKK2_MKKA = 0x43, - DMN_APL_NULL = 0x44, - DMN_APL2_WORLD = 0x45, - DMN_APL2_APLC = 0x46, - DMN_APL3_WORLD = 0x47, - DMN_MKK1_FCCA = 0x48, - DMN_APL2_APLD = 0x49, - DMN_MKK1_MKKA1 = 0x4A, - DMN_MKK1_MKKA2 = 0x4B, - DMN_APL1_WORLD = 0x52, - DMN_APL1_FCCA = 0x53, - DMN_APL1_APLA = 0x54, - DMN_APL1_ETSIC = 0x55, - DMN_APL2_ETSIC = 0x56, - DMN_APL5_WORLD = 0x58, - DMN_WOR0_WORLD = 0x60, - DMN_WOR1_WORLD = 0x61, - DMN_WOR2_WORLD = 0x62, - DMN_WOR3_WORLD = 0x63, - DMN_WOR4_WORLD = 0x64, - DMN_WOR5_ETSIC = 0x65, - DMN_WOR01_WORLD = 0x66, - DMN_WOR02_WORLD = 0x67, - DMN_EU1_WORLD = 0x68, - DMN_WOR9_WORLD = 0x69, - DMN_WORA_WORLD = 0x6A, - - DMN_APL1 = 0xf0000001, - DMN_APL2 = 0xf0000002, - DMN_APL3 = 0xf0000004, - DMN_APL4 = 0xf0000008, - DMN_APL5 = 0xf0000010, - DMN_ETSI1 = 0xf0000020, - DMN_ETSI2 = 0xf0000040, - DMN_ETSI3 = 0xf0000080, - DMN_ETSI4 = 0xf0000100, - DMN_ETSI5 = 0xf0000200, - DMN_ETSI6 = 0xf0000400, - DMN_ETSIA = 0xf0000800, - DMN_ETSIB = 0xf0001000, - DMN_ETSIC = 0xf0002000, - DMN_FCC1 = 0xf0004000, - DMN_FCC2 = 0xf0008000, - DMN_FCC3 = 0xf0010000, - DMN_FCCA = 0xf0020000, - DMN_APLD = 0xf0040000, - DMN_MKK1 = 0xf0080000, - DMN_MKK2 = 0xf0100000, - DMN_MKKA = 0xf0200000, - DMN_NULL = 0xf0400000, - DMN_WORLD = 0xf0800000, - DMN_DEBUG = 0xf1000000 /* used for debugging */ -}; - -#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) - -enum ieee80211_countrycode { - CTRY_DEFAULT = 0, /* Default domain (NA) */ - CTRY_ALBANIA = 8, /* Albania */ - CTRY_ALGERIA = 12, /* Algeria */ - CTRY_ARGENTINA = 32, /* Argentina */ - CTRY_ARMENIA = 51, /* Armenia */ - CTRY_AUSTRALIA = 36, /* Australia */ - CTRY_AUSTRIA = 40, /* Austria */ - CTRY_AZERBAIJAN = 31, /* Azerbaijan */ - CTRY_BAHRAIN = 48, /* Bahrain */ - CTRY_BELARUS = 112, /* Belarus */ - CTRY_BELGIUM = 56, /* Belgium */ - CTRY_BELIZE = 84, /* Belize */ - CTRY_BOLIVIA = 68, /* Bolivia */ - CTRY_BRAZIL = 76, /* Brazil */ - CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ - CTRY_BULGARIA = 100, /* Bulgaria */ - CTRY_CANADA = 124, /* Canada */ - CTRY_CHILE = 152, /* Chile */ - CTRY_CHINA = 156, /* People's Republic of China */ - CTRY_COLOMBIA = 170, /* Colombia */ - CTRY_COSTA_RICA = 188, /* Costa Rica */ - CTRY_CROATIA = 191, /* Croatia */ - CTRY_CYPRUS = 196, /* Cyprus */ - CTRY_CZECH = 203, /* Czech Republic */ - CTRY_DENMARK = 208, /* Denmark */ - CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ - CTRY_ECUADOR = 218, /* Ecuador */ - CTRY_EGYPT = 818, /* Egypt */ - CTRY_EL_SALVADOR = 222, /* El Salvador */ - CTRY_ESTONIA = 233, /* Estonia */ - CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ - CTRY_FINLAND = 246, /* Finland */ - CTRY_FRANCE = 250, /* France */ - CTRY_FRANCE2 = 255, /* France2 */ - CTRY_GEORGIA = 268, /* Georgia */ - CTRY_GERMANY = 276, /* Germany */ - CTRY_GREECE = 300, /* Greece */ - CTRY_GUATEMALA = 320, /* Guatemala */ - CTRY_HONDURAS = 340, /* Honduras */ - CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ - CTRY_HUNGARY = 348, /* Hungary */ - CTRY_ICELAND = 352, /* Iceland */ - CTRY_INDIA = 356, /* India */ - CTRY_INDONESIA = 360, /* Indonesia */ - CTRY_IRAN = 364, /* Iran */ - CTRY_IRAQ = 368, /* Iraq */ - CTRY_IRELAND = 372, /* Ireland */ - CTRY_ISRAEL = 376, /* Israel */ - CTRY_ITALY = 380, /* Italy */ - CTRY_JAMAICA = 388, /* Jamaica */ - CTRY_JAPAN = 392, /* Japan */ - CTRY_JAPAN1 = 393, /* Japan (JP1) */ - CTRY_JAPAN2 = 394, /* Japan (JP0) */ - CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ - CTRY_JAPAN4 = 396, /* Japan (JE1) */ - CTRY_JAPAN5 = 397, /* Japan (JE2) */ - CTRY_JORDAN = 400, /* Jordan */ - CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ - CTRY_KENYA = 404, /* Kenya */ - CTRY_KOREA_NORTH = 408, /* North Korea */ - CTRY_KOREA_ROC = 410, /* South Korea */ - CTRY_KOREA_ROC2 = 411, /* South Korea */ - CTRY_KUWAIT = 414, /* Kuwait */ - CTRY_LATVIA = 428, /* Latvia */ - CTRY_LEBANON = 422, /* Lebanon */ - CTRY_LIBYA = 434, /* Libya */ - CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ - CTRY_LITHUANIA = 440, /* Lithuania */ - CTRY_LUXEMBOURG = 442, /* Luxembourg */ - CTRY_MACAU = 446, /* Macau */ - CTRY_MACEDONIA = 807, /* Republic of Macedonia */ - CTRY_MALAYSIA = 458, /* Malaysia */ - CTRY_MEXICO = 484, /* Mexico */ - CTRY_MONACO = 492, /* Principality of Monaco */ - CTRY_MOROCCO = 504, /* Morocco */ - CTRY_NETHERLANDS = 528, /* Netherlands */ - CTRY_NEW_ZEALAND = 554, /* New Zealand */ - CTRY_NICARAGUA = 558, /* Nicaragua */ - CTRY_NORWAY = 578, /* Norway */ - CTRY_OMAN = 512, /* Oman */ - CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ - CTRY_PANAMA = 591, /* Panama */ - CTRY_PARAGUAY = 600, /* Paraguay */ - CTRY_PERU = 604, /* Peru */ - CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ - CTRY_POLAND = 616, /* Poland */ - CTRY_PORTUGAL = 620, /* Portugal */ - CTRY_PUERTO_RICO = 630, /* Puerto Rico */ - CTRY_QATAR = 634, /* Qatar */ - CTRY_ROMANIA = 642, /* Romania */ - CTRY_RUSSIA = 643, /* Russia */ - CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ - CTRY_SINGAPORE = 702, /* Singapore */ - CTRY_SLOVAKIA = 703, /* Slovak Republic */ - CTRY_SLOVENIA = 705, /* Slovenia */ - CTRY_SOUTH_AFRICA = 710, /* South Africa */ - CTRY_SPAIN = 724, /* Spain */ - CTRY_SRI_LANKA = 728, /* Sri Lanka */ - CTRY_SWEDEN = 752, /* Sweden */ - CTRY_SWITZERLAND = 756, /* Switzerland */ - CTRY_SYRIA = 760, /* Syria */ - CTRY_TAIWAN = 158, /* Taiwan */ - CTRY_THAILAND = 764, /* Thailand */ - CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ - CTRY_TUNISIA = 788, /* Tunisia */ - CTRY_TURKEY = 792, /* Turkey */ - CTRY_UAE = 784, /* U.A.E. */ - CTRY_UKRAINE = 804, /* Ukraine */ - CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ - CTRY_UNITED_STATES = 840, /* United States */ - CTRY_URUGUAY = 858, /* Uruguay */ - CTRY_UZBEKISTAN = 860, /* Uzbekistan */ - CTRY_VENEZUELA = 862, /* Venezuela */ - CTRY_VIET_NAM = 704, /* Viet Nam */ - CTRY_YEMEN = 887, /* Yemen */ - CTRY_ZIMBABWE = 716, /* Zimbabwe */ -}; - -#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ -#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ -#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ -#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ - -struct ieee80211_regchannel { - u16 chan; - enum ieee80211_regdomain domain; - u32 mode; -}; - -#define IEEE80211_CHANNELS_2GHZ { \ -/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \ - \ -/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -} - -#define IEEE80211_CHANNELS_5GHZ { \ -/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \ - \ -/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \ - \ -/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \ - \ -/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \ -/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \ -/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \ -/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \ -/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \ -/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \ -/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \ -/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \ -/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \ - \ -/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \ -/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \ -/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \ - \ -/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \ -/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \ -/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \ -/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \ -/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \ -/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ -} - -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); - -#endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ commit b33c56f60cb0366537c0bfabfe2ba413b96a6ce4 Author: Jiri Slaby Date: Sun Jul 15 14:06:15 2007 +0200 remove some commented stuff diff --git a/ath.c b/ath.c index 970b625..7367a88 100644 --- a/ath.c +++ b/ath.c @@ -47,24 +47,10 @@ printk(_fmt); \ } while (0) enum { - ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ - ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ - ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ - ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ - ATH_DEBUG_RATE = 0x00000010, /* rate control */ ATH_DEBUG_RESET = 0x00000020, /* reset processing */ ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ - ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ ATH_DEBUG_INTR = 0x00001000, /* ISR */ - ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ - ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ - ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ - ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ - ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ - ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ - ATH_DEBUG_NODE = 0x00080000, /* node management */ - ATH_DEBUG_LED = 0x00100000, /* led management */ ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ ATH_DEBUG_ANY = 0xffffffff }; @@ -2044,13 +2030,6 @@ static ctl_table ath_static_sysctls[] = { .maxlen = sizeof(countrycode), .proc_handler = proc_dointvec }, -/* { .ctl_name = CTL_AUTO, - .procname = "regdomain", - .mode = 0444, - .data = &ath_regdomain, - .maxlen = sizeof(ath_regdomain), - .proc_handler = proc_dointvec - },*/ { .ctl_name = CTL_AUTO, .procname = "outdoor", .mode = 0444, @@ -2065,24 +2044,6 @@ static ctl_table ath_static_sysctls[] = { .maxlen = sizeof(xchanmode), .proc_handler = proc_dointvec }, -/* { .ctl_name = CTL_AUTO, - .procname = "dwelltime", - .mode = 0644, - .data = &ath_dwelltime, - .maxlen = sizeof(ath_dwelltime), - .extra1 = &mindwelltime, - .extra2 = &maxint, - .proc_handler = proc_dointvec_minmax - }, - { .ctl_name = CTL_AUTO, - .procname = "calibrate", - .mode = 0644, - .data = &ath_calinterval, - .maxlen = sizeof(ath_calinterval), - .extra1 = &mincalibrate, - .extra2 = &maxint, - .proc_handler = proc_dointvec_minmax - },*/ { 0 } }; static ctl_table ath_ath_table[] = { @@ -2101,9 +2062,6 @@ static ctl_table ath_root_table[] = { }; static struct ctl_table_header *ath_sysctl_header; -/* - * Module glue. - */ static int __init init_ath_pci(void) { int ret; commit 5a8f187a0243fb0cd52b4464e5b85aafe45c6b04 Author: Jiri Slaby Date: Sun Jul 15 15:45:46 2007 +0200 backport madwifi-old-openhal release 2539 diff --git a/ath5k_hw.c b/ath5k_hw.c index a96053f..2b8cce7 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -69,12 +69,18 @@ static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *); /* * Initial register dumps */ -static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI; -static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE; +static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI; static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI; +static const struct ath5k_ini ar5212_ini[] = AR5K_AR5212_INI; static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE; +static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE; + +/* RF Initial BB gain settings */ +static const struct ath5k_ini rf5111_bbgain_ini[] = AR5K_RF5111_BBGAIN_INI; +static const struct ath5k_ini rf5112_bbgain_ini[] = AR5K_RF5112_BBGAIN_INI; + +/* This is going out soon */ static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF; -static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI; /* * Initial gain optimization values @@ -83,11 +89,13 @@ static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT; static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT; /* - * Initial register for the radio chipsets + * Initial register settings for the radio chipsets */ +/* RF Banks */ static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF; static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF; static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF; +/* Common (5111/5112) rf gain table */ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; /* @@ -252,7 +260,34 @@ static int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, return (i <= 0) ? -EAGAIN : 0; } +/* + * Write initial register dump + */ +static void ath5k_hw_ini_registers(struct ath_hw *hal, unsigned int size, + const struct ath5k_ini *ini_regs, bool change_channel) +{ + unsigned int i; + /* Write initial registers */ + for (i = 0; i < size; i++) { + if (change_channel && + ini_regs[i].ini_register >= AR5K_PCU_MIN && + ini_regs[i].ini_register <= AR5K_PCU_MAX) + continue; + + switch (ini_regs[i].ini_mode) { + case AR5K_INI_READ: + /* Cleared on read */ + ath5k_hw_reg_read(hal, ini_regs[i].ini_register); + break; + case AR5K_INI_WRITE: + default: + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(hal, ini_regs[i].ini_value, + ini_regs[i].ini_register); + } + } +} /***************************************\ Attach/Detach Functions @@ -490,7 +525,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) } else if (flags & CHANNEL_G) { /* Dynamic OFDM/CCK is not supported by the AR5211 */ if (hal->ah_version == AR5K_AR5211) { - mode |= AR5K_PHY_MODE_MOD_OFDM; + mode |= AR5K_PHY_MODE_MOD_CCK; } else { mode |= AR5K_PHY_MODE_MOD_DYN; } @@ -831,61 +866,36 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, } /* - * Write initial register settings - * TODO:Do this in a common way + * Initial register dump common for all modes */ /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < ARRAY_SIZE(ar5212_ini); i++) { - if (change_channel == true && - ar5212_ini[i].ini_register >= AR5K_PCU_MIN && - ar5212_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - - if ((hal->ah_radio == AR5K_RF5111 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) || - (hal->ah_radio == AR5K_RF5112 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, - ar5212_ini[i].ini_value, - (u32)ar5212_ini[i].ini_register); - } - } - } - /*For 5211*/ - if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < ARRAY_SIZE(ar5211_ini); i++) { - if (change_channel == true && - ar5211_ini[i].ini_register >= AR5K_PCU_MIN && - ar5211_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - - AR5K_REG_WAIT(i); - ath5k_hw_reg_write(hal, - ar5211_ini[i].ini_value, - (u32)ar5211_ini[i].ini_register); - } - } - /*For 5210*/ - if (hal->ah_version == AR5K_AR5210) - for (i = 0; i < ARRAY_SIZE(ar5210_ini); i++) { - if (change_channel == true && - ar5210_ini[i].ini_register >= AR5K_PCU_MIN && - ar5210_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - - switch (ar5210_ini[i].ini_mode) { - case AR5K_INI_READ: - /* Cleared on read */ - ath5k_hw_reg_read(hal, ar5210_ini[i].ini_register); - break; - - case AR5K_INI_WRITE: - default: - ath5k_hw_reg_write(hal, ar5210_ini[i].ini_value, - ar5210_ini[i].ini_register); + ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5212_ini), + ar5212_ini, change_channel); + if (hal->ah_radio == AR5K_RF5112) { + ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5112, + AR5K_PHY_PAPD_PROBE); + ath5k_hw_ini_registers(hal, + ARRAY_SIZE(rf5112_bbgain_ini), + rf5112_bbgain_ini, change_channel); + } else if (hal->ah_radio == AR5K_RF5111) { + ath5k_hw_reg_write(hal, AR5K_PHY_GAIN_2GHZ_INI_5111, + AR5K_PHY_GAIN_2GHZ); + ath5k_hw_reg_write(hal, AR5K_PHY_PAPD_PROBE_INI_5111, + AR5K_PHY_PAPD_PROBE); + ath5k_hw_ini_registers(hal, + ARRAY_SIZE(rf5111_bbgain_ini), + rf5111_bbgain_ini, change_channel); } + } else if (hal->ah_version == AR5K_AR5211) { + ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5211_ini), + ar5211_ini, change_channel); + /* AR5211 only comes with 5111 */ + ath5k_hw_ini_registers(hal, ARRAY_SIZE(rf5111_bbgain_ini), + rf5111_bbgain_ini, change_channel); + } else if (hal->ah_version == AR5K_AR5210) { + ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5210_ini), + ar5210_ini, change_channel); } /* @@ -3185,34 +3195,30 @@ int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac) { unsigned int i; - u32 key_v[AR5K_KEYCACHE_SIZE - 2] = {}; + __le32 key_v[5] = {}; + u32 keytype; AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); switch (key->keylen) { case 40 / 8: - memcpy(&key_v[0], key->key, 4); - memcpy(&key_v[1], key->key + 4, 1); - key_v[5] = AR5K_KEYTABLE_TYPE_40; + memcpy(&key_v[0], key->key, 5); + keytype = AR5K_KEYTABLE_TYPE_40; break; case 104 / 8: - memcpy(&key_v[0], key->key, 4); - memcpy(&key_v[1], key->key + 4, 2); - memcpy(&key_v[2], key->key + 6, 4); - memcpy(&key_v[3], key->key + 10, 2); - memcpy(&key_v[4], key->key + 12, 1); - key_v[5] = AR5K_KEYTABLE_TYPE_104; + memcpy(&key_v[0], &key->key[0], 6); + memcpy(&key_v[2], &key->key[6], 6); + memcpy(&key_v[4], &key->key[12], 1); + keytype = AR5K_KEYTABLE_TYPE_104; break; case 128 / 8: - memcpy(&key_v[0], key->key, 4); - memcpy(&key_v[1], key->key + 4, 2); - memcpy(&key_v[2], key->key + 6, 4); - memcpy(&key_v[3], key->key + 10, 2); - memcpy(&key_v[4], key->key + 12, 4); - key_v[5] = AR5K_KEYTABLE_TYPE_128; + memcpy(&key_v[0], &key->key[0], 6); + memcpy(&key_v[2], &key->key[6], 6); + memcpy(&key_v[4], &key->key[12], 4); + keytype = AR5K_KEYTABLE_TYPE_128; break; default: @@ -3220,7 +3226,10 @@ int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, } for (i = 0; i < ARRAY_SIZE(key_v); i++) - ath5k_hw_reg_write(hal, key_v[i], AR5K_KEYTABLE_OFF(entry, i)); + ath5k_hw_reg_write(hal, le32_to_cpu(key_v[i]), + AR5K_KEYTABLE_OFF(entry, i)); + + ath5k_hw_reg_write(hal, keytype, AR5K_KEYTABLE_TYPE(entry)); return ath5k_hw_set_key_lladdr(hal, entry, mac); } @@ -4586,8 +4595,8 @@ ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) * Set the channel and wait */ data = ath5k_hw_rf5110_chan2athchan(channel); - AR5K_PHY_WRITE(hal, 0x27, data); - AR5K_PHY_WRITE(hal, 0x30, 0); + ath5k_hw_reg_write(hal, data, AR5K_RF_BUFFER); + ath5k_hw_reg_write(hal, 0, AR5K_RF_BUFFER_CONTROL_0); mdelay(1); return true; @@ -4660,8 +4669,10 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) | (clock << 1) | (1 << 10) | 1; } - AR5K_PHY_WRITE(hal, 0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); - AR5K_PHY_WRITE(hal, 0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); + ath5k_hw_reg_write(hal, (data1 & 0xff) | ((data0 & 0xff) << 8), + AR5K_RF_BUFFER); + ath5k_hw_reg_write(hal, ((data1 >> 8) & 0xff) | (data0 & 0xff00), + AR5K_RF_BUFFER_CONTROL_3); return true; } @@ -4708,8 +4719,8 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; - AR5K_PHY_WRITE(hal, 0x27, data & 0xff); - AR5K_PHY_WRITE(hal, 0x36, (data >> 8) & 0x7f); + ath5k_hw_reg_write(hal, data & 0xff, AR5K_RF_BUFFER); + ath5k_hw_reg_write(hal, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); return true; } @@ -5207,6 +5218,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un rf[i] = rf5111_rf[i].rf_value[mode]; } + /* Modify bank 0 */ if (channel->val & CHANNEL_2GHZ) { if (channel->val & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; @@ -5223,6 +5235,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un return false; obdb = 1; + /* Modify bank 6 */ } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; @@ -5256,6 +5269,7 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) return false; + /* Modify bank 7 */ if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 29, 0, true)) return false; @@ -5313,6 +5327,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un rf[i] = rf_ini[i].rf_value[mode]; } + /* Modify bank 6 */ if (channel->val & CHANNEL_2GHZ) { if (channel->val & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; @@ -5355,6 +5370,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un ee->ee_xpd[ee_mode], 1, 302, 0, true)) return false; + /* Modify bank 7 */ if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 14, 0, true)) return false; diff --git a/ath5k_hw.h b/ath5k_hw.h index 92ff4cf..cd4fbad 100644 --- a/ath5k_hw.h +++ b/ath5k_hw.h @@ -50,8 +50,8 @@ enum ath5k_rfgain { ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) struct ath5k_gain_opt_step { - int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; - int32_t gos_gain; + s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; + s32 gos_gain; }; struct ath5k_gain_opt { @@ -105,6 +105,10 @@ struct ath5k_gain { } \ } +/* + * HW SPECIFIC STRUCTS + */ + /* Some EEPROM defines */ #define AR5K_EEPROM_EEP_SCALE 100 #define AR5K_EEPROM_EEP_DELTA 10 @@ -145,6 +149,7 @@ struct ath5k_gain { #define AR5K_EEPROM_CCK_OFDM_DELTA 15 #define AR5K_EEPROM_N_IQ_CAL 2 +/* Struct to hold EEPROM calibration data */ struct ath5k_eeprom_info { u16 ee_magic; u16 ee_protect; @@ -188,13 +193,259 @@ struct ath5k_eeprom_info { u16 ee_ctls; u16 ee_ctl[AR5K_EEPROM_MAX_CTLS]; - int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; - int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; - int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; + s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; + s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES]; + s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES]; }; /* - * AR5k register access + * Internal RX/TX descriptor structures + * (rX: reserved fields possibily used by future versions of the ar5k chipset) + */ + +struct ath5k_rx_desc { + u32 rx_control_0; /* RX control word 0 */ + +#define AR5K_DESC_RX_CTL0 0x00000000 + + u32 rx_control_1; /* RX control word 1 */ + +#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff +#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 +} __packed; + +/* + * 5210/5211 rx status descriptor + */ +struct ath5k_hw_old_rx_status { + u32 rx_status_0; /* RX status word 0 */ + +#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 + + u32 rx_status_1; /* RX status word 1 */ + +#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 +#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 +} __packed; + +/* + * 5212 rx status descriptor + */ +struct ath5k_hw_new_rx_status { + u32 rx_status_0; /* RX status word 0 */ + +#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 + + u32 rx_status_1; /* RX status word 1 */ + +#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 +#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010 +#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 +} __packed; + +struct ath5k_hw_rx_error { + u32 rx_error_0; /* RX error word 0 */ + +#define AR5K_RX_DESC_ERROR0 0x00000000 + + u32 rx_error_1; /* RX error word 1 */ + +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 +} __packed; + +#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 +#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 +#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 +#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 +#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 +#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 +#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 +#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 + +struct ath5k_hw_2w_tx_desc { + u32 tx_control_0; /* TX control word 0 */ + +#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 +#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 + + u32 tx_control_1; /* TX control word 1 */ + +#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ +} __packed; + +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 + +/* + * 5212 4-word tx control descriptor + */ +struct ath5k_hw_4w_tx_desc { + u32 tx_control_0; /* TX control word 0 */ + +#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 +#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 +#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 +#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 + + u32 tx_control_1; /* TX control word 1 */ + +#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 + + u32 tx_control_2; /* TX control word 2 */ + +#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff +#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 + + u32 tx_control_3; /* TX control word 3 */ + +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 +} __packed; + +/* + * Common tx status descriptor + */ +struct ath5k_hw_tx_status { + u32 tx_status_0; /* TX status word 0 */ + +#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 +#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 +#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 +#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 +/*??? +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 +*/ +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 +/*??? +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 +*/ +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 + + u32 tx_status_1; /* TX status word 1 */ + +#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 +#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe +#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 +#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 +#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 +} __packed; + + +/* + * AR5K REGISTER ACCESS */ /*Swap RX/TX Descriptor for big endian archs*/ @@ -342,9 +593,11 @@ struct ath5k_eeprom_info { ) /* - * Non - common initial register values + * Non-common initial register values which have to be loaded into the + * card at boot time and after each reset. */ +/* Register dumps are done per operation mode */ #define AR5K_INI_VAL_11A 0 #define AR5K_INI_VAL_11A_TURBO 1 #define AR5K_INI_VAL_11B 2 @@ -360,14 +613,17 @@ struct ath5k_eeprom_info { #define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS #define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS +/* Struct to hold initial RF register values */ struct ath5k_ini_rf { - u8 rf_bank; - u16 rf_register; - u32 rf_value[5]; + u8 rf_bank; /* check out ath5k_reg.h */ + u16 rf_register; /* register address */ + u32 rf_value[5]; /* register value for different modes (above) */ }; +/* RF5111 mode-specific init registers */ #define AR5K_RF5111_INI_RF { \ { 0, 0x989c, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ { 0, 0x989c, \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ @@ -459,8 +715,10 @@ struct ath5k_ini_rf { { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ } +/* RF5112 mode-specific init registers */ #define AR5K_RF5112_INI_RF { \ { 1, 0x98d4, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ { 2, 0x98d0, \ { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ @@ -569,9 +827,11 @@ struct ath5k_ini_rf { { 7, 0x98c4, \ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } - + +/* RF5112A mode-specific init registers */ #define AR5K_RF5112A_INI_RF { \ { 1, 0x98d4, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ { 2, 0x98d0, \ { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ @@ -685,9 +945,12 @@ struct ath5k_ini_rf { { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } +/* + * Mode-specific RF Gain registers + */ struct ath5k_ini_rfgain { - u16 rfg_register; - u32 rfg_value[2][2]; + u16 rfg_register; /* RF Gain register address */ + u32 rfg_value[2][2]; /* [phy (above)][freq (below)] */ #define AR5K_INI_RFGAIN_5GHZ 0 #define AR5K_INI_RFGAIN_2GHZ 1 @@ -695,6 +958,7 @@ struct ath5k_ini_rfgain { #define AR5K_INI_RFGAIN { \ { 0x9a00, { \ + /* 5111 5Ghz 5111 2Ghz 5112 5Ghz 5112 2Ghz */ \ { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ { 0x9a04, { \ { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ @@ -824,291 +1088,9 @@ struct ath5k_ini_rfgain { { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ } -/* - * Internal RX/TX descriptor structures - * (rX: reserved fields possibily used by future versions of the ar5k chipset) - */ - -struct ath5k_rx_desc { - /* - * RX control word 0 - */ - u32 rx_control_0; - -#define AR5K_DESC_RX_CTL0 0x00000000 - - /* - * RX control word 1 - */ - u32 rx_control_1; - -#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff -#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 -} __packed; - -struct ath5k_hw_old_rx_status { - /* - * RX status word 0 - */ - u32 rx_status_0; - -#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff -#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 - - /* - * RX status word 1 - */ - u32 rx_status_1; - -#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 -#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 -#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 -#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 -#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9 -#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 -#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 -} __packed; - -struct ath5k_hw_new_rx_status { - /* - * RX status word 0 - */ - u32 rx_status_0; - -#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff -#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 -#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 - - /* - * RX status word 1 - */ - u32 rx_status_1; - -#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 -#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 -#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010 -#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9 -#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 -#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 -} __packed; - -struct ath5k_hw_rx_error { - /* - * RX error word 0 - */ - u32 rx_error_0; - -#define AR5K_RX_DESC_ERROR0 0x00000000 - - /* - * RX error word 1 - */ - u32 rx_error_1; - -#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 -#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 -} __packed; - -#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 -#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 -#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 -#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 -#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 -#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 -#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 -#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 - -struct ath5k_hw_2w_tx_desc { - /* - * TX control word 0 - */ - u32 tx_control_0; - -#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff -#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ -#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 -#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 -#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 -#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 -#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 -#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ -#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ -#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (hal->ah_version == AR5K_AR5210 ? \ - AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ - AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 -#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 - - /* - * TX control word 1 - */ - u32 tx_control_1; - -#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff -#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (hal->ah_version == AR5K_AR5210 ? \ - AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ - AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 -#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ -} __packed; - -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 - -struct ath5k_hw_4w_tx_desc { - /* - * TX control word 0 - */ - u32 tx_control_0; - -#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff -#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 -#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 -#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 -#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 -#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 -#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 -#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 -#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 -#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 - - /* - * TX control word 1 - */ - u32 tx_control_1; - -#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff -#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 -#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 -#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 -#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 -#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 -#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 -#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 - - /* - * TX control word 2 - */ - u32 tx_control_2; - -#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff -#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 - - /* - * TX control word 3 - */ - u32 tx_control_3; - -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 -#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 -#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 -} __packed; - -struct ath5k_hw_tx_status { - /* - * TX status word 0 - */ - u32 tx_status_0; - -#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 -#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 -#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 -#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 -/*??? -#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 -#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 -*/ -#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 -#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 -/*??? -#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 -#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 -*/ -#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 -#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 -#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 -#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 -#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 -#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 - - /* - * TX status word 1 - */ - u32 tx_status_1; - -#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 -#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe -#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 -#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 -#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 -#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 -#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 -#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 -#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 -} __packed; - /* - * Initial register values which have to be loaded into the - * card at boot time and after each reset. + * Mode-independet initial register writes */ struct ath5k_ini { @@ -1116,220 +1098,729 @@ struct ath5k_ini { u32 ini_value; enum { - AR5K_INI_WRITE = 0, - AR5K_INI_READ = 1, + AR5K_INI_WRITE = 0, /* Default */ + AR5K_INI_READ = 1, /* Cleared on read */ } ini_mode; }; -#define AR5K_AR5210_INI { \ - /* PCU and MAC registers */ \ - { AR5K_NOQCU_TXDP0, 0 }, \ - { AR5K_NOQCU_TXDP1, 0 }, \ - { AR5K_RXDP, 0 }, \ - { AR5K_CR, 0 }, \ - { AR5K_ISR, 0, AR5K_INI_READ }, \ - { AR5K_IMR, 0 }, \ - { AR5K_IER, AR5K_IER_DISABLE }, \ - { AR5K_BSR, 0, AR5K_INI_READ }, \ - { AR5K_TXCFG, AR5K_DMASIZE_128B }, \ - { AR5K_RXCFG, AR5K_DMASIZE_128B }, \ - { AR5K_CFG, AR5K_INIT_CFG }, \ - { AR5K_TOPS, AR5K_INIT_TOPS }, \ - { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \ - { AR5K_RPGTO, AR5K_INIT_RPGTO }, \ - { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \ - { AR5K_SFR, 0 }, \ - { AR5K_MIBC, 0 }, \ - { AR5K_MISC, 0 }, \ - { AR5K_RX_FILTER_5210, 0 }, \ - { AR5K_MCAST_FILTER0_5210, 0 }, \ - { AR5K_MCAST_FILTER1_5210, 0 }, \ - { AR5K_TX_MASK0, 0 }, \ - { AR5K_TX_MASK1, 0 }, \ - { AR5K_CLR_TMASK, 0 }, \ - { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ - { AR5K_DIAG_SW_5210, 0 }, \ - { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ - { AR5K_TSF_L32_5210, 0 }, \ - { AR5K_TIMER0_5210, 0 }, \ - { AR5K_TIMER1_5210, 0xffffffff }, \ - { AR5K_TIMER2_5210, 0xffffffff }, \ - { AR5K_TIMER3_5210, 1 }, \ - { AR5K_CFP_DUR_5210, 0 }, \ - { AR5K_CFP_PERIOD_5210, 0 }, \ - /* PHY registers */ \ - { AR5K_PHY(0), 0x00000047 }, \ - { AR5K_PHY_AGC, 0x00000000 }, \ - { AR5K_PHY(3), 0x09848ea6 }, \ - { AR5K_PHY(4), 0x3d32e000 }, \ - { AR5K_PHY(5), 0x0000076b }, \ - { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \ - { AR5K_PHY(8), 0x02020200 }, \ - { AR5K_PHY(9), 0x00000e0e }, \ - { AR5K_PHY(10), 0x0a020201 }, \ - { AR5K_PHY(11), 0x00036ffc }, \ - { AR5K_PHY(12), 0x00000000 }, \ - { AR5K_PHY(13), 0x00000e0e }, \ - { AR5K_PHY(14), 0x00000007 }, \ - { AR5K_PHY(15), 0x00020100 }, \ - { AR5K_PHY(16), 0x89630000 }, \ - { AR5K_PHY(17), 0x1372169c }, \ - { AR5K_PHY(18), 0x0018b633 }, \ - { AR5K_PHY(19), 0x1284613c }, \ - { AR5K_PHY(20), 0x0de8b8e0 }, \ - { AR5K_PHY(21), 0x00074859 }, \ - { AR5K_PHY(22), 0x7e80beba }, \ - { AR5K_PHY(23), 0x313a665e }, \ - { AR5K_PHY_AGCCTL, 0x00001d08 }, \ - { AR5K_PHY(25), 0x0001ce00 }, \ - { AR5K_PHY(26), 0x409a4190 }, \ - { AR5K_PHY(28), 0x0000000f }, \ - { AR5K_PHY(29), 0x00000080 }, \ - { AR5K_PHY(30), 0x00000004 }, \ - { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \ - { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \ - { AR5K_PHY(65), 0x00000000 }, \ - { AR5K_PHY(66), 0x00000000 }, \ - { AR5K_PHY(67), 0x00800000 }, \ - { AR5K_PHY(68), 0x00000003 }, \ - /* BB gain table (64bytes) */ \ - { AR5K_BB_GAIN(0), 0x00000000 }, \ - { AR5K_BB_GAIN(0x01), 0x00000020 }, \ - { AR5K_BB_GAIN(0x02), 0x00000010 }, \ - { AR5K_BB_GAIN(0x03), 0x00000030 }, \ - { AR5K_BB_GAIN(0x04), 0x00000008 }, \ - { AR5K_BB_GAIN(0x05), 0x00000028 }, \ - { AR5K_BB_GAIN(0x06), 0x00000028 }, \ - { AR5K_BB_GAIN(0x07), 0x00000004 }, \ - { AR5K_BB_GAIN(0x08), 0x00000024 }, \ - { AR5K_BB_GAIN(0x09), 0x00000014 }, \ - { AR5K_BB_GAIN(0x0a), 0x00000034 }, \ - { AR5K_BB_GAIN(0x0b), 0x0000000c }, \ - { AR5K_BB_GAIN(0x0c), 0x0000002c }, \ - { AR5K_BB_GAIN(0x0d), 0x00000002 }, \ - { AR5K_BB_GAIN(0x0e), 0x00000022 }, \ - { AR5K_BB_GAIN(0x0f), 0x00000012 }, \ - { AR5K_BB_GAIN(0x10), 0x00000032 }, \ - { AR5K_BB_GAIN(0x11), 0x0000000a }, \ - { AR5K_BB_GAIN(0x12), 0x0000002a }, \ - { AR5K_BB_GAIN(0x13), 0x00000001 }, \ - { AR5K_BB_GAIN(0x14), 0x00000021 }, \ - { AR5K_BB_GAIN(0x15), 0x00000011 }, \ - { AR5K_BB_GAIN(0x16), 0x00000031 }, \ - { AR5K_BB_GAIN(0x17), 0x00000009 }, \ - { AR5K_BB_GAIN(0x18), 0x00000029 }, \ - { AR5K_BB_GAIN(0x19), 0x00000005 }, \ - { AR5K_BB_GAIN(0x1a), 0x00000025 }, \ - { AR5K_BB_GAIN(0x1b), 0x00000015 }, \ - { AR5K_BB_GAIN(0x1c), 0x00000035 }, \ - { AR5K_BB_GAIN(0x1d), 0x0000000d }, \ - { AR5K_BB_GAIN(0x1e), 0x0000002d }, \ - { AR5K_BB_GAIN(0x1f), 0x00000003 }, \ - { AR5K_BB_GAIN(0x20), 0x00000023 }, \ - { AR5K_BB_GAIN(0x21), 0x00000013 }, \ - { AR5K_BB_GAIN(0x22), 0x00000033 }, \ - { AR5K_BB_GAIN(0x23), 0x0000000b }, \ - { AR5K_BB_GAIN(0x24), 0x0000002b }, \ - { AR5K_BB_GAIN(0x25), 0x00000007 }, \ - { AR5K_BB_GAIN(0x26), 0x00000027 }, \ - { AR5K_BB_GAIN(0x27), 0x00000017 }, \ - { AR5K_BB_GAIN(0x28), 0x00000037 }, \ - { AR5K_BB_GAIN(0x29), 0x0000000f }, \ - { AR5K_BB_GAIN(0x2a), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2b), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2c), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2d), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2e), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2f), 0x0000002f }, \ - { AR5K_BB_GAIN(0x30), 0x0000002f }, \ - { AR5K_BB_GAIN(0x31), 0x0000002f }, \ - { AR5K_BB_GAIN(0x32), 0x0000002f }, \ - { AR5K_BB_GAIN(0x33), 0x0000002f }, \ - { AR5K_BB_GAIN(0x34), 0x0000002f }, \ - { AR5K_BB_GAIN(0x35), 0x0000002f }, \ - { AR5K_BB_GAIN(0x36), 0x0000002f }, \ - { AR5K_BB_GAIN(0x37), 0x0000002f }, \ - { AR5K_BB_GAIN(0x38), 0x0000002f }, \ - { AR5K_BB_GAIN(0x39), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3a), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3b), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3c), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3d), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3e), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3f), 0x0000002f }, \ - /* RF gain table (64bytes) */ \ - { AR5K_RF_GAIN(0), 0x0000001d }, \ - { AR5K_RF_GAIN(0x01), 0x0000005d }, \ - { AR5K_RF_GAIN(0x02), 0x0000009d }, \ - { AR5K_RF_GAIN(0x03), 0x000000dd }, \ - { AR5K_RF_GAIN(0x04), 0x0000011d }, \ - { AR5K_RF_GAIN(0x05), 0x00000021 }, \ - { AR5K_RF_GAIN(0x06), 0x00000061 }, \ - { AR5K_RF_GAIN(0x07), 0x000000a1 }, \ - { AR5K_RF_GAIN(0x08), 0x000000e1 }, \ - { AR5K_RF_GAIN(0x09), 0x00000031 }, \ - { AR5K_RF_GAIN(0x0a), 0x00000071 }, \ - { AR5K_RF_GAIN(0x0b), 0x000000b1 }, \ - { AR5K_RF_GAIN(0x0c), 0x0000001c }, \ - { AR5K_RF_GAIN(0x0d), 0x0000005c }, \ - { AR5K_RF_GAIN(0x0e), 0x00000029 }, \ - { AR5K_RF_GAIN(0x0f), 0x00000069 }, \ - { AR5K_RF_GAIN(0x10), 0x000000a9 }, \ - { AR5K_RF_GAIN(0x11), 0x00000020 }, \ - { AR5K_RF_GAIN(0x12), 0x00000019 }, \ - { AR5K_RF_GAIN(0x13), 0x00000059 }, \ - { AR5K_RF_GAIN(0x14), 0x00000099 }, \ - { AR5K_RF_GAIN(0x15), 0x00000030 }, \ - { AR5K_RF_GAIN(0x16), 0x00000005 }, \ - { AR5K_RF_GAIN(0x17), 0x00000025 }, \ - { AR5K_RF_GAIN(0x18), 0x00000065 }, \ - { AR5K_RF_GAIN(0x19), 0x000000a5 }, \ - { AR5K_RF_GAIN(0x1a), 0x00000028 }, \ - { AR5K_RF_GAIN(0x1b), 0x00000068 }, \ - { AR5K_RF_GAIN(0x1c), 0x0000001f }, \ - { AR5K_RF_GAIN(0x1d), 0x0000001e }, \ - { AR5K_RF_GAIN(0x1e), 0x00000018 }, \ - { AR5K_RF_GAIN(0x1f), 0x00000058 }, \ - { AR5K_RF_GAIN(0x20), 0x00000098 }, \ - { AR5K_RF_GAIN(0x21), 0x00000003 }, \ - { AR5K_RF_GAIN(0x22), 0x00000004 }, \ - { AR5K_RF_GAIN(0x23), 0x00000044 }, \ - { AR5K_RF_GAIN(0x24), 0x00000084 }, \ - { AR5K_RF_GAIN(0x25), 0x00000013 }, \ - { AR5K_RF_GAIN(0x26), 0x00000012 }, \ - { AR5K_RF_GAIN(0x27), 0x00000052 }, \ - { AR5K_RF_GAIN(0x28), 0x00000092 }, \ - { AR5K_RF_GAIN(0x29), 0x000000d2 }, \ - { AR5K_RF_GAIN(0x2a), 0x0000002b }, \ - { AR5K_RF_GAIN(0x2b), 0x0000002a }, \ - { AR5K_RF_GAIN(0x2c), 0x0000006a }, \ - { AR5K_RF_GAIN(0x2d), 0x000000aa }, \ - { AR5K_RF_GAIN(0x2e), 0x0000001b }, \ - { AR5K_RF_GAIN(0x2f), 0x0000001a }, \ - { AR5K_RF_GAIN(0x30), 0x0000005a }, \ - { AR5K_RF_GAIN(0x31), 0x0000009a }, \ - { AR5K_RF_GAIN(0x32), 0x000000da }, \ - { AR5K_RF_GAIN(0x33), 0x00000006 }, \ - { AR5K_RF_GAIN(0x34), 0x00000006 }, \ - { AR5K_RF_GAIN(0x35), 0x00000006 }, \ - { AR5K_RF_GAIN(0x36), 0x00000006 }, \ - { AR5K_RF_GAIN(0x37), 0x00000006 }, \ - { AR5K_RF_GAIN(0x38), 0x00000006 }, \ - { AR5K_RF_GAIN(0x39), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3a), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3b), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3c), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3d), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3e), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3f), 0x00000006 }, \ - /* PHY activation */ \ - { AR5K_PHY(53), 0x00000020 }, \ - { AR5K_PHY(51), 0x00000004 }, \ - { AR5K_PHY(50), 0x00060106 }, \ - { AR5K_PHY(39), 0x0000006d }, \ - { AR5K_PHY(48), 0x00000000 }, \ - { AR5K_PHY(52), 0x00000014 }, \ - { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \ +/* Initial register settings for AR5210 */ +#define AR5K_AR5210_INI { \ + /* PCU and MAC registers */ \ + { AR5K_NOQCU_TXDP0, 0 }, \ + { AR5K_NOQCU_TXDP1, 0 }, \ + { AR5K_RXDP, 0 }, \ + { AR5K_CR, 0 }, \ + { AR5K_ISR, 0, AR5K_INI_READ }, \ + { AR5K_IMR, 0 }, \ + { AR5K_IER, AR5K_IER_DISABLE }, \ + { AR5K_BSR, 0, AR5K_INI_READ }, \ + { AR5K_TXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_RXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_CFG, AR5K_INIT_CFG }, \ + { AR5K_TOPS, AR5K_INIT_TOPS }, \ + { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \ + { AR5K_RPGTO, AR5K_INIT_RPGTO }, \ + { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \ + { AR5K_SFR, 0 }, \ + { AR5K_MIBC, 0 }, \ + { AR5K_MISC, 0 }, \ + { AR5K_RX_FILTER_5210, 0 }, \ + { AR5K_MCAST_FILTER0_5210, 0 }, \ + { AR5K_MCAST_FILTER1_5210, 0 }, \ + { AR5K_TX_MASK0, 0 }, \ + { AR5K_TX_MASK1, 0 }, \ + { AR5K_CLR_TMASK, 0 }, \ + { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ + { AR5K_DIAG_SW_5210, 0 }, \ + { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ + { AR5K_TSF_L32_5210, 0 }, \ + { AR5K_TIMER0_5210, 0 }, \ + { AR5K_TIMER1_5210, 0xffffffff }, \ + { AR5K_TIMER2_5210, 0xffffffff }, \ + { AR5K_TIMER3_5210, 1 }, \ + { AR5K_CFP_DUR_5210, 0 }, \ + { AR5K_CFP_PERIOD_5210, 0 }, \ + /* PHY registers */ \ + { AR5K_PHY(0), 0x00000047 }, \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0x09848ea6 }, \ + { AR5K_PHY(4), 0x3d32e000 }, \ + { AR5K_PHY(5), 0x0000076b }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \ + { AR5K_PHY(8), 0x02020200 }, \ + { AR5K_PHY(9), 0x00000e0e }, \ + { AR5K_PHY(10), 0x0a020201 }, \ + { AR5K_PHY(11), 0x00036ffc }, \ + { AR5K_PHY(12), 0x00000000 }, \ + { AR5K_PHY(13), 0x00000e0e }, \ + { AR5K_PHY(14), 0x00000007 }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x89630000 }, \ + { AR5K_PHY(17), 0x1372169c }, \ + { AR5K_PHY(18), 0x0018b633 }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(20), 0x0de8b8e0 }, \ + { AR5K_PHY(21), 0x00074859 }, \ + { AR5K_PHY(22), 0x7e80beba }, \ + { AR5K_PHY(23), 0x313a665e }, \ + { AR5K_PHY_AGCCTL, 0x00001d08 },\ + { AR5K_PHY(25), 0x0001ce00 }, \ + { AR5K_PHY(26), 0x409a4190 }, \ + { AR5K_PHY(28), 0x0000000f }, \ + { AR5K_PHY(29), 0x00000080 }, \ + { AR5K_PHY(30), 0x00000004 }, \ + { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \ + { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000003 }, \ + /* BB gain table (64bytes) */ \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(1), 0x00000020 }, \ + { AR5K_BB_GAIN(2), 0x00000010 }, \ + { AR5K_BB_GAIN(3), 0x00000030 }, \ + { AR5K_BB_GAIN(4), 0x00000008 }, \ + { AR5K_BB_GAIN(5), 0x00000028 }, \ + { AR5K_BB_GAIN(6), 0x00000028 }, \ + { AR5K_BB_GAIN(7), 0x00000004 }, \ + { AR5K_BB_GAIN(8), 0x00000024 }, \ + { AR5K_BB_GAIN(9), 0x00000014 }, \ + { AR5K_BB_GAIN(10), 0x00000034 }, \ + { AR5K_BB_GAIN(11), 0x0000000c }, \ + { AR5K_BB_GAIN(12), 0x0000002c }, \ + { AR5K_BB_GAIN(13), 0x00000002 }, \ + { AR5K_BB_GAIN(14), 0x00000022 }, \ + { AR5K_BB_GAIN(15), 0x00000012 }, \ + { AR5K_BB_GAIN(16), 0x00000032 }, \ + { AR5K_BB_GAIN(17), 0x0000000a }, \ + { AR5K_BB_GAIN(18), 0x0000002a }, \ + { AR5K_BB_GAIN(19), 0x00000001 }, \ + { AR5K_BB_GAIN(20), 0x00000021 }, \ + { AR5K_BB_GAIN(21), 0x00000011 }, \ + { AR5K_BB_GAIN(22), 0x00000031 }, \ + { AR5K_BB_GAIN(23), 0x00000009 }, \ + { AR5K_BB_GAIN(24), 0x00000029 }, \ + { AR5K_BB_GAIN(25), 0x00000005 }, \ + { AR5K_BB_GAIN(26), 0x00000025 }, \ + { AR5K_BB_GAIN(27), 0x00000015 }, \ + { AR5K_BB_GAIN(28), 0x00000035 }, \ + { AR5K_BB_GAIN(29), 0x0000000d }, \ + { AR5K_BB_GAIN(30), 0x0000002d }, \ + { AR5K_BB_GAIN(31), 0x00000003 }, \ + { AR5K_BB_GAIN(32), 0x00000023 }, \ + { AR5K_BB_GAIN(33), 0x00000013 }, \ + { AR5K_BB_GAIN(34), 0x00000033 }, \ + { AR5K_BB_GAIN(35), 0x0000000b }, \ + { AR5K_BB_GAIN(36), 0x0000002b }, \ + { AR5K_BB_GAIN(37), 0x00000007 }, \ + { AR5K_BB_GAIN(38), 0x00000027 }, \ + { AR5K_BB_GAIN(39), 0x00000017 }, \ + { AR5K_BB_GAIN(40), 0x00000037 }, \ + { AR5K_BB_GAIN(41), 0x0000000f }, \ + { AR5K_BB_GAIN(42), 0x0000002f }, \ + { AR5K_BB_GAIN(43), 0x0000002f }, \ + { AR5K_BB_GAIN(44), 0x0000002f }, \ + { AR5K_BB_GAIN(45), 0x0000002f }, \ + { AR5K_BB_GAIN(46), 0x0000002f }, \ + { AR5K_BB_GAIN(47), 0x0000002f }, \ + { AR5K_BB_GAIN(48), 0x0000002f }, \ + { AR5K_BB_GAIN(49), 0x0000002f }, \ + { AR5K_BB_GAIN(50), 0x0000002f }, \ + { AR5K_BB_GAIN(51), 0x0000002f }, \ + { AR5K_BB_GAIN(52), 0x0000002f }, \ + { AR5K_BB_GAIN(53), 0x0000002f }, \ + { AR5K_BB_GAIN(54), 0x0000002f }, \ + { AR5K_BB_GAIN(55), 0x0000002f }, \ + { AR5K_BB_GAIN(56), 0x0000002f }, \ + { AR5K_BB_GAIN(57), 0x0000002f }, \ + { AR5K_BB_GAIN(58), 0x0000002f }, \ + { AR5K_BB_GAIN(59), 0x0000002f }, \ + { AR5K_BB_GAIN(60), 0x0000002f }, \ + { AR5K_BB_GAIN(61), 0x0000002f }, \ + { AR5K_BB_GAIN(62), 0x0000002f }, \ + { AR5K_BB_GAIN(63), 0x0000002f }, \ + /* RF gain table (64btes) */ \ + { AR5K_RF_GAIN(0), 0x0000001d }, \ + { AR5K_RF_GAIN(1), 0x0000005d }, \ + { AR5K_RF_GAIN(2), 0x0000009d }, \ + { AR5K_RF_GAIN(3), 0x000000dd }, \ + { AR5K_RF_GAIN(4), 0x0000011d }, \ + { AR5K_RF_GAIN(5), 0x00000021 }, \ + { AR5K_RF_GAIN(6), 0x00000061 }, \ + { AR5K_RF_GAIN(7), 0x000000a1 }, \ + { AR5K_RF_GAIN(8), 0x000000e1 }, \ + { AR5K_RF_GAIN(9), 0x00000031 }, \ + { AR5K_RF_GAIN(10), 0x00000071 }, \ + { AR5K_RF_GAIN(11), 0x000000b1 }, \ + { AR5K_RF_GAIN(12), 0x0000001c }, \ + { AR5K_RF_GAIN(13), 0x0000005c }, \ + { AR5K_RF_GAIN(14), 0x00000029 }, \ + { AR5K_RF_GAIN(15), 0x00000069 }, \ + { AR5K_RF_GAIN(16), 0x000000a9 }, \ + { AR5K_RF_GAIN(17), 0x00000020 }, \ + { AR5K_RF_GAIN(18), 0x00000019 }, \ + { AR5K_RF_GAIN(19), 0x00000059 }, \ + { AR5K_RF_GAIN(20), 0x00000099 }, \ + { AR5K_RF_GAIN(21), 0x00000030 }, \ + { AR5K_RF_GAIN(22), 0x00000005 }, \ + { AR5K_RF_GAIN(23), 0x00000025 }, \ + { AR5K_RF_GAIN(24), 0x00000065 }, \ + { AR5K_RF_GAIN(25), 0x000000a5 }, \ + { AR5K_RF_GAIN(26), 0x00000028 }, \ + { AR5K_RF_GAIN(27), 0x00000068 }, \ + { AR5K_RF_GAIN(28), 0x0000001f }, \ + { AR5K_RF_GAIN(29), 0x0000001e }, \ + { AR5K_RF_GAIN(30), 0x00000018 }, \ + { AR5K_RF_GAIN(31), 0x00000058 }, \ + { AR5K_RF_GAIN(32), 0x00000098 }, \ + { AR5K_RF_GAIN(33), 0x00000003 }, \ + { AR5K_RF_GAIN(34), 0x00000004 }, \ + { AR5K_RF_GAIN(35), 0x00000044 }, \ + { AR5K_RF_GAIN(36), 0x00000084 }, \ + { AR5K_RF_GAIN(37), 0x00000013 }, \ + { AR5K_RF_GAIN(38), 0x00000012 }, \ + { AR5K_RF_GAIN(39), 0x00000052 }, \ + { AR5K_RF_GAIN(40), 0x00000092 }, \ + { AR5K_RF_GAIN(41), 0x000000d2 }, \ + { AR5K_RF_GAIN(42), 0x0000002b }, \ + { AR5K_RF_GAIN(43), 0x0000002a }, \ + { AR5K_RF_GAIN(44), 0x0000006a }, \ + { AR5K_RF_GAIN(45), 0x000000aa }, \ + { AR5K_RF_GAIN(46), 0x0000001b }, \ + { AR5K_RF_GAIN(47), 0x0000001a }, \ + { AR5K_RF_GAIN(48), 0x0000005a }, \ + { AR5K_RF_GAIN(49), 0x0000009a }, \ + { AR5K_RF_GAIN(50), 0x000000da }, \ + { AR5K_RF_GAIN(51), 0x00000006 }, \ + { AR5K_RF_GAIN(52), 0x00000006 }, \ + { AR5K_RF_GAIN(53), 0x00000006 }, \ + { AR5K_RF_GAIN(54), 0x00000006 }, \ + { AR5K_RF_GAIN(55), 0x00000006 }, \ + { AR5K_RF_GAIN(56), 0x00000006 }, \ + { AR5K_RF_GAIN(57), 0x00000006 }, \ + { AR5K_RF_GAIN(58), 0x00000006 }, \ + { AR5K_RF_GAIN(59), 0x00000006 }, \ + { AR5K_RF_GAIN(60), 0x00000006 }, \ + { AR5K_RF_GAIN(61), 0x00000006 }, \ + { AR5K_RF_GAIN(62), 0x00000006 }, \ + { AR5K_RF_GAIN(63), 0x00000006 }, \ + /* PHY activation */ \ + { AR5K_PHY(53), 0x00000020 }, \ + { AR5K_PHY(51), 0x00000004 }, \ + { AR5K_PHY(50), 0x00060106 }, \ + { AR5K_PHY(39), 0x0000006d }, \ + { AR5K_PHY(48), 0x00000000 }, \ + { AR5K_PHY(52), 0x00000014 }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \ +} + + +/* Initial register settings for AR5211 */ +#define AR5K_AR5211_INI { \ + { AR5K_RXDP, 0x00000000 }, \ + { AR5K_RTSD0, 0x84849c9c }, \ + { AR5K_RTSD1, 0x7c7c7c7c }, \ + { AR5K_RXCFG, 0x00000005 }, \ + { AR5K_MIBC, 0x00000000 }, \ + { AR5K_TOPS, 0x00000008 }, \ + { AR5K_RXNOFRM, 0x00000008 }, \ + { AR5K_TXNOFRM, 0x00000010 }, \ + { AR5K_RPGTO, 0x00000000 }, \ + { AR5K_RFCNT, 0x0000001f }, \ + { AR5K_QUEUE_TXDP(0), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(1), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(2), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(3), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(4), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(5), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(6), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(7), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(8), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(9), 0x00000000 }, \ + { AR5K_DCU_FP, 0x00000000 }, \ + { AR5K_STA_ID1, 0x00000000 }, \ + { AR5K_BSS_ID0, 0x00000000 }, \ + { AR5K_BSS_ID1, 0x00000000 }, \ + { AR5K_RSSI_THR, 0x00000000 }, \ + { AR5K_CFP_PERIOD_5211, 0x00000000 }, \ + { AR5K_TIMER0_5211, 0x00000030 }, \ + { AR5K_TIMER1_5211, 0x0007ffff }, \ + { AR5K_TIMER2_5211, 0x01ffffff }, \ + { AR5K_TIMER3_5211, 0x00000031 }, \ + { AR5K_CFP_DUR_5211, 0x00000000 }, \ + { AR5K_RX_FILTER_5211, 0x00000000 }, \ + { AR5K_MCAST_FILTER0_5211, 0x00000000 },\ + { AR5K_MCAST_FILTER1_5211, 0x00000002 },\ + { AR5K_DIAG_SW_5211, 0x00000000 }, \ + { AR5K_ADDAC_TEST, 0x00000000 }, \ + { AR5K_DEFAULT_ANTENNA, 0x00000000 }, \ + /* PHY registers */ \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0x2d849093 }, \ + { AR5K_PHY(4), 0x7d32e000 }, \ + { AR5K_PHY(5), 0x00000f6b }, \ + { AR5K_PHY_ACT, 0x00000000 }, \ + { AR5K_PHY(11), 0x00026ffe }, \ + { AR5K_PHY(12), 0x00000000 }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x206a017a }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(21), 0x00000859 }, \ + { AR5K_PHY(26), 0x409a4190 }, /* 0x9868 */ \ + { AR5K_PHY(27), 0x050cb081 }, \ + { AR5K_PHY(28), 0x0000000f }, \ + { AR5K_PHY(29), 0x00000080 }, \ + { AR5K_PHY(30), 0x0000000c }, \ + { AR5K_PHY(64), 0x00000000 }, \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000001 }, \ + { AR5K_PHY(71), 0x0000092a }, \ + { AR5K_PHY_IQ, 0x00000000 }, \ + { AR5K_PHY(73), 0x00058a05 }, \ + { AR5K_PHY(74), 0x00000001 }, \ + { AR5K_PHY(75), 0x00000000 }, \ + { AR5K_PHY_PAPD_PROBE, 0x00000000 }, \ + { AR5K_PHY(77), 0x00000000 }, /* 0x9934 */ \ + { AR5K_PHY(78), 0x00000000 }, /* 0x9938 */ \ + { AR5K_PHY(79), 0x0000003f }, /* 0x993c */ \ + { AR5K_PHY(80), 0x00000004 }, \ + { AR5K_PHY(82), 0x00000000 }, \ + { AR5K_PHY(83), 0x00000000 }, \ + { AR5K_PHY(84), 0x00000000 }, \ + { AR5K_PHY_RADAR, 0x5d50f14c }, \ + { AR5K_PHY(86), 0x00000018 }, \ + { AR5K_PHY(87), 0x004b6a8e }, \ + /* Power table (32bytes) */ \ + { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff }, \ + { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff }, \ + { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff }, \ + { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff }, \ + { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff }, \ + { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff }, \ + { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff }, \ + { AR5K_PHY_CCKTXCTL, 0x00000000 }, \ + { AR5K_PHY(642), 0x503e4646 }, \ + { AR5K_PHY_GAIN_2GHZ, 0x6480416c }, \ + { AR5K_PHY(644), 0x0199a003 }, \ + { AR5K_PHY(645), 0x044cd610 }, \ + { AR5K_PHY(646), 0x13800040 }, \ + { AR5K_PHY(647), 0x1be00060 }, \ + { AR5K_PHY(648), 0x0c53800a }, \ + { AR5K_PHY(649), 0x0014df3b }, \ + { AR5K_PHY(650), 0x000001b5 }, \ + { AR5K_PHY(651), 0x00000020 }, \ +} + +/* Initial register settings for AR5212 */ +#define AR5K_AR5212_INI { \ + { AR5K_RXDP, 0x00000000 }, \ + { AR5K_RXCFG, 0x00000005 }, \ + { AR5K_MIBC, 0x00000000 }, \ + { AR5K_TOPS, 0x00000008 }, \ + { AR5K_RXNOFRM, 0x00000008 }, \ + { AR5K_TXNOFRM, 0x00000010 }, \ + { AR5K_RPGTO, 0x00000000 }, \ + { AR5K_RFCNT, 0x0000001f }, \ + { AR5K_QUEUE_TXDP(0), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(1), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(2), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(3), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(4), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(5), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(6), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(7), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(8), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(9), 0x00000000 }, \ + { AR5K_DCU_FP, 0x00000000 }, \ + { AR5K_DCU_TXP, 0x00000000 }, \ + { AR5K_DCU_TX_FILTER, 0x00000000 }, \ + /* Unknown table */ \ + { 0x1078, 0x00000000 }, \ + { 0x10b8, 0x00000000 }, \ + { 0x10f8, 0x00000000 }, \ + { 0x1138, 0x00000000 }, \ + { 0x1178, 0x00000000 }, \ + { 0x11b8, 0x00000000 }, \ + { 0x11f8, 0x00000000 }, \ + { 0x1238, 0x00000000 }, \ + { 0x1278, 0x00000000 }, \ + { 0x12b8, 0x00000000 }, \ + { 0x12f8, 0x00000000 }, \ + { 0x1338, 0x00000000 }, \ + { 0x1378, 0x00000000 }, \ + { 0x13b8, 0x00000000 }, \ + { 0x13f8, 0x00000000 }, \ + { 0x1438, 0x00000000 }, \ + { 0x1478, 0x00000000 }, \ + { 0x14b8, 0x00000000 }, \ + { 0x14f8, 0x00000000 }, \ + { 0x1538, 0x00000000 }, \ + { 0x1578, 0x00000000 }, \ + { 0x15b8, 0x00000000 }, \ + { 0x15f8, 0x00000000 }, \ + { 0x1638, 0x00000000 }, \ + { 0x1678, 0x00000000 }, \ + { 0x16b8, 0x00000000 }, \ + { 0x16f8, 0x00000000 }, \ + { 0x1738, 0x00000000 }, \ + { 0x1778, 0x00000000 }, \ + { 0x17b8, 0x00000000 }, \ + { 0x17f8, 0x00000000 }, \ + { 0x103c, 0x00000000 }, \ + { 0x107c, 0x00000000 }, \ + { 0x10bc, 0x00000000 }, \ + { 0x10fc, 0x00000000 }, \ + { 0x113c, 0x00000000 }, \ + { 0x117c, 0x00000000 }, \ + { 0x11bc, 0x00000000 }, \ + { 0x11fc, 0x00000000 }, \ + { 0x123c, 0x00000000 }, \ + { 0x127c, 0x00000000 }, \ + { 0x12bc, 0x00000000 }, \ + { 0x12fc, 0x00000000 }, \ + { 0x133c, 0x00000000 }, \ + { 0x137c, 0x00000000 }, \ + { 0x13bc, 0x00000000 }, \ + { 0x13fc, 0x00000000 }, \ + { 0x143c, 0x00000000 }, \ + { 0x147c, 0x00000000 }, \ + { AR5K_STA_ID1, 0x00000000 }, \ + { AR5K_BSS_ID0, 0x00000000 }, \ + { AR5K_BSS_ID1, 0x00000000 }, \ + { AR5K_RSSI_THR, 0x00000000 }, \ + { AR5K_BEACON_5211, 0x00000000 }, \ + { AR5K_CFP_PERIOD_5211, 0x00000000 }, \ + { AR5K_TIMER0_5211, 0x00000030 }, \ + { AR5K_TIMER1_5211, 0x0007ffff }, \ + { AR5K_TIMER2_5211, 0x01ffffff }, \ + { AR5K_TIMER3_5211, 0x00000031 }, \ + { AR5K_CFP_DUR_5211, 0x00000000 }, \ + { AR5K_RX_FILTER_5211, 0x00000000 }, \ + { AR5K_DIAG_SW_5211, 0x00000000 }, \ + { AR5K_ADDAC_TEST, 0x00000000 }, \ + { AR5K_DEFAULT_ANTENNA, 0x00000000 }, \ + { 0x805c, 0xffffc7ff }, \ + { 0x8080, 0x00000000 }, \ + { AR5K_NAV_5211, 0x00000000 }, \ + { AR5K_RTS_OK_5211, 0x00000000 }, \ + { AR5K_RTS_FAIL_5211, 0x00000000 }, \ + { AR5K_ACK_FAIL_5211, 0x00000000 }, \ + { AR5K_FCS_FAIL_5211, 0x00000000 }, \ + { AR5K_BEACON_CNT_5211, 0x00000000 }, \ + { AR5K_XRMODE, 0x2a82301a }, \ + { AR5K_XRDELAY, 0x05dc01e0 }, \ + { AR5K_XRTIMEOUT, 0x1f402710 }, \ + { AR5K_XRCHIRP, 0x01f40000 }, \ + { AR5K_XRSTOMP, 0x00001e1c }, \ + { AR5K_SLEEP0, 0x0002aaaa }, \ + { AR5K_SLEEP1, 0x02005555 }, \ + { AR5K_SLEEP2, 0x00000000 }, \ + { AR5K_BSS_IDM0, 0xffffffff }, \ + { AR5K_BSS_IDM1, 0x0000ffff }, \ + { AR5K_TXPC, 0x00000000 }, \ + { AR5K_PROFCNT_TX, 0x00000000 }, \ + { AR5K_PROFCNT_RX, 0x00000000 }, \ + { AR5K_PROFCNT_RXCLR, 0x00000000 }, \ + { AR5K_PROFCNT_CYCLE, 0x00000000 }, \ + { 0x80fc, 0x00000088 }, \ + { AR5K_RATE_DUR(0), 0x00000000 }, \ + { AR5K_RATE_DUR(1), 0x0000008c }, \ + { AR5K_RATE_DUR(2), 0x000000e4 }, \ + { AR5K_RATE_DUR(3), 0x000002d5 }, \ + { AR5K_RATE_DUR(4), 0x00000000 }, \ + { AR5K_RATE_DUR(5), 0x00000000 }, \ + { AR5K_RATE_DUR(6), 0x000000a0 }, \ + { AR5K_RATE_DUR(7), 0x000001c9 }, \ + { AR5K_RATE_DUR(8), 0x0000002c }, \ + { AR5K_RATE_DUR(9), 0x0000002c }, \ + { AR5K_RATE_DUR(10), 0x00000030 }, \ + { AR5K_RATE_DUR(11), 0x0000003c }, \ + { AR5K_RATE_DUR(12), 0x0000002c }, \ + { AR5K_RATE_DUR(13), 0x0000002c }, \ + { AR5K_RATE_DUR(14), 0x00000030 }, \ + { AR5K_RATE_DUR(15), 0x0000003c }, \ + { AR5K_RATE_DUR(16), 0x00000000 }, \ + { AR5K_RATE_DUR(17), 0x00000000 }, \ + { AR5K_RATE_DUR(18), 0x00000000 }, \ + { AR5K_RATE_DUR(19), 0x00000000 }, \ + { AR5K_RATE_DUR(20), 0x00000000 }, \ + { AR5K_RATE_DUR(21), 0x00000000 }, \ + { AR5K_RATE_DUR(22), 0x00000000 }, \ + { AR5K_RATE_DUR(23), 0x00000000 }, \ + { AR5K_RATE_DUR(24), 0x000000d5 }, \ + { AR5K_RATE_DUR(25), 0x000000df }, \ + { AR5K_RATE_DUR(26), 0x00000102 }, \ + { AR5K_RATE_DUR(27), 0x0000013a }, \ + { AR5K_RATE_DUR(28), 0x00000075 }, \ + { AR5K_RATE_DUR(29), 0x0000007f }, \ + { AR5K_RATE_DUR(30), 0x000000a2 }, \ + { AR5K_RATE_DUR(31), 0x00000000 }, \ + { 0x8100, 0x00010002}, \ + { AR5K_TSF_PARM, 0x00000001 }, \ + { 0x8108, 0x000000c0 }, \ + { AR5K_PHY_ERR_FIL, 0x00000000 }, \ + { 0x8110, 0x00000168 }, \ + { 0x8114, 0x00000000 }, \ + /* Some kind of table \ + * also notice ...03<-02<-01<-00) */ \ + { 0x87c0, 0x03020100 }, \ + { 0x87c4, 0x07060504 }, \ + { 0x87c8, 0x0b0a0908 }, \ + { 0x87cc, 0x0f0e0d0c }, \ + { 0x87d0, 0x13121110 }, \ + { 0x87d4, 0x17161514 }, \ + { 0x87d8, 0x1b1a1918 }, \ + { 0x87dc, 0x1f1e1d1c }, \ + { 0x87e0, 0x03020100 }, \ + { 0x87e4, 0x07060504 }, \ + { 0x87e8, 0x0b0a0908 }, \ + { 0x87ec, 0x0f0e0d0c }, \ + { 0x87f0, 0x13121110 }, \ + { 0x87f4, 0x17161514 }, \ + { 0x87f8, 0x1b1a1918 }, \ + { 0x87fc, 0x1f1e1d1c }, \ + /* PHY registers */ \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0xad848e19 }, \ + { AR5K_PHY(4), 0x7d28e000 }, \ + { AR5K_PHY_TIMING_3, 0x9c0a9f6b }, \ + { AR5K_PHY_ACT, 0x00000000 }, \ + { AR5K_PHY(11), 0x00022ffe }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x206a017a }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(21), 0x00000859 }, \ + { AR5K_PHY(64), 0x00000000 }, \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000001 }, \ + { AR5K_PHY(71), 0x0000092a }, \ + { AR5K_PHY_IQ, 0x05100000 }, \ + { AR5K_PHY(74), 0x00000001 }, \ + { AR5K_PHY(75), 0x00000004 }, \ + { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 }, \ + { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d }, \ + { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },\ + { AR5K_PHY(80), 0x00000004 }, \ + { AR5K_PHY(82), 0x9280b212 }, \ + { AR5K_PHY_RADAR, 0x5d50e188 }, \ + { AR5K_PHY(86), 0x000000ff }, \ + { AR5K_PHY(87), 0x004b6a8e }, \ + { AR5K_PHY(90), 0x000003ce }, \ + { AR5K_PHY(92), 0x192fb515 }, \ + { AR5K_PHY(93), 0x00000000 }, \ + { AR5K_PHY(94), 0x00000001 }, \ + { AR5K_PHY(95), 0x00000000 }, \ + /* Power table (32bytes) */ \ + { AR5K_PHY_PCDAC_TXPOWER(1), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(2), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(3), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(4), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(5), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(6), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(7), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(8), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(9), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(10), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(11), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(12), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(13), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(14), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(15), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(16), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(17), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(18), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(19), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(20), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(21), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(22), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(23), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(24), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(25), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(26), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(27), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(28), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(29), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(30), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(31),0x10ff10ff }, \ + { AR5K_PHY(644), 0x0080a333 }, \ + { AR5K_PHY(645), 0x00206c10 }, \ + { AR5K_PHY(646), 0x009c4060 }, \ + { AR5K_PHY(647), 0x1483800a }, \ + { AR5K_PHY(648), 0x01831061 }, \ + { AR5K_PHY(649), 0x00000400 }, \ + { AR5K_PHY(650), 0x000001b5 }, \ + { AR5K_PHY(651), 0x00000000 }, \ + { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, \ + { AR5K_PHY_TXPOWER_RATE2, 0x20202020 }, \ + { AR5K_PHY(655), 0x13c889af }, \ + { AR5K_PHY(656), 0x38490a20 }, \ + { AR5K_PHY(657), 0x00007bb6 }, \ + { AR5K_PHY(658), 0x0fff3ffc }, \ + { AR5K_PHY_CCKTXCTL, 0x00000000 }, \ +} +/* RF5111 Initial BB Gain settings */ +#define AR5K_RF5111_BBGAIN_INI { \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(1), 0x00000020 }, \ + { AR5K_BB_GAIN(2), 0x00000010 }, \ + { AR5K_BB_GAIN(3), 0x00000030 }, \ + { AR5K_BB_GAIN(4), 0x00000008 }, \ + { AR5K_BB_GAIN(5), 0x00000028 }, \ + { AR5K_BB_GAIN(6), 0x00000004 }, \ + { AR5K_BB_GAIN(7), 0x00000024 }, \ + { AR5K_BB_GAIN(8), 0x00000014 }, \ + { AR5K_BB_GAIN(9), 0x00000034 }, \ + { AR5K_BB_GAIN(10), 0x0000000c }, \ + { AR5K_BB_GAIN(11), 0x0000002c }, \ + { AR5K_BB_GAIN(12), 0x00000002 }, \ + { AR5K_BB_GAIN(13), 0x00000022 }, \ + { AR5K_BB_GAIN(14), 0x00000012 }, \ + { AR5K_BB_GAIN(15), 0x00000032 }, \ + { AR5K_BB_GAIN(16), 0x0000000a }, \ + { AR5K_BB_GAIN(17), 0x0000002a }, \ + { AR5K_BB_GAIN(18), 0x00000006 }, \ + { AR5K_BB_GAIN(19), 0x00000026 }, \ + { AR5K_BB_GAIN(20), 0x00000016 }, \ + { AR5K_BB_GAIN(21), 0x00000036 }, \ + { AR5K_BB_GAIN(22), 0x0000000e }, \ + { AR5K_BB_GAIN(23), 0x0000002e }, \ + { AR5K_BB_GAIN(24), 0x00000001 }, \ + { AR5K_BB_GAIN(25), 0x00000021 }, \ + { AR5K_BB_GAIN(26), 0x00000011 }, \ + { AR5K_BB_GAIN(27), 0x00000031 }, \ + { AR5K_BB_GAIN(28), 0x00000009 }, \ + { AR5K_BB_GAIN(29), 0x00000029 }, \ + { AR5K_BB_GAIN(30), 0x00000005 }, \ + { AR5K_BB_GAIN(31), 0x00000025 }, \ + { AR5K_BB_GAIN(32), 0x00000015 }, \ + { AR5K_BB_GAIN(33), 0x00000035 }, \ + { AR5K_BB_GAIN(34), 0x0000000d }, \ + { AR5K_BB_GAIN(35), 0x0000002d }, \ + { AR5K_BB_GAIN(36), 0x00000003 }, \ + { AR5K_BB_GAIN(37), 0x00000023 }, \ + { AR5K_BB_GAIN(38), 0x00000013 }, \ + { AR5K_BB_GAIN(39), 0x00000033 }, \ + { AR5K_BB_GAIN(40), 0x0000000b }, \ + { AR5K_BB_GAIN(41), 0x0000002b }, \ + { AR5K_BB_GAIN(42), 0x0000002b }, \ + { AR5K_BB_GAIN(43), 0x0000002b }, \ + { AR5K_BB_GAIN(44), 0x0000002b }, \ + { AR5K_BB_GAIN(45), 0x0000002b }, \ + { AR5K_BB_GAIN(46), 0x0000002b }, \ + { AR5K_BB_GAIN(47), 0x0000002b }, \ + { AR5K_BB_GAIN(48), 0x0000002b }, \ + { AR5K_BB_GAIN(49), 0x0000002b }, \ + { AR5K_BB_GAIN(50), 0x0000002b }, \ + { AR5K_BB_GAIN(51), 0x0000002b }, \ + { AR5K_BB_GAIN(52), 0x0000002b }, \ + { AR5K_BB_GAIN(53), 0x0000002b }, \ + { AR5K_BB_GAIN(54), 0x0000002b }, \ + { AR5K_BB_GAIN(55), 0x0000002b }, \ + { AR5K_BB_GAIN(56), 0x0000002b }, \ + { AR5K_BB_GAIN(57), 0x0000002b }, \ + { AR5K_BB_GAIN(58), 0x0000002b }, \ + { AR5K_BB_GAIN(59), 0x0000002b }, \ + { AR5K_BB_GAIN(60), 0x0000002b }, \ + { AR5K_BB_GAIN(61), 0x0000002b }, \ + { AR5K_BB_GAIN(62), 0x00000002 }, \ + { AR5K_BB_GAIN(63), 0x00000016 }, \ +} + +/* RF 5112 Initial BB Gain settings */ +#define AR5K_RF5112_BBGAIN_INI { \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(1), 0x00000001 }, \ + { AR5K_BB_GAIN(2), 0x00000002 }, \ + { AR5K_BB_GAIN(3), 0x00000003 }, \ + { AR5K_BB_GAIN(4), 0x00000004 }, \ + { AR5K_BB_GAIN(5), 0x00000005 }, \ + { AR5K_BB_GAIN(6), 0x00000008 }, \ + { AR5K_BB_GAIN(7), 0x00000009 }, \ + { AR5K_BB_GAIN(8), 0x0000000a }, \ + { AR5K_BB_GAIN(9), 0x0000000b }, \ + { AR5K_BB_GAIN(10), 0x0000000c }, \ + { AR5K_BB_GAIN(11), 0x0000000d }, \ + { AR5K_BB_GAIN(12), 0x00000010 }, \ + { AR5K_BB_GAIN(13), 0x00000011 }, \ + { AR5K_BB_GAIN(14), 0x00000012 }, \ + { AR5K_BB_GAIN(15), 0x00000013 }, \ + { AR5K_BB_GAIN(16), 0x00000014 }, \ + { AR5K_BB_GAIN(17), 0x00000015 }, \ + { AR5K_BB_GAIN(18), 0x00000018 }, \ + { AR5K_BB_GAIN(19), 0x00000019 }, \ + { AR5K_BB_GAIN(20), 0x0000001a }, \ + { AR5K_BB_GAIN(21), 0x0000001b }, \ + { AR5K_BB_GAIN(22), 0x0000001c }, \ + { AR5K_BB_GAIN(23), 0x0000001d }, \ + { AR5K_BB_GAIN(24), 0x00000020 }, \ + { AR5K_BB_GAIN(25), 0x00000021 }, \ + { AR5K_BB_GAIN(26), 0x00000022 }, \ + { AR5K_BB_GAIN(27), 0x00000023 }, \ + { AR5K_BB_GAIN(28), 0x00000024 }, \ + { AR5K_BB_GAIN(29), 0x00000025 }, \ + { AR5K_BB_GAIN(30), 0x00000028 }, \ + { AR5K_BB_GAIN(31), 0x00000029 }, \ + { AR5K_BB_GAIN(32), 0x0000002a }, \ + { AR5K_BB_GAIN(33), 0x0000002b }, \ + { AR5K_BB_GAIN(34), 0x0000002c }, \ + { AR5K_BB_GAIN(35), 0x0000002d }, \ + { AR5K_BB_GAIN(36), 0x00000030 }, \ + { AR5K_BB_GAIN(37), 0x00000031 }, \ + { AR5K_BB_GAIN(38), 0x00000032 }, \ + { AR5K_BB_GAIN(39), 0x00000033 }, \ + { AR5K_BB_GAIN(40), 0x00000034 }, \ + { AR5K_BB_GAIN(41), 0x00000035 }, \ + { AR5K_BB_GAIN(42), 0x00000035 }, \ + { AR5K_BB_GAIN(43), 0x00000035 }, \ + { AR5K_BB_GAIN(44), 0x00000035 }, \ + { AR5K_BB_GAIN(45), 0x00000035 }, \ + { AR5K_BB_GAIN(46), 0x00000035 }, \ + { AR5K_BB_GAIN(47), 0x00000035 }, \ + { AR5K_BB_GAIN(48), 0x00000035 }, \ + { AR5K_BB_GAIN(49), 0x00000035 }, \ + { AR5K_BB_GAIN(50), 0x00000035 }, \ + { AR5K_BB_GAIN(51), 0x00000035 }, \ + { AR5K_BB_GAIN(52), 0x00000035 }, \ + { AR5K_BB_GAIN(53), 0x00000035 }, \ + { AR5K_BB_GAIN(54), 0x00000035 }, \ + { AR5K_BB_GAIN(55), 0x00000035 }, \ + { AR5K_BB_GAIN(56), 0x00000035 }, \ + { AR5K_BB_GAIN(57), 0x00000035 }, \ + { AR5K_BB_GAIN(58), 0x00000035 }, \ + { AR5K_BB_GAIN(59), 0x00000035 }, \ + { AR5K_BB_GAIN(60), 0x00000035 }, \ + { AR5K_BB_GAIN(61), 0x00000035 }, \ + { AR5K_BB_GAIN(62), 0x00000010 }, \ + { AR5K_BB_GAIN(63), 0x0000001a }, \ } struct ath5k_ar5210_ini_mode{ @@ -1376,567 +1867,6 @@ struct ath5k_ar5210_ini_mode{ AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x2020 }, \ } -#define AR5K_AR5211_INI { \ - { 0x000c, 0x00000000 }, \ - { 0x0028, 0x84849c9c }, \ - { 0x002c, 0x7c7c7c7c }, \ - { 0x0034, 0x00000005 }, \ - { 0x0040, 0x00000000 }, \ - { 0x0044, 0x00000008 }, \ - { 0x0048, 0x00000008 }, \ - { 0x004c, 0x00000010 }, \ - { 0x0050, 0x00000000 }, \ - { 0x0054, 0x0000001f }, \ - { 0x0800, 0x00000000 }, \ - { 0x0804, 0x00000000 }, \ - { 0x0808, 0x00000000 }, \ - { 0x080c, 0x00000000 }, \ - { 0x0810, 0x00000000 }, \ - { 0x0814, 0x00000000 }, \ - { 0x0818, 0x00000000 }, \ - { 0x081c, 0x00000000 }, \ - { 0x0820, 0x00000000 }, \ - { 0x0824, 0x00000000 }, \ - { 0x1230, 0x00000000 }, \ - { 0x8004, 0x00000000 }, \ - { 0x8008, 0x00000000 }, \ - { 0x800c, 0x00000000 }, \ - { 0x8018, 0x00000000 }, \ - { 0x8024, 0x00000000 }, \ - { 0x8028, 0x00000030 }, \ - { 0x802c, 0x0007ffff }, \ - { 0x8030, 0x01ffffff }, \ - { 0x8034, 0x00000031 }, \ - { 0x8038, 0x00000000 }, \ - { 0x803c, 0x00000000 }, \ - { 0x8040, 0x00000000 }, \ - { 0x8044, 0x00000002 }, \ - { 0x8048, 0x00000000 }, \ - { 0x8054, 0x00000000 }, \ - { 0x8058, 0x00000000 }, \ - /* PHY registers */ \ - { 0x9808, 0x00000000 }, \ - { 0x980c, 0x2d849093 }, \ - { 0x9810, 0x7d32e000 }, \ - { 0x9814, 0x00000f6b }, \ - { 0x981c, 0x00000000 }, \ - { 0x982c, 0x00026ffe }, \ - { 0x9830, 0x00000000 }, \ - { 0x983c, 0x00020100 }, \ - { 0x9840, 0x206a017a }, \ - { 0x984c, 0x1284613c }, \ - { 0x9854, 0x00000859 }, \ - { 0x9868, 0x409a4190 }, \ - { 0x986c, 0x050cb081 }, \ - { 0x9870, 0x0000000f }, \ - { 0x9874, 0x00000080 }, \ - { 0x9878, 0x0000000c }, \ - { 0x9900, 0x00000000 }, \ - { 0x9904, 0x00000000 }, \ - { 0x9908, 0x00000000 }, \ - { 0x990c, 0x00800000 }, \ - { 0x9910, 0x00000001 }, \ - { 0x991c, 0x0000092a }, \ - { 0x9920, 0x00000000 }, \ - { 0x9924, 0x00058a05 }, \ - { 0x9928, 0x00000001 }, \ - { 0x992c, 0x00000000 }, \ - { 0x9930, 0x00000000 }, \ - { 0x9934, 0x00000000 }, \ - { 0x9938, 0x00000000 }, \ - { 0x993c, 0x0000003f }, \ - { 0x9940, 0x00000004 }, \ - { 0x9948, 0x00000000 }, \ - { 0x994c, 0x00000000 }, \ - { 0x9950, 0x00000000 }, \ - { 0x9954, 0x5d50f14c }, \ - { 0x9958, 0x00000018 }, \ - { 0x995c, 0x004b6a8e }, \ - { 0xa184, 0x06ff05ff }, \ - { 0xa188, 0x07ff07ff }, \ - { 0xa18c, 0x08ff08ff }, \ - { 0xa190, 0x09ff09ff }, \ - { 0xa194, 0x0aff0aff }, \ - { 0xa198, 0x0bff0bff }, \ - { 0xa19c, 0x0cff0cff }, \ - { 0xa1a0, 0x0dff0dff }, \ - { 0xa1a4, 0x0fff0eff }, \ - { 0xa1a8, 0x12ff12ff }, \ - { 0xa1ac, 0x14ff13ff }, \ - { 0xa1b0, 0x16ff15ff }, \ - { 0xa1b4, 0x19ff17ff }, \ - { 0xa1b8, 0x1bff1aff }, \ - { 0xa1bc, 0x1eff1dff }, \ - { 0xa1c0, 0x23ff20ff }, \ - { 0xa1c4, 0x27ff25ff }, \ - { 0xa1c8, 0x2cff29ff }, \ - { 0xa1cc, 0x31ff2fff }, \ - { 0xa1d0, 0x37ff34ff }, \ - { 0xa1d4, 0x3aff3aff }, \ - { 0xa1d8, 0x3aff3aff }, \ - { 0xa1dc, 0x3aff3aff }, \ - { 0xa1e0, 0x3aff3aff }, \ - { 0xa1e4, 0x3aff3aff }, \ - { 0xa1e8, 0x3aff3aff }, \ - { 0xa1ec, 0x3aff3aff }, \ - { 0xa1f0, 0x3aff3aff }, \ - { 0xa1f4, 0x3aff3aff }, \ - { 0xa1f8, 0x3aff3aff }, \ - { 0xa1fc, 0x3aff3aff }, \ - /* BB gain table (64bytes) */ \ - { 0x9b00, 0x00000000 }, \ - { 0x9b04, 0x00000020 }, \ - { 0x9b08, 0x00000010 }, \ - { 0x9b0c, 0x00000030 }, \ - { 0x9b10, 0x00000008 }, \ - { 0x9b14, 0x00000028 }, \ - { 0x9b18, 0x00000004 }, \ - { 0x9b1c, 0x00000024 }, \ - { 0x9b20, 0x00000014 }, \ - { 0x9b24, 0x00000034 }, \ - { 0x9b28, 0x0000000c }, \ - { 0x9b2c, 0x0000002c }, \ - { 0x9b30, 0x00000002 }, \ - { 0x9b34, 0x00000022 }, \ - { 0x9b38, 0x00000012 }, \ - { 0x9b3c, 0x00000032 }, \ - { 0x9b40, 0x0000000a }, \ - { 0x9b44, 0x0000002a }, \ - { 0x9b48, 0x00000006 }, \ - { 0x9b4c, 0x00000026 }, \ - { 0x9b50, 0x00000016 }, \ - { 0x9b54, 0x00000036 }, \ - { 0x9b58, 0x0000000e }, \ - { 0x9b5c, 0x0000002e }, \ - { 0x9b60, 0x00000001 }, \ - { 0x9b64, 0x00000021 }, \ - { 0x9b68, 0x00000011 }, \ - { 0x9b6c, 0x00000031 }, \ - { 0x9b70, 0x00000009 }, \ - { 0x9b74, 0x00000029 }, \ - { 0x9b78, 0x00000005 }, \ - { 0x9b7c, 0x00000025 }, \ - { 0x9b80, 0x00000015 }, \ - { 0x9b84, 0x00000035 }, \ - { 0x9b88, 0x0000000d }, \ - { 0x9b8c, 0x0000002d }, \ - { 0x9b90, 0x00000003 }, \ - { 0x9b94, 0x00000023 }, \ - { 0x9b98, 0x00000013 }, \ - { 0x9b9c, 0x00000033 }, \ - { 0x9ba0, 0x0000000b }, \ - { 0x9ba4, 0x0000002b }, \ - { 0x9ba8, 0x0000002b }, \ - { 0x9bac, 0x0000002b }, \ - { 0x9bb0, 0x0000002b }, \ - { 0x9bb4, 0x0000002b }, \ - { 0x9bb8, 0x0000002b }, \ - { 0x9bbc, 0x0000002b }, \ - { 0x9bc0, 0x0000002b }, \ - { 0x9bc4, 0x0000002b }, \ - { 0x9bc8, 0x0000002b }, \ - { 0x9bcc, 0x0000002b }, \ - { 0x9bd0, 0x0000002b }, \ - { 0x9bd4, 0x0000002b }, \ - { 0x9bd8, 0x0000002b }, \ - { 0x9bdc, 0x0000002b }, \ - { 0x9be0, 0x0000002b }, \ - { 0x9be4, 0x0000002b }, \ - { 0x9be8, 0x0000002b }, \ - { 0x9bec, 0x0000002b }, \ - { 0x9bf0, 0x0000002b }, \ - { 0x9bf4, 0x0000002b }, \ - { 0x9bf8, 0x00000002 }, \ - { 0x9bfc, 0x00000016 }, \ - /* PHY activation */ \ - { 0x98d4, 0x00000020 }, \ - { 0x98d8, 0x00601068 }, \ -} - -struct ath5k_ar5212_ini { - u8 ini_flags; - u16 ini_register; - u32 ini_value; - -#define AR5K_INI_FLAG_511X 0x00 -#define AR5K_INI_FLAG_5111 0x01 -#define AR5K_INI_FLAG_5112 0x02 -#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) -}; - -#define AR5K_AR5212_INI { \ - { AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 }, \ - { AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 }, \ - { AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f }, \ - { AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x081c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0820, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0824, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1230, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1270, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1078, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1138, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1178, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1238, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1278, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1338, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1378, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1438, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1478, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1538, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1578, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1638, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1678, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1738, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1778, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x103c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x107c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x113c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x117c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x123c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x127c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x133c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x137c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x143c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x147c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8004, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8008, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x800c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8018, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8020, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8024, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8028, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x802c, 0x0007ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8030, 0x01ffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8034, 0x00000031 }, \ - { AR5K_INI_FLAG_BOTH, 0x8038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x803c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8048, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8054, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8058, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x805c, 0xffffc7ff }, \ - { AR5K_INI_FLAG_BOTH, 0x8080, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8084, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8088, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x808c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8090, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8094, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8098, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c0, 0x2a82301a }, \ - { AR5K_INI_FLAG_BOTH, 0x80c4, 0x05dc01e0 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c8, 0x1f402710 }, \ - { AR5K_INI_FLAG_BOTH, 0x80cc, 0x01f40000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80d0, 0x00001e1c }, \ - { AR5K_INI_FLAG_BOTH, 0x80d4, 0x0002aaaa }, \ - { AR5K_INI_FLAG_BOTH, 0x80d8, 0x02005555 }, \ - { AR5K_INI_FLAG_BOTH, 0x80dc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80e0, 0xffffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e4, 0x0000ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80ec, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f0, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f4, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80fc, 0x00000088 }, \ - { AR5K_INI_FLAG_BOTH, 0x8700, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8704, 0x0000008c }, \ - { AR5K_INI_FLAG_BOTH, 0x8708, 0x000000e4 }, \ - { AR5K_INI_FLAG_BOTH, 0x870c, 0x000002d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8710, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8714, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8718, 0x000000a0 }, \ - { AR5K_INI_FLAG_BOTH, 0x871c, 0x000001c9 }, \ - { AR5K_INI_FLAG_BOTH, 0x8720, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8724, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8728, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x872c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8730, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8734, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8738, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x873c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8740, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8744, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8748, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x874c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8750, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8754, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8758, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x875c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8760, 0x000000d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8764, 0x000000df }, \ - { AR5K_INI_FLAG_BOTH, 0x8768, 0x00000102 }, \ - { AR5K_INI_FLAG_BOTH, 0x876c, 0x0000013a }, \ - { AR5K_INI_FLAG_BOTH, 0x8770, 0x00000075 }, \ - { AR5K_INI_FLAG_BOTH, 0x8774, 0x0000007f }, \ - { AR5K_INI_FLAG_BOTH, 0x8778, 0x000000a2 }, \ - { AR5K_INI_FLAG_BOTH, 0x877c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8100, 0x00010002 }, \ - { AR5K_INI_FLAG_BOTH, 0x8104, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x8108, 0x000000c0 }, \ - { AR5K_INI_FLAG_BOTH, 0x810c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8110, 0x00000168 }, \ - { AR5K_INI_FLAG_BOTH, 0x8114, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87cc, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87d0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87dc, 0x1f1e1d1c }, \ - { AR5K_INI_FLAG_BOTH, 0x87e0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87ec, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87f0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87fc, 0x1f1e1d1c }, \ - /* PHY registers */ \ - { AR5K_INI_FLAG_BOTH, 0x9808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x980c, 0xad848e19 }, \ - { AR5K_INI_FLAG_BOTH, 0x9810, 0x7d28e000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9814, 0x9c0a9f6b }, \ - { AR5K_INI_FLAG_BOTH, 0x981c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x982c, 0x00022ffe }, \ - { AR5K_INI_FLAG_BOTH, 0x983c, 0x00020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x9840, 0x206a017a }, \ - { AR5K_INI_FLAG_BOTH, 0x984c, 0x1284613c }, \ - { AR5K_INI_FLAG_BOTH, 0x9854, 0x00000859 }, \ - { AR5K_INI_FLAG_BOTH, 0x9900, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9904, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a }, \ - { AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9934, 0x1e1f2022 }, \ - { AR5K_INI_FLAG_BOTH, 0x9938, 0x0a0b0c0d }, \ - { AR5K_INI_FLAG_BOTH, 0x993c, 0x0000003f }, \ - { AR5K_INI_FLAG_BOTH, 0x9940, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9948, 0x9280b212 }, \ - { AR5K_INI_FLAG_BOTH, 0x9954, 0x5d50e188 }, \ - { AR5K_INI_FLAG_BOTH, 0x9958, 0x000000ff }, \ - { AR5K_INI_FLAG_BOTH, 0x995c, 0x004b6a8e }, \ - { AR5K_INI_FLAG_BOTH, 0x9968, 0x000003ce }, \ - { AR5K_INI_FLAG_BOTH, 0x9970, 0x192fb515 }, \ - { AR5K_INI_FLAG_BOTH, 0x9974, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9978, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x997c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa184, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa188, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa18c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa190, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa194, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa198, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa19c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ac, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1bc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1cc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1dc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ec, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 }, \ - { AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 }, \ - { AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 }, \ - { AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a }, \ - { AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 }, \ - { AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 }, \ - { AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 }, \ - { AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa234, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa238, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa23c, 0x13c889af }, \ - { AR5K_INI_FLAG_BOTH, 0xa240, 0x38490a20 }, \ - { AR5K_INI_FLAG_BOTH, 0xa244, 0x00007bb6 }, \ - { AR5K_INI_FLAG_BOTH, 0xa248, 0x0fff3ffc }, \ - { AR5K_INI_FLAG_BOTH, 0x9b00, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b28, 0x0000000c }, \ - { AR5K_INI_FLAG_BOTH, 0x9b38, 0x00000012 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \ - { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \ - /* RF5111 specific */ \ - { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \ - { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \ - { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \ - { AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a }, \ - { AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 }, \ - { AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 }, \ - { AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 }, \ - { AR5K_INI_FLAG_5111, 0x9b10, 0x00000008 }, \ - { AR5K_INI_FLAG_5111, 0x9b14, 0x00000028 }, \ - { AR5K_INI_FLAG_5111, 0x9b18, 0x00000004 }, \ - { AR5K_INI_FLAG_5111, 0x9b1c, 0x00000024 }, \ - { AR5K_INI_FLAG_5111, 0x9b20, 0x00000014 }, \ - { AR5K_INI_FLAG_5111, 0x9b24, 0x00000034 }, \ - { AR5K_INI_FLAG_5111, 0x9b2c, 0x0000002c }, \ - { AR5K_INI_FLAG_5111, 0x9b30, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9b34, 0x00000022 }, \ - { AR5K_INI_FLAG_5111, 0x9b3c, 0x00000032 }, \ - { AR5K_INI_FLAG_5111, 0x9b40, 0x0000000a }, \ - { AR5K_INI_FLAG_5111, 0x9b44, 0x0000002a }, \ - { AR5K_INI_FLAG_5111, 0x9b48, 0x00000006 }, \ - { AR5K_INI_FLAG_5111, 0x9b4c, 0x00000026 }, \ - { AR5K_INI_FLAG_5111, 0x9b50, 0x00000016 }, \ - { AR5K_INI_FLAG_5111, 0x9b54, 0x00000036 }, \ - { AR5K_INI_FLAG_5111, 0x9b58, 0x0000000e }, \ - { AR5K_INI_FLAG_5111, 0x9b5c, 0x0000002e }, \ - { AR5K_INI_FLAG_5111, 0x9b60, 0x00000001 }, \ - { AR5K_INI_FLAG_5111, 0x9b68, 0x00000011 }, \ - { AR5K_INI_FLAG_5111, 0x9b6c, 0x00000031 }, \ - { AR5K_INI_FLAG_5111, 0x9b70, 0x00000009 }, \ - { AR5K_INI_FLAG_5111, 0x9b74, 0x00000029 }, \ - { AR5K_INI_FLAG_5111, 0x9b78, 0x00000005 }, \ - { AR5K_INI_FLAG_5111, 0x9b7c, 0x00000025 }, \ - { AR5K_INI_FLAG_5111, 0x9b80, 0x00000015 }, \ - { AR5K_INI_FLAG_5111, 0x9b84, 0x00000035 }, \ - { AR5K_INI_FLAG_5111, 0x9b88, 0x0000000d }, \ - { AR5K_INI_FLAG_5111, 0x9b90, 0x00000003 }, \ - { AR5K_INI_FLAG_5111, 0x9b94, 0x00000023 }, \ - { AR5K_INI_FLAG_5111, 0x9b98, 0x00000013 }, \ - { AR5K_INI_FLAG_5111, 0x9ba0, 0x0000000b }, \ - { AR5K_INI_FLAG_5111, 0x9ba4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9ba8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bac, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bbc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bcc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bdc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bec, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \ - /* RF5112 specific */ \ - { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \ - { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \ - { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \ - { AR5K_INI_FLAG_5112, 0x9b0c, 0x00000003 }, \ - { AR5K_INI_FLAG_5112, 0x9b10, 0x00000004 }, \ - { AR5K_INI_FLAG_5112, 0x9b14, 0x00000005 }, \ - { AR5K_INI_FLAG_5112, 0x9b18, 0x00000008 }, \ - { AR5K_INI_FLAG_5112, 0x9b1c, 0x00000009 }, \ - { AR5K_INI_FLAG_5112, 0x9b20, 0x0000000a }, \ - { AR5K_INI_FLAG_5112, 0x9b24, 0x0000000b }, \ - { AR5K_INI_FLAG_5112, 0x9b2c, 0x0000000d }, \ - { AR5K_INI_FLAG_5112, 0x9b30, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9b34, 0x00000011 }, \ - { AR5K_INI_FLAG_5112, 0x9b3c, 0x00000013 }, \ - { AR5K_INI_FLAG_5112, 0x9b40, 0x00000014 }, \ - { AR5K_INI_FLAG_5112, 0x9b44, 0x00000015 }, \ - { AR5K_INI_FLAG_5112, 0x9b48, 0x00000018 }, \ - { AR5K_INI_FLAG_5112, 0x9b4c, 0x00000019 }, \ - { AR5K_INI_FLAG_5112, 0x9b50, 0x0000001a }, \ - { AR5K_INI_FLAG_5112, 0x9b54, 0x0000001b }, \ - { AR5K_INI_FLAG_5112, 0x9b58, 0x0000001c }, \ - { AR5K_INI_FLAG_5112, 0x9b5c, 0x0000001d }, \ - { AR5K_INI_FLAG_5112, 0x9b60, 0x00000020 }, \ - { AR5K_INI_FLAG_5112, 0x9b68, 0x00000022 }, \ - { AR5K_INI_FLAG_5112, 0x9b6c, 0x00000023 }, \ - { AR5K_INI_FLAG_5112, 0x9b70, 0x00000024 }, \ - { AR5K_INI_FLAG_5112, 0x9b74, 0x00000025 }, \ - { AR5K_INI_FLAG_5112, 0x9b78, 0x00000028 }, \ - { AR5K_INI_FLAG_5112, 0x9b7c, 0x00000029 }, \ - { AR5K_INI_FLAG_5112, 0x9b80, 0x0000002a }, \ - { AR5K_INI_FLAG_5112, 0x9b84, 0x0000002b }, \ - { AR5K_INI_FLAG_5112, 0x9b88, 0x0000002c }, \ - { AR5K_INI_FLAG_5112, 0x9b90, 0x00000030 }, \ - { AR5K_INI_FLAG_5112, 0x9b94, 0x00000031 }, \ - { AR5K_INI_FLAG_5112, 0x9b98, 0x00000032 }, \ - { AR5K_INI_FLAG_5112, 0x9ba0, 0x00000034 }, \ - { AR5K_INI_FLAG_5112, 0x9ba4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9ba8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bac, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bbc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bcc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bdc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bec, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf8, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9bfc, 0x0000001a }, \ -} - struct ath5k_ar5211_ini_mode { u16 mode_register; u32 mode_value[4]; @@ -1986,6 +1916,11 @@ struct ath5k_ar5212_ini_mode { u32 mode_value[2][5]; }; +#define AR5K_INI_FLAG_511X 0x00 +#define AR5K_INI_FLAG_5111 0x01 +#define AR5K_INI_FLAG_5112 0x02 +#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) + #define AR5K_AR5212_INI_MODE { \ { 0x0030, AR5K_INI_FLAG_511X, { \ { 0, }, \ @@ -2143,8 +2078,8 @@ struct ath5k_ar5212_ini_mode { { 0, }, \ { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } \ } }, \ - { 0xa208, AR5K_INI_FLAG_5112, { \ - { 0, }, \ + { 0xa208, AR5K_INI_FLAG_BOTH, { \ + { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 }, \ { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } \ } }, \ { 0xa20c, AR5K_INI_FLAG_5112, { \ @@ -2159,6 +2094,7 @@ struct ath5k_ar5211_ini_rf { }; #define AR5K_AR5211_INI_RF { \ +/* Static -> moved on ar5211_ini */ \ { 0x0000a204, { 0x00000000, 0x00000000 } }, \ { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \ { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \ @@ -2170,6 +2106,7 @@ struct ath5k_ar5211_ini_rf { { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \ { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \ { 0x0000a22c, { 0x00000020, 0x00000020 } }, \ +/* Bank 6 ? */ \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ @@ -2187,7 +2124,7 @@ struct ath5k_ar5211_ini_rf { { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \ { 0x000098d4, { 0x00000000, 0x00000004 } }, \ - \ +/* Bank 7 ? */ \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ diff --git a/ath5k_reg.h b/ath5k_reg.h index 05c0b88..e40706b 100644 --- a/ath5k_reg.h +++ b/ath5k_reg.h @@ -1586,7 +1586,7 @@ #define AR5K_KEYTABLE_0_5210 0x9000 #define AR5K_KEYTABLE_0_5211 0x8800 #define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) -#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) * 32)) +#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5)) #define AR5K_KEYTABLE(_n) (hal->ah_version == AR5K_AR5210 ? \ AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) #define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) @@ -1661,7 +1661,7 @@ #define AR5K_PHY_ACT_DISABLE 0x00000002 /* - * PHY signal register [5110] + * PHY signal register */ #define AR5K_PHY_SIG 0x9858 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 @@ -1670,7 +1670,7 @@ #define AR5K_PHY_SIG_FIRPWR_S 18 /* - * PHY coarse agility control register [5110] + * PHY coarse agility control register */ #define AR5K_PHY_AGCCOARSE 0x985c #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 @@ -1715,7 +1715,7 @@ #define AR5K_PHY_SCAL_32MHZ 0x0000000e /* - * PHY PLL control register [5111+] + * PHY PLL (Phase Locked Loop) control register */ #define AR5K_PHY_PLL 0x987c #define AR5K_PHY_PLL_20MHZ 0x13 /* [5111] */ @@ -1731,7 +1731,58 @@ #define AR5K_PHY_PLL_RF5112 0x00000040 /* - * PHY RF stage register [5110] + * RF Buffer register + * + * There are some special control registers on the RF chip + * that hold various operation settings related mostly to + * the analog parts (channel, gain adjustment etc). + * + * We don't write on those registers directly but + * we send a data packet on the buffer register and + * then write on another special register to notify hw + * to apply the settings. This is done so that control registers + * can be dynamicaly programmed during operation and the settings + * are applied faster on the hw. + * + * We sent such data packets during rf initialization and channel change + * through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions. + * + * The data packets we send during initializadion are inside ath5k_ini_rf + * struct (see ath5k_hw.h) and each one is related to an "rf register bank". + * We use *rfregs functions to modify them acording to current operation + * mode and eeprom values and pass them all together to the chip. + * + * It's obvious from the code that 0x989c is the buffer register but + * for the other special registers that we write to after sending each + * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers + * for now. It's interesting that they are also used for some other operations. + * + * Also check out ath5k_hw.h and U.S. Patent 6677779 B1 (about buffer + * registers and control registers) + */ + +#define AR5K_RF_BUFFER 0x989c +#define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */ +#define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */ +#define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */ + +#define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */ + /* Channel set on 5111 */ + /* Used to read radio revision*/ + +#define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* Bank 0,1,2,6 on 5111 */ + /* Bank 1 on 5112 */ + /* Used during activation on 5111 */ + +#define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */ + /* Used during activation on 5111 */ + /* Channel on 5112 */ + /* Bank 6 on 5112 */ + +#define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */ + +/* + * PHY RF stage register [5210] */ #define AR5K_PHY_RFSTG 0x98d4 #define AR5K_PHY_RFSTG_DISABLE 0x00000021 @@ -1743,7 +1794,7 @@ #define AR5K_PHY_RX_DELAY_M 0x00003fff /* - * PHY timing IQ control register [5111+] + * PHY timing I(nphase) Q(adrature) control register [5111+] */ #define AR5K_PHY_IQ 0x9920 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f @@ -1756,7 +1807,9 @@ /* - * PHY PAPD probe register [5111+] + * PHY PAPD probe register [5111+ (?)] + * Is this only present in 5212 ? + * Because it's always 0 in 5211 initialization code */ #define AR5K_PHY_PAPD_PROBE 0x9930 #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 @@ -1769,10 +1822,12 @@ #define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 #define AR5K_PHY_PAPD_PROBE_GAINF_S 25 +#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ +#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ /* - * PHY TX power registers [5112+] + * PHY TX rate power registers [5112+] */ #define AR5K_PHY_TXPOWER_RATE1 0x9934 #define AR5K_PHY_TXPOWER_RATE2 0x9938 @@ -1863,16 +1918,16 @@ after DFS is enabled */ /* * Misc PHY/radio registers [5110 - 5111] */ -#define AR5K_BB_GAIN_BASE 0x9b00 +#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) -#define AR5K_RF_GAIN_BASE 0x9a00 +#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) /* * PHY timing IQ calibration result register [5111+] */ -#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 -#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 +#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ +#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* @@ -1881,7 +1936,7 @@ after DFS is enabled */ #define AR5K_PHY_CURRENT_RSSI 0x9c1c /* - * PHY PCDAC TX power register [5112+] + * PHY PCDAC TX power register [511+ (?)] */ #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) @@ -1903,15 +1958,16 @@ after DFS is enabled */ #define AR5K_PHY_MODE_XR 0x00000010 /* [5112+] */ /* - * PHY CCK transmit control register [5112+] + * PHY CCK transmit control register [5111+ (?)] */ #define AR5K_PHY_CCKTXCTL 0xa204 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 /* - * PHY 2GHz gain register [5112+] + * PHY 2GHz gain register [5111+] */ #define AR5K_PHY_GAIN_2GHZ 0xa20c #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 +#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c commit c3fc36d0f35c4cee64f2ca4a70a7bd15632073f1 Author: Jiri Slaby Date: Sun Jul 15 16:05:38 2007 +0200 attach cleanup diff --git a/ath.c b/ath.c index 7367a88..871a58d 100644 --- a/ath.c +++ b/ath.c @@ -1645,8 +1645,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) * beacon frames and one data queue for each QoS * priority. Note that the hal handles reseting * these queues at the needed time. - * - * XXX PS-Poll */ ret = ath_beaconq_setup(ah); if (ret < 0) { @@ -1673,28 +1671,14 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); #ifdef BLE - /* - * Setup rate control. Some rate control modules - * call back to change the anntena state so expose - * the necessary entry points. - * XXX maybe belongs in struct ath_ratectrl? - */ - sc->sc_setdefantenna = ath_setdefantenna; - sc->sc_rc = ath_rate_attach(sc); - if (sc->sc_rc == NULL) { - error = EIO; - goto bad2; - } - - setup_timer(&sc->scan_ch, ath_next_scan, (unsigned long)hw); setup_timer(&sc->cal_ch, ath_calibrate, (unsigned long)hw); + setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); sc->blinking = 0; sc->ledstate = 1; sc->ledon = 0; /* low true */ sc->ledidle = msecs_to_jiffies(2700); /* 2.7sec */ - setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); /* * Auto-enable soft led processing for IBM cards and for * 5211 minipci cards. Users can also manually enable/disable @@ -1707,21 +1691,13 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); } - sc->sc_hasclrkey = ath_hal_ciphersupported(ah, AR5K_CIPHER_CLR); sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); /* - * Query the hal about antenna support. - */ - sc->sc_defant = ath5k_hw_get_def_antenna(ah); - - /* * Not all chips have the VEOL support we want to * use with IBSS beacons; check here for it. */ sc->sc_hasveol = ath_hal_hasveol(ah); - - sc->sc_rxfilter = 0; #endif ath5k_hw_get_lladdr(ah, mac); @@ -1737,13 +1713,9 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto err_queues; } -// ath_dynamic_sysctl_register(sc); -// ath_announce(sc); - return 0; err_queues: ath_tx_cleanup(sc); -//err_desc: ath_desc_free(sc, pdev); err: return ret; commit a1091593168be19a255d879254ab39314c848d84 Author: Jiri Slaby Date: Sun Jul 15 17:29:59 2007 +0200 calibration diff --git a/ath.c b/ath.c index 871a58d..e6c38a8 100644 --- a/ath.c +++ b/ath.c @@ -51,10 +51,13 @@ enum { ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ ATH_DEBUG_INTR = 0x00001000, /* ISR */ + ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ ATH_DEBUG_ANY = 0xffffffff }; +static int ath_calinterval = ATH_SHORT_CALIB; + static int countrycode = CTRY_DEFAULT; static int outdoor = true; static int xchanmode = true; @@ -566,6 +569,9 @@ static int ath_init(struct ath_softc *sc) ath5k_hw_set_intr(sc->ah, sc->imask); + mod_timer(&sc->calib_tim, jiffies + + msecs_to_jiffies(ath_calinterval * 1000)); + ret = 0; done: mutex_unlock(&sc->lock); @@ -752,6 +758,9 @@ static int ath_stop_hw(struct ath_softc *sc) } } mutex_unlock(&sc->lock); + + del_timer_sync(&sc->calib_tim); + return ret; } @@ -1138,6 +1147,39 @@ static struct ieee80211_ops ath_hw_ops = { .beacon_update = NULL, }; +/* + * Periodically recalibrate the PHY to account + * for temperature/environment changes. + */ +static void ath_calibrate(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + struct ath_hw *ah = sc->ah; + + sc->stats.ast_per_cal++; + + DPRINTF(sc, ATH_DEBUG_CALIBRATE, "ath: channel %u/%x\n", + sc->curchan->chan, sc->curchan->val); + + if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { + /* + * Rfgain is out of bounds, reset the chip + * to load new gain values. + */ + sc->stats.ast_per_rfgain++; + DPRINTF(sc, ATH_DEBUG_RESET, "calibration, resetting\n"); + ath_reset(sc->hw); + } + if (ath5k_hw_phy_calibrate(ah, sc->curchan)) { + DPRINTF(sc, ATH_DEBUG_ANY, "ath: calibration of channel %u " + "failed\n", sc->curchan->chan); + sc->stats.ast_per_calfail++; + } + + mod_timer(&sc->calib_tim, jiffies + + msecs_to_jiffies(ath_calinterval * 1000)); +} + static irqreturn_t ath_intr(int irq, void *dev_id) { struct ath_softc *sc = dev_id; @@ -1670,8 +1712,8 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); + setup_timer(&sc->calib_tim, ath_calibrate, (unsigned long)sc); #ifdef BLE - setup_timer(&sc->cal_ch, ath_calibrate, (unsigned long)hw); setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); sc->blinking = 0; @@ -1983,6 +2025,8 @@ enum { DEV_ATH = 9, /* XXX known by hal */ }; +static int mincalibrate = 1; +static int maxint = 0x7ffffff / 1000; #define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ static ctl_table ath_static_sysctls[] = { @@ -2016,6 +2060,15 @@ static ctl_table ath_static_sysctls[] = { .maxlen = sizeof(xchanmode), .proc_handler = proc_dointvec }, + { .ctl_name = CTL_AUTO, + .procname = "calibrate", + .mode = 0644, + .data = &ath_calinterval, + .maxlen = sizeof(ath_calinterval), + .extra1 = &mincalibrate, + .extra2 = &maxint, + .proc_handler = proc_dointvec_minmax + }, { 0 } }; static ctl_table ath_ath_table[] = { diff --git a/ath.h b/ath.h index a085294..25393f7 100644 --- a/ath.h +++ b/ath.h @@ -52,6 +52,9 @@ #define ATH_TIMEOUT 1000 +#define ATH_LONG_CALIB 30 /* seconds */ +#define ATH_SHORT_CALIB 1 + /* * Maximum acceptable MTU * MAXFRAMEBODY - WEP - QOS - RSN/WPA: @@ -243,12 +246,11 @@ struct ath_softc { COMMIT /* beacon sent, commit change */ } sc_updateslot; /* slot time update fsm */ - struct timer_list sc_cal_ch; /* calibration timer */ - struct timer_list sc_scan_ch; /* AP scan timer */ struct iw_statistics sc_iwstats; /* wireless statistics block */ struct ctl_table_header *sc_sysctl_header; struct ctl_table *sc_sysctls; #endif + struct timer_list calib_tim; /* calibration timer */ }; void ath_sysctl_register(void); diff --git a/ath/if_ath.c b/ath/if_ath.c index 794df8a..264724f 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -3340,64 +3340,8 @@ ath_tx_tasklet(unsigned long data) netif_wake_queue(&sc->sc_rawdev); } - -static void -ath_tx_timeout(struct net_device *dev) -{ - struct ath_softc *sc = dev->priv; - sc->sc_stats.ast_watchdog++; - ath_init(dev); -} - -#endif -#ifdef BLE #endif -static void -ath_next_scan(unsigned long arg) -{ -#ifdef BLE - struct net_device *dev = (struct net_device *) arg; - struct ath_softc *sc = dev->priv; - - if (ic->ic_state == IEEE80211_S_SCAN) - ieee80211_next_scan(ic); -#endif -} -/* - * Periodically recalibrate the PHY to account - * for temperature/environment changes. - */ -static void -ath_calibrate(unsigned long arg) -{ - struct ieee80211_hw *hw = (void *)arg; - struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; - - sc->sc_stats.ast_per_cal++; - - DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", - __func__, sc->sc_curchan.freq, sc->sc_curchan.channel_flags); - - if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { - /* - * Rfgain is out of bounds, reset the chip - * to load new gain values. - */ - sc->sc_stats.ast_per_rfgain++; - DPRINTF(sc, ATH_DEBUG_RESET, "calibration, resetting\n"); - ath_reset(hw); - } - if (!ath5k_hw_phy_calibrate(ah, &sc->sc_curchan)) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: calibration of channel %u failed\n", - __func__, sc->sc_curchan.freq); - sc->sc_stats.ast_per_calfail++; - } - sc->sc_cal_ch.expires = jiffies + (ath_calinterval * HZ); - add_timer(&sc->sc_cal_ch); -} #ifdef BLE static int ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) @@ -4434,7 +4378,6 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, static int mindwelltime = 100; /* 100ms */ static int mincalibrate = 1; /* once a second */ -static int maxint = 0x7fffffff; /* 32-bit big */ #define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ diff --git a/ath5k.h b/ath5k.h index 012bb46..77e21dd 100644 --- a/ath5k.h +++ b/ath5k.h @@ -968,9 +968,6 @@ struct ath_hw { /* * Prototypes */ -typedef bool (ath5k_rfgain_t)(struct ath_hw *, struct ieee80211_channel *, - unsigned int); - /* General Functions */ u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); /* Attach/Detach Functions */ @@ -1063,15 +1060,7 @@ bool ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags); bool ath_hal_init_channels(struct ath_hw *hal, struct ieee80211_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); u16 ath5k_get_regdomain(struct ath_hw *hal); /* PHY/RF access functions */ -bool ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel); -bool ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan); -bool ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); bool ath5k_hw_phy_disable(struct ath_hw *hal); void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); @@ -1079,10 +1068,6 @@ unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 firs u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal); bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal); s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal); -bool ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); -bool ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); -bool ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode); -void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, unsigned int ee_mode); bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ diff --git a/ath5k_hw.c b/ath5k_hw.c index 2b8cce7..121d464 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -66,6 +66,16 @@ static int ath5k_hw_get_capabilities(struct ath_hw *); static int ath5k_eeprom_init(struct ath_hw *); static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *); +static int ath5k_hw_channel(struct ath_hw *, struct ieee80211_channel *); +static int ath5k_hw_rfregs(struct ath_hw *, struct ieee80211_channel *, + unsigned int); +static int ath5k_hw_rf5111_rfregs(struct ath_hw *, struct ieee80211_channel *, + unsigned int); +static int ath5k_hw_rf5112_rfregs(struct ath_hw *, struct ieee80211_channel *, + unsigned int); +static void ath5k_hw_ar5211_rfregs(struct ath_hw *, struct ieee80211_channel *, + unsigned int, unsigned int); + /* * Initial register dumps */ @@ -983,9 +993,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * Write RF registers * TODO:Does this work on 5211 (5111) ? */ - if (ath5k_hw_rfregs(hal, channel, mode) == false) { - return -EINPROGRESS; - } + ret = ath5k_hw_rfregs(hal, channel, mode); + if (ret) + return ret; /* * Configure additional registers @@ -1137,8 +1147,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Set channel and calibrate the PHY */ - if (ath5k_hw_channel(hal, channel) == false) - return -EIO; + ret = ath5k_hw_channel(hal, channel); + if (ret) + return ret; /* * Enable the PHY and wait until completion @@ -4522,51 +4533,9 @@ ath5k_get_regdomain(struct ath_hw *hal) \*************************/ /* - * Set a channel on the radio chip - */ -bool -ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel *channel) -{ - bool ret; - - /* - * Check bounds supported by the PHY - * (don't care about regulation restrictions at this point) - */ - if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min || - channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) && - (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min || - channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { - AR5K_PRINTF("channel out of supported range (%u MHz)\n", - channel->freq); - return false; - } - - /* - * Set the channel and wait - */ - if (hal->ah_radio == AR5K_RF5110) - ret = ath5k_hw_rf5110_channel(hal, channel); - else if (hal->ah_radio == AR5K_RF5111) - ret = ath5k_hw_rf5111_channel(hal, channel); - else - ret = ath5k_hw_rf5112_channel(hal, channel); - - if (ret == false) - return ret; - - hal->ah_current_channel.freq = channel->freq; - hal->ah_current_channel.val = channel->val; - hal->ah_turbo = channel->val == CHANNEL_T ? true : false; - - return true; -} - -/* * Convertion needed for RF5110 */ -u32 -ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) +static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) { u32 athchan; @@ -4577,8 +4546,7 @@ ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) * different RF/PHY part. */ athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq, - channel->val) - 24) / 2, 5) << 1) | - (1 << 6) | 0x1; + channel->val) - 24) / 2, 5) << 1) | (1 << 6) | 0x1; return athchan; } @@ -4586,8 +4554,7 @@ ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) /* * Set channel on RF5110 */ -bool -ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +static int ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) { u32 data; @@ -4599,14 +4566,14 @@ ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) ath5k_hw_reg_write(hal, 0, AR5K_RF_BUFFER_CONTROL_0); mdelay(1); - return true; + return 0; } /* * Convertion needed for 5111 */ -bool -ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan) +static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, + struct ath5k_athchan_2ghz *athchan) { int channel; @@ -4626,33 +4593,35 @@ ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athch athchan->a2_athchan = ((channel - 14) * 4) + 132; athchan->a2_flags = 0x46; } else - return false; + return -EINVAL; - return true; + return 0; } /* * Set channel on 5111 */ -bool -ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +static int ath5k_hw_rf5111_channel(struct ath_hw *hal, + struct ieee80211_channel *channel) { + struct ath5k_athchan_2ghz ath_channel_2ghz; unsigned int ieee_channel, ath_channel; u32 data0, data1, clock; - struct ath5k_athchan_2ghz ath_channel_2ghz; + int ret; /* * Set the channel on the RF5111 radio */ data0 = data1 = 0; ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, - channel->val); + channel->val); if (channel->val & CHANNEL_2GHZ) { /* Map 2GHz channel to 5GHz Atheros channel ID */ - if (ath5k_hw_rf5111_chan2athchan(ieee_channel, - &ath_channel_2ghz) == false) - return false; + ret = ath5k_hw_rf5111_chan2athchan(ieee_channel, + &ath_channel_2ghz); + if (ret) + return ret; ath_channel = ath_channel_2ghz.a2_athchan; data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) @@ -4674,14 +4643,14 @@ ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) ath5k_hw_reg_write(hal, ((data1 >> 8) & 0xff) | (data0 & 0xff00), AR5K_RF_BUFFER_CONTROL_3); - return true; + return 0; } /* * Set channel on 5112 */ -bool -ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +static int ath5k_hw_rf5112_channel(struct ath_hw *hal, + struct ieee80211_channel *channel) { u32 data, data0, data1, data2; u16 c; @@ -4700,7 +4669,7 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) data0 = ((2 * (c - 672)) - 3040) / 10; data1 = 0; } else - return false; + return -EINVAL; data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); } else { @@ -4714,7 +4683,7 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); data2 = ath5k_hw_bitswap(1, 2); } else - return false; + return -EINVAL; } data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; @@ -4722,44 +4691,64 @@ ath5k_hw_rf5112_channel(struct ath_hw *hal, struct ieee80211_channel *channel) ath5k_hw_reg_write(hal, data & 0xff, AR5K_RF_BUFFER); ath5k_hw_reg_write(hal, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); - return true; + return 0; } /* - * Perform a PHY calibration + * Set a channel on the radio chip */ -bool -ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel){ +static int ath5k_hw_channel(struct ath_hw *hal, + struct ieee80211_channel *channel) +{ + int ret; - bool ret; + /* + * Check bounds supported by the PHY + * (don't care about regulation restrictions at this point) + */ + if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) && + (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { + AR5K_PRINTF("channel out of supported range (%u MHz)\n", + channel->freq); + return -EINVAL; + } - if (hal->ah_radio == AR5K_RF5110) - ret = ath5k_hw_rf5110_calibrate(hal,channel); - else - ret = ath5k_hw_rf511x_calibrate(hal,channel); + /* + * Set the channel and wait + */ + switch (hal->ah_radio) { + case AR5K_RF5110: + ret = ath5k_hw_rf5110_channel(hal, channel); + break; + case AR5K_RF5111: + ret = ath5k_hw_rf5111_channel(hal, channel); + break; + default: + ret = ath5k_hw_rf5112_channel(hal, channel); + break; + } - return ret; + if (ret) + return ret; + + hal->ah_current_channel.freq = channel->freq; + hal->ah_current_channel.val = channel->val; + hal->ah_turbo = channel->val == CHANNEL_T ? true : false; + + return 0; } + /* * Perform a PHY calibration on RF5110 */ -bool -ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) +static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal, + struct ieee80211_channel *channel) { - bool ret = true; u32 phy_sig, phy_agc, phy_sat, beacon, noise_floor; unsigned int i; - -#define AGC_DISABLE { \ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, \ - AR5K_PHY_AGC_DISABLE); \ - udelay(10); \ -} - -#define AGC_ENABLE { \ - AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, \ - AR5K_PHY_AGC_DISABLE); \ -} + int ret; /* * Disable beacons and RX/TX queues, wait @@ -4774,7 +4763,8 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) /* * Set the channel (with AGC turned off) */ - AGC_DISABLE; + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); + udelay(10); ret = ath5k_hw_channel(hal, channel); /* @@ -4783,9 +4773,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); mdelay(1); - AGC_ENABLE; + AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); - if (ret == false) + if (ret) return ret; /* @@ -4813,44 +4803,42 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) udelay(20); - AGC_DISABLE; + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); + udelay(10); ath5k_hw_reg_write(hal, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); - AGC_ENABLE; + AR5K_REG_DISABLE_BITS(hal, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); mdelay(1); /* * Enable calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL); + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); - if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_CAL, 0, false)) { - AR5K_PRINTF("calibration timeout (%uMHz)\n", - channel->freq); - ret = false; - } + ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL, 0, false); /* Reset to normal state */ ath5k_hw_reg_write(hal, phy_sig, AR5K_PHY_SIG); ath5k_hw_reg_write(hal, phy_agc, AR5K_PHY_AGCCOARSE); ath5k_hw_reg_write(hal, phy_sat, AR5K_PHY_ADCSAT); - if (ret == false) - return false; + if (ret) { + AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); + return ret; + } /* * Enable noise floor calibration and wait until completion */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF); + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); - if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF, 0, false)) { + ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF, 0, false); + if (ret) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", channel->freq); - return false; + return ret; } /* Wait until the noise floor is calibrated */ @@ -4858,8 +4846,7 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) mdelay(1); noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF); - if (AR5K_PHY_NF_RVAL(noise_floor) & - AR5K_PHY_NF_ACTIVE) + if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) noise_floor = AR5K_PHY_NF_AVAL(noise_floor); if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) @@ -4869,10 +4856,9 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", channel->freq); - return false; + return -EIO; } - /* * Re-enable RX/TX and beacons */ @@ -4880,24 +4866,21 @@ ath5k_hw_rf5110_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); ath5k_hw_reg_write(hal, beacon, AR5K_BEACON_5210); -#undef AGC_ENABLE -#undef AGC_DISABLE - - return true; + return 0; } /* * Perform a PHY calibration on RF5111/5112 */ -bool -ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) +static int ath5k_hw_rf511x_calibrate(struct ath_hw *hal, + struct ieee80211_channel *channel) { u32 i_pwr, q_pwr; s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; AR5K_TRACE; if (hal->ah_calibration == false || - ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) + ath5k_hw_reg_read(hal, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) goto done; hal->ah_calibration = false; @@ -4915,15 +4898,12 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; /* Commit new IQ value */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_CORR_ENABLE | - ((u32)q_coff) | - ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | + ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); - done: +done: /* Start noise floor calibration */ - AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF); + AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); /* Request RF gain */ if (channel->val & CHANNEL_5GHZ) { @@ -4933,7 +4913,23 @@ ath5k_hw_rf511x_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel) hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } - return true; + return 0; +} + +/* + * Perform a PHY calibration + */ +int ath5k_hw_phy_calibrate(struct ath_hw *hal, + struct ieee80211_channel *channel) +{ + int ret; + + if (hal->ah_radio == AR5K_RF5110) + ret = ath5k_hw_rf5110_calibrate(hal, channel); + else + ret = ath5k_hw_rf511x_calibrate(hal, channel); + + return ret; } bool @@ -4965,9 +4961,8 @@ ath5k_hw_get_def_antenna(struct ath_hw *hal) return false; /*XXX: What do we return for 5210 ?*/ } -unsigned int -ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, - u32 first, u32 col, bool set) +unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, + u32 first, u32 col, bool set) { u32 mask, entry, last, data, shift, position; s32 left; @@ -5091,14 +5086,12 @@ ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) hal->ah_gain.g_current <= level[3])); } -s32 -ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) +s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) { - int ret = 0; const struct ath5k_gain_opt *go; + int ret = 0; - go = hal->ah_radio == AR5K_RF5111 ? - &rf5111_gain_opt : &rf5112_gain_opt; + go = hal->ah_radio == AR5K_RF5111 ? &rf5111_gain_opt : &rf5112_gain_opt; hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; @@ -5106,10 +5099,10 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) if (hal->ah_gain.g_step_idx == 0) return -1; for (hal->ah_gain.g_target = hal->ah_gain.g_current; - hal->ah_gain.g_target >= hal->ah_gain.g_high && - hal->ah_gain.g_step_idx > 0; - hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { + hal->ah_gain.g_target >= hal->ah_gain.g_high && + hal->ah_gain.g_step_idx > 0; + hal->ah_gain.g_step = + &go->go_step[hal->ah_gain.g_step_idx]) { hal->ah_gain.g_target -= 2 * (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - hal->ah_gain.g_step->gos_gain); @@ -5123,12 +5116,12 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) return -2; for (hal->ah_gain.g_target = hal->ah_gain.g_current; - hal->ah_gain.g_target <= hal->ah_gain.g_low && - hal->ah_gain.g_step_idx < (go->go_steps_count - 1); - hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { + hal->ah_gain.g_target <= hal->ah_gain.g_low && + hal->ah_gain.g_step_idx < go->go_steps_count-1; + hal->ah_gain.g_step = + &go->go_step[hal->ah_gain.g_step_idx]) { hal->ah_gain.g_target -= 2 * - (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - + (go->go_step[++hal->ah_gain.g_step_idx].gos_gain - hal->ah_gain.g_step->gos_gain); } @@ -5136,7 +5129,7 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) goto done; } - done: +done: #ifdef AR5K_DEBUG AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", ret, @@ -5151,36 +5144,39 @@ ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) /* * Initialize RF */ -bool -ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) +static int ath5k_hw_rfregs(struct ath_hw *hal, + struct ieee80211_channel *channel, unsigned int mode) { - ath5k_rfgain_t *func = NULL; - bool ret; + int (*func)(struct ath_hw *, struct ieee80211_channel *, unsigned int); + int ret; - if (hal->ah_radio == AR5K_RF5111) { + switch (hal->ah_radio) { + case AR5K_RF5111: hal->ah_rf_banks_size = sizeof(rf5111_rf); func = ath5k_hw_rf5111_rfregs; - } else if (hal->ah_radio == AR5K_RF5112) { + break; + case AR5K_RF5112: if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) hal->ah_rf_banks_size = sizeof(rf5112a_rf); else hal->ah_rf_banks_size = sizeof(rf5112_rf); func = ath5k_hw_rf5112_rfregs; - } else - return false; + break; + default: + return -EINVAL; + } if (hal->ah_rf_banks == NULL) { /* XXX do extra checks? */ - if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, - GFP_KERNEL)) == NULL) { + hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, GFP_KERNEL); + if (hal->ah_rf_banks == NULL) { AR5K_PRINT("out of memory\n"); - return false; + return -ENOMEM; } } - ret = (func)(hal, channel, mode); - - if (ret == true) + ret = func(hal, channel, mode); + if (!ret) hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; return ret; @@ -5189,8 +5185,8 @@ ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned /* * Initialize RF5111 */ -bool -ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) +static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal, + struct ieee80211_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); @@ -5204,10 +5200,9 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un /* Copy values to modify them */ for (i = 0; i < rf_size; i++) { - if (rf5111_rf[i].rf_bank >= - AR5K_RF5111_INI_RF_MAX_BANKS) { + if (rf5111_rf[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return false; + return -EINVAL; } if (bank != rf5111_rf[i].rf_bank) { @@ -5227,12 +5222,12 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un obdb = 0; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 119, 0, true)) - return false; + ee->ee_ob[ee_mode][obdb], 3, 119, 0, true)) + return -EINVAL; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 122, 0, true)) - return false; + ee->ee_ob[ee_mode][obdb], 3, 122, 0, true)) + return -EINVAL; obdb = 1; /* Modify bank 6 */ @@ -5245,38 +5240,38 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un (channel->freq > 4000 ? 0 : -1))); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_84, 1, 51, 3, true)) - return false; + ee->ee_pwd_84, 1, 51, 3, true)) + return -EINVAL; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_90, 1, 45, 3, true)) - return false; + ee->ee_pwd_90, 1, 45, 3, true)) + return -EINVAL; } if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - !ee->ee_xpd[ee_mode], 1, 95, 0, true)) - return false; + !ee->ee_xpd[ee_mode], 1, 95, 0, true)) + return -EINVAL; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 4, 96, 0, true)) - return false; + ee->ee_x_gain[ee_mode], 4, 96, 0, true)) + return -EINVAL; - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true)) - return false; + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? + ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true)) + return -EINVAL; - if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) - return false; + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? + ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true)) + return -EINVAL; /* Modify bank 7 */ if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 29, 0, true)) - return false; + ee->ee_i_gain[ee_mode], 6, 29, 0, true)) + return -EINVAL; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_xpd[ee_mode], 1, 4, 0, true)) - return false; + ee->ee_xpd[ee_mode], 1, 4, 0, true)) + return -EINVAL; /* Write RF values */ for (i = 0; i < rf_size; i++) { @@ -5284,14 +5279,14 @@ ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un ath5k_hw_reg_write(hal, rf[i], rf5111_rf[i].rf_register); } - return true; + return 0; } /* * Initialize RF5112 */ -bool -ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) +static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal, + struct ieee80211_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; unsigned int rf_size; @@ -5316,7 +5311,7 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un for (i = 0; i < rf_size; i++) { if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return false; + return -EINVAL; } if (bank != rf_ini[i].rf_bank) { @@ -5336,12 +5331,12 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un obdb = 0; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 287, 0, true)) - return false; + ee->ee_ob[ee_mode][obdb], 3, 287, 0, true)) + return -EINVAL; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 290, 0, true)) - return false; + ee->ee_ob[ee_mode][obdb], 3, 290, 0, true)) + return -EINVAL; } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; @@ -5351,12 +5346,12 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un (channel->freq > 4000 ? 0 : -1))); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) - return false; + ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) + return -EINVAL; if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 282, 0, true)) - return false; + ee->ee_ob[ee_mode][obdb], 3, 282, 0, true)) + return -EINVAL; } #ifdef notyet @@ -5367,19 +5362,19 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un #endif if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], - ee->ee_xpd[ee_mode], 1, 302, 0, true)) - return false; + ee->ee_xpd[ee_mode], 1, 302, 0, true)) + return -EINVAL; /* Modify bank 7 */ if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 14, 0, true)) - return false; + ee->ee_i_gain[ee_mode], 6, 14, 0, true)) + return -EINVAL; /* Write RF values */ for (i = 0; i < rf_size; i++) ath5k_hw_reg_write(hal, rf[i], rf_ini[i].rf_register); - return true; + return 0; } /* @@ -5387,9 +5382,9 @@ ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, un * TODO: is this needed ? i mean 5211 has a 5111 RF * doesn't ar5k_rfregs work ? */ -void -ath5k_hw_ar5211_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int freq, - unsigned int ee_mode) +static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, + struct ieee80211_channel *channel, unsigned int freq, + unsigned int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; struct ath5k_ar5211_ini_rf rf[ARRAY_SIZE(ar5211_rf)]; @@ -5476,8 +5471,7 @@ ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) return true; } -enum ath5k_rfgain -ath5k_hw_get_rf_gain(struct ath_hw *hal) +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal) { u32 data, type; @@ -5502,18 +5496,18 @@ ath5k_hw_get_rf_gain(struct ath_hw *hal) if (hal->ah_radio == AR5K_RF5112) { ath5k_hw_rfregs_gainf_corr(hal); hal->ah_gain.g_current = - hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? - (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : + hal->ah_gain.g_current>=hal->ah_gain.g_f_corr ? + (hal->ah_gain.g_current-hal->ah_gain.g_f_corr) : 0; } if (ath5k_hw_rfregs_gain_readback(hal) && - AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && - ath5k_hw_rfregs_gain_adjust(hal)) + AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && + ath5k_hw_rfregs_gain_adjust(hal)) hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE; } - done: +done: return hal->ah_rf_gain; } commit b3c184a74e065df8b893d5bd7c67f6eb79b84374 Author: Jiri Slaby Date: Sun Jul 15 21:51:37 2007 +0200 don't ath_stop_hw at detach diff --git a/ath.c b/ath.c index e6c38a8..0898711 100644 --- a/ath.c +++ b/ath.c @@ -1767,7 +1767,6 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; - ath_stop_hw(sc); /* XXX needed? */ /* * NB: the order of these is important: * o call the 802.11 layer before detaching the hal to commit 369d62c54c3a2de5910182407f9134d3b07dacd0 Author: Jiri Slaby Date: Sun Jul 15 22:45:48 2007 +0200 debug stuff cleanup diff --git a/ath.c b/ath.c index 0898711..2b95442 100644 --- a/ath.c +++ b/ath.c @@ -42,10 +42,18 @@ #define ATH_DUMP_SKB 0 /* show skb contents */ #define AR_DEBUG 1 +#if AR_DEBUG #define DPRINTF(sc, _m, _fmt...) do { \ - if ((sc->debug & (_m)) && net_ratelimit()) \ - printk(_fmt); \ + if (((sc)->debug & (_m)) && net_ratelimit()) \ + printk(KERN_DEBUG _fmt); \ } while (0) +#else +static inline int __attribute__ ((format (printf, 3, 4))) +DPRINTF(struct ath_softc *sc, unsigned int m, const char *fmt, ...) +{ + return 0; +} +#endif enum { ATH_DEBUG_RESET = 0x00000020, /* reset processing */ ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ @@ -68,7 +76,7 @@ MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); module_param(xchanmode, int, 0); MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); -#ifdef AR_DEBUG +#if AR_DEBUG static unsigned int ath_debug; module_param_named(debug, ath_debug, uint, 0); #endif @@ -100,12 +108,12 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = { }; MODULE_DEVICE_TABLE(pci, ath_pci_id_table); -#ifdef AR_DEBUG +#if AR_DEBUG static void ath_printrxbuf(struct ath_buf *bf, int done) { struct ath_desc *ds = bf->desc; - printk("R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", + printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1], @@ -116,7 +124,8 @@ static void ath_printtxbuf(struct ath_buf *bf, int done) { struct ath_desc *ds = bf->desc; - printk("T (%p %llx) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", + printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x " + "%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], @@ -125,17 +134,10 @@ static void ath_printtxbuf(struct ath_buf *bf, int done) #endif #if ATH_DUMP_SKB -static void ath_dump_skb(struct sk_buff *skb, unsigned int rx) +static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) { - unsigned int a; - - printk(KERN_DEBUG "%c", rx ? 'r' : 't'); - for (a = 0; a < min(200U, skb->len) + 4; a++) { - printk("%.2x %s", skb->data[a], ((a+1) % 8) ? "" : " "); - if (!((a+1) % 16)) - printk("\n" KERN_DEBUG " "); - } - printk("\n"); + print_hex_dump_bytes(rx ? "r" : "t", DUMP_PREFIX_NONE, skb->data, + min(200U, skb->len)); } #else static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) {} @@ -589,8 +591,8 @@ static void ath_stoprecv(struct ath_softc *sc) ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ mdelay(3); /* 3ms is long enough for 1 frame */ -#ifdef AR_DEBUG - if (sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { // TODO: compiler warns integer overflow +#if AR_DEBUG + if (sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { struct ath_desc *ds; struct ath_buf *bf; int status; @@ -613,9 +615,6 @@ static void ath_stoprecv(struct ath_softc *sc) static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) { -#ifdef AR_DEBUG - struct ath_hw *ah = sc->ah; -#endif struct ath_buf *bf, *bf0; /* @@ -624,9 +623,10 @@ static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) */ spin_lock_bh(&txq->lock); list_for_each_entry_safe(bf, bf0, &txq->q, list) { -#ifdef AR_DEBUG +#if AR_DEBUG if (sc->debug & ATH_DEBUG_RESET) - ath_printtxbuf(bf, !ah->ah_proc_tx_desc(ah, bf->desc)); + ath_printtxbuf(bf, !sc->ah->ah_proc_tx_desc(sc->ah, + bf->desc)); #endif pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, PCI_DMA_TODEVICE); @@ -1890,7 +1890,9 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, * Mark the device as detached to avoid processing * interrupts until setup is complete. */ +#if AR_DEBUG sc->debug = ath_debug; +#endif sc->invalid = 1; sc->iobase = mem; sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ @@ -2029,7 +2031,7 @@ static int maxint = 0x7ffffff / 1000; #define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ static ctl_table ath_static_sysctls[] = { -#ifdef AR_DEBUG +#if AR_DEBUG { .ctl_name = CTL_AUTO, .procname = "debug", .mode = 0644, commit eeba043ed1230c2e427d50b01057c63836ba3a25 Author: Jiri Slaby Date: Mon Jul 16 08:35:17 2007 +0200 leds diff --git a/ath.c b/ath.c index 2b95442..77c5acc 100644 --- a/ath.c +++ b/ath.c @@ -60,10 +60,16 @@ enum { ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ ATH_DEBUG_INTR = 0x00001000, /* ISR */ ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ + ATH_DEBUG_LED = 0x00100000, /* led management */ ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ ATH_DEBUG_ANY = 0xffffffff }; +enum { + ATH_LED_TX, + ATH_LED_RX, +}; + static int ath_calinterval = ATH_SHORT_CALIB; static int countrycode = CTRY_DEFAULT; @@ -108,6 +114,8 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = { }; MODULE_DEVICE_TABLE(pci, ath_pci_id_table); +static void ath_led_event(struct ath_softc *, int); + #if AR_DEBUG static void ath_printrxbuf(struct ath_buf *bf, int done) { @@ -206,6 +214,8 @@ static void ath_tasklet_tx(unsigned long data) ath_tx_processq(sc, sc->txq); ieee80211_wake_queue(sc->hw, 0); + + ath_led_event(sc, ATH_LED_TX); } static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) @@ -408,6 +418,8 @@ accept: ath_dump_skb(skb, 1); __ieee80211_rx(sc->hw, skb, &rxs); + sc->led_rxrate = ds->ds_rxstat.rs_rate; + ath_led_event(sc, ATH_LED_RX); next: list_move_tail(&bf->list, &sc->rxbuf); } while (ath_rxbuf_init(sc, bf) == 0); @@ -700,12 +712,10 @@ static int ath_stop_locked(struct ath_softc *sc) ieee80211_stop_queues(sc->hw); if (!sc->invalid) { - if (sc->softled) { -#ifdef BLE - del_timer(&sc->ledtimer); - ath5k_hw_set_gpio(ah, sc->ledpin, !sc->ledon); - sc->blinking = 0; -#endif + if (sc->led_soft) { + del_timer_sync(&sc->led_tim); + ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); + sc->led_blinking = 0; } ath5k_hw_set_intr(ah, 0); } @@ -766,59 +776,63 @@ static int ath_stop_hw(struct ath_softc *sc) static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) { -#ifdef BLE - /* from Atheros NDIS driver, w/ permission */ - static const struct { - u16 rate; /* tx/rx 802.11 rate */ - u16 timeOn; /* LED on time (ms) */ - u16 timeOff; /* LED off time (ms) */ - } blinkrates[] = { - { 108, 40, 10 }, - { 96, 44, 11 }, - { 72, 50, 13 }, - { 48, 57, 14 }, - { 36, 67, 16 }, - { 24, 80, 20 }, - { 22, 100, 25 }, - { 18, 133, 34 }, - { 12, 160, 40 }, - { 10, 200, 50 }, - { 6, 240, 58 }, - { 4, 267, 66 }, - { 2, 400, 100 }, - { 0, 500, 130 } - }; -#endif - const struct ath5k_rate_table* rt=ath5k_hw_get_rate_table(sc->ah, mode); -// unsigned int i, j; - - BUG_ON(rt == NULL); -#ifdef BLE - memset(sc->hwmap, 0, sizeof(sc->hwmap)); - for (i = 0; i < 32; i++) { - u8 ix = rt->rate_code_to_index[i]; - if (ix == 0xff) { - sc->hwmap[i].ledon = msecs_to_jiffies(500); - sc->hwmap[i].ledoff = msecs_to_jiffies(130); - continue; + if (unlikely(sc->led_soft)) { + /* from Atheros NDIS driver, w/ permission */ + static const struct { + u16 rate; /* tx/rx 802.11 rate */ + u16 timeOn; /* LED on time (ms) */ + u16 timeOff; /* LED off time (ms) */ + } blinkrates[] = { + { 108, 40, 10 }, + { 96, 44, 11 }, + { 72, 50, 13 }, + { 48, 57, 14 }, + { 36, 67, 16 }, + { 24, 80, 20 }, + { 22, 100, 25 }, + { 18, 133, 34 }, + { 12, 160, 40 }, + { 10, 200, 50 }, + { 6, 240, 58 }, + { 4, 267, 66 }, + { 2, 400, 100 }, + { 0, 500, 130 } + }; + const struct ath5k_rate_table* rt = + ath5k_hw_get_rate_table(sc->ah, mode); + unsigned int i, j; + + BUG_ON(rt == NULL); + + memset(sc->hwmap, 0, sizeof(sc->hwmap)); + for (i = 0; i < 32; i++) { + u8 ix = rt->rate_code_to_index[i]; + if (ix == 0xff) { + sc->hwmap[i].ledon = msecs_to_jiffies(500); + sc->hwmap[i].ledoff = msecs_to_jiffies(130); + continue; + } + sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; + if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == + MODULATION_OFDM) + sc->hwmap[i].txflags |= + IEEE80211_RADIOTAP_F_SHORTPRE; + /* receive frames include FCS */ + sc->hwmap[i].rxflags = sc->hwmap[i].txflags | + IEEE80211_RADIOTAP_F_FCS; + /* setup blink rate table to avoid per-packet lookup */ + for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) + if (blinkrates[j].rate == /* XXX why 7f? */ + (rt->rates[ix].dot11_rate&0x7f)) + break; + + sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j]. + timeOn); + sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j]. + timeOff); } - sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; - if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == - MODULATION_OFDM) - sc->hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; - /* receive frames include FCS */ - sc->hwmap[i].rxflags = sc->hwmap[i].txflags | - IEEE80211_RADIOTAP_F_FCS; - /* setup blink rate table to avoid per-packet lookup */ - for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) - if (blinkrates[j].rate == /* XXX why 7f? */ - (rt->rates[ix].dot11_rate & 0x7f)) - break; - - sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].timeOn); - sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].timeOff); } -#endif + sc->curmode = mode; } @@ -953,6 +967,8 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, ath_dump_skb(skb, 0); + sc->led_txrate = ctl->tx_rate; + spin_lock_irqsave(&sc->txbuflock, flags); if (list_empty(&sc->txbuf)) { if (net_ratelimit()) @@ -1180,6 +1196,51 @@ static void ath_calibrate(unsigned long data) msecs_to_jiffies(ath_calinterval * 1000)); } +static void ath_led_off(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + if (sc->led_endblink) + sc->led_blinking = 0; + else { + sc->led_endblink = 0; + ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on); + mod_timer(&sc->led_tim, jiffies + sc->led_off); + } +} + +/* + * Blink the LED according to the specified on/off times. + */ +static void ath_led_blink(struct ath_softc *sc, unsigned int on, + unsigned int off) +{ + DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); + ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on); + sc->led_blinking = 1; + sc->led_endblink = 0; + sc->led_off = off; + mod_timer(&sc->led_tim, jiffies + on); +} + +static void ath_led_event(struct ath_softc *sc, int event) +{ + if (likely(!sc->led_soft)) + return; + if (unlikely(sc->led_blinking)) /* don't interrupt active blink */ + return; + switch (event) { + case ATH_LED_TX: + ath_led_blink(sc, sc->hwmap[sc->led_txrate].ledon, + sc->hwmap[sc->led_txrate].ledoff); + break; + case ATH_LED_RX: + ath_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon, + sc->hwmap[sc->led_rxrate].ledoff); + break; + } +} + static irqreturn_t ath_intr(int irq, void *dev_id) { struct ath_softc *sc = dev_id; @@ -1713,26 +1774,30 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); setup_timer(&sc->calib_tim, ath_calibrate, (unsigned long)sc); -#ifdef BLE - setup_timer(&sc->sc_ledtimer, ath_led_off, (unsigned long)sc); - - sc->blinking = 0; - sc->ledstate = 1; - sc->ledon = 0; /* low true */ - sc->ledidle = msecs_to_jiffies(2700); /* 2.7sec */ + setup_timer(&sc->led_tim, ath_led_off, (unsigned long)sc); + sc->led_blinking = 0; + sc->led_on = 0; /* low true */ /* * Auto-enable soft led processing for IBM cards and for * 5211 minipci cards. Users can also manually enable/disable * support with a sysctl. */ - sc->sc_softled = (devid == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || - devid == PCI_DEVICE_ID_ATHEROS_AR5211); - if (sc->sc_softled) { - ath5k_hw_set_gpio_output(ah, sc->sc_ledpin); - ath5k_hw_set_gpio(ah, sc->sc_ledpin, !sc->sc_ledon); + if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || + pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) { + sc->led_soft = 1; + sc->led_pin = 0; } - + /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */ + if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) { + sc->led_soft = 1; + sc->led_pin = 0; + } + if (sc->led_soft) { + ath5k_hw_set_gpio_output(ah, sc->led_pin); + ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); + } +#ifdef BLE sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); /* @@ -1963,8 +2028,8 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct ath_softc *sc = hw->priv; - if (sc->softled) - ath5k_hw_set_gpio(sc->ah, sc->ledpin, 1); + if (sc->led_soft) + ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); ath_stop_hw(sc); pci_save_state(pdev); @@ -1997,9 +2062,9 @@ static int ath_pci_resume(struct pci_dev *pdev) pci_write_config_byte(pdev, 0x41, 0); ath_init(sc); - if (sc->softled) { - ath5k_hw_set_gpio_output(sc->ah, sc->ledpin); - ath5k_hw_set_gpio(sc->ah, sc->ledpin, 0); + if (sc->led_soft) { + ath5k_hw_set_gpio_output(sc->ah, sc->led_pin); + ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0); } return 0; diff --git a/ath.h b/ath.h index 25393f7..61019ad 100644 --- a/ath.h +++ b/ath.h @@ -148,7 +148,6 @@ struct ath_softc { #endif unsigned int invalid : 1, /* disable hardware accesses */ mrretry : 1, /* multi-rate retry support */ - softled : 1, /* enable LED gpio status */ xxx:1; #ifdef BLE sc_splitmic: 1, /* split TKIP MIC keys */ @@ -156,9 +155,6 @@ struct ath_softc { sc_diversity : 1,/* enable rx diversity */ sc_lockslottime : 1,/* lock slot time value */ sc_hasveol : 1, /* tx VEOL support */ - sc_ledstate: 1, /* LED on/off state */ - sc_blinking: 1, /* LED blink operation active */ - sc_endblink: 1, /* finish LED blink operation */ sc_mcastkey: 1, /* mcast key cache search */ sc_hasclrkey:1; /* CLR key supported */ /* rate tables */ @@ -170,15 +166,14 @@ struct ath_softc { #ifdef BLE u16 sc_curtxpow; /* current tx power limit */ u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ - +#endif struct { -// int ieeerate; /* IEEE rate */ u8 rxflags; /* radiotap rx flags */ u8 txflags; /* radiotap tx flags */ u16 ledon; /* softled on time */ u16 ledoff; /* softled off time */ } hwmap[32]; /* h/w rate ix mappings */ - +#ifdef BLE u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ #endif @@ -187,16 +182,17 @@ struct ath_softc { DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ u8 bssidmask[ETH_ALEN]; - unsigned int ledpin; /* GPIO pin for driving LED */ -#ifdef BLE - u_int sc_ledon; /* pin setting for LED on */ - u_int sc_ledidle; /* idle polling interval */ - int sc_ledevent; /* time of last LED event */ - u8 sc_rxrate; /* current rx rate for LED */ - u8 sc_txrate; /* current tx rate for LED */ - u16 sc_ledoff; /* off time for current blink */ - struct timer_list sc_ledtimer; /* led off timer */ + unsigned int led_pin, /* GPIO pin for driving LED */ + led_on, /* pin setting for LED on */ + led_off, /* off time for current blink */ + led_blinking: 1,/* LED blink operation active */ + led_endblink: 1,/* finish LED blink operation */ + led_soft: 1; /* enable LED gpio status */ + struct timer_list led_tim; /* led off timer */ + u8 led_rxrate; /* current rx rate for LED */ + u8 led_txrate; /* current tx rate for LED */ +#ifdef BLE union { struct ath_tx_radiotap_header th; u8 pad[64]; diff --git a/ath/if_ath.c b/ath/if_ath.c index 264724f..960e48a 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -2,12 +2,6 @@ #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) -enum { - ATH_LED_TX, - ATH_LED_RX, - ATH_LED_POLL, -}; - static const char *hal_status_desc[] = { "Everything went O.K.", "Unable to allocate memory for ath_hal", @@ -3543,66 +3537,7 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) ath_setup_stationkey(ni); } } -#endif -/* - * Turn the LED off: flip the pin and then set a timer so no - * update will happen for the specified duration. - */ -static void -ath_led_off(unsigned long arg) -{ - struct ath_softc *sc = (struct ath_softc *) arg; - - if(sc->sc_endblink == 1){ - /* part of ath_led_done() */ - sc->sc_blinking = 0; - } else{ - ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); - sc->sc_endblink = 1; - mod_timer(&sc->sc_ledtimer, jiffies + sc->sc_ledoff); - } -} -#ifdef BLE -/* - * Blink the LED according to the specified on/off times. - */ -static void -ath_led_blink(struct ath_softc *sc, int on, int off) -{ - DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); - ath5k_hw_set_gpio(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); - sc->sc_blinking = 1; - sc->sc_endblink = 0; - sc->sc_ledoff = off; - mod_timer(&sc->sc_ledtimer, jiffies + on); -} - -static void -ath_led_event(struct ath_softc *sc, int event) -{ - - sc->sc_ledevent = jiffies; /* time of last event */ - if (sc->sc_blinking) /* don't interrupt active blink */ - return; - switch (event) { - case ATH_LED_POLL: - ath_led_blink(sc, sc->sc_hwmap[0].ledon, - sc->sc_hwmap[0].ledoff); - break; - case ATH_LED_TX: - ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, - sc->sc_hwmap[sc->sc_txrate].ledoff); - break; - case ATH_LED_RX: - ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, - sc->sc_hwmap[sc->sc_rxrate].ledoff); - break; - } -} -#endif - -#ifdef BLE static int ath_rawdev_attach(struct ath_softc *sc) { commit 91203cbfafc7eb3d4baec9cb50d12bb396a18a78 Author: Jiri Slaby Date: Mon Jul 16 08:41:21 2007 +0200 remove further unneeded stuff from old ath/if_ath.c diff --git a/ath/if_ath.c b/ath/if_ath.c index 960e48a..57f48ac 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -2,19 +2,6 @@ #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) -static const char *hal_status_desc[] = { - "Everything went O.K.", - "Unable to allocate memory for ath_hal", - "Hardware I/O Error", - "Unable to access EEPROM", - "Invalid EEPROM checksum", - "Unable to get device caps from EEPROM", - "Unable to read MAC address from EEPROM", - "Invalid parameter to function", - "Hardware revision not supported", - "Unexpected error ocured during process" -}; - static int ath_dwelltime = 200; /* 5 channels/second */ static int ath_calinterval = 30; /* calibrate every 30 secs */ static int ath_countrycode = CTRY_DEFAULT; /* country code */ @@ -38,18 +25,6 @@ static void ath_printrxbuf(struct ath_buf *bf, int); #define KEYPRINTF(sc, k, ix, mac) #endif -static int countrycode = -1; -static int outdoor = -1; -static int xchanmode = -1; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,52)) -MODULE_PARM(countrycode, "i"); -MODULE_PARM(outdoor, "i"); -MODULE_PARM(xchanmode, "i"); -#else -module_param(countrycode, int, 0); -module_param(outdoor, int, 0); -module_param(xchanmode, int, 0); -#endif MODULE_PARM_DESC(countrycode, "Override default country code"); MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); @@ -105,15 +80,6 @@ struct wlan_ng_prism2_header { }; static void -ath_fatal_tasklet(unsigned long data) -{ - struct ieee80211_hw *hw = (void *)data; - - printk(KERN_ERR "hardware error; resetting\n"); - ath_reset(hw); -} - -static void ath_radar_tasklet(unsigned long data) { struct ieee80211_hw *hw = (void *)data; @@ -260,522 +226,6 @@ static u_int8_t *rt_el_offset(struct ieee80211_radiotap_header *th, u_int32_t el return offset; } -/* - * ath_start for raw 802.11 packets. - */ -static int -ath_start_raw(struct sk_buff *skb, struct net_device *dev) -{ -#define CTS_DURATION \ - ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, true) -/*#define updateCTSForBursting(_ah, _ds, _txq) \ - ath_hal_updateCTSForBursting(_ah, _ds, \ - _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ - _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \ - txopLimit, CTS_DURATION)*/ - struct ath_softc *sc = dev->priv; -// struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah = sc->sc_ah; -// const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; - struct ath_txq *txq; - struct ath_buf *bf; - AR5K_PKT_TYPE atype; - int pktlen, hdrlen, try0, pri, dot11_rate, txpower; - u_int8_t ctsrate, ctsduration, txrate; -// u_int8_t cix = 0xff; /* NB: silence compiler */ - u_int flags = 0; - struct ieee80211_frame *wh; - struct ath_desc *ds; - const struct ath5k_rate_table *rt; - uint8_t testmac[ETH_ALEN]; - - if ((sc->sc_dev.flags & IFF_RUNNING) == 0 || sc->sc_invalid) { - /* device is not up... silently discard packet */ - dev_kfree_skb(skb); - return 0; - } - - /* - * Grab a TX buffer and associated resources. - */ - ATH_TXBUF_LOCK_BH(sc); - bf = STAILQ_FIRST(&sc->sc_txbuf); - if (bf != NULL) - STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); - /* XXX use a counter and leave at least one for mgmt frames */ - if (STAILQ_EMPTY(&sc->sc_txbuf)) { - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); - sc->sc_stats.ast_tx_qstop++; - netif_stop_queue(&sc->sc_dev); - netif_stop_queue(&sc->sc_rawdev); - } - ATH_TXBUF_UNLOCK_BH(sc); - - if (bf == NULL) { /* NB: should not happen */ - DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", - __func__); - sc->sc_stats.ast_tx_nobuf++; - dev_kfree_skb(skb); - return 0; - } - - rt = sc->sc_currates; - KASSERT(rt != NULL, "no rate table, mode %u", sc->sc_curmode); - flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; - try0 = ATH_TXMAXTRY; - dot11_rate = 0; - ctsrate = 0; - ctsduration = 0; - pri = 0; - txpower = 60; - txq = sc->sc_ac2q[pri]; - txrate = rt->rates[0].rate_code; - atype = AR5K_PKT_TYPE_NORMAL; - - /* - * strip any physical layer header off the skb, if it is - * present, and read out any settings we can, like what txrate - * to send this packet at. - */ - switch(dev->type) { - case ARPHRD_IEEE80211: - break; - case ARPHRD_IEEE80211_PRISM: { - wlan_ng_prism2_header *ph = NULL; - ph = (wlan_ng_prism2_header *) skb->data; - /* does it look like there is a prism header here? */ - if (skb->len > sizeof (wlan_ng_prism2_header) && - ph->msgcode == DIDmsg_lnxind_wlansniffrm && - ph->rate.did == DIDmsg_lnxind_wlansniffrm_rate) { - dot11_rate = ph->rate.data; - skb_pull(skb, sizeof(wlan_ng_prism2_header)); - } - break; - } - case ARPHRD_IEEE80211_RADIOTAP: { - struct ieee80211_radiotap_header *th = (struct ieee80211_radiotap_header *) skb->data; - if (rt_check_header(th, skb->len)) { - if (rt_el_present(th, IEEE80211_RADIOTAP_RATE)) { - dot11_rate = *((u_int8_t *) rt_el_offset(th, - IEEE80211_RADIOTAP_RATE)); - } - if (rt_el_present(th, IEEE80211_RADIOTAP_DATA_RETRIES)) { - try0 = 1 + *((u_int8_t *) rt_el_offset(th, - IEEE80211_RADIOTAP_DATA_RETRIES)); - } - if (rt_el_present(th, IEEE80211_RADIOTAP_DBM_TX_POWER)) { - txpower = *((u_int8_t *) rt_el_offset(th, - IEEE80211_RADIOTAP_DBM_TX_POWER)); - if (txpower > 60) - txpower = 60; - - } - - skb_pull(skb, le16_to_cpu(th->it_len)); - } - break; - } - default: - /* nothing */ - break; - } - - if (dot11_rate != 0) { - int index = sc->sc_rixmap[dot11_rate & IEEE80211_RATE_VAL]; - if (index >= 0 && index < rt->rate_count) { - txrate = rt->rates[index].rate_code; - } - } - - wh = (struct ieee80211_frame *) skb->data; - pktlen = skb->len + IEEE80211_CRC_LEN; - hdrlen = sizeof(struct ieee80211_frame); - - if (hdrlen < pktlen) - hdrlen = pktlen; - - if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { - flags |= AR5K_TXDESC_NOACK; /* no ack on broad/multicast */ - sc->sc_stats.ast_tx_noack++; - } - - testmac[0] = 0x41; /* A */ - testmac[1] = 0x54; /* T */ - testmac[2] = 0x48; /* H */ - testmac[3] = 0x54; /* T */ - testmac[4] = 0x53; /* S */ - testmac[5] = 0x54; /* T */ - - if (IEEE80211_ADDR_EQ(wh->i_addr1, testmac)) { - flags |= AR5K_TXDESC_NOACK; /* no ack for test packets */ - sc->sc_stats.ast_tx_noack++; - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: output testpacket (len %i)\n", - __func__, skb->len); - } - - if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) - ieee80211_dump_pkt(skb->data, skb->len, - sc->sc_hwmap[txrate].ieeerate, -1); - - /* - * Load the DMA map so any coalescing is done. This - * also calculates the number of descriptors we need. - */ - bf->bf_skbaddr = bus_map_single(sc->sc_bdev, - skb->data, pktlen, BUS_DMA_TODEVICE); - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: skb %p [data %p len %u] skbaddr %lx\n", - __func__, skb, skb->data, skb->len, (long unsigned int) bf->bf_skbaddr); - if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { - if_printf(dev, "%s: DMA mapping failed\n", __func__); - dev_kfree_skb(skb); - bf->bf_skb = NULL; - sc->sc_stats.ast_tx_busdma++; - - ATH_TXBUF_LOCK_BH(sc); - STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); - ATH_TXBUF_UNLOCK_BH(sc); - return -EIO; - } - bf->bf_skb = skb; - bf->bf_node = NULL; - - /* setup descriptors */ - ds = bf->bf_desc; - rt = sc->sc_currates; - KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); - - /* - * Formulate first tx descriptor with tx controls. - */ - /* XXX check return value? */ - ah->ah_setup_tx_desc(ah, ds - , pktlen /* packet length */ - , hdrlen /* header length */ - , atype /* Atheros packet type */ - , txpower /* txpower */ - , txrate, try0 /* series 0 rate/tries */ - , AR5K_TXKEYIX_INVALID /* key cache index */ - , sc->sc_txantenna /* antenna mode */ - , flags /* flags */ - , ctsrate /* rts/cts rate */ - , ctsduration /* rts/cts duration */ - ); - - /* - * Fillin the remainder of the descriptor info. - */ - ds->ds_link = 0; - ds->ds_data = bf->bf_skbaddr; - ah->ah_fill_tx_desc(ah, ds - , skb->len /* segment length */ - , true /* first segment */ - , true /* last segment */ - , ds /* first descriptor */ - ); - - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: Q%d: %08x %08x %08x %08x %08x %08x\n", - __func__, txq->axq_qnum, ds->ds_link, ds->ds_data, - ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); - /* - * Insert the frame on the outbound list and - * pass it on to the hardware. - */ - ATH_TXQ_LOCK_BH(txq); -// if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { -// u_int32_t txopLimit = IEEE80211_TXOP_TO_US( -// cap->cap_wmeParams[pri].wmep_txopLimit); - /* - * When bursting, potentially extend the CTS duration - * of a previously queued frame to cover this frame - * and not exceed the txopLimit. If that can be done - * then disable RTS/CTS on this frame since it's now - * covered (burst extension). Otherwise we must terminate - * the burst before this frame goes out so as not to - * violate the WME parameters. All this is complicated - * as we need to update the state of packets on the - * (live) hardware queue. The logic is buried in the hal - * because it's highly chip-specific. - */ -// if (txopLimit != 0) { -// sc->sc_stats.ast_tx_ctsburst++; -// if (updateCTSForBursting(ah, ds, txq) == 0) { - /* - * This frame was not covered by RTS/CTS from - * the previous frame in the burst; update the - * descriptor pointers so this frame is now - * treated as the last frame for extending a - * burst. - */ -// txq->axq_lastdsWithCTS = ds; - /* set gating Desc to final desc */ -// txq->axq_gatingds = -// (struct ath_desc *)txq->axq_link; -// } else -// sc->sc_stats.ast_tx_ctsext++; -// } -// } - ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); - DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: txq depth = %d\n", - __func__, txq->axq_depth); - if (txq->axq_link == NULL) { - ath5k_hw_put_tx_buf(ah, txq->axq_qnum, bf->bf_daddr); - DPRINTF(sc, ATH_DEBUG_XMIT, - "%s: TXDP[%u] = %llx (%p) depth %d\n", __func__, - txq->axq_qnum, (unsigned long long)bf->bf_daddr, - bf->bf_desc, txq->axq_depth); - } else { - *txq->axq_link = bf->bf_daddr; - DPRINTF(sc, ATH_DEBUG_XMIT, - "%s: link[%u](%p)=%llx (%p) depth %d\n", __func__, - txq->axq_qnum, txq->axq_link, - (unsigned long long)bf->bf_daddr, bf->bf_desc, - txq->axq_depth); - } - txq->axq_link = &bf->bf_desc->ds_link; - /* - * The CAB queue is started from the SWBA handler since - * frames only go out on DTIM and to avoid possible races. - */ - if (txq != sc->sc_cabq) - ath5k_hw_tx_start(ah, txq->axq_qnum); - ATH_TXQ_UNLOCK_BH(txq); - - sc->sc_devstats.tx_packets++; - sc->sc_devstats.tx_bytes += skb->len; - sc->sc_dev.trans_start = jiffies; - sc->sc_rawdev.trans_start = jiffies; - - return 0; -//#undef updateCTSForBursting -#undef CTS_DURATION -} - -static int -ath_start(struct sk_buff *skb, struct net_device *dev) -{ -#define CLEANUP() \ - do{ \ - ATH_TXBUF_LOCK_BH(sc); \ - STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); \ - ATH_TXBUF_UNLOCK_BH(sc); \ - if (ni != NULL) \ - ieee80211_free_node(ni); \ - } while (0) - - struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; - struct ieee80211com *ic = &sc->sc_ic; - struct ieee80211_node *ni; - struct ath_buf *bf; - struct ieee80211_cb *cb; - struct sk_buff *skb0; - struct ieee80211_frame *wh; - struct ether_header *eh; - - int ret = 0; - int counter = 0; - - if ((dev->flags & IFF_RUNNING) == 0 || sc->sc_invalid) { - DPRINTF(sc, ATH_DEBUG_XMIT, - "%s: discard, invalid %d flags %x\n", - __func__, sc->sc_invalid, dev->flags); - sc->sc_stats.ast_tx_invalid++; - return -ENETDOWN; - } - - for (;;) { - /* - * Grab a TX buffer and associated resources. - */ - ATH_TXBUF_LOCK_BH(sc); - bf = STAILQ_FIRST(&sc->sc_txbuf); - if (bf != NULL) - STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); - /* XXX use a counter and leave at least one for mgmt frames */ - if (STAILQ_EMPTY(&sc->sc_txbuf)) { - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); - sc->sc_stats.ast_tx_qstop++; - netif_stop_queue(dev); - if (sc->sc_rawdev_enabled) - netif_stop_queue(&sc->sc_rawdev); - } - ATH_TXBUF_UNLOCK_BH(sc); - - if (bf == NULL) { /* NB: should not happen */ - DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", - __func__); - sc->sc_stats.ast_tx_nobuf++; - break; - } - - /* - * Poll the management queue for frames; they - * have priority over normal data frames. - */ - IF_DEQUEUE(&ic->ic_mgtq, skb0); - - if (skb0 == NULL) { - /* - * data frames - */ - if (counter++ > 200) - DPRINTF(sc, ATH_DEBUG_FATAL, "%s (%s): endlessloop (data) (counter=%i)\n", __func__, dev->name, counter); - - if (!skb) { /* NB: no data (called for mgmt) */ - ATH_TXBUF_LOCK_BH(sc); - STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); - ATH_TXBUF_UNLOCK_BH(sc); - break; - } - /* - * No data frames go out unless we're associated; this - * should not happen as the 802.11 layer does not enable - * the xmit queue until we enter the RUN state. - */ - if (ic->ic_state != IEEE80211_S_RUN) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: ignore data packet, state %u\n", - __func__, ic->ic_state); - sc->sc_stats.ast_tx_discard++; - ATH_TXBUF_LOCK_BH(sc); - STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); - ATH_TXBUF_UNLOCK_BH(sc); - break; - } - /* - * Find the node for the destination so we can do - * things like power save and fast frames aggregation. - */ - if (skb->len < sizeof(struct ether_header)) { - ic->ic_stats.is_tx_nobuf++; /* XXX */ - ni = NULL; - - ret = 0; /* error return */ - CLEANUP(); - break; - } - eh = (struct ether_header *)skb->data; - ni = ieee80211_find_txnode(ic, eh->ether_dhost); - if (ni == NULL) { - /* NB: ieee80211_find_txnode does stat+msg */ - - ret = 0; /* error return */ - CLEANUP(); - break; - } - cb = (struct ieee80211_cb *)skb->cb; - if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && - (cb->flags & M_PWR_SAV) == 0) { - /* - * Station in power save mode; pass the frame - * to the 802.11 layer and continue. We'll get - * the frame back when the time is right. - */ - ieee80211_pwrsave(ic, ni, skb); - /* don't free this on function exit point */ - skb = NULL; - CLEANUP(); - break; - } - /* calculate priority so we can find the tx queue */ - if (ieee80211_classify(ic, skb, ni)) { - DPRINTF(sc, ATH_DEBUG_XMIT, - "%s: discard, classification failure\n", - __func__); - - ret = 0; /* error return */ - CLEANUP(); - break; - } - sc->sc_devstats.tx_packets++; - sc->sc_devstats.tx_bytes += skb->len; - - /* - * Encapsulate the packet for transmission. - */ - skb = ieee80211_encap(ic, skb, ni); - if (skb == NULL) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: encapsulation failure\n", - __func__); - sc->sc_stats.ast_tx_encap++; - - ret = 0; /* error return */ - CLEANUP(); - break; - } - - /* - * using unified sk_buff for transmit data and management frames - */ - skb0 = skb; - } else { - /* - * management frames - */ - cb = (struct ieee80211_cb *)skb0->cb; - ni = cb->ni; - - if (counter++ > 200) - DPRINTF(sc, ATH_DEBUG_FATAL, "%s (%s): endlessloop (mgnt) (counter=%i)\n", __func__, dev->name, counter); - - wh = (struct ieee80211_frame *) skb0->data; - if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == - IEEE80211_FC0_SUBTYPE_PROBE_RESP) { - /* fill time stamp */ - u_int64_t tsf; - __le32 *tstamp; - - tsf = ath5k_hw_get_tsf64(ah); - /* XXX: adjust 100us delay to xmit */ - tsf += 100; - tstamp = (__le32 *)&wh[1]; - tstamp[0] = htole32(tsf & 0xffffffff); - tstamp[1] = htole32(tsf >> 32); - } - sc->sc_stats.ast_tx_mgmt++; - } - - if (ath_tx_start(dev, ni, bf, skb0)) { - ret = 0; /* TODO: error value */ - skb = NULL; /* ath_tx_start() already freed this */ - CLEANUP(); - continue; - } - /* - * the data frame is last - */ - if (skb0 == skb) { - skb = NULL; /* will be released by tx_processq */ - break; - } - sc->sc_tx_timer = 5; - mod_timer(&ic->ic_slowtimo, jiffies + HZ); - } - if (skb) - dev_kfree_skb(skb); - return ret; /* NB: return !0 only in a ``hard error condition'' */ -#undef CLEANUP -} - -static int -ath_media_change(struct net_device *dev) -{ -#define IS_UP(dev) \ - ((dev->flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) - int error; - - error = ieee80211_media_change(dev); - if (error == ENETRESET) { - if (IS_UP(dev)) - error = ath_init(dev); - else - error = 0; - } - return error; -#undef IS_UP -} - #ifdef AR_DEBUG static void ath_keyprint(const char *tag, u_int ix, @@ -1110,20 +560,6 @@ ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) } /* - * Set the key cache contents for the specified key. Key cache - * slot(s) must already have been allocated by ath_key_alloc. - */ -static int -ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, - const u_int8_t mac[IEEE80211_ADDR_LEN]) -{ - struct net_device *dev = ic->ic_dev; - struct ath_softc *sc = dev->priv; - - return ath_keyset(sc, k, mac, ic->ic_bss); -} - -/* * Block/unblock tx+rx processing while a key change is done. * We assume the caller serializes key management operations * so we only need to worry about synchronization with other @@ -1768,71 +1204,7 @@ ath_beacon_config(struct ath_softc *sc) } #undef TSF_TO_TU } -#endif - -#ifdef BLE -static struct ieee80211_node * -ath_node_alloc(struct ieee80211_node_table *nt) -{ - struct ieee80211com *ic = nt->nt_ic; - struct ath_softc *sc = ic->ic_dev->priv; - const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; - struct ath_node *an; - an = kmalloc(space, GFP_ATOMIC); - if (an == NULL) { - /* XXX stat+msg */ - return NULL; - } - memset(an, 0, space); - an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; - an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; - an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; - an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; - ath_rate_node_init(sc, an); - - DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); - return &an->an_node; -} - -static void -ath_node_free(struct ieee80211_node *ni) -{ - struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_dev->priv; - DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); -/* - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) // TODO: seems we need this still - if (ATH_TXQ_SETUP(sc, i)) - ath_tx_cleanq(&sc->sc_txq[i], ni); -*/ - ath_rate_node_cleanup(sc, ATH_NODE(ni)); - sc->sc_node_free(ni); -} - -static u_int8_t -ath_node_getrssi(const struct ieee80211_node *ni) -{ -#define AR5K_EP_RND(x, mul) \ - ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) - u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; - int32_t rssi; - - /* - * When only one frame is received there will be no state in - * avgrssi so fallback on the value recorded by the 802.11 layer. - */ - if (avgrssi != ATH_RSSI_DUMMY_MARKER) - rssi = AR5K_EP_RND(avgrssi, AR5K_RSSI_EP_MULTIPLIER); - else - rssi = ni->ni_rssi; - /* NB: theoretically we shouldn't need this, but be paranoid */ - return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; -#undef AR5K_EP_RND -} -#endif - -#ifdef BLE /* * Add additional headers to a transmitted frame and netif_rx it on * a monitor or raw device @@ -2236,365 +1608,8 @@ ath_setdefantenna(struct ath_softc *sc, u_int antenna) sc->sc_rxotherant = 0; } -static void -ath_rx_tasklet(unsigned long data) -{ -#define PA2DESC(_sc, _pa) \ - ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ - ((_pa) - (_sc)->sc_desc_daddr))) - struct net_device *dev = (struct net_device *)data; - struct ath_buf *bf; - struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; - struct ath_desc *ds; - struct sk_buff *skb; -// struct ath_node *an; - int len;//, type; - u_int phyerr; - enum ath5k_status status; - - DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s\n", __func__); - do { -// bf = STAILQ_FIRST(&sc->sc_rxbuf); - bf = NULL; - if (bf == NULL) { /* XXX ??? can this happen */ - printk(KERN_ERR "%s: no buffer!\n", __func__); - break; - } - ds = bf->bf_desc; - if (ds->ds_link == bf->bf_daddr) { - /* NB: never process the self-linked entry at the end */ - break; - } - skb = bf->bf_skb; - if (skb == NULL) { /* XXX ??? can this happen */ - printk(KERN_ERR "%s: no skbuff!\n", __func__); - continue; - } - /* XXX sync descriptor memory */ - /* - * Must provide the virtual address of the current - * descriptor, the physical address, and the virtual - * address of the next descriptor in the h/w chain. - * This allows the HAL to look ahead to see if the - * hardware is done with a descriptor by checking the - * done bit in the following descriptor and the address - * of the current descriptor the DMA engine is working - * on. All this is necessary because of our use of - * a self-linked list to avoid rx overruns. - */ - status = ah->ah_proc_rx_desc(ah, ds, - bf->bf_daddr, PA2DESC(sc, ds->ds_link)); -#ifdef AR_DEBUG - if (sc->sc_debug & ATH_DEBUG_RECV_DESC) - ath_printrxbuf(bf, status == AR5K_OK); -#endif - if (status == AR5K_EINPROGRESS) - break; -// STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); - if (ds->ds_rxstat.rs_more) { - /* - * Frame spans multiple descriptors; this - * cannot happen yet as we don't support - * jumbograms. If not in monitor mode, - * discard the frame. - */ -#ifndef ERROR_FRAMES - /* - * Enable this if you want to see - * error frames in Monitor mode. - */ - if (sc->sc_opmode != IEEE80211_IF_TYPE_MNTR) { - sc->sc_stats.ast_rx_toobig++; - goto rx_next; - } -#endif - /* fall thru for monitor mode handling... */ - } else if (ds->ds_rxstat.rs_status != 0) { - if (ds->ds_rxstat.rs_status & AR5K_RXERR_CRC) - sc->sc_stats.ast_rx_crcerr++; - if (ds->ds_rxstat.rs_status & AR5K_RXERR_FIFO) - sc->sc_stats.ast_rx_fifoerr++; - if (ds->ds_rxstat.rs_status & AR5K_RXERR_PHY) { - sc->sc_stats.ast_rx_phyerr++; - phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; - sc->sc_stats.ast_rx_phy[phyerr]++; -/* - if (phyerr == AR5K_PHYERR_RADAR && ic->ic_opmode == IEEE80211_M_HOSTAP) - { - tasklet_schedule(&sc->sc_radartq); - } -*/ - goto rx_next; - } - if (ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) { - /* - * Decrypt error. If the error occurred - * because there was no hardware key, then - * let the frame through so the upper layers - * can process it. This is necessary for 5210 - * parts which have no way to setup a ``clear'' - * key cache entry. - * - * XXX do key cache faulting - */ - if (ds->ds_rxstat.rs_keyix == AR5K_RXKEYIX_INVALID) - goto rx_accept; - sc->sc_stats.ast_rx_badcrypt++; - } - if (ds->ds_rxstat.rs_status & AR5K_RXERR_MIC) { - sc->sc_stats.ast_rx_badmic++; - /* - * Do minimal work required to hand off - * the 802.11 header for notifcation. - */ - /* XXX frag's and qos frames */ -#ifdef BLE - len = ds->ds_rxstat.rs_datalen; - if (len >= sizeof (struct ieee80211_frame)) { - bus_dma_sync_single(sc->sc_bdev, - bf->bf_skbaddr, len, - BUS_DMA_FROMDEVICE); - ieee80211_notify_michael_failure(ic, - (struct ieee80211_frame *) skb->data, - sc->sc_splitmic ? - ds->ds_rxstat.rs_keyix-32 : - ds->ds_rxstat.rs_keyix - ); - } -#endif - } - - // TODO: correct? -// ic->ic_devstats->rx_errors++; - - /* - * accept error frames on the raw device - * or in monitor mode if we ask for them. - * we'll explicity drop them after capture. - */ - if (sc->sc_rxfilter & AR5K_RX_FILTER_PHYERROR) - goto rx_accept; - - /* - * Reject error frames, we normally don't want - * to see them in monitor mode (in monitor mode - * allow through packets that have crypto problems). - */ - if ((ds->ds_rxstat.rs_status &~ - (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || - sc->sc_opmode != IEEE80211_IF_TYPE_MNTR) - goto rx_next; - } -rx_accept: - /* - * Sync and unmap the frame. At this point we're - * committed to passing the sk_buff somewhere so - * clear buf_skb; this means a new sk_buff must be - * allocated when the rx descriptor is setup again - * to receive another frame. - */ - len = ds->ds_rxstat.rs_datalen; - bus_dma_sync_single(sc->sc_bdev, - bf->bf_skbaddr, len, BUS_DMA_FROMDEVICE); - bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr, - sc->sc_rxbufsize, BUS_DMA_FROMDEVICE); - bf->bf_skb = NULL; - - sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; -#ifdef BLE - if (len < IEEE80211_ACK_LEN) { - DPRINTF(sc, ATH_DEBUG_RECV, - "%s: runt packet %d\n", __func__, len); - sc->sc_stats.ast_rx_tooshort++; - dev_kfree_skb(skb); - goto rx_next; - } -#endif - KASSERT(len <= skb_tailroom(skb), "not enough tailroom " - "(%d vs %d)", len, skb_tailroom(skb)); - - skb_put(skb, len); - skb->protocol = __constant_htons(ETH_P_CONTROL); -#ifdef BLE - if (sc->sc_rawdev_enabled && - (sc->sc_rawdev.flags & IFF_UP)) { - struct sk_buff *skb2; - skb2 = skb_copy(skb, GFP_ATOMIC); - if (skb2) { - ath_rx_capture(&sc->sc_rawdev, ds, skb2); - } - } -#endif - if (sc->sc_opmode == IEEE80211_IF_TYPE_MNTR) { - /* - * Monitor mode: discard anything shorter than - * an ack or cts, clean the skbuff, fabricate - * the Prism header existing tools expect, - * and dispatch. - */ - /* XXX TSF */ - - ath_rx_capture(dev, ds, skb); - goto rx_next; - } - - - /* - * At this point we have no need for error frames - * that aren't crypto problems since we're done - * with capture. - */ - if (ds->ds_rxstat.rs_status &~ - (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) { - dev_kfree_skb(skb); - goto rx_next; - } - /* - * From this point on we assume the frame is at least - * as large as ieee80211_frame_min; verify that. - */ -#ifdef BLE - if (len < IEEE80211_MIN_LEN) { - DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", - __func__, len); - sc->sc_stats.ast_rx_tooshort++; - dev_kfree_skb(skb); - goto rx_next; - } - - /* - * Normal receive. - */ - if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { - ieee80211_dump_pkt(skb->data, len, - sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, - ds->ds_rxstat.rs_rssi); - } - - skb_trim(skb, skb->len - IEEE80211_CRC_LEN); - - /* - * Locate the node for sender, track state, and then - * pass the (referenced) node up to the 802.11 layer - * for its use. If the sender is unknown spam the - * frame; it'll be dropped where it's not wanted. - */ - if (ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID && - (ni = sc->sc_keyixmap[ds->ds_rxstat.rs_keyix]) != NULL) { - /* - * Fast path: node is present in the key map; - * grab a reference for processing the frame. - */ - DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: node %s in keymap\n", - __func__, ether_sprintf(ni->ni_macaddr)); - - an = ATH_NODE(ieee80211_ref_node(ni)); - ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); - type = ieee80211_input(ic, skb, ni, - ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); - } else { - /* - * Locate the node for sender, track state, and then - * pass the (referenced) node up to the 802.11 layer - * for its use. - */ - ni = ieee80211_find_rxnode(ic, - (struct ieee80211_frame_min *)skb->data); - /* - * Track rx rssi and do any rx antenna management. - */ - an = ATH_NODE(ni); - ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); - /* - * Send frame up for processing. - */ - type = ieee80211_input(ic, skb, ni, - ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); - if (ni != ic->ic_bss) { - u_int16_t keyix; - /* - * If the station has a key cache slot assigned - * update the key->node mapping table. - */ - keyix = ni->ni_ucastkey.wk_keyix; - if (keyix != IEEE80211_KEYIX_NONE && - sc->sc_keyixmap[keyix] == NULL) - sc->sc_keyixmap[keyix] = - ieee80211_ref_node(ni); - } - } - ieee80211_free_node(ni); - if (sc->sc_diversity) { - /* - * When using fast diversity, change the default rx - * antenna if diversity chooses the other antenna 3 - * times in a row. - */ - if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { - if (++sc->sc_rxotherant >= 3) - ath_setdefantenna(sc, - ds->ds_rxstat.rs_antenna); - } else - sc->sc_rxotherant = 0; - } - - if (sc->sc_softled) { - /* - * Blink for any data frame. Otherwise do a - * heartbeat-style blink when idle. The latter - * is mainly for station mode where we depend on - * periodic beacon frames to trigger the poll event. - */ - if (type == IEEE80211_FC0_TYPE_DATA) { - sc->sc_rxrate = ds->ds_rxstat.rs_rate; - ath_led_event(sc, ATH_LED_RX); - } else if (jiffies - sc->sc_ledevent >= sc->sc_ledidle) - ath_led_event(sc, ATH_LED_POLL); - } -#endif -rx_next: -// STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); - ; - } while (ath_rxbuf_init(sc, bf) == 0); - - /* rx signal state monitoring */ -// ath5k_hw_set_rx_signal(ah, &ATH_NODE(ic->ic_bss)->an_halstats); - -#undef PA2DESC -} - #ifdef BLE /* - * Setup a hardware data transmit queue for the specified - * access control. The hal may not support all requested - * queues in which case it will return a reference to a - * previously setup queue. We record the mapping from ac's - * to h/w queues for use by ath_tx_start and also track - * the set of h/w queues being used to optimize work in the - * transmit interrupt handler and related routines. - */ -static int -ath_tx_setup(struct ath_softc *sc, int ac, int haltype) -{ -#define N(a) (sizeof(a)/sizeof(a[0])) - struct ath_txq *txq; - - if (ac >= N(sc->sc_ac2q)) { - printk("%s: AC %u out of range, max %u!\n", - sc->sc_dev.name, ac, (unsigned int) N(sc->sc_ac2q)); - return 0; - } - txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, haltype); - if (txq != NULL) { - sc->sc_ac2q[ac] = txq; - return 1; - } else - return 0; -#undef N -} - -/* * Update WME parameters for a transmit queue. */ static int @@ -2640,595 +1655,6 @@ ath_wme_update(struct ieee80211com *ic) !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; } -static int -ath_tx_start(struct net_device *dev, struct ieee80211_node *ni, struct ath_buf *bf, - struct sk_buff *skb) -{ -#define CTS_DURATION \ - ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, true) -/*#define updateCTSForBursting(_ah, _ds, _txq) \ - ath_hal_updateCTSForBursting(_ah, _ds, \ - _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ - _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \ - txopLimit, CTS_DURATION)*/ - struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah = sc->sc_ah; - const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; - int iswep, ismcast, keyix, hdrlen, pktlen, try0; - u_int8_t rix, txrate, ctsrate; - u_int8_t cix = 0xff; /* NB: silence compiler */ - struct ath_desc *ds; - struct ath_txq *txq; - struct ieee80211_frame *wh; - u_int subtype, flags, ctsduration; - AR5K_PKT_TYPE atype; - const struct ath5k_rate_table *rt; - bool short_preamble; - struct ath_node *an; - struct llc *llc; - int eapol; - u_int pri; - - wh = (struct ieee80211_frame *) skb->data; - iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; - ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); - hdrlen = ieee80211_anyhdrsize(wh); - // TODO: not so correct (WDS) - llc = (struct llc *) (skb->data + sizeof(struct ieee80211_frame)); - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: ether_type: 0x%x\n", - __func__, ntohs(llc->llc_snap.ether_type)); - if (llc->llc_snap.ether_type == __constant_htons(ETHERTYPE_PAE)) - eapol = 1; - else - eapol = 0; - llc = NULL; - - /* - * Packet length must not include any - * pad bytes; deduct them here. - */ - //TODO: ??? pktlen = m0->m_pkthdr.len - (hdrlen & 3); - pktlen = skb->len - (hdrlen & 3); - - if (iswep) { - const struct ieee80211_cipher *cip; - struct ieee80211_key *k; - - /* - * Construct the 802.11 header+trailer for an encrypted - * frame. The only reason this can fail is because of an - * unknown or unsupported cipher/key type. - */ - k = ieee80211_crypto_encap(ic, ni, skb); - if (k == NULL) { - /* - * This can happen when the key is yanked after the - * frame was queued. Just discard the frame; the - * 802.11 layer counts failures and provides - * debugging/diagnostics. - */ - dev_kfree_skb(skb); - return -EIO; - } - /* - * Adjust the packet + header lengths for the crypto - * additions and calculate the h/w key index. When - * a s/w mic is done the frame will have had any mic - * added to it prior to entry so skb->len above will - * account for it. Otherwise we need to add it to the - * packet length. - */ - cip = k->wk_cipher; - hdrlen += cip->ic_header; - pktlen += cip->ic_header + cip->ic_trailer; - if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) - pktlen += cip->ic_miclen; - keyix = k->wk_keyix; - - /* packet header may have moved, reset our local pointer */ - wh = (struct ieee80211_frame *) skb->data; - } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { - /* - * Use station key cache slot, if assigned. - */ - keyix = ni->ni_ucastkey.wk_keyix; - if (keyix == IEEE80211_KEYIX_NONE) - keyix = AR5K_TXKEYIX_INVALID; - } else - keyix = AR5K_TXKEYIX_INVALID; - - pktlen += IEEE80211_CRC_LEN; - - /* - * Load the DMA map so any coalescing is done. This - * also calculates the number of descriptors we need. - */ - bf->bf_skbaddr = bus_map_single(sc->sc_bdev, - skb->data, pktlen, BUS_DMA_TODEVICE); - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: skb %p [data %p len %u] skbaddr %lx\n", - __func__, skb, skb->data, skb->len, (long unsigned int) bf->bf_skbaddr); - if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { - if_printf(dev, "%s: DMA mapping failed\n", __func__); - dev_kfree_skb(skb); - bf->bf_skb = NULL; - sc->sc_stats.ast_tx_busdma++; - return -EIO; - } - bf->bf_skb = skb; - bf->bf_node = ni; - - /* setup descriptors */ - ds = bf->bf_desc; - rt = sc->sc_currates; - KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); - - /* - * NB: the 802.11 layer marks whether or not we should - * use short preamble based on the current mode and - * negotiated parameters. - */ - if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && - (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { - short_preamble = true; - sc->sc_stats.ast_tx_shortpre++; - } else { - short_preamble = false; - } - - an = ATH_NODE(ni); - flags = AR5K_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ - /* - * Calculate Atheros packet type from IEEE80211 packet header, - * setup for rate calculations, and select h/w transmit queue. - */ - switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { - case IEEE80211_FC0_TYPE_MGT: - subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; - if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) - atype = AR5K_PKT_TYPE_BEACON; - else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) - atype = AR5K_PKT_TYPE_PROBE_RESP; - else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) - atype = AR5K_PKT_TYPE_ATIM; - else - atype = AR5K_PKT_TYPE_NORMAL; /* XXX */ - rix = 0; /* XXX lowest rate */ - try0 = ATH_TXMAXTRY; - if (short_preamble) - txrate = an->an_tx_mgtratesp; - else - txrate = an->an_tx_mgtrate; - /* NB: force all management frames to highest queue */ - if (ni->ni_flags & IEEE80211_NODE_QOS) { - pri = WME_AC_VO; - } else - pri = WME_AC_BE; - flags |= AR5K_TXDESC_INTREQ; /* force interrupt */ - break; - case IEEE80211_FC0_TYPE_CTL: - atype = AR5K_PKT_TYPE_PSPOLL; /* stop setting of duration */ - rix = 0; /* XXX lowest rate */ - try0 = ATH_TXMAXTRY; - if (short_preamble) - txrate = an->an_tx_mgtratesp; - else - txrate = an->an_tx_mgtrate; - /* NB: force all ctl frames to highest queue */ - if (ni->ni_flags & IEEE80211_NODE_QOS) { - pri = WME_AC_VO; - } else - pri = WME_AC_BE; - flags |= AR5K_TXDESC_INTREQ; /* force interrupt */ - break; - case IEEE80211_FC0_TYPE_DATA: - atype = AR5K_PKT_TYPE_NORMAL; /* default */ - if (ismcast) { - rix = 0; /* XXX lowest rate */ - try0 = 0; - if (short_preamble) - txrate = an->an_tx_mgtratesp; - else - txrate = an->an_tx_mgtrate; - } - else if (eapol) { - rix = 0; /* XXX lowest rate */ - try0 = 0; // TODO: userspace or hardware retry? - if (short_preamble) - txrate = an->an_tx_mgtratesp; - else - txrate = an->an_tx_mgtrate; - flags |= AR5K_TXDESC_INTREQ; /* force interrupt */ - } else { - if (ic->ic_fixed_rate == -1) { - /* - * Data frames; consult the rate control module. - */ - ath_rate_findrate(sc, an, short_preamble, pktlen, - &rix, &try0, &txrate); - } - else { - rix = ic->ic_fixed_rate; - try0 = ATH_TXMAXTRY; //XXX: should be configurabe - if (short_preamble) - txrate = rt->rates[rix].rate_code | SHPREAMBLE_FLAG(rix); - else - txrate = rt->rates[rix].rate_code; - } - } - sc->sc_txrate = txrate; /* for LED blinking */ - /* - * Default all non-QoS traffic to the background queue. - */ - if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { - pri = M_WME_GETAC(skb); - if (cap->cap_wmeParams[pri].wmep_noackPolicy) { - flags |= AR5K_TXDESC_NOACK; - sc->sc_stats.ast_tx_noack++; - } - } else - pri = WME_AC_BE; - break; - default: - if_printf(dev, "bogus frame type 0x%x (%s)\n", - wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); - /* XXX statistic */ - DPRINTF(sc, ATH_DEBUG_FATAL, "%s: kfree_skb: skb %p [data %p len %u] skbaddr %lx\n", - __func__, skb, skb->data, skb->len, (long unsigned int) bf->bf_skbaddr); - dev_kfree_skb(skb); - bf->bf_skb = NULL; - return -EIO; - } - txq = sc->sc_ac2q[pri]; - - DPRINTF(sc, ATH_DEBUG_RATE, "%s: [%s] rix %d, try %d, txrate %d (rs_nrates %d)\n", - __func__, ether_sprintf(ni->ni_macaddr), - rix, try0, txrate, ni->ni_rates.rs_nrates); - - /* - * When servicing one or more stations in power-save mode - * multicast frames must be buffered until after the beacon. - * We use the CAB queue for that. - */ - if (ismcast && ic->ic_ps_sta) { - txq = sc->sc_cabq; - /* XXX? more bit in 802.11 frame header */ - } - - /* - * Calculate miscellaneous flags. - */ - if (ismcast) { - flags |= AR5K_TXDESC_NOACK; /* no ack on broad/multicast */ - sc->sc_stats.ast_tx_noack++; - } else if (pktlen > ic->ic_rtsthreshold) { - flags |= AR5K_TXDESC_RTSENA; /* RTS based on frame length */ - cix = rt->rates[rix].control_rate; - sc->sc_stats.ast_tx_rts++; - } - - /* - * If 802.11g protection is enabled, determine whether - * to use RTS/CTS or just CTS. Note that this is only - * done for OFDM unicast frames. - */ - if ((ic->ic_flags & IEEE80211_F_USEPROT) && - rt->rates[rix].modulation == MODULATION_OFDM && - (flags & AR5K_TXDESC_NOACK) == 0) { - /* XXX fragments must use CCK rates w/ protection */ - if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) - flags |= AR5K_TXDESC_RTSENA; - else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) - flags |= AR5K_TXDESC_CTSENA; - cix = rt->rates[sc->sc_protrix].control_rate; - sc->sc_stats.ast_tx_protect++; - } - - /* - * Calculate duration. This logically belongs in the 802.11 - * layer but it lacks sufficient information to calculate it. - */ - if ((flags & AR5K_TXDESC_NOACK) == 0 && - (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { - u_int16_t dur; - /* - * XXX not right with fragmentation. - */ - if (short_preamble) - dur = rt->rates[rix].sp_ack_duration; - else - dur = rt->rates[rix].lp_ack_duration; - wh->i_dur = htole16(dur); - } - - /* - * Calculate RTS/CTS rate and duration if needed. - */ - ctsduration = 0; - if (flags & (AR5K_TXDESC_RTSENA|AR5K_TXDESC_CTSENA)) { - /* - * CTS transmit rate is derived from the transmit rate - * by looking in the h/w rate table. We must also factor - * in whether or not a short preamble is to be used. - */ - /* NB: cix is set above where RTS/CTS is enabled */ - KASSERT(cix != 0xff, ("cix not setup")); - ctsrate = rt->rates[cix].rate_code; - /* - * Compute the transmit duration based on the frame - * size and the size of an ACK frame. We call into the - * HAL to do the computation since it depends on the - * characteristics of the actual PHY being used. - * - * NB: CTS is assumed the same size as an ACK so we can - * use the precalculated ACK durations. - */ - if (short_preamble) { - ctsrate |= SHPREAMBLE_FLAG(cix); - if (flags & AR5K_TXDESC_RTSENA) /* SIFS + CTS */ - ctsduration += rt->rates[cix].sp_ack_duration; - ctsduration += ath_hal_computetxtime(ah, - rt, pktlen, rix, true); - if ((flags & AR5K_TXDESC_NOACK) == 0) /* SIFS + ACK */ - ctsduration += rt->rates[cix].sp_ack_duration; - } else { - if (flags & AR5K_TXDESC_RTSENA) /* SIFS + CTS */ - ctsduration += rt->rates[cix].lp_ack_duration; - ctsduration += ath_hal_computetxtime(ah, - rt, pktlen, rix, false); - if ((flags & AR5K_TXDESC_NOACK) == 0) /* SIFS + ACK */ - ctsduration += rt->rates[cix].lp_ack_duration; - } - /* - * Must disable multi-rate retry when using RTS/CTS. - */ - try0 = ATH_TXMAXTRY; - } else - ctsrate = 0; - - if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) - ieee80211_dump_pkt(skb->data, skb->len, - sc->sc_hwmap[txrate].ieeerate, -1); - - /* - * Determine if a tx interrupt should be generated for - * this descriptor. We take a tx interrupt to reap - * descriptors when the h/w hits an EOL condition or - * when the descriptor is specifically marked to generate - * an interrupt. We periodically mark descriptors in this - * way to insure timely replenishing of the supply needed - * for sending frames. Defering interrupts reduces system - * load and potentially allows more concurrent work to be - * done but if done to aggressively can cause senders to - * backup. - * - * NB: use >= to deal with sc_txintrperiod changing - * dynamically through sysctl. - */ - if (flags & AR5K_TXDESC_INTREQ) { - txq->axq_intrcnt = 0; - } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { - flags |= AR5K_TXDESC_INTREQ; - txq->axq_intrcnt = 0; - } - - /* - * Formulate first tx descriptor with tx controls. - */ - /* XXX check return value? */ - ah->ah_setup_tx_desc(ah, ds - , pktlen /* packet length */ - , hdrlen /* header length */ - , atype /* Atheros packet type */ - , ni->ni_txpower /* txpower */ - , txrate, try0 /* series 0 rate/tries */ - , keyix /* key cache index */ - , sc->sc_txantenna /* antenna mode */ - , flags /* flags */ - , ctsrate /* rts/cts rate */ - , ctsduration /* rts/cts duration */ - ); - bf->bf_flags = flags; - /* - * Setup the multi-rate retry state only when we're - * going to use it. This assumes ath_hal_setuptxdesc - * initializes the descriptors (so we don't have to) - * when the hardware supports multi-rate retry and - * we don't use it. - */ - if (try0 != ATH_TXMAXTRY) - ath_rate_setupxtxdesc(sc, an, ds, short_preamble, rix); - - /* - * Fillin the remainder of the descriptor info. - */ - ds->ds_link = 0; - ds->ds_data = bf->bf_skbaddr; - ah->ah_fill_tx_desc(ah, ds - , skb->len /* segment length */ - , true /* first segment */ - , true /* last segment */ - , ds /* first descriptor */ - ); - DPRINTF(sc, ATH_DEBUG_XMIT, "%s: Q%d: %08x %08x %08x %08x %08x %08x\n", - __func__, txq->axq_qnum, ds->ds_link, ds->ds_data, - ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); - /* - * Insert the frame on the outbound list and - * pass it on to the hardware. - */ - ATH_TXQ_LOCK_BH(txq); - if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { -// u_int32_t txopLimit = IEEE80211_TXOP_TO_US( -// cap->cap_wmeParams[pri].wmep_txopLimit); - /* - * When bursting, potentially extend the CTS duration - * of a previously queued frame to cover this frame - * and not exceed the txopLimit. If that can be done - * then disable RTS/CTS on this frame since it's now - * covered (burst extension). Otherwise we must terminate - * the burst before this frame goes out so as not to - * violate the WME parameters. All this is complicated - * as we need to update the state of packets on the - * (live) hardware queue. The logic is buried in the hal - * because it's highly chip-specific. - */ -// if (txopLimit != 0) { -// sc->sc_stats.ast_tx_ctsburst++; -// if (updateCTSForBursting(ah, ds, txq) == 0) { - /* - * This frame was not covered by RTS/CTS from - * the previous frame in the burst; update the - * descriptor pointers so this frame is now - * treated as the last frame for extending a - * burst. - */ -// txq->axq_lastdsWithCTS = ds; - /* set gating Desc to final desc */ -// txq->axq_gatingds = -// (struct ath_desc *)txq->axq_link; -// } else -// sc->sc_stats.ast_tx_ctsext++; -// } - } - ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); - DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: txq depth = %d\n", - __func__, txq->axq_depth); - if (txq->axq_link == NULL) { - ath5k_hw_put_tx_buf(ah, txq->axq_qnum, bf->bf_daddr); - DPRINTF(sc, ATH_DEBUG_XMIT, - "%s: TXDP[%u] = %llx (%p) depth %d\n", __func__, - txq->axq_qnum, (unsigned long long)bf->bf_daddr, - bf->bf_desc, txq->axq_depth); - } else { - *txq->axq_link = bf->bf_daddr; - DPRINTF(sc, ATH_DEBUG_XMIT, - "%s: link[%u](%p)=%llx (%p) depth %d\n", __func__, - txq->axq_qnum, txq->axq_link, - (unsigned long long)bf->bf_daddr, bf->bf_desc, - txq->axq_depth); - } - txq->axq_link = &bf->bf_desc->ds_link; - /* - * The CAB queue is started from the SWBA handler since - * frames only go out on DTIM and to avoid possible races. - */ - if (txq != sc->sc_cabq) - ath5k_hw_tx_start(ah, txq->axq_qnum); - ATH_TXQ_UNLOCK_BH(txq); - - dev->trans_start = jiffies; - sc->sc_rawdev.trans_start = jiffies; - return 0; -//#undef updateCTSForBursting -#undef CTS_DURATION -} - -/* - * Process completed xmit descriptors from the specified queue. - */ -static void -ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) -{ - struct ath_hal *ah = sc->sc_ah; - struct ath_buf *bf; - struct ath_desc *ds; -// struct ieee80211_node *ni; -// struct ath_node *an; -// int sr, lr, pri; - enum ath5k_status status; - - DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %x link %p\n", - __func__, txq->axq_qnum, - ath5k_hw_get_tx_buf(sc->sc_ah, txq->axq_qnum), txq->axq_link); - for (;;) { - ATH_TXQ_LOCK(txq); - txq->axq_intrcnt = 0; /* reset periodic desc intr count */ -// bf = STAILQ_FIRST(&txq->axq_q); - if (bf == NULL) { - txq->axq_link = NULL; - ATH_TXQ_UNLOCK(txq); - break; - } - ds = bf->bf_desc; /* NB: last decriptor */ - status = ah->ah_proc_tx_desc(ah, ds); -#ifdef AR_DEBUG - if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) - ath_printtxbuf(bf, status == AR5K_OK); -#endif - if (status == AR5K_EINPROGRESS) { - ATH_TXQ_UNLOCK(txq); - break; - } - if (ds == txq->axq_lastdsWithCTS) - txq->axq_lastdsWithCTS = NULL; - if (ds == txq->axq_gatingds) - txq->axq_gatingds = NULL; -// ATH_TXQ_REMOVE_HEAD(txq, bf_list); - ATH_TXQ_UNLOCK(txq); -#ifdef BLE - ni = bf->bf_node; - if (ni != NULL) { - an = ATH_NODE(ni); - if (ds->ds_txstat.ts_status == 0) { - u_int8_t txant = ds->ds_txstat.ts_antenna; - sc->sc_stats.ast_ant_tx[txant]++; - sc->sc_ant_tx[txant]++; - if (ds->ds_txstat.ts_rate & AR5K_TXSTAT_ALTRATE) - sc->sc_stats.ast_tx_altrate++; - sc->sc_stats.ast_tx_rssi = - ds->ds_txstat.ts_rssi; - ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, - ds->ds_txstat.ts_rssi); - pri = M_WME_GETAC(bf->bf_skb); - if (pri >= WME_AC_VO) - ic->ic_wme.wme_hipri_traffic++; - ni->ni_inact = ni->ni_inact_reload; - } else { - if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) - sc->sc_stats.ast_tx_xretries++; - if (ds->ds_txstat.ts_status & AR5K_TXERR_FIFO) - sc->sc_stats.ast_tx_fifoerr++; - if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) - sc->sc_stats.ast_tx_filtered++; - } - sr = ds->ds_txstat.ts_shortretry; - lr = ds->ds_txstat.ts_longretry; - sc->sc_stats.ast_tx_shortretry += sr; - sc->sc_stats.ast_tx_longretry += lr; - /* - * Hand the descriptor to the rate control algorithm. - */ - if ((ds->ds_txstat.ts_status & AR5K_TXERR_FILT) == 0 && - (bf->bf_flags & AR5K_TXDESC_NOACK) == 0) - ath_rate_tx_complete(sc, an, ds); - /* - * Reclaim reference to node. - * - * NB: the node may be reclaimed here if, for example - * this is a DEAUTH message that was sent and the - * node was timed out due to inactivity. - */ - ieee80211_free_node(ni); - } -#endif - bus_unmap_single(sc->sc_bdev, - bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); - - if (sc->sc_rawdev_enabled) { - ath_tx_capture(&sc->sc_rawdev, ds, bf->bf_skb); - } else { - dev_kfree_skb(bf->bf_skb); - } - bf->bf_skb = NULL; -// bf->bf_node = NULL; - - ATH_TXBUF_LOCK(sc); -// STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); - ATH_TXBUF_UNLOCK(sc); - } -} - /* * Deferred processing of transmit interrupt; special-cased * for a single hardware transmit queue (e.g. 5210 and 5211). @@ -3538,75 +1964,6 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) } } -static int -ath_rawdev_attach(struct ath_softc *sc) -{ - struct net_device *rawdev; - unsigned t; - rawdev = &sc->sc_rawdev; - strcpy(rawdev->name, sc->sc_dev.name); - strcat(rawdev->name, "raw"); - rawdev->priv = sc; - - /* ether_setup clobbers type, so save it */ - t = rawdev->type; - ether_setup(rawdev); - rawdev->type = t; - - rawdev->stop = NULL; - rawdev->hard_start_xmit = ath_start_raw; - rawdev->set_multicast_list = NULL; - rawdev->get_stats = ath_getstats; - rawdev->tx_queue_len = ATH_TXBUF; - rawdev->flags |= IFF_NOARP; - rawdev->flags &= ~IFF_MULTICAST; - rawdev->mtu = IEEE80211_MAX_LEN; - - if (register_netdev(rawdev)) { - goto bad; - } - - if ((sc->sc_dev.flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) - netif_start_queue(&sc->sc_rawdev); - - sc->sc_rawdev_enabled = 1; - - return 0; - bad: - return -1; -} - -static void -ath_rawdev_detach(struct ath_softc *sc) -{ - if (sc->sc_rawdev_enabled) { - sc->sc_rawdev_enabled = 0; - netif_stop_queue(&sc->sc_rawdev); - unregister_netdev(&sc->sc_rawdev); - } -} - -#if IEEE80211_VLAN_TAG_USED -static void -ath_vlan_register(struct net_device *dev, struct vlan_group *grp) -{ - struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; - - ieee80211_vlan_register(ic, grp); -} - -static void -ath_vlan_kill_vid(struct net_device *dev, unsigned short vid) -{ - struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; - - ieee80211_vlan_kill_vid(ic, vid); -} -#endif /* IEEE80211_VLAN_TAG_USED */ -#endif -#ifdef BLE /* * Return netdevice statistics. */ @@ -3662,257 +2019,6 @@ ath_iw_getstats(struct net_device *dev) } /* - * Bounce functions to get to the 802.11 code. These are - * necessary for now because wireless extensions operations - * are done on the underlying device and not the 802.11 instance. - * This will change when there can be multiple 802.11 instances - * associated with a device and we must have a net_device for - * each so we can manipulate them individually. - */ -#define ATH_CHAR_BOUNCE(name) \ -static int \ -ath_ioctl_##name(struct net_device *dev, struct iw_request_info *info, \ - char *erq, char *extra) \ -{ \ - struct ath_softc *sc = dev->priv; \ - return ieee80211_ioctl_##name(&sc->sc_ic, info, erq, extra); \ -} -#define ATH_POINT_BOUNCE(name) \ -static int \ -ath_ioctl_##name(struct net_device *dev, struct iw_request_info *info, \ - struct iw_point *erq, char *extra) \ -{ \ - struct ath_softc *sc = dev->priv; \ - return ieee80211_ioctl_##name(&sc->sc_ic, info, erq, extra); \ -} -#define ATH_PARAM_BOUNCE(name) \ -static int \ -ath_ioctl_##name(struct net_device *dev, struct iw_request_info *info, \ - struct iw_param *erq, char *extra) \ -{ \ - struct ath_softc *sc = dev->priv; \ - return ieee80211_ioctl_##name(&sc->sc_ic, info, erq, extra); \ -} -#define ATH_SOCKADDR_BOUNCE(name) \ -static int \ -ath_ioctl_##name(struct net_device *dev, struct iw_request_info *info, \ - struct sockaddr *erq, char *extra) \ -{ \ - struct ath_softc *sc = dev->priv; \ - return ieee80211_ioctl_##name(&sc->sc_ic, info, erq, extra); \ -} -#define ATH_FREQ_BOUNCE(name) \ -static int \ -ath_ioctl_##name(struct net_device *dev, struct iw_request_info *info, \ - struct iw_freq *erq, char *extra) \ -{ \ - struct ath_softc *sc = dev->priv; \ - return ieee80211_ioctl_##name(&sc->sc_ic, info, erq, extra); \ -} -#define ATH_U32_BOUNCE(name) \ -static int \ -ath_ioctl_##name(struct net_device *dev, struct iw_request_info *info, \ - __u32 *erq, char *extra) \ -{ \ - struct ath_softc *sc = dev->priv; \ - return ieee80211_ioctl_##name(&sc->sc_ic, info, erq, extra); \ -} -#define ATH_VOID_BOUNCE(name) \ -static int \ -ath_ioctl_##name(struct net_device *dev, struct iw_request_info *info, \ - void *erq, char *extra) \ -{ \ - struct ath_softc *sc = dev->priv; \ - return ieee80211_ioctl_##name(&sc->sc_ic, info, erq, extra); \ -} - -ATH_CHAR_BOUNCE(giwname) -ATH_POINT_BOUNCE(siwencode) -ATH_POINT_BOUNCE(giwencode) -ATH_PARAM_BOUNCE(siwrate) -ATH_PARAM_BOUNCE(giwrate) -ATH_PARAM_BOUNCE(siwsens) -ATH_PARAM_BOUNCE(giwsens) -ATH_PARAM_BOUNCE(siwrts) -ATH_PARAM_BOUNCE(giwrts) -ATH_PARAM_BOUNCE(siwfrag) -ATH_PARAM_BOUNCE(giwfrag) -ATH_SOCKADDR_BOUNCE(siwap) -ATH_SOCKADDR_BOUNCE(giwap) -ATH_POINT_BOUNCE(siwnickn) -ATH_POINT_BOUNCE(giwnickn) -ATH_FREQ_BOUNCE(siwfreqx) -ATH_FREQ_BOUNCE(giwfreq) -ATH_POINT_BOUNCE(siwessid) -ATH_POINT_BOUNCE(giwessid) -ATH_POINT_BOUNCE(giwrange) -ATH_U32_BOUNCE(siwmode) -ATH_U32_BOUNCE(giwmode) -ATH_PARAM_BOUNCE(siwpower) -ATH_PARAM_BOUNCE(giwpower) -ATH_PARAM_BOUNCE(siwretry) -ATH_PARAM_BOUNCE(giwretry) -ATH_PARAM_BOUNCE(siwtxpow) -ATH_PARAM_BOUNCE(giwtxpow) -ATH_POINT_BOUNCE(iwaplist) -#ifdef SIOCGIWSCAN -ATH_POINT_BOUNCE(siwscan) -ATH_POINT_BOUNCE(giwscan) -#endif -ATH_VOID_BOUNCE(setparam) -ATH_VOID_BOUNCE(getparam) -ATH_VOID_BOUNCE(setkey) -ATH_VOID_BOUNCE(delkey) -ATH_VOID_BOUNCE(setmlme) -ATH_VOID_BOUNCE(setoptie) -ATH_VOID_BOUNCE(getoptie) -ATH_VOID_BOUNCE(addmac) -ATH_VOID_BOUNCE(delmac) -ATH_VOID_BOUNCE(chanlist) - -/* Structures to export the Wireless Handlers */ -static const iw_handler ath_handlers[] = { - (iw_handler) NULL, /* SIOCSIWCOMMIT */ - (iw_handler) ath_ioctl_giwname, /* SIOCGIWNAME */ - (iw_handler) NULL, /* SIOCSIWNWID */ - (iw_handler) NULL, /* SIOCGIWNWID */ - (iw_handler) ath_ioctl_siwfreqx, /* SIOCSIWFREQ */ - (iw_handler) ath_ioctl_giwfreq, /* SIOCGIWFREQ */ - (iw_handler) ath_ioctl_siwmode, /* SIOCSIWMODE */ - (iw_handler) ath_ioctl_giwmode, /* SIOCGIWMODE */ - (iw_handler) ath_ioctl_siwsens, /* SIOCSIWSENS */ - (iw_handler) ath_ioctl_giwsens, /* SIOCGIWSENS */ - (iw_handler) NULL /* not used */, /* SIOCSIWRANGE */ - (iw_handler) ath_ioctl_giwrange, /* SIOCGIWRANGE */ - (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */ - (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */ - (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */ - (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */ - (iw_handler) NULL, /* SIOCSIWSPY */ - (iw_handler) NULL, /* SIOCGIWSPY */ - (iw_handler) NULL, /* -- hole -- */ - (iw_handler) NULL, /* -- hole -- */ - (iw_handler) ath_ioctl_siwap, /* SIOCSIWAP */ - (iw_handler) ath_ioctl_giwap, /* SIOCGIWAP */ - (iw_handler) NULL, /* -- hole -- */ - (iw_handler) ath_ioctl_iwaplist, /* SIOCGIWAPLIST */ -#ifdef SIOCGIWSCAN - (iw_handler) ath_ioctl_siwscan, /* SIOCSIWSCAN */ - (iw_handler) ath_ioctl_giwscan, /* SIOCGIWSCAN */ -#else - (iw_handler) NULL, /* SIOCSIWSCAN */ - (iw_handler) NULL, /* SIOCGIWSCAN */ -#endif /* SIOCGIWSCAN */ - (iw_handler) ath_ioctl_siwessid, /* SIOCSIWESSID */ - (iw_handler) ath_ioctl_giwessid, /* SIOCGIWESSID */ - (iw_handler) ath_ioctl_siwnickn, /* SIOCSIWNICKN */ - (iw_handler) ath_ioctl_giwnickn, /* SIOCGIWNICKN */ - (iw_handler) NULL, /* -- hole -- */ - (iw_handler) NULL, /* -- hole -- */ - (iw_handler) ath_ioctl_siwrate, /* SIOCSIWRATE */ - (iw_handler) ath_ioctl_giwrate, /* SIOCGIWRATE */ - (iw_handler) ath_ioctl_siwrts, /* SIOCSIWRTS */ - (iw_handler) ath_ioctl_giwrts, /* SIOCGIWRTS */ - (iw_handler) ath_ioctl_siwfrag, /* SIOCSIWFRAG */ - (iw_handler) ath_ioctl_giwfrag, /* SIOCGIWFRAG */ - (iw_handler) ath_ioctl_siwtxpow, /* SIOCSIWTXPOW */ - (iw_handler) ath_ioctl_giwtxpow, /* SIOCGIWTXPOW */ - (iw_handler) ath_ioctl_siwretry, /* SIOCSIWRETRY */ - (iw_handler) ath_ioctl_giwretry, /* SIOCGIWRETRY */ - (iw_handler) ath_ioctl_siwencode, /* SIOCSIWENCODE */ - (iw_handler) ath_ioctl_giwencode, /* SIOCGIWENCODE */ - (iw_handler) ath_ioctl_siwpower, /* SIOCSIWPOWER */ - (iw_handler) ath_ioctl_giwpower, /* SIOCGIWPOWER */ -}; -static const iw_handler ath_priv_handlers[] = { - (iw_handler) ath_ioctl_setparam, /* SIOCWFIRSTPRIV+0 */ - (iw_handler) ath_ioctl_getparam, /* SIOCWFIRSTPRIV+1 */ - (iw_handler) ath_ioctl_setkey, /* SIOCWFIRSTPRIV+2 */ - (iw_handler) NULL, /* SIOCWFIRSTPRIV+3 */ - (iw_handler) ath_ioctl_delkey, /* SIOCWFIRSTPRIV+4 */ - (iw_handler) NULL, /* SIOCWFIRSTPRIV+5 */ - (iw_handler) ath_ioctl_setmlme, /* SIOCWFIRSTPRIV+6 */ - (iw_handler) NULL, /* SIOCWFIRSTPRIV+7 */ - (iw_handler) ath_ioctl_setoptie, /* SIOCWFIRSTPRIV+8 */ - (iw_handler) ath_ioctl_getoptie, /* SIOCWFIRSTPRIV+9 */ - (iw_handler) ath_ioctl_addmac, /* SIOCWFIRSTPRIV+10 */ - (iw_handler) NULL, /* SIOCWFIRSTPRIV+11 */ - (iw_handler) ath_ioctl_delmac, /* SIOCWFIRSTPRIV+12 */ - (iw_handler) NULL, /* SIOCWFIRSTPRIV+13 */ - (iw_handler) ath_ioctl_chanlist, /* SIOCWFIRSTPRIV+14 */ -}; - -static struct iw_handler_def ath_iw_handler_def = { -#define N(a) (sizeof (a) / sizeof (a[0])) -/*get_wireless_stats moved from net_device to iw_handler_def*/ -# if IW_HANDLER_VERSION >= 7 - .get_wireless_stats = ath_iw_getstats, -# endif - .standard = (iw_handler *) ath_handlers, - .num_standard = N(ath_handlers), - .private = (iw_handler *) ath_priv_handlers, - .num_private = N(ath_priv_handlers), -#undef N -}; - -static int -ath_set_mac_address(struct net_device *dev, void *addr) -{ - struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; - struct sockaddr *mac = addr; - int error = 0; - - if (netif_running(dev)) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: cannot set address; device running\n", __func__); - return -EBUSY; - } - DPRINTF(sc, ATH_DEBUG_ANY, "%s: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", - __func__, - mac->sa_data[0], mac->sa_data[1], mac->sa_data[2], - mac->sa_data[3], mac->sa_data[4], mac->sa_data[5]); - - ATH_LOCK(sc); - /* XXX not right for multiple vap's */ -// IEEE80211_ADDR_COPY(ic->ic_myaddr, mac->sa_data); - memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN); - ath5k_hw_set_lladdr(ah, dev->dev_addr); - if ((dev->flags & IFF_RUNNING) && !sc->sc_invalid) { - error = -ath_reset(dev); - } - ATH_UNLOCK(sc); - - return error; -} - -static int -ath_change_mtu(struct net_device *dev, int mtu) -{ - struct ath_softc *sc = dev->priv; - int error = 0; - - if (!(ATH_MIN_MTU < mtu && mtu <= ATH_MAX_MTU)) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d, min %u, max %u\n", - __func__, mtu, ATH_MIN_MTU, ATH_MAX_MTU); - return -EINVAL; - } - DPRINTF(sc, ATH_DEBUG_ANY, "%s: %d\n", __func__, mtu); - - ATH_LOCK(sc); - dev->mtu = mtu; - if ((dev->flags & IFF_RUNNING) && !sc->sc_invalid) { - /* NB: the rx buffers may need to be reallocated */ - tasklet_disable(&sc->sc_rxtq); - error = -ath_reset(dev); - tasklet_enable(&sc->sc_rxtq); - } - ATH_UNLOCK(sc); - - return error; -} - -/* * Diagnostic interface to the HAL. This is used by various * tools to do things like retrieve register contents for * debugging. The mechanism is intentionally opaque so that @@ -4494,56 +2600,3 @@ ath_dynamic_sysctl_unregister(struct ath_softc *sc) sc->sc_sysctls = NULL; } } - -/* - * Announce various information on device/driver attach. - */ -static void -ath_announce(struct ath_softc *sc) -{ -#define AR5K_MODE_DUALBAND (AR5K_MODE_11A|AR5K_MODE_11B) -// struct net_device *dev = &sc->sc_dev; - struct ath_hal *ah = sc->sc_ah; - u_int modes, cc; -// int i; - - printk(KERN_INFO "mac %d.%d phy %d.%d", - ah->ah_mac_version, ah->ah_mac_version, - ah->ah_phy_revision >> 4, ah->ah_phy_revision & 0xf); - /* - * Print radio revision(s). We check the wireless modes - * to avoid falsely printing revs for inoperable parts. - * Dual-band radio revs are returned in the 5Ghz rev number. - */ - cc = ah->ah_country_code; - modes = ath_hal_getwirelessmodes(ah, cc); - if ((modes & AR5K_MODE_DUALBAND) == AR5K_MODE_DUALBAND) { - if (ah->ah_radio_5ghz_revision && ah->ah_radio_2ghz_revision) - printk(" 5ghz radio %d.%d 2ghz radio %d.%d", - ah->ah_radio_5ghz_revision >> 4, - ah->ah_radio_5ghz_revision & 0xf, - ah->ah_radio_2ghz_revision >> 4, - ah->ah_radio_2ghz_revision & 0xf); - else - printk(" radio %d.%d", ah->ah_radio_5ghz_revision >> 4, - ah->ah_radio_5ghz_revision & 0xf); - } else - printk(" radio %d.%d", ah->ah_radio_5ghz_revision >> 4, - ah->ah_radio_5ghz_revision & 0xf); - printk("\n"); -#ifdef BLE - for (i = 0; i <= WME_AC_VO; i++) { - struct ath_txq *txq = sc->sc_ac2q[i]; - printk(KERN_INFO "Use hw queue %u for %s traffic\n", - txq->axq_qnum, ieee80211_wme_acnames[i]); - } -#endif - printk(KERN_INFO "Use hw queue %u for CAB traffic\n", - sc->sc_cabq->axq_qnum); - printk(KERN_INFO "Use hw queue %u for beacons\n", sc->sc_bhalq); - -#ifdef AR_DEBUG - printk("Debugging version (ATH)\n"); -#endif -#undef AR5K_MODE_DUALBAND -} commit eed257a53095c0a9c56c8c42f9f8595736fe7cc0 Author: Jiri Slaby Date: Mon Jul 16 08:44:51 2007 +0200 hal: gpio cleanup diff --git a/ath5k.h b/ath5k.h index 77e21dd..5bdb6da 100644 --- a/ath5k.h +++ b/ath5k.h @@ -1048,10 +1048,10 @@ unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); /* GPIO Functions */ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); -bool ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); -bool ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); +int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); +int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); -bool ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); +int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); /* Regulatory Domain/Channels Setup */ unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); diff --git a/ath5k_hw.c b/ath5k_hw.c index 121d464..4460105 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -4286,8 +4286,7 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, /* * Set led state */ -void -ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) +void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) { u32 led; /*5210 has different led mode handling*/ @@ -4345,79 +4344,74 @@ ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) /* * Set GPIO outputs */ -bool -ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) +int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return false; + return -EINVAL; ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); - return true; + return 0; } /* * Set GPIO inputs */ -bool -ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) +int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return false; + return -EINVAL; ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); - return true; + return 0; } /* * Get GPIO state */ -u32 -ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) +u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio) { AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) return 0xffffffff; /* GPIO input magic */ - return (((ath5k_hw_reg_read(hal, AR5K_GPIODI) & - AR5K_GPIODI_M) >> gpio) & 0x1); + return ((ath5k_hw_reg_read(hal, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) & + 0x1; } /* * Set GPIO state */ -bool -ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) +int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) { u32 data; AR5K_TRACE; if (gpio > AR5K_NUM_GPIO) - return false; + return -EINVAL; /* GPIO output magic */ data = ath5k_hw_reg_read(hal, AR5K_GPIODO); data &= ~(1 << gpio); - data |= (val&1) << gpio; + data |= (val & 1) << gpio; ath5k_hw_reg_write(hal, data, AR5K_GPIODO); - return true; + return 0; } /* * Initialize the GPIO interrupt (RFKill switch) */ -void -ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, - u32 interrupt_level) +void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, + u32 interrupt_level) { u32 data; commit 77ed58d5f9f022d808eac8dee773d8adf8d8155a Author: Jiri Slaby Date: Mon Jul 16 08:57:25 2007 +0200 hal: channels cleanup (remove ath_hal_mhz2ieee and co.) diff --git a/ath.c b/ath.c index 77c5acc..4be0b04 100644 --- a/ath.c +++ b/ath.c @@ -1400,7 +1400,7 @@ static unsigned int ath_copy_channels(struct ath_hw *ah, ch = all ? i + 1 : chans[i].chan; f = ath_ieee2mhz(ch); /* Check if channel is supported by the chipset */ - if (ath5k_check_channel(ah, f, chfreq) == false) + if (!ath5k_channel_ok(ah, f, chfreq)) continue; /* Match regulation domain */ diff --git a/ath5k.h b/ath5k.h index 5bdb6da..d89245e 100644 --- a/ath5k.h +++ b/ath5k.h @@ -1054,10 +1054,7 @@ u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); /* Regulatory Domain/Channels Setup */ -unsigned int ath_hal_mhz2ieee(unsigned int freq, u_int flags); -unsigned int ath_hal_ieee2mhz(unsigned int chan, u_int flags); -bool ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags); -bool ath_hal_init_channels(struct ath_hw *hal, struct ieee80211_channel *channels, unsigned int max_channels, u_int *channels_size, enum ieee80211_countrycode country, u16 mode, bool outdoor, bool extended); +bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags); u16 ath5k_get_regdomain(struct ath_hw *hal); /* PHY/RF access functions */ int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); diff --git a/ath5k_hw.c b/ath5k_hw.c index 4460105..00faf4d 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -4444,43 +4444,9 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, \*********************************/ /* - * Following 2 functions come from net80211 - * TODO: These do not belong here, they have nothing - * to do with hw. I left them here temporarily for - * combatibility. - * M.F. - */ - -/* - * Convert MHz frequency to IEEE channel number. - */ -unsigned int -ath_hal_mhz2ieee(unsigned int freq, u_int flags) -{ - if (flags & CHANNEL_2GHZ) { /* 2GHz band */ - if (freq == 2484) /* Japan */ - return 14; - /* don't number non-IEEE channels unless we do channel tests */ - if ((freq >= 2412) && (freq < 2484)) - return (freq - 2407) / 5; - if (CHAN_DEBUG == 1) /* 15-26 */ - return ((freq - 2512)/20) + 15; - return 0; - } else if (flags & CHANNEL_5GHZ) { /* 5Ghz band */ - /* don't number non-IEEE channels unless we do channel tests */ - if (((freq >= 5150) && (freq <= 5825))|| CHAN_DEBUG == 1) - return (freq - 5000) / 5; - return 0; - } else - /* something is fishy, don't do anything */ - return 0; -} - -/* * Check if a channel is supported */ -bool -ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags) +bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags) { /* Check if the channel is in our supported range */ if (flags & CHANNEL_2GHZ) { @@ -4495,8 +4461,7 @@ ath5k_check_channel(struct ath_hw *hal, u16 freq, unsigned int flags) return false; } -u16 -ath5k_get_regdomain(struct ath_hw *hal) +u16 ath5k_get_regdomain(struct ath_hw *hal) { u16 regdomain; enum ieee80211_regdomain ieee_regdomain; @@ -4539,8 +4504,8 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) * newer chipsets like the AR5212A who have a completely * different RF/PHY part. */ - athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq, - channel->val) - 24) / 2, 5) << 1) | (1 << 6) | 0x1; + athchan = (ath5k_hw_bitswap((channel->chan - 24) / 2, 5) << 1) | + (1 << 6) | 0x1; return athchan; } @@ -4599,7 +4564,7 @@ static int ath5k_hw_rf5111_channel(struct ath_hw *hal, struct ieee80211_channel *channel) { struct ath5k_athchan_2ghz ath_channel_2ghz; - unsigned int ieee_channel, ath_channel; + unsigned int ath_channel = channel->chan; u32 data0, data1, clock; int ret; @@ -4607,12 +4572,10 @@ static int ath5k_hw_rf5111_channel(struct ath_hw *hal, * Set the channel on the RF5111 radio */ data0 = data1 = 0; - ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, - channel->val); if (channel->val & CHANNEL_2GHZ) { /* Map 2GHz channel to 5GHz Atheros channel ID */ - ret = ath5k_hw_rf5111_chan2athchan(ieee_channel, + ret = ath5k_hw_rf5111_chan2athchan(channel->chan, &ath_channel_2ghz); if (ret) return ret; commit 5875b4d8b6f3cbfd5498edecdf8b20cc3f339522 Author: Jiri Slaby Date: Mon Jul 16 09:01:32 2007 +0200 some capability cleanup diff --git a/ath5k.h b/ath5k.h index d89245e..83b2f43 100644 --- a/ath5k.h +++ b/ath5k.h @@ -1071,7 +1071,6 @@ enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); void ath5k_hw_dump_state(struct ath_hw *hal); int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); -int ath5k_hw_set_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 setting); bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); bool ath5k_hw_disable_pspoll(struct ath_hw *hal); diff --git a/ath5k_hw.c b/ath5k_hw.c index 00faf4d..963b695 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -5698,11 +5698,6 @@ int ath5k_hw_get_capability(struct ath_hw *hal, AR5K_TRACE; switch (cap_type) { - case AR5K_CAP_REG_DMN: - if (result){ - *result = ath5k_get_regdomain(hal); - goto yes; - } case AR5K_CAP_NUM_TXQUEUES: if (result) { if (hal->ah_version == AR5K_AR5210) @@ -5743,15 +5738,6 @@ int ath5k_hw_get_capability(struct ath_hw *hal, } -int ath5k_hw_set_capability(struct ath_hw *hal, - enum ath5k_capability_type cap_type, - u32 capability, u32 setting) -{ - AR5K_TRACE; - - return 0; -} - bool ath5k_hw_query_pspoll_support(struct ath_hw *hal) { commit 3f73797a653e5ae300443a809d9de4a5f4f19c21 Author: Jiri Slaby Date: Tue Jul 17 08:06:18 2007 +0200 isr optimisation (likely/unlikely) diff --git a/ath.c b/ath.c index 4be0b04..9b19bb7 100644 --- a/ath.c +++ b/ath.c @@ -43,9 +43,9 @@ #define AR_DEBUG 1 #if AR_DEBUG -#define DPRINTF(sc, _m, _fmt...) do { \ - if (((sc)->debug & (_m)) && net_ratelimit()) \ - printk(KERN_DEBUG _fmt); \ +#define DPRINTF(sc, _m, _fmt...) do { \ + if (unlikely(((sc)->debug & (_m)) && net_ratelimit())) \ + printk(KERN_DEBUG _fmt); \ } while (0) #else static inline int __attribute__ ((format (printf, 3, 4))) @@ -164,9 +164,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) ds = bf->desc; ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); - if (ret == -EINPROGRESS) + if (unlikely(ret == -EINPROGRESS)) break; - else if (ret) { + else if (unlikely(ret)) { printk(KERN_ERR "ath: error %d while processing " "queue %u\n", ret, txq->qnum); break; @@ -180,7 +180,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) txs.control = bf->ctl; txs.retry_count = ds->ds_txstat.ts_shortretry + ds->ds_txstat.ts_longretry / 6; - if (ds->ds_txstat.ts_status) { + if (unlikely(ds->ds_txstat.ts_status)) { sc->ll_stats.dot11ACKFailureCount++; if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { txs.excessive_retries = 1; @@ -202,7 +202,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) list_move_tail(&bf->list, &sc->txbuf); spin_unlock(&sc->txbuflock); } - if (list_empty(&txq->q)) + if (likely(list_empty(&txq->q))) txq->link = NULL; spin_unlock(&txq->lock); } @@ -224,7 +224,7 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) struct sk_buff *skb = bf->skb; struct ath_desc *ds; - if (skb == NULL) { + if (likely(skb == NULL)) { unsigned int off; /* @@ -232,7 +232,7 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) * fake physical layer header at the start. */ skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); - if (skb == NULL) { + if (unlikely(skb == NULL)) { DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " "size %u failed\n", __func__, sc->rxbufsize + sc->cachelsz - 1); @@ -251,7 +251,7 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) bf->skb = skb; bf->skbaddr = pci_map_single(sc->pdev, skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(bf->skbaddr)) { + if (unlikely(pci_dma_mapping_error(bf->skbaddr))) { printk(KERN_ERR "%s: DMA mapping failed\n", __func__); dev_kfree_skb(skb); bf->skb = NULL; @@ -326,7 +326,7 @@ static void ath_tasklet_rx(unsigned long data) spin_lock(&sc->rxbuflock); do { - if (list_empty(&sc->rxbuf)) { + if (unlikely(list_empty(&sc->rxbuf))) { if (net_ratelimit()) printk(KERN_WARNING "ath: empty rx buf pool\n"); break; @@ -335,27 +335,27 @@ static void ath_tasklet_rx(unsigned long data) BUG_ON(bf->skb == NULL); skb = bf->skb; ds = bf->desc; - if (ds->ds_link == bf->daddr) /* this is the end */ + if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */ break; ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); - if (ret == -EINPROGRESS) + if (unlikely(ret == -EINPROGRESS)) break; - else if (ret) { + else if (unlikely(ret)) { if (net_ratelimit()) printk(KERN_ERR "ath: error in processing rx " "descriptor\n"); return; } - if (ds->ds_rxstat.rs_more) { + if (unlikely(ds->ds_rxstat.rs_more)) { if (net_ratelimit()) printk(KERN_INFO "ath: unsupported jumbo\n"); goto next; } stat = ds->ds_rxstat.rs_status; - if (stat) { + if (unlikely(stat)) { if (stat & AR5K_RXERR_CRC) sc->stats.ast_rx_crcerr++; if (stat & AR5K_RXERR_FIFO) @@ -398,7 +398,7 @@ accept: PCI_DMA_FROMDEVICE); bf->skb = NULL; - if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) + if (unlikely((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit())) printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); skb_put(skb, len); @@ -604,7 +604,7 @@ static void ath_stoprecv(struct ath_softc *sc) ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ mdelay(3); /* 3ms is long enough for 1 frame */ #if AR_DEBUG - if (sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { + if (unlikely(sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL))) { struct ath_desc *ds; struct ath_buf *bf; int status; @@ -663,7 +663,7 @@ static void ath_draintxq(struct ath_softc *sc) int i; /* XXX return value */ - if (!sc->invalid) { + if (likely(!sc->invalid)) { #ifdef BLE /* don't touch the hardware if marked invalid */ (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); @@ -1018,14 +1018,14 @@ static int ath_reset(struct ieee80211_hw *hw) ath_stoprecv(sc); ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, sc->curchan, true); - if (ret) { + if (unlikely(ret)) { printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); goto err; } ath_update_txpow(sc); ret = ath_startrecv(sc); - if (ret) { + if (unlikely(ret)) { printk(KERN_ERR "ath: can't start recv logic\n"); goto err; } @@ -1248,7 +1248,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) enum ath5k_int status; unsigned int counter = 1000; - if (sc->invalid || !ath5k_hw_is_intr_pending(ah)) + if (unlikely(sc->invalid || !ath5k_hw_is_intr_pending(ah))) return IRQ_NONE; do { @@ -1262,7 +1262,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x/0x%x\n", __func__, status, sc->imask); status &= sc->imask; /* discard unasked for bits */ - if (status & AR5K_INT_FATAL) { + if (unlikely(status & AR5K_INT_FATAL)) { /* * Fatal errors are unrecoverable. Typically * these are caused by DMA errors. Unfortunately @@ -1271,7 +1271,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) */ sc->stats.ast_hardware++; ath_reset(sc->hw); - } else if (status & AR5K_INT_RXORN) { + } else if (unlikely(status & AR5K_INT_RXORN)) { sc->stats.ast_rxorn++; ath_reset(sc->hw); } else { @@ -1313,7 +1313,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) } } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); - if (!counter && net_ratelimit()) + if (unlikely(!counter && net_ratelimit())) printk(KERN_WARNING "ath: too many interrupts, giving up for " "now\n"); diff --git a/ath5k_hw.c b/ath5k_hw.c index 963b695..6f17542 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -1737,7 +1737,7 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) */ if (hal->ah_version == AR5K_AR5210) { data = ath5k_hw_reg_read(hal, AR5K_ISR); - if (data == AR5K_INT_NOCARD) { + if (unlikely(data == AR5K_INT_NOCARD)) { *interrupt_mask = data; return -ENODEV; } @@ -1753,7 +1753,7 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) */ *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; - if (data == AR5K_INT_NOCARD) + if (unlikely(data == AR5K_INT_NOCARD)) return -ENODEV; if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) @@ -1764,11 +1764,11 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) if (hal->ah_version != AR5K_AR5210) { /*HIU = Host Interface Unit (PCI etc)*/ - if (data & (AR5K_ISR_HIUERR)) + if (unlikely(data & (AR5K_ISR_HIUERR))) *interrupt_mask |= AR5K_INT_FATAL; /*Beacon Not Ready*/ - if (data & (AR5K_ISR_BNR)) + if (unlikely(data & (AR5K_ISR_BNR))) *interrupt_mask |= AR5K_INT_BNR; } @@ -1784,7 +1784,7 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) * In case we didn't handle anything, * print the register value. */ - if (*interrupt_mask == 0 && printk_ratelimit()) + if (unlikely(*interrupt_mask == 0 && net_ratelimit())) AR5K_PRINTF("0x%08x\n", data); return 0; @@ -3976,7 +3976,7 @@ static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0]; /* No frame has been send or error */ - if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) + if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) return -EINPROGRESS; /* @@ -4027,7 +4027,7 @@ static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; /* No frame has been send or error */ - if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) + if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) return -EINPROGRESS; /* @@ -4118,7 +4118,7 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, /* Setup descriptor */ rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; - if (rx_desc->rx_control_1 != size) + if (unlikely(rx_desc->rx_control_1 != size)) return -EINVAL; if (flags & AR5K_RXDESC_INTREQ) @@ -4138,7 +4138,8 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0]; /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) + if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) + == 0)) return -EINPROGRESS; /* @@ -4217,7 +4218,8 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0]; /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) + if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) + == 0)) return -EINPROGRESS; /* commit d87f89c0b4e8cdc1a3f99e2fe691bd676d379a6b Author: Jiri Slaby Date: Tue Jul 17 08:06:41 2007 +0200 fix led bug diff --git a/ath.c b/ath.c index 9b19bb7..dfa2f68 100644 --- a/ath.c +++ b/ath.c @@ -1203,7 +1203,7 @@ static void ath_led_off(unsigned long data) if (sc->led_endblink) sc->led_blinking = 0; else { - sc->led_endblink = 0; + sc->led_endblink = 1; ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on); mod_timer(&sc->led_tim, jiffies + sc->led_off); } commit 9c7ba2b31484fa8e7388cfe2c3e11a9e0aa3f02c Author: Jiri Slaby Date: Tue Jul 17 08:12:33 2007 +0200 reset tasklet (reset is too long (delays) for hardisr) diff --git a/ath.c b/ath.c index dfa2f68..2f3597d 100644 --- a/ath.c +++ b/ath.c @@ -115,6 +115,7 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = { MODULE_DEVICE_TABLE(pci, ath_pci_id_table); static void ath_led_event(struct ath_softc *, int); +static int ath_reset(struct ieee80211_hw *); #if AR_DEBUG static void ath_printrxbuf(struct ath_buf *bf, int done) @@ -151,6 +152,13 @@ static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) {} #endif +static void ath_tasklet_reset(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + ath_reset(sc->hw); +} + static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) { struct ieee80211_tx_status txs = {}; @@ -1270,10 +1278,10 @@ static irqreturn_t ath_intr(int irq, void *dev_id) * by the hal. */ sc->stats.ast_hardware++; - ath_reset(sc->hw); + tasklet_schedule(&sc->restq); } else if (unlikely(status & AR5K_INT_RXORN)) { sc->stats.ast_rxorn++; - ath_reset(sc->hw); + tasklet_schedule(&sc->restq); } else { if (status & AR5K_INT_SWBA) { /* @@ -1773,6 +1781,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); + tasklet_init(&sc->restq, ath_tasklet_reset, (unsigned long)sc); setup_timer(&sc->calib_tim, ath_calibrate, (unsigned long)sc); setup_timer(&sc->led_tim, ath_led_off, (unsigned long)sc); diff --git a/ath.h b/ath.h index 61019ad..b496893 100644 --- a/ath.h +++ b/ath.h @@ -205,6 +205,8 @@ struct ath_softc { int sc_rx_th_len; struct tasklet_struct sc_radartq; /* Radar detection */ #endif + struct tasklet_struct restq; /* reset tasklet */ + unsigned int rxbufsize; /* rx size based on mtu */ struct list_head rxbuf; /* receive buffer */ spinlock_t rxbuflock; commit 4b6190b76e34e774d3099ea60b46fba23bb45cf0 Author: Jiri Slaby Date: Tue Jul 17 08:23:10 2007 +0200 round_jiffies calibration timer (powersave) diff --git a/ath.c b/ath.c index 2f3597d..034e23c 100644 --- a/ath.c +++ b/ath.c @@ -591,8 +591,8 @@ static int ath_init(struct ath_softc *sc) ath5k_hw_set_intr(sc->ah, sc->imask); - mod_timer(&sc->calib_tim, jiffies + - msecs_to_jiffies(ath_calinterval * 1000)); + mod_timer(&sc->calib_tim, round_jiffies(jiffies + + msecs_to_jiffies(ath_calinterval * 1000))); ret = 0; done: @@ -1200,8 +1200,8 @@ static void ath_calibrate(unsigned long data) sc->stats.ast_per_calfail++; } - mod_timer(&sc->calib_tim, jiffies + - msecs_to_jiffies(ath_calinterval * 1000)); + mod_timer(&sc->calib_tim, round_jiffies(jiffies + + msecs_to_jiffies(ath_calinterval * 1000))); } static void ath_led_off(unsigned long data) commit c9fa736c192da4b31c8b418cc0f5859f7f5ecd67 Author: Jiri Slaby Date: Tue Jul 17 08:25:56 2007 +0200 don't alloc ATH_BCBUF diff --git a/ath.c b/ath.c index 034e23c..75c16bc 100644 --- a/ath.c +++ b/ath.c @@ -1551,7 +1551,7 @@ static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); - bf = kcalloc(ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1, + bf = kcalloc(ATH_TXBUF + ATH_RXBUF + /*ATH_BCBUF +*/ 1, sizeof(struct ath_buf), GFP_KERNEL); if (bf == NULL) { dev_err(&pdev->dev, "can't allocate bufptr\n"); commit 20955a02d7ddeef222c7811e31d16be148a45f9c Author: Jiri Slaby Date: Tue Jul 17 08:37:20 2007 +0200 make some functions static diff --git a/ath5k.h b/ath5k.h index 83b2f43..6956326 100644 --- a/ath5k.h +++ b/ath5k.h @@ -968,8 +968,6 @@ struct ath_hw { /* * Prototypes */ -/* General Functions */ -u16 ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble); /* Attach/Detach Functions */ struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); @@ -995,9 +993,6 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); /* EEPROM access functions */ -u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode); -int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode); -int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode); int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); /* Protocol Control Unit Functions */ void ath5k_hw_set_opmode(struct ath_hw *hal); @@ -1061,10 +1056,6 @@ int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel bool ath5k_hw_phy_disable(struct ath_hw *hal); void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); -unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 first, u32 col, bool set); -u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal); -bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal); -s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal); bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ diff --git a/ath5k_hw.c b/ath5k_hw.c index 6f17542..ef8b960 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -14,12 +14,10 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id$ */ /* * HAL interface for Atheros Wireless LAN devices. - * (Please have a look at ar5xxx.h for further information) */ #include @@ -124,7 +122,7 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; * Calculate transmition time of a frame * TODO: Left here for combatibility, change it in ath5k */ -u16 /*TODO: Is this really hardware dependent ?*/ +static u16 /*TODO: Is this really hardware dependent ?*/ ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, u32 frame_length, u16 rate_index, bool short_preamble) { @@ -1976,8 +1974,7 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) return -EIO; } -u16 -ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) +static u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) { u16 val; @@ -2004,8 +2001,8 @@ ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) /* * Read antenna infos from eeprom */ -int -ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode) +static int ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, + unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 o = *offset; @@ -2063,8 +2060,8 @@ ath5k_eeprom_read_ants(struct ath_hw *hal, u32 *offset, unsigned int mode) /* * Read supported modes from eeprom */ -int -ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, unsigned int mode) +static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, + unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u32 o = *offset; @@ -4920,7 +4917,7 @@ ath5k_hw_get_def_antenna(struct ath_hw *hal) return false; /*XXX: What do we return for 5210 ?*/ } -unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, +static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, u32 first, u32 col, bool set) { u32 mask, entry, last, data, shift, position; @@ -4967,8 +4964,7 @@ unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, return data; } -u32 -ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal) +static u32 ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal) { u32 mix, step; u32 *rf; @@ -5003,14 +4999,13 @@ ath5k_hw_rfregs_gainf_corr(struct ath_hw *hal) return hal->ah_gain.g_f_corr; } -bool -ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) +static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) { u32 step, mix, level[4]; u32 *rf; if (hal->ah_rf_banks == NULL) - return 0; + return false; rf = hal->ah_rf_banks; @@ -5045,7 +5040,7 @@ ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) hal->ah_gain.g_current <= level[3])); } -s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) +static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) { const struct ath5k_gain_opt *go; int ret = 0; commit 89e9066109c0f7313198d0e10c5af01a70755493 Author: Jiri Slaby Date: Tue Jul 17 22:15:18 2007 +0200 remove unused fucntions diff --git a/ath5k_hw.c b/ath5k_hw.c index ef8b960..f84c94c 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -22,7 +22,6 @@ #include -#include #include #include "ath5k.h" @@ -227,26 +226,6 @@ static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg) writel(val, hal->ah_sh + reg); } -static inline __u16 ath5k_hw_unaligned_read_16(__le16 *p) -{ - return le16_to_cpu(get_unaligned(p)); -} - -static inline void ath5k_hw_unaligned_write_16(__u16 v, __le16* p) -{ - put_unaligned(cpu_to_le16(v), p); -} - -static inline __u32 ath5k_hw_unaligned_read_32(__le32 *p) -{ - return le32_to_cpu(get_unaligned(p)); -} - -static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p) -{ - put_unaligned(cpu_to_le32(v), p); -} - /* * Check if a register write has been completed */ commit cca3b8ecb67d8ee86b7287f3990915b72d3d618a Author: Jiri Slaby Date: Tue Jul 17 22:15:33 2007 +0200 remove double included linux/pci diff --git a/ath5k_hw.c b/ath5k_hw.c index f84c94c..9cd49fc 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -22,8 +22,6 @@ #include -#include - #include "ath5k.h" #include "ath5k_reg.h" commit d7a430a90058a987923fce5d0a4ecb27d3edec45 Author: Jiri Slaby Date: Tue Jul 17 22:27:35 2007 +0200 allow AR5K_DEBUG diff --git a/ath5k_hw.c b/ath5k_hw.c index 9cd49fc..f74fddc 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -410,7 +410,7 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, ath5k_hw_set_opmode(hal); #ifdef AR5K_DEBUG - hal->ah_dump_state(hal); + ath5k_hw_dump_state(hal); #endif /* @@ -5601,8 +5601,6 @@ ath5k_hw_dump_state(struct ath_hw *hal) AR5K_PRINT_REGISTER(DCU_FP); AR5K_PRINT_REGISTER(DCU_TXP); AR5K_PRINT_REGISTER(DCU_TX_FILTER); - AR5K_PRINT_REGISTER(RC); - AR5K_PRINT_REGISTER(SCR); AR5K_PRINT_REGISTER(INTPEND); AR5K_PRINT_REGISTER(PCICFG); AR5K_PRINT_REGISTER(GPIOCR); @@ -5638,8 +5636,6 @@ ath5k_hw_dump_state(struct ath_hw *hal) AR5K_PRINT_REGISTER(FCS_FAIL); AR5K_PRINT_REGISTER(BEACON_CNT); AR5K_PRINT_REGISTER(TSF_PARM); - AR5K_PRINT_REGISTER(RATE_DUR_0); - AR5K_PRINT_REGISTER(KEYTABLE_0); AR5K_PRINT("\n"); AR5K_PRINT("PHY registers:\n"); @@ -5657,7 +5653,6 @@ ath5k_hw_dump_state(struct ath_hw *hal) AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1); AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2); - AR5K_PRINT_REGISTER(PHY_FC); AR5K_PRINT_REGISTER(PHY_RADAR); AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); commit 9f55076a5d63e32aba592df0c1323b0d48032e27 Author: Jiri Slaby Date: Wed Jul 18 08:23:23 2007 +0200 ath5k_hw whitespace cleanup diff --git a/ath5k_hw.c b/ath5k_hw.c index f74fddc..80a6ca8 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -600,10 +600,9 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) /* * Get the PHY Chip revision */ -static u16 -ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) +static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) { - int i; + unsigned int i; u32 srev; u16 ret; @@ -633,12 +632,10 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) if (hal->ah_version == AR5K_AR5210) { srev = ath5k_hw_reg_read(hal, AR5K_PHY(256) >> 28) & 0xf; - - ret = (u16) ath5k_hw_bitswap(srev, 4) + 1; + ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; } else { srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff; - - ret = (u16) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); } /* Reset to the 5GHz mode */ @@ -651,15 +648,15 @@ ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) * Get the rate table for a specific operation mode * TODO:Limit this per chipset */ -const struct ath5k_rate_table * -ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, + unsigned int mode) { AR5K_TRACE; - /* Get rate tables */ if (!test_bit(mode, hal->ah_capabilities.cap_mode)) return NULL; + /* Get rate tables */ switch (mode) { case MODE_IEEE80211A: return &ath5k_rt_11a; @@ -671,8 +668,6 @@ ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode) return &ath5k_rt_11g; case MODE_ATHEROS_TURBOG: return &ath5k_rt_xr; - default: - return NULL; } return NULL; @@ -1018,13 +1013,12 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* Set antenna mode */ AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44), - hal->ah_antenna[ee_mode][0], 0xfffffc06); - - if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] = AR5K_ANT_FIXED_B; - else - ant[0] = ant[1] = AR5K_ANT_FIXED_A; + hal->ah_antenna[ee_mode][0], 0xfffffc06); + if (freq == AR5K_INI_RFGAIN_2GHZ) + ant[0] = ant[1] = AR5K_ANT_FIXED_B; + else + ant[0] = ant[1] = AR5K_ANT_FIXED_A; ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]], AR5K_PHY_ANT_SWITCH_TABLE_0); @@ -1067,8 +1061,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ, - AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, - ee->ee_margin_tx_rx[ee_mode]); + AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, + ee->ee_margin_tx_rx[ee_mode]); } } else { @@ -1152,8 +1146,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL, 0, false)) { - AR5K_PRINTF("calibration timeout (%uMHz)\n", - channel->freq); + AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq); return -EAGAIN; } @@ -1194,9 +1187,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (!(channel->val & CHANNEL_B)) { hal->ah_calibration = true; AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); + AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, - AR5K_PHY_IQ_RUN); + AR5K_PHY_IQ_RUN); } /* @@ -1250,8 +1243,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Disable beacons and reset the register */ - AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, - AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); + AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE | + AR5K_BEACON_RESET_TSF); return 0; } @@ -1281,11 +1274,8 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) val &= AR5K_RESET_CTL_CHIP; mask &= AR5K_RESET_CTL_CHIP; } else { - val &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; - - mask &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; } ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, false); @@ -1309,8 +1299,8 @@ static int ath5k_hw_nic_reset(struct ath_hw *hal, u32 val) int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration) { + unsigned int i; u32 staid; - int i; AR5K_TRACE; staid = ath5k_hw_reg_read(hal, AR5K_STA_ID1); @@ -1345,7 +1335,7 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, for (i = 5000; i > 0; i--) { /* Check if the chip did wake up */ if ((ath5k_hw_reg_read(hal, AR5K_PCICFG) & - AR5K_PCICFG_SPWR_DN) == 0) + AR5K_PCICFG_SPWR_DN) == 0) break; /* Wait a bit and retry */ @@ -1384,8 +1374,6 @@ ath5k_hw_get_power_mode(struct ath_hw *hal) } - - /***********************\ DMA Related Functions \***********************/ @@ -1507,8 +1495,8 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) { - int i = 100, pending; - u32 tx_queue; + unsigned int i = 100; + u32 tx_queue, pending; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1564,10 +1552,10 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) * Get the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) */ -u32 -ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) +u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) { u16 tx_reg; + AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1601,6 +1589,7 @@ ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) { u16 tx_reg; + AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1646,6 +1635,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) { u32 trigger_level, imr; bool status = false; + AR5K_TRACE; /* @@ -1814,7 +1804,7 @@ enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask) } /* - * Enalbe HW radar detection + * Enable HW radar detection */ void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) @@ -1833,13 +1823,10 @@ ath5k_hw_radar_alert(struct ath_hw *hal, bool enable) * possible radar activity. */ if (hal->ah_version == AR5K_AR5210) { - if (enable == true) { - AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, - AR5K_IMR_RXPHY); - } else { - AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, - AR5K_IMR_RXPHY); - } + if (enable == true) + AR5K_REG_ENABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); + else + AR5K_REG_DISABLE_BITS(hal, AR5K_IMR, AR5K_IMR_RXPHY); } else { /*Also set AR5K_PHY_RADAR register on 5111/5112*/ if (enable == true) { @@ -1891,8 +1878,8 @@ static int ath5k_hw_eeprom_read(struct ath_hw *hal, u32 offset, u16 *data) if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) return -EIO; - *data = (u16) - (ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & 0xffff); + *data = (u16)(ath5k_hw_reg_read(hal, AR5K_EEPROM_DATA) & + 0xffff); return 0; } udelay(15); @@ -1962,9 +1949,8 @@ static u16 ath5k_eeprom_bin2freq(struct ath_hw *hal, u16 bin, unsigned int mode) if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) val = (5 * bin) + 4800; else - val = bin > 62 ? - (10 * 62) + (5 * (bin - 62)) + 5100 : - (bin * 10) + 5100; + val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : + (bin * 10) + 5100; } else { if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) val = bin + 2300; @@ -2050,8 +2036,7 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, ee->ee_thr_62[mode] = val & 0xff; if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) - ee->ee_thr_62[mode] = - mode == AR5K_EEPROM_MODE_11A ? 15 : 28; + ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; AR5K_EEPROM_READ(o++, val); ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; @@ -2103,7 +2088,7 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, } if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && - mode == AR5K_EEPROM_MODE_11A) { + mode == AR5K_EEPROM_MODE_11A) { ee->ee_i_cal[mode] = (val >> 8) & 0x3f; ee->ee_q_cal[mode] = (val >> 3) & 0x1f; } @@ -2124,10 +2109,10 @@ static int ath5k_eeprom_read_modes(struct ath_hw *hal, u32 *offset, static int ath5k_eeprom_init(struct ath_hw *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + unsigned int mode, i; + int ret; u32 offset; u16 val; - int ret, i; - unsigned int mode; /* Initial TX thermal adjustment values */ ee->ee_tx_clip = 4; @@ -2197,8 +2182,7 @@ static int ath5k_eeprom_init(struct ath_hw *hal) */ mode = AR5K_EEPROM_MODE_11A; - ee->ee_turbo_max_power[mode] = - AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); + ee->ee_turbo_max_power[mode] = AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); @@ -2251,13 +2235,13 @@ static int ath5k_eeprom_init(struct ath_hw *hal) if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); } if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { @@ -2286,9 +2270,9 @@ static int ath5k_eeprom_init(struct ath_hw *hal) if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); AR5K_EEPROM_READ(offset++, val); ee->ee_turbo_max_power[mode] = val & 0x7f; @@ -2296,11 +2280,10 @@ static int ath5k_eeprom_init(struct ath_hw *hal) AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; - } AR5K_EEPROM_READ(offset++, val); ee->ee_i_cal[mode] = (val >> 8) & 0x3f; @@ -2336,8 +2319,7 @@ static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) if (ret) return ret; - for (offset = 0x1f, octet = 0, total = 0; - offset >= 0x1d; offset--) { + for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { ret = ath5k_hw_eeprom_read(hal, offset, &data); if (ret) return ret; @@ -2377,8 +2359,7 @@ static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_EEPROM_PROTECT_WR_128_191) return false; - if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, - ee_regdomain) != 0) + if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0) return false; hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; @@ -2548,8 +2529,7 @@ ath5k_hw_set_opmode(struct ath_hw *hal) /* * Get station id */ -void -ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) +void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac) { AR5K_TRACE; memcpy(mac, hal->ah_sta_id, ETH_ALEN); @@ -2610,7 +2590,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, } AR5K_REG_WRITE_BITS(hal, AR5K_BEACON, AR5K_BEACON_TIM, - tim_offset ? tim_offset + 4 : 0); + tim_offset ? tim_offset + 4 : 0); ath5k_hw_enable_pspoll(hal, NULL, 0); } @@ -2625,7 +2605,6 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) AR5K_TRACE; if (hal->ah_version == AR5K_AR5212) { - low_id = AR5K_LOW_ID(mask); high_id = AR5K_HIGH_ID(mask); @@ -2633,8 +2612,9 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); return true; - } else - return false; + } + + return false; } /* @@ -2687,13 +2667,12 @@ ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index) AR5K_TRACE; if (index >= 64) - return false; + return false; else if (index >= 32) - AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, - (1 << (index - 32))); + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER1, + (1 << (index - 32))); else - AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, - (1 << index)); + AR5K_REG_ENABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; } @@ -2707,13 +2686,12 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) AR5K_TRACE; if (index >= 64) - return false; + return false; else if (index >= 32) - AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, - (1 << (index - 32))); + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER1, + (1 << (index - 32))); else - AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, - (1 << index)); + AR5K_REG_DISABLE_BITS(hal, AR5K_MCAST_FILTER0, (1 << index)); return true; } @@ -2735,8 +2713,7 @@ ath5k_hw_get_rx_filter(struct ath_hw *hal) if (data & AR5K_PHY_ERR_FIL_RADAR) filter |= AR5K_RX_FILTER_PHYRADAR; - if (data & (AR5K_PHY_ERR_FIL_OFDM | - AR5K_PHY_ERR_FIL_CCK)) + if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) filter |= AR5K_RX_FILTER_PHYERR; } @@ -2758,8 +2735,7 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) if (filter & AR5K_RX_FILTER_PHYRADAR) data |= AR5K_PHY_ERR_FIL_RADAR; if (filter & AR5K_RX_FILTER_PHYERR) - data |= AR5K_PHY_ERR_FIL_OFDM | - AR5K_PHY_ERR_FIL_CCK; + data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; } /* @@ -2773,11 +2749,9 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) /*Zero length DMA*/ if (data) - AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, - AR5K_RXCFG_ZLFDMA); + AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); else - AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, - AR5K_RXCFG_ZLFDMA); + AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); /*Write RX Filter register*/ ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER); @@ -2826,7 +2800,7 @@ void ath5k_hw_reset_tsf(struct ath_hw *hal) */ void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, - u32 interval) + u32 interval) { u32 timer1, timer2, timer3; @@ -2852,8 +2826,7 @@ ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, 0x00000003; } - timer3 = next_beacon + - (hal->ah_atim_window ? hal->ah_atim_window : 1); + timer3 = next_beacon + (hal->ah_atim_window ? hal->ah_atim_window : 1); /* * Set the beacon register and enable all timers. @@ -2906,9 +2879,9 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * (Contention Free Period) and timer registers */ cfp_period = state->bs_cfp_period * state->bs_dtim_period * - state->bs_interval; + state->bs_interval; next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * - state->bs_interval; + state->bs_interval; AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, AR5K_STA_ID1_DEFAULT_ANTENNA | @@ -2945,8 +2918,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * setting value to a largest value and seeing which values register. */ - AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, - AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); + AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, + state->bs_bmiss_threshold); /* * Set sleep control register @@ -2960,21 +2933,21 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * Set enhanced sleep registers on 5212 */ if (hal->ah_version == AR5K_AR5212) { - if ((state->bs_sleep_duration > state->bs_interval) && - (roundup(state->bs_sleep_duration, interval) == - state->bs_sleep_duration)) + if (state->bs_sleep_duration > state->bs_interval && + roundup(state->bs_sleep_duration, interval) == + state->bs_sleep_duration) interval = state->bs_sleep_duration; - if (state->bs_sleep_duration > dtim && - (dtim == 0 || roundup(state->bs_sleep_duration, dtim) == - state->bs_sleep_duration)) + if (state->bs_sleep_duration > dtim && (dtim == 0 || + roundup(state->bs_sleep_duration, dtim) == + state->bs_sleep_duration)) dtim = state->bs_sleep_duration; if (interval > dtim) return; - next_beacon = interval == dtim ? - state->bs_next_dtim: state->bs_next_beacon; + next_beacon = interval == dtim ? state->bs_next_dtim : + state->bs_next_beacon; ath5k_hw_reg_write(hal, AR5K_REG_SM((state->bs_next_dtim - 3) << 3, @@ -3009,8 +2982,7 @@ ath5k_hw_reset_beacon(struct ath_hw *hal) * Disable some beacon register values */ AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_DEFAULT_ANTENNA | - AR5K_STA_ID1_PCF); + AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); ath5k_hw_reg_write(hal, AR5K_BEACON_PERIOD, AR5K_BEACON); } @@ -3021,8 +2993,8 @@ ath5k_hw_reset_beacon(struct ath_hw *hal) bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) { + unsigned int i; bool ret; - int i; AR5K_TRACE; @@ -3032,9 +3004,13 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) * Wait for beaconn queue to finish by checking * Control Register and Beacon Status Register. */ - for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && - (ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && - (ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); + for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) { + if (!(ath5k_hw_reg_read(hal, AR5K_BSR) & AR5K_BSR_TXQ1F) + || + !(ath5k_hw_reg_read(hal, AR5K_CR) & AR5K_BSR_TXQ1F)) + break; + udelay(10); + } /* Timeout... */ if (i <= 0) { @@ -3042,12 +3018,12 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) * Re-schedule the beacon queue */ ath5k_hw_reg_write(hal, phys_addr, AR5K_NOQCU_TXDP1); - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BCR); + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, + AR5K_BCR); return false; } - ret= true; - + ret = true; } else { /*5211/5212*/ ret = ath5k_hw_register_timeout(hal, @@ -3096,11 +3072,11 @@ ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), - hal->ah_turbo) <= timeout) + hal->ah_turbo) <= timeout) return false; AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, - ath5k_hw_htoclock(timeout, hal->ah_turbo)); + ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; } @@ -3112,8 +3088,9 @@ unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), - AR5K_TIME_OUT_ACK), hal->ah_turbo)); + + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, + AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), hal->ah_turbo)); } /* @@ -3124,11 +3101,11 @@ ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout) { AR5K_TRACE; if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), - hal->ah_turbo) <= timeout) + hal->ah_turbo) <= timeout) return false; AR5K_REG_WRITE_BITS(hal, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, - ath5k_hw_htoclock(timeout, hal->ah_turbo)); + ath5k_hw_htoclock(timeout, hal->ah_turbo)); return true; } @@ -3140,8 +3117,8 @@ unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal) { AR5K_TRACE; - return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, AR5K_TIME_OUT), - AR5K_TIME_OUT_CTS), hal->ah_turbo)); + return (ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(hal, + AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), hal->ah_turbo)); } /* @@ -3298,7 +3275,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, case AR5K_TX_QUEUE_XR_DATA: if (hal->ah_version != AR5K_AR5212) AR5K_PRINTF("XR data queues only " - "supported in 5212!"); + "supported in 5212!\n"); queue = AR5K_TX_QUEUE_ID_XR_DATA; break; default: @@ -3422,14 +3399,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; hal->ah_aifs = AR5K_TUNE_AIFS; /*XR is only supported on 5212*/ - if (IS_CHAN_XR(hal->ah_current_channel) - && (hal->ah_version == AR5K_AR5212)) { + if (IS_CHAN_XR(hal->ah_current_channel) && + hal->ah_version == AR5K_AR5212) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; hal->ah_aifs = AR5K_TUNE_AIFS_XR; /*B mode is not supported on 5210*/ - } else if (IS_CHAN_B(hal->ah_current_channel) - && (hal->ah_version != AR5K_AR5210)) { + } else if (IS_CHAN_B(hal->ah_current_channel) && + hal->ah_version != AR5K_AR5210) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; hal->ah_aifs = AR5K_TUNE_AIFS_11B; @@ -3439,12 +3416,10 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) while (cw_min < hal->ah_cw_min) cw_min = (cw_min << 1) | 1; - cw_min = tq->tqi_cw_min < 0 ? - (cw_min >> (-tq->tqi_cw_min)) : - ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); - cw_max = tq->tqi_cw_max < 0 ? - (cw_max >> (-tq->tqi_cw_max)) : - ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); + cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) : + ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); + cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) : + ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); /* * Calculate and set retry limits @@ -3452,9 +3427,8 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) if (hal->ah_software_retry == true) { /* XXX Need to test this */ retry_lg = hal->ah_limit_tx_retries; - retry_sh = retry_lg = - retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? - AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; + retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? + AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; } else { retry_lg = AR5K_INIT_LG_RETRY; retry_sh = AR5K_INIT_SH_RETRY; @@ -3509,7 +3483,8 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_CBR); if (tq->tqi_cbr_overflow_limit) - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, + AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_CBR_THRES_ENABLE); } @@ -3547,12 +3522,14 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) */ switch (tq->tqi_type) { case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, + AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_FRSHED_DBA_GT | AR5K_QCU_MISC_CBREXP_BCN | AR5K_QCU_MISC_BCN_ENABLE); - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), + AR5K_REG_ENABLE_BITS(hal, + AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << AR5K_DCU_MISC_ARBLOCK_CTL_S) | AR5K_DCU_MISC_POST_FR_BKOFF_DIS | @@ -3594,7 +3571,7 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXOK) | AR5K_REG_SM(hal->ah_txq_interrupts, - AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); + AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, @@ -3651,8 +3628,8 @@ ath5k_hw_get_slot_time(struct ath_hw *hal) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) - return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, AR5K_SLOT_TIME) & - 0xffff, hal->ah_turbo)); + return (ath5k_hw_clocktoh(ath5k_hw_reg_read(hal, + AR5K_SLOT_TIME) & 0xffff, hal->ah_turbo)); else return ath5k_hw_reg_read(hal, AR5K_DCU_GBL_IFS_SLOT) & 0xffff; } @@ -4120,29 +4097,24 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, * Frame receive status */ desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, + AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; + desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, + desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_OLD_RX_DESC_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, + AR5K_OLD_RX_DESC_STATUS0_MORE; + desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); desc->ds_us.rx.rs_status = 0; /* * Key table status */ - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) - desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, + if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) + desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); else desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; @@ -4150,10 +4122,9 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, /* * Receive/descriptor errors */ - if ((rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & - AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) + if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) + == 0) { + if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; if (rx_status->rx_status_1 & @@ -4201,19 +4172,16 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, */ desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & AR5K_NEW_RX_DESC_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); + desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); + desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA; desc->ds_us.rx.rs_more = rx_status->rx_status_0 & AR5K_NEW_RX_DESC_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); + desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, + AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); desc->ds_us.rx.rs_status = 0; /* @@ -4244,8 +4212,7 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; - if (rx_status->rx_status_1 & - AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) + if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } @@ -4253,8 +4220,6 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, } - - /****************\ GPIO Functions \****************/ @@ -4275,8 +4240,7 @@ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); else - AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, - AR5K_PCICFG_LED); + AR5K_REG_DISABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_LED); /* * Some blinking values, define at your wish @@ -4284,28 +4248,23 @@ void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state) switch (state) { case AR5K_LED_SCAN: case AR5K_LED_AUTH: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_PEND; - led_5210 = AR5K_PCICFG_LED_PEND| - AR5K_PCICFG_LED_BCTL; + led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND; + led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL; break; case AR5K_LED_INIT: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_NONE; + led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE; led_5210 = AR5K_PCICFG_LED_PEND; break; case AR5K_LED_ASSOC: case AR5K_LED_RUN: - led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_ASSOC; + led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC; led_5210 = AR5K_PCICFG_LED_ASSOC; break; default: - led = AR5K_PCICFG_LEDMODE_PROM | - AR5K_PCICFG_LED_NONE; + led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE; led_5210 = AR5K_PCICFG_LED_PEND; break; } @@ -4373,7 +4332,7 @@ int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val) return -EINVAL; /* GPIO output magic */ - data = ath5k_hw_reg_read(hal, AR5K_GPIODO); + data = ath5k_hw_reg_read(hal, AR5K_GPIODO); data &= ~(1 << gpio); data |= (val & 1) << gpio; @@ -4399,9 +4358,9 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, * Set the GPIO interrupt */ data = (ath5k_hw_reg_read(hal, AR5K_GPIOCR) & - ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | - AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | - (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); + ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | + AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | + (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); ath5k_hw_reg_write(hal, interrupt_level ? data : (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); @@ -4413,8 +4372,6 @@ void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, } - - /*********************************\ Regulatory Domain/Channels Setup \*********************************/ @@ -4489,7 +4446,8 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) /* * Set channel on RF5110 */ -static int ath5k_hw_rf5110_channel(struct ath_hw *hal, struct ieee80211_channel *channel) +static int ath5k_hw_rf5110_channel(struct ath_hw *hal, + struct ieee80211_channel *channel) { u32 data; @@ -4687,7 +4645,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal, * Disable beacons and RX/TX queues, wait */ AR5K_REG_ENABLE_BITS(hal, AR5K_DIAG_SW_5210, - AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); beacon = ath5k_hw_reg_read(hal, AR5K_BEACON_5210); ath5k_hw_reg_write(hal, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); @@ -4920,16 +4878,15 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits, for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { last = (position + left > 8) ? 8 : position + left; - mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << - (col * 8); + mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8); if (set == true) { rf[entry] &= ~mask; rf[entry] |= ((data << position) << (col * 8)) & mask; data >>= (8 - position); } else { - data = (((rf[entry] & mask) >> (col * 8)) >> - position) << shift; + data = (((rf[entry] & mask) >> (col * 8)) >> position) + << shift; shift += last - position; } @@ -4987,20 +4944,20 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) rf = hal->ah_rf_banks; if (hal->ah_radio == AR5K_RF5111) { - step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 6, 37, 0, false); + step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 6, 37, 0, + false); level[0] = 0; level[1] = (step == 0x3f) ? 0x32 : step + 4; level[2] = (step != 0x3f) ? 0x40 : level[0]; level[3] = level[2] + 0x32; hal->ah_gain.g_high = level[3] - - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); hal->ah_gain.g_low = level[0] + - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); } else { - mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], - 0, 1, 36, 0, false); + mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, + false); level[0] = level[2] = 0; if (mix == 1) { @@ -5011,10 +4968,10 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath_hw *hal) } } - return ((hal->ah_gain.g_current >= level[0] && - hal->ah_gain.g_current <= level[1]) || - (hal->ah_gain.g_current >= level[2] && - hal->ah_gain.g_current <= level[3])); + return (hal->ah_gain.g_current >= level[0] && + hal->ah_gain.g_current <= level[1]) || + (hal->ah_gain.g_current >= level[2] && + hal->ah_gain.g_current <= level[3]); } static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) @@ -5063,10 +5020,8 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) done: #ifdef AR5K_DEBUG AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", - ret, - hal->ah_gain.g_step_idx, - hal->ah_gain.g_current, - hal->ah_gain.g_target); + ret, hal->ah_gain.g_step_idx, hal->ah_gain.g_current, + hal->ah_gain.g_target); #endif return ret; @@ -5120,9 +5075,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); u32 *rf; - int i, obdb = -1, bank = -1; + const unsigned int rf_size = ARRAY_SIZE(rf5111_rf); + unsigned int i; + int obdb = -1, bank = -1; u32 ee_mode; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5165,10 +5121,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal, } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); + (channel->freq > 4000 ? 0 : -1))); if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_84, 1, 51, 3, true)) @@ -5219,12 +5175,12 @@ static int ath5k_hw_rf5111_rfregs(struct ath_hw *hal, static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int mode) { + const struct ath5k_ini_rf *rf_ini; struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - unsigned int rf_size; u32 *rf; - int i, obdb = -1, bank = -1; + unsigned int rf_size, i; + int obdb = -1, bank = -1; u32 ee_mode; - const struct ath5k_ini_rf *rf_ini; AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); @@ -5338,10 +5294,10 @@ static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, if (freq == AR5K_INI_RFGAIN_5GHZ) { /* For 11a and Turbo */ - obdb = channel->freq >= 5725 ? 3 : + obdb = channel->freq >= 5725 ? 3 : (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); } ob = ee->ee_ob[ee_mode][obdb]; @@ -5375,7 +5331,7 @@ static void ath5k_hw_ar5211_rfregs(struct ath_hw *hal, bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq) { - int i; + unsigned int i; switch (phy) { case AR5K_INI_PHY_5111: @@ -5449,10 +5405,11 @@ done: /* * Initialize the tx power table (not fully implemented) */ -static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *channel, s16 max_power) +static void ath5k_txpower_table(struct ath_hw *hal, + struct ieee80211_channel *channel, s16 max_power) { - u16 txpower, *rates; unsigned int i, min, max, n; + u16 txpower, *rates; rates = hal->ah_txpower.txp_rates; @@ -5487,7 +5444,8 @@ static void ath5k_txpower_table(struct ath_hw *hal, struct ieee80211_channel *ch * Set transmition power */ static int /*O.K. - txpower_table is unimplemented so this doesn't work*/ -ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned int txpower) +ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, + unsigned int txpower) { bool tpc = hal->ah_txpower.txp_tpc; unsigned int i; @@ -5510,8 +5468,8 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, unsigned */ for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { ath5k_hw_reg_write(hal, - ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) - | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff) ), + ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) | + (((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff), AR5K_PHY_PCDAC_TXPOWER(i)); } @@ -5724,8 +5682,7 @@ ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { AR5K_REG_DISABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_NO_PSPOLL | - AR5K_STA_ID1_DEFAULT_ANTENNA); + AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; } @@ -5738,8 +5695,7 @@ ath5k_hw_disable_pspoll(struct ath_hw *hal) AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { AR5K_REG_ENABLE_BITS(hal, AR5K_STA_ID1, - AR5K_STA_ID1_NO_PSPOLL | - AR5K_STA_ID1_DEFAULT_ANTENNA); + AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); return true; } commit a3eda4e3c3e5dd2f79111f8de0d9d09fc900e257 Author: Jiri Slaby Date: Thu Jul 19 07:26:12 2007 +0200 RX_FILTER cleanup (remove double defs) diff --git a/ath.c b/ath.c index 75c16bc..92090f1 100644 --- a/ath.c +++ b/ath.c @@ -37,6 +37,7 @@ #include #include "ath.h" +#include "ath5k_reg.h" #define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ #define ATH_DUMP_SKB 0 /* show skb contents */ @@ -457,19 +458,15 @@ static u32 ath_calcrxfilter(struct ath_softc *sc) struct ath_hw *ah = sc->ah; u32 rfilt; - rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERROR) | + rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERR) | AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | - AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_PHYRADAR; + AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_RADARERR; #ifdef BLE - if (ic->ic_opmode != IEEE80211_M_STA && - ic->ic_opmode != IEEE80211_M_AHDEMO) + if (opmode != IEEE80211_M_STA && opmode != IEEE80211_M_AHDEMO) rfilt |= AR5K_RX_FILTER_PROBEREQ; - if (ic->ic_opmode != IEEE80211_M_HOSTAP && - (dev->flags & IFF_PROMISC)) + if (opmode != IEEE80211_M_HOSTAP && (dev->flags & IFF_PROMISC)) rfilt |= AR5K_RX_FILTER_PROM; - if (ic->ic_opmode == IEEE80211_M_STA || - ic->ic_opmode == IEEE80211_M_IBSS || - state == IEEE80211_S_SCAN) + if (opmode == IEEE80211_M_STA || opmode == IEEE80211_M_IBSS || state == IEEE80211_S_SCAN) #endif rfilt |= AR5K_RX_FILTER_BEACON; diff --git a/ath5k.h b/ath5k.h index 6956326..cbab742 100644 --- a/ath5k.h +++ b/ath5k.h @@ -454,21 +454,6 @@ struct ath_rx_status { #define AR5K_RXKEYIX_INVALID ((u8) - 1) #define AR5K_TXKEYIX_INVALID ((u32) - 1) -/* - * RX filters - * Most of them are not yet used inside OpenHAL - */ -#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ -#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ -#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ -#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ -#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ -#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ -#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame */ -#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests */ -#define AR5K_RX_FILTER_PHYERROR 0x00000100 /* Don't filter phy errors */ -#define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ - struct ath5k_mib_stats { u32 ackrcv_bad; u32 rts_bad; diff --git a/ath5k_hw.c b/ath5k_hw.c index 80a6ca8..4cfafc8 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -2700,19 +2700,19 @@ ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index) * Get current rx filter */ u32 -ath5k_hw_get_rx_filter(struct ath_hw *hal) +ath5k_hw_get_rx_filter(struct ath_hw *ah) { u32 data, filter = 0; AR5K_TRACE; - filter = ath5k_hw_reg_read(hal, AR5K_RX_FILTER); + filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); /*Radar detection for 5212*/ - if (hal->ah_version == AR5K_AR5212) { - data = ath5k_hw_reg_read(hal, AR5K_PHY_ERR_FIL); + if (ah->ah_version == AR5K_AR5212) { + data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); if (data & AR5K_PHY_ERR_FIL_RADAR) - filter |= AR5K_RX_FILTER_PHYRADAR; + filter |= AR5K_RX_FILTER_RADARERR; if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) filter |= AR5K_RX_FILTER_PHYERR; } @@ -2724,15 +2724,15 @@ ath5k_hw_get_rx_filter(struct ath_hw *hal) * Set rx filter */ void -ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) +ath5k_hw_set_rx_filter(struct ath_hw *ah, u32 filter) { u32 data = 0; AR5K_TRACE; /* Set PHY error filter register on 5212*/ - if (hal->ah_version == AR5K_AR5212) { - if (filter & AR5K_RX_FILTER_PHYRADAR) + if (ah->ah_version == AR5K_AR5212) { + if (filter & AR5K_RX_FILTER_RADARERR) data |= AR5K_PHY_ERR_FIL_RADAR; if (filter & AR5K_RX_FILTER_PHYERR) data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; @@ -2741,24 +2741,24 @@ ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter) /* * The AR5210 uses promiscous mode to detect radar activity */ - if ((hal->ah_version == AR5K_AR5210) && - (filter & AR5K_RX_FILTER_PHYRADAR)) { - filter &= ~AR5K_RX_FILTER_PHYRADAR; + if (ah->ah_version == AR5K_AR5210 && + (filter & AR5K_RX_FILTER_RADARERR)) { + filter &= ~AR5K_RX_FILTER_RADARERR; filter |= AR5K_RX_FILTER_PROM; } /*Zero length DMA*/ if (data) - AR5K_REG_ENABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); + AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); else - AR5K_REG_DISABLE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); + AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); /*Write RX Filter register*/ - ath5k_hw_reg_write(hal, filter & 0xff, AR5K_RX_FILTER); + ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); /*Write PHY error filter register on 5212*/ - if (hal->ah_version == AR5K_AR5212) - ath5k_hw_reg_write(hal, data, AR5K_PHY_ERR_FIL); + if (ah->ah_version == AR5K_AR5212) + ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); } diff --git a/ath5k_reg.h b/ath5k_reg.h index e40706b..ec79bb7 100644 --- a/ath5k_reg.h +++ b/ath5k_reg.h @@ -1252,7 +1252,7 @@ */ #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ -#define AR5K_RX_FILTER (hal->ah_version == AR5K_AR5210 ? \ +#define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ #define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ @@ -1266,9 +1266,9 @@ #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ #define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ #define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ -#define AR5K_RX_FILTER_PHYERR (hal->ah_version == AR5K_AR5211 ? \ +#define AR5K_RX_FILTER_PHYERR (ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212) -#define AR5K_RX_FILTER_RADARERR (hal->ah_version == AR5K_AR5211 ? \ +#define AR5K_RX_FILTER_RADARERR (ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212) /* * Multicast filter register (lower 32 bits) commit 316fc03fe784c48140839968fd2c6fc7bb8b714a Author: Jiri Slaby Date: Thu Jul 19 08:25:15 2007 +0200 promisc diff --git a/ath.c b/ath.c index 92090f1..fedc3c3 100644 --- a/ath.c +++ b/ath.c @@ -456,18 +456,18 @@ next: static u32 ath_calcrxfilter(struct ath_softc *sc) { struct ath_hw *ah = sc->ah; + unsigned int opmode = IEEE80211_IF_TYPE_STA; u32 rfilt; rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERR) | AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_RADARERR; -#ifdef BLE - if (opmode != IEEE80211_M_STA && opmode != IEEE80211_M_AHDEMO) + + if (opmode != IEEE80211_IF_TYPE_STA) rfilt |= AR5K_RX_FILTER_PROBEREQ; - if (opmode != IEEE80211_M_HOSTAP && (dev->flags & IFF_PROMISC)) + if (opmode != IEEE80211_IF_TYPE_AP && sc->promisc) rfilt |= AR5K_RX_FILTER_PROM; - if (opmode == IEEE80211_M_STA || opmode == IEEE80211_M_IBSS || state == IEEE80211_S_SCAN) -#endif + if (opmode == IEEE80211_IF_TYPE_STA || opmode == IEEE80211_IF_TYPE_IBSS) rfilt |= AR5K_RX_FILTER_BEACON; return rfilt; @@ -1068,6 +1068,20 @@ static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) return ath_chan_set(sc, conf->chan); } +static void ath_set_multicast_list(struct ieee80211_hw *hw, + unsigned short flags, int mc_count) +{ + struct ath_softc *sc = hw->priv; + unsigned int prom = !!(flags & IFF_PROMISC); + u32 rfilt; + + if (sc->promisc != prom) { + sc->promisc = prom; + rfilt = ath_calcrxfilter(sc); + ath5k_hw_set_rx_filter(sc->ah, rfilt); + } +} + static int ath_set_key(struct ieee80211_hw *hw, set_key_cmd cmd, u8 *addr, struct ieee80211_key_conf *key, int aid) { @@ -1159,6 +1173,7 @@ static struct ieee80211_ops ath_hw_ops = { .remove_interface = NULL, .config = ath_config, .config_interface = NULL, + .set_multicast_list = ath_set_multicast_list, .set_key = ath_set_key, .get_stats = ath_get_stats, .conf_tx = NULL, diff --git a/ath.h b/ath.h index b496893..45b3a9f 100644 --- a/ath.h +++ b/ath.h @@ -148,6 +148,7 @@ struct ath_softc { #endif unsigned int invalid : 1, /* disable hardware accesses */ mrretry : 1, /* multi-rate retry support */ + promisc : 1, xxx:1; #ifdef BLE sc_splitmic: 1, /* split TKIP MIC keys */ diff --git a/ath5k_hw.c b/ath5k_hw.c index 4cfafc8..096f267 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -2723,8 +2723,7 @@ ath5k_hw_get_rx_filter(struct ath_hw *ah) /* * Set rx filter */ -void -ath5k_hw_set_rx_filter(struct ath_hw *ah, u32 filter) +void ath5k_hw_set_rx_filter(struct ath_hw *ah, u32 filter) { u32 data = 0; commit 30e00a40ea121bec2efac8a1748b96021d5353cf Author: Jiri Slaby Date: Thu Jul 19 08:28:14 2007 +0200 change BLE to BEACON in beacon related stuff diff --git a/ath.c b/ath.c index fedc3c3..847589b 100644 --- a/ath.c +++ b/ath.c @@ -669,7 +669,7 @@ static void ath_draintxq(struct ath_softc *sc) /* XXX return value */ if (likely(!sc->invalid)) { -#ifdef BLE +#ifdef BEACON /* don't touch the hardware if marked invalid */ (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, @@ -1563,7 +1563,11 @@ static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); - bf = kcalloc(ATH_TXBUF + ATH_RXBUF + /*ATH_BCBUF +*/ 1, + bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF +#ifdef BEACON + + ATH_BCBUF +#endif + , sizeof(struct ath_buf), GFP_KERNEL); if (bf == NULL) { dev_err(&pdev->dev, "can't allocate bufptr\n"); @@ -1586,7 +1590,7 @@ static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) bf->daddr = da; list_add_tail(&bf->list, &sc->txbuf); } -#ifdef BLE +#ifdef BEACON INIT_LIST_HEAD(&sc->bbuf); for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { bf->desc = ds; @@ -1630,7 +1634,7 @@ static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) kfree(sc->bufptr); sc->bufptr = NULL; } -#ifdef BLE +#ifdef BEACON static int ath_beaconq_setup(struct ath_hw *ah) { struct ath5k_txq_info qi; @@ -1762,7 +1766,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto err; } -#ifdef BLE +#ifdef BEACON /* * Allocate hardware transmit queues: one queue for * beacon frames and one data queue for each QoS @@ -1818,9 +1822,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ath5k_hw_set_gpio_output(ah, sc->led_pin); ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); } -#ifdef BLE - sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); - +#ifdef BEACON /* * Not all chips have the VEOL support we want to * use with IBSS beacons; check here for it. commit 9e53d5c1b01e5a1e20c41831c27efe6334144504 Author: Jiri Slaby Date: Thu Jul 19 08:36:49 2007 +0200 remove some unused stuff from ath.h diff --git a/ath.c b/ath.c index 847589b..c6dde74 100644 --- a/ath.c +++ b/ath.c @@ -482,7 +482,7 @@ static void ath_mode_init(struct ath_softc *sc) rfilt = ath_calcrxfilter(sc); ath5k_hw_set_rx_filter(ah, rfilt); - if (ath_hal_hasbssidmask(ah)) + if (ath5k_hw_hasbssidmask(ah)) ath5k_hw_set_bssid_mask(ah, sc->bssidmask); /* configure operational mode */ @@ -1832,7 +1832,7 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ath5k_hw_get_lladdr(ah, mac); SET_IEEE80211_PERM_ADDR(hw, mac); - if (ath_hal_hasbssidmask(ah)) { + if (ath5k_hw_hasbssidmask(ah)) { memset(sc->bssidmask, 0xff, ETH_ALEN); ath5k_hw_set_bssid_mask(ah, sc->bssidmask); } diff --git a/ath.h b/ath.h index 45b3a9f..2baa4aa 100644 --- a/ath.h +++ b/ath.h @@ -130,10 +130,8 @@ struct ath_softc { struct ieee80211_channel channels[ATH_CHAN_MAX]; struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_IEEE80211_MODES]; struct ath_hw *ah; /* Atheros HW */ -#ifdef BLE - enum ieee80211_if_types sc_opmode; - int sc_regdomain; - int sc_countrycode; +#ifdef UNUSED + enum ieee80211_if_types opmode; #endif int debug; @@ -142,39 +140,29 @@ struct ath_softc { dma_addr_t desc_daddr; /* DMA (physical) address */ size_t desc_len; /* size of TX/RX descriptors */ u16 cachelsz; /* cache line size */ -#ifdef BLE - struct ath_ratectrl *sc_rc; /* tx rate control support */ +#ifdef UNUSED void (*sc_setdefantenna)(struct ath_softc *, u_int); #endif unsigned int invalid : 1, /* disable hardware accesses */ mrretry : 1, /* multi-rate retry support */ - promisc : 1, - xxx:1; -#ifdef BLE - sc_splitmic: 1, /* split TKIP MIC keys */ - sc_needmib : 1, /* enable MIB stats intr */ + promisc : 1; +#ifdef UNUSED sc_diversity : 1,/* enable rx diversity */ - sc_lockslottime : 1,/* lock slot time value */ sc_hasveol : 1, /* tx VEOL support */ sc_mcastkey: 1, /* mcast key cache search */ sc_hasclrkey:1; /* CLR key supported */ /* rate tables */ - const struct ath5k_rate_table *sc_rates[NUM_IEEE80211_MODES]; - const struct ath5k_rate_table *sc_currates; /* current rate table */ #endif unsigned int curmode; /* current phy mode */ struct ieee80211_channel *curchan; /* current h/w channel */ -#ifdef BLE - u16 sc_curtxpow; /* current tx power limit */ - u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ -#endif + struct { u8 rxflags; /* radiotap rx flags */ u8 txflags; /* radiotap tx flags */ u16 ledon; /* softled on time */ u16 ledoff; /* softled off time */ } hwmap[32]; /* h/w rate ix mappings */ -#ifdef BLE +#ifdef UNUSED u8 sc_protrix; /* protection rate index */ u_int sc_txantenna; /* tx antenna (fixed or auto) */ #endif @@ -193,19 +181,7 @@ struct ath_softc { struct timer_list led_tim; /* led off timer */ u8 led_rxrate; /* current rx rate for LED */ u8 led_txrate; /* current tx rate for LED */ -#ifdef BLE - union { - struct ath_tx_radiotap_header th; - u8 pad[64]; - } u_tx_rt; - int sc_tx_th_len; - union { - struct ath_rx_radiotap_header th; - u8 pad[64]; - } u_rx_rt; - int sc_rx_th_len; - struct tasklet_struct sc_radartq; /* Radar detection */ -#endif + struct tasklet_struct restq; /* reset tasklet */ unsigned int rxbufsize; /* rx size based on mtu */ @@ -213,22 +189,20 @@ struct ath_softc { spinlock_t rxbuflock; u32 *rxlink; /* link ptr in last RX desc */ struct tasklet_struct rxtq; /* rx intr tasklet */ -#ifdef BLE +#ifdef UNUSED u8 sc_defant; /* current default antenna */ u8 sc_rxotherant; /* rx's on non-default antenna*/ #endif struct list_head txbuf; /* transmit buffer */ spinlock_t txbuflock; struct ath_txq txqs[2]; /* beacon and tx */ -#ifdef BLE - int sc_tx_timer; /* transmit timeout */ - u_int sc_txintrperiod;/* tx interrupt batching */ +#ifdef UNUSED struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ #endif struct ath_txq *txq; /* beacon and tx*/ struct tasklet_struct txtq; /* tx intr tasklet */ -#ifdef BLE +#ifdef BEACON struct list_head bbuf; /* beacon buffers */ unsigned int bhalq; /* HAL q for outgoing beacons */ u_int sc_bmisscount; /* missed beacon transmits */ @@ -237,43 +211,16 @@ struct ath_softc { struct ath_txq *cabq; /* tx q for cab frames */ struct tasklet_struct bmisstq; /* bmiss intr tasklet */ - struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ - enum { - OK, /* no change needed */ - UPDATE, /* update pending */ - COMMIT /* beacon sent, commit change */ - } sc_updateslot; /* slot time update fsm */ - - struct iw_statistics sc_iwstats; /* wireless statistics block */ +#endif +#ifdef UNUSED struct ctl_table_header *sc_sysctl_header; struct ctl_table *sc_sysctls; #endif struct timer_list calib_tim; /* calibration timer */ }; -void ath_sysctl_register(void); -void ath_sysctl_unregister(void); - -#define ath_hal_getcountrycode(_ah, _pcc) \ - (*(_pcc) = (_ah)->ah_country_code) -#define ath_hal_tkipsplit(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TKIP_SPLIT, 0, NULL) == 0) -#define ath_hal_hwphycounters(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_PHYCOUNTERS, 0, NULL) == 0) -#define ath_hal_getnumtxqueues(_ah, _pv) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_NUM_TXQUEUES, 0, _pv) == 0) -#define ath_hal_hasveol(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) -#define ath_hal_hastpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 0, NULL) == 0) -#define ath_hal_gettpc(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_TPC, 1, NULL) == 0) -#define ath_hal_settpc(_ah, _v) \ - ath5k_hw_set_capability(_ah, AR5K_CAP_TPC, 1, _v, NULL) -#define ath_hal_hasbursting(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_BURST, 0, NULL) == 0) -#define ath_hal_hasbssidmask(_ah) \ +#define ath5k_hw_hasbssidmask(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) #endif commit 7bf450afe8809a2dbe42f341930b6017dbf9e154 Author: Jiri Slaby Date: Thu Jul 19 08:41:35 2007 +0200 get rid of BLE eve in old if_ath.c diff --git a/ath/if_ath.c b/ath/if_ath.c index 57f48ac..d0a4b9e 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -83,7 +83,6 @@ static void ath_radar_tasklet(unsigned long data) { struct ieee80211_hw *hw = (void *)data; -#ifdef BLE struct ath_softc *sc = dev->priv; struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_channel *c; @@ -100,7 +99,6 @@ ath_radar_tasklet(unsigned long data) ic->ic_des_chan = c; ic->ic_ibss_chan = c; ieee80211_new_state (ic, IEEE80211_S_INIT, -1); -#endif ath_init(hw); } @@ -116,7 +114,6 @@ ath_rxorn_tasklet(unsigned long data) static void ath_bmiss_tasklet(unsigned long data) { -#ifdef BLE struct ieee80211_hw *dev = (void *)data; struct ath_softc *sc = dev->priv; struct ieee80211com *ic = &sc->sc_ic; @@ -150,13 +147,11 @@ ath_bmiss_tasklet(unsigned long data) IEEE80211_FC0_SUBTYPE_PROBE_REQ, 0); } } -#endif } #define NUM_RADIOTAP_ELEMENTS 18 -#ifdef BLE static int radiotap_elem_to_bytes[NUM_RADIOTAP_ELEMENTS] = {8, /* IEEE80211_RADIOTAP_TSFT */ 1, /* IEEE80211_RADIOTAP_FLAGS */ @@ -634,7 +629,7 @@ ath_setslottime(struct ath_softc *sc) } sc->sc_updateslot = OK; } -#ifdef BLE + /* * Callback from the 802.11 layer to update the * slot time based on the current setting. @@ -675,7 +670,6 @@ ath_beaconq_config(struct ath_softc *sc) qi.tqi_cw_min = ATH_BEACON_CWMIN_DEFAULT; qi.tqi_cw_max = ATH_BEACON_CWMAX_DEFAULT; } else { -#ifdef BLE struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; /* @@ -684,7 +678,6 @@ ath_beaconq_config(struct ath_softc *sc) qi.tqi_aifs = wmep->wmep_aifsn; qi.tqi_cw_min = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); qi.tqi_cw_max = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); -#endif } if (!ath5k_hw_setup_tx_queueprops(ah, sc->sc_bhalq, &qi)) { @@ -739,7 +732,7 @@ ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) return 0; // TODO: return value } -#endif + /* * Setup the beacon frame for transmit. */ @@ -794,12 +787,10 @@ ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, * Calculate rate code. * XXX everything at min xmit rate */ -#ifdef BLE if (USE_SHPREAMBLE(ic)) rate = an->an_tx_mgtratesp; else rate = an->an_tx_mgtrate; -#endif rate = 0; ah->ah_setup_tx_desc(ah, ds , skb->len + FCS_LEN /* frame length */ @@ -886,7 +877,6 @@ ath_beacon_send(struct net_device *dev) */ skb = bf->bf_skb; ncabq = sc->sc_cabq->axq_depth; -#ifdef BLE if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, skb, ncabq)) { DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: update, beacon len changed %d to %d\n", @@ -903,7 +893,6 @@ ath_beacon_send(struct net_device *dev) return; } } -#endif /* * Handle slot time change when a non-ERP station joins/leaves @@ -956,11 +945,10 @@ ath_beacon_send(struct net_device *dev) * * NB: only at DTIM */ -#ifdef BLE if (sc->sc_opmode == IEEE80211_IF_TYPE_AP && ncabq > 0 && sc->sc_boff.bo_tim[4] & 1) ath5k_hw_tx_start(ah, sc->sc_cabq->axq_qnum); -#endif + ath5k_hw_put_tx_buf(ah, sc->sc_bhalq, bf->bf_daddr); ath5k_hw_tx_start(ah, sc->sc_bhalq); DPRINTF(sc, ATH_DEBUG_BEACON_PROC, @@ -983,7 +971,7 @@ ath_bstuck_tasklet(unsigned long data) sc->sc_bmisscount); ath_reset(hw); } -#ifdef BLE + /* * Reclaim beacon resources. */ @@ -993,20 +981,19 @@ ath_beacon_free(struct ath_softc *sc) struct ath_buf *bf; bf = NULL; -// STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { + STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { if (bf->bf_skb != NULL) { bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); dev_kfree_skb(bf->bf_skb); bf->bf_skb = NULL; } -#ifdef BLE + if (bf->bf_node != NULL) { ieee80211_free_node(bf->bf_node); bf->bf_node = NULL; } -#endif -// } + } } /* @@ -1352,7 +1339,6 @@ ath_tx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) bad: dev_kfree_skb(skb); } -#endif /* * Add additional headers to a received frame and netif_rx it on @@ -1361,7 +1347,6 @@ ath_tx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) static void ath_rx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) { -#ifdef BLE #define IS_QOS_DATA(wh) \ ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK|IEEE80211_FC0_SUBTYPE_MASK))==\ (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) @@ -1507,7 +1492,6 @@ ath_rx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) dev_kfree_skb(skb); return; #undef IS_QOS_DATA -#endif } /* @@ -1527,7 +1511,7 @@ ath_tsf_extend(struct ath_hal *ah, uint32_t rstamp) return ((tsf & ~(uint64_t)0x7fff) | rstamp); } -#ifdef BLE + /* * Intercept management frames to collect beacon rssi data * and to do ibss merges. @@ -1591,7 +1575,7 @@ ath_recv_mgmt(struct ieee80211com *ic, struct sk_buff *skb, break; } } -#endif + /* * Set the default antenna. */ @@ -1608,7 +1592,6 @@ ath_setdefantenna(struct ath_softc *sc, u_int antenna) sc->sc_rxotherant = 0; } -#ifdef BLE /* * Update WME parameters for a transmit queue. */ @@ -1760,158 +1743,6 @@ ath_tx_tasklet(unsigned long data) netif_wake_queue(&sc->sc_rawdev); } -#endif - -#ifdef BLE -static int -ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) -{ - struct net_device *dev = ic->ic_dev; - struct ath_softc *sc = dev->priv; - struct ath_hal *ah = sc->sc_ah; - struct ieee80211_node *ni; - int i, error; - const u_int8_t *bssid; - u_int32_t rfilt; - static const AR5K_LED_STATE leds[] = { - AR5K_LED_INIT, /* IEEE80211_S_INIT */ - AR5K_LED_SCAN, /* IEEE80211_S_SCAN */ - AR5K_LED_AUTH, /* IEEE80211_S_AUTH */ - AR5K_LED_ASSOC, /* IEEE80211_S_ASSOC */ - AR5K_LED_RUN, /* IEEE80211_S_RUN */ - }; - - DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, - ieee80211_state_name[ic->ic_state], - ieee80211_state_name[nstate]); - - del_timer(&sc->sc_scan_ch); /* ap/neighbor scan timer */ - del_timer(&sc->sc_cal_ch); /* periodic calibration timer */ - ath5k_hw_set_ledstate(ah, leds[nstate]); /* set LED */ - netif_stop_queue(dev); /* before we do anything else */ - if (sc->sc_rawdev_enabled) - netif_stop_queue(&sc->sc_rawdev); - - if (nstate == IEEE80211_S_INIT) { - sc->sc_imask &= ~(AR5K_INT_SWBA | AR5K_INT_BMISS); - /* - * NB: disable interrupts so we don't rx frames. - */ - ath5k_hw_set_intr(ah, sc->sc_imask &~ AR5K_INT_GLOBAL); - /* - * Notify the rate control algorithm. - */ - ath_rate_newstate(sc, nstate); - goto done; - } - ni = ic->ic_bss; - error = ath_chan_set(sc, ni->ni_chan); - if (error != 0) - goto bad; - rfilt = ath_calcrxfilter(sc, nstate); - if (nstate == IEEE80211_S_SCAN) - bssid = dev->broadcast; - else - bssid = ni->ni_bssid; - ath5k_hw_set_rx_filter(ah, rfilt); - DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", - __func__, rfilt, ether_sprintf(bssid)); - - if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) - ath5k_hw_set_associd(ah, bssid, ni->ni_associd); - else - ath5k_hw_set_associd(ah, bssid, 0); - if (ic->ic_flags & IEEE80211_F_PRIVACY) { - for (i = 0; i < IEEE80211_WEP_NKID; i++) - if (ath5k_hw_is_key_valid(ah, i)) - ath5k_hw_set_key_lladdr(ah, i, bssid); - } - - /* - * Notify the rate control algorithm so rates - * are setup should ath_beacon_alloc be called. - */ - ath_rate_newstate(sc, nstate); - - if (ic->ic_opmode == IEEE80211_M_MONITOR) { - /* nothing to do */; - } else if (nstate == IEEE80211_S_RUN) { - DPRINTF(sc, ATH_DEBUG_STATE, - "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " - "capinfo=0x%04x chan=%d\n" - , __func__ - , ic->ic_flags - , ni->ni_intval - , ether_sprintf(ni->ni_bssid) - , ni->ni_capinfo - , ieee80211_chan2ieee(ic, ni->ni_chan)); - - /* - * Allocate and setup the beacon frame for AP or adhoc mode. - */ - switch (ic->ic_opmode) { - case IEEE80211_M_HOSTAP: - case IEEE80211_M_IBSS: - /* - * Allocate and setup the beacon frame. - * - * Stop any previous beacon DMA. This may be - * necessary, for example, when an ibss merge - * causes reconfiguration; there will be a state - * transition from RUN->RUN that means we may - * be called with beacon transmission active. - */ - ath5k_hw_stop_tx_dma(ah, sc->sc_bhalq); - ath_beacon_free(sc); - error = ath_beacon_alloc(sc, ni); - if (error != 0) - goto bad; - break; - case IEEE80211_M_STA: - /* - * Allocate a key cache slot to the station. - */ - if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && - sc->sc_hasclrkey && - ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) - ath_setup_stationkey(ni); - break; - default: - break; - } - - /* - * Configure the beacon and sleep timers. - */ - ath_beacon_config(sc); - } else { - ath5k_hw_set_intr(ah, - sc->sc_imask &~ (AR5K_INT_SWBA | AR5K_INT_BMISS)); - sc->sc_imask &= ~(AR5K_INT_SWBA | AR5K_INT_BMISS); - } -done: - /* - * Invoke the parent method to complete the work. - */ - error = sc->sc_newstate(ic, nstate, arg); - /* - * Finally, start any timers. - */ - if (nstate == IEEE80211_S_RUN) { - /* start periodic recalibration timer */ - mod_timer(&sc->sc_cal_ch, jiffies + (ath_calinterval * HZ)); - } else if (nstate == IEEE80211_S_SCAN) { - /* start ap/neighbor scan timer */ - mod_timer(&sc->sc_scan_ch, - jiffies + ((HZ * ath_dwelltime) / 1000)); - } -bad: - netif_start_queue(dev); - if (sc->sc_rawdev_enabled) - netif_start_queue(&sc->sc_rawdev); - - return error; -} /* * Allocate a key cache slot to the station so we can @@ -2123,7 +1954,6 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) if (dev->flags & IFF_RUNNING) ath_mode_init(dev); break; -#ifdef BLE case SIOCGATHSTATS: /* NB: embed these numbers to get a consistent view */ sc->sc_stats.ast_tx_packets = ic->ic_devstats->tx_packets; @@ -2136,7 +1966,6 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) else error = 0; break; -#endif case SIOCGATHDIAG: if (!capable(CAP_NET_ADMIN)) error = -EPERM; @@ -2150,7 +1979,6 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) error = ath_ioctl_ethtool(sc, cmd, ifr->ifr_data); break; default: -#ifdef BLE error = ieee80211_ioctlx(ic, ifr, cmd); if (error == -ENETRESET) { if (IS_RUNNING(dev) && @@ -2160,14 +1988,13 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) } if (error == -ERESTART) error = IS_RUNNING(dev) ? ath_reset(dev) : 0; -#endif break; } ATH_UNLOCK(sc); return error; #undef IS_RUNNING } -#endif + /* * Sysctls are split into ``static'' and ``dynamic'' tables. * The former are defined at module load time and are used @@ -2280,7 +2107,6 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, /* XXX validate? */ ath_hal_settpc(ah, val); break; -#ifdef BLE case ATH_TXPOWLIMIT: /* XXX validate? */ ic->ic_txpowlimit = val; @@ -2321,10 +2147,9 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, } ath_reset(&sc->sc_dev); break; -#endif case ATH_RXFILTER: sc->sc_rxfilter = val; -// ath_reset(sc->sc_dev); + ath_reset(sc->sc_dev); break; case ATH_RADARSIM: tasklet_schedule(&sc->sc_radartq); @@ -2387,9 +2212,8 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, val = sc->sc_hasveol; break; case ATH_BINTVAL: -// val = (sc->sc_ic).ic_lintval; + val = (sc->sc_ic).ic_lintval; break; -#ifdef BLE case ATH_RAWDEV: val = sc->sc_rawdev_enabled; break; @@ -2402,7 +2226,6 @@ ath_sysctl_halparam(ctl_table *ctl, int write, struct file *filp, val = 0; } break; -#endif case ATH_RXFILTER: val = sc->sc_rxfilter; break; @@ -2558,7 +2381,7 @@ ath_dynamic_sysctl_register(struct ath_softc *sc) sc->sc_sysctls[0].child = &sc->sc_sysctls[2]; /* [1] is NULL terminator */ sc->sc_sysctls[2].ctl_name = CTL_AUTO; - sc->sc_sysctls[2].procname = "BLE";//sc->sc_dev->name; + sc->sc_sysctls[2].procname = sc->sc_dev->name; sc->sc_sysctls[2].mode = 0555; sc->sc_sysctls[2].child = &sc->sc_sysctls[4]; /* [3] is NULL terminator */ @@ -2570,7 +2393,6 @@ ath_dynamic_sysctl_register(struct ath_softc *sc) for (i = 4; sc->sc_sysctls[i].ctl_name; i++) if (sc->sc_sysctls[i].extra1 == NULL) sc->sc_sysctls[i].extra1 = sc; -#ifdef BLE /* and register everything */ sc->sc_sysctl_header = ATH_REGISTER_SYSCTL_TABLE(sc->sc_sysctls); if (!sc->sc_sysctl_header) { @@ -2578,7 +2400,6 @@ ath_dynamic_sysctl_register(struct ath_softc *sc) kfree(sc->sc_sysctls); sc->sc_sysctls = NULL; } -#endif /* initialize values */ #ifdef AR_DEBUG sc->sc_debug = ath_debug; commit ff92cc39b82c5a033b648937477b21ec30e859a6 Author: Jiri Slaby Date: Thu Jul 19 08:43:21 2007 +0200 add cscope.out to .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..542264a --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +cscope.out commit 3fa7db9c47d55c691701a7cd34d11493c29850bb Author: Jiri Slaby Date: Sat Jul 21 11:50:09 2007 +0200 change ath_dump_skb second param to const char * diff --git a/ath.c b/ath.c index c6dde74..8d7cf57 100644 --- a/ath.c +++ b/ath.c @@ -144,13 +144,13 @@ static void ath_printtxbuf(struct ath_buf *bf, int done) #endif #if ATH_DUMP_SKB -static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) +static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) { - print_hex_dump_bytes(rx ? "r" : "t", DUMP_PREFIX_NONE, skb->data, + print_hex_dump_bytes(prefix, DUMP_PREFIX_NONE, skb->data, min(200U, skb->len)); } #else -static inline void ath_dump_skb(struct sk_buff *skb, unsigned int rx) {} +static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) {} #endif static void ath_tasklet_reset(unsigned long data) @@ -424,7 +424,7 @@ accept: rxs.flag |= ath_rx_decrypted(sc, ds, skb); // printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); - ath_dump_skb(skb, 1); + ath_dump_skb(skb, "r"); __ieee80211_rx(sc->hw, skb, &rxs); sc->led_rxrate = ds->ds_rxstat.rs_rate; @@ -970,7 +970,7 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, struct ath_buf *bf; unsigned long flags; - ath_dump_skb(skb, 0); + ath_dump_skb(skb, "t"); sc->led_txrate = ctl->tx_rate; commit bfaae2441d32f14130888743ab46a3dc88938b62 Author: Jiri Slaby Date: Sat Jul 21 11:51:01 2007 +0200 ath5k_hw_set_opmode whitespace cleanup diff --git a/ath5k_hw.c b/ath5k_hw.c index 096f267..0dae6a4 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -2480,27 +2480,27 @@ ath5k_hw_set_opmode(struct ath_hw *hal) switch (hal->ah_op_mode) { case IEEE80211_IF_TYPE_IBSS: - pcu_reg |= AR5K_STA_ID1_ADHOC | - AR5K_STA_ID1_DESC_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); - + pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA | + (hal->ah_version == AR5K_AR5210 ? + AR5K_STA_ID1_NO_PSPOLL : 0); beacon_reg |= AR5K_BCR_ADHOC; break; case IEEE80211_IF_TYPE_AP: - pcu_reg |= AR5K_STA_ID1_AP | - AR5K_STA_ID1_RTS_DEF_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); - + pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA | + (hal->ah_version == AR5K_AR5210 ? + AR5K_STA_ID1_NO_PSPOLL : 0); beacon_reg |= AR5K_BCR_AP; break; case IEEE80211_IF_TYPE_STA: pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_PWR_SV :0); + (hal->ah_version == AR5K_AR5210 ? + AR5K_STA_ID1_PWR_SV : 0); case IEEE80211_IF_TYPE_MNTR: pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | - (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); + (hal->ah_version == AR5K_AR5210 ? + AR5K_STA_ID1_NO_PSPOLL : 0); break; default: commit f0a19ade9dc1c5707681bb0b7fb934e9a6f3dcd3 Author: Jiri Slaby Date: Sat Jul 21 11:52:28 2007 +0200 add opmode to softc diff --git a/ath.c b/ath.c index 8d7cf57..e6eb3ec 100644 --- a/ath.c +++ b/ath.c @@ -456,7 +456,7 @@ next: static u32 ath_calcrxfilter(struct ath_softc *sc) { struct ath_hw *ah = sc->ah; - unsigned int opmode = IEEE80211_IF_TYPE_STA; + unsigned int opmode = sc->opmode; u32 rfilt; rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERR) | @@ -542,7 +542,7 @@ static int ath_init(struct ath_softc *sc) mutex_lock(&sc->lock); -// DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); /* * Stop anything previously setup. This is safe @@ -558,7 +558,7 @@ static int ath_init(struct ath_softc *sc) * and then setup of the interrupt mask. */ sc->curchan = sc->hw->conf.chan; - ret = ath5k_hw_reset(sc->ah, IEEE80211_IF_TYPE_STA, sc->curchan, false); + ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false); if (ret) { printk(KERN_ERR "unable to reset hardware: %d\n", ret); goto done; @@ -866,7 +866,7 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) ath5k_hw_set_intr(ah, 0); /* disable interrupts */ ath_draintxq(sc); /* clear pending tx frames */ ath_stoprecv(sc); /* turn off frame recv */ - ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, chan, true); + ret = ath5k_hw_reset(ah, sc->opmode, chan, true); if (ret) { printk(KERN_ERR "%s: unable to reset channel %u " "(%u Mhz)\n", __func__, chan->chan, chan->freq); @@ -1022,7 +1022,7 @@ static int ath_reset(struct ieee80211_hw *hw) ath_draintxq(sc); ath_stoprecv(sc); - ret = ath5k_hw_reset(ah, IEEE80211_IF_TYPE_STA, sc->curchan, true); + ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true); if (unlikely(ret)) { printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); goto err; @@ -1984,6 +1984,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, sc->invalid = 1; sc->iobase = mem; sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ + sc->opmode = IEEE80211_IF_TYPE_STA; mutex_init(&sc->lock); spin_lock_init(&sc->rxbuflock); spin_lock_init(&sc->txbuflock); diff --git a/ath.h b/ath.h index 2baa4aa..c616a3e 100644 --- a/ath.h +++ b/ath.h @@ -129,10 +129,9 @@ struct ath_softc { struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; struct ieee80211_channel channels[ATH_CHAN_MAX]; struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_IEEE80211_MODES]; - struct ath_hw *ah; /* Atheros HW */ -#ifdef UNUSED enum ieee80211_if_types opmode; -#endif + struct ath_hw *ah; /* Atheros HW */ + int debug; struct ath_buf *bufptr; /* allocated buffer ptr */ commit 7f972e2fc41b51603ff2a17184be6f633af636d4 Author: Jiri Slaby Date: Sun Jul 22 08:26:07 2007 +0200 remove raw and net80211 stuff diff --git a/ath/if_ath.c b/ath/if_ath.c index d0a4b9e..661f571 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -1193,390 +1193,6 @@ ath_beacon_config(struct ath_softc *sc) } /* - * Add additional headers to a transmitted frame and netif_rx it on - * a monitor or raw device - */ -static void -ath_tx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) -{ - struct ath_softc *sc = dev->priv; - u_int32_t tsf; - - /* - * release the owner of this skb since we're basically - * recycling it - */ - if (atomic_read(&skb->users) != 1) { - struct sk_buff *skb2 = skb; - skb = skb_clone(skb, GFP_ATOMIC); - if (skb == NULL) { - dev_kfree_skb(skb2); - return; - } - kfree_skb(skb2); - } else { - skb_orphan(skb); - } - - switch (dev->type) { - case ARPHRD_IEEE80211: - break; - case ARPHRD_IEEE80211_PRISM: { - wlan_ng_prism2_header *ph; - if (skb_headroom(skb) < sizeof(wlan_ng_prism2_header) && - pskb_expand_head(skb, - sizeof(wlan_ng_prism2_header), - 0, GFP_ATOMIC)) { - DPRINTF(sc, ATH_DEBUG_RECV, - "%s: couldn't pskb_expand_head\n", __func__); - goto bad; - } - - ph = (wlan_ng_prism2_header *) - skb_push(skb, sizeof(wlan_ng_prism2_header)); - memset(ph, 0, sizeof(wlan_ng_prism2_header)); - - ph->msgcode = DIDmsg_lnxind_wlansniffrm; - ph->msglen = sizeof(wlan_ng_prism2_header); - strcpy(ph->devname, sc->sc_dev.name); - - ph->hosttime.did = DIDmsg_lnxind_wlansniffrm_hosttime; - ph->hosttime.status = 0; - ph->hosttime.len = 4; - ph->hosttime.data = jiffies; - - /* Pass up tsf clock in mactime */ - ph->mactime.did = DIDmsg_lnxind_wlansniffrm_mactime; - ph->mactime.status = 0; - ph->mactime.len = 4; - /* - * Rx descriptor has the low 15 bits of the tsf at - * the time the frame was received. Use the current - * tsf to extend this to 32 bits. - */ - tsf = ath5k_hw_get_tsf32(sc->sc_ah); - if ((tsf & 0x7fff) < ds->ds_rxstat.rs_tstamp) - tsf -= 0x8000; - ph->mactime.data = ds->ds_rxstat.rs_tstamp | (tsf &~ 0x7fff); - - ph->istx.did = DIDmsg_lnxind_wlansniffrm_istx; - ph->istx.status = 0; - ph->istx.len = 4; - ph->istx.data = P80211ENUM_truth_true; - - ph->frmlen.did = DIDmsg_lnxind_wlansniffrm_frmlen; - ph->frmlen.status = 0; - ph->frmlen.len = 4; - ph->frmlen.data = ds->ds_rxstat.rs_datalen; - - ph->channel.did = DIDmsg_lnxind_wlansniffrm_channel; - ph->channel.status = 0; - ph->channel.len = 4; - ph->channel.data = ieee80211_mhz2ieee(ic->ic_ibss_chan->ic_freq,0); - - ph->rssi.did = DIDmsg_lnxind_wlansniffrm_rssi; - ph->rssi.status = 0; - ph->rssi.len = 4; - ph->rssi.data = ds->ds_rxstat.rs_rssi; - - ph->noise.did = DIDmsg_lnxind_wlansniffrm_noise; - ph->noise.status = 0; - ph->noise.len = 4; - ph->noise.data = -95; - - ph->signal.did = DIDmsg_lnxind_wlansniffrm_signal; - ph->signal.status = 0; - ph->signal.len = 4; - ph->signal.data = -95 + ds->ds_rxstat.rs_rssi; - - ph->rate.did = DIDmsg_lnxind_wlansniffrm_rate; - ph->rate.status = 0; - ph->rate.len = 4; - ph->rate.data = sc->sc_hwmap[ds->ds_txstat.ts_rate &~ AR5K_TXSTAT_ALTRATE].ieeerate; - break; - } - case ARPHRD_IEEE80211_RADIOTAP: { - struct ath_tx_radiotap_header *th; - - if (skb_headroom(skb) < sizeof(struct ath_tx_radiotap_header) && - pskb_expand_head(skb, - sizeof(struct ath_tx_radiotap_header), - 0, GFP_ATOMIC)) { - DPRINTF(sc, ATH_DEBUG_RECV, - "%s: couldn't pskb_expand_head\n", __func__); - goto bad; - } - - th = (struct ath_tx_radiotap_header *) skb_push(skb, sizeof(struct ath_tx_radiotap_header)); - memset(th, 0, sizeof(struct ath_tx_radiotap_header)); - th->wt_ihdr.it_version = 0; - th->wt_ihdr.it_len = cpu_to_le16(sizeof(struct ath_tx_radiotap_header)); - th->wt_ihdr.it_present = cpu_to_le32(ATH_TX_RADIOTAP_PRESENT); - th->wt_flags = 0; - th->wt_rate = sc->sc_hwmap[ds->ds_txstat.ts_rate &~ AR5K_TXSTAT_ALTRATE].ieeerate; - th->wt_txpower = 0; - th->wt_antenna = ds->ds_txstat.ts_antenna; - th->wt_tx_flags = 0; - if (ds->ds_txstat.ts_status) - th->wt_tx_flags |= cpu_to_le16(IEEE80211_RADIOTAP_F_TX_FAIL); - th->wt_rts_retries = ds->ds_txstat.ts_shortretry; - th->wt_data_retries = ds->ds_txstat.ts_longretry; - - break; - } - default: - break; - } - - skb->dev = dev; - skb_reset_mac_header(skb); - skb->ip_summed = CHECKSUM_NONE; - skb->pkt_type = PACKET_OTHERHOST; - skb->protocol = __constant_htons(0x0019); /* ETH_P_80211_RAW */ - netif_rx(skb); - return; - - bad: - dev_kfree_skb(skb); -} - -/* - * Add additional headers to a received frame and netif_rx it on - * a monitor or raw device - */ -static void -ath_rx_capture(struct net_device *dev, struct ath_desc *ds, struct sk_buff *skb) -{ -#define IS_QOS_DATA(wh) \ - ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK|IEEE80211_FC0_SUBTYPE_MASK))==\ - (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) - struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; - int len = ds->ds_rxstat.rs_datalen; - struct ieee80211_frame *wh; - u_int32_t tsf; - - KASSERT(ic->ic_flags & IEEE80211_F_DATAPAD, - ("data padding not enabled?")); - /* Remove pad bytes */ - wh = (struct ieee80211_frame *) skb->data; - if (IS_QOS_DATA(wh)) { - int headersize = ieee80211_hdrsize(wh); - int padbytes = roundup(headersize,4) - headersize; - - /* - * Copy up 802.11 header and strip h/w padding. - */ - if (padbytes > 0) { - memmove(skb->data + padbytes, skb->data, headersize); - skb_pull(skb, padbytes); - len -= padbytes; - } - } - - switch (dev->type) { - case ARPHRD_IEEE80211: - break; - case ARPHRD_IEEE80211_PRISM: { - wlan_ng_prism2_header *ph; - if (skb_headroom(skb) < sizeof(wlan_ng_prism2_header)) { - DPRINTF(sc, ATH_DEBUG_RECV, - "%s: prism not enough headroom %d/%d\n", - __func__, skb_headroom(skb), - (int)sizeof(wlan_ng_prism2_header)); - goto bad; - } - ph = (wlan_ng_prism2_header *) - skb_push(skb, sizeof(wlan_ng_prism2_header)); - memset(ph, 0, sizeof(wlan_ng_prism2_header)); - - ph->msgcode = DIDmsg_lnxind_wlansniffrm; - ph->msglen = sizeof(wlan_ng_prism2_header); - strcpy(ph->devname, sc->sc_dev.name); - - ph->hosttime.did = DIDmsg_lnxind_wlansniffrm_hosttime; - ph->hosttime.status = 0; - ph->hosttime.len = 4; - ph->hosttime.data = jiffies; - - /* Pass up tsf clock in mactime */ - ph->mactime.did = DIDmsg_lnxind_wlansniffrm_mactime; - ph->mactime.status = 0; - ph->mactime.len = 4; - /* - * Rx descriptor has the low 15 bits of the tsf at - * the time the frame was received. Use the current - * tsf to extend this to 32 bits. - */ - tsf = ath5k_hw_get_tsf32(sc->sc_ah); - if ((tsf & 0x7fff) < ds->ds_rxstat.rs_tstamp) - tsf -= 0x8000; - ph->mactime.data = ds->ds_rxstat.rs_tstamp | (tsf &~ 0x7fff); - - ph->istx.did = DIDmsg_lnxind_wlansniffrm_istx; - ph->istx.status = 0; - ph->istx.len = 4; - ph->istx.data = P80211ENUM_truth_false; - - ph->frmlen.did = DIDmsg_lnxind_wlansniffrm_frmlen; - ph->frmlen.status = 0; - ph->frmlen.len = 4; - ph->frmlen.data = len; - - ph->channel.did = DIDmsg_lnxind_wlansniffrm_channel; - ph->channel.status = 0; - ph->channel.len = 4; - ph->channel.data = ieee80211_mhz2ieee(ic->ic_ibss_chan->ic_freq,0); - - ph->rssi.did = DIDmsg_lnxind_wlansniffrm_rssi; - ph->rssi.status = 0; - ph->rssi.len = 4; - ph->rssi.data = ds->ds_rxstat.rs_rssi; - - ph->noise.did = DIDmsg_lnxind_wlansniffrm_noise; - ph->noise.status = 0; - ph->noise.len = 4; - ph->noise.data = -95; - - ph->signal.did = DIDmsg_lnxind_wlansniffrm_signal; - ph->signal.status = 0; - ph->signal.len = 4; - ph->signal.data = -95 + ds->ds_rxstat.rs_rssi; - - ph->rate.did = DIDmsg_lnxind_wlansniffrm_rate; - ph->rate.status = 0; - ph->rate.len = 4; - ph->rate.data = sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate; - break; - } - case ARPHRD_IEEE80211_RADIOTAP: { - struct ath_rx_radiotap_header *th; - if (skb_headroom(skb) < sizeof(struct ath_rx_radiotap_header)) { - DPRINTF(sc, ATH_DEBUG_RECV, - "%s: radiotap not enough headroom %d/%d\n", - __func__, skb_headroom(skb), - (int)sizeof(struct ath_rx_radiotap_header)); - goto bad; - } - th = (struct ath_rx_radiotap_header *) skb_push(skb, sizeof(struct ath_rx_radiotap_header)); - memset(th, 0, sizeof(struct ath_rx_radiotap_header)); - - th->wr_ihdr.it_version = 0; - th->wr_ihdr.it_len = cpu_to_le16(sizeof(struct ath_rx_radiotap_header)); - th->wr_ihdr.it_present = cpu_to_le32(ATH_RX_RADIOTAP_PRESENT); - th->wr_flags = IEEE80211_RADIOTAP_F_FCS; - th->wr_rate = sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate; - th->wr_chan_freq = cpu_to_le16(ic->ic_ibss_chan->ic_freq); - th->wr_chan_flags = cpu_to_le16(ic->ic_ibss_chan->ic_flags); - th->wr_antenna = ds->ds_rxstat.rs_antenna; - th->wr_antsignal = ds->ds_rxstat.rs_rssi; - if (ds->ds_rxstat.rs_status & AR5K_RXERR_CRC) - th->wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; - - break; - } - default: - break; - } - - skb->dev = dev; - skb_reset_mac_header(skb); - skb->ip_summed = CHECKSUM_NONE; - skb->pkt_type = PACKET_OTHERHOST; - skb->protocol = __constant_htons(0x0019); /* ETH_P_80211_RAW */ - - netif_rx(skb); - return; - - bad: - dev_kfree_skb(skb); - return; -#undef IS_QOS_DATA -} - -/* - * Extend 15-bit time stamp from rx descriptor to - * a full 64-bit TSF using the current h/w TSF. - */ -static inline uint64_t -ath_tsf_extend(struct ath_hal *ah, uint32_t rstamp) -{ - uint64_t tsf; - - tsf = ath5k_hw_get_tsf64(ah); - - /* Compensate for rollover. */ - if ((tsf & 0x7fff) < rstamp) - tsf -= 0x8000; - - return ((tsf & ~(uint64_t)0x7fff) | rstamp); -} - -/* - * Intercept management frames to collect beacon rssi data - * and to do ibss merges. - */ -static void -ath_recv_mgmt(struct ieee80211com *ic, struct sk_buff *skb, - struct ieee80211_node *ni, - int subtype, int rssi, u_int32_t rstamp) -{ - struct ath_softc *sc = ic->ic_dev->priv; - - /* - * Call up first so subsequent work can use information - * potentially stored in the node (e.g. for ibss merge). - */ - sc->sc_recv_mgmt(ic, skb, ni, subtype, rssi, rstamp); - - switch (subtype) { - case IEEE80211_FC0_SUBTYPE_BEACON: - /* update rssi statistics for use by the hal */ - ATH_RSSI_LPF((ATH_NODE(ni))->an_halstats.ns_avgbrssi, rssi); - /* fall thru... */ - case IEEE80211_FC0_SUBTYPE_PROBE_RESP: - if (ic->ic_opmode == IEEE80211_M_IBSS && - ic->ic_state == IEEE80211_S_RUN) { - /* Extend rstamp with the current tsf to 64 bit */ - u_int64_t tsf = ath_tsf_extend(sc->sc_ah, rstamp); - /* - * Handle ibss merge as needed; check the tsf on the - * frame before attempting the merge. The 802.11 spec - * says the station should change it's bssid to match - * the oldest station with the same ssid, where oldest - * is determined by the tsf. Note that hardware - * reconfiguration happens through callback to - * ath_newstate as the state machine will go from - * RUN -> RUN when this happens. - */ - if (le64toh(ni->ni_tstamp.tsf) >= tsf) { - DPRINTF(sc, ATH_DEBUG_STATE, - "ibss merge, rstamp %u tsf %llx " - "tstamp %llx\n", rstamp, tsf, - ni->ni_tstamp.tsf); - ieee80211_ibss_merge(ni); - } - } - if (ic->ic_opmode == IEEE80211_M_STA && - ic->ic_state == IEEE80211_S_RUN && - sc->sc_bmisscount > 0) { - struct ieee80211_frame *wh; - wh = (struct ieee80211_frame *) skb->data; - if (IEEE80211_ADDR_EQ(wh->i_addr2, ic->ic_bss->ni_bssid)) { - DPRINTF(sc, ATH_DEBUG_BEACON, - "[%s] received %s after beacon miss - clear\n", - ether_sprintf(wh->i_addr2), - (subtype == IEEE80211_FC0_SUBTYPE_BEACON) ? - "beacon" : "probe response"); - sc->sc_bmisscount = 0; - ic->ic_mgt_timer = 0; - } - } - break; - } -} - -/* * Set the default antenna. */ static void commit 8463b61ab61c19e31a82ff8e015c954537a62bd2 Author: Jiri Slaby Date: Tue Jul 24 08:49:28 2007 +0200 don't process packets with bad crc diff --git a/ath.c b/ath.c index e6eb3ec..d2c9214 100644 --- a/ath.c +++ b/ath.c @@ -387,7 +387,8 @@ static void ath_tasklet_rx(unsigned long data) * XXX do key cache faulting */ if (ds->ds_rxstat.rs_keyix == - AR5K_RXKEYIX_INVALID) + AR5K_RXKEYIX_INVALID && + !(stat & AR5K_RXERR_CRC)) goto accept; sc->stats.ast_rx_badcrypt++; } commit 7af729b5d56fbe45abf466b656ccab65aa6f6646 Author: Jiri Slaby Date: Tue Jul 24 08:51:32 2007 +0200 add unaligned access macros diff --git a/ath.c b/ath.c index d2c9214..81cd577 100644 --- a/ath.c +++ b/ath.c @@ -35,6 +35,7 @@ #include #include +#include #include "ath.h" #include "ath5k_reg.h" @@ -43,6 +44,10 @@ #define ATH_DUMP_SKB 0 /* show skb contents */ #define AR_DEBUG 1 +/* unaligned little endian access */ +#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) +#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) + #if AR_DEBUG #define DPRINTF(sc, _m, _fmt...) do { \ if (unlikely(((sc)->debug & (_m)) && net_ratelimit())) \ commit 0502eaf38feecbf979967a5cb35e16358ad08355 Author: Jiri Slaby Date: Tue Jul 24 08:53:26 2007 +0200 some whitespaces diff --git a/ath.c b/ath.c index 81cd577..c7a7a20 100644 --- a/ath.c +++ b/ath.c @@ -545,7 +545,7 @@ static int ath_stop_locked(struct ath_softc *); static int ath_init(struct ath_softc *sc) { int ret; - + mutex_lock(&sc->lock); DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); @@ -693,7 +693,7 @@ static void ath_draintxq(struct ath_softc *sc) } } ieee80211_start_queues(sc->hw); /* XXX move to callers */ - + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) if (sc->txqs[i].setup) ath_tx_draintxq(sc, &sc->txqs[i]); @@ -857,7 +857,7 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) { struct ath_hw *ah = sc->ah; int ret; - + DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", __func__, sc->curchan->chan, sc->curchan->freq, chan->chan, chan->freq); @@ -1016,7 +1016,7 @@ static int ath_reset(struct ieee80211_hw *hw) struct ath_softc *sc = hw->priv; struct ath_hw *ah = sc->ah; int ret; - + DPRINTF(sc, ATH_DEBUG_RESET, "resetting\n"); /* * Convert to a HAL channel description with the flags @@ -1027,7 +1027,7 @@ static int ath_reset(struct ieee80211_hw *hw) ath5k_hw_set_intr(ah, 0); ath_draintxq(sc); ath_stoprecv(sc); - + ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true); if (unlikely(ret)) { printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); @@ -1861,7 +1861,7 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; - /* + /* * NB: the order of these is important: * o call the 802.11 layer before detaching the hal to * insure callbacks into the driver to delete global @@ -1998,7 +1998,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, pci_set_drvdata(pdev, hw); ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc); - if (ret) { + if (ret) { dev_err(&pdev->dev, "request_irq failed\n"); goto err_free; } @@ -2058,7 +2058,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct ath_softc *sc = hw->priv; - if (sc->led_soft) + if (sc->led_soft) ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); ath_stop_hw(sc); commit 30cbbf781ec11d88d4ccc73b4cca977891289dbb Author: Jiri Slaby Date: Tue Jul 24 08:56:56 2007 +0200 add ath5k_hw_hasveol diff --git a/ath.h b/ath.h index c616a3e..b83ec04 100644 --- a/ath.h +++ b/ath.h @@ -221,5 +221,7 @@ struct ath_softc { #define ath5k_hw_hasbssidmask(_ah) \ (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) +#define ath5k_hw_hasveol(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) #endif commit d7aa6b9a2a43ddbf4f55b55a198cb2b91b2b565a Author: Jiri Slaby Date: Tue Jul 24 12:22:25 2007 +0200 sync dma descriptors diff --git a/ath.c b/ath.c index c7a7a20..510f5e6 100644 --- a/ath.c +++ b/ath.c @@ -177,6 +177,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) list_for_each_entry_safe(bf, bf0, &txq->q, list) { ds = bf->desc; + /* TODO only one segment */ + pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, + sc->desc_len, PCI_DMA_FROMDEVICE); ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); if (unlikely(ret == -EINPROGRESS)) break; @@ -349,6 +352,11 @@ static void ath_tasklet_rx(unsigned long data) BUG_ON(bf->skb == NULL); skb = bf->skb; ds = bf->desc; + + /* TODO only one segment */ + pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, + sc->desc_len, PCI_DMA_FROMDEVICE); + if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */ break; commit 5f100878786d6f12836a8c771012a7c9aa89f5e4 Author: Jiri Slaby Date: Tue Jul 24 12:26:01 2007 +0200 correct stopping/waking tx queues diff --git a/ath.c b/ath.c index 510f5e6..5a7fc36 100644 --- a/ath.c +++ b/ath.c @@ -217,11 +217,14 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) spin_lock(&sc->txbuflock); sc->tx_stats.data[txq->qnum].len--; list_move_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; spin_unlock(&sc->txbuflock); } if (likely(list_empty(&txq->q))) txq->link = NULL; spin_unlock(&txq->lock); + if (sc->txbuf_len > ATH_TXBUF / 5) + ieee80211_wake_queues(sc->hw); } static void ath_tasklet_tx(unsigned long data) @@ -230,8 +233,6 @@ static void ath_tasklet_tx(unsigned long data) ath_tx_processq(sc, sc->txq); - ieee80211_wake_queue(sc->hw, 0); - ath_led_event(sc, ATH_LED_TX); } @@ -667,6 +668,7 @@ static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) spin_lock_bh(&sc->txbuflock); sc->tx_stats.data[txq->qnum].len--; list_move_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; spin_unlock_bh(&sc->txbuflock); } txq->link = NULL; @@ -995,10 +997,12 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, "dropping packet\n"); sc->stats.ast_tx_nobuf++; spin_unlock_irqrestore(&sc->txbuflock, flags); + ieee80211_stop_queue(hw, ctl->queue); return -1; } bf = list_first_entry(&sc->txbuf, struct ath_buf, list); list_del(&bf->list); + sc->txbuf_len--; if (list_empty(&sc->txbuf)) { sc->stats.ast_tx_qstop++; ieee80211_stop_queues(hw); @@ -1011,6 +1015,7 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, bf->skb = NULL; spin_lock_irqsave(&sc->txbuflock, flags); list_add_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; spin_unlock_irqrestore(&sc->txbuflock, flags); dev_kfree_skb_any(skb); return 0; @@ -1598,6 +1603,7 @@ static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) } INIT_LIST_HEAD(&sc->txbuf); + sc->txbuf_len = ATH_TXBUF; for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC, da += ATH_TXDESC * sizeof(*ds)) { bf->desc = ds; diff --git a/ath.h b/ath.h index b83ec04..613db78 100644 --- a/ath.h +++ b/ath.h @@ -194,6 +194,7 @@ struct ath_softc { #endif struct list_head txbuf; /* transmit buffer */ spinlock_t txbuflock; + unsigned int txbuf_len; /* buf count in txbuf list */ struct ath_txq txqs[2]; /* beacon and tx */ #ifdef UNUSED struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ commit b04cebfdf1788804d0578f818ed102de04a5614c Author: Jiri Slaby Date: Tue Jul 24 13:02:23 2007 +0200 IBSS mode diff --git a/ath.c b/ath.c index 5a7fc36..686d850 100644 --- a/ath.c +++ b/ath.c @@ -63,8 +63,9 @@ DPRINTF(struct ath_softc *sc, unsigned int m, const char *fmt, ...) enum { ATH_DEBUG_RESET = 0x00000020, /* reset processing */ ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ - ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ + ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ ATH_DEBUG_INTR = 0x00001000, /* ISR */ + ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ ATH_DEBUG_LED = 0x00100000, /* led management */ ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ @@ -158,6 +159,17 @@ static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) {} #endif +static inline void ath_cleanup_txbuf(struct ath_softc *sc, struct ath_buf *bf) +{ + BUG_ON(!bf); + if (!bf->skb) + return; + pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, + PCI_DMA_TODEVICE); + dev_kfree_skb(bf->skb); + bf->skb = NULL; +} + static void ath_tasklet_reset(unsigned long data) { struct ath_softc *sc = (void *)data; @@ -451,6 +463,245 @@ next: } /* + * Setup the beacon frame for transmit. + */ +static int ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, + struct ieee80211_tx_control *ctl) +{ + struct sk_buff *skb = bf->skb; + struct ath_hw *ah = sc->ah; + struct ath_desc *ds; + int ret, antenna = 0; + u32 flags; + + bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: skb %p [data %p len %u] " + "skbaddr %llx\n", __func__, skb, skb->data, skb->len, + (unsigned long long)bf->skbaddr); + if (pci_dma_mapping_error(bf->skbaddr)) { + printk(KERN_ERR "ath: beacon DMA mapping failed\n"); + return -EIO; + } + + ds = bf->desc; + + flags = AR5K_TXDESC_NOACK; + if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) { + ds->ds_link = bf->daddr; /* self-linked */ + flags |= AR5K_TXDESC_VEOL; + /* + * Let hardware handle antenna switching if txantenna is not set + */ + } else { + ds->ds_link = 0; + /* + * Switch antenna every 4 beacons if txantenna is not set + * XXX assumes two antenna + */ + if (antenna == 0) { + antenna = (sc->stats.ast_be_xmit & 4 ? 2 : 1); + } + } + + ds->ds_data = bf->skbaddr; + ret = ah->ah_setup_tx_desc(ah, ds, skb->len + FCS_LEN, + ieee80211_get_hdrlen_from_skb(skb), + AR5K_PKT_TYPE_BEACON, 0xffff, ctl->tx_rate, 1, + AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0); + if (ret) + goto err_unmap; + /* NB: beacon's BufLen must be a multiple of 4 bytes */ + ret = ah->ah_fill_tx_desc(ah, ds, roundup(skb->len, 4), true, true); + if (ret) + goto err_unmap; + + return 0; +err_unmap: + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); + return ret; +} + +/* + * Transmit a beacon frame at SWBA. Dynamic updates to the + * frame contents are done as needed and the slot time is + * also adjusted based on current state. + * + * this is usually called from interrupt context (ath_intr()) + * but also from ath_beacon_config() in IBSS mode which in turn + * can be called from a tasklet and user context + */ +static void ath_beacon_send(struct ath_softc *sc) +{ + struct ath_buf *bf = sc->bbuf; + struct ath_hw *ah = sc->ah; + + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__); + + if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA || + sc->opmode == IEEE80211_IF_TYPE_MNTR)) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: bf=%p bf_skb=%p\n", + __func__, bf, bf ? bf->skb : NULL); + return; + } + /* + * Check if the previous beacon has gone out. If + * not don't don't try to post another, skip this + * period and wait for the next. Missed beacons + * indicate a problem and should not occur. If we + * miss too many consecutive beacons reset the device. + */ + if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { + sc->bmisscount++; + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, + "%s: missed %u consecutive beacons\n", + __func__, sc->bmisscount); + if (sc->bmisscount > 3) { /* NB: 3 is a guess */ + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, + "%s: stuck beacon time (%u missed)\n", + __func__, sc->bmisscount); + tasklet_schedule(&sc->restq); + } + return; + } + if (unlikely(sc->bmisscount != 0)) { + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, + "%s: resume beacon xmit after %u misses\n", + __func__, sc->bmisscount); + sc->bmisscount = 0; + } + + /* + * Stop any current dma and put the new frame on the queue. + * This should never fail since we check above that no frames + * are still pending on the queue. + */ + if (unlikely(!ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: beacon queue %u didn't stop?\n", + __func__, sc->bhalq); + /* NB: the HAL still stops DMA, so proceed */ + } + pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len, + PCI_DMA_TODEVICE); + + ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr); + ath5k_hw_tx_start(ah, sc->bhalq); + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: TXDP[%u] = %llx (%p)\n", + __func__, sc->bhalq, (unsigned long long)bf->daddr, bf->desc); + + sc->stats.ast_be_xmit++; +} + +static int ath_beaconq_config(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + struct ath5k_txq_info qi; + int ret; + + ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); + if (ret) + return ret; + if (sc->opmode == IEEE80211_IF_TYPE_AP || + sc->opmode == IEEE80211_IF_TYPE_IBSS) { + /* + * Always burst out beacon and CAB traffic. + */ + qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; + qi.tqi_cw_min = ATH_BEACON_CWMIN_DEFAULT; + qi.tqi_cw_max = ATH_BEACON_CWMAX_DEFAULT; + } + + ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi); + if (ret) { + printk(KERN_ERR "%s: unable to update parameters for beacon " + "hardware queue!\n", __func__); + return ret; + } + + return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; +} + +/* + * Configure the beacon and sleep timers. + * + * When operating as an AP this resets the TSF and sets + * up the hardware to notify us when we need to issue beacons. + * + * When operating in station mode this sets up the beacon + * timers according to the timestamp of the last received + * beacon and the current TSF, configures PCF and DTIM + * handling, programs the sleep registers so the hardware + * will wakeup in time to receive beacons, and configures + * the beacon miss handling so we'll receive a BMISS + * interrupt when we stop seeing beacons from the AP + * we've associated with. + */ +static void ath_beacon_config(struct ath_softc *sc) +{ +#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) + struct ath_hw *ah = sc->ah; + u32 uninitialized_var(nexttbtt), intval, tsftu; + u64 tsf; + + intval = sc->bintval & AR5K_BEACON_PERIOD; + if (WARN_ON(!intval)) + return; + + /* current TSF converted to TU */ + tsf = ath5k_hw_get_tsf64(ah); + tsftu = TSF_TO_TU((u32)(tsf >> 32), (u32)tsf); + + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: intval %u hw tsftu %u\n", __func__, + intval, tsftu); + + if (sc->opmode == IEEE80211_IF_TYPE_STA) { + ath5k_hw_set_intr(ah, 0); + sc->imask |= AR5K_INT_BMISS; + sc->bmisscount = 0; + ath5k_hw_set_intr(ah, sc->imask); + } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS /* TODO || AP */) { + ath5k_hw_set_intr(ah, 0); + if (sc->opmode == IEEE80211_IF_TYPE_IBSS) { + /* + * Pull nexttbtt forward to reflect the current + * TSF. Add one intval otherwise the timespan + * can be too short for ibss merges. + */ + nexttbtt = tsftu + 2 * intval; + + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u " + "intval %u\n", __func__, nexttbtt, intval); + + /* + * In IBSS mode enable the beacon timers but only + * enable SWBA interrupts if we need to manually + * prepare beacon frames. Otherwise we use a + * self-linked tx descriptor and let the hardware + * deal with things. + */ + if (!ath5k_hw_hasveol(ah)) + sc->imask |= AR5K_INT_SWBA; + } /* TODO else AP */ + + intval |= AR5K_BEACON_ENA; + + ath_beaconq_config(sc); + ath5k_hw_init_beacon(ah, nexttbtt, intval); + + sc->bmisscount = 0; + ath5k_hw_set_intr(ah, sc->imask); + /* + * When using a self-linked beacon descriptor in + * ibss mode load it once here. + */ + if (sc->opmode == IEEE80211_IF_TYPE_IBSS && + ath5k_hw_hasveol(ah)) + ath_beacon_send(sc); + } +#undef TSF_TO_TU +} + +/* * Calculate the receive filter according to the * operating mode and state: * @@ -660,10 +911,7 @@ static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) ath_printtxbuf(bf, !sc->ah->ah_proc_tx_desc(sc->ah, bf->desc)); #endif - pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, - PCI_DMA_TODEVICE); - dev_kfree_skb(bf->skb); - bf->skb = NULL; + ath_cleanup_txbuf(sc, bf); spin_lock_bh(&sc->txbuflock); sc->tx_stats.data[txq->qnum].len--; @@ -685,12 +933,10 @@ static void ath_draintxq(struct ath_softc *sc) /* XXX return value */ if (likely(!sc->invalid)) { -#ifdef BEACON /* don't touch the hardware if marked invalid */ (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, ath5k_hw_get_tx_buf(ah, sc->bhalq)); -#endif for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) if (sc->txqs[i].setup) { ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); @@ -788,6 +1034,7 @@ static int ath_stop_hw(struct ath_softc *sc) ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); } } + ath_cleanup_txbuf(sc, sc->bbuf); mutex_unlock(&sc->lock); del_timer_sync(&sc->calib_tim); @@ -1059,7 +1306,8 @@ static int ath_reset(struct ieee80211_hw *hw) * might change as a result. */ // ath_chan_change(sc, c); - ath5k_hw_set_intr(ah, sc->imask); + ath_beacon_config(sc); + /* intrs are started by ath_beacon_config */ ieee80211_wake_queues(hw); @@ -1078,15 +1326,81 @@ static int ath_stop(struct ieee80211_hw *hw) return ath_stop_hw(hw->priv); } +static int ath_add_interface(struct ieee80211_hw *hw, + struct ieee80211_if_init_conf *conf) +{ + struct ath_softc *sc = hw->priv; + int ret; + + mutex_lock(&sc->lock); + if (sc->iface_id) { + ret = 0; + goto end; + } + + sc->iface_id = conf->if_id; + + switch (conf->type) { + case IEEE80211_IF_TYPE_STA: + case IEEE80211_IF_TYPE_IBSS: + sc->opmode = conf->type; + break; + default: + ret = -EOPNOTSUPP; + goto end; + } + ret = 0; +end: + mutex_unlock(&sc->lock); + return ret; +} + +static void ath_remove_interface(struct ieee80211_hw *hw, + struct ieee80211_if_init_conf *conf) +{ + struct ath_softc *sc = hw->priv; + + mutex_lock(&sc->lock); + if (sc->iface_id != conf->if_id) { + goto end; + } + + sc->iface_id = 0; +end: + mutex_unlock(&sc->lock); +} + static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) { struct ath_softc *sc = hw->priv; + sc->bintval = conf->beacon_int * 1000 / 1024; ath_setcurmode(sc, conf->phymode); return ath_chan_set(sc, conf->chan); } +static int ath_config_interface(struct ieee80211_hw *hw, int if_id, + struct ieee80211_if_conf *conf) +{ + struct ath_softc *sc = hw->priv; + int ret; + + mutex_lock(&sc->lock); + if (sc->iface_id != if_id) { + ret = -EIO; + goto unlock; + } + if (conf->bssid) + ath5k_hw_set_associd(sc->ah, conf->bssid, 0 /* FIXME: aid */); + mutex_unlock(&sc->lock); + + return ath_reset(hw); +unlock: + mutex_unlock(&sc->lock); + return ret; +} + static void ath_set_multicast_list(struct ieee80211_hw *hw, unsigned short flags, int mc_count) { @@ -1183,15 +1497,41 @@ static void ath_reset_tsf(struct ieee80211_hw *hw) ath5k_hw_reset_tsf(sc->ah); } +static int ath_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, + struct ieee80211_tx_control *ctl) +{ + struct ath_softc *sc = hw->priv; + int ret; + + ath_dump_skb(skb, "b"); + + mutex_lock(&sc->lock); + + if (sc->opmode != IEEE80211_IF_TYPE_IBSS) { + ret = -EIO; + goto end; + } + + ath_cleanup_txbuf(sc, sc->bbuf); + sc->bbuf->skb = skb; + ret = ath_beacon_setup(sc, sc->bbuf, ctl); + if (ret) + sc->bbuf->skb = NULL; + +end: + mutex_unlock(&sc->lock); + return ret; +} + static struct ieee80211_ops ath_hw_ops = { .tx = ath_tx, .reset = ath_reset, .open = ath_open, .stop = ath_stop, - .add_interface = NULL, - .remove_interface = NULL, + .add_interface = ath_add_interface, + .remove_interface = ath_remove_interface, .config = ath_config, - .config_interface = NULL, + .config_interface = ath_config_interface, .set_multicast_list = ath_set_multicast_list, .set_key = ath_set_key, .get_stats = ath_get_stats, @@ -1199,7 +1539,7 @@ static struct ieee80211_ops ath_hw_ops = { .get_tx_stats = ath_get_tx_stats, .get_tsf = ath_get_tsf, .reset_tsf = ath_reset_tsf, - .beacon_update = NULL, + .beacon_update = ath_beacon_update, }; /* @@ -1280,7 +1620,7 @@ static void ath_led_event(struct ath_softc *sc, int event) } } -static irqreturn_t ath_intr(int irq, void *dev_id) +static irqreturn_t ath_intr(int irq, void *dev_id) { struct ath_softc *sc = dev_id; struct ath_hw *ah = sc->ah; @@ -1289,7 +1629,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) if (unlikely(sc->invalid || !ath5k_hw_is_intr_pending(ah))) return IRQ_NONE; - + do { /* * Figure out the reason(s) for the interrupt. Note @@ -1321,7 +1661,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) * this is too slow to meet timing constraints * under load. */ -// ath_beacon_send(dev); + ath_beacon_send(sc); } if (status & AR5K_INT_RXEOL) { /* @@ -1341,10 +1681,10 @@ static irqreturn_t ath_intr(int irq, void *dev_id) tasklet_schedule(&sc->rxtq); if (status & AR5K_INT_TX) tasklet_schedule(&sc->txtq); -/* if (status & AR5K_INT_BMISS) { + if (status & AR5K_INT_BMISS) { sc->stats.ast_bmiss++; - tasklet_schedule(&sc->bmisstq); - }*/ +/* tasklet_schedule(&sc->bmisstq);*/ + } if (status & AR5K_INT_MIB) { sc->stats.ast_mib++; /* TODO */ @@ -1355,7 +1695,7 @@ static irqreturn_t ath_intr(int irq, void *dev_id) if (unlikely(!counter && net_ratelimit())) printk(KERN_WARNING "ath: too many interrupts, giving up for " "now\n"); - + return IRQ_HANDLED; } @@ -1582,11 +1922,7 @@ static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); - bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF -#ifdef BEACON - + ATH_BCBUF -#endif - , + bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, sizeof(struct ath_buf), GFP_KERNEL); if (bf == NULL) { dev_err(&pdev->dev, "can't allocate bufptr\n"); @@ -1610,14 +1946,11 @@ static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) bf->daddr = da; list_add_tail(&bf->list, &sc->txbuf); } -#ifdef BEACON - INIT_LIST_HEAD(&sc->bbuf); - for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { - bf->desc = ds; - bf->daddr = da; - list_add_tail(&bf->list, &sc->bbuf); - } -#endif + + /* beacon buffer */ + bf->desc = ds; + bf->daddr = da; + sc->bbuf = bf; return 0; err_free: @@ -1627,26 +1960,15 @@ err: return ret; } -static void ath_descdma_cleanup(struct ath_softc *sc, struct pci_dev *pdev, - struct list_head *head) +static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) { struct ath_buf *bf; - list_for_each_entry(bf, head, list) { - if (bf->skb) { - pci_unmap_single(pdev, bf->skbaddr, sc->rxbufsize, - PCI_DMA_FROMDEVICE); - dev_kfree_skb(bf->skb); - bf->skb = NULL; - } - } -} - -static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) -{ -// ath_descdma_cleanup(sc, pdev, &sc->bbuf); - ath_descdma_cleanup(sc, pdev, &sc->txbuf); - ath_descdma_cleanup(sc, pdev, &sc->rxbuf); + ath_cleanup_txbuf(sc, sc->bbuf); + list_for_each_entry(bf, &sc->txbuf, list) + ath_cleanup_txbuf(sc, bf); + list_for_each_entry(bf, &sc->rxbuf, list) + ath_cleanup_txbuf(sc, bf); /* Free memory associated with all descriptors */ pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); @@ -1654,34 +1976,33 @@ static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) kfree(sc->bufptr); sc->bufptr = NULL; } -#ifdef BEACON + static int ath_beaconq_setup(struct ath_hw *ah) { - struct ath5k_txq_info qi; - - memset(&qi, 0, sizeof(qi)); - qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; - /* NB: for dynamic turbo, don't enable any other interrupts */ - qi.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + struct ath5k_txq_info qi = { + .tqi_aifs = AR5K_TXQ_USEDEFAULT, + .tqi_cw_min = AR5K_TXQ_USEDEFAULT, + .tqi_cw_max = AR5K_TXQ_USEDEFAULT, + /* NB: for dynamic turbo, don't enable any other interrupts */ + .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE + }; return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); } -#endif + static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) { struct ath_hw *ah = sc->ah; struct ath_txq *txq; - struct ath5k_txq_info qi; + struct ath5k_txq_info qi = { + .tqi_subtype = subtype, + .tqi_aifs = AR5K_TXQ_USEDEFAULT, + .tqi_cw_min = AR5K_TXQ_USEDEFAULT, + .tqi_cw_max = AR5K_TXQ_USEDEFAULT + }; int qnum; - memset(&qi, 0, sizeof(qi)); - qi.tqi_subtype = subtype; - qi.tqi_aifs = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_min = AR5K_TXQ_USEDEFAULT; - qi.tqi_cw_max = AR5K_TXQ_USEDEFAULT; /* * Enable interrupts only for EOL and DESC conditions. * We mark tx descriptors to receive a DESC interrupt @@ -1786,7 +2107,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) goto err; } -#ifdef BEACON /* * Allocate hardware transmit queues: one queue for * beacon frames and one data queue for each QoS @@ -1800,19 +2120,11 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) } sc->bhalq = ret; - sc->cabq = ath_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); - if (IS_ERR(sc->cabq)) { - dev_err(&pdev->dev, "can't setup CAB xmit queue\n"); - ret = PTR_ERR(sc->cabq); - sc->cabq = NULL; - goto err_queues; - } -#endif sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); if (IS_ERR(sc->txq)) { dev_err(&pdev->dev, "can't setup xmit queue\n"); ret = PTR_ERR(sc->txq); - goto err_queues; + goto err_bhal; } tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); @@ -1842,13 +2154,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ath5k_hw_set_gpio_output(ah, sc->led_pin); ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); } -#ifdef BEACON - /* - * Not all chips have the VEOL support we want to - * use with IBSS beacons; check here for it. - */ - sc->sc_hasveol = ath_hal_hasveol(ah); -#endif ath5k_hw_get_lladdr(ah, mac); SET_IEEE80211_PERM_ADDR(hw, mac); @@ -1866,6 +2171,9 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) return 0; err_queues: ath_tx_cleanup(sc); +err_bhal: + ath5k_hw_release_tx_queue(ah, sc->bhalq); +err_desc: ath_desc_free(sc, pdev); err: return ret; @@ -1890,6 +2198,7 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) ieee80211_unregister_hw(hw); ath_desc_free(sc, pdev); ath_tx_cleanup(sc); + ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); /* * NB: can't reclaim these until after ieee80211_ifdetach diff --git a/ath.h b/ath.h index 613db78..c61119c 100644 --- a/ath.h +++ b/ath.h @@ -155,6 +155,8 @@ struct ath_softc { unsigned int curmode; /* current phy mode */ struct ieee80211_channel *curchan; /* current h/w channel */ + int iface_id; /* add/remove_interface id */ + struct { u8 rxflags; /* radiotap rx flags */ u8 txflags; /* radiotap tx flags */ @@ -202,16 +204,15 @@ struct ath_softc { struct ath_txq *txq; /* beacon and tx*/ struct tasklet_struct txtq; /* tx intr tasklet */ + struct ath_buf *bbuf; /* beacon buffer */ + unsigned int bhalq, /* HAL q for outgoing beacons */ + bmisscount, /* missed beacon transmits */ + bintval; /* beacon interval */ #ifdef BEACON - struct list_head bbuf; /* beacon buffers */ - unsigned int bhalq; /* HAL q for outgoing beacons */ - u_int sc_bmisscount; /* missed beacon transmits */ u32 sc_ant_tx[8]; /* recent tx frames/antenna */ - struct ieee80211_beacon_offsets boff; /* dynamic update state */ struct ath_txq *cabq; /* tx q for cab frames */ struct tasklet_struct bmisstq; /* bmiss intr tasklet */ - struct tasklet_struct sc_bstuckq; /* stuck beacon processing */ #endif #ifdef UNUSED struct ctl_table_header *sc_sysctl_header; diff --git a/ath/if_ath.c b/ath/if_ath.c index 661f571..acc4e2b 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -1,7 +1,3 @@ -/* unaligned little endian access */ -#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) -#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) - static int ath_dwelltime = 200; /* 5 channels/second */ static int ath_calinterval = 30; /* calibrate every 30 secs */ static int ath_countrycode = CTRY_DEFAULT; /* country code */ @@ -650,547 +646,6 @@ ath_updateslot(struct net_device *dev) else ath_setslottime(sc); } -/* - * Setup the transmit queue parameters for the beacon queue. - */ -static int -ath_beaconq_config(struct ath_softc *sc) -{ -#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) -// struct ieee80211com *ic = &sc->sc_ic; - struct ath_hal *ah = sc->sc_ah; - struct ath5k_txq_info qi; - - ath5k_hw_get_tx_queueprops(ah, sc->sc_bhalq, &qi); - if (sc->sc_opmode == IEEE80211_IF_TYPE_AP) { - /* - * Always burst out beacon and CAB traffic. - */ - qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; - qi.tqi_cw_min = ATH_BEACON_CWMIN_DEFAULT; - qi.tqi_cw_max = ATH_BEACON_CWMAX_DEFAULT; - } else { - struct wmeParams *wmep = - &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; - /* - * Adhoc mode; important thing is to use 2x cwmin. - */ - qi.tqi_aifs = wmep->wmep_aifsn; - qi.tqi_cw_min = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); - qi.tqi_cw_max = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); - } - - if (!ath5k_hw_setup_tx_queueprops(ah, sc->sc_bhalq, &qi)) { - printk("%s: unable to update parameters for " - "beacon hardware queue! (%s)\n", __func__, sc->sc_dev.name); - return 0; - } else { - ath5k_hw_reset_tx_queue(ah, sc->sc_bhalq); /* push to h/w */ - return 1; - } -#undef ATH_EXPONENT_TO_VALUE -} - -/* - * Allocate and setup an initial beacon frame. - */ -static int -ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) -{ - struct ieee80211com *ic = &sc->sc_ic; - struct ath_buf *bf; - struct sk_buff *skb; - - bf = STAILQ_FIRST(&sc->sc_bbuf); - if (bf == NULL) { - DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); - sc->sc_stats.ast_be_nobuf++; /* XXX */ - return ENOMEM; /* XXX */ - } - /* - * NB: the beacon data buffer must be 32-bit aligned; - * we assume the mbuf routines will return us something - * with this alignment (perhaps should assert). - */ - skb = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); - if (skb == NULL) { - DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get sk_buff\n", - __func__); - sc->sc_stats.ast_be_nobuf++; - return ENOMEM; - } - - if (bf->bf_skb != NULL) { - bus_unmap_single(sc->sc_bdev, - bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); - dev_kfree_skb(bf->bf_skb); - bf->bf_skb = NULL; - bf->bf_node = NULL; - } - bf->bf_skb = skb; - bf->bf_node = ieee80211_ref_node(ni); - - return 0; // TODO: return value -} - -/* - * Setup the beacon frame for transmit. - */ -static void -ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, - struct ieee80211_tx_control *ctl) -{ -#define USE_SHPREAMBLE(_ic) \ - (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ - == IEEE80211_F_SHPREAMBLE) - struct sk_buff *skb = bf->bf_skb; - struct ath_hal *ah = sc->sc_ah; - struct ath_desc *ds; - int antenna = sc->sc_txantenna; - int flags; - u_int8_t rate; - - bf->bf_skbaddr = bus_map_single(sc->sc_bdev, - skb->data, skb->len, BUS_DMA_TODEVICE); - DPRINTF(sc, ATH_DEBUG_BEACON, - "%s: skb %p [data %p len %u] skbaddr %llx\n", - __func__, skb, skb->data, skb->len, - (unsigned long long)bf->bf_skbaddr); - if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { - printk(KERN_ERR "%s: DMA mapping failed\n", __func__); - return; - } - - /* setup descriptors */ - ds = bf->bf_desc; - - flags = AR5K_TXDESC_NOACK; - if (sc->sc_opmode == IEEE80211_IF_TYPE_IBSS && sc->sc_hasveol) { - ds->ds_link = bf->bf_daddr; /* self-linked */ - flags |= AR5K_TXDESC_VEOL; - /* - * Let hardware handle antenna switching if txantenna is not set - */ - } else { - ds->ds_link = 0; - /* - * Switch antenna every 4 beacons if txantenna is not set - * XXX assumes two antenna - */ - if (antenna == 0) { - antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); - } - } - - ds->ds_data = bf->bf_skbaddr; - /* - * Calculate rate code. - * XXX everything at min xmit rate - */ - if (USE_SHPREAMBLE(ic)) - rate = an->an_tx_mgtratesp; - else - rate = an->an_tx_mgtrate; - rate = 0; - ah->ah_setup_tx_desc(ah, ds - , skb->len + FCS_LEN /* frame length */ - , ieee80211_get_hdrlen_from_skb(skb) /* header length */ - , AR5K_PKT_TYPE_BEACON /* Atheros packet type */ - , min((u8)60u, ctl->power_level) /* txpower XXX */ - , rate, 1 /* series 0 rate/tries */ - , AR5K_TXKEYIX_INVALID /* no encryption */ - , antenna /* antenna mode */ - , flags /* no ack, veol for beacons */ - , 0 /* rts/cts rate */ - , 0 /* rts/cts duration */ - ); - /* NB: beacon's BufLen must be a multiple of 4 bytes */ - ah->ah_fill_tx_desc(ah, ds - , roundup(skb->len, 4) /* buffer length */ - , true /* first segment */ - , true /* last segment */ - , ds /* first descriptor */ - ); -#undef USE_SHPREAMBLE -} - -/* - * Transmit a beacon frame at SWBA. Dynamic updates to the - * frame contents are done as needed and the slot time is - * also adjusted based on current state. - * - * this is usually called from interrupt context (ath_intr()) - * but also from ath_beacon_config() in IBSS mode which in turn - * can be called from a tasklet and user context - */ -static void -ath_beacon_send(struct net_device *dev) -{ - struct ieee80211_tx_control ctl; - struct ath_softc *sc = dev->priv; - struct ath_buf *bf = NULL;//STAILQ_FIRST(&sc->sc_bbuf); - struct ath_hal *ah = sc->sc_ah; - struct sk_buff *skb; - int ncabq, otherant; - - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__); - - if (sc->sc_opmode == IEEE80211_IF_TYPE_STA || - sc->sc_opmode == IEEE80211_IF_TYPE_MNTR || - bf == NULL || bf->bf_skb == NULL) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: bf=%p bf_skb=%p\n", - __func__, bf, bf ? bf->bf_skb : NULL); - return; - } - /* - * Check if the previous beacon has gone out. If - * not don't don't try to post another, skip this - * period and wait for the next. Missed beacons - * indicate a problem and should not occur. If we - * miss too many consecutive beacons reset the device. - */ - if (ath5k_hw_num_tx_pending(ah, sc->sc_bhalq) != 0) { - sc->sc_bmisscount++; - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: missed %u consecutive beacons\n", - __func__, sc->sc_bmisscount); - if (sc->sc_bmisscount > 3) { /* NB: 3 is a guess */ - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: stuck beacon time (%u missed)\n", - __func__, sc->sc_bmisscount); - tasklet_schedule(&sc->sc_bstuckq); - } - return; - } - if (sc->sc_bmisscount != 0) { - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: resume beacon xmit after %u misses\n", - __func__, sc->sc_bmisscount); - sc->sc_bmisscount = 0; - } - - /* - * Update dynamic beacon contents. If this returns - * non-zero then we need to remap the memory because - * the beacon frame changed size (probably because - * of the TIM bitmap). - */ - skb = bf->bf_skb; - ncabq = sc->sc_cabq->axq_depth; - if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, skb, ncabq)) { - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: update, beacon len changed %d to %d\n", - __func__, bf->bf_skb->len, skb->len); - - /* XXX too conservative? */ - bus_unmap_single(sc->sc_bdev, - bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); - - bf->bf_skbaddr = bus_map_single(sc->sc_bdev, - skb->data, skb->len, BUS_DMA_TODEVICE); - if (BUS_DMA_MAP_ERROR(bf->bf_skbaddr)) { - if_printf(dev, "%s: DMA mapping failed\n", __func__); - return; - } - } - - /* - * Handle slot time change when a non-ERP station joins/leaves - * an 11g network. The 802.11 layer notifies us via callback, - * we mark updateslot, then wait one beacon before effecting - * the change. This gives associated stations at least one - * beacon interval to note the state change. - */ - /* XXX locking */ - if (sc->sc_updateslot == UPDATE) - sc->sc_updateslot = COMMIT; /* commit next beacon */ - else if (sc->sc_updateslot == COMMIT) - ath_setslottime(sc); /* commit change to h/w */ - - /* - * Check recent per-antenna transmit statistics and flip - * the default antenna if noticeably more frames went out - * on the non-default antenna. - * XXX assumes 2 anntenae - */ - otherant = sc->sc_defant & 1 ? 2 : 1; - if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) - ath_setdefantenna(sc, otherant); - sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; - - /* - * Construct tx descriptor. - */ - ath_beacon_setup(sc, bf, &ctl); - - /* - * Stop any current dma and put the new frame on the queue. - * This should never fail since we check above that no frames - * are still pending on the queue. - */ - if (!ath5k_hw_stop_tx_dma(ah, sc->sc_bhalq)) { - DPRINTF(sc, ATH_DEBUG_ANY, - "%s: beacon queue %u did not stop?\n", - __func__, sc->sc_bhalq); - /* NB: the HAL still stops DMA, so proceed */ - } - bus_dma_sync_single(sc->sc_bdev, - bf->bf_skbaddr, bf->bf_skb->len, BUS_DMA_TODEVICE); - - /* - * Enable the CAB queue before the beacon queue to - * insure CAB frames are triggered by this beacon. - * The CAB queue holds multicast traffic for stations in - * power-save mode. - * - * NB: only at DTIM - */ - if (sc->sc_opmode == IEEE80211_IF_TYPE_AP && - ncabq > 0 && sc->sc_boff.bo_tim[4] & 1) - ath5k_hw_tx_start(ah, sc->sc_cabq->axq_qnum); - - ath5k_hw_put_tx_buf(ah, sc->sc_bhalq, bf->bf_daddr); - ath5k_hw_tx_start(ah, sc->sc_bhalq); - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: TXDP[%u] = %llx (%p)\n", __func__, - sc->sc_bhalq, (unsigned long long)bf->bf_daddr, bf->bf_desc); - - sc->sc_stats.ast_be_xmit++; -} - -/* - * Reset the hardware after detecting beacons have stopped. - */ -static void -ath_bstuck_tasklet(unsigned long data) -{ - struct ieee80211_hw *hw = (void *)data; - struct ath_softc *sc = hw->priv; - - printk(KERN_WARNING "stuck beacon; resetting (bmiss count %u)\n", - sc->sc_bmisscount); - ath_reset(hw); -} - -/* - * Reclaim beacon resources. - */ -static void -ath_beacon_free(struct ath_softc *sc) -{ - struct ath_buf *bf; - - bf = NULL; - STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { - if (bf->bf_skb != NULL) { - bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr, - bf->bf_skb->len, BUS_DMA_TODEVICE); - dev_kfree_skb(bf->bf_skb); - bf->bf_skb = NULL; - } - - if (bf->bf_node != NULL) { - ieee80211_free_node(bf->bf_node); - bf->bf_node = NULL; - } - } -} - -/* - * Configure the beacon and sleep timers. - * - * When operating as an AP this resets the TSF and sets - * up the hardware to notify us when we need to issue beacons. - * - * When operating in station mode this sets up the beacon - * timers according to the timestamp of the last received - * beacon and the current TSF, configures PCF and DTIM - * handling, programs the sleep registers so the hardware - * will wakeup in time to receive beacons, and configures - * the beacon miss handling so we'll receive a BMISS - * interrupt when we stop seeing beacons from the AP - * we've associated with. - */ -static void -ath_beacon_config(struct ath_softc *sc) -{ -#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) - struct ath_hal *ah = sc->sc_ah; - u_int32_t nexttbtt, intval; - u_int64_t tsf; - u_int32_t tsftu; - - /* extract tstamp from last beacon and convert to TU */ - nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), - LE_READ_4(ni->ni_tstamp.data)); - /* NB: the beacon interval is kept internally in TU's */ - intval = ni->ni_intval & AR5K_BEACON_PERIOD; - /* current TSF converted to TU */ - tsf = ath5k_hw_get_tsf64(ah); - tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf); - - DPRINTF(sc, ATH_DEBUG_BEACON, "%s: last beacon %u intval %u (%u) hw tsftu %u\n", - __func__, nexttbtt, intval, ni->ni_intval, tsftu); - - if (ic->ic_opmode == IEEE80211_M_STA) { - AR5K_BEACON_STATE bs; - int dtimperiod, dtimcount; - int cfpperiod, cfpcount; - - /* - * Setup dtim and cfp parameters according to - * last beacon we received (which may be none). - */ - dtimperiod = ni->ni_dtim_period; - if (dtimperiod <= 0) /* NB: 0 if not known */ - dtimperiod = 1; - dtimcount = ni->ni_dtim_count; - if (dtimcount >= dtimperiod) /* NB: sanity check */ - dtimcount = 0; /* XXX? */ - cfpperiod = 1; /* NB: no PCF support yet */ - cfpcount = 0; -#define FUDGE 2 - /* - * Pull nexttbtt forward to reflect the current - * TSF and calculate dtim+cfp state for the result. - */ - do { - nexttbtt += intval; - if (--dtimcount < 0) { - dtimcount = dtimperiod - 1; - if (--cfpcount < 0) - cfpcount = cfpperiod - 1; - } - } while (nexttbtt < tsftu + FUDGE); -#undef FUDGE - memset(&bs, 0, sizeof(bs)); - bs.bs_interval = intval; - bs.bs_next_beacon = nexttbtt; - bs.bs_dtim_period = dtimperiod*intval; - bs.bs_next_dtim = bs.bs_next_beacon + dtimcount*intval; - bs.bs_cfp_period = cfpperiod*bs.bs_dtim_period; - bs.bs_cfp_next = bs.bs_next_dtim + cfpcount*bs.bs_dtim_period; - bs.bs_cfp_max_duration = 0; -#if 0 - /* - * The 802.11 layer records the offset to the DTIM - * bitmap while receiving beacons; use it here to - * enable h/w detection of our AID being marked in - * the bitmap vector (to indicate frames for us are - * pending at the AP). - * XXX do DTIM handling in s/w to WAR old h/w bugs - * XXX enable based on h/w rev for newer chips - */ - bs.bs_tim_offset = ni->ni_timoff; -#endif - /* - * Calculate the number of consecutive beacons to miss - * before taking a BMISS interrupt. The configuration - * is specified in ms, so we need to convert that to - * TU's and then calculate based on the beacon interval. - * Note that we clamp the result to at most 10 beacons. - */ - bs.bs_bmiss_threshold = howmany(ic->ic_bmisstimeout, intval); - if (bs.bs_bmiss_threshold > 10) - bs.bs_bmiss_threshold = 10; - else if (bs.bs_bmiss_threshold <= 0) - bs.bs_bmiss_threshold = 1; - - /* - * Calculate sleep duration. The configuration is - * given in ms. We insure a multiple of the beacon - * period is used. Also, if the sleep duration is - * greater than the DTIM period then it makes senses - * to make it a multiple of that. - * - * XXX fixed at 100ms - */ - bs.bs_sleep_duration = - roundup(IEEE80211_MS_TO_TU(100), bs.bs_interval); - if (bs.bs_sleep_duration > bs.bs_dtim_period) - bs.bs_sleep_duration = roundup(bs.bs_sleep_duration, bs.bs_dtim_period); - - DPRINTF(sc, ATH_DEBUG_BEACON, - "%s: tsf %llx tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" - , __func__ - , tsf, tsftu - , bs.bs_interval - , bs.bs_next_beacon - , bs.bs_dtim_period - , bs.bs_next_dtim - , bs.bs_bmiss_threshold - , bs.bs_sleep_duration - , bs.bs_cfp_period - , bs.bs_cfp_max_duration - , bs.bs_cfp_next - , bs.bs_tim_offset - ); - ath5k_hw_set_intr(ah, 0); - ath5k_hw_set_beacon_timers(ah, &bs); - sc->sc_imask |= AR5K_INT_BMISS; - sc->sc_bmisscount = 0; - ath5k_hw_set_intr(ah, sc->sc_imask); - } else { /* IBSS or HOSTAP */ - ath5k_hw_set_intr(ah, 0); - - if (ic->ic_opmode == IEEE80211_M_IBSS) { - /* - * Pull nexttbtt forward to reflect the current - * TSF. Add one intval otherwise the timespan - * can be too short for ibss merges. - */ - do { - nexttbtt += intval; - } while (nexttbtt < tsftu+intval); - nexttbtt += intval; - - DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u\n", - __func__, nexttbtt, intval & AR5K_BEACON_PERIOD ); - - /* - * In IBSS mode enable the beacon timers but only - * enable SWBA interrupts if we need to manually - * prepare beacon frames. Otherwise we use a - * self-linked tx descriptor and let the hardware - * deal with things. - */ - if (!sc->sc_hasveol) - sc->sc_imask |= AR5K_INT_SWBA; - - } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { - if (nexttbtt == 0) { - /* - * starting a new BSS: we can reset the TSF - * and start with zero - */ - nexttbtt = intval; - intval |= AR5K_BEACON_RESET_TSF; - } else { - nexttbtt += intval; - } - /* - * In AP mode we enable the beacon timers and - * SWBA interrupts to prepare beacon frames. - */ - sc->sc_imask |= AR5K_INT_SWBA; /* beacon prepare */ - } - - intval |= AR5K_BEACON_ENA; - - ath_beaconq_config(sc); - ath5k_hw_init_beacon(ah, nexttbtt, intval); - - sc->sc_bmisscount = 0; - ath5k_hw_set_intr(ah, sc->sc_imask); - /* - * When using a self-linked beacon descriptor in - * ibss mode load it once here. - */ - if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) - ath_beacon_send(&sc->sc_dev); - } -#undef TSF_TO_TU -} /* * Set the default antenna. diff --git a/ath5k.h b/ath5k.h index cbab742..a62ecc5 100644 --- a/ath5k.h +++ b/ath5k.h @@ -1017,9 +1017,9 @@ int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); /* Queue Control Unit, DFS Control Unit Functions */ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); -bool ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); +int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); +int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); diff --git a/ath5k_hw.c b/ath5k_hw.c index 0dae6a4..501d85c 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -1200,9 +1200,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (hal->ah_version != AR5K_AR5210) AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i); - if (ath5k_hw_reset_tx_queue(hal, i) == false) { + ret = ath5k_hw_reset_tx_queue(hal, i); + if (ret) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); - return -EINVAL; + return ret; } } @@ -2560,8 +2561,7 @@ ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac) * Set BSSID */ void -ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, - u16 assoc_id) +ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id) { u32 low_id, high_id; u16 tim_offset = 0; @@ -2797,9 +2797,7 @@ void ath5k_hw_reset_tsf(struct ath_hw *hal) /* * Initialize beacon timers */ -void -ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, - u32 interval) +void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval) { u32 timer1, timer2, timer3; @@ -3331,12 +3329,12 @@ int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, /* * Get properties for a specific transmit queue */ -bool -ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info) +int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, + struct ath5k_txq_info *queue_info) { AR5K_TRACE; memcpy(queue_info, &hal->ah_txq[queue], sizeof(struct ath5k_txq_info)); - return true; + return 0; } /* @@ -3345,10 +3343,8 @@ ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) { AR5K_TRACE; - if (queue >= hal->ah_capabilities.cap_queues.q_tx_num) { - WARN_ON(1); + if (WARN_ON(queue >= hal->ah_capabilities.cap_queues.q_tx_num)) return; - } /* This queue will be skipped in further operations */ hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; @@ -3359,8 +3355,7 @@ void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue) /* * Set DFS params for a transmit queue */ -bool -ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) +int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) { u32 cw_min, cw_max, retry_lg, retry_sh; struct ath5k_txq_info *tq = &hal->ah_txq[queue]; @@ -3374,12 +3369,12 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) tq = &hal->ah_txq[queue]; if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) - return true; + return 0; if (hal->ah_version == AR5K_AR5210) { /* Only handle data queues, others will be ignored */ if (tq->tqi_type != AR5K_TX_QUEUE_DATA) - return true; + return -EINVAL; /* * Write initial mode register settings @@ -3577,7 +3572,7 @@ ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); } - return true; + return 0; } /* commit 11669f3f3189da8e2598eb6cd580ff3d06796e17 Author: Jiri Slaby Date: Wed Jul 25 09:06:10 2007 +0200 MONITOR mode diff --git a/ath.c b/ath.c index 686d850..e4c79ba 100644 --- a/ath.c +++ b/ath.c @@ -61,6 +61,7 @@ DPRINTF(struct ath_softc *sc, unsigned int m, const char *fmt, ...) } #endif enum { + ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ ATH_DEBUG_RESET = 0x00000020, /* reset processing */ ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ @@ -343,6 +344,16 @@ static unsigned int ath_rx_decrypted(struct ath_softc *sc, return 0; } +static inline u64 ath_extend_tsf(struct ath_hw *ah, u32 rstamp) +{ + u64 tsf = ath5k_hw_get_tsf64(ah); + + if ((tsf & 0x7fff) < rstamp) + tsf -= 0x8000; + + return (tsf &~ 0x7fff) | rstamp; +} + static void ath_tasklet_rx(unsigned long data) { struct ieee80211_rx_status rxs = {}; @@ -424,7 +435,10 @@ static void ath_tasklet_rx(unsigned long data) goto accept; } - goto next; + /* let crypto-error packets fall through in MNTR */ + if ((stat &~ (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || + sc->opmode != IEEE80211_IF_TYPE_MNTR) + goto next; } accept: len = ds->ds_rxstat.rs_datalen; @@ -441,7 +455,11 @@ accept: sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; - rxs.mactime = ds->ds_rxstat.rs_tstamp; + if (sc->opmode == IEEE80211_IF_TYPE_MNTR) + rxs.mactime = ath_extend_tsf(sc->ah, + ds->ds_rxstat.rs_tstamp); + else + rxs.mactime = ds->ds_rxstat.rs_tstamp; rxs.freq = sc->curchan->freq; rxs.channel = sc->curchan->chan; rxs.phymode = sc->curmode; @@ -729,6 +747,9 @@ static u32 ath_calcrxfilter(struct ath_softc *sc) AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_RADARERR; + if (sc->opmode == IEEE80211_IF_TYPE_MNTR) + rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON | + AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM; if (opmode != IEEE80211_IF_TYPE_STA) rfilt |= AR5K_RX_FILTER_PROBEREQ; if (opmode != IEEE80211_IF_TYPE_AP && sc->promisc) @@ -1235,6 +1256,9 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, ath_dump_skb(skb, "t"); + if (sc->opmode == IEEE80211_IF_TYPE_MNTR) + DPRINTF(sc, ATH_DEBUG_XMIT, "tx in monitor (scan?)\n"); + sc->led_txrate = ctl->tx_rate; spin_lock_irqsave(&sc->txbuflock, flags); @@ -1343,6 +1367,7 @@ static int ath_add_interface(struct ieee80211_hw *hw, switch (conf->type) { case IEEE80211_IF_TYPE_STA: case IEEE80211_IF_TYPE_IBSS: + case IEEE80211_IF_TYPE_MNTR: sc->opmode = conf->type; break; default: commit e425abdd9ab4835c5457b05b042929b4c133c032 Author: Jiri Slaby Date: Wed Jul 25 09:17:19 2007 +0200 remove yet another u used stuff from if_ath.c diff --git a/ath/if_ath.c b/ath/if_ath.c index acc4e2b..c92986a 100644 --- a/ath/if_ath.c +++ b/ath/if_ath.c @@ -5,108 +5,10 @@ static int ath_regdomain = 0; /* regulatory domain */ static int ath_outdoor = true; /* enable outdoor use */ static int ath_xchanmode = true; /* enable extended channels */ -#ifdef AR_DEBUG -static int ath_debug = 0; -#define IFF_DUMPPKTS(sc, _m) \ - ((sc->sc_debug & _m) || ieee80211_msg_dumppkts(&sc->sc_ic)) -#define KEYPRINTF(sc, ix, hk, mac) do { \ - if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ - ath_keyprint(__func__, ix, hk, mac); \ -} while (0) -static void ath_printrxbuf(struct ath_buf *bf, int); -//static void ath_printtxbuf(struct ath_buf *bf, int); -#else -#define IFF_DUMPPKTS(sc, _m) 0 -#define DPRINTF(sc, _m, _fmt, ...) -#define KEYPRINTF(sc, k, ix, mac) -#endif - MODULE_PARM_DESC(countrycode, "Override default country code"); MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); - -/* - * For packet capture, define the same physical layer packet header - * structure as used in the wlan-ng driver - */ -enum { - DIDmsg_lnxind_wlansniffrm = 0x00000044, - DIDmsg_lnxind_wlansniffrm_hosttime = 0x00010044, - DIDmsg_lnxind_wlansniffrm_mactime = 0x00020044, - DIDmsg_lnxind_wlansniffrm_channel = 0x00030044, - DIDmsg_lnxind_wlansniffrm_rssi = 0x00040044, - DIDmsg_lnxind_wlansniffrm_sq = 0x00050044, - DIDmsg_lnxind_wlansniffrm_signal = 0x00060044, - DIDmsg_lnxind_wlansniffrm_noise = 0x00070044, - DIDmsg_lnxind_wlansniffrm_rate = 0x00080044, - DIDmsg_lnxind_wlansniffrm_istx = 0x00090044, - DIDmsg_lnxind_wlansniffrm_frmlen = 0x000A0044 -}; -enum { - P80211ENUM_msgitem_status_no_value = 0x00 -}; -enum { - P80211ENUM_truth_false = 0x00, - P80211ENUM_truth_true = 0x01 -}; - -struct p80211item_u32 { - u32 did; - u16 status; - u16 len; - u32 data; -}; - -struct wlan_ng_prism2_header { - u32 msgcode; - u32 msglen; -#define WLAN_DEVNAMELEN_MAX 16 - u8 devname[WLAN_DEVNAMELEN_MAX]; - struct p80211item_u32 hosttime; - struct p80211item_u32 mactime; - struct p80211item_u32 channel; - struct p80211item_u32 rssi; - struct p80211item_u32 sq; - struct p80211item_u32 signal; - struct p80211item_u32 noise; - struct p80211item_u32 rate; - struct p80211item_u32 istx; - struct p80211item_u32 frmlen; -}; - -static void -ath_radar_tasklet(unsigned long data) -{ - struct ieee80211_hw *hw = (void *)data; - struct ath_softc *sc = dev->priv; - struct ieee80211com *ic = &sc->sc_ic; - struct ieee80211_channel *c; - - c = radar_handle_interference (ic); - - if (c == NULL) - { - ath_stop (dev); - printk ("%s: FATAL ERROR - All available channels are marked as being interfered by radar. Stopping radio.\n", dev->name); - return; - } - - ic->ic_des_chan = c; - ic->ic_ibss_chan = c; - ieee80211_new_state (ic, IEEE80211_S_INIT, -1); - ath_init(hw); -} - -static void -ath_rxorn_tasklet(unsigned long data) -{ - struct ieee80211_hw *hw = (void *)data; - - printk(KERN_WARNING "rx FIFO overrun; resetting\n"); - ath_reset(hw); -} - static void ath_bmiss_tasklet(unsigned long data) { @@ -145,78 +47,6 @@ ath_bmiss_tasklet(unsigned long data) } } - -#define NUM_RADIOTAP_ELEMENTS 18 - -static int radiotap_elem_to_bytes[NUM_RADIOTAP_ELEMENTS] = - {8, /* IEEE80211_RADIOTAP_TSFT */ - 1, /* IEEE80211_RADIOTAP_FLAGS */ - 1, /* IEEE80211_RADIOTAP_RATE */ - 4, /* IEEE80211_RADIOTAP_CHANNEL */ - 2, /* IEEE80211_RADIOTAP_FHSS */ - 1, /* IEEE80211_RADIOTAP_DBM_ANTSIGNAL */ - 1, /* IEEE80211_RADIOTAP_DBM_ANTNOISE */ - 2, /* IEEE80211_RADIOTAP_LOCK_QUALITY */ - 2, /* IEEE80211_RADIOTAP_TX_ATTENUATION */ - 2, /* IEEE80211_RADIOTAP_DB_TX_ATTENUATION */ - 1, /* IEEE80211_RADIOTAP_DBM_TX_POWER */ - 1, /* IEEE80211_RADIOTAP_ANTENNA */ - 1, /* IEEE80211_RADIOTAP_DB_ANTSIGNAL */ - 1, /* IEEE80211_RADIOTAP_DB_ANTNOISE */ - 2, /* IEEE80211_RADIOTAP_RX_FLAGS */ - 2, /* IEEE80211_RADIOTAP_TX_FLAGS */ - 1, /* IEEE80211_RADIOTAP_RTS_RETRIES */ - 1, /* IEEE80211_RADIOTAP_DATA_RETRIES */ - }; - -/* - * the following rt_* functions deal with verifying that a valid - * radiotap header is on a packet as well as functions to extracting - * what information is included. - * XXX maybe these should go in ieee_radiotap.c - */ -static int rt_el_present(struct ieee80211_radiotap_header *th, u_int32_t element) -{ - if (element > NUM_RADIOTAP_ELEMENTS) - return 0; - return le32_to_cpu(th->it_present) & (1 << element); -} - -static int rt_check_header(struct ieee80211_radiotap_header *th, int len) -{ - int bytes = 0; - int x = 0; - if (th->it_version != 0) - return 0; - - if (le16_to_cpu(th->it_len) < sizeof(struct ieee80211_radiotap_header)) - return 0; - - for (x = 0; x < NUM_RADIOTAP_ELEMENTS; x++) { - if (rt_el_present(th, x)) - bytes += radiotap_elem_to_bytes[x]; - } - - if (le16_to_cpu(th->it_len) < sizeof(struct ieee80211_radiotap_header) + bytes) - return 0; - - if (le16_to_cpu(th->it_len) > len) - return 0; - - return 1; -} - -static u_int8_t *rt_el_offset(struct ieee80211_radiotap_header *th, u_int32_t element) { - unsigned int x = 0; - u_int8_t *offset = ((u_int8_t *) th) + sizeof(struct ieee80211_radiotap_header); - for (x = 0; x < NUM_RADIOTAP_ELEMENTS && x < element; x++) { - if (rt_el_present(th, x)) - offset += radiotap_elem_to_bytes[x]; - } - - return offset; -} - #ifdef AR_DEBUG static void ath_keyprint(const char *tag, u_int ix, @@ -290,70 +120,6 @@ ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, } /* - * Set a net80211 key into the hardware. This handles the - * potential distribution of key state to multiple key - * cache slots for TKIP with hardware MIC support. - */ -static int -ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, - const u_int8_t mac0[IEEE80211_ADDR_LEN], - struct ieee80211_node *bss) -{ -#define N(a) (sizeof(a)/sizeof(a[0])) - static const u_int8_t ciphermap[] = { - AR5K_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ - AR5K_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ - AR5K_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ - AR5K_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ - (u_int8_t) -1, /* 4 is not allocated */ - AR5K_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ - AR5K_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ - }; - struct ath_hal *ah = sc->sc_ah; - const struct ieee80211_cipher *cip = k->wk_cipher; - u_int8_t gmac[IEEE80211_ADDR_LEN]; - const u_int8_t *mac; - AR5K_KEYVAL hk; - - memset(&hk, 0, sizeof(hk)); - /* - * Software crypto uses a "clear key" so non-crypto - * state kept in the key cache are maintained and - * so that rx frames have an entry to match. - */ - if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { - KASSERT(cip->ic_cipher < N(ciphermap), - ("invalid cipher type %u", cip->ic_cipher)); - hk.wk_type = ciphermap[cip->ic_cipher]; - hk.wk_len = k->wk_keylen; - memcpy(hk.wk_key, k->wk_key, k->wk_keylen); - } else - hk.wk_type = AR5K_CIPHER_CLR; - - if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { - /* - * Group keys on hardware that supports multicast frame - * key search use a mac that is the sender's address with - * the high bit set instead of the app-specified address. - */ - IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); - gmac[0] |= 0x80; - mac = gmac; - } else - mac = mac0; - - if (hk.wk_type == AR5K_CIPHER_TKIP && - (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && - sc->sc_splitmic) { - return ath_keyset_tkip(sc, k, &hk, mac); - } else { - KEYPRINTF(sc, k->wk_keyix, &hk, mac); - return ath5k_hw_set_key(ah, k->wk_keyix, &hk, mac, false); - } -#undef N -} - -/* * Allocate tx/rx key slots for TKIP. We allocate two slots for * each key, one for decrypt/encrypt and the other for the MIC. */ @@ -551,58 +317,6 @@ ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) } /* - * Block/unblock tx+rx processing while a key change is done. - * We assume the caller serializes key management operations - * so we only need to worry about synchronization with other - * uses that originate in the driver. - */ -static void -ath_key_update_begin(struct ieee80211com *ic) -{ - struct net_device *dev = ic->ic_dev; - struct ath_softc *sc = dev->priv; - - DPRINTF(sc, ATH_DEBUG_FATAL, "%lu %s (%s)\n", jiffies, __func__, dev->name); - DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); - /* - * When called from the rx tasklet we cannot use - * tasklet_disable because it will block waiting - * for us to complete execution. - * - * XXX Using in_softirq is not right since we might - * be called from other soft irq contexts than - * ath_rx_tasklet. - * TODO: can cause bugs - */ -#if 1 - if (!in_softirq()) - tasklet_disable(&sc->sc_rxtq); -#endif - netif_stop_queue(dev); // TODO: find a way to not block mgmt frames - if (sc->sc_rawdev_enabled) - netif_stop_queue(&sc->sc_rawdev); -} - -static void -ath_key_update_end(struct ieee80211com *ic) -{ - struct net_device *dev = ic->ic_dev; - struct ath_softc *sc = dev->priv; - - DPRINTF(sc, ATH_DEBUG_FATAL, "%lu %s (%s)\n", jiffies, __func__, dev->name); - DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); - netif_start_queue(dev); - if (sc->sc_rawdev_enabled) - netif_start_queue(&sc->sc_rawdev); -#if 1 - if (!in_softirq()) /* NB: see above */ - tasklet_enable(&sc->sc_rxtq); -#endif -} - - -#endif -/* * Set the slot time based on the current setting. * This is called by ath_updateslot below and when a non-ERP node * joins the network @@ -711,37 +425,6 @@ ath_wme_update(struct ieee80211com *ic) /* * Deferred processing of transmit interrupt; special-cased - * for a single hardware transmit queue (e.g. 5210 and 5211). - */ -static void -ath_tx_tasklet_q0(unsigned long data) -{ - struct net_device *dev = (struct net_device *)data; - struct ath_softc *sc = dev->priv; - - ath_tx_processq(sc, &sc->sc_txq[0]); - ath_tx_processq(sc, sc->sc_cabq); - - sc->sc_tx_timer = 0; - - if (sc->sc_softled) - ath_led_event(sc, ATH_LED_TX); - - // TODO: okay??? - /* - * Don't wakeup unless we're associated; this insures we don't - * signal the upper layer it's ok to start sending data frames. - */ - /* XXX use a low watermark to reduce wakeups */ - if (ic->ic_state == IEEE80211_S_RUN) - netif_wake_queue(dev); - - if (sc->sc_rawdev_enabled) - netif_wake_queue(&sc->sc_rawdev); -} - -/* - * Deferred processing of transmit interrupt; special-cased * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). */ static void @@ -778,44 +461,6 @@ ath_tx_tasklet_q0123(unsigned long data) } /* - * Deferred processing of transmit interrupt. - */ -static void -ath_tx_tasklet(unsigned long data) -{ - struct net_device *dev = (struct net_device *)data; - struct ath_softc *sc = dev->priv; - int i; - - /* - * Process each active queue. - */ - /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ - for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) { - if (ATH_TXQ_SETUP(sc, i)) - ath_tx_processq(sc, &sc->sc_txq[i]); - } - - sc->sc_tx_timer = 0; - - if (sc->sc_softled) - ath_led_event(sc, ATH_LED_TX); - - // TODO: okay??? - /* - * Don't wakeup unless we're associated; this insures we don't - * signal the upper layer it's ok to start sending data frames. - */ - /* XXX use a low watermark to reduce wakeups */ - if (ic->ic_state == IEEE80211_S_RUN) - netif_wake_queue(dev); - - if (sc->sc_rawdev_enabled) - netif_wake_queue(&sc->sc_rawdev); - -} - -/* * Allocate a key cache slot to the station so we can * setup a mapping from key index to node. The key cache * slot is needed for managing antenna state and for @@ -846,27 +491,6 @@ ath_setup_stationkey(struct ieee80211_node *ni) } /* - * Setup driver-specific state for a newly associated node. - * Note that we're called also on a re-associate, the isnew - * param tells us if this is the first time or not. - */ -static void -ath_newassoc(struct ieee80211_node *ni, int isnew) -{ - struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_dev->priv; - - ath_rate_newassoc(sc, ATH_NODE(ni), isnew); - if (isnew && - (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { - KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, - "new assoc with a unicast key already setup (keyix %u)", - ni->ni_ucastkey.wk_keyix); - ath_setup_stationkey(ni); - } -} - -/* * Return netdevice statistics. */ static struct net_device_stats * @@ -985,46 +609,11 @@ bad: static int ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { -#define IS_RUNNING(dev) \ - ((dev->flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) struct ath_softc *sc = dev->priv; int error = 0; ATH_LOCK(sc); switch (cmd) { - case SIOCSIFFLAGS: - if (IS_RUNNING(dev)) { - /* - * To avoid rescanning another access point, - * do not call ath_init() here. Instead, - * only reflect promisc mode settings. - */ - ath_mode_init(dev); - } else if (dev->flags & IFF_UP) { - /* - * Beware of being called during attach/detach - * to reset promiscuous mode. In that case we - * will still be marked UP but not RUNNING. - * However trying to re-init the interface - * is the wrong thing to do as we've already - * torn down much of our state. There's - * probably a better way to deal with this. - */ -// if (!sc->sc_invalid && ic->ic_bss != NULL) - ath_init(dev); /* XXX lose error */ - } else - ath_stop_locked(dev); - break; - case SIOCADDMULTI: - case SIOCDELMULTI: - /* - * The upper layer has already installed/removed - * the multicast address(es), just recalculate the - * multicast filter for the card. - */ - if (dev->flags & IFF_RUNNING) - ath_mode_init(dev); - break; case SIOCGATHSTATS: /* NB: embed these numbers to get a consistent view */ sc->sc_stats.ast_tx_packets = ic->ic_devstats->tx_packets; @@ -1049,17 +638,6 @@ ath_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) else error = ath_ioctl_ethtool(sc, cmd, ifr->ifr_data); break; - default: - error = ieee80211_ioctlx(ic, ifr, cmd); - if (error == -ENETRESET) { - if (IS_RUNNING(dev) && - ic->ic_roaming != IEEE80211_ROAMING_MANUAL) - ath_init(dev); /* XXX lose error */ - error = 0; - } - if (error == -ERESTART) - error = IS_RUNNING(dev) ? ath_reset(dev) : 0; - break; } ATH_UNLOCK(sc); return error; commit 292d622dff0548983cfe5646b3ac5136bdc67d37 Author: Jiri Slaby Date: Fri Jul 27 22:26:34 2007 +0200 prefer g over b diff --git a/ath.c b/ath.c index e4c79ba..28f4a7c 100644 --- a/ath.c +++ b/ath.c @@ -1866,8 +1866,8 @@ static int ath_getchannels(struct ieee80211_hw *hw) int ret; enum { A = MODE_IEEE80211A, - B = MODE_IEEE80211B, - G = MODE_IEEE80211G, + B = MODE_IEEE80211G, /* this is not a typo, but workaround */ + G = MODE_IEEE80211B, /* to prefer g over b */ T = MODE_ATHEROS_TURBO, TG = MODE_ATHEROS_TURBOG, }; commit 8f3458c033ee4261a5c8060007f15ad1e724d60b Author: Jiri Slaby Date: Sat Jul 28 22:13:47 2007 +0200 don't copy nonvalid rates diff --git a/ath.c b/ath.c index 28f4a7c..c455ca3 100644 --- a/ath.c +++ b/ath.c @@ -1738,18 +1738,23 @@ static inline short ath_ieee2mhz(short chan) static unsigned int ath_copy_rates(struct ieee80211_rate *rates, const struct ath5k_rate_table *rt, unsigned int max) { - unsigned int i; + unsigned int i, count; if (rt == NULL) return 0; - for (i = 0; i < rt->rate_count && max > 0; i++, rates++, max--) { + for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) { + if (!rt->rates[i].valid) + continue; rates->rate = rt->rates[i].rate_kbps / 100; rates->val = rt->rates[i].rate_code; rates->flags = rt->rates[i].modulation; + rates++; + count++; + max--; } - return i; + return count; } static unsigned int ath_copy_channels(struct ath_hw *ah, commit b39de83b677f49d269176419bf6849b3ff051ee1 Author: Jiri Slaby Date: Fri Aug 3 22:30:01 2007 +0200 remove unused ioctl structs diff --git a/ath_ioctl.h b/ath_ioctl.h index 6359248..34e6f0d 100644 --- a/ath_ioctl.h +++ b/ath_ioctl.h @@ -110,63 +110,4 @@ struct ath_stats { __u32 ast_ant_tx[8]; /* tx frames with antenna */ }; -struct ath_diag { - char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ - __u16 ad_id; -#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ -#define ATH_DIAG_IN 0x4000 /* copy in parameters */ -#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ -#define ATH_DIAG_ID 0x0fff - __u16 ad_in_size; /* pack to fit, yech */ - void __user *ad_in_data; - void __user *ad_out_data; - u_int ad_out_size; -}; - -/* - * Radio capture format. - */ -#define ATH_RX_RADIOTAP_PRESENT ( \ - (1 << IEEE80211_RADIOTAP_FLAGS) | \ - (1 << IEEE80211_RADIOTAP_RATE) | \ - (1 << IEEE80211_RADIOTAP_CHANNEL) | \ - (1 << IEEE80211_RADIOTAP_ANTENNA) | \ - (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ - 0) - -struct ath_rx_radiotap_header { - struct ieee80211_radiotap_header wr_ihdr; - __u8 wr_flags; /* XXX for padding */ - __u8 wr_rate; - __le16 wr_chan_freq; - __le16 wr_chan_flags; - __u8 wr_antenna; - __u8 wr_antsignal; -}; - -#define ATH_TX_RADIOTAP_PRESENT ( \ - (1 << IEEE80211_RADIOTAP_FLAGS) | \ - (1 << IEEE80211_RADIOTAP_RATE) | \ - (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ - (1 << IEEE80211_RADIOTAP_ANTENNA) | \ - (1 << IEEE80211_RADIOTAP_TX_FLAGS) | \ - (1 << IEEE80211_RADIOTAP_RTS_RETRIES) | \ - (1 << IEEE80211_RADIOTAP_DATA_RETRIES) | \ - 0) - -struct ath_tx_radiotap_header { - struct ieee80211_radiotap_header wt_ihdr; - __u8 wt_flags; /* XXX for padding */ - __u8 wt_rate; - __u8 wt_txpower; - __u8 wt_antenna; - __le16 wt_tx_flags; - __u8 wt_rts_retries; - __u8 wt_data_retries; - -}; - -#define SIOCGATHSTATS (SIOCDEVPRIVATE+0) -#define SIOCGATHDIAG (SIOCDEVPRIVATE+1) - #endif commit bb71b41b7e0862759804d071c8bc6aad754071dd Author: Jiri Slaby Date: Fri Aug 3 22:33:16 2007 +0200 rename ieee80211_regdomain to ath_regdom diff --git a/Makefile b/Makefile index 877d718..f5ce557 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ KDIR=/lib/modules/$(shell uname -r)/build KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) -ath5k-objs := ath.o ath5k_hw.o ieee80211_regdomain.o +ath5k-objs := ath.o ath5k_hw.o ath_regdom.o obj-m += ath5k.o diff --git a/ath5k.h b/ath5k.h index a62ecc5..9615fe3 100644 --- a/ath5k.h +++ b/ath5k.h @@ -32,7 +32,7 @@ #include #include "ath5k_hw.h" -#include "ieee80211_regdomain.h" +#include "ath_regdom.h" /* PCI IDs */ #ifndef PCI_VENDOR_ID_ATHEROS diff --git a/ath_regdom.c b/ath_regdom.c new file mode 100644 index 0000000..1da22aa --- /dev/null +++ b/ath_regdom.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2004, 2005 Reyk Floeter + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + */ + +/* + * Basic regulation domain extensions for the IEEE 802.11 stack + */ + +#include +#include + +#include "ath_regdom.h" + +static const struct ieee80211_regdomainmap { + enum ieee80211_regdomain dmn; + enum ieee80211_regdomain dmn5; + enum ieee80211_regdomain dmn2; +} r_map[] = { + { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, + { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, + { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, + { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, + { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, + { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, + { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, + { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, + { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, + { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, + { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, + { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, + { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, + { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, + { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, + { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, + { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, + { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, + { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, + { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, + { DMN_APL_NULL, DMN_APL1, DMN_NULL }, + { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, + { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, + { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, + { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, + { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, + { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, + { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, + { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, + { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, + { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, + { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, + { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, + { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, + { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, +}; + +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, + u16 mhz) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(r_map); i++) { + if (r_map[i].dmn == dmn) { + if (mhz >= 2000 && mhz <= 3000) + return r_map[i].dmn2; + if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && + mhz <= IEEE80211_CHANNELS_5GHZ_MAX) + return r_map[i].dmn5; + } + } + + return DMN_DEBUG; +} + +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) +{ + u32 regdomain = (u32)ieee; + + /* + * Use the default regulation domain if the value is empty + * or not supported by the net80211 regulation code. + */ + if (ieee80211_regdomain2flag(regdomain, + IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + return (u16)AR5K_TUNE_REGDOMAIN; + + /* It is supported, just return the value */ + return regdomain; +} + +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) +{ + enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; + + return ieee; +} + diff --git a/ath_regdom.h b/ath_regdom.h new file mode 100644 index 0000000..b5f67f3 --- /dev/null +++ b/ath_regdom.h @@ -0,0 +1,492 @@ +/* + * Copyright (c) 2004, 2005 Reyk Floeter + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + */ + +#ifndef _IEEE80211_REGDOMAIN_H_ +#define _IEEE80211_REGDOMAIN_H_ + +#include + +/* Default regulation domain if stored value EEPROM value is invalid */ +#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ +#define AR5K_TUNE_CTRY CTRY_DEFAULT + + +enum ieee80211_regdomain { + DMN_DEFAULT = 0x00, + DMN_NULL_WORLD = 0x03, + DMN_NULL_ETSIB = 0x07, + DMN_NULL_ETSIC = 0x08, + DMN_FCC1_FCCA = 0x10, + DMN_FCC1_WORLD = 0x11, + DMN_FCC2_FCCA = 0x20, + DMN_FCC2_WORLD = 0x21, + DMN_FCC2_ETSIC = 0x22, + DMN_FRANCE_NULL = 0x31, + DMN_FCC3_FCCA = 0x3A, + DMN_ETSI1_WORLD = 0x37, + DMN_ETSI3_ETSIA = 0x32, + DMN_ETSI2_WORLD = 0x35, + DMN_ETSI3_WORLD = 0x36, + DMN_ETSI4_WORLD = 0x30, + DMN_ETSI4_ETSIC = 0x38, + DMN_ETSI5_WORLD = 0x39, + DMN_ETSI6_WORLD = 0x34, + DMN_ETSI_NULL = 0x33, + DMN_MKK1_MKKA = 0x40, + DMN_MKK1_MKKB = 0x41, + DMN_APL4_WORLD = 0x42, + DMN_MKK2_MKKA = 0x43, + DMN_APL_NULL = 0x44, + DMN_APL2_WORLD = 0x45, + DMN_APL2_APLC = 0x46, + DMN_APL3_WORLD = 0x47, + DMN_MKK1_FCCA = 0x48, + DMN_APL2_APLD = 0x49, + DMN_MKK1_MKKA1 = 0x4A, + DMN_MKK1_MKKA2 = 0x4B, + DMN_APL1_WORLD = 0x52, + DMN_APL1_FCCA = 0x53, + DMN_APL1_APLA = 0x54, + DMN_APL1_ETSIC = 0x55, + DMN_APL2_ETSIC = 0x56, + DMN_APL5_WORLD = 0x58, + DMN_WOR0_WORLD = 0x60, + DMN_WOR1_WORLD = 0x61, + DMN_WOR2_WORLD = 0x62, + DMN_WOR3_WORLD = 0x63, + DMN_WOR4_WORLD = 0x64, + DMN_WOR5_ETSIC = 0x65, + DMN_WOR01_WORLD = 0x66, + DMN_WOR02_WORLD = 0x67, + DMN_EU1_WORLD = 0x68, + DMN_WOR9_WORLD = 0x69, + DMN_WORA_WORLD = 0x6A, + + DMN_APL1 = 0xf0000001, + DMN_APL2 = 0xf0000002, + DMN_APL3 = 0xf0000004, + DMN_APL4 = 0xf0000008, + DMN_APL5 = 0xf0000010, + DMN_ETSI1 = 0xf0000020, + DMN_ETSI2 = 0xf0000040, + DMN_ETSI3 = 0xf0000080, + DMN_ETSI4 = 0xf0000100, + DMN_ETSI5 = 0xf0000200, + DMN_ETSI6 = 0xf0000400, + DMN_ETSIA = 0xf0000800, + DMN_ETSIB = 0xf0001000, + DMN_ETSIC = 0xf0002000, + DMN_FCC1 = 0xf0004000, + DMN_FCC2 = 0xf0008000, + DMN_FCC3 = 0xf0010000, + DMN_FCCA = 0xf0020000, + DMN_APLD = 0xf0040000, + DMN_MKK1 = 0xf0080000, + DMN_MKK2 = 0xf0100000, + DMN_MKKA = 0xf0200000, + DMN_NULL = 0xf0400000, + DMN_WORLD = 0xf0800000, + DMN_DEBUG = 0xf1000000 /* used for debugging */ +}; + +#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) + +enum ieee80211_countrycode { + CTRY_DEFAULT = 0, /* Default domain (NA) */ + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_AUSTRALIA = 36, /* Australia */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CANADA = 124, /* Canada */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, /* Cyprus */ + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRI_LANKA = 728, /* Sri Lanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States */ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716, /* Zimbabwe */ +}; + +#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ +#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ +#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ +#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ + +struct ieee80211_regchannel { + u16 chan; + enum ieee80211_regdomain domain; + u32 mode; +}; + +#define IEEE80211_CHANNELS_2GHZ { \ +/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \ + \ +/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +} + +#define IEEE80211_CHANNELS_5GHZ { \ +/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \ + \ +/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \ + \ +/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \ + \ +/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \ + \ +/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \ + \ +/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \ +/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \ +/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \ +/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ +} + +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); + +#endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ diff --git a/ieee80211_regdomain.c b/ieee80211_regdomain.c deleted file mode 100644 index f5da7cf..0000000 --- a/ieee80211_regdomain.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - */ - -/* - * Basic regulation domain extensions for the IEEE 802.11 stack - */ - -#include -#include - -#include "ieee80211_regdomain.h" - -static const struct ieee80211_regdomainmap { - enum ieee80211_regdomain dmn; - enum ieee80211_regdomain dmn5; - enum ieee80211_regdomain dmn2; -} r_map[] = { - { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, - { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, - { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, - { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, - { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, - { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, - { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, - { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, - { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, - { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, - { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, - { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, - { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, - { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, - { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, - { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, - { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, - { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, - { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, - { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, - { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, - { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, - { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, - { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, - { DMN_APL_NULL, DMN_APL1, DMN_NULL }, - { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, - { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, - { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, - { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, - { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, - { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, - { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, - { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, - { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, - { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, - { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, - { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, - { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, - { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, - { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, - { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, -}; - -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, - u16 mhz) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(r_map); i++) { - if (r_map[i].dmn == dmn) { - if (mhz >= 2000 && mhz <= 3000) - return r_map[i].dmn2; - if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && - mhz <= IEEE80211_CHANNELS_5GHZ_MAX) - return r_map[i].dmn5; - } - } - - return DMN_DEBUG; -} - -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) -{ - u32 regdomain = (u32)ieee; - - /* - * Use the default regulation domain if the value is empty - * or not supported by the net80211 regulation code. - */ - if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) - return (u16)AR5K_TUNE_REGDOMAIN; - - /* It is supported, just return the value */ - return regdomain; -} - -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) -{ - enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; - - return ieee; -} - diff --git a/ieee80211_regdomain.h b/ieee80211_regdomain.h deleted file mode 100644 index b5f67f3..0000000 --- a/ieee80211_regdomain.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - */ - -#ifndef _IEEE80211_REGDOMAIN_H_ -#define _IEEE80211_REGDOMAIN_H_ - -#include - -/* Default regulation domain if stored value EEPROM value is invalid */ -#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ -#define AR5K_TUNE_CTRY CTRY_DEFAULT - - -enum ieee80211_regdomain { - DMN_DEFAULT = 0x00, - DMN_NULL_WORLD = 0x03, - DMN_NULL_ETSIB = 0x07, - DMN_NULL_ETSIC = 0x08, - DMN_FCC1_FCCA = 0x10, - DMN_FCC1_WORLD = 0x11, - DMN_FCC2_FCCA = 0x20, - DMN_FCC2_WORLD = 0x21, - DMN_FCC2_ETSIC = 0x22, - DMN_FRANCE_NULL = 0x31, - DMN_FCC3_FCCA = 0x3A, - DMN_ETSI1_WORLD = 0x37, - DMN_ETSI3_ETSIA = 0x32, - DMN_ETSI2_WORLD = 0x35, - DMN_ETSI3_WORLD = 0x36, - DMN_ETSI4_WORLD = 0x30, - DMN_ETSI4_ETSIC = 0x38, - DMN_ETSI5_WORLD = 0x39, - DMN_ETSI6_WORLD = 0x34, - DMN_ETSI_NULL = 0x33, - DMN_MKK1_MKKA = 0x40, - DMN_MKK1_MKKB = 0x41, - DMN_APL4_WORLD = 0x42, - DMN_MKK2_MKKA = 0x43, - DMN_APL_NULL = 0x44, - DMN_APL2_WORLD = 0x45, - DMN_APL2_APLC = 0x46, - DMN_APL3_WORLD = 0x47, - DMN_MKK1_FCCA = 0x48, - DMN_APL2_APLD = 0x49, - DMN_MKK1_MKKA1 = 0x4A, - DMN_MKK1_MKKA2 = 0x4B, - DMN_APL1_WORLD = 0x52, - DMN_APL1_FCCA = 0x53, - DMN_APL1_APLA = 0x54, - DMN_APL1_ETSIC = 0x55, - DMN_APL2_ETSIC = 0x56, - DMN_APL5_WORLD = 0x58, - DMN_WOR0_WORLD = 0x60, - DMN_WOR1_WORLD = 0x61, - DMN_WOR2_WORLD = 0x62, - DMN_WOR3_WORLD = 0x63, - DMN_WOR4_WORLD = 0x64, - DMN_WOR5_ETSIC = 0x65, - DMN_WOR01_WORLD = 0x66, - DMN_WOR02_WORLD = 0x67, - DMN_EU1_WORLD = 0x68, - DMN_WOR9_WORLD = 0x69, - DMN_WORA_WORLD = 0x6A, - - DMN_APL1 = 0xf0000001, - DMN_APL2 = 0xf0000002, - DMN_APL3 = 0xf0000004, - DMN_APL4 = 0xf0000008, - DMN_APL5 = 0xf0000010, - DMN_ETSI1 = 0xf0000020, - DMN_ETSI2 = 0xf0000040, - DMN_ETSI3 = 0xf0000080, - DMN_ETSI4 = 0xf0000100, - DMN_ETSI5 = 0xf0000200, - DMN_ETSI6 = 0xf0000400, - DMN_ETSIA = 0xf0000800, - DMN_ETSIB = 0xf0001000, - DMN_ETSIC = 0xf0002000, - DMN_FCC1 = 0xf0004000, - DMN_FCC2 = 0xf0008000, - DMN_FCC3 = 0xf0010000, - DMN_FCCA = 0xf0020000, - DMN_APLD = 0xf0040000, - DMN_MKK1 = 0xf0080000, - DMN_MKK2 = 0xf0100000, - DMN_MKKA = 0xf0200000, - DMN_NULL = 0xf0400000, - DMN_WORLD = 0xf0800000, - DMN_DEBUG = 0xf1000000 /* used for debugging */ -}; - -#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) - -enum ieee80211_countrycode { - CTRY_DEFAULT = 0, /* Default domain (NA) */ - CTRY_ALBANIA = 8, /* Albania */ - CTRY_ALGERIA = 12, /* Algeria */ - CTRY_ARGENTINA = 32, /* Argentina */ - CTRY_ARMENIA = 51, /* Armenia */ - CTRY_AUSTRALIA = 36, /* Australia */ - CTRY_AUSTRIA = 40, /* Austria */ - CTRY_AZERBAIJAN = 31, /* Azerbaijan */ - CTRY_BAHRAIN = 48, /* Bahrain */ - CTRY_BELARUS = 112, /* Belarus */ - CTRY_BELGIUM = 56, /* Belgium */ - CTRY_BELIZE = 84, /* Belize */ - CTRY_BOLIVIA = 68, /* Bolivia */ - CTRY_BRAZIL = 76, /* Brazil */ - CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ - CTRY_BULGARIA = 100, /* Bulgaria */ - CTRY_CANADA = 124, /* Canada */ - CTRY_CHILE = 152, /* Chile */ - CTRY_CHINA = 156, /* People's Republic of China */ - CTRY_COLOMBIA = 170, /* Colombia */ - CTRY_COSTA_RICA = 188, /* Costa Rica */ - CTRY_CROATIA = 191, /* Croatia */ - CTRY_CYPRUS = 196, /* Cyprus */ - CTRY_CZECH = 203, /* Czech Republic */ - CTRY_DENMARK = 208, /* Denmark */ - CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ - CTRY_ECUADOR = 218, /* Ecuador */ - CTRY_EGYPT = 818, /* Egypt */ - CTRY_EL_SALVADOR = 222, /* El Salvador */ - CTRY_ESTONIA = 233, /* Estonia */ - CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ - CTRY_FINLAND = 246, /* Finland */ - CTRY_FRANCE = 250, /* France */ - CTRY_FRANCE2 = 255, /* France2 */ - CTRY_GEORGIA = 268, /* Georgia */ - CTRY_GERMANY = 276, /* Germany */ - CTRY_GREECE = 300, /* Greece */ - CTRY_GUATEMALA = 320, /* Guatemala */ - CTRY_HONDURAS = 340, /* Honduras */ - CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ - CTRY_HUNGARY = 348, /* Hungary */ - CTRY_ICELAND = 352, /* Iceland */ - CTRY_INDIA = 356, /* India */ - CTRY_INDONESIA = 360, /* Indonesia */ - CTRY_IRAN = 364, /* Iran */ - CTRY_IRAQ = 368, /* Iraq */ - CTRY_IRELAND = 372, /* Ireland */ - CTRY_ISRAEL = 376, /* Israel */ - CTRY_ITALY = 380, /* Italy */ - CTRY_JAMAICA = 388, /* Jamaica */ - CTRY_JAPAN = 392, /* Japan */ - CTRY_JAPAN1 = 393, /* Japan (JP1) */ - CTRY_JAPAN2 = 394, /* Japan (JP0) */ - CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ - CTRY_JAPAN4 = 396, /* Japan (JE1) */ - CTRY_JAPAN5 = 397, /* Japan (JE2) */ - CTRY_JORDAN = 400, /* Jordan */ - CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ - CTRY_KENYA = 404, /* Kenya */ - CTRY_KOREA_NORTH = 408, /* North Korea */ - CTRY_KOREA_ROC = 410, /* South Korea */ - CTRY_KOREA_ROC2 = 411, /* South Korea */ - CTRY_KUWAIT = 414, /* Kuwait */ - CTRY_LATVIA = 428, /* Latvia */ - CTRY_LEBANON = 422, /* Lebanon */ - CTRY_LIBYA = 434, /* Libya */ - CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ - CTRY_LITHUANIA = 440, /* Lithuania */ - CTRY_LUXEMBOURG = 442, /* Luxembourg */ - CTRY_MACAU = 446, /* Macau */ - CTRY_MACEDONIA = 807, /* Republic of Macedonia */ - CTRY_MALAYSIA = 458, /* Malaysia */ - CTRY_MEXICO = 484, /* Mexico */ - CTRY_MONACO = 492, /* Principality of Monaco */ - CTRY_MOROCCO = 504, /* Morocco */ - CTRY_NETHERLANDS = 528, /* Netherlands */ - CTRY_NEW_ZEALAND = 554, /* New Zealand */ - CTRY_NICARAGUA = 558, /* Nicaragua */ - CTRY_NORWAY = 578, /* Norway */ - CTRY_OMAN = 512, /* Oman */ - CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ - CTRY_PANAMA = 591, /* Panama */ - CTRY_PARAGUAY = 600, /* Paraguay */ - CTRY_PERU = 604, /* Peru */ - CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ - CTRY_POLAND = 616, /* Poland */ - CTRY_PORTUGAL = 620, /* Portugal */ - CTRY_PUERTO_RICO = 630, /* Puerto Rico */ - CTRY_QATAR = 634, /* Qatar */ - CTRY_ROMANIA = 642, /* Romania */ - CTRY_RUSSIA = 643, /* Russia */ - CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ - CTRY_SINGAPORE = 702, /* Singapore */ - CTRY_SLOVAKIA = 703, /* Slovak Republic */ - CTRY_SLOVENIA = 705, /* Slovenia */ - CTRY_SOUTH_AFRICA = 710, /* South Africa */ - CTRY_SPAIN = 724, /* Spain */ - CTRY_SRI_LANKA = 728, /* Sri Lanka */ - CTRY_SWEDEN = 752, /* Sweden */ - CTRY_SWITZERLAND = 756, /* Switzerland */ - CTRY_SYRIA = 760, /* Syria */ - CTRY_TAIWAN = 158, /* Taiwan */ - CTRY_THAILAND = 764, /* Thailand */ - CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ - CTRY_TUNISIA = 788, /* Tunisia */ - CTRY_TURKEY = 792, /* Turkey */ - CTRY_UAE = 784, /* U.A.E. */ - CTRY_UKRAINE = 804, /* Ukraine */ - CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ - CTRY_UNITED_STATES = 840, /* United States */ - CTRY_URUGUAY = 858, /* Uruguay */ - CTRY_UZBEKISTAN = 860, /* Uzbekistan */ - CTRY_VENEZUELA = 862, /* Venezuela */ - CTRY_VIET_NAM = 704, /* Viet Nam */ - CTRY_YEMEN = 887, /* Yemen */ - CTRY_ZIMBABWE = 716, /* Zimbabwe */ -}; - -#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ -#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ -#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ -#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ - -struct ieee80211_regchannel { - u16 chan; - enum ieee80211_regdomain domain; - u32 mode; -}; - -#define IEEE80211_CHANNELS_2GHZ { \ -/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \ - \ -/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -} - -#define IEEE80211_CHANNELS_5GHZ { \ -/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \ - \ -/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \ - \ -/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \ - \ -/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \ -/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \ -/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \ -/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \ -/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \ -/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \ -/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \ -/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \ -/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \ - \ -/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \ -/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \ -/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \ - \ -/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \ -/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \ -/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \ -/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \ -/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \ -/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ -} - -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); - -#endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ commit d22f61acfd8493bf1dae2ff29b7bde7db285f0d0 Author: Jiri Slaby Date: Fri Aug 3 22:40:35 2007 +0200 remove ath_ioctl.h and move the stuff to the ath.h diff --git a/ath.h b/ath.h index c61119c..64d1ecf 100644 --- a/ath.h +++ b/ath.h @@ -48,7 +48,6 @@ #include #include "ath5k.h" -#include "ath_ioctl.h" #define ATH_TIMEOUT 1000 @@ -112,6 +111,72 @@ struct ath_txq { bool setup; }; +struct ath_stats { + __u32 ast_watchdog; /* device reset by watchdog */ + __u32 ast_hardware; /* fatal hardware error interrupts */ + __u32 ast_bmiss; /* beacon miss interrupts */ + __u32 ast_bstuck; /* beacon stuck interrupts */ + __u32 ast_rxorn; /* rx overrun interrupts */ + __u32 ast_rxeol; /* rx eol interrupts */ + __u32 ast_txurn; /* tx underrun interrupts */ + __u32 ast_mib; /* mib interrupts */ + __u32 ast_intrcoal; /* interrupts coalesced */ + __u32 ast_tx_packets; /* packet sent on the interface */ + __u32 ast_tx_mgmt; /* management frames transmitted */ + __u32 ast_tx_discard; /* frames discarded prior to assoc */ + __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ + __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ + __u32 ast_tx_encap; /* tx encapsulation failed */ + __u32 ast_tx_nonode; /* tx failed 'cuz no node */ + __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ + __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ + __u32 ast_tx_linear; /* tx linearized to cluster */ + __u32 ast_tx_nodata; /* tx discarded empty frame */ + __u32 ast_tx_busdma; /* tx failed for dma resrcs */ + __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ + __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ + __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ + __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ + __u32 ast_tx_longretry;/* tx on-chip retries (long) */ + __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ + __u32 ast_tx_noack; /* tx frames with no ack marked */ + __u32 ast_tx_rts; /* tx frames with rts enabled */ + __u32 ast_tx_cts; /* tx frames with cts enabled */ + __u32 ast_tx_shortpre;/* tx frames with short preamble */ + __u32 ast_tx_altrate; /* tx frames with alternate rate */ + __u32 ast_tx_protect; /* tx frames with protection */ + __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ + __u32 ast_tx_ctsext; /* tx frames with cts extension */ + __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ + __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ + __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ + __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ + __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ + __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ + __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ + __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ + __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ + __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ + __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ + __u32 ast_rx_packets; /* packet recv on the interface */ + __u32 ast_rx_mgt; /* management frames received */ + __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ + __s8 ast_tx_rssi; /* tx rssi of last ack */ + __s8 ast_rx_rssi; /* rx rssi from histogram */ + __u32 ast_be_xmit; /* beacons transmitted */ + __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ + __u32 ast_per_cal; /* periodic calibration calls */ + __u32 ast_per_calfail;/* periodic calibration failed */ + __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ + __u32 ast_rate_calls; /* rate control checks */ + __u32 ast_rate_raise; /* rate control raised xmit rate */ + __u32 ast_rate_drop; /* rate control dropped xmit rate */ + __u32 ast_ant_defswitch;/* rx/default antenna switches */ + __u32 ast_ant_txswitch;/* tx antenna switches */ + __u32 ast_ant_rx[8]; /* rx frames with antenna */ + __u32 ast_ant_tx[8]; /* tx frames with antenna */ +}; + #if CHAN_DEBUG #define ATH_CHAN_MAX (26+26+26+200+200) #else diff --git a/ath_ioctl.h b/ath_ioctl.h deleted file mode 100644 index 34e6f0d..0000000 --- a/ath_ioctl.h +++ /dev/null @@ -1,113 +0,0 @@ -/*- - * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD: src/sys/dev/ath/if_athioctl.h,v 1.9 2004/12/31 22:41:45 sam Exp $ - */ - -/* - * Ioctl-related defintions for the Atheros Wireless LAN controller driver. - */ -#ifndef _DEV_ATH_ATHIOCTL_H -#define _DEV_ATH_ATHIOCTL_H - -#include - -struct ath_stats { - __u32 ast_watchdog; /* device reset by watchdog */ - __u32 ast_hardware; /* fatal hardware error interrupts */ - __u32 ast_bmiss; /* beacon miss interrupts */ - __u32 ast_bstuck; /* beacon stuck interrupts */ - __u32 ast_rxorn; /* rx overrun interrupts */ - __u32 ast_rxeol; /* rx eol interrupts */ - __u32 ast_txurn; /* tx underrun interrupts */ - __u32 ast_mib; /* mib interrupts */ - __u32 ast_intrcoal; /* interrupts coalesced */ - __u32 ast_tx_packets; /* packet sent on the interface */ - __u32 ast_tx_mgmt; /* management frames transmitted */ - __u32 ast_tx_discard; /* frames discarded prior to assoc */ - __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ - __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ - __u32 ast_tx_encap; /* tx encapsulation failed */ - __u32 ast_tx_nonode; /* tx failed 'cuz no node */ - __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ - __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ - __u32 ast_tx_linear; /* tx linearized to cluster */ - __u32 ast_tx_nodata; /* tx discarded empty frame */ - __u32 ast_tx_busdma; /* tx failed for dma resrcs */ - __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ - __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ - __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ - __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ - __u32 ast_tx_longretry;/* tx on-chip retries (long) */ - __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ - __u32 ast_tx_noack; /* tx frames with no ack marked */ - __u32 ast_tx_rts; /* tx frames with rts enabled */ - __u32 ast_tx_cts; /* tx frames with cts enabled */ - __u32 ast_tx_shortpre;/* tx frames with short preamble */ - __u32 ast_tx_altrate; /* tx frames with alternate rate */ - __u32 ast_tx_protect; /* tx frames with protection */ - __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ - __u32 ast_tx_ctsext; /* tx frames with cts extension */ - __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ - __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ - __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ - __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ - __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ - __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ - __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ - __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ - __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ - __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ - __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ - __u32 ast_rx_packets; /* packet recv on the interface */ - __u32 ast_rx_mgt; /* management frames received */ - __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ - __s8 ast_tx_rssi; /* tx rssi of last ack */ - __s8 ast_rx_rssi; /* rx rssi from histogram */ - __u32 ast_be_xmit; /* beacons transmitted */ - __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ - __u32 ast_per_cal; /* periodic calibration calls */ - __u32 ast_per_calfail;/* periodic calibration failed */ - __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ - __u32 ast_rate_calls; /* rate control checks */ - __u32 ast_rate_raise; /* rate control raised xmit rate */ - __u32 ast_rate_drop; /* rate control dropped xmit rate */ - __u32 ast_ant_defswitch;/* rx/default antenna switches */ - __u32 ast_ant_txswitch;/* tx antenna switches */ - __u32 ast_ant_rx[8]; /* rx frames with antenna */ - __u32 ast_ant_tx[8]; /* tx frames with antenna */ -}; - -#endif commit 020b108495f471dc94ed855bf8e8d8edc5b03066 Author: Jiri Slaby Date: Fri Aug 3 22:41:55 2007 +0200 rename ath_regdom to ath5k_regdom (sorry :)) diff --git a/Makefile b/Makefile index f5ce557..5d941fe 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ KDIR=/lib/modules/$(shell uname -r)/build KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) -ath5k-objs := ath.o ath5k_hw.o ath_regdom.o +ath5k-objs := ath.o ath5k_hw.o ath5k_regdom.o obj-m += ath5k.o diff --git a/ath5k.h b/ath5k.h index 9615fe3..37d7bf9 100644 --- a/ath5k.h +++ b/ath5k.h @@ -32,7 +32,7 @@ #include #include "ath5k_hw.h" -#include "ath_regdom.h" +#include "ath5k_regdom.h" /* PCI IDs */ #ifndef PCI_VENDOR_ID_ATHEROS diff --git a/ath5k_regdom.c b/ath5k_regdom.c new file mode 100644 index 0000000..cdbc618 --- /dev/null +++ b/ath5k_regdom.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2004, 2005 Reyk Floeter + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + */ + +/* + * Basic regulation domain extensions for the IEEE 802.11 stack + */ + +#include +#include + +#include "ath5k_regdom.h" + +static const struct ieee80211_regdomainmap { + enum ieee80211_regdomain dmn; + enum ieee80211_regdomain dmn5; + enum ieee80211_regdomain dmn2; +} r_map[] = { + { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, + { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, + { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, + { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, + { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, + { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, + { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, + { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, + { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, + { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, + { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, + { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, + { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, + { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, + { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, + { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, + { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, + { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, + { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, + { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, + { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, + { DMN_APL_NULL, DMN_APL1, DMN_NULL }, + { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, + { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, + { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, + { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, + { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, + { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, + { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, + { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, + { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, + { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, + { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, + { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, + { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, + { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, + { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, + { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, + { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, +}; + +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, + u16 mhz) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(r_map); i++) { + if (r_map[i].dmn == dmn) { + if (mhz >= 2000 && mhz <= 3000) + return r_map[i].dmn2; + if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && + mhz <= IEEE80211_CHANNELS_5GHZ_MAX) + return r_map[i].dmn5; + } + } + + return DMN_DEBUG; +} + +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) +{ + u32 regdomain = (u32)ieee; + + /* + * Use the default regulation domain if the value is empty + * or not supported by the net80211 regulation code. + */ + if (ieee80211_regdomain2flag(regdomain, + IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + return (u16)AR5K_TUNE_REGDOMAIN; + + /* It is supported, just return the value */ + return regdomain; +} + +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) +{ + enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; + + return ieee; +} + diff --git a/ath5k_regdom.h b/ath5k_regdom.h new file mode 100644 index 0000000..b5f67f3 --- /dev/null +++ b/ath5k_regdom.h @@ -0,0 +1,492 @@ +/* + * Copyright (c) 2004, 2005 Reyk Floeter + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + */ + +#ifndef _IEEE80211_REGDOMAIN_H_ +#define _IEEE80211_REGDOMAIN_H_ + +#include + +/* Default regulation domain if stored value EEPROM value is invalid */ +#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ +#define AR5K_TUNE_CTRY CTRY_DEFAULT + + +enum ieee80211_regdomain { + DMN_DEFAULT = 0x00, + DMN_NULL_WORLD = 0x03, + DMN_NULL_ETSIB = 0x07, + DMN_NULL_ETSIC = 0x08, + DMN_FCC1_FCCA = 0x10, + DMN_FCC1_WORLD = 0x11, + DMN_FCC2_FCCA = 0x20, + DMN_FCC2_WORLD = 0x21, + DMN_FCC2_ETSIC = 0x22, + DMN_FRANCE_NULL = 0x31, + DMN_FCC3_FCCA = 0x3A, + DMN_ETSI1_WORLD = 0x37, + DMN_ETSI3_ETSIA = 0x32, + DMN_ETSI2_WORLD = 0x35, + DMN_ETSI3_WORLD = 0x36, + DMN_ETSI4_WORLD = 0x30, + DMN_ETSI4_ETSIC = 0x38, + DMN_ETSI5_WORLD = 0x39, + DMN_ETSI6_WORLD = 0x34, + DMN_ETSI_NULL = 0x33, + DMN_MKK1_MKKA = 0x40, + DMN_MKK1_MKKB = 0x41, + DMN_APL4_WORLD = 0x42, + DMN_MKK2_MKKA = 0x43, + DMN_APL_NULL = 0x44, + DMN_APL2_WORLD = 0x45, + DMN_APL2_APLC = 0x46, + DMN_APL3_WORLD = 0x47, + DMN_MKK1_FCCA = 0x48, + DMN_APL2_APLD = 0x49, + DMN_MKK1_MKKA1 = 0x4A, + DMN_MKK1_MKKA2 = 0x4B, + DMN_APL1_WORLD = 0x52, + DMN_APL1_FCCA = 0x53, + DMN_APL1_APLA = 0x54, + DMN_APL1_ETSIC = 0x55, + DMN_APL2_ETSIC = 0x56, + DMN_APL5_WORLD = 0x58, + DMN_WOR0_WORLD = 0x60, + DMN_WOR1_WORLD = 0x61, + DMN_WOR2_WORLD = 0x62, + DMN_WOR3_WORLD = 0x63, + DMN_WOR4_WORLD = 0x64, + DMN_WOR5_ETSIC = 0x65, + DMN_WOR01_WORLD = 0x66, + DMN_WOR02_WORLD = 0x67, + DMN_EU1_WORLD = 0x68, + DMN_WOR9_WORLD = 0x69, + DMN_WORA_WORLD = 0x6A, + + DMN_APL1 = 0xf0000001, + DMN_APL2 = 0xf0000002, + DMN_APL3 = 0xf0000004, + DMN_APL4 = 0xf0000008, + DMN_APL5 = 0xf0000010, + DMN_ETSI1 = 0xf0000020, + DMN_ETSI2 = 0xf0000040, + DMN_ETSI3 = 0xf0000080, + DMN_ETSI4 = 0xf0000100, + DMN_ETSI5 = 0xf0000200, + DMN_ETSI6 = 0xf0000400, + DMN_ETSIA = 0xf0000800, + DMN_ETSIB = 0xf0001000, + DMN_ETSIC = 0xf0002000, + DMN_FCC1 = 0xf0004000, + DMN_FCC2 = 0xf0008000, + DMN_FCC3 = 0xf0010000, + DMN_FCCA = 0xf0020000, + DMN_APLD = 0xf0040000, + DMN_MKK1 = 0xf0080000, + DMN_MKK2 = 0xf0100000, + DMN_MKKA = 0xf0200000, + DMN_NULL = 0xf0400000, + DMN_WORLD = 0xf0800000, + DMN_DEBUG = 0xf1000000 /* used for debugging */ +}; + +#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) + +enum ieee80211_countrycode { + CTRY_DEFAULT = 0, /* Default domain (NA) */ + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_AUSTRALIA = 36, /* Australia */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CANADA = 124, /* Canada */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, /* Cyprus */ + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRI_LANKA = 728, /* Sri Lanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States */ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716, /* Zimbabwe */ +}; + +#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ +#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ +#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ +#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ + +struct ieee80211_regchannel { + u16 chan; + enum ieee80211_regdomain domain; + u32 mode; +}; + +#define IEEE80211_CHANNELS_2GHZ { \ +/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + \ +/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \ + \ +/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ +} + +#define IEEE80211_CHANNELS_5GHZ { \ +/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \ + \ +/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \ + \ +/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \ + \ +/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \ +/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \ +/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \ +/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \ +/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \ +/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \ +/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \ +/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \ +/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \ +/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \ +/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \ +/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \ +/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \ +/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \ +/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \ +/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \ +/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \ +/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \ +/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \ +/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \ +/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \ +/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \ +/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \ +/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ +/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \ +/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \ + \ +/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \ + \ +/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \ +/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \ +/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \ +/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \ +/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \ +/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \ +/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \ + \ +/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \ +/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \ +/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \ +/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ +} + +enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); +u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); +enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); + +#endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ diff --git a/ath_regdom.c b/ath_regdom.c deleted file mode 100644 index 1da22aa..0000000 --- a/ath_regdom.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - */ - -/* - * Basic regulation domain extensions for the IEEE 802.11 stack - */ - -#include -#include - -#include "ath_regdom.h" - -static const struct ieee80211_regdomainmap { - enum ieee80211_regdomain dmn; - enum ieee80211_regdomain dmn5; - enum ieee80211_regdomain dmn2; -} r_map[] = { - { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, - { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, - { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, - { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, - { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, - { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, - { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, - { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, - { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, - { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, - { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, - { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, - { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, - { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, - { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, - { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, - { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, - { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, - { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, - { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, - { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, - { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, - { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, - { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, - { DMN_APL_NULL, DMN_APL1, DMN_NULL }, - { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, - { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, - { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, - { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, - { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, - { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, - { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, - { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, - { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, - { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, - { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, - { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, - { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, - { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, - { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, - { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, - { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, -}; - -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, - u16 mhz) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(r_map); i++) { - if (r_map[i].dmn == dmn) { - if (mhz >= 2000 && mhz <= 3000) - return r_map[i].dmn2; - if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN && - mhz <= IEEE80211_CHANNELS_5GHZ_MAX) - return r_map[i].dmn5; - } - } - - return DMN_DEBUG; -} - -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) -{ - u32 regdomain = (u32)ieee; - - /* - * Use the default regulation domain if the value is empty - * or not supported by the net80211 regulation code. - */ - if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) - return (u16)AR5K_TUNE_REGDOMAIN; - - /* It is supported, just return the value */ - return regdomain; -} - -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) -{ - enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; - - return ieee; -} - diff --git a/ath_regdom.h b/ath_regdom.h deleted file mode 100644 index b5f67f3..0000000 --- a/ath_regdom.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - */ - -#ifndef _IEEE80211_REGDOMAIN_H_ -#define _IEEE80211_REGDOMAIN_H_ - -#include - -/* Default regulation domain if stored value EEPROM value is invalid */ -#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ -#define AR5K_TUNE_CTRY CTRY_DEFAULT - - -enum ieee80211_regdomain { - DMN_DEFAULT = 0x00, - DMN_NULL_WORLD = 0x03, - DMN_NULL_ETSIB = 0x07, - DMN_NULL_ETSIC = 0x08, - DMN_FCC1_FCCA = 0x10, - DMN_FCC1_WORLD = 0x11, - DMN_FCC2_FCCA = 0x20, - DMN_FCC2_WORLD = 0x21, - DMN_FCC2_ETSIC = 0x22, - DMN_FRANCE_NULL = 0x31, - DMN_FCC3_FCCA = 0x3A, - DMN_ETSI1_WORLD = 0x37, - DMN_ETSI3_ETSIA = 0x32, - DMN_ETSI2_WORLD = 0x35, - DMN_ETSI3_WORLD = 0x36, - DMN_ETSI4_WORLD = 0x30, - DMN_ETSI4_ETSIC = 0x38, - DMN_ETSI5_WORLD = 0x39, - DMN_ETSI6_WORLD = 0x34, - DMN_ETSI_NULL = 0x33, - DMN_MKK1_MKKA = 0x40, - DMN_MKK1_MKKB = 0x41, - DMN_APL4_WORLD = 0x42, - DMN_MKK2_MKKA = 0x43, - DMN_APL_NULL = 0x44, - DMN_APL2_WORLD = 0x45, - DMN_APL2_APLC = 0x46, - DMN_APL3_WORLD = 0x47, - DMN_MKK1_FCCA = 0x48, - DMN_APL2_APLD = 0x49, - DMN_MKK1_MKKA1 = 0x4A, - DMN_MKK1_MKKA2 = 0x4B, - DMN_APL1_WORLD = 0x52, - DMN_APL1_FCCA = 0x53, - DMN_APL1_APLA = 0x54, - DMN_APL1_ETSIC = 0x55, - DMN_APL2_ETSIC = 0x56, - DMN_APL5_WORLD = 0x58, - DMN_WOR0_WORLD = 0x60, - DMN_WOR1_WORLD = 0x61, - DMN_WOR2_WORLD = 0x62, - DMN_WOR3_WORLD = 0x63, - DMN_WOR4_WORLD = 0x64, - DMN_WOR5_ETSIC = 0x65, - DMN_WOR01_WORLD = 0x66, - DMN_WOR02_WORLD = 0x67, - DMN_EU1_WORLD = 0x68, - DMN_WOR9_WORLD = 0x69, - DMN_WORA_WORLD = 0x6A, - - DMN_APL1 = 0xf0000001, - DMN_APL2 = 0xf0000002, - DMN_APL3 = 0xf0000004, - DMN_APL4 = 0xf0000008, - DMN_APL5 = 0xf0000010, - DMN_ETSI1 = 0xf0000020, - DMN_ETSI2 = 0xf0000040, - DMN_ETSI3 = 0xf0000080, - DMN_ETSI4 = 0xf0000100, - DMN_ETSI5 = 0xf0000200, - DMN_ETSI6 = 0xf0000400, - DMN_ETSIA = 0xf0000800, - DMN_ETSIB = 0xf0001000, - DMN_ETSIC = 0xf0002000, - DMN_FCC1 = 0xf0004000, - DMN_FCC2 = 0xf0008000, - DMN_FCC3 = 0xf0010000, - DMN_FCCA = 0xf0020000, - DMN_APLD = 0xf0040000, - DMN_MKK1 = 0xf0080000, - DMN_MKK2 = 0xf0100000, - DMN_MKKA = 0xf0200000, - DMN_NULL = 0xf0400000, - DMN_WORLD = 0xf0800000, - DMN_DEBUG = 0xf1000000 /* used for debugging */ -}; - -#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) - -enum ieee80211_countrycode { - CTRY_DEFAULT = 0, /* Default domain (NA) */ - CTRY_ALBANIA = 8, /* Albania */ - CTRY_ALGERIA = 12, /* Algeria */ - CTRY_ARGENTINA = 32, /* Argentina */ - CTRY_ARMENIA = 51, /* Armenia */ - CTRY_AUSTRALIA = 36, /* Australia */ - CTRY_AUSTRIA = 40, /* Austria */ - CTRY_AZERBAIJAN = 31, /* Azerbaijan */ - CTRY_BAHRAIN = 48, /* Bahrain */ - CTRY_BELARUS = 112, /* Belarus */ - CTRY_BELGIUM = 56, /* Belgium */ - CTRY_BELIZE = 84, /* Belize */ - CTRY_BOLIVIA = 68, /* Bolivia */ - CTRY_BRAZIL = 76, /* Brazil */ - CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ - CTRY_BULGARIA = 100, /* Bulgaria */ - CTRY_CANADA = 124, /* Canada */ - CTRY_CHILE = 152, /* Chile */ - CTRY_CHINA = 156, /* People's Republic of China */ - CTRY_COLOMBIA = 170, /* Colombia */ - CTRY_COSTA_RICA = 188, /* Costa Rica */ - CTRY_CROATIA = 191, /* Croatia */ - CTRY_CYPRUS = 196, /* Cyprus */ - CTRY_CZECH = 203, /* Czech Republic */ - CTRY_DENMARK = 208, /* Denmark */ - CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ - CTRY_ECUADOR = 218, /* Ecuador */ - CTRY_EGYPT = 818, /* Egypt */ - CTRY_EL_SALVADOR = 222, /* El Salvador */ - CTRY_ESTONIA = 233, /* Estonia */ - CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ - CTRY_FINLAND = 246, /* Finland */ - CTRY_FRANCE = 250, /* France */ - CTRY_FRANCE2 = 255, /* France2 */ - CTRY_GEORGIA = 268, /* Georgia */ - CTRY_GERMANY = 276, /* Germany */ - CTRY_GREECE = 300, /* Greece */ - CTRY_GUATEMALA = 320, /* Guatemala */ - CTRY_HONDURAS = 340, /* Honduras */ - CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ - CTRY_HUNGARY = 348, /* Hungary */ - CTRY_ICELAND = 352, /* Iceland */ - CTRY_INDIA = 356, /* India */ - CTRY_INDONESIA = 360, /* Indonesia */ - CTRY_IRAN = 364, /* Iran */ - CTRY_IRAQ = 368, /* Iraq */ - CTRY_IRELAND = 372, /* Ireland */ - CTRY_ISRAEL = 376, /* Israel */ - CTRY_ITALY = 380, /* Italy */ - CTRY_JAMAICA = 388, /* Jamaica */ - CTRY_JAPAN = 392, /* Japan */ - CTRY_JAPAN1 = 393, /* Japan (JP1) */ - CTRY_JAPAN2 = 394, /* Japan (JP0) */ - CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ - CTRY_JAPAN4 = 396, /* Japan (JE1) */ - CTRY_JAPAN5 = 397, /* Japan (JE2) */ - CTRY_JORDAN = 400, /* Jordan */ - CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ - CTRY_KENYA = 404, /* Kenya */ - CTRY_KOREA_NORTH = 408, /* North Korea */ - CTRY_KOREA_ROC = 410, /* South Korea */ - CTRY_KOREA_ROC2 = 411, /* South Korea */ - CTRY_KUWAIT = 414, /* Kuwait */ - CTRY_LATVIA = 428, /* Latvia */ - CTRY_LEBANON = 422, /* Lebanon */ - CTRY_LIBYA = 434, /* Libya */ - CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ - CTRY_LITHUANIA = 440, /* Lithuania */ - CTRY_LUXEMBOURG = 442, /* Luxembourg */ - CTRY_MACAU = 446, /* Macau */ - CTRY_MACEDONIA = 807, /* Republic of Macedonia */ - CTRY_MALAYSIA = 458, /* Malaysia */ - CTRY_MEXICO = 484, /* Mexico */ - CTRY_MONACO = 492, /* Principality of Monaco */ - CTRY_MOROCCO = 504, /* Morocco */ - CTRY_NETHERLANDS = 528, /* Netherlands */ - CTRY_NEW_ZEALAND = 554, /* New Zealand */ - CTRY_NICARAGUA = 558, /* Nicaragua */ - CTRY_NORWAY = 578, /* Norway */ - CTRY_OMAN = 512, /* Oman */ - CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ - CTRY_PANAMA = 591, /* Panama */ - CTRY_PARAGUAY = 600, /* Paraguay */ - CTRY_PERU = 604, /* Peru */ - CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ - CTRY_POLAND = 616, /* Poland */ - CTRY_PORTUGAL = 620, /* Portugal */ - CTRY_PUERTO_RICO = 630, /* Puerto Rico */ - CTRY_QATAR = 634, /* Qatar */ - CTRY_ROMANIA = 642, /* Romania */ - CTRY_RUSSIA = 643, /* Russia */ - CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ - CTRY_SINGAPORE = 702, /* Singapore */ - CTRY_SLOVAKIA = 703, /* Slovak Republic */ - CTRY_SLOVENIA = 705, /* Slovenia */ - CTRY_SOUTH_AFRICA = 710, /* South Africa */ - CTRY_SPAIN = 724, /* Spain */ - CTRY_SRI_LANKA = 728, /* Sri Lanka */ - CTRY_SWEDEN = 752, /* Sweden */ - CTRY_SWITZERLAND = 756, /* Switzerland */ - CTRY_SYRIA = 760, /* Syria */ - CTRY_TAIWAN = 158, /* Taiwan */ - CTRY_THAILAND = 764, /* Thailand */ - CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ - CTRY_TUNISIA = 788, /* Tunisia */ - CTRY_TURKEY = 792, /* Turkey */ - CTRY_UAE = 784, /* U.A.E. */ - CTRY_UKRAINE = 804, /* Ukraine */ - CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ - CTRY_UNITED_STATES = 840, /* United States */ - CTRY_URUGUAY = 858, /* Uruguay */ - CTRY_UZBEKISTAN = 860, /* Uzbekistan */ - CTRY_VENEZUELA = 862, /* Venezuela */ - CTRY_VIET_NAM = 704, /* Viet Nam */ - CTRY_YEMEN = 887, /* Yemen */ - CTRY_ZIMBABWE = 716, /* Zimbabwe */ -}; - -#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */ -#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */ -#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ -#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ - -struct ieee80211_regchannel { - u16 chan; - enum ieee80211_regdomain domain; - u32 mode; -}; - -#define IEEE80211_CHANNELS_2GHZ { \ -/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ - \ -/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \ - \ -/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ -} - -#define IEEE80211_CHANNELS_5GHZ { \ -/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \ - \ -/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \ - \ -/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \ - \ -/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \ -/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \ -/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \ -/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \ -/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \ -/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \ -/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \ -/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \ -/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \ -/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \ -/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \ -/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \ -/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \ -/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \ -/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \ -/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \ -/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \ -/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \ -/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \ -/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \ -/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \ -/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \ -/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \ -/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \ -/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \ -/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \ -/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \ -/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ -/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \ -/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \ - \ -/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \ -/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \ -/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \ - \ -/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \ -/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \ -/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \ -/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \ -/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \ -/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \ -/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \ - \ -/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \ -/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \ -/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \ -/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ -} - -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); - -#endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ commit 307af1838f7d3ac4127742ac8c988ce347e05140 Author: Jiri Slaby Date: Fri Aug 3 22:55:11 2007 +0200 remove ath5k.h and move the stuff to the ath5k_hw.h mostly diff --git a/ath.h b/ath.h index 64d1ecf..26a8126 100644 --- a/ath.h +++ b/ath.h @@ -47,7 +47,14 @@ #include #include -#include "ath5k.h" +#include "ath5k_hw.h" + +/* Set this to 1 to disable regulatory domain restrictions for channel tests. + * WARNING: This is for debuging only and has side effects (eg. scan takes too + * long and results timeouts). It's also illegal to tune to some of the + * supported frequencies in some countries, so use this at your own risk, + * you've been warned. */ +#define CHAN_DEBUG 0 #define ATH_TIMEOUT 1000 diff --git a/ath5k.h b/ath5k.h deleted file mode 100644 index 37d7bf9..0000000 --- a/ath5k.h +++ /dev/null @@ -1,1053 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AR5K_H -#define _AR5K_H - -/* Set this to 1 to disable regulatory domain restrictions for channel tests. - * WARNING: This is for debuging only and has side effects (eg. scan takes too - * long and results timeouts). It's also illegal to tune to some of the - * supported frequencies in some countries, so use this at your own risk, - * you've been warned. */ -#define CHAN_DEBUG 0 - -/* Uncomment this for debuging (warning that it results in TOO much output) */ -/*#define AR5K_DEBUG 1 */ - -#include -#include - -#include "ath5k_hw.h" -#include "ath5k_regdom.h" - -/* PCI IDs */ -#ifndef PCI_VENDOR_ID_ATHEROS -#define PCI_VENDOR_ID_ATHEROS 0x168c -#endif -#ifndef PCI_VENDOR_ID_3COM_2 -#define PCI_VENDOR_ID_3COM_2 0xa727 -#endif - -#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ -#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ -#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ -#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ -#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ -#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ -#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ -#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ - -/****************************\ - GENERIC DRIVER DEFINITIONS -\****************************/ - -#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) -#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) -#ifdef AR5K_DEBUG -#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) -#else -#define AR5K_TRACE -#endif -#define howmany(x, y) (((x)+((y)-1))/(y)) - -/* - * Some tuneable values (these should be changeable by the user) - */ -#define AR5K_TUNE_DMA_BEACON_RESP 2 -#define AR5K_TUNE_SW_BEACON_RESP 10 -#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 -#define AR5K_TUNE_RADAR_ALERT false -#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 -#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) -#define AR5K_TUNE_RSSI_THRES 1792 -#define AR5K_TUNE_REGISTER_TIMEOUT 20000 -#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 -#define AR5K_TUNE_BEACON_INTERVAL 100 -#define AR5K_TUNE_AIFS 2 -#define AR5K_TUNE_AIFS_11B 2 -#define AR5K_TUNE_AIFS_XR 0 -#define AR5K_TUNE_CWMIN 15 -#define AR5K_TUNE_CWMIN_11B 31 -#define AR5K_TUNE_CWMIN_XR 3 -#define AR5K_TUNE_CWMAX 1023 -#define AR5K_TUNE_CWMAX_11B 1023 -#define AR5K_TUNE_CWMAX_XR 7 -#define AR5K_TUNE_NOISE_FLOOR -72 -#define AR5K_TUNE_MAX_TXPOWER 60 -#define AR5K_TUNE_DEFAULT_TXPOWER 30 -#define AR5K_TUNE_TPC_TXPOWER true -#define AR5K_TUNE_ANT_DIVERSITY true -#define AR5K_TUNE_HWTXTRIES 4 - -/* token to use for aifs, cwmin, cwmax in MadWiFi */ -#define AR5K_TXQ_USEDEFAULT ((u32) -1) - -/* GENERIC CHIPSET DEFINITIONS */ - -/* MAC Chips */ -enum ath5k_version { - AR5K_AR5210 = 0, - AR5K_AR5211 = 1, - AR5K_AR5212 = 2, -}; - -/* PHY Chips */ -enum ath5k_radio { - AR5K_RF5110 = 0, - AR5K_RF5111 = 1, - AR5K_RF5112 = 2, -}; - -/* - * Common silicon revision/version values - */ -enum ath5k_srev_type { - AR5K_VERSION_VER, - AR5K_VERSION_REV, - AR5K_VERSION_RAD, - AR5K_VERSION_DEV -}; - -struct ath5k_srev_name { - const char *sr_name; - enum ath5k_srev_type sr_type; - u_int sr_val; -}; - -#define AR5K_SREV_NAME { \ - { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ - { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ - { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ - { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ - { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ - { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ - { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ - { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ - { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ - { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ - { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ - { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ - { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ - { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ - { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ - { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ - { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ - { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ - { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ - { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ -} - -#define AR5K_SREV_UNKNOWN 0xffff - -#define AR5K_SREV_VER_AR5210 0x00 -#define AR5K_SREV_VER_AR5311 0x10 -#define AR5K_SREV_VER_AR5311A 0x20 -#define AR5K_SREV_VER_AR5311B 0x30 -#define AR5K_SREV_VER_AR5211 0x40 -#define AR5K_SREV_VER_AR5212 0x50 -#define AR5K_SREV_VER_AR5213 0x55 -#define AR5K_SREV_VER_UNSUPP 0x60 - -#define AR5K_SREV_RAD_5110 0x00 -#define AR5K_SREV_RAD_5111 0x10 -#define AR5K_SREV_RAD_5111A 0x15 -#define AR5K_SREV_RAD_2111 0x20 -#define AR5K_SREV_RAD_5112 0x30 -#define AR5K_SREV_RAD_5112A 0x35 -#define AR5K_SREV_RAD_2112 0x40 -#define AR5K_SREV_RAD_2112A 0x45 -#define AR5K_SREV_RAD_UNSUPP 0x50 - - -/* IEEE defs */ - -#define IEEE80211_MAX_LEN 2500 - -#define MAX_PDU_LENGTH IEEE80211_MAX_LEN -#define MODULATION_CCK IEEE80211_RATE_CCK -#define MODULATION_OFDM IEEE80211_RATE_OFDM -#define MODULATION_TURBO IEEE80211_RATE_TURBO -#define MODULATION_XR 0x00000200 /*XR thingie*/ -#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ - -#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code - enables short preamble, see ar5212_reg.h */ -#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) -#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 - -/****************\ - TX DEFINITIONS -\****************/ - -/* - * Tx Descriptor - */ -struct ath_tx_status { - u16 ts_seqnum; - u16 ts_tstamp; - u8 ts_status; - u8 ts_rate; - s8 ts_rssi; - u8 ts_shortretry; - u8 ts_longretry; - u8 ts_virtcol; - u8 ts_antenna; -}; - -#define AR5K_TXSTAT_ALTRATE 0x80 -#define AR5K_TXERR_XRETRY 0x01 -#define AR5K_TXERR_FILT 0x02 -#define AR5K_TXERR_FIFO 0x04 - -/* - * Queue types used to classify tx queues. - */ -enum ath5k_tx_queue { - AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ - AR5K_TX_QUEUE_DATA, /*A normal data queue*/ - AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ - AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ - AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ - AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ -}; - -#define AR5K_NUM_TX_QUEUES 10 -#define AR5K_NUM_TX_QUEUES_NOQCU 2 - -/* - * Queue syb-types to classify normal data queues. - * These are the 4 Access Categories as defined in - * WME spec. 0 is the lowest priority and 4 is the - * highest. Normal data that hasn't been classified - * goes to the Best Effort AC. - */ -enum ath5k_tx_queue_subtype { - AR5K_WME_AC_BK = 0, /*Background traffic*/ - AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ - AR5K_WME_AC_VI, /*Video traffic*/ - AR5K_WME_AC_VO, /*Voice traffic*/ -}; - -/* - * Queue ID numbers as returned by the HAL, each number - * represents a hw queue. If hw does not support hw queues - * (eg 5210) all data goes in one queue. These match - * d80211 definitions (net80211/MadWiFi don't use them). - */ -enum ath5k_tx_queue_id { - AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, - AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, - AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ - AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ - AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ - AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ - AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ - AR5K_TX_QUEUE_ID_UAPSD = 8, - AR5K_TX_QUEUE_ID_XR_DATA = 9, -}; - - -/* - * Flags to set hw queue's parameters... - */ -#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ -#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ -#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ -#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ -#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ -#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ -#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ -#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ - -/* - * A struct to hold tx queue's parameters - */ -struct ath5k_txq_info { - enum ath5k_tx_queue tqi_type; - enum ath5k_tx_queue_subtype tqi_subtype; - u16 tqi_flags; /* Tx queue flags (see above) */ - u32 tqi_aifs; /* Arbitrated Interframe Space */ - s32 tqi_cw_min; /* Minimum Contention Window */ - s32 tqi_cw_max; /* Maximum Contention Window */ - u32 tqi_cbr_period; /* Constant bit rate period */ - u32 tqi_cbr_overflow_limit; - u32 tqi_burst_time; - u32 tqi_ready_time; /* Not used */ - u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ -}; - -/* - * Transmit packet types. - * These are not fully used inside OpenHAL yet - */ -enum ath5k_pkt_type { - AR5K_PKT_TYPE_NORMAL = 0, - AR5K_PKT_TYPE_ATIM = 1, - AR5K_PKT_TYPE_PSPOLL = 2, - AR5K_PKT_TYPE_BEACON = 3, - AR5K_PKT_TYPE_PROBE_RESP = 4, - AR5K_PKT_TYPE_PIFS = 5, -}; - -/* - * TX power and TPC settings - */ -#define AR5K_TXPOWER_OFDM(_r, _v) ( \ - ((0 & 1) << ((_v) + 6)) | \ - (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ -) - -#define AR5K_TXPOWER_CCK(_r, _v) ( \ - (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ -) - -/* - * Used to compute TX times - */ -#define AR5K_CCK_SIFS_TIME 10 -#define AR5K_CCK_PREAMBLE_BITS 144 -#define AR5K_CCK_PLCP_BITS 48 - -#define AR5K_OFDM_SIFS_TIME 16 -#define AR5K_OFDM_PREAMBLE_TIME 20 -#define AR5K_OFDM_PLCP_BITS 22 -#define AR5K_OFDM_SYMBOL_TIME 4 - -#define AR5K_TURBO_SIFS_TIME 8 -#define AR5K_TURBO_PREAMBLE_TIME 14 -#define AR5K_TURBO_PLCP_BITS 22 -#define AR5K_TURBO_SYMBOL_TIME 4 - -#define AR5K_XR_SIFS_TIME 16 -#define AR5K_XR_PLCP_BITS 22 -#define AR5K_XR_SYMBOL_TIME 4 - -/* CCK */ -#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) - -#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ - ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ - (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) - -#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ - AR5K_CCK_PHY_TIME(_sp) + \ - ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ - AR5K_CCK_SIFS_TIME - -/* OFDM */ -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_OFDM_SYMBOL_TIME) / 1000) - -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ - AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ - (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) - -/* TURBO */ -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ - AR5K_TURBO_SYMBOL_TIME) / 1000) - -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ - AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ - AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ - (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) - -/* eXtendent Range (?)*/ -#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) - -#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_XR_SYMBOL_TIME) / 1000) - -#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ - AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ - (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) - -/* - * DMA size definitions (2^n+2) - */ -enum ath5k_dmasize { - AR5K_DMASIZE_4B = 0, - AR5K_DMASIZE_8B, - AR5K_DMASIZE_16B, - AR5K_DMASIZE_32B, - AR5K_DMASIZE_64B, - AR5K_DMASIZE_128B, - AR5K_DMASIZE_256B, - AR5K_DMASIZE_512B -}; - - -/****************\ - RX DEFINITIONS -\****************/ - -/* - * Rx Descriptor - */ -struct ath_rx_status { - u16 rs_datalen; - u16 rs_tstamp; - u8 rs_status; - u8 rs_phyerr; - s8 rs_rssi; - u8 rs_keyix; - u8 rs_rate; - u8 rs_antenna; - u8 rs_more; -}; - -#define AR5K_RXERR_CRC 0x01 -#define AR5K_RXERR_PHY 0x02 -#define AR5K_RXERR_FIFO 0x04 -#define AR5K_RXERR_DECRYPT 0x08 -#define AR5K_RXERR_MIC 0x10 -#define AR5K_RXKEYIX_INVALID ((u8) - 1) -#define AR5K_TXKEYIX_INVALID ((u32) - 1) - -struct ath5k_mib_stats { - u32 ackrcv_bad; - u32 rts_bad; - u32 rts_good; - u32 fcs_bad; - u32 beacons; -}; - - - - -/**************************\ - BEACON TIMERS DEFINITIONS -\**************************/ - -#define AR5K_BEACON_PERIOD 0x0000ffff -#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ -#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ - -/* - * Per-station beacon timer state. - */ -struct ath5k_beacon_state { - u32 bs_next_beacon; - u32 bs_next_dtim; - u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- - can also include the above flags*/ - u8 bs_dtim_period; - u8 bs_cfp_period; - u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with - a Point Coordination Function capable AP*/ - u16 bs_cfp_du_remain; - u16 bs_tim_offset; - u16 bs_sleep_duration; - u16 bs_bmiss_threshold; - u32 bs_cfp_next; -}; - - - - -/********************\ - COMMON DEFINITIONS -\********************/ - -/* - * Atheros descriptor - */ -struct ath_desc { - u32 ds_link; - u32 ds_data; - u32 ds_ctl0; - u32 ds_ctl1; - u32 ds_hw[4]; - - union { - struct ath_rx_status rx; - struct ath_tx_status tx; - } ds_us; - -#define ds_rxstat ds_us.rx -#define ds_txstat ds_us.tx - -} __packed; - -#define AR5K_RXDESC_INTREQ 0x0020 - -#define AR5K_TXDESC_CLRDMASK 0x0001 -#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ -#define AR5K_TXDESC_RTSENA 0x0004 -#define AR5K_TXDESC_CTSENA 0x0008 -#define AR5K_TXDESC_INTREQ 0x0010 -#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ - -#define AR5K_SLOT_TIME_9 396 -#define AR5K_SLOT_TIME_20 880 -#define AR5K_SLOT_TIME_MAX 0xffff - -/* channel_flags */ -#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ -#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ -#define CHANNEL_CCK 0x0020 /* CCK channel */ -#define CHANNEL_OFDM 0x0040 /* OFDM channel */ -#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ -#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ -#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ -#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ -#define CHANNEL_XR 0x0800 /* XR channel */ - -#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) -#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) -#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) -#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_108A CHANNEL_T -#define CHANNEL_108G CHANNEL_TG -#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) - -#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ - CHANNEL_5GHZ | CHANNEL_TURBO) - -#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) -#define CHANNEL_MODES CHANNEL_ALL - -/* - * Used internaly in OpenHAL (ar5211.c/ar5212.c - * for reset_tx_queue). Also see struct struct ieee80211_channel. - */ -#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) -#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) - -/* - * The following structure will be used to map 2GHz channels to - * 5GHz Atheros channels. - */ -struct ath5k_athchan_2ghz { - u32 a2_flags; - u16 a2_athchan; -}; - -/* - * Rate definitions - */ - -#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ - -struct ath5k_rate { - u8 valid; /* Valid for rate control */ - u32 modulation; - u16 rate_kbps; - u8 rate_code; /* Rate mapping for h/w descriptors */ - u8 dot11_rate; - u8 control_rate; - u16 lp_ack_duration;/* long preamble ACK duration */ - u16 sp_ack_duration;/* short preamble ACK duration*/ -}; - -struct ath5k_rate_table { - u16 rate_count; - u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ - struct ath5k_rate rates[AR5K_MAX_RATES]; -}; - -/* - * Rate tables... - */ -#define AR5K_RATES_11A { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_11B { 4, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ -} - -#define AR5K_RATES_11G { 12, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ - { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ - { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -#define AR5K_RATES_TURBO { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ - { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ - { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ - { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ - { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ - { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ - { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ - { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_XR { 12, { \ - 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_XR, 500, 7, 129, 0 }, \ - { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ - { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ - { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ - { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -/* - * Crypto definitions - */ - -#define AR5K_KEYCACHE_SIZE 8 - -/***********************\ - HW RELATED DEFINITIONS -\***********************/ - -/* - * Misc definitions - */ -#define AR5K_RSSI_EP_MULTIPLIER (1<<7) - -#define AR5K_ASSERT_ENTRY(_e, _s) do { \ - if (_e >= _s) \ - return (false); \ -} while (0) - - -struct ath5k_node_stats { - u32 ns_avgbrssi; /* average beacon rssi */ - u32 ns_avgrssi; /* average data rssi */ - u32 ns_avgtxrssi; /* average tx rssi */ -}; - -enum ath5k_ant_setting { - AR5K_ANT_VARIABLE = 0, /* variable by programming */ - AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ - AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ - AR5K_ANT_MAX = 3, -}; - -/* - * HAL interrupt abstraction - */ - -/* - * These are mapped to take advantage of some common bits - * between the MAC chips, to be able to set intr properties - * easier. Some of them are not used yet inside OpenHAL. - */ -enum ath5k_int { - AR5K_INT_RX = 0x00000001, - AR5K_INT_RXDESC = 0x00000002, - AR5K_INT_RXNOFRM = 0x00000008, - AR5K_INT_RXEOL = 0x00000010, - AR5K_INT_RXORN = 0x00000020, - AR5K_INT_TX = 0x00000040, - AR5K_INT_TXDESC = 0x00000080, - AR5K_INT_TXURN = 0x00000800, - AR5K_INT_MIB = 0x00001000, - AR5K_INT_RXPHY = 0x00004000, - AR5K_INT_RXKCM = 0x00008000, - AR5K_INT_SWBA = 0x00010000, - AR5K_INT_BMISS = 0x00040000, - AR5K_INT_BNR = 0x00100000, - AR5K_INT_GPIO = 0x01000000, - AR5K_INT_FATAL = 0x40000000, - AR5K_INT_GLOBAL = 0x80000000, - - /*A sum of all the common bits*/ - AR5K_INT_COMMON = AR5K_INT_RXNOFRM - | AR5K_INT_RXDESC - | AR5K_INT_RXEOL - | AR5K_INT_RXORN - | AR5K_INT_TXURN - | AR5K_INT_TXDESC - | AR5K_INT_MIB - | AR5K_INT_RXPHY - | AR5K_INT_RXKCM - | AR5K_INT_SWBA - | AR5K_INT_BMISS - | AR5K_INT_GPIO, - AR5K_INT_NOCARD = 0xffffffff /*Declare that the card - has been removed*/ -}; - -/* - * Power management - */ -enum ath5k_power_mode { - AR5K_PM_UNDEFINED = 0, - AR5K_PM_AUTO, - AR5K_PM_AWAKE, - AR5K_PM_FULL_SLEEP, - AR5K_PM_NETWORK_SLEEP, -}; - -/* - * These match net80211 definitions (not used in - * d80211). - */ -#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ -#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ -#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ -#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ -#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ - -/* GPIO-controlled software LED */ -#define AR5K_SOFTLED_PIN 0 -#define AR5K_SOFTLED_ON 0 -#define AR5K_SOFTLED_OFF 1 - -/* - * Chipset capabilities -see ath_hal_getcapability- - * get_capability function is not yet fully implemented - * in OpenHAL so most of these don't work yet... - */ -enum ath5k_capability_type { - AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ - AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ - AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ - AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ - AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ - AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ - AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ - AR5K_CAP_COMPRESSION = 8, /* Supports compression */ - AR5K_CAP_BURST = 9, /* Supports packet bursting */ - AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ - AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ - AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ - AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ - AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ - AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ - AR5K_CAP_XR = 16, /* Supports XR mode */ - AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ - AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ - AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ - AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ -}; - -struct ath5k_capabilities { - /* - * Supported PHY modes - * (ie. CHANNEL_A, CHANNEL_B, ...) - */ - DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); - - /* - * Frequency range (without regulation restrictions) - */ - struct { - u16 range_2ghz_min; - u16 range_2ghz_max; - u16 range_5ghz_min; - u16 range_5ghz_max; - } cap_range; - - /* - * Active regulation domain settings - */ - struct { - enum ieee80211_regdomain reg_current; - enum ieee80211_regdomain reg_hw; - } cap_regdomain; - - /* - * Values stored in the EEPROM (some of them...) - */ - struct ath5k_eeprom_info cap_eeprom; - - /* - * Queue information - */ - struct { - u8 q_tx_num; - } cap_queues; -}; - - -/***************************************\ - HARDWARE ABSTRACTION LAYER STRUCTURE -\***************************************/ - -/* - * Misc defines - */ - -#define AR5K_MAX_GPIO 10 -#define AR5K_MAX_RF_BANKS 8 - -struct ath_hw { - u32 ah_magic; - - void *ah_sc; - void __iomem *ah_sh; - enum ieee80211_countrycode ah_country_code; - - enum ath5k_int ah_imr; - - enum ieee80211_if_types ah_op_mode; - enum ath5k_power_mode ah_power_mode; - struct ieee80211_channel ah_current_channel; - bool ah_turbo; - bool ah_calibration; - bool ah_running; - bool ah_single_chip; - enum ath5k_rfgain ah_rf_gain; - - u32 ah_mac_srev; - u16 ah_mac_version; - u16 ah_mac_revision; - u16 ah_phy_revision; - u16 ah_radio_5ghz_revision; - u16 ah_radio_2ghz_revision; - - enum ath5k_version ah_version; - enum ath5k_radio ah_radio; - u32 ah_phy; - - bool ah_5ghz; - bool ah_2ghz; - -#define ah_regdomain ah_capabilities.cap_regdomain.reg_current -#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw -#define ah_modes ah_capabilities.cap_mode -#define ah_ee_version ah_capabilities.cap_eeprom.ee_version - - u32 ah_atim_window; - u32 ah_aifs; - u32 ah_cw_min; - u32 ah_cw_max; - bool ah_software_retry; - u32 ah_limit_tx_retries; - - u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; - bool ah_ant_diversity; - - u8 ah_sta_id[ETH_ALEN]; - u8 ah_bssid[ETH_ALEN]; - - u32 ah_gpio[AR5K_MAX_GPIO]; - int ah_gpio_npins; - - struct ath5k_capabilities ah_capabilities; - - struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; - u32 ah_txq_interrupts; - - u32 *ah_rf_banks; - size_t ah_rf_banks_size; - struct ath5k_gain ah_gain; - u32 ah_offset[AR5K_MAX_RF_BANKS]; - - struct { - u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; - u16 txp_rates[AR5K_MAX_RATES]; - s16 txp_min, txp_max; - bool txp_tpc; - s16 txp_ofdm; - } ah_txpower; - - struct { - bool r_enabled; - int r_last_alert; - struct ieee80211_channel r_last_channel; - } ah_radar; - - /* - * Function pointers - */ - int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int); - bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int); - int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool); - int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); - int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *); -}; - -/* - * Prototypes - */ -/* Attach/Detach Functions */ -struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); -const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); -void ath5k_hw_detach(struct ath_hw *hal); -/* Reset Functions */ -int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); -/* Power management functions */ -int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); -enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); -/* DMA Related Functions */ -void ath5k_hw_start_rx(struct ath_hw *hal); -int ath5k_hw_stop_rx_dma(struct ath_hw *hal); -u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); -void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); -int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); -u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); -int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); -bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); -/* Interrupt handling */ -bool ath5k_hw_is_intr_pending(struct ath_hw *hal); -int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); -enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); -void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); -/* EEPROM access functions */ -int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); -/* Protocol Control Unit Functions */ -void ath5k_hw_set_opmode(struct ath_hw *hal); -/* BSSID Functions */ -void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); -bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); -void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); -bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); -/* Receive start/stop functions */ -void ath5k_hw_start_rx_pcu(struct ath_hw *hal); -void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); -/* RX Filter functions */ -void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); -bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); -bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); -u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); -void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); -/* Beacon related functions */ -u32 ath5k_hw_get_tsf32(struct ath_hw *hal); -u64 ath5k_hw_get_tsf64(struct ath_hw *hal); -void ath5k_hw_reset_tsf(struct ath_hw *hal); -void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); -void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); -void ath5k_hw_reset_beacon(struct ath_hw *hal); -bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); -void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); -/* ACK/CTS Timeouts */ -bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); -unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); -bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); -unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); -/* Key table (WEP) functions */ -int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); -int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); -int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); -int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); -/* Queue Control Unit, DFS Control Unit Functions */ -int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); -int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); -int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); -void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); -int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); -u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); -unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); -/* Hardware Descriptor Functions */ -/* RX Descriptor */ -int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); -/* GPIO Functions */ -void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); -int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); -int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); -u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); -int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); -void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); -/* Regulatory Domain/Channels Setup */ -bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags); -u16 ath5k_get_regdomain(struct ath_hw *hal); -/* PHY/RF access functions */ -int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_phy_disable(struct ath_hw *hal); -void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); -unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); -bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); -enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); -/* Misc functions */ -int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); -void ath5k_hw_dump_state(struct ath_hw *hal); -int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); -bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); -bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); -bool ath5k_hw_disable_pspoll(struct ath_hw *hal); -#endif /* _AR5K_H */ diff --git a/ath5k_hw.c b/ath5k_hw.c index 501d85c..eb02bdd 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -22,7 +22,7 @@ #include -#include "ath5k.h" +#include "ath5k_hw.h" #include "ath5k_reg.h" /*Rate tables*/ diff --git a/ath5k_hw.h b/ath5k_hw.h index cd4fbad..69986e1 100644 --- a/ath5k_hw.h +++ b/ath5k_hw.h @@ -17,6 +17,48 @@ * $Id$ */ +#include + +#include "ath5k_regdom.h" + +/* Uncomment this for debuging (warning that it results in TOO much output) */ +/*#define AR5K_DEBUG 1 */ + +/* PCI IDs */ +#ifndef PCI_VENDOR_ID_ATHEROS +#define PCI_VENDOR_ID_ATHEROS 0x168c +#endif +#ifndef PCI_VENDOR_ID_3COM_2 +#define PCI_VENDOR_ID_3COM_2 0xa727 +#endif + +#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ +#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ +#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ +#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ +#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ +#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ +#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ +#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ + /* * Gain settings */ @@ -2151,3 +2193,986 @@ struct ath5k_ar5211_ini_rf { { 0x0000989c, { 0x0000125a, 0x0000129a } }, \ { 0x000098cc, { 0x0000000e, 0x0000000f } }, \ } + +/****************************\ + GENERIC DRIVER DEFINITIONS +\****************************/ + +#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) +#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) +#ifdef AR5K_DEBUG +#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) +#else +#define AR5K_TRACE +#endif +#define howmany(x, y) (((x)+((y)-1))/(y)) + +/* + * Some tuneable values (these should be changeable by the user) + */ +#define AR5K_TUNE_DMA_BEACON_RESP 2 +#define AR5K_TUNE_SW_BEACON_RESP 10 +#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 +#define AR5K_TUNE_RADAR_ALERT false +#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 +#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) +#define AR5K_TUNE_RSSI_THRES 1792 +#define AR5K_TUNE_REGISTER_TIMEOUT 20000 +#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 +#define AR5K_TUNE_BEACON_INTERVAL 100 +#define AR5K_TUNE_AIFS 2 +#define AR5K_TUNE_AIFS_11B 2 +#define AR5K_TUNE_AIFS_XR 0 +#define AR5K_TUNE_CWMIN 15 +#define AR5K_TUNE_CWMIN_11B 31 +#define AR5K_TUNE_CWMIN_XR 3 +#define AR5K_TUNE_CWMAX 1023 +#define AR5K_TUNE_CWMAX_11B 1023 +#define AR5K_TUNE_CWMAX_XR 7 +#define AR5K_TUNE_NOISE_FLOOR -72 +#define AR5K_TUNE_MAX_TXPOWER 60 +#define AR5K_TUNE_DEFAULT_TXPOWER 30 +#define AR5K_TUNE_TPC_TXPOWER true +#define AR5K_TUNE_ANT_DIVERSITY true +#define AR5K_TUNE_HWTXTRIES 4 + +/* token to use for aifs, cwmin, cwmax in MadWiFi */ +#define AR5K_TXQ_USEDEFAULT ((u32) -1) + +/* GENERIC CHIPSET DEFINITIONS */ + +/* MAC Chips */ +enum ath5k_version { + AR5K_AR5210 = 0, + AR5K_AR5211 = 1, + AR5K_AR5212 = 2, +}; + +/* PHY Chips */ +enum ath5k_radio { + AR5K_RF5110 = 0, + AR5K_RF5111 = 1, + AR5K_RF5112 = 2, +}; + +/* + * Common silicon revision/version values + */ +enum ath5k_srev_type { + AR5K_VERSION_VER, + AR5K_VERSION_REV, + AR5K_VERSION_RAD, + AR5K_VERSION_DEV +}; + +struct ath5k_srev_name { + const char *sr_name; + enum ath5k_srev_type sr_type; + u_int sr_val; +}; + +#define AR5K_SREV_NAME { \ + { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ + { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ + { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ + { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ + { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ + { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ + { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ + { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ + { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ + { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ + { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ + { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ + { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ + { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ + { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ + { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ + { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ + { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ + { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ + { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ +} + +#define AR5K_SREV_UNKNOWN 0xffff + +#define AR5K_SREV_VER_AR5210 0x00 +#define AR5K_SREV_VER_AR5311 0x10 +#define AR5K_SREV_VER_AR5311A 0x20 +#define AR5K_SREV_VER_AR5311B 0x30 +#define AR5K_SREV_VER_AR5211 0x40 +#define AR5K_SREV_VER_AR5212 0x50 +#define AR5K_SREV_VER_AR5213 0x55 +#define AR5K_SREV_VER_UNSUPP 0x60 + +#define AR5K_SREV_RAD_5110 0x00 +#define AR5K_SREV_RAD_5111 0x10 +#define AR5K_SREV_RAD_5111A 0x15 +#define AR5K_SREV_RAD_2111 0x20 +#define AR5K_SREV_RAD_5112 0x30 +#define AR5K_SREV_RAD_5112A 0x35 +#define AR5K_SREV_RAD_2112 0x40 +#define AR5K_SREV_RAD_2112A 0x45 +#define AR5K_SREV_RAD_UNSUPP 0x50 + + +/* IEEE defs */ + +#define IEEE80211_MAX_LEN 2500 + +#define MAX_PDU_LENGTH IEEE80211_MAX_LEN +#define MODULATION_CCK IEEE80211_RATE_CCK +#define MODULATION_OFDM IEEE80211_RATE_OFDM +#define MODULATION_TURBO IEEE80211_RATE_TURBO +#define MODULATION_XR 0x00000200 /*XR thingie*/ +#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ + +#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code + enables short preamble, see ar5212_reg.h */ +#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) +#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 + +/****************\ + TX DEFINITIONS +\****************/ + +/* + * Tx Descriptor + */ +struct ath_tx_status { + u16 ts_seqnum; + u16 ts_tstamp; + u8 ts_status; + u8 ts_rate; + s8 ts_rssi; + u8 ts_shortretry; + u8 ts_longretry; + u8 ts_virtcol; + u8 ts_antenna; +}; + +#define AR5K_TXSTAT_ALTRATE 0x80 +#define AR5K_TXERR_XRETRY 0x01 +#define AR5K_TXERR_FILT 0x02 +#define AR5K_TXERR_FIFO 0x04 + +/* + * Queue types used to classify tx queues. + */ +enum ath5k_tx_queue { + AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ + AR5K_TX_QUEUE_DATA, /*A normal data queue*/ + AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ + AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ + AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ + AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ +}; + +#define AR5K_NUM_TX_QUEUES 10 +#define AR5K_NUM_TX_QUEUES_NOQCU 2 + +/* + * Queue syb-types to classify normal data queues. + * These are the 4 Access Categories as defined in + * WME spec. 0 is the lowest priority and 4 is the + * highest. Normal data that hasn't been classified + * goes to the Best Effort AC. + */ +enum ath5k_tx_queue_subtype { + AR5K_WME_AC_BK = 0, /*Background traffic*/ + AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ + AR5K_WME_AC_VI, /*Video traffic*/ + AR5K_WME_AC_VO, /*Voice traffic*/ +}; + +/* + * Queue ID numbers as returned by the HAL, each number + * represents a hw queue. If hw does not support hw queues + * (eg 5210) all data goes in one queue. These match + * d80211 definitions (net80211/MadWiFi don't use them). + */ +enum ath5k_tx_queue_id { + AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, + AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, + AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ + AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ + AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ + AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ + AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ + AR5K_TX_QUEUE_ID_UAPSD = 8, + AR5K_TX_QUEUE_ID_XR_DATA = 9, +}; + + +/* + * Flags to set hw queue's parameters... + */ +#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ +#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ +#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ +#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ +#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ +#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ +#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ +#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ + +/* + * A struct to hold tx queue's parameters + */ +struct ath5k_txq_info { + enum ath5k_tx_queue tqi_type; + enum ath5k_tx_queue_subtype tqi_subtype; + u16 tqi_flags; /* Tx queue flags (see above) */ + u32 tqi_aifs; /* Arbitrated Interframe Space */ + s32 tqi_cw_min; /* Minimum Contention Window */ + s32 tqi_cw_max; /* Maximum Contention Window */ + u32 tqi_cbr_period; /* Constant bit rate period */ + u32 tqi_cbr_overflow_limit; + u32 tqi_burst_time; + u32 tqi_ready_time; /* Not used */ + u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ +}; + +/* + * Transmit packet types. + * These are not fully used inside OpenHAL yet + */ +enum ath5k_pkt_type { + AR5K_PKT_TYPE_NORMAL = 0, + AR5K_PKT_TYPE_ATIM = 1, + AR5K_PKT_TYPE_PSPOLL = 2, + AR5K_PKT_TYPE_BEACON = 3, + AR5K_PKT_TYPE_PROBE_RESP = 4, + AR5K_PKT_TYPE_PIFS = 5, +}; + +/* + * TX power and TPC settings + */ +#define AR5K_TXPOWER_OFDM(_r, _v) ( \ + ((0 & 1) << ((_v) + 6)) | \ + (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ +) + +#define AR5K_TXPOWER_CCK(_r, _v) ( \ + (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ +) + +/* + * Used to compute TX times + */ +#define AR5K_CCK_SIFS_TIME 10 +#define AR5K_CCK_PREAMBLE_BITS 144 +#define AR5K_CCK_PLCP_BITS 48 + +#define AR5K_OFDM_SIFS_TIME 16 +#define AR5K_OFDM_PREAMBLE_TIME 20 +#define AR5K_OFDM_PLCP_BITS 22 +#define AR5K_OFDM_SYMBOL_TIME 4 + +#define AR5K_TURBO_SIFS_TIME 8 +#define AR5K_TURBO_PREAMBLE_TIME 14 +#define AR5K_TURBO_PLCP_BITS 22 +#define AR5K_TURBO_SYMBOL_TIME 4 + +#define AR5K_XR_SIFS_TIME 16 +#define AR5K_XR_PLCP_BITS 22 +#define AR5K_XR_SYMBOL_TIME 4 + +/* CCK */ +#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) + +#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ + ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ + (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) + +#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ + AR5K_CCK_PHY_TIME(_sp) + \ + ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ + AR5K_CCK_SIFS_TIME + +/* OFDM */ +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_OFDM_SYMBOL_TIME) / 1000) + +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ + AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ + (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) + +/* TURBO */ +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ + AR5K_TURBO_SYMBOL_TIME) / 1000) + +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ + AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ + AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ + (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) + +/* eXtendent Range (?)*/ +#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) + +#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_XR_SYMBOL_TIME) / 1000) + +#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ + AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ + (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) + +/* + * DMA size definitions (2^n+2) + */ +enum ath5k_dmasize { + AR5K_DMASIZE_4B = 0, + AR5K_DMASIZE_8B, + AR5K_DMASIZE_16B, + AR5K_DMASIZE_32B, + AR5K_DMASIZE_64B, + AR5K_DMASIZE_128B, + AR5K_DMASIZE_256B, + AR5K_DMASIZE_512B +}; + + +/****************\ + RX DEFINITIONS +\****************/ + +/* + * Rx Descriptor + */ +struct ath_rx_status { + u16 rs_datalen; + u16 rs_tstamp; + u8 rs_status; + u8 rs_phyerr; + s8 rs_rssi; + u8 rs_keyix; + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; +}; + +#define AR5K_RXERR_CRC 0x01 +#define AR5K_RXERR_PHY 0x02 +#define AR5K_RXERR_FIFO 0x04 +#define AR5K_RXERR_DECRYPT 0x08 +#define AR5K_RXERR_MIC 0x10 +#define AR5K_RXKEYIX_INVALID ((u8) - 1) +#define AR5K_TXKEYIX_INVALID ((u32) - 1) + +struct ath5k_mib_stats { + u32 ackrcv_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 beacons; +}; + + + + +/**************************\ + BEACON TIMERS DEFINITIONS +\**************************/ + +#define AR5K_BEACON_PERIOD 0x0000ffff +#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ +#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ + +/* + * Per-station beacon timer state. + */ +struct ath5k_beacon_state { + u32 bs_next_beacon; + u32 bs_next_dtim; + u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- + can also include the above flags*/ + u8 bs_dtim_period; + u8 bs_cfp_period; + u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with + a Point Coordination Function capable AP*/ + u16 bs_cfp_du_remain; + u16 bs_tim_offset; + u16 bs_sleep_duration; + u16 bs_bmiss_threshold; + u32 bs_cfp_next; +}; + + + + +/********************\ + COMMON DEFINITIONS +\********************/ + +/* + * Atheros descriptor + */ +struct ath_desc { + u32 ds_link; + u32 ds_data; + u32 ds_ctl0; + u32 ds_ctl1; + u32 ds_hw[4]; + + union { + struct ath_rx_status rx; + struct ath_tx_status tx; + } ds_us; + +#define ds_rxstat ds_us.rx +#define ds_txstat ds_us.tx + +} __packed; + +#define AR5K_RXDESC_INTREQ 0x0020 + +#define AR5K_TXDESC_CLRDMASK 0x0001 +#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ +#define AR5K_TXDESC_RTSENA 0x0004 +#define AR5K_TXDESC_CTSENA 0x0008 +#define AR5K_TXDESC_INTREQ 0x0010 +#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ + +#define AR5K_SLOT_TIME_9 396 +#define AR5K_SLOT_TIME_20 880 +#define AR5K_SLOT_TIME_MAX 0xffff + +/* channel_flags */ +#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ +#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ +#define CHANNEL_XR 0x0800 /* XR channel */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_108G CHANNEL_TG +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) + +#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ + CHANNEL_5GHZ | CHANNEL_TURBO) + +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) +#define CHANNEL_MODES CHANNEL_ALL + +/* + * Used internaly in OpenHAL (ar5211.c/ar5212.c + * for reset_tx_queue). Also see struct struct ieee80211_channel. + */ +#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) +#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) + +/* + * The following structure will be used to map 2GHz channels to + * 5GHz Atheros channels. + */ +struct ath5k_athchan_2ghz { + u32 a2_flags; + u16 a2_athchan; +}; + +/* + * Rate definitions + */ + +#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ + +struct ath5k_rate { + u8 valid; /* Valid for rate control */ + u32 modulation; + u16 rate_kbps; + u8 rate_code; /* Rate mapping for h/w descriptors */ + u8 dot11_rate; + u8 control_rate; + u16 lp_ack_duration;/* long preamble ACK duration */ + u16 sp_ack_duration;/* short preamble ACK duration*/ +}; + +struct ath5k_rate_table { + u16 rate_count; + u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ + struct ath5k_rate rates[AR5K_MAX_RATES]; +}; + +/* + * Rate tables... + */ +#define AR5K_RATES_11A { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_11B { 4, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ +} + +#define AR5K_RATES_11G { 12, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ + { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ + { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +#define AR5K_RATES_TURBO { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ + { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ + { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ + { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ + { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ + { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ + { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ + { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_XR { 12, { \ + 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_XR, 500, 7, 129, 0 }, \ + { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ + { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ + { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ + { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +/* + * Crypto definitions + */ + +#define AR5K_KEYCACHE_SIZE 8 + + +/***********************\ + HW RELATED DEFINITIONS +\***********************/ + +/* + * Misc definitions + */ +#define AR5K_RSSI_EP_MULTIPLIER (1<<7) + +#define AR5K_ASSERT_ENTRY(_e, _s) do { \ + if (_e >= _s) \ + return (false); \ +} while (0) + + +struct ath5k_node_stats { + u32 ns_avgbrssi; /* average beacon rssi */ + u32 ns_avgrssi; /* average data rssi */ + u32 ns_avgtxrssi; /* average tx rssi */ +}; + +enum ath5k_ant_setting { + AR5K_ANT_VARIABLE = 0, /* variable by programming */ + AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ + AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ + AR5K_ANT_MAX = 3, +}; + +/* + * HAL interrupt abstraction + */ + +/* + * These are mapped to take advantage of some common bits + * between the MAC chips, to be able to set intr properties + * easier. Some of them are not used yet inside OpenHAL. + */ +enum ath5k_int { + AR5K_INT_RX = 0x00000001, + AR5K_INT_RXDESC = 0x00000002, + AR5K_INT_RXNOFRM = 0x00000008, + AR5K_INT_RXEOL = 0x00000010, + AR5K_INT_RXORN = 0x00000020, + AR5K_INT_TX = 0x00000040, + AR5K_INT_TXDESC = 0x00000080, + AR5K_INT_TXURN = 0x00000800, + AR5K_INT_MIB = 0x00001000, + AR5K_INT_RXPHY = 0x00004000, + AR5K_INT_RXKCM = 0x00008000, + AR5K_INT_SWBA = 0x00010000, + AR5K_INT_BMISS = 0x00040000, + AR5K_INT_BNR = 0x00100000, + AR5K_INT_GPIO = 0x01000000, + AR5K_INT_FATAL = 0x40000000, + AR5K_INT_GLOBAL = 0x80000000, + + /*A sum of all the common bits*/ + AR5K_INT_COMMON = AR5K_INT_RXNOFRM + | AR5K_INT_RXDESC + | AR5K_INT_RXEOL + | AR5K_INT_RXORN + | AR5K_INT_TXURN + | AR5K_INT_TXDESC + | AR5K_INT_MIB + | AR5K_INT_RXPHY + | AR5K_INT_RXKCM + | AR5K_INT_SWBA + | AR5K_INT_BMISS + | AR5K_INT_GPIO, + AR5K_INT_NOCARD = 0xffffffff /*Declare that the card + has been removed*/ +}; + +/* + * Power management + */ +enum ath5k_power_mode { + AR5K_PM_UNDEFINED = 0, + AR5K_PM_AUTO, + AR5K_PM_AWAKE, + AR5K_PM_FULL_SLEEP, + AR5K_PM_NETWORK_SLEEP, +}; + +/* + * These match net80211 definitions (not used in + * d80211). + */ +#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ +#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ +#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ +#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ +#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ + +/* GPIO-controlled software LED */ +#define AR5K_SOFTLED_PIN 0 +#define AR5K_SOFTLED_ON 0 +#define AR5K_SOFTLED_OFF 1 + +/* + * Chipset capabilities -see ath_hal_getcapability- + * get_capability function is not yet fully implemented + * in OpenHAL so most of these don't work yet... + */ +enum ath5k_capability_type { + AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ + AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ + AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ + AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ + AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ + AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ + AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ + AR5K_CAP_COMPRESSION = 8, /* Supports compression */ + AR5K_CAP_BURST = 9, /* Supports packet bursting */ + AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ + AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ + AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ + AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ + AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ + AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ + AR5K_CAP_XR = 16, /* Supports XR mode */ + AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ + AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ + AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ + AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ +}; + +struct ath5k_capabilities { + /* + * Supported PHY modes + * (ie. CHANNEL_A, CHANNEL_B, ...) + */ + DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); + + /* + * Frequency range (without regulation restrictions) + */ + struct { + u16 range_2ghz_min; + u16 range_2ghz_max; + u16 range_5ghz_min; + u16 range_5ghz_max; + } cap_range; + + /* + * Active regulation domain settings + */ + struct { + enum ieee80211_regdomain reg_current; + enum ieee80211_regdomain reg_hw; + } cap_regdomain; + + /* + * Values stored in the EEPROM (some of them...) + */ + struct ath5k_eeprom_info cap_eeprom; + + /* + * Queue information + */ + struct { + u8 q_tx_num; + } cap_queues; +}; + + +/***************************************\ + HARDWARE ABSTRACTION LAYER STRUCTURE +\***************************************/ + +/* + * Misc defines + */ + +#define AR5K_MAX_GPIO 10 +#define AR5K_MAX_RF_BANKS 8 + +struct ath_hw { + u32 ah_magic; + + void *ah_sc; + void __iomem *ah_sh; + enum ieee80211_countrycode ah_country_code; + + enum ath5k_int ah_imr; + + enum ieee80211_if_types ah_op_mode; + enum ath5k_power_mode ah_power_mode; + struct ieee80211_channel ah_current_channel; + bool ah_turbo; + bool ah_calibration; + bool ah_running; + bool ah_single_chip; + enum ath5k_rfgain ah_rf_gain; + + u32 ah_mac_srev; + u16 ah_mac_version; + u16 ah_mac_revision; + u16 ah_phy_revision; + u16 ah_radio_5ghz_revision; + u16 ah_radio_2ghz_revision; + + enum ath5k_version ah_version; + enum ath5k_radio ah_radio; + u32 ah_phy; + + bool ah_5ghz; + bool ah_2ghz; + +#define ah_regdomain ah_capabilities.cap_regdomain.reg_current +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_modes ah_capabilities.cap_mode +#define ah_ee_version ah_capabilities.cap_eeprom.ee_version + + u32 ah_atim_window; + u32 ah_aifs; + u32 ah_cw_min; + u32 ah_cw_max; + bool ah_software_retry; + u32 ah_limit_tx_retries; + + u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + bool ah_ant_diversity; + + u8 ah_sta_id[ETH_ALEN]; + u8 ah_bssid[ETH_ALEN]; + + u32 ah_gpio[AR5K_MAX_GPIO]; + int ah_gpio_npins; + + struct ath5k_capabilities ah_capabilities; + + struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; + u32 ah_txq_interrupts; + + u32 *ah_rf_banks; + size_t ah_rf_banks_size; + struct ath5k_gain ah_gain; + u32 ah_offset[AR5K_MAX_RF_BANKS]; + + struct { + u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; + u16 txp_rates[AR5K_MAX_RATES]; + s16 txp_min, txp_max; + bool txp_tpc; + s16 txp_ofdm; + } ah_txpower; + + struct { + bool r_enabled; + int r_last_alert; + struct ieee80211_channel r_last_channel; + } ah_radar; + + /* + * Function pointers + */ + int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int); + bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); + int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); + int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); + int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *); +}; + +/* + * Prototypes + */ +/* Attach/Detach Functions */ +struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); +void ath5k_hw_detach(struct ath_hw *hal); +/* Reset Functions */ +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); +/* Power management functions */ +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); +/* DMA Related Functions */ +void ath5k_hw_start_rx(struct ath_hw *hal); +int ath5k_hw_stop_rx_dma(struct ath_hw *hal); +u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); +void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); +int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); +int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); +bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); +/* Interrupt handling */ +bool ath5k_hw_is_intr_pending(struct ath_hw *hal); +int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); +enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); +void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); +/* EEPROM access functions */ +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); +/* Protocol Control Unit Functions */ +void ath5k_hw_set_opmode(struct ath_hw *hal); +/* BSSID Functions */ +void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); +bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); +void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); +bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); +/* Receive start/stop functions */ +void ath5k_hw_start_rx_pcu(struct ath_hw *hal); +void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); +/* RX Filter functions */ +void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); +bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); +u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); +void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); +/* Beacon related functions */ +u32 ath5k_hw_get_tsf32(struct ath_hw *hal); +u64 ath5k_hw_get_tsf64(struct ath_hw *hal); +void ath5k_hw_reset_tsf(struct ath_hw *hal); +void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); +void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); +void ath5k_hw_reset_beacon(struct ath_hw *hal); +bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); +void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); +/* ACK/CTS Timeouts */ +bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); +bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); +/* Key table (WEP) functions */ +int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); +int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); +int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); +int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); +/* Queue Control Unit, DFS Control Unit Functions */ +int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); +int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); +int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); +void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); +int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); +unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); +/* Hardware Descriptor Functions */ +/* RX Descriptor */ +int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); +/* GPIO Functions */ +void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); +int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); +int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); +u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); +int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); +void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); +/* Regulatory Domain/Channels Setup */ +bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags); +u16 ath5k_get_regdomain(struct ath_hw *hal); +/* PHY/RF access functions */ +int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_phy_disable(struct ath_hw *hal); +void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); +unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); +bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); +/* Misc functions */ +int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); +void ath5k_hw_dump_state(struct ath_hw *hal); +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); +bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); +bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); +bool ath5k_hw_disable_pspoll(struct ath_hw *hal); commit 38fe84ecf5d4f69eed707ac123c701239596285c Author: Jiri Slaby Date: Fri Aug 3 23:02:24 2007 +0200 ieee80211_regdomain -> ath5k_regdom diff --git a/ath.c b/ath.c index c455ca3..cc4c913 100644 --- a/ath.c +++ b/ath.c @@ -1768,12 +1768,12 @@ static unsigned int ath_copy_channels(struct ath_hw *ah, [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G }, [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG }, }; - static const struct ieee80211_regchannel chans_2ghz[] = + static const struct ath5k_regchannel chans_2ghz[] = IEEE80211_CHANNELS_2GHZ; - static const struct ieee80211_regchannel chans_5ghz[] = + static const struct ath5k_regchannel chans_5ghz[] = IEEE80211_CHANNELS_5GHZ; - const struct ieee80211_regchannel *chans; - enum ieee80211_regdomain dmn; + const struct ath5k_regchannel *chans; + enum ath5k_regdom dmn; unsigned int i, count, size, chfreq, all, f, ch; if (!test_bit(mode, ah->ah_modes)) @@ -1787,7 +1787,7 @@ static unsigned int ath_copy_channels(struct ath_hw *ah, /* 1..220, but 2GHz frequencies are filtered by check_channel */ size = all ? 220 : ARRAY_SIZE(chans_5ghz); chans = chans_5ghz; - dmn = ieee80211_regdomain2flag(ah->ah_regdomain, + dmn = ath5k_regdom2flag(ah->ah_regdomain, IEEE80211_CHANNELS_5GHZ_MIN); chfreq = CHANNEL_5GHZ; break; @@ -1796,7 +1796,7 @@ static unsigned int ath_copy_channels(struct ath_hw *ah, case MODE_ATHEROS_TURBOG: size = all ? 26 : ARRAY_SIZE(chans_2ghz); chans = chans_2ghz; - dmn = ieee80211_regdomain2flag(ah->ah_regdomain, + dmn = ath5k_regdom2flag(ah->ah_regdomain, IEEE80211_CHANNELS_2GHZ_MIN); chfreq = CHANNEL_2GHZ; break; diff --git a/ath5k_hw.c b/ath5k_hw.c index eb02bdd..541228e 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -2343,22 +2343,22 @@ static int ath5k_eeprom_read_mac(struct ath_hw *hal, u8 *mac) * Read/Write regulatory domain */ static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, - enum ieee80211_regdomain *regdomain) + enum ath5k_regdom *regdomain) { u16 ee_regdomain; /* Read current value */ if (write != true) { ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; - *regdomain = ath5k_regdomain_to_ieee(ee_regdomain); + *regdomain = ath5k_regdom_to_ieee(ee_regdomain); return true; } - ee_regdomain = ath5k_regdomain_from_ieee(*regdomain); + ee_regdomain = ath5k_regdom_from_ieee(*regdomain); /* Try to write a new value */ if (hal->ah_capabilities.cap_eeprom.ee_protect & - AR5K_EEPROM_PROTECT_WR_128_191) + AR5K_EEPROM_PROTECT_WR_128_191) return false; if (ath5k_hw_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0) return false; @@ -2373,9 +2373,9 @@ static bool ath5k_eeprom_regulation_domain(struct ath_hw *hal, bool write, */ int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain) { - enum ieee80211_regdomain ieee_regdomain; + enum ath5k_regdom ieee_regdomain; - ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); + ieee_regdomain = ath5k_regdom_to_ieee(regdomain); if (ath5k_eeprom_regulation_domain(hal, true, &ieee_regdomain) == true) return 0; @@ -4391,7 +4391,7 @@ bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags) u16 ath5k_get_regdomain(struct ath_hw *hal) { u16 regdomain; - enum ieee80211_regdomain ieee_regdomain; + enum ath5k_regdom ieee_regdomain; #ifdef COUNTRYCODE u16 code; #endif @@ -4408,7 +4408,7 @@ u16 ath5k_get_regdomain(struct ath_hw *hal) ieee_regdomain = ieee80211_countrycode2regdomain(code); #endif - regdomain = ath5k_regdomain_from_ieee(ieee_regdomain); + regdomain = ath5k_regdom_from_ieee(ieee_regdomain); hal->ah_capabilities.cap_regdomain.reg_current = regdomain; return regdomain; diff --git a/ath5k_hw.h b/ath5k_hw.h index 69986e1..d878ea6 100644 --- a/ath5k_hw.h +++ b/ath5k_hw.h @@ -2954,8 +2954,8 @@ struct ath5k_capabilities { * Active regulation domain settings */ struct { - enum ieee80211_regdomain reg_current; - enum ieee80211_regdomain reg_hw; + enum ath5k_regdom reg_current; + enum ath5k_regdom reg_hw; } cap_regdomain; /* @@ -2988,7 +2988,7 @@ struct ath_hw { void *ah_sc; void __iomem *ah_sh; - enum ieee80211_countrycode ah_country_code; + enum ath5k_countrycode ah_country_code; enum ath5k_int ah_imr; diff --git a/ath5k_regdom.c b/ath5k_regdom.c index cdbc618..455b923 100644 --- a/ath5k_regdom.c +++ b/ath5k_regdom.c @@ -15,10 +15,10 @@ #include "ath5k_regdom.h" -static const struct ieee80211_regdomainmap { - enum ieee80211_regdomain dmn; - enum ieee80211_regdomain dmn5; - enum ieee80211_regdomain dmn2; +static const struct ath5k_regdommap { + enum ath5k_regdom dmn; + enum ath5k_regdom dmn5; + enum ath5k_regdom dmn2; } r_map[] = { { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, @@ -71,8 +71,7 @@ static const struct ieee80211_regdomainmap { { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, }; -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, - u16 mhz) +enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom dmn, u16 mhz) { unsigned int i; @@ -89,7 +88,7 @@ enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain dmn, return DMN_DEBUG; } -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) +u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee) { u32 regdomain = (u32)ieee; @@ -97,17 +96,17 @@ u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee) * Use the default regulation domain if the value is empty * or not supported by the net80211 regulation code. */ - if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + if (ath5k_regdom2flag(regdomain, IEEE80211_CHANNELS_5GHZ_MIN) == + DMN_DEBUG) return (u16)AR5K_TUNE_REGDOMAIN; /* It is supported, just return the value */ return regdomain; } -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain) +enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain) { - enum ieee80211_regdomain ieee = (enum ieee80211_regdomain)regdomain; + enum ath5k_regdom ieee = (enum ath5k_regdom)regdomain; return ieee; } diff --git a/ath5k_regdom.h b/ath5k_regdom.h index b5f67f3..ebaeabe 100644 --- a/ath5k_regdom.h +++ b/ath5k_regdom.h @@ -16,7 +16,7 @@ #define AR5K_TUNE_CTRY CTRY_DEFAULT -enum ieee80211_regdomain { +enum ath5k_regdom { DMN_DEFAULT = 0x00, DMN_NULL_WORLD = 0x03, DMN_NULL_ETSIB = 0x07, @@ -96,7 +96,7 @@ enum ieee80211_regdomain { #define IEEE80211_DMN(_d) ((_d) & ~0xf0000000) -enum ieee80211_countrycode { +enum ath5k_countrycode { CTRY_DEFAULT = 0, /* Default domain (NA) */ CTRY_ALBANIA = 8, /* Albania */ CTRY_ALGERIA = 12, /* Algeria */ @@ -220,9 +220,9 @@ enum ieee80211_countrycode { #define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ #define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ -struct ieee80211_regchannel { +struct ath5k_regchannel { u16 chan; - enum ieee80211_regdomain domain; + enum ath5k_regdom domain; u32 mode; }; @@ -485,8 +485,8 @@ struct ieee80211_regchannel { /*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \ } -enum ieee80211_regdomain ieee80211_regdomain2flag(enum ieee80211_regdomain, u16); -u16 ath5k_regdomain_from_ieee(enum ieee80211_regdomain ieee); -enum ieee80211_regdomain ath5k_regdomain_to_ieee(u16 regdomain); +enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom, u16); +u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee); +enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain); -#endif /* _NET80211_IEEE80211_REGDOMAIN_H_ */ +#endif commit 45551c33f749ad1a0bbb075ac661a66efae07090 Author: Jiri Slaby Date: Fri Aug 3 23:05:14 2007 +0200 ath.c -> ath5k_base.c diff --git a/Makefile b/Makefile index 5d941fe..ace1a37 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ KDIR=/lib/modules/$(shell uname -r)/build KBUILD=$(MAKE) -C $(KDIR) M=$(PWD) -ath5k-objs := ath.o ath5k_hw.o ath5k_regdom.o +ath5k-objs := ath5k_base.o ath5k_hw.o ath5k_regdom.o obj-m += ath5k.o diff --git a/ath.c b/ath.c deleted file mode 100644 index cc4c913..0000000 --- a/ath.c +++ /dev/null @@ -1,2567 +0,0 @@ -/*- - * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting - * Copyright (c) 2004-2005 Atheros Communications, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - */ -#define ATH_PCI_VERSION "0.9.5.0-BSD" - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include "ath.h" -#include "ath5k_reg.h" - -#define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ -#define ATH_DUMP_SKB 0 /* show skb contents */ -#define AR_DEBUG 1 - -/* unaligned little endian access */ -#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) -#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) - -#if AR_DEBUG -#define DPRINTF(sc, _m, _fmt...) do { \ - if (unlikely(((sc)->debug & (_m)) && net_ratelimit())) \ - printk(KERN_DEBUG _fmt); \ -} while (0) -#else -static inline int __attribute__ ((format (printf, 3, 4))) -DPRINTF(struct ath_softc *sc, unsigned int m, const char *fmt, ...) -{ - return 0; -} -#endif -enum { - ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ - ATH_DEBUG_RESET = 0x00000020, /* reset processing */ - ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ - ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ - ATH_DEBUG_INTR = 0x00001000, /* ISR */ - ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ - ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ - ATH_DEBUG_LED = 0x00100000, /* led management */ - ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ - ATH_DEBUG_ANY = 0xffffffff -}; - -enum { - ATH_LED_TX, - ATH_LED_RX, -}; - -static int ath_calinterval = ATH_SHORT_CALIB; - -static int countrycode = CTRY_DEFAULT; -static int outdoor = true; -static int xchanmode = true; -module_param(countrycode, int, 0); -MODULE_PARM_DESC(countrycode, "Override default country code"); -module_param(outdoor, int, 0); -MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); -module_param(xchanmode, int, 0); -MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); - -#if AR_DEBUG -static unsigned int ath_debug; -module_param_named(debug, ath_debug, uint, 0); -#endif - -/* - * User a static table of PCI id's for now. While this is the - * "new way" to do things, we may want to switch back to having - * the HAL check them by defining a probe method. - */ -static struct pci_device_id ath_pci_id_table[] __devinitdata = { - { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */ - { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */ - { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 */ - { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */ - { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */ - { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */ - { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */ - { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */ - { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, - { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ - { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ - { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ - { 0 } -}; -MODULE_DEVICE_TABLE(pci, ath_pci_id_table); - -static void ath_led_event(struct ath_softc *, int); -static int ath_reset(struct ieee80211_hw *); - -#if AR_DEBUG -static void ath_printrxbuf(struct ath_buf *bf, int done) -{ - struct ath_desc *ds = bf->desc; - - printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", - ds, (unsigned long long)bf->daddr, - ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], - !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); -} - -static void ath_printtxbuf(struct ath_buf *bf, int done) -{ - struct ath_desc *ds = bf->desc; - - printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x " - "%08x %c\n", - ds, (unsigned long long)bf->daddr, - ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], - !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); -} -#endif - -#if ATH_DUMP_SKB -static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) -{ - print_hex_dump_bytes(prefix, DUMP_PREFIX_NONE, skb->data, - min(200U, skb->len)); -} -#else -static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) {} -#endif - -static inline void ath_cleanup_txbuf(struct ath_softc *sc, struct ath_buf *bf) -{ - BUG_ON(!bf); - if (!bf->skb) - return; - pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, - PCI_DMA_TODEVICE); - dev_kfree_skb(bf->skb); - bf->skb = NULL; -} - -static void ath_tasklet_reset(unsigned long data) -{ - struct ath_softc *sc = (void *)data; - - ath_reset(sc->hw); -} - -static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) -{ - struct ieee80211_tx_status txs = {}; - struct ath_buf *bf, *bf0; - struct ath_desc *ds; - struct sk_buff *skb; - int ret; - - spin_lock(&txq->lock); - list_for_each_entry_safe(bf, bf0, &txq->q, list) { - ds = bf->desc; - - /* TODO only one segment */ - pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, - sc->desc_len, PCI_DMA_FROMDEVICE); - ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); - if (unlikely(ret == -EINPROGRESS)) - break; - else if (unlikely(ret)) { - printk(KERN_ERR "ath: error %d while processing " - "queue %u\n", ret, txq->qnum); - break; - } - - skb = bf->skb; - bf->skb = NULL; - pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, - PCI_DMA_TODEVICE); - - txs.control = bf->ctl; - txs.retry_count = ds->ds_txstat.ts_shortretry + - ds->ds_txstat.ts_longretry / 6; - if (unlikely(ds->ds_txstat.ts_status)) { - sc->ll_stats.dot11ACKFailureCount++; - if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { - txs.excessive_retries = 1; - } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { - txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; - } - } else { - txs.flags |= IEEE80211_TX_STATUS_ACK; - txs.ack_signal = ds->ds_txstat.ts_rssi; - } - - ieee80211_tx_status(sc->hw, skb, &txs); - sc->tx_stats.data[txq->qnum].count++; - -// printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); - - spin_lock(&sc->txbuflock); - sc->tx_stats.data[txq->qnum].len--; - list_move_tail(&bf->list, &sc->txbuf); - sc->txbuf_len++; - spin_unlock(&sc->txbuflock); - } - if (likely(list_empty(&txq->q))) - txq->link = NULL; - spin_unlock(&txq->lock); - if (sc->txbuf_len > ATH_TXBUF / 5) - ieee80211_wake_queues(sc->hw); -} - -static void ath_tasklet_tx(unsigned long data) -{ - struct ath_softc *sc = (void *)data; - - ath_tx_processq(sc, sc->txq); - - ath_led_event(sc, ATH_LED_TX); -} - -static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) -{ - struct ath_hw *ah = sc->ah; - struct sk_buff *skb = bf->skb; - struct ath_desc *ds; - - if (likely(skb == NULL)) { - unsigned int off; - - /* - * Allocate buffer with headroom_needed space for the - * fake physical layer header at the start. - */ - skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); - if (unlikely(skb == NULL)) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " - "size %u failed\n", __func__, - sc->rxbufsize + sc->cachelsz - 1); - sc->stats.ast_rx_nobuf++; - return -ENOMEM; - } - /* - * Cache-line-align. This is important (for the - * 5210 at least) as not doing so causes bogus data - * in rx'd frames. - */ - off = ((unsigned long)skb->data) % sc->cachelsz; - if (off != 0) - skb_reserve(skb, sc->cachelsz - off); - - bf->skb = skb; - bf->skbaddr = pci_map_single(sc->pdev, - skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); - if (unlikely(pci_dma_mapping_error(bf->skbaddr))) { - printk(KERN_ERR "%s: DMA mapping failed\n", __func__); - dev_kfree_skb(skb); - bf->skb = NULL; - sc->stats.ast_rx_busdma++; - return -ENOMEM; - } - } - - /* - * Setup descriptors. For receive we always terminate - * the descriptor list with a self-linked entry so we'll - * not get overrun under high load (as can happen with a - * 5212 when ANI processing enables PHY error frames). - * - * To insure the last descriptor is self-linked we create - * each descriptor as self-linked and add it to the end. As - * each additional descriptor is added the previous self-linked - * entry is ``fixed'' naturally. This should be safe even - * if DMA is happening. When processing RX interrupts we - * never remove/process the last, self-linked, entry on the - * descriptor list. This insures the hardware always has - * someplace to write a new frame. - */ - ds = bf->desc; - ds->ds_link = bf->daddr; /* link to self */ - ds->ds_data = bf->skbaddr; - ath5k_hw_setup_rx_desc(ah, ds, - skb_tailroom(skb), /* buffer size */ - 0); - - if (sc->rxlink != NULL) - *sc->rxlink = bf->daddr; - sc->rxlink = &ds->ds_link; - return 0; -} - -static unsigned int ath_rx_decrypted(struct ath_softc *sc, - struct ath_desc *ds, struct sk_buff *skb) -{ - struct ieee80211_hdr *hdr = (void *)skb->data; - unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); - - if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && - ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID) - return RX_FLAG_DECRYPTED; - - /* Apparently when a default key is used to decrypt the packet - the hal does not set the index used to decrypt. In such cases - get the index from the packet. */ - if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && - !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && - skb->len >= hlen + 4) { - keyix = skb->data[hlen + 3] >> 6; - - if (test_bit(keyix, sc->keymap)) - return RX_FLAG_DECRYPTED; - } - - return 0; -} - -static inline u64 ath_extend_tsf(struct ath_hw *ah, u32 rstamp) -{ - u64 tsf = ath5k_hw_get_tsf64(ah); - - if ((tsf & 0x7fff) < rstamp) - tsf -= 0x8000; - - return (tsf &~ 0x7fff) | rstamp; -} - -static void ath_tasklet_rx(unsigned long data) -{ - struct ieee80211_rx_status rxs = {}; - struct sk_buff *skb; - struct ath_softc *sc = (void *)data; - struct ath_buf *bf; - struct ath_desc *ds; - u16 len; - u8 stat; - int ret; - - spin_lock(&sc->rxbuflock); - do { - if (unlikely(list_empty(&sc->rxbuf))) { - if (net_ratelimit()) - printk(KERN_WARNING "ath: empty rx buf pool\n"); - break; - } - bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); - BUG_ON(bf->skb == NULL); - skb = bf->skb; - ds = bf->desc; - - /* TODO only one segment */ - pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, - sc->desc_len, PCI_DMA_FROMDEVICE); - - if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */ - break; - - ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); - if (unlikely(ret == -EINPROGRESS)) - break; - else if (unlikely(ret)) { - if (net_ratelimit()) - printk(KERN_ERR "ath: error in processing rx " - "descriptor\n"); - return; - } - - if (unlikely(ds->ds_rxstat.rs_more)) { - if (net_ratelimit()) - printk(KERN_INFO "ath: unsupported jumbo\n"); - goto next; - } - - stat = ds->ds_rxstat.rs_status; - if (unlikely(stat)) { - if (stat & AR5K_RXERR_CRC) - sc->stats.ast_rx_crcerr++; - if (stat & AR5K_RXERR_FIFO) - sc->stats.ast_rx_fifoerr++; - if (stat & AR5K_RXERR_PHY) { - sc->stats.ast_rx_phyerr++; - sc->stats.ast_rx_phy - [ds->ds_rxstat.rs_phyerr & 0x1f]++; - goto next; - } - if (stat & AR5K_RXERR_DECRYPT) { - /* - * Decrypt error. If the error occurred - * because there was no hardware key, then - * let the frame through so the upper layers - * can process it. This is necessary for 5210 - * parts which have no way to setup a ``clear'' - * key cache entry. - * - * XXX do key cache faulting - */ - if (ds->ds_rxstat.rs_keyix == - AR5K_RXKEYIX_INVALID && - !(stat & AR5K_RXERR_CRC)) - goto accept; - sc->stats.ast_rx_badcrypt++; - } - if (stat & AR5K_RXERR_MIC) { - rxs.flag |= RX_FLAG_MMIC_ERROR; - sc->stats.ast_rx_badmic++; - goto accept; - } - - /* let crypto-error packets fall through in MNTR */ - if ((stat &~ (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || - sc->opmode != IEEE80211_IF_TYPE_MNTR) - goto next; - } -accept: - len = ds->ds_rxstat.rs_datalen; - pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len, - PCI_DMA_FROMDEVICE); - pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, - PCI_DMA_FROMDEVICE); - bf->skb = NULL; - - if (unlikely((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit())) - printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); - - skb_put(skb, len); - - sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; - - if (sc->opmode == IEEE80211_IF_TYPE_MNTR) - rxs.mactime = ath_extend_tsf(sc->ah, - ds->ds_rxstat.rs_tstamp); - else - rxs.mactime = ds->ds_rxstat.rs_tstamp; - rxs.freq = sc->curchan->freq; - rxs.channel = sc->curchan->chan; - rxs.phymode = sc->curmode; - rxs.ssi = ds->ds_rxstat.rs_rssi; - rxs.antenna = ds->ds_rxstat.rs_antenna; - rxs.rate = ds->ds_rxstat.rs_rate; - rxs.flag |= ath_rx_decrypted(sc, ds, skb); - -// printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); - ath_dump_skb(skb, "r"); - - __ieee80211_rx(sc->hw, skb, &rxs); - sc->led_rxrate = ds->ds_rxstat.rs_rate; - ath_led_event(sc, ATH_LED_RX); -next: - list_move_tail(&bf->list, &sc->rxbuf); - } while (ath_rxbuf_init(sc, bf) == 0); - spin_unlock(&sc->rxbuflock); -} - -/* - * Setup the beacon frame for transmit. - */ -static int ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, - struct ieee80211_tx_control *ctl) -{ - struct sk_buff *skb = bf->skb; - struct ath_hw *ah = sc->ah; - struct ath_desc *ds; - int ret, antenna = 0; - u32 flags; - - bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, - PCI_DMA_TODEVICE); - DPRINTF(sc, ATH_DEBUG_BEACON, "%s: skb %p [data %p len %u] " - "skbaddr %llx\n", __func__, skb, skb->data, skb->len, - (unsigned long long)bf->skbaddr); - if (pci_dma_mapping_error(bf->skbaddr)) { - printk(KERN_ERR "ath: beacon DMA mapping failed\n"); - return -EIO; - } - - ds = bf->desc; - - flags = AR5K_TXDESC_NOACK; - if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) { - ds->ds_link = bf->daddr; /* self-linked */ - flags |= AR5K_TXDESC_VEOL; - /* - * Let hardware handle antenna switching if txantenna is not set - */ - } else { - ds->ds_link = 0; - /* - * Switch antenna every 4 beacons if txantenna is not set - * XXX assumes two antenna - */ - if (antenna == 0) { - antenna = (sc->stats.ast_be_xmit & 4 ? 2 : 1); - } - } - - ds->ds_data = bf->skbaddr; - ret = ah->ah_setup_tx_desc(ah, ds, skb->len + FCS_LEN, - ieee80211_get_hdrlen_from_skb(skb), - AR5K_PKT_TYPE_BEACON, 0xffff, ctl->tx_rate, 1, - AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0); - if (ret) - goto err_unmap; - /* NB: beacon's BufLen must be a multiple of 4 bytes */ - ret = ah->ah_fill_tx_desc(ah, ds, roundup(skb->len, 4), true, true); - if (ret) - goto err_unmap; - - return 0; -err_unmap: - pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); - return ret; -} - -/* - * Transmit a beacon frame at SWBA. Dynamic updates to the - * frame contents are done as needed and the slot time is - * also adjusted based on current state. - * - * this is usually called from interrupt context (ath_intr()) - * but also from ath_beacon_config() in IBSS mode which in turn - * can be called from a tasklet and user context - */ -static void ath_beacon_send(struct ath_softc *sc) -{ - struct ath_buf *bf = sc->bbuf; - struct ath_hw *ah = sc->ah; - - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__); - - if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA || - sc->opmode == IEEE80211_IF_TYPE_MNTR)) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: bf=%p bf_skb=%p\n", - __func__, bf, bf ? bf->skb : NULL); - return; - } - /* - * Check if the previous beacon has gone out. If - * not don't don't try to post another, skip this - * period and wait for the next. Missed beacons - * indicate a problem and should not occur. If we - * miss too many consecutive beacons reset the device. - */ - if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { - sc->bmisscount++; - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: missed %u consecutive beacons\n", - __func__, sc->bmisscount); - if (sc->bmisscount > 3) { /* NB: 3 is a guess */ - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: stuck beacon time (%u missed)\n", - __func__, sc->bmisscount); - tasklet_schedule(&sc->restq); - } - return; - } - if (unlikely(sc->bmisscount != 0)) { - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, - "%s: resume beacon xmit after %u misses\n", - __func__, sc->bmisscount); - sc->bmisscount = 0; - } - - /* - * Stop any current dma and put the new frame on the queue. - * This should never fail since we check above that no frames - * are still pending on the queue. - */ - if (unlikely(!ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: beacon queue %u didn't stop?\n", - __func__, sc->bhalq); - /* NB: the HAL still stops DMA, so proceed */ - } - pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len, - PCI_DMA_TODEVICE); - - ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr); - ath5k_hw_tx_start(ah, sc->bhalq); - DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: TXDP[%u] = %llx (%p)\n", - __func__, sc->bhalq, (unsigned long long)bf->daddr, bf->desc); - - sc->stats.ast_be_xmit++; -} - -static int ath_beaconq_config(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - struct ath5k_txq_info qi; - int ret; - - ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); - if (ret) - return ret; - if (sc->opmode == IEEE80211_IF_TYPE_AP || - sc->opmode == IEEE80211_IF_TYPE_IBSS) { - /* - * Always burst out beacon and CAB traffic. - */ - qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; - qi.tqi_cw_min = ATH_BEACON_CWMIN_DEFAULT; - qi.tqi_cw_max = ATH_BEACON_CWMAX_DEFAULT; - } - - ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi); - if (ret) { - printk(KERN_ERR "%s: unable to update parameters for beacon " - "hardware queue!\n", __func__); - return ret; - } - - return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; -} - -/* - * Configure the beacon and sleep timers. - * - * When operating as an AP this resets the TSF and sets - * up the hardware to notify us when we need to issue beacons. - * - * When operating in station mode this sets up the beacon - * timers according to the timestamp of the last received - * beacon and the current TSF, configures PCF and DTIM - * handling, programs the sleep registers so the hardware - * will wakeup in time to receive beacons, and configures - * the beacon miss handling so we'll receive a BMISS - * interrupt when we stop seeing beacons from the AP - * we've associated with. - */ -static void ath_beacon_config(struct ath_softc *sc) -{ -#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) - struct ath_hw *ah = sc->ah; - u32 uninitialized_var(nexttbtt), intval, tsftu; - u64 tsf; - - intval = sc->bintval & AR5K_BEACON_PERIOD; - if (WARN_ON(!intval)) - return; - - /* current TSF converted to TU */ - tsf = ath5k_hw_get_tsf64(ah); - tsftu = TSF_TO_TU((u32)(tsf >> 32), (u32)tsf); - - DPRINTF(sc, ATH_DEBUG_BEACON, "%s: intval %u hw tsftu %u\n", __func__, - intval, tsftu); - - if (sc->opmode == IEEE80211_IF_TYPE_STA) { - ath5k_hw_set_intr(ah, 0); - sc->imask |= AR5K_INT_BMISS; - sc->bmisscount = 0; - ath5k_hw_set_intr(ah, sc->imask); - } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS /* TODO || AP */) { - ath5k_hw_set_intr(ah, 0); - if (sc->opmode == IEEE80211_IF_TYPE_IBSS) { - /* - * Pull nexttbtt forward to reflect the current - * TSF. Add one intval otherwise the timespan - * can be too short for ibss merges. - */ - nexttbtt = tsftu + 2 * intval; - - DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u " - "intval %u\n", __func__, nexttbtt, intval); - - /* - * In IBSS mode enable the beacon timers but only - * enable SWBA interrupts if we need to manually - * prepare beacon frames. Otherwise we use a - * self-linked tx descriptor and let the hardware - * deal with things. - */ - if (!ath5k_hw_hasveol(ah)) - sc->imask |= AR5K_INT_SWBA; - } /* TODO else AP */ - - intval |= AR5K_BEACON_ENA; - - ath_beaconq_config(sc); - ath5k_hw_init_beacon(ah, nexttbtt, intval); - - sc->bmisscount = 0; - ath5k_hw_set_intr(ah, sc->imask); - /* - * When using a self-linked beacon descriptor in - * ibss mode load it once here. - */ - if (sc->opmode == IEEE80211_IF_TYPE_IBSS && - ath5k_hw_hasveol(ah)) - ath_beacon_send(sc); - } -#undef TSF_TO_TU -} - -/* - * Calculate the receive filter according to the - * operating mode and state: - * - * o always accept unicast, broadcast, and multicast traffic - * o maintain current state of phy error reception (the hal - * may enable phy error frames for noise immunity work) - * o probe request frames are accepted only when operating in - * hostap, adhoc, or monitor modes - * o enable promiscuous mode according to the interface state - * o accept beacons: - * - when operating in adhoc mode so the 802.11 layer creates - * node table entries for peers, - * - when operating in station mode for collecting rssi data when - * the station is otherwise quiet, or - * - when scanning - * o accept any additional packets specified by sc_rxfilter - */ -static u32 ath_calcrxfilter(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - unsigned int opmode = sc->opmode; - u32 rfilt; - - rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERR) | - AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | - AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_RADARERR; - - if (sc->opmode == IEEE80211_IF_TYPE_MNTR) - rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON | - AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM; - if (opmode != IEEE80211_IF_TYPE_STA) - rfilt |= AR5K_RX_FILTER_PROBEREQ; - if (opmode != IEEE80211_IF_TYPE_AP && sc->promisc) - rfilt |= AR5K_RX_FILTER_PROM; - if (opmode == IEEE80211_IF_TYPE_STA || opmode == IEEE80211_IF_TYPE_IBSS) - rfilt |= AR5K_RX_FILTER_BEACON; - - return rfilt; -} - -static void ath_mode_init(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - u32 rfilt; - - /* configure rx filter */ - rfilt = ath_calcrxfilter(sc); - ath5k_hw_set_rx_filter(ah, rfilt); - - if (ath5k_hw_hasbssidmask(ah)) - ath5k_hw_set_bssid_mask(ah, sc->bssidmask); - - /* configure operational mode */ - ath5k_hw_set_opmode(ah); - - ath5k_hw_set_mcast_filter(ah, 0, 0); - DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); -} - -/* - * Enable the receive h/w following a reset. - */ -static int ath_startrecv(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - struct ath_buf *bf; - int ret; - - sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz); - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: cachelsz %u rxbufsize %u\n", - __func__, sc->cachelsz, sc->rxbufsize); - - sc->rxlink = NULL; - - spin_lock_bh(&sc->rxbuflock); - list_for_each_entry(bf, &sc->rxbuf, list) { - ret = ath_rxbuf_init(sc, bf); - if (ret != 0) { - spin_unlock_bh(&sc->rxbuflock); - goto err; - } - } - bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); - spin_unlock_bh(&sc->rxbuflock); - - ath5k_hw_put_rx_buf(ah, bf->daddr); - ath5k_hw_start_rx(ah); /* enable recv descriptors */ - ath_mode_init(sc); /* set filters, etc. */ - ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ - - return 0; -err: - return ret; -} - -static inline void ath_update_txpow(struct ath_softc *sc) -{ - ath5k_hw_set_txpower_limit(sc->ah, 0); -} - -static int ath_stop_locked(struct ath_softc *); - -static int ath_init(struct ath_softc *sc) -{ - int ret; - - mutex_lock(&sc->lock); - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); - - /* - * Stop anything previously setup. This is safe - * no matter this is the first time through or not. - */ - ath_stop_locked(sc); - - /* - * The basic interface to setting the hardware in a good - * state is ``reset''. On return the hardware is known to - * be powered up and with interrupts disabled. This must - * be followed by initialization of the appropriate bits - * and then setup of the interrupt mask. - */ - sc->curchan = sc->hw->conf.chan; - ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false); - if (ret) { - printk(KERN_ERR "unable to reset hardware: %d\n", ret); - goto done; - } - /* - * This is needed only to setup initial state - * but it's best done after a reset. - */ - ath_update_txpow(sc); - - /* - * Setup the hardware after reset: the key cache - * is filled as needed and the receive engine is - * set going. Frame transmit is handled entirely - * in the frame output path; there's nothing to do - * here except setup the interrupt mask. - */ - ret = ath_startrecv(sc); - if (ret) - goto done; - - /* - * Enable interrupts. - */ - sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN - | AR5K_INT_FATAL | AR5K_INT_GLOBAL; - - ath5k_hw_set_intr(sc->ah, sc->imask); - - mod_timer(&sc->calib_tim, round_jiffies(jiffies + - msecs_to_jiffies(ath_calinterval * 1000))); - - ret = 0; -done: - mutex_unlock(&sc->lock); - return ret; -} - -/* - * Disable the receive h/w in preparation for a reset. - */ -static void ath_stoprecv(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - - ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ - ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ - ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ - mdelay(3); /* 3ms is long enough for 1 frame */ -#if AR_DEBUG - if (unlikely(sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL))) { - struct ath_desc *ds; - struct ath_buf *bf; - int status; - - printk(KERN_DEBUG "%s: rx queue %x, link %p\n", __func__, - ath5k_hw_get_rx_buf(ah), sc->rxlink); - - spin_lock_bh(&sc->rxbuflock); - list_for_each_entry(bf, &sc->rxbuf, list) { - ds = bf->desc; - status = ah->ah_proc_rx_desc(ah, ds); - if (!status || (sc->debug & ATH_DEBUG_FATAL)) - ath_printrxbuf(bf, status == 0); - } - spin_unlock_bh(&sc->rxbuflock); - } -#endif - sc->rxlink = NULL; /* just in case */ -} - -static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) -{ - struct ath_buf *bf, *bf0; - - /* - * NB: this assumes output has been stopped and - * we do not need to block ath_tx_tasklet - */ - spin_lock_bh(&txq->lock); - list_for_each_entry_safe(bf, bf0, &txq->q, list) { -#if AR_DEBUG - if (sc->debug & ATH_DEBUG_RESET) - ath_printtxbuf(bf, !sc->ah->ah_proc_tx_desc(sc->ah, - bf->desc)); -#endif - ath_cleanup_txbuf(sc, bf); - - spin_lock_bh(&sc->txbuflock); - sc->tx_stats.data[txq->qnum].len--; - list_move_tail(&bf->list, &sc->txbuf); - sc->txbuf_len++; - spin_unlock_bh(&sc->txbuflock); - } - txq->link = NULL; - spin_unlock_bh(&txq->lock); -} - -/* - * Drain the transmit queues and reclaim resources. - */ -static void ath_draintxq(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - int i; - - /* XXX return value */ - if (likely(!sc->invalid)) { - /* don't touch the hardware if marked invalid */ - (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, - ath5k_hw_get_tx_buf(ah, sc->bhalq)); - for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) - if (sc->txqs[i].setup) { - ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); - DPRINTF(sc, ATH_DEBUG_RESET, "%s: txq [%u] %x, " - "link %p\n", __func__, - sc->txqs[i].qnum, - ath5k_hw_get_tx_buf(ah, - sc->txqs[i].qnum), - sc->txqs[i].link); - } - } - ieee80211_start_queues(sc->hw); /* XXX move to callers */ - - for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) - if (sc->txqs[i].setup) - ath_tx_draintxq(sc, &sc->txqs[i]); -} - -static int ath_stop_locked(struct ath_softc *sc) -{ - struct ath_hw *ah = sc->ah; - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__, sc->invalid); - - /* - * Shutdown the hardware and driver: - * stop output from above - * disable interrupts - * turn off timers - * turn off the radio - * clear transmit machinery - * clear receive machinery - * drain and release tx queues - * reclaim beacon resources - * power down hardware - * - * Note that some of this work is not possible if the - * hardware is gone (invalid). - */ - ieee80211_stop_queues(sc->hw); - - if (!sc->invalid) { - if (sc->led_soft) { - del_timer_sync(&sc->led_tim); - ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); - sc->led_blinking = 0; - } - ath5k_hw_set_intr(ah, 0); - } - ath_draintxq(sc); - if (!sc->invalid) { - ath_stoprecv(sc); - ath5k_hw_phy_disable(ah); - } else - sc->rxlink = NULL; -// ath_beacon_free(sc); - - return 0; -} - -/* - * Stop the device, grabbing the top-level lock to protect - * against concurrent entry through ath_init (which can happen - * if another thread does a system call and the thread doing the - * stop is preempted). - */ -static int ath_stop_hw(struct ath_softc *sc) -{ - int ret; - - mutex_lock(&sc->lock); - ret = ath_stop_locked(sc); - if (ret == 0 && !sc->invalid) { - /* - * Set the chip in full sleep mode. Note that we are - * careful to do this only when bringing the interface - * completely to a stop. When the chip is in this state - * it must be carefully woken up or references to - * registers in the PCI clock domain may freeze the bus - * (and system). This varies by chip and is mostly an - * issue with newer parts that go to sleep more quickly. - */ - if (sc->ah->ah_mac_version >= 7 && sc->ah->ah_mac_revision >= 8) { - /* - * XXX - * don't put newer MAC revisions > 7.8 to sleep because - * of the above mentioned problems - */ - DPRINTF(sc, ATH_DEBUG_RESET, "%s: mac version > 7.8, " - "not putting device to sleep\n", __func__); - } - else { - DPRINTF(sc, ATH_DEBUG_RESET, - "%s: putting device to full sleep\n", __func__); - ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); - } - } - ath_cleanup_txbuf(sc, sc->bbuf); - mutex_unlock(&sc->lock); - - del_timer_sync(&sc->calib_tim); - - return ret; -} - -static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) -{ - if (unlikely(sc->led_soft)) { - /* from Atheros NDIS driver, w/ permission */ - static const struct { - u16 rate; /* tx/rx 802.11 rate */ - u16 timeOn; /* LED on time (ms) */ - u16 timeOff; /* LED off time (ms) */ - } blinkrates[] = { - { 108, 40, 10 }, - { 96, 44, 11 }, - { 72, 50, 13 }, - { 48, 57, 14 }, - { 36, 67, 16 }, - { 24, 80, 20 }, - { 22, 100, 25 }, - { 18, 133, 34 }, - { 12, 160, 40 }, - { 10, 200, 50 }, - { 6, 240, 58 }, - { 4, 267, 66 }, - { 2, 400, 100 }, - { 0, 500, 130 } - }; - const struct ath5k_rate_table* rt = - ath5k_hw_get_rate_table(sc->ah, mode); - unsigned int i, j; - - BUG_ON(rt == NULL); - - memset(sc->hwmap, 0, sizeof(sc->hwmap)); - for (i = 0; i < 32; i++) { - u8 ix = rt->rate_code_to_index[i]; - if (ix == 0xff) { - sc->hwmap[i].ledon = msecs_to_jiffies(500); - sc->hwmap[i].ledoff = msecs_to_jiffies(130); - continue; - } - sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; - if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == - MODULATION_OFDM) - sc->hwmap[i].txflags |= - IEEE80211_RADIOTAP_F_SHORTPRE; - /* receive frames include FCS */ - sc->hwmap[i].rxflags = sc->hwmap[i].txflags | - IEEE80211_RADIOTAP_F_FCS; - /* setup blink rate table to avoid per-packet lookup */ - for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) - if (blinkrates[j].rate == /* XXX why 7f? */ - (rt->rates[ix].dot11_rate&0x7f)) - break; - - sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j]. - timeOn); - sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j]. - timeOff); - } - } - - sc->curmode = mode; -} - -/* - * Set/change channels. If the channel is really being changed, - * it's done by reseting the chip. To accomplish this we must - * first cleanup any pending DMA, then restart stuff after a la - * ath_init. - */ -static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) -{ - struct ath_hw *ah = sc->ah; - int ret; - - DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", - __func__, sc->curchan->chan, sc->curchan->freq, - chan->chan, chan->freq); - - if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) { - /* - * To switch channels clear any pending DMA operations; - * wait long enough for the RX fifo to drain, reset the - * hardware at the new frequency, and then re-enable - * the relevant bits of the h/w. - */ - ath5k_hw_set_intr(ah, 0); /* disable interrupts */ - ath_draintxq(sc); /* clear pending tx frames */ - ath_stoprecv(sc); /* turn off frame recv */ - ret = ath5k_hw_reset(ah, sc->opmode, chan, true); - if (ret) { - printk(KERN_ERR "%s: unable to reset channel %u " - "(%u Mhz)\n", __func__, chan->chan, chan->freq); - return ret; - } - sc->curchan = chan; - ath_update_txpow(sc); - - /* - * Re-enable rx framework. - */ - ret = ath_startrecv(sc); - if (ret) { - printk(KERN_ERR "%s: unable to restart recv logic\n", - __func__); - return ret; - } - - /* - * Change channels and update the h/w rate map - * if we're switching; e.g. 11a to 11b/g. - */ -// ath_chan_change(sc, chan); - - /* - * Re-enable interrupts. - */ - ath5k_hw_set_intr(ah, sc->imask); - } - - return 0; -} - -static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, - struct ieee80211_tx_control *ctl) -{ - struct ath_hw *ah = sc->ah; - struct ath_txq *txq = sc->txq; - struct ath_desc *ds = bf->desc; - struct sk_buff *skb = bf->skb; - unsigned int hdrpad, pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; - int ret; - - flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; - bf->ctl = *ctl; - /* XXX endianness */ - bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, - PCI_DMA_TODEVICE); - - if (ctl->flags & IEEE80211_TXCTL_NO_ACK) - flags |= AR5K_TXDESC_NOACK; - - if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) - printk(KERN_DEBUG "tx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); - - hdrpad = 0; - pktlen = skb->len - hdrpad + FCS_LEN; - - if (ctl->key_idx != HW_KEY_IDX_INVALID) { - keyidx = ctl->key_idx; - pktlen += ctl->icv_len; - } - - ret = ah->ah_setup_tx_desc(ah, ds, pktlen, - ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, - 0xffff, ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0); - if (ret) - goto err_unmap; - - ds->ds_link = 0; - ds->ds_data = bf->skbaddr; - - ret = ah->ah_fill_tx_desc(ah, ds, skb->len, true, true); - if (ret) - goto err_unmap; - - spin_lock_bh(&txq->lock); - list_add_tail(&bf->list, &txq->q); - sc->tx_stats.data[txq->qnum].len++; - if (txq->link == NULL) /* is this first packet? */ - ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); - else /* no, so only link it */ - *txq->link = bf->daddr; - - txq->link = &ds->ds_link; - ath5k_hw_tx_start(ah, txq->qnum); - spin_unlock_bh(&txq->lock); - -// printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); - - return 0; -err_unmap: - pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); - return ret; -} - -static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, - struct ieee80211_tx_control *ctl) -{ - struct ath_softc *sc = hw->priv; - struct ath_buf *bf; - unsigned long flags; - - ath_dump_skb(skb, "t"); - - if (sc->opmode == IEEE80211_IF_TYPE_MNTR) - DPRINTF(sc, ATH_DEBUG_XMIT, "tx in monitor (scan?)\n"); - - sc->led_txrate = ctl->tx_rate; - - spin_lock_irqsave(&sc->txbuflock, flags); - if (list_empty(&sc->txbuf)) { - if (net_ratelimit()) - printk(KERN_ERR "ath: no further txbuf available, " - "dropping packet\n"); - sc->stats.ast_tx_nobuf++; - spin_unlock_irqrestore(&sc->txbuflock, flags); - ieee80211_stop_queue(hw, ctl->queue); - return -1; - } - bf = list_first_entry(&sc->txbuf, struct ath_buf, list); - list_del(&bf->list); - sc->txbuf_len--; - if (list_empty(&sc->txbuf)) { - sc->stats.ast_tx_qstop++; - ieee80211_stop_queues(hw); - } - spin_unlock_irqrestore(&sc->txbuflock, flags); - - bf->skb = skb; - - if (ath_tx_bf(sc, bf, ctl)) { - bf->skb = NULL; - spin_lock_irqsave(&sc->txbuflock, flags); - list_add_tail(&bf->list, &sc->txbuf); - sc->txbuf_len++; - spin_unlock_irqrestore(&sc->txbuflock, flags); - dev_kfree_skb_any(skb); - return 0; - } - - return 0; -} - -static int ath_reset(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hw *ah = sc->ah; - int ret; - - DPRINTF(sc, ATH_DEBUG_RESET, "resetting\n"); - /* - * Convert to a HAL channel description with the flags - * constrained to reflect the current operating mode. - */ - sc->curchan = hw->conf.chan; - - ath5k_hw_set_intr(ah, 0); - ath_draintxq(sc); - ath_stoprecv(sc); - - ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true); - if (unlikely(ret)) { - printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); - goto err; - } - ath_update_txpow(sc); - - ret = ath_startrecv(sc); - if (unlikely(ret)) { - printk(KERN_ERR "ath: can't start recv logic\n"); - goto err; - } - /* - * We may be doing a reset in response to an ioctl - * that changes the channel so update any state that - * might change as a result. - */ -// ath_chan_change(sc, c); - ath_beacon_config(sc); - /* intrs are started by ath_beacon_config */ - - ieee80211_wake_queues(hw); - - return 0; -err: - return ret; -} - -static int ath_open(struct ieee80211_hw *hw) -{ - return ath_init(hw->priv); -} - -static int ath_stop(struct ieee80211_hw *hw) -{ - return ath_stop_hw(hw->priv); -} - -static int ath_add_interface(struct ieee80211_hw *hw, - struct ieee80211_if_init_conf *conf) -{ - struct ath_softc *sc = hw->priv; - int ret; - - mutex_lock(&sc->lock); - if (sc->iface_id) { - ret = 0; - goto end; - } - - sc->iface_id = conf->if_id; - - switch (conf->type) { - case IEEE80211_IF_TYPE_STA: - case IEEE80211_IF_TYPE_IBSS: - case IEEE80211_IF_TYPE_MNTR: - sc->opmode = conf->type; - break; - default: - ret = -EOPNOTSUPP; - goto end; - } - ret = 0; -end: - mutex_unlock(&sc->lock); - return ret; -} - -static void ath_remove_interface(struct ieee80211_hw *hw, - struct ieee80211_if_init_conf *conf) -{ - struct ath_softc *sc = hw->priv; - - mutex_lock(&sc->lock); - if (sc->iface_id != conf->if_id) { - goto end; - } - - sc->iface_id = 0; -end: - mutex_unlock(&sc->lock); -} - -static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) -{ - struct ath_softc *sc = hw->priv; - - sc->bintval = conf->beacon_int * 1000 / 1024; - ath_setcurmode(sc, conf->phymode); - - return ath_chan_set(sc, conf->chan); -} - -static int ath_config_interface(struct ieee80211_hw *hw, int if_id, - struct ieee80211_if_conf *conf) -{ - struct ath_softc *sc = hw->priv; - int ret; - - mutex_lock(&sc->lock); - if (sc->iface_id != if_id) { - ret = -EIO; - goto unlock; - } - if (conf->bssid) - ath5k_hw_set_associd(sc->ah, conf->bssid, 0 /* FIXME: aid */); - mutex_unlock(&sc->lock); - - return ath_reset(hw); -unlock: - mutex_unlock(&sc->lock); - return ret; -} - -static void ath_set_multicast_list(struct ieee80211_hw *hw, - unsigned short flags, int mc_count) -{ - struct ath_softc *sc = hw->priv; - unsigned int prom = !!(flags & IFF_PROMISC); - u32 rfilt; - - if (sc->promisc != prom) { - sc->promisc = prom; - rfilt = ath_calcrxfilter(sc); - ath5k_hw_set_rx_filter(sc->ah, rfilt); - } -} - -static int ath_set_key(struct ieee80211_hw *hw, set_key_cmd cmd, - u8 *addr, struct ieee80211_key_conf *key, int aid) -{ - struct ath_softc *sc = hw->priv; - int ret = 0; - - mutex_lock(&sc->lock); - - switch (cmd) { - case SET_KEY: - if (key->alg != ALG_WEP && key->alg != ALG_NONE && - key->alg != ALG_NULL) { - ret = -EINVAL; - goto unlock; - } - - ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr); - if (ret) { - printk(KERN_ERR "ath: can't set the key\n"); - goto unlock; - } - - set_bit(key->keyidx, sc->keymap); - key->hw_key_idx = key->keyidx; - key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT; - break; - case DISABLE_KEY: - ath5k_hw_reset_key(sc->ah, key->keyidx); - clear_bit(key->keyidx, sc->keymap); - break; - case REMOVE_ALL_KEYS: { - unsigned int i; - for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) { - ath5k_hw_reset_key(sc->ah, i); - clear_bit(i, sc->keymap); - } - break; - } - default: - ret = -EINVAL; - goto unlock; - } - -unlock: - mutex_unlock(&sc->lock); - return ret; -} - -static int ath_get_stats(struct ieee80211_hw *hw, - struct ieee80211_low_level_stats *stats) -{ - struct ath_softc *sc = hw->priv; - - memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); - - return 0; -} - -static int ath_get_tx_stats(struct ieee80211_hw *hw, - struct ieee80211_tx_queue_stats *stats) -{ - struct ath_softc *sc = hw->priv; - - memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); - - return 0; -} - -static u64 ath_get_tsf(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - - return ath5k_hw_get_tsf64(sc->ah); -} - -static void ath_reset_tsf(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - - ath5k_hw_reset_tsf(sc->ah); -} - -static int ath_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, - struct ieee80211_tx_control *ctl) -{ - struct ath_softc *sc = hw->priv; - int ret; - - ath_dump_skb(skb, "b"); - - mutex_lock(&sc->lock); - - if (sc->opmode != IEEE80211_IF_TYPE_IBSS) { - ret = -EIO; - goto end; - } - - ath_cleanup_txbuf(sc, sc->bbuf); - sc->bbuf->skb = skb; - ret = ath_beacon_setup(sc, sc->bbuf, ctl); - if (ret) - sc->bbuf->skb = NULL; - -end: - mutex_unlock(&sc->lock); - return ret; -} - -static struct ieee80211_ops ath_hw_ops = { - .tx = ath_tx, - .reset = ath_reset, - .open = ath_open, - .stop = ath_stop, - .add_interface = ath_add_interface, - .remove_interface = ath_remove_interface, - .config = ath_config, - .config_interface = ath_config_interface, - .set_multicast_list = ath_set_multicast_list, - .set_key = ath_set_key, - .get_stats = ath_get_stats, - .conf_tx = NULL, - .get_tx_stats = ath_get_tx_stats, - .get_tsf = ath_get_tsf, - .reset_tsf = ath_reset_tsf, - .beacon_update = ath_beacon_update, -}; - -/* - * Periodically recalibrate the PHY to account - * for temperature/environment changes. - */ -static void ath_calibrate(unsigned long data) -{ - struct ath_softc *sc = (void *)data; - struct ath_hw *ah = sc->ah; - - sc->stats.ast_per_cal++; - - DPRINTF(sc, ATH_DEBUG_CALIBRATE, "ath: channel %u/%x\n", - sc->curchan->chan, sc->curchan->val); - - if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { - /* - * Rfgain is out of bounds, reset the chip - * to load new gain values. - */ - sc->stats.ast_per_rfgain++; - DPRINTF(sc, ATH_DEBUG_RESET, "calibration, resetting\n"); - ath_reset(sc->hw); - } - if (ath5k_hw_phy_calibrate(ah, sc->curchan)) { - DPRINTF(sc, ATH_DEBUG_ANY, "ath: calibration of channel %u " - "failed\n", sc->curchan->chan); - sc->stats.ast_per_calfail++; - } - - mod_timer(&sc->calib_tim, round_jiffies(jiffies + - msecs_to_jiffies(ath_calinterval * 1000))); -} - -static void ath_led_off(unsigned long data) -{ - struct ath_softc *sc = (void *)data; - - if (sc->led_endblink) - sc->led_blinking = 0; - else { - sc->led_endblink = 1; - ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on); - mod_timer(&sc->led_tim, jiffies + sc->led_off); - } -} - -/* - * Blink the LED according to the specified on/off times. - */ -static void ath_led_blink(struct ath_softc *sc, unsigned int on, - unsigned int off) -{ - DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); - ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on); - sc->led_blinking = 1; - sc->led_endblink = 0; - sc->led_off = off; - mod_timer(&sc->led_tim, jiffies + on); -} - -static void ath_led_event(struct ath_softc *sc, int event) -{ - if (likely(!sc->led_soft)) - return; - if (unlikely(sc->led_blinking)) /* don't interrupt active blink */ - return; - switch (event) { - case ATH_LED_TX: - ath_led_blink(sc, sc->hwmap[sc->led_txrate].ledon, - sc->hwmap[sc->led_txrate].ledoff); - break; - case ATH_LED_RX: - ath_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon, - sc->hwmap[sc->led_rxrate].ledoff); - break; - } -} - -static irqreturn_t ath_intr(int irq, void *dev_id) -{ - struct ath_softc *sc = dev_id; - struct ath_hw *ah = sc->ah; - enum ath5k_int status; - unsigned int counter = 1000; - - if (unlikely(sc->invalid || !ath5k_hw_is_intr_pending(ah))) - return IRQ_NONE; - - do { - /* - * Figure out the reason(s) for the interrupt. Note - * that the hal returns a pseudo-ISR that may include - * bits we haven't explicitly enabled so we mask the - * value to insure we only process bits we requested. - */ - ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ - DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x/0x%x\n", __func__, - status, sc->imask); - status &= sc->imask; /* discard unasked for bits */ - if (unlikely(status & AR5K_INT_FATAL)) { - /* - * Fatal errors are unrecoverable. Typically - * these are caused by DMA errors. Unfortunately - * the exact reason is not (presently) returned - * by the hal. - */ - sc->stats.ast_hardware++; - tasklet_schedule(&sc->restq); - } else if (unlikely(status & AR5K_INT_RXORN)) { - sc->stats.ast_rxorn++; - tasklet_schedule(&sc->restq); - } else { - if (status & AR5K_INT_SWBA) { - /* - * Software beacon alert--time to send a beacon. - * Handle beacon transmission directly; deferring - * this is too slow to meet timing constraints - * under load. - */ - ath_beacon_send(sc); - } - if (status & AR5K_INT_RXEOL) { - /* - * NB: the hardware should re-read the link when - * RXE bit is written, but it doesn't work at - * least on older hardware revs. - */ - sc->stats.ast_rxeol++; - sc->rxlink = NULL; - } - if (status & AR5K_INT_TXURN) { - sc->stats.ast_txurn++; - /* bump tx trigger level */ - ath5k_hw_update_tx_triglevel(ah, true); - } - if (status & AR5K_INT_RX) - tasklet_schedule(&sc->rxtq); - if (status & AR5K_INT_TX) - tasklet_schedule(&sc->txtq); - if (status & AR5K_INT_BMISS) { - sc->stats.ast_bmiss++; -/* tasklet_schedule(&sc->bmisstq);*/ - } - if (status & AR5K_INT_MIB) { - sc->stats.ast_mib++; - /* TODO */ - } - } - } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); - - if (unlikely(!counter && net_ratelimit())) - printk(KERN_WARNING "ath: too many interrupts, giving up for " - "now\n"); - - return IRQ_HANDLED; -} - -/* - * Convert IEEE channel number to MHz frequency. - */ -static inline short ath_ieee2mhz(short chan) -{ - if (chan <= 14 || chan >= 27) - return ieee80211chan2mhz(chan); - else - return 2212 + chan * 20; -} - -static unsigned int ath_copy_rates(struct ieee80211_rate *rates, - const struct ath5k_rate_table *rt, unsigned int max) -{ - unsigned int i, count; - - if (rt == NULL) - return 0; - - for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) { - if (!rt->rates[i].valid) - continue; - rates->rate = rt->rates[i].rate_kbps / 100; - rates->val = rt->rates[i].rate_code; - rates->flags = rt->rates[i].modulation; - rates++; - count++; - max--; - } - - return count; -} - -static unsigned int ath_copy_channels(struct ath_hw *ah, - struct ieee80211_channel *channels, unsigned int mode, - unsigned int max) -{ - static const struct { unsigned int mode, mask, chan; } map[] = { - [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A }, - [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T }, - [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B }, - [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G }, - [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG }, - }; - static const struct ath5k_regchannel chans_2ghz[] = - IEEE80211_CHANNELS_2GHZ; - static const struct ath5k_regchannel chans_5ghz[] = - IEEE80211_CHANNELS_5GHZ; - const struct ath5k_regchannel *chans; - enum ath5k_regdom dmn; - unsigned int i, count, size, chfreq, all, f, ch; - - if (!test_bit(mode, ah->ah_modes)) - return 0; - - all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1; - - switch (mode) { - case MODE_IEEE80211A: - case MODE_ATHEROS_TURBO: - /* 1..220, but 2GHz frequencies are filtered by check_channel */ - size = all ? 220 : ARRAY_SIZE(chans_5ghz); - chans = chans_5ghz; - dmn = ath5k_regdom2flag(ah->ah_regdomain, - IEEE80211_CHANNELS_5GHZ_MIN); - chfreq = CHANNEL_5GHZ; - break; - case MODE_IEEE80211B: - case MODE_IEEE80211G: - case MODE_ATHEROS_TURBOG: - size = all ? 26 : ARRAY_SIZE(chans_2ghz); - chans = chans_2ghz; - dmn = ath5k_regdom2flag(ah->ah_regdomain, - IEEE80211_CHANNELS_2GHZ_MIN); - chfreq = CHANNEL_2GHZ; - break; - default: - printk(KERN_WARNING "bad mode, not copying channels\n"); - return 0; - } - - for (i = 0, count = 0; i < size && max > 0; i++) { - ch = all ? i + 1 : chans[i].chan; - f = ath_ieee2mhz(ch); - /* Check if channel is supported by the chipset */ - if (!ath5k_channel_ok(ah, f, chfreq)) - continue; - - /* Match regulation domain */ - if (!all && !(IEEE80211_DMN(chans[i].domain) & - IEEE80211_DMN(dmn))) - continue; - - if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode) - continue; - - /* Write channel and increment counter */ - channels->chan = ch; - channels->freq = f; - channels->val = map[mode].chan; - channels++; - count++; - max--; - } - - return count; -} - -#if ATH_DEBUG_MODES -static void ath_dump_modes(struct ieee80211_hw_mode *modes) -{ - unsigned int m, i; - - for (m = 0; m < NUM_IEEE80211_MODES; m++) { - printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m, - modes[m].num_channels, modes[m].num_rates); - printk(KERN_DEBUG " channels:\n"); - for (i = 0; i < modes[m].num_channels; i++) { - printk(KERN_DEBUG " %3d %d %.4x %.4x\n", - modes[m].channels[i].chan, - modes[m].channels[i].freq, - modes[m].channels[i].val, - modes[m].channels[i].flag); - } - printk(KERN_DEBUG " rates:\n"); - for (i = 0; i < modes[m].num_rates; i++) { - printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n", - modes[m].rates[i].rate, - modes[m].rates[i].val, - modes[m].rates[i].flags, - modes[m].rates[i].val2); - } - } -} -#else -static inline void ath_dump_modes(struct ieee80211_hw_mode *modes) {} -#endif - -static int ath_getchannels(struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hw *ah = sc->ah; - struct ieee80211_hw_mode *modes = sc->modes; - unsigned int i, max; - int ret; - enum { - A = MODE_IEEE80211A, - B = MODE_IEEE80211G, /* this is not a typo, but workaround */ - G = MODE_IEEE80211B, /* to prefer g over b */ - T = MODE_ATHEROS_TURBO, - TG = MODE_ATHEROS_TURBOG, - }; - - BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 5); - - ah->ah_country_code = countrycode; - - modes[A].mode = MODE_IEEE80211A; - modes[B].mode = MODE_IEEE80211B; - modes[G].mode = MODE_IEEE80211G; - - max = ARRAY_SIZE(sc->rates); - modes[A].rates = sc->rates; - max -= modes[A].num_rates = ath_copy_rates(modes[A].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211A), max); - modes[B].rates = &modes[A].rates[modes[A].num_rates]; - max -= modes[B].num_rates = ath_copy_rates(modes[B].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211B), max); - modes[G].rates = &modes[B].rates[modes[B].num_rates]; - max -= modes[G].num_rates = ath_copy_rates(modes[G].rates, - ath5k_hw_get_rate_table(ah, MODE_IEEE80211G), max); - - if (!max) - printk(KERN_WARNING "yet another rates found, but there is not " - "sufficient space to store them\n"); - - max = ARRAY_SIZE(sc->channels); - modes[A].channels = sc->channels; - max -= modes[A].num_channels = ath_copy_channels(ah, modes[A].channels, - MODE_IEEE80211A, max); - modes[B].channels = &modes[A].channels[modes[A].num_channels]; - max -= modes[B].num_channels = ath_copy_channels(ah, modes[B].channels, - MODE_IEEE80211B, max); - modes[G].channels = &modes[B].channels[modes[B].num_channels]; - max -= modes[G].num_channels = ath_copy_channels(ah, modes[G].channels, - MODE_IEEE80211G, max); - - if (!max) - printk(KERN_WARNING "yet another modes found, but there is not " - "sufficient space to store them\n"); - - for (i = 0; i < ARRAY_SIZE(sc->modes); i++) - if (modes[i].num_channels) { - ret = ieee80211_register_hwmode(hw, &modes[i]); - if (ret) { - printk(KERN_ERR "can't register hwmode %u\n",i); - goto err; - } - } - ath_dump_modes(modes); - - return 0; -err: - return ret; -} - -static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) -{ - struct ath_desc *ds; - struct ath_buf *bf; - dma_addr_t da; - unsigned int i; - int ret; - - /* allocate descriptors */ - sc->desc_len = sizeof(struct ath_desc) * - (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); - sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); - if (sc->desc == NULL) { - dev_err(&pdev->dev, "can't allocate descriptors\n"); - ret = -ENOMEM; - goto err; - } - ds = sc->desc; - da = sc->desc_daddr; - DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", - __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); - - bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, - sizeof(struct ath_buf), GFP_KERNEL); - if (bf == NULL) { - dev_err(&pdev->dev, "can't allocate bufptr\n"); - ret = -ENOMEM; - goto err_free; - } - sc->bufptr = bf; - - INIT_LIST_HEAD(&sc->rxbuf); - for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { - bf->desc = ds; - bf->daddr = da; - list_add_tail(&bf->list, &sc->rxbuf); - } - - INIT_LIST_HEAD(&sc->txbuf); - sc->txbuf_len = ATH_TXBUF; - for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC, - da += ATH_TXDESC * sizeof(*ds)) { - bf->desc = ds; - bf->daddr = da; - list_add_tail(&bf->list, &sc->txbuf); - } - - /* beacon buffer */ - bf->desc = ds; - bf->daddr = da; - sc->bbuf = bf; - - return 0; -err_free: - pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); -err: - sc->desc = NULL; - return ret; -} - -static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) -{ - struct ath_buf *bf; - - ath_cleanup_txbuf(sc, sc->bbuf); - list_for_each_entry(bf, &sc->txbuf, list) - ath_cleanup_txbuf(sc, bf); - list_for_each_entry(bf, &sc->rxbuf, list) - ath_cleanup_txbuf(sc, bf); - - /* Free memory associated with all descriptors */ - pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); - - kfree(sc->bufptr); - sc->bufptr = NULL; -} - -static int ath_beaconq_setup(struct ath_hw *ah) -{ - struct ath5k_txq_info qi = { - .tqi_aifs = AR5K_TXQ_USEDEFAULT, - .tqi_cw_min = AR5K_TXQ_USEDEFAULT, - .tqi_cw_max = AR5K_TXQ_USEDEFAULT, - /* NB: for dynamic turbo, don't enable any other interrupts */ - .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE - }; - - return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); -} - -static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, - int subtype) -{ - struct ath_hw *ah = sc->ah; - struct ath_txq *txq; - struct ath5k_txq_info qi = { - .tqi_subtype = subtype, - .tqi_aifs = AR5K_TXQ_USEDEFAULT, - .tqi_cw_min = AR5K_TXQ_USEDEFAULT, - .tqi_cw_max = AR5K_TXQ_USEDEFAULT - }; - int qnum; - - /* - * Enable interrupts only for EOL and DESC conditions. - * We mark tx descriptors to receive a DESC interrupt - * when a tx queue gets deep; otherwise waiting for the - * EOL to reap descriptors. Note that this is done to - * reduce interrupt load and this only defers reaping - * descriptors, never transmitting frames. Aside from - * reducing interrupts this also permits more concurrency. - * The only potential downside is if the tx queue backs - * up in which case the top half of the kernel may backup - * due to a lack of tx descriptors. - */ - qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | - AR5K_TXQ_FLAG_TXDESCINT_ENABLE; - qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); - if (qnum < 0) { - /* - * NB: don't print a message, this happens - * normally on parts with too few tx queues - */ - return ERR_PTR(qnum); - } - if (qnum >= ARRAY_SIZE(sc->txqs)) { - printk(KERN_ERR "hal qnum %u out of range, max %u!\n", - qnum, ARRAY_SIZE(sc->txqs)); - ath5k_hw_release_tx_queue(ah, qnum); - return ERR_PTR(-EINVAL); - } - txq = &sc->txqs[qnum]; - if (!txq->setup) { - txq->qnum = qnum; - txq->link = NULL; - INIT_LIST_HEAD(&txq->q); - spin_lock_init(&txq->lock); - txq->setup = true; - } - return &sc->txqs[qnum]; -} - -static void ath_tx_cleanup(struct ath_softc *sc) -{ - struct ath_txq *txq = sc->txqs; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) - if (txq->setup) { - ath5k_hw_release_tx_queue(sc->ah, txq->qnum); - txq->setup = false; - } -} - -static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - struct ath_hw *ah = sc->ah; - u8 mac[ETH_ALEN]; - unsigned int i; - int ret; - - DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); - - /* - * Check if the MAC has multi-rate retry support. - * We do this by trying to setup a fake extended - * descriptor. MAC's that don't have support will - * return false w/o doing anything. MAC's that do - * support it will return true w/o doing anything. - */ - sc->mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); - - /* - * Reset the key cache since some parts do not - * reset the contents on initial power up. - */ - for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) - ath5k_hw_reset_key(ah, i); - - /* - * Collect the channel list using the default country - * code and including outdoor channels. The 802.11 layer - * is resposible for filtering this list based on settings - * like the phy mode. - */ - ret = ath_getchannels(hw); - if (ret) { - dev_err(&pdev->dev, "can't get channels\n"); - goto err; - } - - /* NB: setup here so ath_rate_update is happy */ - if (test_bit(MODE_IEEE80211A, ah->ah_modes)) - ath_setcurmode(sc, MODE_IEEE80211A); - else - ath_setcurmode(sc, MODE_IEEE80211B); - - /* - * Allocate tx+rx descriptors and populate the lists. - */ - ret = ath_desc_alloc(sc, pdev); - if (ret) { - dev_err(&pdev->dev, "can't allocate descriptors\n"); - goto err; - } - - /* - * Allocate hardware transmit queues: one queue for - * beacon frames and one data queue for each QoS - * priority. Note that the hal handles reseting - * these queues at the needed time. - */ - ret = ath_beaconq_setup(ah); - if (ret < 0) { - dev_err(&pdev->dev, "can't setup a beacon xmit queue\n"); - goto err_desc; - } - sc->bhalq = ret; - - sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); - if (IS_ERR(sc->txq)) { - dev_err(&pdev->dev, "can't setup xmit queue\n"); - ret = PTR_ERR(sc->txq); - goto err_bhal; - } - - tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); - tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); - tasklet_init(&sc->restq, ath_tasklet_reset, (unsigned long)sc); - setup_timer(&sc->calib_tim, ath_calibrate, (unsigned long)sc); - setup_timer(&sc->led_tim, ath_led_off, (unsigned long)sc); - - sc->led_blinking = 0; - sc->led_on = 0; /* low true */ - /* - * Auto-enable soft led processing for IBM cards and for - * 5211 minipci cards. Users can also manually enable/disable - * support with a sysctl. - */ - if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || - pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) { - sc->led_soft = 1; - sc->led_pin = 0; - } - /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */ - if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) { - sc->led_soft = 1; - sc->led_pin = 0; - } - if (sc->led_soft) { - ath5k_hw_set_gpio_output(ah, sc->led_pin); - ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); - } - - ath5k_hw_get_lladdr(ah, mac); - SET_IEEE80211_PERM_ADDR(hw, mac); - if (ath5k_hw_hasbssidmask(ah)) { - memset(sc->bssidmask, 0xff, ETH_ALEN); - ath5k_hw_set_bssid_mask(ah, sc->bssidmask); - } - - ret = ieee80211_register_hw(hw); - if (ret) { - dev_err(&pdev->dev, "can't register ieee80211 hw\n"); - goto err_queues; - } - - return 0; -err_queues: - ath_tx_cleanup(sc); -err_bhal: - ath5k_hw_release_tx_queue(ah, sc->bhalq); -err_desc: - ath_desc_free(sc, pdev); -err: - return ret; -} - -static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) -{ - struct ath_softc *sc = hw->priv; - - /* - * NB: the order of these is important: - * o call the 802.11 layer before detaching the hal to - * insure callbacks into the driver to delete global - * key cache entries can be handled - * o reclaim the tx queue data structures after calling - * the 802.11 layer as we'll get called back to reclaim - * node state and potentially want to use them - * o to cleanup the tx queues the hal is called, so detach - * it last - * Other than that, it's straightforward... - */ - ieee80211_unregister_hw(hw); - ath_desc_free(sc, pdev); - ath_tx_cleanup(sc); - ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); - - /* - * NB: can't reclaim these until after ieee80211_ifdetach - * returns because we'll get called back to reclaim node - * state and potentially want to use them. - */ -// ath_dynamic_sysctl_unregister(sc); -} - -static const char *ath_chip_name(u8 mac_version) -{ - switch (mac_version) { - case AR5K_AR5210: - return "AR5210"; - case AR5K_AR5211: - return "AR5211"; - case AR5K_AR5212: - return "AR5212"; - } - return "Unknown"; -} - -static int __devinit ath_pci_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - void __iomem *mem; - struct ath_softc *sc; - struct ieee80211_hw *hw; - int ret; - u8 csz; - - ret = pci_enable_device(pdev); - if (ret) { - dev_err(&pdev->dev, "can't enable device\n"); - goto err; - } - - /* XXX 32-bit addressing only */ - ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); - if (ret) { - dev_err(&pdev->dev, "32-bit DMA not available\n"); - goto err_dis; - } - - /* - * Cache line size is used to size and align various - * structures used to communicate with the hardware. - */ - pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); - if (csz == 0) { - /* - * Linux 2.4.18 (at least) writes the cache line size - * register as a 16-bit wide register which is wrong. - * We must have this setup properly for rx buffer - * DMA to work so force a reasonable value here if it - * comes up zero. - */ - csz = L1_CACHE_BYTES / sizeof(u32); - pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); - } - /* - * The default setting of latency timer yields poor results, - * set it to the value used by other systems. It may be worth - * tweaking this setting more. - */ - pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); - - pci_set_master(pdev); - - /* - * Disable the RETRY_TIMEOUT register (0x41) to keep - * PCI Tx retries from interfering with C3 CPU state. - */ - pci_write_config_byte(pdev, 0x41, 0); - - ret = pci_request_region(pdev, 0, "ath"); - if (ret) { - dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); - goto err_dis; - } - - mem = pci_iomap(pdev, 0, 0); - if (!mem) { - dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; - ret = -EIO; - goto err_reg; - } - - hw = ieee80211_alloc_hw(sizeof(*sc), &ath_hw_ops); - if (hw == NULL) { - dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); - ret = -ENOMEM; - goto err_map; - } - - SET_IEEE80211_DEV(hw, &pdev->dev); - hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_WEP_INCLUDE_IV | - IEEE80211_HW_DATA_NULLFUNC_ACK; - hw->extra_tx_headroom = 2; - hw->channel_change_time = 5000; - hw->max_rssi = 127; /* FIXME: get a real value for this. */ - sc = hw->priv; - sc->hw = hw; - - /* - * Mark the device as detached to avoid processing - * interrupts until setup is complete. - */ -#if AR_DEBUG - sc->debug = ath_debug; -#endif - sc->invalid = 1; - sc->iobase = mem; - sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ - sc->opmode = IEEE80211_IF_TYPE_STA; - mutex_init(&sc->lock); - spin_lock_init(&sc->rxbuflock); - spin_lock_init(&sc->txbuflock); - - pci_set_drvdata(pdev, hw); - - ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc); - if (ret) { - dev_err(&pdev->dev, "request_irq failed\n"); - goto err_free; - } - - sc->ah = ath5k_hw_attach(pdev->device, id->driver_data, sc, sc->iobase); - if (IS_ERR(sc->ah)) { - ret = PTR_ERR(sc->ah); - goto err_irq; - } - - ret = ath_attach(pdev, hw); - if (ret) - goto err_ah; - - dev_info(&pdev->dev, "%s chip found: mac %d.%d phy %d.%d\n", - ath_chip_name(id->driver_data), sc->ah->ah_mac_version, - sc->ah->ah_mac_version, sc->ah->ah_phy_revision >> 4, - sc->ah->ah_phy_revision & 0xf); - - /* ready to process interrupts */ - sc->invalid = 0; - - return 0; -err_ah: - ath5k_hw_detach(sc->ah); -err_irq: - free_irq(pdev->irq, sc); -err_free: - ieee80211_free_hw(hw); -err_map: - pci_iounmap(pdev, mem); -err_reg: - pci_release_region(pdev, 0); -err_dis: - pci_disable_device(pdev); -err: - return ret; -} - -static void __devexit ath_pci_remove(struct pci_dev *pdev) -{ - struct ieee80211_hw *hw = pci_get_drvdata(pdev); - struct ath_softc *sc = hw->priv; - - ath_detach(pdev, hw); - ath5k_hw_detach(sc->ah); - free_irq(pdev->irq, sc); - pci_iounmap(pdev, sc->iobase); - pci_release_region(pdev, 0); - pci_disable_device(pdev); - ieee80211_free_hw(hw); -} - -#ifdef CONFIG_PM -static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) -{ - struct ieee80211_hw *hw = pci_get_drvdata(pdev); - struct ath_softc *sc = hw->priv; - - if (sc->led_soft) - ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); - - ath_stop_hw(sc); - pci_save_state(pdev); - pci_disable_device(pdev); - pci_set_power_state(pdev, PCI_D3hot); - - return 0; -} - -static int ath_pci_resume(struct pci_dev *pdev) -{ - struct ieee80211_hw *hw = pci_get_drvdata(pdev); - struct ath_softc *sc = hw->priv; - int err; - - err = pci_set_power_state(pdev, PCI_D0); - if (err) - return err; - - err = pci_enable_device(pdev); - if (err) - return err; - - pci_restore_state(pdev); - /* - * Suspend/Resume resets the PCI configuration space, so we have to - * re-disable the RETRY_TIMEOUT register (0x41) to keep - * PCI Tx retries from interfering with C3 CPU state - */ - pci_write_config_byte(pdev, 0x41, 0); - - ath_init(sc); - if (sc->led_soft) { - ath5k_hw_set_gpio_output(sc->ah, sc->led_pin); - ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0); - } - - return 0; -} -#else -#define ath_pci_suspend NULL -#define ath_pci_resume NULL -#endif /* CONFIG_PM */ - -static struct pci_driver ath_pci_drv_id = { - .name = "ath_pci", - .id_table = ath_pci_id_table, - .probe = ath_pci_probe, - .remove = __devexit_p(ath_pci_remove), - .suspend = ath_pci_suspend, - .resume = ath_pci_resume, -}; - -/* - * Static (i.e. global) sysctls. Note that the hal sysctls - * are located under ours by sharing the setting for DEV_ATH. - */ -enum { - DEV_ATH = 9, /* XXX known by hal */ -}; - -static int mincalibrate = 1; -static int maxint = 0x7ffffff / 1000; -#define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ - -static ctl_table ath_static_sysctls[] = { -#if AR_DEBUG - { .ctl_name = CTL_AUTO, - .procname = "debug", - .mode = 0644, - .data = &ath_debug, - .maxlen = sizeof(ath_debug), - .proc_handler = proc_dointvec - }, -#endif - { .ctl_name = CTL_AUTO, - .procname = "countrycode", - .mode = 0444, - .data = &countrycode, - .maxlen = sizeof(countrycode), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "outdoor", - .mode = 0444, - .data = &outdoor, - .maxlen = sizeof(outdoor), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "xchanmode", - .mode = 0444, - .data = &xchanmode, - .maxlen = sizeof(xchanmode), - .proc_handler = proc_dointvec - }, - { .ctl_name = CTL_AUTO, - .procname = "calibrate", - .mode = 0644, - .data = &ath_calinterval, - .maxlen = sizeof(ath_calinterval), - .extra1 = &mincalibrate, - .extra2 = &maxint, - .proc_handler = proc_dointvec_minmax - }, - { 0 } -}; -static ctl_table ath_ath_table[] = { - { .ctl_name = DEV_ATH, - .procname = "ath", - .mode = 0555, - .child = ath_static_sysctls - }, { 0 } -}; -static ctl_table ath_root_table[] = { - { .ctl_name = CTL_DEV, - .procname = "dev", - .mode = 0555, - .child = ath_ath_table - }, { 0 } -}; -static struct ctl_table_header *ath_sysctl_header; - -static int __init init_ath_pci(void) -{ - int ret; - - ret = pci_register_driver(&ath_pci_drv_id); - if (ret) { - printk(KERN_ERR "ath_pci: can't register pci driver\n"); - return ret; - } - ath_sysctl_header = register_sysctl_table(ath_root_table); - - return 0; -} - -static void __exit exit_ath_pci(void) -{ - if (ath_sysctl_header) - unregister_sysctl_table(ath_sysctl_header); - pci_unregister_driver(&ath_pci_drv_id); -} - -module_init(init_ath_pci); -module_exit(exit_ath_pci); - -MODULE_AUTHOR("Jiri Slaby"); -MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); -MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); -MODULE_LICENSE("Dual BSD/GPL"); -MODULE_VERSION(ATH_PCI_VERSION " (EXPERIMENTAL)"); diff --git a/ath.h b/ath.h deleted file mode 100644 index 26a8126..0000000 --- a/ath.h +++ /dev/null @@ -1,301 +0,0 @@ -/*- - * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * 3. Neither the names of the above-listed copyright holders nor the names - * of any contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.20 2005/01/24 20:31:24 sam Exp $ - */ - -/* - * Defintions for the Atheros Wireless LAN controller driver. - */ -#ifndef _DEV_ATH_ATHVAR_H -#define _DEV_ATH_ATHVAR_H - -#include -#include -#include -#include - -#include "ath5k_hw.h" - -/* Set this to 1 to disable regulatory domain restrictions for channel tests. - * WARNING: This is for debuging only and has side effects (eg. scan takes too - * long and results timeouts). It's also illegal to tune to some of the - * supported frequencies in some countries, so use this at your own risk, - * you've been warned. */ -#define CHAN_DEBUG 0 - -#define ATH_TIMEOUT 1000 - -#define ATH_LONG_CALIB 30 /* seconds */ -#define ATH_SHORT_CALIB 1 - -/* - * Maximum acceptable MTU - * MAXFRAMEBODY - WEP - QOS - RSN/WPA: - * 2312 - 8 - 2 - 12 = 2290 - */ -#define ATH_MAX_MTU 2290 -#define ATH_MIN_MTU 32 - -#define ATH_RXBUF 40 /* number of RX buffers */ -#define ATH_TXBUF 200 /* number of TX buffers */ -#define ATH_TXDESC 1 /* number of descriptors per buffer */ -#define ATH_BCBUF 1 /* number of beacon buffers */ -#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ -#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ - -#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ -#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ -#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ - -#define ATH_RSSI_LPF_LEN 10 -#define ATH_RSSI_DUMMY_MARKER 0x127 -#define ATH_EP_MUL(x, mul) ((x) * (mul)) -#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), AR5K_RSSI_EP_MULTIPLIER)) -#define ATH_LPF_RSSI(x, y, len) \ - ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) -#define ATH_RSSI_LPF(x, y) do { \ - if ((y) >= -20) \ - x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ -} while (0) - -struct ath_buf { - struct list_head list; - unsigned int flags; /* tx descriptor flags */ - struct ath_desc *desc; /* virtual addr of desc */ - dma_addr_t daddr; /* physical addr of desc */ - struct sk_buff *skb; /* skbuff for buf */ - dma_addr_t skbaddr;/* physical addr of skb data */ - struct ieee80211_tx_control ctl; -}; - -/* - * Data transmit queue state. One of these exists for each - * hardware transmit queue. Packets sent to us from above - * are assigned to queues based on their priority. Not all - * devices support a complete set of hardware transmit queues. - * For those devices the array sc_ac2q will map multiple - * priorities to fewer hardware queues (typically all to one - * hardware queue). - */ -struct ath_txq { - unsigned int qnum; /* hardware q number */ - u32 *link; /* link ptr in last TX desc */ - struct list_head q; /* transmit queue */ - spinlock_t lock; /* lock on q and link */ - bool setup; -}; - -struct ath_stats { - __u32 ast_watchdog; /* device reset by watchdog */ - __u32 ast_hardware; /* fatal hardware error interrupts */ - __u32 ast_bmiss; /* beacon miss interrupts */ - __u32 ast_bstuck; /* beacon stuck interrupts */ - __u32 ast_rxorn; /* rx overrun interrupts */ - __u32 ast_rxeol; /* rx eol interrupts */ - __u32 ast_txurn; /* tx underrun interrupts */ - __u32 ast_mib; /* mib interrupts */ - __u32 ast_intrcoal; /* interrupts coalesced */ - __u32 ast_tx_packets; /* packet sent on the interface */ - __u32 ast_tx_mgmt; /* management frames transmitted */ - __u32 ast_tx_discard; /* frames discarded prior to assoc */ - __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ - __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ - __u32 ast_tx_encap; /* tx encapsulation failed */ - __u32 ast_tx_nonode; /* tx failed 'cuz no node */ - __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ - __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ - __u32 ast_tx_linear; /* tx linearized to cluster */ - __u32 ast_tx_nodata; /* tx discarded empty frame */ - __u32 ast_tx_busdma; /* tx failed for dma resrcs */ - __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ - __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ - __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ - __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ - __u32 ast_tx_longretry;/* tx on-chip retries (long) */ - __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ - __u32 ast_tx_noack; /* tx frames with no ack marked */ - __u32 ast_tx_rts; /* tx frames with rts enabled */ - __u32 ast_tx_cts; /* tx frames with cts enabled */ - __u32 ast_tx_shortpre;/* tx frames with short preamble */ - __u32 ast_tx_altrate; /* tx frames with alternate rate */ - __u32 ast_tx_protect; /* tx frames with protection */ - __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ - __u32 ast_tx_ctsext; /* tx frames with cts extension */ - __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ - __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ - __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ - __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ - __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ - __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ - __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ - __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ - __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ - __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ - __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ - __u32 ast_rx_packets; /* packet recv on the interface */ - __u32 ast_rx_mgt; /* management frames received */ - __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ - __s8 ast_tx_rssi; /* tx rssi of last ack */ - __s8 ast_rx_rssi; /* rx rssi from histogram */ - __u32 ast_be_xmit; /* beacons transmitted */ - __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ - __u32 ast_per_cal; /* periodic calibration calls */ - __u32 ast_per_calfail;/* periodic calibration failed */ - __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ - __u32 ast_rate_calls; /* rate control checks */ - __u32 ast_rate_raise; /* rate control raised xmit rate */ - __u32 ast_rate_drop; /* rate control dropped xmit rate */ - __u32 ast_ant_defswitch;/* rx/default antenna switches */ - __u32 ast_ant_txswitch;/* tx antenna switches */ - __u32 ast_ant_rx[8]; /* rx frames with antenna */ - __u32 ast_ant_tx[8]; /* tx frames with antenna */ -}; - -#if CHAN_DEBUG -#define ATH_CHAN_MAX (26+26+26+200+200) -#else -#define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */ -#endif - -struct ath_softc { - struct pci_dev *pdev; /* for dma mapping */ - void __iomem *iobase; /* address of the device */ - struct mutex lock; /* dev-level lock */ - struct ath_stats stats; /* private statistics */ - struct ieee80211_tx_queue_stats tx_stats; - struct ieee80211_low_level_stats ll_stats; - struct ieee80211_hw *hw; /* IEEE 802.11 common */ - struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; - struct ieee80211_channel channels[ATH_CHAN_MAX]; - struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_IEEE80211_MODES]; - enum ieee80211_if_types opmode; - struct ath_hw *ah; /* Atheros HW */ - - int debug; - - struct ath_buf *bufptr; /* allocated buffer ptr */ - struct ath_desc *desc; /* TX/RX descriptors */ - dma_addr_t desc_daddr; /* DMA (physical) address */ - size_t desc_len; /* size of TX/RX descriptors */ - u16 cachelsz; /* cache line size */ -#ifdef UNUSED - void (*sc_setdefantenna)(struct ath_softc *, u_int); -#endif - unsigned int invalid : 1, /* disable hardware accesses */ - mrretry : 1, /* multi-rate retry support */ - promisc : 1; -#ifdef UNUSED - sc_diversity : 1,/* enable rx diversity */ - sc_hasveol : 1, /* tx VEOL support */ - sc_mcastkey: 1, /* mcast key cache search */ - sc_hasclrkey:1; /* CLR key supported */ - /* rate tables */ -#endif - unsigned int curmode; /* current phy mode */ - struct ieee80211_channel *curchan; /* current h/w channel */ - - int iface_id; /* add/remove_interface id */ - - struct { - u8 rxflags; /* radiotap rx flags */ - u8 txflags; /* radiotap tx flags */ - u16 ledon; /* softled on time */ - u16 ledoff; /* softled off time */ - } hwmap[32]; /* h/w rate ix mappings */ -#ifdef UNUSED - u8 sc_protrix; /* protection rate index */ - u_int sc_txantenna; /* tx antenna (fixed or auto) */ -#endif - enum ath5k_int imask; /* interrupt mask copy */ - - DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ - - u8 bssidmask[ETH_ALEN]; - - unsigned int led_pin, /* GPIO pin for driving LED */ - led_on, /* pin setting for LED on */ - led_off, /* off time for current blink */ - led_blinking: 1,/* LED blink operation active */ - led_endblink: 1,/* finish LED blink operation */ - led_soft: 1; /* enable LED gpio status */ - struct timer_list led_tim; /* led off timer */ - u8 led_rxrate; /* current rx rate for LED */ - u8 led_txrate; /* current tx rate for LED */ - - struct tasklet_struct restq; /* reset tasklet */ - - unsigned int rxbufsize; /* rx size based on mtu */ - struct list_head rxbuf; /* receive buffer */ - spinlock_t rxbuflock; - u32 *rxlink; /* link ptr in last RX desc */ - struct tasklet_struct rxtq; /* rx intr tasklet */ -#ifdef UNUSED - u8 sc_defant; /* current default antenna */ - u8 sc_rxotherant; /* rx's on non-default antenna*/ -#endif - struct list_head txbuf; /* transmit buffer */ - spinlock_t txbuflock; - unsigned int txbuf_len; /* buf count in txbuf list */ - struct ath_txq txqs[2]; /* beacon and tx */ -#ifdef UNUSED - struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ -#endif - struct ath_txq *txq; /* beacon and tx*/ - struct tasklet_struct txtq; /* tx intr tasklet */ - - struct ath_buf *bbuf; /* beacon buffer */ - unsigned int bhalq, /* HAL q for outgoing beacons */ - bmisscount, /* missed beacon transmits */ - bintval; /* beacon interval */ -#ifdef BEACON - u32 sc_ant_tx[8]; /* recent tx frames/antenna */ - struct ath_txq *cabq; /* tx q for cab frames */ - - struct tasklet_struct bmisstq; /* bmiss intr tasklet */ -#endif -#ifdef UNUSED - struct ctl_table_header *sc_sysctl_header; - struct ctl_table *sc_sysctls; -#endif - struct timer_list calib_tim; /* calibration timer */ -}; - -#define ath5k_hw_hasbssidmask(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) -#define ath5k_hw_hasveol(_ah) \ - (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) - -#endif diff --git a/ath5k_base.c b/ath5k_base.c new file mode 100644 index 0000000..10aa888 --- /dev/null +++ b/ath5k_base.c @@ -0,0 +1,2567 @@ +/*- + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2004-2005 Atheros Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + */ +#define ATH_PCI_VERSION "0.9.5.0-BSD" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "ath5k_base.h" +#include "ath5k_reg.h" + +#define ATH_DEBUG_MODES 0 /* Show found modes in the log? */ +#define ATH_DUMP_SKB 0 /* show skb contents */ +#define AR_DEBUG 1 + +/* unaligned little endian access */ +#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) +#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) + +#if AR_DEBUG +#define DPRINTF(sc, _m, _fmt...) do { \ + if (unlikely(((sc)->debug & (_m)) && net_ratelimit())) \ + printk(KERN_DEBUG _fmt); \ +} while (0) +#else +static inline int __attribute__ ((format (printf, 3, 4))) +DPRINTF(struct ath_softc *sc, unsigned int m, const char *fmt, ...) +{ + return 0; +} +#endif +enum { + ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ + ATH_DEBUG_RESET = 0x00000020, /* reset processing */ + ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ + ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ + ATH_DEBUG_INTR = 0x00001000, /* ISR */ + ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ + ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ + ATH_DEBUG_LED = 0x00100000, /* led management */ + ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ + ATH_DEBUG_ANY = 0xffffffff +}; + +enum { + ATH_LED_TX, + ATH_LED_RX, +}; + +static int ath_calinterval = ATH_SHORT_CALIB; + +static int countrycode = CTRY_DEFAULT; +static int outdoor = true; +static int xchanmode = true; +module_param(countrycode, int, 0); +MODULE_PARM_DESC(countrycode, "Override default country code"); +module_param(outdoor, int, 0); +MODULE_PARM_DESC(outdoor, "Enable/disable outdoor use"); +module_param(xchanmode, int, 0); +MODULE_PARM_DESC(xchanmode, "Enable/disable extended channel mode"); + +#if AR_DEBUG +static unsigned int ath_debug; +module_param_named(debug, ath_debug, uint, 0); +#endif + +/* + * User a static table of PCI id's for now. While this is the + * "new way" to do things, we may want to switch back to having + * the HAL check them by defining a probe method. + */ +static struct pci_device_id ath_pci_id_table[] __devinitdata = { + { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */ + { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */ + { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 */ + { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */ + { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */ + { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */ + { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */ + { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */ + { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, + { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ + { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ + { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ + { 0 } +}; +MODULE_DEVICE_TABLE(pci, ath_pci_id_table); + +static void ath_led_event(struct ath_softc *, int); +static int ath_reset(struct ieee80211_hw *); + +#if AR_DEBUG +static void ath_printrxbuf(struct ath_buf *bf, int done) +{ + struct ath_desc *ds = bf->desc; + + printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", + ds, (unsigned long long)bf->daddr, + ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], + !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); +} + +static void ath_printtxbuf(struct ath_buf *bf, int done) +{ + struct ath_desc *ds = bf->desc; + + printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x " + "%08x %c\n", + ds, (unsigned long long)bf->daddr, + ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], + !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); +} +#endif + +#if ATH_DUMP_SKB +static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) +{ + print_hex_dump_bytes(prefix, DUMP_PREFIX_NONE, skb->data, + min(200U, skb->len)); +} +#else +static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) {} +#endif + +static inline void ath_cleanup_txbuf(struct ath_softc *sc, struct ath_buf *bf) +{ + BUG_ON(!bf); + if (!bf->skb) + return; + pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, + PCI_DMA_TODEVICE); + dev_kfree_skb(bf->skb); + bf->skb = NULL; +} + +static void ath_tasklet_reset(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + ath_reset(sc->hw); +} + +static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) +{ + struct ieee80211_tx_status txs = {}; + struct ath_buf *bf, *bf0; + struct ath_desc *ds; + struct sk_buff *skb; + int ret; + + spin_lock(&txq->lock); + list_for_each_entry_safe(bf, bf0, &txq->q, list) { + ds = bf->desc; + + /* TODO only one segment */ + pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, + sc->desc_len, PCI_DMA_FROMDEVICE); + ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); + if (unlikely(ret == -EINPROGRESS)) + break; + else if (unlikely(ret)) { + printk(KERN_ERR "ath: error %d while processing " + "queue %u\n", ret, txq->qnum); + break; + } + + skb = bf->skb; + bf->skb = NULL; + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, + PCI_DMA_TODEVICE); + + txs.control = bf->ctl; + txs.retry_count = ds->ds_txstat.ts_shortretry + + ds->ds_txstat.ts_longretry / 6; + if (unlikely(ds->ds_txstat.ts_status)) { + sc->ll_stats.dot11ACKFailureCount++; + if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { + txs.excessive_retries = 1; + } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { + txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; + } + } else { + txs.flags |= IEEE80211_TX_STATUS_ACK; + txs.ack_signal = ds->ds_txstat.ts_rssi; + } + + ieee80211_tx_status(sc->hw, skb, &txs); + sc->tx_stats.data[txq->qnum].count++; + +// printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); + + spin_lock(&sc->txbuflock); + sc->tx_stats.data[txq->qnum].len--; + list_move_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; + spin_unlock(&sc->txbuflock); + } + if (likely(list_empty(&txq->q))) + txq->link = NULL; + spin_unlock(&txq->lock); + if (sc->txbuf_len > ATH_TXBUF / 5) + ieee80211_wake_queues(sc->hw); +} + +static void ath_tasklet_tx(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + ath_tx_processq(sc, sc->txq); + + ath_led_event(sc, ATH_LED_TX); +} + +static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) +{ + struct ath_hw *ah = sc->ah; + struct sk_buff *skb = bf->skb; + struct ath_desc *ds; + + if (likely(skb == NULL)) { + unsigned int off; + + /* + * Allocate buffer with headroom_needed space for the + * fake physical layer header at the start. + */ + skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); + if (unlikely(skb == NULL)) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " + "size %u failed\n", __func__, + sc->rxbufsize + sc->cachelsz - 1); + sc->stats.ast_rx_nobuf++; + return -ENOMEM; + } + /* + * Cache-line-align. This is important (for the + * 5210 at least) as not doing so causes bogus data + * in rx'd frames. + */ + off = ((unsigned long)skb->data) % sc->cachelsz; + if (off != 0) + skb_reserve(skb, sc->cachelsz - off); + + bf->skb = skb; + bf->skbaddr = pci_map_single(sc->pdev, + skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); + if (unlikely(pci_dma_mapping_error(bf->skbaddr))) { + printk(KERN_ERR "%s: DMA mapping failed\n", __func__); + dev_kfree_skb(skb); + bf->skb = NULL; + sc->stats.ast_rx_busdma++; + return -ENOMEM; + } + } + + /* + * Setup descriptors. For receive we always terminate + * the descriptor list with a self-linked entry so we'll + * not get overrun under high load (as can happen with a + * 5212 when ANI processing enables PHY error frames). + * + * To insure the last descriptor is self-linked we create + * each descriptor as self-linked and add it to the end. As + * each additional descriptor is added the previous self-linked + * entry is ``fixed'' naturally. This should be safe even + * if DMA is happening. When processing RX interrupts we + * never remove/process the last, self-linked, entry on the + * descriptor list. This insures the hardware always has + * someplace to write a new frame. + */ + ds = bf->desc; + ds->ds_link = bf->daddr; /* link to self */ + ds->ds_data = bf->skbaddr; + ath5k_hw_setup_rx_desc(ah, ds, + skb_tailroom(skb), /* buffer size */ + 0); + + if (sc->rxlink != NULL) + *sc->rxlink = bf->daddr; + sc->rxlink = &ds->ds_link; + return 0; +} + +static unsigned int ath_rx_decrypted(struct ath_softc *sc, + struct ath_desc *ds, struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (void *)skb->data; + unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); + + if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && + ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID) + return RX_FLAG_DECRYPTED; + + /* Apparently when a default key is used to decrypt the packet + the hal does not set the index used to decrypt. In such cases + get the index from the packet. */ + if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && + !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && + skb->len >= hlen + 4) { + keyix = skb->data[hlen + 3] >> 6; + + if (test_bit(keyix, sc->keymap)) + return RX_FLAG_DECRYPTED; + } + + return 0; +} + +static inline u64 ath_extend_tsf(struct ath_hw *ah, u32 rstamp) +{ + u64 tsf = ath5k_hw_get_tsf64(ah); + + if ((tsf & 0x7fff) < rstamp) + tsf -= 0x8000; + + return (tsf &~ 0x7fff) | rstamp; +} + +static void ath_tasklet_rx(unsigned long data) +{ + struct ieee80211_rx_status rxs = {}; + struct sk_buff *skb; + struct ath_softc *sc = (void *)data; + struct ath_buf *bf; + struct ath_desc *ds; + u16 len; + u8 stat; + int ret; + + spin_lock(&sc->rxbuflock); + do { + if (unlikely(list_empty(&sc->rxbuf))) { + if (net_ratelimit()) + printk(KERN_WARNING "ath: empty rx buf pool\n"); + break; + } + bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); + BUG_ON(bf->skb == NULL); + skb = bf->skb; + ds = bf->desc; + + /* TODO only one segment */ + pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, + sc->desc_len, PCI_DMA_FROMDEVICE); + + if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */ + break; + + ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); + if (unlikely(ret == -EINPROGRESS)) + break; + else if (unlikely(ret)) { + if (net_ratelimit()) + printk(KERN_ERR "ath: error in processing rx " + "descriptor\n"); + return; + } + + if (unlikely(ds->ds_rxstat.rs_more)) { + if (net_ratelimit()) + printk(KERN_INFO "ath: unsupported jumbo\n"); + goto next; + } + + stat = ds->ds_rxstat.rs_status; + if (unlikely(stat)) { + if (stat & AR5K_RXERR_CRC) + sc->stats.ast_rx_crcerr++; + if (stat & AR5K_RXERR_FIFO) + sc->stats.ast_rx_fifoerr++; + if (stat & AR5K_RXERR_PHY) { + sc->stats.ast_rx_phyerr++; + sc->stats.ast_rx_phy + [ds->ds_rxstat.rs_phyerr & 0x1f]++; + goto next; + } + if (stat & AR5K_RXERR_DECRYPT) { + /* + * Decrypt error. If the error occurred + * because there was no hardware key, then + * let the frame through so the upper layers + * can process it. This is necessary for 5210 + * parts which have no way to setup a ``clear'' + * key cache entry. + * + * XXX do key cache faulting + */ + if (ds->ds_rxstat.rs_keyix == + AR5K_RXKEYIX_INVALID && + !(stat & AR5K_RXERR_CRC)) + goto accept; + sc->stats.ast_rx_badcrypt++; + } + if (stat & AR5K_RXERR_MIC) { + rxs.flag |= RX_FLAG_MMIC_ERROR; + sc->stats.ast_rx_badmic++; + goto accept; + } + + /* let crypto-error packets fall through in MNTR */ + if ((stat &~ (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || + sc->opmode != IEEE80211_IF_TYPE_MNTR) + goto next; + } +accept: + len = ds->ds_rxstat.rs_datalen; + pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len, + PCI_DMA_FROMDEVICE); + pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, + PCI_DMA_FROMDEVICE); + bf->skb = NULL; + + if (unlikely((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit())) + printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + + skb_put(skb, len); + + sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; + + if (sc->opmode == IEEE80211_IF_TYPE_MNTR) + rxs.mactime = ath_extend_tsf(sc->ah, + ds->ds_rxstat.rs_tstamp); + else + rxs.mactime = ds->ds_rxstat.rs_tstamp; + rxs.freq = sc->curchan->freq; + rxs.channel = sc->curchan->chan; + rxs.phymode = sc->curmode; + rxs.ssi = ds->ds_rxstat.rs_rssi; + rxs.antenna = ds->ds_rxstat.rs_antenna; + rxs.rate = ds->ds_rxstat.rs_rate; + rxs.flag |= ath_rx_decrypted(sc, ds, skb); + +// printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); + ath_dump_skb(skb, "r"); + + __ieee80211_rx(sc->hw, skb, &rxs); + sc->led_rxrate = ds->ds_rxstat.rs_rate; + ath_led_event(sc, ATH_LED_RX); +next: + list_move_tail(&bf->list, &sc->rxbuf); + } while (ath_rxbuf_init(sc, bf) == 0); + spin_unlock(&sc->rxbuflock); +} + +/* + * Setup the beacon frame for transmit. + */ +static int ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, + struct ieee80211_tx_control *ctl) +{ + struct sk_buff *skb = bf->skb; + struct ath_hw *ah = sc->ah; + struct ath_desc *ds; + int ret, antenna = 0; + u32 flags; + + bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: skb %p [data %p len %u] " + "skbaddr %llx\n", __func__, skb, skb->data, skb->len, + (unsigned long long)bf->skbaddr); + if (pci_dma_mapping_error(bf->skbaddr)) { + printk(KERN_ERR "ath: beacon DMA mapping failed\n"); + return -EIO; + } + + ds = bf->desc; + + flags = AR5K_TXDESC_NOACK; + if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) { + ds->ds_link = bf->daddr; /* self-linked */ + flags |= AR5K_TXDESC_VEOL; + /* + * Let hardware handle antenna switching if txantenna is not set + */ + } else { + ds->ds_link = 0; + /* + * Switch antenna every 4 beacons if txantenna is not set + * XXX assumes two antenna + */ + if (antenna == 0) { + antenna = (sc->stats.ast_be_xmit & 4 ? 2 : 1); + } + } + + ds->ds_data = bf->skbaddr; + ret = ah->ah_setup_tx_desc(ah, ds, skb->len + FCS_LEN, + ieee80211_get_hdrlen_from_skb(skb), + AR5K_PKT_TYPE_BEACON, 0xffff, ctl->tx_rate, 1, + AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0); + if (ret) + goto err_unmap; + /* NB: beacon's BufLen must be a multiple of 4 bytes */ + ret = ah->ah_fill_tx_desc(ah, ds, roundup(skb->len, 4), true, true); + if (ret) + goto err_unmap; + + return 0; +err_unmap: + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); + return ret; +} + +/* + * Transmit a beacon frame at SWBA. Dynamic updates to the + * frame contents are done as needed and the slot time is + * also adjusted based on current state. + * + * this is usually called from interrupt context (ath_intr()) + * but also from ath_beacon_config() in IBSS mode which in turn + * can be called from a tasklet and user context + */ +static void ath_beacon_send(struct ath_softc *sc) +{ + struct ath_buf *bf = sc->bbuf; + struct ath_hw *ah = sc->ah; + + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__); + + if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA || + sc->opmode == IEEE80211_IF_TYPE_MNTR)) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: bf=%p bf_skb=%p\n", + __func__, bf, bf ? bf->skb : NULL); + return; + } + /* + * Check if the previous beacon has gone out. If + * not don't don't try to post another, skip this + * period and wait for the next. Missed beacons + * indicate a problem and should not occur. If we + * miss too many consecutive beacons reset the device. + */ + if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { + sc->bmisscount++; + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, + "%s: missed %u consecutive beacons\n", + __func__, sc->bmisscount); + if (sc->bmisscount > 3) { /* NB: 3 is a guess */ + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, + "%s: stuck beacon time (%u missed)\n", + __func__, sc->bmisscount); + tasklet_schedule(&sc->restq); + } + return; + } + if (unlikely(sc->bmisscount != 0)) { + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, + "%s: resume beacon xmit after %u misses\n", + __func__, sc->bmisscount); + sc->bmisscount = 0; + } + + /* + * Stop any current dma and put the new frame on the queue. + * This should never fail since we check above that no frames + * are still pending on the queue. + */ + if (unlikely(!ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { + DPRINTF(sc, ATH_DEBUG_ANY, "%s: beacon queue %u didn't stop?\n", + __func__, sc->bhalq); + /* NB: the HAL still stops DMA, so proceed */ + } + pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len, + PCI_DMA_TODEVICE); + + ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr); + ath5k_hw_tx_start(ah, sc->bhalq); + DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: TXDP[%u] = %llx (%p)\n", + __func__, sc->bhalq, (unsigned long long)bf->daddr, bf->desc); + + sc->stats.ast_be_xmit++; +} + +static int ath_beaconq_config(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + struct ath5k_txq_info qi; + int ret; + + ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); + if (ret) + return ret; + if (sc->opmode == IEEE80211_IF_TYPE_AP || + sc->opmode == IEEE80211_IF_TYPE_IBSS) { + /* + * Always burst out beacon and CAB traffic. + */ + qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; + qi.tqi_cw_min = ATH_BEACON_CWMIN_DEFAULT; + qi.tqi_cw_max = ATH_BEACON_CWMAX_DEFAULT; + } + + ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi); + if (ret) { + printk(KERN_ERR "%s: unable to update parameters for beacon " + "hardware queue!\n", __func__); + return ret; + } + + return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; +} + +/* + * Configure the beacon and sleep timers. + * + * When operating as an AP this resets the TSF and sets + * up the hardware to notify us when we need to issue beacons. + * + * When operating in station mode this sets up the beacon + * timers according to the timestamp of the last received + * beacon and the current TSF, configures PCF and DTIM + * handling, programs the sleep registers so the hardware + * will wakeup in time to receive beacons, and configures + * the beacon miss handling so we'll receive a BMISS + * interrupt when we stop seeing beacons from the AP + * we've associated with. + */ +static void ath_beacon_config(struct ath_softc *sc) +{ +#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) + struct ath_hw *ah = sc->ah; + u32 uninitialized_var(nexttbtt), intval, tsftu; + u64 tsf; + + intval = sc->bintval & AR5K_BEACON_PERIOD; + if (WARN_ON(!intval)) + return; + + /* current TSF converted to TU */ + tsf = ath5k_hw_get_tsf64(ah); + tsftu = TSF_TO_TU((u32)(tsf >> 32), (u32)tsf); + + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: intval %u hw tsftu %u\n", __func__, + intval, tsftu); + + if (sc->opmode == IEEE80211_IF_TYPE_STA) { + ath5k_hw_set_intr(ah, 0); + sc->imask |= AR5K_INT_BMISS; + sc->bmisscount = 0; + ath5k_hw_set_intr(ah, sc->imask); + } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS /* TODO || AP */) { + ath5k_hw_set_intr(ah, 0); + if (sc->opmode == IEEE80211_IF_TYPE_IBSS) { + /* + * Pull nexttbtt forward to reflect the current + * TSF. Add one intval otherwise the timespan + * can be too short for ibss merges. + */ + nexttbtt = tsftu + 2 * intval; + + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u " + "intval %u\n", __func__, nexttbtt, intval); + + /* + * In IBSS mode enable the beacon timers but only + * enable SWBA interrupts if we need to manually + * prepare beacon frames. Otherwise we use a + * self-linked tx descriptor and let the hardware + * deal with things. + */ + if (!ath5k_hw_hasveol(ah)) + sc->imask |= AR5K_INT_SWBA; + } /* TODO else AP */ + + intval |= AR5K_BEACON_ENA; + + ath_beaconq_config(sc); + ath5k_hw_init_beacon(ah, nexttbtt, intval); + + sc->bmisscount = 0; + ath5k_hw_set_intr(ah, sc->imask); + /* + * When using a self-linked beacon descriptor in + * ibss mode load it once here. + */ + if (sc->opmode == IEEE80211_IF_TYPE_IBSS && + ath5k_hw_hasveol(ah)) + ath_beacon_send(sc); + } +#undef TSF_TO_TU +} + +/* + * Calculate the receive filter according to the + * operating mode and state: + * + * o always accept unicast, broadcast, and multicast traffic + * o maintain current state of phy error reception (the hal + * may enable phy error frames for noise immunity work) + * o probe request frames are accepted only when operating in + * hostap, adhoc, or monitor modes + * o enable promiscuous mode according to the interface state + * o accept beacons: + * - when operating in adhoc mode so the 802.11 layer creates + * node table entries for peers, + * - when operating in station mode for collecting rssi data when + * the station is otherwise quiet, or + * - when scanning + * o accept any additional packets specified by sc_rxfilter + */ +static u32 ath_calcrxfilter(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + unsigned int opmode = sc->opmode; + u32 rfilt; + + rfilt = (ath5k_hw_get_rx_filter(ah) & AR5K_RX_FILTER_PHYERR) | + AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | + AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_RADARERR; + + if (sc->opmode == IEEE80211_IF_TYPE_MNTR) + rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON | + AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM; + if (opmode != IEEE80211_IF_TYPE_STA) + rfilt |= AR5K_RX_FILTER_PROBEREQ; + if (opmode != IEEE80211_IF_TYPE_AP && sc->promisc) + rfilt |= AR5K_RX_FILTER_PROM; + if (opmode == IEEE80211_IF_TYPE_STA || opmode == IEEE80211_IF_TYPE_IBSS) + rfilt |= AR5K_RX_FILTER_BEACON; + + return rfilt; +} + +static void ath_mode_init(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + u32 rfilt; + + /* configure rx filter */ + rfilt = ath_calcrxfilter(sc); + ath5k_hw_set_rx_filter(ah, rfilt); + + if (ath5k_hw_hasbssidmask(ah)) + ath5k_hw_set_bssid_mask(ah, sc->bssidmask); + + /* configure operational mode */ + ath5k_hw_set_opmode(ah); + + ath5k_hw_set_mcast_filter(ah, 0, 0); + DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); +} + +/* + * Enable the receive h/w following a reset. + */ +static int ath_startrecv(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + struct ath_buf *bf; + int ret; + + sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz); + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: cachelsz %u rxbufsize %u\n", + __func__, sc->cachelsz, sc->rxbufsize); + + sc->rxlink = NULL; + + spin_lock_bh(&sc->rxbuflock); + list_for_each_entry(bf, &sc->rxbuf, list) { + ret = ath_rxbuf_init(sc, bf); + if (ret != 0) { + spin_unlock_bh(&sc->rxbuflock); + goto err; + } + } + bf = list_first_entry(&sc->rxbuf, struct ath_buf, list); + spin_unlock_bh(&sc->rxbuflock); + + ath5k_hw_put_rx_buf(ah, bf->daddr); + ath5k_hw_start_rx(ah); /* enable recv descriptors */ + ath_mode_init(sc); /* set filters, etc. */ + ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ + + return 0; +err: + return ret; +} + +static inline void ath_update_txpow(struct ath_softc *sc) +{ + ath5k_hw_set_txpower_limit(sc->ah, 0); +} + +static int ath_stop_locked(struct ath_softc *); + +static int ath_init(struct ath_softc *sc) +{ + int ret; + + mutex_lock(&sc->lock); + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: mode %d\n", __func__, sc->opmode); + + /* + * Stop anything previously setup. This is safe + * no matter this is the first time through or not. + */ + ath_stop_locked(sc); + + /* + * The basic interface to setting the hardware in a good + * state is ``reset''. On return the hardware is known to + * be powered up and with interrupts disabled. This must + * be followed by initialization of the appropriate bits + * and then setup of the interrupt mask. + */ + sc->curchan = sc->hw->conf.chan; + ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false); + if (ret) { + printk(KERN_ERR "unable to reset hardware: %d\n", ret); + goto done; + } + /* + * This is needed only to setup initial state + * but it's best done after a reset. + */ + ath_update_txpow(sc); + + /* + * Setup the hardware after reset: the key cache + * is filled as needed and the receive engine is + * set going. Frame transmit is handled entirely + * in the frame output path; there's nothing to do + * here except setup the interrupt mask. + */ + ret = ath_startrecv(sc); + if (ret) + goto done; + + /* + * Enable interrupts. + */ + sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN + | AR5K_INT_FATAL | AR5K_INT_GLOBAL; + + ath5k_hw_set_intr(sc->ah, sc->imask); + + mod_timer(&sc->calib_tim, round_jiffies(jiffies + + msecs_to_jiffies(ath_calinterval * 1000))); + + ret = 0; +done: + mutex_unlock(&sc->lock); + return ret; +} + +/* + * Disable the receive h/w in preparation for a reset. + */ +static void ath_stoprecv(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + + ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ + ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ + ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ + mdelay(3); /* 3ms is long enough for 1 frame */ +#if AR_DEBUG + if (unlikely(sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL))) { + struct ath_desc *ds; + struct ath_buf *bf; + int status; + + printk(KERN_DEBUG "%s: rx queue %x, link %p\n", __func__, + ath5k_hw_get_rx_buf(ah), sc->rxlink); + + spin_lock_bh(&sc->rxbuflock); + list_for_each_entry(bf, &sc->rxbuf, list) { + ds = bf->desc; + status = ah->ah_proc_rx_desc(ah, ds); + if (!status || (sc->debug & ATH_DEBUG_FATAL)) + ath_printrxbuf(bf, status == 0); + } + spin_unlock_bh(&sc->rxbuflock); + } +#endif + sc->rxlink = NULL; /* just in case */ +} + +static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) +{ + struct ath_buf *bf, *bf0; + + /* + * NB: this assumes output has been stopped and + * we do not need to block ath_tx_tasklet + */ + spin_lock_bh(&txq->lock); + list_for_each_entry_safe(bf, bf0, &txq->q, list) { +#if AR_DEBUG + if (sc->debug & ATH_DEBUG_RESET) + ath_printtxbuf(bf, !sc->ah->ah_proc_tx_desc(sc->ah, + bf->desc)); +#endif + ath_cleanup_txbuf(sc, bf); + + spin_lock_bh(&sc->txbuflock); + sc->tx_stats.data[txq->qnum].len--; + list_move_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; + spin_unlock_bh(&sc->txbuflock); + } + txq->link = NULL; + spin_unlock_bh(&txq->lock); +} + +/* + * Drain the transmit queues and reclaim resources. + */ +static void ath_draintxq(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + int i; + + /* XXX return value */ + if (likely(!sc->invalid)) { + /* don't touch the hardware if marked invalid */ + (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, + ath5k_hw_get_tx_buf(ah, sc->bhalq)); + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) + if (sc->txqs[i].setup) { + ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: txq [%u] %x, " + "link %p\n", __func__, + sc->txqs[i].qnum, + ath5k_hw_get_tx_buf(ah, + sc->txqs[i].qnum), + sc->txqs[i].link); + } + } + ieee80211_start_queues(sc->hw); /* XXX move to callers */ + + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) + if (sc->txqs[i].setup) + ath_tx_draintxq(sc, &sc->txqs[i]); +} + +static int ath_stop_locked(struct ath_softc *sc) +{ + struct ath_hw *ah = sc->ah; + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__, sc->invalid); + + /* + * Shutdown the hardware and driver: + * stop output from above + * disable interrupts + * turn off timers + * turn off the radio + * clear transmit machinery + * clear receive machinery + * drain and release tx queues + * reclaim beacon resources + * power down hardware + * + * Note that some of this work is not possible if the + * hardware is gone (invalid). + */ + ieee80211_stop_queues(sc->hw); + + if (!sc->invalid) { + if (sc->led_soft) { + del_timer_sync(&sc->led_tim); + ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); + sc->led_blinking = 0; + } + ath5k_hw_set_intr(ah, 0); + } + ath_draintxq(sc); + if (!sc->invalid) { + ath_stoprecv(sc); + ath5k_hw_phy_disable(ah); + } else + sc->rxlink = NULL; +// ath_beacon_free(sc); + + return 0; +} + +/* + * Stop the device, grabbing the top-level lock to protect + * against concurrent entry through ath_init (which can happen + * if another thread does a system call and the thread doing the + * stop is preempted). + */ +static int ath_stop_hw(struct ath_softc *sc) +{ + int ret; + + mutex_lock(&sc->lock); + ret = ath_stop_locked(sc); + if (ret == 0 && !sc->invalid) { + /* + * Set the chip in full sleep mode. Note that we are + * careful to do this only when bringing the interface + * completely to a stop. When the chip is in this state + * it must be carefully woken up or references to + * registers in the PCI clock domain may freeze the bus + * (and system). This varies by chip and is mostly an + * issue with newer parts that go to sleep more quickly. + */ + if (sc->ah->ah_mac_version >= 7 && sc->ah->ah_mac_revision >= 8) { + /* + * XXX + * don't put newer MAC revisions > 7.8 to sleep because + * of the above mentioned problems + */ + DPRINTF(sc, ATH_DEBUG_RESET, "%s: mac version > 7.8, " + "not putting device to sleep\n", __func__); + } + else { + DPRINTF(sc, ATH_DEBUG_RESET, + "%s: putting device to full sleep\n", __func__); + ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); + } + } + ath_cleanup_txbuf(sc, sc->bbuf); + mutex_unlock(&sc->lock); + + del_timer_sync(&sc->calib_tim); + + return ret; +} + +static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) +{ + if (unlikely(sc->led_soft)) { + /* from Atheros NDIS driver, w/ permission */ + static const struct { + u16 rate; /* tx/rx 802.11 rate */ + u16 timeOn; /* LED on time (ms) */ + u16 timeOff; /* LED off time (ms) */ + } blinkrates[] = { + { 108, 40, 10 }, + { 96, 44, 11 }, + { 72, 50, 13 }, + { 48, 57, 14 }, + { 36, 67, 16 }, + { 24, 80, 20 }, + { 22, 100, 25 }, + { 18, 133, 34 }, + { 12, 160, 40 }, + { 10, 200, 50 }, + { 6, 240, 58 }, + { 4, 267, 66 }, + { 2, 400, 100 }, + { 0, 500, 130 } + }; + const struct ath5k_rate_table* rt = + ath5k_hw_get_rate_table(sc->ah, mode); + unsigned int i, j; + + BUG_ON(rt == NULL); + + memset(sc->hwmap, 0, sizeof(sc->hwmap)); + for (i = 0; i < 32; i++) { + u8 ix = rt->rate_code_to_index[i]; + if (ix == 0xff) { + sc->hwmap[i].ledon = msecs_to_jiffies(500); + sc->hwmap[i].ledoff = msecs_to_jiffies(130); + continue; + } + sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; + if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == + MODULATION_OFDM) + sc->hwmap[i].txflags |= + IEEE80211_RADIOTAP_F_SHORTPRE; + /* receive frames include FCS */ + sc->hwmap[i].rxflags = sc->hwmap[i].txflags | + IEEE80211_RADIOTAP_F_FCS; + /* setup blink rate table to avoid per-packet lookup */ + for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) + if (blinkrates[j].rate == /* XXX why 7f? */ + (rt->rates[ix].dot11_rate&0x7f)) + break; + + sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j]. + timeOn); + sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j]. + timeOff); + } + } + + sc->curmode = mode; +} + +/* + * Set/change channels. If the channel is really being changed, + * it's done by reseting the chip. To accomplish this we must + * first cleanup any pending DMA, then restart stuff after a la + * ath_init. + */ +static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) +{ + struct ath_hw *ah = sc->ah; + int ret; + + DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", + __func__, sc->curchan->chan, sc->curchan->freq, + chan->chan, chan->freq); + + if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) { + /* + * To switch channels clear any pending DMA operations; + * wait long enough for the RX fifo to drain, reset the + * hardware at the new frequency, and then re-enable + * the relevant bits of the h/w. + */ + ath5k_hw_set_intr(ah, 0); /* disable interrupts */ + ath_draintxq(sc); /* clear pending tx frames */ + ath_stoprecv(sc); /* turn off frame recv */ + ret = ath5k_hw_reset(ah, sc->opmode, chan, true); + if (ret) { + printk(KERN_ERR "%s: unable to reset channel %u " + "(%u Mhz)\n", __func__, chan->chan, chan->freq); + return ret; + } + sc->curchan = chan; + ath_update_txpow(sc); + + /* + * Re-enable rx framework. + */ + ret = ath_startrecv(sc); + if (ret) { + printk(KERN_ERR "%s: unable to restart recv logic\n", + __func__); + return ret; + } + + /* + * Change channels and update the h/w rate map + * if we're switching; e.g. 11a to 11b/g. + */ +// ath_chan_change(sc, chan); + + /* + * Re-enable interrupts. + */ + ath5k_hw_set_intr(ah, sc->imask); + } + + return 0; +} + +static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, + struct ieee80211_tx_control *ctl) +{ + struct ath_hw *ah = sc->ah; + struct ath_txq *txq = sc->txq; + struct ath_desc *ds = bf->desc; + struct sk_buff *skb = bf->skb; + unsigned int hdrpad, pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; + int ret; + + flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; + bf->ctl = *ctl; + /* XXX endianness */ + bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); + + if (ctl->flags & IEEE80211_TXCTL_NO_ACK) + flags |= AR5K_TXDESC_NOACK; + + if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) + printk(KERN_DEBUG "tx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + + hdrpad = 0; + pktlen = skb->len - hdrpad + FCS_LEN; + + if (ctl->key_idx != HW_KEY_IDX_INVALID) { + keyidx = ctl->key_idx; + pktlen += ctl->icv_len; + } + + ret = ah->ah_setup_tx_desc(ah, ds, pktlen, + ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, + 0xffff, ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0); + if (ret) + goto err_unmap; + + ds->ds_link = 0; + ds->ds_data = bf->skbaddr; + + ret = ah->ah_fill_tx_desc(ah, ds, skb->len, true, true); + if (ret) + goto err_unmap; + + spin_lock_bh(&txq->lock); + list_add_tail(&bf->list, &txq->q); + sc->tx_stats.data[txq->qnum].len++; + if (txq->link == NULL) /* is this first packet? */ + ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); + else /* no, so only link it */ + *txq->link = bf->daddr; + + txq->link = &ds->ds_link; + ath5k_hw_tx_start(ah, txq->qnum); + spin_unlock_bh(&txq->lock); + +// printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); + + return 0; +err_unmap: + pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); + return ret; +} + +static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, + struct ieee80211_tx_control *ctl) +{ + struct ath_softc *sc = hw->priv; + struct ath_buf *bf; + unsigned long flags; + + ath_dump_skb(skb, "t"); + + if (sc->opmode == IEEE80211_IF_TYPE_MNTR) + DPRINTF(sc, ATH_DEBUG_XMIT, "tx in monitor (scan?)\n"); + + sc->led_txrate = ctl->tx_rate; + + spin_lock_irqsave(&sc->txbuflock, flags); + if (list_empty(&sc->txbuf)) { + if (net_ratelimit()) + printk(KERN_ERR "ath: no further txbuf available, " + "dropping packet\n"); + sc->stats.ast_tx_nobuf++; + spin_unlock_irqrestore(&sc->txbuflock, flags); + ieee80211_stop_queue(hw, ctl->queue); + return -1; + } + bf = list_first_entry(&sc->txbuf, struct ath_buf, list); + list_del(&bf->list); + sc->txbuf_len--; + if (list_empty(&sc->txbuf)) { + sc->stats.ast_tx_qstop++; + ieee80211_stop_queues(hw); + } + spin_unlock_irqrestore(&sc->txbuflock, flags); + + bf->skb = skb; + + if (ath_tx_bf(sc, bf, ctl)) { + bf->skb = NULL; + spin_lock_irqsave(&sc->txbuflock, flags); + list_add_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; + spin_unlock_irqrestore(&sc->txbuflock, flags); + dev_kfree_skb_any(skb); + return 0; + } + + return 0; +} + +static int ath_reset(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + int ret; + + DPRINTF(sc, ATH_DEBUG_RESET, "resetting\n"); + /* + * Convert to a HAL channel description with the flags + * constrained to reflect the current operating mode. + */ + sc->curchan = hw->conf.chan; + + ath5k_hw_set_intr(ah, 0); + ath_draintxq(sc); + ath_stoprecv(sc); + + ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true); + if (unlikely(ret)) { + printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret); + goto err; + } + ath_update_txpow(sc); + + ret = ath_startrecv(sc); + if (unlikely(ret)) { + printk(KERN_ERR "ath: can't start recv logic\n"); + goto err; + } + /* + * We may be doing a reset in response to an ioctl + * that changes the channel so update any state that + * might change as a result. + */ +// ath_chan_change(sc, c); + ath_beacon_config(sc); + /* intrs are started by ath_beacon_config */ + + ieee80211_wake_queues(hw); + + return 0; +err: + return ret; +} + +static int ath_open(struct ieee80211_hw *hw) +{ + return ath_init(hw->priv); +} + +static int ath_stop(struct ieee80211_hw *hw) +{ + return ath_stop_hw(hw->priv); +} + +static int ath_add_interface(struct ieee80211_hw *hw, + struct ieee80211_if_init_conf *conf) +{ + struct ath_softc *sc = hw->priv; + int ret; + + mutex_lock(&sc->lock); + if (sc->iface_id) { + ret = 0; + goto end; + } + + sc->iface_id = conf->if_id; + + switch (conf->type) { + case IEEE80211_IF_TYPE_STA: + case IEEE80211_IF_TYPE_IBSS: + case IEEE80211_IF_TYPE_MNTR: + sc->opmode = conf->type; + break; + default: + ret = -EOPNOTSUPP; + goto end; + } + ret = 0; +end: + mutex_unlock(&sc->lock); + return ret; +} + +static void ath_remove_interface(struct ieee80211_hw *hw, + struct ieee80211_if_init_conf *conf) +{ + struct ath_softc *sc = hw->priv; + + mutex_lock(&sc->lock); + if (sc->iface_id != conf->if_id) { + goto end; + } + + sc->iface_id = 0; +end: + mutex_unlock(&sc->lock); +} + +static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) +{ + struct ath_softc *sc = hw->priv; + + sc->bintval = conf->beacon_int * 1000 / 1024; + ath_setcurmode(sc, conf->phymode); + + return ath_chan_set(sc, conf->chan); +} + +static int ath_config_interface(struct ieee80211_hw *hw, int if_id, + struct ieee80211_if_conf *conf) +{ + struct ath_softc *sc = hw->priv; + int ret; + + mutex_lock(&sc->lock); + if (sc->iface_id != if_id) { + ret = -EIO; + goto unlock; + } + if (conf->bssid) + ath5k_hw_set_associd(sc->ah, conf->bssid, 0 /* FIXME: aid */); + mutex_unlock(&sc->lock); + + return ath_reset(hw); +unlock: + mutex_unlock(&sc->lock); + return ret; +} + +static void ath_set_multicast_list(struct ieee80211_hw *hw, + unsigned short flags, int mc_count) +{ + struct ath_softc *sc = hw->priv; + unsigned int prom = !!(flags & IFF_PROMISC); + u32 rfilt; + + if (sc->promisc != prom) { + sc->promisc = prom; + rfilt = ath_calcrxfilter(sc); + ath5k_hw_set_rx_filter(sc->ah, rfilt); + } +} + +static int ath_set_key(struct ieee80211_hw *hw, set_key_cmd cmd, + u8 *addr, struct ieee80211_key_conf *key, int aid) +{ + struct ath_softc *sc = hw->priv; + int ret = 0; + + mutex_lock(&sc->lock); + + switch (cmd) { + case SET_KEY: + if (key->alg != ALG_WEP && key->alg != ALG_NONE && + key->alg != ALG_NULL) { + ret = -EINVAL; + goto unlock; + } + + ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr); + if (ret) { + printk(KERN_ERR "ath: can't set the key\n"); + goto unlock; + } + + set_bit(key->keyidx, sc->keymap); + key->hw_key_idx = key->keyidx; + key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT; + break; + case DISABLE_KEY: + ath5k_hw_reset_key(sc->ah, key->keyidx); + clear_bit(key->keyidx, sc->keymap); + break; + case REMOVE_ALL_KEYS: { + unsigned int i; + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) { + ath5k_hw_reset_key(sc->ah, i); + clear_bit(i, sc->keymap); + } + break; + } + default: + ret = -EINVAL; + goto unlock; + } + +unlock: + mutex_unlock(&sc->lock); + return ret; +} + +static int ath_get_stats(struct ieee80211_hw *hw, + struct ieee80211_low_level_stats *stats) +{ + struct ath_softc *sc = hw->priv; + + memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); + + return 0; +} + +static int ath_get_tx_stats(struct ieee80211_hw *hw, + struct ieee80211_tx_queue_stats *stats) +{ + struct ath_softc *sc = hw->priv; + + memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); + + return 0; +} + +static u64 ath_get_tsf(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + return ath5k_hw_get_tsf64(sc->ah); +} + +static void ath_reset_tsf(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + ath5k_hw_reset_tsf(sc->ah); +} + +static int ath_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, + struct ieee80211_tx_control *ctl) +{ + struct ath_softc *sc = hw->priv; + int ret; + + ath_dump_skb(skb, "b"); + + mutex_lock(&sc->lock); + + if (sc->opmode != IEEE80211_IF_TYPE_IBSS) { + ret = -EIO; + goto end; + } + + ath_cleanup_txbuf(sc, sc->bbuf); + sc->bbuf->skb = skb; + ret = ath_beacon_setup(sc, sc->bbuf, ctl); + if (ret) + sc->bbuf->skb = NULL; + +end: + mutex_unlock(&sc->lock); + return ret; +} + +static struct ieee80211_ops ath_hw_ops = { + .tx = ath_tx, + .reset = ath_reset, + .open = ath_open, + .stop = ath_stop, + .add_interface = ath_add_interface, + .remove_interface = ath_remove_interface, + .config = ath_config, + .config_interface = ath_config_interface, + .set_multicast_list = ath_set_multicast_list, + .set_key = ath_set_key, + .get_stats = ath_get_stats, + .conf_tx = NULL, + .get_tx_stats = ath_get_tx_stats, + .get_tsf = ath_get_tsf, + .reset_tsf = ath_reset_tsf, + .beacon_update = ath_beacon_update, +}; + +/* + * Periodically recalibrate the PHY to account + * for temperature/environment changes. + */ +static void ath_calibrate(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + struct ath_hw *ah = sc->ah; + + sc->stats.ast_per_cal++; + + DPRINTF(sc, ATH_DEBUG_CALIBRATE, "ath: channel %u/%x\n", + sc->curchan->chan, sc->curchan->val); + + if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { + /* + * Rfgain is out of bounds, reset the chip + * to load new gain values. + */ + sc->stats.ast_per_rfgain++; + DPRINTF(sc, ATH_DEBUG_RESET, "calibration, resetting\n"); + ath_reset(sc->hw); + } + if (ath5k_hw_phy_calibrate(ah, sc->curchan)) { + DPRINTF(sc, ATH_DEBUG_ANY, "ath: calibration of channel %u " + "failed\n", sc->curchan->chan); + sc->stats.ast_per_calfail++; + } + + mod_timer(&sc->calib_tim, round_jiffies(jiffies + + msecs_to_jiffies(ath_calinterval * 1000))); +} + +static void ath_led_off(unsigned long data) +{ + struct ath_softc *sc = (void *)data; + + if (sc->led_endblink) + sc->led_blinking = 0; + else { + sc->led_endblink = 1; + ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on); + mod_timer(&sc->led_tim, jiffies + sc->led_off); + } +} + +/* + * Blink the LED according to the specified on/off times. + */ +static void ath_led_blink(struct ath_softc *sc, unsigned int on, + unsigned int off) +{ + DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); + ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on); + sc->led_blinking = 1; + sc->led_endblink = 0; + sc->led_off = off; + mod_timer(&sc->led_tim, jiffies + on); +} + +static void ath_led_event(struct ath_softc *sc, int event) +{ + if (likely(!sc->led_soft)) + return; + if (unlikely(sc->led_blinking)) /* don't interrupt active blink */ + return; + switch (event) { + case ATH_LED_TX: + ath_led_blink(sc, sc->hwmap[sc->led_txrate].ledon, + sc->hwmap[sc->led_txrate].ledoff); + break; + case ATH_LED_RX: + ath_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon, + sc->hwmap[sc->led_rxrate].ledoff); + break; + } +} + +static irqreturn_t ath_intr(int irq, void *dev_id) +{ + struct ath_softc *sc = dev_id; + struct ath_hw *ah = sc->ah; + enum ath5k_int status; + unsigned int counter = 1000; + + if (unlikely(sc->invalid || !ath5k_hw_is_intr_pending(ah))) + return IRQ_NONE; + + do { + /* + * Figure out the reason(s) for the interrupt. Note + * that the hal returns a pseudo-ISR that may include + * bits we haven't explicitly enabled so we mask the + * value to insure we only process bits we requested. + */ + ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ + DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x/0x%x\n", __func__, + status, sc->imask); + status &= sc->imask; /* discard unasked for bits */ + if (unlikely(status & AR5K_INT_FATAL)) { + /* + * Fatal errors are unrecoverable. Typically + * these are caused by DMA errors. Unfortunately + * the exact reason is not (presently) returned + * by the hal. + */ + sc->stats.ast_hardware++; + tasklet_schedule(&sc->restq); + } else if (unlikely(status & AR5K_INT_RXORN)) { + sc->stats.ast_rxorn++; + tasklet_schedule(&sc->restq); + } else { + if (status & AR5K_INT_SWBA) { + /* + * Software beacon alert--time to send a beacon. + * Handle beacon transmission directly; deferring + * this is too slow to meet timing constraints + * under load. + */ + ath_beacon_send(sc); + } + if (status & AR5K_INT_RXEOL) { + /* + * NB: the hardware should re-read the link when + * RXE bit is written, but it doesn't work at + * least on older hardware revs. + */ + sc->stats.ast_rxeol++; + sc->rxlink = NULL; + } + if (status & AR5K_INT_TXURN) { + sc->stats.ast_txurn++; + /* bump tx trigger level */ + ath5k_hw_update_tx_triglevel(ah, true); + } + if (status & AR5K_INT_RX) + tasklet_schedule(&sc->rxtq); + if (status & AR5K_INT_TX) + tasklet_schedule(&sc->txtq); + if (status & AR5K_INT_BMISS) { + sc->stats.ast_bmiss++; +/* tasklet_schedule(&sc->bmisstq);*/ + } + if (status & AR5K_INT_MIB) { + sc->stats.ast_mib++; + /* TODO */ + } + } + } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); + + if (unlikely(!counter && net_ratelimit())) + printk(KERN_WARNING "ath: too many interrupts, giving up for " + "now\n"); + + return IRQ_HANDLED; +} + +/* + * Convert IEEE channel number to MHz frequency. + */ +static inline short ath_ieee2mhz(short chan) +{ + if (chan <= 14 || chan >= 27) + return ieee80211chan2mhz(chan); + else + return 2212 + chan * 20; +} + +static unsigned int ath_copy_rates(struct ieee80211_rate *rates, + const struct ath5k_rate_table *rt, unsigned int max) +{ + unsigned int i, count; + + if (rt == NULL) + return 0; + + for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) { + if (!rt->rates[i].valid) + continue; + rates->rate = rt->rates[i].rate_kbps / 100; + rates->val = rt->rates[i].rate_code; + rates->flags = rt->rates[i].modulation; + rates++; + count++; + max--; + } + + return count; +} + +static unsigned int ath_copy_channels(struct ath_hw *ah, + struct ieee80211_channel *channels, unsigned int mode, + unsigned int max) +{ + static const struct { unsigned int mode, mask, chan; } map[] = { + [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A }, + [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T }, + [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B }, + [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G }, + [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG }, + }; + static const struct ath5k_regchannel chans_2ghz[] = + IEEE80211_CHANNELS_2GHZ; + static const struct ath5k_regchannel chans_5ghz[] = + IEEE80211_CHANNELS_5GHZ; + const struct ath5k_regchannel *chans; + enum ath5k_regdom dmn; + unsigned int i, count, size, chfreq, all, f, ch; + + if (!test_bit(mode, ah->ah_modes)) + return 0; + + all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1; + + switch (mode) { + case MODE_IEEE80211A: + case MODE_ATHEROS_TURBO: + /* 1..220, but 2GHz frequencies are filtered by check_channel */ + size = all ? 220 : ARRAY_SIZE(chans_5ghz); + chans = chans_5ghz; + dmn = ath5k_regdom2flag(ah->ah_regdomain, + IEEE80211_CHANNELS_5GHZ_MIN); + chfreq = CHANNEL_5GHZ; + break; + case MODE_IEEE80211B: + case MODE_IEEE80211G: + case MODE_ATHEROS_TURBOG: + size = all ? 26 : ARRAY_SIZE(chans_2ghz); + chans = chans_2ghz; + dmn = ath5k_regdom2flag(ah->ah_regdomain, + IEEE80211_CHANNELS_2GHZ_MIN); + chfreq = CHANNEL_2GHZ; + break; + default: + printk(KERN_WARNING "bad mode, not copying channels\n"); + return 0; + } + + for (i = 0, count = 0; i < size && max > 0; i++) { + ch = all ? i + 1 : chans[i].chan; + f = ath_ieee2mhz(ch); + /* Check if channel is supported by the chipset */ + if (!ath5k_channel_ok(ah, f, chfreq)) + continue; + + /* Match regulation domain */ + if (!all && !(IEEE80211_DMN(chans[i].domain) & + IEEE80211_DMN(dmn))) + continue; + + if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode) + continue; + + /* Write channel and increment counter */ + channels->chan = ch; + channels->freq = f; + channels->val = map[mode].chan; + channels++; + count++; + max--; + } + + return count; +} + +#if ATH_DEBUG_MODES +static void ath_dump_modes(struct ieee80211_hw_mode *modes) +{ + unsigned int m, i; + + for (m = 0; m < NUM_IEEE80211_MODES; m++) { + printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m, + modes[m].num_channels, modes[m].num_rates); + printk(KERN_DEBUG " channels:\n"); + for (i = 0; i < modes[m].num_channels; i++) { + printk(KERN_DEBUG " %3d %d %.4x %.4x\n", + modes[m].channels[i].chan, + modes[m].channels[i].freq, + modes[m].channels[i].val, + modes[m].channels[i].flag); + } + printk(KERN_DEBUG " rates:\n"); + for (i = 0; i < modes[m].num_rates; i++) { + printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n", + modes[m].rates[i].rate, + modes[m].rates[i].val, + modes[m].rates[i].flags, + modes[m].rates[i].val2); + } + } +} +#else +static inline void ath_dump_modes(struct ieee80211_hw_mode *modes) {} +#endif + +static int ath_getchannels(struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + struct ieee80211_hw_mode *modes = sc->modes; + unsigned int i, max; + int ret; + enum { + A = MODE_IEEE80211A, + B = MODE_IEEE80211G, /* this is not a typo, but workaround */ + G = MODE_IEEE80211B, /* to prefer g over b */ + T = MODE_ATHEROS_TURBO, + TG = MODE_ATHEROS_TURBOG, + }; + + BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 5); + + ah->ah_country_code = countrycode; + + modes[A].mode = MODE_IEEE80211A; + modes[B].mode = MODE_IEEE80211B; + modes[G].mode = MODE_IEEE80211G; + + max = ARRAY_SIZE(sc->rates); + modes[A].rates = sc->rates; + max -= modes[A].num_rates = ath_copy_rates(modes[A].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211A), max); + modes[B].rates = &modes[A].rates[modes[A].num_rates]; + max -= modes[B].num_rates = ath_copy_rates(modes[B].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211B), max); + modes[G].rates = &modes[B].rates[modes[B].num_rates]; + max -= modes[G].num_rates = ath_copy_rates(modes[G].rates, + ath5k_hw_get_rate_table(ah, MODE_IEEE80211G), max); + + if (!max) + printk(KERN_WARNING "yet another rates found, but there is not " + "sufficient space to store them\n"); + + max = ARRAY_SIZE(sc->channels); + modes[A].channels = sc->channels; + max -= modes[A].num_channels = ath_copy_channels(ah, modes[A].channels, + MODE_IEEE80211A, max); + modes[B].channels = &modes[A].channels[modes[A].num_channels]; + max -= modes[B].num_channels = ath_copy_channels(ah, modes[B].channels, + MODE_IEEE80211B, max); + modes[G].channels = &modes[B].channels[modes[B].num_channels]; + max -= modes[G].num_channels = ath_copy_channels(ah, modes[G].channels, + MODE_IEEE80211G, max); + + if (!max) + printk(KERN_WARNING "yet another modes found, but there is not " + "sufficient space to store them\n"); + + for (i = 0; i < ARRAY_SIZE(sc->modes); i++) + if (modes[i].num_channels) { + ret = ieee80211_register_hwmode(hw, &modes[i]); + if (ret) { + printk(KERN_ERR "can't register hwmode %u\n",i); + goto err; + } + } + ath_dump_modes(modes); + + return 0; +err: + return ret; +} + +static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev) +{ + struct ath_desc *ds; + struct ath_buf *bf; + dma_addr_t da; + unsigned int i; + int ret; + + /* allocate descriptors */ + sc->desc_len = sizeof(struct ath_desc) * + (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + ATH_BCBUF + 1); + sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); + if (sc->desc == NULL) { + dev_err(&pdev->dev, "can't allocate descriptors\n"); + ret = -ENOMEM; + goto err; + } + ds = sc->desc; + da = sc->desc_daddr; + DPRINTF(sc, ATH_DEBUG_ANY, "%s: DMA map: %p (%zu) -> %llx\n", + __func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr); + + bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, + sizeof(struct ath_buf), GFP_KERNEL); + if (bf == NULL) { + dev_err(&pdev->dev, "can't allocate bufptr\n"); + ret = -ENOMEM; + goto err_free; + } + sc->bufptr = bf; + + INIT_LIST_HEAD(&sc->rxbuf); + for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->rxbuf); + } + + INIT_LIST_HEAD(&sc->txbuf); + sc->txbuf_len = ATH_TXBUF; + for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC, + da += ATH_TXDESC * sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->txbuf); + } + + /* beacon buffer */ + bf->desc = ds; + bf->daddr = da; + sc->bbuf = bf; + + return 0; +err_free: + pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); +err: + sc->desc = NULL; + return ret; +} + +static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev) +{ + struct ath_buf *bf; + + ath_cleanup_txbuf(sc, sc->bbuf); + list_for_each_entry(bf, &sc->txbuf, list) + ath_cleanup_txbuf(sc, bf); + list_for_each_entry(bf, &sc->rxbuf, list) + ath_cleanup_txbuf(sc, bf); + + /* Free memory associated with all descriptors */ + pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); + + kfree(sc->bufptr); + sc->bufptr = NULL; +} + +static int ath_beaconq_setup(struct ath_hw *ah) +{ + struct ath5k_txq_info qi = { + .tqi_aifs = AR5K_TXQ_USEDEFAULT, + .tqi_cw_min = AR5K_TXQ_USEDEFAULT, + .tqi_cw_max = AR5K_TXQ_USEDEFAULT, + /* NB: for dynamic turbo, don't enable any other interrupts */ + .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE + }; + + return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); +} + +static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, + int subtype) +{ + struct ath_hw *ah = sc->ah; + struct ath_txq *txq; + struct ath5k_txq_info qi = { + .tqi_subtype = subtype, + .tqi_aifs = AR5K_TXQ_USEDEFAULT, + .tqi_cw_min = AR5K_TXQ_USEDEFAULT, + .tqi_cw_max = AR5K_TXQ_USEDEFAULT + }; + int qnum; + + /* + * Enable interrupts only for EOL and DESC conditions. + * We mark tx descriptors to receive a DESC interrupt + * when a tx queue gets deep; otherwise waiting for the + * EOL to reap descriptors. Note that this is done to + * reduce interrupt load and this only defers reaping + * descriptors, never transmitting frames. Aside from + * reducing interrupts this also permits more concurrency. + * The only potential downside is if the tx queue backs + * up in which case the top half of the kernel may backup + * due to a lack of tx descriptors. + */ + qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | + AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); + if (qnum < 0) { + /* + * NB: don't print a message, this happens + * normally on parts with too few tx queues + */ + return ERR_PTR(qnum); + } + if (qnum >= ARRAY_SIZE(sc->txqs)) { + printk(KERN_ERR "hal qnum %u out of range, max %u!\n", + qnum, ARRAY_SIZE(sc->txqs)); + ath5k_hw_release_tx_queue(ah, qnum); + return ERR_PTR(-EINVAL); + } + txq = &sc->txqs[qnum]; + if (!txq->setup) { + txq->qnum = qnum; + txq->link = NULL; + INIT_LIST_HEAD(&txq->q); + spin_lock_init(&txq->lock); + txq->setup = true; + } + return &sc->txqs[qnum]; +} + +static void ath_tx_cleanup(struct ath_softc *sc) +{ + struct ath_txq *txq = sc->txqs; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) + if (txq->setup) { + ath5k_hw_release_tx_queue(sc->ah, txq->qnum); + txq->setup = false; + } +} + +static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + struct ath_hw *ah = sc->ah; + u8 mac[ETH_ALEN]; + unsigned int i; + int ret; + + DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, pdev->device); + + /* + * Check if the MAC has multi-rate retry support. + * We do this by trying to setup a fake extended + * descriptor. MAC's that don't have support will + * return false w/o doing anything. MAC's that do + * support it will return true w/o doing anything. + */ + sc->mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); + + /* + * Reset the key cache since some parts do not + * reset the contents on initial power up. + */ + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) + ath5k_hw_reset_key(ah, i); + + /* + * Collect the channel list using the default country + * code and including outdoor channels. The 802.11 layer + * is resposible for filtering this list based on settings + * like the phy mode. + */ + ret = ath_getchannels(hw); + if (ret) { + dev_err(&pdev->dev, "can't get channels\n"); + goto err; + } + + /* NB: setup here so ath_rate_update is happy */ + if (test_bit(MODE_IEEE80211A, ah->ah_modes)) + ath_setcurmode(sc, MODE_IEEE80211A); + else + ath_setcurmode(sc, MODE_IEEE80211B); + + /* + * Allocate tx+rx descriptors and populate the lists. + */ + ret = ath_desc_alloc(sc, pdev); + if (ret) { + dev_err(&pdev->dev, "can't allocate descriptors\n"); + goto err; + } + + /* + * Allocate hardware transmit queues: one queue for + * beacon frames and one data queue for each QoS + * priority. Note that the hal handles reseting + * these queues at the needed time. + */ + ret = ath_beaconq_setup(ah); + if (ret < 0) { + dev_err(&pdev->dev, "can't setup a beacon xmit queue\n"); + goto err_desc; + } + sc->bhalq = ret; + + sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); + if (IS_ERR(sc->txq)) { + dev_err(&pdev->dev, "can't setup xmit queue\n"); + ret = PTR_ERR(sc->txq); + goto err_bhal; + } + + tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc); + tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc); + tasklet_init(&sc->restq, ath_tasklet_reset, (unsigned long)sc); + setup_timer(&sc->calib_tim, ath_calibrate, (unsigned long)sc); + setup_timer(&sc->led_tim, ath_led_off, (unsigned long)sc); + + sc->led_blinking = 0; + sc->led_on = 0; /* low true */ + /* + * Auto-enable soft led processing for IBM cards and for + * 5211 minipci cards. Users can also manually enable/disable + * support with a sysctl. + */ + if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || + pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) { + sc->led_soft = 1; + sc->led_pin = 0; + } + /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */ + if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) { + sc->led_soft = 1; + sc->led_pin = 0; + } + if (sc->led_soft) { + ath5k_hw_set_gpio_output(ah, sc->led_pin); + ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); + } + + ath5k_hw_get_lladdr(ah, mac); + SET_IEEE80211_PERM_ADDR(hw, mac); + if (ath5k_hw_hasbssidmask(ah)) { + memset(sc->bssidmask, 0xff, ETH_ALEN); + ath5k_hw_set_bssid_mask(ah, sc->bssidmask); + } + + ret = ieee80211_register_hw(hw); + if (ret) { + dev_err(&pdev->dev, "can't register ieee80211 hw\n"); + goto err_queues; + } + + return 0; +err_queues: + ath_tx_cleanup(sc); +err_bhal: + ath5k_hw_release_tx_queue(ah, sc->bhalq); +err_desc: + ath_desc_free(sc, pdev); +err: + return ret; +} + +static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) +{ + struct ath_softc *sc = hw->priv; + + /* + * NB: the order of these is important: + * o call the 802.11 layer before detaching the hal to + * insure callbacks into the driver to delete global + * key cache entries can be handled + * o reclaim the tx queue data structures after calling + * the 802.11 layer as we'll get called back to reclaim + * node state and potentially want to use them + * o to cleanup the tx queues the hal is called, so detach + * it last + * Other than that, it's straightforward... + */ + ieee80211_unregister_hw(hw); + ath_desc_free(sc, pdev); + ath_tx_cleanup(sc); + ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); + + /* + * NB: can't reclaim these until after ieee80211_ifdetach + * returns because we'll get called back to reclaim node + * state and potentially want to use them. + */ +// ath_dynamic_sysctl_unregister(sc); +} + +static const char *ath_chip_name(u8 mac_version) +{ + switch (mac_version) { + case AR5K_AR5210: + return "AR5210"; + case AR5K_AR5211: + return "AR5211"; + case AR5K_AR5212: + return "AR5212"; + } + return "Unknown"; +} + +static int __devinit ath_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + void __iomem *mem; + struct ath_softc *sc; + struct ieee80211_hw *hw; + int ret; + u8 csz; + + ret = pci_enable_device(pdev); + if (ret) { + dev_err(&pdev->dev, "can't enable device\n"); + goto err; + } + + /* XXX 32-bit addressing only */ + ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); + if (ret) { + dev_err(&pdev->dev, "32-bit DMA not available\n"); + goto err_dis; + } + + /* + * Cache line size is used to size and align various + * structures used to communicate with the hardware. + */ + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); + if (csz == 0) { + /* + * Linux 2.4.18 (at least) writes the cache line size + * register as a 16-bit wide register which is wrong. + * We must have this setup properly for rx buffer + * DMA to work so force a reasonable value here if it + * comes up zero. + */ + csz = L1_CACHE_BYTES / sizeof(u32); + pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); + } + /* + * The default setting of latency timer yields poor results, + * set it to the value used by other systems. It may be worth + * tweaking this setting more. + */ + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); + + pci_set_master(pdev); + + /* + * Disable the RETRY_TIMEOUT register (0x41) to keep + * PCI Tx retries from interfering with C3 CPU state. + */ + pci_write_config_byte(pdev, 0x41, 0); + + ret = pci_request_region(pdev, 0, "ath"); + if (ret) { + dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); + goto err_dis; + } + + mem = pci_iomap(pdev, 0, 0); + if (!mem) { + dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; + ret = -EIO; + goto err_reg; + } + + hw = ieee80211_alloc_hw(sizeof(*sc), &ath_hw_ops); + if (hw == NULL) { + dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); + ret = -ENOMEM; + goto err_map; + } + + SET_IEEE80211_DEV(hw, &pdev->dev); + hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_WEP_INCLUDE_IV | + IEEE80211_HW_DATA_NULLFUNC_ACK; + hw->extra_tx_headroom = 2; + hw->channel_change_time = 5000; + hw->max_rssi = 127; /* FIXME: get a real value for this. */ + sc = hw->priv; + sc->hw = hw; + + /* + * Mark the device as detached to avoid processing + * interrupts until setup is complete. + */ +#if AR_DEBUG + sc->debug = ath_debug; +#endif + sc->invalid = 1; + sc->iobase = mem; + sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ + sc->opmode = IEEE80211_IF_TYPE_STA; + mutex_init(&sc->lock); + spin_lock_init(&sc->rxbuflock); + spin_lock_init(&sc->txbuflock); + + pci_set_drvdata(pdev, hw); + + ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc); + if (ret) { + dev_err(&pdev->dev, "request_irq failed\n"); + goto err_free; + } + + sc->ah = ath5k_hw_attach(pdev->device, id->driver_data, sc, sc->iobase); + if (IS_ERR(sc->ah)) { + ret = PTR_ERR(sc->ah); + goto err_irq; + } + + ret = ath_attach(pdev, hw); + if (ret) + goto err_ah; + + dev_info(&pdev->dev, "%s chip found: mac %d.%d phy %d.%d\n", + ath_chip_name(id->driver_data), sc->ah->ah_mac_version, + sc->ah->ah_mac_version, sc->ah->ah_phy_revision >> 4, + sc->ah->ah_phy_revision & 0xf); + + /* ready to process interrupts */ + sc->invalid = 0; + + return 0; +err_ah: + ath5k_hw_detach(sc->ah); +err_irq: + free_irq(pdev->irq, sc); +err_free: + ieee80211_free_hw(hw); +err_map: + pci_iounmap(pdev, mem); +err_reg: + pci_release_region(pdev, 0); +err_dis: + pci_disable_device(pdev); +err: + return ret; +} + +static void __devexit ath_pci_remove(struct pci_dev *pdev) +{ + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; + + ath_detach(pdev, hw); + ath5k_hw_detach(sc->ah); + free_irq(pdev->irq, sc); + pci_iounmap(pdev, sc->iobase); + pci_release_region(pdev, 0); + pci_disable_device(pdev); + ieee80211_free_hw(hw); +} + +#ifdef CONFIG_PM +static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) +{ + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; + + if (sc->led_soft) + ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); + + ath_stop_hw(sc); + pci_save_state(pdev); + pci_disable_device(pdev); + pci_set_power_state(pdev, PCI_D3hot); + + return 0; +} + +static int ath_pci_resume(struct pci_dev *pdev) +{ + struct ieee80211_hw *hw = pci_get_drvdata(pdev); + struct ath_softc *sc = hw->priv; + int err; + + err = pci_set_power_state(pdev, PCI_D0); + if (err) + return err; + + err = pci_enable_device(pdev); + if (err) + return err; + + pci_restore_state(pdev); + /* + * Suspend/Resume resets the PCI configuration space, so we have to + * re-disable the RETRY_TIMEOUT register (0x41) to keep + * PCI Tx retries from interfering with C3 CPU state + */ + pci_write_config_byte(pdev, 0x41, 0); + + ath_init(sc); + if (sc->led_soft) { + ath5k_hw_set_gpio_output(sc->ah, sc->led_pin); + ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0); + } + + return 0; +} +#else +#define ath_pci_suspend NULL +#define ath_pci_resume NULL +#endif /* CONFIG_PM */ + +static struct pci_driver ath_pci_drv_id = { + .name = "ath_pci", + .id_table = ath_pci_id_table, + .probe = ath_pci_probe, + .remove = __devexit_p(ath_pci_remove), + .suspend = ath_pci_suspend, + .resume = ath_pci_resume, +}; + +/* + * Static (i.e. global) sysctls. Note that the hal sysctls + * are located under ours by sharing the setting for DEV_ATH. + */ +enum { + DEV_ATH = 9, /* XXX known by hal */ +}; + +static int mincalibrate = 1; +static int maxint = 0x7ffffff / 1000; +#define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ + +static ctl_table ath_static_sysctls[] = { +#if AR_DEBUG + { .ctl_name = CTL_AUTO, + .procname = "debug", + .mode = 0644, + .data = &ath_debug, + .maxlen = sizeof(ath_debug), + .proc_handler = proc_dointvec + }, +#endif + { .ctl_name = CTL_AUTO, + .procname = "countrycode", + .mode = 0444, + .data = &countrycode, + .maxlen = sizeof(countrycode), + .proc_handler = proc_dointvec + }, + { .ctl_name = CTL_AUTO, + .procname = "outdoor", + .mode = 0444, + .data = &outdoor, + .maxlen = sizeof(outdoor), + .proc_handler = proc_dointvec + }, + { .ctl_name = CTL_AUTO, + .procname = "xchanmode", + .mode = 0444, + .data = &xchanmode, + .maxlen = sizeof(xchanmode), + .proc_handler = proc_dointvec + }, + { .ctl_name = CTL_AUTO, + .procname = "calibrate", + .mode = 0644, + .data = &ath_calinterval, + .maxlen = sizeof(ath_calinterval), + .extra1 = &mincalibrate, + .extra2 = &maxint, + .proc_handler = proc_dointvec_minmax + }, + { 0 } +}; +static ctl_table ath_ath_table[] = { + { .ctl_name = DEV_ATH, + .procname = "ath", + .mode = 0555, + .child = ath_static_sysctls + }, { 0 } +}; +static ctl_table ath_root_table[] = { + { .ctl_name = CTL_DEV, + .procname = "dev", + .mode = 0555, + .child = ath_ath_table + }, { 0 } +}; +static struct ctl_table_header *ath_sysctl_header; + +static int __init init_ath_pci(void) +{ + int ret; + + ret = pci_register_driver(&ath_pci_drv_id); + if (ret) { + printk(KERN_ERR "ath_pci: can't register pci driver\n"); + return ret; + } + ath_sysctl_header = register_sysctl_table(ath_root_table); + + return 0; +} + +static void __exit exit_ath_pci(void) +{ + if (ath_sysctl_header) + unregister_sysctl_table(ath_sysctl_header); + pci_unregister_driver(&ath_pci_drv_id); +} + +module_init(init_ath_pci); +module_exit(exit_ath_pci); + +MODULE_AUTHOR("Jiri Slaby"); +MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards."); +MODULE_SUPPORTED_DEVICE("Atheros WLAN cards"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION(ATH_PCI_VERSION " (EXPERIMENTAL)"); diff --git a/ath5k_base.h b/ath5k_base.h new file mode 100644 index 0000000..26a8126 --- /dev/null +++ b/ath5k_base.h @@ -0,0 +1,301 @@ +/*- + * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.20 2005/01/24 20:31:24 sam Exp $ + */ + +/* + * Defintions for the Atheros Wireless LAN controller driver. + */ +#ifndef _DEV_ATH_ATHVAR_H +#define _DEV_ATH_ATHVAR_H + +#include +#include +#include +#include + +#include "ath5k_hw.h" + +/* Set this to 1 to disable regulatory domain restrictions for channel tests. + * WARNING: This is for debuging only and has side effects (eg. scan takes too + * long and results timeouts). It's also illegal to tune to some of the + * supported frequencies in some countries, so use this at your own risk, + * you've been warned. */ +#define CHAN_DEBUG 0 + +#define ATH_TIMEOUT 1000 + +#define ATH_LONG_CALIB 30 /* seconds */ +#define ATH_SHORT_CALIB 1 + +/* + * Maximum acceptable MTU + * MAXFRAMEBODY - WEP - QOS - RSN/WPA: + * 2312 - 8 - 2 - 12 = 2290 + */ +#define ATH_MAX_MTU 2290 +#define ATH_MIN_MTU 32 + +#define ATH_RXBUF 40 /* number of RX buffers */ +#define ATH_TXBUF 200 /* number of TX buffers */ +#define ATH_TXDESC 1 /* number of descriptors per buffer */ +#define ATH_BCBUF 1 /* number of beacon buffers */ +#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ +#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ + +#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ +#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ +#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ + +#define ATH_RSSI_LPF_LEN 10 +#define ATH_RSSI_DUMMY_MARKER 0x127 +#define ATH_EP_MUL(x, mul) ((x) * (mul)) +#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), AR5K_RSSI_EP_MULTIPLIER)) +#define ATH_LPF_RSSI(x, y, len) \ + ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) +#define ATH_RSSI_LPF(x, y) do { \ + if ((y) >= -20) \ + x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ +} while (0) + +struct ath_buf { + struct list_head list; + unsigned int flags; /* tx descriptor flags */ + struct ath_desc *desc; /* virtual addr of desc */ + dma_addr_t daddr; /* physical addr of desc */ + struct sk_buff *skb; /* skbuff for buf */ + dma_addr_t skbaddr;/* physical addr of skb data */ + struct ieee80211_tx_control ctl; +}; + +/* + * Data transmit queue state. One of these exists for each + * hardware transmit queue. Packets sent to us from above + * are assigned to queues based on their priority. Not all + * devices support a complete set of hardware transmit queues. + * For those devices the array sc_ac2q will map multiple + * priorities to fewer hardware queues (typically all to one + * hardware queue). + */ +struct ath_txq { + unsigned int qnum; /* hardware q number */ + u32 *link; /* link ptr in last TX desc */ + struct list_head q; /* transmit queue */ + spinlock_t lock; /* lock on q and link */ + bool setup; +}; + +struct ath_stats { + __u32 ast_watchdog; /* device reset by watchdog */ + __u32 ast_hardware; /* fatal hardware error interrupts */ + __u32 ast_bmiss; /* beacon miss interrupts */ + __u32 ast_bstuck; /* beacon stuck interrupts */ + __u32 ast_rxorn; /* rx overrun interrupts */ + __u32 ast_rxeol; /* rx eol interrupts */ + __u32 ast_txurn; /* tx underrun interrupts */ + __u32 ast_mib; /* mib interrupts */ + __u32 ast_intrcoal; /* interrupts coalesced */ + __u32 ast_tx_packets; /* packet sent on the interface */ + __u32 ast_tx_mgmt; /* management frames transmitted */ + __u32 ast_tx_discard; /* frames discarded prior to assoc */ + __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ + __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ + __u32 ast_tx_encap; /* tx encapsulation failed */ + __u32 ast_tx_nonode; /* tx failed 'cuz no node */ + __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ + __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ + __u32 ast_tx_linear; /* tx linearized to cluster */ + __u32 ast_tx_nodata; /* tx discarded empty frame */ + __u32 ast_tx_busdma; /* tx failed for dma resrcs */ + __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ + __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ + __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ + __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ + __u32 ast_tx_longretry;/* tx on-chip retries (long) */ + __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ + __u32 ast_tx_noack; /* tx frames with no ack marked */ + __u32 ast_tx_rts; /* tx frames with rts enabled */ + __u32 ast_tx_cts; /* tx frames with cts enabled */ + __u32 ast_tx_shortpre;/* tx frames with short preamble */ + __u32 ast_tx_altrate; /* tx frames with alternate rate */ + __u32 ast_tx_protect; /* tx frames with protection */ + __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ + __u32 ast_tx_ctsext; /* tx frames with cts extension */ + __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ + __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ + __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ + __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ + __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ + __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ + __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ + __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ + __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ + __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ + __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ + __u32 ast_rx_packets; /* packet recv on the interface */ + __u32 ast_rx_mgt; /* management frames received */ + __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ + __s8 ast_tx_rssi; /* tx rssi of last ack */ + __s8 ast_rx_rssi; /* rx rssi from histogram */ + __u32 ast_be_xmit; /* beacons transmitted */ + __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ + __u32 ast_per_cal; /* periodic calibration calls */ + __u32 ast_per_calfail;/* periodic calibration failed */ + __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ + __u32 ast_rate_calls; /* rate control checks */ + __u32 ast_rate_raise; /* rate control raised xmit rate */ + __u32 ast_rate_drop; /* rate control dropped xmit rate */ + __u32 ast_ant_defswitch;/* rx/default antenna switches */ + __u32 ast_ant_txswitch;/* tx antenna switches */ + __u32 ast_ant_rx[8]; /* rx frames with antenna */ + __u32 ast_ant_tx[8]; /* tx frames with antenna */ +}; + +#if CHAN_DEBUG +#define ATH_CHAN_MAX (26+26+26+200+200) +#else +#define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */ +#endif + +struct ath_softc { + struct pci_dev *pdev; /* for dma mapping */ + void __iomem *iobase; /* address of the device */ + struct mutex lock; /* dev-level lock */ + struct ath_stats stats; /* private statistics */ + struct ieee80211_tx_queue_stats tx_stats; + struct ieee80211_low_level_stats ll_stats; + struct ieee80211_hw *hw; /* IEEE 802.11 common */ + struct ieee80211_hw_mode modes[NUM_IEEE80211_MODES]; + struct ieee80211_channel channels[ATH_CHAN_MAX]; + struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_IEEE80211_MODES]; + enum ieee80211_if_types opmode; + struct ath_hw *ah; /* Atheros HW */ + + int debug; + + struct ath_buf *bufptr; /* allocated buffer ptr */ + struct ath_desc *desc; /* TX/RX descriptors */ + dma_addr_t desc_daddr; /* DMA (physical) address */ + size_t desc_len; /* size of TX/RX descriptors */ + u16 cachelsz; /* cache line size */ +#ifdef UNUSED + void (*sc_setdefantenna)(struct ath_softc *, u_int); +#endif + unsigned int invalid : 1, /* disable hardware accesses */ + mrretry : 1, /* multi-rate retry support */ + promisc : 1; +#ifdef UNUSED + sc_diversity : 1,/* enable rx diversity */ + sc_hasveol : 1, /* tx VEOL support */ + sc_mcastkey: 1, /* mcast key cache search */ + sc_hasclrkey:1; /* CLR key supported */ + /* rate tables */ +#endif + unsigned int curmode; /* current phy mode */ + struct ieee80211_channel *curchan; /* current h/w channel */ + + int iface_id; /* add/remove_interface id */ + + struct { + u8 rxflags; /* radiotap rx flags */ + u8 txflags; /* radiotap tx flags */ + u16 ledon; /* softled on time */ + u16 ledoff; /* softled off time */ + } hwmap[32]; /* h/w rate ix mappings */ +#ifdef UNUSED + u8 sc_protrix; /* protection rate index */ + u_int sc_txantenna; /* tx antenna (fixed or auto) */ +#endif + enum ath5k_int imask; /* interrupt mask copy */ + + DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ + + u8 bssidmask[ETH_ALEN]; + + unsigned int led_pin, /* GPIO pin for driving LED */ + led_on, /* pin setting for LED on */ + led_off, /* off time for current blink */ + led_blinking: 1,/* LED blink operation active */ + led_endblink: 1,/* finish LED blink operation */ + led_soft: 1; /* enable LED gpio status */ + struct timer_list led_tim; /* led off timer */ + u8 led_rxrate; /* current rx rate for LED */ + u8 led_txrate; /* current tx rate for LED */ + + struct tasklet_struct restq; /* reset tasklet */ + + unsigned int rxbufsize; /* rx size based on mtu */ + struct list_head rxbuf; /* receive buffer */ + spinlock_t rxbuflock; + u32 *rxlink; /* link ptr in last RX desc */ + struct tasklet_struct rxtq; /* rx intr tasklet */ +#ifdef UNUSED + u8 sc_defant; /* current default antenna */ + u8 sc_rxotherant; /* rx's on non-default antenna*/ +#endif + struct list_head txbuf; /* transmit buffer */ + spinlock_t txbuflock; + unsigned int txbuf_len; /* buf count in txbuf list */ + struct ath_txq txqs[2]; /* beacon and tx */ +#ifdef UNUSED + struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ +#endif + struct ath_txq *txq; /* beacon and tx*/ + struct tasklet_struct txtq; /* tx intr tasklet */ + + struct ath_buf *bbuf; /* beacon buffer */ + unsigned int bhalq, /* HAL q for outgoing beacons */ + bmisscount, /* missed beacon transmits */ + bintval; /* beacon interval */ +#ifdef BEACON + u32 sc_ant_tx[8]; /* recent tx frames/antenna */ + struct ath_txq *cabq; /* tx q for cab frames */ + + struct tasklet_struct bmisstq; /* bmiss intr tasklet */ +#endif +#ifdef UNUSED + struct ctl_table_header *sc_sysctl_header; + struct ctl_table *sc_sysctls; +#endif + struct timer_list calib_tim; /* calibration timer */ +}; + +#define ath5k_hw_hasbssidmask(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) +#define ath5k_hw_hasveol(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) + +#endif commit e6f01ced4b546b08001ab049ac09dd600a0126c6 Author: Jiri Slaby Date: Sat Aug 4 08:16:22 2007 +0200 revert 307af1838f7d3ac4127742ac8c988ce347e05140 diff --git a/ath5k.h b/ath5k.h new file mode 100644 index 0000000..c5e9cbe --- /dev/null +++ b/ath5k.h @@ -0,0 +1,1053 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _AR5K_H +#define _AR5K_H + +/* Set this to 1 to disable regulatory domain restrictions for channel tests. + * WARNING: This is for debuging only and has side effects (eg. scan takes too + * long and results timeouts). It's also illegal to tune to some of the + * supported frequencies in some countries, so use this at your own risk, + * you've been warned. */ +#define CHAN_DEBUG 0 + +/* Uncomment this for debuging (warning that it results in TOO much output) */ +/*#define AR5K_DEBUG 1 */ + +#include +#include + +#include "ath5k_hw.h" +#include "ath5k_regdom.h" + +/* PCI IDs */ +#ifndef PCI_VENDOR_ID_ATHEROS +#define PCI_VENDOR_ID_ATHEROS 0x168c +#endif +#ifndef PCI_VENDOR_ID_3COM_2 +#define PCI_VENDOR_ID_3COM_2 0xa727 +#endif + +#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ +#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ +#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ +#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ +#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ +#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ +#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ +#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ + +/****************************\ + GENERIC DRIVER DEFINITIONS +\****************************/ + +#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) +#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) +#ifdef AR5K_DEBUG +#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) +#else +#define AR5K_TRACE +#endif +#define howmany(x, y) (((x)+((y)-1))/(y)) + +/* + * Some tuneable values (these should be changeable by the user) + */ +#define AR5K_TUNE_DMA_BEACON_RESP 2 +#define AR5K_TUNE_SW_BEACON_RESP 10 +#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 +#define AR5K_TUNE_RADAR_ALERT false +#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 +#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) +#define AR5K_TUNE_RSSI_THRES 1792 +#define AR5K_TUNE_REGISTER_TIMEOUT 20000 +#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 +#define AR5K_TUNE_BEACON_INTERVAL 100 +#define AR5K_TUNE_AIFS 2 +#define AR5K_TUNE_AIFS_11B 2 +#define AR5K_TUNE_AIFS_XR 0 +#define AR5K_TUNE_CWMIN 15 +#define AR5K_TUNE_CWMIN_11B 31 +#define AR5K_TUNE_CWMIN_XR 3 +#define AR5K_TUNE_CWMAX 1023 +#define AR5K_TUNE_CWMAX_11B 1023 +#define AR5K_TUNE_CWMAX_XR 7 +#define AR5K_TUNE_NOISE_FLOOR -72 +#define AR5K_TUNE_MAX_TXPOWER 60 +#define AR5K_TUNE_DEFAULT_TXPOWER 30 +#define AR5K_TUNE_TPC_TXPOWER true +#define AR5K_TUNE_ANT_DIVERSITY true +#define AR5K_TUNE_HWTXTRIES 4 + +/* token to use for aifs, cwmin, cwmax in MadWiFi */ +#define AR5K_TXQ_USEDEFAULT ((u32) -1) + +/* GENERIC CHIPSET DEFINITIONS */ + +/* MAC Chips */ +enum ath5k_version { + AR5K_AR5210 = 0, + AR5K_AR5211 = 1, + AR5K_AR5212 = 2, +}; + +/* PHY Chips */ +enum ath5k_radio { + AR5K_RF5110 = 0, + AR5K_RF5111 = 1, + AR5K_RF5112 = 2, +}; + +/* + * Common silicon revision/version values + */ +enum ath5k_srev_type { + AR5K_VERSION_VER, + AR5K_VERSION_REV, + AR5K_VERSION_RAD, + AR5K_VERSION_DEV +}; + +struct ath5k_srev_name { + const char *sr_name; + enum ath5k_srev_type sr_type; + u_int sr_val; +}; + +#define AR5K_SREV_NAME { \ + { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ + { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ + { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ + { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ + { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ + { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ + { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ + { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ + { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ + { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ + { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ + { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ + { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ + { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ + { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ + { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ + { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ + { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ + { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ + { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ +} + +#define AR5K_SREV_UNKNOWN 0xffff + +#define AR5K_SREV_VER_AR5210 0x00 +#define AR5K_SREV_VER_AR5311 0x10 +#define AR5K_SREV_VER_AR5311A 0x20 +#define AR5K_SREV_VER_AR5311B 0x30 +#define AR5K_SREV_VER_AR5211 0x40 +#define AR5K_SREV_VER_AR5212 0x50 +#define AR5K_SREV_VER_AR5213 0x55 +#define AR5K_SREV_VER_UNSUPP 0x60 + +#define AR5K_SREV_RAD_5110 0x00 +#define AR5K_SREV_RAD_5111 0x10 +#define AR5K_SREV_RAD_5111A 0x15 +#define AR5K_SREV_RAD_2111 0x20 +#define AR5K_SREV_RAD_5112 0x30 +#define AR5K_SREV_RAD_5112A 0x35 +#define AR5K_SREV_RAD_2112 0x40 +#define AR5K_SREV_RAD_2112A 0x45 +#define AR5K_SREV_RAD_UNSUPP 0x50 + + +/* IEEE defs */ + +#define IEEE80211_MAX_LEN 2500 + +#define MAX_PDU_LENGTH IEEE80211_MAX_LEN +#define MODULATION_CCK IEEE80211_RATE_CCK +#define MODULATION_OFDM IEEE80211_RATE_OFDM +#define MODULATION_TURBO IEEE80211_RATE_TURBO +#define MODULATION_XR 0x00000200 /*XR thingie*/ +#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ + +#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code + enables short preamble, see ar5212_reg.h */ +#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) +#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 + +/****************\ + TX DEFINITIONS +\****************/ + +/* + * Tx Descriptor + */ +struct ath_tx_status { + u16 ts_seqnum; + u16 ts_tstamp; + u8 ts_status; + u8 ts_rate; + s8 ts_rssi; + u8 ts_shortretry; + u8 ts_longretry; + u8 ts_virtcol; + u8 ts_antenna; +}; + +#define AR5K_TXSTAT_ALTRATE 0x80 +#define AR5K_TXERR_XRETRY 0x01 +#define AR5K_TXERR_FILT 0x02 +#define AR5K_TXERR_FIFO 0x04 + +/* + * Queue types used to classify tx queues. + */ +enum ath5k_tx_queue { + AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ + AR5K_TX_QUEUE_DATA, /*A normal data queue*/ + AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ + AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ + AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ + AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ +}; + +#define AR5K_NUM_TX_QUEUES 10 +#define AR5K_NUM_TX_QUEUES_NOQCU 2 + +/* + * Queue syb-types to classify normal data queues. + * These are the 4 Access Categories as defined in + * WME spec. 0 is the lowest priority and 4 is the + * highest. Normal data that hasn't been classified + * goes to the Best Effort AC. + */ +enum ath5k_tx_queue_subtype { + AR5K_WME_AC_BK = 0, /*Background traffic*/ + AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ + AR5K_WME_AC_VI, /*Video traffic*/ + AR5K_WME_AC_VO, /*Voice traffic*/ +}; + +/* + * Queue ID numbers as returned by the HAL, each number + * represents a hw queue. If hw does not support hw queues + * (eg 5210) all data goes in one queue. These match + * d80211 definitions (net80211/MadWiFi don't use them). + */ +enum ath5k_tx_queue_id { + AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, + AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, + AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ + AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ + AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ + AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ + AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ + AR5K_TX_QUEUE_ID_UAPSD = 8, + AR5K_TX_QUEUE_ID_XR_DATA = 9, +}; + + +/* + * Flags to set hw queue's parameters... + */ +#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ +#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ +#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ +#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ +#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ +#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ +#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ +#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ + +/* + * A struct to hold tx queue's parameters + */ +struct ath5k_txq_info { + enum ath5k_tx_queue tqi_type; + enum ath5k_tx_queue_subtype tqi_subtype; + u16 tqi_flags; /* Tx queue flags (see above) */ + u32 tqi_aifs; /* Arbitrated Interframe Space */ + s32 tqi_cw_min; /* Minimum Contention Window */ + s32 tqi_cw_max; /* Maximum Contention Window */ + u32 tqi_cbr_period; /* Constant bit rate period */ + u32 tqi_cbr_overflow_limit; + u32 tqi_burst_time; + u32 tqi_ready_time; /* Not used */ + u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ +}; + +/* + * Transmit packet types. + * These are not fully used inside OpenHAL yet + */ +enum ath5k_pkt_type { + AR5K_PKT_TYPE_NORMAL = 0, + AR5K_PKT_TYPE_ATIM = 1, + AR5K_PKT_TYPE_PSPOLL = 2, + AR5K_PKT_TYPE_BEACON = 3, + AR5K_PKT_TYPE_PROBE_RESP = 4, + AR5K_PKT_TYPE_PIFS = 5, +}; + +/* + * TX power and TPC settings + */ +#define AR5K_TXPOWER_OFDM(_r, _v) ( \ + ((0 & 1) << ((_v) + 6)) | \ + (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ +) + +#define AR5K_TXPOWER_CCK(_r, _v) ( \ + (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ +) + +/* + * Used to compute TX times + */ +#define AR5K_CCK_SIFS_TIME 10 +#define AR5K_CCK_PREAMBLE_BITS 144 +#define AR5K_CCK_PLCP_BITS 48 + +#define AR5K_OFDM_SIFS_TIME 16 +#define AR5K_OFDM_PREAMBLE_TIME 20 +#define AR5K_OFDM_PLCP_BITS 22 +#define AR5K_OFDM_SYMBOL_TIME 4 + +#define AR5K_TURBO_SIFS_TIME 8 +#define AR5K_TURBO_PREAMBLE_TIME 14 +#define AR5K_TURBO_PLCP_BITS 22 +#define AR5K_TURBO_SYMBOL_TIME 4 + +#define AR5K_XR_SIFS_TIME 16 +#define AR5K_XR_PLCP_BITS 22 +#define AR5K_XR_SYMBOL_TIME 4 + +/* CCK */ +#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) + +#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ + ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ + (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) + +#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ + AR5K_CCK_PHY_TIME(_sp) + \ + ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ + AR5K_CCK_SIFS_TIME + +/* OFDM */ +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_OFDM_SYMBOL_TIME) / 1000) + +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ + AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ + (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) + +/* TURBO */ +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ + AR5K_TURBO_SYMBOL_TIME) / 1000) + +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ + AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ + AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ + (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) + +/* eXtendent Range (?)*/ +#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) + +#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_XR_SYMBOL_TIME) / 1000) + +#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ + AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ + (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) + +/* + * DMA size definitions (2^n+2) + */ +enum ath5k_dmasize { + AR5K_DMASIZE_4B = 0, + AR5K_DMASIZE_8B, + AR5K_DMASIZE_16B, + AR5K_DMASIZE_32B, + AR5K_DMASIZE_64B, + AR5K_DMASIZE_128B, + AR5K_DMASIZE_256B, + AR5K_DMASIZE_512B +}; + + +/****************\ + RX DEFINITIONS +\****************/ + +/* + * Rx Descriptor + */ +struct ath_rx_status { + u16 rs_datalen; + u16 rs_tstamp; + u8 rs_status; + u8 rs_phyerr; + s8 rs_rssi; + u8 rs_keyix; + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; +}; + +#define AR5K_RXERR_CRC 0x01 +#define AR5K_RXERR_PHY 0x02 +#define AR5K_RXERR_FIFO 0x04 +#define AR5K_RXERR_DECRYPT 0x08 +#define AR5K_RXERR_MIC 0x10 +#define AR5K_RXKEYIX_INVALID ((u8) - 1) +#define AR5K_TXKEYIX_INVALID ((u32) - 1) + +struct ath5k_mib_stats { + u32 ackrcv_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 beacons; +}; + + + + +/**************************\ + BEACON TIMERS DEFINITIONS +\**************************/ + +#define AR5K_BEACON_PERIOD 0x0000ffff +#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ +#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ + +/* + * Per-station beacon timer state. + */ +struct ath5k_beacon_state { + u32 bs_next_beacon; + u32 bs_next_dtim; + u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- + can also include the above flags*/ + u8 bs_dtim_period; + u8 bs_cfp_period; + u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with + a Point Coordination Function capable AP*/ + u16 bs_cfp_du_remain; + u16 bs_tim_offset; + u16 bs_sleep_duration; + u16 bs_bmiss_threshold; + u32 bs_cfp_next; +}; + + + + +/********************\ + COMMON DEFINITIONS +\********************/ + +/* + * Atheros descriptor + */ +struct ath_desc { + u32 ds_link; + u32 ds_data; + u32 ds_ctl0; + u32 ds_ctl1; + u32 ds_hw[4]; + + union { + struct ath_rx_status rx; + struct ath_tx_status tx; + } ds_us; + +#define ds_rxstat ds_us.rx +#define ds_txstat ds_us.tx + +} __packed; + +#define AR5K_RXDESC_INTREQ 0x0020 + +#define AR5K_TXDESC_CLRDMASK 0x0001 +#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ +#define AR5K_TXDESC_RTSENA 0x0004 +#define AR5K_TXDESC_CTSENA 0x0008 +#define AR5K_TXDESC_INTREQ 0x0010 +#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ + +#define AR5K_SLOT_TIME_9 396 +#define AR5K_SLOT_TIME_20 880 +#define AR5K_SLOT_TIME_MAX 0xffff + +/* channel_flags */ +#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ +#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ +#define CHANNEL_XR 0x0800 /* XR channel */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_108G CHANNEL_TG +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) + +#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ + CHANNEL_5GHZ | CHANNEL_TURBO) + +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) +#define CHANNEL_MODES CHANNEL_ALL + +/* + * Used internaly in OpenHAL (ar5211.c/ar5212.c + * for reset_tx_queue). Also see struct struct ieee80211_channel. + */ +#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) +#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) + +/* + * The following structure will be used to map 2GHz channels to + * 5GHz Atheros channels. + */ +struct ath5k_athchan_2ghz { + u32 a2_flags; + u16 a2_athchan; +}; + +/* + * Rate definitions + */ + +#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ + +struct ath5k_rate { + u8 valid; /* Valid for rate control */ + u32 modulation; + u16 rate_kbps; + u8 rate_code; /* Rate mapping for h/w descriptors */ + u8 dot11_rate; + u8 control_rate; + u16 lp_ack_duration;/* long preamble ACK duration */ + u16 sp_ack_duration;/* short preamble ACK duration*/ +}; + +struct ath5k_rate_table { + u16 rate_count; + u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ + struct ath5k_rate rates[AR5K_MAX_RATES]; +}; + +/* + * Rate tables... + */ +#define AR5K_RATES_11A { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_11B { 4, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ +} + +#define AR5K_RATES_11G { 12, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ + { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ + { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +#define AR5K_RATES_TURBO { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ + { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ + { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ + { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ + { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ + { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ + { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ + { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_XR { 12, { \ + 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_XR, 500, 7, 129, 0 }, \ + { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ + { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ + { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ + { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +/* + * Crypto definitions + */ + +#define AR5K_KEYCACHE_SIZE 8 + +/***********************\ + HW RELATED DEFINITIONS +\***********************/ + +/* + * Misc definitions + */ +#define AR5K_RSSI_EP_MULTIPLIER (1<<7) + +#define AR5K_ASSERT_ENTRY(_e, _s) do { \ + if (_e >= _s) \ + return (false); \ +} while (0) + + +struct ath5k_node_stats { + u32 ns_avgbrssi; /* average beacon rssi */ + u32 ns_avgrssi; /* average data rssi */ + u32 ns_avgtxrssi; /* average tx rssi */ +}; + +enum ath5k_ant_setting { + AR5K_ANT_VARIABLE = 0, /* variable by programming */ + AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ + AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ + AR5K_ANT_MAX = 3, +}; + +/* + * HAL interrupt abstraction + */ + +/* + * These are mapped to take advantage of some common bits + * between the MAC chips, to be able to set intr properties + * easier. Some of them are not used yet inside OpenHAL. + */ +enum ath5k_int { + AR5K_INT_RX = 0x00000001, + AR5K_INT_RXDESC = 0x00000002, + AR5K_INT_RXNOFRM = 0x00000008, + AR5K_INT_RXEOL = 0x00000010, + AR5K_INT_RXORN = 0x00000020, + AR5K_INT_TX = 0x00000040, + AR5K_INT_TXDESC = 0x00000080, + AR5K_INT_TXURN = 0x00000800, + AR5K_INT_MIB = 0x00001000, + AR5K_INT_RXPHY = 0x00004000, + AR5K_INT_RXKCM = 0x00008000, + AR5K_INT_SWBA = 0x00010000, + AR5K_INT_BMISS = 0x00040000, + AR5K_INT_BNR = 0x00100000, + AR5K_INT_GPIO = 0x01000000, + AR5K_INT_FATAL = 0x40000000, + AR5K_INT_GLOBAL = 0x80000000, + + /*A sum of all the common bits*/ + AR5K_INT_COMMON = AR5K_INT_RXNOFRM + | AR5K_INT_RXDESC + | AR5K_INT_RXEOL + | AR5K_INT_RXORN + | AR5K_INT_TXURN + | AR5K_INT_TXDESC + | AR5K_INT_MIB + | AR5K_INT_RXPHY + | AR5K_INT_RXKCM + | AR5K_INT_SWBA + | AR5K_INT_BMISS + | AR5K_INT_GPIO, + AR5K_INT_NOCARD = 0xffffffff /*Declare that the card + has been removed*/ +}; + +/* + * Power management + */ +enum ath5k_power_mode { + AR5K_PM_UNDEFINED = 0, + AR5K_PM_AUTO, + AR5K_PM_AWAKE, + AR5K_PM_FULL_SLEEP, + AR5K_PM_NETWORK_SLEEP, +}; + +/* + * These match net80211 definitions (not used in + * d80211). + */ +#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ +#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ +#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ +#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ +#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ + +/* GPIO-controlled software LED */ +#define AR5K_SOFTLED_PIN 0 +#define AR5K_SOFTLED_ON 0 +#define AR5K_SOFTLED_OFF 1 + +/* + * Chipset capabilities -see ath_hal_getcapability- + * get_capability function is not yet fully implemented + * in OpenHAL so most of these don't work yet... + */ +enum ath5k_capability_type { + AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ + AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ + AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ + AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ + AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ + AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ + AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ + AR5K_CAP_COMPRESSION = 8, /* Supports compression */ + AR5K_CAP_BURST = 9, /* Supports packet bursting */ + AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ + AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ + AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ + AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ + AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ + AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ + AR5K_CAP_XR = 16, /* Supports XR mode */ + AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ + AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ + AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ + AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ +}; + +struct ath5k_capabilities { + /* + * Supported PHY modes + * (ie. CHANNEL_A, CHANNEL_B, ...) + */ + DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); + + /* + * Frequency range (without regulation restrictions) + */ + struct { + u16 range_2ghz_min; + u16 range_2ghz_max; + u16 range_5ghz_min; + u16 range_5ghz_max; + } cap_range; + + /* + * Active regulation domain settings + */ + struct { + enum ath5k_regdom reg_current; + enum ath5k_regdom reg_hw; + } cap_regdomain; + + /* + * Values stored in the EEPROM (some of them...) + */ + struct ath5k_eeprom_info cap_eeprom; + + /* + * Queue information + */ + struct { + u8 q_tx_num; + } cap_queues; +}; + + +/***************************************\ + HARDWARE ABSTRACTION LAYER STRUCTURE +\***************************************/ + +/* + * Misc defines + */ + +#define AR5K_MAX_GPIO 10 +#define AR5K_MAX_RF_BANKS 8 + +struct ath_hw { + u32 ah_magic; + + void *ah_sc; + void __iomem *ah_sh; + enum ath5k_countrycode ah_country_code; + + enum ath5k_int ah_imr; + + enum ieee80211_if_types ah_op_mode; + enum ath5k_power_mode ah_power_mode; + struct ieee80211_channel ah_current_channel; + bool ah_turbo; + bool ah_calibration; + bool ah_running; + bool ah_single_chip; + enum ath5k_rfgain ah_rf_gain; + + u32 ah_mac_srev; + u16 ah_mac_version; + u16 ah_mac_revision; + u16 ah_phy_revision; + u16 ah_radio_5ghz_revision; + u16 ah_radio_2ghz_revision; + + enum ath5k_version ah_version; + enum ath5k_radio ah_radio; + u32 ah_phy; + + bool ah_5ghz; + bool ah_2ghz; + +#define ah_regdomain ah_capabilities.cap_regdomain.reg_current +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_modes ah_capabilities.cap_mode +#define ah_ee_version ah_capabilities.cap_eeprom.ee_version + + u32 ah_atim_window; + u32 ah_aifs; + u32 ah_cw_min; + u32 ah_cw_max; + bool ah_software_retry; + u32 ah_limit_tx_retries; + + u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + bool ah_ant_diversity; + + u8 ah_sta_id[ETH_ALEN]; + u8 ah_bssid[ETH_ALEN]; + + u32 ah_gpio[AR5K_MAX_GPIO]; + int ah_gpio_npins; + + struct ath5k_capabilities ah_capabilities; + + struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; + u32 ah_txq_interrupts; + + u32 *ah_rf_banks; + size_t ah_rf_banks_size; + struct ath5k_gain ah_gain; + u32 ah_offset[AR5K_MAX_RF_BANKS]; + + struct { + u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; + u16 txp_rates[AR5K_MAX_RATES]; + s16 txp_min, txp_max; + bool txp_tpc; + s16 txp_ofdm; + } ah_txpower; + + struct { + bool r_enabled; + int r_last_alert; + struct ieee80211_channel r_last_channel; + } ah_radar; + + /* + * Function pointers + */ + int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int); + bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int); + int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, + unsigned int, bool, bool); + int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); + int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *); +}; + +/* + * Prototypes + */ +/* Attach/Detach Functions */ +struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); +const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); +void ath5k_hw_detach(struct ath_hw *hal); +/* Reset Functions */ +int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); +/* Power management functions */ +int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); +enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); +/* DMA Related Functions */ +void ath5k_hw_start_rx(struct ath_hw *hal); +int ath5k_hw_stop_rx_dma(struct ath_hw *hal); +u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); +void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); +int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); +int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); +bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); +/* Interrupt handling */ +bool ath5k_hw_is_intr_pending(struct ath_hw *hal); +int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); +enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); +void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); +/* EEPROM access functions */ +int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); +/* Protocol Control Unit Functions */ +void ath5k_hw_set_opmode(struct ath_hw *hal); +/* BSSID Functions */ +void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); +bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); +void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); +bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); +/* Receive start/stop functions */ +void ath5k_hw_start_rx_pcu(struct ath_hw *hal); +void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); +/* RX Filter functions */ +void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); +bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); +bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); +u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); +void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); +/* Beacon related functions */ +u32 ath5k_hw_get_tsf32(struct ath_hw *hal); +u64 ath5k_hw_get_tsf64(struct ath_hw *hal); +void ath5k_hw_reset_tsf(struct ath_hw *hal); +void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); +void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); +void ath5k_hw_reset_beacon(struct ath_hw *hal); +bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); +void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); +/* ACK/CTS Timeouts */ +bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); +bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); +unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); +/* Key table (WEP) functions */ +int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); +int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); +int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); +int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); +/* Queue Control Unit, DFS Control Unit Functions */ +int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); +int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); +int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); +void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); +int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); +u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); +bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); +unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); +/* Hardware Descriptor Functions */ +/* RX Descriptor */ +int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); +/* GPIO Functions */ +void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); +int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); +int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); +u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); +int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); +void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); +/* Regulatory Domain/Channels Setup */ +bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags); +u16 ath5k_get_regdomain(struct ath_hw *hal); +/* PHY/RF access functions */ +int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); +bool ath5k_hw_phy_disable(struct ath_hw *hal); +void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); +unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); +bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); +enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); +/* Misc functions */ +int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); +void ath5k_hw_dump_state(struct ath_hw *hal); +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); +bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); +bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); +bool ath5k_hw_disable_pspoll(struct ath_hw *hal); +#endif /* _AR5K_H */ diff --git a/ath5k_base.h b/ath5k_base.h index 26a8126..64d1ecf 100644 --- a/ath5k_base.h +++ b/ath5k_base.h @@ -47,14 +47,7 @@ #include #include -#include "ath5k_hw.h" - -/* Set this to 1 to disable regulatory domain restrictions for channel tests. - * WARNING: This is for debuging only and has side effects (eg. scan takes too - * long and results timeouts). It's also illegal to tune to some of the - * supported frequencies in some countries, so use this at your own risk, - * you've been warned. */ -#define CHAN_DEBUG 0 +#include "ath5k.h" #define ATH_TIMEOUT 1000 diff --git a/ath5k_hw.c b/ath5k_hw.c index 541228e..fe37c93 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -22,7 +22,7 @@ #include -#include "ath5k_hw.h" +#include "ath5k.h" #include "ath5k_reg.h" /*Rate tables*/ diff --git a/ath5k_hw.h b/ath5k_hw.h index d878ea6..cd4fbad 100644 --- a/ath5k_hw.h +++ b/ath5k_hw.h @@ -17,48 +17,6 @@ * $Id$ */ -#include - -#include "ath5k_regdom.h" - -/* Uncomment this for debuging (warning that it results in TOO much output) */ -/*#define AR5K_DEBUG 1 */ - -/* PCI IDs */ -#ifndef PCI_VENDOR_ID_ATHEROS -#define PCI_VENDOR_ID_ATHEROS 0x168c -#endif -#ifndef PCI_VENDOR_ID_3COM_2 -#define PCI_VENDOR_ID_3COM_2 0xa727 -#endif - -#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ -#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ -#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ -#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ -#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ -#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ -#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV2 0x0052 /* AR5312 WMAC (AP31) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ -#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ -#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ -#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ - /* * Gain settings */ @@ -2193,986 +2151,3 @@ struct ath5k_ar5211_ini_rf { { 0x0000989c, { 0x0000125a, 0x0000129a } }, \ { 0x000098cc, { 0x0000000e, 0x0000000f } }, \ } - -/****************************\ - GENERIC DRIVER DEFINITIONS -\****************************/ - -#define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) -#define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) -#ifdef AR5K_DEBUG -#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) -#else -#define AR5K_TRACE -#endif -#define howmany(x, y) (((x)+((y)-1))/(y)) - -/* - * Some tuneable values (these should be changeable by the user) - */ -#define AR5K_TUNE_DMA_BEACON_RESP 2 -#define AR5K_TUNE_SW_BEACON_RESP 10 -#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 -#define AR5K_TUNE_RADAR_ALERT false -#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 -#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) -#define AR5K_TUNE_RSSI_THRES 1792 -#define AR5K_TUNE_REGISTER_TIMEOUT 20000 -#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 -#define AR5K_TUNE_BEACON_INTERVAL 100 -#define AR5K_TUNE_AIFS 2 -#define AR5K_TUNE_AIFS_11B 2 -#define AR5K_TUNE_AIFS_XR 0 -#define AR5K_TUNE_CWMIN 15 -#define AR5K_TUNE_CWMIN_11B 31 -#define AR5K_TUNE_CWMIN_XR 3 -#define AR5K_TUNE_CWMAX 1023 -#define AR5K_TUNE_CWMAX_11B 1023 -#define AR5K_TUNE_CWMAX_XR 7 -#define AR5K_TUNE_NOISE_FLOOR -72 -#define AR5K_TUNE_MAX_TXPOWER 60 -#define AR5K_TUNE_DEFAULT_TXPOWER 30 -#define AR5K_TUNE_TPC_TXPOWER true -#define AR5K_TUNE_ANT_DIVERSITY true -#define AR5K_TUNE_HWTXTRIES 4 - -/* token to use for aifs, cwmin, cwmax in MadWiFi */ -#define AR5K_TXQ_USEDEFAULT ((u32) -1) - -/* GENERIC CHIPSET DEFINITIONS */ - -/* MAC Chips */ -enum ath5k_version { - AR5K_AR5210 = 0, - AR5K_AR5211 = 1, - AR5K_AR5212 = 2, -}; - -/* PHY Chips */ -enum ath5k_radio { - AR5K_RF5110 = 0, - AR5K_RF5111 = 1, - AR5K_RF5112 = 2, -}; - -/* - * Common silicon revision/version values - */ -enum ath5k_srev_type { - AR5K_VERSION_VER, - AR5K_VERSION_REV, - AR5K_VERSION_RAD, - AR5K_VERSION_DEV -}; - -struct ath5k_srev_name { - const char *sr_name; - enum ath5k_srev_type sr_type; - u_int sr_val; -}; - -#define AR5K_SREV_NAME { \ - { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ - { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ - { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ - { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ - { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ - { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ - { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ - { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ - { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ - { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ - { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ - { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ - { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ - { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ - { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ - { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ - { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ - { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ - { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ - { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ -} - -#define AR5K_SREV_UNKNOWN 0xffff - -#define AR5K_SREV_VER_AR5210 0x00 -#define AR5K_SREV_VER_AR5311 0x10 -#define AR5K_SREV_VER_AR5311A 0x20 -#define AR5K_SREV_VER_AR5311B 0x30 -#define AR5K_SREV_VER_AR5211 0x40 -#define AR5K_SREV_VER_AR5212 0x50 -#define AR5K_SREV_VER_AR5213 0x55 -#define AR5K_SREV_VER_UNSUPP 0x60 - -#define AR5K_SREV_RAD_5110 0x00 -#define AR5K_SREV_RAD_5111 0x10 -#define AR5K_SREV_RAD_5111A 0x15 -#define AR5K_SREV_RAD_2111 0x20 -#define AR5K_SREV_RAD_5112 0x30 -#define AR5K_SREV_RAD_5112A 0x35 -#define AR5K_SREV_RAD_2112 0x40 -#define AR5K_SREV_RAD_2112A 0x45 -#define AR5K_SREV_RAD_UNSUPP 0x50 - - -/* IEEE defs */ - -#define IEEE80211_MAX_LEN 2500 - -#define MAX_PDU_LENGTH IEEE80211_MAX_LEN -#define MODULATION_CCK IEEE80211_RATE_CCK -#define MODULATION_OFDM IEEE80211_RATE_OFDM -#define MODULATION_TURBO IEEE80211_RATE_TURBO -#define MODULATION_XR 0x00000200 /*XR thingie*/ -#define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ - -#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code - enables short preamble, see ar5212_reg.h */ -#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) -#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 - -/****************\ - TX DEFINITIONS -\****************/ - -/* - * Tx Descriptor - */ -struct ath_tx_status { - u16 ts_seqnum; - u16 ts_tstamp; - u8 ts_status; - u8 ts_rate; - s8 ts_rssi; - u8 ts_shortretry; - u8 ts_longretry; - u8 ts_virtcol; - u8 ts_antenna; -}; - -#define AR5K_TXSTAT_ALTRATE 0x80 -#define AR5K_TXERR_XRETRY 0x01 -#define AR5K_TXERR_FILT 0x02 -#define AR5K_TXERR_FIFO 0x04 - -/* - * Queue types used to classify tx queues. - */ -enum ath5k_tx_queue { - AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ - AR5K_TX_QUEUE_DATA, /*A normal data queue*/ - AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ - AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ - AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ - AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ -}; - -#define AR5K_NUM_TX_QUEUES 10 -#define AR5K_NUM_TX_QUEUES_NOQCU 2 - -/* - * Queue syb-types to classify normal data queues. - * These are the 4 Access Categories as defined in - * WME spec. 0 is the lowest priority and 4 is the - * highest. Normal data that hasn't been classified - * goes to the Best Effort AC. - */ -enum ath5k_tx_queue_subtype { - AR5K_WME_AC_BK = 0, /*Background traffic*/ - AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ - AR5K_WME_AC_VI, /*Video traffic*/ - AR5K_WME_AC_VO, /*Voice traffic*/ -}; - -/* - * Queue ID numbers as returned by the HAL, each number - * represents a hw queue. If hw does not support hw queues - * (eg 5210) all data goes in one queue. These match - * d80211 definitions (net80211/MadWiFi don't use them). - */ -enum ath5k_tx_queue_id { - AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, - AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, - AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ - AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ - AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ - AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ - AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ - AR5K_TX_QUEUE_ID_UAPSD = 8, - AR5K_TX_QUEUE_ID_XR_DATA = 9, -}; - - -/* - * Flags to set hw queue's parameters... - */ -#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ -#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ -#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ -#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ -#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ -#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ -#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ -#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ - -/* - * A struct to hold tx queue's parameters - */ -struct ath5k_txq_info { - enum ath5k_tx_queue tqi_type; - enum ath5k_tx_queue_subtype tqi_subtype; - u16 tqi_flags; /* Tx queue flags (see above) */ - u32 tqi_aifs; /* Arbitrated Interframe Space */ - s32 tqi_cw_min; /* Minimum Contention Window */ - s32 tqi_cw_max; /* Maximum Contention Window */ - u32 tqi_cbr_period; /* Constant bit rate period */ - u32 tqi_cbr_overflow_limit; - u32 tqi_burst_time; - u32 tqi_ready_time; /* Not used */ - u32 tqi_comp_buffer;/* Compression Buffer's phys addr */ -}; - -/* - * Transmit packet types. - * These are not fully used inside OpenHAL yet - */ -enum ath5k_pkt_type { - AR5K_PKT_TYPE_NORMAL = 0, - AR5K_PKT_TYPE_ATIM = 1, - AR5K_PKT_TYPE_PSPOLL = 2, - AR5K_PKT_TYPE_BEACON = 3, - AR5K_PKT_TYPE_PROBE_RESP = 4, - AR5K_PKT_TYPE_PIFS = 5, -}; - -/* - * TX power and TPC settings - */ -#define AR5K_TXPOWER_OFDM(_r, _v) ( \ - ((0 & 1) << ((_v) + 6)) | \ - (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ -) - -#define AR5K_TXPOWER_CCK(_r, _v) ( \ - (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ -) - -/* - * Used to compute TX times - */ -#define AR5K_CCK_SIFS_TIME 10 -#define AR5K_CCK_PREAMBLE_BITS 144 -#define AR5K_CCK_PLCP_BITS 48 - -#define AR5K_OFDM_SIFS_TIME 16 -#define AR5K_OFDM_PREAMBLE_TIME 20 -#define AR5K_OFDM_PLCP_BITS 22 -#define AR5K_OFDM_SYMBOL_TIME 4 - -#define AR5K_TURBO_SIFS_TIME 8 -#define AR5K_TURBO_PREAMBLE_TIME 14 -#define AR5K_TURBO_PLCP_BITS 22 -#define AR5K_TURBO_SYMBOL_TIME 4 - -#define AR5K_XR_SIFS_TIME 16 -#define AR5K_XR_PLCP_BITS 22 -#define AR5K_XR_SYMBOL_TIME 4 - -/* CCK */ -#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) - -#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ - ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ - (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) - -#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ - AR5K_CCK_PHY_TIME(_sp) + \ - ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ - AR5K_CCK_SIFS_TIME - -/* OFDM */ -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_OFDM_SYMBOL_TIME) / 1000) - -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ - AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ - (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) - -/* TURBO */ -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ - AR5K_TURBO_SYMBOL_TIME) / 1000) - -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ - AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ - AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ - (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) - -/* eXtendent Range (?)*/ -#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) - -#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_XR_SYMBOL_TIME) / 1000) - -#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ - AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ - (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) - -/* - * DMA size definitions (2^n+2) - */ -enum ath5k_dmasize { - AR5K_DMASIZE_4B = 0, - AR5K_DMASIZE_8B, - AR5K_DMASIZE_16B, - AR5K_DMASIZE_32B, - AR5K_DMASIZE_64B, - AR5K_DMASIZE_128B, - AR5K_DMASIZE_256B, - AR5K_DMASIZE_512B -}; - - -/****************\ - RX DEFINITIONS -\****************/ - -/* - * Rx Descriptor - */ -struct ath_rx_status { - u16 rs_datalen; - u16 rs_tstamp; - u8 rs_status; - u8 rs_phyerr; - s8 rs_rssi; - u8 rs_keyix; - u8 rs_rate; - u8 rs_antenna; - u8 rs_more; -}; - -#define AR5K_RXERR_CRC 0x01 -#define AR5K_RXERR_PHY 0x02 -#define AR5K_RXERR_FIFO 0x04 -#define AR5K_RXERR_DECRYPT 0x08 -#define AR5K_RXERR_MIC 0x10 -#define AR5K_RXKEYIX_INVALID ((u8) - 1) -#define AR5K_TXKEYIX_INVALID ((u32) - 1) - -struct ath5k_mib_stats { - u32 ackrcv_bad; - u32 rts_bad; - u32 rts_good; - u32 fcs_bad; - u32 beacons; -}; - - - - -/**************************\ - BEACON TIMERS DEFINITIONS -\**************************/ - -#define AR5K_BEACON_PERIOD 0x0000ffff -#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ -#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ - -/* - * Per-station beacon timer state. - */ -struct ath5k_beacon_state { - u32 bs_next_beacon; - u32 bs_next_dtim; - u32 bs_interval; /*in TU's -see net80211/ieee80211_var.h- - can also include the above flags*/ - u8 bs_dtim_period; - u8 bs_cfp_period; - u16 bs_cfp_max_duration; /*if non-zero hw is setup to coexist with - a Point Coordination Function capable AP*/ - u16 bs_cfp_du_remain; - u16 bs_tim_offset; - u16 bs_sleep_duration; - u16 bs_bmiss_threshold; - u32 bs_cfp_next; -}; - - - - -/********************\ - COMMON DEFINITIONS -\********************/ - -/* - * Atheros descriptor - */ -struct ath_desc { - u32 ds_link; - u32 ds_data; - u32 ds_ctl0; - u32 ds_ctl1; - u32 ds_hw[4]; - - union { - struct ath_rx_status rx; - struct ath_tx_status tx; - } ds_us; - -#define ds_rxstat ds_us.rx -#define ds_txstat ds_us.tx - -} __packed; - -#define AR5K_RXDESC_INTREQ 0x0020 - -#define AR5K_TXDESC_CLRDMASK 0x0001 -#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ -#define AR5K_TXDESC_RTSENA 0x0004 -#define AR5K_TXDESC_CTSENA 0x0008 -#define AR5K_TXDESC_INTREQ 0x0010 -#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ - -#define AR5K_SLOT_TIME_9 396 -#define AR5K_SLOT_TIME_20 880 -#define AR5K_SLOT_TIME_MAX 0xffff - -/* channel_flags */ -#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ -#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ -#define CHANNEL_CCK 0x0020 /* CCK channel */ -#define CHANNEL_OFDM 0x0040 /* OFDM channel */ -#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ -#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ -#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ -#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ -#define CHANNEL_XR 0x0800 /* XR channel */ - -#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) -#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) -#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) -#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_108A CHANNEL_T -#define CHANNEL_108G CHANNEL_TG -#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) - -#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ - CHANNEL_5GHZ | CHANNEL_TURBO) - -#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) -#define CHANNEL_MODES CHANNEL_ALL - -/* - * Used internaly in OpenHAL (ar5211.c/ar5212.c - * for reset_tx_queue). Also see struct struct ieee80211_channel. - */ -#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) -#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) - -/* - * The following structure will be used to map 2GHz channels to - * 5GHz Atheros channels. - */ -struct ath5k_athchan_2ghz { - u32 a2_flags; - u16 a2_athchan; -}; - -/* - * Rate definitions - */ - -#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ - -struct ath5k_rate { - u8 valid; /* Valid for rate control */ - u32 modulation; - u16 rate_kbps; - u8 rate_code; /* Rate mapping for h/w descriptors */ - u8 dot11_rate; - u8 control_rate; - u16 lp_ack_duration;/* long preamble ACK duration */ - u16 sp_ack_duration;/* short preamble ACK duration*/ -}; - -struct ath5k_rate_table { - u16 rate_count; - u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ - struct ath5k_rate rates[AR5K_MAX_RATES]; -}; - -/* - * Rate tables... - */ -#define AR5K_RATES_11A { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_11B { 4, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ -} - -#define AR5K_RATES_11G { 12, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ - { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ - { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -#define AR5K_RATES_TURBO { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ - { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ - { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ - { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ - { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ - { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ - { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ - { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_XR { 12, { \ - 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_XR, 500, 7, 129, 0 }, \ - { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ - { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ - { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ - { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -/* - * Crypto definitions - */ - -#define AR5K_KEYCACHE_SIZE 8 - - -/***********************\ - HW RELATED DEFINITIONS -\***********************/ - -/* - * Misc definitions - */ -#define AR5K_RSSI_EP_MULTIPLIER (1<<7) - -#define AR5K_ASSERT_ENTRY(_e, _s) do { \ - if (_e >= _s) \ - return (false); \ -} while (0) - - -struct ath5k_node_stats { - u32 ns_avgbrssi; /* average beacon rssi */ - u32 ns_avgrssi; /* average data rssi */ - u32 ns_avgtxrssi; /* average tx rssi */ -}; - -enum ath5k_ant_setting { - AR5K_ANT_VARIABLE = 0, /* variable by programming */ - AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ - AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ - AR5K_ANT_MAX = 3, -}; - -/* - * HAL interrupt abstraction - */ - -/* - * These are mapped to take advantage of some common bits - * between the MAC chips, to be able to set intr properties - * easier. Some of them are not used yet inside OpenHAL. - */ -enum ath5k_int { - AR5K_INT_RX = 0x00000001, - AR5K_INT_RXDESC = 0x00000002, - AR5K_INT_RXNOFRM = 0x00000008, - AR5K_INT_RXEOL = 0x00000010, - AR5K_INT_RXORN = 0x00000020, - AR5K_INT_TX = 0x00000040, - AR5K_INT_TXDESC = 0x00000080, - AR5K_INT_TXURN = 0x00000800, - AR5K_INT_MIB = 0x00001000, - AR5K_INT_RXPHY = 0x00004000, - AR5K_INT_RXKCM = 0x00008000, - AR5K_INT_SWBA = 0x00010000, - AR5K_INT_BMISS = 0x00040000, - AR5K_INT_BNR = 0x00100000, - AR5K_INT_GPIO = 0x01000000, - AR5K_INT_FATAL = 0x40000000, - AR5K_INT_GLOBAL = 0x80000000, - - /*A sum of all the common bits*/ - AR5K_INT_COMMON = AR5K_INT_RXNOFRM - | AR5K_INT_RXDESC - | AR5K_INT_RXEOL - | AR5K_INT_RXORN - | AR5K_INT_TXURN - | AR5K_INT_TXDESC - | AR5K_INT_MIB - | AR5K_INT_RXPHY - | AR5K_INT_RXKCM - | AR5K_INT_SWBA - | AR5K_INT_BMISS - | AR5K_INT_GPIO, - AR5K_INT_NOCARD = 0xffffffff /*Declare that the card - has been removed*/ -}; - -/* - * Power management - */ -enum ath5k_power_mode { - AR5K_PM_UNDEFINED = 0, - AR5K_PM_AUTO, - AR5K_PM_AWAKE, - AR5K_PM_FULL_SLEEP, - AR5K_PM_NETWORK_SLEEP, -}; - -/* - * These match net80211 definitions (not used in - * d80211). - */ -#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ -#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ -#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ -#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ -#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ - -/* GPIO-controlled software LED */ -#define AR5K_SOFTLED_PIN 0 -#define AR5K_SOFTLED_ON 0 -#define AR5K_SOFTLED_OFF 1 - -/* - * Chipset capabilities -see ath_hal_getcapability- - * get_capability function is not yet fully implemented - * in OpenHAL so most of these don't work yet... - */ -enum ath5k_capability_type { - AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ - AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ - AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ - AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ - AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ - AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ - AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ - AR5K_CAP_COMPRESSION = 8, /* Supports compression */ - AR5K_CAP_BURST = 9, /* Supports packet bursting */ - AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ - AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ - AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ - AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ - AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ - AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ - AR5K_CAP_XR = 16, /* Supports XR mode */ - AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ - AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ - AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ - AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ -}; - -struct ath5k_capabilities { - /* - * Supported PHY modes - * (ie. CHANNEL_A, CHANNEL_B, ...) - */ - DECLARE_BITMAP(cap_mode, NUM_IEEE80211_MODES); - - /* - * Frequency range (without regulation restrictions) - */ - struct { - u16 range_2ghz_min; - u16 range_2ghz_max; - u16 range_5ghz_min; - u16 range_5ghz_max; - } cap_range; - - /* - * Active regulation domain settings - */ - struct { - enum ath5k_regdom reg_current; - enum ath5k_regdom reg_hw; - } cap_regdomain; - - /* - * Values stored in the EEPROM (some of them...) - */ - struct ath5k_eeprom_info cap_eeprom; - - /* - * Queue information - */ - struct { - u8 q_tx_num; - } cap_queues; -}; - - -/***************************************\ - HARDWARE ABSTRACTION LAYER STRUCTURE -\***************************************/ - -/* - * Misc defines - */ - -#define AR5K_MAX_GPIO 10 -#define AR5K_MAX_RF_BANKS 8 - -struct ath_hw { - u32 ah_magic; - - void *ah_sc; - void __iomem *ah_sh; - enum ath5k_countrycode ah_country_code; - - enum ath5k_int ah_imr; - - enum ieee80211_if_types ah_op_mode; - enum ath5k_power_mode ah_power_mode; - struct ieee80211_channel ah_current_channel; - bool ah_turbo; - bool ah_calibration; - bool ah_running; - bool ah_single_chip; - enum ath5k_rfgain ah_rf_gain; - - u32 ah_mac_srev; - u16 ah_mac_version; - u16 ah_mac_revision; - u16 ah_phy_revision; - u16 ah_radio_5ghz_revision; - u16 ah_radio_2ghz_revision; - - enum ath5k_version ah_version; - enum ath5k_radio ah_radio; - u32 ah_phy; - - bool ah_5ghz; - bool ah_2ghz; - -#define ah_regdomain ah_capabilities.cap_regdomain.reg_current -#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw -#define ah_modes ah_capabilities.cap_mode -#define ah_ee_version ah_capabilities.cap_eeprom.ee_version - - u32 ah_atim_window; - u32 ah_aifs; - u32 ah_cw_min; - u32 ah_cw_max; - bool ah_software_retry; - u32 ah_limit_tx_retries; - - u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; - bool ah_ant_diversity; - - u8 ah_sta_id[ETH_ALEN]; - u8 ah_bssid[ETH_ALEN]; - - u32 ah_gpio[AR5K_MAX_GPIO]; - int ah_gpio_npins; - - struct ath5k_capabilities ah_capabilities; - - struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; - u32 ah_txq_interrupts; - - u32 *ah_rf_banks; - size_t ah_rf_banks_size; - struct ath5k_gain ah_gain; - u32 ah_offset[AR5K_MAX_RF_BANKS]; - - struct { - u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; - u16 txp_rates[AR5K_MAX_RATES]; - s16 txp_min, txp_max; - bool txp_tpc; - s16 txp_ofdm; - } ah_txpower; - - struct { - bool r_enabled; - int r_last_alert; - struct ieee80211_channel r_last_channel; - } ah_radar; - - /* - * Function pointers - */ - int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int); - bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int); - int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *, - unsigned int, bool, bool); - int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *); - int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *); -}; - -/* - * Prototypes - */ -/* Attach/Detach Functions */ -struct ath_hw *ath5k_hw_attach(u16 device, u8 macversion, void *sc, void __iomem *sh); -const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal, unsigned int mode); -void ath5k_hw_detach(struct ath_hw *hal); -/* Reset Functions */ -int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel); -/* Power management functions */ -int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); -enum ath5k_power_mode ath5k_hw_get_power_mode(struct ath_hw *hal); -/* DMA Related Functions */ -void ath5k_hw_start_rx(struct ath_hw *hal); -int ath5k_hw_stop_rx_dma(struct ath_hw *hal); -u32 ath5k_hw_get_rx_buf(struct ath_hw *hal); -void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr); -int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue); -u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue); -int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr); -bool ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase); -/* Interrupt handling */ -bool ath5k_hw_is_intr_pending(struct ath_hw *hal); -int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask); -enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int new_mask); -void ath5k_hw_radar_alert(struct ath_hw *hal, bool enable); -/* EEPROM access functions */ -int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain); -/* Protocol Control Unit Functions */ -void ath5k_hw_set_opmode(struct ath_hw *hal); -/* BSSID Functions */ -void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); -bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); -void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); -bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); -/* Receive start/stop functions */ -void ath5k_hw_start_rx_pcu(struct ath_hw *hal); -void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); -/* RX Filter functions */ -void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1); -bool ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index); -bool ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index); -u32 ath5k_hw_get_rx_filter(struct ath_hw *hal); -void ath5k_hw_set_rx_filter(struct ath_hw *hal, u32 filter); -/* Beacon related functions */ -u32 ath5k_hw_get_tsf32(struct ath_hw *hal); -u64 ath5k_hw_get_tsf64(struct ath_hw *hal); -void ath5k_hw_reset_tsf(struct ath_hw *hal); -void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval); -void ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state); -void ath5k_hw_reset_beacon(struct ath_hw *hal); -bool ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr); -void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics); -/* ACK/CTS Timeouts */ -bool ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout); -unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal); -bool ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout); -unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal); -/* Key table (WEP) functions */ -int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry); -int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry); -int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); -int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac); -/* Queue Control Unit, DFS Control Unit Functions */ -int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); -int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const struct ath5k_txq_info *queue_info); -int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct ath5k_txq_info *queue_info); -void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue); -int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue); -u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue); -bool ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time); -unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal); -/* Hardware Descriptor Functions */ -/* RX Descriptor */ -int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, u32 size, unsigned int flags); -/* GPIO Functions */ -void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state); -int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio); -int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio); -u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio); -int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val); -void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32 interrupt_level); -/* Regulatory Domain/Channels Setup */ -bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags); -u16 ath5k_get_regdomain(struct ath_hw *hal); -/* PHY/RF access functions */ -int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel *channel); -bool ath5k_hw_phy_disable(struct ath_hw *hal); -void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant); -unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal); -bool ath5k_hw_rfgain(struct ath_hw *hal, unsigned int phy, u_int freq); -enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); -/* Misc functions */ -int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); -void ath5k_hw_dump_state(struct ath_hw *hal); -int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); -bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); -bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); -bool ath5k_hw_disable_pspoll(struct ath_hw *hal); commit f61a61790b5500179ca7b70b73dd8b123a7ef6de Author: Jiri Slaby Date: Sat Aug 4 08:31:08 2007 +0200 add delay.h to includes diff --git a/ath5k_base.c b/ath5k_base.c index 10aa888..2bf80ed 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/ath5k_hw.c b/ath5k_hw.c index fe37c93..fee1d0b 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -21,6 +21,7 @@ */ #include +#include #include "ath5k.h" #include "ath5k_reg.h" commit 755587b3a3dd0294cb1b6818adcf2cfa92ddb8b9 Author: Jiri Slaby Date: Sat Aug 4 22:11:11 2007 +0200 add me to copyrights diff --git a/ath5k_base.c b/ath5k_base.c index 2bf80ed..2372fb3 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -1,6 +1,7 @@ /*- * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting * Copyright (c) 2004-2005 Atheros Communications, Inc. + * Copyright (c) 2007 Jiri Slaby * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/ath5k_hw.c b/ath5k_hw.c index fee1d0b..85f5a9f 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2004-2007 Reyk Floeter * Copyright (c) 2006-2007 Nick Kossifidis + * Copyright (c) 2007 Jiri Slaby * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above commit 4bd851aa3e1119b449a85fd8c9534d0ffec8caf1 Author: Jiri Slaby Date: Sat Aug 4 22:24:42 2007 +0200 remove // comments diff --git a/ath5k_base.c b/ath5k_base.c index 2372fb3..f74f5e3 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -227,8 +227,6 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) ieee80211_tx_status(sc->hw, skb, &txs); sc->tx_stats.data[txq->qnum].count++; -// printk(KERN_DEBUG "DONE skb: %p, rssi: %d, stat: %x, seq: %u, stamp: %u\n", skb, ds->ds_txstat.ts_rssi, ds->ds_txstat.ts_status, ds->ds_txstat.ts_seqnum, ds->ds_txstat.ts_tstamp); - spin_lock(&sc->txbuflock); sc->tx_stats.data[txq->qnum].len--; list_move_tail(&bf->list, &sc->txbuf); @@ -470,7 +468,6 @@ accept: rxs.rate = ds->ds_rxstat.rs_rate; rxs.flag |= ath_rx_decrypted(sc, ds, skb); -// printk(KERN_DEBUG "stat: %x, dlen: %u (hdr: %u), rssi: %d, rate: %u\n", ds->ds_rxstat.rs_status, len, ieee80211_get_hdrlen_from_skb(skb), ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_rate); ath_dump_skb(skb, "r"); __ieee80211_rx(sc->hw, skb, &rxs); @@ -1174,8 +1171,10 @@ static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) /* * Change channels and update the h/w rate map * if we're switching; e.g. 11a to 11b/g. + * + * XXX needed? */ -// ath_chan_change(sc, chan); +/* ath_chan_change(sc, chan); */ /* * Re-enable interrupts. @@ -1241,8 +1240,6 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, ath5k_hw_tx_start(ah, txq->qnum); spin_unlock_bh(&txq->lock); -// printk(KERN_DEBUG "bf: %p, skb: %p, flags: %x, daddr: %x, dlink: %x, tlink: %x\n", bf, skb, flags, bf->daddr, ds->ds_link, *txq->link); - return 0; err_unmap: pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); @@ -1330,8 +1327,10 @@ static int ath_reset(struct ieee80211_hw *hw) * We may be doing a reset in response to an ioctl * that changes the channel so update any state that * might change as a result. + * + * XXX needed? */ -// ath_chan_change(sc, c); +/* ath_chan_change(sc, c); */ ath_beacon_config(sc); /* intrs are started by ath_beacon_config */ @@ -2237,7 +2236,6 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) * returns because we'll get called back to reclaim node * state and potentially want to use them. */ -// ath_dynamic_sysctl_unregister(sc); } static const char *ath_chip_name(u8 mac_version) commit 31ba44286359464c6cb2bd32119d486353561944 Author: Jiri Slaby Date: Sat Aug 4 22:26:29 2007 +0200 remove beacon_free commented line diff --git a/ath5k_base.c b/ath5k_base.c index f74f5e3..5b3ea0e 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -1012,7 +1012,6 @@ static int ath_stop_locked(struct ath_softc *sc) ath5k_hw_phy_disable(ah); } else sc->rxlink = NULL; -// ath_beacon_free(sc); return 0; } commit f989c827e19e1eff36d6e5c2c443255d0ca81fa9 Author: Jiri Slaby Date: Sat Aug 4 22:40:06 2007 +0200 remove stats diff --git a/ath5k_base.c b/ath5k_base.c index 5b3ea0e..261e4aa 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -267,7 +267,6 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " "size %u failed\n", __func__, sc->rxbufsize + sc->cachelsz - 1); - sc->stats.ast_rx_nobuf++; return -ENOMEM; } /* @@ -286,7 +285,6 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) printk(KERN_ERR "%s: DMA mapping failed\n", __func__); dev_kfree_skb(skb); bf->skb = NULL; - sc->stats.ast_rx_busdma++; return -ENOMEM; } } @@ -402,16 +400,8 @@ static void ath_tasklet_rx(unsigned long data) stat = ds->ds_rxstat.rs_status; if (unlikely(stat)) { - if (stat & AR5K_RXERR_CRC) - sc->stats.ast_rx_crcerr++; - if (stat & AR5K_RXERR_FIFO) - sc->stats.ast_rx_fifoerr++; - if (stat & AR5K_RXERR_PHY) { - sc->stats.ast_rx_phyerr++; - sc->stats.ast_rx_phy - [ds->ds_rxstat.rs_phyerr & 0x1f]++; + if (stat & AR5K_RXERR_PHY) goto next; - } if (stat & AR5K_RXERR_DECRYPT) { /* * Decrypt error. If the error occurred @@ -427,11 +417,9 @@ static void ath_tasklet_rx(unsigned long data) AR5K_RXKEYIX_INVALID && !(stat & AR5K_RXERR_CRC)) goto accept; - sc->stats.ast_rx_badcrypt++; } if (stat & AR5K_RXERR_MIC) { rxs.flag |= RX_FLAG_MMIC_ERROR; - sc->stats.ast_rx_badmic++; goto accept; } @@ -453,8 +441,6 @@ accept: skb_put(skb, len); - sc->stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; - if (sc->opmode == IEEE80211_IF_TYPE_MNTR) rxs.mactime = ath_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp); @@ -514,11 +500,10 @@ static int ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf, ds->ds_link = 0; /* * Switch antenna every 4 beacons if txantenna is not set - * XXX assumes two antenna + * XXX assumes two antennas */ - if (antenna == 0) { - antenna = (sc->stats.ast_be_xmit & 4 ? 2 : 1); - } + if (antenna == 0) + antenna = sc->bsent & 4 ? 2 : 1; } ds->ds_data = bf->skbaddr; @@ -606,7 +591,7 @@ static void ath_beacon_send(struct ath_softc *sc) DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: TXDP[%u] = %llx (%p)\n", __func__, sc->bhalq, (unsigned long long)bf->daddr, bf->desc); - sc->stats.ast_be_xmit++; + sc->bsent++; } static int ath_beaconq_config(struct ath_softc *sc) @@ -1264,7 +1249,6 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, if (net_ratelimit()) printk(KERN_ERR "ath: no further txbuf available, " "dropping packet\n"); - sc->stats.ast_tx_nobuf++; spin_unlock_irqrestore(&sc->txbuflock, flags); ieee80211_stop_queue(hw, ctl->queue); return -1; @@ -1272,10 +1256,8 @@ static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb, bf = list_first_entry(&sc->txbuf, struct ath_buf, list); list_del(&bf->list); sc->txbuf_len--; - if (list_empty(&sc->txbuf)) { - sc->stats.ast_tx_qstop++; + if (list_empty(&sc->txbuf)) ieee80211_stop_queues(hw); - } spin_unlock_irqrestore(&sc->txbuflock, flags); bf->skb = skb; @@ -1576,8 +1558,6 @@ static void ath_calibrate(unsigned long data) struct ath_softc *sc = (void *)data; struct ath_hw *ah = sc->ah; - sc->stats.ast_per_cal++; - DPRINTF(sc, ATH_DEBUG_CALIBRATE, "ath: channel %u/%x\n", sc->curchan->chan, sc->curchan->val); @@ -1586,15 +1566,12 @@ static void ath_calibrate(unsigned long data) * Rfgain is out of bounds, reset the chip * to load new gain values. */ - sc->stats.ast_per_rfgain++; DPRINTF(sc, ATH_DEBUG_RESET, "calibration, resetting\n"); ath_reset(sc->hw); } - if (ath5k_hw_phy_calibrate(ah, sc->curchan)) { + if (ath5k_hw_phy_calibrate(ah, sc->curchan)) DPRINTF(sc, ATH_DEBUG_ANY, "ath: calibration of channel %u " "failed\n", sc->curchan->chan); - sc->stats.ast_per_calfail++; - } mod_timer(&sc->calib_tim, round_jiffies(jiffies + msecs_to_jiffies(ath_calinterval * 1000))); @@ -1673,10 +1650,8 @@ static irqreturn_t ath_intr(int irq, void *dev_id) * the exact reason is not (presently) returned * by the hal. */ - sc->stats.ast_hardware++; tasklet_schedule(&sc->restq); } else if (unlikely(status & AR5K_INT_RXORN)) { - sc->stats.ast_rxorn++; tasklet_schedule(&sc->restq); } else { if (status & AR5K_INT_SWBA) { @@ -1694,11 +1669,9 @@ static irqreturn_t ath_intr(int irq, void *dev_id) * RXE bit is written, but it doesn't work at * least on older hardware revs. */ - sc->stats.ast_rxeol++; sc->rxlink = NULL; } if (status & AR5K_INT_TXURN) { - sc->stats.ast_txurn++; /* bump tx trigger level */ ath5k_hw_update_tx_triglevel(ah, true); } @@ -1707,11 +1680,9 @@ static irqreturn_t ath_intr(int irq, void *dev_id) if (status & AR5K_INT_TX) tasklet_schedule(&sc->txtq); if (status & AR5K_INT_BMISS) { - sc->stats.ast_bmiss++; /* tasklet_schedule(&sc->bmisstq);*/ } if (status & AR5K_INT_MIB) { - sc->stats.ast_mib++; /* TODO */ } } diff --git a/ath5k_base.h b/ath5k_base.h index 64d1ecf..bc38bec 100644 --- a/ath5k_base.h +++ b/ath5k_base.h @@ -111,72 +111,6 @@ struct ath_txq { bool setup; }; -struct ath_stats { - __u32 ast_watchdog; /* device reset by watchdog */ - __u32 ast_hardware; /* fatal hardware error interrupts */ - __u32 ast_bmiss; /* beacon miss interrupts */ - __u32 ast_bstuck; /* beacon stuck interrupts */ - __u32 ast_rxorn; /* rx overrun interrupts */ - __u32 ast_rxeol; /* rx eol interrupts */ - __u32 ast_txurn; /* tx underrun interrupts */ - __u32 ast_mib; /* mib interrupts */ - __u32 ast_intrcoal; /* interrupts coalesced */ - __u32 ast_tx_packets; /* packet sent on the interface */ - __u32 ast_tx_mgmt; /* management frames transmitted */ - __u32 ast_tx_discard; /* frames discarded prior to assoc */ - __u32 ast_tx_invalid; /* frames discarded 'cuz device gone */ - __u32 ast_tx_qstop; /* output stopped 'cuz no buffer */ - __u32 ast_tx_encap; /* tx encapsulation failed */ - __u32 ast_tx_nonode; /* tx failed 'cuz no node */ - __u32 ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ - __u32 ast_tx_nobufmgt;/* tx failed 'cuz no tx buffer (mgmt)*/ - __u32 ast_tx_linear; /* tx linearized to cluster */ - __u32 ast_tx_nodata; /* tx discarded empty frame */ - __u32 ast_tx_busdma; /* tx failed for dma resrcs */ - __u32 ast_tx_xretries;/* tx failed 'cuz too many retries */ - __u32 ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ - __u32 ast_tx_filtered;/* tx failed 'cuz xmit filtered */ - __u32 ast_tx_shortretry;/* tx on-chip retries (short) */ - __u32 ast_tx_longretry;/* tx on-chip retries (long) */ - __u32 ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ - __u32 ast_tx_noack; /* tx frames with no ack marked */ - __u32 ast_tx_rts; /* tx frames with rts enabled */ - __u32 ast_tx_cts; /* tx frames with cts enabled */ - __u32 ast_tx_shortpre;/* tx frames with short preamble */ - __u32 ast_tx_altrate; /* tx frames with alternate rate */ - __u32 ast_tx_protect; /* tx frames with protection */ - __u32 ast_tx_ctsburst;/* tx frames with cts and bursting */ - __u32 ast_tx_ctsext; /* tx frames with cts extension */ - __u32 ast_rx_nobuf; /* rx setup failed 'cuz no skb */ - __u32 ast_rx_busdma; /* rx setup failed for dma resrcs */ - __u32 ast_rx_orn; /* rx failed 'cuz of desc overrun */ - __u32 ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ - __u32 ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ - __u32 ast_rx_badcrypt;/* rx failed 'cuz decryption */ - __u32 ast_rx_badmic; /* rx failed 'cuz MIC failure */ - __u32 ast_rx_phyerr; /* rx failed 'cuz of PHY err */ - __u32 ast_rx_phy[32]; /* rx PHY error per-code counts */ - __u32 ast_rx_tooshort;/* rx discarded 'cuz frame too short */ - __u32 ast_rx_toobig; /* rx discarded 'cuz frame too large */ - __u32 ast_rx_packets; /* packet recv on the interface */ - __u32 ast_rx_mgt; /* management frames received */ - __u32 ast_rx_ctl; /* rx discarded 'cuz ctl frame */ - __s8 ast_tx_rssi; /* tx rssi of last ack */ - __s8 ast_rx_rssi; /* rx rssi from histogram */ - __u32 ast_be_xmit; /* beacons transmitted */ - __u32 ast_be_nobuf; /* beacon setup failed 'cuz no skb */ - __u32 ast_per_cal; /* periodic calibration calls */ - __u32 ast_per_calfail;/* periodic calibration failed */ - __u32 ast_per_rfgain; /* periodic calibration rfgain reset */ - __u32 ast_rate_calls; /* rate control checks */ - __u32 ast_rate_raise; /* rate control raised xmit rate */ - __u32 ast_rate_drop; /* rate control dropped xmit rate */ - __u32 ast_ant_defswitch;/* rx/default antenna switches */ - __u32 ast_ant_txswitch;/* tx antenna switches */ - __u32 ast_ant_rx[8]; /* rx frames with antenna */ - __u32 ast_ant_tx[8]; /* tx frames with antenna */ -}; - #if CHAN_DEBUG #define ATH_CHAN_MAX (26+26+26+200+200) #else @@ -187,7 +121,6 @@ struct ath_softc { struct pci_dev *pdev; /* for dma mapping */ void __iomem *iobase; /* address of the device */ struct mutex lock; /* dev-level lock */ - struct ath_stats stats; /* private statistics */ struct ieee80211_tx_queue_stats tx_stats; struct ieee80211_low_level_stats ll_stats; struct ieee80211_hw *hw; /* IEEE 802.11 common */ @@ -272,7 +205,8 @@ struct ath_softc { struct ath_buf *bbuf; /* beacon buffer */ unsigned int bhalq, /* HAL q for outgoing beacons */ bmisscount, /* missed beacon transmits */ - bintval; /* beacon interval */ + bintval, /* beacon interval */ + bsent; #ifdef BEACON u32 sc_ant_tx[8]; /* recent tx frames/antenna */ struct ath_txq *cabq; /* tx q for cab frames */ commit 843e51274172ba1b8ea5d8e8420b438f0da19434 Author: Jiri Slaby Date: Sat Aug 4 22:47:23 2007 +0200 some of ATH_DEBUG_ANY -> printk diff --git a/ath5k_base.c b/ath5k_base.c index 261e4aa..79ed348 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -264,9 +264,8 @@ static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) */ skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); if (unlikely(skb == NULL)) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: skbuff alloc of " - "size %u failed\n", __func__, - sc->rxbufsize + sc->cachelsz - 1); + printk(KERN_ERR "ath: can't alloc skbuff of size %u\n", + sc->rxbufsize + sc->cachelsz - 1); return -ENOMEM; } /* @@ -542,8 +541,8 @@ static void ath_beacon_send(struct ath_softc *sc) if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA || sc->opmode == IEEE80211_IF_TYPE_MNTR)) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: bf=%p bf_skb=%p\n", - __func__, bf, bf ? bf->skb : NULL); + printk(KERN_WARNING "ath: bf=%p bf_skb=%p\n", bf, + bf ? bf->skb : NULL); return; } /* @@ -579,8 +578,8 @@ static void ath_beacon_send(struct ath_softc *sc) * are still pending on the queue. */ if (unlikely(!ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { - DPRINTF(sc, ATH_DEBUG_ANY, "%s: beacon queue %u didn't stop?\n", - __func__, sc->bhalq); + printk(KERN_WARNING "ath: beacon queue %u didn't stop?\n", + sc->bhalq); /* NB: the HAL still stops DMA, so proceed */ } pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len, @@ -1570,8 +1569,8 @@ static void ath_calibrate(unsigned long data) ath_reset(sc->hw); } if (ath5k_hw_phy_calibrate(ah, sc->curchan)) - DPRINTF(sc, ATH_DEBUG_ANY, "ath: calibration of channel %u " - "failed\n", sc->curchan->chan); + printk(KERN_ERR "ath: calibration of channel %u failed\n", + sc->curchan->chan); mod_timer(&sc->calib_tim, round_jiffies(jiffies + msecs_to_jiffies(ath_calinterval * 1000))); commit 2db4f998eb5009f73ce434d041208cd1044282ec Author: Jiri Slaby Date: Sat Aug 4 22:55:24 2007 +0200 fix anti-cyclic 1st ifdef in ath5k.h diff --git a/ath5k.h b/ath5k.h index c5e9cbe..2154864 100644 --- a/ath5k.h +++ b/ath5k.h @@ -15,8 +15,8 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#ifndef _AR5K_H -#define _AR5K_H +#ifndef _ATH5K_H +#define _ATH5K_H /* Set this to 1 to disable regulatory domain restrictions for channel tests. * WARNING: This is for debuging only and has side effects (eg. scan takes too @@ -1050,4 +1050,5 @@ int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_t bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); bool ath5k_hw_disable_pspoll(struct ath_hw *hal); -#endif /* _AR5K_H */ + +#endif commit 8050a3fbf9d830995b80b32d72f6d4f405c9042f Author: Jiri Slaby Date: Sat Aug 4 23:00:27 2007 +0200 remove UNUSED entries from softc diff --git a/ath5k_base.c b/ath5k_base.c index 79ed348..751388b 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -1679,7 +1679,6 @@ static irqreturn_t ath_intr(int irq, void *dev_id) if (status & AR5K_INT_TX) tasklet_schedule(&sc->txtq); if (status & AR5K_INT_BMISS) { -/* tasklet_schedule(&sc->bmisstq);*/ } if (status & AR5K_INT_MIB) { /* TODO */ diff --git a/ath5k_base.h b/ath5k_base.h index bc38bec..da20ef2 100644 --- a/ath5k_base.h +++ b/ath5k_base.h @@ -137,21 +137,13 @@ struct ath_softc { dma_addr_t desc_daddr; /* DMA (physical) address */ size_t desc_len; /* size of TX/RX descriptors */ u16 cachelsz; /* cache line size */ -#ifdef UNUSED - void (*sc_setdefantenna)(struct ath_softc *, u_int); -#endif + unsigned int invalid : 1, /* disable hardware accesses */ mrretry : 1, /* multi-rate retry support */ promisc : 1; -#ifdef UNUSED - sc_diversity : 1,/* enable rx diversity */ - sc_hasveol : 1, /* tx VEOL support */ - sc_mcastkey: 1, /* mcast key cache search */ - sc_hasclrkey:1; /* CLR key supported */ - /* rate tables */ -#endif - unsigned int curmode; /* current phy mode */ - struct ieee80211_channel *curchan; /* current h/w channel */ + + unsigned int curmode; /* current phy mode */ + struct ieee80211_channel *curchan; /* current h/w channel */ int iface_id; /* add/remove_interface id */ @@ -161,10 +153,7 @@ struct ath_softc { u16 ledon; /* softled on time */ u16 ledoff; /* softled off time */ } hwmap[32]; /* h/w rate ix mappings */ -#ifdef UNUSED - u8 sc_protrix; /* protection rate index */ - u_int sc_txantenna; /* tx antenna (fixed or auto) */ -#endif + enum ath5k_int imask; /* interrupt mask copy */ DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ @@ -188,17 +177,12 @@ struct ath_softc { spinlock_t rxbuflock; u32 *rxlink; /* link ptr in last RX desc */ struct tasklet_struct rxtq; /* rx intr tasklet */ -#ifdef UNUSED - u8 sc_defant; /* current default antenna */ - u8 sc_rxotherant; /* rx's on non-default antenna*/ -#endif + struct list_head txbuf; /* transmit buffer */ spinlock_t txbuflock; unsigned int txbuf_len; /* buf count in txbuf list */ struct ath_txq txqs[2]; /* beacon and tx */ -#ifdef UNUSED - struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ -#endif + struct ath_txq *txq; /* beacon and tx*/ struct tasklet_struct txtq; /* tx intr tasklet */ @@ -207,16 +191,7 @@ struct ath_softc { bmisscount, /* missed beacon transmits */ bintval, /* beacon interval */ bsent; -#ifdef BEACON - u32 sc_ant_tx[8]; /* recent tx frames/antenna */ - struct ath_txq *cabq; /* tx q for cab frames */ - struct tasklet_struct bmisstq; /* bmiss intr tasklet */ -#endif -#ifdef UNUSED - struct ctl_table_header *sc_sysctl_header; - struct ctl_table *sc_sysctls; -#endif struct timer_list calib_tim; /* calibration timer */ }; commit 557152e73f9344da1694368ce1c32c7ce44c998c Author: Jiri Slaby Date: Sun Aug 5 17:20:10 2007 +0200 howmany -> DIV_ROUND_UP diff --git a/ath5k.h b/ath5k.h index 2154864..26afdb3 100644 --- a/ath5k.h +++ b/ath5k.h @@ -80,7 +80,6 @@ #else #define AR5K_TRACE #endif -#define howmany(x, y) (((x)+((y)-1))/(y)) /* * Some tuneable values (these should be changeable by the user) @@ -375,7 +374,8 @@ enum ath5k_pkt_type { #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) #define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) + DIV_ROUND_UP(AR5K_OFDM_NUM_BITS(_frmlen), \ + AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) #define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ @@ -390,8 +390,8 @@ enum ath5k_pkt_type { #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) #define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ - AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) + DIV_ROUND_UP(AR5K_TURBO_NUM_BITS(_frmlen), \ + AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) #define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ @@ -406,7 +406,7 @@ enum ath5k_pkt_type { #define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) + DIV_ROUND_UP(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) #define AR5K_XR_TX_TIME(_kbps, _frmlen) \ AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ commit 1bb90dddbc88dd1d9091d7f19a970d21cc66e816 Author: Jiri Slaby Date: Sun Aug 5 17:43:06 2007 +0200 remove vendor ids (they are in recent versions) diff --git a/ath5k.h b/ath5k.h index 26afdb3..2fb1bee 100644 --- a/ath5k.h +++ b/ath5k.h @@ -35,13 +35,6 @@ #include "ath5k_regdom.h" /* PCI IDs */ -#ifndef PCI_VENDOR_ID_ATHEROS -#define PCI_VENDOR_ID_ATHEROS 0x168c -#endif -#ifndef PCI_VENDOR_ID_3COM_2 -#define PCI_VENDOR_ID_3COM_2 0xa727 -#endif - #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ commit b54c1b1283d993cf4d15e75bb4ab8a8d58bacf1a Author: Jiri Slaby Date: Sun Aug 5 17:44:57 2007 +0200 0x7ffffff -> INT_MAX diff --git a/ath5k_base.c b/ath5k_base.c index 751388b..8a14496 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -2443,7 +2443,7 @@ enum { }; static int mincalibrate = 1; -static int maxint = 0x7ffffff / 1000; +static int maxcalibrate = INT_MAX / 1000; #define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */ static ctl_table ath_static_sysctls[] = { @@ -2483,7 +2483,7 @@ static ctl_table ath_static_sysctls[] = { .data = &ath_calinterval, .maxlen = sizeof(ath_calinterval), .extra1 = &mincalibrate, - .extra2 = &maxint, + .extra2 = &maxcalibrate, .proc_handler = proc_dointvec_minmax }, { 0 } commit 40c11c49f672d5d2a1430247d651d649b9ead471 Author: Jiri Slaby Date: Sun Aug 5 17:53:04 2007 +0200 make AR5K_TRACE output on KERN_DEBUG lvl diff --git a/ath5k.h b/ath5k.h index 2fb1bee..fd85a9c 100644 --- a/ath5k.h +++ b/ath5k.h @@ -69,7 +69,7 @@ #define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) #define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) #ifdef AR5K_DEBUG -#define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__) +#define AR5K_TRACE printk(KERN_DEBUG "%s:%d\n", __func__, __LINE__) #else #define AR5K_TRACE #endif commit 1ee6c2c27fab905aa282016b1c0451d90eb4d15d Author: Jiri Slaby Date: Tue Aug 7 08:12:34 2007 +0200 remove trailing whitespace diff --git a/ath5k.h b/ath5k.h index fd85a9c..b57e16b 100644 --- a/ath5k.h +++ b/ath5k.h @@ -576,7 +576,7 @@ struct ath5k_athchan_2ghz { struct ath5k_rate { u8 valid; /* Valid for rate control */ u32 modulation; - u16 rate_kbps; + u16 rate_kbps; u8 rate_code; /* Rate mapping for h/w descriptors */ u8 dot11_rate; u8 control_rate; @@ -585,7 +585,7 @@ struct ath5k_rate { }; struct ath5k_rate_table { - u16 rate_count; + u16 rate_count; u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ struct ath5k_rate rates[AR5K_MAX_RATES]; }; @@ -742,7 +742,7 @@ enum ath5k_int { | AR5K_INT_SWBA | AR5K_INT_BMISS | AR5K_INT_GPIO, - AR5K_INT_NOCARD = 0xffffffff /*Declare that the card + AR5K_INT_NOCARD = 0xffffffff /*Declare that the card has been removed*/ }; diff --git a/ath5k_base.c b/ath5k_base.c index 8a14496..9af70e1 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -538,7 +538,7 @@ static void ath_beacon_send(struct ath_softc *sc) struct ath_hw *ah = sc->ah; DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__); - + if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA || sc->opmode == IEEE80211_IF_TYPE_MNTR)) { printk(KERN_WARNING "ath: bf=%p bf_skb=%p\n", bf, @@ -651,7 +651,7 @@ static void ath_beacon_config(struct ath_softc *sc) /* current TSF converted to TU */ tsf = ath5k_hw_get_tsf64(ah); tsftu = TSF_TO_TU((u32)(tsf >> 32), (u32)tsf); - + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: intval %u hw tsftu %u\n", __func__, intval, tsftu); @@ -669,10 +669,10 @@ static void ath_beacon_config(struct ath_softc *sc) * can be too short for ibss merges. */ nexttbtt = tsftu + 2 * intval; - + DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u " "intval %u\n", __func__, nexttbtt, intval); - + /* * In IBSS mode enable the beacon timers but only * enable SWBA interrupts if we need to manually diff --git a/ath5k_hw.c b/ath5k_hw.c index 85f5a9f..ba76103 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -402,15 +402,15 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, hal->ah_phy = AR5K_PHY(0); - /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a - * temporary variable for setting our BSSID. Right bellow we update + /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a + * temporary variable for setting our BSSID. Right bellow we update * it with ath5k_hw_get_lladdr() */ memset(mac, 0xff, ETH_ALEN); ath5k_hw_set_associd(hal, mac, 0); ath5k_hw_get_lladdr(hal, mac); ath5k_hw_set_opmode(hal); - + #ifdef AR5K_DEBUG ath5k_hw_dump_state(hal); #endif @@ -487,7 +487,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) /* * Get channel mode flags */ - + if (hal->ah_radio >= AR5K_RF5112) { mode = AR5K_PHY_MODE_RAD_RF5112; clock = AR5K_PHY_PLL_RF5112; @@ -879,7 +879,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ath5k_hw_ini_registers(hal, ARRAY_SIZE(ar5210_ini), ar5210_ini, change_channel); } - + /* * 5211/5212 Specific */ @@ -921,7 +921,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (AR5K_SET_SHORT_PREAMBLE << 2)); } } - + } else { /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ @@ -1095,7 +1095,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*PISR/SISR Not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR); - /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so + /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so * direct write using ath5k_hw_reg_write seems wrong. Test with: * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); @@ -1173,7 +1173,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) noise_floor = AR5K_PHY_NF_AVAL(noise_floor); - + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) break; } @@ -1183,7 +1183,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, channel->freq); return -EIO; } - + hal->ah_calibration = false; if (!(channel->val & CHANNEL_B)) { @@ -1243,7 +1243,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY_SPENDING); } - /* + /* * Disable beacons and reset the register */ AR5K_REG_DISABLE_BITS(hal, AR5K_BEACON, AR5K_BEACON_ENABLE | @@ -1465,7 +1465,7 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) break; case AR5K_TX_QUEUE_BEACON: tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BSR); break; case AR5K_TX_QUEUE_CAB: @@ -1554,7 +1554,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) /* * Get the address of the TX Descriptor for a specific queue * (see also QCU/DCU functions) - */ + */ u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) { u16 tx_reg; @@ -1614,7 +1614,7 @@ int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) } } else { /* - * Set the transmit queue descriptor pointer for + * Set the transmit queue descriptor pointer for * the selected queue on QCU for 5211+ * (this won't work if the queue is still active) */ @@ -1740,8 +1740,8 @@ int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int *interrupt_mask) *interrupt_mask |= AR5K_INT_BNR; } - /* - * XXX: BMISS interrupts may occur after association. + /* + * XXX: BMISS interrupts may occur after association. * I found this on 5210 code but it needs testing */ #if 0 @@ -2427,7 +2427,7 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) if (AR5K_EEPROM_HDR_11A(ee_header)) { hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ hal->ah_capabilities.cap_range.range_5ghz_max = 6100; - + /* Set supported modes */ set_bit(MODE_IEEE80211A, hal->ah_capabilities.cap_mode); set_bit(MODE_ATHEROS_TURBO, @@ -2436,12 +2436,12 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) set_bit(MODE_ATHEROS_TURBOG, hal->ah_capabilities.cap_mode); } - + /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ hal->ah_capabilities.cap_range.range_2ghz_max = 2732; - + if (AR5K_EEPROM_HDR_11B(ee_header)) set_bit(MODE_IEEE80211B, hal->ah_capabilities.cap_mode); @@ -2610,10 +2610,10 @@ ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) low_id = AR5K_LOW_ID(mask); high_id = AR5K_HIGH_ID(mask); - ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); - ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); + ath5k_hw_reg_write(hal, low_id, AR5K_BSS_IDM0); + ath5k_hw_reg_write(hal, high_id, AR5K_BSS_IDM1); - return true; + return true; } return false; @@ -2849,7 +2849,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * { u32 cfp_period, next_cfp, dtim, interval, next_beacon; - /* + /* * TODO: should be changed through *state * review struct ath5k_beacon_state struct * @@ -2873,8 +2873,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * * PCF support? */ if (state->bs_cfp_period > 0) { - /* - * Enable PCF mode and set the CFP + /* + * Enable PCF mode and set the CFP * (Contention Free Period) and timer registers */ cfp_period = state->bs_cfp_period * state->bs_dtim_period * @@ -2944,7 +2944,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * if (interval > dtim) return; - + next_beacon = interval == dtim ? state->bs_next_dtim : state->bs_next_beacon; @@ -3203,7 +3203,7 @@ int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) /* Invalid entry (key table overflow) */ AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - /* MAC may be NULL if it's a broadcast key. In this case no need to + /* MAC may be NULL if it's a broadcast key. In this case no need to * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ if (unlikely(mac == NULL)) { low_id = 0xffffffff; @@ -3255,7 +3255,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, switch (queue_type) { case AR5K_TX_QUEUE_DATA: for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != + hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; queue++) { if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) @@ -3279,7 +3279,7 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, break; default: return -EINVAL; - } + } } /* @@ -3313,13 +3313,13 @@ int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) return -EIO; memcpy(&hal->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); /*XXX: Is this supported on 5210 ?*/ - if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && + if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) @@ -3362,7 +3362,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) u32 cw_min, cw_max, retry_lg, retry_sh; struct ath5k_txq_info *tq = &hal->ah_txq[queue]; int i; - struct ath5k_ar5210_ini_mode ar5210_mode[] = + struct ath5k_ar5210_ini_mode ar5210_mode[] = AR5K_AR5210_INI_MODE(hal, hal->ah_aifs + tq->tqi_aifs); AR5K_TRACE; @@ -3533,7 +3533,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) ath5k_hw_reg_write(hal, ((AR5K_TUNE_BEACON_INTERVAL - - (AR5K_TUNE_SW_BEACON_RESP - + (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | AR5K_QCU_RDYTIMECFG_ENABLE, @@ -3572,7 +3572,7 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_SIMR1_QCU_TXERR), AR5K_SIMR1); ath5k_hw_reg_write(hal, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); - } + } return 0; } @@ -4051,10 +4051,10 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0; /* - *Clear ds_hw + *Clear ds_hw * If we don't clean the status descriptor, - * while scanning we get too many results, - * most of them virtual, after some secs + * while scanning we get too many results, + * most of them virtual, after some secs * of scanning system hangs. M.F. */ memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); @@ -4382,7 +4382,7 @@ bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags) if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) return true; - } else if (flags & CHANNEL_5GHZ) + } else if (flags & CHANNEL_5GHZ) if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) return true; @@ -4466,7 +4466,7 @@ static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, { int channel; - /* Cast this value to catch negative channel numbers (>= -19) */ + /* Cast this value to catch negative channel numbers (>= -19) */ channel = (int)ieee; /* @@ -4735,7 +4735,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal, if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE) noise_floor = AR5K_PHY_NF_AVAL(noise_floor); - + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) break; } @@ -5261,7 +5261,7 @@ static int ath5k_hw_rf5112_rfregs(struct ath_hw *hal, } /* - * Initialize 5211 RF + * Initialize 5211 RF * TODO: is this needed ? i mean 5211 has a 5111 RF * doesn't ar5k_rfregs work ? */ @@ -5459,7 +5459,7 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, /* Initialize TX power table */ ath5k_txpower_table(hal, channel, txpower); - /* + /* * Write TX power values */ for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { @@ -5621,7 +5621,7 @@ int ath5k_hw_get_capability(struct ath_hw *hal, AR5K_TRACE; switch (cap_type) { - case AR5K_CAP_NUM_TXQUEUES: + case AR5K_CAP_NUM_TXQUEUES: if (result) { if (hal->ah_version == AR5K_AR5210) *result = AR5K_NUM_TX_QUEUES_NOQCU; @@ -5650,15 +5650,14 @@ int ath5k_hw_get_capability(struct ath_hw *hal, goto yes; else goto no; - default: + default: goto no; } - no: +no: return -EINVAL; - yes: +yes: return 0; - } bool diff --git a/ath5k_hw.h b/ath5k_hw.h index cd4fbad..2dfcf92 100644 --- a/ath5k_hw.h +++ b/ath5k_hw.h @@ -469,8 +469,8 @@ struct ath5k_hw_tx_status { /* Some registers can hold multiple values of interest. For this * reason when we want to write to these registers we must first - * retrieve the values which we do not want to clear (lets call this - * old_data) and then set the register with this and our new_value: + * retrieve the values which we do not want to clear (lets call this + * old_data) and then set the register with this and our new_value: * ( old_data | new_value) */ #define AR5K_REG_WRITE_BITS(hal, _reg, _flags, _val) \ ath5k_hw_reg_write(hal, (ath5k_hw_reg_read(hal, _reg) & ~(_flags)) | \ @@ -827,7 +827,7 @@ struct ath5k_ini_rf { { 7, 0x98c4, \ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } - + /* RF5112A mode-specific init registers */ #define AR5K_RF5112A_INI_RF { \ { 1, 0x98d4, \ diff --git a/ath5k_reg.h b/ath5k_reg.h index ec79bb7..59547d1 100644 --- a/ath5k_reg.h +++ b/ath5k_reg.h @@ -39,9 +39,9 @@ * maintained by Reyk Floeter * * I tried to document those registers by looking at ar5k code, some - * 802.11 (802.11e mostly) papers and by reading various public available + * 802.11 (802.11e mostly) papers and by reading various public available * Atheros presentations and papers like these: - * + * * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf * @@ -70,7 +70,7 @@ #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ #define AR5K_CR_RXD 0x00000020 /* RX Disable */ -#define AR5K_CR_SWI 0x00000040 +#define AR5K_CR_SWI 0x00000040 /* * RX Descriptor Pointer register @@ -95,7 +95,7 @@ #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ #define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ -#define AR5K_CFG_PCI_THRES_S 17 +#define AR5K_CFG_PCI_THRES_S 17 /* * Interrupt enable register @@ -119,7 +119,7 @@ #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ -#define AR5K_BCR_BCGET 0x00000010 +#define AR5K_BCR_BCGET 0x00000010 /* * First RTS duration register [5211] @@ -135,7 +135,7 @@ #define AR5K_RTSD0_18_S 24 -/* +/* * 0x002c is Beacon Status Register on 5210 * and second RTS duration register on 5211 */ @@ -145,7 +145,7 @@ * * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning - * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). + * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. @@ -160,7 +160,7 @@ #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ -#define AR5K_BSR_SWBA_CNT 0x00ff0000 +#define AR5K_BSR_SWBA_CNT 0x00ff0000 /* * Second RTS duration register [5211] @@ -191,7 +191,7 @@ #define AR5K_TXCFG_TXFULL_128B 0x00000020 #define AR5K_TXCFG_TXFULL_192B 0x00000030 #define AR5K_TXCFG_TXFULL_256B 0x00000040 -#define AR5K_TXCFG_TXCONT_EN 0x00000080 +#define AR5K_TXCFG_TXCONT_EN 0x00000080 #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ #define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ @@ -219,10 +219,10 @@ * MIB control register */ #define AR5K_MIBC 0x0040 /* Register Address */ -#define AR5K_MIBC_COW 0x00000001 +#define AR5K_MIBC_COW 0x00000001 #define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ #define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ -#define AR5K_MIBC_MCS 0x00000008 +#define AR5K_MIBC_MCS 0x00000008 /* * Timeout prescale register @@ -260,13 +260,13 @@ * Misc settings register */ #define AR5K_MISC 0x0058 /* Register Address */ -#define AR5K_MISC_DMA_OBS_M 0x000001e0 +#define AR5K_MISC_DMA_OBS_M 0x000001e0 #define AR5K_MISC_DMA_OBS_S 5 -#define AR5K_MISC_MISC_OBS_M 0x00000e00 +#define AR5K_MISC_MISC_OBS_M 0x00000e00 #define AR5K_MISC_MISC_OBS_S 9 -#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 +#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 #define AR5K_MISC_MAC_OBS_LSB_S 12 -#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 +#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 #define AR5K_MISC_MAC_OBS_MSB_S 15 #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ @@ -303,9 +303,9 @@ #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ #define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ -#define AR5K_ISR_RXKCM 0x00008000 +#define AR5K_ISR_RXKCM 0x00008000 #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ -#define AR5K_ISR_BRSSI 0x00020000 +#define AR5K_ISR_BRSSI 0x00020000 #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ @@ -323,7 +323,7 @@ /* * Secondary status registers [5211+] (0 - 4) * - * I guess from the names that these give the status for each + * I guess from the names that these give the status for each * queue, that's why only masks are defined here, haven't got * any info about them (couldn't find them anywhere in ar5k code). */ @@ -337,9 +337,9 @@ #define AR5K_SISR2 0x008c /* Register Address [5211+] */ #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ -#define AR5K_SISR2_MCABT 0x00100000 -#define AR5K_SISR2_SSERR 0x00200000 -#define AR5K_SISR2_DPERR 0x00400000 +#define AR5K_SISR2_MCABT 0x00100000 +#define AR5K_SISR2_SSERR 0x00200000 +#define AR5K_SISR2_DPERR 0x00400000 #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ @@ -385,11 +385,11 @@ #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ -#define AR5K_IMR_SWI 0x00002000 +#define AR5K_IMR_SWI 0x00002000 #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ -#define AR5K_IMR_RXKCM 0x00008000 +#define AR5K_IMR_RXKCM 0x00008000 #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ -#define AR5K_IMR_BRSSI 0x00020000 +#define AR5K_IMR_BRSSI 0x00020000 #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ @@ -422,9 +422,9 @@ #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ #define AR5K_SIMR2_QCU_TXURN_S 0 -#define AR5K_SIMR2_MCABT 0x00100000 -#define AR5K_SIMR2_SSERR 0x00200000 -#define AR5K_SIMR2_DPERR 0x00400000 +#define AR5K_SIMR2_MCABT 0x00100000 +#define AR5K_SIMR2_SSERR 0x00200000 +#define AR5K_SIMR2_DPERR 0x00400000 #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ @@ -452,13 +452,13 @@ /* * Decompression configuration registers [5212+] */ -#define AR5K_DCCFG 0x0420 +#define AR5K_DCCFG 0x0420 /* * Compression configuration registers [5212+] */ -#define AR5K_CCFG 0x0600 -#define AR5K_CCFG_CUP 0x0604 +#define AR5K_CCFG 0x0600 +#define AR5K_CCFG_CUP 0x0604 /* * Compression performance counter registers [5212+] @@ -473,11 +473,11 @@ /* * Queue control unit (QCU) registers [5211+] * - * Card has 12 TX Queues but i see that only 0-9 are used (?) - * both in binary HAL (see ah.h) and ar5k. Each queue has it's own - * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) + * Card has 12 TX Queues but i see that only 0-9 are used (?) + * both in binary HAL (see ah.h) and ar5k. Each queue has it's own + * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) * configuration register (0x08c0 - 0x08ec), a ready time configuration - * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - + * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some * global registers, QCU transmit enable/disable and "one shot arm (?)" * set/clear, which contain status for all queues (we shift by 1 for each @@ -493,7 +493,7 @@ #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) - + /* * QCU Transmit descriptor pointer registers */ @@ -595,7 +595,7 @@ /* - * Distributed Coordination Function (DCF) control unit (DCU) + * Distributed Coordination Function (DCF) control unit (DCU) * registers [5211+] * * These registers control the various characteristics of each queue @@ -607,7 +607,7 @@ * a sequence number register (0x1140 - 0x116c). It seems that "global" * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). * We use the same macros here for easier register access. - * + * */ /* @@ -655,15 +655,15 @@ /* * DCU misc registers [5211+] * - * For some of the registers i couldn't find in the code - * (only backoff stuff is there realy) i tried to match the - * names with 802.11e parameters etc, so i guess VIRTCOL here + * For some of the registers i couldn't find in the code + * (only backoff stuff is there realy) i tried to match the + * names with 802.11e parameters etc, so i guess VIRTCOL here * means Virtual Collision and HCFPOLL means Hybrid Coordination * factor Poll (CF- Poll). Arbiter lockout control controls the * behaviour on low priority queues when we have multiple queues * with pending frames. Intra-frame lockout means we wait until * the queue's current frame transmits (with post frame backoff and bursting) - * before we transmit anything else and global lockout means we + * before we transmit anything else and global lockout means we * wait for the whole queue to finish before higher priority queues * can transmit (this is used on beacon and CAB queues). * No lockout means there is no special handling. @@ -684,11 +684,11 @@ #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ -#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 +#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ -#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 +#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) @@ -721,11 +721,11 @@ * DCU global IFS misc registers */ #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ -#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 +#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ -#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 -#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 +#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 +#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* * DCU frame prefetch control register @@ -780,7 +780,7 @@ #define AR5K_SLEEP_CTL_SLE_S 16 #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ -#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 +#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ /* @@ -822,7 +822,7 @@ #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ -#define AR5K_PCICFG_LEDBLINK 0x00700000 +#define AR5K_PCICFG_LEDBLINK 0x00700000 #define AR5K_PCICFG_LEDBLINK_S 20 #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ #define AR5K_PCICFG_LEDSTATE \ @@ -915,7 +915,7 @@ * For more infos check eeprom_* functs and the ar5k.c * file posted in madwifi-devel mailing list. * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 - * + * */ #define AR5K_EEPROM_BASE 0x6000 @@ -1046,7 +1046,7 @@ /* * Protocol Control Unit (PCU) registers */ -/* +/* * Used for checking initial register writes * during channel reset (see reset func) */ @@ -1318,7 +1318,7 @@ #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ #define AR5K_DIAG_SW (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) -#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 +#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ @@ -1332,11 +1332,11 @@ #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 #define AR5K_DIAG_SW_LOOP_BACK (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) -#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 +#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 #define AR5K_DIAG_SW_CORR_FCS (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) -#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 +#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 #define AR5K_DIAG_SW_CHAN_INFO (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) @@ -1349,11 +1349,11 @@ #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ #define AR5K_DIAG_SW_SCRAM_SEED_S 10 #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ -#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 +#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 #define AR5K_DIAG_SW_FRAME_NV0 (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) -#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 +#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 #define AR5K_DIAG_SW_OBSPT_S 18 /* @@ -1625,8 +1625,8 @@ * There is another frame control register for [5111+] * at address 0x9944 (see below) but the 2 first flags * are common here between 5110 frame control register - * and [5111+] turbo mode register, so this also works as - * a "turbo mode register" for 5110. We treat this one as + * and [5111+] turbo mode register, so this also works as + * a "turbo mode register" for 5110. We treat this one as * a frame control register for 5110 below. */ #define AR5K_PHY_TURBO 0x9804 @@ -1746,13 +1746,13 @@ * * We sent such data packets during rf initialization and channel change * through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions. - * + * * The data packets we send during initializadion are inside ath5k_ini_rf * struct (see ath5k_hw.h) and each one is related to an "rf register bank". * We use *rfregs functions to modify them acording to current operation * mode and eeprom values and pass them all together to the chip. * - * It's obvious from the code that 0x989c is the buffer register but + * It's obvious from the code that 0x989c is the buffer register but * for the other special registers that we write to after sending each * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers * for now. It's interesting that they are also used for some other operations. @@ -1866,34 +1866,34 @@ /* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... at power on. */ -#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 +#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 /* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1 after DFS is enabled */ #define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d -/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ +/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ * power out threshold. * 7-bits, standard power range {0..127} in 1/2 dBm units. */ -#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 +#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 #define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24 -/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ +/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ * 6-bits, dBm range {0..63} in dBm units. */ -#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 +#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 #define AR5K_PHY_RADAR_RADARRSSITHR_S 18 -/* Pulse height threshold ........ ......11 1111.... ........ +/* Pulse height threshold ........ ......11 1111.... ........ * 6-bits, dBm range {0..63} in dBm units. */ #define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000 #define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12 -/* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... +/* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... * 6-bits, dBm range {0..63} in dBm units. */ #define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0 #define AR5K_PHY_RADAR_PULSERSSITHR_S 6 -/* Inband threshold ........ ........ ........ ..11111. +/* Inband threshold ........ ........ ........ ..11111. * 5-bits, units unknown {0..31} (? MHz ?) */ #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e #define AR5K_PHY_RADAR_INBANDTHR_S 1 @@ -1963,7 +1963,7 @@ after DFS is enabled */ #define AR5K_PHY_CCKTXCTL 0xa204 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 - + /* * PHY 2GHz gain register [5111+] */ diff --git a/ath5k_regdom.c b/ath5k_regdom.c index 455b923..c345da8 100644 --- a/ath5k_regdom.c +++ b/ath5k_regdom.c @@ -74,7 +74,7 @@ static const struct ath5k_regdommap { enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom dmn, u16 mhz) { unsigned int i; - + for (i = 0; i < ARRAY_SIZE(r_map); i++) { if (r_map[i].dmn == dmn) { if (mhz >= 2000 && mhz <= 3000) commit 57ba7c06221ec54c1c91f04582d71332879076c0 Author: Jiri Slaby Date: Tue Aug 7 08:19:20 2007 +0200 remove sp[ace on the line beginning diff --git a/ath5k.h b/ath5k.h index b57e16b..b679055 100644 --- a/ath5k.h +++ b/ath5k.h @@ -156,9 +156,9 @@ struct ath5k_srev_name { { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ { "2413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR2413 },\ - { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ - { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ - { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ + { "5413", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5413 },\ + { "5424", AR5K_VERSION_DEV, PCI_DEVICE_ID_ATHEROS_AR5424 },\ + { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ } #define AR5K_SREV_UNKNOWN 0xffff diff --git a/ath5k_base.c b/ath5k_base.c index 9af70e1..0d5281b 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -562,7 +562,7 @@ static void ath_beacon_send(struct ath_softc *sc) "%s: stuck beacon time (%u missed)\n", __func__, sc->bmisscount); tasklet_schedule(&sc->restq); - } + } return; } if (unlikely(sc->bmisscount != 0)) { diff --git a/ath5k_base.h b/ath5k_base.h index da20ef2..39ad8f9 100644 --- a/ath5k_base.h +++ b/ath5k_base.h @@ -80,8 +80,8 @@ #define ATH_LPF_RSSI(x, y, len) \ ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) #define ATH_RSSI_LPF(x, y) do { \ - if ((y) >= -20) \ - x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ + if ((y) >= -20) \ + x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ } while (0) struct ath_buf { diff --git a/ath5k_hw.c b/ath5k_hw.c index ba76103..def9b8f 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -123,7 +123,7 @@ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; */ static u16 /*TODO: Is this really hardware dependent ?*/ ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates, - u32 frame_length, u16 rate_index, bool short_preamble) + u32 frame_length, u16 rate_index, bool short_preamble) { const struct ath5k_rate *rate; u32 value; @@ -403,8 +403,8 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, hal->ah_phy = AR5K_PHY(0); /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a - * temporary variable for setting our BSSID. Right bellow we update - * it with ath5k_hw_get_lladdr() */ + * temporary variable for setting our BSSID. Right bellow we update + * it with ath5k_hw_get_lladdr() */ memset(mac, 0xff, ETH_ALEN); ath5k_hw_set_associd(hal, mac, 0); @@ -1096,7 +1096,7 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, if (hal->ah_version != AR5K_AR5210) { ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR); /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so - * direct write using ath5k_hw_reg_write seems wrong. Test with: + * direct write using ath5k_hw_reg_write seems wrong. Test with: * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR, * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); * with different variables and check results compared @@ -1153,8 +1153,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, } /* - * Enable noise floor calibration and wait until completion - */ + * Enable noise floor calibration and wait until completion + */ AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); @@ -1668,7 +1668,7 @@ ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase) status = true; - done: +done: /* * Restore interrupt mask */ @@ -2651,8 +2651,7 @@ ath5k_hw_stop_pcu_recv(struct ath_hw *hal) * Set multicast filter */ void -ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, - u32 filter1) +ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32 filter1) { AR5K_TRACE; /* Set the multicat filter */ @@ -2849,7 +2848,7 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * { u32 cfp_period, next_cfp, dtim, interval, next_beacon; - /* + /* * TODO: should be changed through *state * review struct ath5k_beacon_state struct * @@ -3204,7 +3203,7 @@ int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8 *mac) AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); /* MAC may be NULL if it's a broadcast key. In this case no need to - * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ + * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ if (unlikely(mac == NULL)) { low_id = 0xffffffff; high_id = 0xffff | AR5K_KEYTABLE_VALID; @@ -3820,8 +3819,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, */ static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, - unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - unsigned int tx_rate3, u_int tx_tries3) + unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, + unsigned int tx_rate3, u_int tx_tries3) { struct ath5k_hw_4w_tx_desc *tx_desc; @@ -4716,8 +4715,8 @@ static int ath5k_hw_rf5110_calibrate(struct ath_hw *hal, } /* - * Enable noise floor calibration and wait until completion - */ + * Enable noise floor calibration and wait until completion + */ AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF); ret = ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, @@ -5671,8 +5670,7 @@ ath5k_hw_query_pspoll_support(struct ath_hw *hal) } bool -ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, - u16 assoc_id) +ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id) { AR5K_TRACE; if (hal->ah_version == AR5K_AR5210) { commit 2f875dbedbd9d9cc0f106fd01f70d2332d890a08 Author: Jiri Slaby Date: Wed Aug 8 21:49:23 2007 +0200 fix some whitespace (checkpatch) diff --git a/ath5k.h b/ath5k.h index b679055..2913a0a 100644 --- a/ath5k.h +++ b/ath5k.h @@ -195,7 +195,8 @@ struct ath5k_srev_name { #define MODULATION_CCK_SP IEEE80211_RATE_CCK_2 /*CCK + Shortpreamble*/ #define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code - enables short preamble, see ar5212_reg.h */ + enables short preamble, see + ar5212_reg.h */ #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) #define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 @@ -227,7 +228,7 @@ struct ath_tx_status { * Queue types used to classify tx queues. */ enum ath5k_tx_queue { - AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ + AR5K_TX_QUEUE_INACTIVE = 0, /* q is unused -- see ath5k_hw_release_tx_queue */ AR5K_TX_QUEUE_DATA, /*A normal data queue*/ AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ @@ -354,9 +355,9 @@ enum ath5k_pkt_type { (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) #define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ - AR5K_CCK_PHY_TIME(_sp) + \ - ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ - AR5K_CCK_SIFS_TIME + (AR5K_CCK_PHY_TIME(_sp) + \ + ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ + AR5K_CCK_SIFS_TIME) /* OFDM */ #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) @@ -371,8 +372,8 @@ enum ath5k_pkt_type { AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) #define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ - AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ - (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) + (AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ + (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)) /* TURBO */ #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) @@ -387,8 +388,8 @@ enum ath5k_pkt_type { AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) #define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ - AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ - (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) + (AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ + (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)) /* eXtendent Range (?)*/ #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) @@ -401,9 +402,9 @@ enum ath5k_pkt_type { #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ DIV_ROUND_UP(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) -#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ - AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ - (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) +#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ + (AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ + (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)) /* * DMA size definitions (2^n+2) @@ -545,11 +546,11 @@ struct ath_desc { #define CHANNEL_108G CHANNEL_TG #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) -#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ - CHANNEL_5GHZ | CHANNEL_TURBO) +#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ + CHANNEL_TURBO) -#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) -#define CHANNEL_MODES CHANNEL_ALL +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) +#define CHANNEL_MODES CHANNEL_ALL /* * Used internaly in OpenHAL (ar5211.c/ar5212.c @@ -916,7 +917,8 @@ struct ath_hw { struct { u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; u16 txp_rates[AR5K_MAX_RATES]; - s16 txp_min, txp_max; + s16 txp_min; + s16 txp_max; bool txp_tpc; s16 txp_ofdm; } ah_txpower; @@ -978,7 +980,7 @@ void ath5k_hw_set_opmode(struct ath_hw *hal); void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac); bool ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac); void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id); -bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask); +bool ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask); /* Receive start/stop functions */ void ath5k_hw_start_rx_pcu(struct ath_hw *hal); void ath5k_hw_stop_pcu_recv(struct ath_hw *hal); @@ -1039,7 +1041,7 @@ enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal); /* Misc functions */ int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power); void ath5k_hw_dump_state(struct ath_hw *hal); -int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type,u32 capability, u32 *result); +int ath5k_hw_get_capability(struct ath_hw *hal, enum ath5k_capability_type cap_type, u32 capability, u32 *result); bool ath5k_hw_query_pspoll_support(struct ath_hw *hal); bool ath5k_hw_enable_pspoll(struct ath_hw *hal, u8 *bssid, u16 assoc_id); bool ath5k_hw_disable_pspoll(struct ath_hw *hal); diff --git a/ath5k_base.c b/ath5k_base.c index 0d5281b..d8f4b8e 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -33,10 +33,10 @@ #include #include #include +#include #include -#include #include #include "ath5k_base.h" @@ -133,10 +133,10 @@ static void ath_printrxbuf(struct ath_buf *bf, int done) struct ath_desc *ds = bf->desc; printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n", - ds, (unsigned long long)bf->daddr, - ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], - !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); + ds, (unsigned long long)bf->daddr, + ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], + !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); } static void ath_printtxbuf(struct ath_buf *bf, int done) @@ -144,11 +144,10 @@ static void ath_printtxbuf(struct ath_buf *bf, int done) struct ath_desc *ds = bf->desc; printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x " - "%08x %c\n", - ds, (unsigned long long)bf->daddr, - ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, - ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], - !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); + "%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link, + ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, + ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], + !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); } #endif @@ -214,11 +213,10 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) ds->ds_txstat.ts_longretry / 6; if (unlikely(ds->ds_txstat.ts_status)) { sc->ll_stats.dot11ACKFailureCount++; - if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) { + if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) txs.excessive_retries = 1; - } else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) { + else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; - } } else { txs.flags |= IEEE80211_TX_STATUS_ACK; txs.ack_signal = ds->ds_txstat.ts_rssi; @@ -348,7 +346,7 @@ static inline u64 ath_extend_tsf(struct ath_hw *ah, u32 rstamp) if ((tsf & 0x7fff) < rstamp) tsf -= 0x8000; - return (tsf &~ 0x7fff) | rstamp; + return (tsf & ~0x7fff) | rstamp; } static void ath_tasklet_rx(unsigned long data) @@ -423,7 +421,7 @@ static void ath_tasklet_rx(unsigned long data) } /* let crypto-error packets fall through in MNTR */ - if ((stat &~ (AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || + if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || sc->opmode != IEEE80211_IF_TYPE_MNTR) goto next; } @@ -435,8 +433,10 @@ accept: PCI_DMA_FROMDEVICE); bf->skb = NULL; - if (unlikely((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit())) - printk(KERN_DEBUG "rx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + if (unlikely((ieee80211_get_hdrlen_from_skb(skb) & 3) && + net_ratelimit())) + printk(KERN_DEBUG "rx len is not %%4: %u\n", + ieee80211_get_hdrlen_from_skb(skb)); skb_put(skb, len); @@ -639,7 +639,7 @@ static int ath_beaconq_config(struct ath_softc *sc) */ static void ath_beacon_config(struct ath_softc *sc) { -#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) +#define TSF_TO_TU(_h, _l) (((_h) << 22) | ((_l) >> 10)) struct ath_hw *ah = sc->ah; u32 uninitialized_var(nexttbtt), intval, tsftu; u64 tsf; @@ -853,8 +853,8 @@ static int ath_init(struct ath_softc *sc) /* * Enable interrupts. */ - sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | AR5K_INT_RXORN - | AR5K_INT_FATAL | AR5K_INT_GLOBAL; + sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | + AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL; ath5k_hw_set_intr(sc->ah, sc->imask); @@ -1022,7 +1022,8 @@ static int ath_stop_hw(struct ath_softc *sc) * (and system). This varies by chip and is mostly an * issue with newer parts that go to sleep more quickly. */ - if (sc->ah->ah_mac_version >= 7 && sc->ah->ah_mac_revision >= 8) { + if (sc->ah->ah_mac_version >= 7 && + sc->ah->ah_mac_revision >= 8) { /* * XXX * don't put newer MAC revisions > 7.8 to sleep because @@ -1030,8 +1031,7 @@ static int ath_stop_hw(struct ath_softc *sc) */ DPRINTF(sc, ATH_DEBUG_RESET, "%s: mac version > 7.8, " "not putting device to sleep\n", __func__); - } - else { + } else { DPRINTF(sc, ATH_DEBUG_RESET, "%s: putting device to full sleep\n", __func__); ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); @@ -1069,7 +1069,7 @@ static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) { 2, 400, 100 }, { 0, 500, 130 } }; - const struct ath5k_rate_table* rt = + const struct ath5k_rate_table *rt = ath5k_hw_get_rate_table(sc->ah, mode); unsigned int i, j; @@ -1188,7 +1188,8 @@ static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf, flags |= AR5K_TXDESC_NOACK; if ((ieee80211_get_hdrlen_from_skb(skb) & 3) && net_ratelimit()) - printk(KERN_DEBUG "tx len is not %%4: %u\n", ieee80211_get_hdrlen_from_skb(skb)); + printk(KERN_DEBUG "tx len is not %%4: %u\n", + ieee80211_get_hdrlen_from_skb(skb)); hdrpad = 0; pktlen = skb->len - hdrpad + FCS_LEN; @@ -1367,9 +1368,8 @@ static void ath_remove_interface(struct ieee80211_hw *hw, struct ath_softc *sc = hw->priv; mutex_lock(&sc->lock); - if (sc->iface_id != conf->if_id) { + if (sc->iface_id != conf->if_id) goto end; - } sc->iface_id = 0; end: @@ -1810,21 +1810,19 @@ static void ath_dump_modes(struct ieee80211_hw_mode *modes) printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m, modes[m].num_channels, modes[m].num_rates); printk(KERN_DEBUG " channels:\n"); - for (i = 0; i < modes[m].num_channels; i++) { + for (i = 0; i < modes[m].num_channels; i++) printk(KERN_DEBUG " %3d %d %.4x %.4x\n", modes[m].channels[i].chan, modes[m].channels[i].freq, modes[m].channels[i].val, modes[m].channels[i].flag); - } printk(KERN_DEBUG " rates:\n"); - for (i = 0; i < modes[m].num_rates; i++) { + for (i = 0; i < modes[m].num_rates; i++) printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n", modes[m].rates[i].rate, modes[m].rates[i].val, modes[m].rates[i].flags, modes[m].rates[i].val2); - } } } #else @@ -2209,12 +2207,12 @@ static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) static const char *ath_chip_name(u8 mac_version) { switch (mac_version) { - case AR5K_AR5210: - return "AR5210"; - case AR5K_AR5211: - return "AR5211"; - case AR5K_AR5212: - return "AR5212"; + case AR5K_AR5210: + return "AR5210"; + case AR5K_AR5211: + return "AR5211"; + case AR5K_AR5212: + return "AR5212"; } return "Unknown"; } @@ -2380,7 +2378,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) struct ath_softc *sc = hw->priv; if (sc->led_soft) - ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); + ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); ath_stop_hw(sc); pci_save_state(pdev); @@ -2414,8 +2412,8 @@ static int ath_pci_resume(struct pci_dev *pdev) ath_init(sc); if (sc->led_soft) { - ath5k_hw_set_gpio_output(sc->ah, sc->led_pin); - ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0); + ath5k_hw_set_gpio_output(sc->ah, sc->led_pin); + ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0); } return 0; @@ -2449,7 +2447,7 @@ static int maxcalibrate = INT_MAX / 1000; static ctl_table ath_static_sysctls[] = { #if AR_DEBUG { .ctl_name = CTL_AUTO, - .procname = "debug", + .procname = "debug", .mode = 0644, .data = &ath_debug, .maxlen = sizeof(ath_debug), diff --git a/ath5k_hw.c b/ath5k_hw.c index def9b8f..56f78d3 100644 --- a/ath5k_hw.c +++ b/ath5k_hw.c @@ -325,20 +325,20 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; switch (device) { - case PCI_DEVICE_ID_ATHEROS_AR2413: - case PCI_DEVICE_ID_ATHEROS_AR5413: - case PCI_DEVICE_ID_ATHEROS_AR5424: - /* - * Known single chip solutions - */ - hal->ah_single_chip = true; - break; - default: - /* - * Multi chip solutions - */ - hal->ah_single_chip = false; - break; + case PCI_DEVICE_ID_ATHEROS_AR2413: + case PCI_DEVICE_ID_ATHEROS_AR5413: + case PCI_DEVICE_ID_ATHEROS_AR5424: + /* + * Known single chip solutions + */ + hal->ah_single_chip = true; + break; + default: + /* + * Multi chip solutions + */ + hal->ah_single_chip = false; + break; } /* @@ -379,15 +379,16 @@ struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc, hal->ah_mac_srev = srev; hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); - hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & 0x00ffffffff; - hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,CHANNEL_5GHZ); + hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) & + 0xffffffff; + hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal, + CHANNEL_5GHZ); - if (hal->ah_version == AR5K_AR5210) { + if (hal->ah_version == AR5K_AR5210) hal->ah_radio_2ghz_revision = 0; - } else { + else hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal, CHANNEL_2GHZ); - } /* Single chip radio */ if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) @@ -511,11 +512,10 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) mode |= AR5K_PHY_MODE_MOD_CCK; } else if (flags & CHANNEL_G) { /* Dynamic OFDM/CCK is not supported by the AR5211 */ - if (hal->ah_version == AR5K_AR5211) { + if (hal->ah_version == AR5K_AR5211) mode |= AR5K_PHY_MODE_MOD_CCK; - } else { + else mode |= AR5K_PHY_MODE_MOD_DYN; - } } else if (flags & CHANNEL_OFDM) { mode |= AR5K_PHY_MODE_MOD_OFDM; } else { @@ -523,17 +523,9 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) return -EINVAL; } - if (flags & CHANNEL_TURBO) { - turbo = AR5K_PHY_TURBO_MODE | - AR5K_PHY_TURBO_SHORT; - } - } - - /* - * Reset and wakeup the device - */ - - else { + if (flags & CHANNEL_TURBO) + turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; + } else { /* Reset and wakeup the device */ if (initial == true) { /* ...reset hardware */ if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) { @@ -553,7 +545,8 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) /* ...enable Atheros turbo mode if requested */ if (flags & CHANNEL_TURBO) - ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO); + ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE, + AR5K_PHY_TURBO); /* ...reset chipset */ if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) { @@ -587,7 +580,7 @@ static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial) return -EIO; } - if (hal->ah_version != AR5K_AR5210){ + if (hal->ah_version != AR5K_AR5210) { /* ...set the PHY operating mode */ ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL); udelay(300); @@ -637,7 +630,8 @@ static u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan) ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; } else { srev = (ath5k_hw_reg_read(hal, AR5K_PHY(0x100)) >> 24) & 0xff; - ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | + ((srev & 0x0f) << 4), 8); } /* Reset to the 5GHz mode */ @@ -721,15 +715,16 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /*DCU/Antenna selection not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { if (change_channel == true) { - /*Sequence number for queue 0 -do this for all queues ?*/ - s_seq = ath5k_hw_reg_read(hal, AR5K_QUEUE_DFS_SEQNUM(0)); + /* Seq number for queue 0 -do this for all queues ? */ + s_seq = ath5k_hw_reg_read(hal, + AR5K_QUEUE_DFS_SEQNUM(0)); /*Default antenna*/ s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA); } } /*GPIOs*/ - s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; + s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR); s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO); @@ -807,7 +802,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* * Write initial RF registers on 5211 - * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ? + * do we need that ? Is ath5k_hw_rfregs going to work for + * 5211 (5111) ? */ if (hal->ah_version == AR5K_AR5211) ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode); @@ -822,11 +818,11 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, for (i = 0; i < ARRAY_SIZE(ar5212_mode); i++) { if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) off = AR5K_INI_PHY_511X; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && - hal->ah_radio == AR5K_RF5111) + else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 + && hal->ah_radio == AR5K_RF5111) off = AR5K_INI_PHY_5111; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 && - hal->ah_radio == AR5K_RF5112) + else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 + && hal->ah_radio == AR5K_RF5112) off = AR5K_INI_PHY_5112; else continue; @@ -888,9 +884,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * Write initial RF gain settings * This should work for both 5111/5112 */ - if (ath5k_hw_rfgain(hal, phy, freq) == false) { + if (ath5k_hw_rfgain(hal, phy, freq) == false) return -EIO; - } mdelay(1); @@ -913,37 +908,38 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, ath_hal_computetxtime(hal, rt, 14, rt->rates[i].control_rate, false), data); - if (HAS_SHPREAMBLE(i)) { + if (HAS_SHPREAMBLE(i)) ath5k_hw_reg_write(hal, - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, false), - data + + ath_hal_computetxtime(hal, + rt, 14, + rt->rates[i].control_rate, + false), data + (AR5K_SET_SHORT_PREAMBLE << 2)); - } } } else { - /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ + /* For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is + * O.K. for both a/g - OFDM) */ - /*Get rate table for this operation mode*/ + /* Get rate table for this operation mode */ rt = ath5k_hw_get_rate_table(hal, channel->val & CHANNEL_TURBO ? MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG); - /*Write rate duration table*/ - for (i = 0; i < rt->rate_count; i++) { + /* Write rate duration table */ + for (i = 0; i < rt->rate_count; i++) ath5k_hw_reg_write(hal, ath_hal_computetxtime(hal, rt, 14, rt->rates[i].control_rate, false), AR5K_RATE_DUR(rt->rates[i].rate_code)); - } } } /* Fix for first revision of the RF5112 RF chipset */ - if (hal->ah_radio >= AR5K_RF5112 && hal->ah_radio_5ghz_revision< + if (hal->ah_radio >= AR5K_RF5112 && + hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD, AR5K_PHY_CCKTXCTL); @@ -976,22 +972,23 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, /* Write OFDM timings on 5212*/ if (hal->ah_version == AR5K_AR5212) { if (channel->val & CHANNEL_OFDM) { - u32 coef_scaled, coef_exp, coef_man, ds_coef_exp, - ds_coef_man, clock; + u32 coef_scaled, coef_exp, coef_man, + ds_coef_exp, ds_coef_man, clock; clock = channel->val & CHANNEL_T ? 80 : 40; - coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; + coef_scaled = ((5 * (clock << 24)) / 2) / + channel->freq; for (coef_exp = 31; coef_exp > 0; coef_exp--) if ((coef_scaled >> coef_exp) & 0x1) break; - if (!coef_exp) { + if (!coef_exp) return -EINVAL; - } coef_exp = 14 - (coef_exp - 24); - coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); + coef_man = coef_scaled + + (1 << (24 - coef_exp - 1)); ds_coef_man = coef_man >> (24 - coef_exp); ds_coef_exp = coef_exp - 16; @@ -1037,12 +1034,15 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, AR5K_PHY(0x5a)); AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11), - (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); + (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, + 0xffffc07f); AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12), - (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); + (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, + 0xfffc0fff); AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14), - (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | - ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); + (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | + ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), + 0xffff0000); ath5k_hw_reg_write(hal, (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | @@ -1051,9 +1051,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a), - ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); + ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19), - (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); + (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01); AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ, @@ -1061,11 +1061,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | ee->ee_q_cal[ee_mode]); - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ, AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, ee->ee_margin_tx_rx[ee_mode]); - } } else { mdelay(1); @@ -1131,9 +1130,10 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, * 5111/5112 Specific */ if (hal->ah_version != AR5K_AR5210) { - data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; + data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) & + AR5K_PHY_RX_DELAY_M; data = (channel->val & CHANNEL_CCK) ? - ((data << 2) / 22) : (data / 10); + ((data << 2) / 22) : (data / 10); udelay(100 + data); } else { @@ -1210,9 +1210,9 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, } /* Pre-enable interrupts on 5211/5212*/ - if (hal->ah_version != AR5K_AR5210) { - ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); - } + if (hal->ah_version != AR5K_AR5210) + ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | + AR5K_INT_FATAL); /* * Set RF kill flags if supported by the device (read from the EEPROM) @@ -1222,7 +1222,8 @@ int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode, #if 0 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { ath5k_hw_set_gpio_input(hal, 0); - if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0) + hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0); + if (hal->ah_gpio[0] == 0) ath5k_hw_set_gpio_intr(hal, 0, 1); else ath5k_hw_set_gpio_intr(hal, 0, 0); @@ -1313,19 +1314,19 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; /* fallthrough */ case AR5K_PM_NETWORK_SLEEP: - if (set_chip == true) { + if (set_chip == true) ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE | sleep_duration, AR5K_SLEEP_CTL); - } + staid |= AR5K_STA_ID1_PWR_SV; break; case AR5K_PM_FULL_SLEEP: - if (set_chip == true) { + if (set_chip == true) ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_SLP, AR5K_SLEEP_CTL); - } + staid |= AR5K_STA_ID1_PWR_SV; break; @@ -1333,7 +1334,8 @@ int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode, if (set_chip == false) goto commit; - ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, AR5K_SLEEP_CTL); + ath5k_hw_reg_write(hal, AR5K_SLEEP_CTL_SLE_WAKE, + AR5K_SLEEP_CTL); for (i = 5000; i > 0; i--) { /* Check if the chip did wake up */ @@ -1460,22 +1462,21 @@ int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue) * Set the queue by type on 5210 */ switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; - break; - case AR5K_TX_QUEUE_BEACON: - tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | - AR5K_BCR_BDMAE, AR5K_BSR); - break; - case AR5K_TX_QUEUE_CAB: - tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | - AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, + case AR5K_TX_QUEUE_DATA: + tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; + break; + case AR5K_TX_QUEUE_BEACON: + tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, AR5K_BSR); - break; - default: - return -EINVAL; + break; + case AR5K_TX_QUEUE_CAB: + tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; + ath5k_hw_reg_write(hal, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V | + AR5K_BCR_BDMAE, AR5K_BSR); + break; + default: + return -EINVAL; } /* Start queue */ ath5k_hw_reg_write(hal, tx_queue, AR5K_CR); @@ -1515,17 +1516,17 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) * Set by queue type */ switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - /* XXX Fix me... */ - tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; - ath5k_hw_reg_write(hal, 0, AR5K_BSR); - break; - default: - return false; + case AR5K_TX_QUEUE_DATA: + tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + /* XXX Fix me... */ + tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; + ath5k_hw_reg_write(hal, 0, AR5K_BSR); + break; + default: + return false; } /* Stop queue */ @@ -1538,8 +1539,9 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) /*Check for pending frames*/ do { - pending = ath5k_hw_reg_read(hal, AR5K_QUEUE_STATUS(queue)) & - AR5K_QCU_STS_FRMPENDCNT; + pending = ath5k_hw_reg_read(hal, + AR5K_QUEUE_STATUS(queue)) & + AR5K_QCU_STS_FRMPENDCNT; udelay(100); } while (--i && pending); @@ -1547,7 +1549,7 @@ ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue) ath5k_hw_reg_write(hal, 0, AR5K_QCU_TXD); } - /*TODO: Check for success else return false*/ + /* TODO: Check for success else return false */ return true; } @@ -1568,15 +1570,15 @@ u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue) /*5210 doesn't have QCU*/ if (hal->ah_version == AR5K_AR5210) { switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_reg = AR5K_NOQCU_TXDP0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - tx_reg = AR5K_NOQCU_TXDP1; - break; - default: - return 0xffffffff; + case AR5K_TX_QUEUE_DATA: + tx_reg = AR5K_NOQCU_TXDP0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + tx_reg = AR5K_NOQCU_TXDP1; + break; + default: + return 0xffffffff; } } else { tx_reg = AR5K_QUEUE_TXDP(queue); @@ -1602,15 +1604,15 @@ int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32 phys_addr) */ if (hal->ah_version == AR5K_AR5210) { switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_reg = AR5K_NOQCU_TXDP0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - tx_reg = AR5K_NOQCU_TXDP1; - break; - default: - return -EINVAL; + case AR5K_TX_QUEUE_DATA: + tx_reg = AR5K_NOQCU_TXDP0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + tx_reg = AR5K_NOQCU_TXDP1; + break; + default: + return -EINVAL; } } else { /* @@ -1908,7 +1910,8 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) if (hal->ah_version == AR5K_AR5210) { AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, AR5K_PCICFG_EEAE); } else { - AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_RESET); } /* @@ -1920,7 +1923,8 @@ static int ath5k_hw_eeprom_write(struct ath_hw *hal, u32 offset, u16 data) } else { ath5k_hw_reg_write(hal, offset, AR5K_EEPROM_BASE); ath5k_hw_reg_write(hal, data, AR5K_EEPROM_DATA); - AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); + AR5K_REG_ENABLE_BITS(hal, AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_WRITE); } /* @@ -2185,7 +2189,8 @@ static int ath5k_eeprom_init(struct ath_hw *hal) */ mode = AR5K_EEPROM_MODE_11A; - ee->ee_turbo_max_power[mode] = AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); + ee->ee_turbo_max_power[mode] = + AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); @@ -2247,9 +2252,8 @@ static int ath5k_eeprom_init(struct ath_hw *hal) ath5k_eeprom_bin2freq(hal, val & 0xff, mode); } - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; - } /* * Get values for 802.11g (2.4GHz) @@ -2412,12 +2416,13 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) } else { /* * XXX The tranceiver supports frequencies from 4920 to 6100GHz - * XXX and from 2312 to 2732GHz. There are problems with the current - * XXX ieee80211 implementation because the IEEE channel mapping - * XXX does not support negative channel numbers (2312MHz is channel - * XXX -19). Of course, this doesn't matter because these channels - * XXX are out of range but some regulation domains like MKK (Japan) - * XXX will support frequencies somewhere around 4.8GHz. + * XXX and from 2312 to 2732GHz. There are problems with the + * XXX current ieee80211 implementation because the IEEE + * XXX channel mapping does not support negative channel + * XXX numbers (2312MHz is channel -19). Of course, this + * XXX doesn't matter because these channels are out of range + * XXX but some regulation domains like MKK (Japan) will + * XXX support frequencies somewhere around 4.8GHz. */ /* @@ -2437,8 +2442,10 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) hal->ah_capabilities.cap_mode); } - /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ - if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { + /* Enable 802.11b if a 2GHz capable radio (2111/5112) is + * connected */ + if (AR5K_EEPROM_HDR_11B(ee_header) || + AR5K_EEPROM_HDR_11G(ee_header)) { hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ hal->ah_capabilities.cap_range.range_2ghz_max = 2732; @@ -2457,7 +2464,8 @@ static int ath5k_hw_get_capabilities(struct ath_hw *hal) /* Set number of supported TX queues */ if (hal->ah_version == AR5K_AR5210) - hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU; + hal->ah_capabilities.cap_queues.q_tx_num = + AR5K_NUM_TX_QUEUES_NOQCU; else hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; @@ -2601,7 +2609,7 @@ ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16 assoc_id) * Set BSSID mask on 5212 */ bool -ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8* mask) +ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask) { u32 low_id, high_id; AR5K_TRACE; @@ -2844,7 +2852,8 @@ void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32 interval) * Set beacon timers */ void -ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state *state) +ath5k_hw_set_beacon_timers(struct ath_hw *hal, + const struct ath5k_beacon_state *state) { u32 cfp_period, next_cfp, dtim, interval, next_beacon; @@ -2885,7 +2894,8 @@ ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct ath5k_beacon_state * AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); ath5k_hw_reg_write(hal, cfp_period, AR5K_CFP_PERIOD); - ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, AR5K_CFP_DUR); + ath5k_hw_reg_write(hal, state->bs_cfp_max_duration, + AR5K_CFP_DUR); ath5k_hw_reg_write(hal, (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3, AR5K_TIMER2); } else { @@ -3039,7 +3049,8 @@ ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long phys_addr) * Update mib counters (statistics) */ void -ath5k_hw_update_mib_counters(struct ath_hw *hal, struct ath5k_mib_stats *statistics) +ath5k_hw_update_mib_counters(struct ath_hw *hal, + struct ath5k_mib_stats *statistics) { AR5K_TRACE; /* Read-And-Clear */ @@ -3240,44 +3251,44 @@ int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue queue_type, /*5210 only has 2 queues*/ if (hal->ah_version == AR5K_AR5210) { switch (queue_type) { - case AR5K_TX_QUEUE_DATA: - queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; - break; - default: - return -EINVAL; + case AR5K_TX_QUEUE_DATA: + queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; + break; + default: + return -EINVAL; } } else { switch (queue_type) { - case AR5K_TX_QUEUE_DATA: - for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != - AR5K_TX_QUEUE_INACTIVE; queue++) { + case AR5K_TX_QUEUE_DATA: + for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; + hal->ah_txq[queue].tqi_type != + AR5K_TX_QUEUE_INACTIVE; queue++) { - if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) - return -EINVAL; - } - break; - case AR5K_TX_QUEUE_UAPSD: - queue = AR5K_TX_QUEUE_ID_UAPSD; - break; - case AR5K_TX_QUEUE_BEACON: - queue = AR5K_TX_QUEUE_ID_BEACON; - break; - case AR5K_TX_QUEUE_CAB: - queue = AR5K_TX_QUEUE_ID_CAB; - break; - case AR5K_TX_QUEUE_XR_DATA: - if (hal->ah_version != AR5K_AR5212) - AR5K_PRINTF("XR data queues only " - "supported in 5212!\n"); - queue = AR5K_TX_QUEUE_ID_XR_DATA; - break; - default: - return -EINVAL; + if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) + return -EINVAL; + } + break; + case AR5K_TX_QUEUE_UAPSD: + queue = AR5K_TX_QUEUE_ID_UAPSD; + break; + case AR5K_TX_QUEUE_BEACON: + queue = AR5K_TX_QUEUE_ID_BEACON; + break; + case AR5K_TX_QUEUE_CAB: + queue = AR5K_TX_QUEUE_ID_CAB; + break; + case AR5K_TX_QUEUE_XR_DATA: + if (hal->ah_version != AR5K_AR5212) + AR5K_PRINTF("XR data queues only supported in " + "5212!\n"); + queue = AR5K_TX_QUEUE_ID_XR_DATA; + break; + default: + return -EINVAL; } } @@ -3461,7 +3472,8 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, - AR5K_DCU_LCL_IFS_AIFS), AR5K_QUEUE_DFS_LOCAL_IFS(queue)); + AR5K_DCU_LCL_IFS_AIFS), + AR5K_QUEUE_DFS_LOCAL_IFS(queue)); /* * Set misc registers @@ -3483,12 +3495,11 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_QCU_MISC_CBR_THRES_ENABLE); } - if (tq->tqi_ready_time) { + if (tq->tqi_ready_time) ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_ready_time, AR5K_QCU_RDYTIMECFG_INTVAL) | AR5K_QCU_RDYTIMECFG_ENABLE, AR5K_QUEUE_RDYTIMECFG(queue)); - } if (tq->tqi_burst_time) { ath5k_hw_reg_write(hal, AR5K_REG_SM(tq->tqi_burst_time, @@ -3496,48 +3507,43 @@ int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue) AR5K_DCU_CHAN_TIME_ENABLE, AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); - if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { - AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) + AR5K_REG_ENABLE_BITS(hal, + AR5K_QUEUE_MISC(queue), AR5K_QCU_MISC_TXE); - } } - if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { + if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) ath5k_hw_reg_write(hal, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, AR5K_QUEUE_DFS_MISC(queue)); - } - if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { + if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) ath5k_hw_reg_write(hal, AR5K_DCU_MISC_BACKOFF_FRAG, AR5K_QUEUE_DFS_MISC(queue)); - } /* * Set registers by queue type */ switch (tq->tqi_type) { - case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(hal, - AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_FRSHED_DBA_GT | - AR5K_QCU_MISC_CBREXP_BCN | - AR5K_QCU_MISC_BCN_ENABLE); + case AR5K_TX_QUEUE_BEACON: + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_DBA_GT | + AR5K_QCU_MISC_CBREXP_BCN | + AR5K_QCU_MISC_BCN_ENABLE); - AR5K_REG_ENABLE_BITS(hal, - AR5K_QUEUE_DFS_MISC(queue), - (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_DCU_MISC_ARBLOCK_CTL_S) | - AR5K_DCU_MISC_POST_FR_BKOFF_DIS | - AR5K_DCU_MISC_BCN_ENABLE); - - ath5k_hw_reg_write(hal, - ((AR5K_TUNE_BEACON_INTERVAL - - (AR5K_TUNE_SW_BEACON_RESP - - AR5K_TUNE_DMA_BEACON_RESP) - - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | - AR5K_QCU_RDYTIMECFG_ENABLE, - AR5K_QUEUE_RDYTIMECFG(queue)); - break; + AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_DFS_MISC(queue), + (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << + AR5K_DCU_MISC_ARBLOCK_CTL_S) | + AR5K_DCU_MISC_POST_FR_BKOFF_DIS | + AR5K_DCU_MISC_BCN_ENABLE); + + ath5k_hw_reg_write(hal, ((AR5K_TUNE_BEACON_INTERVAL - + (AR5K_TUNE_SW_BEACON_RESP - + AR5K_TUNE_DMA_BEACON_RESP) - + AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); + break; case AR5K_TX_QUEUE_CAB: AR5K_REG_ENABLE_BITS(hal, AR5K_QUEUE_MISC(queue), @@ -3650,8 +3656,8 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, { u32 frame_type; struct ath5k_hw_2w_tx_desc *tx_desc; - - tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; + + tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0; if (tx_tries0 == 0) return -EINVAL; @@ -3671,7 +3677,8 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, * XXX: I only found that on 5210 code, does it work on 5211 ? */ if (hal->ah_version == AR5K_AR5210) { - tx_desc->tx_control_0 = hdr_len & AR5K_2W_TX_DESC_CTL0_HEADER_LEN; + tx_desc->tx_control_0 = hdr_len & + AR5K_2W_TX_DESC_CTL0_HEADER_LEN; if (tx_desc->tx_control_0 != hdr_len) return -EINVAL; } @@ -3679,17 +3686,17 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, /*Diferences between 5210-5211*/ if (hal->ah_version == AR5K_AR5210) { switch (type) { - case AR5K_PKT_TYPE_BEACON: - case AR5K_PKT_TYPE_PROBE_RESP: - frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; - case AR5K_PKT_TYPE_PIFS: - frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; - default: - frame_type = type /*<< 2 ?*/; + case AR5K_PKT_TYPE_BEACON: + case AR5K_PKT_TYPE_PROBE_RESP: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; + case AR5K_PKT_TYPE_PIFS: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; + default: + frame_type = type /*<< 2 ?*/; } tx_desc->tx_control_0 = - AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE)| + AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) | AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); } else { tx_desc->tx_control_0 |= @@ -3726,10 +3733,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath_hw *hal, struct ath_desc *desc, * RTS/CTS Duration [5210 ?] */ if ((hal->ah_version == AR5K_AR5210) && - (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) { - tx_desc->tx_control_1 |= - rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; - } + (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) + tx_desc->tx_control_1 |= rtscts_duration & + AR5K_2W_TX_DESC_CTL1_RTS_DURATION; return 0; } @@ -3748,7 +3754,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, AR5K_TRACE; - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; /* * Validate input @@ -3803,7 +3809,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *hal, * RTS/CTS */ if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { - if ((flags & AR5K_TXDESC_RTSENA) &&(flags & AR5K_TXDESC_CTSENA)) + if ((flags & AR5K_TXDESC_RTSENA) && + (flags & AR5K_TXDESC_CTSENA)) return -EINVAL; tx_desc->tx_control_2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION; @@ -3825,7 +3832,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, struct ath5k_hw_4w_tx_desc *tx_desc; if (hal->ah_version == AR5K_AR5212) { - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; #define _XTX_TRIES(_n) \ if (tx_tries##_n) { \ @@ -3846,7 +3853,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath_hw *hal, struct ath_desc *desc, return true; } - return(false); + return false; } /* @@ -3858,7 +3865,7 @@ static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *hal, { struct ath5k_hw_2w_tx_desc *tx_desc; - tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; + tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0; /* Clear status descriptor */ memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); @@ -3889,8 +3896,8 @@ static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *hal, struct ath5k_hw_tx_status *tx_status; AR5K_TRACE; - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; + tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2]; /* Clear status descriptor */ memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status)); @@ -3918,8 +3925,8 @@ static int ath5k_hw_proc_2word_tx_status(struct ath_hw *hal, struct ath5k_hw_tx_status *tx_status; struct ath5k_hw_2w_tx_desc *tx_desc; - tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0]; + tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0]; /* No frame has been send or error */ if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) @@ -3969,8 +3976,8 @@ static int ath5k_hw_proc_4word_tx_status(struct ath_hw *hal, struct ath5k_hw_4w_tx_desc *tx_desc; AR5K_TRACE; - tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; + tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2]; /* No frame has been send or error */ if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) @@ -4047,7 +4054,7 @@ int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc, struct ath5k_rx_desc *rx_desc; AR5K_TRACE; - rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0; + rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0; /* *Clear ds_hw @@ -4081,7 +4088,7 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, { struct ath5k_hw_old_rx_status *rx_status; - rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0]; + rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0]; /* No frame received / not ready */ if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) @@ -4094,15 +4101,15 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, - AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, - AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; desc->ds_us.rx.rs_more = rx_status->rx_status_0 & AR5K_OLD_RX_DESC_STATUS0_MORE; desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, - AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); + AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); desc->ds_us.rx.rs_status = 0; /* @@ -4110,7 +4117,7 @@ static int ath5k_hw_proc_old_rx_status(struct ath_hw *hal, */ if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, - AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); + AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); else desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; @@ -4152,10 +4159,10 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, struct ath5k_hw_rx_error *rx_err; AR5K_TRACE; - rx_status = (struct ath5k_hw_new_rx_status*)&desc->ds_hw[0]; + rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0]; /* Overlay on error */ - rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0]; + rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0]; /* No frame received / not ready */ if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) @@ -4196,7 +4203,8 @@ static int ath5k_hw_proc_new_rx_status(struct ath_hw *hal, if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; - if (rx_status->rx_status_1 &AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR){ + if (rx_status->rx_status_1 & + AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) { desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; desc->ds_us.rx.rs_phyerr = AR5K_REG_MS(rx_err->rx_error_1, @@ -4516,12 +4524,12 @@ static int ath5k_hw_rf5111_channel(struct ath_hw *hal, if (ath_channel < 145 || !(ath_channel & 1)) { clock = 1; - data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) - | (clock << 1) | (1 << 10) | 1; + data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) | + (clock << 1) | (1 << 10) | 1; } else { clock = 0; - data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) - | (clock << 1) | (1 << 10) | 1; + data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) + << 2) | (clock << 1) | (1 << 10) | 1; } ath5k_hw_reg_write(hal, (data1 & 0xff) | ((data0 & 0xff) << 8), @@ -4985,11 +4993,10 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) hal->ah_gain.g_target >= hal->ah_gain.g_high && hal->ah_gain.g_step_idx > 0; hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { + &go->go_step[hal->ah_gain.g_step_idx]) hal->ah_gain.g_target -= 2 * (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - hal->ah_gain.g_step->gos_gain); - } ret = 1; goto done; @@ -5002,11 +5009,10 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath_hw *hal) hal->ah_gain.g_target <= hal->ah_gain.g_low && hal->ah_gain.g_step_idx < go->go_steps_count-1; hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { + &go->go_step[hal->ah_gain.g_step_idx]) hal->ah_gain.g_target -= 2 * (go->go_step[++hal->ah_gain.g_step_idx].gos_gain - hal->ah_gain.g_step->gos_gain); - } ret = 2; goto done; @@ -5484,13 +5490,12 @@ ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel *channel, AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); - if (hal->ah_txpower.txp_tpc == true) { + if (hal->ah_txpower.txp_tpc == true) ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); - } else { + else ath5k_hw_reg_write(hal, AR5K_PHY_TXPOWER_RATE_MAX | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); - } return 0; } @@ -5502,7 +5507,7 @@ int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power) AR5K_TRACE; #ifdef AR5K_DEBUG - AR5K_PRINTF("changing txpower to %d\n",power); + AR5K_PRINTF("changing txpower to %d\n", power); #endif return ath5k_hw_txpower(hal, channel, power); } diff --git a/ath5k_hw.h b/ath5k_hw.h index 2dfcf92..bd5162e 100644 --- a/ath5k_hw.h +++ b/ath5k_hw.h @@ -492,14 +492,15 @@ struct ath5k_hw_tx_status { #define AR5K_PHY_READ(hal, _reg) \ ath5k_hw_reg_read(hal, (hal)->ah_phy + ((_reg) << 2)) -#define AR5K_REG_WAIT(_i) \ +#define AR5K_REG_WAIT(_i) do { \ if (_i % 64) \ - udelay(1); + udelay(1); \ +} while (0) -#define AR5K_EEPROM_READ(_o, _v) { \ +#define AR5K_EEPROM_READ(_o, _v) do { \ if ((ret = ath5k_hw_eeprom_read(hal, (_o), &(_v))) != 0) \ return (ret); \ -} +} while (0) #define AR5K_EEPROM_READ_HDR(_o, _v) \ AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ @@ -584,7 +585,7 @@ struct ath5k_hw_tx_status { (AR5K_INIT_PROG_IFS) \ ) #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ - (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ (AR5K_INIT_PROG_IFS_TURBO) \ ) #define AR5K_INIT_BEACON_CONTROL ( \ @@ -621,328 +622,328 @@ struct ath5k_ini_rf { }; /* RF5111 mode-specific init registers */ -#define AR5K_RF5111_INI_RF { \ - { 0, 0x989c, \ - /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ - { 0, 0x989c, \ - { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ - { 0, 0x98d4, \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ - { 1, 0x98d4, \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d4, \ - { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ - { 3, 0x98d8, \ - { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ - { 6, 0x989c, \ - { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ - { 6, 0x989c, \ - { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ - { 6, 0x989c, \ - { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ - { 6, 0x989c, \ - { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ - { 6, 0x989c, \ - { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ - { 6, 0x98d4, \ - { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ - { 7, 0x989c, \ - { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ - { 7, 0x989c, \ - { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ - { 7, 0x989c, \ - { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ - { 7, 0x989c, \ - { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ - { 7, 0x989c, \ - { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ - { 7, 0x989c, \ - { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ - { 7, 0x989c, \ - { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ - { 7, 0x98cc, \ - { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ +#define AR5K_RF5111_INI_RF { \ + { 0, 0x989c, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ + { 0, 0x989c, \ + { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ + { 0, 0x98d4, \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d4, \ + { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ + { 3, 0x98d8, \ + { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ + { 6, 0x989c, \ + { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ + { 6, 0x989c, \ + { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ + { 6, 0x989c, \ + { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ + { 6, 0x989c, \ + { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ + { 6, 0x989c, \ + { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ + { 6, 0x98d4, \ + { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ + { 7, 0x989c, \ + { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ + { 7, 0x989c, \ + { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ + { 7, 0x989c, \ + { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ + { 7, 0x989c, \ + { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ + { 7, 0x989c, \ + { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ + { 7, 0x989c, \ + { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ + { 7, 0x989c, \ + { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ + { 7, 0x98cc, \ + { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ } /* RF5112 mode-specific init registers */ -#define AR5K_RF5112_INI_RF { \ - { 1, 0x98d4, \ - /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d0, \ - { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ - { 3, 0x98dc, \ - { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ - { 6, 0x989c, \ - { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ - { 6, 0x989c, \ - { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ - { 6, 0x989c, \ - { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ - { 6, 0x989c, \ - { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ - { 6, 0x989c, \ - { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ - { 6, 0x989c, \ - { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ - { 6, 0x989c, \ - { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ - { 6, 0x989c, \ - { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ - { 6, 0x989c, \ - { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ - { 6, 0x989c, \ - { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ - { 6, 0x989c, \ - { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ - { 6, 0x989c, \ - { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ - { 6, 0x989c, \ - { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ - { 6, 0x989c, \ - { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ - { 6, 0x989c, \ - { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ - { 6, 0x989c, \ - { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ - { 6, 0x989c, \ - { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ - { 6, 0x989c, \ - { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ - { 6, 0x989c, \ - { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ - { 6, 0x989c, \ - { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ - { 6, 0x989c, \ - { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ - { 6, 0x98d0, \ - { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ - { 7, 0x989c, \ - { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ - { 7, 0x989c, \ - { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ - { 7, 0x989c, \ - { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ - { 7, 0x989c, \ - { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ - { 7, 0x989c, \ - { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ - { 7, 0x989c, \ - { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ - { 7, 0x989c, \ - { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ - { 7, 0x989c, \ - { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ - { 7, 0x989c, \ - { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ - { 7, 0x989c, \ - { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ - { 7, 0x989c, \ - { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ - { 7, 0x989c, \ - { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ - { 7, 0x98c4, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ +#define AR5K_RF5112_INI_RF { \ + { 1, 0x98d4, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ + { 6, 0x989c, \ + { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ + { 6, 0x989c, \ + { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ + { 6, 0x989c, \ + { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ + { 6, 0x989c, \ + { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ + { 6, 0x989c, \ + { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ + { 6, 0x989c, \ + { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ + { 6, 0x989c, \ + { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ + { 6, 0x989c, \ + { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ + { 6, 0x989c, \ + { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ + { 6, 0x989c, \ + { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ + { 6, 0x989c, \ + { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ + { 6, 0x989c, \ + { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ + { 6, 0x989c, \ + { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ + { 6, 0x989c, \ + { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ + { 6, 0x98d0, \ + { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ + { 7, 0x989c, \ + { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } /* RF5112A mode-specific init registers */ -#define AR5K_RF5112A_INI_RF { \ - { 1, 0x98d4, \ - /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d0, \ - { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ - { 3, 0x98dc, \ - { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ - { 6, 0x989c, \ - { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ - { 6, 0x989c, \ - { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ - { 6, 0x989c, \ - { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ - { 6, 0x989c, \ - { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ - { 6, 0x989c, \ - { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ - { 6, 0x989c, \ - { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ - { 6, 0x989c, \ - { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ - { 6, 0x989c, \ - { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ - { 6, 0x989c, \ - { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ - { 6, 0x989c, \ - { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ - { 6, 0x989c, \ - { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ - { 6, 0x989c, \ - { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ - { 6, 0x989c, \ - { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ - { 6, 0x989c, \ - { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ - { 6, 0x989c, \ - { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ - { 6, 0x989c, \ - { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ - { 6, 0x989c, \ - { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ - { 6, 0x989c, \ - { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ - { 6, 0x989c, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ - { 6, 0x989c, \ - { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ - { 6, 0x989c, \ - { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ - { 6, 0x989c, \ - { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ - { 6, 0x989c, \ - { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ - { 6, 0x98d8, \ - { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ - { 7, 0x989c, \ - { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ - { 7, 0x989c, \ - { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ - { 7, 0x989c, \ - { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ - { 7, 0x989c, \ - { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ - { 7, 0x989c, \ - { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ - { 7, 0x989c, \ - { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ - { 7, 0x989c, \ - { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ - { 7, 0x989c, \ - { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ - { 7, 0x989c, \ - { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ - { 7, 0x989c, \ - { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ - { 7, 0x989c, \ - { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ - { 7, 0x989c, \ - { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ - { 7, 0x98c4, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ +#define AR5K_RF5112A_INI_RF { \ + { 1, 0x98d4, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ + { 6, 0x989c, \ + { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ + { 6, 0x989c, \ + { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ + { 6, 0x989c, \ + { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ + { 6, 0x989c, \ + { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ + { 6, 0x989c, \ + { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ + { 6, 0x989c, \ + { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ + { 6, 0x989c, \ + { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ + { 6, 0x989c, \ + { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ + { 6, 0x989c, \ + { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ + { 6, 0x989c, \ + { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ + { 6, 0x989c, \ + { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ + { 6, 0x989c, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ + { 6, 0x989c, \ + { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ + { 6, 0x989c, \ + { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ + { 6, 0x989c, \ + { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ + { 6, 0x989c, \ + { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ + { 6, 0x98d8, \ + { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ + { 7, 0x989c, \ + { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } /* @@ -956,136 +957,136 @@ struct ath5k_ini_rfgain { #define AR5K_INI_RFGAIN_2GHZ 1 }; -#define AR5K_INI_RFGAIN { \ - { 0x9a00, { \ - /* 5111 5Ghz 5111 2Ghz 5112 5Ghz 5112 2Ghz */ \ - { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ - { 0x9a04, { \ - { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ - { 0x9a08, { \ - { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ - { 0x9a0c, { \ - { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ - { 0x9a10, { \ - { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ - { 0x9a14, { \ - { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ - { 0x9a18, { \ - { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ - { 0x9a1c, { \ - { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ - { 0x9a20, { \ - { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ - { 0x9a24, { \ - { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ - { 0x9a28, { \ - { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ - { 0x9a2c, { \ - { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ - { 0x9a30, { \ - { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ - { 0x9a34, { \ - { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ - { 0x9a38, { \ - { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ - { 0x9a3c, { \ - { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ - { 0x9a40, { \ - { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ - { 0x9a44, { \ - { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ - { 0x9a48, { \ - { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ - { 0x9a4c, { \ - { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ - { 0x9a50, { \ - { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ - { 0x9a54, { \ - { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ - { 0x9a58, { \ - { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ - { 0x9a5c, { \ - { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ - { 0x9a60, { \ - { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ - { 0x9a64, { \ - { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ - { 0x9a68, { \ - { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ - { 0x9a6c, { \ - { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ - { 0x9a70, { \ - { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ - { 0x9a74, { \ - { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ - { 0x9a78, { \ - { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ - { 0x9a7c, { \ - { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ - { 0x9a80, { \ - { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ - { 0x9a84, { \ - { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ - { 0x9a88, { \ - { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ - { 0x9a8c, { \ - { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ - { 0x9a90, { \ - { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ - { 0x9a94, { \ - { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ - { 0x9a98, { \ - { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ - { 0x9a9c, { \ - { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ - { 0x9aa0, { \ - { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ - { 0x9aa4, { \ - { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ - { 0x9aa8, { \ - { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ - { 0x9aac, { \ - { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ - { 0x9ab0, { \ - { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ - { 0x9ab4, { \ - { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ - { 0x9ab8, { \ - { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ - { 0x9abc, { \ - { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ - { 0x9ac0, { \ - { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ - { 0x9ac4, { \ - { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ - { 0x9ac8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ - { 0x9acc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ - { 0x9ad0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ - { 0x9ad4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ - { 0x9ad8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9adc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9aec, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9afc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ +#define AR5K_INI_RFGAIN { \ + { 0x9a00, { \ + /* 5111 5Ghz 5111 2Ghz 5112 5Ghz 5112 2Ghz */ \ + { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ + { 0x9a04, { \ + { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ + { 0x9a08, { \ + { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ + { 0x9a0c, { \ + { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ + { 0x9a10, { \ + { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ + { 0x9a14, { \ + { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ + { 0x9a18, { \ + { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ + { 0x9a1c, { \ + { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ + { 0x9a20, { \ + { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ + { 0x9a24, { \ + { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ + { 0x9a28, { \ + { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ + { 0x9a2c, { \ + { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ + { 0x9a30, { \ + { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ + { 0x9a34, { \ + { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ + { 0x9a38, { \ + { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ + { 0x9a3c, { \ + { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ + { 0x9a40, { \ + { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ + { 0x9a44, { \ + { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ + { 0x9a48, { \ + { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ + { 0x9a4c, { \ + { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ + { 0x9a50, { \ + { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ + { 0x9a54, { \ + { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ + { 0x9a58, { \ + { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ + { 0x9a5c, { \ + { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ + { 0x9a60, { \ + { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ + { 0x9a64, { \ + { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ + { 0x9a68, { \ + { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ + { 0x9a6c, { \ + { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ + { 0x9a70, { \ + { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ + { 0x9a74, { \ + { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ + { 0x9a78, { \ + { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ + { 0x9a7c, { \ + { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ + { 0x9a80, { \ + { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ + { 0x9a84, { \ + { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ + { 0x9a88, { \ + { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ + { 0x9a8c, { \ + { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ + { 0x9a90, { \ + { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ + { 0x9a94, { \ + { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ + { 0x9a98, { \ + { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ + { 0x9a9c, { \ + { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ + { 0x9aa0, { \ + { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ + { 0x9aa4, { \ + { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ + { 0x9aa8, { \ + { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ + { 0x9aac, { \ + { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ + { 0x9ab0, { \ + { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ + { 0x9ab4, { \ + { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ + { 0x9ab8, { \ + { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ + { 0x9abc, { \ + { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ + { 0x9ac0, { \ + { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ + { 0x9ac4, { \ + { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ + { 0x9ac8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ + { 0x9acc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ + { 0x9ad0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ + { 0x9ad4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ + { 0x9ad8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9adc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9aec, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9afc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ } @@ -1355,7 +1356,7 @@ struct ath5k_ini { { AR5K_DIAG_SW_5211, 0x00000000 }, \ { AR5K_ADDAC_TEST, 0x00000000 }, \ { AR5K_DEFAULT_ANTENNA, 0x00000000 }, \ - /* PHY registers */ \ + /* PHY registers */ \ { AR5K_PHY_AGC, 0x00000000 }, \ { AR5K_PHY(3), 0x2d849093 }, \ { AR5K_PHY(4), 0x7d32e000 }, \ @@ -1670,7 +1671,7 @@ struct ath5k_ini { { AR5K_PHY_PCDAC_TXPOWER(28), 0x10ff10ff }, \ { AR5K_PHY_PCDAC_TXPOWER(29), 0x10ff10ff }, \ { AR5K_PHY_PCDAC_TXPOWER(30), 0x10ff10ff }, \ - { AR5K_PHY_PCDAC_TXPOWER(31),0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(31), 0x10ff10ff }, \ { AR5K_PHY(644), 0x0080a333 }, \ { AR5K_PHY(645), 0x00206c10 }, \ { AR5K_PHY(646), 0x009c4060 }, \ @@ -1757,7 +1758,7 @@ struct ath5k_ini { /* RF 5112 Initial BB Gain settings */ #define AR5K_RF5112_BBGAIN_INI { \ - { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ { AR5K_BB_GAIN(1), 0x00000001 }, \ { AR5K_BB_GAIN(2), 0x00000002 }, \ { AR5K_BB_GAIN(3), 0x00000003 }, \ @@ -1828,7 +1829,7 @@ struct ath5k_ar5210_ini_mode{ u32 mode_base, mode_turbo; }; -#define AR5K_AR5210_INI_MODE(hal, _aifs) { \ +#define AR5K_AR5210_INI_MODE(hal, _aifs) { \ { AR5K_SLOT_TIME, \ AR5K_INIT_SLOT_TIME, \ AR5K_INIT_SLOT_TIME_TURBO }, \ @@ -1922,9 +1923,9 @@ struct ath5k_ar5212_ini_mode { #define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) #define AR5K_AR5212_INI_MODE { \ - { 0x0030, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \ + { 0x0030, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \ } }, \ { 0x1040, AR5K_INI_FLAG_511X, { \ { 0, }, \ @@ -2011,7 +2012,7 @@ struct ath5k_ar5212_ini_mode { { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } \ } }, \ { 0x9858, AR5K_INI_FLAG_511X, { \ - { 0, }, \ + { 0, }, \ { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } \ } }, \ { 0x9860, AR5K_INI_FLAG_511X, { \ commit 1c1ef53f99c819920530e54a9bc91a1117e7bc97 Author: Jiri Slaby Date: Thu Aug 9 08:41:49 2007 +0200 get rid of bitfields diff --git a/ath5k_base.c b/ath5k_base.c index d8f4b8e..9002585 100644 --- a/ath5k_base.c +++ b/ath5k_base.c @@ -735,7 +735,8 @@ static u32 ath_calcrxfilter(struct ath_softc *sc) AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM; if (opmode != IEEE80211_IF_TYPE_STA) rfilt |= AR5K_RX_FILTER_PROBEREQ; - if (opmode != IEEE80211_IF_TYPE_AP && sc->promisc) + if (opmode != IEEE80211_IF_TYPE_AP && test_bit(ATH_STAT_PROMISC, + sc->status)) rfilt |= AR5K_RX_FILTER_PROM; if (opmode == IEEE80211_IF_TYPE_STA || opmode == IEEE80211_IF_TYPE_IBSS) rfilt |= AR5K_RX_FILTER_BEACON; @@ -936,7 +937,7 @@ static void ath_draintxq(struct ath_softc *sc) int i; /* XXX return value */ - if (likely(!sc->invalid)) { + if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) { /* don't touch the hardware if marked invalid */ (void)ath5k_hw_stop_tx_dma(ah, sc->bhalq); DPRINTF(sc, ATH_DEBUG_RESET, "%s: beacon queue %x\n", __func__, @@ -963,7 +964,8 @@ static int ath_stop_locked(struct ath_softc *sc) { struct ath_hw *ah = sc->ah; - DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__, sc->invalid); + DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__, + test_bit(ATH_STAT_INVALID, sc->status)); /* * Shutdown the hardware and driver: @@ -982,16 +984,16 @@ static int ath_stop_locked(struct ath_softc *sc) */ ieee80211_stop_queues(sc->hw); - if (!sc->invalid) { - if (sc->led_soft) { + if (!test_bit(ATH_STAT_INVALID, sc->status)) { + if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { del_timer_sync(&sc->led_tim); ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); - sc->led_blinking = 0; + __clear_bit(ATH_STAT_LEDBLINKING, sc->status); } ath5k_hw_set_intr(ah, 0); } ath_draintxq(sc); - if (!sc->invalid) { + if (!test_bit(ATH_STAT_INVALID, sc->status)) { ath_stoprecv(sc); ath5k_hw_phy_disable(ah); } else @@ -1012,7 +1014,7 @@ static int ath_stop_hw(struct ath_softc *sc) mutex_lock(&sc->lock); ret = ath_stop_locked(sc); - if (ret == 0 && !sc->invalid) { + if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { /* * Set the chip in full sleep mode. Note that we are * careful to do this only when bringing the interface @@ -1047,7 +1049,7 @@ static int ath_stop_hw(struct ath_softc *sc) static void ath_setcurmode(struct ath_softc *sc, unsigned int mode) { - if (unlikely(sc->led_soft)) { + if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) { /* from Atheros NDIS driver, w/ permission */ static const struct { u16 rate; /* tx/rx 802.11 rate */ @@ -1414,8 +1416,11 @@ static void ath_set_multicast_list(struct ieee80211_hw *hw, unsigned int prom = !!(flags & IFF_PROMISC); u32 rfilt; - if (sc->promisc != prom) { - sc->promisc = prom; + if (test_bit(ATH_STAT_PROMISC, sc->status) != prom) { + if (prom) + __set_bit(ATH_STAT_PROMISC, sc->status); + else + __clear_bit(ATH_STAT_PROMISC, sc->status); rfilt = ath_calcrxfilter(sc); ath5k_hw_set_rx_filter(sc->ah, rfilt); } @@ -1443,19 +1448,19 @@ static int ath_set_key(struct ieee80211_hw *hw, set_key_cmd cmd, goto unlock; } - set_bit(key->keyidx, sc->keymap); + __set_bit(key->keyidx, sc->keymap); key->hw_key_idx = key->keyidx; key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT; break; case DISABLE_KEY: ath5k_hw_reset_key(sc->ah, key->keyidx); - clear_bit(key->keyidx, sc->keymap); + __clear_bit(key->keyidx, sc->keymap); break; case REMOVE_ALL_KEYS: { unsigned int i; for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) { ath5k_hw_reset_key(sc->ah, i); - clear_bit(i, sc->keymap); + __clear_bit(i, sc->keymap); } break; } @@ -1580,10 +1585,10 @@ static void ath_led_off(unsigned long data) { struct ath_softc *sc = (void *)data; - if (sc->led_endblink) - sc->led_blinking = 0; + if (test_bit(ATH_STAT_LEDENDBLINK, sc->status)) + __clear_bit(ATH_STAT_LEDBLINKING, sc->status); else { - sc->led_endblink = 1; + __set_bit(ATH_STAT_LEDENDBLINK, sc->status); ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on); mod_timer(&sc->led_tim, jiffies + sc->led_off); } @@ -1597,18 +1602,18 @@ static void ath_led_blink(struct ath_softc *sc, unsigned int on, { DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on); - sc->led_blinking = 1; - sc->led_endblink = 0; + __set_bit(ATH_STAT_LEDBLINKING, sc->status); + __clear_bit(ATH_STAT_LEDENDBLINK, sc->status); sc->led_off = off; mod_timer(&sc->led_tim, jiffies + on); } static void ath_led_event(struct ath_softc *sc, int event) { - if (likely(!sc->led_soft)) - return; - if (unlikely(sc->led_blinking)) /* don't interrupt active blink */ + if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status))) return; + if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status))) + return; /* don't interrupt active blink */ switch (event) { case ATH_LED_TX: ath_led_blink(sc, sc->hwmap[sc->led_txrate].ledon, @@ -1628,7 +1633,8 @@ static irqreturn_t ath_intr(int irq, void *dev_id) enum ath5k_int status; unsigned int counter = 1000; - if (unlikely(sc->invalid || !ath5k_hw_is_intr_pending(ah))) + if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || + !ath5k_hw_is_intr_pending(ah))) return IRQ_NONE; do { @@ -2068,7 +2074,8 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) * return false w/o doing anything. MAC's that do * support it will return true w/o doing anything. */ - sc->mrretry = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); + if (ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0)) + __set_bit(ATH_STAT_MRRETRY, sc->status); /* * Reset the key cache since some parts do not @@ -2130,7 +2137,6 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) setup_timer(&sc->calib_tim, ath_calibrate, (unsigned long)sc); setup_timer(&sc->led_tim, ath_led_off, (unsigned long)sc); - sc->led_blinking = 0; sc->led_on = 0; /* low true */ /* * Auto-enable soft led processing for IBM cards and for @@ -2139,15 +2145,15 @@ static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) */ if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) { - sc->led_soft = 1; + __set_bit(ATH_STAT_LEDSOFT, sc->status); sc->led_pin = 0; } /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */ if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) { - sc->led_soft = 1; + __set_bit(ATH_STAT_LEDSOFT, sc->status); sc->led_pin = 0; } - if (sc->led_soft) { + if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { ath5k_hw_set_gpio_output(ah, sc->led_pin); ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); } @@ -2306,7 +2312,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, #if AR_DEBUG sc->debug = ath_debug; #endif - sc->invalid = 1; + __set_bit(ATH_STAT_INVALID, sc->status); sc->iobase = mem; sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ sc->opmode = IEEE80211_IF_TYPE_STA; @@ -2338,7 +2344,7 @@ static int __devinit ath_pci_probe(struct pci_dev *pdev, sc->ah->ah_phy_revision & 0xf); /* ready to process interrupts */ - sc->invalid = 0; + __clear_bit(ATH_STAT_INVALID, sc->status); return 0; err_ah: @@ -2377,7 +2383,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct ath_softc *sc = hw->priv; - if (sc->led_soft) + if (test_bit(ATH_STAT_LEDSOFT, sc->status)) ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); ath_stop_hw(sc); @@ -2411,7 +2417,7 @@ static int ath_pci_resume(struct pci_dev *pdev) pci_write_config_byte(pdev, 0x41, 0); ath_init(sc); - if (sc->led_soft) { + if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { ath5k_hw_set_gpio_output(sc->ah, sc->led_pin); ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0); } diff --git a/ath5k_base.h b/ath5k_base.h index 39ad8f9..15560ad 100644 --- a/ath5k_base.h +++ b/ath5k_base.h @@ -138,9 +138,13 @@ struct ath_softc { size_t desc_len; /* size of TX/RX descriptors */ u16 cachelsz; /* cache line size */ - unsigned int invalid : 1, /* disable hardware accesses */ - mrretry : 1, /* multi-rate retry support */ - promisc : 1; + DECLARE_BITMAP(status, 6); +#define ATH_STAT_INVALID 0 /* disable hardware accesses */ +#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */ +#define ATH_STAT_PROMISC 2 +#define ATH_STAT_LEDBLINKING 3 /* LED blink operation active */ +#define ATH_STAT_LEDENDBLINK 4 /* finish LED blink operation */ +#define ATH_STAT_LEDSOFT 5 /* enable LED gpio status */ unsigned int curmode; /* current phy mode */ struct ieee80211_channel *curchan; /* current h/w channel */ @@ -162,10 +166,7 @@ struct ath_softc { unsigned int led_pin, /* GPIO pin for driving LED */ led_on, /* pin setting for LED on */ - led_off, /* off time for current blink */ - led_blinking: 1,/* LED blink operation active */ - led_endblink: 1,/* finish LED blink operation */ - led_soft: 1; /* enable LED gpio status */ + led_off; /* off time for current blink */ struct timer_list led_tim; /* led off timer */ u8 led_rxrate; /* current rx rate for LED */ u8 led_txrate; /* current tx rate for LED */