Index: ar5xxx.c =================================================================== --- ar5xxx.c (revision 1948) +++ ar5xxx.c (revision 1972) @@ -1,7 +1,6 @@ -/* $OpenBSD: ar5xxx.c,v 1.32 2005/12/18 17:59:58 reyk Exp $ */ - /* - * Copyright (c) 2004, 2005 Reyk Floeter + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -14,6 +13,8 @@ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ */ /* @@ -95,27 +96,27 @@ ar5k_ar5212_attach }, }; -static const HAL_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A; -static const HAL_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B; -static const HAL_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G; -static const HAL_RATE_TABLE ar5k_rt_turbo = AR5K_RATES_TURBO; -static const HAL_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR; +static const AR5K_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A; +static const AR5K_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B; +static const AR5K_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G; +static const AR5K_RATE_TABLE ar5k_rt_turbo = AR5K_RATES_TURBO; +static const AR5K_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR; int ar5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); int ar5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); u_int16_t ar5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); -HAL_BOOL ar5k_ar5110_channel(struct ath_hal *, HAL_CHANNEL *); -u_int32_t ar5k_ar5110_chan2athchan(HAL_CHANNEL *); -HAL_BOOL ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *); -HAL_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *); -HAL_BOOL ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *); -HAL_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); +AR5K_BOOL ar5k_ar5110_channel(struct ath_hal *, AR5K_CHANNEL *); +u_int32_t ar5k_ar5110_chan2athchan(AR5K_CHANNEL *); +AR5K_BOOL ar5k_ar5111_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *); +AR5K_BOOL ar5k_ar5112_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); -HAL_BOOL ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); -HAL_BOOL ar5k_ar5112_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); +AR5K_BOOL ar5k_ar5111_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +AR5K_BOOL ar5k_ar5112_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); u_int ar5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, - u_int32_t, u_int32_t, HAL_BOOL); + u_int32_t, u_int32_t, AR5K_BOOL); /* * Supported channels @@ -170,14 +171,14 @@ * Fills in the HAL structure and initialises the device */ struct ath_hal * /*O.K. -added country code + get regdomain-*/ -ath_hal_attach(u_int16_t device, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) +ath_hal_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, AR5K_BUS_HANDLE sh, AR5K_STATUS *status) { struct ath_hal *hal = NULL; ar5k_attach_t *attach = NULL; u_int8_t mac[IEEE80211_ADDR_LEN]; int i; - *status = HAL_EINVAL; + *status = AR5K_EINVAL; /* * Call the chipset-dependent attach routine by device id @@ -189,14 +190,14 @@ } if (attach == NULL) { - *status = HAL_ENXIO; + *status = AR5K_ENOTSUPP; AR5K_PRINTF("device not supported: 0x%04x\n", device); return (NULL); } if ((hal = malloc(sizeof(struct ath_hal), M_DEVBUF, M_NOWAIT)) == NULL) { - *status = HAL_ENOMEM; + *status = AR5K_ENOMEM; AR5K_PRINT("out of memory\n"); return (NULL); } @@ -217,17 +218,16 @@ hal->ah_country_code = AR5K_TUNE_CTRY; ar5k_get_regdomain(hal); - hal->ah_abi = HAL_ABI_VERSION; - hal->ah_op_mode = HAL_M_STA; + hal->ah_op_mode = AR5K_M_STA; hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; - hal->ah_turbo = AH_FALSE; + hal->ah_turbo = FALSE; hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; hal->ah_imr = 0; hal->ah_atim_window = 0; hal->ah_aifs = AR5K_TUNE_AIFS; hal->ah_cw_min = AR5K_TUNE_CWMIN; hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; - hal->ah_software_retry = AH_FALSE; + hal->ah_software_retry = FALSE; hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; switch (device) { @@ -237,13 +237,13 @@ /* * Known single chip solutions */ - hal->ah_single_chip = AH_TRUE; + hal->ah_single_chip = TRUE; break; default: /* * Multi chip solutions */ - hal->ah_single_chip = AH_FALSE; + hal->ah_single_chip = FALSE; break; } @@ -259,14 +259,14 @@ */ if (ar5k_eeprom_init(hal) != 0) { - *status = HAL_EELOCKED; + *status = AR5K_EELOCKED; AR5K_PRINT("unable to init EEPROM\n"); goto failed; } /* Get misc capabilities */ - if (hal->ah_get_capabilities(hal) != AH_TRUE) { - *status = HAL_EEREAD; + if (hal->ah_get_capabilities(hal) != TRUE) { + *status = AR5K_EEREAD; AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", device); goto failed; @@ -274,7 +274,7 @@ /* Get MAC address */ if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) { - *status = HAL_EEBADMAC; + *status = AR5K_EEBADMAC; AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", device); goto failed; @@ -283,15 +283,15 @@ hal->ah_set_lladdr(hal, mac); /* Get rate tables */ - if (hal->ah_capabilities.cap_mode & HAL_MODE_11A) + if (hal->ah_capabilities.cap_mode & AR5K_MODE_11A) ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a); - if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) + if (hal->ah_capabilities.cap_mode & AR5K_MODE_11B) ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b); - if (hal->ah_capabilities.cap_mode & HAL_MODE_11G) + if (hal->ah_capabilities.cap_mode & AR5K_MODE_11G) ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g); - if (hal->ah_capabilities.cap_mode & HAL_MODE_TURBO) + if (hal->ah_capabilities.cap_mode & AR5K_MODE_TURBO) ar5k_rt_copy(&hal->ah_rt_turbo, &ar5k_rt_turbo); - if (hal->ah_capabilities.cap_mode & HAL_MODE_XR) + if (hal->ah_capabilities.cap_mode & AR5K_MODE_XR) ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr); /* Initialize the gain optimization values */ @@ -311,7 +311,7 @@ hal->ah_gain.g_active = 1; } - *status = HAL_OK; + *status = AR5K_OK; return (hal); @@ -321,58 +321,58 @@ } u_int16_t /*O.K.*/ -ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates, - u_int32_t frame_length, u_int16_t rate_index, HAL_BOOL short_preamble) +ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates, + u_int32_t frame_length, u_int16_t rate_index, AR5K_BOOL short_preamble) { - const HAL_RATE *rate; + const AR5K_RATE *rate; u_int32_t value; - AR5K_ASSERT_ENTRY(rate_index, rates->rateCount); + AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); /* * Get rate by index */ - rate = &rates->info[rate_index]; + rate = &rates->rates[rate_index]; /* * Calculate the transmission time by operation (PHY) mode */ - switch (rate->phy) { - case IEEE80211_T_CCK: + switch (rate->modulation) { + case MODULATION_CCK: /* * CCK / DS mode (802.11b) */ - value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length, - (short_preamble && rate->shortPreamble)); + value = AR5K_CCK_TX_TIME(rate->rate_kbps, frame_length, + (short_preamble && (rate->modulation == MODULATION_CCK_SP))); break; - case IEEE80211_T_OFDM: + case MODULATION_OFDM: /* * Orthogonal Frequency Division Multiplexing */ - if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0) + if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) return (0); - value = AR5K_OFDM_TX_TIME(rate->rateKbps, frame_length); + value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length); break; - case IEEE80211_T_TURBO: + case MODULATION_TURBO: /* * Orthogonal Frequency Division Multiplexing * Atheros "Turbo Mode" (doubled rates) */ - if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0) + if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) return (0); - value = AR5K_TURBO_TX_TIME(rate->rateKbps, frame_length); + value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length); break; - case IEEE80211_T_XR: + case MODULATION_XR: /* * Orthogonal Frequency Division Multiplexing * Atheros "eXtended Range" (XR) */ - if (AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0) + if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) return (0); - value = AR5K_XR_TX_TIME(rate->rateKbps, frame_length); + value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length); break; default: @@ -384,50 +384,86 @@ /*Following 2 functions come from net80211 M.F.*/ - +/* + * Convert MHz frequency to IEEE channel number. + */ u_int -ath_hal_mhz2ieee(u_int mhz, u_int flags) +ath_hal_mhz2ieee(u_int freq, u_int flags) { - return (ieee80211_mhz2ieee(mhz, flags)); + if (flags & CHANNEL_2GHZ) { /* 2GHz band */ + if (freq == 2484) /* Japan */ + return 14; + if ((freq >= 2412) && (freq < 2484)) /* don't number non-IEEE channels */ + return (freq - 2407) / 5; + return 0; + } else if (flags & CHANNEL_5GHZ) { /* 5Ghz band */ + if ((freq >= 5150) && (freq <= 5825)) /* don't number non-IEEE channels */ + return (freq - 5000) / 5; + return 0; + } else { + /* something is fishy, don't do anything */ + return 0; + } } +/* + * Convert IEEE channel number to MHz frequency. + */ u_int -ath_hal_ieee2mhz(u_int ieee, u_int flags) +ath_hal_ieee2mhz(u_int chan, u_int flags) { - return (ieee80211_ieee2mhz(ieee, flags)); + if (flags & CHANNEL_2GHZ) { /* 2GHz band */ + if (chan == 14) + return 2484; + if (chan < 14) + return 2407 + chan * 5; + else + return 2512 + ((chan - 15) * 20); + } else if (flags & CHANNEL_5GHZ) /* 5Ghz band */ + return 5000 + (chan * 5); + else { /* either, guess */ + if (chan == 14) + return 2484; + if (chan < 14) /* 0-13 */ + return 2407 + chan * 5; + if (chan < 27) /* 15-26 */ + return 2512 + ((chan - 15) * 20); + return 5000 + (chan * 5); + } } -HAL_BOOL /*O.K.*/ + +AR5K_BOOL /*O.K.*/ ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) { /* Check if the channel is in our supported range */ - if (flags & IEEE80211_CHAN_2GHZ) { + if (flags & CHANNEL_2GHZ) { if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) - return (AH_TRUE); - } else if (flags & IEEE80211_CHAN_5GHZ) { + return (TRUE); + } else if (flags & CHANNEL_5GHZ) { if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) - return (AH_TRUE); + return (TRUE); } - return (AH_FALSE); + return (FALSE); } -HAL_BOOL /*Ported, added SUPERCHANNEL & country code + FIX in debug mode*/ -ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels, - u_int max_channels, u_int *channels_size, HAL_CTRY_CODE country, u_int16_t mode, - HAL_BOOL outdoor, HAL_BOOL extended) +AR5K_BOOL /*Ported, added SUPERCHANNEL & country code + FIX in debug mode*/ +ath_hal_init_channels(struct ath_hal *hal, AR5K_CHANNEL *channels, + u_int max_channels, u_int *channels_size, AR5K_CTRY_CODE country, u_int16_t mode, + AR5K_BOOL outdoor, AR5K_BOOL extended) { u_int i, c; u_int32_t domain_current; u_int domain_5ghz, domain_2ghz; - HAL_CHANNEL *all_channels; - HAL_CTRY_CODE country_current; + AR5K_CHANNEL *all_channels; + AR5K_CTRY_CODE country_current; - if ((all_channels = malloc(sizeof(HAL_CHANNEL) * max_channels, + if ((all_channels = malloc(sizeof(AR5K_CHANNEL) * max_channels, M_TEMP, M_NOWAIT)) == NULL) - return (AH_FALSE); + return (FALSE); i = c = 0; domain_current = hal->ah_regdomain; @@ -442,9 +478,9 @@ u_int flags; min = ath_hal_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN, - IEEE80211_CHAN_2GHZ); + CHANNEL_2GHZ); max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX, - IEEE80211_CHAN_2GHZ); + CHANNEL_2GHZ); flags = CHANNEL_B /*| CHANNEL_TG | (hal->ah_version == AR5K_AR5211 ? CHANNEL_PUREG : CHANNEL_G)*/; @@ -452,22 +488,22 @@ debugchan: for (i = min; i <= max && c < max_channels; i++) { freq = ath_hal_ieee2mhz(i, flags); - if (ar5k_check_channel(hal, freq, flags) == AH_FALSE) + if (ar5k_check_channel(hal, freq, flags) == FALSE) continue; - all_channels[c].c_channel = freq; - all_channels[c++].c_channel_flags = flags; + all_channels[c].freq = freq; + all_channels[c++].channel_flags = flags; } /* If is there to protect from infinite loop */ - if (flags & IEEE80211_CHAN_2GHZ) { + if (flags & CHANNEL_2GHZ) { /* ath_hal_mhz2ieee returns 1 for IEEE80211_CHANNELS_5GHZ_MIN for loop starts from 1 and all channels are marked as 5GHz M.F.*/ // min = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, -// IEEE80211_CHAN_5GHZ); +// CHANNEL_5GHZ); /* Continue from where we stoped, skip last 2GHz channel */ min = max + 1; max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, - IEEE80211_CHAN_5GHZ); + CHANNEL_5GHZ); flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR; goto debugchan; } @@ -490,7 +526,7 @@ /* Check if channel is supported by the chipset */ if (ar5k_check_channel(hal, ar5k_5ghz_channels[i].rc_channel, - IEEE80211_CHAN_5GHZ) == AH_FALSE) + CHANNEL_5GHZ) == FALSE) continue; /* Match regulation domain */ @@ -499,16 +535,16 @@ continue; /* Match modes */ - if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) { - all_channels[c].c_channel_flags = CHANNEL_T; + if (ar5k_5ghz_channels[i].rc_mode & CHANNEL_TURBO) { + all_channels[c].channel_flags = CHANNEL_T; } else if (ar5k_5ghz_channels[i].rc_mode & - IEEE80211_CHAN_OFDM) { - all_channels[c].c_channel_flags = CHANNEL_A; + CHANNEL_OFDM) { + all_channels[c].channel_flags = CHANNEL_A; } else continue; /* Write channel and increment counter */ - all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel; + all_channels[c++].freq = ar5k_5ghz_channels[i].rc_channel; } /* @@ -520,7 +556,7 @@ /* Check if channel is supported by the chipset */ if (ar5k_check_channel(hal, ar5k_2ghz_channels[i].rc_channel, - IEEE80211_CHAN_2GHZ) == AH_FALSE) + CHANNEL_2GHZ) == FALSE) continue; /* Match regulation domain */ @@ -529,29 +565,29 @@ continue; /* Match modes */ - if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) && - (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK)) - all_channels[c].c_channel_flags = CHANNEL_B; + if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11B) && + (ar5k_2ghz_channels[i].rc_mode & CHANNEL_CCK)) + all_channels[c].channel_flags = CHANNEL_B; - if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) && - (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)) { - all_channels[c].c_channel_flags |= + if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11G) && + (ar5k_2ghz_channels[i].rc_mode & CHANNEL_OFDM)) { + all_channels[c].channel_flags |= hal->ah_version == AR5K_AR5211 ? CHANNEL_PUREG : CHANNEL_G; if (ar5k_2ghz_channels[i].rc_mode & - IEEE80211_CHAN_TURBO) - all_channels[c].c_channel_flags |= CHANNEL_TG; + CHANNEL_TURBO) + all_channels[c].channel_flags |= CHANNEL_TG; } /* Write channel and increment counter */ - all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel; + all_channels[c++].freq = ar5k_2ghz_channels[i].rc_channel; } done: - bcopy(all_channels, channels, sizeof(HAL_CHANNEL) * max_channels); + bcopy(all_channels, channels, sizeof(AR5K_CHANNEL) * max_channels); *channels_size = c; free(all_channels, M_TEMP); - return (AH_TRUE); + return (TRUE); } /* @@ -593,19 +629,19 @@ * Limit ~1/s */ -// if (hal->ah_radar.r_last_channel.channel == -// hal->ah_current_channel.channel && +// if (hal->ah_radar.r_last_channel.freq == +// hal->ah_current_channel.freq && // tick < (hal->ah_radar.r_last_alert + hz)) return; -/* hal->ah_radar.r_last_channel.channel = - hal->ah_current_channel.channel; - hal->ah_radar.r_last_channel.c_channel_flags = - hal->ah_current_channel.c_channel_flags; +/* hal->ah_radar.r_last_channel.freq = + hal->ah_current_channel.freq; + hal->ah_radar.r_last_channel.channel_flags = + hal->ah_current_channel.channel_flags; hal->ah_radar.r_last_alert = tick; AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", - hal->ah_radar.r_last_alert, hal->ah_current_channel.channel);*/ + hal->ah_radar.r_last_alert, hal->ah_current_channel.freq);*/ } u_int16_t /*O.K.*/ @@ -642,7 +678,7 @@ u_int16_t code; #endif - ar5k_eeprom_regulation_domain(hal, AH_FALSE, &ieee_regdomain); + ar5k_eeprom_regulation_domain(hal, FALSE, &ieee_regdomain); hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; #ifdef COUNTRYCODE @@ -674,35 +710,35 @@ } u_int /*O.K.*/ -ar5k_htoclock(u_int usec, HAL_BOOL turbo) +ar5k_htoclock(u_int usec, AR5K_BOOL turbo) { - return (turbo == AH_TRUE ? (usec * 80) : (usec * 40)); + return (turbo == TRUE ? (usec * 80) : (usec * 40)); } u_int /*O.K.*/ -ar5k_clocktoh(u_int clock, HAL_BOOL turbo) +ar5k_clocktoh(u_int clock, AR5K_BOOL turbo) { - return (turbo == AH_TRUE ? (clock / 80) : (clock / 40)); + return (turbo == TRUE ? (clock / 80) : (clock / 40)); } void /*O.K.*/ -ar5k_rt_copy(HAL_RATE_TABLE *dst, const HAL_RATE_TABLE *src) +ar5k_rt_copy(AR5K_RATE_TABLE *dst, const AR5K_RATE_TABLE *src) { - bzero(dst, sizeof(HAL_RATE_TABLE)); - dst->rateCount = src->rateCount; - bcopy(src->info, dst->info, sizeof(dst->info)); + bzero(dst, sizeof(AR5K_RATE_TABLE)); + dst->rate_count = src->rate_count; + bcopy(src->rates, dst->rates, sizeof(dst->rates)); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, - u_int32_t val, HAL_BOOL is_set) + u_int32_t val, AR5K_BOOL is_set) { int i; u_int32_t data; for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { data = AR5K_REG_READ(reg); - if ((is_set == AH_TRUE) && (data & flag)) + if ((is_set == TRUE) && (data & flag)) break; else if ((data & flag) == val) break; @@ -710,9 +746,9 @@ } if (i <= 0) - return (AH_FALSE); + return (FALSE); - return (AH_TRUE); + return (TRUE); } /* @@ -781,13 +817,13 @@ /* Get antenna modes */ hal->ah_antenna[mode][0] = (ee->ee_ant_control[mode][0] << 4) | 0x1; - hal->ah_antenna[mode][HAL_ANT_FIXED_A] = + hal->ah_antenna[mode][AR5K_ANT_FIXED_A] = ee->ee_ant_control[mode][1] | (ee->ee_ant_control[mode][2] << 6) | (ee->ee_ant_control[mode][3] << 12) | (ee->ee_ant_control[mode][4] << 18) | (ee->ee_ant_control[mode][5] << 24); - hal->ah_antenna[mode][HAL_ANT_FIXED_B] = + hal->ah_antenna[mode][AR5K_ANT_FIXED_B] = ee->ee_ant_control[mode][6] | (ee->ee_ant_control[mode][7] << 6) | (ee->ee_ant_control[mode][8] << 12) | @@ -919,7 +955,7 @@ } if (cksum != AR5K_EEPROM_INFO_CKSUM) { AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); - return (HAL_EEBADSUM); + return (AR5K_EEBADSUM); } #endif @@ -1086,12 +1122,12 @@ bzero(&mac_d, IEEE80211_ADDR_LEN); if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) - return (HAL_EIO); + return (AR5K_EIO); for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { if (hal->ah_eeprom_read(hal, offset, &data) != 0) - return (HAL_EIO); + return (AR5K_EIO); total += data; mac_d[octet + 1] = data & 0xff; @@ -1102,22 +1138,22 @@ bcopy(mac_d, mac, IEEE80211_ADDR_LEN); if ((!total) || total == (3 * 0xffff)) - return (HAL_EINVAL); + return (AR5K_EINVAL); return (0); } -HAL_BOOL /*O.K*/ -ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write, +AR5K_BOOL /*O.K*/ +ar5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, ieee80211_regdomain_t *regdomain) { u_int16_t ee_regdomain; /* Read current value */ - if (write != AH_TRUE) { + if (write != TRUE) { ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; *regdomain = ar5k_regdomain_to_ieee(ee_regdomain); - return (AH_TRUE); + return (TRUE); } ee_regdomain = ar5k_regdomain_from_ieee(*regdomain); @@ -1125,36 +1161,36 @@ /* Try to write a new value */ if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_EEPROM_PROTECT_WR_128_191) - return (AH_FALSE); + return (FALSE); if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, ee_regdomain) != 0) - return (AH_FALSE); + return (FALSE); hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; - return (AH_TRUE); + return (TRUE); } /* * PHY/RF access functions */ -HAL_BOOL /*O.K.*/ -ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL /*O.K.*/ +ar5k_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { - HAL_BOOL ret; + AR5K_BOOL ret; /* * Check bounds supported by the PHY * (don't care about regulation restrictions at this point) */ - if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min || - channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) && - (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min || - channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) { + if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) && + (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { AR5K_PRINTF("channel out of supported range (%u MHz)\n", - channel->channel); - return (AH_FALSE); + channel->freq); + return (FALSE); } /* @@ -1167,19 +1203,19 @@ else ret = ar5k_ar5112_channel(hal, channel); - if (ret == AH_FALSE) + if (ret == FALSE) return (ret); - hal->ah_current_channel.c_channel = channel->c_channel; - hal->ah_current_channel.c_channel_flags = channel->c_channel_flags; - hal->ah_turbo = channel->c_channel_flags == CHANNEL_T ? - AH_TRUE : AH_FALSE; + hal->ah_current_channel.freq = channel->freq; + hal->ah_current_channel.channel_flags = channel->channel_flags; + hal->ah_turbo = channel->channel_flags == CHANNEL_T ? + TRUE : FALSE; - return (AH_TRUE); + return (TRUE); } u_int32_t /*O.K.*/ -ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel) +ar5k_ar5110_chan2athchan(AR5K_CHANNEL *channel) { u_int32_t athchan; @@ -1189,15 +1225,15 @@ * newer chipsets like the AR5212A who have a completely * different RF/PHY part. */ - athchan = (ar5k_bitswap((ath_hal_mhz2ieee(channel->c_channel, - channel->c_channel_flags) - 24) / 2, 5) << 1) | + athchan = (ar5k_bitswap((ath_hal_mhz2ieee(channel->freq, + channel->channel_flags) - 24) / 2, 5) << 1) | (1 << 6) | 0x1; return (athchan); } -HAL_BOOL /*O.K.*/ -ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL /*O.K.*/ +ar5k_ar5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int32_t data; @@ -1209,10 +1245,10 @@ AR5K_PHY_WRITE(0x30, 0); AR5K_DELAY(1000); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan) { int channel; @@ -1233,13 +1269,13 @@ athchan->a2_athchan = ((channel - 14) * 4) + 132; athchan->a2_flags = 0x46; } else - return (AH_FALSE); + return (FALSE); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ -ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL /*O.K.*/ +ar5k_ar5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int ieee_channel, ath_channel; u_int32_t data0, data1, clock; @@ -1249,14 +1285,14 @@ * Set the channel on the AR5111 radio */ data0 = data1 = 0; - ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->c_channel, - channel->c_channel_flags); + ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, + channel->channel_flags); - if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { + if (channel->channel_flags & CHANNEL_2GHZ) { /* Map 2GHz channel to 5GHz Atheros channel ID */ if (ar5k_ar5111_chan2athchan(ieee_channel, - &ath_channel_2ghz) == AH_FALSE) - return (AH_FALSE); + &ath_channel_2ghz) == FALSE) + return (FALSE); ath_channel = ath_channel_2ghz.a2_athchan; data0 = ((ar5k_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) @@ -1276,17 +1312,17 @@ AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ -ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL /*O.K.*/ +ar5k_ar5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int32_t data, data0, data1, data2; u_int16_t c; data = data0 = data1 = data2 = 0; - c = channel->c_channel; + c = channel->freq; /* * Set the channel on the AR5112 or newer @@ -1299,7 +1335,7 @@ data0 = ((2 * (c - 672)) - 3040) / 10; data1 = 0; } else - return (AH_FALSE); + return (FALSE); data0 = ar5k_bitswap((data0 << 2) & 0xff, 8); } else { @@ -1313,7 +1349,7 @@ data0 = ar5k_bitswap((c - 4800) / 5, 8); data2 = ar5k_bitswap(1, 2); } else - return (AH_FALSE); + return (FALSE); } data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; @@ -1321,12 +1357,12 @@ AR5K_PHY_WRITE(0x27, data & 0xff); AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); - return (AH_TRUE); + return (TRUE); } u_int /*O.K. data initialized */ ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, - u_int32_t first, u_int32_t col, HAL_BOOL set) + u_int32_t first, u_int32_t col, AR5K_BOOL set) { u_int32_t mask, entry, last, data, shift, position; int32_t left; @@ -1347,7 +1383,7 @@ entry = ((first - 1) / 8) + offset; position = (first - 1) % 8; - if (set == AH_TRUE) + if (set == TRUE) data = ar5k_bitswap(reg, bits); for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { @@ -1355,7 +1391,7 @@ mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8); - if (set == AH_TRUE) { + if (set == TRUE) { rf[entry] &= ~mask; rf[entry] |= ((data << position) << (col * 8)) & mask; data >>= (8 - position); @@ -1368,7 +1404,7 @@ left -= 8 - position; } - data = set == AH_TRUE ? 1 : ar5k_bitswap(data, bits); + data = set == TRUE ? 1 : ar5k_bitswap(data, bits); return (data); } @@ -1385,10 +1421,10 @@ rf = hal->ah_rf_banks; hal->ah_gain.g_f_corr = 0; - if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1) + if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1) return (0); - step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE); + step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE); mix = hal->ah_gain.g_step->gos_param[0]; switch (mix) { @@ -1409,7 +1445,7 @@ return (hal->ah_gain.g_f_corr); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_rfregs_gain_readback(struct ath_hal *hal) { u_int32_t step, mix, level[4]; @@ -1422,7 +1458,7 @@ if (hal->ah_radio == AR5K_AR5111) { step = ar5k_rfregs_op(rf, hal->ah_offset[7], - 0, 6, 37, 0, AH_FALSE); + 0, 6, 37, 0, FALSE); level[0] = 0; level[1] = (step == 0x3f) ? 0x32 : step + 4; level[2] = (step != 0x3f) ? 0x40 : level[0]; @@ -1434,7 +1470,7 @@ (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); } else { mix = ar5k_rfregs_op(rf, hal->ah_offset[7], - 0, 1, 36, 0, AH_FALSE); + 0, 1, 36, 0, FALSE); level[0] = level[2] = 0; if (mix == 1) { @@ -1508,11 +1544,11 @@ return (ret); } -HAL_BOOL /*O.K.*/ -ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) +AR5K_BOOL /*O.K.*/ +ar5k_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) { ar5k_rfgain_t *func = NULL; - HAL_BOOL ret; + AR5K_BOOL ret; if (hal->ah_radio == AR5K_AR5111) { hal->ah_rf_banks_size = sizeof(ar5111_rf); @@ -1524,27 +1560,27 @@ hal->ah_rf_banks_size = sizeof(ar5112_rf); func = ar5k_ar5112_rfregs; } else - return (AH_FALSE); + return (FALSE); if (hal->ah_rf_banks == NULL) { /* XXX do extra checks? */ if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, M_DEVBUF, M_NOWAIT)) == NULL) { AR5K_PRINT("out of memory\n"); - return (AH_FALSE); + return (FALSE); } } ret = (func)(hal, channel, mode); - if (ret == AH_TRUE) - hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; + if (ret == TRUE) + hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; return (ret); } -HAL_BOOL /*O.K*/ -ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) +AR5K_BOOL /*O.K*/ +ar5k_ar5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) { struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; const u_int rf_size = AR5K_ELEMENTS(ar5111_rf); @@ -1561,7 +1597,7 @@ if (ar5111_rf[i].rf_bank >= AR5K_AR5111_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (AH_FALSE); + return (FALSE); } if (bank != ar5111_rf[i].rf_bank) { @@ -1572,62 +1608,62 @@ rf[i] = ar5111_rf[i].rf_value[mode]; } - if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { - if (channel->c_channel_flags & IEEE80211_CHAN_B) + if (channel->channel_flags & CHANNEL_2GHZ) { + if (channel->channel_flags & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; else ee_mode = AR5K_EEPROM_MODE_11G; obdb = 0; if (!ar5k_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 119, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_ob[ee_mode][obdb], 3, 119, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 122, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_ob[ee_mode][obdb], 3, 122, 0, TRUE)) + return (FALSE); obdb = 1; } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->c_channel >= 5725 ? 3 : - (channel->c_channel >= 5500 ? 2 : - (channel->c_channel >= 5260 ? 1 : - (channel->c_channel > 4000 ? 0 : -1))); + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_84, 1, 51, 3, AH_TRUE)) - return (AH_FALSE); + ee->ee_pwd_84, 1, 51, 3, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_90, 1, 45, 3, AH_TRUE)) - return (AH_FALSE); + ee->ee_pwd_90, 1, 45, 3, TRUE)) + return (FALSE); } if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - !ee->ee_xpd[ee_mode], 1, 95, 0, AH_TRUE)) - return (AH_FALSE); + !ee->ee_xpd[ee_mode], 1, 95, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 4, 96, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_x_gain[ee_mode], 4, 96, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, AH_TRUE)) - return (AH_FALSE); + obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, AH_TRUE)) - return (AH_FALSE); + obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 29, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[7], - ee->ee_xpd[ee_mode], 1, 4, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_xpd[ee_mode], 1, 4, 0, TRUE)) + return (FALSE); /* Write RF values */ for (i = 0; i < rf_size; i++) { @@ -1635,11 +1671,11 @@ AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K*/ -ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) +AR5K_BOOL /*O.K*/ +ar5k_ar5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) { struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int rf_size; @@ -1665,7 +1701,7 @@ if (rf_ini[i].rf_bank >= AR5K_AR5112_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); - return (AH_FALSE); + return (FALSE); } if (bank != rf_ini[i].rf_bank) { @@ -1676,60 +1712,60 @@ rf[i] = rf_ini[i].rf_value[mode]; } - if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { - if (channel->c_channel_flags & IEEE80211_CHAN_B) + if (channel->channel_flags & CHANNEL_2GHZ) { + if (channel->channel_flags & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; else ee_mode = AR5K_EEPROM_MODE_11G; obdb = 0; if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 287, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_ob[ee_mode][obdb], 3, 287, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 290, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_ob[ee_mode][obdb], 3, 290, 0, TRUE)) + return (FALSE); } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->c_channel >= 5725 ? 3 : - (channel->c_channel >= 5500 ? 2 : - (channel->c_channel >= 5260 ? 1 : - (channel->c_channel > 4000 ? 0 : -1))); + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 279, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_ob[ee_mode][obdb], 3, 279, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 282, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_ob[ee_mode][obdb], 3, 282, 0, TRUE)) + return (FALSE); } #ifdef notyet ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 270, 0, AH_TRUE); + ee->ee_x_gain[ee_mode], 2, 270, 0, TRUE); ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 257, 0, AH_TRUE); + ee->ee_x_gain[ee_mode], 2, 257, 0, TRUE); #endif if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_xpd[ee_mode], 1, 302, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_xpd[ee_mode], 1, 302, 0, TRUE)) + return (FALSE); if (!ar5k_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 14, 0, AH_TRUE)) - return (AH_FALSE); + ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE)) + return (FALSE); /* Write RF values */ for (i = 0; i < rf_size; i++) AR5K_REG_WRITE(ar5112_rf[i].rf_register, rf[i]); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq) { int i; @@ -1739,7 +1775,7 @@ case AR5K_INI_PHY_5112: break; default: - return (AH_FALSE); + return (FALSE); } switch (freq) { @@ -1747,7 +1783,7 @@ case AR5K_INI_RFGAIN_5GHZ: break; default: - return (AH_FALSE); + return (FALSE); } for (i = 0; i < AR5K_ELEMENTS(ar5k_rfg); i++) { @@ -1756,14 +1792,14 @@ ar5k_rfg[i].rfg_value[phy][freq]); } - return (AH_TRUE); + return (TRUE); } /* * Common TX power setup */ void /*O.K.*/ -ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power) +ar5k_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t max_power) { u_int16_t txpower, *rates; int i, min, max, n; @@ -1801,14 +1837,14 @@ /* Functions not found in OpenBSD */ u_int /*New*/ -ath_hal_getwirelessmodes(struct ath_hal *hal, HAL_CTRY_CODE country) +ath_hal_getwirelessmodes(struct ath_hal *hal, AR5K_CTRY_CODE country) { switch(hal->ah_version){ case AR5K_AR5212: - return (HAL_MODE_108A|HAL_MODE_11B|HAL_MODE_108G); + return (AR5K_MODE_11A|AR5K_MODE_11B); case AR5K_AR5211: - return (HAL_MODE_11B|HAL_MODE_108G); + return (AR5K_MODE_11B|AR5K_MODE_108G); default : - return(HAL_MODE_11A); + return(AR5K_MODE_11A); } } Index: ar5xxx.h =================================================================== --- ar5xxx.h (revision 0) +++ ar5xxx.h (revision 1972) @@ -0,0 +1,2102 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + +/* + * HAL interface for Atheros Wireless LAN devices. + * + * ar5k is a free replacement of the binary-only HAL used by some drivers + * for Atheros chipsets. While using a different ABI, it tries to be + * source-compatible with the original (non-free) HAL interface. + * + * Many thanks to various contributors who supported the development of + * ar5k with hard work and useful information. And, of course, for all the + * people who encouraged me to continue this work which has been based + * on my initial approach found on http://team.vantronix.net/ar5k/. + */ + +#ifndef _AR5K_H +#define _AR5K_H + +/*Os dependent definitions*/ +#include "ah_osdep.h" + +/*Regulatory domain & Channel definitions*/ +#include "ieee80211_regdomain.h" + +/*Options*/ +#include "opt_ah.h" + +/* + *Translation for MadWiFi combatibility + *(damn this is changed AGAIN in if_ath.pci :P) + */ +#include "translation.h" + +/*Use with MadWiFi/net80211*/ +#include "stack_net80211.h" + + +/****************************\ + GENERIC DRIVER DEFINITIONS +\****************************/ + +/* + * C doesn't support boolean ;-( + * TODO: See if there is a bool definition somewere else + * in the kernel, we shouldn't redefine it if it does... + */ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif +typedef u_int8_t AR5K_BOOL; + +/* + * Error codes reported from HAL to the driver + */ +typedef enum { + AR5K_OK = 0, /* Everything went O.K.*/ + AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/ + AR5K_EIO = 2, /* Hardware I/O Error*/ + AR5K_EELOCKED = 3, /* Unable to access EEPROM*/ + AR5K_EEBADSUM = 4, /* Invalid EEPROM checksum*/ + AR5K_EEREAD = 5, /* Unable to get device caps from EEPROM */ + AR5K_EEBADMAC = 6, /* Unable to read MAC address from EEPROM */ + AR5K_EINVAL = 7, /* Invalid parameter to function */ + AR5K_ENOTSUPP = 8, /* Hardware revision not supported */ + AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */ +} AR5K_STATUS; + +/* + * Some tuneable values (these should be changeable by the user) + */ +#define AR5K_TUNE_DMA_BEACON_RESP 2 +#define AR5K_TUNE_SW_BEACON_RESP 10 +#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 +#define AR5K_TUNE_RADAR_ALERT FALSE +#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 +#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) +#define AR5K_TUNE_RSSI_THRES 1792 +#define AR5K_TUNE_REGISTER_TIMEOUT 20000 +#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 +#define AR5K_TUNE_BEACON_INTERVAL 100 +#define AR5K_TUNE_AIFS 2 +#define AR5K_TUNE_AIFS_11B 2 +#define AR5K_TUNE_AIFS_XR 0 +#define AR5K_TUNE_CWMIN 15 +#define AR5K_TUNE_CWMIN_11B 31 +#define AR5K_TUNE_CWMIN_XR 3 +#define AR5K_TUNE_CWMAX 1023 +#define AR5K_TUNE_CWMAX_11B 1023 +#define AR5K_TUNE_CWMAX_XR 7 +#define AR5K_TUNE_NOISE_FLOOR -72 +#define AR5K_TUNE_MAX_TXPOWER 60 +#define AR5K_TUNE_DEFAULT_TXPOWER 30 +#define AR5K_TUNE_TPC_TXPOWER TRUE +#define AR5K_TUNE_ANT_DIVERSITY TRUE +#define AR5K_TUNE_HWTXTRIES 4 + +/* token to use for aifs, cwmin, cwmax in MadWiFi */ +#define AR5K_TXQ_USEDEFAULT ((u_int32_t) -1) + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ +static const u_char etherbroadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +//#define etherbroadcastaddr 0xff + + + + +/*****************************\ + GENERIC CHIPSET DEFINITIONS +\*****************************/ + +/* MAC Chips*/ +enum ar5k_version { + AR5K_AR5210 = 0, + AR5K_AR5211 = 1, + AR5K_AR5212 = 2, +}; + +/*PHY Chips*/ +enum ar5k_radio { + AR5K_AR5110 = 0, + AR5K_AR5111 = 1, + AR5K_AR5112 = 2, +}; + +/* + * Common silicon revision/version values + */ +enum ar5k_srev_type { + AR5K_VERSION_VER, + AR5K_VERSION_REV, + AR5K_VERSION_RAD, + AR5K_VERSION_DEV +}; + +struct ar5k_srev_name { + const char *sr_name; + enum ar5k_srev_type sr_type; + u_int sr_val; +}; + +#define AR5K_SREV_NAME { \ + { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ + { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ + { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ + { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ + { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ + { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ + { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ + { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ + { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ + { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ + { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ + { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ + { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ + { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ + { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ + { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ + { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \ + { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \ + { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \ + { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ +} + +#define AR5K_SREV_UNKNOWN 0xffff + +#define AR5K_SREV_VER_AR5210 0x00 +#define AR5K_SREV_VER_AR5311 0x10 +#define AR5K_SREV_VER_AR5311A 0x20 +#define AR5K_SREV_VER_AR5311B 0x30 +#define AR5K_SREV_VER_AR5211 0x40 +#define AR5K_SREV_VER_AR5212 0x50 +#define AR5K_SREV_VER_AR5213 0x55 +#define AR5K_SREV_VER_UNSUPP 0x60 + +#define AR5K_SREV_RAD_5110 0x00 +#define AR5K_SREV_RAD_5111 0x10 +#define AR5K_SREV_RAD_5111A 0x15 +#define AR5K_SREV_RAD_2111 0x20 +#define AR5K_SREV_RAD_5112 0x30 +#define AR5K_SREV_RAD_5112A 0x35 +#define AR5K_SREV_RAD_2112 0x40 +#define AR5K_SREV_RAD_2112A 0x45 +#define AR5K_SREV_RAD_UNSUPP 0x50 + + + + +/****************\ + TX DEFINITIONS +\****************/ + +/* + * Tx Descriptor + */ +struct ath_tx_status { + u_int16_t ts_seqnum; + u_int16_t ts_tstamp; + u_int8_t ts_status; + u_int8_t ts_rate; + int8_t ts_rssi; + u_int8_t ts_shortretry; + u_int8_t ts_longretry; + u_int8_t ts_virtcol; + u_int8_t ts_antenna; +}; + +#define AR5K_TXSTAT_ALTRATE 0x80 +#define AR5K_TXERR_XRETRY 0x01 +#define AR5K_TXERR_FILT 0x02 +#define AR5K_TXERR_FIFO 0x04 + +/* + * Queue types used to classify tx queues. + */ +typedef enum { + AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ + AR5K_TX_QUEUE_DATA, /*A normal data queue*/ + AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ + AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ + AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ + AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ +} AR5K_TX_QUEUE; + +#define AR5K_NUM_TX_QUEUES 10 + +/* + * Queue syb-types to classify normal data queues. + * These are the 4 Access Categories as defined in + * WME spec. 0 is the lowest priority and 4 is the + * highest. Normal data that hasn't been classified + * goes to the Best Effort AC. + */ +typedef enum { + AR5K_WME_AC_BK = 0, /*Background traffic*/ + AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ + AR5K_WME_AC_VI, /*Video traffic*/ + AR5K_WME_AC_VO, /*Voice traffic*/ +} AR5K_TX_QUEUE_SUBTYPE; + +/* + * Queue ID numbers as returned by the HAL, each number + * represents a hw queue. If hw does not support hw queues + * (eg 5210/5211) all data goes in one queue. These match + * d80211 definitions (net80211/MadWiFi don't use them). + */ +typedef enum { + AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ + AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ + AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ + AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ + AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ + AR5K_TX_QUEUE_ID_UAPSD = 8, + AR5K_TX_QUEUE_ID_XR_DATA = 9, +} AR5K_TX_QUEUE_ID; + + +/* + * Flags to set hw queue's parameters... + */ +#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ +#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ +#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ +#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ +#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ +#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ +#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ +#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ + +/* + * A struct to hold tx queue's parameters + */ +typedef struct { + AR5K_TX_QUEUE tqi_type; /* See AR5K_TX_QUEUE */ + AR5K_TX_QUEUE_SUBTYPE tqi_subtype; /* See AR5K_TX_QUEUE_SUBTYPE */ + u_int16_t tqi_flags; /* Tx queue flags (see above) */ + u_int32_t tqi_aifs; /* Arbitrated Interframe Space */ + int32_t tqi_cw_min; /* Minimum Contention Window */ + int32_t tqi_cw_max; /* Maximum Contention Window */ + u_int32_t tqi_cbr_period; /* Constant bit rate period */ + u_int32_t tqi_cbr_overflow_limit; + u_int32_t tqi_burst_time; + u_int32_t tqi_ready_time; /* Not used */ + u_int32_t tqi_comp_buffer;/* Compression Buffer's phys addr */ +} AR5K_TXQ_INFO; + +/* + * Transmit packet types. + * These are not fully used inside OpenHAL yet + */ +typedef enum { + AR5K_PKT_TYPE_NORMAL = 0, + AR5K_PKT_TYPE_ATIM = 1, + AR5K_PKT_TYPE_PSPOLL = 2, + AR5K_PKT_TYPE_BEACON = 3, + AR5K_PKT_TYPE_PROBE_RESP = 4, + AR5K_PKT_TYPE_PIFS = 5, +} AR5K_PKT_TYPE; + +/* + * TX power and TPC settings + */ +#define AR5K_TXPOWER_OFDM(_r, _v) ( \ + ((0 & 1) << ((_v) + 6)) | \ + (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ +) + +#define AR5K_TXPOWER_CCK(_r, _v) ( \ + (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ +) + +/* + * Used to compute TX times + */ +#define AR5K_CCK_SIFS_TIME 10 +#define AR5K_CCK_PREAMBLE_BITS 144 +#define AR5K_CCK_PLCP_BITS 48 + +#define AR5K_OFDM_SIFS_TIME 16 +#define AR5K_OFDM_PREAMBLE_TIME 20 +#define AR5K_OFDM_PLCP_BITS 22 +#define AR5K_OFDM_SYMBOL_TIME 4 + +#define AR5K_TURBO_SIFS_TIME 8 +#define AR5K_TURBO_PREAMBLE_TIME 14 +#define AR5K_TURBO_PLCP_BITS 22 +#define AR5K_TURBO_SYMBOL_TIME 4 + +#define AR5K_XR_SIFS_TIME 16 +#define AR5K_XR_PLCP_BITS 22 +#define AR5K_XR_SYMBOL_TIME 4 + +/* CCK */ +#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) + +#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ + ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ + (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) + +#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ + AR5K_CCK_PHY_TIME(_sp) + \ + ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ + AR5K_CCK_SIFS_TIME + +/* OFDM */ +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_OFDM_SYMBOL_TIME) / 1000) + +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ + AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ + (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) + +/* TURBO */ +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ + AR5K_TURBO_SYMBOL_TIME) / 1000) + +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ + AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ + AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ + (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) + +/* eXtendent Range (?)*/ +#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) + +#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_XR_SYMBOL_TIME) / 1000) + +#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ + AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ + (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) + + + + +/****************\ + RX DEFINITIONS +\****************/ + +/* + * Rx Descriptor + */ +struct ath_rx_status { + u_int16_t rs_datalen; + u_int16_t rs_tstamp; + u_int8_t rs_status; + u_int8_t rs_phyerr; + int8_t rs_rssi; + u_int8_t rs_keyix; + u_int8_t rs_rate; + u_int8_t rs_antenna; + u_int8_t rs_more; +}; + +#define AR5K_RXERR_CRC 0x01 +#define AR5K_RXERR_PHY 0x02 +#define AR5K_RXERR_FIFO 0x04 +#define AR5K_RXERR_DECRYPT 0x08 +#define AR5K_RXERR_MIC 0x10 +#define AR5K_RXKEYIX_INVALID ((u_int8_t) - 1) +#define AR5K_TXKEYIX_INVALID ((u_int32_t) - 1) + +/* + * RX filters + * Most of them are not yet used inside OpenHAL + */ +#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ +#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ +#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ +#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ +#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ +#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ +#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame */ +#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests */ +#define AR5K_RX_FILTER_PHYERR 0x00000100 /* Don't filter phy errors */ +#define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ + +typedef struct { + u_int32_t ackrcv_bad; + u_int32_t rts_bad; + u_int32_t rts_good; + u_int32_t fcs_bad; + u_int32_t beacons; +} AR5K_MIB_STATS; + + + + +/**************************\ + BEACON TIMERS DEFINITIONS +\**************************/ + +#define AR5K_BEACON_PERIOD 0x0000ffff +#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ +#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ + +/* + * Per-station beacon timer state. + */ +typedef struct { + u_int32_t bs_next_beacon; + u_int32_t bs_next_dtim; + u_int32_t bs_interval; /*in TU's -see net80211/ieee80211_var.h- + can also include the above flags*/ + u_int8_t bs_dtim_period; + u_int8_t bs_cfp_period; + u_int16_t bs_cfp_max_duration; /*if non-zero hw is setup to coexist with + a Point Coordination Function capable AP*/ + u_int16_t bs_cfp_du_remain; + u_int16_t bs_tim_offset; + u_int16_t bs_sleep_duration; + u_int16_t bs_bmiss_threshold; + u_int32_t bs_cfp_next; +} AR5K_BEACON_STATE; + + + + +/********************\ + COMMON DEFINITIONS +\********************/ + +/* + * Atheros descriptor + */ +struct ath_desc { + u_int32_t ds_link; + u_int32_t ds_data; + u_int32_t ds_ctl0; + u_int32_t ds_ctl1; + u_int32_t ds_hw[4]; + + union { + struct ath_rx_status rx; + struct ath_tx_status tx; + } ds_us; + +#define ds_rxstat ds_us.rx +#define ds_txstat ds_us.tx + +} __packed; + +#define AR5K_RXDESC_INTREQ 0x0020 + +#define AR5K_TXDESC_CLRDMASK 0x0001 +#define AR5K_TXDESC_NOACK 0x0002 +#define AR5K_TXDESC_RTSENA 0x0004 +#define AR5K_TXDESC_CTSENA 0x0008 +#define AR5K_TXDESC_INTREQ 0x0010 +#define AR5K_TXDESC_VEOL 0x0020 + +/* + * 802.11 operating modes... + */ +#define AR5K_MODE_11A 0x01 +#define AR5K_MODE_11B 0x02 +#define AR5K_MODE_11G 0x04 +#define AR5K_MODE_TURBO 0x08 +#define AR5K_MODE_108G 0x16 +#define AR5K_MODE_XR 0x32 +#define AR5K_MODE_ALL (AR5K_MODE_11A| \ + AR5K_MODE_11B| \ + AR5K_MODE_11G| \ + AR5K_MODE_TURBO|\ + AR5K_MODE_108G| \ + AR5K_MODE_XR) + +/* + * Channel definitions + */ +typedef struct { + u_int16_t freq; /* setting in Mhz */ + u_int16_t channel_flags; + u_int8_t private_flags; /* not used in OpenHAL yet*/ +} AR5K_CHANNEL; + +#define AR5K_SLOT_TIME_9 396 +#define AR5K_SLOT_TIME_20 880 +#define AR5K_SLOT_TIME_MAX 0xffff + +/* channel_flags */ +#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ +#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation)*/ +#define CHANNEL_XR 0x0800 /* XR channel */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) +//#ifdef notdef +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN) +//#else +//#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +//#endif +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_108G CHANNEL_TG +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) + +#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ + CHANNEL_5GHZ | CHANNEL_TURBO) + +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) +#define CHANNEL_MODES CHANNEL_ALL + +/* + * Used internaly in OpenHAL (ar5211.c/ar5212.c + * for reset_tx_queue). Also see struct AR5K_CHANNEL. + */ +#define IS_CHAN_XR(_c) \ + ((_c.channel_flags & CHANNEL_XR) != 0) + +#define IS_CHAN_B(_c) \ + ((_c.channel_flags & CHANNEL_B) != 0) + +typedef enum { + AR5K_CHIP_5GHZ = CHANNEL_5GHZ, + AR5K_CHIP_2GHZ = CHANNEL_2GHZ, +} AR5K_CHIP; + +/* + * The following structure will be used to map 2GHz channels to + * 5GHz Atheros channels. + */ +struct ar5k_athchan_2ghz { + u_int32_t a2_flags; + u_int16_t a2_athchan; +}; + +/* + * Rate definitions + */ + +#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ + +typedef struct { + u_int8_t valid; /* Valid for rate control */ + u_int32_t modulation; + u_int16_t rate_kbps; + u_int8_t rate_code; /* Rate mapping for h/w descriptors */ + u_int8_t dot11_rate; + u_int8_t control_rate; + u_int16_t lp_ack_duration;/* long preamble ACK duration */ + u_int16_t sp_ack_duration;/* short preamble ACK duration*/ +} AR5K_RATE; + +typedef struct { + u_int16_t rate_count; + u_int8_t rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ + AR5K_RATE rates[AR5K_MAX_RATES]; +} AR5K_RATE_TABLE; + +/* + * Rate tables... + */ +#define AR5K_RATES_11A { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_11B { 4, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ +} + +#define AR5K_RATES_11G { 12, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ + { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ + { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +#define AR5K_RATES_TURBO { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ + { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ + { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ + { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ + { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ + { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ + { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ + { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_XR { 12, { \ + 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_XR, 500, 7, 129, 0 }, \ + { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ + { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ + { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ + { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +/* + * Crypto definitions + */ + +/* key types */ +typedef enum { + AR5K_CIPHER_WEP = 0, + AR5K_CIPHER_AES_OCB = 1, + AR5K_CIPHER_AES_CCM = 2, + AR5K_CIPHER_CKIP = 3, + AR5K_CIPHER_TKIP = 4, + AR5K_CIPHER_CLR = 5, /* no encryption */ + AR5K_CIPHER_MIC = 127 /* used for Message + Integrity Code */ +} AR5K_CIPHER; + +#define AR5K_KEYVAL_LENGTH_40 5 +#define AR5K_KEYVAL_LENGTH_104 13 +#define AR5K_KEYVAL_LENGTH_128 16 +#define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128 + +typedef struct { + int wk_len; /* key's length */ + u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX]; + u_int8_t wk_type; /* see above */ + u_int8_t wk_mic[8]; /* TKIP MIC key */ +} AR5K_KEYVAL; + + + +/***********************\ + HW RELATED DEFINITIONS +\***********************/ + +/* + * Misc definitions + */ +#define AR5K_RSSI_EP_MULTIPLIER (1<<7) + +#define AR5K_ASSERT_ENTRY(_e, _s) do { \ + if (_e >= _s) \ + return (FALSE); \ +} while (0) + + +typedef struct { + u_int32_t ns_avgbrssi; /* average beacon rssi */ + u_int32_t ns_avgrssi; /* average data rssi */ + u_int32_t ns_avgtxrssi; /* average tx rssi */ +} AR5K_NODE_STATS; + +typedef enum { + AR5K_ANT_VARIABLE = 0, /* variable by programming */ + AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ + AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ + AR5K_ANT_MAX = 3, +} AR5K_ANT_SETTING; + +/* + * HAL interrupt abstraction + */ + +/* + * These are maped to take advantage of some common bits + * between the MAC chips, to be able to set intr properties + * easier. Some of them are not used yet inside OpenHAL. + */ +typedef enum { + AR5K_INT_RX = 0x00000001, + AR5K_INT_RXDESC = 0x00000002, + AR5K_INT_RXNOFRM = 0x00000008, + AR5K_INT_RXEOL = 0x00000010, + AR5K_INT_RXORN = 0x00000020, + AR5K_INT_TX = 0x00000040, + AR5K_INT_TXDESC = 0x00000080, + AR5K_INT_TXURN = 0x00000800, + AR5K_INT_MIB = 0x00001000, + AR5K_INT_RXPHY = 0x00004000, + AR5K_INT_RXKCM = 0x00008000, + AR5K_INT_SWBA = 0x00010000, + AR5K_INT_BMISS = 0x00040000, + AR5K_INT_BNR = 0x00100000, + AR5K_INT_GPIO = 0x01000000, + AR5K_INT_FATAL = 0x40000000, + AR5K_INT_GLOBAL = 0x80000000, + + /*A sum of all the common bits*/ + AR5K_INT_COMMON = AR5K_INT_RXNOFRM + | AR5K_INT_RXDESC + | AR5K_INT_RXEOL + | AR5K_INT_RXORN + | AR5K_INT_TXURN + | AR5K_INT_TXDESC + | AR5K_INT_MIB + | AR5K_INT_RXPHY + | AR5K_INT_RXKCM + | AR5K_INT_SWBA + | AR5K_INT_BMISS + | AR5K_INT_GPIO, + AR5K_INT_NOCARD = 0xffffffff /*Declare that the card + has been removed*/ +} AR5K_INT; + +/* + * Power management + */ +typedef enum { + AR5K_PM_UNDEFINED = 0, + AR5K_PM_AUTO, + AR5K_PM_AWAKE, + AR5K_PM_FULL_SLEEP, + AR5K_PM_NETWORK_SLEEP, +} AR5K_POWER_MODE; + + +/* + * LED states + */ +typedef int AR5K_LED_STATE; + +/* + * These match net80211 definitions (not used in + * d80211). + */ +#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ +#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ +#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ +#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ +#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ + +/* GPIO-controlled software LED */ +#define AR5K_SOFTLED_PIN 0 +#define AR5K_SOFTLED_ON 0 +#define AR5K_SOFTLED_OFF 1 + +/* + * Gain settings + */ +typedef enum { + AR5K_RFGAIN_INACTIVE = 0, + AR5K_RFGAIN_READ_REQUESTED, + AR5K_RFGAIN_NEED_CHANGE, +} AR5K_RFGAIN; + +#define AR5K_GAIN_CRN_FIX_BITS_5111 4 +#define AR5K_GAIN_CRN_FIX_BITS_5112 7 +#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 +#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 +#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 +#define AR5K_GAIN_CCK_PROBE_CORR 5 +#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 +#define AR5K_GAIN_STEP_COUNT 10 +#define AR5K_GAIN_PARAM_TX_CLIP 0 +#define AR5K_GAIN_PARAM_PD_90 1 +#define AR5K_GAIN_PARAM_PD_84 2 +#define AR5K_GAIN_PARAM_GAIN_SEL 3 +#define AR5K_GAIN_PARAM_MIX_ORN 0 +#define AR5K_GAIN_PARAM_PD_138 1 +#define AR5K_GAIN_PARAM_PD_137 2 +#define AR5K_GAIN_PARAM_PD_136 3 +#define AR5K_GAIN_PARAM_PD_132 4 +#define AR5K_GAIN_PARAM_PD_131 5 +#define AR5K_GAIN_PARAM_PD_130 6 +#define AR5K_GAIN_CHECK_ADJUST(_g) \ + ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) + +struct ar5k_gain_opt_step { + int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; + int32_t gos_gain; +}; + +struct ar5k_gain_opt { + u_int32_t go_default; + u_int32_t go_steps_count; + const struct ar5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; +}; + +struct ar5k_gain { + u_int32_t g_step_idx; + u_int32_t g_current; + u_int32_t g_target; + u_int32_t g_low; + u_int32_t g_high; + u_int32_t g_f_corr; + u_int32_t g_active; + const struct ar5k_gain_opt_step *g_step; +}; + +/* + * Gain optimization tables... + */ +#define AR5K_AR5111_GAIN_OPT { \ + 4, \ + 9, \ + { \ + { { 4, 1, 1, 1 }, 6 }, \ + { { 4, 0, 1, 1 }, 4 }, \ + { { 3, 1, 1, 1 }, 3 }, \ + { { 4, 0, 0, 1 }, 1 }, \ + { { 4, 1, 1, 0 }, 0 }, \ + { { 4, 0, 1, 0 }, -2 }, \ + { { 3, 1, 1, 0 }, -3 }, \ + { { 4, 0, 0, 0 }, -4 }, \ + { { 2, 1, 1, 0 }, -6 } \ + } \ +} + +#define AR5K_AR5112_GAIN_OPT { \ + 1, \ + 8, \ + { \ + { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \ + { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \ + { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \ + { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \ + { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \ + { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \ + { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \ + { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \ + } \ +} + +/* + * Common ar5xxx EEPROM data registers + */ +#define AR5K_EEPROM_MAGIC 0x003d +#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 +#define AR5K_EEPROM_PROTECT 0x003f +#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 +#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 +#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 +#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 +#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 +#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 +#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 +#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 +#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 +#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 +#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 +#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 +#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 +#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 +#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 +#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 +#define AR5K_EEPROM_REG_DOMAIN 0x00bf +#define AR5K_EEPROM_INFO_BASE 0x00c0 +#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) +#define AR5K_EEPROM_INFO_CKSUM 0xffff +#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) + +#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) +#define AR5K_EEPROM_VERSION_3_0 0x3000 +#define AR5K_EEPROM_VERSION_3_1 0x3001 +#define AR5K_EEPROM_VERSION_3_2 0x3002 +#define AR5K_EEPROM_VERSION_3_3 0x3003 +#define AR5K_EEPROM_VERSION_3_4 0x3004 +#define AR5K_EEPROM_VERSION_4_0 0x4000 +#define AR5K_EEPROM_VERSION_4_1 0x4001 +#define AR5K_EEPROM_VERSION_4_2 0x4002 +#define AR5K_EEPROM_VERSION_4_3 0x4003 +#define AR5K_EEPROM_VERSION_4_6 0x4006 +#define AR5K_EEPROM_VERSION_4_7 0x3007 + +#define AR5K_EEPROM_MODE_11A 0 +#define AR5K_EEPROM_MODE_11B 1 +#define AR5K_EEPROM_MODE_11G 2 + +#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) +#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) +#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) +#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) +#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) +#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) +#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) +#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) +#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) + +#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c +#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 +#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 +#define AR5K_EEPROM_RFKILL_POLARITY_S 1 + +/* Newer EEPROMs are using a different offset */ +#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ + (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) + +#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) +#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) +#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) + +#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) +#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) +#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) +#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) + +/* Since 3.1 */ +#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec +#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed + +/* Misc values available since EEPROM 4.0 */ +#define AR5K_EEPROM_MISC0 0x00c4 +#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) +#define AR5K_EEPROM_MISC1 0x00c5 +#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) + +/* Some EEPROM defines */ +#define AR5K_EEPROM_EEP_SCALE 100 +#define AR5K_EEPROM_EEP_DELTA 10 +#define AR5K_EEPROM_N_MODES 3 +#define AR5K_EEPROM_N_5GHZ_CHAN 10 +#define AR5K_EEPROM_N_2GHZ_CHAN 3 +#define AR5K_EEPROM_MAX_CHAN 10 +#define AR5K_EEPROM_N_PCDAC 11 +#define AR5K_EEPROM_N_TEST_FREQ 8 +#define AR5K_EEPROM_N_EDGES 8 +#define AR5K_EEPROM_N_INTERCEPTS 11 +#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) +#define AR5K_EEPROM_PCDAC_M 0x3f +#define AR5K_EEPROM_PCDAC_START 1 +#define AR5K_EEPROM_PCDAC_STOP 63 +#define AR5K_EEPROM_PCDAC_STEP 1 +#define AR5K_EEPROM_NON_EDGE_M 0x40 +#define AR5K_EEPROM_CHANNEL_POWER 8 +#define AR5K_EEPROM_N_OBDB 4 +#define AR5K_EEPROM_OBDB_DIS 0xffff +#define AR5K_EEPROM_CHANNEL_DIS 0xff +#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) +#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) +#define AR5K_EEPROM_MAX_CTLS 32 +#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 +#define AR5K_EEPROM_N_XPD0_POINTS 4 +#define AR5K_EEPROM_N_XPD3_POINTS 3 +#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 +#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 +#define AR5K_EEPROM_POWER_M 0x3f +#define AR5K_EEPROM_POWER_MIN 0 +#define AR5K_EEPROM_POWER_MAX 3150 +#define AR5K_EEPROM_POWER_STEP 50 +#define AR5K_EEPROM_POWER_TABLE_SIZE 64 +#define AR5K_EEPROM_N_POWER_LOC_11B 4 +#define AR5K_EEPROM_N_POWER_LOC_11G 6 +#define AR5K_EEPROM_I_GAIN 10 +#define AR5K_EEPROM_CCK_OFDM_DELTA 15 +#define AR5K_EEPROM_N_IQ_CAL 2 + +struct ar5k_eeprom_info { + u_int16_t ee_magic; + u_int16_t ee_protect; + u_int16_t ee_regdomain; + u_int16_t ee_version; + u_int16_t ee_header; + u_int16_t ee_ant_gain; + u_int16_t ee_misc0; + u_int16_t ee_misc1; + u_int16_t ee_cck_ofdm_gain_delta; + u_int16_t ee_cck_ofdm_power_delta; + u_int16_t ee_scaled_cck_delta; + u_int16_t ee_tx_clip; + u_int16_t ee_pwd_84; + u_int16_t ee_pwd_90; + u_int16_t ee_gain_select; + + u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES]; + u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES]; + u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES]; + u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES]; + u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES]; + u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES]; + u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; + u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; + u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; + u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; + u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; + u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES]; + u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES]; + u_int16_t ee_xpd[AR5K_EEPROM_N_MODES]; + u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES]; + u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES]; + u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; + u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; + u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; + u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; + + u_int16_t ee_ctls; + u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS]; + + int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; + int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; + int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; +}; + +/* + * AR5k register access + */ + +/*O.S. dependent functions are located in ah_osdep.h*/ +#define AR5K_REG_SM(_val, _flags) \ + (((_val) << _flags##_S) & (_flags)) + +#define AR5K_REG_MS(_val, _flags) \ + (((_val) & (_flags)) >> _flags##_S) + +#define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ + AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ + (((_val) << _flags##_S) & (_flags))) + +#define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \ + AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags)) + +#define AR5K_REG_ENABLE_BITS(_reg, _flags) \ + AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) + +#define AR5K_REG_DISABLE_BITS(_reg, _flags) \ + AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) + +#define AR5K_PHY_WRITE(_reg, _val) \ + AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val) + +#define AR5K_PHY_READ(_reg) \ + AR5K_REG_READ(hal->ah_phy + ((_reg) << 2)) + +#define AR5K_REG_WAIT(_i) \ + if (_i % 64) \ + AR5K_DELAY(1); + +#define AR5K_EEPROM_READ(_o, _v) { \ + if ((ret = hal->ah_eeprom_read(hal, (_o), \ + &(_v))) != 0) \ + return (ret); \ +} + +#define AR5K_EEPROM_READ_HDR(_o, _v) \ + AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ + +/* Read status of selected queue */ +#define AR5K_REG_READ_Q(_reg, _queue) \ + (AR5K_REG_READ(_reg) & (1 << _queue)) \ + +#define AR5K_REG_WRITE_Q(_reg, _queue) \ + AR5K_REG_WRITE(_reg, (1 << _queue)) + +#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ + _reg |= 1 << _queue; \ +} while (0) + +#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ + _reg &= ~(1 << _queue); \ +} while (0) + +/* + * Unaligned little endian access + */ +#define AR5K_LE_READ_2(_p) \ + (((const u_int8_t *)(_p))[0] | (((const u_int8_t *)(_p))[1] << 8)) +#define AR5K_LE_READ_4(_p) \ + (((const u_int8_t *)(_p))[0] | \ + (((const u_int8_t *)(_p))[1] << 8) | \ + (((const u_int8_t *)(_p))[2] << 16) | \ + (((const u_int8_t *)(_p))[3] << 24)) +#define AR5K_LE_WRITE_2(_p, _val) \ + ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ + (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff))) +#define AR5K_LE_WRITE_4(_p, _val) \ + ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ + (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \ + (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \ + (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff))) + +/* + * Initial register values + */ + +/* + * Common initial register values + */ +#define AR5K_INIT_MODE CHANNEL_B + +#define AR5K_INIT_TX_LATENCY 502 +#define AR5K_INIT_USEC 39 +#define AR5K_INIT_USEC_TURBO 79 +#define AR5K_INIT_USEC_32 31 +#define AR5K_INIT_CARR_SENSE_EN 1 +#define AR5K_INIT_PROG_IFS 920 +#define AR5K_INIT_PROG_IFS_TURBO 960 +#define AR5K_INIT_EIFS 3440 +#define AR5K_INIT_EIFS_TURBO 6880 +#define AR5K_INIT_SLOT_TIME 396 +#define AR5K_INIT_SLOT_TIME_TURBO 480 +#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 +#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 +#define AR5K_INIT_SIFS 560 +#define AR5K_INIT_SIFS_TURBO 480 +#define AR5K_INIT_SH_RETRY 10 +#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY +#define AR5K_INIT_SSH_RETRY 32 +#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY +#define AR5K_INIT_TX_RETRY 10 +#define AR5K_INIT_TOPS 8 +#define AR5K_INIT_RXNOFRM 8 +#define AR5K_INIT_RPGTO 0 +#define AR5K_INIT_TXNOFRM 0 +#define AR5K_INIT_BEACON_PERIOD 65535 +#define AR5K_INIT_TIM_OFFSET 0 +#define AR5K_INIT_BEACON_EN 0 +#define AR5K_INIT_RESET_TSF 0 + +#define AR5K_INIT_TRANSMIT_LATENCY ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC) \ +) +#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC_TURBO) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ + (AR5K_INIT_PROG_IFS) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ + (AR5K_INIT_PROG_IFS_TURBO) \ +) +#define AR5K_INIT_BEACON_CONTROL ( \ + (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ + (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ +) + +/* + * Non - common initial register values + */ +struct ar5k_ini { + u_int16_t ini_register; + u_int32_t ini_value; + + enum { + AR5K_INI_WRITE = 0, + AR5K_INI_READ = 1, + } ini_mode; +}; + +#define AR5K_INI_VAL_11A 0 +#define AR5K_INI_VAL_11A_TURBO 1 +#define AR5K_INI_VAL_11B 2 +#define AR5K_INI_VAL_11G 3 +#define AR5K_INI_VAL_11G_TURBO 4 +#define AR5K_INI_VAL_XR 0 +#define AR5K_INI_VAL_MAX 5 + +#define AR5K_INI_PHY_5111 0 +#define AR5K_INI_PHY_5112 1 +#define AR5K_INI_PHY_511X 1 + +#define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS +#define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS + +struct ar5k_ini_rf { + u_int8_t rf_bank; + u_int16_t rf_register; + u_int32_t rf_value[5]; +}; + +#define AR5K_AR5111_INI_RF { \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ + { 0, 0x989c, \ + { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ + { 0, 0x98d4, \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d4, \ + { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ + { 3, 0x98d8, \ + { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ + { 6, 0x989c, \ + { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ + { 6, 0x989c, \ + { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ + { 6, 0x989c, \ + { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ + { 6, 0x989c, \ + { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ + { 6, 0x989c, \ + { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ + { 6, 0x98d4, \ + { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ + { 7, 0x989c, \ + { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ + { 7, 0x989c, \ + { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ + { 7, 0x989c, \ + { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ + { 7, 0x989c, \ + { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ + { 7, 0x989c, \ + { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ + { 7, 0x989c, \ + { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ + { 7, 0x989c, \ + { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ + { 7, 0x98cc, \ + { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ +} + +#define AR5K_AR5112_INI_RF { \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ + { 6, 0x989c, \ + { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ + { 6, 0x989c, \ + { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ + { 6, 0x989c, \ + { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ + { 6, 0x989c, \ + { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ + { 6, 0x989c, \ + { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ + { 6, 0x989c, \ + { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ + { 6, 0x989c, \ + { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ + { 6, 0x989c, \ + { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ + { 6, 0x989c, \ + { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ + { 6, 0x989c, \ + { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ + { 6, 0x989c, \ + { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ + { 6, 0x989c, \ + { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ + { 6, 0x989c, \ + { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ + { 6, 0x989c, \ + { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ + { 6, 0x98d0, \ + { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ + { 7, 0x989c, \ + { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ + } + +#define AR5K_AR5112A_INI_RF { \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ + { 6, 0x989c, \ + { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ + { 6, 0x989c, \ + { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ + { 6, 0x989c, \ + { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ + { 6, 0x989c, \ + { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ + { 6, 0x989c, \ + { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ + { 6, 0x989c, \ + { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ + { 6, 0x989c, \ + { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ + { 6, 0x989c, \ + { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ + { 6, 0x989c, \ + { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ + { 6, 0x989c, \ + { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ + { 6, 0x989c, \ + { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ + { 6, 0x989c, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ + { 6, 0x989c, \ + { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ + { 6, 0x989c, \ + { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ + { 6, 0x989c, \ + { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ + { 6, 0x989c, \ + { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ + { 6, 0x98d8, \ + { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ + { 7, 0x989c, \ + { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ +} + +struct ar5k_ini_rfgain { + u_int16_t rfg_register; + u_int32_t rfg_value[2][2]; + +#define AR5K_INI_RFGAIN_5GHZ 0 +#define AR5K_INI_RFGAIN_2GHZ 1 +}; + +#define AR5K_INI_RFGAIN { \ + { 0x9a00, { \ + { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ + { 0x9a04, { \ + { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ + { 0x9a08, { \ + { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ + { 0x9a0c, { \ + { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ + { 0x9a10, { \ + { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ + { 0x9a14, { \ + { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ + { 0x9a18, { \ + { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ + { 0x9a1c, { \ + { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ + { 0x9a20, { \ + { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ + { 0x9a24, { \ + { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ + { 0x9a28, { \ + { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ + { 0x9a2c, { \ + { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ + { 0x9a30, { \ + { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ + { 0x9a34, { \ + { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ + { 0x9a38, { \ + { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ + { 0x9a3c, { \ + { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ + { 0x9a40, { \ + { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ + { 0x9a44, { \ + { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ + { 0x9a48, { \ + { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ + { 0x9a4c, { \ + { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ + { 0x9a50, { \ + { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ + { 0x9a54, { \ + { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ + { 0x9a58, { \ + { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ + { 0x9a5c, { \ + { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ + { 0x9a60, { \ + { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ + { 0x9a64, { \ + { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ + { 0x9a68, { \ + { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ + { 0x9a6c, { \ + { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ + { 0x9a70, { \ + { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ + { 0x9a74, { \ + { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ + { 0x9a78, { \ + { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ + { 0x9a7c, { \ + { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ + { 0x9a80, { \ + { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ + { 0x9a84, { \ + { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ + { 0x9a88, { \ + { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ + { 0x9a8c, { \ + { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ + { 0x9a90, { \ + { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ + { 0x9a94, { \ + { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ + { 0x9a98, { \ + { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ + { 0x9a9c, { \ + { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ + { 0x9aa0, { \ + { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ + { 0x9aa4, { \ + { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ + { 0x9aa8, { \ + { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ + { 0x9aac, { \ + { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ + { 0x9ab0, { \ + { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ + { 0x9ab4, { \ + { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ + { 0x9ab8, { \ + { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ + { 0x9abc, { \ + { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ + { 0x9ac0, { \ + { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ + { 0x9ac4, { \ + { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ + { 0x9ac8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ + { 0x9acc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ + { 0x9ad0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ + { 0x9ad4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ + { 0x9ad8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9adc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9aec, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9afc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ +} + +/* + * Chipset capabilities -see ath_hal_getcapability- + * get_capability function is not yet fully implemented + * in OpenHAL so most of these don't work yet... + */ +typedef enum { + AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ + AR5K_CAP_CIPHER = 1, /* Can handle encryption */ + AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ + AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ + AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ + AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ + AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ + AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ + AR5K_CAP_COMPRESSION = 8, /* Supports compression */ + AR5K_CAP_BURST = 9, /* Supports packet bursting */ + AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ + AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ + AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ + AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ + AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ + AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ + AR5K_CAP_XR = 16, /* Supports XR mode */ + AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ + AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ + AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ + AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ +} AR5K_CAPABILITY_TYPE; + +typedef struct { + /* + * Supported PHY modes + * (ie. CHANNEL_A, CHANNEL_B, ...) + */ + u_int16_t cap_mode; + + /* + * Frequency range (without regulation restrictions) + */ + struct { + u_int16_t range_2ghz_min; + u_int16_t range_2ghz_max; + u_int16_t range_5ghz_min; + u_int16_t range_5ghz_max; + } cap_range; + + /* + * Active regulation domain settings + */ + struct { + ieee80211_regdomain_t reg_current; + ieee80211_regdomain_t reg_hw; + } cap_regdomain; + + /* + * Values stored in the EEPROM (some of them...) + */ + struct ar5k_eeprom_info cap_eeprom; + + /* + * Queue information + */ + struct { + u_int8_t q_tx_num; + } cap_queues; +} ar5k_capabilities_t; + + + + +/***************************************\ + HARDWARE ABSTRACTION LAYER STRUCTURE +\***************************************/ + +/* + * Regulation stuff + */ +typedef enum ieee80211_countrycode AR5K_CTRY_CODE; + +/* Default regulation domain if stored value EEPROM value is invalid */ +#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ +#define AR5K_TUNE_CTRY CTRY_DEFAULT + +/* + * Misc defines + */ +#define AR5K_ABI_VERSION 0x04090901 /* YYMMDDnn */ + +#define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0])) + +typedef struct ath_hal * (ar5k_attach_t) + (u_int16_t, AR5K_SOFTC, AR5K_BUS_TAG, AR5K_BUS_HANDLE, AR5K_STATUS *); + +typedef AR5K_BOOL (ar5k_rfgain_t) + (struct ath_hal *, AR5K_CHANNEL *, u_int); + +/* + * HAL Functions that have different implementations for each chipset... + */ +#define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ar5k_##_n##_##_f +#define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ + _t const AR5K_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, u_int mode); \ + _t void (_a _n##_detach)(struct ath_hal *); \ + /* Reset functions */ \ + _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, AR5K_OPMODE, AR5K_CHANNEL *, \ + AR5K_BOOL change_channel, AR5K_STATUS *status); \ + _t void (_a _n##_set_opmode)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ + /* Transmit functions */ \ + _t AR5K_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, AR5K_BOOL level); \ + _t int (_a _n##_setup_tx_queue)(struct ath_hal *, AR5K_TX_QUEUE, AR5K_TXQ_INFO *); \ + _t AR5K_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ + const AR5K_TXQ_INFO *); \ + _t AR5K_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ + _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u_int32_t phys_addr); \ + _t AR5K_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, \ + u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index,\ + u_int antenna_mode, u_int flags, u_int rtscts_rate, \ + u_int rtscts_duration); \ + _t AR5K_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ + u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ + _t AR5K_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ + AR5K_BOOL firstSeg, AR5K_BOOL lastSeg, const struct ath_desc *);\ + _t AR5K_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ + _t AR5K_BOOL (_a _n##_has_veol)(struct ath_hal *); \ + /* Receive Functions */ \ + _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \ + _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \ + _t void (_a _n##_start_rx)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \ + _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \ + _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \ + _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u_int32_t filter0, \ + u_int32_t filter1); \ + _t AR5K_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, u_int32_t index); \ + _t AR5K_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*,u_int32_t index); \ + _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \ + _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \ + _t AR5K_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int32_t size, u_int flags); \ + _t AR5K_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int32_t phyAddr, struct ath_desc *next); \ + _t void (_a _n##_set_rx_signal)(struct ath_hal *, const AR5K_NODE_STATS *); \ + /* Misc Functions */ \ + _t void (_a _n##_dump_state)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ + u_int32_t argsize, void **result, u_int32_t *resultsize); \ + _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \ + _t AR5K_BOOL (_a _n##_set_lladdr)(struct ath_hal *, const u_int8_t*); \ + _t AR5K_BOOL (_a _n##_set_regdomain)(struct ath_hal*, u_int16_t, AR5K_STATUS *); \ + _t void (_a _n##_set_ledstate)(struct ath_hal*, AR5K_LED_STATE); \ + _t void (_a _n##_set_associd)(struct ath_hal*, const u_int8_t *bssid, \ + u_int16_t assocId); \ + _t AR5K_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, u_int32_t gpio); \ + _t AR5K_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, u_int32_t gpio); \ + _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \ + _t AR5K_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, u_int32_t val); \ + _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \ + _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \ + _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \ + _t void (_a _n##_reset_tsf)(struct ath_hal*); \ + _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \ + _t void (_a _n##_update_mib_counters)(struct ath_hal*, AR5K_MIB_STATS*); \ + _t AR5K_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \ + _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \ + _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \ + /* Key Cache Functions */ \ + _t AR5K_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, AR5K_CIPHER); \ + _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_reset_key)(struct ath_hal*, u_int16_t); \ + _t AR5K_BOOL (_a _n##_is_key_valid)(struct ath_hal *, u_int16_t); \ + _t AR5K_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, const AR5K_KEYVAL *, \ + const u_int8_t *, int); \ + _t AR5K_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, u_int16_t, const u_int8_t *); \ + /* Power Management Functions */ \ + _t AR5K_BOOL (_a _n##_set_power)(struct ath_hal*, AR5K_POWER_MODE mode, \ + AR5K_BOOL set_chip, u_int16_t sleep_duration); \ + _t AR5K_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, u_int16_t); \ + _t AR5K_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \ + /* Beacon Management Functions */ \ + _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, u_int32_t intval); \ + _t void (_a _n##_set_beacon_timers)(struct ath_hal *, const AR5K_BEACON_STATE *); \ + _t void (_a _n##_reset_beacon)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, AR5K_BUS_ADDR); \ + /* Interrupt functions */ \ + _t AR5K_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_get_isr)(struct ath_hal *, u_int32_t *); \ + _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \ + _t AR5K_INT (_a _n##_set_intr)(struct ath_hal *, AR5K_INT); \ + /* Chipset functions (ar5k-specific, non-HAL) */ \ + _t AR5K_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \ + _t void (_a _n##_radar_alert)(struct ath_hal *, AR5K_BOOL enable); \ + _t AR5K_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \ + _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, u_int16_t *data); \ + _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, u_int16_t data); \ + /* Functions not found in OpenBSD */ \ + _t AR5K_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, AR5K_TXQ_INFO *); \ + _t AR5K_STATUS (_a _n##_get_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, \ + u_int32_t, u_int32_t *); \ + _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ + _t AR5K_BOOL (_a _n##_phy_disable)(struct ath_hal *); \ + _t void (_a _n##_set_pcu_config)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ + _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \ + _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \ + /*Totaly unimplemented*/ \ + _t AR5K_BOOL (_a _n##_set_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, u_int32_t,\ + u_int32_t,AR5K_STATUS *) ; \ + _t void (_a _n##_proc_mib_event)(struct ath_hal *, const AR5K_NODE_STATS *) ; \ + _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *); + + +#define AR5K_MAX_GPIO 10 +#define AR5K_MAX_RF_BANKS 8 + +struct ath_hal { + u_int32_t ah_magic; + u_int16_t ah_device; + u_int16_t ah_sub_vendor; + + AR5K_SOFTC ah_sc; + bus_space_tag_t ah_st; + bus_space_handle_t ah_sh; + AR5K_CTRY_CODE ah_country_code; + + AR5K_INT ah_imr; + + AR5K_OPMODE ah_op_mode; + AR5K_POWER_MODE ah_power_mode; + AR5K_CHANNEL ah_current_channel; + AR5K_BOOL ah_turbo; + AR5K_BOOL ah_calibration; + AR5K_BOOL ah_running; + AR5K_BOOL ah_single_chip; + AR5K_RFGAIN ah_rf_gain; + + AR5K_RATE_TABLE ah_rt_11a; + AR5K_RATE_TABLE ah_rt_11b; + AR5K_RATE_TABLE ah_rt_11g; + AR5K_RATE_TABLE ah_rt_turbo; + AR5K_RATE_TABLE ah_rt_xr; + + u_int32_t ah_mac_srev; + u_int16_t ah_mac_version; + u_int16_t ah_mac_revision; + u_int16_t ah_phy_revision; + u_int16_t ah_radio_5ghz_revision; + u_int16_t ah_radio_2ghz_revision; + + enum ar5k_version ah_version; + enum ar5k_radio ah_radio; + u_int32_t ah_phy; + + AR5K_BOOL ah_5ghz; + AR5K_BOOL ah_2ghz; + +#define ah_regdomain ah_capabilities.cap_regdomain.reg_current +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_modes ah_capabilities.cap_mode +#define ah_ee_version ah_capabilities.cap_eeprom.ee_version + + u_int32_t ah_atim_window; + u_int32_t ah_aifs; + u_int32_t ah_cw_min; + u_int32_t ah_cw_max; + AR5K_BOOL ah_software_retry; + u_int32_t ah_limit_tx_retries; + + u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + AR5K_BOOL ah_ant_diversity; + + u_int8_t ah_sta_id[IEEE80211_ADDR_LEN]; + u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; + + u_int32_t ah_gpio[AR5K_MAX_GPIO]; + int ah_gpio_npins; + + ar5k_capabilities_t ah_capabilities; + + AR5K_TXQ_INFO ah_txq[AR5K_NUM_TX_QUEUES]; + u_int32_t ah_txq_interrupts; + + u_int32_t *ah_rf_banks; + size_t ah_rf_banks_size; + struct ar5k_gain ah_gain; + u_int32_t ah_offset[AR5K_MAX_RF_BANKS]; + + struct { + u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; + u_int16_t txp_rates[AR5K_MAX_RATES]; + int16_t txp_min, txp_max; + AR5K_BOOL txp_tpc; + int16_t txp_ofdm; + } ah_txpower; + + struct { + AR5K_BOOL r_enabled; + int r_last_alert; + AR5K_CHANNEL r_last_channel; + } ah_radar; + + /* + * Function pointers + */ + AR5K_HAL_FUNCTIONS(, ah, *); + +}; + +/* + * Prototypes -functions common for all chipsets- + */ + + +const char *ath_hal_probe(u_int16_t, u_int16_t); +struct ath_hal *ath_hal_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG, + AR5K_BUS_HANDLE, AR5K_STATUS *); +u_int16_t ath_hal_computetxtime(struct ath_hal *, const AR5K_RATE_TABLE *, + u_int32_t, u_int16_t, AR5K_BOOL); +u_int ath_hal_mhz2ieee(u_int, u_int); +u_int ath_hal_ieee2mhz(u_int, u_int); +AR5K_BOOL ath_hal_init_channels(struct ath_hal *, AR5K_CHANNEL *, + u_int, u_int *, AR5K_CTRY_CODE, u_int16_t, + AR5K_BOOL, AR5K_BOOL); +const char *ar5k_printver(enum ar5k_srev_type, u_int32_t); +void ar5k_radar_alert(struct ath_hal *); +ieee80211_regdomain_t ar5k_regdomain_to_ieee(u_int16_t); +u_int16_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t); +u_int16_t ar5k_get_regdomain(struct ath_hal *); +u_int32_t ar5k_bitswap(u_int32_t, u_int); +u_int ar5k_clocktoh(u_int, AR5K_BOOL); +u_int ar5k_htoclock(u_int, AR5K_BOOL); +void ar5k_rt_copy(AR5K_RATE_TABLE *, const AR5K_RATE_TABLE *); +AR5K_BOOL ar5k_register_timeout(struct ath_hal *, u_int32_t, u_int32_t, + u_int32_t, AR5K_BOOL); +int ar5k_eeprom_init(struct ath_hal *); +int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); +AR5K_BOOL ar5k_eeprom_regulation_domain(struct ath_hal *, AR5K_BOOL, + ieee80211_regdomain_t *); +AR5K_BOOL ar5k_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ar5k_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +u_int32_t ar5k_rfregs_gainf_corr(struct ath_hal *); +AR5K_BOOL ar5k_rfregs_gain_readback(struct ath_hal *); +int32_t ar5k_rfregs_gain_adjust(struct ath_hal *); +AR5K_BOOL ar5k_rfgain(struct ath_hal *, u_int, u_int); +void ar5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); + +/*added*/ +extern u_int ath_hal_getwirelessmodes(struct ath_hal*, AR5K_CTRY_CODE); +void ath_hal_detach(struct ath_hal *ah); +struct ath_hal * _ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, AR5K_BUS_TAG t, + AR5K_BUS_HANDLE h, void* s); +#endif /* _AR5K_H */ Index: ar5210.c =================================================================== --- ar5210.c (revision 1948) +++ ar5210.c (revision 1972) @@ -1,7 +1,6 @@ -/* $OpenBSD: ar5210.c,v 1.33 2005/12/18 17:59:58 reyk Exp $ */ - /* - * Copyright (c) 2004, 2005 Reyk Floeter + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -14,6 +13,8 @@ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ */ /* @@ -25,12 +26,12 @@ #include "ar5210reg.h" #include "ar5210var.h" -HAL_BOOL ar5k_ar5210_nic_reset(struct ath_hal *, u_int32_t); -HAL_BOOL ar5k_ar5210_nic_wakeup(struct ath_hal *, HAL_BOOL, HAL_BOOL); -void ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, HAL_BOOL); +AR5K_BOOL ar5k_ar5210_nic_reset(struct ath_hal *, u_int32_t); +AR5K_BOOL ar5k_ar5210_nic_wakeup(struct ath_hal *, AR5K_BOOL, AR5K_BOOL); +void ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, AR5K_BOOL); void ar5k_ar5210_fill(struct ath_hal *); -HAL_BOOL ar5k_ar5210_do_calibrate(struct ath_hal *, HAL_CHANNEL *); -HAL_BOOL ar5k_ar5210_noise_floor(struct ath_hal *, HAL_CHANNEL *); +AR5K_BOOL ar5k_ar5210_do_calibrate(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ar5k_ar5210_noise_floor(struct ath_hal *, AR5K_CHANNEL *); /* * Initial register setting for the AR5210 @@ -191,8 +192,8 @@ } struct ath_hal * /*Ported & removed an arg from call to set_associd*/ -ar5k_ar5210_attach(u_int16_t device, HAL_SOFTC sc, HAL_BUS_TAG st, - HAL_BUS_HANDLE sh, HAL_STATUS *status) +ar5k_ar5210_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, + AR5K_BUS_HANDLE sh, AR5K_STATUS *status) { int i; struct ath_hal *hal = (struct ath_hal*) sc; @@ -202,7 +203,7 @@ ar5k_ar5210_fill(hal); /* Bring device out of sleep and reset it's units */ - if (ar5k_ar5210_nic_wakeup(hal, AH_FALSE, AH_TRUE) != AH_TRUE) + if (ar5k_ar5210_nic_wakeup(hal, FALSE, TRUE) != TRUE) return (NULL); /* Get MAC, PHY and RADIO revisions */ @@ -235,10 +236,10 @@ return (hal); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val) { - HAL_BOOL ret = AH_FALSE; + AR5K_BOOL ret = FALSE; u_int32_t mask = val ? val : ~0; /* @@ -257,7 +258,7 @@ AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC | AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA; - ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, AH_FALSE); + ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, FALSE); /* * Reset configuration register @@ -269,19 +270,19 @@ return (ret); } -HAL_BOOL -ar5k_ar5210_nic_wakeup(struct ath_hal *hal, HAL_BOOL turbo, HAL_BOOL initial) +AR5K_BOOL +ar5k_ar5210_nic_wakeup(struct ath_hal *hal, AR5K_BOOL turbo, AR5K_BOOL initial) { /* * Reset and wakeup the device */ - if (initial == AH_TRUE) { + if (initial == TRUE) { /* ...reset hardware */ if (ar5k_ar5210_nic_reset(hal, - AR5K_AR5210_RC_PCI) == AH_FALSE) { + AR5K_AR5210_RC_PCI) == FALSE) { AR5K_PRINT("failed to reset the PCI chipset\n"); - return (AH_FALSE); + return (FALSE); } AR5K_DELAY(1000); @@ -289,58 +290,58 @@ /* ...wakeup the device */ if (ar5k_ar5210_set_power(hal, - HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { + AR5K_PM_AWAKE, TRUE, 0) == FALSE) { AR5K_PRINT("failed to resume the AR5210 chipset\n"); - return (AH_FALSE); + return (FALSE); } /* ...enable Atheros turbo mode if requested */ AR5K_REG_WRITE(AR5K_AR5210_PHY_FC, - turbo == AH_TRUE ? AR5K_AR5210_PHY_FC_TURBO_MODE : 0); + turbo == TRUE ? AR5K_AR5210_PHY_FC_TURBO_MODE : 0); /* ...reset chipset */ - if (ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == AH_FALSE) { + if (ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == FALSE) { AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return (AH_FALSE); + return (FALSE); } AR5K_DELAY(1000); /* ...reset chipset and PCI device */ if (ar5k_ar5210_nic_reset(hal, - AR5K_AR5210_RC_CHIP | AR5K_AR5210_RC_PCI) == AH_FALSE) { + AR5K_AR5210_RC_CHIP | AR5K_AR5210_RC_PCI) == FALSE) { AR5K_PRINT("failed to reset the AR5210 + PCI chipset\n"); - return (AH_FALSE); + return (FALSE); } AR5K_DELAY(2300); /* ...wakeup (again) */ if (ar5k_ar5210_set_power(hal, - HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { + AR5K_PM_AWAKE, TRUE, 0) == FALSE) { AR5K_PRINT("failed to resume the AR5210 (again)\n"); - return (AH_FALSE); + return (FALSE); } /* ...final warm reset */ - if (ar5k_ar5210_nic_reset(hal, 0) == AH_FALSE) { + if (ar5k_ar5210_nic_reset(hal, 0) == FALSE) { AR5K_PRINT("failed to warm reset the AR5210\n"); - return (AH_FALSE); + return (FALSE); } - return (AH_TRUE); + return (TRUE); } -const HAL_RATE_TABLE * +const AR5K_RATE_TABLE * ar5k_ar5210_get_rate_table(struct ath_hal *hal, u_int mode) { switch (mode) { - case HAL_MODE_11A: + case AR5K_MODE_11A: return (&hal->ah_rt_11a); - case HAL_MODE_TURBO: + case AR5K_MODE_TURBO: return (&hal->ah_rt_turbo); - case HAL_MODE_11B: - case HAL_MODE_11G: + case AR5K_MODE_11B: + case AR5K_MODE_11G: default: return (NULL); } @@ -357,28 +358,28 @@ free(hal, M_DEVBUF); } -HAL_BOOL /*New*/ +AR5K_BOOL /*New*/ ar5k_ar5210_phy_disable(struct ath_hal *hal) { AR5K_TRACE; /*Just a try M.F.*/ AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); - return AH_TRUE; + return TRUE; } -HAL_BOOL -ar5k_ar5210_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, - HAL_BOOL change_channel, HAL_STATUS *status) +AR5K_BOOL +ar5k_ar5210_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, + AR5K_BOOL change_channel, AR5K_STATUS *status) { int i; /* Not used, keep for HAL compatibility */ - *status = HAL_OK; + *status = AR5K_OK; if (ar5k_ar5210_nic_wakeup(hal, - channel->c_channel_flags & IEEE80211_CHAN_T ? - AH_TRUE : AH_FALSE, AH_FALSE) == AH_FALSE) - return (AH_FALSE); + channel->channel_flags & CHANNEL_T ? + TRUE : FALSE, FALSE) == FALSE) + return (FALSE); /* * Initialize operating mode @@ -390,7 +391,7 @@ * Write initial mode register settings */ for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) { - if (change_channel == AH_TRUE && + if (change_channel == TRUE && ar5210_ini[i].ini_register >= AR5K_AR5210_PCU_MIN && ar5210_ini[i].ini_register <= AR5K_AR5210_PCU_MAX) continue; @@ -418,8 +419,8 @@ AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); AR5K_DELAY(1000); - if (ar5k_channel(hal, channel) == AH_FALSE) - return (AH_FALSE); + if (ar5k_channel(hal, channel) == FALSE) + return (FALSE); /* * Activate phy and wait @@ -428,13 +429,13 @@ AR5K_DELAY(1000); ar5k_ar5210_do_calibrate(hal, channel); - if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE) - return (AH_FALSE); + if (ar5k_ar5210_noise_floor(hal, channel) == FALSE) + return (FALSE); /* * Set RF kill flags if supported by the device (read from the EEPROM) */ - if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { +/* if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { ar5k_ar5210_set_gpio_input(hal, 0); if ((hal->ah_gpio[0] = ar5k_ar5210_get_gpio(hal, 0)) == 0) { ar5k_ar5210_set_gpio_intr(hal, 0, 1); @@ -442,21 +443,21 @@ ar5k_ar5210_set_gpio_intr(hal, 0, 0); } } - +*/ /* * Reset queues and start beacon timers at the end of the reset routine */ for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { - if (ar5k_ar5210_reset_tx_queue(hal, i) == AH_FALSE) { + if (ar5k_ar5210_reset_tx_queue(hal, i) == FALSE) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); - return (AH_FALSE); + return (FALSE); } } AR5K_REG_DISABLE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_EN | AR5K_AR5210_BEACON_RESET_TSF); - return (AH_TRUE); + return (TRUE); } void /*Unimplemented*/ @@ -481,27 +482,27 @@ pcu_reg = 0; switch (hal->ah_op_mode) { - case IEEE80211_M_STA: + case AR5K_M_STA: pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DESC_ANTENNA | AR5K_AR5210_STA_ID1_PWR_SV; break; - case IEEE80211_M_IBSS: + case AR5K_M_IBSS: pcu_reg |= AR5K_AR5210_STA_ID1_ADHOC | AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DESC_ANTENNA; beacon_reg |= AR5K_AR5210_BCR_ADHOC; break; - case IEEE80211_M_HOSTAP: + case AR5K_M_HOSTAP: pcu_reg |= AR5K_AR5210_STA_ID1_AP | AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DESC_ANTENNA; beacon_reg |= AR5K_AR5210_BCR_AP; break; - case IEEE80211_M_MONITOR: + case AR5K_M_MONITOR: pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL; break; @@ -529,10 +530,10 @@ return; } -HAL_BOOL -ar5k_ar5210_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL +ar5k_ar5210_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) { - HAL_BOOL ret = AH_TRUE; + AR5K_BOOL ret = TRUE; u_int32_t phy_sig, phy_agc, phy_sat, beacon; #define AGC_DISABLE { \ @@ -570,7 +571,7 @@ AGC_ENABLE; - if (ret == AH_FALSE) + if (ret == FALSE) return (ret); /* @@ -614,11 +615,11 @@ AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, phy_agc); AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, phy_sat); - if (ret == AH_FALSE) - return (AH_FALSE); + if (ret == FALSE) + return (FALSE); - if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE) - return (AH_FALSE); + if (ar5k_ar5210_noise_floor(hal, channel) == FALSE) + return (FALSE); /* * Re-enable RX/TX and beacons @@ -630,11 +631,11 @@ #undef AGC_ENABLE #undef AGC_DISABLE - return (AH_TRUE); + return (TRUE); } -HAL_BOOL -ar5k_ar5210_do_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL +ar5k_ar5210_do_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) { /* * Enable calibration and wait until completion @@ -643,17 +644,17 @@ AR5K_AR5210_PHY_AGCCTL_CAL); if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, - AR5K_AR5210_PHY_AGCCTL_CAL, 0, AH_FALSE) == AH_FALSE) { + AR5K_AR5210_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) { AR5K_PRINTF("calibration timeout (%uMHz)\n", - channel->c_channel); - return (AH_FALSE); + channel->freq); + return (FALSE); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL -ar5k_ar5210_noise_floor(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL +ar5k_ar5210_noise_floor(struct ath_hal *hal, AR5K_CHANNEL *channel) { int i; u_int32_t noise_floor; @@ -665,10 +666,10 @@ AR5K_AR5210_PHY_AGCCTL_NF); if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, - AR5K_AR5210_PHY_AGCCTL_NF, 0, AH_FALSE) == AH_FALSE) { + AR5K_AR5210_PHY_AGCCTL_NF, 0, FALSE) == FALSE) { AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", - channel->c_channel); - return (AH_FALSE); + channel->freq); + return (FALSE); } /* wait until the noise floor is calibrated */ @@ -684,31 +685,31 @@ if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", - channel->c_channel); - return (AH_FALSE); + channel->freq); + return (FALSE); } - return (AH_TRUE); + return (TRUE); } /* * Transmit functions */ -HAL_BOOL -ar5k_ar5210_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) +AR5K_BOOL +ar5k_ar5210_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) { u_int32_t trigger_level; - HAL_BOOL status = AH_FALSE; + AR5K_BOOL status = FALSE; /* * Disable interrupts by setting the mask */ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL); + AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR, AR5K_INT_GLOBAL); trigger_level = AR5K_REG_READ(AR5K_AR5210_TRIG_LVL); - if (increase == AH_FALSE) { + if (increase == FALSE) { if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) goto done; } else { @@ -720,20 +721,20 @@ * Update trigger level on success */ AR5K_REG_WRITE(AR5K_AR5210_TRIG_LVL, trigger_level); - status = AH_TRUE; + status = TRUE; done: /* * Restore interrupt mask */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL); + AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_INT_GLOBAL); return (status); } int -ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, - HAL_TXQ_INFO *queue_info) +ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, + AR5K_TXQ_INFO *queue_info) { u_int queue; @@ -741,11 +742,11 @@ * Get queue by type */ switch (queue_type) { - case HAL_TX_QUEUE_DATA: + case AR5K_TX_QUEUE_DATA: queue = 0; break; - case HAL_TX_QUEUE_BEACON: - case HAL_TX_QUEUE_CAB: + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: queue = 1; break; default: @@ -755,57 +756,57 @@ /* * Setup internal queue structure */ - bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); + bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); hal->ah_txq[queue].tqi_type = queue_type; if (queue_info != NULL) { queue_info->tqi_type = queue_type; if (ar5k_ar5210_setup_tx_queueprops(hal, - queue, queue_info) != AH_TRUE) + queue, queue_info) != TRUE) return (-1); } return (queue); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_setup_tx_queueprops(struct ath_hal *hal, int queue, - const HAL_TXQ_INFO *queue_info) + const AR5K_TXQ_INFO *queue_info) { AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) - return (AH_FALSE); + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (FALSE); hal->ah_txq[queue].tqi_aifs = queue_info->tqi_aifs; hal->ah_txq[queue].tqi_cw_max = queue_info->tqi_cw_max; hal->ah_txq[queue].tqi_cw_min = queue_info->tqi_cw_min; hal->ah_txq[queue].tqi_flags = queue_info->tqi_flags; - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*New*/ -ar5k_ar5210_get_tx_queueprops(struct ath_hal *hal, int queue, HAL_TXQ_INFO *queue_info) +AR5K_BOOL /*New*/ +ar5k_ar5210_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) { AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); - return (AH_TRUE); + memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_release_tx_queue(struct ath_hal *hal, u_int queue) { AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* This queue will be skipped in further operations */ - hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; + hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; - return (AH_FALSE); + return (FALSE); } void -ar5k_ar5210_init_tx_queue(struct ath_hal *hal, u_int aifs, HAL_BOOL turbo) +ar5k_ar5210_init_tx_queue(struct ath_hal *hal, u_int aifs, AR5K_BOOL turbo) { int i; struct { @@ -818,32 +819,32 @@ */ for (i = 0; i < AR5K_ELEMENTS(initial); i++) AR5K_REG_WRITE((u_int32_t)initial[i].mode_register, - turbo == AH_TRUE ? + turbo == TRUE ? initial[i].mode_turbo : initial[i].mode_base); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_reset_tx_queue(struct ath_hal *hal, u_int queue) { u_int32_t cw_min, retry_lg, retry_sh; - HAL_TXQ_INFO *tq; + AR5K_TXQ_INFO *tq; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); tq = &hal->ah_txq[queue]; /* Only handle data queues, others will be ignored */ - if (tq->tqi_type != HAL_TX_QUEUE_DATA) - return (AH_TRUE); + if (tq->tqi_type != AR5K_TX_QUEUE_DATA) + return (TRUE); /* Set turbo/base mode parameters */ ar5k_ar5210_init_tx_queue(hal, hal->ah_aifs + tq->tqi_aifs, - hal->ah_turbo == AH_TRUE ? AH_TRUE : AH_FALSE); + hal->ah_turbo == TRUE ? TRUE : FALSE); /* * Set retry limits */ - if (hal->ah_software_retry == AH_TRUE) { + if (hal->ah_software_retry == TRUE) { /* XXX Need to test this */ retry_lg = hal->ah_limit_tx_retries; retry_sh = retry_lg = @@ -873,7 +874,7 @@ | AR5K_REG_SM(retry_lg, AR5K_AR5210_RETRY_LMT_LG_RETRY) | AR5K_REG_SM(retry_sh, AR5K_AR5210_RETRY_LMT_SH_RETRY)); - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -887,11 +888,11 @@ * Get the transmit queue descriptor pointer register by type */ switch (hal->ah_txq[queue].tqi_type) { - case HAL_TX_QUEUE_DATA: + case AR5K_TX_QUEUE_DATA: tx_reg = AR5K_AR5210_TXDP0; break; - case HAL_TX_QUEUE_BEACON: - case HAL_TX_QUEUE_CAB: + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: tx_reg = AR5K_AR5210_TXDP1; break; default: @@ -901,7 +902,7 @@ return (AR5K_REG_READ(tx_reg)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) { u_int16_t tx_reg; @@ -912,30 +913,30 @@ * Get the transmit queue descriptor pointer register by type */ switch (hal->ah_txq[queue].tqi_type) { - case HAL_TX_QUEUE_DATA: + case AR5K_TX_QUEUE_DATA: tx_reg = AR5K_AR5210_TXDP0; break; - case HAL_TX_QUEUE_BEACON: - case HAL_TX_QUEUE_CAB: + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: tx_reg = AR5K_AR5210_TXDP1; break; default: - return (AH_FALSE); + return (FALSE); } /* Set descriptor pointer */ AR5K_REG_WRITE(tx_reg, phys_addr); - return (AH_TRUE); + return (TRUE); } u_int32_t /*Unimplemented*/ ar5k_ar5210_num_tx_pending(struct ath_hal *hal, u_int queue) { AR5K_TRACE; - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_tx_start(struct ath_hal *hal, u_int queue) { u_int32_t tx_queue; @@ -948,17 +949,17 @@ * Set the queue type */ switch (hal->ah_txq[queue].tqi_type) { - case HAL_TX_QUEUE_DATA: + case AR5K_TX_QUEUE_DATA: tx_queue |= AR5K_AR5210_CR_TXE0 & ~AR5K_AR5210_CR_TXD0; break; - case HAL_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_BEACON: tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1; AR5K_REG_WRITE(AR5K_AR5210_BSR, AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE); break; - case HAL_TX_QUEUE_CAB: + case AR5K_TX_QUEUE_CAB: tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1; AR5K_REG_WRITE(AR5K_AR5210_BSR, AR5K_AR5210_BCR_TQ1FV | AR5K_AR5210_BCR_TQ1V | @@ -966,16 +967,16 @@ break; default: - return (AH_FALSE); + return (FALSE); } /* Start queue */ AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_stop_tx_dma(struct ath_hal *hal, u_int queue) { u_int32_t tx_queue; @@ -988,30 +989,30 @@ * Set by queue type */ switch (hal->ah_txq[queue].tqi_type) { - case HAL_TX_QUEUE_DATA: + case AR5K_TX_QUEUE_DATA: tx_queue |= AR5K_AR5210_CR_TXD0 & ~AR5K_AR5210_CR_TXE0; break; - case HAL_TX_QUEUE_BEACON: - case HAL_TX_QUEUE_CAB: + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: /* XXX Fix me... */ tx_queue |= AR5K_AR5210_CR_TXD1 & ~AR5K_AR5210_CR_TXD1; AR5K_REG_WRITE(AR5K_AR5210_BSR, 0); break; default: - return (AH_FALSE); + return (FALSE); } /* Stop queue */ AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K. - Initialize tx_desc and clear ds_hw */ +AR5K_BOOL /*O.K. - Initialize tx_desc and clear ds_hw */ ar5k_ar5210_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, + u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { @@ -1027,7 +1028,7 @@ * Validate input */ if (tx_tries0 == 0) - return (AH_FALSE); + return (FALSE); /* Initialize status descriptor */ tx_desc->tx_control_0 = 0; @@ -1037,15 +1038,15 @@ if ((tx_desc->tx_control_0 = (packet_length & AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN)) != packet_length) - return (AH_FALSE); + return (FALSE); if ((tx_desc->tx_control_0 = (header_length & AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN)) != header_length) - return (AH_FALSE); + return (FALSE); - if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP) + if (type == AR5K_PKT_TYPE_BEACON || type == AR5K_PKT_TYPE_PROBE_RESP) frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY; - else if (type == HAL_PKT_TYPE_PIFS) + else if (type == AR5K_PKT_TYPE_PIFS) frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS; else frame_type = type; @@ -1056,7 +1057,7 @@ AR5K_REG_SM(tx_rate0, AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE); #define _TX_FLAGS(_c, _flag) \ - if (flags & HAL_TXDESC_##_flag) \ + if (flags & AR5K_TXDESC_##_flag) \ tx_desc->tx_control_##_c |= \ AR5K_AR5210_DESC_TX_CTL##_c##_##_flag @@ -1069,7 +1070,7 @@ /* * WEP crap */ - if (key_index != HAL_TXKEYIX_INVALID) { + if (key_index != AR5K_TXKEYIX_INVALID) { tx_desc->tx_control_0 |= AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID; tx_desc->tx_control_1 |= @@ -1080,17 +1081,17 @@ /* * RTS/CTS */ - if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { + if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { tx_desc->tx_control_1 |= rtscts_duration & AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION; } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*Added an argument *last_desc -need revision -don't clear descriptor here*/ +AR5K_BOOL /*Added an argument *last_desc -need revision -don't clear descriptor here*/ ar5k_ar5210_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment, const struct ath_desc *last_desc) + u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) { struct ar5k_ar5210_tx_desc *tx_desc; @@ -1102,18 +1103,18 @@ /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_AR5210_DESC_TX_CTL1_BUF_LEN)) != segment_length) - return (AH_FALSE); + return (FALSE); - if (first_segment != AH_TRUE) + if (first_segment != TRUE) tx_desc->tx_control_0 &= ~AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN; - if (last_segment != AH_TRUE) + if (last_segment != TRUE) tx_desc->tx_control_1 |= AR5K_AR5210_DESC_TX_CTL1_MORE; - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, u_int tx_rate3, u_int tx_tries3) @@ -1123,10 +1124,10 @@ * Nevertheless, I didn't find any information about XR support * by the AR5210. This seems to be a slightly new feature. */ - return (AH_FALSE); + return (FALSE); } -HAL_STATUS +AR5K_STATUS ar5k_ar5210_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) { struct ar5k_ar5210_tx_status *tx_status; @@ -1137,7 +1138,7 @@ /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_AR5210_DESC_TX_STATUS1_DONE) == 0) - return (HAL_EINPROGRESS); + return (AR5K_EINPROGRESS); /* * Get descriptor status @@ -1167,24 +1168,24 @@ AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { if (tx_status->tx_status_0 & AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; + desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; if (tx_status->tx_status_0 & AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; + desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; if (tx_status->tx_status_0 & AR5K_AR5210_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; + desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return (HAL_OK); + return (AR5K_OK); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_has_veol(struct ath_hal *hal) { - return (AH_FALSE); + return (FALSE); } void /*Unimplemented*/ @@ -1217,7 +1218,7 @@ AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_stop_rx_dma(struct ath_hal *hal) { int i; @@ -1232,7 +1233,7 @@ i--) AR5K_DELAY(10); - return (i > 0 ? AH_TRUE : AH_FALSE); + return (i > 0 ? TRUE : FALSE); } void @@ -1256,11 +1257,11 @@ AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL1, filter1); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) { if (index >= 64) { - return (AH_FALSE); + return (FALSE); } else if (index >= 32) { AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL1, (1 << (index - 32))); @@ -1269,14 +1270,14 @@ (1 << index)); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) { if (index >= 64) { - return (AH_FALSE); + return (FALSE); } else if (index >= 32) { AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL1, (1 << (index - 32))); @@ -1285,7 +1286,7 @@ (1 << index)); } - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -1300,15 +1301,15 @@ /* * The AR5210 uses promiscous mode to detect radar activity */ - if (filter & HAL_RX_FILTER_PHYRADAR) { - filter &= ~HAL_RX_FILTER_PHYRADAR; + if (filter & AR5K_RX_FILTER_PHYRADAR) { + filter &= ~AR5K_RX_FILTER_PHYRADAR; filter |= AR5K_AR5210_RX_FILTER_PROMISC; } AR5K_REG_WRITE(AR5K_AR5210_RX_FILTER, filter); } -HAL_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ +AR5K_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ ar5k_ar5210_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t size, u_int flags) { @@ -1333,15 +1334,15 @@ if ((rx_desc->rx_control_1 = (size & AR5K_AR5210_DESC_RX_CTL1_BUF_LEN)) != size) - return (AH_FALSE); + return (FALSE); - if (flags & HAL_RXDESC_INTREQ) + if (flags & AR5K_RXDESC_INTREQ) rx_desc->rx_control_1 |= AR5K_AR5210_DESC_RX_CTL1_INTREQ; - return (AH_TRUE); + return (TRUE); } -HAL_STATUS +AR5K_STATUS ar5k_ar5210_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { @@ -1351,7 +1352,7 @@ /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_DONE) == 0) - return (HAL_EINPROGRESS); + return (AR5K_EINPROGRESS); /* * Frame receive status @@ -1382,7 +1383,7 @@ AR5K_REG_MS(rx_status->rx_status_1, AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX); } else { - desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; + desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; } /* @@ -1392,15 +1393,15 @@ AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { if (rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; + desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; if (rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN) - desc->ds_us.rx.rs_status |= HAL_RXERR_FIFO; + desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; if (rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR) { - desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; + desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; desc->ds_us.rx.rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1, AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR); @@ -1408,14 +1409,14 @@ if (rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; + desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; } - return (HAL_OK); + return (AR5K_OK); } -void /*Added HAL_NODE_STATS argument*/ -ar5k_ar5210_set_rx_signal(struct ath_hal *hal, const HAL_NODE_STATS *stats) +void /*Added AR5K_NODE_STATS argument*/ +ar5k_ar5210_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) { /* Signal state monitoring is not yet supported */ } @@ -1514,14 +1515,14 @@ #endif } -HAL_BOOL /*Added arguments*/ +AR5K_BOOL /*Added arguments*/ ar5k_ar5210_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) { /* * We'll ignore this right now. This seems to be some kind of an obscure * debugging interface for the binary-only HAL. */ - return (AH_FALSE); + return (FALSE); } void @@ -1530,7 +1531,7 @@ bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) { u_int32_t low_id, high_id; @@ -1545,30 +1546,30 @@ AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id); AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, high_id); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - HAL_STATUS *status) + AR5K_STATUS *status) { ieee80211_regdomain_t ieee_regdomain; ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); - if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, - &ieee_regdomain) == AH_TRUE) { - *status = HAL_OK; - return (AH_TRUE); + if (ar5k_eeprom_regulation_domain(hal, TRUE, + &ieee_regdomain) == TRUE) { + *status = AR5K_OK; + return (TRUE); } *status = EIO; - return (AH_FALSE); + return (FALSE); } void -ar5k_ar5210_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) +ar5k_ar5210_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) { u_int32_t led; @@ -1578,13 +1579,13 @@ * Some blinking values, define at your wish */ switch (state) { - case IEEE80211_S_SCAN: - case IEEE80211_S_INIT: + case AR5K_LED_SCAN: + case AR5K_LED_INIT: led |= AR5K_AR5210_PCICFG_LED_PEND | AR5K_AR5210_PCICFG_LED_BCTL; break; - case IEEE80211_S_RUN: + case AR5K_LED_RUN: led |= AR5K_AR5210_PCICFG_LED_ACT; break; @@ -1626,30 +1627,30 @@ ar5k_ar5210_enable_pspoll(hal, NULL, 0); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) { if (gpio > AR5K_AR5210_NUM_GPIO) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) | AR5K_AR5210_GPIOCR_OUT1(gpio)); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) { if (gpio > AR5K_AR5210_NUM_GPIO) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) | AR5K_AR5210_GPIOCR_IN(gpio)); - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -1663,13 +1664,13 @@ AR5K_AR5210_GPIOD_MASK) >> gpio) & 0x1); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) { u_int32_t data; if (gpio > AR5K_AR5210_NUM_GPIO) - return (0xffffffff); + return (FALSE); /* GPIO output magic */ data = AR5K_REG_READ(AR5K_AR5210_GPIODO); @@ -1679,7 +1680,7 @@ AR5K_REG_WRITE(AR5K_AR5210_GPIODO, data); - return (AH_TRUE); + return (TRUE); } void @@ -1734,7 +1735,7 @@ return (ar5k_get_regdomain(hal)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_detect_card_present(struct ath_hal *hal) { u_int16_t magic; @@ -1745,13 +1746,13 @@ * way to do this. */ if (ar5k_ar5210_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (AH_FALSE); + return (FALSE); - return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); + return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); } void -ar5k_ar5210_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) +ar5k_ar5210_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) { statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5210_ACK_FAIL); statistics->rts_bad += AR5K_REG_READ(AR5K_AR5210_RTS_FAIL); @@ -1761,28 +1762,28 @@ } void /*Unimplemented*/ -ar5k_ar5210_proc_mib_event(struct ath_hal *hal, const HAL_NODE_STATS *stats) +ar5k_ar5210_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) { AR5K_TRACE; return; } -HAL_RFGAIN +AR5K_RFGAIN ar5k_ar5210_get_rf_gain(struct ath_hal *hal) { - return (HAL_RFGAIN_INACTIVE); + return (AR5K_RFGAIN_INACTIVE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_slot_time(struct ath_hal *hal, u_int slot_time) { - if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) - return (AH_FALSE); + if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) + return (FALSE); AR5K_REG_WRITE(AR5K_AR5210_SLOT_TIME, ar5k_htoclock(slot_time, hal->ah_turbo)); - return (AH_TRUE); + return (TRUE); } u_int @@ -1792,17 +1793,17 @@ 0xffff, hal->ah_turbo)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_ack_timeout(struct ath_hal *hal, u_int timeout) { if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo) <= timeout) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_ACK, ar5k_htoclock(timeout, hal->ah_turbo)); - return (AH_TRUE); + return (TRUE); } u_int @@ -1812,17 +1813,17 @@ AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_cts_timeout(struct ath_hal *hal, u_int timeout) { if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo) <= timeout) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_CTS, ar5k_htoclock(timeout, hal->ah_turbo)); - return (AH_TRUE); + return (TRUE); } u_int @@ -1832,79 +1833,77 @@ AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo)); } -HAL_STATUS /*New*/ -ar5k_ar5210_get_capability(struct ath_hal *hal, HAL_CAPABILITY_TYPE cap_type, +AR5K_STATUS /*New*/ +ar5k_ar5210_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, u_int32_t capability, u_int32_t *result) { AR5K_TRACE; switch (cap_type) { - case HAL_CAP_REG_DMN: + case AR5K_CAP_REG_DMN: if (result){ *result = ar5k_get_regdomain(hal); goto yes; } - case HAL_CAP_CIPHER: + case AR5K_CAP_CIPHER: switch (capability) { - case HAL_CIPHER_WEP: goto yes; + case AR5K_CIPHER_WEP: goto yes; default: goto no; } - case HAL_CAP_NUM_TXQUEUES: + case AR5K_CAP_NUM_TXQUEUES: if (result) { *result = AR5K_AR5210_TX_NUM_QUEUES; goto yes; } - case HAL_CAP_VEOL: + case AR5K_CAP_VEOL: goto yes; - case HAL_CAP_PSPOLL: - goto no; - case HAL_CAP_COMPRESSION: + case AR5K_CAP_COMPRESSION: goto yes; - case HAL_CAP_BURST: + case AR5K_CAP_BURST: goto yes; - case HAL_CAP_TPC: + case AR5K_CAP_TPC: goto yes; - case HAL_CAP_BSSIDMASK: + case AR5K_CAP_BSSIDMASK: goto yes; - case HAL_CAP_XR: + case AR5K_CAP_XR: goto yes; default: goto no; } no: - return (HAL_EINVAL); + return (AR5K_EINVAL); yes: - return HAL_OK; + return AR5K_OK; } -HAL_BOOL -ar5k_ar5210_set_capability(struct ath_hal *hal, HAL_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, HAL_STATUS *status) +AR5K_BOOL +ar5k_ar5210_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, + u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) { AR5K_TRACE; if (status) { - *status = HAL_OK; + *status = AR5K_OK; } - return (AH_FALSE); + return (FALSE); } /* * Key table (WEP) functions */ -HAL_BOOL -ar5k_ar5210_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) +AR5K_BOOL +ar5k_ar5210_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) { /* * The AR5210 only supports WEP */ - if (cipher == HAL_CIPHER_WEP) - return (AH_TRUE); + if (cipher == AR5K_CIPHER_WEP) + return (TRUE); - return (AH_FALSE); + return (FALSE); } u_int32_t @@ -1913,7 +1912,7 @@ return (AR5K_AR5210_KEYCACHE_SIZE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_reset_key(struct ath_hal *hal, u_int16_t entry) { int i; @@ -1923,10 +1922,10 @@ for (i = 0; i < AR5K_AR5210_KEYCACHE_SIZE; i++) AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), 0); - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_is_key_valid(struct ath_hal *hal, u_int16_t entry) { AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); @@ -1936,14 +1935,14 @@ */ if (AR5K_REG_READ(AR5K_AR5210_KEYTABLE_MAC1(entry)) & AR5K_AR5210_KEYTABLE_VALID) - return (AH_TRUE); + return (TRUE); - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_key(struct ath_hal *hal, u_int16_t entry, - const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) + const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) { int i; u_int32_t key_v[AR5K_AR5210_KEYCACHE_SIZE - 2]; @@ -1979,7 +1978,7 @@ default: /* Unsupported key length (not WEP40/104/128) */ - return (AH_FALSE); + return (FALSE); } for (i = 0; i < AR5K_ELEMENTS(key_v); i++) @@ -1988,7 +1987,7 @@ return (ar5k_ar5210_set_key_lladdr(hal, entry, mac)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, const u_int8_t *mac) { @@ -2010,16 +2009,16 @@ AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC1(entry), high_id); - return (AH_TRUE); + return (TRUE); } /* * Power management functions */ -HAL_BOOL -ar5k_ar5210_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, - HAL_BOOL set_chip, u_int16_t sleep_duration) +AR5K_BOOL +ar5k_ar5210_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, + AR5K_BOOL set_chip, u_int16_t sleep_duration) { u_int32_t staid; int i; @@ -2027,27 +2026,27 @@ staid = AR5K_REG_READ(AR5K_AR5210_STA_ID1); switch (mode) { - case HAL_PM_AUTO: + case AR5K_PM_AUTO: staid &= ~AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA; /* fallthrough */ - case HAL_PM_NETWORK_SLEEP: - if (set_chip == AH_TRUE) { + case AR5K_PM_NETWORK_SLEEP: + if (set_chip == TRUE) { AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE | sleep_duration); } staid |= AR5K_AR5210_STA_ID1_PWR_SV; break; - case HAL_PM_FULL_SLEEP: - if (set_chip == AH_TRUE) { + case AR5K_PM_FULL_SLEEP: + if (set_chip == TRUE) { AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_SLP); } staid |= AR5K_AR5210_STA_ID1_PWR_SV; break; - case HAL_PM_AWAKE: - if (set_chip == AH_FALSE) + case AR5K_PM_AWAKE: + if (set_chip == FALSE) goto commit; AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_WAKE); @@ -2066,13 +2065,13 @@ /* Fail if the AR5210 didn't wake up */ if (i <= 0) - return (AH_FALSE); + return (FALSE); staid &= ~AR5K_AR5210_STA_ID1_PWR_SV; break; default: - return (AH_FALSE); + return (FALSE); } commit: @@ -2080,32 +2079,32 @@ AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, staid); - return (AH_TRUE); + return (TRUE); } -HAL_POWER_MODE +AR5K_POWER_MODE ar5k_ar5210_get_power_mode(struct ath_hal *hal) { return (hal->ah_power_mode); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_query_pspoll_support(struct ath_hal *hal) { /* I think so, why not? */ - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_init_pspoll(struct ath_hal *hal) { /* * Not used on the AR5210 */ - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, u_int16_t assoc_id) { @@ -2113,27 +2112,27 @@ AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_disable_pspoll(struct ath_hal *hal) { AR5K_REG_ENABLE_BITS(AR5K_AR5210_STA_ID1, AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*Unimplemented*/ +AR5K_BOOL /*Unimplemented*/ ar5k_ar5210_set_txpower_limit(struct ath_hal *hal, u_int32_t power) { -// HAL_CHANNEL *channel = &hal->ah_current_channel; +// AR5K_CHANNEL *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n unimplemented ;-(",power); - return AH_FALSE; + return FALSE; } /* @@ -2150,7 +2149,7 @@ * Set the additional timers by mode */ switch (hal->ah_op_mode) { - case HAL_M_STA: + case AR5K_M_STA: timer1 = 0xffffffff; timer2 = 0xffffffff; timer3 = 1; @@ -2177,8 +2176,8 @@ AR5K_AR5210_BEACON_EN)); } -void /*Removed arguments - should be changed through *state - review HAL_BEACON_STATE struct*/ -ar5k_ar5210_set_beacon_timers(struct ath_hal *hal, const HAL_BEACON_STATE *state) +void /*Removed arguments - should be changed through *state - review AR5K_BEACON_STATE struct*/ +ar5k_ar5210_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) { u_int32_t cfp_period, next_cfp; @@ -2255,8 +2254,8 @@ AR5K_REG_WRITE(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_PERIOD); } -HAL_BOOL -ar5k_ar5210_wait_for_beacon(struct ath_hal *hal, HAL_BUS_ADDR phys_addr) +AR5K_BOOL +ar5k_ar5210_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) { int i; @@ -2278,55 +2277,55 @@ AR5K_REG_WRITE(AR5K_AR5210_BCR, AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE); - return (AH_FALSE); + return (FALSE); } - return (AH_TRUE); + return (TRUE); } /* * Interrupt handling */ -HAL_BOOL +AR5K_BOOL ar5k_ar5210_is_intr_pending(struct ath_hal *hal) { - return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE); + return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? FALSE : TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5210_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) { u_int32_t data; - if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == HAL_INT_NOCARD) { + if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == AR5K_INT_NOCARD) { *interrupt_mask = data; - return (AH_FALSE); + return (FALSE); } /* * Get abstract interrupt mask (HAL-compatible) */ - *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; + *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; if (data & (AR5K_AR5210_ISR_RXOK | AR5K_AR5210_ISR_RXERR)) - *interrupt_mask |= HAL_INT_RX; + *interrupt_mask |= AR5K_INT_RX; if (data & (AR5K_AR5210_ISR_TXOK | AR5K_AR5210_ISR_TXERR)) - *interrupt_mask |= HAL_INT_TX; + *interrupt_mask |= AR5K_INT_TX; if (data & AR5K_AR5210_ISR_FATAL) - *interrupt_mask |= HAL_INT_FATAL; + *interrupt_mask |= AR5K_INT_FATAL; /* * Special interrupt handling (not caught by the driver) */ if (((*interrupt_mask) & AR5K_AR5210_ISR_RXPHY) && - hal->ah_radar.r_enabled == AH_TRUE) + hal->ah_radar.r_enabled == TRUE) ar5k_radar_alert(hal); /* XXX BMISS interrupts may occur after association */ - *interrupt_mask &= ~HAL_INT_BMISS; + *interrupt_mask &= ~AR5K_INT_BMISS; - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -2336,10 +2335,10 @@ return (hal->ah_imr); } -HAL_INT -ar5k_ar5210_set_intr(struct ath_hal *hal, HAL_INT new_mask) +AR5K_INT +ar5k_ar5210_set_intr(struct ath_hal *hal, AR5K_INT new_mask) { - HAL_INT old_mask, int_mask; + AR5K_INT old_mask, int_mask; /* * Disable card interrupts to prevent any race conditions @@ -2353,15 +2352,15 @@ * Add additional, chipset-dependent interrupt mask flags * and write them to the IMR (interrupt mask register). */ - int_mask = new_mask & HAL_INT_COMMON; + int_mask = new_mask & AR5K_INT_COMMON; - if (new_mask & HAL_INT_RX) + if (new_mask & AR5K_INT_RX) int_mask |= AR5K_AR5210_IMR_RXOK | AR5K_AR5210_IMR_RXERR | AR5K_AR5210_IMR_RXORN; - if (new_mask & HAL_INT_TX) + if (new_mask & AR5K_INT_TX) int_mask |= AR5K_AR5210_IMR_TXOK | AR5K_AR5210_IMR_TXERR | @@ -2384,7 +2383,7 @@ * Misc internal functions */ -HAL_BOOL +AR5K_BOOL ar5k_ar5210_get_capabilities(struct ath_hal *hal) { /* Set number of supported TX queues */ @@ -2400,16 +2399,16 @@ hal->ah_capabilities.cap_range.range_2ghz_max = 0; /* Set supported modes */ - hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; + hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO; /* Set number of GPIO pins */ hal->ah_gpio_npins = AR5K_AR5210_NUM_GPIO; - return (AH_TRUE); + return (TRUE); } void -ar5k_ar5210_radar_alert(struct ath_hal *hal, HAL_BOOL enable) +ar5k_ar5210_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) { /* * Set the RXPHY interrupt to be able to detect @@ -2417,7 +2416,7 @@ */ AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); - if (enable == AH_TRUE) { + if (enable == TRUE) { AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_AR5210_IMR_RXPHY); } else { @@ -2432,11 +2431,11 @@ * EEPROM access functions */ -HAL_BOOL +AR5K_BOOL ar5k_ar5210_eeprom_is_busy(struct ath_hal *hal) { return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ? - AH_TRUE : AH_FALSE); + TRUE : FALSE); } int Index: ar5211.c =================================================================== --- ar5211.c (revision 1948) +++ ar5211.c (revision 1972) @@ -1,7 +1,6 @@ -/* $OpenBSD: ar5211.c,v 1.25 2005/12/18 17:59:58 reyk Exp $ */ - /* - * Copyright (c) 2004, 2005 Reyk Floeter + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -14,6 +13,8 @@ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ */ /* @@ -25,11 +26,11 @@ #include "ar5211reg.h" #include "ar5211var.h" -HAL_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t); -HAL_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t); -u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, HAL_CHIP); +AR5K_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t); +AR5K_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t); +u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, AR5K_CHIP); void ar5k_ar5211_fill(struct ath_hal *); -void ar5k_ar5211_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int, +void ar5k_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int, u_int); /* @@ -194,8 +195,8 @@ } struct ath_hal * /*Ported & removed an arg from call to set_associd*/ -ar5k_ar5211_attach(u_int16_t device, HAL_SOFTC sc, HAL_BUS_TAG st, - HAL_BUS_HANDLE sh, HAL_STATUS *status) +ar5k_ar5211_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, + AR5K_BUS_HANDLE sh, AR5K_STATUS *status) { struct ath_hal *hal = (struct ath_hal*) sc; u_int8_t mac[IEEE80211_ADDR_LEN]; @@ -204,7 +205,7 @@ ar5k_ar5211_fill(hal); /* Bring device out of sleep and reset it's units */ - if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) + if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != TRUE) return (NULL); /* Get MAC, PHY and RADIO revisions */ @@ -215,7 +216,7 @@ hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) & 0x00ffffffff; hal->ah_radio_5ghz_revision = - ar5k_ar5211_radio_revision(hal, HAL_CHIP_5GHZ); + ar5k_ar5211_radio_revision(hal, AR5K_CHIP_5GHZ); hal->ah_radio_2ghz_revision = 0; /* Identify the chipset (this has to be done in an early step) */ @@ -231,10 +232,10 @@ return (hal); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val) { - HAL_BOOL ret = AH_FALSE; + AR5K_BOOL ret = FALSE; u_int32_t mask = val ? val : ~0; /* Read-and-clear */ @@ -254,7 +255,7 @@ mask &= AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; - ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE); + ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, FALSE); /* * Reset configuration register @@ -265,7 +266,7 @@ return (ret); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags) { u_int32_t turbo, mode, clock; @@ -278,29 +279,29 @@ * Get channel mode flags */ - if (flags & IEEE80211_CHAN_2GHZ) { + if (flags & CHANNEL_2GHZ) { mode |= AR5K_AR5211_PHY_MODE_FREQ_2GHZ; clock |= AR5K_AR5211_PHY_PLL_44MHZ; - } else if (flags & IEEE80211_CHAN_5GHZ) { + } else if (flags & CHANNEL_5GHZ) { mode |= AR5K_AR5211_PHY_MODE_FREQ_5GHZ; clock |= AR5K_AR5211_PHY_PLL_40MHZ; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (AH_FALSE); + return (FALSE); } - if ((flags & IEEE80211_CHAN_CCK) || - (flags & IEEE80211_CHAN_DYN)) { + if ((flags & CHANNEL_CCK) || + (flags & CHANNEL_DYN)) { /* Dynamic OFDM/CCK is not supported by the AR5211 */ mode |= AR5K_AR5211_PHY_MODE_MOD_CCK; - } else if (flags & IEEE80211_CHAN_OFDM) { + } else if (flags & CHANNEL_OFDM) { mode |= AR5K_AR5211_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (AH_FALSE); + return (FALSE); } - if (flags & IEEE80211_CHAN_TURBO) { + if (flags & CHANNEL_TURBO) { turbo = AR5K_AR5211_PHY_TURBO_MODE | AR5K_AR5211_PHY_TURBO_SHORT; } @@ -311,22 +312,22 @@ /* ...reset chipset and PCI device */ if (ar5k_ar5211_nic_reset(hal, - AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == AH_FALSE) { + AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == FALSE) { AR5K_PRINT("failed to reset the AR5211 + PCI chipset\n"); - return (AH_FALSE); + return (FALSE); } /* ...wakeup */ if (ar5k_ar5211_set_power(hal, - HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { + AR5K_PM_AWAKE, TRUE, 0) == FALSE) { AR5K_PRINT("failed to resume the AR5211 (again)\n"); - return (AH_FALSE); + return (FALSE); } /* ...final warm reset */ - if (ar5k_ar5211_nic_reset(hal, 0) == AH_FALSE) { + if (ar5k_ar5211_nic_reset(hal, 0) == FALSE) { AR5K_PRINT("failed to warm reset the AR5211\n"); - return (AH_FALSE); + return (FALSE); } /* ...set the PHY operating mode */ @@ -336,11 +337,11 @@ AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode); AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo); - return (AH_TRUE); + return (TRUE); } u_int16_t -ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip) +ar5k_ar5211_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) { int i; u_int32_t srev; @@ -350,10 +351,10 @@ * Set the radio chip access register */ switch (chip) { - case HAL_CHIP_2GHZ: + case AR5K_CHIP_2GHZ: AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ); break; - case HAL_CHIP_5GHZ: + case AR5K_CHIP_5GHZ: AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); break; default: @@ -377,18 +378,17 @@ return (ret); } -const HAL_RATE_TABLE * +const AR5K_RATE_TABLE * ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode) { switch (mode) { - case HAL_MODE_11A: + case AR5K_MODE_11A: return (&hal->ah_rt_11a); - case HAL_MODE_TURBO: + case AR5K_MODE_TURBO: return (&hal->ah_rt_turbo); - case HAL_MODE_11B: + case AR5K_MODE_11B: return (&hal->ah_rt_11b); - case HAL_MODE_11G: - case HAL_MODE_PUREG: + case AR5K_MODE_11G: return (&hal->ah_rt_11g); default: return (NULL); @@ -406,18 +406,18 @@ free(hal, M_DEVBUF); } -HAL_BOOL /*New*/ +AR5K_BOOL /*New*/ ar5k_ar5211_phy_disable(struct ath_hal *hal) { AR5K_TRACE; /*Just a try M.F.*/ AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE); - return AH_TRUE; + return TRUE; } -HAL_BOOL /*Ported*/ -ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, - HAL_BOOL change_channel, HAL_STATUS *status) +AR5K_BOOL /*Ported*/ +ar5k_ar5211_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, + AR5K_BOOL change_channel, AR5K_STATUS *status) { struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int8_t mac[IEEE80211_ADDR_LEN]; @@ -427,7 +427,7 @@ /* * Save some registers before a reset */ - if (change_channel == AH_TRUE) { + if (change_channel == TRUE) { s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0)); s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); } else { @@ -440,15 +440,15 @@ s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR); s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO); - if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) - return (AH_FALSE); + if (ar5k_ar5211_nic_wakeup(hal, channel->channel_flags) == FALSE) + return (FALSE); /* * Initialize operating mode */ hal->ah_op_mode = op_mode; - switch (channel->c_channel_flags & CHANNEL_MODES) { + switch (channel->channel_flags & CHANNEL_MODES) { case CHANNEL_A: mode = AR5K_INI_VAL_11A; freq = AR5K_INI_RFGAIN_5GHZ; @@ -465,14 +465,13 @@ ee_mode = AR5K_EEPROM_MODE_11B; break; case CHANNEL_G: - case CHANNEL_PUREG: mode = AR5K_INI_VAL_11G; freq = AR5K_INI_RFGAIN_2GHZ; ee_mode = AR5K_EEPROM_MODE_11G; break; default: - AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); - return (AH_FALSE); + AR5K_PRINTF("invalid channel: %d\n", channel->freq); + return (FALSE); } /* PHY access enable */ @@ -496,7 +495,7 @@ * Write initial register settings */ for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { - if (change_channel == AH_TRUE && + if (change_channel == TRUE && ar5211_ini[i].ini_register >= AR5K_AR5211_PCU_MIN && ar5211_ini[i].ini_register <= AR5K_AR5211_PCU_MAX) continue; @@ -509,8 +508,8 @@ /* * Write initial RF gain settings */ - if (ar5k_rfgain(hal, AR5K_INI_PHY_5111, freq) == AH_FALSE) - return (AH_FALSE); + if (ar5k_rfgain(hal, AR5K_INI_PHY_5111, freq) == FALSE) + return (FALSE); AR5K_DELAY(1000); @@ -519,7 +518,7 @@ */ if (hal->ah_radio == AR5K_AR5111) { - if (channel->c_channel_flags & IEEE80211_CHAN_B) + if (channel->channel_flags & CHANNEL_B) AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_B_MODE); else @@ -532,9 +531,9 @@ hal->ah_antenna[ee_mode][0], 0xfffffc06); if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] =HAL_ANT_FIXED_B; + ant[0] = ant[1] =AR5K_ANT_FIXED_B; else - ant[0] = ant[1] = HAL_ANT_FIXED_A; + ant[0] = ant[1] = AR5K_ANT_FIXED_A; AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0, hal->ah_antenna[ee_mode][ant[0]]); @@ -602,8 +601,8 @@ /* * Set channel and calibrate the PHY */ - if (ar5k_channel(hal, channel) == AH_FALSE) - return (AH_FALSE); + if (ar5k_channel(hal, channel) == FALSE) + return (FALSE); /* * Enable the PHY and wait until completion @@ -612,7 +611,7 @@ data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) & AR5K_AR5211_PHY_RX_DELAY_M; - data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? + data = (channel->channel_flags & CHANNEL_CCK) ? ((data << 2) / 22) : (data / 10); AR5K_DELAY(100 + data); @@ -624,10 +623,10 @@ AR5K_AR5211_PHY_AGCCTL_NF | AR5K_AR5211_PHY_AGCCTL_CAL); - if (channel->c_channel_flags & IEEE80211_CHAN_B) { - hal->ah_calibration = AH_FALSE; + if (channel->channel_flags & CHANNEL_B) { + hal->ah_calibration = FALSE; } else { - hal->ah_calibration = AH_TRUE; + hal->ah_calibration = TRUE; AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_IQ, AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX, 15); AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, @@ -639,33 +638,33 @@ */ for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { AR5K_REG_WRITE_Q(AR5K_AR5211_DCU_QCUMASK(i), i); - if (ar5k_ar5211_reset_tx_queue(hal, i) == AH_FALSE) { + if (ar5k_ar5211_reset_tx_queue(hal, i) == FALSE) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); - return (AH_FALSE); + return (FALSE); } } /* Pre-enable interrupts */ - ar5k_ar5211_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); + ar5k_ar5211_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); /* * Set RF kill flags if supported by the device (read from the EEPROM) */ - if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { +/* if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { ar5k_ar5211_set_gpio_input(hal, 0); if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0) ar5k_ar5211_set_gpio_intr(hal, 0, 1); else ar5k_ar5211_set_gpio_intr(hal, 0, 0); } - +*/ /* * Disable beacons and reset the register */ AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_ENABLE | AR5K_AR5211_BEACON_RESET_TSF); - return (AH_TRUE); + return (TRUE); } void /*New*/ @@ -693,18 +692,18 @@ pcu_reg = 0; switch (hal->ah_op_mode) { - case IEEE80211_M_IBSS: + case AR5K_M_IBSS: pcu_reg |= AR5K_AR5211_STA_ID1_ADHOC | AR5K_AR5211_STA_ID1_DESC_ANTENNA; break; - case IEEE80211_M_HOSTAP: + case AR5K_M_HOSTAP: pcu_reg |= AR5K_AR5211_STA_ID1_AP | AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA; break; - case IEEE80211_M_STA: - case IEEE80211_M_MONITOR: + case AR5K_M_STA: + case AR5K_M_MONITOR: pcu_reg |= AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; break; @@ -731,17 +730,17 @@ return; } -HAL_BOOL -ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL +ar5k_ar5211_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int32_t i_pwr, q_pwr; int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; - if (hal->ah_calibration == AH_FALSE || + if (hal->ah_calibration == FALSE || AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN) goto done; - hal->ah_calibration = AH_FALSE; + hal->ah_calibration = FALSE; iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR); i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I); @@ -766,28 +765,28 @@ AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, AR5K_AR5211_PHY_AGCCTL_NF); - return (AH_TRUE); + return (TRUE); } /* * Transmit functions */ -HAL_BOOL -ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) +AR5K_BOOL +ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) { u_int32_t trigger_level, imr; - HAL_BOOL status = AH_FALSE; + AR5K_BOOL status = FALSE; /* * Disable interrupts by setting the mask */ - imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); + imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG), AR5K_AR5211_TXCFG_TXFULL); - if (increase == AH_FALSE) { + if (increase == FALSE) { if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) goto done; } else @@ -799,7 +798,7 @@ */ AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_TXFULL, trigger_level); - status = AH_TRUE; + status = TRUE; done: /* @@ -811,39 +810,39 @@ } int -ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, - HAL_TXQ_INFO *queue_info) +ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, + AR5K_TXQ_INFO *queue_info) { u_int queue; /* * Get queue by type */ - if (queue_type == HAL_TX_QUEUE_DATA) { - for (queue = HAL_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; + if (queue_type == AR5K_TX_QUEUE_DATA) { + for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; + hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; queue++) - if (queue > HAL_TX_QUEUE_ID_DATA_MAX) + if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) return (-1); - } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { - queue = HAL_TX_QUEUE_ID_PSPOLL; - } else if (queue_type == HAL_TX_QUEUE_BEACON) { - queue = HAL_TX_QUEUE_ID_BEACON; - } else if (queue_type == HAL_TX_QUEUE_CAB) { - queue = HAL_TX_QUEUE_ID_CAB; + } else if (queue_type == AR5K_TX_QUEUE_UAPSD) { + queue = AR5K_TX_QUEUE_ID_UAPSD; + } else if (queue_type == AR5K_TX_QUEUE_BEACON) { + queue = AR5K_TX_QUEUE_ID_BEACON; + } else if (queue_type == AR5K_TX_QUEUE_CAB) { + queue = AR5K_TX_QUEUE_ID_CAB; } else return (-1); /* * Setup internal queue structure */ - bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); + bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); hal->ah_txq[queue].tqi_type = queue_type; if (queue_info != NULL) { queue_info->tqi_type = queue_type; if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info) - != AH_TRUE) + != TRUE) return (-1); } @@ -852,65 +851,64 @@ return (queue); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue, - const HAL_TXQ_INFO *queue_info) + const AR5K_TXQ_INFO *queue_info) { AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - if (hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE) - return (AH_FALSE); + if (hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE) + return (FALSE); - bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); + bcopy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && - (queue_info->tqi_subtype >= HAL_WME_AC_VI) && - (queue_info->tqi_subtype <= HAL_WME_UPSD)) + if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && + ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || + (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || + queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*New*/ -ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue, HAL_TXQ_INFO *queue_info) +AR5K_BOOL /*New*/ +ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) { AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); - return (AH_TRUE); + memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue) { AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* This queue will be skipped in further operations */ - hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; + hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue) { u_int32_t cw_min, cw_max, retry_lg, retry_sh; - struct ieee80211_channel *channel = (struct ieee80211_channel*) - &hal->ah_current_channel; - HAL_TXQ_INFO *tq; + AR5K_TXQ_INFO *tq; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); tq = &hal->ah_txq[queue]; - if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) - return (AH_TRUE); + if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (TRUE); /* * Set registers by channel mode */ - if (IEEE80211_IS_CHAN_B(channel)) { + if (IS_CHAN_B(hal->ah_current_channel)) { hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; hal->ah_aifs = AR5K_TUNE_AIFS_11B; @@ -923,7 +921,7 @@ /* * Set retry limits */ - if (hal->ah_software_retry == AH_TRUE) { + if (hal->ah_software_retry == TRUE) { /* XXX Need to test this */ retry_lg = hal->ah_limit_tx_retries; retry_sh = retry_lg = @@ -1014,7 +1012,7 @@ * Set registers by queue type */ switch (tq->tqi_type) { - case HAL_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_BEACON: AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | AR5K_AR5211_QCU_MISC_CBREXP_BCN | @@ -1033,7 +1031,7 @@ AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); break; - case HAL_TX_QUEUE_CAB: + case AR5K_TX_QUEUE_CAB: AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | AR5K_AR5211_QCU_MISC_CBREXP | @@ -1044,12 +1042,12 @@ AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL)); break; - case HAL_TX_QUEUE_PSPOLL: + case AR5K_TX_QUEUE_UAPSD: AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_AR5211_QCU_MISC_CBREXP); break; - case HAL_TX_QUEUE_DATA: + case AR5K_TX_QUEUE_DATA: default: break; } @@ -1065,7 +1063,7 @@ AR5K_REG_WRITE(AR5K_AR5211_SIMR2, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN)); - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -1079,7 +1077,7 @@ return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue))); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) { AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -1089,11 +1087,11 @@ * (this won't work if the queue is still active) */ if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue)) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr); - return (AH_TRUE); + return (TRUE); } u_int32_t /*Code from roofnet*/ @@ -1103,22 +1101,22 @@ return (AR5K_AR5211_QCU_STS(queue) & AR5K_AR5211_QCU_STS_FRMPENDCNT); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue) { AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* Return if queue is disabled */ if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXD, queue)) - return (AH_FALSE); + return (FALSE); /* Start queue */ AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXE, queue); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*Fixed delay*/ +AR5K_BOOL /*Fixed delay*/ ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue) { int i = 100, pending; @@ -1139,12 +1137,12 @@ /* Clear register */ AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K. - Initialize tx_desc and clear ds_hw */ +AR5K_BOOL /*O.K. - Initialize tx_desc and clear ds_hw */ ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, + u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { @@ -1159,7 +1157,7 @@ * Validate input */ if (tx_tries0 == 0) - return (AH_FALSE); + return (FALSE); /* Initialize status descriptor */ tx_desc->tx_control_0 = 0; @@ -1169,7 +1167,7 @@ if ((tx_desc->tx_control_0 = (packet_length & AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) - return (AH_FALSE); + return (FALSE); tx_desc->tx_control_0 |= AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | @@ -1178,7 +1176,7 @@ AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); #define _TX_FLAGS(_c, _flag) \ - if (flags & HAL_TXDESC_##_flag) \ + if (flags & AR5K_TXDESC_##_flag) \ tx_desc->tx_control_##_c |= \ AR5K_AR5211_DESC_TX_CTL##_c##_##_flag @@ -1193,7 +1191,7 @@ /* * WEP crap */ - if (key_index != HAL_TXKEYIX_INVALID) { + if (key_index != AR5K_TXKEYIX_INVALID) { tx_desc->tx_control_0 |= AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; tx_desc->tx_control_1 |= @@ -1201,12 +1199,12 @@ AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL/*Added an argument *last_desc -need revision -don't clear descriptor here*/ +AR5K_BOOL/*Added an argument *last_desc -need revision -don't clear descriptor here*/ ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment, const struct ath_desc *last_desc) + u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) { struct ar5k_ar5211_tx_desc *tx_desc; @@ -1218,26 +1216,26 @@ /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_AR5211_DESC_TX_CTL1_BUF_LEN)) != segment_length) - return (AH_FALSE); + return (FALSE); - if (first_segment != AH_TRUE) + if (first_segment != TRUE) tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; - if (last_segment != AH_TRUE) + if (last_segment != TRUE) tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, u_int tx_rate3, u_int tx_tries3) { - return (AH_FALSE); + return (FALSE); } -HAL_STATUS +AR5K_STATUS ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) { struct ar5k_ar5211_tx_status *tx_status; @@ -1248,7 +1246,7 @@ /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0) - return (HAL_EINPROGRESS); + return (AR5K_EINPROGRESS); /* * Get descriptor status @@ -1278,24 +1276,24 @@ AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { if (tx_status->tx_status_0 & AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; + desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; if (tx_status->tx_status_0 & AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; + desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; if (tx_status->tx_status_0 & AR5K_AR5211_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; + desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return (HAL_OK); + return (AR5K_OK); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_has_veol(struct ath_hal *hal) { - return (AH_TRUE); + return (TRUE); } void /*Unimplemented*/ @@ -1328,7 +1326,7 @@ AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_stop_rx_dma(struct ath_hal *hal) { int i; @@ -1343,7 +1341,7 @@ i--) AR5K_DELAY(10); - return (i > 0 ? AH_TRUE : AH_FALSE); + return (i > 0 ? TRUE : FALSE); } void @@ -1367,11 +1365,11 @@ AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) { if (index >= 64) { - return (AH_FALSE); + return (FALSE); } else if (index >= 32) { AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1, (1 << (index - 32))); @@ -1380,15 +1378,15 @@ (1 << index)); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) { if (index >= 64) { - return (AH_FALSE); + return (FALSE); } else if (index >= 32) { AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL1, (1 << (index - 32))); @@ -1397,7 +1395,7 @@ (1 << index)); } - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -1412,7 +1410,7 @@ AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter); } -HAL_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ +AR5K_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t size, u_int flags) { @@ -1437,15 +1435,15 @@ if ((rx_desc->rx_control_1 = (size & AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size) - return (AH_FALSE); + return (FALSE); - if (flags & HAL_RXDESC_INTREQ) + if (flags & AR5K_RXDESC_INTREQ) rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ; - return (AH_TRUE); + return (TRUE); } -HAL_STATUS +AR5K_STATUS ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { @@ -1455,7 +1453,7 @@ /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) - return (HAL_EINPROGRESS); + return (AR5K_EINPROGRESS); /* * Frame receive status @@ -1486,7 +1484,7 @@ AR5K_REG_MS(rx_status->rx_status_1, AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); } else { - desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; + desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; } /* @@ -1496,11 +1494,11 @@ AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { if (rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; + desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; if (rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { - desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; + desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; desc->ds_us.rx.rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1, AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); @@ -1508,14 +1506,14 @@ if (rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; + desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; } - return (HAL_OK); + return (AR5K_OK); } -void /*Added HAL_NODE_STATS argument*/ -ar5k_ar5211_set_rx_signal(struct ath_hal *hal, const HAL_NODE_STATS *stats) +void /*Added AR5K_NODE_STATS argument*/ +ar5k_ar5211_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) { /* Signal state monitoring is not yet supported */ } @@ -1613,14 +1611,14 @@ #endif } -HAL_BOOL /*Added arguments*/ +AR5K_BOOL /*Added arguments*/ ar5k_ar5211_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) { /* * We'll ignore this right now. This seems to be some kind of an obscure * debugging interface for the binary-only HAL. */ - return (AH_FALSE); + return (FALSE); } void @@ -1629,7 +1627,7 @@ bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) { u_int32_t low_id, high_id; @@ -1644,30 +1642,30 @@ AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - HAL_STATUS *status) + AR5K_STATUS *status) { ieee80211_regdomain_t ieee_regdomain; ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); - if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, - &ieee_regdomain) == AH_TRUE) { - *status = HAL_OK; - return (AH_TRUE); + if (ar5k_eeprom_regulation_domain(hal, TRUE, + &ieee_regdomain) == TRUE) { + *status = AR5K_OK; + return (TRUE); } *status = EIO; - return (AH_FALSE); + return (FALSE); } void -ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) +ar5k_ar5211_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) { u_int32_t led; @@ -1678,19 +1676,19 @@ * Some blinking values, define at your wish */ switch (state) { - case IEEE80211_S_SCAN: - case IEEE80211_S_AUTH: + case AR5K_LED_SCAN: + case AR5K_LED_AUTH: led = AR5K_AR5211_PCICFG_LEDMODE_PROP | AR5K_AR5211_PCICFG_LED_PEND; break; - case IEEE80211_S_INIT: + case AR5K_LED_INIT: led = AR5K_AR5211_PCICFG_LEDMODE_PROP | AR5K_AR5211_PCICFG_LED_NONE; break; - case IEEE80211_S_ASSOC: - case IEEE80211_S_RUN: + case AR5K_LED_ASSOC: + case AR5K_LED_RUN: led = AR5K_AR5211_PCICFG_LEDMODE_PROP | AR5K_AR5211_PCICFG_LED_ASSOC; break; @@ -1736,30 +1734,30 @@ ar5k_ar5211_enable_pspoll(hal, NULL, 0); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) { if (gpio > AR5K_AR5211_NUM_GPIO) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) | AR5K_AR5211_GPIOCR_ALL(gpio)); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) { if (gpio > AR5K_AR5211_NUM_GPIO) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) | AR5K_AR5211_GPIOCR_NONE(gpio)); - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -1773,13 +1771,13 @@ AR5K_AR5211_GPIODI_M) >> gpio) & 0x1); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) { u_int32_t data; if (gpio > AR5K_AR5211_NUM_GPIO) - return (0xffffffff); + return (FALSE); /* GPIO output magic */ data = AR5K_REG_READ(AR5K_AR5211_GPIODO); @@ -1789,7 +1787,7 @@ AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data); - return (AH_TRUE); + return (TRUE); } void @@ -1845,7 +1843,7 @@ return (ar5k_get_regdomain(hal)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_detect_card_present(struct ath_hal *hal) { u_int16_t magic; @@ -1856,13 +1854,13 @@ * way to do this. */ if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (AH_FALSE); + return (FALSE); - return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); + return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); } void -ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) +ar5k_ar5211_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) { statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL); statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL); @@ -1872,27 +1870,27 @@ } void /*Unimplemented*/ -ar5k_ar5211_proc_mib_event(struct ath_hal *hal, const HAL_NODE_STATS *stats) +ar5k_ar5211_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) { AR5K_TRACE; return; } -HAL_RFGAIN +AR5K_RFGAIN ar5k_ar5211_get_rf_gain(struct ath_hal *hal) { - return (HAL_RFGAIN_INACTIVE); + return (AR5K_RFGAIN_INACTIVE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time) { - if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) - return (AH_FALSE); + if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) + return (FALSE); AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time); - return (AH_TRUE); + return (TRUE); } u_int @@ -1901,17 +1899,17 @@ return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout) { if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK), hal->ah_turbo) <= timeout) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_ACK, ar5k_htoclock(timeout, hal->ah_turbo)); - return (AH_TRUE); + return (TRUE); } u_int @@ -1921,17 +1919,17 @@ AR5K_AR5211_TIME_OUT_ACK), hal->ah_turbo)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout) { if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS), hal->ah_turbo) <= timeout) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_CTS, ar5k_htoclock(timeout, hal->ah_turbo)); - return (AH_TRUE); + return (TRUE); } u_int @@ -1941,79 +1939,77 @@ AR5K_AR5211_TIME_OUT_CTS), hal->ah_turbo)); } -HAL_STATUS /*New*/ -ar5k_ar5211_get_capability(struct ath_hal *hal, HAL_CAPABILITY_TYPE cap_type, +AR5K_STATUS /*New*/ +ar5k_ar5211_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, u_int32_t capability, u_int32_t *result) { AR5K_TRACE; switch (cap_type) { - case HAL_CAP_REG_DMN: + case AR5K_CAP_REG_DMN: if (result){ *result = ar5k_get_regdomain(hal); goto yes; } - case HAL_CAP_CIPHER: + case AR5K_CAP_CIPHER: switch (capability) { - case HAL_CIPHER_WEP: goto yes; + case AR5K_CIPHER_WEP: goto yes; default: goto no; } - case HAL_CAP_NUM_TXQUEUES: + case AR5K_CAP_NUM_TXQUEUES: if (result) { *result = AR5K_AR5211_TX_NUM_QUEUES; goto yes; } - case HAL_CAP_VEOL: + case AR5K_CAP_VEOL: goto yes; - case HAL_CAP_PSPOLL: - goto no; - case HAL_CAP_COMPRESSION: + case AR5K_CAP_COMPRESSION: goto yes; - case HAL_CAP_BURST: + case AR5K_CAP_BURST: goto yes; - case HAL_CAP_TPC: + case AR5K_CAP_TPC: goto yes; - case HAL_CAP_BSSIDMASK: + case AR5K_CAP_BSSIDMASK: goto yes; - case HAL_CAP_XR: + case AR5K_CAP_XR: goto yes; default: goto no; } no: - return (HAL_EINVAL); + return (AR5K_EINVAL); yes: - return HAL_OK; + return AR5K_OK; } -HAL_BOOL -ar5k_ar5211_set_capability(struct ath_hal *hal, HAL_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, HAL_STATUS *status) +AR5K_BOOL +ar5k_ar5211_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, + u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) { AR5K_TRACE; if (status) { - *status = HAL_OK; + *status = AR5K_OK; } - return (AH_FALSE); + return (FALSE); } /* * Key table (WEP) functions */ -HAL_BOOL -ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) +AR5K_BOOL +ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) { /* * The AR5211 only supports WEP */ - if (cipher == HAL_CIPHER_WEP) - return (AH_TRUE); + if (cipher == AR5K_CIPHER_WEP) + return (TRUE); - return (AH_FALSE); + return (FALSE); } u_int32_t @@ -2022,7 +2018,7 @@ return (AR5K_AR5211_KEYCACHE_SIZE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry) { int i; @@ -2032,10 +2028,10 @@ for (i = 0; i < AR5K_AR5211_KEYCACHE_SIZE; i++) AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0); - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry) { AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); @@ -2045,14 +2041,14 @@ */ if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) & AR5K_AR5211_KEYTABLE_VALID) - return (AH_TRUE); + return (TRUE); - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry, - const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) + const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) { int i; u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2]; @@ -2088,7 +2084,7 @@ default: /* Unsupported key length (not WEP40/104/128) */ - return (AH_FALSE); + return (FALSE); } for (i = 0; i < AR5K_ELEMENTS(key_v); i++) @@ -2097,7 +2093,7 @@ return (ar5k_ar5211_set_key_lladdr(hal, entry, mac)); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, const u_int8_t *mac) { @@ -2119,16 +2115,16 @@ AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id); - return (AH_TRUE); + return (TRUE); } /* * Power management functions */ -HAL_BOOL -ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, - HAL_BOOL set_chip, u_int16_t sleep_duration) +AR5K_BOOL +ar5k_ar5211_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, + AR5K_BOOL set_chip, u_int16_t sleep_duration) { u_int32_t staid; int i; @@ -2136,27 +2132,27 @@ staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1); switch (mode) { - case HAL_PM_AUTO: + case AR5K_PM_AUTO: staid &= ~AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; /* fallthrough */ - case HAL_PM_NETWORK_SLEEP: - if (set_chip == AH_TRUE) { + case AR5K_PM_NETWORK_SLEEP: + if (set_chip == TRUE) { AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE | sleep_duration); } staid |= AR5K_AR5211_STA_ID1_PWR_SV; break; - case HAL_PM_FULL_SLEEP: - if (set_chip == AH_TRUE) { + case AR5K_PM_FULL_SLEEP: + if (set_chip == TRUE) { AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_SLP); } staid |= AR5K_AR5211_STA_ID1_PWR_SV; break; - case HAL_PM_AWAKE: - if (set_chip == AH_FALSE) + case AR5K_PM_AWAKE: + if (set_chip == FALSE) goto commit; AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE); @@ -2175,13 +2171,13 @@ /* Fail if the AR5211 didn't wake up */ if (i <= 0) - return (AH_FALSE); + return (FALSE); staid &= ~AR5K_AR5211_STA_ID1_PWR_SV; break; default: - return (AH_FALSE); + return (FALSE); } commit: @@ -2189,52 +2185,52 @@ AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid); - return (AH_TRUE); + return (TRUE); } -HAL_POWER_MODE +AR5K_POWER_MODE ar5k_ar5211_get_power_mode(struct ath_hal *hal) { return (hal->ah_power_mode); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_query_pspoll_support(struct ath_hal *hal) { /* nope */ - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_init_pspoll(struct ath_hal *hal) { /* * Not used on the AR5211 */ - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, u_int16_t assoc_id) { - return (AH_FALSE); + return (FALSE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_disable_pspoll(struct ath_hal *hal) { - return (AH_FALSE); + return (FALSE); } -HAL_BOOL /*Unimplemented*/ +AR5K_BOOL /*Unimplemented*/ ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int32_t power) { -// HAL_CHANNEL *channel = &hal->ah_current_channel; +// AR5K_CHANNEL *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n unimplemented ;-(",power); - return AH_FALSE; + return FALSE; } /* @@ -2251,7 +2247,7 @@ * Set the additional timers by mode */ switch (hal->ah_op_mode) { - case HAL_M_STA: + case AR5K_M_STA: timer1 = 0x0000ffff; timer2 = 0x0007ffff; break; @@ -2280,8 +2276,8 @@ AR5K_AR5211_BEACON_ENABLE)); } -void /*Removed arguments - should be changed through *state - review HAL_BEACON_STATE struct*/ -ar5k_ar5211_set_beacon_timers(struct ath_hal *hal, const HAL_BEACON_STATE *state) +void /*Removed arguments - should be changed through *state - review AR5K_BEACON_STATE struct*/ +ar5k_ar5211_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) { u_int32_t cfp_period, next_cfp; @@ -2342,7 +2338,7 @@ AR5K_REG_WRITE_BITS(AR5K_AR5211_RSSI_THR_M, AR5K_AR5211_RSSI_THR_BMISS, state->bs_bmiss_threshold); AR5K_REG_WRITE_BITS(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLDUR, - (state->bs_sleepduration - 3) << 3); + (state->bs_sleep_duration - 3) << 3); } void @@ -2361,20 +2357,20 @@ AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD); } -HAL_BOOL -ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, HAL_BUS_ADDR phys_addr) +AR5K_BOOL +ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) { - HAL_BOOL ret; + AR5K_BOOL ret; /* * Wait for beaconn queue to be done */ ret = ar5k_register_timeout(hal, - AR5K_AR5211_QCU_STS(HAL_TX_QUEUE_ID_BEACON), - AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE); + AR5K_AR5211_QCU_STS(AR5K_TX_QUEUE_ID_BEACON), + AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, FALSE); - if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) - return (AH_FALSE); + if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) + return (FALSE); return (ret); } @@ -2383,13 +2379,13 @@ * Interrupt handling */ -HAL_BOOL +AR5K_BOOL ar5k_ar5211_is_intr_pending(struct ath_hal *hal) { - return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE); + return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? FALSE : TRUE); } -HAL_BOOL +AR5K_BOOL ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) { u_int32_t data; @@ -2402,28 +2398,28 @@ /* * Get abstract interrupt mask (HAL-compatible) */ - *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; + *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; - if (data == HAL_INT_NOCARD) - return (AH_FALSE); + if (data == AR5K_INT_NOCARD) + return (FALSE); if (data & (AR5K_AR5211_PISR_RXOK | AR5K_AR5211_PISR_RXERR)) - *interrupt_mask |= HAL_INT_RX; + *interrupt_mask |= AR5K_INT_RX; if (data & (AR5K_AR5211_PISR_TXOK | AR5K_AR5211_PISR_TXERR)) - *interrupt_mask |= HAL_INT_TX; + *interrupt_mask |= AR5K_INT_TX; if (data & (AR5K_AR5211_PISR_HIUERR)) - *interrupt_mask |= HAL_INT_FATAL; + *interrupt_mask |= AR5K_INT_FATAL; /* * Special interrupt handling (not caught by the driver) */ if (((*interrupt_mask) & AR5K_AR5211_PISR_RXPHY) && - hal->ah_radar.r_enabled == AH_TRUE) + hal->ah_radar.r_enabled == TRUE) ar5k_radar_alert(hal); - return (AH_TRUE); + return (TRUE); } u_int32_t @@ -2433,10 +2429,10 @@ return (hal->ah_imr); } -HAL_INT -ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask) +AR5K_INT +ar5k_ar5211_set_intr(struct ath_hal *hal, AR5K_INT new_mask) { - HAL_INT old_mask, int_mask; + AR5K_INT old_mask, int_mask; /* * Disable card interrupts to prevent any race conditions @@ -2450,23 +2446,23 @@ * Add additional, chipset-dependent interrupt mask flags * and write them to the IMR (interrupt mask register). */ - int_mask = new_mask & HAL_INT_COMMON; + int_mask = new_mask & AR5K_INT_COMMON; - if (new_mask & HAL_INT_RX) + if (new_mask & AR5K_INT_RX) int_mask |= AR5K_AR5211_PIMR_RXOK | AR5K_AR5211_PIMR_RXERR | AR5K_AR5211_PIMR_RXORN | AR5K_AR5211_PIMR_RXDESC; - if (new_mask & HAL_INT_TX) + if (new_mask & AR5K_INT_TX) int_mask |= AR5K_AR5211_PIMR_TXOK | AR5K_AR5211_PIMR_TXERR | AR5K_AR5211_PIMR_TXDESC | AR5K_AR5211_PIMR_TXURN; - if (new_mask & HAL_INT_FATAL) { + if (new_mask & AR5K_INT_FATAL) { int_mask |= AR5K_AR5211_PIMR_HIUERR; AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2, AR5K_AR5211_SIMR2_MCABT | @@ -2489,7 +2485,7 @@ * Misc internal functions */ -HAL_BOOL +AR5K_BOOL ar5k_ar5211_get_capabilities(struct ath_hal *hal) { u_int16_t ee_header; @@ -2516,7 +2512,7 @@ hal->ah_capabilities.cap_range.range_5ghz_max = 6100; /* Set supported modes */ - hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; + hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO; } /* This chip will support 802.11b if the 2GHz radio is connected */ @@ -2525,10 +2521,10 @@ hal->ah_capabilities.cap_range.range_2ghz_max = 2732; if (AR5K_EEPROM_HDR_11B(ee_header)) - hal->ah_capabilities.cap_mode |= HAL_MODE_11B; + hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; #if 0 if (AR5K_EEPROM_HDR_11G(ee_header)) - hal->ah_capabilities.cap_mode |= HAL_MODE_11G; + hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; #endif } @@ -2538,18 +2534,18 @@ /* Set number of supported TX queues */ hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES; - return (AH_TRUE); + return (TRUE); } void -ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable) +ar5k_ar5211_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) { /* * Enable radar detection */ AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); - if (enable == AH_TRUE) { + if (enable == TRUE) { AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, AR5K_AR5211_PHY_RADAR_ENABLE); AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, @@ -2568,11 +2564,11 @@ * EEPROM access functions */ -HAL_BOOL +AR5K_BOOL ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal) { return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ? - AH_TRUE : AH_FALSE); + TRUE : FALSE); } int @@ -2636,7 +2632,7 @@ */ void -ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq, +ar5k_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, u_int ee_mode) { struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -2660,10 +2656,10 @@ if (freq == AR5K_INI_RFGAIN_5GHZ) { /* For 11a and Turbo */ - obdb = channel->c_channel >= 5725 ? 3 : - (channel->c_channel >= 5500 ? 2 : - (channel->c_channel >= 5260 ? 1 : - (channel->c_channel > 4000 ? 0 : -1))); + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); } ob = ee->ee_ob[ee_mode][obdb]; @@ -2691,5 +2687,5 @@ rf[i].rf_value[freq]); } - hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; + hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; } Index: ar5212.c =================================================================== --- ar5212.c (revision 1948) +++ ar5212.c (revision 1972) @@ -1,7 +1,6 @@ -/* $OpenBSD: ar5212.c,v 1.28 2005/12/18 17:59:58 reyk Exp $ */ - /* - * Copyright (c) 2004, 2005 Reyk Floeter + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -14,6 +13,8 @@ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ */ /* @@ -25,11 +26,11 @@ #include "ar5212reg.h" #include "ar5212var.h" -HAL_BOOL ar5k_ar5212_nic_reset(struct ath_hal *, u_int32_t); -HAL_BOOL ar5k_ar5212_nic_wakeup(struct ath_hal *, u_int16_t); -u_int16_t ar5k_ar5212_radio_revision(struct ath_hal *, HAL_CHIP); +AR5K_BOOL ar5k_ar5212_nic_reset(struct ath_hal *, u_int32_t); +AR5K_BOOL ar5k_ar5212_nic_wakeup(struct ath_hal *, u_int16_t); +u_int16_t ar5k_ar5212_radio_revision(struct ath_hal *, AR5K_CHIP); void ar5k_ar5212_fill(struct ath_hal *); -HAL_BOOL ar5k_ar5212_txpower(struct ath_hal *, HAL_CHANNEL *, u_int); +AR5K_BOOL ar5k_ar5212_txpower(struct ath_hal *, AR5K_CHANNEL *, u_int); /* @@ -193,8 +194,8 @@ } struct ath_hal * /*Ported & removed an arg from call to set_associd*/ -ar5k_ar5212_attach(u_int16_t device, HAL_SOFTC sc, HAL_BUS_TAG st, - HAL_BUS_HANDLE sh, HAL_STATUS *status) +ar5k_ar5212_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, + AR5K_BUS_HANDLE sh, AR5K_STATUS *status) { struct ath_hal *hal = (struct ath_hal*) sc; u_int8_t mac[IEEE80211_ADDR_LEN]; @@ -205,7 +206,7 @@ ar5k_ar5212_fill(hal); /* Bring device out of sleep and reset it's units */ - if (ar5k_ar5212_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) + if (ar5k_ar5212_nic_wakeup(hal, AR5K_INIT_MODE) != TRUE) return (NULL); /* Get MAC, PHY and RADIO revisions */ @@ -216,9 +217,9 @@ hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID) & 0x00ffffffff; hal->ah_radio_5ghz_revision = - ar5k_ar5212_radio_revision(hal, HAL_CHIP_5GHZ); + ar5k_ar5212_radio_revision(hal, AR5K_CHIP_5GHZ); hal->ah_radio_2ghz_revision = - ar5k_ar5212_radio_revision(hal, HAL_CHIP_2GHZ); + ar5k_ar5212_radio_revision(hal, AR5K_CHIP_2GHZ); /* Single chip radio */ if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) @@ -238,10 +239,10 @@ return (hal); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val) { - HAL_BOOL ret = AH_FALSE; + AR5K_BOOL ret = FALSE; u_int32_t mask = val ? val : ~0; AR5K_TRACE; @@ -263,7 +264,7 @@ mask &= AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; - ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, AH_FALSE); + ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, FALSE); /* * Reset configuration register @@ -274,7 +275,7 @@ return (ret); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_nic_wakeup(struct ath_hal *hal, u_int16_t flags) { u_int32_t turbo, mode, clock; @@ -297,29 +298,29 @@ clock = AR5K_AR5212_PHY_PLL_AR5111; } - if (flags & IEEE80211_CHAN_2GHZ) { + if (flags & CHANNEL_2GHZ) { mode |= AR5K_AR5212_PHY_MODE_FREQ_2GHZ; clock |= AR5K_AR5212_PHY_PLL_44MHZ; - } else if (flags & IEEE80211_CHAN_5GHZ) { + } else if (flags & CHANNEL_5GHZ) { mode |= AR5K_AR5212_PHY_MODE_FREQ_5GHZ; clock |= AR5K_AR5212_PHY_PLL_40MHZ; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (AH_FALSE); + return (FALSE); } - if (flags & IEEE80211_CHAN_CCK) { + if (flags & CHANNEL_CCK) { mode |= AR5K_AR5212_PHY_MODE_MOD_CCK; - } else if (flags & IEEE80211_CHAN_OFDM) { + } else if (flags & CHANNEL_OFDM) { mode |= AR5K_AR5212_PHY_MODE_MOD_OFDM; - } else if (flags & IEEE80211_CHAN_DYN) { + } else if (flags & CHANNEL_DYN) { mode |= AR5K_AR5212_PHY_MODE_MOD_DYN; } else { AR5K_PRINT("invalid radio frequency mode\n"); - return (AH_FALSE); + return (FALSE); } - if (flags & IEEE80211_CHAN_TURBO) { + if (flags & CHANNEL_TURBO) { turbo = AR5K_AR5212_PHY_TURBO_MODE | AR5K_AR5212_PHY_TURBO_SHORT; } @@ -329,23 +330,23 @@ */ /* ...reset chipset and PCI device */ - if (hal->ah_single_chip == AH_FALSE && - ar5k_ar5212_nic_reset(hal,AR5K_AR5212_RC_CHIP | AR5K_AR5212_RC_PCI) == AH_FALSE) { + if (hal->ah_single_chip == FALSE && + ar5k_ar5212_nic_reset(hal,AR5K_AR5212_RC_CHIP | AR5K_AR5212_RC_PCI) == FALSE) { AR5K_PRINT("failed to reset the AR5212 + PCI chipset\n"); - return (AH_FALSE); + return (FALSE); } /* ...wakeup */ if (ar5k_ar5212_set_power(hal, - HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { + AR5K_PM_AWAKE, TRUE, 0) == FALSE) { AR5K_PRINT("failed to resume the AR5212 (again)\n"); - return (AH_FALSE); + return (FALSE); } /* ...final warm reset */ - if (ar5k_ar5212_nic_reset(hal, 0) == AH_FALSE) { + if (ar5k_ar5212_nic_reset(hal, 0) == FALSE) { AR5K_PRINT("failed to warm reset the AR5212\n"); - return (AH_FALSE); + return (FALSE); } /* ...set the PHY operating mode */ @@ -355,11 +356,11 @@ AR5K_REG_WRITE(AR5K_AR5212_PHY_MODE, mode); AR5K_REG_WRITE(AR5K_AR5212_PHY_TURBO, turbo); - return (AH_TRUE); + return (TRUE); } u_int16_t /*O.K.*/ -ar5k_ar5212_radio_revision(struct ath_hal *hal, HAL_CHIP chip) +ar5k_ar5212_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) { int i; u_int32_t srev; @@ -371,10 +372,10 @@ * Set the radio chip access register */ switch (chip) { - case HAL_CHIP_2GHZ: + case AR5K_CHIP_2GHZ: AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_2GHZ); break; - case HAL_CHIP_5GHZ: + case AR5K_CHIP_5GHZ: AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); break; default: @@ -398,23 +399,22 @@ return (ret); } -const HAL_RATE_TABLE * /*O.K.*/ +const AR5K_RATE_TABLE * /*O.K.*/ ar5k_ar5212_get_rate_table(struct ath_hal *hal, u_int mode) { AR5K_TRACE; switch (mode) { - case HAL_MODE_11A: + case AR5K_MODE_11A: return (&hal->ah_rt_11a); - case HAL_MODE_TURBO: + case AR5K_MODE_TURBO: return (&hal->ah_rt_turbo); - case HAL_MODE_11B: + case AR5K_MODE_11B: return (&hal->ah_rt_11b); - case HAL_MODE_11G: - case HAL_MODE_PUREG: + case AR5K_MODE_11G: return (&hal->ah_rt_11g); - case HAL_MODE_XR: + case AR5K_MODE_XR: return (&hal->ah_rt_xr); default: return (NULL); @@ -437,33 +437,33 @@ free(hal, M_DEVBUF); } -HAL_BOOL /*New*/ +AR5K_BOOL /*New*/ ar5k_ar5212_phy_disable(struct ath_hal *hal) { AR5K_TRACE; /*Just a try M.F.*/ AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_DISABLE); - return AH_TRUE; + return TRUE; } -HAL_BOOL /*Ported & removed last argument from call to set_associd*/ -ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, - HAL_BOOL change_channel, HAL_STATUS *status) +AR5K_BOOL /*Ported & removed last argument from call to set_associd*/ +ar5k_ar5212_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, + AR5K_BOOL change_channel, AR5K_STATUS *status) { struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int8_t mac[IEEE80211_ADDR_LEN]; u_int32_t data, s_seq, s_ant, s_led[3]; u_int i, phy, mode, freq, off, ee_mode, ant[2]; - const HAL_RATE_TABLE *rt; + const AR5K_RATE_TABLE *rt; AR5K_TRACE; - *status = HAL_OK; + *status = AR5K_OK; /* * Save some registers before a reset */ - if (change_channel == AH_TRUE) { + if (change_channel == TRUE) { s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0)); s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA); } else { @@ -476,12 +476,12 @@ s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR); s_led[2] = AR5K_REG_READ(AR5K_AR5212_GPIODO); - if (change_channel == AH_TRUE && hal->ah_rf_banks != NULL) + if (change_channel == TRUE && hal->ah_rf_banks != NULL) ar5k_ar5212_get_rf_gain(hal); - if (ar5k_ar5212_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) { - *status = HAL_EIO; - return (AH_FALSE); + if (ar5k_ar5212_nic_wakeup(hal, channel->channel_flags) == FALSE) { + *status = AR5K_EIO; + return (FALSE); } /* @@ -495,11 +495,11 @@ phy = AR5K_INI_PHY_5112; } else { AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); - *status = HAL_EINVAL; - return (AH_FALSE); + *status = AR5K_EINVAL; + return (FALSE); } - switch (channel->c_channel_flags & CHANNEL_MODES) { + switch (channel->channel_flags & CHANNEL_MODES) { case CHANNEL_A: mode = AR5K_INI_VAL_11A; freq = AR5K_INI_RFGAIN_5GHZ; @@ -511,7 +511,6 @@ ee_mode = AR5K_EEPROM_MODE_11B; break; case CHANNEL_G: - case CHANNEL_PUREG: mode = AR5K_INI_VAL_11G; freq = AR5K_INI_RFGAIN_2GHZ; ee_mode = AR5K_EEPROM_MODE_11G; @@ -532,9 +531,9 @@ ee_mode = AR5K_EEPROM_MODE_11A; break; default: - AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); - *status = HAL_EINVAL; - return (AH_FALSE); + AR5K_PRINTF("invalid channel: %d\n", channel->freq); + *status = AR5K_EINVAL; + return (FALSE); } /* PHY access enable */ @@ -564,7 +563,7 @@ * Write initial register settings */ for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) { - if (change_channel == AH_TRUE && + if (change_channel == TRUE && ar5212_ini[i].ini_register >= AR5K_AR5212_PCU_MIN && ar5212_ini[i].ini_register <= AR5K_AR5212_PCU_MAX) continue; @@ -582,9 +581,9 @@ /* * Write initial RF gain settings */ - if (ar5k_rfgain(hal, phy, freq) == AH_FALSE) { - *status = HAL_EIO; - return (AH_FALSE); + if (ar5k_rfgain(hal, phy, freq) == FALSE) { + *status = AR5K_EIO; + return (FALSE); } AR5K_DELAY(1000); @@ -593,27 +592,27 @@ * Set rate duration table */ rt = ar5k_ar5212_get_rate_table(hal, - channel->c_channel_flags & IEEE80211_CHAN_TURBO ? - HAL_MODE_TURBO : HAL_MODE_XR); + channel->channel_flags & CHANNEL_TURBO ? + AR5K_MODE_TURBO : AR5K_MODE_XR); - for (i = 0; i < rt->rt_rate_count; i++) { - AR5K_REG_WRITE(AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code), + for (i = 0; i < rt->rate_count; i++) { + AR5K_REG_WRITE(AR5K_AR5212_RATE_DUR(rt->rates[i].rate_code), ath_hal_computetxtime(hal, rt, 14, - rt->rt_info[i].r_control_rate, AH_FALSE)); + rt->rates[i].control_rate, FALSE)); } - if ((channel->c_channel_flags & IEEE80211_CHAN_TURBO) == 0) { - rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_11B); - for (i = 0; i < rt->rt_rate_count; i++) { - data = AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code); + if ((channel->channel_flags & CHANNEL_TURBO) == 0) { + rt = ar5k_ar5212_get_rate_table(hal, AR5K_MODE_11B); + for (i = 0; i < rt->rate_count; i++) { + data = AR5K_AR5212_RATE_DUR(rt->rates[i].rate_code); AR5K_REG_WRITE(data, ath_hal_computetxtime(hal, rt, 14, - rt->rt_info[i].r_control_rate, AH_FALSE)); - if (rt->rt_info[i].r_short_preamble) { + rt->rates[i].control_rate, FALSE)); + if (HAS_SHPREAMBLE(i)) { AR5K_REG_WRITE(data + - (rt->rt_info[i].r_short_preamble << 2), + (AR5K_SET_SHORT_PREAMBLE << 2), ath_hal_computetxtime(hal, rt, 14, - rt->rt_info[i].r_control_rate, AH_FALSE)); + rt->rates[i].control_rate, FALSE)); } } } @@ -623,7 +622,7 @@ hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { AR5K_REG_WRITE(AR5K_AR5212_PHY_CCKTXCTL, AR5K_AR5212_PHY_CCKTXCTL_WORLD); - if (channel->c_channel_flags & IEEE80211_CHAN_OFDM) + if (channel->channel_flags & CHANNEL_OFDM) data = 0xffb81020; else data = 0xffb80d20; @@ -634,17 +633,17 @@ * Set TX power (XXX use txpower from net80211) */ if (ar5k_ar5212_txpower(hal, channel, - AR5K_TUNE_DEFAULT_TXPOWER) == AH_FALSE) { - *status = HAL_EIO; - return (AH_FALSE); + AR5K_TUNE_DEFAULT_TXPOWER) == FALSE) { + *status = AR5K_EIO; + return (FALSE); } /* * Write RF registers */ - if (ar5k_rfregs(hal, channel, mode) == AH_FALSE) { - *status = HAL_EINPROGRESS; - return (AH_FALSE); + if (ar5k_rfregs(hal, channel, mode) == FALSE) { + *status = AR5K_EINPROGRESS; + return (FALSE); } /* @@ -652,20 +651,20 @@ */ /* OFDM timings */ - if (channel->c_channel_flags & IEEE80211_CHAN_OFDM) { + if (channel->channel_flags & CHANNEL_OFDM) { u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man, clock; - clock = channel->c_channel_flags & IEEE80211_CHAN_T ? 80 : 40; - coef_scaled = ((5 * (clock << 24)) / 2) / channel->c_channel; + clock = channel->channel_flags & CHANNEL_T ? 80 : 40; + coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; for (coef_exp = 31; coef_exp > 0; coef_exp--) if ((coef_scaled >> coef_exp) & 0x1) break; if (!coef_exp) { - *status = HAL_EINVAL; - return (AH_FALSE); + *status = AR5K_EINVAL; + return (FALSE); } coef_exp = 14 - (coef_exp - 24); @@ -680,7 +679,7 @@ } if (hal->ah_radio == AR5K_AR5111) { - if (channel->c_channel_flags & IEEE80211_CHAN_B) + if (channel->channel_flags & CHANNEL_B) AR5K_REG_ENABLE_BITS(AR5K_AR5212_TXCFG, AR5K_AR5212_TXCFG_B_MODE); else @@ -693,9 +692,9 @@ hal->ah_antenna[ee_mode][0], 0xfffffc06); if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] = HAL_ANT_FIXED_B; + ant[0] = ant[1] = AR5K_ANT_FIXED_B; else - ant[0] = ant[1] = HAL_ANT_FIXED_A; + ant[0] = ant[1] = AR5K_ANT_FIXED_A; AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0, @@ -771,9 +770,9 @@ /* * Set channel and calibrate the PHY */ - if (ar5k_channel(hal, channel) == AH_FALSE) { - *status = HAL_EIO; - return (AH_FALSE); + if (ar5k_channel(hal, channel) == FALSE) { + *status = AR5K_EIO; + return (FALSE); } /* @@ -783,7 +782,7 @@ data = AR5K_REG_READ(AR5K_AR5212_PHY_RX_DELAY) & AR5K_AR5212_PHY_RX_DELAY_M; - data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? + data = (channel->channel_flags & CHANNEL_CCK) ? ((data << 2) / 22) : (data / 10); AR5K_DELAY(100 + data); @@ -796,9 +795,9 @@ AR5K_AR5212_PHY_AGCCTL_CAL); - hal->ah_calibration = AH_FALSE; - if ((channel->c_channel_flags & IEEE80211_CHAN_B) == 0) { - hal->ah_calibration = AH_TRUE; + hal->ah_calibration = FALSE; + if ((channel->channel_flags & CHANNEL_B) == 0) { + hal->ah_calibration = TRUE; AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_IQ, AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX, 15); AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, @@ -810,15 +809,15 @@ */ for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { AR5K_REG_WRITE_Q(AR5K_AR5212_DCU_QCUMASK(i), i); - if (ar5k_ar5212_reset_tx_queue(hal, i) == AH_FALSE) { + if (ar5k_ar5212_reset_tx_queue(hal, i) == FALSE) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); - *status = HAL_EINVAL; - return (AH_FALSE); + *status = AR5K_EINVAL; + return (FALSE); } } /* Pre-enable interrupts */ - ar5k_ar5212_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); + ar5k_ar5212_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); /* * Set RF kill flags if supported by the device (read from the EEPROM) @@ -849,7 +848,7 @@ AR5K_REG_DISABLE_BITS(AR5K_AR5212_BEACON, AR5K_AR5212_BEACON_ENABLE | AR5K_AR5212_BEACON_RESET_TSF); - return (AH_TRUE); + return (TRUE); } void /*New*/ @@ -879,18 +878,18 @@ AR5K_TRACE; switch (hal->ah_op_mode) { - case IEEE80211_M_IBSS: + case AR5K_M_IBSS: pcu_reg |= AR5K_AR5212_STA_ID1_ADHOC | AR5K_AR5212_STA_ID1_DESC_ANTENNA; break; - case IEEE80211_M_HOSTAP: + case AR5K_M_HOSTAP: pcu_reg |= AR5K_AR5212_STA_ID1_AP | AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA; break; - case IEEE80211_M_STA: - case IEEE80211_M_MONITOR: + case AR5K_M_STA: + case AR5K_M_MONITOR: pcu_reg |= AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; break; @@ -917,18 +916,18 @@ return; } -HAL_BOOL /*O.K.*/ -ar5k_ar5212_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) +AR5K_BOOL /*O.K.*/ +ar5k_ar5212_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int32_t i_pwr, q_pwr; int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; AR5K_TRACE; - if (hal->ah_calibration == AH_FALSE || + if (hal->ah_calibration == FALSE || AR5K_REG_READ(AR5K_AR5212_PHY_IQ) & AR5K_AR5212_PHY_IQ_RUN) goto done; - hal->ah_calibration = AH_FALSE; + hal->ah_calibration = FALSE; iq_corr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_CORR); i_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_I); @@ -954,37 +953,37 @@ AR5K_AR5212_PHY_AGCCTL_NF); /* Request RF gain */ - if (channel->c_channel_flags & IEEE80211_CHAN_5GHZ) { + if (channel->channel_flags & CHANNEL_5GHZ) { AR5K_REG_WRITE(AR5K_AR5212_PHY_PAPD_PROBE, AR5K_REG_SM(hal->ah_txpower.txp_max, AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER) | AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT); - hal->ah_rf_gain = HAL_RFGAIN_READ_REQUESTED; + hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } - return (AH_TRUE); + return (TRUE); } /* * Transmit functions */ -HAL_BOOL /*O.K.*/ -ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) +AR5K_BOOL /*O.K.*/ +ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) { u_int32_t trigger_level, imr; - HAL_BOOL status = AH_FALSE; + AR5K_BOOL status = FALSE; AR5K_TRACE; /* * Disable interrupts by setting the mask */ - imr = ar5k_ar5212_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); + imr = ar5k_ar5212_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TXCFG), AR5K_AR5212_TXCFG_TXFULL); - if (increase == AH_FALSE) { + if (increase == FALSE) { if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) goto done; } else @@ -996,7 +995,7 @@ */ AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, AR5K_AR5212_TXCFG_TXFULL, trigger_level); - status = AH_TRUE; + status = TRUE; done: /* @@ -1008,8 +1007,8 @@ } int /*O.K.*/ -ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, - HAL_TXQ_INFO *queue_info) +ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, + AR5K_TXQ_INFO *queue_info) { u_int queue; AR5K_TRACE; @@ -1017,31 +1016,31 @@ /* * Get queue by type */ - if (queue_type == HAL_TX_QUEUE_DATA) { - for (queue = HAL_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; + if (queue_type == AR5K_TX_QUEUE_DATA) { + for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; + hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; queue++) - if (queue > HAL_TX_QUEUE_ID_DATA_MAX) + if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) return (-1); - } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { - queue = HAL_TX_QUEUE_ID_PSPOLL; - } else if (queue_type == HAL_TX_QUEUE_BEACON) { - queue = HAL_TX_QUEUE_ID_BEACON; - } else if (queue_type == HAL_TX_QUEUE_CAB) { - queue = HAL_TX_QUEUE_ID_CAB; + } else if (queue_type == AR5K_TX_QUEUE_UAPSD) { + queue = AR5K_TX_QUEUE_ID_UAPSD; + } else if (queue_type == AR5K_TX_QUEUE_BEACON) { + queue = AR5K_TX_QUEUE_ID_BEACON; + } else if (queue_type == AR5K_TX_QUEUE_CAB) { + queue = AR5K_TX_QUEUE_ID_CAB; } else return (-1); /* * Setup internal queue structure */ - bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); + bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); hal->ah_txq[queue].tqi_type = queue_type; if (queue_info != NULL) { queue_info->tqi_type = queue_type; if (ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info) - != AH_TRUE) + != TRUE) return (-1); } @@ -1050,63 +1049,62 @@ return (queue); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_setup_tx_queueprops(struct ath_hal *hal, int queue, - const HAL_TXQ_INFO *queue_info) + const AR5K_TXQ_INFO *queue_info) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) - return (AH_FALSE); + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (FALSE); - bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); + bcopy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && - (queue_info->tqi_subtype >= HAL_WME_AC_VI) && - (queue_info->tqi_subtype <= HAL_WME_UPSD)) + if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && + ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || + (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || + queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) hal->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*New*/ -ar5k_ar5212_get_tx_queueprops(struct ath_hal *hal, int queue, HAL_TXQ_INFO *queue_info) +AR5K_BOOL /*New*/ +ar5k_ar5212_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) { AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); - return (AH_TRUE); + memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + return (TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_release_tx_queue(struct ath_hal *hal, u_int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* This queue will be skipped in further operations */ - hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; + hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - return (AH_FALSE); /*???*/ + return (FALSE); /*???*/ } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue) { u_int32_t cw_min, cw_max, retry_lg, retry_sh; - struct ieee80211_channel *channel = (struct ieee80211_channel*) - &hal->ah_current_channel; - HAL_TXQ_INFO *tq; + AR5K_TXQ_INFO *tq; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); tq = &hal->ah_txq[queue]; - if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) - return (AH_TRUE); + if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (TRUE); /* * Set registers by channel mode @@ -1114,11 +1112,11 @@ cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; hal->ah_aifs = AR5K_TUNE_AIFS; - if (IEEE80211_IS_CHAN_XR(channel)) { + if (IS_CHAN_XR(hal->ah_current_channel)) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; hal->ah_aifs = AR5K_TUNE_AIFS_XR; - } else if (IEEE80211_IS_CHAN_B(channel)) { + } else if (IS_CHAN_B(hal->ah_current_channel)) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; hal->ah_aifs = AR5K_TUNE_AIFS_11B; @@ -1127,7 +1125,7 @@ /* * Set retry limits */ - if (hal->ah_software_retry == AH_TRUE) { + if (hal->ah_software_retry == TRUE) { /* XXX Need to test this */ retry_lg = hal->ah_limit_tx_retries; retry_sh = retry_lg = @@ -1219,7 +1217,7 @@ * Set registers by queue type */ switch (tq->tqi_type) { - case HAL_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_BEACON: AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | AR5K_AR5212_QCU_MISC_CBREXP_BCN | @@ -1238,7 +1236,7 @@ AR5K_AR5212_QCU_RDYTIMECFG_ENABLE); break; - case HAL_TX_QUEUE_CAB: + case AR5K_TX_QUEUE_CAB: AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | AR5K_AR5212_QCU_MISC_CBREXP | @@ -1249,12 +1247,12 @@ AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL)); break; - case HAL_TX_QUEUE_PSPOLL: + case AR5K_TX_QUEUE_UAPSD: AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_AR5212_QCU_MISC_CBREXP); break; - case HAL_TX_QUEUE_DATA: + case AR5K_TX_QUEUE_DATA: default: break; } @@ -1270,7 +1268,7 @@ AR5K_REG_WRITE(AR5K_AR5212_SIMR2, AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN)); - return (AH_TRUE); + return (TRUE); } u_int32_t /*O.K.*/ @@ -1285,7 +1283,7 @@ return (AR5K_REG_READ(AR5K_AR5212_QCU_TXDP(queue))); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) { AR5K_TRACE; @@ -1296,11 +1294,11 @@ * (this won't work if the queue is still active) */ if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, queue)) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5212_QCU_TXDP(queue), phys_addr); - return (AH_TRUE); + return (TRUE); } u_int32_t /*Code from roofnet*/ @@ -1310,7 +1308,7 @@ return (AR5K_AR5212_QCU_STS(queue) & AR5K_AR5212_QCU_STS_FRMPENDCNT); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_tx_start(struct ath_hal *hal, u_int queue) { AR5K_TRACE; @@ -1318,15 +1316,15 @@ /* Return if queue is disabled */ if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXD, queue)) - return (AH_FALSE); + return (FALSE); /* Start queue */ AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXE, queue); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*Fixed delay*/ +AR5K_BOOL /*Fixed delay*/ ar5k_ar5212_stop_tx_dma(struct ath_hal *hal, u_int queue) { int i = 100, pending; @@ -1348,12 +1346,12 @@ /* Clear register */ AR5K_REG_WRITE(AR5K_AR5212_QCU_TXD, 0); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K. - Initialize tx_desc */ +AR5K_BOOL /*O.K. - Initialize tx_desc */ ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, + u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { @@ -1367,7 +1365,7 @@ * Validate input */ if (tx_tries0 == 0) - return (AH_FALSE); + return (FALSE); /* Initialize status descriptor */ tx_desc->tx_control_0 = 0; @@ -1379,7 +1377,7 @@ if ((tx_desc->tx_control_0 = (packet_length & AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length) - return (AH_FALSE); + return (FALSE); tx_desc->tx_control_0 |= AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) | @@ -1393,7 +1391,7 @@ tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; #define _TX_FLAGS(_c, _flag) \ - if (flags & HAL_TXDESC_##_flag) \ + if (flags & AR5K_TXDESC_##_flag) \ tx_desc->tx_control_##_c |= \ AR5K_AR5212_DESC_TX_CTL##_c##_##_flag @@ -1409,7 +1407,7 @@ /* * WEP crap */ - if (key_index != HAL_TXKEYIX_INVALID) { + if (key_index != AR5K_TXKEYIX_INVALID) { tx_desc->tx_control_0 |= AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID; tx_desc->tx_control_1 |= @@ -1420,10 +1418,10 @@ /* * RTS/CTS */ - if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { - if ((flags & HAL_TXDESC_RTSENA) && - (flags & HAL_TXDESC_CTSENA)) - return (AH_FALSE); + if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { + if ((flags & AR5K_TXDESC_RTSENA) && + (flags & AR5K_TXDESC_CTSENA)) + return (FALSE); tx_desc->tx_control_2 |= rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION; tx_desc->tx_control_3 |= @@ -1431,12 +1429,12 @@ AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*Added an argument *last_desc -need revision -don't clear descriptor here*/ +AR5K_BOOL /*Added an argument *last_desc -need revision -don't clear descriptor here*/ ar5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment, const struct ath_desc *last_desc) + u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) { struct ar5k_ar5212_tx_desc *tx_desc; struct ar5k_ar5212_tx_status *tx_status; @@ -1451,25 +1449,25 @@ /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & AR5K_AR5212_DESC_TX_CTL1_BUF_LEN)) != segment_length) - return (AH_FALSE); + return (FALSE); /*Code from roofnet*/ // if (segment_length> AR5K_AR5212_DESC_TX_CTL1_BUF_LEN){ -// return (AH_FALSE); +// return (FALSE); //} // tx_desc->tx_control_1 &= ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN; // tx_desc->tx_control_1 |= (segment_length & AR5K_AR5212_DESC_TX_CTL1_BUF_LEN); /* */ - if (first_segment != AH_TRUE) + if (first_segment != TRUE) tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN; - if (last_segment != AH_TRUE) + if (last_segment != TRUE) tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE; - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, u_int tx_rate3, u_int tx_tries3) @@ -1494,10 +1492,10 @@ #undef _XTX_TRIES - return (AH_TRUE); + return (TRUE); } -HAL_STATUS /*O.K.*/ +AR5K_STATUS /*O.K.*/ ar5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) { struct ar5k_ar5212_tx_status *tx_status; @@ -1509,7 +1507,7 @@ /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE) == 0) - return (HAL_EINPROGRESS); + return (AR5K_EINPROGRESS); /* * Get descriptor status @@ -1569,24 +1567,24 @@ AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { if (tx_status->tx_status_0 & AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; + desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; if (tx_status->tx_status_0 & AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; + desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; if (tx_status->tx_status_0 & AR5K_AR5212_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; + desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } - return (HAL_OK); + return (AR5K_OK); } -HAL_BOOL /*O.K. - needs revision (what about VEOL cap ?)*/ +AR5K_BOOL /*O.K. - needs revision (what about VEOL cap ?)*/ ar5k_ar5212_has_veol(struct ath_hal *hal) { - return (AH_TRUE); + return (TRUE); } void /*Unimplemented*/ @@ -1621,7 +1619,7 @@ AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_stop_rx_dma(struct ath_hal *hal) { int i; @@ -1637,7 +1635,7 @@ i--) AR5K_DELAY(10); - return (i > 0 ? AH_TRUE : AH_FALSE); + return (i > 0 ? TRUE : FALSE); } void /*O.K.*/ @@ -1664,13 +1662,13 @@ AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL1, filter1); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) { AR5K_TRACE; if (index >= 64) { - return (AH_FALSE); + return (FALSE); } else if (index >= 32) { AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL1, (1 << (index - 32))); @@ -1679,16 +1677,16 @@ (1 << index)); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) { AR5K_TRACE; if (index >= 64) { - return (AH_FALSE); + return (FALSE); } else if (index >= 32) { AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL1, (1 << (index - 32))); @@ -1697,7 +1695,7 @@ (1 << index)); } - return (AH_TRUE); + return (TRUE); } u_int32_t /*O.K.*/ @@ -1710,10 +1708,10 @@ data = AR5K_REG_READ(AR5K_AR5212_PHY_ERR_FIL); if (data & AR5K_AR5212_PHY_ERR_FIL_RADAR) - filter |= HAL_RX_FILTER_PHYRADAR; + filter |= AR5K_RX_FILTER_PHYRADAR; if (data & (AR5K_AR5212_PHY_ERR_FIL_OFDM | AR5K_AR5212_PHY_ERR_FIL_CCK)) - filter |= HAL_RX_FILTER_PHYERR; + filter |= AR5K_RX_FILTER_PHYERR; return (filter); } @@ -1724,14 +1722,14 @@ u_int32_t data = 0; AR5K_TRACE; - if (filter & HAL_RX_FILTER_PHYRADAR) + if (filter & AR5K_RX_FILTER_PHYRADAR) data |= AR5K_AR5212_PHY_ERR_FIL_RADAR; - if (filter & HAL_RX_FILTER_PHYERR) + if (filter & AR5K_RX_FILTER_PHYERR) data |= AR5K_AR5212_PHY_ERR_FIL_OFDM | AR5K_AR5212_PHY_ERR_FIL_CCK; /* Got that from roofnet*/ - data |= HAL_RX_FILTER_PROM | HAL_RX_FILTER_CONTROL; + data |= AR5K_RX_FILTER_PROM | AR5K_RX_FILTER_CONTROL; if (data) { AR5K_REG_ENABLE_BITS(AR5K_AR5212_RXCFG, @@ -1745,7 +1743,7 @@ AR5K_REG_WRITE(AR5K_AR5212_PHY_ERR_FIL, data); } -HAL_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ +AR5K_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ ar5k_ar5212_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t size, u_int flags) { @@ -1771,15 +1769,15 @@ if ((rx_desc->rx_control_1 = (size & AR5K_AR5212_DESC_RX_CTL1_BUF_LEN)) != size) - return (AH_FALSE); + return (FALSE); - if (flags & HAL_RXDESC_INTREQ) + if (flags & AR5K_RXDESC_INTREQ) rx_desc->rx_control_1 |= AR5K_AR5212_DESC_RX_CTL1_INTREQ; - return (AH_TRUE); + return (TRUE); } -HAL_STATUS /*O.K.*/ +AR5K_STATUS /*O.K.*/ ar5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int32_t phys_addr, struct ath_desc *next) { @@ -1794,7 +1792,7 @@ /* No frame received / not ready */ if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0) - return (HAL_EINPROGRESS); + return (AR5K_EINPROGRESS); /* * Frame receive status @@ -1825,7 +1823,7 @@ AR5K_REG_MS(rx_status->rx_status_1, AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX); } else { - desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; + desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; } /* @@ -1835,11 +1833,11 @@ AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { if (rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; + desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; if (rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) { - desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; + desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; desc->ds_us.rx.rs_phyerr = AR5K_REG_MS(rx_err->rx_error_1, AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE); @@ -1847,18 +1845,18 @@ if (rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; + desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; if (rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR) - desc->ds_us.rx.rs_status |= HAL_RXERR_MIC; + desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } - return (HAL_OK); + return (AR5K_OK); } -void /*Added HAL_NODE_STATS argument*/ -ar5k_ar5212_set_rx_signal(struct ath_hal *hal, const HAL_NODE_STATS *stats) +void /*Added AR5K_NODE_STATS argument*/ +ar5k_ar5212_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) { AR5K_TRACE; /* Signal state monitoring is not yet supported */ @@ -1972,7 +1970,7 @@ #endif } -HAL_BOOL /*Added arguments*/ +AR5K_BOOL /*Added arguments*/ ar5k_ar5212_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) { AR5K_TRACE; @@ -1980,7 +1978,7 @@ * We'll ignore this right now. This seems to be some kind of an obscure * debugging interface for the binary-only HAL. */ - return (AH_FALSE); + return (FALSE); } void /*O.K.*/ @@ -1990,7 +1988,7 @@ bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) { u_int32_t low_id, high_id; @@ -2006,30 +2004,30 @@ AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, high_id); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - HAL_STATUS *status) + AR5K_STATUS *status) { ieee80211_regdomain_t ieee_regdomain; ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); - if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, - &ieee_regdomain) == AH_TRUE) { - *status = HAL_OK; - return (AH_TRUE); + if (ar5k_eeprom_regulation_domain(hal, TRUE, + &ieee_regdomain) == TRUE) { + *status = AR5K_OK; + return (TRUE); } - *status = HAL_EIO; + *status = AR5K_EIO; - return (AH_FALSE); + return (FALSE); } void /*O.K.*/ -ar5k_ar5212_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) +ar5k_ar5212_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) { u_int32_t led; @@ -2041,19 +2039,19 @@ * Some blinking values, define at your wish */ switch (state) { - case IEEE80211_S_SCAN: - case IEEE80211_S_AUTH: + case AR5K_LED_SCAN: + case AR5K_LED_AUTH: led = AR5K_AR5212_PCICFG_LEDMODE_PROP | AR5K_AR5212_PCICFG_LED_PEND; break; - case IEEE80211_S_INIT: + case AR5K_LED_INIT: led = AR5K_AR5212_PCICFG_LEDMODE_PROP | AR5K_AR5212_PCICFG_LED_NONE; break; - case IEEE80211_S_ASSOC: - case IEEE80211_S_RUN: + case AR5K_LED_ASSOC: + case AR5K_LED_RUN: led = AR5K_AR5212_PCICFG_LEDMODE_PROP | AR5K_AR5212_PCICFG_LED_ASSOC; break; @@ -2105,32 +2103,32 @@ ar5k_ar5212_enable_pspoll(hal, NULL, 0); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; if (gpio > AR5K_AR5212_NUM_GPIO) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) | AR5K_AR5212_GPIOCR_ALL(gpio)); - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) { AR5K_TRACE; if (gpio > AR5K_AR5212_NUM_GPIO) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) | AR5K_AR5212_GPIOCR_NONE(gpio)); - return (AH_TRUE); + return (TRUE); } u_int32_t /*O.K.*/ @@ -2145,14 +2143,14 @@ AR5K_AR5212_GPIODI_M) >> gpio) & 0x1); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) { u_int32_t data; AR5K_TRACE; if (gpio > AR5K_AR5212_NUM_GPIO) - return (0xffffffff); + return (FALSE); /* GPIO output magic */ data = AR5K_REG_READ(AR5K_AR5212_GPIODO); @@ -2162,7 +2160,7 @@ AR5K_REG_WRITE(AR5K_AR5212_GPIODO, data); - return (AH_TRUE); + return (TRUE); } void /*O.K.*/ @@ -2223,7 +2221,7 @@ return (ar5k_get_regdomain(hal)); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_detect_card_present(struct ath_hal *hal) { u_int16_t magic; @@ -2234,13 +2232,13 @@ * way to do this. */ if (ar5k_ar5212_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (AH_FALSE); + return (FALSE); - return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); + return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); } void /*O.K.*/ -ar5k_ar5212_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) +ar5k_ar5212_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) { AR5K_TRACE; /* Read-And-Clear */ @@ -2258,22 +2256,22 @@ } void /*Unimplemented*/ -ar5k_ar5212_proc_mib_event(struct ath_hal *hal, const HAL_NODE_STATS *stats) +ar5k_ar5212_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) { AR5K_TRACE; return; } -HAL_RFGAIN /*O.K.*/ +AR5K_RFGAIN /*O.K.*/ ar5k_ar5212_get_rf_gain(struct ath_hal *hal) { u_int32_t data, type; AR5K_TRACE; if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active)) - return (HAL_RFGAIN_INACTIVE); + return (AR5K_RFGAIN_INACTIVE); - if (hal->ah_rf_gain != HAL_RFGAIN_READ_REQUESTED) + if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) goto done; data = AR5K_REG_READ(AR5K_AR5212_PHY_PAPD_PROBE); @@ -2297,23 +2295,23 @@ if (ar5k_rfregs_gain_readback(hal) && AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && ar5k_rfregs_gain_adjust(hal)) - hal->ah_rf_gain = HAL_RFGAIN_NEED_CHANGE; + hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE; } done: return (hal->ah_rf_gain); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_slot_time(struct ath_hal *hal, u_int slot_time) { AR5K_TRACE; - if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) - return (AH_FALSE); + if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) + return (FALSE); AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT, slot_time); - return (AH_TRUE); + return (TRUE); } u_int /*O.K.*/ @@ -2323,18 +2321,18 @@ return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_ack_timeout(struct ath_hal *hal, u_int timeout) { AR5K_TRACE; if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_ACK), hal->ah_turbo) <= timeout) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_ACK, ar5k_htoclock(timeout, hal->ah_turbo)); - return (AH_TRUE); + return (TRUE); } u_int /*O.K.*/ @@ -2345,18 +2343,18 @@ AR5K_AR5212_TIME_OUT_ACK), hal->ah_turbo)); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_cts_timeout(struct ath_hal *hal, u_int timeout) { AR5K_TRACE; if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_CTS), hal->ah_turbo) <= timeout) - return (AH_FALSE); + return (FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_CTS, ar5k_htoclock(timeout, hal->ah_turbo)); - return (AH_TRUE); + return (TRUE); } u_int /*O.K.*/ @@ -2367,80 +2365,78 @@ AR5K_AR5212_TIME_OUT_CTS), hal->ah_turbo)); } -HAL_STATUS /*New*/ -ar5k_ar5212_get_capability(struct ath_hal *hal, HAL_CAPABILITY_TYPE cap_type, +AR5K_STATUS /*New*/ +ar5k_ar5212_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, u_int32_t capability, u_int32_t *result) { AR5K_TRACE; switch (cap_type) { - case HAL_CAP_REG_DMN: + case AR5K_CAP_REG_DMN: if (result){ *result = ar5k_get_regdomain(hal); goto yes; } - case HAL_CAP_CIPHER: + case AR5K_CAP_CIPHER: switch (capability) { - case HAL_CIPHER_WEP: goto yes; + case AR5K_CIPHER_WEP: goto yes; default: goto no; } - case HAL_CAP_NUM_TXQUEUES: + case AR5K_CAP_NUM_TXQUEUES: if (result) { *result = AR5K_AR5212_TX_NUM_QUEUES; goto yes; } - case HAL_CAP_VEOL: + case AR5K_CAP_VEOL: goto yes; - case HAL_CAP_PSPOLL: - goto no; - case HAL_CAP_COMPRESSION: + case AR5K_CAP_COMPRESSION: goto yes; - case HAL_CAP_BURST: + case AR5K_CAP_BURST: goto yes; - case HAL_CAP_TPC: + case AR5K_CAP_TPC: goto yes; - case HAL_CAP_BSSIDMASK: + case AR5K_CAP_BSSIDMASK: goto yes; - case HAL_CAP_XR: + case AR5K_CAP_XR: goto yes; default: goto no; } no: - return (HAL_EINVAL); + return (AR5K_EINVAL); yes: - return HAL_OK; + return AR5K_OK; } -HAL_BOOL -ar5k_ar5212_set_capability(struct ath_hal *hal, HAL_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, HAL_STATUS *status) +AR5K_BOOL +ar5k_ar5212_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, + u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) { AR5K_TRACE; if (status) { - *status = HAL_OK; + *status = AR5K_OK; } - return (AH_FALSE); + return (FALSE); } /* * Key table (WEP) functions */ -HAL_BOOL /*O.K.*/ -ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) +AR5K_BOOL /*O.K.*/ +ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) { AR5K_TRACE; /* * The AR5212 only supports WEP */ - if (cipher == HAL_CIPHER_WEP) - return (AH_TRUE); + if (cipher == AR5K_CIPHER_WEP) + return (TRUE); - return (AH_FALSE); + return (FALSE); } u_int32_t /*O.K.*/ @@ -2450,7 +2446,7 @@ return (AR5K_AR5212_KEYCACHE_SIZE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_reset_key(struct ath_hal *hal, u_int16_t entry) { int i; @@ -2465,10 +2461,10 @@ AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_TYPE(entry), AR5K_AR5212_KEYTABLE_TYPE_NULL); - return (AH_FALSE); + return (FALSE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_is_key_valid(struct ath_hal *hal, u_int16_t entry) { AR5K_TRACE; @@ -2479,14 +2475,14 @@ */ if (AR5K_REG_READ(AR5K_AR5212_KEYTABLE_MAC1(entry)) & AR5K_AR5212_KEYTABLE_VALID) - return (AH_TRUE); + return (TRUE); - return (AH_FALSE); + return (FALSE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_set_key(struct ath_hal *hal, u_int16_t entry, - const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) + const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) { int i; u_int32_t key_v[AR5K_AR5212_KEYCACHE_SIZE - 2]; @@ -2523,7 +2519,7 @@ default: /* Unsupported key length (not WEP40/104/128) */ - return (AH_FALSE); + return (FALSE); } for (i = 0; i < AR5K_ELEMENTS(key_v); i++) @@ -2532,7 +2528,7 @@ return (ar5k_ar5212_set_key_lladdr(hal, entry, mac)); } -HAL_BOOL /*O.K. */ +AR5K_BOOL /*O.K. */ ar5k_ar5212_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, const u_int8_t *mac) { @@ -2555,16 +2551,16 @@ AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC1(entry), high_id); - return (AH_TRUE); + return (TRUE); } /* * Power management functions */ -HAL_BOOL /*O.K.*/ -ar5k_ar5212_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, - HAL_BOOL set_chip, u_int16_t sleep_duration) +AR5K_BOOL /*O.K.*/ +ar5k_ar5212_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, + AR5K_BOOL set_chip, u_int16_t sleep_duration) { u_int32_t staid; int i; @@ -2573,27 +2569,27 @@ staid = AR5K_REG_READ(AR5K_AR5212_STA_ID1); switch (mode) { - case HAL_PM_AUTO: + case AR5K_PM_AUTO: staid &= ~AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; /* fallthrough */ - case HAL_PM_NETWORK_SLEEP: - if (set_chip == AH_TRUE) { + case AR5K_PM_NETWORK_SLEEP: + if (set_chip == TRUE) { AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE | sleep_duration); } staid |= AR5K_AR5212_STA_ID1_PWR_SV; break; - case HAL_PM_FULL_SLEEP: - if (set_chip == AH_TRUE) { + case AR5K_PM_FULL_SLEEP: + if (set_chip == TRUE) { AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE_SLP); } staid |= AR5K_AR5212_STA_ID1_PWR_SV; break; - case HAL_PM_AWAKE: - if (set_chip == AH_FALSE) + case AR5K_PM_AWAKE: + if (set_chip == FALSE) goto commit; AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE_WAKE); @@ -2612,13 +2608,13 @@ /* Fail if the AR5212 didn't wake up */ if (i <= 0) - return (AH_FALSE); + return (FALSE); staid &= ~AR5K_AR5212_STA_ID1_PWR_SV; break; default: - return (AH_FALSE); + return (FALSE); } commit: @@ -2626,47 +2622,47 @@ AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, staid); - return (AH_TRUE); + return (TRUE); } -HAL_POWER_MODE /*O.K.*/ +AR5K_POWER_MODE /*O.K.*/ ar5k_ar5212_get_power_mode(struct ath_hal *hal) { AR5K_TRACE; return (hal->ah_power_mode); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_query_pspoll_support(struct ath_hal *hal) { AR5K_TRACE; /* nope */ - return (AH_FALSE); + return (FALSE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_init_pspoll(struct ath_hal *hal) { AR5K_TRACE; /* * Not used on the AR5212 */ - return (AH_FALSE); + return (FALSE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, u_int16_t assoc_id) { AR5K_TRACE; - return (AH_FALSE); + return (FALSE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_disable_pspoll(struct ath_hal *hal) { AR5K_TRACE; - return (AH_FALSE); + return (FALSE); } /* @@ -2684,7 +2680,7 @@ * Set the additional timers by mode */ switch (hal->ah_op_mode) { - case HAL_M_STA: + case AR5K_M_STA: timer1 = 0x0000ffff; timer2 = 0x0007ffff; break; @@ -2713,8 +2709,8 @@ AR5K_AR5212_BEACON_ENABLE)); } -void /*Removed arguments - should be changed through *state - review HAL_BEACON_STATE struct*/ -ar5k_ar5212_set_beacon_timers(struct ath_hal *hal, const HAL_BEACON_STATE *state) +void /*Removed arguments - should be changed through *state - review AR5K_BEACON_STATE struct*/ +ar5k_ar5212_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) { u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; @@ -2727,8 +2723,8 @@ if (state->bs_interval < 1) return; - interval = state->bs_intval; - dtim = state->bs_dtimperiod; + interval = state->bs_interval; + dtim = state->bs_dtim_period; /* * PCF support? @@ -2780,24 +2776,24 @@ /* * Set sleep registers */ - if ((state->bs_sleepduration > state->bs_interval) && - (roundup(state->bs_sleepduration, interval) == - state->bs_sleepduration)) - interval = state->bs_sleepduration; + if ((state->bs_sleep_duration > state->bs_interval) && + (roundup(state->bs_sleep_duration, interval) == + state->bs_sleep_duration)) + interval = state->bs_sleep_duration; - if (state->bs_sleepduration > dtim && - (dtim == 0 || roundup(state->bs_sleepduration, dtim) == - state->bs_sleepduration)) - dtim = state->bs_sleepduration; + if (state->bs_sleep_duration > dtim && + (dtim == 0 || roundup(state->bs_sleep_duration, dtim) == + state->bs_sleep_duration)) + dtim = state->bs_sleep_duration; if (interval > dtim) return; next_beacon = interval == dtim ? - state->bs_nextdtim: state->bs_nexttbtt; + state->bs_next_dtim: state->bs_next_beacon; AR5K_REG_WRITE(AR5K_AR5212_SLEEP0, - AR5K_REG_SM((state->bs_nextdtim - 3) << 3, + AR5K_REG_SM((state->bs_next_dtim - 3) << 3, AR5K_AR5212_SLEEP0_NEXT_DTIM) | AR5K_REG_SM(10, AR5K_AR5212_SLEEP0_CABTO) | AR5K_AR5212_SLEEP0_ENH_SLEEP_EN | @@ -2828,21 +2824,21 @@ AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_AR5212_BEACON_PERIOD); } -HAL_BOOL /*O.K.*/ -ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, HAL_BUS_ADDR phys_addr) +AR5K_BOOL /*O.K.*/ +ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) { - HAL_BOOL ret; + AR5K_BOOL ret; AR5K_TRACE; /* * Wait for beaconn queue to be done */ ret = ar5k_register_timeout(hal, - AR5K_AR5212_QCU_STS(HAL_TX_QUEUE_ID_BEACON), - AR5K_AR5212_QCU_STS_FRMPENDCNT, 0, AH_FALSE); + AR5K_AR5212_QCU_STS(AR5K_TX_QUEUE_ID_BEACON), + AR5K_AR5212_QCU_STS_FRMPENDCNT, 0, FALSE); - if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) - return (AH_FALSE); + if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) + return (FALSE); return (ret); } @@ -2851,14 +2847,14 @@ * Interrupt handling */ -HAL_BOOL +AR5K_BOOL ar5k_ar5212_is_intr_pending(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? AH_FALSE : AH_TRUE); + return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? FALSE : TRUE); } -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) { u_int32_t data; @@ -2872,34 +2868,34 @@ /* * Get abstract interrupt mask (HAL-compatible) */ - *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; + *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; - if (data == HAL_INT_NOCARD) - return (AH_FALSE); + if (data == AR5K_INT_NOCARD) + return (FALSE); if (data & (AR5K_AR5212_PISR_RXOK | AR5K_AR5212_PISR_RXERR)) - *interrupt_mask |= HAL_INT_RX; + *interrupt_mask |= AR5K_INT_RX; if (data & (AR5K_AR5212_PISR_TXOK | AR5K_AR5212_PISR_TXERR)) - *interrupt_mask |= HAL_INT_TX; + *interrupt_mask |= AR5K_INT_TX; if (data & (AR5K_AR5212_PISR_HIUERR)) - *interrupt_mask |= HAL_INT_FATAL; + *interrupt_mask |= AR5K_INT_FATAL; if (data & (AR5K_AR5212_PISR_BNR)) - *interrupt_mask |= HAL_INT_BNR; + *interrupt_mask |= AR5K_INT_BNR; /* * Special interrupt handling (not caught by the driver) */ if (((*interrupt_mask) & AR5K_AR5212_PISR_RXPHY) && - hal->ah_radar.r_enabled == AH_TRUE) + hal->ah_radar.r_enabled == TRUE) ar5k_radar_alert(hal); if (*interrupt_mask == 0) AR5K_PRINTF("0x%08x\n", data); - return (AH_TRUE); + return (TRUE); } u_int32_t /*O.K.*/ @@ -2910,10 +2906,10 @@ return (hal->ah_imr); } -HAL_INT /*O.K.*/ -ar5k_ar5212_set_intr(struct ath_hal *hal, HAL_INT new_mask) +AR5K_INT /*O.K.*/ +ar5k_ar5212_set_intr(struct ath_hal *hal, AR5K_INT new_mask) { - HAL_INT old_mask, int_mask; + AR5K_INT old_mask, int_mask; /* * Disable card interrupts to prevent any race conditions @@ -2927,23 +2923,23 @@ * Add additional, chipset-dependent interrupt mask flags * and write them to the IMR (interrupt mask register). */ - int_mask = new_mask & HAL_INT_COMMON; + int_mask = new_mask & AR5K_INT_COMMON; - if (new_mask & HAL_INT_RX) + if (new_mask & AR5K_INT_RX) int_mask |= AR5K_AR5212_PIMR_RXOK | AR5K_AR5212_PIMR_RXERR | AR5K_AR5212_PIMR_RXORN | AR5K_AR5212_PIMR_RXDESC; - if (new_mask & HAL_INT_TX) + if (new_mask & AR5K_INT_TX) int_mask |= AR5K_AR5212_PIMR_TXOK | AR5K_AR5212_PIMR_TXERR | AR5K_AR5212_PIMR_TXDESC | AR5K_AR5212_PIMR_TXURN; - if (new_mask & HAL_INT_FATAL) { + if (new_mask & AR5K_INT_FATAL) { int_mask |= AR5K_AR5212_PIMR_HIUERR; AR5K_REG_ENABLE_BITS(AR5K_AR5212_SIMR2, AR5K_AR5212_SIMR2_MCABT | @@ -2966,7 +2962,7 @@ * Misc internal functions */ -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_get_capabilities(struct ath_hal *hal) { u_int16_t ee_header; @@ -2995,7 +2991,7 @@ /* Set supported modes */ hal->ah_capabilities.cap_mode = - HAL_MODE_11A | HAL_MODE_TURBO | HAL_MODE_XR; + AR5K_MODE_11A | AR5K_MODE_TURBO | AR5K_MODE_XR; } /* This chip will support 802.11b if the 2GHz radio is connected */ @@ -3004,10 +3000,10 @@ hal->ah_capabilities.cap_range.range_2ghz_max = 2732; if (AR5K_EEPROM_HDR_11B(ee_header)) - hal->ah_capabilities.cap_mode |= HAL_MODE_11B; + hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; #if 0 if (AR5K_EEPROM_HDR_11G(ee_header)) - hal->ah_capabilities.cap_mode |= HAL_MODE_11G; + hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; #endif } @@ -3017,11 +3013,11 @@ /* Set number of supported TX queues */ hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5212_TX_NUM_QUEUES; - return (AH_TRUE); + return (TRUE); } void /*O.K.*/ -ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable) +ar5k_ar5212_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) { AR5K_TRACE; @@ -3030,7 +3026,7 @@ */ AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); - if (enable == AH_TRUE) { + if (enable == TRUE) { AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, AR5K_AR5212_PHY_RADAR_ENABLE); AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, @@ -3049,12 +3045,12 @@ * EEPROM access functions */ -HAL_BOOL /*O.K.*/ +AR5K_BOOL /*O.K.*/ ar5k_ar5212_eeprom_is_busy(struct ath_hal *hal) { AR5K_TRACE; return (AR5K_REG_READ(AR5K_AR5212_CFG) & AR5K_AR5212_CFG_EEBS ? - AH_TRUE : AH_FALSE); + TRUE : FALSE); } int /*O.K.*/ @@ -3119,16 +3115,16 @@ * TX power setup */ -HAL_BOOL /*O.K.*/ -ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower) +AR5K_BOOL /*O.K.*/ +ar5k_ar5212_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower) { - HAL_BOOL tpc = hal->ah_txpower.txp_tpc; + AR5K_BOOL tpc = hal->ah_txpower.txp_tpc; int i; AR5K_TRACE; if (txpower > AR5K_TUNE_MAX_TXPOWER) { AR5K_PRINTF("invalid tx power: %u\n", txpower); - return (AH_FALSE); + return (FALSE); } /* Reset TX power values */ @@ -3164,7 +3160,7 @@ AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); - if (hal->ah_txpower.txp_tpc == AH_TRUE) { + if (hal->ah_txpower.txp_tpc == TRUE) { AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | AR5K_TUNE_MAX_TXPOWER); @@ -3174,14 +3170,14 @@ AR5K_TUNE_MAX_TXPOWER); } - return (AH_TRUE); + return (TRUE); } -HAL_BOOL /*New*/ +AR5K_BOOL /*New*/ ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int power) { /*Just a try M.F.*/ - HAL_CHANNEL *channel = &hal->ah_current_channel; + AR5K_CHANNEL *channel = &hal->ah_current_channel; AR5K_TRACE; AR5K_PRINTF("changing txpower to %d\n",power); Index: stack_net80211.h =================================================================== --- stack_net80211.h (revision 0) +++ stack_net80211.h (revision 1972) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + +/*net80211 definitions needed for use with madwifi*/ +#include +#include + +#define MAX_PDU_LENGTH IEEE80211_MAX_LEN +#define MODULATION_CCK IEEE80211_T_CCK +#define MODULATION_OFDM IEEE80211_T_OFDM +#define MODULATION_TURBO IEEE80211_T_TURBO +#define MODULATION_XR 7 /*XR thingie*/ +#define MODULATION_CCK_SP 8 /*CCK + Shortpreamble*/ + +#define AR5K_SET_SHORT_PREAMBLE 0x04 /* adding this flag to rate_code + enables short preamble, see ar5212_reg.h */ +#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == MODULATION_CCK_SP) +#define SHPREAMBLE_FLAG(_ix) HAS_SHPREAMBLE(_ix)?AR5K_SET_SHORT_PREAMBLE:0 + +typedef enum { + AR5K_M_STA = IEEE80211_M_STA, + AR5K_M_IBSS = IEEE80211_M_IBSS, + AR5K_M_HOSTAP = IEEE80211_M_HOSTAP, + AR5K_M_MONITOR = IEEE80211_M_MONITOR, +}AR5K_OPMODE; Index: ah_osdep.c =================================================================== --- ah_osdep.c (revision 1948) +++ ah_osdep.c (revision 1972) @@ -1,3 +1,25 @@ +/* + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + #include "ah.h" /*Definitions for module loading/unloading @@ -27,13 +49,13 @@ /*Attach/Dettach to HAL*/ struct ath_hal * -_ath_hal_attach(u_int16_t devid, HAL_SOFTC sc, - HAL_BUS_TAG t, HAL_BUS_HANDLE h, void* s) +_ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, + AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void* s) { - HAL_STATUS status; + AR5K_STATUS status; struct ath_hal *ah = ath_hal_attach(devid, sc, t, h, &status); - *(HAL_STATUS *)s = status; + *(AR5K_STATUS *)s = status; if (ah) AH_MOD_INC_USE_COUNT(THIS_MODULE); return ah; @@ -58,7 +80,7 @@ static int __init init_ath_hal(void) { - printk(KERN_INFO "%s: OpenHAL loaded (AR5210, AR5211, AR5212)\n", dev_info); + printk(KERN_INFO "%s: OpenHAL loaded (AR5210, AR5211, AR5212, RF5110/1/2)\n", dev_info); return (0); } module_init(init_ath_hal); Index: ah_osdep.h =================================================================== --- ah_osdep.h (revision 1948) +++ ah_osdep.h (revision 1972) @@ -1,3 +1,25 @@ +/* + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + #include #include #include @@ -16,12 +38,12 @@ #include -typedef void* HAL_SOFTC; -typedef int HAL_BUS_TAG; -typedef void* HAL_BUS_HANDLE; -typedef u_int32_t HAL_BUS_ADDR; -#define bus_space_tag_t HAL_BUS_TAG -#define bus_space_handle_t HAL_BUS_HANDLE +typedef void* AR5K_SOFTC; +typedef int AR5K_BUS_TAG; +typedef void* AR5K_BUS_HANDLE; +typedef u_int32_t AR5K_BUS_ADDR; +#define bus_space_tag_t AR5K_BUS_TAG +#define bus_space_handle_t AR5K_BUS_HANDLE //#define hz cpufreq_get(0) / 1000 //#define tick 1000000 / hz Index: ieee80211_regdomain.h =================================================================== --- ieee80211_regdomain.h (revision 1948) +++ ieee80211_regdomain.h (revision 1972) @@ -106,81 +106,81 @@ const char *rn_name; }; -#define IEEE80211_REGDOMAIN_NAMES { \ - { DMN_APL1, "APL1" }, \ - { DMN_APL1_APLA, "APL1A" }, \ - { DMN_APL1_ETSIC, "APL1_ETSIC" }, \ - { DMN_APL1_FCCA, "APL1_FCCA" }, \ - { DMN_APL1_WORLD, "APL1W" }, \ - { DMN_APL2, "APL2" }, \ - { DMN_APL2_APLC, "APL2C" }, \ - { DMN_APL2_APLD, "APL2D" }, \ - { DMN_APL2_ETSIC, "APL2_ETSIC" }, \ - { DMN_APL2_WORLD, "APL2W" }, \ - { DMN_APL3, "APL3" }, \ - { DMN_APL3_WORLD, "APL3W" }, \ - { DMN_APL4, "APL4" }, \ - { DMN_APL4_WORLD, "APL4W" }, \ - { DMN_APL5, "APL5" }, \ - { DMN_APL5_WORLD, "APL5W" }, \ - { DMN_APLD, "APLD" }, \ - { DMN_APL_NULL, "APL" }, \ - { DMN_DEBUG, "DEBUG" }, \ - { DMN_ETSI1, "ETSI1" }, \ - { DMN_ETSI1_WORLD, "ETSI1W" }, \ - { DMN_ETSI2, "ETSI2" }, \ - { DMN_ETSI2_WORLD, "ETSI2W" }, \ - { DMN_ETSI3, "ETSI3" }, \ - { DMN_ETSI3_ETSIA, "ETSI3A" }, \ - { DMN_ETSI3_WORLD, "ETSI3W," }, \ - { DMN_ETSI4, "ETSI4" }, \ - { DMN_ETSI4_ETSIC, "ETSI4C" }, \ - { DMN_ETSI4_WORLD, "ETSI4W" }, \ - { DMN_ETSI5, "ETSI5" }, \ - { DMN_ETSI5_WORLD, "ETSI5W" }, \ - { DMN_ETSI6, "ETSI6" }, \ - { DMN_ETSI6_WORLD, "ETSI6W" }, \ - { DMN_ETSIA, "ETSIA" }, \ - { DMN_ETSIB, "ETSIB" }, \ - { DMN_ETSIC, "ETSIC" }, \ - { DMN_ETSI_NULL, "ETSI" }, \ - { DMN_EU1_WORLD, "EU1W" }, \ - { DMN_FCC1, "FCC1" }, \ - { DMN_FCC1_FCCA, "FCC1A" }, \ - { DMN_FCC1_WORLD, "FCC1W" }, \ - { DMN_FCC2, "FCC2" }, \ - { DMN_FCC2_ETSIC, "FCC2C" }, \ - { DMN_FCC2_FCCA, "FCC2A" }, \ - { DMN_FCC2_WORLD, "FCC2W" }, \ - { DMN_FCC3, "FCC3" }, \ - { DMN_FCC3_FCCA, "FCC3A" }, \ - { DMN_FCCA, "FCCA" }, \ - { DMN_FRANCE_NULL, "FRANCE" }, \ - { DMN_MKK1, "MKK1" }, \ - { DMN_MKK1_FCCA, "MKK1_FCCA" }, \ - { DMN_MKK1_MKKA, "MKK1A" }, \ - { DMN_MKK1_MKKA1, "MKK1A1" }, \ - { DMN_MKK1_MKKA2, "MKK1A2" }, \ - { DMN_MKK1_MKKB, "MKK1B" }, \ - { DMN_MKK2, "MKK2" }, \ - { DMN_MKK2_MKKA, "MKK2A" }, \ - { DMN_MKKA, "MKKA" }, \ - { DMN_DEFAULT, "NONE" }, \ - { DMN_NULL, "NONE" }, \ - { DMN_NULL_ETSIB, "ETSIB" }, \ - { DMN_NULL_ETSIC, "ETSIC" }, \ - { DMN_WOR01_WORLD, "WOR01W" }, \ - { DMN_WOR02_WORLD, "WOR02W" }, \ - { DMN_WOR0_WORLD, "WOR0W" }, \ - { DMN_WOR1_WORLD, "WOR1W" }, \ - { DMN_WOR2_WORLD, "WOR2W" }, \ - { DMN_WOR3_WORLD, "WOR3W" }, \ - { DMN_WOR4_WORLD, "WOR4W" }, \ - { DMN_WOR5_ETSIC, "WOR5_ETSIC" }, \ - { DMN_WOR9_WORLD, "WOR9W" }, \ - { DMN_WORA_WORLD, "WORAW" }, \ - { DMN_NULL_WORLD, "WORLD" }, \ - { DMN_WORLD, "WORLD" } \ +#define IEEE80211_REGDOMAIN_NAMES { \ + { DMN_APL1, "APL1" }, \ + { DMN_APL1_APLA, "APL1A" }, \ + { DMN_APL1_ETSIC, "APL1_ETSIC" }, \ + { DMN_APL1_FCCA, "APL1_FCCA" }, \ + { DMN_APL1_WORLD, "APL1W" }, \ + { DMN_APL2, "APL2" }, \ + { DMN_APL2_APLC, "APL2C" }, \ + { DMN_APL2_APLD, "APL2D" }, \ + { DMN_APL2_ETSIC, "APL2_ETSIC" }, \ + { DMN_APL2_WORLD, "APL2W" }, \ + { DMN_APL3, "APL3" }, \ + { DMN_APL3_WORLD, "APL3W" }, \ + { DMN_APL4, "APL4" }, \ + { DMN_APL4_WORLD, "APL4W" }, \ + { DMN_APL5, "APL5" }, \ + { DMN_APL5_WORLD, "APL5W" }, \ + { DMN_APLD, "APLD" }, \ + { DMN_APL_NULL, "APL" }, \ + { DMN_DEBUG, "DEBUG" }, \ + { DMN_ETSI1, "ETSI1" }, \ + { DMN_ETSI1_WORLD, "ETSI1W" }, \ + { DMN_ETSI2, "ETSI2" }, \ + { DMN_ETSI2_WORLD, "ETSI2W" }, \ + { DMN_ETSI3, "ETSI3" }, \ + { DMN_ETSI3_ETSIA, "ETSI3A" }, \ + { DMN_ETSI3_WORLD, "ETSI3W," }, \ + { DMN_ETSI4, "ETSI4" }, \ + { DMN_ETSI4_ETSIC, "ETSI4C" }, \ + { DMN_ETSI4_WORLD, "ETSI4W" }, \ + { DMN_ETSI5, "ETSI5" }, \ + { DMN_ETSI5_WORLD, "ETSI5W" }, \ + { DMN_ETSI6, "ETSI6" }, \ + { DMN_ETSI6_WORLD, "ETSI6W" }, \ + { DMN_ETSIA, "ETSIA" }, \ + { DMN_ETSIB, "ETSIB" }, \ + { DMN_ETSIC, "ETSIC" }, \ + { DMN_ETSI_NULL, "ETSI" }, \ + { DMN_EU1_WORLD, "EU1W" }, \ + { DMN_FCC1, "FCC1" }, \ + { DMN_FCC1_FCCA, "FCC1A" }, \ + { DMN_FCC1_WORLD, "FCC1W" }, \ + { DMN_FCC2, "FCC2" }, \ + { DMN_FCC2_ETSIC, "FCC2C" }, \ + { DMN_FCC2_FCCA, "FCC2A" }, \ + { DMN_FCC2_WORLD, "FCC2W" }, \ + { DMN_FCC3, "FCC3" }, \ + { DMN_FCC3_FCCA, "FCC3A" }, \ + { DMN_FCCA, "FCCA" }, \ + { DMN_FRANCE_NULL, "FRANCE" }, \ + { DMN_MKK1, "MKK1" }, \ + { DMN_MKK1_FCCA, "MKK1_FCCA" }, \ + { DMN_MKK1_MKKA, "MKK1A" }, \ + { DMN_MKK1_MKKA1, "MKK1A1" }, \ + { DMN_MKK1_MKKA2, "MKK1A2" }, \ + { DMN_MKK1_MKKB, "MKK1B" }, \ + { DMN_MKK2, "MKK2" }, \ + { DMN_MKK2_MKKA, "MKK2A" }, \ + { DMN_MKKA, "MKKA" }, \ + { DMN_DEFAULT, "NONE" }, \ + { DMN_NULL, "NONE" }, \ + { DMN_NULL_ETSIB, "ETSIB" }, \ + { DMN_NULL_ETSIC, "ETSIC" }, \ + { DMN_WOR01_WORLD, "WOR01W" }, \ + { DMN_WOR02_WORLD, "WOR02W" }, \ + { DMN_WOR0_WORLD, "WOR0W" }, \ + { DMN_WOR1_WORLD, "WOR1W" }, \ + { DMN_WOR2_WORLD, "WOR2W" }, \ + { DMN_WOR3_WORLD, "WOR3W" }, \ + { DMN_WOR4_WORLD, "WOR4W" }, \ + { DMN_WOR5_ETSIC, "WOR5_ETSIC" }, \ + { DMN_WOR9_WORLD, "WOR9W" }, \ + { DMN_WORA_WORLD, "WORAW" }, \ + { DMN_NULL_WORLD, "WORLD" }, \ + { DMN_WORLD, "WORLD" } \ } struct ieee80211_regdomainmap { @@ -189,56 +189,56 @@ u_int32_t rm_domain_2ghz; }; -#define IEEE80211_REGDOMAIN_MAP { \ - { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, \ - { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, \ - { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, \ - { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, \ - { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, \ - { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, \ - { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, \ - { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, \ - { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, \ - { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, \ - { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, \ - { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, \ - { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, \ - { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, \ - { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, \ - { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, \ - { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, \ - { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, \ - { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, \ - { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, \ - { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, \ - { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, \ - { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, \ - { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, \ - { DMN_APL_NULL, DMN_APL1, DMN_NULL }, \ - { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, \ - { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, \ - { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, \ - { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, \ - { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, \ - { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, \ - { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, \ - { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, \ - { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, \ - { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, \ - { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, \ - { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, \ - { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, \ - { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, \ - { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, \ - { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, \ +#define IEEE80211_REGDOMAIN_MAP { \ + { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG }, \ + { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD }, \ + { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB }, \ + { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC }, \ + { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA }, \ + { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD }, \ + { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA }, \ + { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD }, \ + { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC }, \ + { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 }, \ + { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD }, \ + { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD }, \ + { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD }, \ + { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD }, \ + { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD }, \ + { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD }, \ + { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC }, \ + { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD }, \ + { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD }, \ + { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 }, \ + { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA }, \ + { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA }, \ + { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD }, \ + { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA }, \ + { DMN_APL_NULL, DMN_APL1, DMN_NULL }, \ + { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD }, \ + { DMN_APL2_APLC, DMN_APL2, DMN_WORLD }, \ + { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD }, \ + { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA }, \ + { DMN_APL2_APLD, DMN_APL2, DMN_APLD }, \ + { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA }, \ + { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA }, \ + { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD }, \ + { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA }, \ + { DMN_APL1_APLA, DMN_APL1, DMN_WORLD }, \ + { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC }, \ + { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC }, \ + { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD }, \ + { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD }, \ + { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD }, \ + { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD }, \ + { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD }, \ } enum ieee80211_countrycode { @@ -366,123 +366,123 @@ u_int32_t cn_domain; }; -#define IEEE80211_REGDOMAIN_COUNTRY_NAMES { \ - { CTRY_DEFAULT, "00", DMN_DEFAULT }, \ - { CTRY_UAE, "ae", DMN_NULL_WORLD }, \ - { CTRY_ALBANIA, "al", DMN_NULL_WORLD }, \ - { CTRY_ARMENIA, "am", DMN_ETSI4_WORLD }, \ - { CTRY_ARGENTINA, "ar", DMN_APL3_WORLD }, \ - { CTRY_AUSTRIA, "at", DMN_ETSI5_WORLD }, \ - { CTRY_AUSTRALIA, "au", DMN_FCC2_WORLD }, \ - { CTRY_AZERBAIJAN, "az", DMN_ETSI4_WORLD }, \ - { CTRY_BELGIUM, "be", DMN_ETSI4_WORLD }, \ - { CTRY_BULGARIA, "bg", DMN_ETSI6_WORLD }, \ - { CTRY_BAHRAIN, "bh", DMN_NULL_WORLD }, \ - { CTRY_BRUNEI_DARUSSALAM, "bn", DMN_APL1_WORLD }, \ - { CTRY_BOLIVIA, "bo", DMN_APL1_ETSIC }, \ - { CTRY_BRAZIL, "br", DMN_NULL_ETSIC }, \ - { CTRY_BELARUS, "by", DMN_NULL_WORLD }, \ - { CTRY_BELIZE, "bz", DMN_NULL_ETSIC }, \ - { CTRY_CANADA, "ca", DMN_FCC2_FCCA }, \ - { CTRY_SWITZERLAND, "ch", DMN_ETSI2_WORLD }, \ - { CTRY_CHILE, "cl", DMN_APL5_WORLD }, \ - { CTRY_CHINA, "cn", DMN_APL1_WORLD }, \ - { CTRY_COLOMBIA, "co", DMN_FCC1_FCCA }, \ - { CTRY_COSTA_RICA, "cr", DMN_NULL_WORLD }, \ - { CTRY_CYPRUS, "cy", DMN_ETSI1_WORLD }, \ - { CTRY_CZECH, "cz", DMN_ETSI3_WORLD }, \ - { CTRY_GERMANY, "de", DMN_ETSI1_WORLD }, \ - { CTRY_DENMARK, "dk", DMN_ETSI1_WORLD }, \ - { CTRY_DOMINICAN_REPUBLIC, "do", DMN_FCC1_FCCA }, \ - { CTRY_ALGERIA, "dz", DMN_NULL_WORLD }, \ - { CTRY_ECUADOR, "ec", DMN_NULL_WORLD }, \ - { CTRY_ESTONIA, "ee", DMN_ETSI1_WORLD }, \ - { CTRY_EGYPT, "eg", DMN_NULL_WORLD }, \ - { CTRY_SPAIN, "es", DMN_ETSI1_WORLD }, \ - { CTRY_FRANCE2, "f2", DMN_ETSI3_WORLD }, \ - { CTRY_FINLAND, "fi", DMN_ETSI1_WORLD }, \ - { CTRY_FAEROE_ISLANDS, "fo", DMN_NULL_WORLD }, \ - { CTRY_FRANCE, "fr", DMN_ETSI3_WORLD }, \ - { CTRY_GEORGIA, "ge", DMN_ETSI4_WORLD }, \ - { CTRY_GREECE, "gr", DMN_NULL_WORLD }, \ - { CTRY_GUATEMALA, "gt", DMN_FCC1_FCCA }, \ - { CTRY_HONG_KONG, "hk", DMN_FCC2_WORLD }, \ - { CTRY_HONDURAS, "hn", DMN_NULL_WORLD }, \ - { CTRY_CROATIA, "hr", DMN_ETSI3_WORLD }, \ - { CTRY_HUNGARY, "hu", DMN_ETSI2_WORLD }, \ - { CTRY_INDONESIA, "id", DMN_NULL_WORLD }, \ - { CTRY_IRELAND, "ie", DMN_ETSI1_WORLD }, \ - { CTRY_ISRAEL, "il", DMN_NULL_WORLD }, \ - { CTRY_INDIA, "in", DMN_NULL_WORLD }, \ - { CTRY_IRAQ, "iq", DMN_NULL_WORLD }, \ - { CTRY_IRAN, "ir", DMN_APL1_WORLD }, \ - { CTRY_ICELAND, "is", DMN_ETSI1_WORLD }, \ - { CTRY_ITALY, "it", DMN_ETSI1_WORLD }, \ - { CTRY_JAPAN1, "j1", DMN_MKK1_MKKB }, \ - { CTRY_JAPAN2, "j2", DMN_MKK1_FCCA }, \ - { CTRY_JAPAN3, "j3", DMN_MKK2_MKKA }, \ - { CTRY_JAPAN4, "j4", DMN_MKK1_MKKA1 }, \ - { CTRY_JAPAN5, "j5", DMN_MKK1_MKKA2 }, \ - { CTRY_JAMAICA, "jm", DMN_NULL_WORLD }, \ - { CTRY_JORDAN, "jo", DMN_NULL_WORLD }, \ - { CTRY_JAPAN, "jp", DMN_MKK1_MKKA }, \ - { CTRY_KOREA_ROC2, "k2", DMN_APL2_APLD }, \ - { CTRY_KENYA, "ke", DMN_NULL_WORLD }, \ - { CTRY_KOREA_NORTH, "kp", DMN_APL2_WORLD }, \ - { CTRY_KOREA_ROC, "kr", DMN_APL2_WORLD }, \ - { CTRY_KUWAIT, "kw", DMN_NULL_WORLD }, \ - { CTRY_KAZAKHSTAN, "kz", DMN_NULL_WORLD }, \ - { CTRY_LEBANON, "lb", DMN_NULL_WORLD }, \ - { CTRY_LIECHTENSTEIN, "li", DMN_ETSI2_WORLD }, \ - { CTRY_SRI_LANKA, "lk", DMN_NULL_WORLD }, \ - { CTRY_LITHUANIA, "lt", DMN_ETSI1_WORLD }, \ - { CTRY_LUXEMBOURG, "lu", DMN_ETSI1_WORLD }, \ - { CTRY_LATVIA, "lv", DMN_NULL_WORLD }, \ - { CTRY_LIBYA, "ly", DMN_NULL_WORLD }, \ - { CTRY_MOROCCO, "ma", DMN_NULL_WORLD }, \ - { CTRY_MONACO, "mc", DMN_ETSI4_WORLD }, \ - { CTRY_MACEDONIA, "mk", DMN_NULL_WORLD }, \ - { CTRY_MACAU, "mo", DMN_FCC2_WORLD }, \ - { CTRY_MEXICO, "mx", DMN_FCC1_FCCA }, \ - { CTRY_MALAYSIA, "my", DMN_NULL_WORLD }, \ - { CTRY_NICARAGUA, "ni", DMN_NULL_WORLD }, \ - { CTRY_NETHERLANDS, "nl", DMN_ETSI1_WORLD }, \ - { CTRY_NORWAY, "no", DMN_ETSI1_WORLD }, \ - { CTRY_NEW_ZEALAND, "nz", DMN_FCC2_ETSIC }, \ - { CTRY_OMAN, "om", DMN_NULL_WORLD }, \ - { CTRY_PANAMA, "pa", DMN_FCC1_FCCA }, \ - { CTRY_PERU, "pe", DMN_NULL_WORLD }, \ - { CTRY_PHILIPPINES, "ph", DMN_FCC1_WORLD }, \ - { CTRY_PAKISTAN, "pk", DMN_NULL_WORLD }, \ - { CTRY_POLAND, "pl", DMN_ETSI1_WORLD }, \ - { CTRY_PUERTO_RICO, "pr", DMN_FCC1_FCCA }, \ - { CTRY_PORTUGAL, "pt", DMN_ETSI1_WORLD }, \ - { CTRY_PARAGUAY, "py", DMN_NULL_WORLD }, \ - { CTRY_QATAR, "qa", DMN_NULL_WORLD }, \ - { CTRY_ROMANIA, "ro", DMN_NULL_WORLD }, \ - { CTRY_RUSSIA, "ru", DMN_NULL_WORLD }, \ - { CTRY_SAUDI_ARABIA, "sa", DMN_NULL_WORLD }, \ - { CTRY_SWEDEN, "se", DMN_ETSI1_WORLD }, \ - { CTRY_SINGAPORE, "sg", DMN_APL4_WORLD }, \ - { CTRY_SLOVENIA, "si", DMN_ETSI1_WORLD }, \ - { CTRY_SLOVAKIA, "sk", DMN_ETSI3_WORLD }, \ - { CTRY_EL_SALVADOR, "sv", DMN_NULL_WORLD }, \ - { CTRY_SYRIA, "sy", DMN_NULL_WORLD }, \ - { CTRY_THAILAND, "th", DMN_APL2_WORLD }, \ - { CTRY_TUNISIA, "tn", DMN_ETSI3_WORLD }, \ - { CTRY_TURKEY, "tr", DMN_ETSI3_WORLD }, \ - { CTRY_TRINIDAD_Y_TOBAGO, "tt", DMN_ETSI4_WORLD }, \ - { CTRY_TAIWAN, "tw", DMN_APL3_WORLD }, \ - { CTRY_UKRAINE, "ua", DMN_NULL_WORLD }, \ - { CTRY_UNITED_KINGDOM, "uk", DMN_ETSI1_WORLD }, \ - { CTRY_UNITED_STATES, "us", DMN_FCC1_FCCA }, \ - { CTRY_URUGUAY, "uy", DMN_APL2_WORLD }, \ - { CTRY_UZBEKISTAN, "uz", DMN_FCC3_FCCA }, \ - { CTRY_VENEZUELA, "ve", DMN_APL2_ETSIC }, \ - { CTRY_VIET_NAM, "vn", DMN_NULL_WORLD }, \ - { CTRY_YEMEN, "ye", DMN_NULL_WORLD }, \ - { CTRY_SOUTH_AFRICA, "za", DMN_ETSI1_WORLD }, \ - { CTRY_ZIMBABWE, "zw", DMN_NULL_WORLD }, \ +#define IEEE80211_REGDOMAIN_COUNTRY_NAMES { \ + { CTRY_DEFAULT, "00", DMN_DEFAULT }, \ + { CTRY_UAE, "ae", DMN_NULL_WORLD }, \ + { CTRY_ALBANIA, "al", DMN_NULL_WORLD }, \ + { CTRY_ARMENIA, "am", DMN_ETSI4_WORLD }, \ + { CTRY_ARGENTINA, "ar", DMN_APL3_WORLD }, \ + { CTRY_AUSTRIA, "at", DMN_ETSI5_WORLD }, \ + { CTRY_AUSTRALIA, "au", DMN_FCC2_WORLD }, \ + { CTRY_AZERBAIJAN, "az", DMN_ETSI4_WORLD }, \ + { CTRY_BELGIUM, "be", DMN_ETSI4_WORLD }, \ + { CTRY_BULGARIA, "bg", DMN_ETSI6_WORLD }, \ + { CTRY_BAHRAIN, "bh", DMN_NULL_WORLD }, \ + { CTRY_BRUNEI_DARUSSALAM, "bn", DMN_APL1_WORLD }, \ + { CTRY_BOLIVIA, "bo", DMN_APL1_ETSIC }, \ + { CTRY_BRAZIL, "br", DMN_NULL_ETSIC }, \ + { CTRY_BELARUS, "by", DMN_NULL_WORLD }, \ + { CTRY_BELIZE, "bz", DMN_NULL_ETSIC }, \ + { CTRY_CANADA, "ca", DMN_FCC2_FCCA }, \ + { CTRY_SWITZERLAND, "ch", DMN_ETSI2_WORLD }, \ + { CTRY_CHILE, "cl", DMN_APL5_WORLD }, \ + { CTRY_CHINA, "cn", DMN_APL1_WORLD }, \ + { CTRY_COLOMBIA, "co", DMN_FCC1_FCCA }, \ + { CTRY_COSTA_RICA, "cr", DMN_NULL_WORLD }, \ + { CTRY_CYPRUS, "cy", DMN_ETSI1_WORLD }, \ + { CTRY_CZECH, "cz", DMN_ETSI3_WORLD }, \ + { CTRY_GERMANY, "de", DMN_ETSI1_WORLD }, \ + { CTRY_DENMARK, "dk", DMN_ETSI1_WORLD }, \ + { CTRY_DOMINICAN_REPUBLIC, "do", DMN_FCC1_FCCA }, \ + { CTRY_ALGERIA, "dz", DMN_NULL_WORLD }, \ + { CTRY_ECUADOR, "ec", DMN_NULL_WORLD }, \ + { CTRY_ESTONIA, "ee", DMN_ETSI1_WORLD }, \ + { CTRY_EGYPT, "eg", DMN_NULL_WORLD }, \ + { CTRY_SPAIN, "es", DMN_ETSI1_WORLD }, \ + { CTRY_FRANCE2, "f2", DMN_ETSI3_WORLD }, \ + { CTRY_FINLAND, "fi", DMN_ETSI1_WORLD }, \ + { CTRY_FAEROE_ISLANDS, "fo", DMN_NULL_WORLD }, \ + { CTRY_FRANCE, "fr", DMN_ETSI3_WORLD }, \ + { CTRY_GEORGIA, "ge", DMN_ETSI4_WORLD }, \ + { CTRY_GREECE, "gr", DMN_NULL_WORLD }, \ + { CTRY_GUATEMALA, "gt", DMN_FCC1_FCCA }, \ + { CTRY_HONG_KONG, "hk", DMN_FCC2_WORLD }, \ + { CTRY_HONDURAS, "hn", DMN_NULL_WORLD }, \ + { CTRY_CROATIA, "hr", DMN_ETSI3_WORLD }, \ + { CTRY_HUNGARY, "hu", DMN_ETSI2_WORLD }, \ + { CTRY_INDONESIA, "id", DMN_NULL_WORLD }, \ + { CTRY_IRELAND, "ie", DMN_ETSI1_WORLD }, \ + { CTRY_ISRAEL, "il", DMN_NULL_WORLD }, \ + { CTRY_INDIA, "in", DMN_NULL_WORLD }, \ + { CTRY_IRAQ, "iq", DMN_NULL_WORLD }, \ + { CTRY_IRAN, "ir", DMN_APL1_WORLD }, \ + { CTRY_ICELAND, "is", DMN_ETSI1_WORLD }, \ + { CTRY_ITALY, "it", DMN_ETSI1_WORLD }, \ + { CTRY_JAPAN1, "j1", DMN_MKK1_MKKB }, \ + { CTRY_JAPAN2, "j2", DMN_MKK1_FCCA }, \ + { CTRY_JAPAN3, "j3", DMN_MKK2_MKKA }, \ + { CTRY_JAPAN4, "j4", DMN_MKK1_MKKA1 }, \ + { CTRY_JAPAN5, "j5", DMN_MKK1_MKKA2 }, \ + { CTRY_JAMAICA, "jm", DMN_NULL_WORLD }, \ + { CTRY_JORDAN, "jo", DMN_NULL_WORLD }, \ + { CTRY_JAPAN, "jp", DMN_MKK1_MKKA }, \ + { CTRY_KOREA_ROC2, "k2", DMN_APL2_APLD }, \ + { CTRY_KENYA, "ke", DMN_NULL_WORLD }, \ + { CTRY_KOREA_NORTH, "kp", DMN_APL2_WORLD }, \ + { CTRY_KOREA_ROC, "kr", DMN_APL2_WORLD }, \ + { CTRY_KUWAIT, "kw", DMN_NULL_WORLD }, \ + { CTRY_KAZAKHSTAN, "kz", DMN_NULL_WORLD }, \ + { CTRY_LEBANON, "lb", DMN_NULL_WORLD }, \ + { CTRY_LIECHTENSTEIN, "li", DMN_ETSI2_WORLD }, \ + { CTRY_SRI_LANKA, "lk", DMN_NULL_WORLD }, \ + { CTRY_LITHUANIA, "lt", DMN_ETSI1_WORLD }, \ + { CTRY_LUXEMBOURG, "lu", DMN_ETSI1_WORLD }, \ + { CTRY_LATVIA, "lv", DMN_NULL_WORLD }, \ + { CTRY_LIBYA, "ly", DMN_NULL_WORLD }, \ + { CTRY_MOROCCO, "ma", DMN_NULL_WORLD }, \ + { CTRY_MONACO, "mc", DMN_ETSI4_WORLD }, \ + { CTRY_MACEDONIA, "mk", DMN_NULL_WORLD }, \ + { CTRY_MACAU, "mo", DMN_FCC2_WORLD }, \ + { CTRY_MEXICO, "mx", DMN_FCC1_FCCA }, \ + { CTRY_MALAYSIA, "my", DMN_NULL_WORLD }, \ + { CTRY_NICARAGUA, "ni", DMN_NULL_WORLD }, \ + { CTRY_NETHERLANDS, "nl", DMN_ETSI1_WORLD }, \ + { CTRY_NORWAY, "no", DMN_ETSI1_WORLD }, \ + { CTRY_NEW_ZEALAND, "nz", DMN_FCC2_ETSIC }, \ + { CTRY_OMAN, "om", DMN_NULL_WORLD }, \ + { CTRY_PANAMA, "pa", DMN_FCC1_FCCA }, \ + { CTRY_PERU, "pe", DMN_NULL_WORLD }, \ + { CTRY_PHILIPPINES, "ph", DMN_FCC1_WORLD }, \ + { CTRY_PAKISTAN, "pk", DMN_NULL_WORLD }, \ + { CTRY_POLAND, "pl", DMN_ETSI1_WORLD }, \ + { CTRY_PUERTO_RICO, "pr", DMN_FCC1_FCCA }, \ + { CTRY_PORTUGAL, "pt", DMN_ETSI1_WORLD }, \ + { CTRY_PARAGUAY, "py", DMN_NULL_WORLD }, \ + { CTRY_QATAR, "qa", DMN_NULL_WORLD }, \ + { CTRY_ROMANIA, "ro", DMN_NULL_WORLD }, \ + { CTRY_RUSSIA, "ru", DMN_NULL_WORLD }, \ + { CTRY_SAUDI_ARABIA, "sa", DMN_NULL_WORLD }, \ + { CTRY_SWEDEN, "se", DMN_ETSI1_WORLD }, \ + { CTRY_SINGAPORE, "sg", DMN_APL4_WORLD }, \ + { CTRY_SLOVENIA, "si", DMN_ETSI1_WORLD }, \ + { CTRY_SLOVAKIA, "sk", DMN_ETSI3_WORLD }, \ + { CTRY_EL_SALVADOR, "sv", DMN_NULL_WORLD }, \ + { CTRY_SYRIA, "sy", DMN_NULL_WORLD }, \ + { CTRY_THAILAND, "th", DMN_APL2_WORLD }, \ + { CTRY_TUNISIA, "tn", DMN_ETSI3_WORLD }, \ + { CTRY_TURKEY, "tr", DMN_ETSI3_WORLD }, \ + { CTRY_TRINIDAD_Y_TOBAGO, "tt", DMN_ETSI4_WORLD }, \ + { CTRY_TAIWAN, "tw", DMN_APL3_WORLD }, \ + { CTRY_UKRAINE, "ua", DMN_NULL_WORLD }, \ + { CTRY_UNITED_KINGDOM, "uk", DMN_ETSI1_WORLD }, \ + { CTRY_UNITED_STATES, "us", DMN_FCC1_FCCA }, \ + { CTRY_URUGUAY, "uy", DMN_APL2_WORLD }, \ + { CTRY_UZBEKISTAN, "uz", DMN_FCC3_FCCA }, \ + { CTRY_VENEZUELA, "ve", DMN_APL2_ETSIC }, \ + { CTRY_VIET_NAM, "vn", DMN_NULL_WORLD }, \ + { CTRY_YEMEN, "ye", DMN_NULL_WORLD }, \ + { CTRY_SOUTH_AFRICA, "za", DMN_ETSI1_WORLD }, \ + { CTRY_ZIMBABWE, "zw", DMN_NULL_WORLD }, \ } enum ieee80211_ctl { @@ -507,269 +507,265 @@ }; #define IEEE80211_CHANNELS_2GHZ { \ - { 2412, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2417, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2422, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2427, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2432, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2437, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2442, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2447, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2452, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2457, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2462, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2467, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2472, DMN_APLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ + { 2412, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2417, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2422, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2427, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2432, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2437, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2442, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2447, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2452, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2457, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2462, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2467, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2472, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2432, DMN_ETSIB, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2437, DMN_ETSIB, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM| \ - IEEE80211_CHAN_TURBO }, \ - { 2442, DMN_ETSIB, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ + { 2432, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2437, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 2442, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2412, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2417, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2422, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2427, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2432, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2437, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM| \ - IEEE80211_CHAN_TURBO }, \ - { 2442, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2447, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2452, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2457, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2462, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2467, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2472, DMN_ETSIC, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ + { 2412, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2417, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2422, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2427, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2432, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2437, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 2442, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2447, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2452, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2457, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2462, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2467, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2472, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2412, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2417, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2422, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2427, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2432, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2437, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM| \ - IEEE80211_CHAN_TURBO }, \ - { 2442, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2447, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2452, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2457, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2462, DMN_FCCA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ + { 2412, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2417, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2422, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2427, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2432, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2437, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 2442, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2447, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2452, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2457, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2462, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \ \ - { 2412, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2417, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2422, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2427, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2432, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2437, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2442, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2447, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2452, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2457, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2462, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2467, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2472, DMN_MKKA, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2484, DMN_MKKA, IEEE80211_CHAN_CCK }, \ + { 2412, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2417, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2422, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2427, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2432, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2437, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2442, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2447, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2452, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2457, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2462, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2467, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2472, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2484, DMN_MKKA, CHANNEL_CCK }, \ \ - { 2412, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2417, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2422, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2427, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2432, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2437, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM| \ - IEEE80211_CHAN_TURBO }, \ - { 2442, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2447, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2452, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2457, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2462, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2467, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ - { 2472, DMN_WORLD, IEEE80211_CHAN_CCK|IEEE80211_CHAN_OFDM }, \ + { 2412, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2417, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2422, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2427, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2432, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2437, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 2442, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2447, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2452, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2457, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2462, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2467, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ + { 2472, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \ } #define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */ #define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */ -#define IEEE80211_CHANNELS_5GHZ { \ - { 5745, DMN_APL1, IEEE80211_CHAN_OFDM }, \ - { 5765, DMN_APL1, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_APL1, IEEE80211_CHAN_OFDM }, \ - { 5805, DMN_APL1, IEEE80211_CHAN_OFDM }, \ - { 5825, DMN_APL1, IEEE80211_CHAN_OFDM }, \ - \ - { 5745, DMN_APL2, IEEE80211_CHAN_OFDM }, \ - { 5765, DMN_APL2, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_APL2, IEEE80211_CHAN_OFDM }, \ - { 5805, DMN_APL2, IEEE80211_CHAN_OFDM }, \ - \ - { 5280, DMN_APL3, IEEE80211_CHAN_OFDM }, \ - { 5300, DMN_APL3, IEEE80211_CHAN_OFDM }, \ - { 5320, DMN_APL3, IEEE80211_CHAN_OFDM }, \ - { 5745, DMN_APL3, IEEE80211_CHAN_OFDM }, \ - { 5765, DMN_APL3, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_APL3, IEEE80211_CHAN_OFDM }, \ - { 5805, DMN_APL3, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5745, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5765, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5805, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - { 5825, DMN_APL4, IEEE80211_CHAN_OFDM }, \ - \ - { 5745, DMN_APL5, IEEE80211_CHAN_OFDM }, \ - { 5765, DMN_APL5, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_APL5, IEEE80211_CHAN_OFDM }, \ - { 5805, DMN_APL5, IEEE80211_CHAN_OFDM }, \ - { 5825, DMN_APL5, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5260, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5280, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5300, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5320, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5500, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5520, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5540, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5560, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5580, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5600, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5620, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5640, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5660, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5680, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - { 5700, DMN_ETSI1, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_ETSI2, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_ETSI2, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_ETSI2, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_ETSI2, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - { 5260, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - { 5280, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - { 5300, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - { 5320, DMN_ETSI3, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - { 5260, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - { 5280, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - { 5300, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - { 5320, DMN_ETSI4, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_ETSI5, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_ETSI5, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_ETSI5, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_ETSI5, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5260, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5280, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5500, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5520, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5540, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5560, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5580, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5600, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5620, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5640, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5660, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5680, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - { 5700, DMN_ETSI6, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5210, DMN_FCC1, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5220, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5250, DMN_FCC1, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5260, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5280, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5290, DMN_FCC1, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5300, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5320, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5745, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5760, DMN_FCC1, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5765, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5800, DMN_FCC1, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5805, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - { 5825, DMN_FCC1, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5260, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5280, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5300, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5320, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5745, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5765, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5805, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - { 5825, DMN_FCC2, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5210, DMN_FCC3, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5220, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5250, DMN_FCC3, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5260, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5280, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5290, DMN_FCC3, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5300, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5320, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5500, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5520, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5540, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5560, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5580, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5600, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5620, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5640, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5660, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5680, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5700, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5745, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5760, DMN_FCC3, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5765, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5785, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5800, DMN_FCC3, IEEE80211_CHAN_OFDM|IEEE80211_CHAN_TURBO }, \ - { 5805, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - { 5825, DMN_FCC3, IEEE80211_CHAN_OFDM }, \ - \ - { 5170, DMN_MKK1, IEEE80211_CHAN_OFDM }, \ - { 5190, DMN_MKK1, IEEE80211_CHAN_OFDM }, \ - { 5210, DMN_MKK1, IEEE80211_CHAN_OFDM }, \ - { 5230, DMN_MKK1, IEEE80211_CHAN_OFDM }, \ - \ - { 5040, DMN_MKK2, IEEE80211_CHAN_OFDM }, \ - { 5060, DMN_MKK2, IEEE80211_CHAN_OFDM }, \ - { 5080, DMN_MKK2, IEEE80211_CHAN_OFDM }, \ - { 5170, DMN_MKK2, IEEE80211_CHAN_OFDM }, \ - { 5190, DMN_MKK2, IEEE80211_CHAN_OFDM }, \ - { 5210, DMN_MKK2, IEEE80211_CHAN_OFDM }, \ - { 5230, DMN_MKK2, IEEE80211_CHAN_OFDM }, \ - \ - { 5180, DMN_WORLD, IEEE80211_CHAN_OFDM }, \ - { 5200, DMN_WORLD, IEEE80211_CHAN_OFDM }, \ - { 5220, DMN_WORLD, IEEE80211_CHAN_OFDM }, \ - { 5240, DMN_WORLD, IEEE80211_CHAN_OFDM }, \ +#define IEEE80211_CHANNELS_5GHZ { \ + { 5745, DMN_APL1, CHANNEL_OFDM }, \ + { 5765, DMN_APL1, CHANNEL_OFDM }, \ + { 5785, DMN_APL1, CHANNEL_OFDM }, \ + { 5805, DMN_APL1, CHANNEL_OFDM }, \ + { 5825, DMN_APL1, CHANNEL_OFDM }, \ + \ + { 5745, DMN_APL2, CHANNEL_OFDM }, \ + { 5765, DMN_APL2, CHANNEL_OFDM }, \ + { 5785, DMN_APL2, CHANNEL_OFDM }, \ + { 5805, DMN_APL2, CHANNEL_OFDM }, \ + \ + { 5280, DMN_APL3, CHANNEL_OFDM }, \ + { 5300, DMN_APL3, CHANNEL_OFDM }, \ + { 5320, DMN_APL3, CHANNEL_OFDM }, \ + { 5745, DMN_APL3, CHANNEL_OFDM }, \ + { 5765, DMN_APL3, CHANNEL_OFDM }, \ + { 5785, DMN_APL3, CHANNEL_OFDM }, \ + { 5805, DMN_APL3, CHANNEL_OFDM }, \ + \ + { 5180, DMN_APL4, CHANNEL_OFDM }, \ + { 5200, DMN_APL4, CHANNEL_OFDM }, \ + { 5220, DMN_APL4, CHANNEL_OFDM }, \ + { 5240, DMN_APL4, CHANNEL_OFDM }, \ + { 5745, DMN_APL4, CHANNEL_OFDM }, \ + { 5765, DMN_APL4, CHANNEL_OFDM }, \ + { 5785, DMN_APL4, CHANNEL_OFDM }, \ + { 5805, DMN_APL4, CHANNEL_OFDM }, \ + { 5825, DMN_APL4, CHANNEL_OFDM }, \ + \ + { 5745, DMN_APL5, CHANNEL_OFDM }, \ + { 5765, DMN_APL5, CHANNEL_OFDM }, \ + { 5785, DMN_APL5, CHANNEL_OFDM }, \ + { 5805, DMN_APL5, CHANNEL_OFDM }, \ + { 5825, DMN_APL5, CHANNEL_OFDM }, \ + \ + { 5180, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5200, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5220, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5240, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5260, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5280, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5300, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5320, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5500, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5520, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5540, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5560, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5580, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5600, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5620, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5640, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5660, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5680, DMN_ETSI1, CHANNEL_OFDM }, \ + { 5700, DMN_ETSI1, CHANNEL_OFDM }, \ + \ + { 5180, DMN_ETSI2, CHANNEL_OFDM }, \ + { 5200, DMN_ETSI2, CHANNEL_OFDM }, \ + { 5220, DMN_ETSI2, CHANNEL_OFDM }, \ + { 5240, DMN_ETSI2, CHANNEL_OFDM }, \ + \ + { 5180, DMN_ETSI3, CHANNEL_OFDM }, \ + { 5200, DMN_ETSI3, CHANNEL_OFDM }, \ + { 5220, DMN_ETSI3, CHANNEL_OFDM }, \ + { 5240, DMN_ETSI3, CHANNEL_OFDM }, \ + { 5260, DMN_ETSI3, CHANNEL_OFDM }, \ + { 5280, DMN_ETSI3, CHANNEL_OFDM }, \ + { 5300, DMN_ETSI3, CHANNEL_OFDM }, \ + { 5320, DMN_ETSI3, CHANNEL_OFDM }, \ + \ + { 5180, DMN_ETSI4, CHANNEL_OFDM }, \ + { 5200, DMN_ETSI4, CHANNEL_OFDM }, \ + { 5220, DMN_ETSI4, CHANNEL_OFDM }, \ + { 5240, DMN_ETSI4, CHANNEL_OFDM }, \ + { 5260, DMN_ETSI4, CHANNEL_OFDM }, \ + { 5280, DMN_ETSI4, CHANNEL_OFDM }, \ + { 5300, DMN_ETSI4, CHANNEL_OFDM }, \ + { 5320, DMN_ETSI4, CHANNEL_OFDM }, \ + \ + { 5180, DMN_ETSI5, CHANNEL_OFDM }, \ + { 5200, DMN_ETSI5, CHANNEL_OFDM }, \ + { 5220, DMN_ETSI5, CHANNEL_OFDM }, \ + { 5240, DMN_ETSI5, CHANNEL_OFDM }, \ + \ + { 5180, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5200, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5220, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5240, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5260, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5280, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5500, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5520, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5540, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5560, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5580, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5600, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5620, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5640, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5660, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5680, DMN_ETSI6, CHANNEL_OFDM }, \ + { 5700, DMN_ETSI6, CHANNEL_OFDM }, \ + \ + { 5180, DMN_FCC1, CHANNEL_OFDM }, \ + { 5200, DMN_FCC1, CHANNEL_OFDM }, \ + { 5210, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5220, DMN_FCC1, CHANNEL_OFDM }, \ + { 5240, DMN_FCC1, CHANNEL_OFDM }, \ + { 5250, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5260, DMN_FCC1, CHANNEL_OFDM }, \ + { 5280, DMN_FCC1, CHANNEL_OFDM }, \ + { 5290, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5300, DMN_FCC1, CHANNEL_OFDM }, \ + { 5320, DMN_FCC1, CHANNEL_OFDM }, \ + { 5745, DMN_FCC1, CHANNEL_OFDM }, \ + { 5760, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5765, DMN_FCC1, CHANNEL_OFDM }, \ + { 5785, DMN_FCC1, CHANNEL_OFDM }, \ + { 5800, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5805, DMN_FCC1, CHANNEL_OFDM }, \ + { 5825, DMN_FCC1, CHANNEL_OFDM }, \ + \ + { 5180, DMN_FCC2, CHANNEL_OFDM }, \ + { 5200, DMN_FCC2, CHANNEL_OFDM }, \ + { 5220, DMN_FCC2, CHANNEL_OFDM }, \ + { 5240, DMN_FCC2, CHANNEL_OFDM }, \ + { 5260, DMN_FCC2, CHANNEL_OFDM }, \ + { 5280, DMN_FCC2, CHANNEL_OFDM }, \ + { 5300, DMN_FCC2, CHANNEL_OFDM }, \ + { 5320, DMN_FCC2, CHANNEL_OFDM }, \ + { 5745, DMN_FCC2, CHANNEL_OFDM }, \ + { 5765, DMN_FCC2, CHANNEL_OFDM }, \ + { 5785, DMN_FCC2, CHANNEL_OFDM }, \ + { 5805, DMN_FCC2, CHANNEL_OFDM }, \ + { 5825, DMN_FCC2, CHANNEL_OFDM }, \ + \ + { 5180, DMN_FCC3, CHANNEL_OFDM }, \ + { 5200, DMN_FCC3, CHANNEL_OFDM }, \ + { 5210, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5220, DMN_FCC3, CHANNEL_OFDM }, \ + { 5240, DMN_FCC3, CHANNEL_OFDM }, \ + { 5250, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5260, DMN_FCC3, CHANNEL_OFDM }, \ + { 5280, DMN_FCC3, CHANNEL_OFDM }, \ + { 5290, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5300, DMN_FCC3, CHANNEL_OFDM }, \ + { 5320, DMN_FCC3, CHANNEL_OFDM }, \ + { 5500, DMN_FCC3, CHANNEL_OFDM }, \ + { 5520, DMN_FCC3, CHANNEL_OFDM }, \ + { 5540, DMN_FCC3, CHANNEL_OFDM }, \ + { 5560, DMN_FCC3, CHANNEL_OFDM }, \ + { 5580, DMN_FCC3, CHANNEL_OFDM }, \ + { 5600, DMN_FCC3, CHANNEL_OFDM }, \ + { 5620, DMN_FCC3, CHANNEL_OFDM }, \ + { 5640, DMN_FCC3, CHANNEL_OFDM }, \ + { 5660, DMN_FCC3, CHANNEL_OFDM }, \ + { 5680, DMN_FCC3, CHANNEL_OFDM }, \ + { 5700, DMN_FCC3, CHANNEL_OFDM }, \ + { 5745, DMN_FCC3, CHANNEL_OFDM }, \ + { 5760, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5765, DMN_FCC3, CHANNEL_OFDM }, \ + { 5785, DMN_FCC3, CHANNEL_OFDM }, \ + { 5800, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \ + { 5805, DMN_FCC3, CHANNEL_OFDM }, \ + { 5825, DMN_FCC3, CHANNEL_OFDM }, \ + \ + { 5170, DMN_MKK1, CHANNEL_OFDM }, \ + { 5190, DMN_MKK1, CHANNEL_OFDM }, \ + { 5210, DMN_MKK1, CHANNEL_OFDM }, \ + { 5230, DMN_MKK1, CHANNEL_OFDM }, \ + \ + { 5040, DMN_MKK2, CHANNEL_OFDM }, \ + { 5060, DMN_MKK2, CHANNEL_OFDM }, \ + { 5080, DMN_MKK2, CHANNEL_OFDM }, \ + { 5170, DMN_MKK2, CHANNEL_OFDM }, \ + { 5190, DMN_MKK2, CHANNEL_OFDM }, \ + { 5210, DMN_MKK2, CHANNEL_OFDM }, \ + { 5230, DMN_MKK2, CHANNEL_OFDM }, \ + \ + { 5180, DMN_WORLD, CHANNEL_OFDM }, \ + { 5200, DMN_WORLD, CHANNEL_OFDM }, \ + { 5220, DMN_WORLD, CHANNEL_OFDM }, \ + { 5240, DMN_WORLD, CHANNEL_OFDM }, \ }