Index: ar5xxx.c =================================================================== --- ar5xxx.c (revision 2185) +++ ar5xxx.c (revision 2232) @@ -1,1850 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for Atheros Wireless LAN devices. - * (Please have a look at ar5xxx.h for further information) - */ - -#include "ah_devid.h" -#include "ar5xxx.h" - -/* - * Per chipset attach functions - */ - -extern ar5k_attach_t ar5k_ar5210_attach; -extern ar5k_attach_t ar5k_ar5211_attach; -extern ar5k_attach_t ar5k_ar5212_attach; - -static const struct { - u_int16_t vendor; - u_int16_t device; - ar5k_attach_t (*attach); -} ar5k_known_products[] = { - /* - * From pcidevs_data.h - */ - - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210, - ar5k_ar5210_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP, - ar5k_ar5210_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT, - ar5k_ar5210_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211, - ar5k_ar5211_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT, - ar5k_ar5211_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5311, - ar5k_ar5211_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_FPGA11B, - ar5k_ar5211_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY, - ar5k_ar5211_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_IBM, - ar5k_ar5212_attach }, - { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675, - ar5k_ar5212_attach }, - { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_REV2, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_REV7, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_REV8, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0014, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0015, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0016, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0017, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0018, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_0019, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413, - ar5k_ar5212_attach }, - { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424, - ar5k_ar5212_attach }, -}; - -static const AR5K_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A; -static const AR5K_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B; -static const AR5K_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G; -static const AR5K_RATE_TABLE ar5k_rt_turbo = AR5K_RATES_TURBO; -static const AR5K_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR; - -int ar5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); -int ar5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); -u_int16_t ar5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); - -AR5K_BOOL ar5k_ar5110_channel(struct ath_hal *, AR5K_CHANNEL *); -u_int32_t ar5k_ar5110_chan2athchan(AR5K_CHANNEL *); -AR5K_BOOL ar5k_ar5111_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *); -AR5K_BOOL ar5k_ar5112_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); - -AR5K_BOOL ar5k_ar5111_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -AR5K_BOOL ar5k_ar5112_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -u_int ar5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, - u_int32_t, u_int32_t, AR5K_BOOL); - -/* - * Supported channels - */ -static const struct -ieee80211_regchannel ar5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; -static const struct -ieee80211_regchannel ar5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; - -/* - * Initial gain optimization values - */ -static const struct ar5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT; -static const struct ar5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT; - -/* - * Initial register for the radio chipsets - */ -static const struct ar5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF; -static const struct ar5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF; -static const struct ar5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF; -static const struct ar5k_ini_rfgain ar5k_rfg[] = AR5K_INI_RFGAIN; - -/* - * Enable to overwrite the country code (use "00" for debug) - */ -#if 0 -#define COUNTRYCODE "00" -#endif - -/* - * Perform a lookup if the device is supported by the HAL - */ -const char * /*O.K.*/ -ath_hal_probe(u_int16_t vendor, u_int16_t device) -{ - int i; - - /* - * Perform a linear search on the table of supported devices - */ - for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { - if (vendor == ar5k_known_products[i].vendor && - device == ar5k_known_products[i].device) - return (""); - } - - return (NULL); -} - -/* - * Fills in the HAL structure and initialises the device - */ -struct ath_hal * /*O.K. -added country code + get regdomain-*/ -ath_hal_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, AR5K_BUS_HANDLE sh, AR5K_STATUS *status) -{ - struct ath_hal *hal = NULL; - ar5k_attach_t *attach = NULL; - u_int8_t mac[IEEE80211_ADDR_LEN]; - int i; - - *status = AR5K_EINVAL; - - /* - * Call the chipset-dependent attach routine by device id - */ - for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { - if (device == ar5k_known_products[i].device && - ar5k_known_products[i].attach != NULL) - attach = ar5k_known_products[i].attach; - } - - if (attach == NULL) { - *status = AR5K_ENOTSUPP; - AR5K_PRINTF("device not supported: 0x%04x\n", device); - return (NULL); - } - - if ((hal = malloc(sizeof(struct ath_hal), - M_DEVBUF, M_NOWAIT)) == NULL) { - *status = AR5K_ENOMEM; - AR5K_PRINT("out of memory\n"); - return (NULL); - } - - bzero(hal, sizeof(struct ath_hal)); - - hal->ah_sc = sc; - hal->ah_st = st; - hal->ah_sh = sh; - hal->ah_device = device; - hal->ah_sub_vendor = 0; /* XXX unknown?! */ - - /* - * HAL information - */ - - /* Regulation Stuff */ - hal->ah_country_code = AR5K_TUNE_CTRY; - ar5k_get_regdomain(hal); - - hal->ah_op_mode = AR5K_M_STA; - hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; - hal->ah_turbo = FALSE; - hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; - hal->ah_imr = 0; - hal->ah_atim_window = 0; - hal->ah_aifs = AR5K_TUNE_AIFS; - hal->ah_cw_min = AR5K_TUNE_CWMIN; - hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; - hal->ah_software_retry = FALSE; - hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; - - switch (device) { - case PCI_PRODUCT_ATHEROS_AR2413: - case PCI_PRODUCT_ATHEROS_AR5413: - case PCI_PRODUCT_ATHEROS_AR5424: - /* - * Known single chip solutions - */ - hal->ah_single_chip = TRUE; - break; - default: - /* - * Multi chip solutions - */ - hal->ah_single_chip = FALSE; - break; - } - - if ((attach)(device, hal, st, sh, status) == NULL) - goto failed; - -#ifdef AR5K_DEBUG - hal->ah_dump_state(hal); -#endif - - /* - * Get card capabilities, values, ... - */ - - if (ar5k_eeprom_init(hal) != 0) { - *status = AR5K_EELOCKED; - AR5K_PRINT("unable to init EEPROM\n"); - goto failed; - } - - /* Get misc capabilities */ - if (hal->ah_get_capabilities(hal) != TRUE) { - *status = AR5K_EEREAD; - AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", - device); - goto failed; - } - - /* Get MAC address */ - if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) { - *status = AR5K_EEBADMAC; - AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", - device); - goto failed; - } - - hal->ah_set_lladdr(hal, mac); - - /* Get rate tables */ - if (hal->ah_capabilities.cap_mode & AR5K_MODE_11A) - ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_11B) - ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_11G) - ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_TURBO) - ar5k_rt_copy(&hal->ah_rt_turbo, &ar5k_rt_turbo); - if (hal->ah_capabilities.cap_mode & AR5K_MODE_XR) - ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr); - - /* Initialize the gain optimization values */ - if (hal->ah_radio == AR5K_AR5111) { - hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default; - hal->ah_gain.g_step = - &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; - hal->ah_gain.g_low = 20; - hal->ah_gain.g_high = 35; - hal->ah_gain.g_active = 1; - } else if (hal->ah_radio == AR5K_AR5112) { - hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default; - hal->ah_gain.g_step = - &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; - hal->ah_gain.g_low = 20; - hal->ah_gain.g_high = 85; - hal->ah_gain.g_active = 1; - } - - *status = AR5K_OK; - - return (hal); - - failed: - free(hal, M_DEVBUF); - return (NULL); -} - -u_int16_t /*O.K.*/ -ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates, - u_int32_t frame_length, u_int16_t rate_index, AR5K_BOOL short_preamble) -{ - const AR5K_RATE *rate; - u_int32_t value; - - AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); - - /* - * Get rate by index - */ - rate = &rates->rates[rate_index]; - - /* - * Calculate the transmission time by operation (PHY) mode - */ - switch (rate->modulation) { - case MODULATION_CCK: - /* - * CCK / DS mode (802.11b) - */ - value = AR5K_CCK_TX_TIME(rate->rate_kbps, frame_length, - (short_preamble && (rate->modulation == MODULATION_CCK_SP))); - break; - - case MODULATION_OFDM: - /* - * Orthogonal Frequency Division Multiplexing - */ - if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); - value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length); - break; - - case MODULATION_TURBO: - /* - * Orthogonal Frequency Division Multiplexing - * Atheros "Turbo Mode" (doubled rates) - */ - if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); - value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length); - break; - - case MODULATION_XR: - /* - * Orthogonal Frequency Division Multiplexing - * Atheros "eXtended Range" (XR) - */ - if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) - return (0); - value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length); - break; - - default: - return (0); - } - - return (value); -} - -/*Following 2 functions come from net80211 M.F.*/ - -/* - * Convert MHz frequency to IEEE channel number. - */ -u_int -ath_hal_mhz2ieee(u_int freq, u_int flags) -{ - if (flags & CHANNEL_2GHZ) { /* 2GHz band */ - if (freq == 2484) /* Japan */ - return 14; - if ((freq >= 2412) && (freq < 2484)) /* don't number non-IEEE channels */ - return (freq - 2407) / 5; - return 0; - } else if (flags & CHANNEL_5GHZ) { /* 5Ghz band */ - if ((freq >= 5150) && (freq <= 5825)) /* don't number non-IEEE channels */ - return (freq - 5000) / 5; - return 0; - } else { - /* something is fishy, don't do anything */ - return 0; - } -} - -/* - * Convert IEEE channel number to MHz frequency. - */ -u_int -ath_hal_ieee2mhz(u_int chan, u_int flags) -{ - if (flags & CHANNEL_2GHZ) { /* 2GHz band */ - if (chan == 14) - return 2484; - if (chan < 14) - return 2407 + chan * 5; - else - return 2512 + ((chan - 15) * 20); - } else if (flags & CHANNEL_5GHZ) /* 5Ghz band */ - return 5000 + (chan * 5); - else { /* either, guess */ - if (chan == 14) - return 2484; - if (chan < 14) /* 0-13 */ - return 2407 + chan * 5; - if (chan < 27) /* 15-26 */ - return 2512 + ((chan - 15) * 20); - return 5000 + (chan * 5); - } -} - - -AR5K_BOOL /*O.K.*/ -ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) -{ - /* Check if the channel is in our supported range */ - if (flags & CHANNEL_2GHZ) { - if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && - (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) - return (TRUE); - } else if (flags & CHANNEL_5GHZ) { - if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && - (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) - return (TRUE); - } - - return (FALSE); -} - -AR5K_BOOL /*Ported, added SUPERCHANNEL & country code + FIX in debug mode*/ -ath_hal_init_channels(struct ath_hal *hal, AR5K_CHANNEL *channels, - u_int max_channels, u_int *channels_size, AR5K_CTRY_CODE country, u_int16_t mode, - AR5K_BOOL outdoor, AR5K_BOOL extended) -{ - u_int i, c; - u_int32_t domain_current; - u_int domain_5ghz, domain_2ghz; - AR5K_CHANNEL *all_channels; - AR5K_CTRY_CODE country_current; - - if ((all_channels = malloc(sizeof(AR5K_CHANNEL) * max_channels, - M_TEMP, M_NOWAIT)) == NULL) - return (FALSE); - - i = c = 0; - domain_current = hal->ah_regdomain; - hal->ah_country_code = country; - country_current = hal->ah_country_code; - - /* - * In debugging mode, enable all channels supported by the chipset - */ - if (domain_current == DMN_DEFAULT || SUPERCHANNEL == 1) { - int min, max, freq; - u_int flags; - - min = ath_hal_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN, - CHANNEL_2GHZ); - max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX, - CHANNEL_2GHZ); - flags = CHANNEL_B /*| CHANNEL_TG | - (hal->ah_version == AR5K_AR5211 ? - CHANNEL_PUREG : CHANNEL_G)*/; - - debugchan: - for (i = min; i <= max && c < max_channels; i++) { - freq = ath_hal_ieee2mhz(i, flags); - if (ar5k_check_channel(hal, freq, flags) == FALSE) - continue; - all_channels[c].freq = freq; - all_channels[c++].channel_flags = flags; - } - - /* If is there to protect from infinite loop */ - if (flags & CHANNEL_2GHZ) { -/* ath_hal_mhz2ieee returns 1 for IEEE80211_CHANNELS_5GHZ_MIN -for loop starts from 1 and all channels are marked as 5GHz M.F.*/ -// min = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, -// CHANNEL_5GHZ); -/* Continue from where we stoped, skip last 2GHz channel */ - min = max + 1; - max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, - CHANNEL_5GHZ); - flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR; - goto debugchan; - } - - goto done; - } - - domain_5ghz = ieee80211_regdomain2flag(domain_current, - IEEE80211_CHANNELS_5GHZ_MIN); - domain_2ghz = ieee80211_regdomain2flag(domain_current, - IEEE80211_CHANNELS_2GHZ_MIN); - - /* - * Create channel list based on chipset capabilities, regulation domain - * and mode. 5GHz... - */ - for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && - (i < AR5K_ELEMENTS(ar5k_5ghz_channels)) && - (c < max_channels); i++) { - /* Check if channel is supported by the chipset */ - if (ar5k_check_channel(hal, - ar5k_5ghz_channels[i].rc_channel, - CHANNEL_5GHZ) == FALSE) - continue; - - /* Match regulation domain */ - if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domain) & - IEEE80211_DMN(domain_5ghz)) == 0) - continue; - - /* Match modes */ - if (ar5k_5ghz_channels[i].rc_mode & CHANNEL_TURBO) { - all_channels[c].channel_flags = CHANNEL_T; - } else if (ar5k_5ghz_channels[i].rc_mode & - CHANNEL_OFDM) { - all_channels[c].channel_flags = CHANNEL_A; - } else - continue; - - /* Write channel and increment counter */ - all_channels[c++].freq = ar5k_5ghz_channels[i].rc_channel; - } - - /* - * ...and 2GHz. - */ - for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && - (i < AR5K_ELEMENTS(ar5k_2ghz_channels)) && - (c < max_channels); i++) { - /* Check if channel is supported by the chipset */ - if (ar5k_check_channel(hal, - ar5k_2ghz_channels[i].rc_channel, - CHANNEL_2GHZ) == FALSE) - continue; - - /* Match regulation domain */ - if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domain) & - IEEE80211_DMN(domain_2ghz)) == 0) - continue; - - /* Match modes */ - if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11B) && - (ar5k_2ghz_channels[i].rc_mode & CHANNEL_CCK)) - all_channels[c].channel_flags = CHANNEL_B; - - if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11G) && - (ar5k_2ghz_channels[i].rc_mode & CHANNEL_OFDM)) { - all_channels[c].channel_flags |= - hal->ah_version == AR5K_AR5211 ? - CHANNEL_PUREG : CHANNEL_G; - if (ar5k_2ghz_channels[i].rc_mode & - CHANNEL_TURBO) - all_channels[c].channel_flags |= CHANNEL_TG; - } - - /* Write channel and increment counter */ - all_channels[c++].freq = ar5k_2ghz_channels[i].rc_channel; - } - - done: - bcopy(all_channels, channels, sizeof(AR5K_CHANNEL) * max_channels); - *channels_size = c; - free(all_channels, M_TEMP); - return (TRUE); -} - -/* - * Common internal functions - */ - -const char * /*O.K.*/ -ar5k_printver(enum ar5k_srev_type type, u_int32_t val) -{ - struct ar5k_srev_name names[] = AR5K_SREV_NAME; - const char *name = "xxxx"; - int i; - - for (i = 0; i < AR5K_ELEMENTS(names); i++) { - if (type == AR5K_VERSION_DEV) { - if (names[i].sr_type == type && - names[i].sr_val == val) { - name = names[i].sr_name; - break; - } - continue; - } - if (names[i].sr_type != type || - names[i].sr_val == AR5K_SREV_UNKNOWN) - continue; - if ((val & 0xff) < names[i + 1].sr_val) { - name = names[i].sr_name; - break; - } - } - - return (name); -} - -void /*O.K.*/ -ar5k_radar_alert(struct ath_hal *hal) -{ - /* - * Limit ~1/s - */ - -// if (hal->ah_radar.r_last_channel.freq == -// hal->ah_current_channel.freq && -// tick < (hal->ah_radar.r_last_alert + hz)) - return; - -/* hal->ah_radar.r_last_channel.freq = - hal->ah_current_channel.freq; - hal->ah_radar.r_last_channel.channel_flags = - hal->ah_current_channel.channel_flags; - hal->ah_radar.r_last_alert = tick; - - AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", - hal->ah_radar.r_last_alert, hal->ah_current_channel.freq);*/ -} - -u_int16_t /*O.K.*/ -ar5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) -{ - u_int32_t regdomain = (u_int32_t)ieee; - - /* - * Use the default regulation domain if the value is empty - * or not supported by the net80211 regulation code. - */ - if (ieee80211_regdomain2flag(regdomain, - IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) - return ((u_int16_t)AR5K_TUNE_REGDOMAIN); - - /* It is supported, just return the value */ - return (regdomain); -} - -ieee80211_regdomain_t /*O.K.*/ -ar5k_regdomain_to_ieee(u_int16_t regdomain) -{ - ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; - - return (ieee); -} - -u_int16_t /*O.K*/ -ar5k_get_regdomain(struct ath_hal *hal) -{ - u_int16_t regdomain; - ieee80211_regdomain_t ieee_regdomain; -#ifdef COUNTRYCODE - u_int16_t code; -#endif - - ar5k_eeprom_regulation_domain(hal, FALSE, &ieee_regdomain); - hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; - -#ifdef COUNTRYCODE - /* - * Get the regulation domain by country code. This will ignore - * the settings found in the EEPROM. - */ - code = ieee80211_name2countrycode(COUNTRYCODE); - ieee_regdomain = ieee80211_countrycode2regdomain(code); -#endif - - regdomain = ar5k_regdomain_from_ieee(ieee_regdomain); - hal->ah_capabilities.cap_regdomain.reg_current = regdomain; - - return (regdomain); -} - -u_int32_t /*O.K.*/ -ar5k_bitswap(u_int32_t val, u_int bits) -{ - u_int32_t retval = 0, bit, i; - - for (i = 0; i < bits; i++) { - bit = (val >> i) & 1; - retval = (retval << 1) | bit; - } - - return (retval); -} - -u_int /*O.K.*/ -ar5k_htoclock(u_int usec, AR5K_BOOL turbo) -{ - return (turbo == TRUE ? (usec * 80) : (usec * 40)); -} - -u_int /*O.K.*/ -ar5k_clocktoh(u_int clock, AR5K_BOOL turbo) -{ - return (turbo == TRUE ? (clock / 80) : (clock / 40)); -} - -void /*O.K.*/ -ar5k_rt_copy(AR5K_RATE_TABLE *dst, const AR5K_RATE_TABLE *src) -{ - bzero(dst, sizeof(AR5K_RATE_TABLE)); - dst->rate_count = src->rate_count; - bcopy(src->rates, dst->rates, sizeof(dst->rates)); -} - -AR5K_BOOL /*O.K.*/ -ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, - u_int32_t val, AR5K_BOOL is_set) -{ - int i; - u_int32_t data; - - for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { - data = AR5K_REG_READ(reg); - if ((is_set == TRUE) && (data & flag)) - break; - else if ((data & flag) == val) - break; - AR5K_DELAY(15); - } - - if (i <= 0) - return (FALSE); - - return (TRUE); -} - -/* - * Common ar5xx EEPROM access functions - */ - -u_int16_t /*O.K.*/ -ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) -{ - u_int16_t val; - - if (bin == AR5K_EEPROM_CHANNEL_DIS) - return (bin); - - if (mode == AR5K_EEPROM_MODE_11A) { - if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) - val = (5 * bin) + 4800; - else - val = bin > 62 ? - (10 * 62) + (5 * (bin - 62)) + 5100 : - (bin * 10) + 5100; - } else { - if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) - val = bin + 2300; - else - val = bin + 2400; - } - - return (val); -} - -int /*O.K.*/ -ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t o = *offset; - u_int16_t val; - int ret, i = 0; - - AR5K_EEPROM_READ(o++, val); - ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; - ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; - ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; - ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; - ee->ee_ant_control[mode][i++] = val & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; - ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; - ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; - ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; - ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; - ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; - - AR5K_EEPROM_READ(o++, val); - ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; - ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; - ee->ee_ant_control[mode][i++] = val & 0x3f; - - /* Get antenna modes */ - hal->ah_antenna[mode][0] = - (ee->ee_ant_control[mode][0] << 4) | 0x1; - hal->ah_antenna[mode][AR5K_ANT_FIXED_A] = - ee->ee_ant_control[mode][1] | - (ee->ee_ant_control[mode][2] << 6) | - (ee->ee_ant_control[mode][3] << 12) | - (ee->ee_ant_control[mode][4] << 18) | - (ee->ee_ant_control[mode][5] << 24); - hal->ah_antenna[mode][AR5K_ANT_FIXED_B] = - ee->ee_ant_control[mode][6] | - (ee->ee_ant_control[mode][7] << 6) | - (ee->ee_ant_control[mode][8] << 12) | - (ee->ee_ant_control[mode][9] << 18) | - (ee->ee_ant_control[mode][10] << 24); - - /* return new offset */ - *offset = o; - - return (0); -} - -int /*O.K.*/ -ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t o = *offset; - u_int16_t val; - int ret; - - AR5K_EEPROM_READ(o++, val); - ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; - ee->ee_thr_62[mode] = val & 0xff; - - if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) - ee->ee_thr_62[mode] = - mode == AR5K_EEPROM_MODE_11A ? 15 : 28; - - AR5K_EEPROM_READ(o++, val); - ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; - ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; - - AR5K_EEPROM_READ(o++, val); - ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; - - if ((val & 0xff) & 0x80) - ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); - else - ee->ee_noise_floor_thr[mode] = val & 0xff; - - if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) - ee->ee_noise_floor_thr[mode] = - mode == AR5K_EEPROM_MODE_11A ? -54 : -1; - - AR5K_EEPROM_READ(o++, val); - ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; - ee->ee_x_gain[mode] = (val >> 1) & 0xf; - ee->ee_xpd[mode] = val & 0x1; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) - ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { - AR5K_EEPROM_READ(o++, val); - ee->ee_false_detect[mode] = (val >> 6) & 0x7f; - - if (mode == AR5K_EEPROM_MODE_11A) - ee->ee_xr_power[mode] = val & 0x3f; - else { - ee->ee_ob[mode][0] = val & 0x7; - ee->ee_db[mode][0] = (val >> 3) & 0x7; - } - } - - if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { - ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; - ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; - } else { - ee->ee_i_gain[mode] = (val >> 13) & 0x7; - - AR5K_EEPROM_READ(o++, val); - ee->ee_i_gain[mode] |= (val << 3) & 0x38; - - if (mode == AR5K_EEPROM_MODE_11G) - ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; - } - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && - mode == AR5K_EEPROM_MODE_11A) { - ee->ee_i_cal[mode] = (val >> 8) & 0x3f; - ee->ee_q_cal[mode] = (val >> 3) & 0x1f; - } - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && - mode == AR5K_EEPROM_MODE_11G) - ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; - - /* return new offset */ - *offset = o; - - return (0); -} - -int /*O.K.*/ -ar5k_eeprom_init(struct ath_hal *hal) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int32_t offset; - u_int16_t val; - int ret, i; - u_int mode; - - /* Initial TX thermal adjustment values */ - ee->ee_tx_clip = 4; - ee->ee_pwd_84 = ee->ee_pwd_90 = 1; - ee->ee_gain_select = 1; - - /* - * Read values from EEPROM and store them in the capability structure - */ - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); - - /* Return if we have an old EEPROM */ - if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) - return (0); - -#ifdef notyet - /* - * Validate the checksum of the EEPROM date. There are some - * devices with invalid EEPROMs. - */ - for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { - AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); - cksum ^= val; - } - if (cksum != AR5K_EEPROM_INFO_CKSUM) { - AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); - return (AR5K_EEBADSUM); - } -#endif - - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), - ee_ant_gain); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); - AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); - } - - if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { - AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); - ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; - ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; - - AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); - ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; - ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; - } - - /* - * Get conformance test limit values - */ - offset = AR5K_EEPROM_CTL(hal->ah_ee_version); - ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); - - for (i = 0; i < ee->ee_ctls; i++) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_ctl[i] = (val >> 8) & 0xff; - ee->ee_ctl[i + 1] = val & 0xff; - } - - /* - * Get values for 802.11a (5GHz) - */ - mode = AR5K_EEPROM_MODE_11A; - - ee->ee_turbo_max_power[mode] = - AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); - - offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); - - if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); - - AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); - ee->ee_ob[mode][3] = (val >> 5) & 0x7; - ee->ee_db[mode][3] = (val >> 2) & 0x7; - ee->ee_ob[mode][2] = (val << 1) & 0x7; - - AR5K_EEPROM_READ(offset++, val); - ee->ee_ob[mode][2] |= (val >> 15) & 0x1; - ee->ee_db[mode][2] = (val >> 12) & 0x7; - ee->ee_ob[mode][1] = (val >> 9) & 0x7; - ee->ee_db[mode][1] = (val >> 6) & 0x7; - ee->ee_ob[mode][0] = (val >> 3) & 0x7; - ee->ee_db[mode][0] = val & 0x7; - - if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_margin_tx_rx[mode] = val & 0x3f; - } - - /* - * Get values for 802.11b (2.4GHz) - */ - mode = AR5K_EEPROM_MODE_11B; - offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); - - if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); - - AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); - ee->ee_ob[mode][1] = (val >> 4) & 0x7; - ee->ee_db[mode][1] = val & 0x7; - - if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][0] = - ar5k_eeprom_bin2freq(hal, val & 0xff, mode); - ee->ee_cal_pier[mode][1] = - ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); - - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][2] = - ar5k_eeprom_bin2freq(hal, val & 0xff, mode); - } - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; - } - - /* - * Get values for 802.11g (2.4GHz) - */ - mode = AR5K_EEPROM_MODE_11G; - offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); - - if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) - return (ret); - - AR5K_EEPROM_READ(offset++, val); - ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); - ee->ee_ob[mode][1] = (val >> 4) & 0x7; - ee->ee_db[mode][1] = val & 0x7; - - if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) - return (ret); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][0] = - ar5k_eeprom_bin2freq(hal, val & 0xff, mode); - ee->ee_cal_pier[mode][1] = - ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); - - AR5K_EEPROM_READ(offset++, val); - ee->ee_turbo_max_power[mode] = val & 0x7f; - ee->ee_xr_power[mode] = (val >> 7) & 0x3f; - - AR5K_EEPROM_READ(offset++, val); - ee->ee_cal_pier[mode][2] = - ar5k_eeprom_bin2freq(hal, val & 0xff, mode); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; - } - - AR5K_EEPROM_READ(offset++, val); - ee->ee_i_cal[mode] = (val >> 8) & 0x3f; - ee->ee_q_cal[mode] = (val >> 3) & 0x1f; - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { - AR5K_EEPROM_READ(offset++, val); - ee->ee_cck_ofdm_gain_delta = val & 0xff; - } - } - - /* - * Read 5GHz EEPROM channels - */ - - return (0); -} - -int /*O.K.*/ -ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) -{ - u_int32_t total, offset; - u_int16_t data; - int octet; - u_int8_t mac_d[IEEE80211_ADDR_LEN]; - - bzero(mac, IEEE80211_ADDR_LEN); - bzero(&mac_d, IEEE80211_ADDR_LEN); - - if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) - return (AR5K_EIO); - - for (offset = 0x1f, octet = 0, total = 0; - offset >= 0x1d; offset--) { - if (hal->ah_eeprom_read(hal, offset, &data) != 0) - return (AR5K_EIO); - - total += data; - mac_d[octet + 1] = data & 0xff; - mac_d[octet] = data >> 8; - octet += 2; - } - - bcopy(mac_d, mac, IEEE80211_ADDR_LEN); - - if ((!total) || total == (3 * 0xffff)) - return (AR5K_EINVAL); - - return (0); -} - -AR5K_BOOL /*O.K*/ -ar5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, - ieee80211_regdomain_t *regdomain) -{ - u_int16_t ee_regdomain; - - /* Read current value */ - if (write != TRUE) { - ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; - *regdomain = ar5k_regdomain_to_ieee(ee_regdomain); - return (TRUE); - } - - ee_regdomain = ar5k_regdomain_from_ieee(*regdomain); - - /* Try to write a new value */ - if (hal->ah_capabilities.cap_eeprom.ee_protect & - AR5K_EEPROM_PROTECT_WR_128_191) - return (FALSE); - if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, - ee_regdomain) != 0) - return (FALSE); - - hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; - - return (TRUE); -} - -/* - * PHY/RF access functions - */ - -AR5K_BOOL /*O.K.*/ -ar5k_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - AR5K_BOOL ret; - - /* - * Check bounds supported by the PHY - * (don't care about regulation restrictions at this point) - */ - if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min || - channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) && - (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min || - channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { - AR5K_PRINTF("channel out of supported range (%u MHz)\n", - channel->freq); - return (FALSE); - } - - /* - * Set the channel and wait - */ - if (hal->ah_radio == AR5K_AR5110) - ret = ar5k_ar5110_channel(hal, channel); - else if (hal->ah_radio == AR5K_AR5111) - ret = ar5k_ar5111_channel(hal, channel); - else - ret = ar5k_ar5112_channel(hal, channel); - - if (ret == FALSE) - return (ret); - - hal->ah_current_channel.freq = channel->freq; - hal->ah_current_channel.channel_flags = channel->channel_flags; - hal->ah_turbo = channel->channel_flags == CHANNEL_T ? - TRUE : FALSE; - - return (TRUE); -} - -u_int32_t /*O.K.*/ -ar5k_ar5110_chan2athchan(AR5K_CHANNEL *channel) -{ - u_int32_t athchan; - - /* - * Convert IEEE channel/MHz to an internal channel value used - * by the AR5210 chipset. This has not been verified with - * newer chipsets like the AR5212A who have a completely - * different RF/PHY part. - */ - athchan = (ar5k_bitswap((ath_hal_mhz2ieee(channel->freq, - channel->channel_flags) - 24) / 2, 5) << 1) | - (1 << 6) | 0x1; - - return (athchan); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - u_int32_t data; - - /* - * Set the channel and wait - */ - data = ar5k_ar5110_chan2athchan(channel); - AR5K_PHY_WRITE(0x27, data); - AR5K_PHY_WRITE(0x30, 0); - AR5K_DELAY(1000); - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan) -{ - int channel; - - /* Cast this value to catch negative channel numbers (>= -19) */ - channel = (int)ieee; - - /* - * Map 2GHz IEEE channel to 5GHz Atheros channel - */ - if (channel <= 13) { - athchan->a2_athchan = 115 + channel; - athchan->a2_flags = 0x46; - } else if (channel == 14) { - athchan->a2_athchan = 124; - athchan->a2_flags = 0x44; - } else if (channel >= 15 && channel <= 26) { - athchan->a2_athchan = ((channel - 14) * 4) + 132; - athchan->a2_flags = 0x46; - } else - return (FALSE); - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - u_int ieee_channel, ath_channel; - u_int32_t data0, data1, clock; - struct ar5k_athchan_2ghz ath_channel_2ghz; - - /* - * Set the channel on the AR5111 radio - */ - data0 = data1 = 0; - ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, - channel->channel_flags); - - if (channel->channel_flags & CHANNEL_2GHZ) { - /* Map 2GHz channel to 5GHz Atheros channel ID */ - if (ar5k_ar5111_chan2athchan(ieee_channel, - &ath_channel_2ghz) == FALSE) - return (FALSE); - - ath_channel = ath_channel_2ghz.a2_athchan; - data0 = ((ar5k_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) - << 5) | (1 << 4); - } - - if (ath_channel < 145 || !(ath_channel & 1)) { - clock = 1; - data1 = ((ar5k_bitswap(ath_channel - 24, 8) & 0xff) << 2) - | (clock << 1) | (1 << 10) | 1; - } else { - clock = 0; - data1 = ((ar5k_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) - | (clock << 1) | (1 << 10) | 1; - } - - AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); - AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - u_int32_t data, data0, data1, data2; - u_int16_t c; - - data = data0 = data1 = data2 = 0; - c = channel->freq; - - /* - * Set the channel on the AR5112 or newer - */ - if (c < 4800) { - if (!((c - 2224) % 5)) { - data0 = ((2 * (c - 704)) - 3040) / 10; - data1 = 1; - } else if (!((c - 2192) % 5)) { - data0 = ((2 * (c - 672)) - 3040) / 10; - data1 = 0; - } else - return (FALSE); - - data0 = ar5k_bitswap((data0 << 2) & 0xff, 8); - } else { - if (!(c % 20) && c >= 5120) { - data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8); - data2 = ar5k_bitswap(3, 2); - } else if (!(c % 10)) { - data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8); - data2 = ar5k_bitswap(2, 2); - } else if (!(c % 5)) { - data0 = ar5k_bitswap((c - 4800) / 5, 8); - data2 = ar5k_bitswap(1, 2); - } else - return (FALSE); - } - - data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; - - AR5K_PHY_WRITE(0x27, data & 0xff); - AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); - - return (TRUE); -} - -u_int /*O.K. data initialized */ -ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, - u_int32_t first, u_int32_t col, AR5K_BOOL set) -{ - u_int32_t mask, entry, last, data, shift, position; - int32_t left; - int i; - - data = 0; - - if (rf == NULL) { - /* should not happen */ - return (0); - } - - if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { - AR5K_PRINTF("invalid values at offset %u\n", offset); - return (0); - } - - entry = ((first - 1) / 8) + offset; - position = (first - 1) % 8; - - if (set == TRUE) - data = ar5k_bitswap(reg, bits); - - for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { - last = (position + left > 8) ? 8 : position + left; - mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << - (col * 8); - - if (set == TRUE) { - rf[entry] &= ~mask; - rf[entry] |= ((data << position) << (col * 8)) & mask; - data >>= (8 - position); - } else { - data = (((rf[entry] & mask) >> (col * 8)) >> - position) << shift; - shift += last - position; - } - - left -= 8 - position; - } - - data = set == TRUE ? 1 : ar5k_bitswap(data, bits); - - return (data); -} - -u_int32_t /*O.K.*/ -ar5k_rfregs_gainf_corr(struct ath_hal *hal) -{ - u_int32_t mix, step; - u_int32_t *rf; - - if (hal->ah_rf_banks == NULL) - return (0); - - rf = hal->ah_rf_banks; - hal->ah_gain.g_f_corr = 0; - - if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1) - return (0); - - step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE); - mix = hal->ah_gain.g_step->gos_param[0]; - - switch (mix) { - case 3: - hal->ah_gain.g_f_corr = step * 2; - break; - case 2: - hal->ah_gain.g_f_corr = (step - 5) * 2; - break; - case 1: - hal->ah_gain.g_f_corr = step; - break; - default: - hal->ah_gain.g_f_corr = 0; - break; - } - - return (hal->ah_gain.g_f_corr); -} - -AR5K_BOOL /*O.K.*/ -ar5k_rfregs_gain_readback(struct ath_hal *hal) -{ - u_int32_t step, mix, level[4]; - u_int32_t *rf; - - if (hal->ah_rf_banks == NULL) - return (0); - - rf = hal->ah_rf_banks; - - if (hal->ah_radio == AR5K_AR5111) { - step = ar5k_rfregs_op(rf, hal->ah_offset[7], - 0, 6, 37, 0, FALSE); - level[0] = 0; - level[1] = (step == 0x3f) ? 0x32 : step + 4; - level[2] = (step != 0x3f) ? 0x40 : level[0]; - level[3] = level[2] + 0x32; - - hal->ah_gain.g_high = level[3] - - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); - hal->ah_gain.g_low = level[0] + - (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); - } else { - mix = ar5k_rfregs_op(rf, hal->ah_offset[7], - 0, 1, 36, 0, FALSE); - level[0] = level[2] = 0; - - if (mix == 1) { - level[1] = level[3] = 83; - } else { - level[1] = level[3] = 107; - hal->ah_gain.g_high = 55; - } - } - - return ((hal->ah_gain.g_current >= level[0] && - hal->ah_gain.g_current <= level[1]) || - (hal->ah_gain.g_current >= level[2] && - hal->ah_gain.g_current <= level[3])); -} - -int32_t /*O.K.*/ -ar5k_rfregs_gain_adjust(struct ath_hal *hal) -{ - int ret = 0; - const struct ar5k_gain_opt *go; - - go = hal->ah_radio == AR5K_AR5111 ? - &ar5111_gain_opt : &ar5112_gain_opt; - - hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; - - if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { - if (hal->ah_gain.g_step_idx == 0) - return (-1); - for (hal->ah_gain.g_target = hal->ah_gain.g_current; - hal->ah_gain.g_target >= hal->ah_gain.g_high && - hal->ah_gain.g_step_idx > 0; - hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { - hal->ah_gain.g_target -= 2 * - (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - - hal->ah_gain.g_step->gos_gain); - } - - ret = 1; - goto done; - } - - if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { - if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) - return (-2); - for (hal->ah_gain.g_target = hal->ah_gain.g_current; - hal->ah_gain.g_target <= hal->ah_gain.g_low && - hal->ah_gain.g_step_idx < (go->go_steps_count - 1); - hal->ah_gain.g_step = - &go->go_step[hal->ah_gain.g_step_idx]) { - hal->ah_gain.g_target -= 2 * - (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - - hal->ah_gain.g_step->gos_gain); - } - - ret = 2; - goto done; - } - - done: -#ifdef AR5K_DEBUG - AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", - ret, - hal->ah_gain.g_step_idx, - hal->ah_gain.g_current, - hal->ah_gain.g_target); -#endif - - return (ret); -} - -AR5K_BOOL /*O.K.*/ -ar5k_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) -{ - ar5k_rfgain_t *func = NULL; - AR5K_BOOL ret; - - if (hal->ah_radio == AR5K_AR5111) { - hal->ah_rf_banks_size = sizeof(ar5111_rf); - func = ar5k_ar5111_rfregs; - } else if (hal->ah_radio == AR5K_AR5112) { - if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) - hal->ah_rf_banks_size = sizeof(ar5112a_rf); - else - hal->ah_rf_banks_size = sizeof(ar5112_rf); - func = ar5k_ar5112_rfregs; - } else - return (FALSE); - - if (hal->ah_rf_banks == NULL) { - /* XXX do extra checks? */ - if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, - M_DEVBUF, M_NOWAIT)) == NULL) { - AR5K_PRINT("out of memory\n"); - return (FALSE); - } - } - - ret = (func)(hal, channel, mode); - - if (ret == TRUE) - hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; - - return (ret); -} - -AR5K_BOOL /*O.K*/ -ar5k_ar5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - const u_int rf_size = AR5K_ELEMENTS(ar5111_rf); - u_int32_t *rf; - int i, obdb = -1, bank = -1; - u_int32_t ee_mode; - - AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); - - rf = hal->ah_rf_banks; - - /* Copy values to modify them */ - for (i = 0; i < rf_size; i++) { - if (ar5111_rf[i].rf_bank >= - AR5K_AR5111_INI_RF_MAX_BANKS) { - AR5K_PRINT("invalid bank\n"); - return (FALSE); - } - - if (bank != ar5111_rf[i].rf_bank) { - bank = ar5111_rf[i].rf_bank; - hal->ah_offset[bank] = i; - } - - rf[i] = ar5111_rf[i].rf_value[mode]; - } - - if (channel->channel_flags & CHANNEL_2GHZ) { - if (channel->channel_flags & CHANNEL_B) - ee_mode = AR5K_EEPROM_MODE_11B; - else - ee_mode = AR5K_EEPROM_MODE_11G; - obdb = 0; - - if (!ar5k_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 119, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[0], - ee->ee_ob[ee_mode][obdb], 3, 122, 0, TRUE)) - return (FALSE); - - obdb = 1; - } else { - /* For 11a, Turbo and XR */ - ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_84, 1, 51, 3, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_pwd_90, 1, 45, 3, TRUE)) - return (FALSE); - } - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - !ee->ee_xpd[ee_mode], 1, 95, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 4, 96, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[7], - ee->ee_xpd[ee_mode], 1, 4, 0, TRUE)) - return (FALSE); - - /* Write RF values */ - for (i = 0; i < rf_size; i++) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); - } - - return (TRUE); -} - -AR5K_BOOL /*O.K*/ -ar5k_ar5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int rf_size; - u_int32_t *rf; - int i, obdb = -1, bank = -1; - u_int32_t ee_mode; - const struct ar5k_ini_rf *rf_ini; - - AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); - - rf = hal->ah_rf_banks; - - if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { - rf_ini = ar5112a_rf; - rf_size = AR5K_ELEMENTS(ar5112a_rf); - } else { - rf_ini = ar5112_rf; - rf_size = AR5K_ELEMENTS(ar5112_rf); - } - - /* Copy values to modify them */ - for (i = 0; i < rf_size; i++) { - if (rf_ini[i].rf_bank >= - AR5K_AR5112_INI_RF_MAX_BANKS) { - AR5K_PRINT("invalid bank\n"); - return (FALSE); - } - - if (bank != rf_ini[i].rf_bank) { - bank = rf_ini[i].rf_bank; - hal->ah_offset[bank] = i; - } - - rf[i] = rf_ini[i].rf_value[mode]; - } - - if (channel->channel_flags & CHANNEL_2GHZ) { - if (channel->channel_flags & CHANNEL_B) - ee_mode = AR5K_EEPROM_MODE_11B; - else - ee_mode = AR5K_EEPROM_MODE_11G; - obdb = 0; - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 287, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 290, 0, TRUE)) - return (FALSE); - } else { - /* For 11a, Turbo and XR */ - ee_mode = AR5K_EEPROM_MODE_11A; - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 279, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_ob[ee_mode][obdb], 3, 282, 0, TRUE)) - return (FALSE); - } - -#ifdef notyet - ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 270, 0, TRUE); - ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_x_gain[ee_mode], 2, 257, 0, TRUE); -#endif - - if (!ar5k_rfregs_op(rf, hal->ah_offset[6], - ee->ee_xpd[ee_mode], 1, 302, 0, TRUE)) - return (FALSE); - - if (!ar5k_rfregs_op(rf, hal->ah_offset[7], - ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE)) - return (FALSE); - - /* Write RF values */ - for (i = 0; i < rf_size; i++) - AR5K_REG_WRITE(ar5112_rf[i].rf_register, rf[i]); - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq) -{ - int i; - - switch (phy) { - case AR5K_INI_PHY_5111: - case AR5K_INI_PHY_5112: - break; - default: - return (FALSE); - } - - switch (freq) { - case AR5K_INI_RFGAIN_2GHZ: - case AR5K_INI_RFGAIN_5GHZ: - break; - default: - return (FALSE); - } - - for (i = 0; i < AR5K_ELEMENTS(ar5k_rfg); i++) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5k_rfg[i].rfg_register, - ar5k_rfg[i].rfg_value[phy][freq]); - } - - return (TRUE); -} - -/* - * Common TX power setup - */ -void /*O.K.*/ -ar5k_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t max_power) -{ - u_int16_t txpower, *rates; - int i, min, max, n; - - rates = hal->ah_txpower.txp_rates; - - txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; - if (max_power > txpower) { - txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? - AR5K_TUNE_MAX_TXPOWER : max_power; - } - - for (i = 0; i < AR5K_MAX_RATES; i++) - rates[i] = txpower; - - /* XXX setup target powers by rate */ - - hal->ah_txpower.txp_min = rates[7]; - hal->ah_txpower.txp_max = rates[0]; - hal->ah_txpower.txp_ofdm = rates[0]; - - /* Calculate the power table */ - n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac); - min = AR5K_EEPROM_PCDAC_START; - max = AR5K_EEPROM_PCDAC_STOP; - for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) - hal->ah_txpower.txp_pcdac[i] = -//#ifdef notyet - min + ((i * (max - min)) / n); -//#else -// min; -//#endif -} - -/* Functions not found in OpenBSD */ - -u_int /*New*/ -ath_hal_getwirelessmodes(struct ath_hal *hal, AR5K_CTRY_CODE country) -{ - switch(hal->ah_version){ - case AR5K_AR5212: - return (AR5K_MODE_11A|AR5K_MODE_11B); - case AR5K_AR5211: - return (AR5K_MODE_11B|AR5K_MODE_108G); - default : - return(AR5K_MODE_11A); - } -} Index: ar5xxx.h =================================================================== --- ar5xxx.h (revision 2185) +++ ar5xxx.h (revision 2232) @@ -1,2108 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for Atheros Wireless LAN devices. - * - * ar5k is a free replacement of the binary-only HAL used by some drivers - * for Atheros chipsets. While using a different ABI, it tries to be - * source-compatible with the original (non-free) HAL interface. - * - * Many thanks to various contributors who supported the development of - * ar5k with hard work and useful information. And, of course, for all the - * people who encouraged me to continue this work which has been based - * on my initial approach found on http://team.vantronix.net/ar5k/. - */ - -#ifndef _AR5K_H -#define _AR5K_H - -/*Os dependent definitions*/ -#include "ah_osdep.h" - -/*Regulatory domain & Channel definitions*/ -#include "ieee80211_regdomain.h" - -/*Options*/ -#include "opt_ah.h" - -/* - *Translation for MadWiFi combatibility - *(damn this is changed AGAIN in if_ath.pci :P) - */ -#include "translation.h" - -/*Use with MadWiFi/net80211*/ -#include "stack_net80211.h" - - -/****************************\ - GENERIC DRIVER DEFINITIONS -\****************************/ - -/* - * C doesn't support boolean ;-( - * TODO: See if there is a bool definition somewere else - * in the kernel, we shouldn't redefine it if it does... - */ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif -typedef u_int8_t AR5K_BOOL; - -/* - * Error codes reported from HAL to the driver - */ -typedef enum { - AR5K_OK = 0, /* Everything went O.K.*/ - AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/ - AR5K_EIO = 2, /* Hardware I/O Error*/ - AR5K_EELOCKED = 3, /* Unable to access EEPROM*/ - AR5K_EEBADSUM = 4, /* Invalid EEPROM checksum*/ - AR5K_EEREAD = 5, /* Unable to get device caps from EEPROM */ - AR5K_EEBADMAC = 6, /* Unable to read MAC address from EEPROM */ - AR5K_EINVAL = 7, /* Invalid parameter to function */ - AR5K_ENOTSUPP = 8, /* Hardware revision not supported */ - AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */ -} AR5K_STATUS; - -/* - * Some tuneable values (these should be changeable by the user) - */ -#define AR5K_TUNE_DMA_BEACON_RESP 2 -#define AR5K_TUNE_SW_BEACON_RESP 10 -#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 -#define AR5K_TUNE_RADAR_ALERT FALSE -#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 -#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) -#define AR5K_TUNE_RSSI_THRES 1792 -#define AR5K_TUNE_REGISTER_TIMEOUT 20000 -#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 -#define AR5K_TUNE_BEACON_INTERVAL 100 -#define AR5K_TUNE_AIFS 2 -#define AR5K_TUNE_AIFS_11B 2 -#define AR5K_TUNE_AIFS_XR 0 -#define AR5K_TUNE_CWMIN 15 -#define AR5K_TUNE_CWMIN_11B 31 -#define AR5K_TUNE_CWMIN_XR 3 -#define AR5K_TUNE_CWMAX 1023 -#define AR5K_TUNE_CWMAX_11B 1023 -#define AR5K_TUNE_CWMAX_XR 7 -#define AR5K_TUNE_NOISE_FLOOR -72 -#define AR5K_TUNE_MAX_TXPOWER 60 -#define AR5K_TUNE_DEFAULT_TXPOWER 30 -#define AR5K_TUNE_TPC_TXPOWER TRUE -#define AR5K_TUNE_ANT_DIVERSITY TRUE -#define AR5K_TUNE_HWTXTRIES 4 - -/* token to use for aifs, cwmin, cwmax in MadWiFi */ -#define AR5K_TXQ_USEDEFAULT ((u_int32_t) -1) - -#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ -#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ -static const u_char etherbroadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; -//#define etherbroadcastaddr 0xff - - - - -/*****************************\ - GENERIC CHIPSET DEFINITIONS -\*****************************/ - -/* MAC Chips*/ -enum ar5k_version { - AR5K_AR5210 = 0, - AR5K_AR5211 = 1, - AR5K_AR5212 = 2, -}; - -/*PHY Chips*/ -enum ar5k_radio { - AR5K_AR5110 = 0, - AR5K_AR5111 = 1, - AR5K_AR5112 = 2, -}; - -/* - * Common silicon revision/version values - */ -enum ar5k_srev_type { - AR5K_VERSION_VER, - AR5K_VERSION_REV, - AR5K_VERSION_RAD, - AR5K_VERSION_DEV -}; - -struct ar5k_srev_name { - const char *sr_name; - enum ar5k_srev_type sr_type; - u_int sr_val; -}; - -#define AR5K_SREV_NAME { \ - { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ - { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ - { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ - { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ - { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ - { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ - { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ - { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ - { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ - { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ - { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ - { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ - { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ - { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ - { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ - { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ - { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \ - { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \ - { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \ - { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ -} - -#define AR5K_SREV_UNKNOWN 0xffff - -#define AR5K_SREV_VER_AR5210 0x00 -#define AR5K_SREV_VER_AR5311 0x10 -#define AR5K_SREV_VER_AR5311A 0x20 -#define AR5K_SREV_VER_AR5311B 0x30 -#define AR5K_SREV_VER_AR5211 0x40 -#define AR5K_SREV_VER_AR5212 0x50 -#define AR5K_SREV_VER_AR5213 0x55 -#define AR5K_SREV_VER_UNSUPP 0x60 - -#define AR5K_SREV_RAD_5110 0x00 -#define AR5K_SREV_RAD_5111 0x10 -#define AR5K_SREV_RAD_5111A 0x15 -#define AR5K_SREV_RAD_2111 0x20 -#define AR5K_SREV_RAD_5112 0x30 -#define AR5K_SREV_RAD_5112A 0x35 -#define AR5K_SREV_RAD_2112 0x40 -#define AR5K_SREV_RAD_2112A 0x45 -#define AR5K_SREV_RAD_UNSUPP 0x50 - - - - -/****************\ - TX DEFINITIONS -\****************/ - -/* - * Tx Descriptor - */ -struct ath_tx_status { - u_int16_t ts_seqnum; - u_int16_t ts_tstamp; - u_int8_t ts_status; - u_int8_t ts_rate; - int8_t ts_rssi; - u_int8_t ts_shortretry; - u_int8_t ts_longretry; - u_int8_t ts_virtcol; - u_int8_t ts_antenna; -}; - -#define AR5K_TXSTAT_ALTRATE 0x80 -#define AR5K_TXERR_XRETRY 0x01 -#define AR5K_TXERR_FILT 0x02 -#define AR5K_TXERR_FIFO 0x04 - -/* - * Queue types used to classify tx queues. - */ -typedef enum { - AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ - AR5K_TX_QUEUE_DATA, /*A normal data queue*/ - AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ - AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ - AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ - AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ -} AR5K_TX_QUEUE; - -#define AR5K_NUM_TX_QUEUES 10 - -/* - * Queue syb-types to classify normal data queues. - * These are the 4 Access Categories as defined in - * WME spec. 0 is the lowest priority and 4 is the - * highest. Normal data that hasn't been classified - * goes to the Best Effort AC. - */ -typedef enum { - AR5K_WME_AC_BK = 0, /*Background traffic*/ - AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ - AR5K_WME_AC_VI, /*Video traffic*/ - AR5K_WME_AC_VO, /*Voice traffic*/ -} AR5K_TX_QUEUE_SUBTYPE; - -/* - * Queue ID numbers as returned by the HAL, each number - * represents a hw queue. If hw does not support hw queues - * (eg 5210/5211) all data goes in one queue. These match - * d80211 definitions (net80211/MadWiFi don't use them). - */ -typedef enum { - AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ - AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ - AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ - AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ - AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ - AR5K_TX_QUEUE_ID_UAPSD = 8, - AR5K_TX_QUEUE_ID_XR_DATA = 9, -} AR5K_TX_QUEUE_ID; - - -/* - * Flags to set hw queue's parameters... - */ -#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ -#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ -#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ -#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ -#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ -#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ -#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ -#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ - -/* - * A struct to hold tx queue's parameters - */ -typedef struct { - AR5K_TX_QUEUE tqi_type; /* See AR5K_TX_QUEUE */ - AR5K_TX_QUEUE_SUBTYPE tqi_subtype; /* See AR5K_TX_QUEUE_SUBTYPE */ - u_int16_t tqi_flags; /* Tx queue flags (see above) */ - u_int32_t tqi_aifs; /* Arbitrated Interframe Space */ - int32_t tqi_cw_min; /* Minimum Contention Window */ - int32_t tqi_cw_max; /* Maximum Contention Window */ - u_int32_t tqi_cbr_period; /* Constant bit rate period */ - u_int32_t tqi_cbr_overflow_limit; - u_int32_t tqi_burst_time; - u_int32_t tqi_ready_time; /* Not used */ - u_int32_t tqi_comp_buffer;/* Compression Buffer's phys addr */ -} AR5K_TXQ_INFO; - -/* - * Transmit packet types. - * These are not fully used inside OpenHAL yet - */ -typedef enum { - AR5K_PKT_TYPE_NORMAL = 0, - AR5K_PKT_TYPE_ATIM = 1, - AR5K_PKT_TYPE_PSPOLL = 2, - AR5K_PKT_TYPE_BEACON = 3, - AR5K_PKT_TYPE_PROBE_RESP = 4, - AR5K_PKT_TYPE_PIFS = 5, -} AR5K_PKT_TYPE; - -/* - * TX power and TPC settings - */ -#define AR5K_TXPOWER_OFDM(_r, _v) ( \ - ((0 & 1) << ((_v) + 6)) | \ - (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ -) - -#define AR5K_TXPOWER_CCK(_r, _v) ( \ - (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ -) - -/* - * Used to compute TX times - */ -#define AR5K_CCK_SIFS_TIME 10 -#define AR5K_CCK_PREAMBLE_BITS 144 -#define AR5K_CCK_PLCP_BITS 48 - -#define AR5K_OFDM_SIFS_TIME 16 -#define AR5K_OFDM_PREAMBLE_TIME 20 -#define AR5K_OFDM_PLCP_BITS 22 -#define AR5K_OFDM_SYMBOL_TIME 4 - -#define AR5K_TURBO_SIFS_TIME 8 -#define AR5K_TURBO_PREAMBLE_TIME 14 -#define AR5K_TURBO_PLCP_BITS 22 -#define AR5K_TURBO_SYMBOL_TIME 4 - -#define AR5K_XR_SIFS_TIME 16 -#define AR5K_XR_PLCP_BITS 22 -#define AR5K_XR_SYMBOL_TIME 4 - -/* CCK */ -#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) - -#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ - ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ - (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) - -#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ - AR5K_CCK_PHY_TIME(_sp) + \ - ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ - AR5K_CCK_SIFS_TIME - -/* OFDM */ -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_OFDM_SYMBOL_TIME) / 1000) - -#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ - AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ - (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) - -/* TURBO */ -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ - AR5K_TURBO_SYMBOL_TIME) / 1000) - -#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ - AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ - AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ - (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) - -/* eXtendent Range (?)*/ -#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) - -#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ - AR5K_XR_SYMBOL_TIME) / 1000) - -#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) - -#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) - -#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ - AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ - (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) - - - - -/****************\ - RX DEFINITIONS -\****************/ - -/* - * Rx Descriptor - */ -struct ath_rx_status { - u_int16_t rs_datalen; - u_int16_t rs_tstamp; - u_int8_t rs_status; - u_int8_t rs_phyerr; - int8_t rs_rssi; - u_int8_t rs_keyix; - u_int8_t rs_rate; - u_int8_t rs_antenna; - u_int8_t rs_more; -}; - -#define AR5K_RXERR_CRC 0x01 -#define AR5K_RXERR_PHY 0x02 -#define AR5K_RXERR_FIFO 0x04 -#define AR5K_RXERR_DECRYPT 0x08 -#define AR5K_RXERR_MIC 0x10 -#define AR5K_RXKEYIX_INVALID ((u_int8_t) - 1) -#define AR5K_TXKEYIX_INVALID ((u_int32_t) - 1) - -/* - * RX filters - * Most of them are not yet used inside OpenHAL - */ -#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ -#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ -#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ -#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ -#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ -#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ -#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame */ -#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests */ -#define AR5K_RX_FILTER_PHYERR 0x00000100 /* Don't filter phy errors */ -#define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ - -typedef struct { - u_int32_t ackrcv_bad; - u_int32_t rts_bad; - u_int32_t rts_good; - u_int32_t fcs_bad; - u_int32_t beacons; -} AR5K_MIB_STATS; - - - - -/**************************\ - BEACON TIMERS DEFINITIONS -\**************************/ - -#define AR5K_BEACON_PERIOD 0x0000ffff -#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ -#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ - -/* - * Per-station beacon timer state. - */ -typedef struct { - u_int32_t bs_next_beacon; - u_int32_t bs_next_dtim; - u_int32_t bs_interval; /*in TU's -see net80211/ieee80211_var.h- - can also include the above flags*/ - u_int8_t bs_dtim_period; - u_int8_t bs_cfp_period; - u_int16_t bs_cfp_max_duration; /*if non-zero hw is setup to coexist with - a Point Coordination Function capable AP*/ - u_int16_t bs_cfp_du_remain; - u_int16_t bs_tim_offset; - u_int16_t bs_sleep_duration; - u_int16_t bs_bmiss_threshold; - u_int32_t bs_cfp_next; -} AR5K_BEACON_STATE; - - - - -/********************\ - COMMON DEFINITIONS -\********************/ - -/* - * Atheros descriptor - */ -struct ath_desc { - u_int32_t ds_link; - u_int32_t ds_data; - u_int32_t ds_ctl0; - u_int32_t ds_ctl1; - u_int32_t ds_hw[4]; - - union { - struct ath_rx_status rx; - struct ath_tx_status tx; - } ds_us; - -#define ds_rxstat ds_us.rx -#define ds_txstat ds_us.tx - -} __packed; - -#define AR5K_RXDESC_INTREQ 0x0020 - -#define AR5K_TXDESC_CLRDMASK 0x0001 -#define AR5K_TXDESC_NOACK 0x0002 -#define AR5K_TXDESC_RTSENA 0x0004 -#define AR5K_TXDESC_CTSENA 0x0008 -#define AR5K_TXDESC_INTREQ 0x0010 -#define AR5K_TXDESC_VEOL 0x0020 - -/* - * 802.11 operating modes... - */ -#define AR5K_MODE_11A 0x01 -#define AR5K_MODE_11B 0x02 -#define AR5K_MODE_11G 0x04 -#define AR5K_MODE_TURBO 0x08 -#define AR5K_MODE_108G 0x16 -#define AR5K_MODE_XR 0x32 -#define AR5K_MODE_ALL (AR5K_MODE_11A| \ - AR5K_MODE_11B| \ - AR5K_MODE_11G| \ - AR5K_MODE_TURBO|\ - AR5K_MODE_108G| \ - AR5K_MODE_XR) - -/* - * Channel definitions - */ -typedef struct { - u_int16_t freq; /* setting in Mhz */ - u_int16_t channel_flags; - u_int8_t private_flags; /* not used in OpenHAL yet*/ -} AR5K_CHANNEL; - -#define AR5K_SLOT_TIME_9 396 -#define AR5K_SLOT_TIME_20 880 -#define AR5K_SLOT_TIME_MAX 0xffff - -/* channel_flags */ -#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ -#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ -#define CHANNEL_CCK 0x0020 /* CCK channel */ -#define CHANNEL_OFDM 0x0040 /* OFDM channel */ -#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ -#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ -#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ -#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation)*/ -#define CHANNEL_XR 0x0800 /* XR channel */ - -#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) -#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) -#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) -//#ifdef notdef -#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN) -//#else -//#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) -//#endif -#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) -#define CHANNEL_108A CHANNEL_T -#define CHANNEL_108G CHANNEL_TG -#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) - -#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ - CHANNEL_5GHZ | CHANNEL_TURBO) - -#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) -#define CHANNEL_MODES CHANNEL_ALL - -/* - * Used internaly in OpenHAL (ar5211.c/ar5212.c - * for reset_tx_queue). Also see struct AR5K_CHANNEL. - */ -#define IS_CHAN_XR(_c) \ - ((_c.channel_flags & CHANNEL_XR) != 0) - -#define IS_CHAN_B(_c) \ - ((_c.channel_flags & CHANNEL_B) != 0) - -typedef enum { - AR5K_CHIP_5GHZ = CHANNEL_5GHZ, - AR5K_CHIP_2GHZ = CHANNEL_2GHZ, -} AR5K_CHIP; - -/* - * The following structure will be used to map 2GHz channels to - * 5GHz Atheros channels. - */ -struct ar5k_athchan_2ghz { - u_int32_t a2_flags; - u_int16_t a2_athchan; -}; - -/* - * Rate definitions - */ - -#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ - -typedef struct { - u_int8_t valid; /* Valid for rate control */ - u_int32_t modulation; - u_int16_t rate_kbps; - u_int8_t rate_code; /* Rate mapping for h/w descriptors */ - u_int8_t dot11_rate; - u_int8_t control_rate; - u_int16_t lp_ack_duration;/* long preamble ACK duration */ - u_int16_t sp_ack_duration;/* short preamble ACK duration*/ -} AR5K_RATE; - -typedef struct { - u_int16_t rate_count; - u_int8_t rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ - AR5K_RATE rates[AR5K_MAX_RATES]; -} AR5K_RATE_TABLE; - -/* - * Rate tables... - */ -#define AR5K_RATES_11A { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_11B { 4, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ -} - -#define AR5K_RATES_11G { 12, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 3, 2, 1, 0, 255, 255, 255, 255 }, { \ - { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ - { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ - { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ - { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ - { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ - { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -#define AR5K_RATES_TURBO { 8, { \ - 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ - 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ - { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ - { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ - { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ - { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ - { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ - { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ - { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ -} - -#define AR5K_RATES_XR { 12, { \ - 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ - 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ - 255, 255, 255, 255, 255, 255, 255, 255 }, { \ - { 1, MODULATION_XR, 500, 7, 129, 0 }, \ - { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ - { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ - { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ - { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ - { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ - { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ - { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ - { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ - { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ - { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ - { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ -} - -/* - * Crypto definitions - */ - -/* key types */ -typedef enum { - AR5K_CIPHER_WEP = 0, - AR5K_CIPHER_AES_OCB = 1, - AR5K_CIPHER_AES_CCM = 2, - AR5K_CIPHER_CKIP = 3, - AR5K_CIPHER_TKIP = 4, - AR5K_CIPHER_CLR = 5, /* no encryption */ - AR5K_CIPHER_MIC = 127 /* used for Message - Integrity Code */ -} AR5K_CIPHER; - -#define AR5K_KEYVAL_LENGTH_40 5 -#define AR5K_KEYVAL_LENGTH_104 13 -#define AR5K_KEYVAL_LENGTH_128 16 -#define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128 - -typedef struct { - int wk_len; /* key's length */ - u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX]; - u_int8_t wk_type; /* see above */ - u_int8_t wk_mic[8]; /* TKIP MIC key */ -} AR5K_KEYVAL; - - - -/***********************\ - HW RELATED DEFINITIONS -\***********************/ - -/* - * Misc definitions - */ -#define AR5K_RSSI_EP_MULTIPLIER (1<<7) - -#define AR5K_ASSERT_ENTRY(_e, _s) do { \ - if (_e >= _s) \ - return (FALSE); \ -} while (0) - - -typedef struct { - u_int32_t ns_avgbrssi; /* average beacon rssi */ - u_int32_t ns_avgrssi; /* average data rssi */ - u_int32_t ns_avgtxrssi; /* average tx rssi */ -} AR5K_NODE_STATS; - -typedef enum { - AR5K_ANT_VARIABLE = 0, /* variable by programming */ - AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ - AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ - AR5K_ANT_MAX = 3, -} AR5K_ANT_SETTING; - -/* - * HAL interrupt abstraction - */ - -/* - * These are maped to take advantage of some common bits - * between the MAC chips, to be able to set intr properties - * easier. Some of them are not used yet inside OpenHAL. - */ -typedef enum { - AR5K_INT_RX = 0x00000001, - AR5K_INT_RXDESC = 0x00000002, - AR5K_INT_RXNOFRM = 0x00000008, - AR5K_INT_RXEOL = 0x00000010, - AR5K_INT_RXORN = 0x00000020, - AR5K_INT_TX = 0x00000040, - AR5K_INT_TXDESC = 0x00000080, - AR5K_INT_TXURN = 0x00000800, - AR5K_INT_MIB = 0x00001000, - AR5K_INT_RXPHY = 0x00004000, - AR5K_INT_RXKCM = 0x00008000, - AR5K_INT_SWBA = 0x00010000, - AR5K_INT_BMISS = 0x00040000, - AR5K_INT_BNR = 0x00100000, - AR5K_INT_GPIO = 0x01000000, - AR5K_INT_FATAL = 0x40000000, - AR5K_INT_GLOBAL = 0x80000000, - - /*A sum of all the common bits*/ - AR5K_INT_COMMON = AR5K_INT_RXNOFRM - | AR5K_INT_RXDESC - | AR5K_INT_RXEOL - | AR5K_INT_RXORN - | AR5K_INT_TXURN - | AR5K_INT_TXDESC - | AR5K_INT_MIB - | AR5K_INT_RXPHY - | AR5K_INT_RXKCM - | AR5K_INT_SWBA - | AR5K_INT_BMISS - | AR5K_INT_GPIO, - AR5K_INT_NOCARD = 0xffffffff /*Declare that the card - has been removed*/ -} AR5K_INT; - -/* - * Power management - */ -typedef enum { - AR5K_PM_UNDEFINED = 0, - AR5K_PM_AUTO, - AR5K_PM_AWAKE, - AR5K_PM_FULL_SLEEP, - AR5K_PM_NETWORK_SLEEP, -} AR5K_POWER_MODE; - - -/* - * LED states - */ -typedef int AR5K_LED_STATE; - -/* - * These match net80211 definitions (not used in - * d80211). - */ -#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ -#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ -#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ -#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ -#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ - -/* GPIO-controlled software LED */ -#define AR5K_SOFTLED_PIN 0 -#define AR5K_SOFTLED_ON 0 -#define AR5K_SOFTLED_OFF 1 - -/* - * Gain settings - */ -typedef enum { - AR5K_RFGAIN_INACTIVE = 0, - AR5K_RFGAIN_READ_REQUESTED, - AR5K_RFGAIN_NEED_CHANGE, -} AR5K_RFGAIN; - -#define AR5K_GAIN_CRN_FIX_BITS_5111 4 -#define AR5K_GAIN_CRN_FIX_BITS_5112 7 -#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 -#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 -#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 -#define AR5K_GAIN_CCK_PROBE_CORR 5 -#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 -#define AR5K_GAIN_STEP_COUNT 10 -#define AR5K_GAIN_PARAM_TX_CLIP 0 -#define AR5K_GAIN_PARAM_PD_90 1 -#define AR5K_GAIN_PARAM_PD_84 2 -#define AR5K_GAIN_PARAM_GAIN_SEL 3 -#define AR5K_GAIN_PARAM_MIX_ORN 0 -#define AR5K_GAIN_PARAM_PD_138 1 -#define AR5K_GAIN_PARAM_PD_137 2 -#define AR5K_GAIN_PARAM_PD_136 3 -#define AR5K_GAIN_PARAM_PD_132 4 -#define AR5K_GAIN_PARAM_PD_131 5 -#define AR5K_GAIN_PARAM_PD_130 6 -#define AR5K_GAIN_CHECK_ADJUST(_g) \ - ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) - -struct ar5k_gain_opt_step { - int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; - int32_t gos_gain; -}; - -struct ar5k_gain_opt { - u_int32_t go_default; - u_int32_t go_steps_count; - const struct ar5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; -}; - -struct ar5k_gain { - u_int32_t g_step_idx; - u_int32_t g_current; - u_int32_t g_target; - u_int32_t g_low; - u_int32_t g_high; - u_int32_t g_f_corr; - u_int32_t g_active; - const struct ar5k_gain_opt_step *g_step; -}; - -/* - * Gain optimization tables... - */ -#define AR5K_AR5111_GAIN_OPT { \ - 4, \ - 9, \ - { \ - { { 4, 1, 1, 1 }, 6 }, \ - { { 4, 0, 1, 1 }, 4 }, \ - { { 3, 1, 1, 1 }, 3 }, \ - { { 4, 0, 0, 1 }, 1 }, \ - { { 4, 1, 1, 0 }, 0 }, \ - { { 4, 0, 1, 0 }, -2 }, \ - { { 3, 1, 1, 0 }, -3 }, \ - { { 4, 0, 0, 0 }, -4 }, \ - { { 2, 1, 1, 0 }, -6 } \ - } \ -} - -#define AR5K_AR5112_GAIN_OPT { \ - 1, \ - 8, \ - { \ - { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \ - { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \ - { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \ - { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \ - { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \ - { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \ - { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \ - { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \ - } \ -} - -/* - * Common ar5xxx EEPROM data registers - */ -#define AR5K_EEPROM_MAGIC 0x003d -#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 -#define AR5K_EEPROM_PROTECT 0x003f -#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 -#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 -#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 -#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 -#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 -#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 -#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 -#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 -#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 -#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 -#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 -#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 -#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 -#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 -#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 -#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 -#define AR5K_EEPROM_REG_DOMAIN 0x00bf -#define AR5K_EEPROM_INFO_BASE 0x00c0 -#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) -#define AR5K_EEPROM_INFO_CKSUM 0xffff -#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) - -#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) -#define AR5K_EEPROM_VERSION_3_0 0x3000 -#define AR5K_EEPROM_VERSION_3_1 0x3001 -#define AR5K_EEPROM_VERSION_3_2 0x3002 -#define AR5K_EEPROM_VERSION_3_3 0x3003 -#define AR5K_EEPROM_VERSION_3_4 0x3004 -#define AR5K_EEPROM_VERSION_4_0 0x4000 -#define AR5K_EEPROM_VERSION_4_1 0x4001 -#define AR5K_EEPROM_VERSION_4_2 0x4002 -#define AR5K_EEPROM_VERSION_4_3 0x4003 -#define AR5K_EEPROM_VERSION_4_6 0x4006 -#define AR5K_EEPROM_VERSION_4_7 0x3007 - -#define AR5K_EEPROM_MODE_11A 0 -#define AR5K_EEPROM_MODE_11B 1 -#define AR5K_EEPROM_MODE_11G 2 - -#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) -#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) -#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) -#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) -#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) -#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) -#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) -#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) -#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) - -#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c -#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 -#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 -#define AR5K_EEPROM_RFKILL_POLARITY_S 1 - -/* Newer EEPROMs are using a different offset */ -#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ - (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) - -#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) -#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) -#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) - -#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) -#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) -#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) -#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) - -/* Since 3.1 */ -#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec -#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed - -/* Misc values available since EEPROM 4.0 */ -#define AR5K_EEPROM_MISC0 0x00c4 -#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) -#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) -#define AR5K_EEPROM_MISC1 0x00c5 -#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) -#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) - -/* Some EEPROM defines */ -#define AR5K_EEPROM_EEP_SCALE 100 -#define AR5K_EEPROM_EEP_DELTA 10 -#define AR5K_EEPROM_N_MODES 3 -#define AR5K_EEPROM_N_5GHZ_CHAN 10 -#define AR5K_EEPROM_N_2GHZ_CHAN 3 -#define AR5K_EEPROM_MAX_CHAN 10 -#define AR5K_EEPROM_N_PCDAC 11 -#define AR5K_EEPROM_N_TEST_FREQ 8 -#define AR5K_EEPROM_N_EDGES 8 -#define AR5K_EEPROM_N_INTERCEPTS 11 -#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) -#define AR5K_EEPROM_PCDAC_M 0x3f -#define AR5K_EEPROM_PCDAC_START 1 -#define AR5K_EEPROM_PCDAC_STOP 63 -#define AR5K_EEPROM_PCDAC_STEP 1 -#define AR5K_EEPROM_NON_EDGE_M 0x40 -#define AR5K_EEPROM_CHANNEL_POWER 8 -#define AR5K_EEPROM_N_OBDB 4 -#define AR5K_EEPROM_OBDB_DIS 0xffff -#define AR5K_EEPROM_CHANNEL_DIS 0xff -#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) -#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) -#define AR5K_EEPROM_MAX_CTLS 32 -#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 -#define AR5K_EEPROM_N_XPD0_POINTS 4 -#define AR5K_EEPROM_N_XPD3_POINTS 3 -#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 -#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 -#define AR5K_EEPROM_POWER_M 0x3f -#define AR5K_EEPROM_POWER_MIN 0 -#define AR5K_EEPROM_POWER_MAX 3150 -#define AR5K_EEPROM_POWER_STEP 50 -#define AR5K_EEPROM_POWER_TABLE_SIZE 64 -#define AR5K_EEPROM_N_POWER_LOC_11B 4 -#define AR5K_EEPROM_N_POWER_LOC_11G 6 -#define AR5K_EEPROM_I_GAIN 10 -#define AR5K_EEPROM_CCK_OFDM_DELTA 15 -#define AR5K_EEPROM_N_IQ_CAL 2 - -struct ar5k_eeprom_info { - u_int16_t ee_magic; - u_int16_t ee_protect; - u_int16_t ee_regdomain; - u_int16_t ee_version; - u_int16_t ee_header; - u_int16_t ee_ant_gain; - u_int16_t ee_misc0; - u_int16_t ee_misc1; - u_int16_t ee_cck_ofdm_gain_delta; - u_int16_t ee_cck_ofdm_power_delta; - u_int16_t ee_scaled_cck_delta; - u_int16_t ee_tx_clip; - u_int16_t ee_pwd_84; - u_int16_t ee_pwd_90; - u_int16_t ee_gain_select; - - u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES]; - u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES]; - u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES]; - u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES]; - u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES]; - u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; - u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; - u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; - u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; - u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_xpd[AR5K_EEPROM_N_MODES]; - u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES]; - u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; - u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; - u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; - u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; - - u_int16_t ee_ctls; - u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS]; - - int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; - int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; - int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; -}; - -/* - * AR5k register access - */ - -/*O.S. dependent functions are located in ah_osdep.h*/ -#define AR5K_REG_SM(_val, _flags) \ - (((_val) << _flags##_S) & (_flags)) - -#define AR5K_REG_MS(_val, _flags) \ - (((_val) & (_flags)) >> _flags##_S) - -#define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ - AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ - (((_val) << _flags##_S) & (_flags))) - -#define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \ - AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags)) - -#define AR5K_REG_ENABLE_BITS(_reg, _flags) \ - AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) - -#define AR5K_REG_DISABLE_BITS(_reg, _flags) \ - AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) - -#define AR5K_PHY_WRITE(_reg, _val) \ - AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val) - -#define AR5K_PHY_READ(_reg) \ - AR5K_REG_READ(hal->ah_phy + ((_reg) << 2)) - -#define AR5K_REG_WAIT(_i) \ - if (_i % 64) \ - AR5K_DELAY(1); - -#define AR5K_EEPROM_READ(_o, _v) { \ - if ((ret = hal->ah_eeprom_read(hal, (_o), \ - &(_v))) != 0) \ - return (ret); \ -} - -#define AR5K_EEPROM_READ_HDR(_o, _v) \ - AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ - -/* Read status of selected queue */ -#define AR5K_REG_READ_Q(_reg, _queue) \ - (AR5K_REG_READ(_reg) & (1 << _queue)) \ - -#define AR5K_REG_WRITE_Q(_reg, _queue) \ - AR5K_REG_WRITE(_reg, (1 << _queue)) - -#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ - _reg |= 1 << _queue; \ -} while (0) - -#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ - _reg &= ~(1 << _queue); \ -} while (0) - -/* - * Unaligned little endian access - */ -#define AR5K_LE_READ_2(_p) \ - (((const u_int8_t *)(_p))[0] | (((const u_int8_t *)(_p))[1] << 8)) -#define AR5K_LE_READ_4(_p) \ - (((const u_int8_t *)(_p))[0] | \ - (((const u_int8_t *)(_p))[1] << 8) | \ - (((const u_int8_t *)(_p))[2] << 16) | \ - (((const u_int8_t *)(_p))[3] << 24)) -#define AR5K_LE_WRITE_2(_p, _val) \ - ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ - (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff))) -#define AR5K_LE_WRITE_4(_p, _val) \ - ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ - (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \ - (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \ - (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff))) - -/* - * Initial register values - */ - -/* - * Common initial register values - */ -#define AR5K_INIT_MODE CHANNEL_B - -#define AR5K_INIT_TX_LATENCY 502 -#define AR5K_INIT_USEC 39 -#define AR5K_INIT_USEC_TURBO 79 -#define AR5K_INIT_USEC_32 31 -#define AR5K_INIT_CARR_SENSE_EN 1 -#define AR5K_INIT_PROG_IFS 920 -#define AR5K_INIT_PROG_IFS_TURBO 960 -#define AR5K_INIT_EIFS 3440 -#define AR5K_INIT_EIFS_TURBO 6880 -#define AR5K_INIT_SLOT_TIME 396 -#define AR5K_INIT_SLOT_TIME_TURBO 480 -#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 -#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 -#define AR5K_INIT_SIFS 560 -#define AR5K_INIT_SIFS_TURBO 480 -#define AR5K_INIT_SH_RETRY 10 -#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY -#define AR5K_INIT_SSH_RETRY 32 -#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY -#define AR5K_INIT_TX_RETRY 10 -#define AR5K_INIT_TOPS 8 -#define AR5K_INIT_RXNOFRM 8 -#define AR5K_INIT_RPGTO 0 -#define AR5K_INIT_TXNOFRM 0 -#define AR5K_INIT_BEACON_PERIOD 65535 -#define AR5K_INIT_TIM_OFFSET 0 -#define AR5K_INIT_BEACON_EN 0 -#define AR5K_INIT_RESET_TSF 0 - -#define AR5K_INIT_TRANSMIT_LATENCY ( \ - (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ - (AR5K_INIT_USEC) \ -) -#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ - (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ - (AR5K_INIT_USEC_TURBO) \ -) -#define AR5K_INIT_PROTO_TIME_CNTRL ( \ - (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ - (AR5K_INIT_PROG_IFS) \ -) -#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ - (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ - (AR5K_INIT_PROG_IFS_TURBO) \ -) -#define AR5K_INIT_BEACON_CONTROL ( \ - (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ - (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ -) - -#define AR5K_LOW_ID(_a) ( \ - (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ -) -#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) - -/* - * Non - common initial register values - */ -struct ar5k_ini { - u_int16_t ini_register; - u_int32_t ini_value; - - enum { - AR5K_INI_WRITE = 0, - AR5K_INI_READ = 1, - } ini_mode; -}; - -#define AR5K_INI_VAL_11A 0 -#define AR5K_INI_VAL_11A_TURBO 1 -#define AR5K_INI_VAL_11B 2 -#define AR5K_INI_VAL_11G 3 -#define AR5K_INI_VAL_11G_TURBO 4 -#define AR5K_INI_VAL_XR 0 -#define AR5K_INI_VAL_MAX 5 - -#define AR5K_INI_PHY_5111 0 -#define AR5K_INI_PHY_5112 1 -#define AR5K_INI_PHY_511X 1 - -#define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS -#define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS - -struct ar5k_ini_rf { - u_int8_t rf_bank; - u_int16_t rf_register; - u_int32_t rf_value[5]; -}; - -#define AR5K_AR5111_INI_RF { \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 0, 0x989c, \ - { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ - { 0, 0x989c, \ - { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ - { 0, 0x98d4, \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ - { 1, 0x98d4, \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d4, \ - { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ - { 3, 0x98d8, \ - { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ - { 6, 0x989c, \ - { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ - { 6, 0x989c, \ - { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ - { 6, 0x989c, \ - { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ - { 6, 0x989c, \ - { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ - { 6, 0x989c, \ - { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ - { 6, 0x98d4, \ - { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ - { 7, 0x989c, \ - { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ - { 7, 0x989c, \ - { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ - { 7, 0x989c, \ - { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ - { 7, 0x989c, \ - { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ - { 7, 0x989c, \ - { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ - { 7, 0x989c, \ - { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ - { 7, 0x989c, \ - { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ - { 7, 0x98cc, \ - { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ -} - -#define AR5K_AR5112_INI_RF { \ - { 1, 0x98d4, \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d0, \ - { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ - { 3, 0x98dc, \ - { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ - { 6, 0x989c, \ - { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ - { 6, 0x989c, \ - { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ - { 6, 0x989c, \ - { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ - { 6, 0x989c, \ - { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ - { 6, 0x989c, \ - { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ - { 6, 0x989c, \ - { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ - { 6, 0x989c, \ - { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ - { 6, 0x989c, \ - { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ - { 6, 0x989c, \ - { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ - { 6, 0x989c, \ - { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ - { 6, 0x989c, \ - { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ - { 6, 0x989c, \ - { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ - { 6, 0x989c, \ - { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ - { 6, 0x989c, \ - { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ - { 6, 0x989c, \ - { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ - { 6, 0x989c, \ - { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ - { 6, 0x989c, \ - { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ - { 6, 0x989c, \ - { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ - { 6, 0x989c, \ - { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ - { 6, 0x989c, \ - { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ - { 6, 0x989c, \ - { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ - { 6, 0x98d0, \ - { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ - { 7, 0x989c, \ - { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ - { 7, 0x989c, \ - { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ - { 7, 0x989c, \ - { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ - { 7, 0x989c, \ - { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ - { 7, 0x989c, \ - { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ - { 7, 0x989c, \ - { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ - { 7, 0x989c, \ - { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ - { 7, 0x989c, \ - { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ - { 7, 0x989c, \ - { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ - { 7, 0x989c, \ - { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ - { 7, 0x989c, \ - { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ - { 7, 0x989c, \ - { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ - { 7, 0x98c4, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ - } - -#define AR5K_AR5112A_INI_RF { \ - { 1, 0x98d4, \ - { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ - { 2, 0x98d0, \ - { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ - { 3, 0x98dc, \ - { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ - { 6, 0x989c, \ - { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ - { 6, 0x989c, \ - { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ - { 6, 0x989c, \ - { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ - { 6, 0x989c, \ - { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ - { 6, 0x989c, \ - { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ - { 6, 0x989c, \ - { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ - { 6, 0x989c, \ - { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ - { 6, 0x989c, \ - { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ - { 6, 0x989c, \ - { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ - { 6, 0x989c, \ - { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ - { 6, 0x989c, \ - { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ - { 6, 0x989c, \ - { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ - { 6, 0x989c, \ - { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ - { 6, 0x989c, \ - { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ - { 6, 0x989c, \ - { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ - { 6, 0x989c, \ - { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ - { 6, 0x989c, \ - { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ - { 6, 0x989c, \ - { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ - { 6, 0x989c, \ - { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ - { 6, 0x989c, \ - { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ - { 6, 0x989c, \ - { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ - { 6, 0x989c, \ - { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ - { 6, 0x989c, \ - { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ - { 6, 0x989c, \ - { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ - { 6, 0x989c, \ - { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ - { 6, 0x989c, \ - { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ - { 6, 0x989c, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ - { 6, 0x989c, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ - { 6, 0x989c, \ - { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ - { 6, 0x989c, \ - { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ - { 6, 0x989c, \ - { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ - { 6, 0x989c, \ - { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ - { 6, 0x989c, \ - { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ - { 6, 0x98d8, \ - { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ - { 7, 0x989c, \ - { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ - { 7, 0x989c, \ - { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ - { 7, 0x989c, \ - { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ - { 7, 0x989c, \ - { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ - { 7, 0x989c, \ - { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ - { 7, 0x989c, \ - { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ - { 7, 0x989c, \ - { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ - { 7, 0x989c, \ - { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ - { 7, 0x989c, \ - { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ - { 7, 0x989c, \ - { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ - { 7, 0x989c, \ - { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ - { 7, 0x989c, \ - { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ - { 7, 0x98c4, \ - { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ -} - -struct ar5k_ini_rfgain { - u_int16_t rfg_register; - u_int32_t rfg_value[2][2]; - -#define AR5K_INI_RFGAIN_5GHZ 0 -#define AR5K_INI_RFGAIN_2GHZ 1 -}; - -#define AR5K_INI_RFGAIN { \ - { 0x9a00, { \ - { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ - { 0x9a04, { \ - { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ - { 0x9a08, { \ - { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ - { 0x9a0c, { \ - { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ - { 0x9a10, { \ - { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ - { 0x9a14, { \ - { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ - { 0x9a18, { \ - { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ - { 0x9a1c, { \ - { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ - { 0x9a20, { \ - { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ - { 0x9a24, { \ - { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ - { 0x9a28, { \ - { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ - { 0x9a2c, { \ - { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ - { 0x9a30, { \ - { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ - { 0x9a34, { \ - { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ - { 0x9a38, { \ - { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ - { 0x9a3c, { \ - { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ - { 0x9a40, { \ - { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ - { 0x9a44, { \ - { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ - { 0x9a48, { \ - { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ - { 0x9a4c, { \ - { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ - { 0x9a50, { \ - { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ - { 0x9a54, { \ - { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ - { 0x9a58, { \ - { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ - { 0x9a5c, { \ - { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ - { 0x9a60, { \ - { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ - { 0x9a64, { \ - { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ - { 0x9a68, { \ - { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ - { 0x9a6c, { \ - { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ - { 0x9a70, { \ - { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ - { 0x9a74, { \ - { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ - { 0x9a78, { \ - { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ - { 0x9a7c, { \ - { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ - { 0x9a80, { \ - { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ - { 0x9a84, { \ - { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ - { 0x9a88, { \ - { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ - { 0x9a8c, { \ - { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ - { 0x9a90, { \ - { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ - { 0x9a94, { \ - { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ - { 0x9a98, { \ - { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ - { 0x9a9c, { \ - { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ - { 0x9aa0, { \ - { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ - { 0x9aa4, { \ - { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ - { 0x9aa8, { \ - { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ - { 0x9aac, { \ - { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ - { 0x9ab0, { \ - { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ - { 0x9ab4, { \ - { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ - { 0x9ab8, { \ - { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ - { 0x9abc, { \ - { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ - { 0x9ac0, { \ - { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ - { 0x9ac4, { \ - { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ - { 0x9ac8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ - { 0x9acc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ - { 0x9ad0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ - { 0x9ad4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ - { 0x9ad8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9adc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9aec, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9afc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ -} - -/* - * Chipset capabilities -see ath_hal_getcapability- - * get_capability function is not yet fully implemented - * in OpenHAL so most of these don't work yet... - */ -typedef enum { - AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ - AR5K_CAP_CIPHER = 1, /* Can handle encryption */ - AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ - AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ - AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ - AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ - AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ - AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ - AR5K_CAP_COMPRESSION = 8, /* Supports compression */ - AR5K_CAP_BURST = 9, /* Supports packet bursting */ - AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ - AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ - AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ - AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ - AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ - AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ - AR5K_CAP_XR = 16, /* Supports XR mode */ - AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ - AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ - AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ - AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ -} AR5K_CAPABILITY_TYPE; - -typedef struct { - /* - * Supported PHY modes - * (ie. CHANNEL_A, CHANNEL_B, ...) - */ - u_int16_t cap_mode; - - /* - * Frequency range (without regulation restrictions) - */ - struct { - u_int16_t range_2ghz_min; - u_int16_t range_2ghz_max; - u_int16_t range_5ghz_min; - u_int16_t range_5ghz_max; - } cap_range; - - /* - * Active regulation domain settings - */ - struct { - ieee80211_regdomain_t reg_current; - ieee80211_regdomain_t reg_hw; - } cap_regdomain; - - /* - * Values stored in the EEPROM (some of them...) - */ - struct ar5k_eeprom_info cap_eeprom; - - /* - * Queue information - */ - struct { - u_int8_t q_tx_num; - } cap_queues; -} ar5k_capabilities_t; - - - - -/***************************************\ - HARDWARE ABSTRACTION LAYER STRUCTURE -\***************************************/ - -/* - * Regulation stuff - */ -typedef enum ieee80211_countrycode AR5K_CTRY_CODE; - -/* Default regulation domain if stored value EEPROM value is invalid */ -#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ -#define AR5K_TUNE_CTRY CTRY_DEFAULT - -/* - * Misc defines - */ -#define AR5K_ABI_VERSION 0x04090901 /* YYMMDDnn */ - -#define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0])) - -typedef struct ath_hal * (ar5k_attach_t) - (u_int16_t, AR5K_SOFTC, AR5K_BUS_TAG, AR5K_BUS_HANDLE, AR5K_STATUS *); - -typedef AR5K_BOOL (ar5k_rfgain_t) - (struct ath_hal *, AR5K_CHANNEL *, u_int); - -/* - * HAL Functions that have different implementations for each chipset... - */ -#define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ar5k_##_n##_##_f -#define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ - _t const AR5K_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, u_int mode); \ - _t void (_a _n##_detach)(struct ath_hal *); \ - /* Reset functions */ \ - _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, AR5K_OPMODE, AR5K_CHANNEL *, \ - AR5K_BOOL change_channel, AR5K_STATUS *status); \ - _t void (_a _n##_set_opmode)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ - /* Transmit functions */ \ - _t AR5K_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, AR5K_BOOL level); \ - _t int (_a _n##_setup_tx_queue)(struct ath_hal *, AR5K_TX_QUEUE, AR5K_TXQ_INFO *); \ - _t AR5K_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ - const AR5K_TXQ_INFO *); \ - _t AR5K_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ - _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u_int32_t phys_addr); \ - _t AR5K_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ - _t AR5K_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, \ - u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index,\ - u_int antenna_mode, u_int flags, u_int rtscts_rate, \ - u_int rtscts_duration); \ - _t AR5K_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ - u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ - _t AR5K_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ - AR5K_BOOL firstSeg, AR5K_BOOL lastSeg, const struct ath_desc *);\ - _t AR5K_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ - _t AR5K_BOOL (_a _n##_has_veol)(struct ath_hal *); \ - /* Receive Functions */ \ - _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \ - _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \ - _t void (_a _n##_start_rx)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \ - _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \ - _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \ - _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u_int32_t filter0, \ - u_int32_t filter1); \ - _t AR5K_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, u_int32_t index); \ - _t AR5K_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*,u_int32_t index); \ - _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \ - _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \ - _t AR5K_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t size, u_int flags); \ - _t AR5K_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t phyAddr, struct ath_desc *next); \ - _t void (_a _n##_set_rx_signal)(struct ath_hal *, const AR5K_NODE_STATS *); \ - /* Misc Functions */ \ - _t void (_a _n##_dump_state)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ - u_int32_t argsize, void **result, u_int32_t *resultsize); \ - _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \ - _t AR5K_BOOL (_a _n##_set_lladdr)(struct ath_hal *, const u_int8_t*); \ - _t AR5K_BOOL (_a _n##_set_regdomain)(struct ath_hal*, u_int16_t, AR5K_STATUS *); \ - _t void (_a _n##_set_ledstate)(struct ath_hal*, AR5K_LED_STATE); \ - _t void (_a _n##_set_associd)(struct ath_hal*, const u_int8_t *bssid, \ - u_int16_t assocId); \ - _t AR5K_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, u_int32_t gpio); \ - _t AR5K_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, u_int32_t gpio); \ - _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \ - _t AR5K_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, u_int32_t val); \ - _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \ - _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \ - _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \ - _t void (_a _n##_reset_tsf)(struct ath_hal*); \ - _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \ - _t void (_a _n##_update_mib_counters)(struct ath_hal*, AR5K_MIB_STATS*); \ - _t AR5K_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \ - _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ - _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \ - _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \ - /* Key Cache Functions */ \ - _t AR5K_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, AR5K_CIPHER); \ - _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_reset_key)(struct ath_hal*, u_int16_t); \ - _t AR5K_BOOL (_a _n##_is_key_valid)(struct ath_hal *, u_int16_t); \ - _t AR5K_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, const AR5K_KEYVAL *, \ - const u_int8_t *, int); \ - _t AR5K_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, u_int16_t, const u_int8_t *); \ - /* Power Management Functions */ \ - _t AR5K_BOOL (_a _n##_set_power)(struct ath_hal*, AR5K_POWER_MODE mode, \ - AR5K_BOOL set_chip, u_int16_t sleep_duration); \ - _t AR5K_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \ - _t AR5K_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, u_int16_t); \ - _t AR5K_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \ - /* Beacon Management Functions */ \ - _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, u_int32_t intval); \ - _t void (_a _n##_set_beacon_timers)(struct ath_hal *, const AR5K_BEACON_STATE *); \ - _t void (_a _n##_reset_beacon)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, AR5K_BUS_ADDR); \ - /* Interrupt functions */ \ - _t AR5K_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_get_isr)(struct ath_hal *, u_int32_t *); \ - _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \ - _t AR5K_INT (_a _n##_set_intr)(struct ath_hal *, AR5K_INT); \ - /* Chipset functions (ar5k-specific, non-HAL) */ \ - _t AR5K_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \ - _t void (_a _n##_radar_alert)(struct ath_hal *, AR5K_BOOL enable); \ - _t AR5K_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \ - _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, u_int16_t *data); \ - _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, u_int16_t data); \ - /* Functions not found in OpenBSD */ \ - _t AR5K_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, AR5K_TXQ_INFO *); \ - _t AR5K_STATUS (_a _n##_get_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, \ - u_int32_t, u_int32_t *); \ - _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ - _t AR5K_BOOL (_a _n##_phy_disable)(struct ath_hal *); \ - _t void (_a _n##_set_pcu_config)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ - _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \ - _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n ##_set_bssid_mask)(struct ath_hal *, const u_int8_t*); \ - /*Totaly unimplemented*/ \ - _t AR5K_BOOL (_a _n##_set_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, u_int32_t,\ - u_int32_t,AR5K_STATUS *) ; \ - _t void (_a _n##_proc_mib_event)(struct ath_hal *, const AR5K_NODE_STATS *) ; \ - _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *); - - -#define AR5K_MAX_GPIO 10 -#define AR5K_MAX_RF_BANKS 8 - -struct ath_hal { - u_int32_t ah_magic; - u_int16_t ah_device; - u_int16_t ah_sub_vendor; - - AR5K_SOFTC ah_sc; - bus_space_tag_t ah_st; - bus_space_handle_t ah_sh; - AR5K_CTRY_CODE ah_country_code; - - AR5K_INT ah_imr; - - AR5K_OPMODE ah_op_mode; - AR5K_POWER_MODE ah_power_mode; - AR5K_CHANNEL ah_current_channel; - AR5K_BOOL ah_turbo; - AR5K_BOOL ah_calibration; - AR5K_BOOL ah_running; - AR5K_BOOL ah_single_chip; - AR5K_RFGAIN ah_rf_gain; - - AR5K_RATE_TABLE ah_rt_11a; - AR5K_RATE_TABLE ah_rt_11b; - AR5K_RATE_TABLE ah_rt_11g; - AR5K_RATE_TABLE ah_rt_turbo; - AR5K_RATE_TABLE ah_rt_xr; - - u_int32_t ah_mac_srev; - u_int16_t ah_mac_version; - u_int16_t ah_mac_revision; - u_int16_t ah_phy_revision; - u_int16_t ah_radio_5ghz_revision; - u_int16_t ah_radio_2ghz_revision; - - enum ar5k_version ah_version; - enum ar5k_radio ah_radio; - u_int32_t ah_phy; - - AR5K_BOOL ah_5ghz; - AR5K_BOOL ah_2ghz; - -#define ah_regdomain ah_capabilities.cap_regdomain.reg_current -#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw -#define ah_modes ah_capabilities.cap_mode -#define ah_ee_version ah_capabilities.cap_eeprom.ee_version - - u_int32_t ah_atim_window; - u_int32_t ah_aifs; - u_int32_t ah_cw_min; - u_int32_t ah_cw_max; - AR5K_BOOL ah_software_retry; - u_int32_t ah_limit_tx_retries; - - u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; - AR5K_BOOL ah_ant_diversity; - - u_int8_t ah_sta_id[IEEE80211_ADDR_LEN]; - u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; - - u_int32_t ah_gpio[AR5K_MAX_GPIO]; - int ah_gpio_npins; - - ar5k_capabilities_t ah_capabilities; - - AR5K_TXQ_INFO ah_txq[AR5K_NUM_TX_QUEUES]; - u_int32_t ah_txq_interrupts; - - u_int32_t *ah_rf_banks; - size_t ah_rf_banks_size; - struct ar5k_gain ah_gain; - u_int32_t ah_offset[AR5K_MAX_RF_BANKS]; - - struct { - u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; - u_int16_t txp_rates[AR5K_MAX_RATES]; - int16_t txp_min, txp_max; - AR5K_BOOL txp_tpc; - int16_t txp_ofdm; - } ah_txpower; - - struct { - AR5K_BOOL r_enabled; - int r_last_alert; - AR5K_CHANNEL r_last_channel; - } ah_radar; - - /* - * Function pointers - */ - AR5K_HAL_FUNCTIONS(, ah, *) - -}; - -/* - * Prototypes -functions common for all chipsets- - */ - - -const char *ath_hal_probe(u_int16_t, u_int16_t); -struct ath_hal *ath_hal_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG, - AR5K_BUS_HANDLE, AR5K_STATUS *); -u_int16_t ath_hal_computetxtime(struct ath_hal *, const AR5K_RATE_TABLE *, - u_int32_t, u_int16_t, AR5K_BOOL); -u_int ath_hal_mhz2ieee(u_int, u_int); -u_int ath_hal_ieee2mhz(u_int, u_int); -AR5K_BOOL ath_hal_init_channels(struct ath_hal *, AR5K_CHANNEL *, - u_int, u_int *, AR5K_CTRY_CODE, u_int16_t, - AR5K_BOOL, AR5K_BOOL); -const char *ar5k_printver(enum ar5k_srev_type, u_int32_t); -void ar5k_radar_alert(struct ath_hal *); -ieee80211_regdomain_t ar5k_regdomain_to_ieee(u_int16_t); -u_int16_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t); -u_int16_t ar5k_get_regdomain(struct ath_hal *); -u_int32_t ar5k_bitswap(u_int32_t, u_int); -u_int ar5k_clocktoh(u_int, AR5K_BOOL); -u_int ar5k_htoclock(u_int, AR5K_BOOL); -void ar5k_rt_copy(AR5K_RATE_TABLE *, const AR5K_RATE_TABLE *); -AR5K_BOOL ar5k_register_timeout(struct ath_hal *, u_int32_t, u_int32_t, - u_int32_t, AR5K_BOOL); -int ar5k_eeprom_init(struct ath_hal *); -int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); -AR5K_BOOL ar5k_eeprom_regulation_domain(struct ath_hal *, AR5K_BOOL, - ieee80211_regdomain_t *); -AR5K_BOOL ar5k_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ar5k_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -u_int32_t ar5k_rfregs_gainf_corr(struct ath_hal *); -AR5K_BOOL ar5k_rfregs_gain_readback(struct ath_hal *); -int32_t ar5k_rfregs_gain_adjust(struct ath_hal *); -AR5K_BOOL ar5k_rfgain(struct ath_hal *, u_int, u_int); -void ar5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); - -/*added*/ -extern u_int ath_hal_getwirelessmodes(struct ath_hal*, AR5K_CTRY_CODE); -void ath_hal_detach(struct ath_hal *ah); -struct ath_hal * _ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, AR5K_BUS_TAG t, - AR5K_BUS_HANDLE h, void* s); -#endif /* _AR5K_H */ Index: ar5210.c =================================================================== --- ar5210.c (revision 2185) +++ ar5210.c (revision 2232) @@ -1,2500 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for the Atheros AR5000 Wireless LAN chipset - * (AR5210 + AR5110). - */ - -#include "ar5xxx.h" -#include "ar5210reg.h" -#include "ar5210var.h" - -AR5K_BOOL ar5k_ar5210_nic_reset(struct ath_hal *, u_int32_t); -AR5K_BOOL ar5k_ar5210_nic_wakeup(struct ath_hal *, AR5K_BOOL, AR5K_BOOL); -void ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, AR5K_BOOL); -void ar5k_ar5210_fill(struct ath_hal *); -AR5K_BOOL ar5k_ar5210_do_calibrate(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ar5k_ar5210_noise_floor(struct ath_hal *, AR5K_CHANNEL *); - -/* - * Initial register setting for the AR5210 - */ -static const struct ar5k_ini ar5210_ini[] = - AR5K_AR5210_INI; - -AR5K_HAL_FUNCTIONS(extern, ar5k_ar5210,); - -void -ar5k_ar5210_fill(struct ath_hal *hal) -{ - hal->ah_magic = AR5K_AR5210_MAGIC; - - /* - * Init/Exit functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, get_rate_table); - AR5K_HAL_FUNCTION(hal, ar5210, detach); - - /* - * Reset functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, reset); - AR5K_HAL_FUNCTION(hal, ar5210, set_opmode); - AR5K_HAL_FUNCTION(hal, ar5210, calibrate); - - /* - * TX functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, update_tx_triglevel); - AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queueprops); - AR5K_HAL_FUNCTION(hal, ar5210, release_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5210, reset_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5210, get_tx_buf); - AR5K_HAL_FUNCTION(hal, ar5210, put_tx_buf); - AR5K_HAL_FUNCTION(hal, ar5210, tx_start); - AR5K_HAL_FUNCTION(hal, ar5210, stop_tx_dma); - AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5210, setup_xtx_desc); - AR5K_HAL_FUNCTION(hal, ar5210, fill_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5210, proc_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5210, has_veol); - - /* - * RX functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, get_rx_buf); - AR5K_HAL_FUNCTION(hal, ar5210, put_rx_buf); - AR5K_HAL_FUNCTION(hal, ar5210, start_rx); - AR5K_HAL_FUNCTION(hal, ar5210, stop_rx_dma); - AR5K_HAL_FUNCTION(hal, ar5210, start_rx_pcu); - AR5K_HAL_FUNCTION(hal, ar5210, stop_pcu_recv); - AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filter); - AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filterindex); - AR5K_HAL_FUNCTION(hal, ar5210, clear_mcast_filter_idx); - AR5K_HAL_FUNCTION(hal, ar5210, get_rx_filter); - AR5K_HAL_FUNCTION(hal, ar5210, set_rx_filter); - AR5K_HAL_FUNCTION(hal, ar5210, setup_rx_desc); - AR5K_HAL_FUNCTION(hal, ar5210, proc_rx_desc); - AR5K_HAL_FUNCTION(hal, ar5210, set_rx_signal); - - /* - * Misc functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, dump_state); - AR5K_HAL_FUNCTION(hal, ar5210, get_diag_state); - AR5K_HAL_FUNCTION(hal, ar5210, get_lladdr); - AR5K_HAL_FUNCTION(hal, ar5210, set_lladdr); - AR5K_HAL_FUNCTION(hal, ar5210, set_regdomain); - AR5K_HAL_FUNCTION(hal, ar5210, set_ledstate); - AR5K_HAL_FUNCTION(hal, ar5210, set_associd); - AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_input); - AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_output); - AR5K_HAL_FUNCTION(hal, ar5210, get_gpio); - AR5K_HAL_FUNCTION(hal, ar5210, set_gpio); - AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_intr); - AR5K_HAL_FUNCTION(hal, ar5210, get_tsf32); - AR5K_HAL_FUNCTION(hal, ar5210, get_tsf64); - AR5K_HAL_FUNCTION(hal, ar5210, reset_tsf); - AR5K_HAL_FUNCTION(hal, ar5210, get_regdomain); - AR5K_HAL_FUNCTION(hal, ar5210, detect_card_present); - AR5K_HAL_FUNCTION(hal, ar5210, update_mib_counters); - AR5K_HAL_FUNCTION(hal, ar5210, get_rf_gain); - AR5K_HAL_FUNCTION(hal, ar5210, set_slot_time); - AR5K_HAL_FUNCTION(hal, ar5210, get_slot_time); - AR5K_HAL_FUNCTION(hal, ar5210, set_ack_timeout); - AR5K_HAL_FUNCTION(hal, ar5210, get_ack_timeout); - AR5K_HAL_FUNCTION(hal, ar5210, set_cts_timeout); - AR5K_HAL_FUNCTION(hal, ar5210, get_cts_timeout); - - /* - * Key table (WEP) functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, is_cipher_supported); - AR5K_HAL_FUNCTION(hal, ar5210, get_keycache_size); - AR5K_HAL_FUNCTION(hal, ar5210, reset_key); - AR5K_HAL_FUNCTION(hal, ar5210, is_key_valid); - AR5K_HAL_FUNCTION(hal, ar5210, set_key); - AR5K_HAL_FUNCTION(hal, ar5210, set_key_lladdr); - - /* - * Power management functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, set_power); - AR5K_HAL_FUNCTION(hal, ar5210, get_power_mode); - AR5K_HAL_FUNCTION(hal, ar5210, query_pspoll_support); - AR5K_HAL_FUNCTION(hal, ar5210, init_pspoll); - AR5K_HAL_FUNCTION(hal, ar5210, enable_pspoll); - AR5K_HAL_FUNCTION(hal, ar5210, disable_pspoll); - - /* - * Beacon functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, init_beacon); - AR5K_HAL_FUNCTION(hal, ar5210, set_beacon_timers); - AR5K_HAL_FUNCTION(hal, ar5210, reset_beacon); - AR5K_HAL_FUNCTION(hal, ar5210, wait_for_beacon); - - /* - * Interrupt functions - */ - AR5K_HAL_FUNCTION(hal, ar5210, is_intr_pending); - AR5K_HAL_FUNCTION(hal, ar5210, get_isr); - AR5K_HAL_FUNCTION(hal, ar5210, get_intr); - AR5K_HAL_FUNCTION(hal, ar5210, set_intr); - - /* - * Chipset functions (ar5k-specific, non-HAL) - */ - AR5K_HAL_FUNCTION(hal, ar5210, get_capabilities); - AR5K_HAL_FUNCTION(hal, ar5210, radar_alert); - - /* - * EEPROM access - */ - AR5K_HAL_FUNCTION(hal, ar5210, eeprom_is_busy); - AR5K_HAL_FUNCTION(hal, ar5210, eeprom_read); - AR5K_HAL_FUNCTION(hal, ar5210, eeprom_write); - - /* Functions not found in OpenBSD */ - AR5K_HAL_FUNCTION(hal, ar5210, get_tx_queueprops); - AR5K_HAL_FUNCTION(hal, ar5210, get_capability); - AR5K_HAL_FUNCTION(hal, ar5210, num_tx_pending); - AR5K_HAL_FUNCTION(hal, ar5210, phy_disable); - AR5K_HAL_FUNCTION(hal, ar5210, set_pcu_config); - AR5K_HAL_FUNCTION(hal, ar5210, set_txpower_limit); - AR5K_HAL_FUNCTION(hal, ar5210, set_def_antenna); - AR5K_HAL_FUNCTION(hal, ar5210, get_def_antenna); - AR5K_HAL_FUNCTION(hal, ar5210, set_bssid_mask); - /*Totaly unimplemented*/ - AR5K_HAL_FUNCTION(hal, ar5210, set_capability); - AR5K_HAL_FUNCTION(hal, ar5210, proc_mib_event); - AR5K_HAL_FUNCTION(hal, ar5210, get_tx_inter_queue); - -} - -struct ath_hal * /*Ported & removed an arg from call to set_associd*/ -ar5k_ar5210_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, - AR5K_BUS_HANDLE sh, AR5K_STATUS *status) -{ - int i; - struct ath_hal *hal = (struct ath_hal*) sc; - u_int8_t mac[IEEE80211_ADDR_LEN]; - u_int32_t srev; - - ar5k_ar5210_fill(hal); - - /* Bring device out of sleep and reset it's units */ - if (ar5k_ar5210_nic_wakeup(hal, FALSE, TRUE) != TRUE) - return (NULL); - - /* Get MAC, PHY and RADIO revisions */ - srev = AR5K_REG_READ(AR5K_AR5210_SREV); - hal->ah_mac_srev = srev; - hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5210_SREV_VER); - hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5210_SREV_REV); - hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5210_PHY_CHIP_ID) & - 0x00ffffffff; - - /* ...wait until PHY is ready and read RADIO revision */ - AR5K_REG_WRITE(AR5K_AR5210_PHY(0x34), 0x00001c16); - for (i = 0; i < 4; i++) - AR5K_REG_WRITE(AR5K_AR5210_PHY(0x20), 0x00010000); - hal->ah_radio_5ghz_revision = (u_int16_t) - (ar5k_bitswap((AR5K_REG_READ(AR5K_AR5210_PHY(256) >> 28) & 0xf), 4) - + 1); - hal->ah_radio_2ghz_revision = 0; - - /* Identify the chipset */ - hal->ah_version = AR5K_AR5210; - hal->ah_radio = AR5K_AR5110; - hal->ah_phy = AR5K_AR5210_PHY(0); - - bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); - ar5k_ar5210_set_associd(hal, mac, 0); - ar5k_ar5210_get_lladdr(hal, mac); - ar5k_ar5210_set_opmode(hal); - - return (hal); -} - -AR5K_BOOL -ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val) -{ - AR5K_BOOL ret = FALSE; - u_int32_t mask = val ? val : ~0; - - /* - * Reset the device and wait until success - */ - AR5K_REG_WRITE(AR5K_AR5210_RC, val); - - /* Wait at least 128 PCI clocks */ - AR5K_DELAY(15); - - val &= - AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC | - AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA; - - mask &= - AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC | - AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA; - - ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, FALSE); - - /* - * Reset configuration register - */ - if ((val & AR5K_AR5210_RC_MAC) == 0) { - AR5K_REG_WRITE(AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG); - } - - return (ret); -} - -AR5K_BOOL -ar5k_ar5210_nic_wakeup(struct ath_hal *hal, AR5K_BOOL turbo, AR5K_BOOL initial) -{ - /* - * Reset and wakeup the device - */ - - if (initial == TRUE) { - /* ...reset hardware */ - if (ar5k_ar5210_nic_reset(hal, - AR5K_AR5210_RC_PCI) == FALSE) { - AR5K_PRINT("failed to reset the PCI chipset\n"); - return (FALSE); - } - - AR5K_DELAY(1000); - } - - /* ...wakeup the device */ - if (ar5k_ar5210_set_power(hal, - AR5K_PM_AWAKE, TRUE, 0) == FALSE) { - AR5K_PRINT("failed to resume the AR5210 chipset\n"); - return (FALSE); - } - - /* ...enable Atheros turbo mode if requested */ - AR5K_REG_WRITE(AR5K_AR5210_PHY_FC, - turbo == TRUE ? AR5K_AR5210_PHY_FC_TURBO_MODE : 0); - - /* ...reset chipset */ - if (ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == FALSE) { - AR5K_PRINT("failed to reset the AR5210 chipset\n"); - return (FALSE); - } - - AR5K_DELAY(1000); - - /* ...reset chipset and PCI device */ - if (ar5k_ar5210_nic_reset(hal, - AR5K_AR5210_RC_CHIP | AR5K_AR5210_RC_PCI) == FALSE) { - AR5K_PRINT("failed to reset the AR5210 + PCI chipset\n"); - return (FALSE); - } - - AR5K_DELAY(2300); - - /* ...wakeup (again) */ - if (ar5k_ar5210_set_power(hal, - AR5K_PM_AWAKE, TRUE, 0) == FALSE) { - AR5K_PRINT("failed to resume the AR5210 (again)\n"); - return (FALSE); - } - - /* ...final warm reset */ - if (ar5k_ar5210_nic_reset(hal, 0) == FALSE) { - AR5K_PRINT("failed to warm reset the AR5210\n"); - return (FALSE); - } - - return (TRUE); -} - -const AR5K_RATE_TABLE * -ar5k_ar5210_get_rate_table(struct ath_hal *hal, u_int mode) -{ - switch (mode) { - case AR5K_MODE_11A: - return (&hal->ah_rt_11a); - case AR5K_MODE_TURBO: - return (&hal->ah_rt_turbo); - case AR5K_MODE_11B: - case AR5K_MODE_11G: - default: - return (NULL); - } - - return (NULL); -} - -void /*Ported*/ -ar5k_ar5210_detach(struct ath_hal *hal) -{ - /* - * Free HAL structure, assume interrupts are down - */ - free(hal, M_DEVBUF); -} - -AR5K_BOOL /*New*/ -ar5k_ar5210_phy_disable(struct ath_hal *hal) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); - return TRUE; -} - -AR5K_BOOL -ar5k_ar5210_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, - AR5K_BOOL change_channel, AR5K_STATUS *status) -{ - int i; - - /* Not used, keep for HAL compatibility */ - *status = AR5K_OK; - - if (ar5k_ar5210_nic_wakeup(hal, - channel->channel_flags & CHANNEL_T ? - TRUE : FALSE, FALSE) == FALSE) - return (FALSE); - - /* - * Initialize operating mode - */ - hal->ah_op_mode = op_mode; - ar5k_ar5210_set_opmode(hal); - - /* - * Write initial mode register settings - */ - for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) { - if (change_channel == TRUE && - ar5210_ini[i].ini_register >= AR5K_AR5210_PCU_MIN && - ar5210_ini[i].ini_register <= AR5K_AR5210_PCU_MAX) - continue; - - switch (ar5210_ini[i].ini_mode) { - case AR5K_INI_READ: - /* Cleared on read */ - AR5K_REG_READ(ar5210_ini[i].ini_register); - break; - - case AR5K_INI_WRITE: - default: - AR5K_REG_WRITE(ar5210_ini[i].ini_register, - ar5210_ini[i].ini_value); - } - } - - AR5K_DELAY(1000); - - /* - * Set channel and calibrate the PHY - */ - - /* Disable phy and wait */ - AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); - AR5K_DELAY(1000); - - if (ar5k_channel(hal, channel) == FALSE) - return (FALSE); - - /* - * Activate phy and wait - */ - AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE); - AR5K_DELAY(1000); - - ar5k_ar5210_do_calibrate(hal, channel); - if (ar5k_ar5210_noise_floor(hal, channel) == FALSE) - return (FALSE); - - /* - * Set RF kill flags if supported by the device (read from the EEPROM) - */ -/* if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { - ar5k_ar5210_set_gpio_input(hal, 0); - if ((hal->ah_gpio[0] = ar5k_ar5210_get_gpio(hal, 0)) == 0) { - ar5k_ar5210_set_gpio_intr(hal, 0, 1); - } else { - ar5k_ar5210_set_gpio_intr(hal, 0, 0); - } - } -*/ - /* - * Reset queues and start beacon timers at the end of the reset routine - */ - for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { - if (ar5k_ar5210_reset_tx_queue(hal, i) == FALSE) { - AR5K_PRINTF("failed to reset TX queue #%d\n", i); - return (FALSE); - } - } - - AR5K_REG_DISABLE_BITS(AR5K_AR5210_BEACON, - AR5K_AR5210_BEACON_EN | AR5K_AR5210_BEACON_RESET_TSF); - - return (TRUE); -} - -void /*Unimplemented*/ -ar5k_ar5210_set_def_antenna(struct ath_hal *hal, u_int ant) -{ - AR5K_TRACE; -} - -u_int/*Unimplemented*/ -ar5k_ar5210_get_def_antenna(struct ath_hal *hal) -{ - AR5K_TRACE; - return 0; -} - -void -ar5k_ar5210_set_opmode(struct ath_hal *hal) -{ - u_int32_t pcu_reg, beacon_reg, low_id, high_id; - - beacon_reg = 0; - pcu_reg = 0; - - switch (hal->ah_op_mode) { - case AR5K_M_STA: - pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL | - AR5K_AR5210_STA_ID1_DESC_ANTENNA | - AR5K_AR5210_STA_ID1_PWR_SV; - break; - - case AR5K_M_IBSS: - pcu_reg |= AR5K_AR5210_STA_ID1_ADHOC | - AR5K_AR5210_STA_ID1_NO_PSPOLL | - AR5K_AR5210_STA_ID1_DESC_ANTENNA; - beacon_reg |= AR5K_AR5210_BCR_ADHOC; - break; - - case AR5K_M_HOSTAP: - pcu_reg |= AR5K_AR5210_STA_ID1_AP | - AR5K_AR5210_STA_ID1_NO_PSPOLL | - AR5K_AR5210_STA_ID1_DESC_ANTENNA; - beacon_reg |= AR5K_AR5210_BCR_AP; - break; - - case AR5K_M_MONITOR: - pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL; - break; - - default: - return; - } - - /* - * Set PCU and BCR registers - */ - low_id = AR5K_LOW_ID(hal->ah_sta_id); - high_id = AR5K_HIGH_ID(hal->ah_sta_id); - AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, pcu_reg | high_id); - AR5K_REG_WRITE(AR5K_AR5210_BCR, beacon_reg); - - return; -} - -void /*New*/ -ar5k_ar5210_set_pcu_config(struct ath_hal *hal) -{ - AR5K_TRACE; - ar5k_ar5210_set_opmode(hal); - return; -} - -AR5K_BOOL -ar5k_ar5210_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - AR5K_BOOL ret = TRUE; - u_int32_t phy_sig, phy_agc, phy_sat, beacon; - -#define AGC_DISABLE { \ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGC, \ - AR5K_AR5210_PHY_AGC_DISABLE); \ - AR5K_DELAY(10); \ -} - -#define AGC_ENABLE { \ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_PHY_AGC, \ - AR5K_AR5210_PHY_AGC_DISABLE); \ -} - - /* - * Disable beacons and RX/TX queues, wait - */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, - AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX); - beacon = AR5K_REG_READ(AR5K_AR5210_BEACON); - AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon & ~AR5K_AR5210_BEACON_EN); - - AR5K_DELAY(2300); - - /* - * Set the channel (with AGC turned off) - */ - AGC_DISABLE; - ret = ar5k_channel(hal, channel); - - /* - * Activate PHY and wait - */ - AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE); - AR5K_DELAY(1000); - - AGC_ENABLE; - - if (ret == FALSE) - return (ret); - - /* - * Calibrate the radio chip - */ - - /* Remember normal state */ - phy_sig = AR5K_REG_READ(AR5K_AR5210_PHY_SIG); - phy_agc = AR5K_REG_READ(AR5K_AR5210_PHY_AGCCOARSE); - phy_sat = AR5K_REG_READ(AR5K_AR5210_PHY_ADCSAT); - - /* Update radio registers */ - AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG, - (phy_sig & ~(AR5K_AR5210_PHY_SIG_FIRPWR)) | - AR5K_REG_SM(-1, AR5K_AR5210_PHY_SIG_FIRPWR)); - - AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, - (phy_agc & ~(AR5K_AR5210_PHY_AGCCOARSE_HI | - AR5K_AR5210_PHY_AGCCOARSE_LO)) | - AR5K_REG_SM(-1, AR5K_AR5210_PHY_AGCCOARSE_HI) | - AR5K_REG_SM(-127, AR5K_AR5210_PHY_AGCCOARSE_LO)); - - AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, - (phy_sat & ~(AR5K_AR5210_PHY_ADCSAT_ICNT | - AR5K_AR5210_PHY_ADCSAT_THR)) | - AR5K_REG_SM(2, AR5K_AR5210_PHY_ADCSAT_ICNT) | - AR5K_REG_SM(12, AR5K_AR5210_PHY_ADCSAT_THR)); - - AR5K_DELAY(20); - - AGC_DISABLE; - AR5K_REG_WRITE(AR5K_AR5210_PHY_RFSTG, AR5K_AR5210_PHY_RFSTG_DISABLE); - AGC_ENABLE; - - AR5K_DELAY(1000); - - ret = ar5k_ar5210_do_calibrate(hal, channel); - - /* Reset to normal state */ - AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG, phy_sig); - AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, phy_agc); - AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, phy_sat); - - if (ret == FALSE) - return (FALSE); - - if (ar5k_ar5210_noise_floor(hal, channel) == FALSE) - return (FALSE); - - /* - * Re-enable RX/TX and beacons - */ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, - AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX); - AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon); - -#undef AGC_ENABLE -#undef AGC_DISABLE - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_do_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - /* - * Enable calibration and wait until completion - */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL, - AR5K_AR5210_PHY_AGCCTL_CAL); - - if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, - AR5K_AR5210_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) { - AR5K_PRINTF("calibration timeout (%uMHz)\n", - channel->freq); - return (FALSE); - } - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_noise_floor(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - int i; - u_int32_t noise_floor; - - /* - * Enable noise floor calibration and wait until completion - */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL, - AR5K_AR5210_PHY_AGCCTL_NF); - - if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, - AR5K_AR5210_PHY_AGCCTL_NF, 0, FALSE) == FALSE) { - AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", - channel->freq); - return (FALSE); - } - - /* wait until the noise floor is calibrated */ - for (i = 20; i > 0; i--) { - AR5K_DELAY(1000); - noise_floor = AR5K_REG_READ(AR5K_AR5210_PHY_NF); - if (AR5K_AR5210_PHY_NF_RVAL(noise_floor) & - AR5K_AR5210_PHY_NF_ACTIVE) - noise_floor = AR5K_AR5210_PHY_NF_AVAL(noise_floor); - if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) - break; - } - - if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { - AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", - channel->freq); - return (FALSE); - } - - return (TRUE); -} - -/* - * Transmit functions - */ - -AR5K_BOOL -ar5k_ar5210_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) -{ - u_int32_t trigger_level; - AR5K_BOOL status = FALSE; - - /* - * Disable interrupts by setting the mask - */ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR, AR5K_INT_GLOBAL); - - trigger_level = AR5K_REG_READ(AR5K_AR5210_TRIG_LVL); - - if (increase == FALSE) { - if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) - goto done; - } else { - trigger_level += - ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); - } - - /* - * Update trigger level on success - */ - AR5K_REG_WRITE(AR5K_AR5210_TRIG_LVL, trigger_level); - status = TRUE; - - done: - /* - * Restore interrupt mask - */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_INT_GLOBAL); - - return (status); -} - -int -ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, - AR5K_TXQ_INFO *queue_info) -{ - u_int queue; - - /* - * Get queue by type - */ - switch (queue_type) { - case AR5K_TX_QUEUE_DATA: - queue = 0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - queue = 1; - break; - default: - return (-1); - } - - /* - * Setup internal queue structure - */ - bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - hal->ah_txq[queue].tqi_type = queue_type; - - if (queue_info != NULL) { - queue_info->tqi_type = queue_type; - if (ar5k_ar5210_setup_tx_queueprops(hal, - queue, queue_info) != TRUE) - return (-1); - } - - return (queue); -} - -AR5K_BOOL -ar5k_ar5210_setup_tx_queueprops(struct ath_hal *hal, int queue, - const AR5K_TXQ_INFO *queue_info) -{ - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (FALSE); - - hal->ah_txq[queue].tqi_aifs = queue_info->tqi_aifs; - hal->ah_txq[queue].tqi_cw_max = queue_info->tqi_cw_max; - hal->ah_txq[queue].tqi_cw_min = queue_info->tqi_cw_min; - hal->ah_txq[queue].tqi_flags = queue_info->tqi_flags; - - return (TRUE); -} - -AR5K_BOOL /*New*/ -ar5k_ar5210_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) -{ - AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_release_tx_queue(struct ath_hal *hal, u_int queue) -{ - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* This queue will be skipped in further operations */ - hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; - - return (FALSE); -} - -void -ar5k_ar5210_init_tx_queue(struct ath_hal *hal, u_int aifs, AR5K_BOOL turbo) -{ - int i; - struct { - u_int16_t mode_register; - u_int32_t mode_base, mode_turbo; - } initial[] = AR5K_AR5210_INI_MODE(aifs); - - /* - * Write initial mode register settings - */ - for (i = 0; i < AR5K_ELEMENTS(initial); i++) - AR5K_REG_WRITE((u_int32_t)initial[i].mode_register, - turbo == TRUE ? - initial[i].mode_turbo : initial[i].mode_base); -} - -AR5K_BOOL -ar5k_ar5210_reset_tx_queue(struct ath_hal *hal, u_int queue) -{ - u_int32_t cw_min, retry_lg, retry_sh; - AR5K_TXQ_INFO *tq; - - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - tq = &hal->ah_txq[queue]; - - /* Only handle data queues, others will be ignored */ - if (tq->tqi_type != AR5K_TX_QUEUE_DATA) - return (TRUE); - - /* Set turbo/base mode parameters */ - ar5k_ar5210_init_tx_queue(hal, hal->ah_aifs + tq->tqi_aifs, - hal->ah_turbo == TRUE ? TRUE : FALSE); - - /* - * Set retry limits - */ - if (hal->ah_software_retry == TRUE) { - /* XXX Need to test this */ - retry_lg = hal->ah_limit_tx_retries; - retry_sh = retry_lg = - retry_lg > AR5K_AR5210_RETRY_LMT_SH_RETRY ? - AR5K_AR5210_RETRY_LMT_SH_RETRY : retry_lg; - } else { - retry_lg = AR5K_INIT_LG_RETRY; - retry_sh = AR5K_INIT_SH_RETRY; - } - - /* - * Set initial content window (cw_min/cw_max) - */ - cw_min = 1; - while (cw_min < hal->ah_cw_min) - cw_min = (cw_min << 1) | 1; - - cw_min = tq->tqi_cw_min < 0 ? - (cw_min >> (-tq->tqi_cw_min)) : - ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); - - /* Commit values */ - AR5K_REG_WRITE(AR5K_AR5210_RETRY_LMT, - (cw_min << AR5K_AR5210_RETRY_LMT_CW_MIN_S) - | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_AR5210_RETRY_LMT_SLG_RETRY) - | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_AR5210_RETRY_LMT_SSH_RETRY) - | AR5K_REG_SM(retry_lg, AR5K_AR5210_RETRY_LMT_LG_RETRY) - | AR5K_REG_SM(retry_sh, AR5K_AR5210_RETRY_LMT_SH_RETRY)); - - return (TRUE); -} - -u_int32_t -ar5k_ar5210_get_tx_buf(struct ath_hal *hal, u_int queue) -{ - u_int16_t tx_reg; - - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Get the transmit queue descriptor pointer register by type - */ - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_reg = AR5K_AR5210_TXDP0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - tx_reg = AR5K_AR5210_TXDP1; - break; - default: - return (0xffffffff); - } - - return (AR5K_REG_READ(tx_reg)); -} - -AR5K_BOOL -ar5k_ar5210_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) -{ - u_int16_t tx_reg; - - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Get the transmit queue descriptor pointer register by type - */ - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_reg = AR5K_AR5210_TXDP0; - break; - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - tx_reg = AR5K_AR5210_TXDP1; - break; - default: - return (FALSE); - } - - /* Set descriptor pointer */ - AR5K_REG_WRITE(tx_reg, phys_addr); - - return (TRUE); -} - -u_int32_t /*Unimplemented*/ -ar5k_ar5210_num_tx_pending(struct ath_hal *hal, u_int queue) { - AR5K_TRACE; - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5210_tx_start(struct ath_hal *hal, u_int queue) -{ - u_int32_t tx_queue; - - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - tx_queue = AR5K_REG_READ(AR5K_AR5210_CR); - - /* - * Set the queue type - */ - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_queue |= AR5K_AR5210_CR_TXE0 & ~AR5K_AR5210_CR_TXD0; - break; - - case AR5K_TX_QUEUE_BEACON: - tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1; - AR5K_REG_WRITE(AR5K_AR5210_BSR, - AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE); - break; - - case AR5K_TX_QUEUE_CAB: - tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1; - AR5K_REG_WRITE(AR5K_AR5210_BSR, - AR5K_AR5210_BCR_TQ1FV | AR5K_AR5210_BCR_TQ1V | - AR5K_AR5210_BCR_BDMAE); - break; - - default: - return (FALSE); - } - - /* Start queue */ - AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_stop_tx_dma(struct ath_hal *hal, u_int queue) -{ - u_int32_t tx_queue; - - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - tx_queue = AR5K_REG_READ(AR5K_AR5210_CR); - - /* - * Set by queue type - */ - switch (hal->ah_txq[queue].tqi_type) { - case AR5K_TX_QUEUE_DATA: - tx_queue |= AR5K_AR5210_CR_TXD0 & ~AR5K_AR5210_CR_TXE0; - break; - - case AR5K_TX_QUEUE_BEACON: - case AR5K_TX_QUEUE_CAB: - /* XXX Fix me... */ - tx_queue |= AR5K_AR5210_CR_TXD1 & ~AR5K_AR5210_CR_TXD1; - AR5K_REG_WRITE(AR5K_AR5210_BSR, 0); - break; - - default: - return (FALSE); - } - - /* Stop queue */ - AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); - - return (TRUE); -} - -AR5K_BOOL /*O.K. - Initialize tx_desc and clear ds_hw */ -ar5k_ar5210_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, - u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - u_int flags, u_int rtscts_rate, u_int rtscts_duration) -{ - u_int32_t frame_type; - struct ar5k_ar5210_tx_desc *tx_desc; - - tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0; - - /*Clear ds_hw*/ - bzero(desc->ds_hw, sizeof(desc->ds_hw)); - - /* - * Validate input - */ - if (tx_tries0 == 0) - return (FALSE); - - /* Initialize status descriptor */ - tx_desc->tx_control_0 = 0; - tx_desc->tx_control_1 = 0; - - /* Setup status descriptor */ - - if ((tx_desc->tx_control_0 = (packet_length & - AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN)) != packet_length) - return (FALSE); - - if ((tx_desc->tx_control_0 = (header_length & - AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN)) != header_length) - return (FALSE); - - if (type == AR5K_PKT_TYPE_BEACON || type == AR5K_PKT_TYPE_PROBE_RESP) - frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY; - else if (type == AR5K_PKT_TYPE_PIFS) - frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS; - else - frame_type = type; - - tx_desc->tx_control_0 = - AR5K_REG_SM(frame_type, AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE); - tx_desc->tx_control_0 |= - AR5K_REG_SM(tx_rate0, AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE); - -#define _TX_FLAGS(_c, _flag) \ - if (flags & AR5K_TXDESC_##_flag) \ - tx_desc->tx_control_##_c |= \ - AR5K_AR5210_DESC_TX_CTL##_c##_##_flag - - _TX_FLAGS(0, CLRDMASK); - _TX_FLAGS(0, INTREQ); - _TX_FLAGS(0, RTSENA); - -#undef _TX_FLAGS - - /* - * WEP crap - */ - if (key_index != AR5K_TXKEYIX_INVALID) { - tx_desc->tx_control_0 |= - AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID; - tx_desc->tx_control_1 |= - AR5K_REG_SM(key_index, - AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); - } - - /* - * RTS/CTS - */ - if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { - tx_desc->tx_control_1 |= - rtscts_duration & AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION; - } - - return (TRUE); -} - -AR5K_BOOL /*Added an argument *last_desc -need revision -don't clear descriptor here*/ -ar5k_ar5210_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) -{ - struct ar5k_ar5210_tx_desc *tx_desc; - - tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0; - - /* Clear status descriptor */ -// bzero(desc->ds_hw, sizeof(desc->ds_hw)); - - /* Validate segment length and initialize the descriptor */ - if ((tx_desc->tx_control_1 = (segment_length & - AR5K_AR5210_DESC_TX_CTL1_BUF_LEN)) != segment_length) - return (FALSE); - - if (first_segment != TRUE) - tx_desc->tx_control_0 &= ~AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN; - - if (last_segment != TRUE) - tx_desc->tx_control_1 |= AR5K_AR5210_DESC_TX_CTL1_MORE; - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - u_int tx_rate3, u_int tx_tries3) -{ - /* - * Does this function is for setting up XR? Not sure... - * Nevertheless, I didn't find any information about XR support - * by the AR5210. This seems to be a slightly new feature. - */ - return (FALSE); -} - -AR5K_STATUS -ar5k_ar5210_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) -{ - struct ar5k_ar5210_tx_status *tx_status; - struct ar5k_ar5210_tx_desc *tx_desc; - - tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ar5k_ar5210_tx_status*)&desc->ds_hw[0]; - - /* No frame has been send or error */ - if ((tx_status->tx_status_1 & AR5K_AR5210_DESC_TX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); - - /* - * Get descriptor status - */ - desc->ds_us.tx.ts_tstamp = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP); - desc->ds_us.tx.ts_shortretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT); - desc->ds_us.tx.ts_longretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT); - desc->ds_us.tx.ts_seqnum = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM); - desc->ds_us.tx.ts_rssi = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH); - desc->ds_us.tx.ts_antenna = 1; - desc->ds_us.tx.ts_status = 0; - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_0, - AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE); - - if ((tx_status->tx_status_0 & - AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { - if (tx_status->tx_status_0 & - AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; - - if (tx_status->tx_status_0 & - AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; - - if (tx_status->tx_status_0 & - AR5K_AR5210_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; - } - - return (AR5K_OK); -} - -AR5K_BOOL -ar5k_ar5210_has_veol(struct ath_hal *hal) -{ - return (FALSE); -} - -void /*Unimplemented*/ -ar5k_ar5210_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) -{ - AR5K_TRACE; - /* XXX */ - return; -} - -/* - * Receive functions - */ - -u_int32_t -ar5k_ar5210_get_rx_buf(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5210_RXDP)); -} - -void -ar5k_ar5210_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) -{ - AR5K_REG_WRITE(AR5K_AR5210_RXDP, phys_addr); -} - -void -ar5k_ar5210_start_rx(struct ath_hal *hal) -{ - AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXE); -} - -AR5K_BOOL -ar5k_ar5210_stop_rx_dma(struct ath_hal *hal) -{ - int i; - - AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXD); - - /* - * It may take some time to disable the DMA receive unit - */ - for (i = 2000; - i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0; - i--) - AR5K_DELAY(10); - - return (i > 0 ? TRUE : FALSE); -} - -void -ar5k_ar5210_start_rx_pcu(struct ath_hal *hal) -{ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX); -} - -void -ar5k_ar5210_stop_pcu_recv(struct ath_hal *hal) -{ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX); -} - -void -ar5k_ar5210_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, - u_int32_t filter1) -{ - /* Set the multicat filter */ - AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL0, filter0); - AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL1, filter1); -} - -AR5K_BOOL -ar5k_ar5210_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) -{ - if (index >= 64) { - return (FALSE); - } else if (index >= 32) { - AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL1, - (1 << (index - 32))); - } else { - AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL0, - (1 << index)); - } - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) -{ - if (index >= 64) { - return (FALSE); - } else if (index >= 32) { - AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL1, - (1 << (index - 32))); - } else { - AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL0, - (1 << index)); - } - - return (TRUE); -} - -u_int32_t -ar5k_ar5210_get_rx_filter(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5210_RX_FILTER)); -} - -void -ar5k_ar5210_set_rx_filter(struct ath_hal *hal, u_int32_t filter) -{ - /* - * The AR5210 uses promiscous mode to detect radar activity - */ - if (filter & AR5K_RX_FILTER_PHYRADAR) { - filter &= ~AR5K_RX_FILTER_PHYRADAR; - filter |= AR5K_AR5210_RX_FILTER_PROMISC; - } - - AR5K_REG_WRITE(AR5K_AR5210_RX_FILTER, filter); -} - -AR5K_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ -ar5k_ar5210_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t size, u_int flags) -{ - struct ar5k_ar5210_rx_desc *rx_desc; - - rx_desc = (struct ar5k_ar5210_rx_desc*)&desc->ds_ctl0; - - /* - *Clear ds_hw - * If we don't clean the descriptor, while - * scanning we get too many results, - * most of them virtual, after some secs - * of scanning system halts. M.F. - */ - bzero(desc->ds_hw, sizeof(desc->ds_hw)); - - /*Initialize rx descriptor*/ - rx_desc->rx_control_0 = 0; - rx_desc->rx_control_1 = 0; - - /*Setup descriptor*/ - - if ((rx_desc->rx_control_1 = (size & - AR5K_AR5210_DESC_RX_CTL1_BUF_LEN)) != size) - return (FALSE); - - if (flags & AR5K_RXDESC_INTREQ) - rx_desc->rx_control_1 |= AR5K_AR5210_DESC_RX_CTL1_INTREQ; - - return (TRUE); -} - -AR5K_STATUS -ar5k_ar5210_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) -{ - struct ar5k_ar5210_rx_status *rx_status; - - rx_status = (struct ar5k_ar5210_rx_status*)&desc->ds_hw[0]; - - /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); - - /* - * Frame receive status - */ - desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE); - desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA; - desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_AR5210_DESC_RX_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); - desc->ds_us.rx.rs_status = 0; - - /* - * Key table status - */ - if (rx_status->rx_status_1 & - AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID) { - desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX); - } else { - desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; - } - - /* - * Receive/descriptor errors - */ - if ((rx_status->rx_status_1 & - AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & - AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; - - if (rx_status->rx_status_1 & - AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN) - desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; - - if (rx_status->rx_status_1 & - AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR) { - desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; - desc->ds_us.rx.rs_phyerr = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR); - } - - if (rx_status->rx_status_1 & - AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; - } - - return (AR5K_OK); -} - -void /*Added AR5K_NODE_STATS argument*/ -ar5k_ar5210_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) -{ - /* Signal state monitoring is not yet supported */ -} - -/* - * Misc functions - */ - -void -ar5k_ar5210_dump_state(struct ath_hal *hal) -{ -#ifdef AR5K_DEBUG -#define AR5K_PRINT_REGISTER(_x) \ - AR5K_PRINTF("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5210_##_x)); - - AR5K_PRINT("DMA registers:\n"); - AR5K_PRINT_REGISTER(TXDP0); - AR5K_PRINT_REGISTER(TXDP1); - AR5K_PRINT_REGISTER(CR); - AR5K_PRINT_REGISTER(RXDP); - AR5K_PRINT_REGISTER(CFG); - AR5K_PRINT_REGISTER(ISR); - AR5K_PRINT_REGISTER(IMR); - AR5K_PRINT_REGISTER(IER); - AR5K_PRINT_REGISTER(BCR); - AR5K_PRINT_REGISTER(BSR); - AR5K_PRINT_REGISTER(TXCFG); - AR5K_PRINT_REGISTER(RXCFG); - AR5K_PRINT_REGISTER(MIBC); - AR5K_PRINT_REGISTER(TOPS); - AR5K_PRINT_REGISTER(RXNOFRM); - AR5K_PRINT_REGISTER(TXNOFRM); - AR5K_PRINT_REGISTER(RPGTO); - AR5K_PRINT_REGISTER(RFCNT); - AR5K_PRINT_REGISTER(MISC); - AR5K_PRINT_REGISTER(RC); - AR5K_PRINT_REGISTER(SCR); - AR5K_PRINT_REGISTER(INTPEND); - AR5K_PRINT_REGISTER(SFR); - AR5K_PRINT_REGISTER(PCICFG); - AR5K_PRINT_REGISTER(GPIOCR); - AR5K_PRINT_REGISTER(GPIODO); - AR5K_PRINT_REGISTER(GPIODI); - AR5K_PRINT_REGISTER(SREV); - AR5K_PRINT("\n"); - - AR5K_PRINT("PCU registers:\n"); - AR5K_PRINT_REGISTER(STA_ID0); - AR5K_PRINT_REGISTER(STA_ID1); - AR5K_PRINT_REGISTER(BSS_ID0); - AR5K_PRINT_REGISTER(BSS_ID1); - AR5K_PRINT_REGISTER(SLOT_TIME); - AR5K_PRINT_REGISTER(TIME_OUT); - AR5K_PRINT_REGISTER(RSSI_THR); - AR5K_PRINT_REGISTER(RETRY_LMT); - AR5K_PRINT_REGISTER(USEC); - AR5K_PRINT_REGISTER(BEACON); - AR5K_PRINT_REGISTER(CFP_PERIOD); - AR5K_PRINT_REGISTER(TIMER0); - AR5K_PRINT_REGISTER(TIMER1); - AR5K_PRINT_REGISTER(TIMER2); - AR5K_PRINT_REGISTER(TIMER3); - AR5K_PRINT_REGISTER(IFS0); - AR5K_PRINT_REGISTER(IFS1); - AR5K_PRINT_REGISTER(CFP_DUR); - AR5K_PRINT_REGISTER(RX_FILTER); - AR5K_PRINT_REGISTER(MCAST_FIL0); - AR5K_PRINT_REGISTER(MCAST_FIL1); - AR5K_PRINT_REGISTER(TX_MASK0); - AR5K_PRINT_REGISTER(TX_MASK1); - AR5K_PRINT_REGISTER(CLR_TMASK); - AR5K_PRINT_REGISTER(TRIG_LVL); - AR5K_PRINT_REGISTER(DIAG_SW); - AR5K_PRINT_REGISTER(TSF_L32); - AR5K_PRINT_REGISTER(TSF_U32); - AR5K_PRINT_REGISTER(LAST_TSTP); - AR5K_PRINT_REGISTER(RETRY_CNT); - AR5K_PRINT_REGISTER(BACKOFF); - AR5K_PRINT_REGISTER(NAV); - AR5K_PRINT_REGISTER(RTS_OK); - AR5K_PRINT_REGISTER(RTS_FAIL); - AR5K_PRINT_REGISTER(ACK_FAIL); - AR5K_PRINT_REGISTER(FCS_FAIL); - AR5K_PRINT_REGISTER(BEACON_CNT); - AR5K_PRINT_REGISTER(KEYTABLE_0); - AR5K_PRINT("\n"); - - AR5K_PRINT("PHY registers:\n"); - AR5K_PRINT_REGISTER(PHY(0)); - AR5K_PRINT_REGISTER(PHY_FC); - AR5K_PRINT_REGISTER(PHY_AGC); - AR5K_PRINT_REGISTER(PHY_CHIP_ID); - AR5K_PRINT_REGISTER(PHY_ACTIVE); - AR5K_PRINT_REGISTER(PHY_AGCCTL); - AR5K_PRINT("\n"); -#endif -} - -AR5K_BOOL /*Added arguments*/ -ar5k_ar5210_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) -{ - /* - * We'll ignore this right now. This seems to be some kind of an obscure - * debugging interface for the binary-only HAL. - */ - return (FALSE); -} - -void -ar5k_ar5210_get_lladdr(struct ath_hal *hal, u_int8_t *mac) -{ - bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); -} - -AR5K_BOOL -ar5k_ar5210_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) -{ - u_int32_t low_id, high_id; - - /* Set new station ID */ - bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); - - low_id = AR5K_LOW_ID(mac); - high_id = AR5K_HIGH_ID(mac); - - AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, high_id); - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - AR5K_STATUS *status) -{ - ieee80211_regdomain_t ieee_regdomain; - - ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); - - if (ar5k_eeprom_regulation_domain(hal, TRUE, - &ieee_regdomain) == TRUE) { - *status = AR5K_OK; - return (TRUE); - } - - *status = EIO; - - return (FALSE); -} - -void -ar5k_ar5210_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) -{ - u_int32_t led; - - led = AR5K_REG_READ(AR5K_AR5210_PCICFG); - - /* - * Some blinking values, define at your wish - */ - switch (state) { - case AR5K_LED_SCAN: - case AR5K_LED_INIT: - led |= - AR5K_AR5210_PCICFG_LED_PEND | - AR5K_AR5210_PCICFG_LED_BCTL; - break; - case AR5K_LED_RUN: - led |= - AR5K_AR5210_PCICFG_LED_ACT; - break; - default: - led |= - AR5K_AR5210_PCICFG_LED_ACT | - AR5K_AR5210_PCICFG_LED_BCTL; - break; - } - - AR5K_REG_WRITE(AR5K_AR5210_PCICFG, led); -} - -void /*Removed argument trim_offset for combatibility -need revision*/ -ar5k_ar5210_set_associd(struct ath_hal *hal, const u_int8_t *bssid, - u_int16_t assoc_id) -{ - u_int32_t low_id, high_id; - u_int16_t tim_offset = 0; - - /* - * Set BSSID which triggers the "SME Join" operation - */ - low_id = AR5K_LOW_ID(bssid); - high_id = AR5K_HIGH_ID(bssid); - AR5K_REG_WRITE(AR5K_AR5210_BSS_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5210_BSS_ID1, high_id | - ((assoc_id & 0x3fff) << AR5K_AR5210_BSS_ID1_AID_S)); - bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN); - - if (assoc_id == 0) { - ar5k_ar5210_disable_pspoll(hal); - return; - } - - AR5K_REG_WRITE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_TIM, - tim_offset ? tim_offset + 4 : 0); - - ar5k_ar5210_enable_pspoll(hal, NULL, 0); -} - -AR5K_BOOL /*New*/ -ar5k_ar5210_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) -{ - /*Not supported in 5210*/ - AR5K_TRACE; - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5210_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) -{ - if (gpio > AR5K_AR5210_NUM_GPIO) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, - (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) - | AR5K_AR5210_GPIOCR_OUT1(gpio)); - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) -{ - if (gpio > AR5K_AR5210_NUM_GPIO) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, - (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) - | AR5K_AR5210_GPIOCR_IN(gpio)); - - return (TRUE); -} - -u_int32_t -ar5k_ar5210_get_gpio(struct ath_hal *hal, u_int32_t gpio) -{ - if (gpio > AR5K_AR5210_NUM_GPIO) - return (0xffffffff); - - /* GPIO input magic */ - return (((AR5K_REG_READ(AR5K_AR5210_GPIODI) & - AR5K_AR5210_GPIOD_MASK) >> gpio) & 0x1); -} - -AR5K_BOOL -ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) -{ - u_int32_t data; - - if (gpio > AR5K_AR5210_NUM_GPIO) - return (FALSE); - - /* GPIO output magic */ - data = AR5K_REG_READ(AR5K_AR5210_GPIODO); - - data &= ~(1 << gpio); - data |= (val&1) << gpio; - - AR5K_REG_WRITE(AR5K_AR5210_GPIODO, data); - - return (TRUE); -} - -void -ar5k_ar5210_set_gpio_intr(struct ath_hal *hal, u_int gpio, - u_int32_t interrupt_level) -{ - u_int32_t data; - - if (gpio > AR5K_AR5210_NUM_GPIO) - return; - - /* - * Set the GPIO interrupt - */ - data = (AR5K_REG_READ(AR5K_AR5210_GPIOCR) & - ~(AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_SELH | - AR5K_AR5210_GPIOCR_INT_ENA | AR5K_AR5210_GPIOCR_ALL(gpio))) | - (AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_ENA); - - AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, - interrupt_level ? data : (data | AR5K_AR5210_GPIOCR_INT_SELH)); - - hal->ah_imr |= AR5K_AR5210_IMR_GPIO; - - /* Enable GPIO interrupts */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_AR5210_IMR_GPIO); -} - -u_int32_t -ar5k_ar5210_get_tsf32(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5210_TSF_L32)); -} - -u_int64_t -ar5k_ar5210_get_tsf64(struct ath_hal *hal) -{ - u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32); - return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32)); -} - -void -ar5k_ar5210_reset_tsf(struct ath_hal *hal) -{ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON, - AR5K_AR5210_BEACON_RESET_TSF); -} - -u_int16_t -ar5k_ar5210_get_regdomain(struct ath_hal *hal) -{ - return (ar5k_get_regdomain(hal)); -} - -AR5K_BOOL -ar5k_ar5210_detect_card_present(struct ath_hal *hal) -{ - u_int16_t magic; - - /* - * Checking the EEPROM's magic value could be an indication - * if the card is still present. I didn't find another suitable - * way to do this. - */ - if (ar5k_ar5210_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (FALSE); - - return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); -} - -void -ar5k_ar5210_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) -{ - statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5210_ACK_FAIL); - statistics->rts_bad += AR5K_REG_READ(AR5K_AR5210_RTS_FAIL); - statistics->rts_good += AR5K_REG_READ(AR5K_AR5210_RTS_OK); - statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5210_FCS_FAIL); - statistics->beacons += AR5K_REG_READ(AR5K_AR5210_BEACON_CNT); -} - -void /*Unimplemented*/ -ar5k_ar5210_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) -{ - AR5K_TRACE; - return; -} - -AR5K_RFGAIN -ar5k_ar5210_get_rf_gain(struct ath_hal *hal) -{ - return (AR5K_RFGAIN_INACTIVE); -} - -AR5K_BOOL -ar5k_ar5210_set_slot_time(struct ath_hal *hal, u_int slot_time) -{ - if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5210_SLOT_TIME, - ar5k_htoclock(slot_time, hal->ah_turbo)); - - return (TRUE); -} - -u_int -ar5k_ar5210_get_slot_time(struct ath_hal *hal) -{ - return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) & - 0xffff, hal->ah_turbo)); -} - -AR5K_BOOL -ar5k_ar5210_set_ack_timeout(struct ath_hal *hal, u_int timeout) -{ - if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_ACK), - hal->ah_turbo) <= timeout) - return (FALSE); - - AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_ACK, - ar5k_htoclock(timeout, hal->ah_turbo)); - - return (TRUE); -} - -u_int -ar5k_ar5210_get_ack_timeout(struct ath_hal *hal) -{ - return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), - AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo)); -} - -AR5K_BOOL -ar5k_ar5210_set_cts_timeout(struct ath_hal *hal, u_int timeout) -{ - if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_CTS), - hal->ah_turbo) <= timeout) - return (FALSE); - - AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_CTS, - ar5k_htoclock(timeout, hal->ah_turbo)); - - return (TRUE); -} - -u_int -ar5k_ar5210_get_cts_timeout(struct ath_hal *hal) -{ - return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), - AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo)); -} - -AR5K_STATUS /*New*/ -ar5k_ar5210_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t *result) -{ - AR5K_TRACE; - - switch (cap_type) { - case AR5K_CAP_REG_DMN: - if (result){ - *result = ar5k_get_regdomain(hal); - goto yes; - } - case AR5K_CAP_CIPHER: - switch (capability) { - case AR5K_CIPHER_WEP: goto yes; - default: goto no; - } - case AR5K_CAP_NUM_TXQUEUES: - if (result) { - *result = AR5K_AR5210_TX_NUM_QUEUES; - goto yes; - } - case AR5K_CAP_VEOL: - goto yes; - case AR5K_CAP_COMPRESSION: - goto yes; - case AR5K_CAP_BURST: - goto yes; - case AR5K_CAP_TPC: - goto yes; - case AR5K_CAP_BSSIDMASK: - goto yes; - case AR5K_CAP_XR: - goto yes; - default: - goto no; - } - - no: - return (AR5K_EINVAL); - yes: - return AR5K_OK; - -} - -AR5K_BOOL -ar5k_ar5210_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) -{ - - AR5K_TRACE; - if (status) { - *status = AR5K_OK; - } - return (FALSE); -} - -/* - * Key table (WEP) functions - */ - -AR5K_BOOL -ar5k_ar5210_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) -{ - /* - * The AR5210 only supports WEP - */ - if (cipher == AR5K_CIPHER_WEP) - return (TRUE); - - return (FALSE); -} - -u_int32_t -ar5k_ar5210_get_keycache_size(struct ath_hal *hal) -{ - return (AR5K_AR5210_KEYCACHE_SIZE); -} - -AR5K_BOOL -ar5k_ar5210_reset_key(struct ath_hal *hal, u_int16_t entry) -{ - int i; - - AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); - - for (i = 0; i < AR5K_AR5210_KEYCACHE_SIZE; i++) - AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), 0); - - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5210_is_key_valid(struct ath_hal *hal, u_int16_t entry) -{ - AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); - - /* - * Check the validation flag at the end of the entry - */ - if (AR5K_REG_READ(AR5K_AR5210_KEYTABLE_MAC1(entry)) & - AR5K_AR5210_KEYTABLE_VALID) - return (TRUE); - - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5210_set_key(struct ath_hal *hal, u_int16_t entry, - const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) -{ - int i; - u_int32_t key_v[AR5K_AR5210_KEYCACHE_SIZE - 2]; - - AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); - - bzero(&key_v, sizeof(key_v)); - - switch (keyval->wk_len) { - case AR5K_KEYVAL_LENGTH_40: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 1); - key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_40; - break; - - case AR5K_KEYVAL_LENGTH_104: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 1); - key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_104; - break; - - case AR5K_KEYVAL_LENGTH_128: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 4); - key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_128; - break; - - default: - /* Unsupported key length (not WEP40/104/128) */ - return (FALSE); - } - - for (i = 0; i < AR5K_ELEMENTS(key_v); i++) - AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), key_v[i]); - - return (ar5k_ar5210_set_key_lladdr(hal, entry, mac)); -} - -AR5K_BOOL -ar5k_ar5210_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, - const u_int8_t *mac) -{ - u_int32_t low_id, high_id; - const u_int8_t *mac_v; - - /* - * Invalid entry (key table overflow) - */ - AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); - - /* MAC may be NULL if it's a broadcast key */ - mac_v = mac == NULL ? etherbroadcastaddr : mac; - - low_id = AR5K_LOW_ID(mac_v); - high_id = AR5K_HIGH_ID(mac_v); - high_id |= AR5K_AR5210_KEYTABLE_VALID; - - AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC0(entry), low_id); - AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC1(entry), high_id); - - return (TRUE); -} - -/* - * Power management functions - */ - -AR5K_BOOL -ar5k_ar5210_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, - AR5K_BOOL set_chip, u_int16_t sleep_duration) -{ - u_int32_t staid; - int i; - - staid = AR5K_REG_READ(AR5K_AR5210_STA_ID1); - - switch (mode) { - case AR5K_PM_AUTO: - staid &= ~AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA; - /* fallthrough */ - case AR5K_PM_NETWORK_SLEEP: - if (set_chip == TRUE) { - AR5K_REG_WRITE(AR5K_AR5210_SCR, - AR5K_AR5210_SCR_SLE | sleep_duration); - } - staid |= AR5K_AR5210_STA_ID1_PWR_SV; - break; - - case AR5K_PM_FULL_SLEEP: - if (set_chip == TRUE) { - AR5K_REG_WRITE(AR5K_AR5210_SCR, - AR5K_AR5210_SCR_SLE_SLP); - } - staid |= AR5K_AR5210_STA_ID1_PWR_SV; - break; - - case AR5K_PM_AWAKE: - if (set_chip == FALSE) - goto commit; - - AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_WAKE); - - for (i = 5000; i > 0; i--) { - /* Check if the AR5210 did wake up */ - if ((AR5K_REG_READ(AR5K_AR5210_PCICFG) & - AR5K_AR5210_PCICFG_SPWR_DN) == 0) - break; - - /* Wait a bit and retry */ - AR5K_DELAY(200); - AR5K_REG_WRITE(AR5K_AR5210_SCR, - AR5K_AR5210_SCR_SLE_WAKE); - } - - /* Fail if the AR5210 didn't wake up */ - if (i <= 0) - return (FALSE); - - staid &= ~AR5K_AR5210_STA_ID1_PWR_SV; - break; - - default: - return (FALSE); - } - - commit: - hal->ah_power_mode = mode; - - AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, staid); - - return (TRUE); -} - -AR5K_POWER_MODE -ar5k_ar5210_get_power_mode(struct ath_hal *hal) -{ - return (hal->ah_power_mode); -} - -AR5K_BOOL -ar5k_ar5210_query_pspoll_support(struct ath_hal *hal) -{ - /* I think so, why not? */ - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_init_pspoll(struct ath_hal *hal) -{ - /* - * Not used on the AR5210 - */ - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5210_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, - u_int16_t assoc_id) -{ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, - AR5K_AR5210_STA_ID1_NO_PSPOLL | - AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5210_disable_pspoll(struct ath_hal *hal) -{ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_STA_ID1, - AR5K_AR5210_STA_ID1_NO_PSPOLL | - AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); - - return (TRUE); -} - -AR5K_BOOL /*Unimplemented*/ -ar5k_ar5210_set_txpower_limit(struct ath_hal *hal, u_int32_t power) -{ -// AR5K_CHANNEL *channel = &hal->ah_current_channel; - - AR5K_TRACE; - AR5K_PRINTF("changing txpower to %d\n unimplemented ;-(",power); - return FALSE; -} - -/* - * Beacon functions - */ - -void -ar5k_ar5210_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, - u_int32_t interval) -{ - u_int32_t timer1, timer2, timer3; - - /* - * Set the additional timers by mode - */ - switch (hal->ah_op_mode) { - case AR5K_M_STA: - timer1 = 0xffffffff; - timer2 = 0xffffffff; - timer3 = 1; - break; - - default: - timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; - timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; - timer3 = next_beacon + hal->ah_atim_window; - break; - } - - /* - * Enable all timers and set the beacon register - * (next beacon, DMA beacon, software beacon, ATIM window time) - */ - AR5K_REG_WRITE(AR5K_AR5210_TIMER0, next_beacon); - AR5K_REG_WRITE(AR5K_AR5210_TIMER1, timer1); - AR5K_REG_WRITE(AR5K_AR5210_TIMER2, timer2); - AR5K_REG_WRITE(AR5K_AR5210_TIMER3, timer3); - - AR5K_REG_WRITE(AR5K_AR5210_BEACON, interval & - (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_RESET_TSF | - AR5K_AR5210_BEACON_EN)); -} - -void /*Removed arguments - should be changed through *state - review AR5K_BEACON_STATE struct*/ -ar5k_ar5210_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) -{ - u_int32_t cfp_period, next_cfp; - - u_int32_t dtim_count = 0; /* XXX */ - u_int32_t cfp_count = 0; /* XXX */ - u_int32_t tsf = 0; /* XXX */ - - /* Return on an invalid beacon state */ - if (state->bs_interval < 1) - return; - - /* - * PCF support? - */ - if (state->bs_cfp_period > 0) { - /* Enable CFP mode and set the CFP and timer registers */ - cfp_period = state->bs_cfp_period * state->bs_dtim_period * - state->bs_interval; - next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * - state->bs_interval; - - AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, - AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA | - AR5K_AR5210_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_AR5210_CFP_PERIOD, cfp_period); - AR5K_REG_WRITE(AR5K_AR5210_CFP_DUR, state->bs_cfp_max_duration); - AR5K_REG_WRITE(AR5K_AR5210_TIMER2, - (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); - } else { - /* Disable PCF mode */ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, - AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA | - AR5K_AR5210_STA_ID1_PCF); - } - - /* - * Enable the beacon timer register - */ - AR5K_REG_WRITE(AR5K_AR5210_TIMER0, state->bs_next_beacon); - - /* - * Start the beacon timers - */ - AR5K_REG_WRITE(AR5K_AR5210_BEACON, - (AR5K_REG_READ(AR5K_AR5210_BEACON) &~ - (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_TIM)) | - AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, - AR5K_AR5210_BEACON_TIM) | - AR5K_REG_SM(state->bs_interval, AR5K_AR5210_BEACON_PERIOD)); - - /* - * Write new beacon miss threshold, if it appears to be valid - */ - if (state->bs_bmiss_threshold <= - (AR5K_AR5210_RSSI_THR_BM_THR >> AR5K_AR5210_RSSI_THR_BM_THR_S)) { - AR5K_REG_WRITE_BITS(AR5K_AR5210_RSSI_THR, - AR5K_AR5210_RSSI_THR_BM_THR, state->bs_bmiss_threshold); - } -} - -void -ar5k_ar5210_reset_beacon(struct ath_hal *hal) -{ - /* - * Disable beacon timer - */ - AR5K_REG_WRITE(AR5K_AR5210_TIMER0, 0); - - /* - * Disable some beacon register values - */ - AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, - AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5210_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_PERIOD); -} - -AR5K_BOOL -ar5k_ar5210_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) -{ - int i; - - /* - * Wait for beaconn queue to be done - */ - for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && - (AR5K_REG_READ(AR5K_AR5210_BSR) & - AR5K_AR5210_BSR_TXQ1F) != 0 && - (AR5K_REG_READ(AR5K_AR5210_CR) & - AR5K_AR5210_CR_TXE1) != 0; i--); - - /* Timeout... */ - if (i <= 0) { - /* - * Re-schedule the beacon queue - */ - AR5K_REG_WRITE(AR5K_AR5210_TXDP1, (u_int32_t)phys_addr); - AR5K_REG_WRITE(AR5K_AR5210_BCR, - AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE); - - return (FALSE); - } - - return (TRUE); -} - -/* - * Interrupt handling - */ - -AR5K_BOOL -ar5k_ar5210_is_intr_pending(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? FALSE : TRUE); -} - -AR5K_BOOL -ar5k_ar5210_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) -{ - u_int32_t data; - - if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == AR5K_INT_NOCARD) { - *interrupt_mask = data; - return (FALSE); - } - - /* - * Get abstract interrupt mask (HAL-compatible) - */ - *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; - - if (data & (AR5K_AR5210_ISR_RXOK | AR5K_AR5210_ISR_RXERR)) - *interrupt_mask |= AR5K_INT_RX; - if (data & (AR5K_AR5210_ISR_TXOK | AR5K_AR5210_ISR_TXERR)) - *interrupt_mask |= AR5K_INT_TX; - if (data & AR5K_AR5210_ISR_FATAL) - *interrupt_mask |= AR5K_INT_FATAL; - - /* - * Special interrupt handling (not caught by the driver) - */ - if (((*interrupt_mask) & AR5K_AR5210_ISR_RXPHY) && - hal->ah_radar.r_enabled == TRUE) - ar5k_radar_alert(hal); - - /* XXX BMISS interrupts may occur after association */ - *interrupt_mask &= ~AR5K_INT_BMISS; - - return (TRUE); -} - -u_int32_t -ar5k_ar5210_get_intr(struct ath_hal *hal) -{ - /* Return the interrupt mask stored previously */ - return (hal->ah_imr); -} - -AR5K_INT -ar5k_ar5210_set_intr(struct ath_hal *hal, AR5K_INT new_mask) -{ - AR5K_INT old_mask, int_mask; - - /* - * Disable card interrupts to prevent any race conditions - * (they will be re-enabled afterwards). - */ - AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); - - old_mask = hal->ah_imr; - - /* - * Add additional, chipset-dependent interrupt mask flags - * and write them to the IMR (interrupt mask register). - */ - int_mask = new_mask & AR5K_INT_COMMON; - - if (new_mask & AR5K_INT_RX) - int_mask |= - AR5K_AR5210_IMR_RXOK | - AR5K_AR5210_IMR_RXERR | - AR5K_AR5210_IMR_RXORN; - - if (new_mask & AR5K_INT_TX) - int_mask |= - AR5K_AR5210_IMR_TXOK | - AR5K_AR5210_IMR_TXERR | - AR5K_AR5210_IMR_TXURN; - - AR5K_REG_WRITE(AR5K_AR5210_IMR, int_mask); - - /* Store new interrupt mask */ - hal->ah_imr = new_mask; - - /* ..re-enable interrupts */ - if (int_mask) { - AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE); - } - - return (old_mask); -} - -/* - * Misc internal functions - */ - -AR5K_BOOL -ar5k_ar5210_get_capabilities(struct ath_hal *hal) -{ - /* Set number of supported TX queues */ - hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5210_TX_NUM_QUEUES; - - /* - * Set radio capabilities - * (The AR5210 only supports the middle 5GHz band) - */ - hal->ah_capabilities.cap_range.range_5ghz_min = 5120; - hal->ah_capabilities.cap_range.range_5ghz_max = 5430; - hal->ah_capabilities.cap_range.range_2ghz_min = 0; - hal->ah_capabilities.cap_range.range_2ghz_max = 0; - - /* Set supported modes */ - hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO; - - /* Set number of GPIO pins */ - hal->ah_gpio_npins = AR5K_AR5210_NUM_GPIO; - - return (TRUE); -} - -void -ar5k_ar5210_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) -{ - /* - * Set the RXPHY interrupt to be able to detect - * possible radar activity. - */ - AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); - - if (enable == TRUE) { - AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, - AR5K_AR5210_IMR_RXPHY); - } else { - AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR, - AR5K_AR5210_IMR_RXPHY); - } - - AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE); -} - -/* - * EEPROM access functions - */ - -AR5K_BOOL -ar5k_ar5210_eeprom_is_busy(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ? - TRUE : FALSE); -} - -int -ar5k_ar5210_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) -{ - u_int32_t status, timeout; - - /* Enable eeprom access */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE); - - /* - * Prime read pump - */ - (void)AR5K_REG_READ(AR5K_AR5210_EEPROM_BASE + (4 * offset)); - - for (timeout = 10000; timeout > 0; timeout--) { - AR5K_DELAY(1); - status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS); - if (status & AR5K_AR5210_EEPROM_STAT_RDDONE) { - if (status & AR5K_AR5210_EEPROM_STAT_RDERR) - return (EIO); - *data = (u_int16_t) - (AR5K_REG_READ(AR5K_AR5210_EEPROM_RDATA) & 0xffff); - return (0); - } - } - - return (ETIMEDOUT); -} - -int -ar5k_ar5210_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) -{ - u_int32_t status, timeout; - - /* Enable eeprom access */ - AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE); - - /* - * Prime write pump - */ - AR5K_REG_WRITE(AR5K_AR5210_EEPROM_BASE + (4 * offset), data); - - for (timeout = 10000; timeout > 0; timeout--) { - AR5K_DELAY(1); - status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS); - if (status & AR5K_AR5210_EEPROM_STAT_WRDONE) { - if (status & AR5K_AR5210_EEPROM_STAT_WRERR) - return (EIO); - return (0); - } - } - - return (ETIMEDOUT); -} - Index: ar5211.c =================================================================== --- ar5211.c (revision 2185) +++ ar5211.c (revision 2232) @@ -1,2698 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for the Atheros AR5001 Wireless LAN chipset - * (AR5211 + AR5111). - */ - -#include "ar5xxx.h" -#include "ar5211reg.h" -#include "ar5211var.h" - -AR5K_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t); -AR5K_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t); -u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, AR5K_CHIP); -void ar5k_ar5211_fill(struct ath_hal *); -void ar5k_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int, - u_int); - -/* - * Initial register setting for the AR5211 - */ -static const struct ar5k_ini ar5211_ini[] = - AR5K_AR5211_INI; -static const struct ar5k_ar5211_ini_mode ar5211_mode[] = - AR5K_AR5211_INI_MODE; -static const struct ar5k_ar5211_ini_rf ar5211_rf[] = - AR5K_AR5211_INI_RF; - -AR5K_HAL_FUNCTIONS(extern, ar5k_ar5211,); - -void -ar5k_ar5211_fill(struct ath_hal *hal) -{ - hal->ah_magic = AR5K_AR5211_MAGIC; - - /* - * Init/Exit functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, get_rate_table); - AR5K_HAL_FUNCTION(hal, ar5211, detach); - - /* - * Reset functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, reset); - AR5K_HAL_FUNCTION(hal, ar5211, set_opmode); - AR5K_HAL_FUNCTION(hal, ar5211, calibrate); - - /* - * TX functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, update_tx_triglevel); - AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queueprops); - AR5K_HAL_FUNCTION(hal, ar5211, release_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5211, reset_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5211, get_tx_buf); - AR5K_HAL_FUNCTION(hal, ar5211, put_tx_buf); - AR5K_HAL_FUNCTION(hal, ar5211, tx_start); - AR5K_HAL_FUNCTION(hal, ar5211, stop_tx_dma); - AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, has_veol); - - /* - * RX functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, get_rx_buf); - AR5K_HAL_FUNCTION(hal, ar5211, put_rx_buf); - AR5K_HAL_FUNCTION(hal, ar5211, start_rx); - AR5K_HAL_FUNCTION(hal, ar5211, stop_rx_dma); - AR5K_HAL_FUNCTION(hal, ar5211, start_rx_pcu); - AR5K_HAL_FUNCTION(hal, ar5211, stop_pcu_recv); - AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filter); - AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filterindex); - AR5K_HAL_FUNCTION(hal, ar5211, clear_mcast_filter_idx); - AR5K_HAL_FUNCTION(hal, ar5211, get_rx_filter); - AR5K_HAL_FUNCTION(hal, ar5211, set_rx_filter); - AR5K_HAL_FUNCTION(hal, ar5211, setup_rx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, set_rx_signal); - - /* - * Misc functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, dump_state); - AR5K_HAL_FUNCTION(hal, ar5211, get_diag_state); - AR5K_HAL_FUNCTION(hal, ar5211, get_lladdr); - AR5K_HAL_FUNCTION(hal, ar5211, set_lladdr); - AR5K_HAL_FUNCTION(hal, ar5211, set_regdomain); - AR5K_HAL_FUNCTION(hal, ar5211, set_ledstate); - AR5K_HAL_FUNCTION(hal, ar5211, set_associd); - AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_input); - AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_output); - AR5K_HAL_FUNCTION(hal, ar5211, get_gpio); - AR5K_HAL_FUNCTION(hal, ar5211, set_gpio); - AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_intr); - AR5K_HAL_FUNCTION(hal, ar5211, get_tsf32); - AR5K_HAL_FUNCTION(hal, ar5211, get_tsf64); - AR5K_HAL_FUNCTION(hal, ar5211, reset_tsf); - AR5K_HAL_FUNCTION(hal, ar5211, get_regdomain); - AR5K_HAL_FUNCTION(hal, ar5211, detect_card_present); - AR5K_HAL_FUNCTION(hal, ar5211, update_mib_counters); - AR5K_HAL_FUNCTION(hal, ar5211, get_rf_gain); - AR5K_HAL_FUNCTION(hal, ar5211, set_slot_time); - AR5K_HAL_FUNCTION(hal, ar5211, get_slot_time); - AR5K_HAL_FUNCTION(hal, ar5211, set_ack_timeout); - AR5K_HAL_FUNCTION(hal, ar5211, get_ack_timeout); - AR5K_HAL_FUNCTION(hal, ar5211, set_cts_timeout); - AR5K_HAL_FUNCTION(hal, ar5211, get_cts_timeout); - - /* - * Key table (WEP) functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, is_cipher_supported); - AR5K_HAL_FUNCTION(hal, ar5211, get_keycache_size); - AR5K_HAL_FUNCTION(hal, ar5211, reset_key); - AR5K_HAL_FUNCTION(hal, ar5211, is_key_valid); - AR5K_HAL_FUNCTION(hal, ar5211, set_key); - AR5K_HAL_FUNCTION(hal, ar5211, set_key_lladdr); - - /* - * Power management functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, set_power); - AR5K_HAL_FUNCTION(hal, ar5211, get_power_mode); - AR5K_HAL_FUNCTION(hal, ar5211, query_pspoll_support); - AR5K_HAL_FUNCTION(hal, ar5211, init_pspoll); - AR5K_HAL_FUNCTION(hal, ar5211, enable_pspoll); - AR5K_HAL_FUNCTION(hal, ar5211, disable_pspoll); - - /* - * Beacon functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, init_beacon); - AR5K_HAL_FUNCTION(hal, ar5211, set_beacon_timers); - AR5K_HAL_FUNCTION(hal, ar5211, reset_beacon); - AR5K_HAL_FUNCTION(hal, ar5211, wait_for_beacon); - - /* - * Interrupt functions - */ - AR5K_HAL_FUNCTION(hal, ar5211, is_intr_pending); - AR5K_HAL_FUNCTION(hal, ar5211, get_isr); - AR5K_HAL_FUNCTION(hal, ar5211, get_intr); - AR5K_HAL_FUNCTION(hal, ar5211, set_intr); - - /* - * Chipset functions (ar5k-specific, non-HAL) - */ - AR5K_HAL_FUNCTION(hal, ar5211, get_capabilities); - AR5K_HAL_FUNCTION(hal, ar5211, radar_alert); - - /* - * EEPROM access - */ - AR5K_HAL_FUNCTION(hal, ar5211, eeprom_is_busy); - AR5K_HAL_FUNCTION(hal, ar5211, eeprom_read); - AR5K_HAL_FUNCTION(hal, ar5211, eeprom_write); - - /* Functions not found in OpenBSD */ - AR5K_HAL_FUNCTION(hal, ar5211, get_tx_queueprops); - AR5K_HAL_FUNCTION(hal, ar5211, get_capability); - AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending); - AR5K_HAL_FUNCTION(hal, ar5211, phy_disable); - AR5K_HAL_FUNCTION(hal, ar5211, set_pcu_config); - AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit); - AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna); - AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna); - AR5K_HAL_FUNCTION(hal, ar5211, set_bssid_mask); - /*Totaly unimplemented*/ - AR5K_HAL_FUNCTION(hal, ar5211, set_capability); - AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event); - AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue); - -} - -struct ath_hal * /*Ported & removed an arg from call to set_associd*/ -ar5k_ar5211_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, - AR5K_BUS_HANDLE sh, AR5K_STATUS *status) -{ - struct ath_hal *hal = (struct ath_hal*) sc; - u_int8_t mac[IEEE80211_ADDR_LEN]; - u_int32_t srev; - - ar5k_ar5211_fill(hal); - - /* Bring device out of sleep and reset it's units */ - if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != TRUE) - return (NULL); - - /* Get MAC, PHY and RADIO revisions */ - srev = AR5K_REG_READ(AR5K_AR5211_SREV); - hal->ah_mac_srev = srev; - hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5211_SREV_VER); - hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5211_SREV_REV); - hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) & - 0x00ffffffff; - hal->ah_radio_5ghz_revision = - ar5k_ar5211_radio_revision(hal, AR5K_CHIP_5GHZ); - hal->ah_radio_2ghz_revision = 0; - - /* Identify the chipset (this has to be done in an early step) */ - hal->ah_version = AR5K_AR5211; - hal->ah_radio = AR5K_AR5111; - hal->ah_phy = AR5K_AR5211_PHY(0); - - bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); - ar5k_ar5211_set_associd(hal, mac, 0); - ar5k_ar5211_get_lladdr(hal, mac); - ar5k_ar5211_set_opmode(hal); - - return (hal); -} - -AR5K_BOOL -ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val) -{ - AR5K_BOOL ret = FALSE; - u_int32_t mask = val ? val : ~0; - - /* Read-and-clear */ - AR5K_REG_READ(AR5K_AR5211_RXDP); - - /* - * Reset the device and wait until success - */ - AR5K_REG_WRITE(AR5K_AR5211_RC, val); - - /* Wait at least 128 PCI clocks */ - AR5K_DELAY(15); - - val &= - AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; - - mask &= - AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; - - ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, FALSE); - - /* - * Reset configuration register - */ - if ((val & AR5K_AR5211_RC_PCU) == 0) - AR5K_REG_WRITE(AR5K_AR5211_CFG, AR5K_AR5211_INIT_CFG); - - return (ret); -} - -AR5K_BOOL -ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags) -{ - u_int32_t turbo, mode, clock; - - turbo = 0; - mode = 0; - clock = 0; - - /* - * Get channel mode flags - */ - - if (flags & CHANNEL_2GHZ) { - mode |= AR5K_AR5211_PHY_MODE_FREQ_2GHZ; - clock |= AR5K_AR5211_PHY_PLL_44MHZ; - } else if (flags & CHANNEL_5GHZ) { - mode |= AR5K_AR5211_PHY_MODE_FREQ_5GHZ; - clock |= AR5K_AR5211_PHY_PLL_40MHZ; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); - } - - if ((flags & CHANNEL_CCK) || - (flags & CHANNEL_DYN)) { - /* Dynamic OFDM/CCK is not supported by the AR5211 */ - mode |= AR5K_AR5211_PHY_MODE_MOD_CCK; - } else if (flags & CHANNEL_OFDM) { - mode |= AR5K_AR5211_PHY_MODE_MOD_OFDM; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); - } - - if (flags & CHANNEL_TURBO) { - turbo = AR5K_AR5211_PHY_TURBO_MODE | - AR5K_AR5211_PHY_TURBO_SHORT; - } - - /* - * Reset and wakeup the device - */ - - /* ...reset chipset and PCI device */ - if (ar5k_ar5211_nic_reset(hal, - AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == FALSE) { - AR5K_PRINT("failed to reset the AR5211 + PCI chipset\n"); - return (FALSE); - } - - /* ...wakeup */ - if (ar5k_ar5211_set_power(hal, - AR5K_PM_AWAKE, TRUE, 0) == FALSE) { - AR5K_PRINT("failed to resume the AR5211 (again)\n"); - return (FALSE); - } - - /* ...final warm reset */ - if (ar5k_ar5211_nic_reset(hal, 0) == FALSE) { - AR5K_PRINT("failed to warm reset the AR5211\n"); - return (FALSE); - } - - /* ...set the PHY operating mode */ - AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock); - AR5K_DELAY(300); - - AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode); - AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo); - - return (TRUE); -} - -u_int16_t -ar5k_ar5211_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) -{ - int i; - u_int32_t srev; - u_int16_t ret; - - /* - * Set the radio chip access register - */ - switch (chip) { - case AR5K_CHIP_2GHZ: - AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ); - break; - case AR5K_CHIP_5GHZ: - AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); - break; - default: - return (0); - } - - AR5K_DELAY(2000); - - /* ...wait until PHY is ready and read the selected radio revision */ - AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16); - - for (i = 0; i < 8; i++) - AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000); - srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff; - - ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); - - /* Reset to the 5GHz mode */ - AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); - - return (ret); -} - -const AR5K_RATE_TABLE * -ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode) -{ - switch (mode) { - case AR5K_MODE_11A: - return (&hal->ah_rt_11a); - case AR5K_MODE_TURBO: - return (&hal->ah_rt_turbo); - case AR5K_MODE_11B: - return (&hal->ah_rt_11b); - case AR5K_MODE_11G: - return (&hal->ah_rt_11g); - default: - return (NULL); - } - - return (NULL); -} - -void /*O.K.*/ -ar5k_ar5211_detach(struct ath_hal *hal) -{ - /* - * Free HAL structure, assume interrupts are down - */ - free(hal, M_DEVBUF); -} - -AR5K_BOOL /*New*/ -ar5k_ar5211_phy_disable(struct ath_hal *hal) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE); - return TRUE; -} - -AR5K_BOOL /*Ported*/ -ar5k_ar5211_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, - AR5K_BOOL change_channel, AR5K_STATUS *status) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int8_t mac[IEEE80211_ADDR_LEN]; - u_int32_t data, s_seq, s_ant, s_led[3]; - u_int i, mode, freq, ee_mode, ant[2]; - - /* - * Save some registers before a reset - */ - if (change_channel == TRUE) { - s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0)); - s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); - } else { - s_seq = 0; - s_ant = 1; - } - - s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) & - AR5K_AR5211_PCICFG_LEDSTATE; - s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR); - s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO); - - if (ar5k_ar5211_nic_wakeup(hal, channel->channel_flags) == FALSE) - return (FALSE); - - /* - * Initialize operating mode - */ - hal->ah_op_mode = op_mode; - - switch (channel->channel_flags & CHANNEL_MODES) { - case CHANNEL_A: - mode = AR5K_INI_VAL_11A; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break ; - case CHANNEL_T: - mode = AR5K_INI_VAL_11A_TURBO; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - case CHANNEL_B: - mode = AR5K_INI_VAL_11B; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11B; - break; - case CHANNEL_G: - mode = AR5K_INI_VAL_11G; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11G; - break; - default: - AR5K_PRINTF("invalid channel: %d\n", channel->freq); - return (FALSE); - } - - /* PHY access enable */ - AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); - - /* - * Write initial RF registers - */ - ar5k_ar5211_rfregs(hal, channel, freq, ee_mode); - - /* - * Write initial mode settings - */ - for (i = 0; i < AR5K_ELEMENTS(ar5211_mode); i++) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, - ar5211_mode[i].mode_value[mode]); - } - - /* - * Write initial register settings - */ - for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { - if (change_channel == TRUE && - ar5211_ini[i].ini_register >= AR5K_AR5211_PCU_MIN && - ar5211_ini[i].ini_register <= AR5K_AR5211_PCU_MAX) - continue; - - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, - ar5211_ini[i].ini_value); - } - - /* - * Write initial RF gain settings - */ - if (ar5k_rfgain(hal, AR5K_INI_PHY_5111, freq) == FALSE) - return (FALSE); - - AR5K_DELAY(1000); - - /* - * Configure additional registers - */ - - if (hal->ah_radio == AR5K_AR5111) { - if (channel->channel_flags & CHANNEL_B) - AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG, - AR5K_AR5211_TXCFG_B_MODE); - else - AR5K_REG_DISABLE_BITS(AR5K_AR5211_TXCFG, - AR5K_AR5211_TXCFG_B_MODE); - } - - /* Set antenna mode */ - AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44), - hal->ah_antenna[ee_mode][0], 0xfffffc06); - - if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] =AR5K_ANT_FIXED_B; - else - ant[0] = ant[1] = AR5K_ANT_FIXED_A; - - AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0, - hal->ah_antenna[ee_mode][ant[0]]); - AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1, - hal->ah_antenna[ee_mode][ant[1]]); - - /* Commit values from EEPROM */ - AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_FC, - AR5K_AR5211_PHY_FC_TX_CLIP, ee->ee_tx_clip); - - AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a), - AR5K_AR5211_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); - - AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x11), - (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); - AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x12), - (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); - AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x14), - (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | - ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); - - AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d), - (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | - (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | - (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | - (ee->ee_tx_frm2xpa_enable[ee_mode])); - - AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x0a), - ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); - AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x19), - (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); - AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x49), 4, 0xffffff01); - - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, - AR5K_AR5211_PHY_IQ_CORR_ENABLE | - (ee->ee_i_cal[ee_mode] << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S) | - ee->ee_q_cal[ee_mode]); - - /* - * Restore saved values - */ - AR5K_REG_WRITE(AR5K_AR5211_DCU_SEQNUM(0), s_seq); - AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, s_ant); - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, s_led[0]); - AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, s_led[1]); - AR5K_REG_WRITE(AR5K_AR5211_GPIODO, s_led[2]); - - /* - * Misc - */ - bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); - ar5k_ar5211_set_associd(hal, mac, 0); - ar5k_ar5211_set_opmode(hal); - AR5K_REG_WRITE(AR5K_AR5211_PISR, 0xffffffff); - AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES); - - /* - * Set Rx/Tx DMA Configuration - */ - AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_SDMAMR, - AR5K_AR5211_DMASIZE_512B | AR5K_AR5211_TXCFG_DMASIZE); - AR5K_REG_WRITE_BITS(AR5K_AR5211_RXCFG, AR5K_AR5211_RXCFG_SDMAMW, - AR5K_AR5211_DMASIZE_512B); - - /* - * Set channel and calibrate the PHY - */ - if (ar5k_channel(hal, channel) == FALSE) - return (FALSE); - - /* - * Enable the PHY and wait until completion - */ - AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_ENABLE); - - data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) & - AR5K_AR5211_PHY_RX_DELAY_M; - data = (channel->channel_flags & CHANNEL_CCK) ? - ((data << 2) / 22) : (data / 10); - - AR5K_DELAY(100 + data); - - /* - * Start calibration - */ - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, - AR5K_AR5211_PHY_AGCCTL_NF | - AR5K_AR5211_PHY_AGCCTL_CAL); - - if (channel->channel_flags & CHANNEL_B) { - hal->ah_calibration = FALSE; - } else { - hal->ah_calibration = TRUE; - AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_IQ, - AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX, 15); - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, - AR5K_AR5211_PHY_IQ_RUN); - } - - /* - * Reset queues and start beacon timers at the end of the reset routine - */ - for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { - AR5K_REG_WRITE_Q(AR5K_AR5211_DCU_QCUMASK(i), i); - if (ar5k_ar5211_reset_tx_queue(hal, i) == FALSE) { - AR5K_PRINTF("failed to reset TX queue #%d\n", i); - return (FALSE); - } - } - - /* Pre-enable interrupts */ - ar5k_ar5211_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); - - /* - * Set RF kill flags if supported by the device (read from the EEPROM) - */ -/* if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { - ar5k_ar5211_set_gpio_input(hal, 0); - if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0) - ar5k_ar5211_set_gpio_intr(hal, 0, 1); - else - ar5k_ar5211_set_gpio_intr(hal, 0, 0); - } -*/ - /* - * Disable beacons and reset the register - */ - AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON, - AR5K_AR5211_BEACON_ENABLE | AR5K_AR5211_BEACON_RESET_TSF); - - return (TRUE); -} - -void /*New*/ -ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant); - return; -} - -u_int/*New*/ -ar5k_ar5211_get_def_antenna(struct ath_hal *hal) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); -} - -void -ar5k_ar5211_set_opmode(struct ath_hal *hal) -{ - u_int32_t pcu_reg, low_id, high_id; - - pcu_reg = 0; - - switch (hal->ah_op_mode) { - case AR5K_M_IBSS: - pcu_reg |= AR5K_AR5211_STA_ID1_ADHOC | - AR5K_AR5211_STA_ID1_DESC_ANTENNA; - break; - - case AR5K_M_HOSTAP: - pcu_reg |= AR5K_AR5211_STA_ID1_AP | - AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA; - break; - - case AR5K_M_STA: - case AR5K_M_MONITOR: - pcu_reg |= AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; - break; - - default: - return; - } - - /* - * Set PCU registers - */ - low_id = AR5K_LOW_ID(hal->ah_sta_id); - high_id = AR5K_HIGH_ID(hal->ah_sta_id); - AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, pcu_reg | high_id); - - return; -} - -void /*New*/ -ar5k_ar5211_set_pcu_config(struct ath_hal *hal) -{ - AR5K_TRACE; - ar5k_ar5211_set_opmode(hal); - return; -} - -AR5K_BOOL -ar5k_ar5211_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - u_int32_t i_pwr, q_pwr; - int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; - - if (hal->ah_calibration == FALSE || - AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN) - goto done; - - hal->ah_calibration = FALSE; - - iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR); - i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I); - q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q); - i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; - q_coffd = q_pwr >> 6; - - if (i_coffd == 0 || q_coffd == 0) - goto done; - - i_coff = ((-iq_corr) / i_coffd) & 0x3f; - q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; - - /* Commit new IQ value */ - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, - AR5K_AR5211_PHY_IQ_CORR_ENABLE | - ((u_int32_t)q_coff) | - ((u_int32_t)i_coff << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S)); - - done: - /* Start noise floor calibration */ - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, - AR5K_AR5211_PHY_AGCCTL_NF); - - return (TRUE); -} - -/* - * Transmit functions - */ - -AR5K_BOOL -ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) -{ - u_int32_t trigger_level, imr; - AR5K_BOOL status = FALSE; - - /* - * Disable interrupts by setting the mask - */ - imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); - - trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG), - AR5K_AR5211_TXCFG_TXFULL); - - if (increase == FALSE) { - if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) - goto done; - } else - trigger_level += - ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); - - /* - * Update trigger level on success - */ - AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, - AR5K_AR5211_TXCFG_TXFULL, trigger_level); - status = TRUE; - - done: - /* - * Restore interrupt mask - */ - ar5k_ar5211_set_intr(hal, imr); - - return (status); -} - -int -ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, - AR5K_TXQ_INFO *queue_info) -{ - u_int queue; - - /* - * Get queue by type - */ - if (queue_type == AR5K_TX_QUEUE_DATA) { - for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; - queue++) - if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) - return (-1); - } else if (queue_type == AR5K_TX_QUEUE_UAPSD) { - queue = AR5K_TX_QUEUE_ID_UAPSD; - } else if (queue_type == AR5K_TX_QUEUE_BEACON) { - queue = AR5K_TX_QUEUE_ID_BEACON; - } else if (queue_type == AR5K_TX_QUEUE_CAB) { - queue = AR5K_TX_QUEUE_ID_CAB; - } else - return (-1); - - /* - * Setup internal queue structure - */ - bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - hal->ah_txq[queue].tqi_type = queue_type; - - if (queue_info != NULL) { - queue_info->tqi_type = queue_type; - if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info) - != TRUE) - return (-1); - } - - AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); - - return (queue); -} - -AR5K_BOOL -ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue, - const AR5K_TXQ_INFO *queue_info) -{ - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - if (hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE) - return (FALSE); - - bcopy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - - if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && - ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || - (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || - queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) - hal->ah_txq[queue].tqi_flags |= - AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - - return (TRUE); -} - -AR5K_BOOL /*New*/ -ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) -{ - AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue) -{ - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* This queue will be skipped in further operations */ - hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; - AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue) -{ - u_int32_t cw_min, cw_max, retry_lg, retry_sh; - AR5K_TXQ_INFO *tq; - - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - tq = &hal->ah_txq[queue]; - - if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (TRUE); - - /* - * Set registers by channel mode - */ - if (IS_CHAN_B(hal->ah_current_channel)) { - hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; - hal->ah_aifs = AR5K_TUNE_AIFS_11B; - } else { - hal->ah_cw_min = AR5K_TUNE_CWMIN; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; - hal->ah_aifs = AR5K_TUNE_AIFS; - } - - /* - * Set retry limits - */ - if (hal->ah_software_retry == TRUE) { - /* XXX Need to test this */ - retry_lg = hal->ah_limit_tx_retries; - retry_sh = retry_lg = - retry_lg > AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY ? - AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY : retry_lg; - } else { - retry_lg = AR5K_INIT_LG_RETRY; - retry_sh = AR5K_INIT_SH_RETRY; - } - - AR5K_REG_WRITE(AR5K_AR5211_DCU_RETRY_LMT(queue), - AR5K_REG_SM(AR5K_INIT_SLG_RETRY, - AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY) | - AR5K_REG_SM(AR5K_INIT_SSH_RETRY, - AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY) | - AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) | - AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY)); - - /* - * Set initial content window (cw_min/cw_max) - */ - cw_min = 1; - while (cw_min < hal->ah_cw_min) - cw_min = (cw_min << 1) | 1; - - cw_min = tq->tqi_cw_min < 0 ? - (cw_min >> (-tq->tqi_cw_min)) : - ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); - cw_max = tq->tqi_cw_max < 0 ? - (cw_max >> (-tq->tqi_cw_max)) : - ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); - - AR5K_REG_WRITE(AR5K_AR5211_DCU_LCL_IFS(queue), - AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) | - AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) | - AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, - AR5K_AR5211_DCU_LCL_IFS_AIFS)); - - /* - * Set misc registers - */ - AR5K_REG_WRITE(AR5K_AR5211_QCU_MISC(queue), - AR5K_AR5211_QCU_MISC_DCU_EARLY); - - if (tq->tqi_cbr_period) { - AR5K_REG_WRITE(AR5K_AR5211_QCU_CBRCFG(queue), - AR5K_REG_SM(tq->tqi_cbr_period, - AR5K_AR5211_QCU_CBRCFG_INTVAL) | - AR5K_REG_SM(tq->tqi_cbr_overflow_limit, - AR5K_AR5211_QCU_CBRCFG_ORN_THRES)); - AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), - AR5K_AR5211_QCU_MISC_FRSHED_CBR); - if (tq->tqi_cbr_overflow_limit) - AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), - AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE); - } - - if (tq->tqi_ready_time) { - AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), - AR5K_REG_SM(tq->tqi_ready_time, - AR5K_AR5211_QCU_RDYTIMECFG_INTVAL) | - AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); - } - - if (tq->tqi_burst_time) { - AR5K_REG_WRITE(AR5K_AR5211_DCU_CHAN_TIME(queue), - AR5K_REG_SM(tq->tqi_burst_time, - AR5K_AR5211_DCU_CHAN_TIME_DUR) | - AR5K_AR5211_DCU_CHAN_TIME_ENABLE); - - if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { - AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), - AR5K_AR5211_QCU_MISC_TXE); - } - } - - if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { - AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), - AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS); - } - - if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { - AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), - AR5K_AR5211_DCU_MISC_BACKOFF_FRAG); - } - - /* - * Set registers by queue type - */ - switch (tq->tqi_type) { - case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), - AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | - AR5K_AR5211_QCU_MISC_CBREXP_BCN | - AR5K_AR5211_QCU_MISC_BCN_ENABLE); - - AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), - (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL) | - AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS | - AR5K_AR5211_DCU_MISC_BCN_ENABLE); - - AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), - ((AR5K_TUNE_BEACON_INTERVAL - - (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | - AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); - break; - - case AR5K_TX_QUEUE_CAB: - AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), - AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | - AR5K_AR5211_QCU_MISC_CBREXP | - AR5K_AR5211_QCU_MISC_CBREXP_BCN); - - AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), - (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL)); - break; - - case AR5K_TX_QUEUE_UAPSD: - AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), - AR5K_AR5211_QCU_MISC_CBREXP); - break; - - case AR5K_TX_QUEUE_DATA: - default: - break; - } - - /* - * Enable tx queue in the secondary interrupt mask registers - */ - AR5K_REG_WRITE(AR5K_AR5211_SIMR0, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) | - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC)); - AR5K_REG_WRITE(AR5K_AR5211_SIMR1, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR)); - AR5K_REG_WRITE(AR5K_AR5211_SIMR2, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN)); - - return (TRUE); -} - -u_int32_t -ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue) -{ - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Get the transmit queue descriptor pointer from the selected queue - */ - return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue))); -} - -AR5K_BOOL -ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) -{ - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Set the transmit queue descriptor pointer for the selected queue - * (this won't work if the queue is still active) - */ - if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue)) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr); - - return (TRUE); -} - -u_int32_t /*Code from roofnet*/ -ar5k_ar5211_num_tx_pending(struct ath_hal *hal, u_int queue) { - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - return (AR5K_AR5211_QCU_STS(queue) & AR5K_AR5211_QCU_STS_FRMPENDCNT); -} - -AR5K_BOOL -ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue) -{ - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* Return if queue is disabled */ - if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXD, queue)) - return (FALSE); - - /* Start queue */ - AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXE, queue); - - return (TRUE); -} - -AR5K_BOOL /*Fixed delay*/ -ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue) -{ - int i = 100, pending; - - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Schedule TX disable and wait until queue is empty - */ - AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue); - - do { - pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) & - AR5K_AR5211_QCU_STS_FRMPENDCNT; - AR5K_DELAY(100); - } while (--i && pending); - - /* Clear register */ - AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0); - - return (TRUE); -} - -AR5K_BOOL /*O.K. - Initialize tx_desc and clear ds_hw */ -ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, - u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - u_int flags, u_int rtscts_rate, u_int rtscts_duration) -{ - struct ar5k_ar5211_tx_desc *tx_desc; - - tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; - - /*Clear ds_hw*/ - bzero(desc->ds_hw, sizeof(desc->ds_hw)); - - /* - * Validate input - */ - if (tx_tries0 == 0) - return (FALSE); - - /* Initialize status descriptor */ - tx_desc->tx_control_0 = 0; - tx_desc->tx_control_1 = 0; - - /* Setup status descriptor */ - - if ((tx_desc->tx_control_0 = (packet_length & - AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) - return (FALSE); - - tx_desc->tx_control_0 |= - AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | - AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); - tx_desc->tx_control_1 = - AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); - -#define _TX_FLAGS(_c, _flag) \ - if (flags & AR5K_TXDESC_##_flag) \ - tx_desc->tx_control_##_c |= \ - AR5K_AR5211_DESC_TX_CTL##_c##_##_flag - - _TX_FLAGS(0, CLRDMASK); - _TX_FLAGS(0, VEOL); - _TX_FLAGS(0, INTREQ); - _TX_FLAGS(0, RTSENA); - _TX_FLAGS(1, NOACK); - -#undef _TX_FLAGS - - /* - * WEP crap - */ - if (key_index != AR5K_TXKEYIX_INVALID) { - tx_desc->tx_control_0 |= - AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; - tx_desc->tx_control_1 |= - AR5K_REG_SM(key_index, - AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); - } - - return (TRUE); -} - -AR5K_BOOL/*Added an argument *last_desc -need revision -don't clear descriptor here*/ -ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) -{ - struct ar5k_ar5211_tx_desc *tx_desc; - - tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; - - /* Clear status descriptor */ -// bzero(desc->ds_hw, sizeof(desc->ds_hw)); - - /* Validate segment length and initialize the descriptor */ - if ((tx_desc->tx_control_1 = (segment_length & - AR5K_AR5211_DESC_TX_CTL1_BUF_LEN)) != segment_length) - return (FALSE); - - if (first_segment != TRUE) - tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; - - if (last_segment != TRUE) - tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - u_int tx_rate3, u_int tx_tries3) -{ - return (FALSE); -} - -AR5K_STATUS -ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) -{ - struct ar5k_ar5211_tx_status *tx_status; - struct ar5k_ar5211_tx_desc *tx_desc; - - tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0]; - - /* No frame has been send or error */ - if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); - - /* - * Get descriptor status - */ - desc->ds_us.tx.ts_tstamp = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP); - desc->ds_us.tx.ts_shortretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT); - desc->ds_us.tx.ts_longretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT); - desc->ds_us.tx.ts_seqnum = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM); - desc->ds_us.tx.ts_rssi = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH); - desc->ds_us.tx.ts_antenna = 1; - desc->ds_us.tx.ts_status = 0; - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_0, - AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE); - - if ((tx_status->tx_status_0 & - AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { - if (tx_status->tx_status_0 & - AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; - - if (tx_status->tx_status_0 & - AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; - - if (tx_status->tx_status_0 & - AR5K_AR5211_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; - } - - return (AR5K_OK); -} - -AR5K_BOOL -ar5k_ar5211_has_veol(struct ath_hal *hal) -{ - return (TRUE); -} - -void /*Unimplemented*/ -ar5k_ar5211_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) -{ - AR5K_TRACE; - /* XXX */ - return; -} - -/* - * Receive functions - */ - -u_int32_t -ar5k_ar5211_get_rx_buf(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5211_RXDP)); -} - -void -ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) -{ - AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr); -} - -void -ar5k_ar5211_start_rx(struct ath_hal *hal) -{ - AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE); -} - -AR5K_BOOL -ar5k_ar5211_stop_rx_dma(struct ath_hal *hal) -{ - int i; - - AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXD); - - /* - * It may take some time to disable the DMA receive unit - */ - for (i = 2000; - i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0; - i--) - AR5K_DELAY(10); - - return (i > 0 ? TRUE : FALSE); -} - -void -ar5k_ar5211_start_rx_pcu(struct ath_hal *hal) -{ - AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); -} - -void -ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal) -{ - AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); -} - -void -ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, - u_int32_t filter1) -{ - /* Set the multicat filter */ - AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0); - AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1); -} - -AR5K_BOOL -ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) -{ - if (index >= 64) { - return (FALSE); - } else if (index >= 32) { - AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1, - (1 << (index - 32))); - } else { - AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL0, - (1 << index)); - } - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) -{ - - if (index >= 64) { - return (FALSE); - } else if (index >= 32) { - AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL1, - (1 << (index - 32))); - } else { - AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL0, - (1 << index)); - } - - return (TRUE); -} - -u_int32_t -ar5k_ar5211_get_rx_filter(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER)); -} - -void -ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter) -{ - AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter); -} - -AR5K_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ -ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t size, u_int flags) -{ - struct ar5k_ar5211_rx_desc *rx_desc; - - rx_desc = (struct ar5k_ar5211_rx_desc*)&desc->ds_ctl0; - - /* - * Clear ds_hw - * If we don't clean the descriptor, while - * scanning we get too many results, - * most of them virtual, after some secs - * of scanning system halts. M.F. - */ - bzero(desc->ds_hw, sizeof(desc->ds_hw)); - - /*Initialize rx descriptor*/ - rx_desc->rx_control_0 = 0; - rx_desc->rx_control_1 = 0; - - /*Setup descriptor*/ - - if ((rx_desc->rx_control_1 = (size & - AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size) - return (FALSE); - - if (flags & AR5K_RXDESC_INTREQ) - rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ; - - return (TRUE); -} - -AR5K_STATUS -ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) -{ - struct ar5k_ar5211_rx_status *rx_status; - - rx_status = (struct ar5k_ar5211_rx_status*)&desc->ds_hw[0]; - - /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); - - /* - * Frame receive status - */ - desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE); - desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA; - desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_AR5211_DESC_RX_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); - desc->ds_us.rx.rs_status = 0; - - /* - * Key table status - */ - if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) { - desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); - } else { - desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; - } - - /* - * Receive/descriptor errors - */ - if ((rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; - - if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { - desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; - desc->ds_us.rx.rs_phyerr = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); - } - - if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; - } - - return (AR5K_OK); -} - -void /*Added AR5K_NODE_STATS argument*/ -ar5k_ar5211_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) -{ - /* Signal state monitoring is not yet supported */ -} - -/* - * Misc functions - */ - -void -ar5k_ar5211_dump_state(struct ath_hal *hal) -{ -#ifdef AR5K_DEBUG -#define AR5K_PRINT_REGISTER(_x) \ - AR5K_PRINTF("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x)); - - AR5K_PRINT("MAC registers:\n"); - AR5K_PRINT_REGISTER(CR); - AR5K_PRINT_REGISTER(CFG); - AR5K_PRINT_REGISTER(IER); - AR5K_PRINT_REGISTER(RTSD0); - AR5K_PRINT_REGISTER(TXCFG); - AR5K_PRINT_REGISTER(RXCFG); - AR5K_PRINT_REGISTER(RXJLA); - AR5K_PRINT_REGISTER(MIBC); - AR5K_PRINT_REGISTER(TOPS); - AR5K_PRINT_REGISTER(RXNOFRM); - AR5K_PRINT_REGISTER(RPGTO); - AR5K_PRINT_REGISTER(RFCNT); - AR5K_PRINT_REGISTER(MISC); - AR5K_PRINT_REGISTER(PISR); - AR5K_PRINT_REGISTER(SISR0); - AR5K_PRINT_REGISTER(SISR1); - AR5K_PRINT_REGISTER(SISR3); - AR5K_PRINT_REGISTER(SISR4); - AR5K_PRINT_REGISTER(QCU_TXE); - AR5K_PRINT_REGISTER(QCU_TXD); - AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); - AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); - AR5K_PRINT_REGISTER(DCU_FP); - AR5K_PRINT_REGISTER(DCU_TXP); - AR5K_PRINT_REGISTER(DCU_TX_FILTER); - AR5K_PRINT_REGISTER(RC); - AR5K_PRINT_REGISTER(SCR); - AR5K_PRINT_REGISTER(INTPEND); - AR5K_PRINT_REGISTER(PCICFG); - AR5K_PRINT_REGISTER(GPIOCR); - AR5K_PRINT_REGISTER(GPIODO); - AR5K_PRINT_REGISTER(SREV); - AR5K_PRINT_REGISTER(EEPROM_BASE); - AR5K_PRINT_REGISTER(EEPROM_DATA); - AR5K_PRINT_REGISTER(EEPROM_CMD); - AR5K_PRINT_REGISTER(EEPROM_CFG); - AR5K_PRINT_REGISTER(PCU_MIN); - AR5K_PRINT_REGISTER(STA_ID0); - AR5K_PRINT_REGISTER(STA_ID1); - AR5K_PRINT_REGISTER(BSS_ID0); - AR5K_PRINT_REGISTER(SLOT_TIME); - AR5K_PRINT_REGISTER(TIME_OUT); - AR5K_PRINT_REGISTER(RSSI_THR); - AR5K_PRINT_REGISTER(BEACON); - AR5K_PRINT_REGISTER(CFP_PERIOD); - AR5K_PRINT_REGISTER(TIMER0); - AR5K_PRINT_REGISTER(TIMER2); - AR5K_PRINT_REGISTER(TIMER3); - AR5K_PRINT_REGISTER(CFP_DUR); - AR5K_PRINT_REGISTER(MCAST_FIL0); - AR5K_PRINT_REGISTER(MCAST_FIL1); - AR5K_PRINT_REGISTER(DIAG_SW); - AR5K_PRINT_REGISTER(TSF_U32); - AR5K_PRINT_REGISTER(ADDAC_TEST); - AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); - AR5K_PRINT_REGISTER(LAST_TSTP); - AR5K_PRINT_REGISTER(NAV); - AR5K_PRINT_REGISTER(RTS_OK); - AR5K_PRINT_REGISTER(ACK_FAIL); - AR5K_PRINT_REGISTER(FCS_FAIL); - AR5K_PRINT_REGISTER(BEACON_CNT); - AR5K_PRINT_REGISTER(KEYTABLE_0); - AR5K_PRINT("\n"); - - AR5K_PRINT("PHY registers:\n"); - AR5K_PRINT_REGISTER(PHY_TURBO); - AR5K_PRINT_REGISTER(PHY_AGC); - AR5K_PRINT_REGISTER(PHY_CHIP_ID); - AR5K_PRINT_REGISTER(PHY_AGCCTL); - AR5K_PRINT_REGISTER(PHY_NF); - AR5K_PRINT_REGISTER(PHY_RX_DELAY); - AR5K_PRINT_REGISTER(PHY_IQ); - AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); - AR5K_PRINT_REGISTER(PHY_FC); - AR5K_PRINT_REGISTER(PHY_RADAR); - AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); - AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); - AR5K_PRINT("\n"); -#endif -} - -AR5K_BOOL /*Added arguments*/ -ar5k_ar5211_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) -{ - /* - * We'll ignore this right now. This seems to be some kind of an obscure - * debugging interface for the binary-only HAL. - */ - return (FALSE); -} - -void -ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac) -{ - bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); -} - -AR5K_BOOL -ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) -{ - u_int32_t low_id, high_id; - - /* Set new station ID */ - bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); - - low_id = AR5K_LOW_ID(mac); - high_id = AR5K_HIGH_ID(mac); - - AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id); - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - AR5K_STATUS *status) -{ - ieee80211_regdomain_t ieee_regdomain; - - ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); - - if (ar5k_eeprom_regulation_domain(hal, TRUE, - &ieee_regdomain) == TRUE) { - *status = AR5K_OK; - return (TRUE); - } - - *status = EIO; - - return (FALSE); -} - -void -ar5k_ar5211_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) -{ - u_int32_t led; - - AR5K_REG_DISABLE_BITS(AR5K_AR5211_PCICFG, - AR5K_AR5211_PCICFG_LEDMODE | AR5K_AR5211_PCICFG_LED); - - /* - * Some blinking values, define at your wish - */ - switch (state) { - case AR5K_LED_SCAN: - case AR5K_LED_AUTH: - led = AR5K_AR5211_PCICFG_LEDMODE_PROP | - AR5K_AR5211_PCICFG_LED_PEND; - break; - - case AR5K_LED_INIT: - led = AR5K_AR5211_PCICFG_LEDMODE_PROP | - AR5K_AR5211_PCICFG_LED_NONE; - break; - - case AR5K_LED_ASSOC: - case AR5K_LED_RUN: - led = AR5K_AR5211_PCICFG_LEDMODE_PROP | - AR5K_AR5211_PCICFG_LED_ASSOC; - break; - - default: - led = AR5K_AR5211_PCICFG_LEDMODE_PROM | - AR5K_AR5211_PCICFG_LED_NONE; - break; - } - - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, led); -} - -void /*Removed argument trim_offset for combatibility -need revision*/ -ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid, - u_int16_t assoc_id) -{ - u_int32_t low_id, high_id; - u_int16_t tim_offset = 0; - - /* - * Set BSSID which triggers the "SME Join" operation - */ - low_id = AR5K_LOW_ID(bssid); - high_id = AR5K_HIGH_ID(bssid); - AR5K_REG_WRITE(AR5K_AR5211_BSS_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5211_BSS_ID1, high_id | - ((assoc_id & 0x3fff) << AR5K_AR5211_BSS_ID1_AID_S)); - bcopy(bssid, hal->ah_bssid, IEEE80211_ADDR_LEN); - - if (assoc_id == 0) { - ar5k_ar5211_disable_pspoll(hal); - return; - } - - AR5K_REG_WRITE(AR5K_AR5211_BEACON, - (AR5K_REG_READ(AR5K_AR5211_BEACON) & - ~AR5K_AR5211_BEACON_TIM) | - (((tim_offset ? tim_offset + 4 : 0) << - AR5K_AR5211_BEACON_TIM_S) & - AR5K_AR5211_BEACON_TIM)); - - ar5k_ar5211_enable_pspoll(hal, NULL, 0); -} - -AR5K_BOOL /*New*/ -ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) -{ - /*Not supported in 5211*/ - AR5K_TRACE; - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) -{ - if (gpio > AR5K_AR5211_NUM_GPIO) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, - (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) - | AR5K_AR5211_GPIOCR_ALL(gpio)); - - return (TRUE); -} - -AR5K_BOOL -ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) -{ - if (gpio > AR5K_AR5211_NUM_GPIO) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, - (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) - | AR5K_AR5211_GPIOCR_NONE(gpio)); - - return (TRUE); -} - -u_int32_t -ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio) -{ - if (gpio > AR5K_AR5211_NUM_GPIO) - return (0xffffffff); - - /* GPIO input magic */ - return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) & - AR5K_AR5211_GPIODI_M) >> gpio) & 0x1); -} - -AR5K_BOOL -ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) -{ - u_int32_t data; - - if (gpio > AR5K_AR5211_NUM_GPIO) - return (FALSE); - - /* GPIO output magic */ - data = AR5K_REG_READ(AR5K_AR5211_GPIODO); - - data &= ~(1 << gpio); - data |= (val&1) << gpio; - - AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data); - - return (TRUE); -} - -void -ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio, - u_int32_t interrupt_level) -{ - u_int32_t data; - - if (gpio > AR5K_AR5211_NUM_GPIO) - return; - - /* - * Set the GPIO interrupt - */ - data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) & - ~(AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_SELH | - AR5K_AR5211_GPIOCR_INT_ENA | AR5K_AR5211_GPIOCR_ALL(gpio))) | - (AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_ENA); - - AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, - interrupt_level ? data : (data | AR5K_AR5211_GPIOCR_INT_SELH)); - - hal->ah_imr |= AR5K_AR5211_PIMR_GPIO; - - /* Enable GPIO interrupts */ - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_AR5211_PIMR_GPIO); -} - -u_int32_t -ar5k_ar5211_get_tsf32(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5211_TSF_L32)); -} - -u_int64_t -ar5k_ar5211_get_tsf64(struct ath_hal *hal) -{ - u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32); - - return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32)); -} - -void -ar5k_ar5211_reset_tsf(struct ath_hal *hal) -{ - AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON, - AR5K_AR5211_BEACON_RESET_TSF); -} - -u_int16_t -ar5k_ar5211_get_regdomain(struct ath_hal *hal) -{ - return (ar5k_get_regdomain(hal)); -} - -AR5K_BOOL -ar5k_ar5211_detect_card_present(struct ath_hal *hal) -{ - u_int16_t magic; - - /* - * Checking the EEPROM's magic value could be an indication - * if the card is still present. I didn't find another suitable - * way to do this. - */ - if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (FALSE); - - return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); -} - -void -ar5k_ar5211_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) -{ - statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL); - statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL); - statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK); - statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL); - statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT); -} - -void /*Unimplemented*/ -ar5k_ar5211_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) -{ - AR5K_TRACE; - return; -} - -AR5K_RFGAIN -ar5k_ar5211_get_rf_gain(struct ath_hal *hal) -{ - return (AR5K_RFGAIN_INACTIVE); -} - -AR5K_BOOL -ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time) -{ - if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time); - - return (TRUE); -} - -u_int -ar5k_ar5211_get_slot_time(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff); -} - -AR5K_BOOL -ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout) -{ - if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK), - hal->ah_turbo) <= timeout) - return (FALSE); - - AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_ACK, - ar5k_htoclock(timeout, hal->ah_turbo)); - - return (TRUE); -} - -u_int -ar5k_ar5211_get_ack_timeout(struct ath_hal *hal) -{ - return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), - AR5K_AR5211_TIME_OUT_ACK), hal->ah_turbo)); -} - -AR5K_BOOL -ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout) -{ - if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS), - hal->ah_turbo) <= timeout) - return (FALSE); - - AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_CTS, - ar5k_htoclock(timeout, hal->ah_turbo)); - - return (TRUE); -} - -u_int -ar5k_ar5211_get_cts_timeout(struct ath_hal *hal) -{ - return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), - AR5K_AR5211_TIME_OUT_CTS), hal->ah_turbo)); -} - -AR5K_STATUS /*New*/ -ar5k_ar5211_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t *result) -{ - AR5K_TRACE; - - switch (cap_type) { - case AR5K_CAP_REG_DMN: - if (result){ - *result = ar5k_get_regdomain(hal); - goto yes; - } - case AR5K_CAP_CIPHER: - switch (capability) { - case AR5K_CIPHER_WEP: goto yes; - default: goto no; - } - case AR5K_CAP_NUM_TXQUEUES: - if (result) { - *result = AR5K_AR5211_TX_NUM_QUEUES; - goto yes; - } - case AR5K_CAP_VEOL: - goto yes; - case AR5K_CAP_COMPRESSION: - goto yes; - case AR5K_CAP_BURST: - goto yes; - case AR5K_CAP_TPC: - goto yes; - case AR5K_CAP_BSSIDMASK: - goto yes; - case AR5K_CAP_XR: - goto yes; - default: - goto no; - } - - no: - return (AR5K_EINVAL); - yes: - return AR5K_OK; - -} - -AR5K_BOOL -ar5k_ar5211_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) -{ - - AR5K_TRACE; - if (status) { - *status = AR5K_OK; - } - return (FALSE); -} - -/* - * Key table (WEP) functions - */ - -AR5K_BOOL -ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) -{ - /* - * The AR5211 only supports WEP - */ - if (cipher == AR5K_CIPHER_WEP) - return (TRUE); - - return (FALSE); -} - -u_int32_t -ar5k_ar5211_get_keycache_size(struct ath_hal *hal) -{ - return (AR5K_AR5211_KEYCACHE_SIZE); -} - -AR5K_BOOL -ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry) -{ - int i; - - AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); - - for (i = 0; i < AR5K_AR5211_KEYCACHE_SIZE; i++) - AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0); - - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry) -{ - AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); - - /* - * Check the validation flag at the end of the entry - */ - if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) & - AR5K_AR5211_KEYTABLE_VALID) - return (TRUE); - - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry, - const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) -{ - int i; - u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2]; - - AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); - - bzero(&key_v, sizeof(key_v)); - - switch (keyval->wk_len) { - case AR5K_KEYVAL_LENGTH_40: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 1); - key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_40; - break; - - case AR5K_KEYVAL_LENGTH_104: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 1); - key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_104; - break; - - case AR5K_KEYVAL_LENGTH_128: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 4); - key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_128; - break; - - default: - /* Unsupported key length (not WEP40/104/128) */ - return (FALSE); - } - - for (i = 0; i < AR5K_ELEMENTS(key_v); i++) - AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), key_v[i]); - - return (ar5k_ar5211_set_key_lladdr(hal, entry, mac)); -} - -AR5K_BOOL -ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, - const u_int8_t *mac) -{ - u_int32_t low_id, high_id; - const u_int8_t *mac_v; - - /* - * Invalid entry (key table overflow) - */ - AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); - - /* MAC may be NULL if it's a broadcast key */ - mac_v = mac == NULL ? etherbroadcastaddr : mac; - - low_id = AR5K_LOW_ID(mac_v); - high_id = AR5K_HIGH_ID(mac_v); - high_id |= AR5K_AR5211_KEYTABLE_VALID; - - AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id); - AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id); - - return (TRUE); -} - -/* - * Power management functions - */ - -AR5K_BOOL -ar5k_ar5211_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, - AR5K_BOOL set_chip, u_int16_t sleep_duration) -{ - u_int32_t staid; - int i; - - staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1); - - switch (mode) { - case AR5K_PM_AUTO: - staid &= ~AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; - /* fallthrough */ - case AR5K_PM_NETWORK_SLEEP: - if (set_chip == TRUE) { - AR5K_REG_WRITE(AR5K_AR5211_SCR, - AR5K_AR5211_SCR_SLE | sleep_duration); - } - staid |= AR5K_AR5211_STA_ID1_PWR_SV; - break; - - case AR5K_PM_FULL_SLEEP: - if (set_chip == TRUE) { - AR5K_REG_WRITE(AR5K_AR5211_SCR, - AR5K_AR5211_SCR_SLE_SLP); - } - staid |= AR5K_AR5211_STA_ID1_PWR_SV; - break; - - case AR5K_PM_AWAKE: - if (set_chip == FALSE) - goto commit; - - AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE); - - for (i = 5000; i > 0; i--) { - /* Check if the AR5211 did wake up */ - if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) & - AR5K_AR5211_PCICFG_SPWR_DN) == 0) - break; - - /* Wait a bit and retry */ - AR5K_DELAY(200); - AR5K_REG_WRITE(AR5K_AR5211_SCR, - AR5K_AR5211_SCR_SLE_WAKE); - } - - /* Fail if the AR5211 didn't wake up */ - if (i <= 0) - return (FALSE); - - staid &= ~AR5K_AR5211_STA_ID1_PWR_SV; - break; - - default: - return (FALSE); - } - - commit: - hal->ah_power_mode = mode; - - AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid); - - return (TRUE); -} - -AR5K_POWER_MODE -ar5k_ar5211_get_power_mode(struct ath_hal *hal) -{ - return (hal->ah_power_mode); -} - -AR5K_BOOL -ar5k_ar5211_query_pspoll_support(struct ath_hal *hal) -{ - /* nope */ - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5211_init_pspoll(struct ath_hal *hal) -{ - /* - * Not used on the AR5211 - */ - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, - u_int16_t assoc_id) -{ - return (FALSE); -} - -AR5K_BOOL -ar5k_ar5211_disable_pspoll(struct ath_hal *hal) -{ - return (FALSE); -} - -AR5K_BOOL /*Unimplemented*/ -ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int32_t power) -{ -// AR5K_CHANNEL *channel = &hal->ah_current_channel; - - AR5K_TRACE; - AR5K_PRINTF("changing txpower to %d\n unimplemented ;-(",power); - return FALSE; -} - -/* - * Beacon functions - */ - -void -ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, - u_int32_t interval) -{ - u_int32_t timer1, timer2, timer3; - - /* - * Set the additional timers by mode - */ - switch (hal->ah_op_mode) { - case AR5K_M_STA: - timer1 = 0x0000ffff; - timer2 = 0x0007ffff; - break; - - default: - timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << - 0x00000003; - timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << - 0x00000003; - } - - timer3 = next_beacon + - (hal->ah_atim_window ? hal->ah_atim_window : 1); - - /* - * Enable all timers and set the beacon register - * (next beacon, DMA beacon, software beacon, ATIM window time) - */ - AR5K_REG_WRITE(AR5K_AR5211_TIMER0, next_beacon); - AR5K_REG_WRITE(AR5K_AR5211_TIMER1, timer1); - AR5K_REG_WRITE(AR5K_AR5211_TIMER2, timer2); - AR5K_REG_WRITE(AR5K_AR5211_TIMER3, timer3); - - AR5K_REG_WRITE(AR5K_AR5211_BEACON, interval & - (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_RESET_TSF | - AR5K_AR5211_BEACON_ENABLE)); -} - -void /*Removed arguments - should be changed through *state - review AR5K_BEACON_STATE struct*/ -ar5k_ar5211_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) -{ - u_int32_t cfp_period, next_cfp; - - u_int32_t dtim_count = 0; /* XXX */ - u_int32_t cfp_count = 0; /* XXX */ - u_int32_t tsf = 0; /* XXX */ - - /* Return on an invalid beacon state */ - if (state->bs_interval < 1) - return; - - /* - * PCF support? - */ - if (state->bs_cfp_period > 0) { - /* Enable CFP mode and set the CFP and timer registers */ - cfp_period = state->bs_cfp_period * state->bs_dtim_period * - state->bs_interval; - next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * - state->bs_interval; - - AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, - AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | - AR5K_AR5211_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_AR5211_CFP_PERIOD, cfp_period); - AR5K_REG_WRITE(AR5K_AR5211_CFP_DUR, state->bs_cfp_max_duration); - AR5K_REG_WRITE(AR5K_AR5211_TIMER2, - (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); - } else { - /* Disable PCF mode */ - AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, - AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | - AR5K_AR5211_STA_ID1_PCF); - } - - /* - * Enable the beacon timer register - */ - AR5K_REG_WRITE(AR5K_AR5211_TIMER0, state->bs_next_beacon); - - /* - * Start the beacon timers - */ - AR5K_REG_WRITE(AR5K_AR5211_BEACON, - (AR5K_REG_READ(AR5K_AR5211_BEACON) &~ - (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_TIM)) | - AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, - AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, - AR5K_AR5211_BEACON_PERIOD)); - - /* - * Write new beacon miss threshold, if it appears to be valid - */ - if ((AR5K_AR5211_RSSI_THR_BMISS >> AR5K_AR5211_RSSI_THR_BMISS_S) < - state->bs_bmiss_threshold) - return; - - AR5K_REG_WRITE_BITS(AR5K_AR5211_RSSI_THR_M, - AR5K_AR5211_RSSI_THR_BMISS, state->bs_bmiss_threshold); - AR5K_REG_WRITE_BITS(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLDUR, - (state->bs_sleep_duration - 3) << 3); -} - -void -ar5k_ar5211_reset_beacon(struct ath_hal *hal) -{ - /* - * Disable beacon timer - */ - AR5K_REG_WRITE(AR5K_AR5211_TIMER0, 0); - - /* - * Disable some beacon register values - */ - AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, - AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5211_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD); -} - -AR5K_BOOL -ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) -{ - AR5K_BOOL ret; - - /* - * Wait for beaconn queue to be done - */ - ret = ar5k_register_timeout(hal, - AR5K_AR5211_QCU_STS(AR5K_TX_QUEUE_ID_BEACON), - AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, FALSE); - - if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) - return (FALSE); - - return (ret); -} - -/* - * Interrupt handling - */ - -AR5K_BOOL -ar5k_ar5211_is_intr_pending(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? FALSE : TRUE); -} - -AR5K_BOOL -ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) -{ - u_int32_t data; - - /* - * Read interrupt status from the Read-And-Clear shadow register - */ - data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR); - - /* - * Get abstract interrupt mask (HAL-compatible) - */ - *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; - - if (data == AR5K_INT_NOCARD) - return (FALSE); - - if (data & (AR5K_AR5211_PISR_RXOK | AR5K_AR5211_PISR_RXERR)) - *interrupt_mask |= AR5K_INT_RX; - - if (data & (AR5K_AR5211_PISR_TXOK | AR5K_AR5211_PISR_TXERR)) - *interrupt_mask |= AR5K_INT_TX; - - if (data & (AR5K_AR5211_PISR_HIUERR)) - *interrupt_mask |= AR5K_INT_FATAL; - - /* - * Special interrupt handling (not caught by the driver) - */ - if (((*interrupt_mask) & AR5K_AR5211_PISR_RXPHY) && - hal->ah_radar.r_enabled == TRUE) - ar5k_radar_alert(hal); - - return (TRUE); -} - -u_int32_t -ar5k_ar5211_get_intr(struct ath_hal *hal) -{ - /* Return the interrupt mask stored previously */ - return (hal->ah_imr); -} - -AR5K_INT -ar5k_ar5211_set_intr(struct ath_hal *hal, AR5K_INT new_mask) -{ - AR5K_INT old_mask, int_mask; - - /* - * Disable card interrupts to prevent any race conditions - * (they will be re-enabled afterwards). - */ - AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); - - old_mask = hal->ah_imr; - - /* - * Add additional, chipset-dependent interrupt mask flags - * and write them to the IMR (interrupt mask register). - */ - int_mask = new_mask & AR5K_INT_COMMON; - - if (new_mask & AR5K_INT_RX) - int_mask |= - AR5K_AR5211_PIMR_RXOK | - AR5K_AR5211_PIMR_RXERR | - AR5K_AR5211_PIMR_RXORN | - AR5K_AR5211_PIMR_RXDESC; - - if (new_mask & AR5K_INT_TX) - int_mask |= - AR5K_AR5211_PIMR_TXOK | - AR5K_AR5211_PIMR_TXERR | - AR5K_AR5211_PIMR_TXDESC | - AR5K_AR5211_PIMR_TXURN; - - if (new_mask & AR5K_INT_FATAL) { - int_mask |= AR5K_AR5211_PIMR_HIUERR; - AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2, - AR5K_AR5211_SIMR2_MCABT | - AR5K_AR5211_SIMR2_SSERR | - AR5K_AR5211_SIMR2_DPERR); - } - - AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask); - - /* Store new interrupt mask */ - hal->ah_imr = new_mask; - - /* ..re-enable interrupts */ - AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); - - return (old_mask); -} - -/* - * Misc internal functions - */ - -AR5K_BOOL -ar5k_ar5211_get_capabilities(struct ath_hal *hal) -{ - u_int16_t ee_header; - - /* Capabilities stored in the EEPROM */ - ee_header = hal->ah_capabilities.cap_eeprom.ee_header; - - /* - * XXX The AR5211 tranceiver supports frequencies from 4920 to 6100GHz - * XXX and from 2312 to 2732GHz. There are problems with the current - * XXX ieee80211 implementation because the IEEE channel mapping - * XXX does not support negative channel numbers (2312MHz is channel - * XXX -19). Of course, this doesn't matter because these channels - * XXX are out of range but some regulation domains like MKK (Japan) - * XXX will support frequencies somewhere around 4.8GHz. - */ - - /* - * Set radio capabilities - */ - - if (AR5K_EEPROM_HDR_11A(ee_header)) { - hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ - hal->ah_capabilities.cap_range.range_5ghz_max = 6100; - - /* Set supported modes */ - hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO; - } - - /* This chip will support 802.11b if the 2GHz radio is connected */ - if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { - hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ - hal->ah_capabilities.cap_range.range_2ghz_max = 2732; - - if (AR5K_EEPROM_HDR_11B(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; -#if 0 - if (AR5K_EEPROM_HDR_11G(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; -#endif - } - - /* GPIO */ - hal->ah_gpio_npins = AR5K_AR5211_NUM_GPIO; - - /* Set number of supported TX queues */ - hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES; - - return (TRUE); -} - -void -ar5k_ar5211_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) -{ - /* - * Enable radar detection - */ - AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); - - if (enable == TRUE) { - AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, - AR5K_AR5211_PHY_RADAR_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, - AR5K_AR5211_PIMR_RXPHY); - } else { - AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, - AR5K_AR5211_PHY_RADAR_DISABLE); - AR5K_REG_DISABLE_BITS(AR5K_AR5211_PIMR, - AR5K_AR5211_PIMR_RXPHY); - } - - AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); -} - -/* - * EEPROM access functions - */ - -AR5K_BOOL -ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ? - TRUE : FALSE); -} - -int -ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) -{ - u_int32_t status, i; - - /* - * Initialize EEPROM access - */ - AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset); - AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, - AR5K_AR5211_EEPROM_CMD_READ); - - for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { - status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); - if (status & AR5K_AR5211_EEPROM_STAT_RDDONE) { - if (status & AR5K_AR5211_EEPROM_STAT_RDERR) - return (EIO); - *data = (u_int16_t) - (AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff); - return (0); - } - AR5K_DELAY(15); - } - - return (ETIMEDOUT); -} - -int -ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) -{ - u_int32_t status, timeout; - - /* Enable eeprom access */ - AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, - AR5K_AR5211_EEPROM_CMD_RESET); - AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, - AR5K_AR5211_EEPROM_CMD_WRITE); - - /* - * Prime write pump - */ - AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset - 1); - - for (timeout = 10000; timeout > 0; timeout--) { - AR5K_DELAY(1); - status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); - if (status & AR5K_AR5211_EEPROM_STAT_WRDONE) { - if (status & AR5K_AR5211_EEPROM_STAT_WRERR) - return (EIO); - return (0); - } - } - - return (ETIMEDOUT); -} - -/* - * RF register settings - */ - -void -ar5k_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, - u_int ee_mode) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - struct ar5k_ar5211_ini_rf rf[AR5K_ELEMENTS(ar5211_rf)]; - u_int32_t ob, db, obdb, xpds, xpdp, x_gain; - u_int i; - - bcopy(ar5211_rf, rf, sizeof(rf)); - obdb = 0; - - if (freq == AR5K_INI_RFGAIN_2GHZ && - hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { - ob = ar5k_bitswap(ee->ee_ob[ee_mode][0], 3); - db = ar5k_bitswap(ee->ee_db[ee_mode][0], 3); - rf[25].rf_value[freq] = - ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); - rf[26].rf_value[freq] = - (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | - (rf[26].rf_value[freq] & ~0xf); - } - - if (freq == AR5K_INI_RFGAIN_5GHZ) { - /* For 11a and Turbo */ - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); - } - - ob = ee->ee_ob[ee_mode][obdb]; - db = ee->ee_db[ee_mode][obdb]; - x_gain = ee->ee_x_gain[ee_mode]; - xpds = ee->ee_xpd[ee_mode]; - xpdp = !xpds; - - rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | - (((ar5k_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); - rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | - ((ar5k_bitswap(x_gain, 4) >> 1) & 0x7); - rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | - ((ar5k_bitswap(ob, 3) << 7) & 0x80); - rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | - ((ar5k_bitswap(ob, 3) >> 1) & 0x3); - rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | - ((ar5k_bitswap(db, 3) << 2) & 0x1c); - rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | - ((xpds << 3) & 0x8); - - for (i = 0; i < AR5K_ELEMENTS(rf); i++) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, - rf[i].rf_value[freq]); - } - - hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; -} Index: ar5212.c =================================================================== --- ar5212.c (revision 2185) +++ ar5212.c (revision 2232) @@ -1,3199 +0,0 @@ -/* - * Copyright (c) 2004-2007 Reyk Floeter - * Copyright (c) 2006-2007 Nick Kossifidis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $Id$ - */ - -/* - * HAL interface for the Atheros AR5001 Wireless LAN chipset - * (AR5212 + AR5111/AR5112). - */ - -#include "ar5xxx.h" -#include "ar5212reg.h" -#include "ar5212var.h" - -AR5K_BOOL ar5k_ar5212_nic_reset(struct ath_hal *, u_int32_t); -AR5K_BOOL ar5k_ar5212_nic_wakeup(struct ath_hal *, u_int16_t); -u_int16_t ar5k_ar5212_radio_revision(struct ath_hal *, AR5K_CHIP); -void ar5k_ar5212_fill(struct ath_hal *); -AR5K_BOOL ar5k_ar5212_txpower(struct ath_hal *, AR5K_CHANNEL *, u_int); - - -/* - * Initial register setting for the AR5212 - */ -static const struct ar5k_ar5212_ini ar5212_ini[] = - AR5K_AR5212_INI; -static const struct ar5k_ar5212_ini_mode ar5212_mode[] = - AR5K_AR5212_INI_MODE; - -AR5K_HAL_FUNCTIONS(extern, ar5k_ar5212,); - - -void /*Functions added*/ -ar5k_ar5212_fill(struct ath_hal *hal) -{ - hal->ah_magic = AR5K_AR5212_MAGIC; - - /* - * Init/Exit functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, get_rate_table); - AR5K_HAL_FUNCTION(hal, ar5212, detach); - - /* - * Reset functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, reset); - AR5K_HAL_FUNCTION(hal, ar5212, set_opmode); - AR5K_HAL_FUNCTION(hal, ar5212, calibrate); - - /* - * TX functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, update_tx_triglevel); - AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queueprops); - AR5K_HAL_FUNCTION(hal, ar5212, release_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5212, reset_tx_queue); - AR5K_HAL_FUNCTION(hal, ar5212, get_tx_buf); - AR5K_HAL_FUNCTION(hal, ar5212, put_tx_buf); - AR5K_HAL_FUNCTION(hal, ar5212, tx_start); - AR5K_HAL_FUNCTION(hal, ar5212, stop_tx_dma); - AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, setup_xtx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, fill_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, proc_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, has_veol); - - /* - * RX functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, get_rx_buf); - AR5K_HAL_FUNCTION(hal, ar5212, put_rx_buf); - AR5K_HAL_FUNCTION(hal, ar5212, start_rx); - AR5K_HAL_FUNCTION(hal, ar5212, stop_rx_dma); - AR5K_HAL_FUNCTION(hal, ar5212, start_rx_pcu); - AR5K_HAL_FUNCTION(hal, ar5212, stop_pcu_recv); - AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filter); - AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filterindex); - AR5K_HAL_FUNCTION(hal, ar5212, clear_mcast_filter_idx); - AR5K_HAL_FUNCTION(hal, ar5212, get_rx_filter); - AR5K_HAL_FUNCTION(hal, ar5212, set_rx_filter); - AR5K_HAL_FUNCTION(hal, ar5212, setup_rx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, proc_rx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, set_rx_signal); - - /* - * Misc functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, dump_state); - AR5K_HAL_FUNCTION(hal, ar5212, get_diag_state); - AR5K_HAL_FUNCTION(hal, ar5212, get_lladdr); - AR5K_HAL_FUNCTION(hal, ar5212, set_lladdr); - AR5K_HAL_FUNCTION(hal, ar5212, set_regdomain); - AR5K_HAL_FUNCTION(hal, ar5212, set_ledstate); - AR5K_HAL_FUNCTION(hal, ar5212, set_associd); - AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_input); - AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_output); - AR5K_HAL_FUNCTION(hal, ar5212, get_gpio); - AR5K_HAL_FUNCTION(hal, ar5212, set_gpio); - AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_intr); - AR5K_HAL_FUNCTION(hal, ar5212, get_tsf32); - AR5K_HAL_FUNCTION(hal, ar5212, get_tsf64); - AR5K_HAL_FUNCTION(hal, ar5212, reset_tsf); - AR5K_HAL_FUNCTION(hal, ar5212, get_regdomain); - AR5K_HAL_FUNCTION(hal, ar5212, detect_card_present); - AR5K_HAL_FUNCTION(hal, ar5212, update_mib_counters); - AR5K_HAL_FUNCTION(hal, ar5212, get_rf_gain); - AR5K_HAL_FUNCTION(hal, ar5212, set_slot_time); - AR5K_HAL_FUNCTION(hal, ar5212, get_slot_time); - AR5K_HAL_FUNCTION(hal, ar5212, set_ack_timeout); - AR5K_HAL_FUNCTION(hal, ar5212, get_ack_timeout); - AR5K_HAL_FUNCTION(hal, ar5212, set_cts_timeout); - AR5K_HAL_FUNCTION(hal, ar5212, get_cts_timeout); - - /* - * Key table (WEP) functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, is_cipher_supported); - AR5K_HAL_FUNCTION(hal, ar5212, get_keycache_size); - AR5K_HAL_FUNCTION(hal, ar5212, reset_key); - AR5K_HAL_FUNCTION(hal, ar5212, is_key_valid); - AR5K_HAL_FUNCTION(hal, ar5212, set_key); - AR5K_HAL_FUNCTION(hal, ar5212, set_key_lladdr); - - /* - * Power management functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, set_power); - AR5K_HAL_FUNCTION(hal, ar5212, get_power_mode); - AR5K_HAL_FUNCTION(hal, ar5212, query_pspoll_support); - AR5K_HAL_FUNCTION(hal, ar5212, init_pspoll); - AR5K_HAL_FUNCTION(hal, ar5212, enable_pspoll); - AR5K_HAL_FUNCTION(hal, ar5212, disable_pspoll); - - /* - * Beacon functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, init_beacon); - AR5K_HAL_FUNCTION(hal, ar5212, set_beacon_timers); - AR5K_HAL_FUNCTION(hal, ar5212, reset_beacon); - AR5K_HAL_FUNCTION(hal, ar5212, wait_for_beacon); - - /* - * Interrupt functions - */ - AR5K_HAL_FUNCTION(hal, ar5212, is_intr_pending); - AR5K_HAL_FUNCTION(hal, ar5212, get_isr); - AR5K_HAL_FUNCTION(hal, ar5212, get_intr); - AR5K_HAL_FUNCTION(hal, ar5212, set_intr); - - /* - * Chipset functions (ar5k-specific, non-HAL) - */ - AR5K_HAL_FUNCTION(hal, ar5212, get_capabilities); - AR5K_HAL_FUNCTION(hal, ar5212, radar_alert); - - /* - * EEPROM access - */ - AR5K_HAL_FUNCTION(hal, ar5212, eeprom_is_busy); - AR5K_HAL_FUNCTION(hal, ar5212, eeprom_read); - AR5K_HAL_FUNCTION(hal, ar5212, eeprom_write); - - /* Functions not found in OpenBSD */ - AR5K_HAL_FUNCTION(hal, ar5212, get_tx_queueprops); - AR5K_HAL_FUNCTION(hal, ar5212, get_capability); - AR5K_HAL_FUNCTION(hal, ar5212, num_tx_pending); - AR5K_HAL_FUNCTION(hal, ar5212, phy_disable); - AR5K_HAL_FUNCTION(hal, ar5212, set_pcu_config); - AR5K_HAL_FUNCTION(hal, ar5212, set_txpower_limit); - AR5K_HAL_FUNCTION(hal, ar5212, set_def_antenna); - AR5K_HAL_FUNCTION(hal, ar5212, get_def_antenna); - AR5K_HAL_FUNCTION(hal, ar5212, set_bssid_mask); - /*Totaly unimplemented*/ - AR5K_HAL_FUNCTION(hal, ar5212, set_capability); - AR5K_HAL_FUNCTION(hal, ar5212, proc_mib_event); - AR5K_HAL_FUNCTION(hal, ar5212, get_tx_inter_queue); - -} - -struct ath_hal * /*Ported & removed an arg from call to set_associd*/ -ar5k_ar5212_attach(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, - AR5K_BUS_HANDLE sh, AR5K_STATUS *status) -{ - struct ath_hal *hal = (struct ath_hal*) sc; - u_int8_t mac[IEEE80211_ADDR_LEN]; - u_int32_t srev; - - AR5K_TRACE; - - ar5k_ar5212_fill(hal); - - /* Bring device out of sleep and reset it's units */ - if (ar5k_ar5212_nic_wakeup(hal, AR5K_INIT_MODE) != TRUE) - return (NULL); - - /* Get MAC, PHY and RADIO revisions */ - srev = AR5K_REG_READ(AR5K_AR5212_SREV); - hal->ah_mac_srev = srev; - hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5212_SREV_VER); - hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5212_SREV_REV); - hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID) & - 0x00ffffffff; - hal->ah_radio_5ghz_revision = - ar5k_ar5212_radio_revision(hal, AR5K_CHIP_5GHZ); - hal->ah_radio_2ghz_revision = - ar5k_ar5212_radio_revision(hal, AR5K_CHIP_2GHZ); - - /* Single chip radio */ - if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) - hal->ah_radio_2ghz_revision = 0; - - /* Identify the chipset (this has to be done in an early step) */ - hal->ah_version = AR5K_AR5212; - hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ? - AR5K_AR5111 : AR5K_AR5112; - hal->ah_phy = AR5K_AR5212_PHY(0); - - bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); - ar5k_ar5212_set_associd(hal, mac, 0); - ar5k_ar5212_get_lladdr(hal, mac); - ar5k_ar5212_set_opmode(hal); - - return (hal); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val) -{ - AR5K_BOOL ret = FALSE; - u_int32_t mask = val ? val : ~0; - - AR5K_TRACE; - - /* Read-and-clear */ - AR5K_REG_READ(AR5K_AR5212_RXDP); - - /* - * Reset the device and wait until success - */ - AR5K_REG_WRITE(AR5K_AR5212_RC, val); - - /* Wait at least 128 PCI clocks */ - AR5K_DELAY(15); - - val &= - AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; - - mask &= - AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; - - ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, FALSE); - - /* - * Reset configuration register - */ - if ((val & AR5K_AR5212_RC_PCU) == 0) - AR5K_REG_WRITE(AR5K_AR5212_CFG, AR5K_AR5212_INIT_CFG); - - return (ret); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_nic_wakeup(struct ath_hal *hal, u_int16_t flags) -{ - u_int32_t turbo, mode, clock; - - turbo = 0; - mode = 0; - clock = 0; - - AR5K_TRACE; - - /* - * Get channel mode flags - */ - - if (hal->ah_radio >= AR5K_AR5112) { - mode = AR5K_AR5212_PHY_MODE_RAD_AR5112; - clock = AR5K_AR5212_PHY_PLL_AR5112; - } else { - mode = AR5K_AR5212_PHY_MODE_RAD_AR5111; - clock = AR5K_AR5212_PHY_PLL_AR5111; - } - - if (flags & CHANNEL_2GHZ) { - mode |= AR5K_AR5212_PHY_MODE_FREQ_2GHZ; - clock |= AR5K_AR5212_PHY_PLL_44MHZ; - } else if (flags & CHANNEL_5GHZ) { - mode |= AR5K_AR5212_PHY_MODE_FREQ_5GHZ; - clock |= AR5K_AR5212_PHY_PLL_40MHZ; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); - } - - if (flags & CHANNEL_CCK) { - mode |= AR5K_AR5212_PHY_MODE_MOD_CCK; - } else if (flags & CHANNEL_OFDM) { - mode |= AR5K_AR5212_PHY_MODE_MOD_OFDM; - } else if (flags & CHANNEL_DYN) { - mode |= AR5K_AR5212_PHY_MODE_MOD_DYN; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); - } - - if (flags & CHANNEL_TURBO) { - turbo = AR5K_AR5212_PHY_TURBO_MODE | - AR5K_AR5212_PHY_TURBO_SHORT; - } - - /* - * Reset and wakeup the device - */ - - /* ...reset chipset and PCI device */ - if (hal->ah_single_chip == FALSE && - ar5k_ar5212_nic_reset(hal,AR5K_AR5212_RC_CHIP | AR5K_AR5212_RC_PCI) == FALSE) { - AR5K_PRINT("failed to reset the AR5212 + PCI chipset\n"); - return (FALSE); - } - - /* ...wakeup */ - if (ar5k_ar5212_set_power(hal, - AR5K_PM_AWAKE, TRUE, 0) == FALSE) { - AR5K_PRINT("failed to resume the AR5212 (again)\n"); - return (FALSE); - } - - /* ...final warm reset */ - if (ar5k_ar5212_nic_reset(hal, 0) == FALSE) { - AR5K_PRINT("failed to warm reset the AR5212\n"); - return (FALSE); - } - - /* ...set the PHY operating mode */ - AR5K_REG_WRITE(AR5K_AR5212_PHY_PLL, clock); - AR5K_DELAY(300); - - AR5K_REG_WRITE(AR5K_AR5212_PHY_MODE, mode); - AR5K_REG_WRITE(AR5K_AR5212_PHY_TURBO, turbo); - - return (TRUE); -} - -u_int16_t /*O.K.*/ -ar5k_ar5212_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) -{ - int i; - u_int32_t srev; - u_int16_t ret; - - AR5K_TRACE; - - /* - * Set the radio chip access register - */ - switch (chip) { - case AR5K_CHIP_2GHZ: - AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_2GHZ); - break; - case AR5K_CHIP_5GHZ: - AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); - break; - default: - return (0); - } - - AR5K_DELAY(2000); - - /* ...wait until PHY is ready and read the selected radio revision */ - AR5K_REG_WRITE(AR5K_AR5212_PHY(0x34), 0x00001c16); - - for (i = 0; i < 8; i++) - AR5K_REG_WRITE(AR5K_AR5212_PHY(0x20), 0x00010000); - srev = (AR5K_REG_READ(AR5K_AR5212_PHY(0x100)) >> 24) & 0xff; - - ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); - - /* Reset to the 5GHz mode */ - AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); - - return (ret); -} - -const AR5K_RATE_TABLE * /*O.K.*/ -ar5k_ar5212_get_rate_table(struct ath_hal *hal, u_int mode) -{ - - AR5K_TRACE; - - switch (mode) { - case AR5K_MODE_11A: - return (&hal->ah_rt_11a); - case AR5K_MODE_TURBO: - return (&hal->ah_rt_turbo); - case AR5K_MODE_11B: - return (&hal->ah_rt_11b); - case AR5K_MODE_11G: - return (&hal->ah_rt_11g); - case AR5K_MODE_XR: - return (&hal->ah_rt_xr); - default: - return (NULL); - } - - return (NULL); -} - -void /*O.K.*/ -ar5k_ar5212_detach(struct ath_hal *hal) -{ - AR5K_TRACE; - - if (hal->ah_rf_banks != NULL) - free(hal->ah_rf_banks, M_DEVBUF); - - /* - * Free HAL structure, assume interrupts are down - */ - free(hal, M_DEVBUF); -} - -AR5K_BOOL /*New*/ -ar5k_ar5212_phy_disable(struct ath_hal *hal) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_DISABLE); - return TRUE; -} - -AR5K_BOOL /*Ported & removed last argument from call to set_associd*/ -ar5k_ar5212_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, - AR5K_BOOL change_channel, AR5K_STATUS *status) -{ - struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int8_t mac[IEEE80211_ADDR_LEN]; - u_int32_t data, s_seq, s_ant, s_led[3]; - u_int i, phy, mode, freq, off, ee_mode, ant[2]; - const AR5K_RATE_TABLE *rt; - - AR5K_TRACE; - - *status = AR5K_OK; - - /* - * Save some registers before a reset - */ - if (change_channel == TRUE) { - s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0)); - s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA); - } else { - s_seq = 0; - s_ant = 1; - } - - s_led[0] = AR5K_REG_READ(AR5K_AR5212_PCICFG) & - AR5K_AR5212_PCICFG_LEDSTATE; - s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR); - s_led[2] = AR5K_REG_READ(AR5K_AR5212_GPIODO); - - if (change_channel == TRUE && hal->ah_rf_banks != NULL) - ar5k_ar5212_get_rf_gain(hal); - - if (ar5k_ar5212_nic_wakeup(hal, channel->channel_flags) == FALSE) { - *status = AR5K_EIO; - return (FALSE); - } - - /* - * Initialize operating mode - */ - hal->ah_op_mode = op_mode; - - if (hal->ah_radio == AR5K_AR5111) { - phy = AR5K_INI_PHY_5111; - } else if (hal->ah_radio == AR5K_AR5112) { - phy = AR5K_INI_PHY_5112; - } else { - AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); - *status = AR5K_EINVAL; - return (FALSE); - } - - switch (channel->channel_flags & CHANNEL_MODES) { - case CHANNEL_A: - mode = AR5K_INI_VAL_11A; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - case CHANNEL_B: - mode = AR5K_INI_VAL_11B; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11B; - break; - case CHANNEL_G: - mode = AR5K_INI_VAL_11G; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11G; - break; - case CHANNEL_T: - mode = AR5K_INI_VAL_11A_TURBO; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - case CHANNEL_TG: - mode = AR5K_INI_VAL_11G_TURBO; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11G; - break; - case CHANNEL_XR: - mode = AR5K_INI_VAL_XR; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - default: - AR5K_PRINTF("invalid channel: %d\n", channel->freq); - *status = AR5K_EINVAL; - return (FALSE); - } - - /* PHY access enable */ - AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); - - /* - * Write initial mode settings - */ - for (i = 0; i < AR5K_ELEMENTS(ar5212_mode); i++) { - if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) - off = AR5K_INI_PHY_511X; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && - hal->ah_radio == AR5K_AR5111) - off = AR5K_INI_PHY_5111; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 && - hal->ah_radio == AR5K_AR5112) - off = AR5K_INI_PHY_5112; - else - continue; - - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_mode[i].mode_register, - ar5212_mode[i].mode_value[off][mode]); - } - - /* - * Write initial register settings - */ - for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) { - if (change_channel == TRUE && - ar5212_ini[i].ini_register >= AR5K_AR5212_PCU_MIN && - ar5212_ini[i].ini_register <= AR5K_AR5212_PCU_MAX) - continue; - - if ((hal->ah_radio == AR5K_AR5111 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) || - (hal->ah_radio == AR5K_AR5112 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_ini[i].ini_register, - ar5212_ini[i].ini_value); - } - } - - /* - * Write initial RF gain settings - */ - if (ar5k_rfgain(hal, phy, freq) == FALSE) { - *status = AR5K_EIO; - return (FALSE); - } - - AR5K_DELAY(1000); - - /* - * Set rate duration table - */ - rt = ar5k_ar5212_get_rate_table(hal, - channel->channel_flags & CHANNEL_TURBO ? - AR5K_MODE_TURBO : AR5K_MODE_XR); - - for (i = 0; i < rt->rate_count; i++) { - AR5K_REG_WRITE(AR5K_AR5212_RATE_DUR(rt->rates[i].rate_code), - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); - } - - if ((channel->channel_flags & CHANNEL_TURBO) == 0) { - rt = ar5k_ar5212_get_rate_table(hal, AR5K_MODE_11B); - for (i = 0; i < rt->rate_count; i++) { - data = AR5K_AR5212_RATE_DUR(rt->rates[i].rate_code); - AR5K_REG_WRITE(data, - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); - if (HAS_SHPREAMBLE(i)) { - AR5K_REG_WRITE(data + - (AR5K_SET_SHORT_PREAMBLE << 2), - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); - } - } - } - - /* Fix for first revision of the AR5112 RF chipset */ - if (hal->ah_radio >= AR5K_AR5112 && - hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { - AR5K_REG_WRITE(AR5K_AR5212_PHY_CCKTXCTL, - AR5K_AR5212_PHY_CCKTXCTL_WORLD); - if (channel->channel_flags & CHANNEL_OFDM) - data = 0xffb81020; - else - data = 0xffb80d20; - AR5K_REG_WRITE(AR5K_AR5212_PHY_FC, data); - } - - /* - * Set TX power (XXX use txpower from net80211) - */ - if (ar5k_ar5212_txpower(hal, channel, - AR5K_TUNE_DEFAULT_TXPOWER) == FALSE) { - *status = AR5K_EIO; - return (FALSE); - } - - /* - * Write RF registers - */ - if (ar5k_rfregs(hal, channel, mode) == FALSE) { - *status = AR5K_EINPROGRESS; - return (FALSE); - } - - /* - * Configure additional registers - */ - - /* OFDM timings */ - if (channel->channel_flags & CHANNEL_OFDM) { - u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, - ds_coef_man, clock; - - clock = channel->channel_flags & CHANNEL_T ? 80 : 40; - coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; - - for (coef_exp = 31; coef_exp > 0; coef_exp--) - if ((coef_scaled >> coef_exp) & 0x1) - break; - - if (!coef_exp) { - *status = AR5K_EINVAL; - return (FALSE); - } - - coef_exp = 14 - (coef_exp - 24); - coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); - ds_coef_man = coef_man >> (24 - coef_exp); - ds_coef_exp = coef_exp - 16; - - AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3, - AR5K_AR5212_PHY_TIMING_3_DSC_MAN, ds_coef_man); - AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3, - AR5K_AR5212_PHY_TIMING_3_DSC_EXP, ds_coef_exp); - } - - if (hal->ah_radio == AR5K_AR5111) { - if (channel->channel_flags & CHANNEL_B) - AR5K_REG_ENABLE_BITS(AR5K_AR5212_TXCFG, - AR5K_AR5212_TXCFG_B_MODE); - else - AR5K_REG_DISABLE_BITS(AR5K_AR5212_TXCFG, - AR5K_AR5212_TXCFG_B_MODE); - } - - /* Set antenna mode */ - AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x44), - hal->ah_antenna[ee_mode][0], 0xfffffc06); - - if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] = AR5K_ANT_FIXED_B; - else - ant[0] = ant[1] = AR5K_ANT_FIXED_A; - - - AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0, - hal->ah_antenna[ee_mode][ant[0]]); - AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1, - hal->ah_antenna[ee_mode][ant[1]]); - - /* Commit values from EEPROM */ - if (hal->ah_radio == AR5K_AR5111) - AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_FC, - AR5K_AR5212_PHY_FC_TX_CLIP, ee->ee_tx_clip); - - AR5K_REG_WRITE(AR5K_AR5212_PHY(0x5a), - AR5K_AR5212_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); - - AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x11), - (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); - AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x12), - (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); - AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x14), - (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | - ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); - - AR5K_REG_WRITE(AR5K_AR5212_PHY(0x0d), - (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | - (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | - (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | - (ee->ee_tx_frm2xpa_enable[ee_mode])); - - AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x0a), - ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); - AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x19), - (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); - AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49), 4, 0xffffff01); - - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, - AR5K_AR5212_PHY_IQ_CORR_ENABLE | - (ee->ee_i_cal[ee_mode] << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S) | - ee->ee_q_cal[ee_mode]); - - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_GAIN_2GHZ, - AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX, - ee->ee_margin_tx_rx[ee_mode]); - } - - /* - * Restore saved values - */ - AR5K_REG_WRITE(AR5K_AR5212_DCU_SEQNUM(0), s_seq); - AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, s_ant); - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, s_led[0]); - AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, s_led[1]); - AR5K_REG_WRITE(AR5K_AR5212_GPIODO, s_led[2]); - - /* - * Misc - */ - bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); - ar5k_ar5212_set_associd(hal, mac, 0); - ar5k_ar5212_set_opmode(hal); - AR5K_REG_WRITE(AR5K_AR5212_PISR, 0xffffffff); - AR5K_REG_WRITE(AR5K_AR5212_RSSI_THR, AR5K_TUNE_RSSI_THRES); - - /* - * Set Rx/Tx DMA Configuration - */ - AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, AR5K_AR5212_TXCFG_SDMAMR, - AR5K_AR5212_DMASIZE_512B | AR5K_AR5212_TXCFG_DMASIZE); - AR5K_REG_WRITE_BITS(AR5K_AR5212_RXCFG, AR5K_AR5212_RXCFG_SDMAMW, - AR5K_AR5212_DMASIZE_512B); - - /* - * Set channel and calibrate the PHY - */ - if (ar5k_channel(hal, channel) == FALSE) { - *status = AR5K_EIO; - return (FALSE); - } - - /* - * Enable the PHY and wait until completion - */ - AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_ENABLE); - - data = AR5K_REG_READ(AR5K_AR5212_PHY_RX_DELAY) & - AR5K_AR5212_PHY_RX_DELAY_M; - data = (channel->channel_flags & CHANNEL_CCK) ? - ((data << 2) / 22) : (data / 10); - - AR5K_DELAY(100 + data); - - /* - * Start calibration - */ - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, - AR5K_AR5212_PHY_AGCCTL_NF | - AR5K_AR5212_PHY_AGCCTL_CAL); - - - hal->ah_calibration = FALSE; - if ((channel->channel_flags & CHANNEL_B) == 0) { - hal->ah_calibration = TRUE; - AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_IQ, - AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX, 15); - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, - AR5K_AR5212_PHY_IQ_RUN); - } - - /* - * Reset queues and start beacon timers at the end of the reset routine - */ - for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { - AR5K_REG_WRITE_Q(AR5K_AR5212_DCU_QCUMASK(i), i); - if (ar5k_ar5212_reset_tx_queue(hal, i) == FALSE) { - AR5K_PRINTF("failed to reset TX queue #%d\n", i); - *status = AR5K_EINVAL; - return (FALSE); - } - } - - /* Pre-enable interrupts */ - ar5k_ar5212_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); - - /* - * Set RF kill flags if supported by the device (read from the EEPROM) - * Disable gpio_intr for now since it results system hang. - */ -/* if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { - ar5k_ar5212_set_gpio_input(hal, 0); - if ((hal->ah_gpio[0] = ar5k_ar5212_get_gpio(hal, 0)) == 0) - ar5k_ar5212_set_gpio_intr(hal, 0, 1); - else - ar5k_ar5212_set_gpio_intr(hal, 0, 0); - } -*/ - /* - * Set the 32MHz reference clock - */ - AR5K_REG_WRITE(AR5K_AR5212_PHY_SCR, AR5K_AR5212_PHY_SCR_32MHZ); - AR5K_REG_WRITE(AR5K_AR5212_PHY_SLMT, AR5K_AR5212_PHY_SLMT_32MHZ); - AR5K_REG_WRITE(AR5K_AR5212_PHY_SCAL, AR5K_AR5212_PHY_SCAL_32MHZ); - AR5K_REG_WRITE(AR5K_AR5212_PHY_SCLOCK, AR5K_AR5212_PHY_SCLOCK_32MHZ); - AR5K_REG_WRITE(AR5K_AR5212_PHY_SDELAY, AR5K_AR5212_PHY_SDELAY_32MHZ); - AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, hal->ah_radio == AR5K_AR5111 ? - AR5K_AR5212_PHY_SPENDING_AR5111 : AR5K_AR5212_PHY_SPENDING_AR5112); - - /* - * Disable beacons and reset the register - */ - AR5K_REG_DISABLE_BITS(AR5K_AR5212_BEACON, - AR5K_AR5212_BEACON_ENABLE | AR5K_AR5212_BEACON_RESET_TSF); - - return (TRUE); -} - -void /*New*/ -ar5k_ar5212_set_def_antenna(struct ath_hal *hal, u_int ant) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, ant); - return; -} - -u_int/*New*/ -ar5k_ar5212_get_def_antenna(struct ath_hal *hal) -{ - AR5K_TRACE; - /*Just a try M.F.*/ - return AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA); -} - -void /*O.K.*/ -ar5k_ar5212_set_opmode(struct ath_hal *hal) -{ - u_int32_t pcu_reg, low_id, high_id; - - pcu_reg = 0; - - AR5K_TRACE; - - switch (hal->ah_op_mode) { - case AR5K_M_IBSS: - pcu_reg |= AR5K_AR5212_STA_ID1_ADHOC | - AR5K_AR5212_STA_ID1_DESC_ANTENNA; - break; - - case AR5K_M_HOSTAP: - pcu_reg |= AR5K_AR5212_STA_ID1_AP | - AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA; - break; - - case AR5K_M_STA: - case AR5K_M_MONITOR: - pcu_reg |= AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; - break; - - default: - return; - } - - /* - * Set PCU registers - */ - low_id = AR5K_LOW_ID(hal->ah_sta_id); - high_id = AR5K_HIGH_ID(hal->ah_sta_id); - AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, pcu_reg | high_id); - - return; -} - -void /*New*/ -ar5k_ar5212_set_pcu_config(struct ath_hal *hal) -{ - AR5K_TRACE; - ar5k_ar5212_set_opmode(hal); - return; -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) -{ - u_int32_t i_pwr, q_pwr; - int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; - AR5K_TRACE; - - if (hal->ah_calibration == FALSE || - AR5K_REG_READ(AR5K_AR5212_PHY_IQ) & AR5K_AR5212_PHY_IQ_RUN) - goto done; - - hal->ah_calibration = FALSE; - - iq_corr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_CORR); - i_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_I); - q_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_Q); - i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; - q_coffd = q_pwr >> 6; - - if (i_coffd == 0 || q_coffd == 0) - goto done; - - i_coff = ((-iq_corr) / i_coffd) & 0x3f; - q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; - - /* Commit new IQ value */ - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, - AR5K_AR5212_PHY_IQ_CORR_ENABLE | - ((u_int32_t)q_coff) | - ((u_int32_t)i_coff << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S)); - - done: - /* Start noise floor calibration */ - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, - AR5K_AR5212_PHY_AGCCTL_NF); - - /* Request RF gain */ - if (channel->channel_flags & CHANNEL_5GHZ) { - AR5K_REG_WRITE(AR5K_AR5212_PHY_PAPD_PROBE, - AR5K_REG_SM(hal->ah_txpower.txp_max, - AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER) | - AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT); - hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; - } - - return (TRUE); -} - -/* - * Transmit functions - */ - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) -{ - u_int32_t trigger_level, imr; - AR5K_BOOL status = FALSE; - AR5K_TRACE; - - /* - * Disable interrupts by setting the mask - */ - imr = ar5k_ar5212_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); - - trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TXCFG), - AR5K_AR5212_TXCFG_TXFULL); - - if (increase == FALSE) { - if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) - goto done; - } else - trigger_level += - ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); - - /* - * Update trigger level on success - */ - AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, - AR5K_AR5212_TXCFG_TXFULL, trigger_level); - status = TRUE; - - done: - /* - * Restore interrupt mask - */ - ar5k_ar5212_set_intr(hal, imr); - - return (status); -} - -int /*O.K.*/ -ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, - AR5K_TXQ_INFO *queue_info) -{ - u_int queue; - AR5K_TRACE; - - /* - * Get queue by type - */ - if (queue_type == AR5K_TX_QUEUE_DATA) { - for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; - queue++) - if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) - return (-1); - } else if (queue_type == AR5K_TX_QUEUE_UAPSD) { - queue = AR5K_TX_QUEUE_ID_UAPSD; - } else if (queue_type == AR5K_TX_QUEUE_BEACON) { - queue = AR5K_TX_QUEUE_ID_BEACON; - } else if (queue_type == AR5K_TX_QUEUE_CAB) { - queue = AR5K_TX_QUEUE_ID_CAB; - } else - return (-1); - - /* - * Setup internal queue structure - */ - bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - hal->ah_txq[queue].tqi_type = queue_type; - - if (queue_info != NULL) { - queue_info->tqi_type = queue_type; - if (ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info) - != TRUE) - return (-1); - } - - AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); - - return (queue); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_setup_tx_queueprops(struct ath_hal *hal, int queue, - const AR5K_TXQ_INFO *queue_info) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (FALSE); - - bcopy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - - if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && - ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || - (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || - queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) - hal->ah_txq[queue].tqi_flags |= - AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; - - return (TRUE); -} - -AR5K_BOOL /*New*/ -ar5k_ar5212_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) -{ - AR5K_TRACE; - memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_release_tx_queue(struct ath_hal *hal, u_int queue) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* This queue will be skipped in further operations */ - hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; - AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); - - return (FALSE); /*???*/ -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue) -{ - u_int32_t cw_min, cw_max, retry_lg, retry_sh; - AR5K_TXQ_INFO *tq; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - tq = &hal->ah_txq[queue]; - - if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) - return (TRUE); - - /* - * Set registers by channel mode - */ - cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; - hal->ah_aifs = AR5K_TUNE_AIFS; - if (IS_CHAN_XR(hal->ah_current_channel)) { - cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; - hal->ah_aifs = AR5K_TUNE_AIFS_XR; - } else if (IS_CHAN_B(hal->ah_current_channel)) { - cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; - cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; - hal->ah_aifs = AR5K_TUNE_AIFS_11B; - } - - /* - * Set retry limits - */ - if (hal->ah_software_retry == TRUE) { - /* XXX Need to test this */ - retry_lg = hal->ah_limit_tx_retries; - retry_sh = retry_lg = - retry_lg > AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY ? - AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY : retry_lg; - } else { - retry_lg = AR5K_INIT_LG_RETRY; - retry_sh = AR5K_INIT_SH_RETRY; - } - - AR5K_REG_WRITE(AR5K_AR5212_DCU_RETRY_LMT(queue), - AR5K_REG_SM(AR5K_INIT_SLG_RETRY, - AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY) | - AR5K_REG_SM(AR5K_INIT_SSH_RETRY, - AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY) | - AR5K_REG_SM(retry_lg, AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY) | - AR5K_REG_SM(retry_sh, AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY)); - - /* - * Set initial content window (cw_min/cw_max) - */ - cw_min = 1; - - while (cw_min < hal->ah_cw_min) - cw_min = (cw_min << 1) | 1; - - cw_min = tq->tqi_cw_min < 0 ? - (cw_min >> (-tq->tqi_cw_min)) : - ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); - cw_max = tq->tqi_cw_max < 0 ? - (cw_max >> (-tq->tqi_cw_max)) : - ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); - - AR5K_REG_WRITE(AR5K_AR5212_DCU_LCL_IFS(queue), - AR5K_REG_SM(cw_min, AR5K_AR5212_DCU_LCL_IFS_CW_MIN) | - AR5K_REG_SM(cw_max, AR5K_AR5212_DCU_LCL_IFS_CW_MAX) | - AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, - AR5K_AR5212_DCU_LCL_IFS_AIFS)); - - /* - * Set misc registers - */ - AR5K_REG_WRITE(AR5K_AR5212_QCU_MISC(queue), - AR5K_AR5212_QCU_MISC_DCU_EARLY); - - if (tq->tqi_cbr_period) { - AR5K_REG_WRITE(AR5K_AR5212_QCU_CBRCFG(queue), - AR5K_REG_SM(tq->tqi_cbr_period, - AR5K_AR5212_QCU_CBRCFG_INTVAL) | - AR5K_REG_SM(tq->tqi_cbr_overflow_limit, - AR5K_AR5212_QCU_CBRCFG_ORN_THRES)); - AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), - AR5K_AR5212_QCU_MISC_FRSHED_CBR); - if (tq->tqi_cbr_overflow_limit) - AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), - AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE); - } - - if (tq->tqi_ready_time) { - AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), - AR5K_REG_SM(tq->tqi_ready_time, - AR5K_AR5212_QCU_RDYTIMECFG_INTVAL) | - AR5K_AR5212_QCU_RDYTIMECFG_ENABLE); - } - - if (tq->tqi_burst_time) { - AR5K_REG_WRITE(AR5K_AR5212_DCU_CHAN_TIME(queue), - AR5K_REG_SM(tq->tqi_burst_time, - AR5K_AR5212_DCU_CHAN_TIME_DUR) | - AR5K_AR5212_DCU_CHAN_TIME_ENABLE); - - if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { - AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), - AR5K_AR5212_QCU_MISC_TXE); - } - } - - if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { - AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), - AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS); - } - - if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { - AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), - AR5K_AR5212_DCU_MISC_BACKOFF_FRAG); - } - - /* - * Set registers by queue type - */ - switch (tq->tqi_type) { - case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), - AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | - AR5K_AR5212_QCU_MISC_CBREXP_BCN | - AR5K_AR5212_QCU_MISC_BCN_ENABLE); - - AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), - (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL) | - AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS | - AR5K_AR5212_DCU_MISC_BCN_ENABLE); - - AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), - ((AR5K_TUNE_BEACON_INTERVAL - - (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | - AR5K_AR5212_QCU_RDYTIMECFG_ENABLE); - break; - - case AR5K_TX_QUEUE_CAB: - AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), - AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | - AR5K_AR5212_QCU_MISC_CBREXP | - AR5K_AR5212_QCU_MISC_CBREXP_BCN); - - AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), - (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL)); - break; - - case AR5K_TX_QUEUE_UAPSD: - AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), - AR5K_AR5212_QCU_MISC_CBREXP); - break; - - case AR5K_TX_QUEUE_DATA: - default: - break; - } - - /* - * Enable tx queue in the secondary interrupt mask registers - */ - AR5K_REG_WRITE(AR5K_AR5212_SIMR0, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) | - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC)); - AR5K_REG_WRITE(AR5K_AR5212_SIMR1, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR)); - AR5K_REG_WRITE(AR5K_AR5212_SIMR2, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN)); - - return (TRUE); -} - -u_int32_t /*O.K.*/ -ar5k_ar5212_get_tx_buf(struct ath_hal *hal, u_int queue) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Get the transmit queue descriptor pointer from the selected queue - */ - return (AR5K_REG_READ(AR5K_AR5212_QCU_TXDP(queue))); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Set the transmit queue descriptor pointer for the selected queue - * (this won't work if the queue is still active) - */ - if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, queue)) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5212_QCU_TXDP(queue), phys_addr); - - return (TRUE); -} - -u_int32_t /*Code from roofnet*/ -ar5k_ar5212_num_tx_pending(struct ath_hal *hal, u_int queue) { - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - return (AR5K_AR5212_QCU_STS(queue) & AR5K_AR5212_QCU_STS_FRMPENDCNT); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_tx_start(struct ath_hal *hal, u_int queue) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* Return if queue is disabled */ - if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXD, queue)) - return (FALSE); - - /* Start queue */ - AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXE, queue); - - return (TRUE); -} - -AR5K_BOOL /*Fixed delay*/ -ar5k_ar5212_stop_tx_dma(struct ath_hal *hal, u_int queue) -{ - int i = 100, pending; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - - /* - * Schedule TX disable and wait until queue is empty - */ - AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXD, queue); - - do { - pending = AR5K_REG_READ(AR5K_AR5212_QCU_STS(queue)) & - AR5K_AR5212_QCU_STS_FRMPENDCNT; - AR5K_DELAY(100); - } while (--i && pending); - - /* Clear register */ - AR5K_REG_WRITE(AR5K_AR5212_QCU_TXD, 0); - - return (TRUE); -} - -AR5K_BOOL /*O.K. - Initialize tx_desc */ -ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, - u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, - u_int flags, u_int rtscts_rate, u_int rtscts_duration) -{ - struct ar5k_ar5212_tx_desc *tx_desc; - - AR5K_TRACE; - - tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; - - /* - * Validate input - */ - if (tx_tries0 == 0) - return (FALSE); - - /* Initialize status descriptor */ - tx_desc->tx_control_0 = 0; - tx_desc->tx_control_1 = 0; - tx_desc->tx_control_2 = 0; - tx_desc->tx_control_3 = 0; - - /* Setup status descriptor */ - - if ((tx_desc->tx_control_0 = (packet_length & - AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length) - return (FALSE); - - tx_desc->tx_control_0 |= - AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) | - AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT); - tx_desc->tx_control_1 = - AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE); - tx_desc->tx_control_2 = - AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0); - tx_desc->tx_control_3 = - tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; - -#define _TX_FLAGS(_c, _flag) \ - if (flags & AR5K_TXDESC_##_flag) \ - tx_desc->tx_control_##_c |= \ - AR5K_AR5212_DESC_TX_CTL##_c##_##_flag - - _TX_FLAGS(0, CLRDMASK); - _TX_FLAGS(0, VEOL); - _TX_FLAGS(0, INTREQ); - _TX_FLAGS(0, RTSENA); - _TX_FLAGS(0, CTSENA); - _TX_FLAGS(1, NOACK); - -#undef _TX_FLAGS - - /* - * WEP crap - */ - if (key_index != AR5K_TXKEYIX_INVALID) { - tx_desc->tx_control_0 |= - AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID; - tx_desc->tx_control_1 |= - AR5K_REG_SM(key_index, - AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); - } - - /* - * RTS/CTS - */ - if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { - if ((flags & AR5K_TXDESC_RTSENA) && - (flags & AR5K_TXDESC_CTSENA)) - return (FALSE); - tx_desc->tx_control_2 |= - rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION; - tx_desc->tx_control_3 |= - AR5K_REG_SM(rtscts_rate, - AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE); - } - - return (TRUE); -} - -AR5K_BOOL /*Added an argument *last_desc -need revision -don't clear descriptor here*/ -ar5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) -{ - struct ar5k_ar5212_tx_desc *tx_desc; - struct ar5k_ar5212_tx_status *tx_status; - - AR5K_TRACE; - tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2]; - - /* Clear status descriptor */ - bzero(tx_status, sizeof(struct ar5k_ar5212_tx_status)); - - /* Validate segment length and initialize the descriptor */ - if ((tx_desc->tx_control_1 = (segment_length & - AR5K_AR5212_DESC_TX_CTL1_BUF_LEN)) != segment_length) - return (FALSE); - -/*Code from roofnet*/ -// if (segment_length> AR5K_AR5212_DESC_TX_CTL1_BUF_LEN){ -// return (FALSE); -//} -// tx_desc->tx_control_1 &= ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN; -// tx_desc->tx_control_1 |= (segment_length & AR5K_AR5212_DESC_TX_CTL1_BUF_LEN); -/* */ - if (first_segment != TRUE) - tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN; - - if (last_segment != TRUE) - tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE; - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - u_int tx_rate3, u_int tx_tries3) -{ - struct ar5k_ar5212_tx_desc *tx_desc; - - tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; - -#define _XTX_TRIES(_n) \ - if (tx_tries##_n) { \ - tx_desc->tx_control_2 |= \ - AR5K_REG_SM(tx_tries##_n, \ - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n); \ - tx_desc->tx_control_3 |= \ - AR5K_REG_SM(tx_rate##_n, \ - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n); \ - } - - _XTX_TRIES(1); - _XTX_TRIES(2); - _XTX_TRIES(3); - -#undef _XTX_TRIES - - return (TRUE); -} - -AR5K_STATUS /*O.K.*/ -ar5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) -{ - struct ar5k_ar5212_tx_status *tx_status; - struct ar5k_ar5212_tx_desc *tx_desc; - - AR5K_TRACE; - tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2]; - - /* No frame has been send or error */ - if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); - - /* - * Get descriptor status - */ - desc->ds_us.tx.ts_tstamp = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP); - desc->ds_us.tx.ts_shortretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT); - desc->ds_us.tx.ts_longretry = - AR5K_REG_MS(tx_status->tx_status_0, - AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT); - desc->ds_us.tx.ts_seqnum = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM); - desc->ds_us.tx.ts_rssi = - AR5K_REG_MS(tx_status->tx_status_1, - AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH); - desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & - AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; - desc->ds_us.tx.ts_status = 0; - - switch (AR5K_REG_MS(tx_status->tx_status_1, - AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX)) { - case 0: - desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; - break; - case 1: - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1); - desc->ds_us.tx.ts_longretry += - AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1); - break; - case 2: - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2); - desc->ds_us.tx.ts_longretry += - AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2); - break; - case 3: - desc->ds_us.tx.ts_rate = - AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3); - desc->ds_us.tx.ts_longretry += - AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3); - break; - } - - if ((tx_status->tx_status_0 & - AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { - if (tx_status->tx_status_0 & - AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES) - desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; - - if (tx_status->tx_status_0 & - AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; - - if (tx_status->tx_status_0 & - AR5K_AR5212_DESC_TX_STATUS0_FILTERED) - desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; - } - - return (AR5K_OK); -} - -AR5K_BOOL /*O.K. - needs revision (what about VEOL cap ?)*/ -ar5k_ar5212_has_veol(struct ath_hal *hal) -{ - return (TRUE); -} - -void /*Unimplemented*/ -ar5k_ar5212_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) -{ - AR5K_TRACE; - /* XXX */ - return; -} - -/* - * Receive functions - */ - -u_int32_t /*O.K.*/ -ar5k_ar5212_get_rx_buf(struct ath_hal *hal) -{ - return (AR5K_REG_READ(AR5K_AR5212_RXDP)); -} - -void /*O.K.*/ -ar5k_ar5212_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) -{ - AR5K_TRACE; - AR5K_REG_WRITE(AR5K_AR5212_RXDP, phys_addr); -} - -void /*O.K.*/ -ar5k_ar5212_start_rx(struct ath_hal *hal) -{ - AR5K_TRACE; - AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_stop_rx_dma(struct ath_hal *hal) -{ - int i; - - AR5K_TRACE; - AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXD); - - /* - * It may take some time to disable the DMA receive unit - */ - for (i = 2000; - i > 0 && (AR5K_REG_READ(AR5K_AR5212_CR) & AR5K_AR5212_CR_RXE) != 0; - i--) - AR5K_DELAY(10); - - return (i > 0 ? TRUE : FALSE); -} - -void /*O.K.*/ -ar5k_ar5212_start_rx_pcu(struct ath_hal *hal) -{ - AR5K_TRACE; - AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX); -} - -void /*O.K.*/ -ar5k_ar5212_stop_pcu_recv(struct ath_hal *hal) -{ - AR5K_TRACE; - AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX); -} - -void /*O.K.*/ -ar5k_ar5212_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, - u_int32_t filter1) -{ - AR5K_TRACE; - /* Set the multicat filter */ - AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL0, filter0); - AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL1, filter1); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) -{ - - AR5K_TRACE; - if (index >= 64) { - return (FALSE); - } else if (index >= 32) { - AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL1, - (1 << (index - 32))); - } else { - AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL0, - (1 << index)); - } - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) -{ - - AR5K_TRACE; - if (index >= 64) { - return (FALSE); - } else if (index >= 32) { - AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL1, - (1 << (index - 32))); - } else { - AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL0, - (1 << index)); - } - - return (TRUE); -} - -u_int32_t /*O.K.*/ -ar5k_ar5212_get_rx_filter(struct ath_hal *hal) -{ - u_int32_t data, filter = 0; - - AR5K_TRACE; - filter = AR5K_REG_READ(AR5K_AR5212_RX_FILTER); - data = AR5K_REG_READ(AR5K_AR5212_PHY_ERR_FIL); - - if (data & AR5K_AR5212_PHY_ERR_FIL_RADAR) - filter |= AR5K_RX_FILTER_PHYRADAR; - if (data & (AR5K_AR5212_PHY_ERR_FIL_OFDM | - AR5K_AR5212_PHY_ERR_FIL_CCK)) - filter |= AR5K_RX_FILTER_PHYERR; - - return (filter); -} - -void /*O.K. - added code from roofnet*/ -ar5k_ar5212_set_rx_filter(struct ath_hal *hal, u_int32_t filter) -{ - u_int32_t data = 0; - - AR5K_TRACE; - if (filter & AR5K_RX_FILTER_PHYRADAR) - data |= AR5K_AR5212_PHY_ERR_FIL_RADAR; - if (filter & AR5K_RX_FILTER_PHYERR) - data |= AR5K_AR5212_PHY_ERR_FIL_OFDM | - AR5K_AR5212_PHY_ERR_FIL_CCK; - - /* Got that from roofnet*/ - data |= AR5K_RX_FILTER_PROM | AR5K_RX_FILTER_CONTROL; - - if (data) { - AR5K_REG_ENABLE_BITS(AR5K_AR5212_RXCFG, - AR5K_AR5212_RXCFG_ZLFDMA); - } else { - AR5K_REG_DISABLE_BITS(AR5K_AR5212_RXCFG, - AR5K_AR5212_RXCFG_ZLFDMA); - } - - AR5K_REG_WRITE(AR5K_AR5212_RX_FILTER, filter & 0xff); - AR5K_REG_WRITE(AR5K_AR5212_PHY_ERR_FIL, data); -} - -AR5K_BOOL /*O.K. - Initialize rx_desc and clear ds_hw */ -ar5k_ar5212_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t size, u_int flags) -{ - struct ar5k_ar5212_rx_desc *rx_desc; - - AR5K_TRACE; - rx_desc = (struct ar5k_ar5212_rx_desc*)&desc->ds_ctl0; - - /* - *Clear ds_hw - * If we don't clean the descriptor, while - * scanning we get too many results, - * most of them virtual, after some secs - * of scanning system halts. M.F. - */ - bzero(desc->ds_hw, sizeof(desc->ds_hw)); - - /*Initialize rx descriptor*/ - rx_desc->rx_control_0 = 0; - rx_desc->rx_control_1 = 0; - - /*Setup descriptor*/ - - if ((rx_desc->rx_control_1 = (size & - AR5K_AR5212_DESC_RX_CTL1_BUF_LEN)) != size) - return (FALSE); - - if (flags & AR5K_RXDESC_INTREQ) - rx_desc->rx_control_1 |= AR5K_AR5212_DESC_RX_CTL1_INTREQ; - - return (TRUE); -} - -AR5K_STATUS /*O.K.*/ -ar5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) -{ - struct ar5k_ar5212_rx_status *rx_status; - struct ar5k_ar5212_rx_error *rx_err; - - AR5K_TRACE; - rx_status = (struct ar5k_ar5212_rx_status*)&desc->ds_hw[0]; - - /* Overlay on error */ - rx_err = (struct ar5k_ar5212_rx_error*)&desc->ds_hw[0]; - - /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0) - return (AR5K_EINPROGRESS); - - /* - * Frame receive status - */ - desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN; - desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL); - desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE); - desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA; - desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_AR5212_DESC_RX_STATUS0_MORE; - desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); - desc->ds_us.rx.rs_status = 0; - - /* - * Key table status - */ - if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID) { - desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX); - } else { - desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; - } - - /* - * Receive/descriptor errors - */ - if ((rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { - if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; - - if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) { - desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; - desc->ds_us.rx.rs_phyerr = - AR5K_REG_MS(rx_err->rx_error_1, - AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE); - } - - if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; - - if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR) - desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; - } - - return (AR5K_OK); -} - -void /*Added AR5K_NODE_STATS argument*/ -ar5k_ar5212_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) -{ - AR5K_TRACE; - /* Signal state monitoring is not yet supported */ -} - -/* - * Misc functions - */ - -void /*O.K.*/ -ar5k_ar5212_dump_state(struct ath_hal *hal) -{ -#ifdef AR5K_DEBUG -#define AR5K_PRINT_REGISTER(_x) \ - AR5K_PRINTF("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5212_##_x)); - - AR5K_PRINT("MAC registers:\n"); - AR5K_PRINT_REGISTER(CR); - AR5K_PRINT_REGISTER(CFG); - AR5K_PRINT_REGISTER(IER); - AR5K_PRINT_REGISTER(TXCFG); - AR5K_PRINT_REGISTER(RXCFG); - AR5K_PRINT_REGISTER(MIBC); - AR5K_PRINT_REGISTER(TOPS); - AR5K_PRINT_REGISTER(RXNOFRM); - AR5K_PRINT_REGISTER(RPGTO); - AR5K_PRINT_REGISTER(RFCNT); - AR5K_PRINT_REGISTER(MISC); - AR5K_PRINT_REGISTER(PISR); - AR5K_PRINT_REGISTER(SISR0); - AR5K_PRINT_REGISTER(SISR1); - AR5K_PRINT_REGISTER(SISR3); - AR5K_PRINT_REGISTER(SISR4); - AR5K_PRINT_REGISTER(DCM_ADDR); - AR5K_PRINT_REGISTER(DCM_DATA); - AR5K_PRINT_REGISTER(DCCFG); - AR5K_PRINT_REGISTER(CCFG); - AR5K_PRINT_REGISTER(CCFG_CUP); - AR5K_PRINT_REGISTER(CPC0); - AR5K_PRINT_REGISTER(CPC1); - AR5K_PRINT_REGISTER(CPC2); - AR5K_PRINT_REGISTER(CPCORN); - AR5K_PRINT_REGISTER(QCU_TXE); - AR5K_PRINT_REGISTER(QCU_TXD); - AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); - AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); - AR5K_PRINT_REGISTER(DCU_FP); - AR5K_PRINT_REGISTER(DCU_TXP); - AR5K_PRINT_REGISTER(DCU_TX_FILTER); - AR5K_PRINT_REGISTER(RC); - AR5K_PRINT_REGISTER(SCR); - AR5K_PRINT_REGISTER(INTPEND); - AR5K_PRINT_REGISTER(PCICFG); - AR5K_PRINT_REGISTER(GPIOCR); - AR5K_PRINT_REGISTER(GPIODO); - AR5K_PRINT_REGISTER(SREV); - AR5K_PRINT_REGISTER(EEPROM_BASE); - AR5K_PRINT_REGISTER(EEPROM_DATA); - AR5K_PRINT_REGISTER(EEPROM_CMD); - AR5K_PRINT_REGISTER(EEPROM_CFG); - AR5K_PRINT_REGISTER(PCU_MIN); - AR5K_PRINT_REGISTER(STA_ID0); - AR5K_PRINT_REGISTER(STA_ID1); - AR5K_PRINT_REGISTER(BSS_ID0); - AR5K_PRINT_REGISTER(SLOT_TIME); - AR5K_PRINT_REGISTER(TIME_OUT); - AR5K_PRINT_REGISTER(RSSI_THR); - AR5K_PRINT_REGISTER(BEACON); - AR5K_PRINT_REGISTER(CFP_PERIOD); - AR5K_PRINT_REGISTER(TIMER0); - AR5K_PRINT_REGISTER(TIMER2); - AR5K_PRINT_REGISTER(TIMER3); - AR5K_PRINT_REGISTER(CFP_DUR); - AR5K_PRINT_REGISTER(MCAST_FIL0); - AR5K_PRINT_REGISTER(MCAST_FIL1); - AR5K_PRINT_REGISTER(DIAG_SW); - AR5K_PRINT_REGISTER(TSF_U32); - AR5K_PRINT_REGISTER(ADDAC_TEST); - AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); - AR5K_PRINT_REGISTER(LAST_TSTP); - AR5K_PRINT_REGISTER(NAV); - AR5K_PRINT_REGISTER(RTS_OK); - AR5K_PRINT_REGISTER(ACK_FAIL); - AR5K_PRINT_REGISTER(FCS_FAIL); - AR5K_PRINT_REGISTER(BEACON_CNT); - AR5K_PRINT_REGISTER(TSF_PARM); - AR5K_PRINT_REGISTER(RATE_DUR_0); - AR5K_PRINT_REGISTER(KEYTABLE_0); - AR5K_PRINT("\n"); - - AR5K_PRINT("PHY registers:\n"); - AR5K_PRINT_REGISTER(PHY_TURBO); - AR5K_PRINT_REGISTER(PHY_AGC); - AR5K_PRINT_REGISTER(PHY_TIMING_3); - AR5K_PRINT_REGISTER(PHY_CHIP_ID); - AR5K_PRINT_REGISTER(PHY_AGCCTL); - AR5K_PRINT_REGISTER(PHY_NF); - AR5K_PRINT_REGISTER(PHY_SCR); - AR5K_PRINT_REGISTER(PHY_SLMT); - AR5K_PRINT_REGISTER(PHY_SCAL); - AR5K_PRINT_REGISTER(PHY_RX_DELAY); - AR5K_PRINT_REGISTER(PHY_IQ); - AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); - AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1); - AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2); - AR5K_PRINT_REGISTER(PHY_FC); - AR5K_PRINT_REGISTER(PHY_RADAR); - AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); - AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); - AR5K_PRINT("\n"); -#endif -} - -AR5K_BOOL /*Added arguments*/ -ar5k_ar5212_get_diag_state(struct ath_hal *hal, int request, const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) -{ - AR5K_TRACE; - /* - * We'll ignore this right now. This seems to be some kind of an obscure - * debugging interface for the binary-only HAL. - */ - return (FALSE); -} - -void /*O.K.*/ -ar5k_ar5212_get_lladdr(struct ath_hal *hal, u_int8_t *mac) -{ - AR5K_TRACE; - bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) -{ - u_int32_t low_id, high_id; - - AR5K_TRACE; - /* Set new station ID */ - bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); - - low_id = AR5K_LOW_ID(mac); - high_id = AR5K_HIGH_ID(mac); - - AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, high_id); - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, - AR5K_STATUS *status) -{ - ieee80211_regdomain_t ieee_regdomain; - - ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); - - if (ar5k_eeprom_regulation_domain(hal, TRUE, - &ieee_regdomain) == TRUE) { - *status = AR5K_OK; - return (TRUE); - } - - *status = AR5K_EIO; - - return (FALSE); -} - -void /*O.K.*/ -ar5k_ar5212_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) -{ - u_int32_t led; - - AR5K_TRACE; - AR5K_REG_DISABLE_BITS(AR5K_AR5212_PCICFG, - AR5K_AR5212_PCICFG_LEDMODE | AR5K_AR5212_PCICFG_LED); - - /* - * Some blinking values, define at your wish - */ - switch (state) { - case AR5K_LED_SCAN: - case AR5K_LED_AUTH: - led = AR5K_AR5212_PCICFG_LEDMODE_PROP | - AR5K_AR5212_PCICFG_LED_PEND; - break; - - case AR5K_LED_INIT: - led = AR5K_AR5212_PCICFG_LEDMODE_PROP | - AR5K_AR5212_PCICFG_LED_NONE; - break; - - case AR5K_LED_ASSOC: - case AR5K_LED_RUN: - led = AR5K_AR5212_PCICFG_LEDMODE_PROP | - AR5K_AR5212_PCICFG_LED_ASSOC; - break; - - default: - led = AR5K_AR5212_PCICFG_LEDMODE_PROM | - AR5K_AR5212_PCICFG_LED_NONE; - break; - } - - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, led); -} - -void /*Removed argument trim_offset for combatibility -need revision*/ -ar5k_ar5212_set_associd(struct ath_hal *hal, const u_int8_t *bssid, - u_int16_t assoc_id) -{ - u_int32_t low_id, high_id; - u_int16_t tim_offset = 0; - - /* - * Set simple BSSID mask - */ - AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, 0xfffffff); - AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, 0xfffffff); - - /* - * Set BSSID which triggers the "SME Join" operation - */ - low_id = AR5K_LOW_ID(bssid); - high_id = AR5K_HIGH_ID(bssid); - AR5K_REG_WRITE(AR5K_AR5212_BSS_ID0, low_id); - AR5K_REG_WRITE(AR5K_AR5212_BSS_ID1, high_id | - ((assoc_id & 0x3fff) << AR5K_AR5212_BSS_ID1_AID_S)); - bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN); - - if (assoc_id == 0) { - ar5k_ar5212_disable_pspoll(hal); - return; - } - - AR5K_REG_WRITE(AR5K_AR5212_BEACON, - (AR5K_REG_READ(AR5K_AR5212_BEACON) & - ~AR5K_AR5212_BEACON_TIM) | - (((tim_offset ? tim_offset + 4 : 0) << - AR5K_AR5212_BEACON_TIM_S) & - AR5K_AR5212_BEACON_TIM)); - - ar5k_ar5212_enable_pspoll(hal, NULL, 0); -} - -AR5K_BOOL /*New*/ -ar5k_ar5212_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) -{ - u_int32_t low_id, high_id; - - AR5K_TRACE; - - low_id = AR5K_LOW_ID(mask); - high_id = AR5K_HIGH_ID(mask); - - AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, low_id); - AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, high_id); - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) -{ - AR5K_TRACE; - if (gpio > AR5K_AR5212_NUM_GPIO) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, - (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) - | AR5K_AR5212_GPIOCR_ALL(gpio)); - - return (TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) -{ - AR5K_TRACE; - if (gpio > AR5K_AR5212_NUM_GPIO) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, - (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) - | AR5K_AR5212_GPIOCR_NONE(gpio)); - - return (TRUE); -} - -u_int32_t /*O.K.*/ -ar5k_ar5212_get_gpio(struct ath_hal *hal, u_int32_t gpio) -{ - AR5K_TRACE; - if (gpio > AR5K_AR5212_NUM_GPIO) - return (0xffffffff); - - /* GPIO input magic */ - return (((AR5K_REG_READ(AR5K_AR5212_GPIODI) & - AR5K_AR5212_GPIODI_M) >> gpio) & 0x1); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) -{ - u_int32_t data; - AR5K_TRACE; - - if (gpio > AR5K_AR5212_NUM_GPIO) - return (FALSE); - - /* GPIO output magic */ - data = AR5K_REG_READ(AR5K_AR5212_GPIODO); - - data &= ~(1 << gpio); - data |= (val&1) << gpio; - - AR5K_REG_WRITE(AR5K_AR5212_GPIODO, data); - - return (TRUE); -} - -void /*O.K.*/ -ar5k_ar5212_set_gpio_intr(struct ath_hal *hal, u_int gpio, - u_int32_t interrupt_level) -{ - u_int32_t data; - - AR5K_TRACE; - if (gpio > AR5K_AR5212_NUM_GPIO) - return; - - /* - * Set the GPIO interrupt - */ - data = (AR5K_REG_READ(AR5K_AR5212_GPIOCR) & - ~(AR5K_AR5212_GPIOCR_INT_SEL(gpio) | AR5K_AR5212_GPIOCR_INT_SELH | - AR5K_AR5212_GPIOCR_INT_ENA | AR5K_AR5212_GPIOCR_ALL(gpio))) | - (AR5K_AR5212_GPIOCR_INT_SEL(gpio) | AR5K_AR5212_GPIOCR_INT_ENA); - - AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, - interrupt_level ? data : (data | AR5K_AR5212_GPIOCR_INT_SELH)); - - hal->ah_imr |= AR5K_AR5212_PIMR_GPIO; - - /* Enable GPIO interrupts */ - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, AR5K_AR5212_PIMR_GPIO); -} - -u_int32_t /*O.K.*/ -ar5k_ar5212_get_tsf32(struct ath_hal *hal) -{ - AR5K_TRACE; - return (AR5K_REG_READ(AR5K_AR5212_TSF_L32)); -} - -u_int64_t /*O.K.*/ -ar5k_ar5212_get_tsf64(struct ath_hal *hal) -{ - u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32); - AR5K_TRACE; - - return (AR5K_REG_READ(AR5K_AR5212_TSF_L32) | (tsf << 32)); -} - -void /*O.K.*/ -ar5k_ar5212_reset_tsf(struct ath_hal *hal) -{ - AR5K_TRACE; - AR5K_REG_ENABLE_BITS(AR5K_AR5212_BEACON, - AR5K_AR5212_BEACON_RESET_TSF); -} - -u_int16_t /*O.K.*/ -ar5k_ar5212_get_regdomain(struct ath_hal *hal) -{ - AR5K_TRACE; - return (ar5k_get_regdomain(hal)); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_detect_card_present(struct ath_hal *hal) -{ - u_int16_t magic; - AR5K_TRACE; - /* - * Checking the EEPROM's magic value could be an indication - * if the card is still present. I didn't find another suitable - * way to do this. - */ - if (ar5k_ar5212_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) - return (FALSE); - - return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); -} - -void /*O.K.*/ -ar5k_ar5212_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) -{ - AR5K_TRACE; - /* Read-And-Clear */ - statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5212_ACK_FAIL); - statistics->rts_bad += AR5K_REG_READ(AR5K_AR5212_RTS_FAIL); - statistics->rts_good += AR5K_REG_READ(AR5K_AR5212_RTS_OK); - statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5212_FCS_FAIL); - statistics->beacons += AR5K_REG_READ(AR5K_AR5212_BEACON_CNT); - - /* Reset profile count registers */ - AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_TX, 0); - AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RX, 0); - AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RXCLR, 0); - AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_CYCLE, 0); -} - -void /*Unimplemented*/ -ar5k_ar5212_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) -{ - AR5K_TRACE; - return; -} - -AR5K_RFGAIN /*O.K.*/ -ar5k_ar5212_get_rf_gain(struct ath_hal *hal) -{ - u_int32_t data, type; - - AR5K_TRACE; - if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active)) - return (AR5K_RFGAIN_INACTIVE); - - if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) - goto done; - - data = AR5K_REG_READ(AR5K_AR5212_PHY_PAPD_PROBE); - - if (!(data & AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT)) { - hal->ah_gain.g_current = - data >> AR5K_AR5212_PHY_PAPD_PROBE_GAINF_S; - type = AR5K_REG_MS(data, AR5K_AR5212_PHY_PAPD_PROBE_TYPE); - - if (type == AR5K_AR5212_PHY_PAPD_PROBE_TYPE_CCK) - hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR; - - if (hal->ah_radio == AR5K_AR5112) { - ar5k_rfregs_gainf_corr(hal); - hal->ah_gain.g_current = - hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? - (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : - 0; - } - - if (ar5k_rfregs_gain_readback(hal) && - AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && - ar5k_rfregs_gain_adjust(hal)) - hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE; - } - - done: - return (hal->ah_rf_gain); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_slot_time(struct ath_hal *hal, u_int slot_time) -{ - AR5K_TRACE; - if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) - return (FALSE); - - AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT, slot_time); - - return (TRUE); -} - -u_int /*O.K.*/ -ar5k_ar5212_get_slot_time(struct ath_hal *hal) -{ - AR5K_TRACE; - return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_ack_timeout(struct ath_hal *hal, u_int timeout) -{ - AR5K_TRACE; - if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_ACK), - hal->ah_turbo) <= timeout) - return (FALSE); - - AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_ACK, - ar5k_htoclock(timeout, hal->ah_turbo)); - - return (TRUE); -} - -u_int /*O.K.*/ -ar5k_ar5212_get_ack_timeout(struct ath_hal *hal) -{ - AR5K_TRACE; - return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT), - AR5K_AR5212_TIME_OUT_ACK), hal->ah_turbo)); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_cts_timeout(struct ath_hal *hal, u_int timeout) -{ - AR5K_TRACE; - if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_CTS), - hal->ah_turbo) <= timeout) - return (FALSE); - - AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_CTS, - ar5k_htoclock(timeout, hal->ah_turbo)); - - return (TRUE); -} - -u_int /*O.K.*/ -ar5k_ar5212_get_cts_timeout(struct ath_hal *hal) -{ - AR5K_TRACE; - return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT), - AR5K_AR5212_TIME_OUT_CTS), hal->ah_turbo)); -} - -AR5K_STATUS /*New*/ -ar5k_ar5212_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t *result) -{ - AR5K_TRACE; - - switch (cap_type) { - case AR5K_CAP_REG_DMN: - if (result){ - *result = ar5k_get_regdomain(hal); - goto yes; - } - case AR5K_CAP_CIPHER: - switch (capability) { - case AR5K_CIPHER_WEP: goto yes; - default: goto no; - } - case AR5K_CAP_NUM_TXQUEUES: - if (result) { - *result = AR5K_AR5212_TX_NUM_QUEUES; - goto yes; - } - case AR5K_CAP_VEOL: - goto yes; - case AR5K_CAP_COMPRESSION: - goto yes; - case AR5K_CAP_BURST: - goto yes; - case AR5K_CAP_TPC: - goto yes; - case AR5K_CAP_BSSIDMASK: - goto yes; - case AR5K_CAP_XR: - goto yes; - default: - goto no; - } - - no: - return (AR5K_EINVAL); - yes: - return AR5K_OK; - -} - -AR5K_BOOL -ar5k_ar5212_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, - u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) -{ - - AR5K_TRACE; - if (status) { - *status = AR5K_OK; - } - return (FALSE); -} - -/* - * Key table (WEP) functions - */ - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) -{ - AR5K_TRACE; - /* - * The AR5212 only supports WEP - */ - if (cipher == AR5K_CIPHER_WEP) - return (TRUE); - - return (FALSE); -} - -u_int32_t /*O.K.*/ -ar5k_ar5212_get_keycache_size(struct ath_hal *hal) -{ - AR5K_TRACE; - return (AR5K_AR5212_KEYCACHE_SIZE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_reset_key(struct ath_hal *hal, u_int16_t entry) -{ - int i; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); - - for (i = 0; i < AR5K_AR5212_KEYCACHE_SIZE; i++) - AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), 0); - - /* Set NULL encryption */ - AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_TYPE(entry), - AR5K_AR5212_KEYTABLE_TYPE_NULL); - - return (FALSE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_is_key_valid(struct ath_hal *hal, u_int16_t entry) -{ - AR5K_TRACE; - AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); - - /* - * Check the validation flag at the end of the entry - */ - if (AR5K_REG_READ(AR5K_AR5212_KEYTABLE_MAC1(entry)) & - AR5K_AR5212_KEYTABLE_VALID) - return (TRUE); - - return (FALSE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_key(struct ath_hal *hal, u_int16_t entry, - const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) -{ - int i; - u_int32_t key_v[AR5K_AR5212_KEYCACHE_SIZE - 2]; - - AR5K_TRACE; - AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); - - bzero(&key_v, sizeof(key_v)); - - switch (keyval->wk_len) { - case AR5K_KEYVAL_LENGTH_40: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 1); - key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_40; - break; - - case AR5K_KEYVAL_LENGTH_104: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 1); - key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_104; - break; - - case AR5K_KEYVAL_LENGTH_128: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 4); - key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_128; - break; - - default: - /* Unsupported key length (not WEP40/104/128) */ - return (FALSE); - } - - for (i = 0; i < AR5K_ELEMENTS(key_v); i++) - AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), key_v[i]); - - return (ar5k_ar5212_set_key_lladdr(hal, entry, mac)); -} - -AR5K_BOOL /*O.K. */ -ar5k_ar5212_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, - const u_int8_t *mac) -{ - u_int32_t low_id, high_id; - const u_int8_t *mac_v; - - AR5K_TRACE; - /* - * Invalid entry (key table overflow) - */ - AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); - - /* MAC may be NULL if it's a broadcast key */ - mac_v = mac == NULL ? etherbroadcastaddr : mac; - - low_id = AR5K_LOW_ID(mac_v); - high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5212_KEYTABLE_VALID; - - AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC0(entry), low_id); - AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC1(entry), high_id); - - return (TRUE); -} - -/* - * Power management functions - */ - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, - AR5K_BOOL set_chip, u_int16_t sleep_duration) -{ - u_int32_t staid; - int i; - - AR5K_TRACE; - staid = AR5K_REG_READ(AR5K_AR5212_STA_ID1); - - switch (mode) { - case AR5K_PM_AUTO: - staid &= ~AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; - /* fallthrough */ - case AR5K_PM_NETWORK_SLEEP: - if (set_chip == TRUE) { - AR5K_REG_WRITE(AR5K_AR5212_SCR, - AR5K_AR5212_SCR_SLE | sleep_duration); - } - staid |= AR5K_AR5212_STA_ID1_PWR_SV; - break; - - case AR5K_PM_FULL_SLEEP: - if (set_chip == TRUE) { - AR5K_REG_WRITE(AR5K_AR5212_SCR, - AR5K_AR5212_SCR_SLE_SLP); - } - staid |= AR5K_AR5212_STA_ID1_PWR_SV; - break; - - case AR5K_PM_AWAKE: - if (set_chip == FALSE) - goto commit; - - AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE_WAKE); - - for (i = 5000; i > 0; i--) { - /* Check if the AR5212 did wake up */ - if ((AR5K_REG_READ(AR5K_AR5212_PCICFG) & - AR5K_AR5212_PCICFG_SPWR_DN) == 0) - break; - - /* Wait a bit and retry */ - AR5K_DELAY(200); - AR5K_REG_WRITE(AR5K_AR5212_SCR, - AR5K_AR5212_SCR_SLE_WAKE); - } - - /* Fail if the AR5212 didn't wake up */ - if (i <= 0) - return (FALSE); - - staid &= ~AR5K_AR5212_STA_ID1_PWR_SV; - break; - - default: - return (FALSE); - } - - commit: - hal->ah_power_mode = mode; - - AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, staid); - - return (TRUE); -} - -AR5K_POWER_MODE /*O.K.*/ -ar5k_ar5212_get_power_mode(struct ath_hal *hal) -{ - AR5K_TRACE; - return (hal->ah_power_mode); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_query_pspoll_support(struct ath_hal *hal) -{ - AR5K_TRACE; - /* nope */ - return (FALSE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_init_pspoll(struct ath_hal *hal) -{ - AR5K_TRACE; - /* - * Not used on the AR5212 - */ - return (FALSE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, - u_int16_t assoc_id) -{ - AR5K_TRACE; - return (FALSE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_disable_pspoll(struct ath_hal *hal) -{ - AR5K_TRACE; - return (FALSE); -} - -/* - * Beacon functions - */ - -void /*O.K.*/ -ar5k_ar5212_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, - u_int32_t interval) -{ - u_int32_t timer1, timer2, timer3; - - AR5K_TRACE; - /* - * Set the additional timers by mode - */ - switch (hal->ah_op_mode) { - case AR5K_M_STA: - timer1 = 0x0000ffff; - timer2 = 0x0007ffff; - break; - - default: - timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << - 0x00000003; - timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << - 0x00000003; - } - - timer3 = next_beacon + - (hal->ah_atim_window ? hal->ah_atim_window : 1); - - /* - * Enable all timers and set the beacon register - * (next beacon, DMA beacon, software beacon, ATIM window time) - */ - AR5K_REG_WRITE(AR5K_AR5212_TIMER0, next_beacon); - AR5K_REG_WRITE(AR5K_AR5212_TIMER1, timer1); - AR5K_REG_WRITE(AR5K_AR5212_TIMER2, timer2); - AR5K_REG_WRITE(AR5K_AR5212_TIMER3, timer3); - - AR5K_REG_WRITE(AR5K_AR5212_BEACON, interval & - (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_RESET_TSF | - AR5K_AR5212_BEACON_ENABLE)); -} - -void /*Removed arguments - should be changed through *state - review AR5K_BEACON_STATE struct*/ -ar5k_ar5212_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) -{ - u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; - - u_int32_t dtim_count = 0; /* XXX */ - u_int32_t cfp_count = 0; /* XXX */ - u_int32_t tsf = 0; /* XXX */ - - AR5K_TRACE; - /* Return on an invalid beacon state */ - if (state->bs_interval < 1) - return; - - interval = state->bs_interval; - dtim = state->bs_dtim_period; - - /* - * PCF support? - */ - if (state->bs_cfp_period > 0) { - /* Enable CFP mode and set the CFP and timer registers */ - cfp_period = state->bs_cfp_period * state->bs_dtim_period * - state->bs_interval; - next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * - state->bs_interval; - - AR5K_REG_ENABLE_BITS(AR5K_AR5212_STA_ID1, - AR5K_AR5212_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_AR5212_CFP_PERIOD, cfp_period); - AR5K_REG_WRITE(AR5K_AR5212_CFP_DUR, state->bs_cfp_max_duration); - AR5K_REG_WRITE(AR5K_AR5212_TIMER2, - (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); - } else { - /* Disable PCF mode */ - AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1, - AR5K_AR5212_STA_ID1_PCF); - } - - /* - * Enable the beacon timer register - */ - AR5K_REG_WRITE(AR5K_AR5212_TIMER0, state->bs_next_beacon); - - /* - * Start the beacon timers - */ - AR5K_REG_WRITE(AR5K_AR5212_BEACON, - (AR5K_REG_READ(AR5K_AR5212_BEACON) &~ - (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_TIM)) | - AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, - AR5K_AR5212_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, - AR5K_AR5212_BEACON_PERIOD)); - - /* - * Write new beacon miss threshold, if it appears to be valid - */ - if ((AR5K_AR5212_RSSI_THR_BMISS >> AR5K_AR5212_RSSI_THR_BMISS_S) < - state->bs_bmiss_threshold) - return; - - AR5K_REG_WRITE_BITS(AR5K_AR5212_RSSI_THR_M, - AR5K_AR5212_RSSI_THR_BMISS, state->bs_bmiss_threshold); - - /* - * Set sleep registers - */ - if ((state->bs_sleep_duration > state->bs_interval) && - (roundup(state->bs_sleep_duration, interval) == - state->bs_sleep_duration)) - interval = state->bs_sleep_duration; - - if (state->bs_sleep_duration > dtim && - (dtim == 0 || roundup(state->bs_sleep_duration, dtim) == - state->bs_sleep_duration)) - dtim = state->bs_sleep_duration; - - if (interval > dtim) - return; - - next_beacon = interval == dtim ? - state->bs_next_dtim: state->bs_next_beacon; - - AR5K_REG_WRITE(AR5K_AR5212_SLEEP0, - AR5K_REG_SM((state->bs_next_dtim - 3) << 3, - AR5K_AR5212_SLEEP0_NEXT_DTIM) | - AR5K_REG_SM(10, AR5K_AR5212_SLEEP0_CABTO) | - AR5K_AR5212_SLEEP0_ENH_SLEEP_EN | - AR5K_AR5212_SLEEP0_ASSUME_DTIM); - AR5K_REG_WRITE(AR5K_AR5212_SLEEP1, - AR5K_REG_SM((next_beacon - 3) << 3, - AR5K_AR5212_SLEEP1_NEXT_TIM) | - AR5K_REG_SM(10, AR5K_AR5212_SLEEP1_BEACON_TO)); - AR5K_REG_WRITE(AR5K_AR5212_SLEEP2, - AR5K_REG_SM(interval, AR5K_AR5212_SLEEP2_TIM_PER) | - AR5K_REG_SM(dtim, AR5K_AR5212_SLEEP2_DTIM_PER)); -} - -void /*O.K.*/ -ar5k_ar5212_reset_beacon(struct ath_hal *hal) -{ - AR5K_TRACE; - /* - * Disable beacon timer - */ - AR5K_REG_WRITE(AR5K_AR5212_TIMER0, 0); - - /* - * Disable some beacon register values - */ - AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1, - AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5212_STA_ID1_PCF); - AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_AR5212_BEACON_PERIOD); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) -{ - AR5K_BOOL ret; - - AR5K_TRACE; - /* - * Wait for beaconn queue to be done - */ - ret = ar5k_register_timeout(hal, - AR5K_AR5212_QCU_STS(AR5K_TX_QUEUE_ID_BEACON), - AR5K_AR5212_QCU_STS_FRMPENDCNT, 0, FALSE); - - if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) - return (FALSE); - - return (ret); -} - -/* - * Interrupt handling - */ - -AR5K_BOOL -ar5k_ar5212_is_intr_pending(struct ath_hal *hal) -{ - AR5K_TRACE; - return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? FALSE : TRUE); -} - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) -{ - u_int32_t data; - - AR5K_TRACE; - /* - * Read interrupt status from the Read-And-Clear shadow register - */ - data = AR5K_REG_READ(AR5K_AR5212_RAC_PISR); - - /* - * Get abstract interrupt mask (HAL-compatible) - */ - *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; - - if (data == AR5K_INT_NOCARD) - return (FALSE); - - if (data & (AR5K_AR5212_PISR_RXOK | AR5K_AR5212_PISR_RXERR)) - *interrupt_mask |= AR5K_INT_RX; - - if (data & (AR5K_AR5212_PISR_TXOK | AR5K_AR5212_PISR_TXERR)) - *interrupt_mask |= AR5K_INT_TX; - - if (data & (AR5K_AR5212_PISR_HIUERR)) - *interrupt_mask |= AR5K_INT_FATAL; - - if (data & (AR5K_AR5212_PISR_BNR)) - *interrupt_mask |= AR5K_INT_BNR; - - /* - * Special interrupt handling (not caught by the driver) - */ - if (((*interrupt_mask) & AR5K_AR5212_PISR_RXPHY) && - hal->ah_radar.r_enabled == TRUE) - ar5k_radar_alert(hal); - - if (*interrupt_mask == 0) - AR5K_PRINTF("0x%08x\n", data); - - return (TRUE); -} - -u_int32_t /*O.K.*/ -ar5k_ar5212_get_intr(struct ath_hal *hal) -{ - AR5K_TRACE; - /* Return the interrupt mask stored previously */ - return (hal->ah_imr); -} - -AR5K_INT /*O.K.*/ -ar5k_ar5212_set_intr(struct ath_hal *hal, AR5K_INT new_mask) -{ - AR5K_INT old_mask, int_mask; - - /* - * Disable card interrupts to prevent any race conditions - * (they will be re-enabled afterwards). - */ - AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); - - old_mask = hal->ah_imr; - - /* - * Add additional, chipset-dependent interrupt mask flags - * and write them to the IMR (interrupt mask register). - */ - int_mask = new_mask & AR5K_INT_COMMON; - - if (new_mask & AR5K_INT_RX) - int_mask |= - AR5K_AR5212_PIMR_RXOK | - AR5K_AR5212_PIMR_RXERR | - AR5K_AR5212_PIMR_RXORN | - AR5K_AR5212_PIMR_RXDESC; - - if (new_mask & AR5K_INT_TX) - int_mask |= - AR5K_AR5212_PIMR_TXOK | - AR5K_AR5212_PIMR_TXERR | - AR5K_AR5212_PIMR_TXDESC | - AR5K_AR5212_PIMR_TXURN; - - if (new_mask & AR5K_INT_FATAL) { - int_mask |= AR5K_AR5212_PIMR_HIUERR; - AR5K_REG_ENABLE_BITS(AR5K_AR5212_SIMR2, - AR5K_AR5212_SIMR2_MCABT | - AR5K_AR5212_SIMR2_SSERR | - AR5K_AR5212_SIMR2_DPERR); - } - - AR5K_REG_WRITE(AR5K_AR5212_PIMR, int_mask); - - /* Store new interrupt mask */ - hal->ah_imr = new_mask; - - /* ..re-enable interrupts */ - AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); - - return (old_mask); -} - -/* - * Misc internal functions - */ - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_get_capabilities(struct ath_hal *hal) -{ - u_int16_t ee_header; - - AR5K_TRACE; - /* Capabilities stored in the EEPROM */ - ee_header = hal->ah_capabilities.cap_eeprom.ee_header; - - /* - * XXX The AR5212 tranceiver supports frequencies from 4920 to 6100GHz - * XXX and from 2312 to 2732GHz. There are problems with the current - * XXX ieee80211 implementation because the IEEE channel mapping - * XXX does not support negative channel numbers (2312MHz is channel - * XXX -19). Of course, this doesn't matter because these channels - * XXX are out of range but some regulation domains like MKK (Japan) - * XXX will support frequencies somewhere around 4.8GHz. - */ - - /* - * Set radio capabilities - */ - - if (AR5K_EEPROM_HDR_11A(ee_header)) { - hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ - hal->ah_capabilities.cap_range.range_5ghz_max = 6100; - - /* Set supported modes */ - hal->ah_capabilities.cap_mode = - AR5K_MODE_11A | AR5K_MODE_TURBO | AR5K_MODE_XR; - } - - /* This chip will support 802.11b if the 2GHz radio is connected */ - if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { - hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ - hal->ah_capabilities.cap_range.range_2ghz_max = 2732; - - if (AR5K_EEPROM_HDR_11B(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; -#if 0 - if (AR5K_EEPROM_HDR_11G(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; -#endif - } - - /* GPIO */ - hal->ah_gpio_npins = AR5K_AR5212_NUM_GPIO; - - /* Set number of supported TX queues */ - hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5212_TX_NUM_QUEUES; - - return (TRUE); -} - -void /*O.K.*/ -ar5k_ar5212_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) -{ - - AR5K_TRACE; - /* - * Enable radar detection - */ - AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); - - if (enable == TRUE) { - AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, - AR5K_AR5212_PHY_RADAR_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, - AR5K_AR5212_PIMR_RXPHY); - } else { - AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, - AR5K_AR5212_PHY_RADAR_DISABLE); - AR5K_REG_DISABLE_BITS(AR5K_AR5212_PIMR, - AR5K_AR5212_PIMR_RXPHY); - } - - AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); -} - -/* - * EEPROM access functions - */ - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_eeprom_is_busy(struct ath_hal *hal) -{ - AR5K_TRACE; - return (AR5K_REG_READ(AR5K_AR5212_CFG) & AR5K_AR5212_CFG_EEBS ? - TRUE : FALSE); -} - -int /*O.K.*/ -ar5k_ar5212_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) -{ - u_int32_t status, i; - - AR5K_TRACE; - /* - * Initialize EEPROM access - */ - AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset); - AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, - AR5K_AR5212_EEPROM_CMD_READ); - - for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { - status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS); - if (status & AR5K_AR5212_EEPROM_STAT_RDDONE) { - if (status & AR5K_AR5212_EEPROM_STAT_RDERR) - return (EIO); - *data = (u_int16_t) - (AR5K_REG_READ(AR5K_AR5212_EEPROM_DATA) & 0xffff); - return (0); - } - AR5K_DELAY(15); - } - - return (ETIMEDOUT); -} - -int /*O.K.*/ -ar5k_ar5212_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) -{ - u_int32_t status, timeout; - - AR5K_TRACE; - /* Enable eeprom access */ - AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, - AR5K_AR5212_EEPROM_CMD_RESET); - AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, - AR5K_AR5212_EEPROM_CMD_WRITE); - - /* - * Prime write pump - */ - AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset - 1); - - for (timeout = 10000; timeout > 0; timeout--) { - AR5K_DELAY(1); - status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS); - if (status & AR5K_AR5212_EEPROM_STAT_WRDONE) { - if (status & AR5K_AR5212_EEPROM_STAT_WRERR) - return (EIO); - return (0); - } - } - - return (ETIMEDOUT); -} - -/* - * TX power setup - */ - -AR5K_BOOL /*O.K.*/ -ar5k_ar5212_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower) -{ - AR5K_BOOL tpc = hal->ah_txpower.txp_tpc; - int i; - - AR5K_TRACE; - if (txpower > AR5K_TUNE_MAX_TXPOWER) { - AR5K_PRINTF("invalid tx power: %u\n", txpower); - return (FALSE); - } - - /* Reset TX power values */ - bzero(&hal->ah_txpower, sizeof(hal->ah_txpower)); - hal->ah_txpower.txp_tpc = tpc; - - /* Initialize TX power table */ - ar5k_txpower_table(hal, channel, txpower); - - /* - * Write TX power values - */ - for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { - AR5K_REG_WRITE(AR5K_AR5212_PHY_PCDAC_TXPOWER(i), - ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & - 0xffff) << 16) | (((hal->ah_txpower.txp_pcdac[i << 1] << 8) - | 0xff) & 0xffff)); - } - - AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE1, - AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16) - | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0)); - - AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE2, - AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16) - | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0)); - - AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE3, - AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16) - | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0)); - - AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE4, - AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) - | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); - - if (hal->ah_txpower.txp_tpc == TRUE) { - AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, - AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | - AR5K_TUNE_MAX_TXPOWER); - } else { - AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, - AR5K_AR5212_PHY_TXPOWER_RATE_MAX | - AR5K_TUNE_MAX_TXPOWER); - } - - return (TRUE); -} - -AR5K_BOOL /*New*/ -ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int power) -{ - /*Just a try M.F.*/ - AR5K_CHANNEL *channel = &hal->ah_current_channel; - - AR5K_TRACE; - AR5K_PRINTF("changing txpower to %d\n",power); - return (ar5k_ar5212_txpower(hal, channel, power)); -} Index: ar5210reg.h =================================================================== --- ar5210reg.h (revision 2185) +++ ar5210reg.h (revision 2232) @@ -1,706 +0,0 @@ -/* $OpenBSD: ar5210reg.h,v 1.10 2005/12/18 17:59:58 reyk Exp $ */ - -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Known registers of the Atheros AR5000 Wireless LAN chipset - * (AR5210 + AR5110). - */ - -#ifndef _AR5K_AR5210_REG_H -#define _AR5K_AR5210_REG_H - -/* - * First tansmit queue descriptor pointer register ("data queue") - */ -#define AR5K_AR5210_TXDP0 0x0000 - -/* - * Second transmit queue descriptor pointer register ("beacon queue") - */ -#define AR5K_AR5210_TXDP1 0x0004 - -/* - * Command register - */ -#define AR5K_AR5210_CR 0x0008 -#define AR5K_AR5210_CR_TXE0 0x00000001 -#define AR5K_AR5210_CR_TXE1 0x00000002 -#define AR5K_AR5210_CR_RXE 0x00000004 -#define AR5K_AR5210_CR_TXD0 0x00000008 -#define AR5K_AR5210_CR_TXD1 0x00000010 -#define AR5K_AR5210_CR_RXD 0x00000020 -#define AR5K_AR5210_CR_SWI 0x00000040 - -/* - * Receive queue descriptor pointer register - */ -#define AR5K_AR5210_RXDP 0x000c - -/* - * Configuration and status register - */ -#define AR5K_AR5210_CFG 0x0014 -#define AR5K_AR5210_CFG_SWTD 0x00000001 -#define AR5K_AR5210_CFG_SWTB 0x00000002 -#define AR5K_AR5210_CFG_SWRD 0x00000004 -#define AR5K_AR5210_CFG_SWRB 0x00000008 -#define AR5K_AR5210_CFG_SWRG 0x00000010 -#define AR5K_AR5210_CFG_EEBS 0x00000200 -#define AR5K_AR5210_CFG_TXCNT 0x00007800 -#define AR5K_AR5210_CFG_TXCNT_S 11 -#define AR5K_AR5210_CFG_TXFSTAT 0x00008000 -#define AR5K_AR5210_CFG_TXFSTRT 0x00010000 - -/* - * Interrupt service register - */ -#define AR5K_AR5210_ISR 0x001c -#define AR5K_AR5210_ISR_RXOK 0x00000001 -#define AR5K_AR5210_ISR_RXDESC 0x00000002 -#define AR5K_AR5210_ISR_RXERR 0x00000004 -#define AR5K_AR5210_ISR_RXNOFRM 0x00000008 -#define AR5K_AR5210_ISR_RXEOL 0x00000010 -#define AR5K_AR5210_ISR_RXORN 0x00000020 -#define AR5K_AR5210_ISR_TXOK 0x00000040 -#define AR5K_AR5210_ISR_TXDESC 0x00000080 -#define AR5K_AR5210_ISR_TXERR 0x00000100 -#define AR5K_AR5210_ISR_TXNOFRM 0x00000200 -#define AR5K_AR5210_ISR_TXEOL 0x00000400 -#define AR5K_AR5210_ISR_TXURN 0x00000800 -#define AR5K_AR5210_ISR_MIB 0x00001000 -#define AR5K_AR5210_ISR_SWI 0x00002000 -#define AR5K_AR5210_ISR_RXPHY 0x00004000 -#define AR5K_AR5210_ISR_RXKCM 0x00008000 -#define AR5K_AR5210_ISR_SWBA 0x00010000 -#define AR5K_AR5210_ISR_BRSSI 0x00020000 -#define AR5K_AR5210_ISR_BMISS 0x00040000 -#define AR5K_AR5210_ISR_MCABT 0x00100000 -#define AR5K_AR5210_ISR_SSERR 0x00200000 -#define AR5K_AR5210_ISR_DPERR 0x00400000 -#define AR5K_AR5210_ISR_GPIO 0x01000000 -#define AR5K_AR5210_ISR_FATAL ( \ - AR5K_AR5210_ISR_MCABT | AR5K_AR5210_ISR_SSERR | \ - AR5K_AR5210_ISR_DPERR | AR5K_AR5210_ISR_RXORN \ -) - -/* - * Interrupt mask register - */ -#define AR5K_AR5210_IMR 0x0020 -#define AR5K_AR5210_IMR_RXOK 0x00000001 -#define AR5K_AR5210_IMR_RXDESC 0x00000002 -#define AR5K_AR5210_IMR_RXERR 0x00000004 -#define AR5K_AR5210_IMR_RXNOFRM 0x00000008 -#define AR5K_AR5210_IMR_RXEOL 0x00000010 -#define AR5K_AR5210_IMR_RXORN 0x00000020 -#define AR5K_AR5210_IMR_TXOK 0x00000040 -#define AR5K_AR5210_IMR_TXDESC 0x00000080 -#define AR5K_AR5210_IMR_TXERR 0x00000100 -#define AR5K_AR5210_IMR_TXNOFRM 0x00000200 -#define AR5K_AR5210_IMR_TXEOL 0x00000400 -#define AR5K_AR5210_IMR_TXURN 0x00000800 -#define AR5K_AR5210_IMR_MIB 0x00001000 -#define AR5K_AR5210_IMR_SWI 0x00002000 -#define AR5K_AR5210_IMR_RXPHY 0x00004000 -#define AR5K_AR5210_IMR_RXKCM 0x00008000 -#define AR5K_AR5210_IMR_SWBA 0x00010000 -#define AR5K_AR5210_IMR_BRSSI 0x00020000 -#define AR5K_AR5210_IMR_BMISS 0x00040000 -#define AR5K_AR5210_IMR_MCABT 0x00100000 -#define AR5K_AR5210_IMR_SSERR 0x00200000 -#define AR5K_AR5210_IMR_DPERR 0x00400000 -#define AR5K_AR5210_IMR_GPIO 0x01000000 - -/* - * Interrupt enable register - */ -#define AR5K_AR5210_IER 0x0024 -#define AR5K_AR5210_IER_DISABLE 0x00000000 -#define AR5K_AR5210_IER_ENABLE 0x00000001 - -/* - * Beacon control register - */ -#define AR5K_AR5210_BCR 0x0028 -#define AR5K_AR5210_BCR_AP 0x00000000 -#define AR5K_AR5210_BCR_ADHOC 0x00000001 -#define AR5K_AR5210_BCR_BDMAE 0x00000002 -#define AR5K_AR5210_BCR_TQ1FV 0x00000004 -#define AR5K_AR5210_BCR_TQ1V 0x00000008 -#define AR5K_AR5210_BCR_BCGET 0x00000010 - -/* - * Beacon status register - */ -#define AR5K_AR5210_BSR 0x002c -#define AR5K_AR5210_BSR_BDLYSW 0x00000001 -#define AR5K_AR5210_BSR_BDLYDMA 0x00000002 -#define AR5K_AR5210_BSR_TXQ1F 0x00000004 -#define AR5K_AR5210_BSR_ATIMDLY 0x00000008 -#define AR5K_AR5210_BSR_SNPBCMD 0x00000100 -#define AR5K_AR5210_BSR_SNPBDMAE 0x00000200 -#define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400 -#define AR5K_AR5210_BSR_SNPTQ1V 0x00000800 -#define AR5K_AR5210_BSR_SNAPPEDBCRVALID 0x00001000 -#define AR5K_AR5210_BSR_SWBA_CNT 0x00ff0000 - -/* - * DMA size definitions - */ -typedef enum { - AR5K_AR5210_DMASIZE_4B = 0, - AR5K_AR5210_DMASIZE_8B, - AR5K_AR5210_DMASIZE_16B, - AR5K_AR5210_DMASIZE_32B, - AR5K_AR5210_DMASIZE_64B, - AR5K_AR5210_DMASIZE_128B, - AR5K_AR5210_DMASIZE_256B, - AR5K_AR5210_DMASIZE_512B -} ar5k_ar5210_dmasize_t; - -/* - * Transmit configuration register - */ -#define AR5K_AR5210_TXCFG 0x0030 -#define AR5K_AR5210_TXCFG_SDMAMR 0x00000007 -#define AR5K_AR5210_TXCFG_TXFSTP 0x00000008 -#define AR5K_AR5210_TXCFG_TXFULL 0x00000070 -#define AR5K_AR5210_TXCFG_TXCONT_EN 0x00000080 - -/* - * Receive configuration register - */ -#define AR5K_AR5210_RXCFG 0x0034 -#define AR5K_AR5210_RXCFG_SDMAMW 0x00000007 -#define AR5K_AR5210_RXCFG_ZLFDMA 0x00000010 - -/* - * MIB control register - */ -#define AR5K_AR5210_MIBC 0x0040 -#define AR5K_AR5210_MIBC_COW 0x00000001 -#define AR5K_AR5210_MIBC_FMC 0x00000002 -#define AR5K_AR5210_MIBC_CMC 0x00000004 -#define AR5K_AR5210_MIBC_MCS 0x00000008 - -/* - * Timeout prescale register - */ -#define AR5K_AR5210_TOPS 0x0044 - -/* - * Receive timeout register (no frame received) - */ -#define AR5K_AR5210_RXNOFRM 0x0048 - -/* - * Transmit timeout register (no frame sent) - */ -#define AR5K_AR5210_TXNOFRM 0x004c - -/* - * Receive frame gap timeout register - */ -#define AR5K_AR5210_RPGTO 0x0050 - -/* - * Receive frame count limit register - */ -#define AR5K_AR5210_RFCNT 0x0054 -#define AR5K_AR5210_RFCNT_RFCL 0x0000000f - -/* - * Misc settings/status register - */ -#define AR5K_AR5210_MISC 0x0058 -#define AR5K_AR5210_MISC_LED_DECAY 0x001c0000 -#define AR5K_AR5210_MISC_LED_BLINK 0x00e00000 - -/* - * Reset control register - */ -#define AR5K_AR5210_RC 0x4000 -#define AR5K_AR5210_RC_PCU 0x00000001 -#define AR5K_AR5210_RC_DMA 0x00000002 -#define AR5K_AR5210_RC_MAC 0x00000004 -#define AR5K_AR5210_RC_PHY 0x00000008 -#define AR5K_AR5210_RC_PCI 0x00000010 -#define AR5K_AR5210_RC_CHIP ( \ - AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_DMA | \ - AR5K_AR5210_RC_MAC | AR5K_AR5210_RC_PHY \ -) - -/* - * Sleep control register - */ -#define AR5K_AR5210_SCR 0x4004 -#define AR5K_AR5210_SCR_SLDUR 0x0000ffff -#define AR5K_AR5210_SCR_SLE 0x00030000 -#define AR5K_AR5210_SCR_SLE_WAKE 0x00000000 -#define AR5K_AR5210_SCR_SLE_SLP 0x00010000 -#define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000 - -/* - * Interrupt pending register - */ -#define AR5K_AR5210_INTPEND 0x4008 -#define AR5K_AR5210_INTPEND_IP 0x00000001 - -/* - * Sleep force register - */ -#define AR5K_AR5210_SFR 0x400c -#define AR5K_AR5210_SFR_SF 0x00000001 - -/* - * PCI configuration register - */ -#define AR5K_AR5210_PCICFG 0x4010 -#define AR5K_AR5210_PCICFG_EEAE 0x00000001 -#define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004 -#define AR5K_AR5210_PCICFG_LED_PEND 0x00000020 -#define AR5K_AR5210_PCICFG_LED_ACT 0x00000040 -#define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800 -#define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000 -#define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800 -#define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000 - -/* - * "General Purpose Input/Output" (GPIO) control register - */ -#define AR5K_AR5210_GPIOCR 0x4014 -#define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000 -#define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000 -#define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000 -#define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2)) -#define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12) - -#define AR5K_AR5210_NUM_GPIO 6 - -/* - * "General Purpose Input/Output" (GPIO) data output register - */ -#define AR5K_AR5210_GPIODO 0x4018 - -/* - * "General Purpose Input/Output" (GPIO) data input register - */ -#define AR5K_AR5210_GPIODI 0x401c -#define AR5K_AR5210_GPIOD_MASK 0x0000002f - -/* - * Silicon revision register - */ -#define AR5K_AR5210_SREV 0x4020 -#define AR5K_AR5210_SREV_REV 0x0000000f -#define AR5K_AR5210_SREV_REV_S 0 -#define AR5K_AR5210_SREV_VER 0x000000ff -#define AR5K_AR5210_SREV_VER_S 4 - -/* - * EEPROM access registers - */ -#define AR5K_AR5210_EEPROM_BASE 0x6000 -#define AR5K_AR5210_EEPROM_RDATA 0x6800 -#define AR5K_AR5210_EEPROM_STATUS 0x6c00 -#define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001 -#define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002 -#define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004 -#define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008 - -/* - * PCU registers - */ - -#define AR5K_AR5210_PCU_MIN 0x8000 -#define AR5K_AR5210_PCU_MAX 0x8fff - -/* - * First station id register (MAC address in lower 32 bits) - */ -#define AR5K_AR5210_STA_ID0 0x8000 - -/* - * Second station id register (MAC address in upper 16 bits) - */ -#define AR5K_AR5210_STA_ID1 0x8004 -#define AR5K_AR5210_STA_ID1_AP 0x00010000 -#define AR5K_AR5210_STA_ID1_ADHOC 0x00020000 -#define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000 -#define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000 -#define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000 -#define AR5K_AR5210_STA_ID1_PCF 0x00200000 -#define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000 -#define AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA 0x00800000 -#define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000 - -/* - * First BSSID register (MAC address, lower 32bits) - */ -#define AR5K_AR5210_BSS_ID0 0x8008 - -/* - * Second BSSID register (MAC address in upper 16 bits) - * - * AID: Association ID - */ -#define AR5K_AR5210_BSS_ID1 0x800c -#define AR5K_AR5210_BSS_ID1_AID 0xffff0000 -#define AR5K_AR5210_BSS_ID1_AID_S 16 - -/* - * Backoff slot time register - */ -#define AR5K_AR5210_SLOT_TIME 0x8010 - -/* - * ACK/CTS timeout register - */ -#define AR5K_AR5210_TIME_OUT 0x8014 -#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff -#define AR5K_AR5210_TIME_OUT_ACK_S 0 -#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000 -#define AR5K_AR5210_TIME_OUT_CTS_S 16 - -/* - * RSSI threshold register - */ -#define AR5K_AR5210_RSSI_THR 0x8018 -#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700 -#define AR5K_AR5210_RSSI_THR_BM_THR_S 8 - -/* - * Retry limit register - */ -#define AR5K_AR5210_RETRY_LMT 0x801c -#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f -#define AR5K_AR5210_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0 -#define AR5K_AR5210_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00 -#define AR5K_AR5210_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000 -#define AR5K_AR5210_RETRY_LMT_SLG_RETRY_S 14 -#define AR5K_AR5210_RETRY_LMT_CW_MIN 0x3ff00000 -#define AR5K_AR5210_RETRY_LMT_CW_MIN_S 20 - -/* - * Transmit latency register - */ -#define AR5K_AR5210_USEC 0x8020 -#define AR5K_AR5210_USEC_1 0x0000007f -#define AR5K_AR5210_USEC_1_S 0 -#define AR5K_AR5210_USEC_32 0x00003f80 -#define AR5K_AR5210_USEC_32_S 7 -#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000 -#define AR5K_AR5210_USEC_TX_LATENCY_S 14 -#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000 -#define AR5K_AR5210_USEC_RX_LATENCY_S 20 - -/* - * PCU beacon control register - */ -#define AR5K_AR5210_BEACON 0x8024 -#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff -#define AR5K_AR5210_BEACON_PERIOD_S 0 -#define AR5K_AR5210_BEACON_TIM 0x007f0000 -#define AR5K_AR5210_BEACON_TIM_S 16 -#define AR5K_AR5210_BEACON_EN 0x00800000 -#define AR5K_AR5210_BEACON_RESET_TSF 0x01000000 - -/* - * CFP period register - */ -#define AR5K_AR5210_CFP_PERIOD 0x8028 - -/* - * Next beacon time register - */ -#define AR5K_AR5210_TIMER0 0x802c - -/* - * Next DMA beacon alert register - */ -#define AR5K_AR5210_TIMER1 0x8030 - -/* - * Next software beacon alert register - */ -#define AR5K_AR5210_TIMER2 0x8034 - -/* - * Next ATIM window time register - */ -#define AR5K_AR5210_TIMER3 0x8038 - -/* - * First inter frame spacing register (IFS) - */ -#define AR5K_AR5210_IFS0 0x8040 -#define AR5K_AR5210_IFS0_SIFS 0x000007ff -#define AR5K_AR5210_IFS0_SIFS_S 0 -#define AR5K_AR5210_IFS0_DIFS 0x007ff800 -#define AR5K_AR5210_IFS0_DIFS_S 11 - -/* - * Second inter frame spacing register (IFS) - */ -#define AR5K_AR5210_IFS1 0x8044 -#define AR5K_AR5210_IFS1_PIFS 0x00000fff -#define AR5K_AR5210_IFS1_PIFS_S 0 -#define AR5K_AR5210_IFS1_EIFS 0x03fff000 -#define AR5K_AR5210_IFS1_EIFS_S 12 -#define AR5K_AR5210_IFS1_CS_EN 0x04000000 - -/* - * CFP duration register - */ -#define AR5K_AR5210_CFP_DUR 0x8048 - -/* - * Receive filter register - */ -#define AR5K_AR5210_RX_FILTER 0x804c -#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001 -#define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002 -#define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004 -#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008 -#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010 -#define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020 - -/* - * Multicast filter register (lower 32 bits) - */ -#define AR5K_AR5210_MCAST_FIL0 0x8050 - -/* - * Multicast filter register (higher 16 bits) - */ -#define AR5K_AR5210_MCAST_FIL1 0x8054 - -/* - * Transmit mask register (lower 32 bits) - */ -#define AR5K_AR5210_TX_MASK0 0x8058 - -/* - * Transmit mask register (higher 16 bits) - */ -#define AR5K_AR5210_TX_MASK1 0x805c - -/* - * Clear transmit mask - */ -#define AR5K_AR5210_CLR_TMASK 0x8060 - -/* - * Trigger level register (before transmission) - */ -#define AR5K_AR5210_TRIG_LVL 0x8064 - -/* - * PCU control register - */ -#define AR5K_AR5210_DIAG_SW 0x8068 -#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001 -#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002 -#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004 -#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008 -#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010 -#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020 -#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040 -#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080 -#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100 -#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200 -#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400 -#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800 -#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000 -#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000 - -/* - * TSF (clock) register (lower 32 bits) - */ -#define AR5K_AR5210_TSF_L32 0x806c - -/* - * TSF (clock) register (higher 32 bits) - */ -#define AR5K_AR5210_TSF_U32 0x8070 - -/* - * Last beacon timestamp register - */ -#define AR5K_AR5210_LAST_TSTP 0x8080 - -/* - * Retry count register - */ -#define AR5K_AR5210_RETRY_CNT 0x8084 -#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f -#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0 - -/* - * Back-off status register - */ -#define AR5K_AR5210_BACKOFF 0x8088 -#define AR5K_AR5210_BACKOFF_CW 0x000003ff -#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000 - -/* - * NAV register (current) - */ -#define AR5K_AR5210_NAV 0x808c - -/* - * RTS success register - */ -#define AR5K_AR5210_RTS_OK 0x8090 - -/* - * RTS failure register - */ -#define AR5K_AR5210_RTS_FAIL 0x8094 - -/* - * ACK failure register - */ -#define AR5K_AR5210_ACK_FAIL 0x8098 - -/* - * FCS failure register - */ -#define AR5K_AR5210_FCS_FAIL 0x809c - -/* - * Beacon count register - */ -#define AR5K_AR5210_BEACON_CNT 0x80a0 - -/* - * Key table (WEP) register - */ -#define AR5K_AR5210_KEYTABLE_0 0x9000 -#define AR5K_AR5210_KEYTABLE(n) (AR5K_AR5210_KEYTABLE_0 + ((n) << 5)) -#define AR5K_AR5210_KEYTABLE_OFF(_n, x) (AR5K_AR5210_KEYTABLE(_n) + (x << 2)) -#define AR5K_AR5210_KEYTABLE_TYPE(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 5) -#define AR5K_AR5210_KEYTABLE_TYPE_40 0x00000000 -#define AR5K_AR5210_KEYTABLE_TYPE_104 0x00000001 -#define AR5K_AR5210_KEYTABLE_TYPE_128 0x00000003 -#define AR5K_AR5210_KEYTABLE_MAC0(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 6) -#define AR5K_AR5210_KEYTABLE_MAC1(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 7) -#define AR5K_AR5210_KEYTABLE_VALID 0x00008000 - -#define AR5K_AR5210_KEYTABLE_SIZE 64 -#define AR5K_AR5210_KEYCACHE_SIZE 8 - -/* - * PHY register - */ -#define AR5K_AR5210_PHY(_n) (0x9800 + ((_n) << 2)) - -/* - * PHY frame control register - */ -#define AR5K_AR5210_PHY_FC 0x9804 -#define AR5K_AR5210_PHY_FC_TURBO_MODE 0x00000001 -#define AR5K_AR5210_PHY_FC_TURBO_SHORT 0x00000002 -#define AR5K_AR5210_PHY_FC_TIMING_ERR 0x01000000 -#define AR5K_AR5210_PHY_FC_PARITY_ERR 0x02000000 -#define AR5K_AR5210_PHY_FC_ILLRATE_ERR 0x04000000 -#define AR5K_AR5210_PHY_FC_ILLLEN_ERR 0x08000000 -#define AR5K_AR5210_PHY_FC_SERVICE_ERR 0x20000000 -#define AR5K_AR5210_PHY_FC_TXURN_ERR 0x40000000 - -/* - * PHY agility command register - */ -#define AR5K_AR5210_PHY_AGC 0x9808 -#define AR5K_AR5210_PHY_AGC_DISABLE 0x08000000 - -/* - * PHY chip revision register - */ -#define AR5K_AR5210_PHY_CHIP_ID 0x9818 - -/* - * PHY activation register - */ -#define AR5K_AR5210_PHY_ACTIVE 0x981c -#define AR5K_AR5210_PHY_ENABLE 0x00000001 -#define AR5K_AR5210_PHY_DISABLE 0x00000002 - -/* - * PHY signal register - */ -#define AR5K_AR5210_PHY_SIG 0x9858 -#define AR5K_AR5210_PHY_SIG_FIRSTEP 0x0003f000 -#define AR5K_AR5210_PHY_SIG_FIRSTEP_S 12 -#define AR5K_AR5210_PHY_SIG_FIRPWR 0x03fc0000 -#define AR5K_AR5210_PHY_SIG_FIRPWR_S 18 - -/* - * PHY coarse agility control register - */ -#define AR5K_AR5210_PHY_AGCCOARSE 0x985c -#define AR5K_AR5210_PHY_AGCCOARSE_LO 0x00007f80 -#define AR5K_AR5210_PHY_AGCCOARSE_LO_S 7 -#define AR5K_AR5210_PHY_AGCCOARSE_HI 0x003f8000 -#define AR5K_AR5210_PHY_AGCCOARSE_HI_S 15 - -/* - * PHY agility control register - */ -#define AR5K_AR5210_PHY_AGCCTL 0x9860 -#define AR5K_AR5210_PHY_AGCCTL_CAL 0x00000001 -#define AR5K_AR5210_PHY_AGCCTL_NF 0x00000002 - -/* - * PHY noise floor status register - */ -#define AR5K_AR5210_PHY_NF 0x9864 -#define AR5K_AR5210_PHY_NF_M 0x000001ff -#define AR5K_AR5210_PHY_NF_ACTIVE 0x00000100 -#define AR5K_AR5210_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5210_PHY_NF_M) -#define AR5K_AR5210_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5210_PHY_NF_M) + 1) - -/* - * PHY ADC saturation register - */ -#define AR5K_AR5210_PHY_ADCSAT 0x9868 -#define AR5K_AR5210_PHY_ADCSAT_ICNT 0x0001f800 -#define AR5K_AR5210_PHY_ADCSAT_ICNT_S 11 -#define AR5K_AR5210_PHY_ADCSAT_THR 0x000007e0 -#define AR5K_AR5210_PHY_ADCSAT_THR_S 5 - -/* - * PHY RF stage register - */ -#define AR5K_AR5210_PHY_RFSTG 0x98d4 -#define AR5K_AR5210_PHY_RFSTG_DISABLE 0x00000021 - -/* - * Misc PHY/radio registers - */ -#define AR5K_AR5210_BB_GAIN(_n) (0x9b00 + ((_n) << 2)) -#define AR5K_AR5210_RF_GAIN(_n) (0x9a00 + ((_n) << 2)) - -#endif Index: ar5211reg.h =================================================================== --- ar5211reg.h (revision 2185) +++ ar5211reg.h (revision 2232) @@ -1,1045 +0,0 @@ -/* $OpenBSD: ar5211reg.h,v 1.8 2005/12/18 17:59:58 reyk Exp $ */ - -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Known registers of the Atheros AR5001 Wireless LAN chipsets - * (AR5211/AR5311). - */ - -#ifndef _AR5K_AR5211_REG_H -#define _AR5K_AR5211_REG_H - -/* - * Command register - */ -#define AR5K_AR5211_CR 0x0008 -#define AR5K_AR5211_CR_RXE 0x00000004 -#define AR5K_AR5211_CR_RXD 0x00000020 -#define AR5K_AR5211_CR_SWI 0x00000040 - -/* - * Receive queue descriptor pointer register - */ -#define AR5K_AR5211_RXDP 0x000c - -/* - * Configuration and status register - */ -#define AR5K_AR5211_CFG 0x0014 -#define AR5K_AR5211_CFG_SWTD 0x00000001 -#define AR5K_AR5211_CFG_SWTB 0x00000002 -#define AR5K_AR5211_CFG_SWRD 0x00000004 -#define AR5K_AR5211_CFG_SWRB 0x00000008 -#define AR5K_AR5211_CFG_SWRG 0x00000010 -#define AR5K_AR5211_CFG_ADHOC 0x00000020 -#define AR5K_AR5211_CFG_PHY_OK 0x00000100 -#define AR5K_AR5211_CFG_EEBS 0x00000200 -#define AR5K_AR5211_CFG_CLKGD 0x00000400 -#define AR5K_AR5211_CFG_PCI_THRES 0x00060000 -#define AR5K_AR5211_CFG_PCI_THRES_S 17 - -/* - * Interrupt enable register - */ -#define AR5K_AR5211_IER 0x0024 -#define AR5K_AR5211_IER_DISABLE 0x00000000 -#define AR5K_AR5211_IER_ENABLE 0x00000001 - -/* - * First RTS duration register - */ -#define AR5K_AR5211_RTSD0 0x0028 -#define AR5K_AR5211_RTSD0_6 0x000000ff -#define AR5K_AR5211_RTSD0_6_S 0 -#define AR5K_AR5211_RTSD0_9 0x0000ff00 -#define AR5K_AR5211_RTSD0_9_S 8 -#define AR5K_AR5211_RTSD0_12 0x00ff0000 -#define AR5K_AR5211_RTSD0_12_S 16 -#define AR5K_AR5211_RTSD0_18 0xff000000 -#define AR5K_AR5211_RTSD0_18_S 24 - -/* - * Second RTS duration register - */ -#define AR5K_AR5211_RTSD1 0x002c -#define AR5K_AR5211_RTSD1_24 0x000000ff -#define AR5K_AR5211_RTSD1_24_S 0 -#define AR5K_AR5211_RTSD1_36 0x0000ff00 -#define AR5K_AR5211_RTSD1_36_S 8 -#define AR5K_AR5211_RTSD1_48 0x00ff0000 -#define AR5K_AR5211_RTSD1_48_S 16 -#define AR5K_AR5211_RTSD1_54 0xff000000 -#define AR5K_AR5211_RTSD1_54_S 24 - -/* - * Transmit configuration register - */ -#define AR5K_AR5211_TXCFG 0x0030 -#define AR5K_AR5211_TXCFG_SDMAMR 0x00000007 -#define AR5K_AR5211_TXCFG_SDMAMR_S 0 -#define AR5K_AR5211_TXCFG_B_MODE 0x00000008 -#define AR5K_AR5211_TXCFG_TXFULL 0x000003f0 -#define AR5K_AR5211_TXCFG_TXFULL_S 4 -#define AR5K_AR5211_TXCFG_TXFULL_0B 0x00000000 -#define AR5K_AR5211_TXCFG_TXFULL_64B 0x00000010 -#define AR5K_AR5211_TXCFG_TXFULL_128B 0x00000020 -#define AR5K_AR5211_TXCFG_TXFULL_192B 0x00000030 -#define AR5K_AR5211_TXCFG_TXFULL_256B 0x00000040 -#define AR5K_AR5211_TXCFG_TXCONT_ENABLE 0x00000080 -#define AR5K_AR5211_TXCFG_DMASIZE 0x00000100 -#define AR5K_AR5211_TXCFG_JUMBO_TXE 0x00000400 -#define AR5K_AR5211_TXCFG_RTSRND 0x00001000 -#define AR5K_AR5211_TXCFG_FRMPAD_DIS 0x00002000 -#define AR5K_AR5211_TXCFG_RDY_DIS 0x00004000 - -/* - * Receive configuration register - */ -#define AR5K_AR5211_RXCFG 0x0034 -#define AR5K_AR5211_RXCFG_SDMAMW 0x00000007 -#define AR5K_AR5211_RXCFG_SDMAMW_S 0 -#define AR5K_AR5311_RXCFG_DEFAULT_ANTENNA 0x00000008 -#define AR5K_AR5211_RXCFG_ZLFDMA 0x00000010 -#define AR5K_AR5211_RXCFG_JUMBO_RXE 0x00000020 -#define AR5K_AR5211_RXCFG_JUMBO_WRAP 0x00000040 - -/* - * Receive jumbo descriptor last address register - */ -#define AR5K_AR5211_RXJLA 0x0038 - -/* - * MIB control register - */ -#define AR5K_AR5211_MIBC 0x0040 -#define AR5K_AR5211_MIBC_COW 0x00000001 -#define AR5K_AR5211_MIBC_FMC 0x00000002 -#define AR5K_AR5211_MIBC_CMC 0x00000004 -#define AR5K_AR5211_MIBC_MCS 0x00000008 - -/* - * Timeout prescale register - */ -#define AR5K_AR5211_TOPS 0x0044 -#define AR5K_AR5211_TOPS_M 0x0000ffff - -/* - * Receive timeout register (no frame received) - */ -#define AR5K_AR5211_RXNOFRM 0x0048 -#define AR5K_AR5211_RXNOFRM_M 0x000003ff - -/* - * Transmit timeout register (no frame sent) - */ -#define AR5K_AR5211_TXNOFRM 0x004c -#define AR5K_AR5211_TXNOFRM_M 0x000003ff -#define AR5K_AR5211_TXNOFRM_QCU 0x000ffc00 - -/* - * Receive frame gap timeout register - */ -#define AR5K_AR5211_RPGTO 0x0050 -#define AR5K_AR5211_RPGTO_M 0x000003ff - -/* - * Receive frame count limit register - */ -#define AR5K_AR5211_RFCNT 0x0054 -#define AR5K_AR5211_RFCNT_M 0x0000001f - -/* - * Misc settings register - */ -#define AR5K_AR5211_MISC 0x0058 -#define AR5K_AR5211_MISC_DMA_OBS_M 0x000001e0 -#define AR5K_AR5211_MISC_DMA_OBS_S 5 -#define AR5K_AR5211_MISC_MISC_OBS_M 0x00000e00 -#define AR5K_AR5211_MISC_MISC_OBS_S 9 -#define AR5K_AR5211_MISC_MAC_OBS_LSB_M 0x00007000 -#define AR5K_AR5211_MISC_MAC_OBS_LSB_S 12 -#define AR5K_AR5211_MISC_MAC_OBS_MSB_M 0x00038000 -#define AR5K_AR5211_MISC_MAC_OBS_MSB_S 15 - -/* - * QCU/DCU clock gating register - */ -#define AR5K_AR5311_QCUDCU_CLKGT -#define AR5K_AR5311_QCUDCU_CLKGT_QCU 0x0000ffff -#define AR5K_AR5311_QCUDCU_CLKGT_DCU 0x07ff0000 - -/* - * Primary interrupt status register - */ -#define AR5K_AR5211_PISR 0x0080 -#define AR5K_AR5211_PISR_RXOK 0x00000001 -#define AR5K_AR5211_PISR_RXDESC 0x00000002 -#define AR5K_AR5211_PISR_RXERR 0x00000004 -#define AR5K_AR5211_PISR_RXNOFRM 0x00000008 -#define AR5K_AR5211_PISR_RXEOL 0x00000010 -#define AR5K_AR5211_PISR_RXORN 0x00000020 -#define AR5K_AR5211_PISR_TXOK 0x00000040 -#define AR5K_AR5211_PISR_TXDESC 0x00000080 -#define AR5K_AR5211_PISR_TXERR 0x00000100 -#define AR5K_AR5211_PISR_TXNOFRM 0x00000200 -#define AR5K_AR5211_PISR_TXEOL 0x00000400 -#define AR5K_AR5211_PISR_TXURN 0x00000800 -#define AR5K_AR5211_PISR_MIB 0x00001000 -#define AR5K_AR5211_PISR_SWI 0x00002000 -#define AR5K_AR5211_PISR_RXPHY 0x00004000 -#define AR5K_AR5211_PISR_RXKCM 0x00008000 -#define AR5K_AR5211_PISR_SWBA 0x00010000 -#define AR5K_AR5211_PISR_BRSSI 0x00020000 -#define AR5K_AR5211_PISR_BMISS 0x00040000 -#define AR5K_AR5211_PISR_HIUERR 0x00080000 -#define AR5K_AR5211_PISR_BNR 0x00100000 -#define AR5K_AR5211_PISR_TIM 0x00800000 -#define AR5K_AR5211_PISR_GPIO 0x01000000 -#define AR5K_AR5211_PISR_QCBRORN 0x02000000 -#define AR5K_AR5211_PISR_QCBRURN 0x04000000 -#define AR5K_AR5211_PISR_QTRIG 0x08000000 - -/* - * Secondary interrupt status registers (0 - 4) - */ -#define AR5K_AR5211_SISR0 0x0084 -#define AR5K_AR5211_SISR0_QCU_TXOK 0x000003ff -#define AR5K_AR5211_SISR0_QCU_TXDESC 0x03ff0000 - -#define AR5K_AR5211_SISR1 0x0088 -#define AR5K_AR5211_SISR1_QCU_TXERR 0x000003ff -#define AR5K_AR5211_SISR1_QCU_TXEOL 0x03ff0000 - -#define AR5K_AR5211_SISR2 0x008c -#define AR5K_AR5211_SISR2_QCU_TXURN 0x000003ff -#define AR5K_AR5211_SISR2_MCABT 0x00100000 -#define AR5K_AR5211_SISR2_SSERR 0x00200000 -#define AR5K_AR5211_SISR2_DPERR 0x00400000 - -#define AR5K_AR5211_SISR3 0x0090 -#define AR5K_AR5211_SISR3_QCBRORN 0x000003ff -#define AR5K_AR5211_SISR3_QCBRURN 0x03ff0000 - -#define AR5K_AR5211_SISR4 0x0094 -#define AR5K_AR5211_SISR4_QTRIG 0x000003ff - -/* - * Shadow read-and-clear interrupt status registers - */ -#define AR5K_AR5211_RAC_PISR 0x00c0 -#define AR5K_AR5211_RAC_SISR0 0x00c4 -#define AR5K_AR5211_RAC_SISR1 0x00c8 -#define AR5K_AR5211_RAC_SISR2 0x00cc -#define AR5K_AR5211_RAC_SISR3 0c00d0 -#define AR5K_AR5211_RAC_SISR4 0c00d4 - -/* - * Primary interrupt mask register - */ -#define AR5K_AR5211_PIMR 0x00a0 -#define AR5K_AR5211_PIMR_RXOK 0x00000001 -#define AR5K_AR5211_PIMR_RXDESC 0x00000002 -#define AR5K_AR5211_PIMR_RXERR 0x00000004 -#define AR5K_AR5211_PIMR_RXNOFRM 0x00000008 -#define AR5K_AR5211_PIMR_RXEOL 0x00000010 -#define AR5K_AR5211_PIMR_RXORN 0x00000020 -#define AR5K_AR5211_PIMR_TXOK 0x00000040 -#define AR5K_AR5211_PIMR_TXDESC 0x00000080 -#define AR5K_AR5211_PIMR_TXERR 0x00000100 -#define AR5K_AR5211_PIMR_TXNOFRM 0x00000200 -#define AR5K_AR5211_PIMR_TXEOL 0x00000400 -#define AR5K_AR5211_PIMR_TXURN 0x00000800 -#define AR5K_AR5211_PIMR_MIB 0x00001000 -#define AR5K_AR5211_PIMR_SWI 0x00002000 -#define AR5K_AR5211_PIMR_RXPHY 0x00004000 -#define AR5K_AR5211_PIMR_RXKCM 0x00008000 -#define AR5K_AR5211_PIMR_SWBA 0x00010000 -#define AR5K_AR5211_PIMR_BRSSI 0x00020000 -#define AR5K_AR5211_PIMR_BMISS 0x00040000 -#define AR5K_AR5211_PIMR_HIUERR 0x00080000 -#define AR5K_AR5211_PIMR_BNR 0x00100000 -#define AR5K_AR5211_PIMR_TIM 0x00800000 -#define AR5K_AR5211_PIMR_GPIO 0x01000000 -#define AR5K_AR5211_PIMR_QCBRORN 0x02000000 -#define AR5K_AR5211_PIMR_QCBRURN 0x04000000 -#define AR5K_AR5211_PIMR_QTRIG 0x08000000 - -/* - * Secondary interrupt mask registers (0 - 4) - */ -#define AR5K_AR5211_SIMR0 0x00a4 -#define AR5K_AR5211_SIMR0_QCU_TXOK 0x000003ff -#define AR5K_AR5211_SIMR0_QCU_TXOK_S 0 -#define AR5K_AR5211_SIMR0_QCU_TXDESC 0x03ff0000 -#define AR5K_AR5211_SIMR0_QCU_TXDESC_S 16 - -#define AR5K_AR5211_SIMR1 0x00a8 -#define AR5K_AR5211_SIMR1_QCU_TXERR 0x000003ff -#define AR5K_AR5211_SIMR1_QCU_TXERR_S 0 -#define AR5K_AR5211_SIMR1_QCU_TXEOL 0x03ff0000 -#define AR5K_AR5211_SIMR1_QCU_TXEOL_S 16 - -#define AR5K_AR5211_SIMR2 0x00ac -#define AR5K_AR5211_SIMR2_QCU_TXURN 0x000003ff -#define AR5K_AR5211_SIMR2_QCU_TXURN_S 0 -#define AR5K_AR5211_SIMR2_MCABT 0x00100000 -#define AR5K_AR5211_SIMR2_SSERR 0x00200000 -#define AR5K_AR5211_SIMR2_DPERR 0x00400000 - -#define AR5K_AR5211_SIMR3 0x00b0 -#define AR5K_AR5211_SIMR3_QCBRORN 0x000003ff -#define AR5K_AR5211_SIMR3_QCBRORN_S 0 -#define AR5K_AR5211_SIMR3_QCBRURN 0x03ff0000 -#define AR5K_AR5211_SIMR3_QCBRURN_S 16 - -#define AR5K_AR5211_SIMR4 0x00b4 -#define AR5K_AR5211_SIMR4_QTRIG 0x000003ff -#define AR5K_AR5211_SIMR4_QTRIG_S 0 - -/* - * Queue control unit (QCU) registers (0 - 9) - */ -#define AR5K_AR5211_QCU(_n, _a) (((_n) << 2) + _a) - -/* - * QCU Transmit descriptor pointer registers - */ -#define AR5K_AR5211_QCU_TXDP(_n) AR5K_AR5211_QCU(_n, 0x0800) - -/* - * QCU Transmit enable register - */ -#define AR5K_AR5211_QCU_TXE 0x0840 - -/* - * QCU Transmit disable register - */ -#define AR5K_AR5211_QCU_TXD 0x0880 - -/* - * QCU CBR configuration registers - */ -#define AR5K_AR5211_QCU_CBRCFG(_n) AR5K_AR5211_QCU(_n, 0x08c0) -#define AR5K_AR5211_QCU_CBRCFG_INTVAL 0x00ffffff -#define AR5K_AR5211_QCU_CBRCFG_INTVAL_S 0 -#define AR5K_AR5211_QCU_CBRCFG_ORN_THRES 0xff000000 -#define AR5K_AR5211_QCU_CBRCFG_ORN_THRES_S 24 - -/* - * QCU Ready time configuration registers - */ -#define AR5K_AR5211_QCU_RDYTIMECFG(_n) AR5K_AR5211_QCU(_n, 0x0900) -#define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL 0x00ffffff -#define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL_S 0 -#define AR5K_AR5211_QCU_RDYTIMECFG_DURATION 0x00ffffff -#define AR5K_AR5211_QCU_RDYTIMECFG_ENABLE 0x01000000 - -/* - * QCU one shot arm set registers - */ -#define AR5K_AR5211_QCU_ONESHOTARMS(_n) AR5K_AR5211_QCU(_n, 0x0940) -#define AR5K_AR5211_QCU_ONESHOTARMS_M 0x0000ffff - -/* - * QCU one shot arm clear registers - */ -#define AR5K_AR5211_QCU_ONESHOTARMC(_n) AR5K_AR5211_QCU(_n, 0x0980) -#define AR5K_AR5211_QCU_ONESHOTARMC_M 0x0000ffff - -/* - * QCU misc registers - */ -#define AR5K_AR5211_QCU_MISC(_n) AR5K_AR5211_QCU(_n, 0x09c0) -#define AR5K_AR5211_QCU_MISC_FRSHED_M 0x0000000f -#define AR5K_AR5211_QCU_MISC_FRSHED_ASAP 0 -#define AR5K_AR5211_QCU_MISC_FRSHED_CBR 1 -#define AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT 2 -#define AR5K_AR5211_QCU_MISC_FRSHED_TIM_GT 3 -#define AR5K_AR5211_QCU_MISC_FRSHED_BCN_SENT_GT 4 -#define AR5K_AR5211_QCU_MISC_ONESHOT_ENABLE 0x00000010 -#define AR5K_AR5211_QCU_MISC_CBREXP 0x00000020 -#define AR5K_AR5211_QCU_MISC_CBREXP_BCN 0x00000040 -#define AR5K_AR5211_QCU_MISC_BCN_ENABLE 0x00000080 -#define AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE 0x00000100 -#define AR5K_AR5211_QCU_MISC_TXE 0x00000200 -#define AR5K_AR5211_QCU_MISC_CBR 0x00000400 -#define AR5K_AR5211_QCU_MISC_DCU_EARLY 0x00000800 - -/* - * QCU status registers - */ -#define AR5K_AR5211_QCU_STS(_n) AR5K_AR5211_QCU(_n, 0x0a00) -#define AR5K_AR5211_QCU_STS_FRMPENDCNT 0x00000003 -#define AR5K_AR5211_QCU_STS_CBREXPCNT 0x0000ff00 - -/* - * QCU ready time shutdown register - */ -#define AR5K_AR5211_QCU_RDYTIMESHDN 0x0a40 -#define AR5K_AR5211_QCU_RDYTIMESHDN_M 0x000003ff - -/* - * DCF control unit (DCU) registers (0 - 9) - */ -#define AR5K_AR5211_DCU(_n, _a) AR5K_AR5211_QCU(_n, _a) - -/* - * DCU QCU mask registers - */ -#define AR5K_AR5211_DCU_QCUMASK(_n) AR5K_AR5211_DCU(_n, 0x1000) -#define AR5K_AR5211_DCU_QCUMASK_M 0x000003ff - -/* - * DCU local IFS settings register - */ -#define AR5K_AR5211_DCU_LCL_IFS(_n) AR5K_AR5211_DCU(_n, 0x1040) -#define AR5K_AR5211_DCU_LCL_IFS_CW_MIN 0x000003ff -#define AR5K_AR5211_DCU_LCL_IFS_CW_MIN_S 0 -#define AR5K_AR5211_DCU_LCL_IFS_CW_MAX 0x000ffc00 -#define AR5K_AR5211_DCU_LCL_IFS_CW_MAX_S 10 -#define AR5K_AR5211_DCU_LCL_IFS_AIFS 0x0ff00000 -#define AR5K_AR5211_DCU_LCL_IFS_AIFS_S 20 - -/* - * DCU retry limit registers - */ -#define AR5K_AR5211_DCU_RETRY_LMT(_n) AR5K_AR5211_DCU(_n, 0x1080) -#define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY 0x0000000f -#define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY 0x000000f0 -#define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 -#define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 -#define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY_S 14 - -/* - * DCU channel time registers - */ -#define AR5K_AR5211_DCU_CHAN_TIME(_n) AR5K_AR5211_DCU(_n, 0x10c0) -#define AR5K_AR5211_DCU_CHAN_TIME_ENABLE 0x00100000 -#define AR5K_AR5211_DCU_CHAN_TIME_DUR 0x000fffff -#define AR5K_AR5211_DCU_CHAN_TIME_DUR_S 0 - -/* - * DCU misc registers - */ -#define AR5K_AR5211_DCU_MISC(_n) AR5K_AR5211_DCU(_n, 0x1100) -#define AR5K_AR5211_DCU_MISC_BACKOFF 0x000007ff -#define AR5K_AR5211_DCU_MISC_BACKOFF_FRAG 0x00000200 -#define AR5K_AR5211_DCU_MISC_HCFPOLL_ENABLE 0x00000800 -#define AR5K_AR5211_DCU_MISC_BACKOFF_PERSIST 0x00001000 -#define AR5K_AR5211_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 -#define AR5K_AR5211_DCU_MISC_VIRTCOL 0x0000c000 -#define AR5K_AR5211_DCU_MISC_VIRTCOL_NORMAL 0 -#define AR5K_AR5211_DCU_MISC_VIRTCOL_MODIFIED 1 -#define AR5K_AR5211_DCU_MISC_VIRTCOL_IGNORE 2 -#define AR5K_AR5211_DCU_MISC_BCN_ENABLE 0x00010000 -#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL 0x00060000 -#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_S 17 -#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_NONE 0 -#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_INTFRM 1 -#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 -#define AR5K_AR5211_DCU_MISC_ARBLOCK_IGNORE 0x00080000 -#define AR5K_AR5211_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 -#define AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 -#define AR5K_AR5211_DCU_MISC_VIRT_COLL_POLICY 0x00400000 -#define AR5K_AR5211_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 -#define AR5K_AR5211_DCU_MISC_SEQNUM_CTL 0x01000000 - -/* - * DCU frame sequence number registers - */ -#define AR5K_AR5211_DCU_SEQNUM(_n) AR5K_AR5211_DCU(_n, 0x1140) -#define AR5K_AR5211_DCU_SEQNUM_M 0x00000fff -/* - * DCU global IFS SIFS registers - */ -#define AR5K_AR5211_DCU_GBL_IFS_SIFS 0x1030 -#define AR5K_AR5211_DCU_GBL_IFS_SIFS_M 0x0000ffff - -/* - * DCU global IFS slot interval registers - */ -#define AR5K_AR5211_DCU_GBL_IFS_SLOT 0x1070 -#define AR5K_AR5211_DCU_GBL_IFS_SLOT_M 0x0000ffff - -/* - * DCU global IFS EIFS registers - */ -#define AR5K_AR5211_DCU_GBL_IFS_EIFS 0x10b0 -#define AR5K_AR5211_DCU_GBL_IFS_EIFS_M 0x0000ffff - -/* - * DCU global IFS misc registers - */ -#define AR5K_AR5211_DCU_GBL_IFS_MISC 0x10f0 -#define AR5K_AR5211_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 -#define AR5K_AR5211_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 -#define AR5K_AR5211_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 -#define AR5K_AR5211_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 -#define AR5K_AR5211_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 - -/* - * DCU frame prefetch control register - */ -#define AR5K_AR5211_DCU_FP 0x1230 - -/* - * DCU transmit pause control/status register - */ -#define AR5K_AR5211_DCU_TXP 0x1270 -#define AR5K_AR5211_DCU_TXP_M 0x000003ff -#define AR5K_AR5211_DCU_TXP_STATUS 0x00010000 - -/* - * DCU transmit filter register - */ -#define AR5K_AR5211_DCU_TX_FILTER 0x1038 - -/* - * DCU clear transmit filter register - */ -#define AR5K_AR5211_DCU_TX_FILTER_CLR 0x143c - -/* - * DCU set transmit filter register - */ -#define AR5K_AR5211_DCU_TX_FILTER_SET 0x147c - -/* - * DMA size definitions - */ -typedef enum { - AR5K_AR5211_DMASIZE_4B = 0, - AR5K_AR5211_DMASIZE_8B = 1, - AR5K_AR5211_DMASIZE_16B = 2, - AR5K_AR5211_DMASIZE_32B = 3, - AR5K_AR5211_DMASIZE_64B = 4, - AR5K_AR5211_DMASIZE_128B = 5, - AR5K_AR5211_DMASIZE_256B = 6, - AR5K_AR5211_DMASIZE_512B = 7 -} ar5k_ar5211_dmasize_t; - -/* - * Reset control register - */ -#define AR5K_AR5211_RC 0x4000 -#define AR5K_AR5211_RC_PCU 0x00000001 -#define AR5K_AR5211_RC_BB 0x00000002 -#define AR5K_AR5211_RC_PCI 0x00000010 -#define AR5K_AR5211_RC_CHIP ( \ - AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB | AR5K_AR5211_RC_PCI \ -) - -/* - * Sleep control register - */ -#define AR5K_AR5211_SCR 0x4004 -#define AR5K_AR5211_SCR_SLDUR 0x0000ffff -#define AR5K_AR5211_SCR_SLDUR_S 0 -#define AR5K_AR5211_SCR_SLE 0x00030000 -#define AR5K_AR5211_SCR_SLE_S 16 -#define AR5K_AR5211_SCR_SLE_WAKE 0x00000000 -#define AR5K_AR5211_SCR_SLE_SLP 0x00010000 -#define AR5K_AR5211_SCR_SLE_ALLOW 0x00020000 -#define AR5K_AR5211_SCR_SLE_UNITS 0x00000008 - -/* - * Interrupt pending register - */ -#define AR5K_AR5211_INTPEND 0x4008 -#define AR5K_AR5211_INTPEND_M 0x00000001 - -/* - * Sleep force register - */ -#define AR5K_AR5211_SFR 0x400c -#define AR5K_AR5211_SFR_M 0x00000001 - -/* - * PCI configuration register - */ -#define AR5K_AR5211_PCICFG 0x4010 -#define AR5K_AR5211_PCICFG_CLKRUNEN 0x00000004 -#define AR5K_AR5211_PCICFG_EESIZE 0x00000018 -#define AR5K_AR5211_PCICFG_EESIZE_S 3 -#define AR5K_AR5211_PCICFG_EESIZE_4K 0 -#define AR5K_AR5211_PCICFG_EESIZE_8K 1 -#define AR5K_AR5211_PCICFG_EESIZE_16K 2 -#define AR5K_AR5211_PCICFG_EESIZE_FAIL 3 -#define AR5K_AR5211_PCICFG_LED 0x00000060 -#define AR5K_AR5211_PCICFG_LED_NONE 0x00000000 -#define AR5K_AR5211_PCICFG_LED_PEND 0x00000020 -#define AR5K_AR5211_PCICFG_LED_ASSOC 0x00000040 -#define AR5K_AR5211_PCICFG_BUS_SEL 0x00000380 -#define AR5K_AR5211_PCICFG_CBEFIX_DIS 0x00000400 -#define AR5K_AR5211_PCICFG_SL_INTEN 0x00000800 -#define AR5K_AR5211_PCICFG_SL_INPEN 0x00002800 -#define AR5K_AR5211_PCICFG_SPWR_DN 0x00010000 -#define AR5K_AR5211_PCICFG_LEDMODE 0x000e0000 -#define AR5K_AR5211_PCICFG_LEDMODE_PROP 0x00000000 -#define AR5K_AR5211_PCICFG_LEDMODE_PROM 0x00020000 -#define AR5K_AR5211_PCICFG_LEDMODE_PWR 0x00040000 -#define AR5K_AR5211_PCICFG_LEDMODE_RAND 0x00060000 -#define AR5K_AR5211_PCICFG_LEDBLINK 0x00700000 -#define AR5K_AR5211_PCICFG_LEDBLINK_S 20 -#define AR5K_AR5211_PCICFG_LEDSLOW 0x00800000 -#define AR5K_AR5211_PCICFG_LEDSTATE \ - (AR5K_AR5211_PCICFG_LED | AR5K_AR5211_PCICFG_LEDMODE | \ - AR5K_AR5211_PCICFG_LEDBLINK | AR5K_AR5211_PCICFG_LEDSLOW) - -/* - * "General Purpose Input/Output" (GPIO) control register - */ -#define AR5K_AR5211_GPIOCR 0x4014 -#define AR5K_AR5211_GPIOCR_INT_ENA 0x00008000 -#define AR5K_AR5211_GPIOCR_INT_SELL 0x00000000 -#define AR5K_AR5211_GPIOCR_INT_SELH 0x00010000 -#define AR5K_AR5211_GPIOCR_NONE(n) (0 << ((n) * 2)) -#define AR5K_AR5211_GPIOCR_OUT0(n) (1 << ((n) * 2)) -#define AR5K_AR5211_GPIOCR_OUT1(n) (2 << ((n) * 2)) -#define AR5K_AR5211_GPIOCR_ALL(n) (3 << ((n) * 2)) -#define AR5K_AR5211_GPIOCR_INT_SEL(n) ((n) << 12) - -#define AR5K_AR5211_NUM_GPIO 6 - -/* - * "General Purpose Input/Output" (GPIO) data output register - */ -#define AR5K_AR5211_GPIODO 0x4018 - -/* - * "General Purpose Input/Output" (GPIO) data input register - */ -#define AR5K_AR5211_GPIODI 0x401c -#define AR5K_AR5211_GPIODI_M 0x0000002f - -/* - * Silicon revision register - */ -#define AR5K_AR5211_SREV 0x4020 -#define AR5K_AR5211_SREV_REV 0x0000000f -#define AR5K_AR5211_SREV_REV_S 0 -#define AR5K_AR5211_SREV_VER 0x000000ff -#define AR5K_AR5211_SREV_VER_S 4 - -/* - * EEPROM access registers - */ -#define AR5K_AR5211_EEPROM_BASE 0x6000 -#define AR5K_AR5211_EEPROM_DATA 0x6004 -#define AR5K_AR5211_EEPROM_CMD 0x6008 -#define AR5K_AR5211_EEPROM_CMD_READ 0x00000001 -#define AR5K_AR5211_EEPROM_CMD_WRITE 0x00000002 -#define AR5K_AR5211_EEPROM_CMD_RESET 0x00000004 -#define AR5K_AR5211_EEPROM_STATUS 0x600c -#define AR5K_AR5211_EEPROM_STAT_RDERR 0x00000001 -#define AR5K_AR5211_EEPROM_STAT_RDDONE 0x00000002 -#define AR5K_AR5211_EEPROM_STAT_WRERR 0x00000004 -#define AR5K_AR5211_EEPROM_STAT_WRDONE 0x00000008 -#define AR5K_AR5211_EEPROM_CFG 0x6010 - -/* - * AR5211 EEPROM data registers - */ -#define AR5K_AR5211_EEPROM_MAGIC 0x3d -#define AR5K_AR5211_EEPROM_MAGIC_VALUE 0x5aa5 -#define AR5K_AR5211_EEPROM_PROTECT 0x3f -#define AR5K_AR5211_EEPROM_PROTECT_128_191 0x80 -#define AR5K_AR5211_EEPROM_REG_DOMAIN 0xbf -#define AR5K_AR5211_EEPROM_INFO_BASE 0xc0 -#define AR5K_AR5211_EEPROM_INFO_VERSION \ - (AR5K_AR5211_EEPROM_INFO_BASE + 1) -#define AR5K_AR5211_EEPROM_INFO_MAX \ - (0x400 - AR5K_AR5211_EEPROM_INFO_BASE) - -/* - * PCU registers - */ - -#define AR5K_AR5211_PCU_MIN 0x8000 -#define AR5K_AR5211_PCU_MAX 0x8fff - -/* - * First station id register (MAC address in lower 32 bits) - */ -#define AR5K_AR5211_STA_ID0 0x8000 - -/* - * Second station id register (MAC address in upper 16 bits) - */ -#define AR5K_AR5211_STA_ID1 0x8004 -#define AR5K_AR5211_STA_ID1_AP 0x00010000 -#define AR5K_AR5211_STA_ID1_ADHOC 0x00020000 -#define AR5K_AR5211_STA_ID1_PWR_SV 0x00040000 -#define AR5K_AR5211_STA_ID1_NO_KEYSRCH 0x00080000 -#define AR5K_AR5211_STA_ID1_PCF 0x00100000 -#define AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA 0x00200000 -#define AR5K_AR5211_STA_ID1_DESC_ANTENNA 0x00400000 -#define AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000 -#define AR5K_AR5211_STA_ID1_ACKCTS_6MB 0x01000000 -#define AR5K_AR5211_STA_ID1_BASE_RATE_11B 0x02000000 - -/* - * First BSSID register (MAC address, lower 32bits) - */ -#define AR5K_AR5211_BSS_ID0 0x8008 - -/* - * Second BSSID register (MAC address in upper 16 bits) - * - * AID: Association ID - */ -#define AR5K_AR5211_BSS_ID1 0x800c -#define AR5K_AR5211_BSS_ID1_AID 0xffff0000 -#define AR5K_AR5211_BSS_ID1_AID_S 16 - -/* - * Backoff slot time register - */ -#define AR5K_AR5211_SLOT_TIME 0x8010 - -/* - * ACK/CTS timeout register - */ -#define AR5K_AR5211_TIME_OUT 0x8014 -#define AR5K_AR5211_TIME_OUT_ACK 0x00001fff -#define AR5K_AR5211_TIME_OUT_ACK_S 0 -#define AR5K_AR5211_TIME_OUT_CTS 0x1fff0000 -#define AR5K_AR5211_TIME_OUT_CTS_S 16 - -/* - * RSSI threshold register - */ -#define AR5K_AR5211_RSSI_THR 0x8018 -#define AR5K_AR5211_RSSI_THR_M 0x000000ff -#define AR5K_AR5211_RSSI_THR_BMISS 0x0000ff00 -#define AR5K_AR5211_RSSI_THR_BMISS_S 8 - -/* - * Transmit latency register - */ -#define AR5K_AR5211_USEC 0x801c -#define AR5K_AR5211_USEC_1 0x0000007f -#define AR5K_AR5211_USEC_1_S 0 -#define AR5K_AR5211_USEC_32 0x00003f80 -#define AR5K_AR5211_USEC_32_S 7 -#define AR5K_AR5211_USEC_TX_LATENCY 0x007fc000 -#define AR5K_AR5211_USEC_TX_LATENCY_S 14 -#define AR5K_AR5211_USEC_RX_LATENCY 0x1f800000 -#define AR5K_AR5211_USEC_RX_LATENCY_S 23 -#define AR5K_AR5311_USEC_TX_LATENCY 0x000fc000 -#define AR5K_AR5311_USEC_TX_LATENCY_S 14 -#define AR5K_AR5311_USEC_RX_LATENCY 0x03f00000 -#define AR5K_AR5311_USEC_RX_LATENCY_S 20 - -/* - * PCU beacon control register - */ -#define AR5K_AR5211_BEACON 0x8020 -#define AR5K_AR5211_BEACON_PERIOD 0x0000ffff -#define AR5K_AR5211_BEACON_PERIOD_S 0 -#define AR5K_AR5211_BEACON_TIM 0x007f0000 -#define AR5K_AR5211_BEACON_TIM_S 16 -#define AR5K_AR5211_BEACON_ENABLE 0x00800000 -#define AR5K_AR5211_BEACON_RESET_TSF 0x01000000 - -/* - * CFP period register - */ -#define AR5K_AR5211_CFP_PERIOD 0x8024 - -/* - * Next beacon time register - */ -#define AR5K_AR5211_TIMER0 0x8028 - -/* - * Next DMA beacon alert register - */ -#define AR5K_AR5211_TIMER1 0x802c - -/* - * Next software beacon alert register - */ -#define AR5K_AR5211_TIMER2 0x8030 - -/* - * Next ATIM window time register - */ -#define AR5K_AR5211_TIMER3 0x8034 - -/* - * CFP duration register - */ -#define AR5K_AR5211_CFP_DUR 0x8038 - -/* - * Receive filter register - */ -#define AR5K_AR5211_RX_FILTER 0x803c -#define AR5K_AR5211_RX_FILTER_UNICAST 0x00000001 -#define AR5K_AR5211_RX_FILTER_MULTICAST 0x00000002 -#define AR5K_AR5211_RX_FILTER_BROADCAST 0x00000004 -#define AR5K_AR5211_RX_FILTER_CONTROL 0x00000008 -#define AR5K_AR5211_RX_FILTER_BEACON 0x00000010 -#define AR5K_AR5211_RX_FILTER_PROMISC 0x00000020 -#define AR5K_AR5211_RX_FILTER_PHYERR 0x00000040 -#define AR5K_AR5211_RX_FILTER_RADARERR 0x00000080 - -/* - * Multicast filter register (lower 32 bits) - */ -#define AR5K_AR5211_MCAST_FIL0 0x8040 - -/* - * Multicast filter register (higher 16 bits) - */ -#define AR5K_AR5211_MCAST_FIL1 0x8044 - -/* - * PCU control register - */ -#define AR5K_AR5211_DIAG_SW 0x8048 -#define AR5K_AR5211_DIAG_SW_DIS_WEP_ACK 0x00000001 -#define AR5K_AR5211_DIAG_SW_DIS_ACK 0x00000002 -#define AR5K_AR5211_DIAG_SW_DIS_CTS 0x00000004 -#define AR5K_AR5211_DIAG_SW_DIS_ENC 0x00000008 -#define AR5K_AR5211_DIAG_SW_DIS_DEC 0x00000010 -#define AR5K_AR5211_DIAG_SW_DIS_RX 0x00000020 -#define AR5K_AR5211_DIAG_SW_LOOP_BACK 0x00000040 -#define AR5K_AR5211_DIAG_SW_CORR_FCS 0x00000080 -#define AR5K_AR5211_DIAG_SW_CHAN_INFO 0x00000100 -#define AR5K_AR5211_DIAG_SW_EN_SCRAM_SEED 0x00000200 -#define AR5K_AR5211_DIAG_SW_ECO_ENABLE 0x00000400 -#define AR5K_AR5211_DIAG_SW_SCRAM_SEED_M 0x0001fc00 -#define AR5K_AR5211_DIAG_SW_SCRAM_SEED_S 10 -#define AR5K_AR5211_DIAG_SW_FRAME_NV0 0x00020000 -#define AR5K_AR5211_DIAG_SW_OBSPT_M 0x000c0000 -#define AR5K_AR5211_DIAG_SW_OBSPT_S 18 - -/* - * TSF (clock) register (lower 32 bits) - */ -#define AR5K_AR5211_TSF_L32 0x804c - -/* - * TSF (clock) register (higher 32 bits) - */ -#define AR5K_AR5211_TSF_U32 0x8050 - -/* - * ADDAC test register - */ -#define AR5K_AR5211_ADDAC_TEST 0x8054 - -/* - * Default antenna register - */ -#define AR5K_AR5211_DEFAULT_ANTENNA 0x8058 - -/* - * Last beacon timestamp register - */ -#define AR5K_AR5211_LAST_TSTP 0x8080 - -/* - * NAV register (current) - */ -#define AR5K_AR5211_NAV 0x8084 - -/* - * RTS success register - */ -#define AR5K_AR5211_RTS_OK 0x8088 - -/* - * RTS failure register - */ -#define AR5K_AR5211_RTS_FAIL 0x808c - -/* - * ACK failure register - */ -#define AR5K_AR5211_ACK_FAIL 0x8090 - -/* - * FCS failure register - */ -#define AR5K_AR5211_FCS_FAIL 0x8094 - -/* - * Beacon count register - */ -#define AR5K_AR5211_BEACON_CNT 0x8098 - -/* - * Key table (WEP) register - */ -#define AR5K_AR5211_KEYTABLE_0 0x8800 -#define AR5K_AR5211_KEYTABLE(n) (AR5K_AR5211_KEYTABLE_0 + ((n) * 32)) -#define AR5K_AR5211_KEYTABLE_OFF(_n, x) (AR5K_AR5211_KEYTABLE(_n) + (x << 2)) -#define AR5K_AR5211_KEYTABLE_TYPE(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 5) -#define AR5K_AR5211_KEYTABLE_TYPE_40 0x00000000 -#define AR5K_AR5211_KEYTABLE_TYPE_104 0x00000001 -#define AR5K_AR5211_KEYTABLE_TYPE_128 0x00000003 -#define AR5K_AR5211_KEYTABLE_TYPE_AES 0x00000005 -#define AR5K_AR5211_KEYTABLE_TYPE_NULL 0x00000007 -#define AR5K_AR5211_KEYTABLE_MAC0(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 6) -#define AR5K_AR5211_KEYTABLE_MAC1(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 7) -#define AR5K_AR5211_KEYTABLE_VALID 0x00008000 - -#define AR5K_AR5211_KEYTABLE_SIZE 128 -#define AR5K_AR5211_KEYCACHE_SIZE 8 - -/* - * PHY register - */ -#define AR5K_AR5211_PHY(_n) (0x9800 + ((_n) << 2)) -#define AR5K_AR5211_PHY_SHIFT_2GHZ 0x00004007 -#define AR5K_AR5211_PHY_SHIFT_5GHZ 0x00000007 - -/* - * PHY turbo mode register - */ -#define AR5K_AR5211_PHY_TURBO 0x9804 -#define AR5K_AR5211_PHY_TURBO_MODE 0x00000001 -#define AR5K_AR5211_PHY_TURBO_SHORT 0x00000002 - -/* - * PHY agility command register - */ -#define AR5K_AR5211_PHY_AGC 0x9808 -#define AR5K_AR5211_PHY_AGC_DISABLE 0x08000000 - -/* - * PHY chip revision register - */ -#define AR5K_AR5211_PHY_CHIP_ID 0x9818 - -/* - * PHY activation register - */ -#define AR5K_AR5211_PHY_ACTIVE 0x981c -#define AR5K_AR5211_PHY_ENABLE 0x00000001 -#define AR5K_AR5211_PHY_DISABLE 0x00000002 - -/* - * PHY agility control register - */ -#define AR5K_AR5211_PHY_AGCCTL 0x9860 -#define AR5K_AR5211_PHY_AGCCTL_CAL 0x00000001 -#define AR5K_AR5211_PHY_AGCCTL_NF 0x00000002 - -/* - * PHY noise floor status register - */ -#define AR5K_AR5211_PHY_NF 0x9864 -#define AR5K_AR5211_PHY_NF_M 0x000001ff -#define AR5K_AR5211_PHY_NF_ACTIVE 0x00000100 -#define AR5K_AR5211_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5211_PHY_NF_M) -#define AR5K_AR5211_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5211_PHY_NF_M) + 1) -#define AR5K_AR5211_PHY_NF_SVAL(_n) (((_n) & AR5K_AR5211_PHY_NF_M) | (1 << 9)) - -/* - * PHY PLL control register - */ -#define AR5K_AR5211_PHY_PLL 0x987c -#define AR5K_AR5211_PHY_PLL_20MHZ 0x13 -#define AR5K_AR5211_PHY_PLL_40MHZ 0x18 -#define AR5K_AR5211_PHY_PLL_44MHZ 0x19 - -/* - * PHY receiver delay register - */ -#define AR5K_AR5211_PHY_RX_DELAY 0x9914 -#define AR5K_AR5211_PHY_RX_DELAY_M 0x00003fff - -/* - * PHY timing IQ control register - */ -#define AR5K_AR5211_PHY_IQ 0x9920 -#define AR5K_AR5211_PHY_IQ_CORR_Q_Q_COFF 0x0000001f -#define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF 0x000007e0 -#define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S 5 -#define AR5K_AR5211_PHY_IQ_CORR_ENABLE 0x00000800 -#define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 -#define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX_S 12 -#define AR5K_AR5211_PHY_IQ_RUN 0x00010000 - -/* - * PHY PAPD probe register - */ -#define AR5K_AR5211_PHY_PAPD_PROBE 0x9930 -#define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR 0x00007e00 -#define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR_S 9 -#define AR5K_AR5211_PHY_PAPD_PROBE_TX_NEXT 0x00008000 -#define AR5K_AR5211_PHY_PAPD_PROBE_GAINF 0xfe000000 -#define AR5K_AR5211_PHY_PAPD_PROBE_GAINF_S 25 - -/* - * PHY frame control register - */ -#define AR5K_AR5211_PHY_FC 0x9944 -#define AR5K_AR5211_PHY_FC_TX_CLIP 0x00000038 -#define AR5K_AR5211_PHY_FC_TX_CLIP_S 3 - -/* - * PHY radar detection enable register - */ -#define AR5K_AR5211_PHY_RADAR 0x9954 -#define AR5K_AR5211_PHY_RADAR_DISABLE 0x00000000 -#define AR5K_AR5211_PHY_RADAR_ENABLE 0x00000001 - -/* - * PHY antenna switch table registers - */ -#define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0 0x9960 -#define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1 0x9964 - -/* - * PHY timing IQ calibration result register - */ -#define AR5K_AR5211_PHY_IQRES_CAL_PWR_I 0x9c10 -#define AR5K_AR5211_PHY_IQRES_CAL_PWR_Q 0x9c14 -#define AR5K_AR5211_PHY_IQRES_CAL_CORR 0x9c18 - -/* - * PHY current RSSI register - */ -#define AR5K_AR5211_PHY_CURRENT_RSSI 0x9c1c - -/* - * PHY mode register - */ -#define AR5K_AR5211_PHY_MODE 0xa200 -#define AR5K_AR5211_PHY_MODE_MOD 0x00000001 -#define AR5K_AR5211_PHY_MODE_MOD_OFDM 0 -#define AR5K_AR5211_PHY_MODE_MOD_CCK 1 -#define AR5K_AR5211_PHY_MODE_FREQ 0x00000002 -#define AR5K_AR5211_PHY_MODE_FREQ_5GHZ 0 -#define AR5K_AR5211_PHY_MODE_FREQ_2GHZ 2 - -/* - * Misc PHY/radio registers - */ -#define AR5K_AR5211_BB_GAIN(_n) (0x9b00 + ((_n) << 2)) -#define AR5K_AR5211_RF_GAIN(_n) (0x9a00 + ((_n) << 2)) - -#endif Index: ar5212reg.h =================================================================== --- ar5212reg.h (revision 2185) +++ ar5212reg.h (revision 2232) @@ -1,1233 +0,0 @@ -/* $OpenBSD: ar5212reg.h,v 1.7 2005/12/18 17:59:58 reyk Exp $ */ - -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Known registers of the Atheros AR5001 Wireless LAN chipsets - * (AR5212/AR5311). - */ - -#ifndef _AR5K_AR5212_REG_H -#define _AR5K_AR5212_REG_H - -/* - * Command register - */ -#define AR5K_AR5212_CR 0x0008 -#define AR5K_AR5212_CR_RXE 0x00000004 -#define AR5K_AR5212_CR_RXD 0x00000020 -#define AR5K_AR5212_CR_SWI 0x00000040 - -/* - * Receive queue descriptor pointer register - */ -#define AR5K_AR5212_RXDP 0x000c - -/* - * Configuration and status register - */ -#define AR5K_AR5212_CFG 0x0014 -#define AR5K_AR5212_CFG_SWTD 0x00000001 -#define AR5K_AR5212_CFG_SWTB 0x00000002 -#define AR5K_AR5212_CFG_SWRD 0x00000004 -#define AR5K_AR5212_CFG_SWRB 0x00000008 -#define AR5K_AR5212_CFG_SWRG 0x00000010 -#define AR5K_AR5212_CFG_ADHOC 0x00000020 -#define AR5K_AR5212_CFG_PHY_OK 0x00000100 -#define AR5K_AR5212_CFG_EEBS 0x00000200 -#define AR5K_AR5212_CFG_CLKGD 0x00000400 -#define AR5K_AR5212_CFG_PCI_THRES 0x00060000 -#define AR5K_AR5212_CFG_PCI_THRES_S 17 - -/* - * Interrupt enable register - */ -#define AR5K_AR5212_IER 0x0024 -#define AR5K_AR5212_IER_DISABLE 0x00000000 -#define AR5K_AR5212_IER_ENABLE 0x00000001 - -/* - * Transmit configuration register - */ -#define AR5K_AR5212_TXCFG 0x0030 -#define AR5K_AR5212_TXCFG_SDMAMR 0x00000007 -#define AR5K_AR5212_TXCFG_SDMAMR_S 0 -#define AR5K_AR5212_TXCFG_B_MODE 0x00000008 -#define AR5K_AR5212_TXCFG_TXFULL 0x000003f0 -#define AR5K_AR5212_TXCFG_TXFULL_S 4 -#define AR5K_AR5212_TXCFG_TXFULL_0B 0x00000000 -#define AR5K_AR5212_TXCFG_TXFULL_64B 0x00000010 -#define AR5K_AR5212_TXCFG_TXFULL_128B 0x00000020 -#define AR5K_AR5212_TXCFG_TXFULL_192B 0x00000030 -#define AR5K_AR5212_TXCFG_TXFULL_256B 0x00000040 -#define AR5K_AR5212_TXCFG_TXCONT_ENABLE 0x00000080 -#define AR5K_AR5212_TXCFG_DMASIZE 0x00000100 -#define AR5K_AR5212_TXCFG_JUMBO_TXE 0x00000400 -#define AR5K_AR5212_TXCFG_RTSRND 0x00001000 -#define AR5K_AR5212_TXCFG_FRMPAD_DIS 0x00002000 -#define AR5K_AR5212_TXCFG_RDY_DIS 0x00004000 - -/* - * Receive configuration register - */ -#define AR5K_AR5212_RXCFG 0x0034 -#define AR5K_AR5212_RXCFG_SDMAMW 0x00000007 -#define AR5K_AR5212_RXCFG_SDMAMW_S 0 -#define AR5K_AR5311_RXCFG_DEFAULT_ANTENNA 0x00000008 -#define AR5K_AR5212_RXCFG_ZLFDMA 0x00000010 -#define AR5K_AR5212_RXCFG_JUMBO_RXE 0x00000020 -#define AR5K_AR5212_RXCFG_JUMBO_WRAP 0x00000040 - -/* - * MIB control register - */ -#define AR5K_AR5212_MIBC 0x0040 -#define AR5K_AR5212_MIBC_COW 0x00000001 -#define AR5K_AR5212_MIBC_FMC 0x00000002 -#define AR5K_AR5212_MIBC_CMC 0x00000004 -#define AR5K_AR5212_MIBC_MCS 0x00000008 - -/* - * Timeout prescale register - */ -#define AR5K_AR5212_TOPS 0x0044 -#define AR5K_AR5212_TOPS_M 0x0000ffff - -/* - * Receive timeout register (no frame received) - */ -#define AR5K_AR5212_RXNOFRM 0x0048 -#define AR5K_AR5212_RXNOFRM_M 0x000003ff - -/* - * Transmit timeout register (no frame sent) - */ -#define AR5K_AR5212_TXNOFRM 0x004c -#define AR5K_AR5212_TXNOFRM_M 0x000003ff -#define AR5K_AR5212_TXNOFRM_QCU 0x000ffc00 - -/* - * Receive frame gap timeout register - */ -#define AR5K_AR5212_RPGTO 0x0050 -#define AR5K_AR5212_RPGTO_M 0x000003ff - -/* - * Receive frame count limit register - */ -#define AR5K_AR5212_RFCNT 0x0054 -#define AR5K_AR5212_RFCNT_M 0x0000001f - -/* - * Misc settings register - */ -#define AR5K_AR5212_MISC 0x0058 -#define AR5K_AR5212_MISC_DMA_OBS_M 0x000001e0 -#define AR5K_AR5212_MISC_DMA_OBS_S 5 -#define AR5K_AR5212_MISC_MISC_OBS_M 0x00000e00 -#define AR5K_AR5212_MISC_MISC_OBS_S 9 -#define AR5K_AR5212_MISC_MAC_OBS_LSB_M 0x00007000 -#define AR5K_AR5212_MISC_MAC_OBS_LSB_S 12 -#define AR5K_AR5212_MISC_MAC_OBS_MSB_M 0x00038000 -#define AR5K_AR5212_MISC_MAC_OBS_MSB_S 15 - -/* - * Primary interrupt status register - */ -#define AR5K_AR5212_PISR 0x0080 -#define AR5K_AR5212_PISR_RXOK 0x00000001 -#define AR5K_AR5212_PISR_RXDESC 0x00000002 -#define AR5K_AR5212_PISR_RXERR 0x00000004 -#define AR5K_AR5212_PISR_RXNOFRM 0x00000008 -#define AR5K_AR5212_PISR_RXEOL 0x00000010 -#define AR5K_AR5212_PISR_RXORN 0x00000020 -#define AR5K_AR5212_PISR_TXOK 0x00000040 -#define AR5K_AR5212_PISR_TXDESC 0x00000080 -#define AR5K_AR5212_PISR_TXERR 0x00000100 -#define AR5K_AR5212_PISR_TXNOFRM 0x00000200 -#define AR5K_AR5212_PISR_TXEOL 0x00000400 -#define AR5K_AR5212_PISR_TXURN 0x00000800 -#define AR5K_AR5212_PISR_MIB 0x00001000 -#define AR5K_AR5212_PISR_SWI 0x00002000 -#define AR5K_AR5212_PISR_RXPHY 0x00004000 -#define AR5K_AR5212_PISR_RXKCM 0x00008000 -#define AR5K_AR5212_PISR_SWBA 0x00010000 -#define AR5K_AR5212_PISR_BRSSI 0x00020000 -#define AR5K_AR5212_PISR_BMISS 0x00040000 -#define AR5K_AR5212_PISR_HIUERR 0x00080000 -#define AR5K_AR5212_PISR_BNR 0x00100000 -#define AR5K_AR5212_PISR_RXCHIRP 0x00200000 -#define AR5K_AR5212_PISR_TIM 0x00800000 -#define AR5K_AR5212_PISR_BCNMISC 0x00800000 -#define AR5K_AR5212_PISR_GPIO 0x01000000 -#define AR5K_AR5212_PISR_QCBRORN 0x02000000 -#define AR5K_AR5212_PISR_QCBRURN 0x04000000 -#define AR5K_AR5212_PISR_QTRIG 0x08000000 - -/* - * Secondary interrupt status registers (0 - 4) - */ -#define AR5K_AR5212_SISR0 0x0084 -#define AR5K_AR5212_SISR0_QCU_TXOK 0x000003ff -#define AR5K_AR5212_SISR0_QCU_TXDESC 0x03ff0000 - -#define AR5K_AR5212_SISR1 0x0088 -#define AR5K_AR5212_SISR1_QCU_TXERR 0x000003ff -#define AR5K_AR5212_SISR1_QCU_TXEOL 0x03ff0000 - -#define AR5K_AR5212_SISR2 0x008c -#define AR5K_AR5212_SISR2_QCU_TXURN 0x000003ff -#define AR5K_AR5212_SISR2_MCABT 0x00100000 -#define AR5K_AR5212_SISR2_SSERR 0x00200000 -#define AR5K_AR5212_SISR2_DPERR 0x00400000 -#define AR5K_AR5212_SISR2_TIM 0x01000000 -#define AR5K_AR5212_SISR2_CAB_END 0x02000000 -#define AR5K_AR5212_SISR2_DTIM_SYNC 0x04000000 -#define AR5K_AR5212_SISR2_BCN_TIMEOUT 0x08000000 -#define AR5K_AR5212_SISR2_CAB_TIMEOUT 0x10000000 -#define AR5K_AR5212_SISR2_DTIM 0x20000000 - -#define AR5K_AR5212_SISR3 0x0090 -#define AR5K_AR5212_SISR3_QCBRORN 0x000003ff -#define AR5K_AR5212_SISR3_QCBRURN 0x03ff0000 - -#define AR5K_AR5212_SISR4 0x0094 -#define AR5K_AR5212_SISR4_QTRIG 0x000003ff - -/* - * Shadow read-and-clear interrupt status registers - */ -#define AR5K_AR5212_RAC_PISR 0x00c0 -#define AR5K_AR5212_RAC_SISR0 0x00c4 -#define AR5K_AR5212_RAC_SISR1 0x00c8 -#define AR5K_AR5212_RAC_SISR2 0x00cc -#define AR5K_AR5212_RAC_SISR3 0c00d0 -#define AR5K_AR5212_RAC_SISR4 0c00d4 - -/* - * Primary interrupt mask register - */ -#define AR5K_AR5212_PIMR 0x00a0 -#define AR5K_AR5212_PIMR_RXOK 0x00000001 -#define AR5K_AR5212_PIMR_RXDESC 0x00000002 -#define AR5K_AR5212_PIMR_RXERR 0x00000004 -#define AR5K_AR5212_PIMR_RXNOFRM 0x00000008 -#define AR5K_AR5212_PIMR_RXEOL 0x00000010 -#define AR5K_AR5212_PIMR_RXORN 0x00000020 -#define AR5K_AR5212_PIMR_TXOK 0x00000040 -#define AR5K_AR5212_PIMR_TXDESC 0x00000080 -#define AR5K_AR5212_PIMR_TXERR 0x00000100 -#define AR5K_AR5212_PIMR_TXNOFRM 0x00000200 -#define AR5K_AR5212_PIMR_TXEOL 0x00000400 -#define AR5K_AR5212_PIMR_TXURN 0x00000800 -#define AR5K_AR5212_PIMR_MIB 0x00001000 -#define AR5K_AR5212_PIMR_SWI 0x00002000 -#define AR5K_AR5212_PIMR_RXPHY 0x00004000 -#define AR5K_AR5212_PIMR_RXKCM 0x00008000 -#define AR5K_AR5212_PIMR_SWBA 0x00010000 -#define AR5K_AR5212_PIMR_BRSSI 0x00020000 -#define AR5K_AR5212_PIMR_BMISS 0x00040000 -#define AR5K_AR5212_PIMR_HIUERR 0x00080000 -#define AR5K_AR5212_PIMR_BNR 0x00100000 -#define AR5K_AR5212_PIMR_RXCHIRP 0x00200000 -#define AR5K_AR5212_PIMR_TIM 0x00800000 -#define AR5K_AR5212_PIMR_BCNMISC 0x00800000 -#define AR5K_AR5212_PIMR_GPIO 0x01000000 -#define AR5K_AR5212_PIMR_QCBRORN 0x02000000 -#define AR5K_AR5212_PIMR_QCBRURN 0x04000000 -#define AR5K_AR5212_PIMR_QTRIG 0x08000000 - -/* - * Secondary interrupt mask registers (0 - 4) - */ -#define AR5K_AR5212_SIMR0 0x00a4 -#define AR5K_AR5212_SIMR0_QCU_TXOK 0x000003ff -#define AR5K_AR5212_SIMR0_QCU_TXOK_S 0 -#define AR5K_AR5212_SIMR0_QCU_TXDESC 0x03ff0000 -#define AR5K_AR5212_SIMR0_QCU_TXDESC_S 16 - -#define AR5K_AR5212_SIMR1 0x00a8 -#define AR5K_AR5212_SIMR1_QCU_TXERR 0x000003ff -#define AR5K_AR5212_SIMR1_QCU_TXERR_S 0 -#define AR5K_AR5212_SIMR1_QCU_TXEOL 0x03ff0000 -#define AR5K_AR5212_SIMR1_QCU_TXEOL_S 16 - -#define AR5K_AR5212_SIMR2 0x00ac -#define AR5K_AR5212_SIMR2_QCU_TXURN 0x000003ff -#define AR5K_AR5212_SIMR2_QCU_TXURN_S 0 -#define AR5K_AR5212_SIMR2_MCABT 0x00100000 -#define AR5K_AR5212_SIMR2_SSERR 0x00200000 -#define AR5K_AR5212_SIMR2_DPERR 0x00400000 -#define AR5K_AR5212_SIMR2_TIM 0x01000000 -#define AR5K_AR5212_SIMR2_CAB_END 0x02000000 -#define AR5K_AR5212_SIMR2_DTIM_SYNC 0x04000000 -#define AR5K_AR5212_SIMR2_BCN_TIMEOUT 0x08000000 -#define AR5K_AR5212_SIMR2_CAB_TIMEOUT 0x10000000 -#define AR5K_AR5212_SIMR2_DTIM 0x20000000 - -#define AR5K_AR5212_SIMR3 0x00b0 -#define AR5K_AR5212_SIMR3_QCBRORN 0x000003ff -#define AR5K_AR5212_SIMR3_QCBRORN_S 0 -#define AR5K_AR5212_SIMR3_QCBRURN 0x03ff0000 -#define AR5K_AR5212_SIMR3_QCBRURN_S 16 - -#define AR5K_AR5212_SIMR4 0x00b4 -#define AR5K_AR5212_SIMR4_QTRIG 0x000003ff -#define AR5K_AR5212_SIMR4_QTRIG_S 0 - -/* - * Decompression mask registers - */ -#define AR5K_AR5212_DCM_ADDR 0x0400 -#define AR5K_AR5212_DCM_DATA 0x0404 - -/* - * Decompression configuration registers - */ -#define AR5K_AR5212_DCCFG 0x0420 - -/* - * Compression configuration registers - */ -#define AR5K_AR5212_CCFG 0x0600 -#define AR5K_AR5212_CCFG_CUP 0x0604 - -/* - * Compression performance counter registers - */ -#define AR5K_AR5212_CPC0 0x0610 -#define AR5K_AR5212_CPC1 0x0614 -#define AR5K_AR5212_CPC2 0x0618 -#define AR5K_AR5212_CPC3 0x061c -#define AR5K_AR5212_CPCORN 0x0620 - -/* - * Queue control unit (QCU) registers (0 - 9) - */ -#define AR5K_AR5212_QCU(_n, _a) (((_n) << 2) + _a) - -/* - * QCU Transmit descriptor pointer registers - */ -#define AR5K_AR5212_QCU_TXDP(_n) AR5K_AR5212_QCU(_n, 0x0800) - -/* - * QCU Transmit enable register - */ -#define AR5K_AR5212_QCU_TXE 0x0840 - -/* - * QCU Transmit disable register - */ -#define AR5K_AR5212_QCU_TXD 0x0880 - -/* - * QCU CBR configuration registers - */ -#define AR5K_AR5212_QCU_CBRCFG(_n) AR5K_AR5212_QCU(_n, 0x08c0) -#define AR5K_AR5212_QCU_CBRCFG_INTVAL 0x00ffffff -#define AR5K_AR5212_QCU_CBRCFG_INTVAL_S 0 -#define AR5K_AR5212_QCU_CBRCFG_ORN_THRES 0xff000000 -#define AR5K_AR5212_QCU_CBRCFG_ORN_THRES_S 24 - -/* - * QCU Ready time configuration registers - */ -#define AR5K_AR5212_QCU_RDYTIMECFG(_n) AR5K_AR5212_QCU(_n, 0x0900) -#define AR5K_AR5212_QCU_RDYTIMECFG_INTVAL 0x00ffffff -#define AR5K_AR5212_QCU_RDYTIMECFG_INTVAL_S 0 -#define AR5K_AR5212_QCU_RDYTIMECFG_DURATION 0x00ffffff -#define AR5K_AR5212_QCU_RDYTIMECFG_ENABLE 0x01000000 - -/* - * QCU one shot arm set registers - */ -#define AR5K_AR5212_QCU_ONESHOTARMS(_n) AR5K_AR5212_QCU(_n, 0x0940) -#define AR5K_AR5212_QCU_ONESHOTARMS_M 0x0000ffff - -/* - * QCU one shot arm clear registers - */ -#define AR5K_AR5212_QCU_ONESHOTARMC(_n) AR5K_AR5212_QCU(_n, 0x0980) -#define AR5K_AR5212_QCU_ONESHOTARMC_M 0x0000ffff - -/* - * QCU misc registers - */ -#define AR5K_AR5212_QCU_MISC(_n) AR5K_AR5212_QCU(_n, 0x09c0) -#define AR5K_AR5212_QCU_MISC_FRSHED_M 0x0000000f -#define AR5K_AR5212_QCU_MISC_FRSHED_ASAP 0 -#define AR5K_AR5212_QCU_MISC_FRSHED_CBR 1 -#define AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT 2 -#define AR5K_AR5212_QCU_MISC_FRSHED_TIM_GT 3 -#define AR5K_AR5212_QCU_MISC_FRSHED_BCN_SENT_GT 4 -#define AR5K_AR5212_QCU_MISC_ONESHOT_ENABLE 0x00000010 -#define AR5K_AR5212_QCU_MISC_CBREXP 0x00000020 -#define AR5K_AR5212_QCU_MISC_CBREXP_BCN 0x00000040 -#define AR5K_AR5212_QCU_MISC_BCN_ENABLE 0x00000080 -#define AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE 0x00000100 -#define AR5K_AR5212_QCU_MISC_TXE 0x00000200 -#define AR5K_AR5212_QCU_MISC_CBR 0x00000400 -#define AR5K_AR5212_QCU_MISC_DCU_EARLY 0x00000800 - -/* - * QCU status registers - */ -#define AR5K_AR5212_QCU_STS(_n) AR5K_AR5212_QCU(_n, 0x0a00) -#define AR5K_AR5212_QCU_STS_FRMPENDCNT 0x00000003 -#define AR5K_AR5212_QCU_STS_CBREXPCNT 0x0000ff00 - -/* - * QCU ready time shutdown register - */ -#define AR5K_AR5212_QCU_RDYTIMESHDN 0x0a40 -#define AR5K_AR5212_QCU_RDYTIMESHDN_M 0x000003ff - -/* - * QCU compression buffer base registers - */ -#define AR5K_AR5212_QCU_CBB_SELECT 0x0b00 -#define AR5K_AR5212_QCU_CBB_ADDR 0x0b04 - -/* - * QCU compression buffer configuration register - */ -#define AR5K_AR5212_QCU_CBCFG 0x0b08 - -/* - * DCF control unit (DCU) registers (0 - 9) - */ -#define AR5K_AR5212_DCU(_n, _a) AR5K_AR5212_QCU(_n, _a) - -/* - * DCU QCU mask registers - */ -#define AR5K_AR5212_DCU_QCUMASK(_n) AR5K_AR5212_DCU(_n, 0x1000) -#define AR5K_AR5212_DCU_QCUMASK_M 0x000003ff - -/* - * DCU local IFS settings register - */ -#define AR5K_AR5212_DCU_LCL_IFS(_n) AR5K_AR5212_DCU(_n, 0x1040) -#define AR5K_AR5212_DCU_LCL_IFS_CW_MIN 0x000003ff -#define AR5K_AR5212_DCU_LCL_IFS_CW_MIN_S 0 -#define AR5K_AR5212_DCU_LCL_IFS_CW_MAX 0x000ffc00 -#define AR5K_AR5212_DCU_LCL_IFS_CW_MAX_S 10 -#define AR5K_AR5212_DCU_LCL_IFS_AIFS 0x0ff00000 -#define AR5K_AR5212_DCU_LCL_IFS_AIFS_S 20 - -/* - * DCU retry limit registers - */ -#define AR5K_AR5212_DCU_RETRY_LMT(_n) AR5K_AR5212_DCU(_n, 0x1080) -#define AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY 0x0000000f -#define AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY 0x000000f0 -#define AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 -#define AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 -#define AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY_S 14 - -/* - * DCU channel time registers - */ -#define AR5K_AR5212_DCU_CHAN_TIME(_n) AR5K_AR5212_DCU(_n, 0x10c0) -#define AR5K_AR5212_DCU_CHAN_TIME_DUR 0x000fffff -#define AR5K_AR5212_DCU_CHAN_TIME_DUR_S 0 -#define AR5K_AR5212_DCU_CHAN_TIME_ENABLE 0x00100000 - -/* - * DCU misc registers - */ -#define AR5K_AR5212_DCU_MISC(_n) AR5K_AR5212_DCU(_n, 0x1100) -#define AR5K_AR5212_DCU_MISC_BACKOFF 0x000007ff -#define AR5K_AR5212_DCU_MISC_BACKOFF_FRAG 0x00000200 -#define AR5K_AR5212_DCU_MISC_HCFPOLL_ENABLE 0x00000800 -#define AR5K_AR5212_DCU_MISC_BACKOFF_PERSIST 0x00001000 -#define AR5K_AR5212_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 -#define AR5K_AR5212_DCU_MISC_VIRTCOL 0x0000c000 -#define AR5K_AR5212_DCU_MISC_VIRTCOL_NORMAL 0 -#define AR5K_AR5212_DCU_MISC_VIRTCOL_MODIFIED 1 -#define AR5K_AR5212_DCU_MISC_VIRTCOL_IGNORE 2 -#define AR5K_AR5212_DCU_MISC_BCN_ENABLE 0x00010000 -#define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL 0x00060000 -#define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_S 17 -#define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_NONE 0 -#define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_INTFRM 1 -#define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 -#define AR5K_AR5212_DCU_MISC_ARBLOCK_IGNORE 0x00080000 -#define AR5K_AR5212_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 -#define AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 -#define AR5K_AR5212_DCU_MISC_VIRT_COLL_POLICY 0x00400000 -#define AR5K_AR5212_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 -#define AR5K_AR5212_DCU_MISC_SEQNUM_CTL 0x01000000 - -/* - * DCU frame sequence number registers - */ -#define AR5K_AR5212_DCU_SEQNUM(_n) AR5K_AR5212_DCU(_n, 0x1140) -#define AR5K_AR5212_DCU_SEQNUM_M 0x00000fff -/* - * DCU global IFS SIFS registers - */ -#define AR5K_AR5212_DCU_GBL_IFS_SIFS 0x1030 -#define AR5K_AR5212_DCU_GBL_IFS_SIFS_M 0x0000ffff - -/* - * DCU global IFS slot interval registers - */ -#define AR5K_AR5212_DCU_GBL_IFS_SLOT 0x1070 -#define AR5K_AR5212_DCU_GBL_IFS_SLOT_M 0x0000ffff - -/* - * DCU global IFS EIFS registers - */ -#define AR5K_AR5212_DCU_GBL_IFS_EIFS 0x10b0 -#define AR5K_AR5212_DCU_GBL_IFS_EIFS_M 0x0000ffff - -/* - * DCU global IFS misc registers - */ -#define AR5K_AR5212_DCU_GBL_IFS_MISC 0x10f0 -#define AR5K_AR5212_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 -#define AR5K_AR5212_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 -#define AR5K_AR5212_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 -#define AR5K_AR5212_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 -#define AR5K_AR5212_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 - -/* - * DCU frame prefetch control register - */ -#define AR5K_AR5212_DCU_FP 0x1230 - -/* - * DCU transmit pause control/status register - */ -#define AR5K_AR5212_DCU_TXP 0x1270 -#define AR5K_AR5212_DCU_TXP_M 0x000003ff -#define AR5K_AR5212_DCU_TXP_STATUS 0x00010000 - -/* - * DCU transmit filter register - */ -#define AR5K_AR5212_DCU_TX_FILTER 0x1038 - -/* - * DCU clear transmit filter register - */ -#define AR5K_AR5212_DCU_TX_FILTER_CLR 0x143c - -/* - * DCU set transmit filter register - */ -#define AR5K_AR5212_DCU_TX_FILTER_SET 0x147c - -/* - * DMA size definitions - */ -typedef enum { - AR5K_AR5212_DMASIZE_4B = 0, - AR5K_AR5212_DMASIZE_8B = 1, - AR5K_AR5212_DMASIZE_16B = 2, - AR5K_AR5212_DMASIZE_32B = 3, - AR5K_AR5212_DMASIZE_64B = 4, - AR5K_AR5212_DMASIZE_128B = 5, - AR5K_AR5212_DMASIZE_256B = 6, - AR5K_AR5212_DMASIZE_512B = 7 -} ar5k_ar5212_dmasize_t; - -/* - * Reset control register - */ -#define AR5K_AR5212_RC 0x4000 -#define AR5K_AR5212_RC_PCU 0x00000001 -#define AR5K_AR5212_RC_BB 0x00000002 -#define AR5K_AR5212_RC_PCI 0x00000010 -#define AR5K_AR5212_RC_CHIP ( \ - AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB | AR5K_AR5212_RC_PCI \ -) - -/* - * Sleep control register - */ -#define AR5K_AR5212_SCR 0x4004 -#define AR5K_AR5212_SCR_SLDUR 0x0000ffff -#define AR5K_AR5212_SCR_SLE 0x00030000 -#define AR5K_AR5212_SCR_SLE_S 16 -#define AR5K_AR5212_SCR_SLE_WAKE 0x00000000 -#define AR5K_AR5212_SCR_SLE_SLP 0x00010000 -#define AR5K_AR5212_SCR_SLE_ALLOW 0x00020000 -#define AR5K_AR5212_SCR_SLE_UNITS 0x00000008 - -/* - * Interrupt pending register - */ -#define AR5K_AR5212_INTPEND 0x4008 -#define AR5K_AR5212_INTPEND_M 0x00000001 - -/* - * Sleep force register - */ -#define AR5K_AR5212_SFR 0x400c -#define AR5K_AR5212_SFR_M 0x00000001 - -/* - * PCI configuration register - */ -#define AR5K_AR5212_PCICFG 0x4010 -#define AR5K_AR5212_PCICFG_CLKRUNEN 0x00000004 -#define AR5K_AR5212_PCICFG_EESIZE 0x00000018 -#define AR5K_AR5212_PCICFG_EESIZE_S 3 -#define AR5K_AR5212_PCICFG_EESIZE_4K 0 -#define AR5K_AR5212_PCICFG_EESIZE_8K 1 -#define AR5K_AR5212_PCICFG_EESIZE_16K 2 -#define AR5K_AR5212_PCICFG_EESIZE_FAIL 3 -#define AR5K_AR5212_PCICFG_LED 0x00000060 -#define AR5K_AR5212_PCICFG_LED_NONE 0x00000000 -#define AR5K_AR5212_PCICFG_LED_PEND 0x00000020 -#define AR5K_AR5212_PCICFG_LED_ASSOC 0x00000040 -#define AR5K_AR5212_PCICFG_BUS_SEL 0x00000380 -#define AR5K_AR5212_PCICFG_CBEFIX_DIS 0x00000400 -#define AR5K_AR5212_PCICFG_SL_INTEN 0x00000800 -#define AR5K_AR5212_PCICFG_SL_INPEN 0x00002800 -#define AR5K_AR5212_PCICFG_SPWR_DN 0x00010000 -#define AR5K_AR5212_PCICFG_LEDMODE 0x000e0000 -#define AR5K_AR5212_PCICFG_LEDMODE_PROP 0x00000000 -#define AR5K_AR5212_PCICFG_LEDMODE_PROM 0x00020000 -#define AR5K_AR5212_PCICFG_LEDMODE_PWR 0x00040000 -#define AR5K_AR5212_PCICFG_LEDMODE_RAND 0x00060000 -#define AR5K_AR5212_PCICFG_LEDBLINK 0x00700000 -#define AR5K_AR5212_PCICFG_LEDBLINK_S 20 -#define AR5K_AR5212_PCICFG_LEDSLOW 0x00800000 -#define AR5K_AR5212_PCICFG_LEDSTATE \ - (AR5K_AR5212_PCICFG_LED | AR5K_AR5212_PCICFG_LEDMODE | \ - AR5K_AR5212_PCICFG_LEDBLINK | AR5K_AR5212_PCICFG_LEDSLOW) - -/* - * "General Purpose Input/Output" (GPIO) control register - */ -#define AR5K_AR5212_GPIOCR 0x4014 -#define AR5K_AR5212_GPIOCR_INT_ENA 0x00008000 -#define AR5K_AR5212_GPIOCR_INT_SELL 0x00000000 -#define AR5K_AR5212_GPIOCR_INT_SELH 0x00010000 -#define AR5K_AR5212_GPIOCR_NONE(n) (0 << ((n) * 2)) -#define AR5K_AR5212_GPIOCR_OUT0(n) (1 << ((n) * 2)) -#define AR5K_AR5212_GPIOCR_OUT1(n) (2 << ((n) * 2)) -#define AR5K_AR5212_GPIOCR_ALL(n) (3 << ((n) * 2)) -#define AR5K_AR5212_GPIOCR_INT_SEL(n) ((n) << 12) - -#define AR5K_AR5212_NUM_GPIO 6 - -/* - * "General Purpose Input/Output" (GPIO) data output register - */ -#define AR5K_AR5212_GPIODO 0x4018 - -/* - * "General Purpose Input/Output" (GPIO) data input register - */ -#define AR5K_AR5212_GPIODI 0x401c -#define AR5K_AR5212_GPIODI_M 0x0000002f - -/* - * Silicon revision register - */ -#define AR5K_AR5212_SREV 0x4020 -#define AR5K_AR5212_SREV_REV 0x0000000f -#define AR5K_AR5212_SREV_REV_S 0 -#define AR5K_AR5212_SREV_VER 0x000000ff -#define AR5K_AR5212_SREV_VER_S 4 - -/* - * EEPROM access registers - */ -#define AR5K_AR5212_EEPROM_BASE 0x6000 -#define AR5K_AR5212_EEPROM_DATA 0x6004 -#define AR5K_AR5212_EEPROM_CMD 0x6008 -#define AR5K_AR5212_EEPROM_CMD_READ 0x00000001 -#define AR5K_AR5212_EEPROM_CMD_WRITE 0x00000002 -#define AR5K_AR5212_EEPROM_CMD_RESET 0x00000004 -#define AR5K_AR5212_EEPROM_STATUS 0x600c -#define AR5K_AR5212_EEPROM_STAT_RDERR 0x00000001 -#define AR5K_AR5212_EEPROM_STAT_RDDONE 0x00000002 -#define AR5K_AR5212_EEPROM_STAT_WRERR 0x00000004 -#define AR5K_AR5212_EEPROM_STAT_WRDONE 0x00000008 -#define AR5K_AR5212_EEPROM_CFG 0x6010 - -/* - * PCU registers - */ - -#define AR5K_AR5212_PCU_MIN 0x8000 -#define AR5K_AR5212_PCU_MAX 0x8fff - -/* - * First station id register (MAC address in lower 32 bits) - */ -#define AR5K_AR5212_STA_ID0 0x8000 - -/* - * Second station id register (MAC address in upper 16 bits) - */ -#define AR5K_AR5212_STA_ID1 0x8004 -#define AR5K_AR5212_STA_ID1_AP 0x00010000 -#define AR5K_AR5212_STA_ID1_ADHOC 0x00020000 -#define AR5K_AR5212_STA_ID1_PWR_SV 0x00040000 -#define AR5K_AR5212_STA_ID1_NO_KEYSRCH 0x00080000 -#define AR5K_AR5212_STA_ID1_PCF 0x00100000 -#define AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA 0x00200000 -#define AR5K_AR5212_STA_ID1_DESC_ANTENNA 0x00400000 -#define AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000 -#define AR5K_AR5212_STA_ID1_ACKCTS_6MB 0x01000000 -#define AR5K_AR5212_STA_ID1_BASE_RATE_11B 0x02000000 - -/* - * First BSSID register (MAC address, lower 32bits) - */ -#define AR5K_AR5212_BSS_ID0 0x8008 - -/* - * Second BSSID register (MAC address in upper 16 bits) - * - * AID: Association ID - */ -#define AR5K_AR5212_BSS_ID1 0x800c -#define AR5K_AR5212_BSS_ID1_AID 0xffff0000 -#define AR5K_AR5212_BSS_ID1_AID_S 16 - -/* - * Backoff slot time register - */ -#define AR5K_AR5212_SLOT_TIME 0x8010 - -/* - * ACK/CTS timeout register - */ -#define AR5K_AR5212_TIME_OUT 0x8014 -#define AR5K_AR5212_TIME_OUT_ACK 0x00001fff -#define AR5K_AR5212_TIME_OUT_ACK_S 0 -#define AR5K_AR5212_TIME_OUT_CTS 0x1fff0000 -#define AR5K_AR5212_TIME_OUT_CTS_S 16 - -/* - * RSSI threshold register - */ -#define AR5K_AR5212_RSSI_THR 0x8018 -#define AR5K_AR5212_RSSI_THR_M 0x000000ff -#define AR5K_AR5212_RSSI_THR_BMISS 0x0000ff00 -#define AR5K_AR5212_RSSI_THR_BMISS_S 8 - -/* - * Transmit latency register - */ -#define AR5K_AR5212_USEC 0x801c -#define AR5K_AR5212_USEC_1 0x0000007f -#define AR5K_AR5212_USEC_1_S 0 -#define AR5K_AR5212_USEC_32 0x00003f80 -#define AR5K_AR5212_USEC_32_S 7 -#define AR5K_AR5212_USEC_TX_LATENCY 0x007fc000 -#define AR5K_AR5212_USEC_TX_LATENCY_S 14 -#define AR5K_AR5212_USEC_RX_LATENCY 0x1f800000 -#define AR5K_AR5212_USEC_RX_LATENCY_S 23 -#define AR5K_AR5311_USEC_TX_LATENCY 0x000fc000 -#define AR5K_AR5311_USEC_TX_LATENCY_S 14 -#define AR5K_AR5311_USEC_RX_LATENCY 0x03f00000 -#define AR5K_AR5311_USEC_RX_LATENCY_S 20 - -/* - * PCU beacon control register - */ -#define AR5K_AR5212_BEACON 0x8020 -#define AR5K_AR5212_BEACON_PERIOD 0x0000ffff -#define AR5K_AR5212_BEACON_PERIOD_S 0 -#define AR5K_AR5212_BEACON_TIM 0x007f0000 -#define AR5K_AR5212_BEACON_TIM_S 16 -#define AR5K_AR5212_BEACON_ENABLE 0x00800000 -#define AR5K_AR5212_BEACON_RESET_TSF 0x01000000 - -/* - * CFP period register - */ -#define AR5K_AR5212_CFP_PERIOD 0x8024 - -/* - * Next beacon time register - */ -#define AR5K_AR5212_TIMER0 0x8028 - -/* - * Next DMA beacon alert register - */ -#define AR5K_AR5212_TIMER1 0x802c - -/* - * Next software beacon alert register - */ -#define AR5K_AR5212_TIMER2 0x8030 - -/* - * Next ATIM window time register - */ -#define AR5K_AR5212_TIMER3 0x8034 - -/* - * CFP duration register - */ -#define AR5K_AR5212_CFP_DUR 0x8038 - -/* - * Receive filter register - */ -#define AR5K_AR5212_RX_FILTER 0x803c -#define AR5K_AR5212_RX_FILTER_UNICAST 0x00000001 -#define AR5K_AR5212_RX_FILTER_MULTICAST 0x00000002 -#define AR5K_AR5212_RX_FILTER_BROADCAST 0x00000004 -#define AR5K_AR5212_RX_FILTER_CONTROL 0x00000008 -#define AR5K_AR5212_RX_FILTER_BEACON 0x00000010 -#define AR5K_AR5212_RX_FILTER_PROMISC 0x00000020 -#define AR5K_AR5212_RX_FILTER_XR_POLL 0x00000040 -#define AR5K_AR5212_RX_FILTER_PROBE_REQ 0x00000080 - -/* - * Multicast filter register (lower 32 bits) - */ -#define AR5K_AR5212_MCAST_FIL0 0x8040 - -/* - * Multicast filter register (higher 16 bits) - */ -#define AR5K_AR5212_MCAST_FIL1 0x8044 - -/* - * PCU control register - */ -#define AR5K_AR5212_DIAG_SW 0x8048 -#define AR5K_AR5212_DIAG_SW_DIS_WEP_ACK 0x00000001 -#define AR5K_AR5212_DIAG_SW_DIS_ACK 0x00000002 -#define AR5K_AR5212_DIAG_SW_DIS_CTS 0x00000004 -#define AR5K_AR5212_DIAG_SW_DIS_ENC 0x00000008 -#define AR5K_AR5212_DIAG_SW_DIS_DEC 0x00000010 -#define AR5K_AR5212_DIAG_SW_DIS_RX 0x00000020 -#define AR5K_AR5212_DIAG_SW_LOOP_BACK 0x00000040 -#define AR5K_AR5212_DIAG_SW_CORR_FCS 0x00000080 -#define AR5K_AR5212_DIAG_SW_CHAN_INFO 0x00000100 -#define AR5K_AR5212_DIAG_SW_EN_SCRAM_SEED 0x00000200 -#define AR5K_AR5212_DIAG_SW_ECO_ENABLE 0x00000400 -#define AR5K_AR5212_DIAG_SW_SCRAM_SEED_M 0x0001fc00 -#define AR5K_AR5212_DIAG_SW_SCRAM_SEED_S 10 -#define AR5K_AR5212_DIAG_SW_FRAME_NV0 0x00020000 -#define AR5K_AR5212_DIAG_SW_OBSPT_M 0x000c0000 -#define AR5K_AR5212_DIAG_SW_OBSPT_S 18 - -/* - * TSF (clock) register (lower 32 bits) - */ -#define AR5K_AR5212_TSF_L32 0x804c - -/* - * TSF (clock) register (higher 32 bits) - */ -#define AR5K_AR5212_TSF_U32 0x8050 - -/* - * ADDAC test register - */ -#define AR5K_AR5212_ADDAC_TEST 0x8054 - -/* - * Default antenna register - */ -#define AR5K_AR5212_DEFAULT_ANTENNA 0x8058 - -/* - * Last beacon timestamp register - */ -#define AR5K_AR5212_LAST_TSTP 0x8080 - -/* - * NAV register (current) - */ -#define AR5K_AR5212_NAV 0x8084 - -/* - * RTS success register - */ -#define AR5K_AR5212_RTS_OK 0x8088 - -/* - * RTS failure register - */ -#define AR5K_AR5212_RTS_FAIL 0x808c - -/* - * ACK failure register - */ -#define AR5K_AR5212_ACK_FAIL 0x8090 - -/* - * FCS failure register - */ -#define AR5K_AR5212_FCS_FAIL 0x8094 - -/* - * Beacon count register - */ -#define AR5K_AR5212_BEACON_CNT 0x8098 - -/* - * XR (eXtended Range) mode register - */ -#define AR5K_AR5212_XRMODE 0x80c0 -#define AR5K_AR5212_XRMODE_POLL_TYPE_M 0x0000003f -#define AR5K_AR5212_XRMODE_POLL_TYPE_S 0 -#define AR5K_AR5212_XRMODE_POLL_SUBTYPE_M 0x0000003c -#define AR5K_AR5212_XRMODE_POLL_SUBTYPE_S 2 -#define AR5K_AR5212_XRMODE_POLL_WAIT_ALL 0x00000080 -#define AR5K_AR5212_XRMODE_SIFS_DELAY 0x000fff00 -#define AR5K_AR5212_XRMODE_FRAME_HOLD_M 0xfff00000 -#define AR5K_AR5212_XRMODE_FRAME_HOLD_S 20 - -/* - * XR delay register - */ -#define AR5K_AR5212_XRDELAY 0x80c4 -#define AR5K_AR5212_XRDELAY_SLOT_DELAY_M 0x0000ffff -#define AR5K_AR5212_XRDELAY_SLOT_DELAY_S 0 -#define AR5K_AR5212_XRDELAY_CHIRP_DELAY_M 0xffff0000 -#define AR5K_AR5212_XRDELAY_CHIRP_DELAY_S 16 - -/* - * XR timeout register - */ -#define AR5K_AR5212_XRTIMEOUT 0x80c8 -#define AR5K_AR5212_XRTIMEOUT_CHIRP_M 0x0000ffff -#define AR5K_AR5212_XRTIMEOUT_CHIRP_S 0 -#define AR5K_AR5212_XRTIMEOUT_POLL_M 0xffff0000 -#define AR5K_AR5212_XRTIMEOUT_POLL_S 16 - -/* - * XR chirp register - */ -#define AR5K_AR5212_XRCHIRP 0x80cc -#define AR5K_AR5212_XRCHIRP_SEND 0x00000001 -#define AR5K_AR5212_XRCHIRP_GAP 0xffff0000 - -/* - * XR stomp register - */ -#define AR5K_AR5212_XRSTOMP 0x80d0 -#define AR5K_AR5212_XRSTOMP_TX 0x00000001 -#define AR5K_AR5212_XRSTOMP_RX_ABORT 0x00000002 -#define AR5K_AR5212_XRSTOMP_RSSI_THRES 0x0000ff00 - -/* - * First enhanced sleep register - */ -#define AR5K_AR5212_SLEEP0 0x80d4 -#define AR5K_AR5212_SLEEP0_NEXT_DTIM 0x0007ffff -#define AR5K_AR5212_SLEEP0_NEXT_DTIM_S 0 -#define AR5K_AR5212_SLEEP0_ASSUME_DTIM 0x00080000 -#define AR5K_AR5212_SLEEP0_ENH_SLEEP_EN 0x00100000 -#define AR5K_AR5212_SLEEP0_CABTO 0xff000000 -#define AR5K_AR5212_SLEEP0_CABTO_S 24 - -/* - * Second enhanced sleep register - */ -#define AR5K_AR5212_SLEEP1 0x80d8 -#define AR5K_AR5212_SLEEP1_NEXT_TIM 0x0007ffff -#define AR5K_AR5212_SLEEP1_NEXT_TIM_S 0 -#define AR5K_AR5212_SLEEP1_BEACON_TO 0xff000000 -#define AR5K_AR5212_SLEEP1_BEACON_TO_S 24 - -/* - * Third enhanced sleep register - */ -#define AR5K_AR5212_SLEEP2 0x80dc -#define AR5K_AR5212_SLEEP2_TIM_PER 0x0000ffff -#define AR5K_AR5212_SLEEP2_TIM_PER_S 0 -#define AR5K_AR5212_SLEEP2_DTIM_PER 0xffff0000 -#define AR5K_AR5212_SLEEP2_DTIM_PER_S 16 - -/* - * BSSID mask registers - */ -#define AR5K_AR5212_BSS_IDM0 0x80e0 -#define AR5K_AR5212_BSS_IDM1 0x80e4 - -/* - * TX power control (TPC) register - */ -#define AR5K_AR5212_TXPC 0x80e8 -#define AR5K_AR5212_TXPC_ACK_M 0x0000003f -#define AR5K_AR5212_TXPC_ACK_S 0 -#define AR5K_AR5212_TXPC_CTS_M 0x00003f00 -#define AR5K_AR5212_TXPC_CTS_S 8 -#define AR5K_AR5212_TXPC_CHIRP_M 0x003f0000 -#define AR5K_AR5212_TXPC_CHIRP_S 22 - -/* - * Profile count registers - */ -#define AR5K_AR5212_PROFCNT_TX 0x80ec -#define AR5K_AR5212_PROFCNT_RX 0x80f0 -#define AR5K_AR5212_PROFCNT_RXCLR 0x80f4 -#define AR5K_AR5212_PROFCNT_CYCLE 0x80f8 - -/* - * TSF parameter register - */ -#define AR5K_AR5212_TSF_PARM 0x8104 -#define AR5K_AR5212_TSF_PARM_INC_M 0x000000ff -#define AR5K_AR5212_TSF_PARM_INC_S 0 - -/* - * PHY error filter register - */ -#define AR5K_AR5212_PHY_ERR_FIL 0x810c -#define AR5K_AR5212_PHY_ERR_FIL_RADAR 0x00000020 -#define AR5K_AR5212_PHY_ERR_FIL_OFDM 0x00020000 -#define AR5K_AR5212_PHY_ERR_FIL_CCK 0x02000000 - -/* - * Rate duration register - */ -#define AR5K_AR5212_RATE_DUR_0 0x8700 -#define AR5K_AR5212_RATE_DUR(_n) (AR5K_AR5212_RATE_DUR_0 + ((_n) << 2)) - -/* - * Key table (WEP) register - */ -#define AR5K_AR5212_KEYTABLE_0 0x8800 -#define AR5K_AR5212_KEYTABLE(_n) (AR5K_AR5212_KEYTABLE_0 + ((_n) << 5)) -#define AR5K_AR5212_KEYTABLE_OFF(_n, x) (AR5K_AR5212_KEYTABLE(_n) + (x << 2)) -#define AR5K_AR5212_KEYTABLE_TYPE(_n) AR5K_AR5212_KEYTABLE_OFF(_n, 5) -#define AR5K_AR5212_KEYTABLE_TYPE_40 0x00000000 -#define AR5K_AR5212_KEYTABLE_TYPE_104 0x00000001 -#define AR5K_AR5212_KEYTABLE_TYPE_128 0x00000003 -#define AR5K_AR5212_KEYTABLE_TYPE_TKIP 0x00000004 -#define AR5K_AR5212_KEYTABLE_TYPE_AES 0x00000005 -#define AR5K_AR5212_KEYTABLE_TYPE_CCM 0x00000006 -#define AR5K_AR5212_KEYTABLE_TYPE_NULL 0x00000007 -#define AR5K_AR5212_KEYTABLE_ANTENNA 0x00000008 -#define AR5K_AR5212_KEYTABLE_MAC0(_n) AR5K_AR5212_KEYTABLE_OFF(_n, 6) -#define AR5K_AR5212_KEYTABLE_MAC1(_n) AR5K_AR5212_KEYTABLE_OFF(_n, 7) -#define AR5K_AR5212_KEYTABLE_VALID 0x00008000 - -#define AR5K_AR5212_KEYTABLE_SIZE 128 -#define AR5K_AR5212_KEYCACHE_SIZE 8 - -/* - * PHY register - */ -#define AR5K_AR5212_PHY(_n) (0x9800 + ((_n) << 2)) -#define AR5K_AR5212_PHY_SHIFT_2GHZ 0x00004007 -#define AR5K_AR5212_PHY_SHIFT_5GHZ 0x00000007 - -/* - * PHY turbo mode register - */ -#define AR5K_AR5212_PHY_TURBO 0x9804 -#define AR5K_AR5212_PHY_TURBO_MODE 0x00000001 -#define AR5K_AR5212_PHY_TURBO_SHORT 0x00000002 - -/* - * PHY agility command register - */ -#define AR5K_AR5212_PHY_AGC 0x9808 -#define AR5K_AR5212_PHY_AGC_DISABLE 0x08000000 - -/* - * PHY timing register - */ -#define AR5K_AR5212_PHY_TIMING_3 0x9814 -#define AR5K_AR5212_PHY_TIMING_3_DSC_MAN 0xfffe0000 -#define AR5K_AR5212_PHY_TIMING_3_DSC_MAN_S 17 -#define AR5K_AR5212_PHY_TIMING_3_DSC_EXP 0x0001e000 -#define AR5K_AR5212_PHY_TIMING_3_DSC_EXP_S 13 - -/* - * PHY chip revision register - */ -#define AR5K_AR5212_PHY_CHIP_ID 0x9818 - -/* - * PHY activation register - */ -#define AR5K_AR5212_PHY_ACTIVE 0x981c -#define AR5K_AR5212_PHY_ENABLE 0x00000001 -#define AR5K_AR5212_PHY_DISABLE 0x00000002 - -/* - * PHY agility control register - */ -#define AR5K_AR5212_PHY_AGCCTL 0x9860 -#define AR5K_AR5212_PHY_AGCCTL_CAL 0x00000001 -#define AR5K_AR5212_PHY_AGCCTL_NF 0x00000002 - -/* - * PHY noise floor status register - */ -#define AR5K_AR5212_PHY_NF 0x9864 -#define AR5K_AR5212_PHY_NF_M 0x000001ff -#define AR5K_AR5212_PHY_NF_ACTIVE 0x00000100 -#define AR5K_AR5212_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5212_PHY_NF_M) -#define AR5K_AR5212_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5212_PHY_NF_M) + 1) -#define AR5K_AR5212_PHY_NF_SVAL(_n) (((_n) & AR5K_AR5212_PHY_NF_M) | (1 << 9)) - -/* - * PHY sleep registers - */ -#define AR5K_AR5212_PHY_SCR 0x9870 -#define AR5K_AR5212_PHY_SCR_32MHZ 0x0000001f -#define AR5K_AR5212_PHY_SLMT 0x9874 -#define AR5K_AR5212_PHY_SLMT_32MHZ 0x0000007f -#define AR5K_AR5212_PHY_SCAL 0x9878 -#define AR5K_AR5212_PHY_SCAL_32MHZ 0x0000000e - -/* - * PHY PLL control register - */ -#define AR5K_AR5212_PHY_PLL 0x987c -#define AR5K_AR5212_PHY_PLL_40MHZ 0x000000aa -#define AR5K_AR5212_PHY_PLL_44MHZ 0x000000ab -#define AR5K_AR5212_PHY_PLL_AR5111 0x00000000 -#define AR5K_AR5212_PHY_PLL_AR5112 0x00000040 - -/* - * PHY receiver delay register - */ -#define AR5K_AR5212_PHY_RX_DELAY 0x9914 -#define AR5K_AR5212_PHY_RX_DELAY_M 0x00003fff - -/* - * PHY timing IQ control register - */ -#define AR5K_AR5212_PHY_IQ 0x9920 -#define AR5K_AR5212_PHY_IQ_CORR_Q_Q_COFF 0x0000001f -#define AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF 0x000007e0 -#define AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S 5 -#define AR5K_AR5212_PHY_IQ_CORR_ENABLE 0x00000800 -#define AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 -#define AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX_S 12 -#define AR5K_AR5212_PHY_IQ_RUN 0x00010000 - -/* - * PHY PAPD probe register - */ -#define AR5K_AR5212_PHY_PAPD_PROBE 0x9930 -#define AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER 0x00007e00 -#define AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER_S 9 -#define AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT 0x00008000 -#define AR5K_AR5212_PHY_PAPD_PROBE_TYPE 0x01800000 -#define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_S 23 -#define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_OFDM 0 -#define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_XR 1 -#define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_CCK 2 -#define AR5K_AR5212_PHY_PAPD_PROBE_GAINF 0xfe000000 -#define AR5K_AR5212_PHY_PAPD_PROBE_GAINF_S 25 - -/* - * PHY TX power registers - */ -#define AR5K_AR5212_PHY_TXPOWER_RATE1 0x9934 -#define AR5K_AR5212_PHY_TXPOWER_RATE2 0x9938 -#define AR5K_AR5212_PHY_TXPOWER_RATE_MAX 0x993c -#define AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 -#define AR5K_AR5212_PHY_TXPOWER_RATE3 0xa234 -#define AR5K_AR5212_PHY_TXPOWER_RATE4 0xa238 - -/* - * PHY frame control register - */ -#define AR5K_AR5212_PHY_FC 0x9944 -#define AR5K_AR5212_PHY_FC_TX_CLIP 0x00000038 -#define AR5K_AR5212_PHY_FC_TX_CLIP_S 3 - -/* - * PHY radar detection enable register - */ -#define AR5K_AR5212_PHY_RADAR 0x9954 -#define AR5K_AR5212_PHY_RADAR_DISABLE 0x00000000 -#define AR5K_AR5212_PHY_RADAR_ENABLE 0x00000001 - -/* - * PHY antenna switch table registers - */ -#define AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0 0x9960 -#define AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1 0x9964 - -/* - * PHY clock sleep registers - */ -#define AR5K_AR5212_PHY_SCLOCK 0x99f0 -#define AR5K_AR5212_PHY_SCLOCK_32MHZ 0x0000000c -#define AR5K_AR5212_PHY_SDELAY 0x99f4 -#define AR5K_AR5212_PHY_SDELAY_32MHZ 0x000000ff -#define AR5K_AR5212_PHY_SPENDING 0x99f8 -#define AR5K_AR5212_PHY_SPENDING_AR5111 0x00000018 -#define AR5K_AR5212_PHY_SPENDING_AR5112 0x00000014 - -/* - * PHY timing IQ calibration result register - */ -#define AR5K_AR5212_PHY_IQRES_CAL_PWR_I 0x9c10 -#define AR5K_AR5212_PHY_IQRES_CAL_PWR_Q 0x9c14 -#define AR5K_AR5212_PHY_IQRES_CAL_CORR 0x9c18 - -/* - * PHY current RSSI register - */ -#define AR5K_AR5212_PHY_CURRENT_RSSI 0x9c1c - -/* - * PHY PCDAC TX power register - */ -#define AR5K_AR5212_PHY_PCDAC_TXPOWER(_n) (0xa180 + ((_n) << 2)) - -/* - * PHY mode register - */ -#define AR5K_AR5212_PHY_MODE 0x0a200 -#define AR5K_AR5212_PHY_MODE_MOD 0x00000001 -#define AR5K_AR5212_PHY_MODE_MOD_OFDM 0 -#define AR5K_AR5212_PHY_MODE_MOD_CCK 1 -#define AR5K_AR5212_PHY_MODE_FREQ 0x00000002 -#define AR5K_AR5212_PHY_MODE_FREQ_5GHZ 0 -#define AR5K_AR5212_PHY_MODE_FREQ_2GHZ 2 -#define AR5K_AR5212_PHY_MODE_MOD_DYN 0x00000004 -#define AR5K_AR5212_PHY_MODE_RAD 0x00000008 -#define AR5K_AR5212_PHY_MODE_RAD_AR5111 0 -#define AR5K_AR5212_PHY_MODE_RAD_AR5112 8 -#define AR5K_AR5212_PHY_MODE_XR 0x00000010 - -/* - * PHY CCK transmit control register - */ -#define AR5K_AR5212_PHY_CCKTXCTL 0xa204 -#define AR5K_AR5212_PHY_CCKTXCTL_WORLD 0x00000000 -#define AR5K_AR5212_PHY_CCKTXCTL_JAPAN 0x00000010 - -/* - * PHY 2GHz gain register - */ -#define AR5K_AR5212_PHY_GAIN_2GHZ 0xa20c -#define AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 -#define AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 - -#endif Index: ar5210var.h =================================================================== --- ar5210var.h (revision 2185) +++ ar5210var.h (revision 2232) @@ -1,439 +0,0 @@ -/* $OpenBSD: ar5210var.h,v 1.11 2005/12/18 17:59:58 reyk Exp $ */ - -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Specific definitions for the Atheros AR5000 Wireless LAN chipset - * (AR5210 + AR5110). - */ - -#ifndef _AR5K_AR5210_VAR_H -#define _AR5K_AR5210_VAR_H - -#include "ar5xxx.h" - -/* - * Define a "magic" code for the AR5210 (the HAL layer wants it) - */ - -#define AR5K_AR5210_MAGIC 0x0000145a /* 5210 */ -#define AR5K_AR5210_TX_NUM_QUEUES 2 - -#if BYTE_ORDER == BIG_ENDIAN -#define AR5K_AR5210_INIT_CFG ( \ - AR5K_AR5210_CFG_SWTD | AR5K_AR5210_CFG_SWRD \ -) -#else -#define AR5K_AR5210_INIT_CFG 0x00000000 -#endif - -/* - * Internal RX/TX descriptor structures - * (rX: reserved fields possibily used by future versions of the ar5k chipset) - */ - -struct ar5k_ar5210_rx_desc { - /* - * RX control word 0 - */ - u_int32_t rx_control_0; - -#define AR5K_AR5210_DESC_RX_CTL0 0x00000000 - - /* - * RX control word 1 - */ - u_int32_t rx_control_1; - -#define AR5K_AR5210_DESC_RX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5210_DESC_RX_CTL1_INTREQ 0x00002000 -} __packed; - -struct ar5k_ar5210_rx_status { - /* - * RX status word 0 - */ - u_int32_t rx_status_0; - -#define AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN 0x00000fff -#define AR5K_AR5210_DESC_RX_STATUS0_MORE 0x00001000 -#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x00004000 -#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000 -#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000 -#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19 - - /* - * RX status word 1 - */ - u_int32_t rx_status_1; - -#define AR5K_AR5210_DESC_RX_STATUS1_DONE 0x00000001 -#define AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008 -#define AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010 -#define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR 0x000000e0 -#define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR_S 5 -#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX 0x00007e00 -#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_S 9 -#define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 -#define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15 -#define AR5K_AR5210_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000 -} __packed; - -#define AR5K_AR5210_DESC_RX_PHY_ERROR_NONE 0x00 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_TIMING 0x20 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_PARITY 0x40 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_RATE 0x60 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_LENGTH 0x80 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_64QAM 0xa0 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_SERVICE 0xc0 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 - -struct ar5k_ar5210_tx_desc { - /* - * TX control word 0 - */ - u_int32_t tx_control_0; - -#define AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN 0x00000fff -#define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN 0x0003f000 -#define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN_S 12 -#define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE 0x003c0000 -#define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE_S 18 -#define AR5K_AR5210_DESC_TX_CTL0_RTSENA 0x00400000 -#define AR5K_AR5210_DESC_TX_CTL0_LONG_PACKET 0x00800000 -#define AR5K_AR5210_DESC_TX_CTL0_CLRDMASK 0x01000000 -#define AR5K_AR5210_DESC_TX_CTL0_ANT_MODE_XMIT 0x02000000 -#define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE 0x1c000000 -#define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE_S 26 -#define AR5K_AR5210_DESC_TX_CTL0_INTREQ 0x20000000 -#define AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 - - /* - * TX control word 1 - */ - u_int32_t tx_control_1; - -#define AR5K_AR5210_DESC_TX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5210_DESC_TX_CTL1_MORE 0x00001000 -#define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x0007e000 -#define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION 0xfff80000 -} __packed; - -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL 0x00 -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM 0x04 -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL 0x08 -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS 0x10 - -struct ar5k_ar5210_tx_status { - /* - * TX status word 0 - */ - u_int32_t tx_status_0; - -#define AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 -#define AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 -#define AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 -#define AR5K_AR5210_DESC_TX_STATUS0_FILTERED 0x00000008 -#define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 -#define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 -#define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 -#define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 -#define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 -#define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 - - /* - * TX status word 1 - */ - u_int32_t tx_status_1; - -#define AR5K_AR5210_DESC_TX_STATUS1_DONE 0x00000001 -#define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe -#define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM_S 1 -#define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 -#define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 -} __packed; - -/* - * Public function prototypes - */ -extern ar5k_attach_t ar5k_ar5210_attach; - -/* - * Initial mode settings ("Base Mode" or "Turbo Mode") - */ - -#define AR5K_AR5210_INI_MODE(_aifs) { \ - { AR5K_AR5210_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME_TURBO }, \ - { AR5K_AR5210_SLOT_TIME, \ - AR5K_INIT_ACK_CTS_TIMEOUT, \ - AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \ - { AR5K_AR5210_USEC, \ - AR5K_INIT_TRANSMIT_LATENCY, \ - AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \ - { AR5K_AR5210_IFS0, \ - ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ - << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS, \ - ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \ - << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \ - { AR5K_AR5210_IFS1, \ - AR5K_INIT_PROTO_TIME_CNTRL, \ - AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ - { AR5K_AR5210_PHY(17), \ - (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C, \ - (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x38 }, \ - { AR5K_AR5210_PHY_FC, \ - AR5K_AR5210_PHY_FC_SERVICE_ERR | \ - AR5K_AR5210_PHY_FC_TXURN_ERR | \ - AR5K_AR5210_PHY_FC_ILLLEN_ERR | \ - AR5K_AR5210_PHY_FC_ILLRATE_ERR | \ - AR5K_AR5210_PHY_FC_PARITY_ERR | \ - AR5K_AR5210_PHY_FC_TIMING_ERR | 0x1020, \ - AR5K_AR5210_PHY_FC_SERVICE_ERR | \ - AR5K_AR5210_PHY_FC_TXURN_ERR | \ - AR5K_AR5210_PHY_FC_ILLLEN_ERR | \ - AR5K_AR5210_PHY_FC_ILLRATE_ERR | \ - AR5K_AR5210_PHY_FC_PARITY_ERR | \ - AR5K_AR5210_PHY_FC_TURBO_MODE | \ - AR5K_AR5210_PHY_FC_TURBO_SHORT | \ - AR5K_AR5210_PHY_FC_TIMING_ERR | 0x2020 }, \ -} - -/* - * Initial register values which have to be loaded into the - * card at boot time and after each reset. - */ - -#define AR5K_AR5210_INI { \ - /* PCU and MAC registers */ \ - { AR5K_AR5210_TXDP0, 0 }, \ - { AR5K_AR5210_TXDP1, 0 }, \ - { AR5K_AR5210_RXDP, 0 }, \ - { AR5K_AR5210_CR, 0 }, \ - { AR5K_AR5210_ISR, 0, AR5K_INI_READ }, \ - { AR5K_AR5210_IMR, 0 }, \ - { AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE }, \ - { AR5K_AR5210_BSR, 0, AR5K_INI_READ }, \ - { AR5K_AR5210_TXCFG, AR5K_AR5210_DMASIZE_128B }, \ - { AR5K_AR5210_RXCFG, AR5K_AR5210_DMASIZE_128B }, \ - { AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG }, \ - { AR5K_AR5210_TOPS, AR5K_INIT_TOPS }, \ - { AR5K_AR5210_RXNOFRM, AR5K_INIT_RXNOFRM }, \ - { AR5K_AR5210_RPGTO, AR5K_INIT_RPGTO }, \ - { AR5K_AR5210_TXNOFRM, AR5K_INIT_TXNOFRM }, \ - { AR5K_AR5210_SFR, 0 }, \ - { AR5K_AR5210_MIBC, 0 }, \ - { AR5K_AR5210_MISC, 0 }, \ - { AR5K_AR5210_RX_FILTER, 0 }, \ - { AR5K_AR5210_MCAST_FIL0, 0 }, \ - { AR5K_AR5210_MCAST_FIL1, 0 }, \ - { AR5K_AR5210_TX_MASK0, 0 }, \ - { AR5K_AR5210_TX_MASK1, 0 }, \ - { AR5K_AR5210_CLR_TMASK, 0 }, \ - { AR5K_AR5210_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ - { AR5K_AR5210_DIAG_SW, 0 }, \ - { AR5K_AR5210_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ - { AR5K_AR5210_TSF_L32, 0 }, \ - { AR5K_AR5210_TIMER0, 0 }, \ - { AR5K_AR5210_TIMER1, 0xffffffff }, \ - { AR5K_AR5210_TIMER2, 0xffffffff }, \ - { AR5K_AR5210_TIMER3, 1 }, \ - { AR5K_AR5210_CFP_DUR, 0 }, \ - { AR5K_AR5210_CFP_PERIOD, 0 }, \ - /* PHY registers */ \ - { AR5K_AR5210_PHY(0), 0x00000047 }, \ - { AR5K_AR5210_PHY_AGC, 0x00000000 }, \ - { AR5K_AR5210_PHY(3), 0x09848ea6 }, \ - { AR5K_AR5210_PHY(4), 0x3d32e000 }, \ - { AR5K_AR5210_PHY(5), 0x0000076b }, \ - { AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE }, \ - { AR5K_AR5210_PHY(8), 0x02020200 }, \ - { AR5K_AR5210_PHY(9), 0x00000e0e }, \ - { AR5K_AR5210_PHY(10), 0x0a020201 }, \ - { AR5K_AR5210_PHY(11), 0x00036ffc }, \ - { AR5K_AR5210_PHY(12), 0x00000000 }, \ - { AR5K_AR5210_PHY(13), 0x00000e0e }, \ - { AR5K_AR5210_PHY(14), 0x00000007 }, \ - { AR5K_AR5210_PHY(15), 0x00020100 }, \ - { AR5K_AR5210_PHY(16), 0x89630000 }, \ - { AR5K_AR5210_PHY(17), 0x1372169c }, \ - { AR5K_AR5210_PHY(18), 0x0018b633 }, \ - { AR5K_AR5210_PHY(19), 0x1284613c }, \ - { AR5K_AR5210_PHY(20), 0x0de8b8e0 }, \ - { AR5K_AR5210_PHY(21), 0x00074859 }, \ - { AR5K_AR5210_PHY(22), 0x7e80beba }, \ - { AR5K_AR5210_PHY(23), 0x313a665e }, \ - { AR5K_AR5210_PHY_AGCCTL, 0x00001d08 }, \ - { AR5K_AR5210_PHY(25), 0x0001ce00 }, \ - { AR5K_AR5210_PHY(26), 0x409a4190 }, \ - { AR5K_AR5210_PHY(28), 0x0000000f }, \ - { AR5K_AR5210_PHY(29), 0x00000080 }, \ - { AR5K_AR5210_PHY(30), 0x00000004 }, \ - { AR5K_AR5210_PHY(31), 0x00000018 }, /* 0x987c */ \ - { AR5K_AR5210_PHY(64), 0x00000000 }, /* 0x9900 */ \ - { AR5K_AR5210_PHY(65), 0x00000000 }, \ - { AR5K_AR5210_PHY(66), 0x00000000 }, \ - { AR5K_AR5210_PHY(67), 0x00800000 }, \ - { AR5K_AR5210_PHY(68), 0x00000003 }, \ - /* BB gain table (64bytes) */ \ - { AR5K_AR5210_BB_GAIN(0), 0x00000000 }, \ - { AR5K_AR5210_BB_GAIN(0x01), 0x00000020 }, \ - { AR5K_AR5210_BB_GAIN(0x02), 0x00000010 }, \ - { AR5K_AR5210_BB_GAIN(0x03), 0x00000030 }, \ - { AR5K_AR5210_BB_GAIN(0x04), 0x00000008 }, \ - { AR5K_AR5210_BB_GAIN(0x05), 0x00000028 }, \ - { AR5K_AR5210_BB_GAIN(0x06), 0x00000028 }, \ - { AR5K_AR5210_BB_GAIN(0x07), 0x00000004 }, \ - { AR5K_AR5210_BB_GAIN(0x08), 0x00000024 }, \ - { AR5K_AR5210_BB_GAIN(0x09), 0x00000014 }, \ - { AR5K_AR5210_BB_GAIN(0x0a), 0x00000034 }, \ - { AR5K_AR5210_BB_GAIN(0x0b), 0x0000000c }, \ - { AR5K_AR5210_BB_GAIN(0x0c), 0x0000002c }, \ - { AR5K_AR5210_BB_GAIN(0x0d), 0x00000002 }, \ - { AR5K_AR5210_BB_GAIN(0x0e), 0x00000022 }, \ - { AR5K_AR5210_BB_GAIN(0x0f), 0x00000012 }, \ - { AR5K_AR5210_BB_GAIN(0x10), 0x00000032 }, \ - { AR5K_AR5210_BB_GAIN(0x11), 0x0000000a }, \ - { AR5K_AR5210_BB_GAIN(0x12), 0x0000002a }, \ - { AR5K_AR5210_BB_GAIN(0x13), 0x00000001 }, \ - { AR5K_AR5210_BB_GAIN(0x14), 0x00000021 }, \ - { AR5K_AR5210_BB_GAIN(0x15), 0x00000011 }, \ - { AR5K_AR5210_BB_GAIN(0x16), 0x00000031 }, \ - { AR5K_AR5210_BB_GAIN(0x17), 0x00000009 }, \ - { AR5K_AR5210_BB_GAIN(0x18), 0x00000029 }, \ - { AR5K_AR5210_BB_GAIN(0x19), 0x00000005 }, \ - { AR5K_AR5210_BB_GAIN(0x1a), 0x00000025 }, \ - { AR5K_AR5210_BB_GAIN(0x1b), 0x00000015 }, \ - { AR5K_AR5210_BB_GAIN(0x1c), 0x00000035 }, \ - { AR5K_AR5210_BB_GAIN(0x1d), 0x0000000d }, \ - { AR5K_AR5210_BB_GAIN(0x1e), 0x0000002d }, \ - { AR5K_AR5210_BB_GAIN(0x1f), 0x00000003 }, \ - { AR5K_AR5210_BB_GAIN(0x20), 0x00000023 }, \ - { AR5K_AR5210_BB_GAIN(0x21), 0x00000013 }, \ - { AR5K_AR5210_BB_GAIN(0x22), 0x00000033 }, \ - { AR5K_AR5210_BB_GAIN(0x23), 0x0000000b }, \ - { AR5K_AR5210_BB_GAIN(0x24), 0x0000002b }, \ - { AR5K_AR5210_BB_GAIN(0x25), 0x00000007 }, \ - { AR5K_AR5210_BB_GAIN(0x26), 0x00000027 }, \ - { AR5K_AR5210_BB_GAIN(0x27), 0x00000017 }, \ - { AR5K_AR5210_BB_GAIN(0x28), 0x00000037 }, \ - { AR5K_AR5210_BB_GAIN(0x29), 0x0000000f }, \ - { AR5K_AR5210_BB_GAIN(0x2a), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x2b), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x2c), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x2d), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x2e), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x2f), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x30), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x31), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x32), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x33), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x34), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x35), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x36), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x37), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x38), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x39), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x3a), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x3b), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x3c), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x3d), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x3e), 0x0000002f }, \ - { AR5K_AR5210_BB_GAIN(0x3f), 0x0000002f }, \ - /* RF gain table (64bytes) */ \ - { AR5K_AR5210_RF_GAIN(0), 0x0000001d }, \ - { AR5K_AR5210_RF_GAIN(0x01), 0x0000005d }, \ - { AR5K_AR5210_RF_GAIN(0x02), 0x0000009d }, \ - { AR5K_AR5210_RF_GAIN(0x03), 0x000000dd }, \ - { AR5K_AR5210_RF_GAIN(0x04), 0x0000011d }, \ - { AR5K_AR5210_RF_GAIN(0x05), 0x00000021 }, \ - { AR5K_AR5210_RF_GAIN(0x06), 0x00000061 }, \ - { AR5K_AR5210_RF_GAIN(0x07), 0x000000a1 }, \ - { AR5K_AR5210_RF_GAIN(0x08), 0x000000e1 }, \ - { AR5K_AR5210_RF_GAIN(0x09), 0x00000031 }, \ - { AR5K_AR5210_RF_GAIN(0x0a), 0x00000071 }, \ - { AR5K_AR5210_RF_GAIN(0x0b), 0x000000b1 }, \ - { AR5K_AR5210_RF_GAIN(0x0c), 0x0000001c }, \ - { AR5K_AR5210_RF_GAIN(0x0d), 0x0000005c }, \ - { AR5K_AR5210_RF_GAIN(0x0e), 0x00000029 }, \ - { AR5K_AR5210_RF_GAIN(0x0f), 0x00000069 }, \ - { AR5K_AR5210_RF_GAIN(0x10), 0x000000a9 }, \ - { AR5K_AR5210_RF_GAIN(0x11), 0x00000020 }, \ - { AR5K_AR5210_RF_GAIN(0x12), 0x00000019 }, \ - { AR5K_AR5210_RF_GAIN(0x13), 0x00000059 }, \ - { AR5K_AR5210_RF_GAIN(0x14), 0x00000099 }, \ - { AR5K_AR5210_RF_GAIN(0x15), 0x00000030 }, \ - { AR5K_AR5210_RF_GAIN(0x16), 0x00000005 }, \ - { AR5K_AR5210_RF_GAIN(0x17), 0x00000025 }, \ - { AR5K_AR5210_RF_GAIN(0x18), 0x00000065 }, \ - { AR5K_AR5210_RF_GAIN(0x19), 0x000000a5 }, \ - { AR5K_AR5210_RF_GAIN(0x1a), 0x00000028 }, \ - { AR5K_AR5210_RF_GAIN(0x1b), 0x00000068 }, \ - { AR5K_AR5210_RF_GAIN(0x1c), 0x0000001f }, \ - { AR5K_AR5210_RF_GAIN(0x1d), 0x0000001e }, \ - { AR5K_AR5210_RF_GAIN(0x1e), 0x00000018 }, \ - { AR5K_AR5210_RF_GAIN(0x1f), 0x00000058 }, \ - { AR5K_AR5210_RF_GAIN(0x20), 0x00000098 }, \ - { AR5K_AR5210_RF_GAIN(0x21), 0x00000003 }, \ - { AR5K_AR5210_RF_GAIN(0x22), 0x00000004 }, \ - { AR5K_AR5210_RF_GAIN(0x23), 0x00000044 }, \ - { AR5K_AR5210_RF_GAIN(0x24), 0x00000084 }, \ - { AR5K_AR5210_RF_GAIN(0x25), 0x00000013 }, \ - { AR5K_AR5210_RF_GAIN(0x26), 0x00000012 }, \ - { AR5K_AR5210_RF_GAIN(0x27), 0x00000052 }, \ - { AR5K_AR5210_RF_GAIN(0x28), 0x00000092 }, \ - { AR5K_AR5210_RF_GAIN(0x29), 0x000000d2 }, \ - { AR5K_AR5210_RF_GAIN(0x2a), 0x0000002b }, \ - { AR5K_AR5210_RF_GAIN(0x2b), 0x0000002a }, \ - { AR5K_AR5210_RF_GAIN(0x2c), 0x0000006a }, \ - { AR5K_AR5210_RF_GAIN(0x2d), 0x000000aa }, \ - { AR5K_AR5210_RF_GAIN(0x2e), 0x0000001b }, \ - { AR5K_AR5210_RF_GAIN(0x2f), 0x0000001a }, \ - { AR5K_AR5210_RF_GAIN(0x30), 0x0000005a }, \ - { AR5K_AR5210_RF_GAIN(0x31), 0x0000009a }, \ - { AR5K_AR5210_RF_GAIN(0x32), 0x000000da }, \ - { AR5K_AR5210_RF_GAIN(0x33), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x34), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x35), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x36), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x37), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x38), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x39), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x3a), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x3b), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x3c), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x3d), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x3e), 0x00000006 }, \ - { AR5K_AR5210_RF_GAIN(0x3f), 0x00000006 }, \ - /* PHY activation */ \ - { AR5K_AR5210_PHY(53), 0x00000020 }, \ - { AR5K_AR5210_PHY(51), 0x00000004 }, \ - { AR5K_AR5210_PHY(50), 0x00060106 }, \ - { AR5K_AR5210_PHY(39), 0x0000006d }, \ - { AR5K_AR5210_PHY(48), 0x00000000 }, \ - { AR5K_AR5210_PHY(52), 0x00000014 }, \ - { AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE }, \ -} - -#endif /* _AR5K_AR5210_VAR_H */ Index: ar5211var.h =================================================================== --- ar5211var.h (revision 2185) +++ ar5211var.h (revision 2232) @@ -1,464 +0,0 @@ -/* $OpenBSD: ar5211var.h,v 1.7 2005/12/18 17:59:58 reyk Exp $ */ - -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Specific definitions for the Atheros AR5001 Wireless LAN chipset - * (AR5211/AR5311). - */ - -#ifndef _AR5K_AR5211_VAR_H -#define _AR5K_AR5211_VAR_H - -#include "ar5xxx.h" - -/* - * Define a "magic" code for the AR5211 (the HAL layer wants it) - */ - -#define AR5K_AR5211_MAGIC 0x0000145b /* 5211 */ -#define AR5K_AR5211_TX_NUM_QUEUES 10 - -#if BYTE_ORDER == BIG_ENDIAN -#define AR5K_AR5211_INIT_CFG ( \ - AR5K_AR5211_CFG_SWTD | AR5K_AR5211_CFG_SWRD \ -) -#else -#define AR5K_AR5211_INIT_CFG 0x00000000 -#endif - -/* - * Internal RX/TX descriptor structures - * (rX: reserved fields possibily used by future versions of the ar5k chipset) - */ - -struct ar5k_ar5211_rx_desc { - /* - * RX control word 0 - */ - u_int32_t rx_control_0; - -#define AR5K_AR5211_DESC_RX_CTL0 0x00000000 - - /* - * RX control word 1 - */ - u_int32_t rx_control_1; - -#define AR5K_AR5211_DESC_RX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5211_DESC_RX_CTL1_INTREQ 0x00002000 -} __packed; - -struct ar5k_ar5211_rx_status { - /* - * RX status word 0 - */ - u_int32_t rx_status_0; - -#define AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN 0x00000fff -#define AR5K_AR5211_DESC_RX_STATUS0_MORE 0x00001000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x38000000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 27 - - /* - * RX status word 1 - */ - u_int32_t rx_status_1; - -#define AR5K_AR5211_DESC_RX_STATUS1_DONE 0x00000001 -#define AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_AR5211_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008 -#define AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010 -#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR 0x000000e0 -#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR_S 5 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX 0x00007e00 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_S 9 -#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 -#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000 -} __packed; - -#define AR5K_AR5211_DESC_RX_PHY_ERROR_NONE 0x00 -#define AR5K_AR5211_DESC_RX_PHY_ERROR_TIMING 0x20 -#define AR5K_AR5211_DESC_RX_PHY_ERROR_PARITY 0x40 -#define AR5K_AR5211_DESC_RX_PHY_ERROR_RATE 0x60 -#define AR5K_AR5211_DESC_RX_PHY_ERROR_LENGTH 0x80 -#define AR5K_AR5211_DESC_RX_PHY_ERROR_64QAM 0xa0 -#define AR5K_AR5211_DESC_RX_PHY_ERROR_SERVICE 0xc0 -#define AR5K_AR5211_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 - -struct ar5k_ar5211_tx_desc { - /* - * TX control word 0 - */ - u_int32_t tx_control_0; - -#define AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN 0x00000fff -#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE 0x003c0000 -#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE_S 18 -#define AR5K_AR5211_DESC_TX_CTL0_RTSENA 0x00400000 -#define AR5K_AR5211_DESC_TX_CTL0_VEOL 0x00800000 -#define AR5K_AR5211_DESC_TX_CTL0_CLRDMASK 0x01000000 -#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000 -#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_AR5211_DESC_TX_CTL0_INTREQ 0x20000000 -#define AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 - - /* - * TX control word 1 - */ - u_int32_t tx_control_1; - -#define AR5K_AR5211_DESC_TX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5211_DESC_TX_CTL1_MORE 0x00001000 -#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 -#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE 0x00700000 -#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE_S 20 -#define AR5K_AR5211_DESC_TX_CTL1_NOACK 0x00800000 -} __packed; - -struct ar5k_ar5211_tx_status { - /* - * TX status word 0 - */ - u_int32_t tx_status_0; - -#define AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 -#define AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 -#define AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 -#define AR5K_AR5211_DESC_TX_STATUS0_FILTERED 0x00000008 -#define AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 -#define AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 -#define AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 -#define AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 -#define AR5K_AR5211_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 -#define AR5K_AR5211_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 -#define AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 -#define AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 - - /* - * TX status word 1 - */ - u_int32_t tx_status_1; - -#define AR5K_AR5211_DESC_TX_STATUS1_DONE 0x00000001 -#define AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe -#define AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM_S 1 -#define AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 -#define AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 -} __packed; - -/* - * Public function prototypes - */ -extern ar5k_attach_t ar5k_ar5211_attach; - -/* - * Initial register values which have to be loaded into the - * card at boot time and after each reset. - */ - -#define AR5K_AR5211_INI { \ - { 0x000c, 0x00000000 }, \ - { 0x0028, 0x84849c9c }, \ - { 0x002c, 0x7c7c7c7c }, \ - { 0x0034, 0x00000005 }, \ - { 0x0040, 0x00000000 }, \ - { 0x0044, 0x00000008 }, \ - { 0x0048, 0x00000008 }, \ - { 0x004c, 0x00000010 }, \ - { 0x0050, 0x00000000 }, \ - { 0x0054, 0x0000001f }, \ - { 0x0800, 0x00000000 }, \ - { 0x0804, 0x00000000 }, \ - { 0x0808, 0x00000000 }, \ - { 0x080c, 0x00000000 }, \ - { 0x0810, 0x00000000 }, \ - { 0x0814, 0x00000000 }, \ - { 0x0818, 0x00000000 }, \ - { 0x081c, 0x00000000 }, \ - { 0x0820, 0x00000000 }, \ - { 0x0824, 0x00000000 }, \ - { 0x1230, 0x00000000 }, \ - { 0x8004, 0x00000000 }, \ - { 0x8008, 0x00000000 }, \ - { 0x800c, 0x00000000 }, \ - { 0x8018, 0x00000000 }, \ - { 0x8024, 0x00000000 }, \ - { 0x8028, 0x00000030 }, \ - { 0x802c, 0x0007ffff }, \ - { 0x8030, 0x01ffffff }, \ - { 0x8034, 0x00000031 }, \ - { 0x8038, 0x00000000 }, \ - { 0x803c, 0x00000000 }, \ - { 0x8040, 0x00000000 }, \ - { 0x8044, 0x00000002 }, \ - { 0x8048, 0x00000000 }, \ - { 0x8054, 0x00000000 }, \ - { 0x8058, 0x00000000 }, \ - /* PHY registers */ \ - { 0x9808, 0x00000000 }, \ - { 0x980c, 0x2d849093 }, \ - { 0x9810, 0x7d32e000 }, \ - { 0x9814, 0x00000f6b }, \ - { 0x981c, 0x00000000 }, \ - { 0x982c, 0x00026ffe }, \ - { 0x9830, 0x00000000 }, \ - { 0x983c, 0x00020100 }, \ - { 0x9840, 0x206a017a }, \ - { 0x984c, 0x1284613c }, \ - { 0x9854, 0x00000859 }, \ - { 0x9868, 0x409a4190 }, \ - { 0x986c, 0x050cb081 }, \ - { 0x9870, 0x0000000f }, \ - { 0x9874, 0x00000080 }, \ - { 0x9878, 0x0000000c }, \ - { 0x9900, 0x00000000 }, \ - { 0x9904, 0x00000000 }, \ - { 0x9908, 0x00000000 }, \ - { 0x990c, 0x00800000 }, \ - { 0x9910, 0x00000001 }, \ - { 0x991c, 0x0000092a }, \ - { 0x9920, 0x00000000 }, \ - { 0x9924, 0x00058a05 }, \ - { 0x9928, 0x00000001 }, \ - { 0x992c, 0x00000000 }, \ - { 0x9930, 0x00000000 }, \ - { 0x9934, 0x00000000 }, \ - { 0x9938, 0x00000000 }, \ - { 0x993c, 0x0000003f }, \ - { 0x9940, 0x00000004 }, \ - { 0x9948, 0x00000000 }, \ - { 0x994c, 0x00000000 }, \ - { 0x9950, 0x00000000 }, \ - { 0x9954, 0x5d50f14c }, \ - { 0x9958, 0x00000018 }, \ - { 0x995c, 0x004b6a8e }, \ - { 0xa184, 0x06ff05ff }, \ - { 0xa188, 0x07ff07ff }, \ - { 0xa18c, 0x08ff08ff }, \ - { 0xa190, 0x09ff09ff }, \ - { 0xa194, 0x0aff0aff }, \ - { 0xa198, 0x0bff0bff }, \ - { 0xa19c, 0x0cff0cff }, \ - { 0xa1a0, 0x0dff0dff }, \ - { 0xa1a4, 0x0fff0eff }, \ - { 0xa1a8, 0x12ff12ff }, \ - { 0xa1ac, 0x14ff13ff }, \ - { 0xa1b0, 0x16ff15ff }, \ - { 0xa1b4, 0x19ff17ff }, \ - { 0xa1b8, 0x1bff1aff }, \ - { 0xa1bc, 0x1eff1dff }, \ - { 0xa1c0, 0x23ff20ff }, \ - { 0xa1c4, 0x27ff25ff }, \ - { 0xa1c8, 0x2cff29ff }, \ - { 0xa1cc, 0x31ff2fff }, \ - { 0xa1d0, 0x37ff34ff }, \ - { 0xa1d4, 0x3aff3aff }, \ - { 0xa1d8, 0x3aff3aff }, \ - { 0xa1dc, 0x3aff3aff }, \ - { 0xa1e0, 0x3aff3aff }, \ - { 0xa1e4, 0x3aff3aff }, \ - { 0xa1e8, 0x3aff3aff }, \ - { 0xa1ec, 0x3aff3aff }, \ - { 0xa1f0, 0x3aff3aff }, \ - { 0xa1f4, 0x3aff3aff }, \ - { 0xa1f8, 0x3aff3aff }, \ - { 0xa1fc, 0x3aff3aff }, \ - /* BB gain table (64bytes) */ \ - { 0x9b00, 0x00000000 }, \ - { 0x9b04, 0x00000020 }, \ - { 0x9b08, 0x00000010 }, \ - { 0x9b0c, 0x00000030 }, \ - { 0x9b10, 0x00000008 }, \ - { 0x9b14, 0x00000028 }, \ - { 0x9b18, 0x00000004 }, \ - { 0x9b1c, 0x00000024 }, \ - { 0x9b20, 0x00000014 }, \ - { 0x9b24, 0x00000034 }, \ - { 0x9b28, 0x0000000c }, \ - { 0x9b2c, 0x0000002c }, \ - { 0x9b30, 0x00000002 }, \ - { 0x9b34, 0x00000022 }, \ - { 0x9b38, 0x00000012 }, \ - { 0x9b3c, 0x00000032 }, \ - { 0x9b40, 0x0000000a }, \ - { 0x9b44, 0x0000002a }, \ - { 0x9b48, 0x00000006 }, \ - { 0x9b4c, 0x00000026 }, \ - { 0x9b50, 0x00000016 }, \ - { 0x9b54, 0x00000036 }, \ - { 0x9b58, 0x0000000e }, \ - { 0x9b5c, 0x0000002e }, \ - { 0x9b60, 0x00000001 }, \ - { 0x9b64, 0x00000021 }, \ - { 0x9b68, 0x00000011 }, \ - { 0x9b6c, 0x00000031 }, \ - { 0x9b70, 0x00000009 }, \ - { 0x9b74, 0x00000029 }, \ - { 0x9b78, 0x00000005 }, \ - { 0x9b7c, 0x00000025 }, \ - { 0x9b80, 0x00000015 }, \ - { 0x9b84, 0x00000035 }, \ - { 0x9b88, 0x0000000d }, \ - { 0x9b8c, 0x0000002d }, \ - { 0x9b90, 0x00000003 }, \ - { 0x9b94, 0x00000023 }, \ - { 0x9b98, 0x00000013 }, \ - { 0x9b9c, 0x00000033 }, \ - { 0x9ba0, 0x0000000b }, \ - { 0x9ba4, 0x0000002b }, \ - { 0x9ba8, 0x0000002b }, \ - { 0x9bac, 0x0000002b }, \ - { 0x9bb0, 0x0000002b }, \ - { 0x9bb4, 0x0000002b }, \ - { 0x9bb8, 0x0000002b }, \ - { 0x9bbc, 0x0000002b }, \ - { 0x9bc0, 0x0000002b }, \ - { 0x9bc4, 0x0000002b }, \ - { 0x9bc8, 0x0000002b }, \ - { 0x9bcc, 0x0000002b }, \ - { 0x9bd0, 0x0000002b }, \ - { 0x9bd4, 0x0000002b }, \ - { 0x9bd8, 0x0000002b }, \ - { 0x9bdc, 0x0000002b }, \ - { 0x9be0, 0x0000002b }, \ - { 0x9be4, 0x0000002b }, \ - { 0x9be8, 0x0000002b }, \ - { 0x9bec, 0x0000002b }, \ - { 0x9bf0, 0x0000002b }, \ - { 0x9bf4, 0x0000002b }, \ - { 0x9bf8, 0x00000002 }, \ - { 0x9bfc, 0x00000016 }, \ - /* PHY activation */ \ - { 0x98d4, 0x00000020 }, \ - { 0x98d8, 0x00601068 }, \ -} - -struct ar5k_ar5211_ini_mode { - u_int16_t mode_register; - u_int32_t mode_value[4]; -}; - -#define AR5K_AR5211_INI_MODE { \ - { 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \ - { 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, \ - { 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, \ - { 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, \ - { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, \ - { 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, \ - { 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, \ - { 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, \ - { 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, \ - { 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, \ - { 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, \ - { 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ - { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, \ - { 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, \ - { 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, \ - { 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \ - { 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, \ - { 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, \ - { 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, \ - { 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ - { 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, \ - { 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, \ - { 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, \ - { 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, \ - { 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, \ -} - -struct ar5k_ar5211_ini_rf { - u_int16_t rf_register; - u_int32_t rf_value[2]; -}; - -#define AR5K_AR5211_INI_RF { \ - { 0x0000a204, { 0x00000000, 0x00000000 } }, \ - { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \ - { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \ - { 0x0000a210, { 0x0199a003, 0x0199a003 } }, \ - { 0x0000a214, { 0x044cd610, 0x044cd610 } }, \ - { 0x0000a218, { 0x13800040, 0x13800040 } }, \ - { 0x0000a21c, { 0x1be00060, 0x1be00060 } }, \ - { 0x0000a220, { 0x0c53800a, 0x0c53800a } }, \ - { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \ - { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \ - { 0x0000a22c, { 0x00000020, 0x00000020 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00380000, 0x00380000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \ - { 0x000098d4, { 0x00000000, 0x00000004 } }, \ - \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x10000000, 0x10000000 } }, \ - { 0x0000989c, { 0x04000000, 0x04000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x0a000000 } }, \ - { 0x0000989c, { 0x00380080, 0x02380080 } }, \ - { 0x0000989c, { 0x00020006, 0x00000006 } }, \ - { 0x0000989c, { 0x00000092, 0x00000092 } }, \ - { 0x0000989c, { 0x000000a0, 0x000000a0 } }, \ - { 0x0000989c, { 0x00040007, 0x00040007 } }, \ - { 0x000098d4, { 0x0000001a, 0x0000001a } }, \ - { 0x0000989c, { 0x00000048, 0x00000048 } }, \ - { 0x0000989c, { 0x00000010, 0x00000010 } }, \ - { 0x0000989c, { 0x00000008, 0x00000008 } }, \ - { 0x0000989c, { 0x0000000f, 0x0000000f } }, \ - { 0x0000989c, { 0x000000f2, 0x00000062 } }, \ - { 0x0000989c, { 0x0000904f, 0x0000904c } }, \ - { 0x0000989c, { 0x0000125a, 0x0000129a } }, \ - { 0x000098cc, { 0x0000000e, 0x0000000f } }, \ -} - -#endif /* _AR5K_AR5211_VAR_H */ Index: ar5212var.h =================================================================== --- ar5212var.h (revision 2185) +++ ar5212var.h (revision 2232) @@ -1,798 +0,0 @@ -/* $OpenBSD: ar5212var.h,v 1.10 2005/12/18 17:59:58 reyk Exp $ */ - -/* - * Copyright (c) 2004, 2005 Reyk Floeter - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Specific definitions for the Atheros AR5001 Wireless LAN chipset - * (AR5212/AR5311). - */ - -#ifndef _AR5K_AR5212_VAR_H -#define _AR5K_AR5212_VAR_H - -#include "ar5xxx.h" - -/* - * Define a "magic" code for the AR5212 (the HAL layer wants it) - */ - -#define AR5K_AR5212_MAGIC 0x0000145c /* 5212 */ -#define AR5K_AR5212_TX_NUM_QUEUES 10 - -#if BYTE_ORDER == BIG_ENDIAN -#define AR5K_AR5212_INIT_CFG ( \ - AR5K_AR5212_CFG_SWTD | AR5K_AR5212_CFG_SWRD \ -) -#else -#define AR5K_AR5212_INIT_CFG 0x00000000 -#endif - -/* - * Internal RX/TX descriptor structures - * (rX: reserved fields possibily used by future versions of the ar5k chipset) - */ - -struct ar5k_ar5212_rx_desc { - /* - * RX control word 0 - */ - u_int32_t rx_control_0; - -#define AR5K_AR5212_DESC_RX_CTL0 0x00000000 - - /* - * RX control word 1 - */ - u_int32_t rx_control_1; - -#define AR5K_AR5212_DESC_RX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5212_DESC_RX_CTL1_INTREQ 0x00002000 -} __packed; - -struct ar5k_ar5212_rx_status { - /* - * RX status word 0 - */ - u_int32_t rx_status_0; - -#define AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN 0x00000fff -#define AR5K_AR5212_DESC_RX_STATUS0_MORE 0x00001000 -#define AR5K_AR5212_DESC_RX_STATUS0_DECOMP_CRC_ERROR 0x00002000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE 0x000f8000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x0ff00000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 20 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA 0xf0000000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 28 - - /* - * RX status word 1 - */ - u_int32_t rx_status_1; - -#define AR5K_AR5212_DESC_RX_STATUS1_DONE 0x00000001 -#define AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000008 -#define AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR 0x00000010 -#define AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR 0x00000020 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX 0x0000fe00 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_S 9 -#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 -#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 16 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_CACHE_MISS 0x80000000 -} __packed; - -struct ar5k_ar5212_rx_error { - /* - * RX error word 0 - */ - u_int32_t rx_error_0; - -#define AR5K_AR5212_DESC_RX_ERROR0 0x00000000 - - /* - * RX error word 1 - */ - u_int32_t rx_error_1; - -#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE 0x0000ff00 -#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE_S 8 -} __packed; - -#define AR5K_AR5212_DESC_RX_PHY_ERROR_NONE 0x00 -#define AR5K_AR5212_DESC_RX_PHY_ERROR_TIMING 0x20 -#define AR5K_AR5212_DESC_RX_PHY_ERROR_PARITY 0x40 -#define AR5K_AR5212_DESC_RX_PHY_ERROR_RATE 0x60 -#define AR5K_AR5212_DESC_RX_PHY_ERROR_LENGTH 0x80 -#define AR5K_AR5212_DESC_RX_PHY_ERROR_64QAM 0xa0 -#define AR5K_AR5212_DESC_RX_PHY_ERROR_SERVICE 0xc0 -#define AR5K_AR5212_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 - -struct ar5k_ar5212_tx_desc { - /* - * TX control word 0 - */ - u_int32_t tx_control_0; - -#define AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN 0x00000fff -#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER 0x003f0000 -#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER_S 16 -#define AR5K_AR5212_DESC_TX_CTL0_RTSENA 0x00400000 -#define AR5K_AR5212_DESC_TX_CTL0_VEOL 0x00800000 -#define AR5K_AR5212_DESC_TX_CTL0_CLRDMASK 0x01000000 -#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000 -#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_AR5212_DESC_TX_CTL0_INTREQ 0x20000000 -#define AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 -#define AR5K_AR5212_DESC_TX_CTL0_CTSENA 0x80000000 - - /* - * TX control word 1 - */ - u_int32_t tx_control_1; - -#define AR5K_AR5212_DESC_TX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5212_DESC_TX_CTL1_MORE 0x00001000 -#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 -#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE 0x00f00000 -#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE_S 20 -#define AR5K_AR5212_DESC_TX_CTL1_NOACK 0x01000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC 0x06000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC_S 25 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN 0x18000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN_S 27 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN 0x60000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN_S 29 - - /* - * TX control word 2 - */ - u_int32_t tx_control_2; - -#define AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION 0x00007fff -#define AR5K_AR5212_DESC_TX_CTL2_DURATION_UPDATE_ENABLE 0x00008000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0 0x000f0000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0_S 16 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1 0x00f00000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1_S 20 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2 0x0f000000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2_S 24 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3 0xf0000000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3_S 28 - - /* - * TX control word 3 - */ - u_int32_t tx_control_3; - -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0 0x0000001f -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1 0x000003e0 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1_S 5 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2 0x00007c00 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2_S 10 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3 0x000f8000 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3_S 15 -#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE 0x01f00000 -#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE_S 20 -} __packed; - -struct ar5k_ar5212_tx_status { - /* - * TX status word 0 - */ - u_int32_t tx_status_0; - -#define AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 -#define AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 -#define AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 -#define AR5K_AR5212_DESC_TX_STATUS0_FILTERED 0x00000008 -#define AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 -#define AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 -#define AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 -#define AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 -#define AR5K_AR5212_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 -#define AR5K_AR5212_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 -#define AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 -#define AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 - - /* - * TX status word 1 - */ - u_int32_t tx_status_1; - -#define AR5K_AR5212_DESC_TX_STATUS1_DONE 0x00000001 -#define AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe -#define AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM_S 1 -#define AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 -#define AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 -#define AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 -#define AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 -#define AR5K_AR5212_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 -#define AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 -} __packed; - -/* - * Public function prototypes - */ -extern ar5k_attach_t ar5k_ar5212_attach; - -/* - * Initial register values which have to be loaded into the - * card at boot time and after each reset. - */ - -struct ar5k_ar5212_ini { - u_int8_t ini_flags; - u_int16_t ini_register; - u_int32_t ini_value; - -#define AR5K_INI_FLAG_511X 0x00 -#define AR5K_INI_FLAG_5111 0x01 -#define AR5K_INI_FLAG_5112 0x02 -#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) -}; - -#define AR5K_AR5212_INI { \ - { AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 }, \ - { AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 }, \ - { AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f }, \ - { AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x081c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0820, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0824, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1230, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1270, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1078, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1138, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1178, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1238, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1278, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1338, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1378, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1438, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1478, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1538, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1578, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1638, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1678, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1738, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1778, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x103c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x107c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x113c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x117c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x123c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x127c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x133c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x137c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x143c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x147c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8004, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8008, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x800c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8018, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8020, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8024, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8028, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x802c, 0x0007ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8030, 0x01ffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8034, 0x00000031 }, \ - { AR5K_INI_FLAG_BOTH, 0x8038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x803c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8048, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8054, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8058, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x805c, 0xffffc7ff }, \ - { AR5K_INI_FLAG_BOTH, 0x8080, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8084, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8088, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x808c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8090, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8094, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8098, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c0, 0x2a82301a }, \ - { AR5K_INI_FLAG_BOTH, 0x80c4, 0x05dc01e0 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c8, 0x1f402710 }, \ - { AR5K_INI_FLAG_BOTH, 0x80cc, 0x01f40000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80d0, 0x00001e1c }, \ - { AR5K_INI_FLAG_BOTH, 0x80d4, 0x0002aaaa }, \ - { AR5K_INI_FLAG_BOTH, 0x80d8, 0x02005555 }, \ - { AR5K_INI_FLAG_BOTH, 0x80dc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80e0, 0xffffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e4, 0x0000ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80ec, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f0, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f4, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80fc, 0x00000088 }, \ - { AR5K_INI_FLAG_BOTH, 0x8700, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8704, 0x0000008c }, \ - { AR5K_INI_FLAG_BOTH, 0x8708, 0x000000e4 }, \ - { AR5K_INI_FLAG_BOTH, 0x870c, 0x000002d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8710, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8714, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8718, 0x000000a0 }, \ - { AR5K_INI_FLAG_BOTH, 0x871c, 0x000001c9 }, \ - { AR5K_INI_FLAG_BOTH, 0x8720, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8724, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8728, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x872c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8730, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8734, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8738, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x873c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8740, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8744, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8748, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x874c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8750, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8754, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8758, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x875c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8760, 0x000000d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8764, 0x000000df }, \ - { AR5K_INI_FLAG_BOTH, 0x8768, 0x00000102 }, \ - { AR5K_INI_FLAG_BOTH, 0x876c, 0x0000013a }, \ - { AR5K_INI_FLAG_BOTH, 0x8770, 0x00000075 }, \ - { AR5K_INI_FLAG_BOTH, 0x8774, 0x0000007f }, \ - { AR5K_INI_FLAG_BOTH, 0x8778, 0x000000a2 }, \ - { AR5K_INI_FLAG_BOTH, 0x877c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8100, 0x00010002 }, \ - { AR5K_INI_FLAG_BOTH, 0x8104, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x8108, 0x000000c0 }, \ - { AR5K_INI_FLAG_BOTH, 0x810c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8110, 0x00000168 }, \ - { AR5K_INI_FLAG_BOTH, 0x8114, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87cc, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87d0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87dc, 0x1f1e1d1c }, \ - { AR5K_INI_FLAG_BOTH, 0x87e0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87ec, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87f0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87fc, 0x1f1e1d1c }, \ - /* PHY registers */ \ - { AR5K_INI_FLAG_BOTH, 0x9808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x980c, 0xad848e19 }, \ - { AR5K_INI_FLAG_BOTH, 0x9810, 0x7d28e000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9814, 0x9c0a9f6b }, \ - { AR5K_INI_FLAG_BOTH, 0x981c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x982c, 0x00022ffe }, \ - { AR5K_INI_FLAG_BOTH, 0x983c, 0x00020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x9840, 0x206a017a }, \ - { AR5K_INI_FLAG_BOTH, 0x984c, 0x1284613c }, \ - { AR5K_INI_FLAG_BOTH, 0x9854, 0x00000859 }, \ - { AR5K_INI_FLAG_BOTH, 0x9900, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9904, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a }, \ - { AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9934, 0x1e1f2022 }, \ - { AR5K_INI_FLAG_BOTH, 0x9938, 0x0a0b0c0d }, \ - { AR5K_INI_FLAG_BOTH, 0x993c, 0x0000003f }, \ - { AR5K_INI_FLAG_BOTH, 0x9940, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9948, 0x9280b212 }, \ - { AR5K_INI_FLAG_BOTH, 0x9954, 0x5d50e188 }, \ - { AR5K_INI_FLAG_BOTH, 0x9958, 0x000000ff }, \ - { AR5K_INI_FLAG_BOTH, 0x995c, 0x004b6a8e }, \ - { AR5K_INI_FLAG_BOTH, 0x9968, 0x000003ce }, \ - { AR5K_INI_FLAG_BOTH, 0x9970, 0x192fb515 }, \ - { AR5K_INI_FLAG_BOTH, 0x9974, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9978, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x997c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa184, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa188, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa18c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa190, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa194, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa198, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa19c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ac, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1bc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1cc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1dc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ec, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 }, \ - { AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 }, \ - { AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 }, \ - { AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a }, \ - { AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 }, \ - { AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 }, \ - { AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 }, \ - { AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa234, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa238, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa23c, 0x13c889af }, \ - { AR5K_INI_FLAG_BOTH, 0xa240, 0x38490a20 }, \ - { AR5K_INI_FLAG_BOTH, 0xa244, 0x00007bb6 }, \ - { AR5K_INI_FLAG_BOTH, 0xa248, 0x0fff3ffc }, \ - { AR5K_INI_FLAG_BOTH, 0x9b00, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b28, 0x0000000c }, \ - { AR5K_INI_FLAG_BOTH, 0x9b38, 0x00000012 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \ - { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \ - /* AR5111 specific */ \ - { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \ - { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \ - { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \ - { AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a }, \ - { AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 }, \ - { AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 }, \ - { AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 }, \ - { AR5K_INI_FLAG_5111, 0x9b10, 0x00000008 }, \ - { AR5K_INI_FLAG_5111, 0x9b14, 0x00000028 }, \ - { AR5K_INI_FLAG_5111, 0x9b18, 0x00000004 }, \ - { AR5K_INI_FLAG_5111, 0x9b1c, 0x00000024 }, \ - { AR5K_INI_FLAG_5111, 0x9b20, 0x00000014 }, \ - { AR5K_INI_FLAG_5111, 0x9b24, 0x00000034 }, \ - { AR5K_INI_FLAG_5111, 0x9b2c, 0x0000002c }, \ - { AR5K_INI_FLAG_5111, 0x9b30, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9b34, 0x00000022 }, \ - { AR5K_INI_FLAG_5111, 0x9b3c, 0x00000032 }, \ - { AR5K_INI_FLAG_5111, 0x9b40, 0x0000000a }, \ - { AR5K_INI_FLAG_5111, 0x9b44, 0x0000002a }, \ - { AR5K_INI_FLAG_5111, 0x9b48, 0x00000006 }, \ - { AR5K_INI_FLAG_5111, 0x9b4c, 0x00000026 }, \ - { AR5K_INI_FLAG_5111, 0x9b50, 0x00000016 }, \ - { AR5K_INI_FLAG_5111, 0x9b54, 0x00000036 }, \ - { AR5K_INI_FLAG_5111, 0x9b58, 0x0000000e }, \ - { AR5K_INI_FLAG_5111, 0x9b5c, 0x0000002e }, \ - { AR5K_INI_FLAG_5111, 0x9b60, 0x00000001 }, \ - { AR5K_INI_FLAG_5111, 0x9b68, 0x00000011 }, \ - { AR5K_INI_FLAG_5111, 0x9b6c, 0x00000031 }, \ - { AR5K_INI_FLAG_5111, 0x9b70, 0x00000009 }, \ - { AR5K_INI_FLAG_5111, 0x9b74, 0x00000029 }, \ - { AR5K_INI_FLAG_5111, 0x9b78, 0x00000005 }, \ - { AR5K_INI_FLAG_5111, 0x9b7c, 0x00000025 }, \ - { AR5K_INI_FLAG_5111, 0x9b80, 0x00000015 }, \ - { AR5K_INI_FLAG_5111, 0x9b84, 0x00000035 }, \ - { AR5K_INI_FLAG_5111, 0x9b88, 0x0000000d }, \ - { AR5K_INI_FLAG_5111, 0x9b90, 0x00000003 }, \ - { AR5K_INI_FLAG_5111, 0x9b94, 0x00000023 }, \ - { AR5K_INI_FLAG_5111, 0x9b98, 0x00000013 }, \ - { AR5K_INI_FLAG_5111, 0x9ba0, 0x0000000b }, \ - { AR5K_INI_FLAG_5111, 0x9ba4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9ba8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bac, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bbc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bcc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bdc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bec, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \ - /* AR5112 specific */ \ - { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \ - { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \ - { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \ - { AR5K_INI_FLAG_5112, 0x9b0c, 0x00000003 }, \ - { AR5K_INI_FLAG_5112, 0x9b10, 0x00000004 }, \ - { AR5K_INI_FLAG_5112, 0x9b14, 0x00000005 }, \ - { AR5K_INI_FLAG_5112, 0x9b18, 0x00000008 }, \ - { AR5K_INI_FLAG_5112, 0x9b1c, 0x00000009 }, \ - { AR5K_INI_FLAG_5112, 0x9b20, 0x0000000a }, \ - { AR5K_INI_FLAG_5112, 0x9b24, 0x0000000b }, \ - { AR5K_INI_FLAG_5112, 0x9b2c, 0x0000000d }, \ - { AR5K_INI_FLAG_5112, 0x9b30, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9b34, 0x00000011 }, \ - { AR5K_INI_FLAG_5112, 0x9b3c, 0x00000013 }, \ - { AR5K_INI_FLAG_5112, 0x9b40, 0x00000014 }, \ - { AR5K_INI_FLAG_5112, 0x9b44, 0x00000015 }, \ - { AR5K_INI_FLAG_5112, 0x9b48, 0x00000018 }, \ - { AR5K_INI_FLAG_5112, 0x9b4c, 0x00000019 }, \ - { AR5K_INI_FLAG_5112, 0x9b50, 0x0000001a }, \ - { AR5K_INI_FLAG_5112, 0x9b54, 0x0000001b }, \ - { AR5K_INI_FLAG_5112, 0x9b58, 0x0000001c }, \ - { AR5K_INI_FLAG_5112, 0x9b5c, 0x0000001d }, \ - { AR5K_INI_FLAG_5112, 0x9b60, 0x00000020 }, \ - { AR5K_INI_FLAG_5112, 0x9b68, 0x00000022 }, \ - { AR5K_INI_FLAG_5112, 0x9b6c, 0x00000023 }, \ - { AR5K_INI_FLAG_5112, 0x9b70, 0x00000024 }, \ - { AR5K_INI_FLAG_5112, 0x9b74, 0x00000025 }, \ - { AR5K_INI_FLAG_5112, 0x9b78, 0x00000028 }, \ - { AR5K_INI_FLAG_5112, 0x9b7c, 0x00000029 }, \ - { AR5K_INI_FLAG_5112, 0x9b80, 0x0000002a }, \ - { AR5K_INI_FLAG_5112, 0x9b84, 0x0000002b }, \ - { AR5K_INI_FLAG_5112, 0x9b88, 0x0000002c }, \ - { AR5K_INI_FLAG_5112, 0x9b90, 0x00000030 }, \ - { AR5K_INI_FLAG_5112, 0x9b94, 0x00000031 }, \ - { AR5K_INI_FLAG_5112, 0x9b98, 0x00000032 }, \ - { AR5K_INI_FLAG_5112, 0x9ba0, 0x00000034 }, \ - { AR5K_INI_FLAG_5112, 0x9ba4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9ba8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bac, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bbc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bcc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bdc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bec, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf8, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9bfc, 0x0000001a }, \ -} - -struct ar5k_ar5212_ini_mode { - u_int16_t mode_register; - u_int8_t mode_flags; - u_int32_t mode_value[2][5]; -}; - -#define AR5K_AR5212_INI_MODE { \ - { 0x0030, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \ - } }, \ - { 0x1040, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1044, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1048, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x104c, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1050, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1054, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1058, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x105c, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1060, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1064, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1030, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } \ - } }, \ - { 0x1070, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } \ - } }, \ - { 0x10b0, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } \ - } }, \ - { 0x10f0, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } \ - } }, \ - { 0x8014, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } \ - } }, \ - { 0x9804, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } \ - } }, \ - { 0x9820, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } \ - } }, \ - { 0x9834, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ - } }, \ - { 0x9838, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } \ - } }, \ - { 0x9844, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 } \ - } }, \ - { 0x9850, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } \ - } }, \ - { 0x9858, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } \ - } }, \ - { 0x9860, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 } \ - } }, \ - { 0x9864, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } \ - } }, \ - { 0x9868, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } \ - } }, \ - { 0x9918, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } \ - } }, \ - { 0x9924, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } \ - } }, \ - { 0xa180, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff } \ - } }, \ - { 0xa230, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } \ - } }, \ - { 0x801c, AR5K_INI_FLAG_BOTH, { \ - { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x128d8fab, 0x09880fcf }, \ - { 0x128d93a7, 0x098813cf, 0x04e01395, 0x128d93ab, 0x098813cf } \ - } }, \ - { 0x9824, AR5K_INI_FLAG_BOTH, { \ - { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e }, \ - { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ - } }, \ - { 0x9828, AR5K_INI_FLAG_BOTH, { \ - { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 }, \ - { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } \ - } }, \ - { 0x9848, AR5K_INI_FLAG_BOTH, { \ - { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 }, \ - { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } \ - } }, \ - { 0x985c, AR5K_INI_FLAG_BOTH, { \ - { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e }, \ - { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } \ - } }, \ - { 0x986c, AR5K_INI_FLAG_BOTH, { \ - { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 }, \ - { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } \ - } }, \ - { 0x9914, AR5K_INI_FLAG_BOTH, { \ - { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 }, \ - { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } \ - } }, \ - { 0x9944, AR5K_INI_FLAG_BOTH, { \ - { 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 }, \ - { 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 } \ - } }, \ - { 0xa204, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } \ - } }, \ - { 0xa208, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } \ - } }, \ - { 0xa20c, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } \ - } }, \ -} - -#endif /* _AR5K_AR5212_VAR_H */ Index: ath5k_hw.c =================================================================== --- ath5k_hw.c (revision 0) +++ ath5k_hw.c (revision 2232) @@ -0,0 +1,5873 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + +/* + * HAL interface for Atheros Wireless LAN devices. + * (Please have a look at ar5xxx.h for further information) + */ + +#include "ah_devid.h" +#include "ath5k.h" +#include "ath5kreg.h" + +/* + * Known pci ids + */ + +static const struct { + u_int16_t vendor; + u_int16_t device; + u_int8_t mac_version; +} ath5k_known_products[] = { + /* + * From pcidevs_data.h + */ + /* 5210 is not supported yet + { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210,AR5K_AR5210}, + { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP,AR5K_AR5210}, + { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT,AR5K_AR5210},*/ + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5211, AR5K_AR5211}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5211_DEFAULT,AR5K_AR5211}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5311, AR5K_AR5211}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5211_FPGA11B,AR5K_AR5211}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5211_LEGACY, AR5K_AR5211}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_DEFAULT,AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_FPGA, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_IBM, AR5K_AR5212}, + { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675, AR5K_AR5212}, + { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_REV2, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_REV7, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_REV8, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_0014, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_0015, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_0016, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_0017, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_0018, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5212_0019, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR2413, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5413, AR5K_AR5212}, + { PCI_VENDOR_ATHEROS,PCI_PRODUCT_ATHEROS_AR5424, AR5K_AR5212}, +}; + +/*Rate tables*/ +static const AR5K_RATE_TABLE ath5k_rt_11a = AR5K_RATES_11A; +static const AR5K_RATE_TABLE ath5k_rt_11b = AR5K_RATES_11B; +static const AR5K_RATE_TABLE ath5k_rt_11g = AR5K_RATES_11G; +static const AR5K_RATE_TABLE ath5k_rt_turbo = AR5K_RATES_TURBO; +static const AR5K_RATE_TABLE ath5k_rt_xr = AR5K_RATES_XR; + +/*Prototypes*/ +AR5K_BOOL ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); +AR5K_BOOL ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t); +u_int16_t ath5k_hw_radio_revision(struct ath_hal *, AR5K_CHIP); +void ath5k_hw_fill(struct ath_hal *); +AR5K_BOOL ath5k_hw_txpower(struct ath_hal *, AR5K_CHANNEL *, u_int); + +AR5K_HAL_FUNCTIONS(extern, ath5k_hw,); + +/* + * Supported channels + */ +static const struct +ieee80211_regchannel ath5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; +static const struct +ieee80211_regchannel ath5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; + +/* + * Initial register dumps + */ +static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI; +static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE; +static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI; +static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE; +static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF; + +/* + * Initial gain optimization values + */ +static const struct ath5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT; +static const struct ath5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT; + +/* + * Initial register for the radio chipsets + */ +static const struct ath5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF; +static const struct ath5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF; +static const struct ath5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF; +static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; + +/* + * Enable to overwrite the country code (use "00" for debug) + */ +#if 0 +#define COUNTRYCODE "00" +#endif + +/*******************\ + General Functions +\*******************/ + +/* + * Perform a lookup if the device is supported by the HAL + * and return the chip name. + * TODO:Left here for combatibility, change it in at5k + */ +const char * +ath_hal_probe(u_int16_t vendor, u_int16_t device) +{ + int i; + + /* + * Perform a linear search on the table of supported devices + */ + for (i = 0; i < AR5K_ELEMENTS(ath5k_known_products); i++) { + if (vendor == ath5k_known_products[i].vendor && + device == ath5k_known_products[i].device){ + switch (ath5k_known_products[i].mac_version) { + case AR5K_AR5210: + return("AR5210"); + case AR5K_AR5211: + return("AR5211"); + case AR5K_AR5212: + return("AR5212"); + default: + return (""); + } + } + } + + return (NULL); +} + +/* + * Calculate transmition time of a frame + * TODO:Left here for combatibility, change it in at5k + */ +u_int16_t /*TODO: Is this realy hardware dependent ?*/ +ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates, + u_int32_t frame_length, u_int16_t rate_index, AR5K_BOOL short_preamble) +{ + const AR5K_RATE *rate; + u_int32_t value; + + AR5K_ASSERT_ENTRY(rate_index, rates->rate_count); + + /* + * Get rate by index + */ + rate = &rates->rates[rate_index]; + + /* + * Calculate the transmission time by operation (PHY) mode + */ + switch (rate->modulation) { + case MODULATION_CCK: + /* + * CCK / DS mode (802.11b) + */ + value = AR5K_CCK_TX_TIME(rate->rate_kbps, frame_length, + (short_preamble && (rate->modulation == MODULATION_CCK_SP))); + break; + + case MODULATION_OFDM: + /* + * Orthogonal Frequency Division Multiplexing + */ + if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) + return (0); + value = AR5K_OFDM_TX_TIME(rate->rate_kbps, frame_length); + break; + + case MODULATION_TURBO: + /* + * Orthogonal Frequency Division Multiplexing + * Atheros "Turbo Mode" (doubled rates) + */ + if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) + return (0); + value = AR5K_TURBO_TX_TIME(rate->rate_kbps, frame_length); + break; + + case MODULATION_XR: + /* + * Orthogonal Frequency Division Multiplexing + * Atheros "eXtended Range" (XR) + */ + if (AR5K_XR_NUM_BITS_PER_SYM(rate->rate_kbps) == 0) + return (0); + value = AR5K_XR_TX_TIME(rate->rate_kbps, frame_length); + break; + + default: + return (0); + } + + return (value); +} + +/* + * Return the supported 802.11 operation modes + * TODO:Left here for combatibility, change it in at5k + */ +u_int/*TODO:Fix this & fix g support*/ +ath_hal_getwirelessmodes(struct ath_hal *hal, AR5K_CTRY_CODE country) +{ + switch(hal->ah_version){ + case AR5K_AR5212: + return (AR5K_MODE_11A|AR5K_MODE_11B); + case AR5K_AR5211: + return (AR5K_MODE_11A|AR5K_MODE_11B); + default : + return(AR5K_MODE_11A); + } +} + +/* + * Functions used internaly + */ + +u_int32_t +ath5k_hw_bitswap(u_int32_t val, u_int bits) +{ + u_int32_t retval = 0, bit, i; + + for (i = 0; i < bits; i++) { + bit = (val >> i) & 1; + retval = (retval << 1) | bit; + } + + return (retval); +} + +inline u_int +ath5k_hw_htoclock(u_int usec, AR5K_BOOL turbo) +{ + return (turbo == TRUE ? (usec * 80) : (usec * 40)); +} + +inline u_int +ath5k_hw_clocktoh(u_int clock, AR5K_BOOL turbo) +{ + return (turbo == TRUE ? (clock / 80) : (clock / 40)); +} + +/* + * Copy a rate table to a new one + */ +inline void +ath5k_hw_rtcopy(AR5K_RATE_TABLE *dst, const AR5K_RATE_TABLE *src) +{ + bzero(dst, sizeof(AR5K_RATE_TABLE)); + dst->rate_count = src->rate_count; + bcopy(src->rates, dst->rates, sizeof(dst->rates)); +} + +/* + * Read from a device register + */ +static inline u32 ath5k_hw_reg_read(struct ath_hal *hal, u16 reg) +{ + return readl(hal->ah_sh + reg); +} + +/* + * Write to a device register + */ +static inline void ath5k_hw_reg_write(struct ath_hal *hal, u32 val, u16 reg) +{ + writel(val, hal->ah_sh + reg); +} + +/* + * Check if a register write has been completed + */ +AR5K_BOOL +ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, + u_int32_t val, AR5K_BOOL is_set) +{ + int i; + u_int32_t data; + + for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { + data = AR5K_REG_READ(reg); + if ((is_set == TRUE) && (data & flag)) + break; + else if ((data & flag) == val) + break; + AR5K_DELAY(15); + } + + if (i <= 0) + return (FALSE); + + return (TRUE); +} + + + +/***************************************\ + Attach/Detach Functions +\***************************************/ + +/* + * Check if the device is supported and initialize the needed structs + */ +struct ath_hal * +ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG st, + AR5K_BUS_HANDLE sh, AR5K_STATUS *status) +{ + struct ath_hal *hal = NULL; + u_int8_t mac[IEEE80211_ADDR_LEN]; + u_int8_t mac_version = 255; /*Initialize this to something else than ath5k_version*/ + int i; + u_int32_t srev; + *status = AR5K_EINVAL; + + /*TODO:Use eeprom_magic to verify chipset*/ + + /* + * Check if device is a known one + */ + for (i = 0; i < AR5K_ELEMENTS(ath5k_known_products); i++) { + if (device == ath5k_known_products[i].device) + mac_version = ath5k_known_products[i].mac_version; + } + + /*If there wasn't a match, the device is not supported*/ + if (mac_version == 255) { + *status = AR5K_ENOTSUPP; + AR5K_PRINTF("device not supported: 0x%04x\n", device); + return (NULL); + } + + /*If we passed the test malloc a hal struct*/ + if ((hal = malloc(sizeof(struct ath_hal), + M_DEVBUF, M_NOWAIT)) == NULL) { + *status = AR5K_ENOMEM; + AR5K_PRINT("out of memory\n"); + return (NULL); + } + + /*Initialize it*/ + bzero(hal, sizeof(struct ath_hal)); + + hal->ah_sc = sc; + hal->ah_st = st; + hal->ah_sh = sh; + hal->ah_device = device; + hal->ah_sub_vendor = 0; /* XXX unknown?! */ + + /* + * HAL information + */ + + /* Regulation Stuff */ + hal->ah_country_code = AR5K_TUNE_CTRY; + ath5k_get_regdomain(hal); + + hal->ah_op_mode = AR5K_M_STA; + hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; + hal->ah_turbo = FALSE; + hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; + hal->ah_imr = 0; + hal->ah_atim_window = 0; + hal->ah_aifs = AR5K_TUNE_AIFS; + hal->ah_cw_min = AR5K_TUNE_CWMIN; + hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; + hal->ah_software_retry = FALSE; + hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; + + switch (device) { + case PCI_PRODUCT_ATHEROS_AR2413: + case PCI_PRODUCT_ATHEROS_AR5413: + case PCI_PRODUCT_ATHEROS_AR5424: + /* + * Known single chip solutions + */ + hal->ah_single_chip = TRUE; + break; + default: + /* + * Multi chip solutions + */ + hal->ah_single_chip = FALSE; + break; + } + + /* + * Set the mac revision based on the pci id + */ + hal->ah_version = mac_version; + + /*Fill the hal struct with the needed functions*/ + ath5k_hw_fill(hal); + + /* Bring device out of sleep and reset it's units */ + if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE) != TRUE) + goto failed; + + /* Get MAC, PHY and RADIO revisions */ + srev = AR5K_REG_READ(AR5K_SREV); + hal->ah_mac_srev = srev; + hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); + hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); + hal->ah_phy_revision = AR5K_REG_READ(AR5K_PHY_CHIP_ID) & + 0x00ffffffff; + hal->ah_radio_5ghz_revision = + ath5k_hw_radio_revision(hal, AR5K_CHIP_5GHZ); + hal->ah_radio_2ghz_revision = + ath5k_hw_radio_revision(hal, AR5K_CHIP_2GHZ); + + /* Single chip radio */ + if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) + hal->ah_radio_2ghz_revision = 0; + + /* Identify the radio chip*/ + hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ? + AR5K_AR5111 : AR5K_AR5112; + + hal->ah_phy = AR5K_PHY(0); + + /*Is this bcopy O.K. ?*/ + bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); + + ath5k_hw_set_associd(hal, mac, 0); + ath5k_hw_get_lladdr(hal, mac); + ath5k_hw_set_opmode(hal); + +#ifdef AR5K_DEBUG + hal->ah_dump_state(hal); +#endif + + /* + * Get card capabilities, values, ... + */ + + if (ath5k_eeprom_init(hal) != 0) { + *status = AR5K_EELOCKED; + AR5K_PRINT("unable to init EEPROM\n"); + goto failed; + } + + /* Get misc capabilities */ + if (hal->ah_get_capabilities(hal) != TRUE) { + *status = AR5K_EEREAD; + AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", + device); + goto failed; + } + + /* Get MAC address */ + if ((*status = ath5k_eeprom_read_mac(hal, mac)) != 0) { + *status = AR5K_EEBADMAC; + AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", + device); + goto failed; + } + + hal->ah_set_lladdr(hal, mac); + + /* Get rate tables */ + if (hal->ah_capabilities.cap_mode & AR5K_MODE_11A) + ath5k_hw_rtcopy(&hal->ah_rt_11a, &ath5k_rt_11a); + if (hal->ah_capabilities.cap_mode & AR5K_MODE_11B) + ath5k_hw_rtcopy(&hal->ah_rt_11b, &ath5k_rt_11b); + if (hal->ah_capabilities.cap_mode & AR5K_MODE_11G) + ath5k_hw_rtcopy(&hal->ah_rt_11g, &ath5k_rt_11g); + if (hal->ah_capabilities.cap_mode & AR5K_MODE_TURBO) + ath5k_hw_rtcopy(&hal->ah_rt_turbo, &ath5k_rt_turbo); + if (hal->ah_capabilities.cap_mode & AR5K_MODE_XR) + ath5k_hw_rtcopy(&hal->ah_rt_xr, &ath5k_rt_xr); + + /* Initialize the gain optimization values */ + /*For RF5111*/ + if (hal->ah_radio == AR5K_AR5111) { + hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default; + hal->ah_gain.g_step = + &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; + hal->ah_gain.g_low = 20; + hal->ah_gain.g_high = 35; + hal->ah_gain.g_active = 1; + /*For RF5112*/ + } else if (hal->ah_radio == AR5K_AR5112) { + hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default; + hal->ah_gain.g_step = + &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; + hal->ah_gain.g_low = 20; + hal->ah_gain.g_high = 85; + hal->ah_gain.g_active = 1; + } + + *status = AR5K_OK; + + return (hal); + + failed: + free(hal, M_DEVBUF); + return (NULL); +} + +/* + * Bring up MAC + PHY Chips + */ +AR5K_BOOL +ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags) +{ + u_int32_t turbo, mode, clock; + + turbo = 0; + mode = 0; + clock = 0; + + AR5K_TRACE; + + /* + * Get channel mode flags + */ + + if (hal->ah_radio >= AR5K_AR5112) { + mode = AR5K_PHY_MODE_RAD_AR5112; + clock = AR5K_PHY_PLL_AR5112; + } else { + mode = AR5K_PHY_MODE_RAD_AR5111; /*Zero -backwards combatible*/ + clock = AR5K_PHY_PLL_AR5111; /*Zero -backwards combatible*/ + } + + if (flags & CHANNEL_2GHZ) { + mode |= AR5K_PHY_MODE_FREQ_2GHZ; + clock |= AR5K_PHY_PLL_44MHZ; + } else if (flags & CHANNEL_5GHZ) { + mode |= AR5K_PHY_MODE_FREQ_5GHZ; + clock |= AR5K_PHY_PLL_40MHZ; + } else { + AR5K_PRINT("invalid radio frequency mode\n"); + return (FALSE); + } + + if (flags & CHANNEL_CCK) { + mode |= AR5K_PHY_MODE_MOD_CCK; + } else if (flags & CHANNEL_OFDM) { + mode |= AR5K_PHY_MODE_MOD_OFDM; + } else if (flags & CHANNEL_DYN) { + /* Dynamic OFDM/CCK is not supported by the AR5211 */ + if (hal->ah_version == AR5K_AR5211){ + mode |= AR5K_PHY_MODE_MOD_CCK; + }else{ + mode |= AR5K_PHY_MODE_MOD_DYN; + } + } else { + AR5K_PRINT("invalid radio frequency mode\n"); + return (FALSE); + } + + if (flags & CHANNEL_TURBO) { + turbo = AR5K_PHY_TURBO_MODE | + AR5K_PHY_TURBO_SHORT; + } + + /* + * Reset and wakeup the device + */ + + /* ...reset chipset and PCI device */ + if (hal->ah_single_chip == FALSE && + ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == FALSE) { + AR5K_PRINT("failed to reset the MAC + PCI Chipset\n"); + return (FALSE); + } + + /* ...wakeup */ + if (ath5k_hw_set_power(hal, + AR5K_PM_AWAKE, TRUE, 0) == FALSE) { + AR5K_PRINT("failed to resume the MAC Chip (again)\n"); + return (FALSE); + } + + /* ...final warm reset */ + if (ath5k_hw_nic_reset(hal, 0) == FALSE) { + AR5K_PRINT("failed to warm reset the MAC Chip\n"); + return (FALSE); + } + + /* ...set the PHY operating mode */ + AR5K_REG_WRITE(AR5K_PHY_PLL, clock); + AR5K_DELAY(300); + + AR5K_REG_WRITE(AR5K_PHY_MODE, mode); + AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); + + return (TRUE); +} + +/* + * Get the PHY Chip revision + */ +u_int16_t +ath5k_hw_radio_revision(struct ath_hal *hal, AR5K_CHIP chip) +{ + int i; + u_int32_t srev; + u_int16_t ret; + + AR5K_TRACE; + + /* + * Set the radio chip access register + */ + switch (chip) { + case AR5K_CHIP_2GHZ: + AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_2GHZ); + break; + case AR5K_CHIP_5GHZ: + AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + break; + default: + return (0); + } + + AR5K_DELAY(2000); + + /* ...wait until PHY is ready and read the selected radio revision */ + AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16); + + for (i = 0; i < 8; i++) + AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000); + srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff; + + ret = ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + + /* Reset to the 5GHz mode */ + AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + + return (ret); +} + +/* + * Get the rate table for a specific operation mode + */ +const AR5K_RATE_TABLE * +ath5k_hw_get_rate_table(struct ath_hal *hal, u_int mode) +{ + + AR5K_TRACE; + + switch (mode) { + case AR5K_MODE_11A: + return (&hal->ah_rt_11a); + case AR5K_MODE_TURBO: + return (&hal->ah_rt_turbo); + case AR5K_MODE_11B: + return (&hal->ah_rt_11b); + case AR5K_MODE_11G: + return (&hal->ah_rt_11g); + case AR5K_MODE_XR: + return (&hal->ah_rt_xr); + default: + return (NULL); + } + + return (NULL); +} + +/* + * Free the hal struct + */ +void +ath5k_hw_detach(struct ath_hal *hal) +{ + AR5K_TRACE; + + if (hal->ah_rf_banks != NULL) + free(hal->ah_rf_banks, M_DEVBUF); + + /* + * Free HAL structure, assume interrupts are down + */ + free(hal, M_DEVBUF); +} + + + + +/*******************************\ + Reset Functions +\*******************************/ + +/* + * Main reset function + */ +AR5K_BOOL +ath5k_hw_reset(struct ath_hal *hal, AR5K_OPMODE op_mode, AR5K_CHANNEL *channel, + AR5K_BOOL change_channel, AR5K_STATUS *status) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u_int8_t mac[IEEE80211_ADDR_LEN]; + u_int32_t data, s_seq, s_ant, s_led[3]; + u_int i, phy, mode, freq, off, ee_mode, ant[2]; + const AR5K_RATE_TABLE *rt; + + AR5K_TRACE; + + *status = AR5K_OK; + + /* + * Save some registers before a reset + */ + if (change_channel == TRUE) { + /*Sequence number for queue 0 -do this for all queues ?*/ + s_seq = AR5K_REG_READ(AR5K_QUEUE_DFS_SEQNUM(0)); + /*Default antenna*/ + s_ant = AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + } else { + s_seq = 0; + s_ant = 1; + } + + /*GPIOs*/ + s_led[0] = AR5K_REG_READ(AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; + s_led[1] = AR5K_REG_READ(AR5K_GPIOCR); + s_led[2] = AR5K_REG_READ(AR5K_GPIODO); + + if (change_channel == TRUE && hal->ah_rf_banks != NULL) + ath5k_hw_get_rf_gain(hal); + + if (ath5k_hw_nic_wakeup(hal, channel->channel_flags) == FALSE) { + *status = AR5K_EIO; + return (FALSE); + } + + /* + * Initialize operating mode + */ + hal->ah_op_mode = op_mode; + + if (hal->ah_radio == AR5K_AR5111) { + phy = AR5K_INI_PHY_5111; + } else if (hal->ah_radio == AR5K_AR5112) { + phy = AR5K_INI_PHY_5112; + } else { + AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); + *status = AR5K_EINVAL; + return (FALSE); + } + + switch (channel->channel_flags & CHANNEL_MODES) { + case CHANNEL_A: + mode = AR5K_INI_VAL_11A; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + case CHANNEL_B: + mode = AR5K_INI_VAL_11B; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11B; + break; + case CHANNEL_G: + mode = AR5K_INI_VAL_11G; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_T: + mode = AR5K_INI_VAL_11A_TURBO; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + /*Is this ok on 5211 too ?*/ + case CHANNEL_TG: + mode = AR5K_INI_VAL_11G_TURBO; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_XR: + if(hal->ah_version == AR5K_AR5211){ + AR5K_PRINTF("XR mode not available on 5211"); + return (FALSE); + } + mode = AR5K_INI_VAL_XR; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + default: + AR5K_PRINTF("invalid channel: %d\n", channel->freq); + *status = AR5K_EINVAL; + return (FALSE); + } + + /* PHY access enable */ + AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + + /* + * Write initial RF registers on 5211 + * do we need that ? Is ath5k_rfregs going to work for 5211 (5111) ? + */ + if(hal->ah_version == AR5K_AR5211){ + ath5k_ar5211_rfregs(hal, channel, freq, ee_mode); + } + + /* + * Write initial mode settings + * TODO:Clean/merge arrays + */ + /*For 5212*/ + if(hal->ah_version == AR5K_AR5212){ + for (i = 0; i < AR5K_ELEMENTS(ar5212_mode); i++) { + if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) + off = AR5K_INI_PHY_511X; + else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && + hal->ah_radio == AR5K_AR5111) + off = AR5K_INI_PHY_5111; + else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 && + hal->ah_radio == AR5K_AR5112) + off = AR5K_INI_PHY_5112; + else + continue; + + AR5K_REG_WAIT(i); + AR5K_REG_WRITE((u_int32_t)ar5212_mode[i].mode_register, + ar5212_mode[i].mode_value[off][mode]); + } + } + /*For 5211*/ + if(hal->ah_version == AR5K_AR5211){ + for (i = 0; i < AR5K_ELEMENTS(ar5211_mode); i++) { + AR5K_REG_WAIT(i); + AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, + ar5211_mode[i].mode_value[mode]); + } + } + + /* + * Write initial register settings + * TODO:Clean/merge arrays + */ + /*For 5212*/ + if(hal->ah_version == AR5K_AR5212){ + for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) { + if (change_channel == TRUE && + ar5212_ini[i].ini_register >= AR5K_PCU_MIN && + ar5212_ini[i].ini_register <= AR5K_PCU_MAX) + continue; + + if ((hal->ah_radio == AR5K_AR5111 && + ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) || + (hal->ah_radio == AR5K_AR5112 && + ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { + AR5K_REG_WAIT(i); + AR5K_REG_WRITE((u_int32_t)ar5212_ini[i].ini_register, + ar5212_ini[i].ini_value); + } + } + } + /*For 5211*/ + if(hal->ah_version == AR5K_AR5211){ + for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { + if (change_channel == TRUE && + ar5211_ini[i].ini_register >= AR5K_PCU_MIN && + ar5211_ini[i].ini_register <= AR5K_PCU_MAX) + continue; + + AR5K_REG_WAIT(i); + AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, + ar5211_ini[i].ini_value); + } + } + + /* + * Write initial RF gain settings + * This should work for all chipsets + */ + if (ath5k_rfgain(hal, phy, freq) == FALSE) { + *status = AR5K_EIO; + return (FALSE); + } + + AR5K_DELAY(1000); + + /* + * Set rate duration table on 5212 + */ + if(hal->ah_version == AR5K_AR5212){ + + /*For 802.11b*/ + if (!(channel->channel_flags & CHANNEL_B)) { + + /*Get rate table for this operation mode*/ + rt = ath5k_hw_get_rate_table(hal, AR5K_MODE_11B); + + /*Write rate duration table*/ + for (i = 0; i < rt->rate_count; i++) { + data = AR5K_RATE_DUR(rt->rates[i].rate_code); + AR5K_REG_WRITE(data, + ath_hal_computetxtime(hal, rt, 14, + rt->rates[i].control_rate, FALSE)); + if (HAS_SHPREAMBLE(i)) { + AR5K_REG_WRITE(data + + (AR5K_SET_SHORT_PREAMBLE << 2), + ath_hal_computetxtime(hal, rt, 14, + rt->rates[i].control_rate, FALSE)); + } + } + + } else { + /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ + + /*Get rate table for this operation mode*/ + rt = ath5k_hw_get_rate_table(hal, + channel->channel_flags & CHANNEL_TURBO ? + AR5K_MODE_TURBO : AR5K_MODE_XR); + + /*Write rate duration table*/ + for (i = 0; i < rt->rate_count; i++) { + AR5K_REG_WRITE(AR5K_RATE_DUR(rt->rates[i].rate_code), + ath_hal_computetxtime(hal, rt, 14, + rt->rates[i].control_rate, FALSE)); + } + + } + } + + /* Fix for first revision of the AR5112 RF chipset */ + if (hal->ah_radio >= AR5K_AR5112 && + hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { + AR5K_REG_WRITE(AR5K_PHY_CCKTXCTL, + AR5K_PHY_CCKTXCTL_WORLD); + if (channel->channel_flags & CHANNEL_OFDM) + data = 0xffb81020; + else + data = 0xffb80d20; + AR5K_REG_WRITE(AR5K_PHY_FRAME_CTL, data); + } + + /* + * Set TX power (XXX use txpower from net80211) + */ + if (ath5k_hw_txpower(hal, channel, + AR5K_TUNE_DEFAULT_TXPOWER) == FALSE) { + *status = AR5K_EIO; + return (FALSE); + } + + /* + * Write RF registers + * TODO:Does this work on 5211 (5111) ? + */ + if (ath5k_rfregs(hal, channel, mode) == FALSE) { + *status = AR5K_EINPROGRESS; + return (FALSE); + } + + /* + * Configure additional registers + */ + + /* Write OFDM timings on 5212*/ + if(hal->ah_version == AR5K_AR5212){ + if (channel->channel_flags & CHANNEL_OFDM) { + u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, + ds_coef_man, clock; + + clock = channel->channel_flags & CHANNEL_T ? 80 : 40; + coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; + + for (coef_exp = 31; coef_exp > 0; coef_exp--) + if ((coef_scaled >> coef_exp) & 0x1) + break; + + if (!coef_exp) { + *status = AR5K_EINVAL; + return (FALSE); + } + + coef_exp = 14 - (coef_exp - 24); + coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); + ds_coef_man = coef_man >> (24 - coef_exp); + ds_coef_exp = coef_exp - 16; + + AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); + AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); + } + } + + /*Enable/disable 802.11b mode on 5111 + (enable 2111 frequency converter + CCK)*/ + if (hal->ah_radio == AR5K_AR5111) { + if (channel->channel_flags & CHANNEL_B) + AR5K_REG_ENABLE_BITS(AR5K_TXCFG, + AR5K_TXCFG_B_MODE); + else + AR5K_REG_DISABLE_BITS(AR5K_TXCFG, + AR5K_TXCFG_B_MODE); + } + + /* Set antenna mode */ + AR5K_REG_MASKED_BITS(AR5K_PHY(0x44), + hal->ah_antenna[ee_mode][0], 0xfffffc06); + + if (freq == AR5K_INI_RFGAIN_2GHZ) + ant[0] = ant[1] = AR5K_ANT_FIXED_B; + else + ant[0] = ant[1] = AR5K_ANT_FIXED_A; + + + AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_0, + hal->ah_antenna[ee_mode][ant[0]]); + AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_1, + hal->ah_antenna[ee_mode][ant[1]]); + + /* Commit values from EEPROM */ + if (hal->ah_radio == AR5K_AR5111) + AR5K_REG_WRITE_BITS(AR5K_PHY_FRAME_CTL, + AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); + + AR5K_REG_WRITE(AR5K_PHY(0x5a), + AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); + + AR5K_REG_MASKED_BITS(AR5K_PHY(0x11), + (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x12), + (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x14), + (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | + ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); + + AR5K_REG_WRITE(AR5K_PHY(0x0d), + (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | + (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | + (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | + (ee->ee_tx_frm2xpa_enable[ee_mode])); + + AR5K_REG_MASKED_BITS(AR5K_PHY(0x0a), + ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x19), + (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x49), 4, 0xffffff01); + + AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_PHY_IQ_CORR_ENABLE | + (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | + ee->ee_q_cal[ee_mode]); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + AR5K_REG_WRITE_BITS(AR5K_PHY_GAIN_2GHZ, + AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, + ee->ee_margin_tx_rx[ee_mode]); + } + + /* + * Restore saved values + */ + AR5K_REG_WRITE(AR5K_QUEUE_DFS_SEQNUM(0), s_seq); + AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, s_ant); + AR5K_REG_ENABLE_BITS(AR5K_PCICFG, s_led[0]); + AR5K_REG_WRITE(AR5K_GPIOCR, s_led[1]); + AR5K_REG_WRITE(AR5K_GPIODO, s_led[2]); + + /* + * Misc + */ + bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); + ath5k_hw_set_associd(hal, mac, 0); + ath5k_hw_set_opmode(hal); + AR5K_REG_WRITE(AR5K_PISR, 0xffffffff); + AR5K_REG_WRITE(AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES); + + /* + * Set Rx/Tx DMA Configuration + */ + AR5K_REG_WRITE_BITS(AR5K_TXCFG, AR5K_TXCFG_SDMAMR, + AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); + AR5K_REG_WRITE_BITS(AR5K_RXCFG, AR5K_RXCFG_SDMAMW, + AR5K_DMASIZE_512B); + + /* + * Set channel and calibrate the PHY + */ + if (ath5k_channel(hal, channel) == FALSE) { + *status = AR5K_EIO; + return (FALSE); + } + + /* + * Enable the PHY and wait until completion + */ + AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); + + data = AR5K_REG_READ(AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; + data = (channel->channel_flags & CHANNEL_CCK) ? + ((data << 2) / 22) : (data / 10); + + AR5K_DELAY(100 + data); + + /* + * Start calibration + */ + AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF | + AR5K_PHY_AGCCTL_CAL); + + + hal->ah_calibration = FALSE; + + if (!(channel->channel_flags & CHANNEL_B)) { + hal->ah_calibration = TRUE; + AR5K_REG_WRITE_BITS(AR5K_PHY_IQ, + AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); + AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_PHY_IQ_RUN); + } + + /* + * Reset queues and start beacon timers at the end of the reset routine + */ + for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { + AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i); + if (ath5k_hw_reset_tx_queue(hal, i) == FALSE) { + AR5K_PRINTF("failed to reset TX queue #%d\n", i); + *status = AR5K_EINVAL; + return (FALSE); + } + } + + /* Pre-enable interrupts */ + ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); + + /* + * Set RF kill flags if supported by the device (read from the EEPROM) + * Disable gpio_intr for now since it results system hang. + * TODO:Handle this in ath_intr + */ +/* if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { + ath5k_hw_set_gpio_input(hal, 0); + if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0) + ath5k_hw_set_gpio_intr(hal, 0, 1); + else + ath5k_hw_set_gpio_intr(hal, 0, 0); + } +*/ + + /* + * Set the 32MHz reference clock on 5212 phy clock sleep register + */ + if(hal->ah_version == AR5K_AR5212){ + AR5K_REG_WRITE(AR5K_PHY_SCR, AR5K_PHY_SCR_32MHZ); + AR5K_REG_WRITE(AR5K_PHY_SLMT, AR5K_PHY_SLMT_32MHZ); + AR5K_REG_WRITE(AR5K_PHY_SCAL, AR5K_PHY_SCAL_32MHZ); + AR5K_REG_WRITE(AR5K_PHY_SCLOCK, AR5K_PHY_SCLOCK_32MHZ); + AR5K_REG_WRITE(AR5K_PHY_SDELAY, AR5K_PHY_SDELAY_32MHZ); + AR5K_REG_WRITE(AR5K_PHY_SPENDING, hal->ah_radio == AR5K_AR5111 ? + AR5K_PHY_SPENDING_AR5111 : AR5K_PHY_SPENDING_AR5112); + } + + /* + * Disable beacons and reset the register + */ + AR5K_REG_DISABLE_BITS(AR5K_BEACON, + AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); + + return (TRUE); +} + +/* + * Reset chipset + */ +AR5K_BOOL +ath5k_hw_nic_reset(struct ath_hal *hal, u_int32_t val) +{ + AR5K_BOOL ret = FALSE; + u_int32_t mask = val ? val : ~0; + + AR5K_TRACE; + + /* Read-and-clear RX Descriptor Pointer*/ + AR5K_REG_READ(AR5K_RXDP); + + /* + * Reset the device and wait until success + */ + AR5K_REG_WRITE(AR5K_RESET_CTL, val); + + /* Wait at least 128 PCI clocks */ + AR5K_DELAY(15); + + val &= + AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + + mask &= + AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + + ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, FALSE); + + /* + * Reset configuration register (for hw bitswap) + */ + if ((val & AR5K_RESET_CTL_PCU) == 0) + AR5K_REG_WRITE(AR5K_CFG, AR5K_INIT_CFG); + + return (ret); +} + +/* + * Power management functions + */ + +/* + * Sleep control + */ +AR5K_BOOL +ath5k_hw_set_power(struct ath_hal *hal, AR5K_POWER_MODE mode, + AR5K_BOOL set_chip, u_int16_t sleep_duration) +{ + u_int32_t staid; + int i; + + AR5K_TRACE; + staid = AR5K_REG_READ(AR5K_STA_ID1); + + switch (mode) { + case AR5K_PM_AUTO: + staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; + /* fallthrough */ + case AR5K_PM_NETWORK_SLEEP: + if (set_chip == TRUE) { + AR5K_REG_WRITE(AR5K_SLEEP_CTL, + AR5K_SLEEP_CTL_SLE | sleep_duration); + } + staid |= AR5K_STA_ID1_PWR_SV; + break; + + case AR5K_PM_FULL_SLEEP: + if (set_chip == TRUE) { + AR5K_REG_WRITE(AR5K_SLEEP_CTL, + AR5K_SLEEP_CTL_SLE_SLP); + } + staid |= AR5K_STA_ID1_PWR_SV; + break; + + case AR5K_PM_AWAKE: + if (set_chip == FALSE) + goto commit; + + AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE_WAKE); + + for (i = 5000; i > 0; i--) { + /* Check if the chip did wake up */ + if ((AR5K_REG_READ(AR5K_PCICFG) & + AR5K_PCICFG_SPWR_DN) == 0) + break; + + /* Wait a bit and retry */ + AR5K_DELAY(200); + AR5K_REG_WRITE(AR5K_SLEEP_CTL, + AR5K_SLEEP_CTL_SLE_WAKE); + } + + /* Fail if the chip didn't wake up */ + if (i <= 0) + return (FALSE); + + staid &= ~AR5K_STA_ID1_PWR_SV; + break; + + default: + return (FALSE); + } + + commit: + hal->ah_power_mode = mode; + + AR5K_REG_WRITE(AR5K_STA_ID1, staid); + + return (TRUE); +} + +/* + * Get power mode (sleep state) + * TODO:Remove ? + */ +AR5K_POWER_MODE +ath5k_hw_get_power_mode(struct ath_hal *hal) +{ + AR5K_TRACE; + return (hal->ah_power_mode); +} + + + + +/***********************\ + DMA Related Functions +\***********************/ + +/* + * Receive functions + */ + +/* + * Start DMA receive + */ +void +ath5k_hw_start_rx(struct ath_hal *hal) +{ + AR5K_TRACE; + AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXE); +} + +/* + * Stop DMA receive + */ +AR5K_BOOL +ath5k_hw_stop_rx_dma(struct ath_hal *hal) +{ + int i; + + AR5K_TRACE; + AR5K_REG_WRITE(AR5K_CR, AR5K_CR_RXD); + + /* + * It may take some time to disable the DMA receive unit + */ + for (i = 2000; + i > 0 && (AR5K_REG_READ(AR5K_CR) & AR5K_CR_RXE) != 0; + i--) + AR5K_DELAY(10); + + return (i > 0 ? TRUE : FALSE); +} + +/* + * Get the address of the RX Descriptor + */ +u_int32_t +ath5k_hw_get_rx_buf(struct ath_hal *hal) +{ + return (AR5K_REG_READ(AR5K_RXDP)); +} + +/* + * Set the address of the RX Descriptor + */ +void +ath5k_hw_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) +{ + AR5K_TRACE; + + /*TODO:Shouldn't we check if RX is enabled first ?*/ + AR5K_REG_WRITE(AR5K_RXDP, phys_addr); +} + +/* + * Transmit functions + */ + +/* + * Start DMA transmit for a specific queue + * (see also QCU/DCU functions) + */ +AR5K_BOOL +ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* Return if queue is disabled */ + if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) + return (FALSE); + + /* Start queue */ + AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); + + return (TRUE); +} + +/* + * Stop DMA transmit for a specific queue + * (see also QCU/DCU functions) + */ +AR5K_BOOL +ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) +{ + int i = 100, pending; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* + * Schedule TX disable and wait until queue is empty + */ + AR5K_REG_WRITE_Q(AR5K_QCU_TXD, queue); + + /*Check for pending frames*/ + do { + pending = AR5K_REG_READ(AR5K_QUEUE_STATUS(queue)) & + AR5K_QCU_STS_FRMPENDCNT; + AR5K_DELAY(100); + } while (--i && pending); + + /* Clear register */ + AR5K_REG_WRITE(AR5K_QCU_TXD, 0); + + /*TODO: Check for success else return false*/ + return (TRUE); +} + +/* + * Get the address of the TX Descriptor for a specific queue + * (see also QCU/DCU functions) + */ +u_int32_t +ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* + * Get the transmit queue descriptor pointer from the selected queue + */ + return (AR5K_REG_READ(AR5K_QUEUE_TXDP(queue))); +} + +/* + * Set the address of the TX Descriptor for a specific queue + * (see also QCU/DCU functions) + */ +AR5K_BOOL +ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* + * Set the transmit queue descriptor pointer for the selected queue + * (this won't work if the queue is still active) + */ + if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) + return (FALSE); + + AR5K_REG_WRITE(AR5K_QUEUE_TXDP(queue), phys_addr); + + return (TRUE); +} + +/* + * Update tx trigger level + */ +AR5K_BOOL +ath5k_hw_update_tx_triglevel(struct ath_hal *hal, AR5K_BOOL increase) +{ + u_int32_t trigger_level, imr; + AR5K_BOOL status = FALSE; + AR5K_TRACE; + + /* + * Disable interrupts by setting the mask + */ + imr = ath5k_hw_set_intr(hal, hal->ah_imr & ~AR5K_INT_GLOBAL); + + /*TODO: Boundary check on trigger_level*/ + trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_TXCFG), + AR5K_TXCFG_TXFULL); + + if (increase == FALSE) { + if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) + goto done; + } else + trigger_level += + ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); + + /* + * Update trigger level on success + */ + AR5K_REG_WRITE_BITS(AR5K_TXCFG, + AR5K_TXCFG_TXFULL, trigger_level); + status = TRUE; + + done: + /* + * Restore interrupt mask + */ + ath5k_hw_set_intr(hal, imr); + + return (status); +} + +/* + * Interrupt handling + */ + +/* + * Check if we have pending interrupts + */ +AR5K_BOOL +ath5k_hw_is_intr_pending(struct ath_hal *hal) +{ + AR5K_TRACE; + return (AR5K_REG_READ(AR5K_INTPEND) == TRUE ? TRUE : FALSE); +} + +/* + * Get interrupt mask (ISR) + */ +AR5K_BOOL +ath5k_hw_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) +{ + u_int32_t data; + + AR5K_TRACE; + /* + * Read interrupt status from the Read-And-Clear shadow register + */ + data = AR5K_REG_READ(AR5K_RAC_PISR); + + /* + * Get abstract interrupt mask (HAL-compatible) + */ + *interrupt_mask = (data & AR5K_INT_COMMON) & hal->ah_imr; + + if (data == AR5K_INT_NOCARD) + return (FALSE); + + if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) + *interrupt_mask |= AR5K_INT_RX; + + if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR)) + *interrupt_mask |= AR5K_INT_TX; + + /*HIU = Host Interface Unit (PCI etc)*/ + if (data & (AR5K_ISR_HIUERR)) + *interrupt_mask |= AR5K_INT_FATAL; + + /*Beacon Not Ready*/ + if (data & (AR5K_ISR_BNR)) + *interrupt_mask |= AR5K_INT_BNR; + + /* + * Special interrupt handling (not caught by the driver) + */ + if (((*interrupt_mask) & AR5K_ISR_RXPHY) && + hal->ah_radar.r_enabled == TRUE) + ath5k_radar_alert(hal); + + if (*interrupt_mask == 0) + AR5K_PRINTF("0x%08x\n", data); + + return (TRUE); +} + +/* + * Return the interrupt mask stored previously + * TODO: Remove ? + */ +u_int32_t +ath5k_hw_get_intr(struct ath_hal *hal) +{ + AR5K_TRACE; + return (hal->ah_imr); +} + +/* + * Set interrupt mask + */ +AR5K_INT +ath5k_hw_set_intr(struct ath_hal *hal, AR5K_INT new_mask) +{ + AR5K_INT old_mask, int_mask; + + /* + * Disable card interrupts to prevent any race conditions + * (they will be re-enabled afterwards). + */ + AR5K_REG_WRITE(AR5K_IER, AR5K_IER_DISABLE); + + old_mask = hal->ah_imr; + + /* + * Add additional, chipset-dependent interrupt mask flags + * and write them to the IMR (interrupt mask register). + */ + int_mask = new_mask & AR5K_INT_COMMON; + + if (new_mask & AR5K_INT_RX) + int_mask |= + AR5K_IMR_RXOK | + AR5K_IMR_RXERR | + AR5K_IMR_RXORN | + AR5K_IMR_RXDESC; + + if (new_mask & AR5K_INT_TX) + int_mask |= + AR5K_IMR_TXOK | + AR5K_IMR_TXERR | + AR5K_IMR_TXDESC | + AR5K_IMR_TXURN; + + if (new_mask & AR5K_INT_FATAL) { + int_mask |= AR5K_IMR_HIUERR; + AR5K_REG_ENABLE_BITS(AR5K_SIMR2, + AR5K_SIMR2_MCABT | + AR5K_SIMR2_SSERR | + AR5K_SIMR2_DPERR); + } + + AR5K_REG_WRITE(AR5K_PIMR, int_mask); + + /* Store new interrupt mask */ + hal->ah_imr = new_mask; + + /* ..re-enable interrupts */ + AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); + + return (old_mask); +} + +/* + * Enalbe HW radar detection + */ +void +ath5k_hw_radar_alert(struct ath_hal *hal, AR5K_BOOL enable) +{ + + AR5K_TRACE; + /* + * Enable radar detection + */ + + /*Disable interupts*/ + AR5K_REG_WRITE(AR5K_IER, AR5K_IER_DISABLE); + + /*Set AR5K_PHY_RADAR register*/ + if (enable == TRUE) { + AR5K_REG_WRITE(AR5K_PHY_RADAR, + AR5K_PHY_RADAR_ENABLE); + AR5K_REG_ENABLE_BITS(AR5K_PIMR, + AR5K_IMR_RXPHY); + } else { + AR5K_REG_WRITE(AR5K_PHY_RADAR, + AR5K_PHY_RADAR_DISABLE); + AR5K_REG_DISABLE_BITS(AR5K_PIMR, + AR5K_IMR_RXPHY); + } + + /*Re-enable interrupts*/ + AR5K_REG_WRITE(AR5K_IER, AR5K_IER_ENABLE); +} + + + + +/*************************\ + EEPROM access functions +\*************************/ + +/* + * Check if eeprom is busy + */ +AR5K_BOOL +ath5k_hw_eeprom_is_busy(struct ath_hal *hal) +{ + AR5K_TRACE; + return (AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? + TRUE : FALSE); +} + +/* + * Read from eeprom + */ +int +ath5k_hw_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) +{ + u_int32_t status, i; + + AR5K_TRACE; + /* + * Initialize EEPROM access + */ + AR5K_REG_WRITE(AR5K_EEPROM_BASE, (u_int8_t)offset); + AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_READ); + + for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { + status = AR5K_REG_READ(AR5K_EEPROM_STATUS); + if (status & AR5K_EEPROM_STAT_RDDONE) { + if (status & AR5K_EEPROM_STAT_RDERR) + return (EIO); + *data = (u_int16_t) + (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); + return (0); + } + AR5K_DELAY(15); + } + + return (ETIMEDOUT); +} + +/* + * Write to eeprom - currently disabled, use at your own risk + */ +int +ath5k_hw_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) +{ + u_int32_t status, timeout; + + AR5K_TRACE; + /* Enable eeprom access */ + AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_RESET); + + /* + * Write data to data register + * Disable this, it's not needed for + * normal operation, uncomment it if you + * need it. + */ + /* + AR5K_REG_WRITE(AR5K_EEPROM_DATA, data); + */ + AR5K_PRINTF("EEPROM Write is disabled!"); + + /* Write offset to base register */ + AR5K_REG_WRITE(AR5K_EEPROM_BASE, (u_int8_t)offset - 1); + + /* Issue write command */ + AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_WRITE); + + /* + * Check status + */ + + for (timeout = 10000; timeout > 0; timeout--) { + AR5K_DELAY(1); + status = AR5K_REG_READ(AR5K_EEPROM_STATUS); + if (status & AR5K_EEPROM_STAT_WRDONE) { + if (status & AR5K_EEPROM_STAT_WRERR) + return (EIO); + return (0); + } + } + + return (ETIMEDOUT); +} + +u_int16_t +ath5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) +{ + u_int16_t val; + + if (bin == AR5K_EEPROM_CHANNEL_DIS) + return (bin); + + if (mode == AR5K_EEPROM_MODE_11A) { + if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) + val = (5 * bin) + 4800; + else + val = bin > 62 ? + (10 * 62) + (5 * (bin - 62)) + 5100 : + (bin * 10) + 5100; + } else { + if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) + val = bin + 2300; + else + val = bin + 2400; + } + + return (val); +} + +/* + * Read antenna infos from eeprom + */ +int +ath5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u_int32_t o = *offset; + u_int16_t val; + int ret, i = 0; + + AR5K_EEPROM_READ(o++, val); + ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; + ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; + ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; + ee->ee_ant_control[mode][i++] = val & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; + ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; + ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; + ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; + ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; + ee->ee_ant_control[mode][i++] = val & 0x3f; + + /* Get antenna modes */ + hal->ah_antenna[mode][0] = + (ee->ee_ant_control[mode][0] << 4) | 0x1; + hal->ah_antenna[mode][AR5K_ANT_FIXED_A] = + ee->ee_ant_control[mode][1] | + (ee->ee_ant_control[mode][2] << 6) | + (ee->ee_ant_control[mode][3] << 12) | + (ee->ee_ant_control[mode][4] << 18) | + (ee->ee_ant_control[mode][5] << 24); + hal->ah_antenna[mode][AR5K_ANT_FIXED_B] = + ee->ee_ant_control[mode][6] | + (ee->ee_ant_control[mode][7] << 6) | + (ee->ee_ant_control[mode][8] << 12) | + (ee->ee_ant_control[mode][9] << 18) | + (ee->ee_ant_control[mode][10] << 24); + + /* return new offset */ + *offset = o; + + return (0); +} + +/* + * Read supported modes from eeprom + */ +int +ath5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u_int32_t o = *offset; + u_int16_t val; + int ret; + + AR5K_EEPROM_READ(o++, val); + ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; + ee->ee_thr_62[mode] = val & 0xff; + + if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) + ee->ee_thr_62[mode] = + mode == AR5K_EEPROM_MODE_11A ? 15 : 28; + + AR5K_EEPROM_READ(o++, val); + ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; + ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; + + AR5K_EEPROM_READ(o++, val); + ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; + + if ((val & 0xff) & 0x80) + ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); + else + ee->ee_noise_floor_thr[mode] = val & 0xff; + + if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) + ee->ee_noise_floor_thr[mode] = + mode == AR5K_EEPROM_MODE_11A ? -54 : -1; + + AR5K_EEPROM_READ(o++, val); + ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; + ee->ee_x_gain[mode] = (val >> 1) & 0xf; + ee->ee_xpd[mode] = val & 0x1; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) + ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { + AR5K_EEPROM_READ(o++, val); + ee->ee_false_detect[mode] = (val >> 6) & 0x7f; + + if (mode == AR5K_EEPROM_MODE_11A) + ee->ee_xr_power[mode] = val & 0x3f; + else { + ee->ee_ob[mode][0] = val & 0x7; + ee->ee_db[mode][0] = (val >> 3) & 0x7; + } + } + + if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { + ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; + ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; + } else { + ee->ee_i_gain[mode] = (val >> 13) & 0x7; + + AR5K_EEPROM_READ(o++, val); + ee->ee_i_gain[mode] |= (val << 3) & 0x38; + + if (mode == AR5K_EEPROM_MODE_11G) + ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; + } + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && + mode == AR5K_EEPROM_MODE_11A) { + ee->ee_i_cal[mode] = (val >> 8) & 0x3f; + ee->ee_q_cal[mode] = (val >> 3) & 0x1f; + } + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && + mode == AR5K_EEPROM_MODE_11G) + ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; + + /* return new offset */ + *offset = o; + + return (0); +} + +/* + * Initialize eeprom & capabilities structs + */ +int +ath5k_eeprom_init(struct ath_hal *hal) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u_int32_t offset; + u_int16_t val; + int ret, i; + u_int mode; + + /* Initial TX thermal adjustment values */ + ee->ee_tx_clip = 4; + ee->ee_pwd_84 = ee->ee_pwd_90 = 1; + ee->ee_gain_select = 1; + + /* + * Read values from EEPROM and store them in the capability structure + */ + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); + + /* Return if we have an old EEPROM */ + if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) + return (0); + +#ifdef notyet + /* + * Validate the checksum of the EEPROM date. There are some + * devices with invalid EEPROMs. + */ + for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { + AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); + cksum ^= val; + } + if (cksum != AR5K_EEPROM_INFO_CKSUM) { + AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); + return (AR5K_EEBADSUM); + } +#endif + + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), + ee_ant_gain); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); + } + + if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { + AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); + ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; + ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; + + AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); + ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; + ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; + } + + /* + * Get conformance test limit values + */ + offset = AR5K_EEPROM_CTL(hal->ah_ee_version); + ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); + + for (i = 0; i < ee->ee_ctls; i++) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_ctl[i] = (val >> 8) & 0xff; + ee->ee_ctl[i + 1] = val & 0xff; + } + + /* + * Get values for 802.11a (5GHz) + */ + mode = AR5K_EEPROM_MODE_11A; + + ee->ee_turbo_max_power[mode] = + AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); + + offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); + + if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + return (ret); + + AR5K_EEPROM_READ(offset++, val); + ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_ob[mode][3] = (val >> 5) & 0x7; + ee->ee_db[mode][3] = (val >> 2) & 0x7; + ee->ee_ob[mode][2] = (val << 1) & 0x7; + + AR5K_EEPROM_READ(offset++, val); + ee->ee_ob[mode][2] |= (val >> 15) & 0x1; + ee->ee_db[mode][2] = (val >> 12) & 0x7; + ee->ee_ob[mode][1] = (val >> 9) & 0x7; + ee->ee_db[mode][1] = (val >> 6) & 0x7; + ee->ee_ob[mode][0] = (val >> 3) & 0x7; + ee->ee_db[mode][0] = val & 0x7; + + if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + return (ret); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_margin_tx_rx[mode] = val & 0x3f; + } + + /* + * Get values for 802.11b (2.4GHz) + */ + mode = AR5K_EEPROM_MODE_11B; + offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); + + if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + return (ret); + + AR5K_EEPROM_READ(offset++, val); + ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_ob[mode][1] = (val >> 4) & 0x7; + ee->ee_db[mode][1] = val & 0x7; + + if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + return (ret); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][0] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ee->ee_cal_pier[mode][1] = + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][2] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + } + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; + } + + /* + * Get values for 802.11g (2.4GHz) + */ + mode = AR5K_EEPROM_MODE_11G; + offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); + + if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + return (ret); + + AR5K_EEPROM_READ(offset++, val); + ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); + ee->ee_ob[mode][1] = (val >> 4) & 0x7; + ee->ee_db[mode][1] = val & 0x7; + + if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + return (ret); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][0] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ee->ee_cal_pier[mode][1] = + ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + + AR5K_EEPROM_READ(offset++, val); + ee->ee_turbo_max_power[mode] = val & 0x7f; + ee->ee_xr_power[mode] = (val >> 7) & 0x3f; + + AR5K_EEPROM_READ(offset++, val); + ee->ee_cal_pier[mode][2] = + ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; + } + + AR5K_EEPROM_READ(offset++, val); + ee->ee_i_cal[mode] = (val >> 8) & 0x3f; + ee->ee_q_cal[mode] = (val >> 3) & 0x1f; + + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_cck_ofdm_gain_delta = val & 0xff; + } + } + + /* + * Read 5GHz EEPROM channels + */ + + return (0); +} + +/* + * Read the MAC address from eeprom + */ +int +ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) +{ + u_int32_t total, offset; + u_int16_t data; + int octet; + u_int8_t mac_d[IEEE80211_ADDR_LEN]; + + bzero(mac, IEEE80211_ADDR_LEN); + bzero(&mac_d, IEEE80211_ADDR_LEN); + + if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) + return (AR5K_EIO); + + for (offset = 0x1f, octet = 0, total = 0; + offset >= 0x1d; offset--) { + if (hal->ah_eeprom_read(hal, offset, &data) != 0) + return (AR5K_EIO); + + total += data; + mac_d[octet + 1] = data & 0xff; + mac_d[octet] = data >> 8; + octet += 2; + } + + bcopy(mac_d, mac, IEEE80211_ADDR_LEN); + + if ((!total) || total == (3 * 0xffff)) + return (AR5K_EINVAL); + + return (0); +} + +/* + * Read/Write refulatory domain + */ +AR5K_BOOL +ath5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, + ieee80211_regdomain_t *regdomain) +{ + u_int16_t ee_regdomain; + + /* Read current value */ + if (write != TRUE) { + ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; + *regdomain = ath5k_regdomain_to_ieee(ee_regdomain); + return (TRUE); + } + + ee_regdomain = ath5k_regdomain_from_ieee(*regdomain); + + /* Try to write a new value */ + if (hal->ah_capabilities.cap_eeprom.ee_protect & + AR5K_EEPROM_PROTECT_WR_128_191) + return (FALSE); + if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, + ee_regdomain) != 0) + return (FALSE); + + hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; + + return (TRUE); +} + +/* + * Use the above to write a new regulatory domain + */ +AR5K_BOOL +ath5k_hw_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, + AR5K_STATUS *status) +{ + ieee80211_regdomain_t ieee_regdomain; + + ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); + + if (ath5k_eeprom_regulation_domain(hal, TRUE, + &ieee_regdomain) == TRUE) { + *status = AR5K_OK; + return (TRUE); + } + + *status = AR5K_EIO; + + return (FALSE); +} + +/* + * Fill the capabilities struct + */ +AR5K_BOOL +ath5k_hw_get_capabilities(struct ath_hal *hal) +{ + u_int16_t ee_header; + + AR5K_TRACE; + /* Capabilities stored in the EEPROM */ + ee_header = hal->ah_capabilities.cap_eeprom.ee_header; + + /* + * XXX The tranceiver supports frequencies from 4920 to 6100GHz + * XXX and from 2312 to 2732GHz. There are problems with the current + * XXX ieee80211 implementation because the IEEE channel mapping + * XXX does not support negative channel numbers (2312MHz is channel + * XXX -19). Of course, this doesn't matter because these channels + * XXX are out of range but some regulation domains like MKK (Japan) + * XXX will support frequencies somewhere around 4.8GHz. + */ + + /* + * Set radio capabilities + */ + + if (AR5K_EEPROM_HDR_11A(ee_header)) { + hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ + hal->ah_capabilities.cap_range.range_5ghz_max = 6100; + + /* Set supported modes */ + hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO | + (hal->ah_version == AR5K_AR5212 ? AR5K_MODE_XR : 0); + } + + /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ + if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { + hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ + hal->ah_capabilities.cap_range.range_2ghz_max = 2732; + + if (AR5K_EEPROM_HDR_11B(ee_header)) + hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; +#if 0 + if (AR5K_EEPROM_HDR_11G(ee_header)) + hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; +#endif + } + + /* GPIO */ + hal->ah_gpio_npins = AR5K_NUM_GPIO; + + /* Set number of supported TX queues */ + hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; + + return (TRUE); +} + + + + +/*********************************\ + Protocol Control Unit Functions +\*********************************/ + +/* + * Set Operation mode + */ +void +ath5k_hw_set_opmode(struct ath_hal *hal) +{ + u_int32_t pcu_reg, low_id, high_id; + + pcu_reg = 0; + + AR5K_TRACE; + + switch (hal->ah_op_mode) { + case AR5K_M_IBSS: + pcu_reg |= AR5K_STA_ID1_ADHOC | + AR5K_STA_ID1_DESC_ANTENNA; + break; + + case AR5K_M_HOSTAP: + pcu_reg |= AR5K_STA_ID1_AP | + AR5K_STA_ID1_RTS_DEF_ANTENNA; + break; + + case AR5K_M_STA: + case AR5K_M_MONITOR: + pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA; + break; + + default: + return; + } + + /* + * Set PCU registers + * TODO: Test this on big endian + */ + low_id = AR5K_LOW_ID(hal->ah_sta_id); + high_id = AR5K_HIGH_ID(hal->ah_sta_id); + AR5K_REG_WRITE(AR5K_STA_ID0, low_id); + AR5K_REG_WRITE(AR5K_STA_ID1, pcu_reg | high_id); + + return; +} + +void /*TODO: Get rid of this, clean up the driver code, only set_opmode is needed*/ +ath5k_hw_set_pcu_config(struct ath_hal *hal) +{ + AR5K_TRACE; + ath5k_hw_set_opmode(hal); + return; +} + +/* + * BSSID Functions + */ + +/* + * Get station id + */ +void +ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) +{ + AR5K_TRACE; + bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); +} + +/* + * Set station id + */ +AR5K_BOOL +ath5k_hw_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) +{ + u_int32_t low_id, high_id; + + AR5K_TRACE; + /* Set new station ID */ + bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); + + low_id = AR5K_LOW_ID(mac); + high_id = AR5K_HIGH_ID(mac); + + AR5K_REG_WRITE(AR5K_STA_ID0, low_id); + AR5K_REG_WRITE(AR5K_STA_ID1, high_id); + + return (TRUE); +} + +/* + * Set BSSID + */ +void +ath5k_hw_set_associd(struct ath_hal *hal, const u_int8_t *bssid, + u_int16_t assoc_id) +{ + u_int32_t low_id, high_id; + u_int16_t tim_offset = 0; + + /* + * Set simple BSSID mask on 5212 + */ + if(hal->ah_version == AR5K_AR5212){ + AR5K_REG_WRITE(AR5K_BSS_IDM0, 0xfffffff); + AR5K_REG_WRITE(AR5K_BSS_IDM1, 0xfffffff); + } + + /* + * Set BSSID which triggers the "SME Join" operation + */ + low_id = AR5K_LOW_ID(bssid); + high_id = AR5K_HIGH_ID(bssid); + AR5K_REG_WRITE(AR5K_BSS_ID0, low_id); + AR5K_REG_WRITE(AR5K_BSS_ID1, high_id | + ((assoc_id & 0x3fff) << AR5K_BSS_ID1_AID_S)); + bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN); + + if (assoc_id == 0) { + ath5k_hw_disable_pspoll(hal); + return; + } + + AR5K_REG_WRITE(AR5K_BEACON, + (AR5K_REG_READ(AR5K_BEACON) & + ~AR5K_BEACON_TIM) | + (((tim_offset ? tim_offset + 4 : 0) << + AR5K_BEACON_TIM_S) & + AR5K_BEACON_TIM)); + + ath5k_hw_enable_pspoll(hal, NULL, 0); +} + +/* + * Set BSSID mask on 5212 + */ +AR5K_BOOL +ath5k_hw_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) +{ + u_int32_t low_id, high_id; + AR5K_TRACE; + + if(hal->ah_version == AR5K_AR5212){ + + low_id = AR5K_LOW_ID(mask); + high_id = AR5K_HIGH_ID(mask); + + AR5K_REG_WRITE(AR5K_BSS_IDM0, low_id); + AR5K_REG_WRITE(AR5K_BSS_IDM1, high_id); + + return (TRUE); + } else { + return (FALSE); + } +} + +/* + * Receive start/stop functions + */ + +/* + * Start receive on PCU + */ +void +ath5k_hw_start_rx_pcu(struct ath_hal *hal) +{ + AR5K_TRACE; + AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); +} + +/* + * Stop receive on PCU + */ +void +ath5k_hw_stop_pcu_recv(struct ath_hal *hal) +{ + AR5K_TRACE; + AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); +} + +/* + * RX Filter functions + */ + +/* + * Set multicast filter + */ +void +ath5k_hw_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, + u_int32_t filter1) +{ + AR5K_TRACE; + /* Set the multicat filter */ + AR5K_REG_WRITE(AR5K_MCAST_FILTER0, filter0); + AR5K_REG_WRITE(AR5K_MCAST_FILTER1, filter1); +} + +/* + * Set multicast filter by index + */ +AR5K_BOOL +ath5k_hw_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) +{ + + AR5K_TRACE; + if (index >= 64) { + return (FALSE); + } else if (index >= 32) { + AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1, + (1 << (index - 32))); + } else { + AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0, + (1 << index)); + } + + return (TRUE); +} + +/* + * Clear Multicast filter + */ +AR5K_BOOL +ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) +{ + + AR5K_TRACE; + if (index >= 64) { + return (FALSE); + } else if (index >= 32) { + AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1, + (1 << (index - 32))); + } else { + AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0, + (1 << index)); + } + + return (TRUE); +} + +/* + * Get current rx filter + */ +u_int32_t +ath5k_hw_get_rx_filter(struct ath_hal *hal) +{ + u_int32_t data, filter = 0; + + AR5K_TRACE; + filter = AR5K_REG_READ(AR5K_RX_FILTER); + + /*Radar detection for 5212*/ + if(hal->ah_version == AR5K_AR5212){ + data = AR5K_REG_READ(AR5K_PHY_ERR_FIL); + + if (data & AR5K_PHY_ERR_FIL_RADAR) + filter |= AR5K_RX_FILTER_PHYRADAR; + if (data & (AR5K_PHY_ERR_FIL_OFDM | + AR5K_PHY_ERR_FIL_CCK)) + filter |= AR5K_RX_FILTER_PHYERR; + } + + return (filter); +} + +/* + * Set rx filter + */ +void +ath5k_hw_set_rx_filter(struct ath_hal *hal, u_int32_t filter) +{ + u_int32_t data = 0; + + AR5K_TRACE; + + /* Set PHY error filter register on 5212*/ + if(hal->ah_version == AR5K_AR5212){ + if (filter & AR5K_RX_FILTER_PHYRADAR) + data |= AR5K_PHY_ERR_FIL_RADAR; + if (filter & AR5K_RX_FILTER_PHYERR) + data |= AR5K_PHY_ERR_FIL_OFDM | + AR5K_PHY_ERR_FIL_CCK; + } + + /* + * Got that from roofnet... + * Don't filter control frames & set promiscuous mode + */ + data |= AR5K_RX_FILTER_PROM | AR5K_RX_FILTER_CONTROL; + + /*Zero length DMA*/ + if (data) { + AR5K_REG_ENABLE_BITS(AR5K_RXCFG, + AR5K_RXCFG_ZLFDMA); + } else { + AR5K_REG_DISABLE_BITS(AR5K_RXCFG, + AR5K_RXCFG_ZLFDMA); + } + + /*Write RX Filter register*/ + AR5K_REG_WRITE(AR5K_RX_FILTER, filter & 0xff); + + /*Write PHY error filter register on 5212*/ + if(hal->ah_version == AR5K_AR5212){ + AR5K_REG_WRITE(AR5K_PHY_ERR_FIL, data); + } + +} + +/* + * Beacon related functions + */ + +/* + * Get a 32bit TSF + */ +u_int32_t +ath5k_hw_get_tsf32(struct ath_hal *hal) +{ + AR5K_TRACE; + return (AR5K_REG_READ(AR5K_TSF_L32)); +} + +/* + * Get the full 64bit TSF + */ +u_int64_t +ath5k_hw_get_tsf64(struct ath_hal *hal) +{ + u_int64_t tsf = AR5K_REG_READ(AR5K_TSF_U32); + AR5K_TRACE; + + return (AR5K_REG_READ(AR5K_TSF_L32) | (tsf << 32)); +} + +/* + * Force a TSF reset + */ +void +ath5k_hw_reset_tsf(struct ath_hal *hal) +{ + AR5K_TRACE; + AR5K_REG_ENABLE_BITS(AR5K_BEACON, + AR5K_BEACON_RESET_TSF); +} + +/* + * Initialize beacon timers + */ +void +ath5k_hw_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, + u_int32_t interval) +{ + u_int32_t timer1, timer2, timer3; + + AR5K_TRACE; + /* + * Set the additional timers by mode + */ + switch (hal->ah_op_mode) { + case AR5K_M_STA: + timer1 = 0x0000ffff; + timer2 = 0x0007ffff; + break; + + default: + timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << + 0x00000003; + timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << + 0x00000003; + } + + timer3 = next_beacon + + (hal->ah_atim_window ? hal->ah_atim_window : 1); + + /* + * Enable all timers and set the beacon register + * (next beacon, DMA beacon, software beacon, ATIM window time) + */ + AR5K_REG_WRITE(AR5K_TIMER0, next_beacon); + AR5K_REG_WRITE(AR5K_TIMER1, timer1); + AR5K_REG_WRITE(AR5K_TIMER2, timer2); + AR5K_REG_WRITE(AR5K_TIMER3, timer3); + + AR5K_REG_WRITE(AR5K_BEACON, interval & + (AR5K_BEACON_PERIOD | AR5K_BEACON_RESET_TSF | + AR5K_BEACON_ENABLE)); +} + +/* + * Set beacon timers + * TODO: should be changed through *state - review AR5K_BEACON_STATE struct + */ +void +ath5k_hw_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) +{ + u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; + + u_int32_t dtim_count = 0; /* XXX */ + u_int32_t cfp_count = 0; /* XXX */ + u_int32_t tsf = 0; /* XXX */ + + AR5K_TRACE; + /* Return on an invalid beacon state */ + if (state->bs_interval < 1) + return; + + interval = state->bs_interval; + dtim = state->bs_dtim_period; + + /* + * PCF support? + */ + if (state->bs_cfp_period > 0) { + /* + * Enable CFP (Contention Free Period) mode and set the CFP + * and timer registers + */ + cfp_period = state->bs_cfp_period * state->bs_dtim_period * + state->bs_interval; + next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * + state->bs_interval; + + AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, + AR5K_STA_ID1_DEFAULT_ANTENNA | + AR5K_STA_ID1_PCF); + AR5K_REG_WRITE(AR5K_CFP_PERIOD, cfp_period); + AR5K_REG_WRITE(AR5K_CFP_DUR, state->bs_cfp_max_duration); + AR5K_REG_WRITE(AR5K_TIMER2, + (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); + } else { + /* Disable PCF mode */ + AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_STA_ID1_DEFAULT_ANTENNA | + AR5K_STA_ID1_PCF); + } + + /* + * Enable the beacon timer register + */ + AR5K_REG_WRITE(AR5K_TIMER0, state->bs_next_beacon); + + /* + * Start the beacon timers + */ + AR5K_REG_WRITE(AR5K_BEACON, + (AR5K_REG_READ(AR5K_BEACON) &~ + (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | + AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, + AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, + AR5K_BEACON_PERIOD)); + + /* + * Write new beacon miss threshold, if it appears to be valid + */ + if ((AR5K_RSSI_THR_BMISS >> AR5K_RSSI_THR_BMISS_S) < + state->bs_bmiss_threshold) + return; + + AR5K_REG_WRITE_BITS(AR5K_RSSI_THR_M, + AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); + + /* + * Set sleep control register + */ + AR5K_REG_WRITE_BITS(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, + (state->bs_sleep_duration - 3) << 3); + + /* + * Set enhanced sleep registers on 5212 + */ + if(hal->ah_version == AR5K_AR5212){ + if ((state->bs_sleep_duration > state->bs_interval) && + (roundup(state->bs_sleep_duration, interval) == + state->bs_sleep_duration)) + interval = state->bs_sleep_duration; + + if (state->bs_sleep_duration > dtim && + (dtim == 0 || roundup(state->bs_sleep_duration, dtim) == + state->bs_sleep_duration)) + dtim = state->bs_sleep_duration; + + if (interval > dtim) + return; + + next_beacon = interval == dtim ? + state->bs_next_dtim: state->bs_next_beacon; + + AR5K_REG_WRITE(AR5K_SLEEP0, + AR5K_REG_SM((state->bs_next_dtim - 3) << 3, + AR5K_SLEEP0_NEXT_DTIM) | + AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | + AR5K_SLEEP0_ENH_SLEEP_EN | + AR5K_SLEEP0_ASSUME_DTIM); + + AR5K_REG_WRITE(AR5K_SLEEP1, + AR5K_REG_SM((next_beacon - 3) << 3, + AR5K_SLEEP1_NEXT_TIM) | + AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO)); + + AR5K_REG_WRITE(AR5K_SLEEP2, + AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | + AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER)); + } +} + +/* + * Reset beacon timers + */ +void +ath5k_hw_reset_beacon(struct ath_hal *hal) +{ + AR5K_TRACE; + /* + * Disable beacon timer + */ + AR5K_REG_WRITE(AR5K_TIMER0, 0); + + /* + * Disable some beacon register values + */ + AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); + AR5K_REG_WRITE(AR5K_BEACON, AR5K_BEACON_PERIOD); +} + +/* + * Wait for beacon queue to finish + */ +AR5K_BOOL +ath5k_hw_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) +{ + AR5K_BOOL ret; + + AR5K_TRACE; + + ret = ath5k_hw_register_timeout(hal, + AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), + AR5K_QCU_STS_FRMPENDCNT, 0, FALSE); + + if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) + return (FALSE); + + return (ret); +} + +/* + * Update mib counters (statistics) + */ +void +ath5k_hw_update_mib_counters(struct ath_hal *hal, AR5K_MIB_STATS *statistics) +{ + AR5K_TRACE; + /* Read-And-Clear */ + statistics->ackrcv_bad += AR5K_REG_READ(AR5K_ACK_FAIL); + statistics->rts_bad += AR5K_REG_READ(AR5K_RTS_FAIL); + statistics->rts_good += AR5K_REG_READ(AR5K_RTS_OK); + statistics->fcs_bad += AR5K_REG_READ(AR5K_FCS_FAIL); + statistics->beacons += AR5K_REG_READ(AR5K_BEACON_CNT); + + /* Reset profile count registers on 5212*/ + if(hal->ah_version == AR5K_AR5212){ + AR5K_REG_WRITE(AR5K_PROFCNT_TX, 0); + AR5K_REG_WRITE(AR5K_PROFCNT_RX, 0); + AR5K_REG_WRITE(AR5K_PROFCNT_RXCLR, 0); + AR5K_REG_WRITE(AR5K_PROFCNT_CYCLE, 0); + } +} + +void /*Unimplemented*/ +ath5k_hw_proc_mib_event(struct ath_hal *hal, const AR5K_NODE_STATS *stats) +{ + AR5K_TRACE; + return; +} + +/* + * ACK/CTS Timeouts + */ + +/* + * Set ACK timeout on PCU + */ +AR5K_BOOL +ath5k_hw_set_ack_timeout(struct ath_hal *hal, u_int timeout) +{ + AR5K_TRACE; + if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), + hal->ah_turbo) <= timeout) + return (FALSE); + + AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, + ath5k_hw_htoclock(timeout, hal->ah_turbo)); + + return (TRUE); +} + +/* + * Read the ACK timeout from PCU + */ +u_int +ath5k_hw_get_ack_timeout(struct ath_hal *hal) +{ + AR5K_TRACE; + return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), + AR5K_TIME_OUT_ACK), hal->ah_turbo)); +} + +/* + * Set CTS timeout on PCU + */ +AR5K_BOOL +ath5k_hw_set_cts_timeout(struct ath_hal *hal, u_int timeout) +{ + AR5K_TRACE; + if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), + hal->ah_turbo) <= timeout) + return (FALSE); + + AR5K_REG_WRITE_BITS(AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, + ath5k_hw_htoclock(timeout, hal->ah_turbo)); + + return (TRUE); +} + +/* + * Read CTS timeout from PCU + */ +u_int +ath5k_hw_get_cts_timeout(struct ath_hal *hal) +{ + AR5K_TRACE; + return (ath5k_hw_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_TIME_OUT), + AR5K_TIME_OUT_CTS), hal->ah_turbo)); +} + +/* + * Key table (WEP) functions + */ + +/* + * Return which ciphers are supported by hw + */ +AR5K_BOOL +ath5k_hw_is_cipher_supported(struct ath_hal *hal, AR5K_CIPHER cipher) +{ + AR5K_TRACE; + /* + * Only WEP for now + */ + if (cipher == AR5K_CIPHER_WEP) + return (TRUE); + + return (FALSE); +} + +/* + * Get key cache size + */ +u_int32_t +ath5k_hw_get_keycache_size(struct ath_hal *hal) +{ + AR5K_TRACE; + return (AR5K_KEYCACHE_SIZE); +} + +/* + * Reset encryption key + */ +AR5K_BOOL +ath5k_hw_reset_key(struct ath_hal *hal, u_int16_t entry) +{ + int i; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) + AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), 0); + + /* Set NULL encryption */ + AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), + AR5K_KEYTABLE_TYPE_NULL); + + return (FALSE); /*????*/ +} + +/* + * Check if a key entry is valid + */ +AR5K_BOOL +ath5k_hw_is_key_valid(struct ath_hal *hal, u_int16_t entry) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + /* + * Check the validation flag at the end of the entry + */ + if (AR5K_REG_READ(AR5K_KEYTABLE_MAC1(entry)) & + AR5K_KEYTABLE_VALID) + return (TRUE); + + return (FALSE); +} + +/* + * Set encryption key + */ +AR5K_BOOL +ath5k_hw_set_key(struct ath_hal *hal, u_int16_t entry, + const AR5K_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) +{ + int i; + u_int32_t key_v[AR5K_KEYCACHE_SIZE - 2]; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + bzero(&key_v, sizeof(key_v)); + + switch (keyval->wk_len) { + case AR5K_KEYVAL_LENGTH_40: + bcopy(keyval->wk_key, &key_v[0], 4); + bcopy(keyval->wk_key + 4, &key_v[1], 1); + key_v[5] = AR5K_KEYTABLE_TYPE_40; + break; + + case AR5K_KEYVAL_LENGTH_104: + bcopy(keyval->wk_key, &key_v[0], 4); + bcopy(keyval->wk_key + 4, &key_v[1], 2); + bcopy(keyval->wk_key + 6, &key_v[2], 4); + bcopy(keyval->wk_key + 10, &key_v[3], 2); + bcopy(keyval->wk_key + 12, &key_v[4], 1); + key_v[5] = AR5K_KEYTABLE_TYPE_104; + break; + + case AR5K_KEYVAL_LENGTH_128: + bcopy(keyval->wk_key, &key_v[0], 4); + bcopy(keyval->wk_key + 4, &key_v[1], 2); + bcopy(keyval->wk_key + 6, &key_v[2], 4); + bcopy(keyval->wk_key + 10, &key_v[3], 2); + bcopy(keyval->wk_key + 12, &key_v[4], 4); + key_v[5] = AR5K_KEYTABLE_TYPE_128; + break; + + default: + /* Unsupported key length (not WEP40/104/128) */ + return (FALSE); + } + + for (i = 0; i < AR5K_ELEMENTS(key_v); i++) + AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), key_v[i]); + + return (ath5k_hw_set_key_lladdr(hal, entry, mac)); +} + +AR5K_BOOL +ath5k_hw_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, + const u_int8_t *mac) +{ + u_int32_t low_id, high_id; + const u_int8_t *mac_v; + + AR5K_TRACE; + /* + * Invalid entry (key table overflow) + */ + AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); + + /* MAC may be NULL if it's a broadcast key */ + mac_v = mac == NULL ? etherbroadcastaddr : mac; + + low_id = AR5K_LOW_ID(mac_v); + high_id = AR5K_HIGH_ID(mac_v) | AR5K_KEYTABLE_VALID; + + AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id); + AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id); + + return (TRUE); +} + + + + +/********************************************\ +Queue Control Unit, DFS Control Unit Functions +\********************************************/ + +/* + * Initialize a transmit queue + */ +int +ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, + AR5K_TXQ_INFO *queue_info) +{ + u_int queue; + AR5K_TRACE; + + /* + * Get queue by type + */ + if (queue_type == AR5K_TX_QUEUE_DATA) { + for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; + hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; + queue++) + if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) + return (-1); + } else if (queue_type == AR5K_TX_QUEUE_UAPSD) { + queue = AR5K_TX_QUEUE_ID_UAPSD; + } else if (queue_type == AR5K_TX_QUEUE_BEACON) { + queue = AR5K_TX_QUEUE_ID_BEACON; + } else if (queue_type == AR5K_TX_QUEUE_CAB) { + queue = AR5K_TX_QUEUE_ID_CAB; + } else + return (-1); + + /* + * Setup internal queue structure + */ + bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + hal->ah_txq[queue].tqi_type = queue_type; + + if (queue_info != NULL) { + queue_info->tqi_type = queue_type; + if (ath5k_hw_setup_tx_queueprops(hal, queue, queue_info) + != TRUE) + return (-1); + } + + AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); + + return (queue); +} + +/* + * Setup a transmit queue + * TODO: Shouldn't we set DFS params here (see reset_tx_queue) ? + */ +AR5K_BOOL +ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, + const AR5K_TXQ_INFO *queue_info) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (FALSE); + + bcopy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + + if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && + ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || + (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || + queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) + hal->ah_txq[queue].tqi_flags |= + AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; + + return (TRUE); +} + +/* + * Get properties for a specific transmit queue + */ +AR5K_BOOL +ath5k_hw_get_tx_queueprops(struct ath_hal *hal, int queue, AR5K_TXQ_INFO *queue_info) +{ + AR5K_TRACE; + memcpy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + return (TRUE); +} + +/* + * Set a transmit queue inactive + */ +AR5K_BOOL +ath5k_hw_release_tx_queue(struct ath_hal *hal, u_int queue) +{ + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + /* This queue will be skipped in further operations */ + hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; + AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); + + return (FALSE); /*???*/ +} + +/* + * Set DFS params for a transmit queue + */ +AR5K_BOOL +ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) +{ + u_int32_t cw_min, cw_max, retry_lg, retry_sh; + AR5K_TXQ_INFO *tq; + + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + tq = &hal->ah_txq[queue]; + + if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (TRUE); + + /* + * Set registers by channel mode + */ + cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; + cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; + hal->ah_aifs = AR5K_TUNE_AIFS; + /*XR is only supported on 5212*/ + if (IS_CHAN_XR(hal->ah_current_channel) && (hal->ah_version == AR5K_AR5212)) { + cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; + cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; + hal->ah_aifs = AR5K_TUNE_AIFS_XR; + } else if (IS_CHAN_B(hal->ah_current_channel)) { + cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; + cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; + hal->ah_aifs = AR5K_TUNE_AIFS_11B; + } + + /* + * Set retry limits + */ + if (hal->ah_software_retry == TRUE) { + /* XXX Need to test this */ + retry_lg = hal->ah_limit_tx_retries; + retry_sh = retry_lg = + retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? + AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; + } else { + retry_lg = AR5K_INIT_LG_RETRY; + retry_sh = AR5K_INIT_SH_RETRY; + } + + AR5K_REG_WRITE(AR5K_QUEUE_DFS_RETRY_LIMIT(queue), + AR5K_REG_SM(AR5K_INIT_SLG_RETRY, + AR5K_DCU_RETRY_LMT_SLG_RETRY) | + AR5K_REG_SM(AR5K_INIT_SSH_RETRY, + AR5K_DCU_RETRY_LMT_SSH_RETRY) | + AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | + AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY)); + + /* + * Set initial content window (cw_min/cw_max) + * and arbitrated interframe space (aifs)... + */ + cw_min = 1; + + while (cw_min < hal->ah_cw_min) + cw_min = (cw_min << 1) | 1; + + cw_min = tq->tqi_cw_min < 0 ? + (cw_min >> (-tq->tqi_cw_min)) : + ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); + cw_max = tq->tqi_cw_max < 0 ? + (cw_max >> (-tq->tqi_cw_max)) : + ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); + + AR5K_REG_WRITE(AR5K_QUEUE_DFS_LOCAL_IFS(queue), + AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | + AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | + AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, + AR5K_DCU_LCL_IFS_AIFS)); + + /* + * Set misc registers + */ + AR5K_REG_WRITE(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_DCU_EARLY); + + if (tq->tqi_cbr_period) { + AR5K_REG_WRITE(AR5K_QUEUE_CBRCFG(queue), + AR5K_REG_SM(tq->tqi_cbr_period, + AR5K_QCU_CBRCFG_INTVAL) | + AR5K_REG_SM(tq->tqi_cbr_overflow_limit, + AR5K_QCU_CBRCFG_ORN_THRES)); + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_CBR); + if (tq->tqi_cbr_overflow_limit) + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_CBR_THRES_ENABLE); + } + + if (tq->tqi_ready_time) { + AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), + AR5K_REG_SM(tq->tqi_ready_time, + AR5K_QCU_RDYTIMECFG_INTVAL) | + AR5K_QCU_RDYTIMECFG_ENABLE); + } + + if (tq->tqi_burst_time) { + AR5K_REG_WRITE(AR5K_QUEUE_DFS_CHANNEL_TIME(queue), + AR5K_REG_SM(tq->tqi_burst_time, + AR5K_DCU_CHAN_TIME_DUR) | + AR5K_DCU_CHAN_TIME_ENABLE); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_TXE); + } + } + + if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { + AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), + AR5K_DCU_MISC_POST_FR_BKOFF_DIS); + } + + if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { + AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), + AR5K_DCU_MISC_BACKOFF_FRAG); + } + + /* + * Set registers by queue type + */ + switch (tq->tqi_type) { + case AR5K_TX_QUEUE_BEACON: + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_DBA_GT | + AR5K_QCU_MISC_CBREXP_BCN | + AR5K_QCU_MISC_BCN_ENABLE); + + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << + AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL) | + AR5K_DCU_MISC_POST_FR_BKOFF_DIS | + AR5K_DCU_MISC_BCN_ENABLE); + + AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), + ((AR5K_TUNE_BEACON_INTERVAL - + (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - + AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | + AR5K_QCU_RDYTIMECFG_ENABLE); + break; + + case AR5K_TX_QUEUE_CAB: + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_DBA_GT | + AR5K_QCU_MISC_CBREXP | + AR5K_QCU_MISC_CBREXP_BCN); + + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << + AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL)); + break; + + case AR5K_TX_QUEUE_UAPSD: + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_CBREXP); + break; + + case AR5K_TX_QUEUE_DATA: + default: + break; + } + + /* + * Enable tx queue in the secondary interrupt mask registers + */ + AR5K_REG_WRITE(AR5K_SIMR0, + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXOK) | + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXDESC)); + AR5K_REG_WRITE(AR5K_SIMR1, + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR1_QCU_TXERR)); + AR5K_REG_WRITE(AR5K_SIMR2, + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); + + return (TRUE); +} + +/* + * Get number of pending frames + * for a specific queue + */ +u_int32_t +ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) { + AR5K_TRACE; + AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + return (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT); +} + +/* + * Set slot time + */ +AR5K_BOOL +ath5k_hw_set_slot_time(struct ath_hal *hal, u_int slot_time) +{ + AR5K_TRACE; + if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) + return (FALSE); + + AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); + + return (TRUE); +} + +/* + * Get slot time + */ +u_int +ath5k_hw_get_slot_time(struct ath_hal *hal) +{ + AR5K_TRACE; + return (AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff); +} + + + + +/******************************\ + Hardware Descriptor Functions +\******************************/ + +/* + * TX Descriptor + */ + +/* + * Initialize the tx descriptor on 5211 + */ +AR5K_BOOL +ath5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, + u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, + u_int flags, u_int rtscts_rate, u_int rtscts_duration) +{ + struct ath5k_ar5211_tx_desc *tx_desc; + + tx_desc = (struct ath5k_ar5211_tx_desc*)&desc->ds_ctl0; + + /* + * Validate input + */ + if (tx_tries0 == 0) + return (FALSE); + + /* Initialize status descriptor */ + tx_desc->tx_control_0 = 0; + tx_desc->tx_control_1 = 0; + + /* Setup status descriptor */ + + if ((tx_desc->tx_control_0 = (packet_length & + AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) + return (FALSE); + + tx_desc->tx_control_0 |= + AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | + AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); + tx_desc->tx_control_1 = + AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); + +#define _TX_FLAGS(_c, _flag) \ + if (flags & AR5K_TXDESC_##_flag) \ + tx_desc->tx_control_##_c |= \ + AR5K_AR5211_DESC_TX_CTL##_c##_##_flag + + _TX_FLAGS(0, CLRDMASK); + _TX_FLAGS(0, VEOL); + _TX_FLAGS(0, INTREQ); + _TX_FLAGS(0, RTSENA); + _TX_FLAGS(1, NOACK); + +#undef _TX_FLAGS + + /* + * WEP crap + */ + if (key_index != AR5K_TXKEYIX_INVALID) { + tx_desc->tx_control_0 |= + AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; + tx_desc->tx_control_1 |= + AR5K_REG_SM(key_index, + AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); + } + + return (TRUE); +} + +/* + * Initialize tx descriptor on 5212 + */ +AR5K_BOOL +ath5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, + u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, + u_int flags, u_int rtscts_rate, u_int rtscts_duration) +{ + struct ath5k_ar5212_tx_desc *tx_desc; + + AR5K_TRACE; + + tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; + + /* + * Validate input + */ + if (tx_tries0 == 0) + return (FALSE); + + /* Initialize status descriptor */ + tx_desc->tx_control_0 = 0; + tx_desc->tx_control_1 = 0; + tx_desc->tx_control_2 = 0; + tx_desc->tx_control_3 = 0; + + /* Setup status descriptor */ + if ((tx_desc->tx_control_0 = (packet_length & + AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length) + return (FALSE); + + tx_desc->tx_control_0 |= + AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) | + AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT); + tx_desc->tx_control_1 = + AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE); + tx_desc->tx_control_2 = + AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, + AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0); + tx_desc->tx_control_3 = + tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; + +#define _TX_FLAGS(_c, _flag) \ + if (flags & AR5K_TXDESC_##_flag) \ + tx_desc->tx_control_##_c |= \ + AR5K_AR5212_DESC_TX_CTL##_c##_##_flag + + _TX_FLAGS(0, CLRDMASK); + _TX_FLAGS(0, VEOL); + _TX_FLAGS(0, INTREQ); + _TX_FLAGS(0, RTSENA); + _TX_FLAGS(0, CTSENA); + _TX_FLAGS(1, NOACK); + +#undef _TX_FLAGS + + /* + * WEP crap + */ + if (key_index != AR5K_TXKEYIX_INVALID) { + tx_desc->tx_control_0 |= + AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID; + tx_desc->tx_control_1 |= + AR5K_REG_SM(key_index, + AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); + } + + /* + * RTS/CTS + */ + if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { + if ((flags & AR5K_TXDESC_RTSENA) && + (flags & AR5K_TXDESC_CTSENA)) + return (FALSE); + tx_desc->tx_control_2 |= + rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION; + tx_desc->tx_control_3 |= + AR5K_REG_SM(rtscts_rate, + AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE); + } + + return (TRUE); +} + +/* + * Fill tx descriptor on 5211 + */ +AR5K_BOOL/*Added an argument *last_desc -need revision*/ +ath5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) +{ + struct ath5k_ar5211_tx_desc *tx_desc; + + tx_desc = (struct ath5k_ar5211_tx_desc*)&desc->ds_ctl0; + + /* Clear status descriptor */ + bzero(desc->ds_hw, sizeof(desc->ds_hw)); + + /* Validate segment length and initialize the descriptor */ + if ((tx_desc->tx_control_1 = (segment_length & + AR5K_AR5211_DESC_TX_CTL1_BUF_LEN)) != segment_length) + return (FALSE); + + if (first_segment != TRUE) + tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; + + if (last_segment != TRUE) + tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; + + return (TRUE); +} + +/* + * Fill tx descriptor on 5212 + */ +AR5K_BOOL /*Added an argument *last_desc -need revision*/ +ath5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, + const struct ath_desc *last_desc) +{ + struct ath5k_ar5212_tx_desc *tx_desc; + struct ath5k_tx_status *tx_status; + + AR5K_TRACE; + tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_tx_status*)&desc->ds_hw[2]; + + /* Clear status descriptor */ + bzero(tx_status, sizeof(struct ath5k_tx_status)); + + /* Validate segment length and initialize the descriptor */ + if ((tx_desc->tx_control_1 = (segment_length & + AR5K_AR5212_DESC_TX_CTL1_BUF_LEN)) != segment_length) + return (FALSE); + +/*Code from roofnet*/ +// if (segment_length> AR5K_AR5212_DESC_TX_CTL1_BUF_LEN){ +// return (FALSE); +//} +// tx_desc->tx_control_1 &= ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN; +// tx_desc->tx_control_1 |= (segment_length & AR5K_AR5212_DESC_TX_CTL1_BUF_LEN); +/* */ + if (first_segment != TRUE) + tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN; + + if (last_segment != TRUE) + tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE; + + return (TRUE); +} + +/* + * There is no XR in5211 + */ +AR5K_BOOL +ath5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, + u_int tx_rate3, u_int tx_tries3) +{ + /*XR not supported on 5211*/ + return (FALSE); +} + +/* + * Initialize an XR tx descriptor on 5212 + */ +AR5K_BOOL +ath5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, + u_int tx_rate3, u_int tx_tries3) +{ + struct ath5k_ar5212_tx_desc *tx_desc; + + tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; + +#define _XTX_TRIES(_n) \ + if (tx_tries##_n) { \ + tx_desc->tx_control_2 |= \ + AR5K_REG_SM(tx_tries##_n, \ + AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n); \ + tx_desc->tx_control_3 |= \ + AR5K_REG_SM(tx_rate##_n, \ + AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n); \ + } + + _XTX_TRIES(1); + _XTX_TRIES(2); + _XTX_TRIES(3); + +#undef _XTX_TRIES + + return (TRUE); +} + +/* + * Proccess a tx descriptor on 5211 + */ +AR5K_STATUS +ath5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) +{ + struct ath5k_tx_status *tx_status; + struct ath5k_ar5211_tx_desc *tx_desc; + + tx_desc = (struct ath5k_ar5211_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_tx_status*)&desc->ds_hw[0]; + + /* No frame has been send or error */ + if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) + return (AR5K_EINPROGRESS); + + /* + * Get descriptor status + */ + desc->ds_us.tx.ts_tstamp = + AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + desc->ds_us.tx.ts_shortretry = + AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT); + desc->ds_us.tx.ts_longretry = + AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT); + desc->ds_us.tx.ts_seqnum = + AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + desc->ds_us.tx.ts_rssi = + AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + desc->ds_us.tx.ts_antenna = 1; + desc->ds_us.tx.ts_status = 0; + desc->ds_us.tx.ts_rate = + AR5K_REG_MS(tx_desc->tx_control_0, + AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE); + + if ((tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; + + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; + + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_FILTERED) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; + } + + return (AR5K_OK); +} + +/* + * Proccess a tx descriptor on 5212 + */ +AR5K_STATUS +ath5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) +{ + struct ath5k_tx_status *tx_status; + struct ath5k_ar5212_tx_desc *tx_desc; + + AR5K_TRACE; + tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_tx_status*)&desc->ds_hw[2]; + + /* No frame has been send or error */ + if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) + return (AR5K_EINPROGRESS); + + /* + * Get descriptor status + */ + desc->ds_us.tx.ts_tstamp = + AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + desc->ds_us.tx.ts_shortretry = + AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT); + desc->ds_us.tx.ts_longretry = + AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT); + desc->ds_us.tx.ts_seqnum = + AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + desc->ds_us.tx.ts_rssi = + AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & + AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; + desc->ds_us.tx.ts_status = 0; + + switch (AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { + case 0: + desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & + AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; + break; + case 1: + desc->ds_us.tx.ts_rate = + AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1); + desc->ds_us.tx.ts_longretry += + AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1); + break; + case 2: + desc->ds_us.tx.ts_rate = + AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2); + desc->ds_us.tx.ts_longretry += + AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2); + break; + case 3: + desc->ds_us.tx.ts_rate = + AR5K_REG_MS(tx_desc->tx_control_3, + AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3); + desc->ds_us.tx.ts_longretry += + AR5K_REG_MS(tx_desc->tx_control_2, + AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3); + break; + } + + if ((tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; + + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; + + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_FILTERED) + desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; + } + + return (AR5K_OK); +} + +/* + * RX Descriptor + */ + +/* + * Initialize an rx descriptor + */ +AR5K_BOOL +ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int32_t size, u_int flags) +{ + struct ath5k_rx_desc *rx_desc; + + AR5K_TRACE; + rx_desc = (struct ath5k_rx_desc*)&desc->ds_ctl0; + + /* + *Clear ds_hw + * If we don't clean the descriptor, while + * scanning we get too many results, + * most of them virtual, after some secs + * of scanning system hangs. M.F. + */ + bzero(desc->ds_hw, sizeof(desc->ds_hw)); + + /*Initialize rx descriptor*/ + rx_desc->rx_control_0 = 0; + rx_desc->rx_control_1 = 0; + + /*Setup descriptor*/ + if ((rx_desc->rx_control_1 = (size & + AR5K_DESC_RX_CTL1_BUF_LEN)) != size) + return (FALSE); + + if (flags & AR5K_RXDESC_INTREQ) + rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; + + return (TRUE); +} + +/* + * Proccess an rx descriptor on 5211 + */ +AR5K_STATUS +ath5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int32_t phys_addr, struct ath_desc *next) +{ + struct ath5k_ar5211_rx_status *rx_status; + + rx_status = (struct ath5k_ar5211_rx_status*)&desc->ds_hw[0]; + + /* No frame received / not ready */ + if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) + return (AR5K_EINPROGRESS); + + /* + * Frame receive status + */ + desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & + AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN; + desc->ds_us.rx.rs_rssi = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL); + desc->ds_us.rx.rs_rate = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE); + desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & + AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA; + desc->ds_us.rx.rs_more = rx_status->rx_status_0 & + AR5K_AR5211_DESC_RX_STATUS0_MORE; + desc->ds_us.rx.rs_tstamp = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); + desc->ds_us.rx.rs_status = 0; + + /* + * Key table status + */ + if (rx_status->rx_status_1 & + AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) { + desc->ds_us.rx.rs_keyix = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); + } else { + desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; + } + + /* + * Receive/descriptor errors + */ + if ((rx_status->rx_status_1 & + AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { + if (rx_status->rx_status_1 & + AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; + + if (rx_status->rx_status_1 & + AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { + desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; + desc->ds_us.rx.rs_phyerr = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); + } + + if (rx_status->rx_status_1 & + AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; + } + + return (AR5K_OK); +} + +/* + * Proccess an rx descriptor on 5212 + */ +AR5K_STATUS +ath5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int32_t phys_addr, struct ath_desc *next) +{ + struct ath5k_ar5212_rx_status *rx_status; + struct ath5k_ar5212_rx_error *rx_err; + + AR5K_TRACE; + rx_status = (struct ath5k_ar5212_rx_status*)&desc->ds_hw[0]; + + /* Overlay on error */ + rx_err = (struct ath5k_ar5212_rx_error*)&desc->ds_hw[0]; + + /* No frame received / not ready */ + if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0) + return (AR5K_EINPROGRESS); + + /* + * Frame receive status + */ + desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & + AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN; + desc->ds_us.rx.rs_rssi = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL); + desc->ds_us.rx.rs_rate = + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE); + desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & + AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA; + desc->ds_us.rx.rs_more = rx_status->rx_status_0 & + AR5K_AR5212_DESC_RX_STATUS0_MORE; + desc->ds_us.rx.rs_tstamp = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); + desc->ds_us.rx.rs_status = 0; + + /* + * Key table status + */ + if (rx_status->rx_status_1 & + AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID) { + desc->ds_us.rx.rs_keyix = + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX); + } else { + desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; + } + + /* + * Receive/descriptor errors + */ + if ((rx_status->rx_status_1 & + AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { + if (rx_status->rx_status_1 & + AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; + + if (rx_status->rx_status_1 & + AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) { + desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; + desc->ds_us.rx.rs_phyerr = + AR5K_REG_MS(rx_err->rx_error_1, + AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE); + } + + if (rx_status->rx_status_1 & + AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; + + if (rx_status->rx_status_1 & + AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR) + desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; + } + + return (AR5K_OK); +} + + + + +/****************\ + GPIO Functions +\****************/ + +/* + * Set led state + */ +void +ath5k_hw_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) +{ + u_int32_t led; + + AR5K_TRACE; + AR5K_REG_DISABLE_BITS(AR5K_PCICFG, + AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); + + /* + * Some blinking values, define at your wish + */ + switch (state) { + case AR5K_LED_SCAN: + case AR5K_LED_AUTH: + led = AR5K_PCICFG_LEDMODE_PROP | + AR5K_PCICFG_LED_PEND; + break; + + case AR5K_LED_INIT: + led = AR5K_PCICFG_LEDMODE_PROP | + AR5K_PCICFG_LED_NONE; + break; + + case AR5K_LED_ASSOC: + case AR5K_LED_RUN: + led = AR5K_PCICFG_LEDMODE_PROP | + AR5K_PCICFG_LED_ASSOC; + break; + + default: + led = AR5K_PCICFG_LEDMODE_PROM | + AR5K_PCICFG_LED_NONE; + break; + } + + AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led); +} + +/* + * Set GPIO outputs + */ +AR5K_BOOL +ath5k_hw_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) +{ + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return (FALSE); + + AR5K_REG_WRITE(AR5K_GPIOCR, + (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) + | AR5K_GPIOCR_OUT(gpio)); + + return (TRUE); +} + +/* + * Set GPIO inputs + */ +AR5K_BOOL +ath5k_hw_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) +{ + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return (FALSE); + + AR5K_REG_WRITE(AR5K_GPIOCR, + (AR5K_REG_READ(AR5K_GPIOCR) &~ AR5K_GPIOCR_OUT(gpio)) + | AR5K_GPIOCR_IN(gpio)); + + return (TRUE); +} + +/* + * Get GPIO state + */ +u_int32_t +ath5k_hw_get_gpio(struct ath_hal *hal, u_int32_t gpio) +{ + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return (0xffffffff); + + /* GPIO input magic */ + return (((AR5K_REG_READ(AR5K_GPIODI) & + AR5K_GPIODI_M) >> gpio) & 0x1); +} + +/* + * Set GPIO state + */ +AR5K_BOOL +ath5k_hw_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) +{ + u_int32_t data; + AR5K_TRACE; + + if (gpio > AR5K_NUM_GPIO) + return (FALSE); + + /* GPIO output magic */ + data = AR5K_REG_READ(AR5K_GPIODO); + + data &= ~(1 << gpio); + data |= (val&1) << gpio; + + AR5K_REG_WRITE(AR5K_GPIODO, data); + + return (TRUE); +} + +/* + * Initialize the GPIO interrupt (RFKill switch) + */ +void +ath5k_hw_set_gpio_intr(struct ath_hal *hal, u_int gpio, + u_int32_t interrupt_level) +{ + u_int32_t data; + + AR5K_TRACE; + if (gpio > AR5K_NUM_GPIO) + return; + + /* + * Set the GPIO interrupt + */ + data = (AR5K_REG_READ(AR5K_GPIOCR) & + ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | + AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | + (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); + + AR5K_REG_WRITE(AR5K_GPIOCR, + interrupt_level ? data : (data | AR5K_GPIOCR_INT_SELH)); + + hal->ah_imr |= AR5K_IMR_GPIO; + + /* Enable GPIO interrupts */ + AR5K_REG_ENABLE_BITS(AR5K_PIMR, AR5K_IMR_GPIO); +} + + + + +/*********************************\ + Regulatory Domain/Channels Setup +\*********************************/ + +/* + * Following 2 functions come from net80211 + * TODO: These do not belong here, they have nothing + * to do with hw. I left them here temporarily for + * combatibility. + * M.F. + */ + +/* + * Convert MHz frequency to IEEE channel number. + */ +u_int +ath_hal_mhz2ieee(u_int freq, u_int flags) +{ + if (flags & CHANNEL_2GHZ) { /* 2GHz band */ + if (freq == 2484) /* Japan */ + return 14; + if ((freq >= 2412) && (freq < 2484)) /* don't number non-IEEE channels */ + return (freq - 2407) / 5; + return 0; + } else if (flags & CHANNEL_5GHZ) { /* 5Ghz band */ + if ((freq >= 5150) && (freq <= 5825)) /* don't number non-IEEE channels */ + return (freq - 5000) / 5; + return 0; + } else { + /* something is fishy, don't do anything */ + return 0; + } +} + +/* + * Convert IEEE channel number to MHz frequency. + */ +u_int +ath_hal_ieee2mhz(u_int chan, u_int flags) +{ + if (flags & CHANNEL_2GHZ) { /* 2GHz band */ + if (chan == 14) + return 2484; + if (chan < 14) + return 2407 + chan * 5; + else + return 2512 + ((chan - 15) * 20); + } else if (flags & CHANNEL_5GHZ) /* 5Ghz band */ + return 5000 + (chan * 5); + else { /* either, guess */ + if (chan == 14) + return 2484; + if (chan < 14) /* 0-13 */ + return 2407 + chan * 5; + if (chan < 27) /* 15-26 */ + return 2512 + ((chan - 15) * 20); + return 5000 + (chan * 5); + } +} + +/* + * Check if a channel is supported + */ +AR5K_BOOL +ath5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) +{ + /* Check if the channel is in our supported range */ + if (flags & CHANNEL_2GHZ) { + if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && + (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) + return (TRUE); + } else if (flags & CHANNEL_5GHZ) { + if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && + (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) + return (TRUE); + } + + return (FALSE); +} + +/* + * Initialize channels array + * TODO: Do this in the driver, only check_channel is hw related + * also left here temporarily for combatibility. + */ +AR5K_BOOL +ath_hal_init_channels(struct ath_hal *hal, AR5K_CHANNEL *channels, + u_int max_channels, u_int *channels_size, AR5K_CTRY_CODE country, u_int16_t mode, + AR5K_BOOL outdoor, AR5K_BOOL extended) +{ + u_int i, c; + u_int32_t domain_current; + u_int domain_5ghz, domain_2ghz; + AR5K_CHANNEL *all_channels; + AR5K_CTRY_CODE country_current; + + if ((all_channels = malloc(sizeof(AR5K_CHANNEL) * max_channels, + M_TEMP, M_NOWAIT)) == NULL) + return (FALSE); + + i = c = 0; + domain_current = hal->ah_regdomain; + hal->ah_country_code = country; + country_current = hal->ah_country_code; + + /* + * In debugging mode, enable all channels supported by the chipset + */ + if (domain_current == DMN_DEFAULT || SUPERCHANNEL == 1) { + int min, max, freq; + u_int flags; + + min = ath_hal_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN, + CHANNEL_2GHZ); + max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX, + CHANNEL_2GHZ); + flags = CHANNEL_B /*| CHANNEL_TG | + (hal->ah_version == AR5K_AR5211 ? + CHANNEL_PUREG : CHANNEL_G)*/; + + debugchan: + for (i = min; i <= max && c < max_channels; i++) { + freq = ath_hal_ieee2mhz(i, flags); + if (ath5k_check_channel(hal, freq, flags) == FALSE) + continue; + all_channels[c].freq = freq; + all_channels[c++].channel_flags = flags; + } + + /* If is there to protect from infinite loop */ + if (flags & CHANNEL_2GHZ) { +/* ath_hal_mhz2ieee returns 1 for IEEE80211_CHANNELS_5GHZ_MIN +for loop starts from 1 and all channels are marked as 5GHz M.F.*/ +// min = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, +// CHANNEL_5GHZ); +/* Continue from where we stoped, skip last 2GHz channel */ + min = max + 1; + max = ath_hal_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, + CHANNEL_5GHZ); + flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR; + goto debugchan; + } + + goto done; + } + + domain_5ghz = ieee80211_regdomain2flag(domain_current, + IEEE80211_CHANNELS_5GHZ_MIN); + domain_2ghz = ieee80211_regdomain2flag(domain_current, + IEEE80211_CHANNELS_2GHZ_MIN); + + /* + * Create channel list based on chipset capabilities, regulation domain + * and mode. 5GHz... + */ + for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && + (i < AR5K_ELEMENTS(ath5k_5ghz_channels)) && + (c < max_channels); i++) { + /* Check if channel is supported by the chipset */ + if (ath5k_check_channel(hal, + ath5k_5ghz_channels[i].rc_channel, + CHANNEL_5GHZ) == FALSE) + continue; + + /* Match regulation domain */ + if ((IEEE80211_DMN(ath5k_5ghz_channels[i].rc_domain) & + IEEE80211_DMN(domain_5ghz)) == 0) + continue; + + /* Match modes */ + if (ath5k_5ghz_channels[i].rc_mode & CHANNEL_TURBO) { + all_channels[c].channel_flags = CHANNEL_T; + } else if (ath5k_5ghz_channels[i].rc_mode & + CHANNEL_OFDM) { + all_channels[c].channel_flags = CHANNEL_A; + } else + continue; + + /* Write channel and increment counter */ + all_channels[c++].freq = ath5k_5ghz_channels[i].rc_channel; + } + + /* + * ...and 2GHz. + */ + for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && + (i < AR5K_ELEMENTS(ath5k_2ghz_channels)) && + (c < max_channels); i++) { + /* Check if channel is supported by the chipset */ + if (ath5k_check_channel(hal, + ath5k_2ghz_channels[i].rc_channel, + CHANNEL_2GHZ) == FALSE) + continue; + + /* Match regulation domain */ + if ((IEEE80211_DMN(ath5k_2ghz_channels[i].rc_domain) & + IEEE80211_DMN(domain_2ghz)) == 0) + continue; + + /* Match modes */ + if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11B) && + (ath5k_2ghz_channels[i].rc_mode & CHANNEL_CCK)) + all_channels[c].channel_flags = CHANNEL_B; + + if ((hal->ah_capabilities.cap_mode & AR5K_MODE_11G) && + (ath5k_2ghz_channels[i].rc_mode & CHANNEL_OFDM)) { + all_channels[c].channel_flags |= + hal->ah_version == AR5K_AR5211 ? + CHANNEL_PUREG : CHANNEL_G; + if (ath5k_2ghz_channels[i].rc_mode & + CHANNEL_TURBO) + all_channels[c].channel_flags |= CHANNEL_TG; + } + + /* Write channel and increment counter */ + all_channels[c++].freq = ath5k_2ghz_channels[i].rc_channel; + } + + done: + bcopy(all_channels, channels, sizeof(AR5K_CHANNEL) * max_channels); + *channels_size = c; + free(all_channels, M_TEMP); + return (TRUE); +} + +/* + * Regdomain stuff, these also don't belong here etc + */ + +u_int16_t +ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) +{ + u_int32_t regdomain = (u_int32_t)ieee; + + /* + * Use the default regulation domain if the value is empty + * or not supported by the net80211 regulation code. + */ + if (ieee80211_regdomain2flag(regdomain, + IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) + return ((u_int16_t)AR5K_TUNE_REGDOMAIN); + + /* It is supported, just return the value */ + return (regdomain); +} + +ieee80211_regdomain_t +ath5k_regdomain_to_ieee(u_int16_t regdomain) +{ + ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; + + return (ieee); +} + +u_int16_t +ath5k_get_regdomain(struct ath_hal *hal) +{ + u_int16_t regdomain; + ieee80211_regdomain_t ieee_regdomain; +#ifdef COUNTRYCODE + u_int16_t code; +#endif + + ath5k_eeprom_regulation_domain(hal, FALSE, &ieee_regdomain); + hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; + +#ifdef COUNTRYCODE + /* + * Get the regulation domain by country code. This will ignore + * the settings found in the EEPROM. + */ + code = ieee80211_name2countrycode(COUNTRYCODE); + ieee_regdomain = ieee80211_countrycode2regdomain(code); +#endif + + regdomain = ath5k_regdomain_from_ieee(ieee_regdomain); + hal->ah_capabilities.cap_regdomain.reg_current = regdomain; + + return (regdomain); +} + +u_int16_t /*TODO:Get rid of this*/ +ath5k_hw_get_regdomain(struct ath_hal *hal) +{ + AR5K_TRACE; + return (ath5k_get_regdomain(hal)); +} + + + + +/*************************\ + PHY/RF access functions +\*************************/ + +/* + * Set a channel on the radio chip + */ +AR5K_BOOL +ath5k_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +{ + AR5K_BOOL ret; + + /* + * Check bounds supported by the PHY + * (don't care about regulation restrictions at this point) + */ + if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) && + (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min || + channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) { + AR5K_PRINTF("channel out of supported range (%u MHz)\n", + channel->freq); + return (FALSE); + } + + /* + * Set the channel and wait + */ + if (hal->ah_radio == AR5K_AR5110) + ret = ath5k_ar5110_channel(hal, channel); + else if (hal->ah_radio == AR5K_AR5111) + ret = ath5k_ar5111_channel(hal, channel); + else + ret = ath5k_ar5112_channel(hal, channel); + + if (ret == FALSE) + return (ret); + + hal->ah_current_channel.freq = channel->freq; + hal->ah_current_channel.channel_flags = channel->channel_flags; + hal->ah_turbo = channel->channel_flags == CHANNEL_T ? + TRUE : FALSE; + + return (TRUE); +} + +/* + * Convertion needed for RF5210 + */ +u_int32_t +ath5k_ar5110_chan2athchan(AR5K_CHANNEL *channel) +{ + u_int32_t athchan; + + /* + * Convert IEEE channel/MHz to an internal channel value used + * by the AR5210 chipset. This has not been verified with + * newer chipsets like the AR5212A who have a completely + * different RF/PHY part. + */ + athchan = (ath5k_hw_bitswap((ath_hal_mhz2ieee(channel->freq, + channel->channel_flags) - 24) / 2, 5) << 1) | + (1 << 6) | 0x1; + + return (athchan); +} + +/* + * Set channel on RF5110 + */ +AR5K_BOOL +ath5k_ar5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +{ + u_int32_t data; + + /* + * Set the channel and wait + */ + data = ath5k_ar5110_chan2athchan(channel); + AR5K_PHY_WRITE(0x27, data); + AR5K_PHY_WRITE(0x30, 0); + AR5K_DELAY(1000); + + return (TRUE); +} + +/* + * Convertion needed for 5111 + */ +AR5K_BOOL +ath5k_ar5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) +{ + int channel; + + /* Cast this value to catch negative channel numbers (>= -19) */ + channel = (int)ieee; + + /* + * Map 2GHz IEEE channel to 5GHz Atheros channel + */ + if (channel <= 13) { + athchan->a2_athchan = 115 + channel; + athchan->a2_flags = 0x46; + } else if (channel == 14) { + athchan->a2_athchan = 124; + athchan->a2_flags = 0x44; + } else if (channel >= 15 && channel <= 26) { + athchan->a2_athchan = ((channel - 14) * 4) + 132; + athchan->a2_flags = 0x46; + } else + return (FALSE); + + return (TRUE); +} + +/* + * Set channel on 5111 + */ +AR5K_BOOL +ath5k_ar5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +{ + u_int ieee_channel, ath_channel; + u_int32_t data0, data1, clock; + struct ath5k_athchan_2ghz ath_channel_2ghz; + + /* + * Set the channel on the AR5111 radio + */ + data0 = data1 = 0; + ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, + channel->channel_flags); + + if (channel->channel_flags & CHANNEL_2GHZ) { + /* Map 2GHz channel to 5GHz Atheros channel ID */ + if (ath5k_ar5111_chan2athchan(ieee_channel, + &ath_channel_2ghz) == FALSE) + return (FALSE); + + ath_channel = ath_channel_2ghz.a2_athchan; + data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) + << 5) | (1 << 4); + } + + if (ath_channel < 145 || !(ath_channel & 1)) { + clock = 1; + data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2) + | (clock << 1) | (1 << 10) | 1; + } else { + clock = 0; + data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) + | (clock << 1) | (1 << 10) | 1; + } + + AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); + AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); + + return (TRUE); +} + +/* + * Set channel on 5112 + */ +AR5K_BOOL +ath5k_ar5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +{ + u_int32_t data, data0, data1, data2; + u_int16_t c; + + data = data0 = data1 = data2 = 0; + c = channel->freq; + + /* + * Set the channel on the AR5112 or newer + */ + if (c < 4800) { + if (!((c - 2224) % 5)) { + data0 = ((2 * (c - 704)) - 3040) / 10; + data1 = 1; + } else if (!((c - 2192) % 5)) { + data0 = ((2 * (c - 672)) - 3040) / 10; + data1 = 0; + } else + return (FALSE); + + data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); + } else { + if (!(c % 20) && c >= 5120) { + data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); + data2 = ath5k_hw_bitswap(3, 2); + } else if (!(c % 10)) { + data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); + data2 = ath5k_hw_bitswap(2, 2); + } else if (!(c % 5)) { + data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); + data2 = ath5k_hw_bitswap(1, 2); + } else + return (FALSE); + } + + data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; + + AR5K_PHY_WRITE(0x27, data & 0xff); + AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); + + return (TRUE); +} + +/* + * Perform a PHY calibration + */ +AR5K_BOOL +ath5k_hw_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) +{ + u_int32_t i_pwr, q_pwr; + int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; + AR5K_TRACE; + + if (hal->ah_calibration == FALSE || + AR5K_REG_READ(AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) + goto done; + + hal->ah_calibration = FALSE; + + iq_corr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_CORR); + i_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_I); + q_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_Q); + i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; + q_coffd = q_pwr >> 6; + + if (i_coffd == 0 || q_coffd == 0) + goto done; + + i_coff = ((-iq_corr) / i_coffd) & 0x3f; + q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; + + /* Commit new IQ value */ + AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_PHY_IQ_CORR_ENABLE | + ((u_int32_t)q_coff) | + ((u_int32_t)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + + done: + /* Start noise floor calibration */ + AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF); + + /* Request RF gain */ + if (channel->channel_flags & CHANNEL_5GHZ) { + AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE, + AR5K_REG_SM(hal->ah_txpower.txp_max, + AR5K_PHY_PAPD_PROBE_TXPOWER) | + AR5K_PHY_PAPD_PROBE_TX_NEXT); + hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; + } + + return (TRUE); +} + +AR5K_BOOL +ath5k_hw_phy_disable(struct ath_hal *hal) +{ + AR5K_TRACE; + /*Just a try M.F.*/ + AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); + return TRUE; +} + +void /*TODO:Boundary check*/ +ath5k_hw_set_def_antenna(struct ath_hal *hal, u_int ant) +{ + AR5K_TRACE; + /*Just a try M.F.*/ + AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant); + return; +} + +u_int +ath5k_hw_get_def_antenna(struct ath_hal *hal) +{ + AR5K_TRACE; + /*Just a try M.F.*/ + return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); +} + +u_int +ath5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, + u_int32_t first, u_int32_t col, AR5K_BOOL set) +{ + u_int32_t mask, entry, last, data, shift, position; + int32_t left; + int i; + + data = 0; + + if (rf == NULL) { + /* should not happen */ + return (0); + } + + if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { + AR5K_PRINTF("invalid values at offset %u\n", offset); + return (0); + } + + entry = ((first - 1) / 8) + offset; + position = (first - 1) % 8; + + if (set == TRUE) + data = ath5k_hw_bitswap(reg, bits); + + for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { + last = (position + left > 8) ? 8 : position + left; + mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << + (col * 8); + + if (set == TRUE) { + rf[entry] &= ~mask; + rf[entry] |= ((data << position) << (col * 8)) & mask; + data >>= (8 - position); + } else { + data = (((rf[entry] & mask) >> (col * 8)) >> + position) << shift; + shift += last - position; + } + + left -= 8 - position; + } + + data = set == TRUE ? 1 : ath5k_hw_bitswap(data, bits); + + return (data); +} + +u_int32_t +ath5k_rfregs_gainf_corr(struct ath_hal *hal) +{ + u_int32_t mix, step; + u_int32_t *rf; + + if (hal->ah_rf_banks == NULL) + return (0); + + rf = hal->ah_rf_banks; + hal->ah_gain.g_f_corr = 0; + + if (ath5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1) + return (0); + + step = ath5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE); + mix = hal->ah_gain.g_step->gos_param[0]; + + switch (mix) { + case 3: + hal->ah_gain.g_f_corr = step * 2; + break; + case 2: + hal->ah_gain.g_f_corr = (step - 5) * 2; + break; + case 1: + hal->ah_gain.g_f_corr = step; + break; + default: + hal->ah_gain.g_f_corr = 0; + break; + } + + return (hal->ah_gain.g_f_corr); +} + +AR5K_BOOL +ath5k_rfregs_gain_readback(struct ath_hal *hal) +{ + u_int32_t step, mix, level[4]; + u_int32_t *rf; + + if (hal->ah_rf_banks == NULL) + return (0); + + rf = hal->ah_rf_banks; + + if (hal->ah_radio == AR5K_AR5111) { + step = ath5k_rfregs_op(rf, hal->ah_offset[7], + 0, 6, 37, 0, FALSE); + level[0] = 0; + level[1] = (step == 0x3f) ? 0x32 : step + 4; + level[2] = (step != 0x3f) ? 0x40 : level[0]; + level[3] = level[2] + 0x32; + + hal->ah_gain.g_high = level[3] - + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); + hal->ah_gain.g_low = level[0] + + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); + } else { + mix = ath5k_rfregs_op(rf, hal->ah_offset[7], + 0, 1, 36, 0, FALSE); + level[0] = level[2] = 0; + + if (mix == 1) { + level[1] = level[3] = 83; + } else { + level[1] = level[3] = 107; + hal->ah_gain.g_high = 55; + } + } + + return ((hal->ah_gain.g_current >= level[0] && + hal->ah_gain.g_current <= level[1]) || + (hal->ah_gain.g_current >= level[2] && + hal->ah_gain.g_current <= level[3])); +} + +int32_t +ath5k_rfregs_gain_adjust(struct ath_hal *hal) +{ + int ret = 0; + const struct ath5k_gain_opt *go; + + go = hal->ah_radio == AR5K_AR5111 ? + &ar5111_gain_opt : &ar5112_gain_opt; + + hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; + + if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { + if (hal->ah_gain.g_step_idx == 0) + return (-1); + for (hal->ah_gain.g_target = hal->ah_gain.g_current; + hal->ah_gain.g_target >= hal->ah_gain.g_high && + hal->ah_gain.g_step_idx > 0; + hal->ah_gain.g_step = + &go->go_step[hal->ah_gain.g_step_idx]) { + hal->ah_gain.g_target -= 2 * + (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - + hal->ah_gain.g_step->gos_gain); + } + + ret = 1; + goto done; + } + + if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { + if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) + return (-2); + for (hal->ah_gain.g_target = hal->ah_gain.g_current; + hal->ah_gain.g_target <= hal->ah_gain.g_low && + hal->ah_gain.g_step_idx < (go->go_steps_count - 1); + hal->ah_gain.g_step = + &go->go_step[hal->ah_gain.g_step_idx]) { + hal->ah_gain.g_target -= 2 * + (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - + hal->ah_gain.g_step->gos_gain); + } + + ret = 2; + goto done; + } + + done: +#ifdef AR5K_DEBUG + AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", + ret, + hal->ah_gain.g_step_idx, + hal->ah_gain.g_current, + hal->ah_gain.g_target); +#endif + + return (ret); +} + +/* + * Initialize RF + */ +AR5K_BOOL +ath5k_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +{ + ath5k_rfgain_t *func = NULL; + AR5K_BOOL ret; + + if (hal->ah_radio == AR5K_AR5111) { + hal->ah_rf_banks_size = sizeof(ar5111_rf); + func = ath5k_ar5111_rfregs; + } else if (hal->ah_radio == AR5K_AR5112) { + if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) + hal->ah_rf_banks_size = sizeof(ar5112a_rf); + else + hal->ah_rf_banks_size = sizeof(ar5112_rf); + func = ath5k_ar5112_rfregs; + } else + return (FALSE); + + if (hal->ah_rf_banks == NULL) { + /* XXX do extra checks? */ + if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, + M_DEVBUF, M_NOWAIT)) == NULL) { + AR5K_PRINT("out of memory\n"); + return (FALSE); + } + } + + ret = (func)(hal, channel, mode); + + if (ret == TRUE) + hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; + + return (ret); +} + +/* + * Initialize RF5111 + */ +AR5K_BOOL +ath5k_ar5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + const u_int rf_size = AR5K_ELEMENTS(ar5111_rf); + u_int32_t *rf; + int i, obdb = -1, bank = -1; + u_int32_t ee_mode; + + AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); + + rf = hal->ah_rf_banks; + + /* Copy values to modify them */ + for (i = 0; i < rf_size; i++) { + if (ar5111_rf[i].rf_bank >= + AR5K_AR5111_INI_RF_MAX_BANKS) { + AR5K_PRINT("invalid bank\n"); + return (FALSE); + } + + if (bank != ar5111_rf[i].rf_bank) { + bank = ar5111_rf[i].rf_bank; + hal->ah_offset[bank] = i; + } + + rf[i] = ar5111_rf[i].rf_value[mode]; + } + + if (channel->channel_flags & CHANNEL_2GHZ) { + if (channel->channel_flags & CHANNEL_B) + ee_mode = AR5K_EEPROM_MODE_11B; + else + ee_mode = AR5K_EEPROM_MODE_11G; + obdb = 0; + + if (!ath5k_rfregs_op(rf, hal->ah_offset[0], + ee->ee_ob[ee_mode][obdb], 3, 119, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[0], + ee->ee_ob[ee_mode][obdb], 3, 122, 0, TRUE)) + return (FALSE); + + obdb = 1; + } else { + /* For 11a, Turbo and XR */ + ee_mode = AR5K_EEPROM_MODE_11A; + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_pwd_84, 1, 51, 3, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_pwd_90, 1, 45, 3, TRUE)) + return (FALSE); + } + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + !ee->ee_xpd[ee_mode], 1, 95, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_x_gain[ee_mode], 4, 96, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[7], + ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[7], + ee->ee_xpd[ee_mode], 1, 4, 0, TRUE)) + return (FALSE); + + /* Write RF values */ + for (i = 0; i < rf_size; i++) { + AR5K_REG_WAIT(i); + AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); + } + + return (TRUE); +} + +/* + * Initialize RF5112 + */ +AR5K_BOOL +ath5k_ar5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + u_int rf_size; + u_int32_t *rf; + int i, obdb = -1, bank = -1; + u_int32_t ee_mode; + const struct ath5k_ini_rf *rf_ini; + + AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); + + rf = hal->ah_rf_banks; + + if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { + rf_ini = ar5112a_rf; + rf_size = AR5K_ELEMENTS(ar5112a_rf); + } else { + rf_ini = ar5112_rf; + rf_size = AR5K_ELEMENTS(ar5112_rf); + } + + /* Copy values to modify them */ + for (i = 0; i < rf_size; i++) { + if (rf_ini[i].rf_bank >= + AR5K_AR5112_INI_RF_MAX_BANKS) { + AR5K_PRINT("invalid bank\n"); + return (FALSE); + } + + if (bank != rf_ini[i].rf_bank) { + bank = rf_ini[i].rf_bank; + hal->ah_offset[bank] = i; + } + + rf[i] = rf_ini[i].rf_value[mode]; + } + + if (channel->channel_flags & CHANNEL_2GHZ) { + if (channel->channel_flags & CHANNEL_B) + ee_mode = AR5K_EEPROM_MODE_11B; + else + ee_mode = AR5K_EEPROM_MODE_11G; + obdb = 0; + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 287, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 290, 0, TRUE)) + return (FALSE); + } else { + /* For 11a, Turbo and XR */ + ee_mode = AR5K_EEPROM_MODE_11A; + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 279, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_ob[ee_mode][obdb], 3, 282, 0, TRUE)) + return (FALSE); + } + +#ifdef notyet + ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_x_gain[ee_mode], 2, 270, 0, TRUE); + ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_x_gain[ee_mode], 2, 257, 0, TRUE); +#endif + + if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + ee->ee_xpd[ee_mode], 1, 302, 0, TRUE)) + return (FALSE); + + if (!ath5k_rfregs_op(rf, hal->ah_offset[7], + ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE)) + return (FALSE); + + /* Write RF values */ + for (i = 0; i < rf_size; i++) + AR5K_REG_WRITE(ar5112_rf[i].rf_register, rf[i]); + + return (TRUE); +} + +/* + * Initialize 5211 RF + * TODO: is this needed ? i mean 5211 has a 5111 RF + * doesn't ar5k_rfregs work ? + */ +void +ath5k_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, + u_int ee_mode) +{ + struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; + struct ath5k_ar5211_ini_rf rf[AR5K_ELEMENTS(ar5211_rf)]; + u_int32_t ob, db, obdb, xpds, xpdp, x_gain; + u_int i; + + bcopy(ar5211_rf, rf, sizeof(rf)); + obdb = 0; + + if (freq == AR5K_INI_RFGAIN_2GHZ && + hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { + ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3); + db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3); + rf[25].rf_value[freq] = + ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); + rf[26].rf_value[freq] = + (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | + (rf[26].rf_value[freq] & ~0xf); + } + + if (freq == AR5K_INI_RFGAIN_5GHZ) { + /* For 11a and Turbo */ + obdb = channel->freq >= 5725 ? 3 : + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); + } + + ob = ee->ee_ob[ee_mode][obdb]; + db = ee->ee_db[ee_mode][obdb]; + x_gain = ee->ee_x_gain[ee_mode]; + xpds = ee->ee_xpd[ee_mode]; + xpdp = !xpds; + + rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | + (((ath5k_hw_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); + rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | + ((ath5k_hw_bitswap(x_gain, 4) >> 1) & 0x7); + rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | + ((ath5k_hw_bitswap(ob, 3) << 7) & 0x80); + rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | + ((ath5k_hw_bitswap(ob, 3) >> 1) & 0x3); + rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | + ((ath5k_hw_bitswap(db, 3) << 2) & 0x1c); + rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | + ((xpds << 3) & 0x8); + + for (i = 0; i < AR5K_ELEMENTS(rf); i++) { + AR5K_REG_WAIT(i); + AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, + rf[i].rf_value[freq]); + } + + hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; +} + +AR5K_BOOL +ath5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq) +{ + int i; + + switch (phy) { + case AR5K_INI_PHY_5111: + case AR5K_INI_PHY_5112: + break; + default: + return (FALSE); + } + + switch (freq) { + case AR5K_INI_RFGAIN_2GHZ: + case AR5K_INI_RFGAIN_5GHZ: + break; + default: + return (FALSE); + } + + for (i = 0; i < AR5K_ELEMENTS(ath5k_rfg); i++) { + AR5K_REG_WAIT(i); + AR5K_REG_WRITE((u_int32_t)ath5k_rfg[i].rfg_register, + ath5k_rfg[i].rfg_value[phy][freq]); + } + + return (TRUE); +} + +AR5K_RFGAIN +ath5k_hw_get_rf_gain(struct ath_hal *hal) +{ + u_int32_t data, type; + + AR5K_TRACE; + + if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active) + || (hal->ah_version == AR5K_AR5211)) + return (AR5K_RFGAIN_INACTIVE); + + if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) + goto done; + + data = AR5K_REG_READ(AR5K_PHY_PAPD_PROBE); + + if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { + hal->ah_gain.g_current = + data >> AR5K_PHY_PAPD_PROBE_GAINF_S; + type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); + + if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) + hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR; + + if (hal->ah_radio == AR5K_AR5112) { + ath5k_rfregs_gainf_corr(hal); + hal->ah_gain.g_current = + hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? + (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : + 0; + } + + if (ath5k_rfregs_gain_readback(hal) && + AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && + ath5k_rfregs_gain_adjust(hal)) + hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE; + } + + done: + return (hal->ah_rf_gain); +} + +/* + * TX power setup + */ + +/* + * Initialize the tx power table (not fully implemented) + */ +void +ath5k_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t max_power) +{ + u_int16_t txpower, *rates; + int i, min, max, n; + + rates = hal->ah_txpower.txp_rates; + + txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; + if (max_power > txpower) { + txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? + AR5K_TUNE_MAX_TXPOWER : max_power; + } + + for (i = 0; i < AR5K_MAX_RATES; i++) + rates[i] = txpower; + + /* XXX setup target powers by rate */ + + hal->ah_txpower.txp_min = rates[7]; + hal->ah_txpower.txp_max = rates[0]; + hal->ah_txpower.txp_ofdm = rates[0]; + + /* Calculate the power table */ + n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac); + min = AR5K_EEPROM_PCDAC_START; + max = AR5K_EEPROM_PCDAC_STOP; + for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) + hal->ah_txpower.txp_pcdac[i] = +#ifdef notyet + min + ((i * (max - min)) / n); +#else + min; +#endif +} + +/* + * Set transmition power + */ +AR5K_BOOL /*O.K. - txpower_table is unimplemented so this doesn't work*/ +ath5k_hw_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower) +{ + AR5K_BOOL tpc = hal->ah_txpower.txp_tpc; + int i; + + AR5K_TRACE; + if (txpower > AR5K_TUNE_MAX_TXPOWER) { + AR5K_PRINTF("invalid tx power: %u\n", txpower); + return (FALSE); + } + + /* Reset TX power values */ + bzero(&hal->ah_txpower, sizeof(hal->ah_txpower)); + hal->ah_txpower.txp_tpc = tpc; + + /* Initialize TX power table */ + ath5k_txpower_table(hal, channel, txpower); + + /* + * Write TX power values + */ + for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { + AR5K_REG_WRITE(AR5K_PHY_PCDAC_TXPOWER(i), + ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & + 0xffff) << 16) | (((hal->ah_txpower.txp_pcdac[i << 1] << 8) + | 0xff) & 0xffff)); + } + + AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE1, + AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16) + | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0)); + + AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE2, + AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16) + | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0)); + + AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE3, + AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16) + | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0)); + + AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE4, + AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) + | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); + + if (hal->ah_txpower.txp_tpc == TRUE) { + AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX, + AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | + AR5K_TUNE_MAX_TXPOWER); + } else { + AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX, + AR5K_PHY_TXPOWER_RATE_MAX | + AR5K_TUNE_MAX_TXPOWER); + } + + return (TRUE); +} + +AR5K_BOOL +ath5k_hw_set_txpower_limit(struct ath_hal *hal, u_int power) +{ + /*Just a try M.F.*/ + AR5K_CHANNEL *channel = &hal->ah_current_channel; + + AR5K_TRACE; + AR5K_PRINTF("changing txpower to %d\n",power); + return (ath5k_hw_txpower(hal, channel, power)); +} + + + + +/****************\ + Misc functions +\****************/ + +void /*O.K.*/ +ath5k_hw_dump_state(struct ath_hal *hal) +{ +#ifdef AR5K_DEBUG +#define AR5K_PRINT_REGISTER(_x) \ + AR5K_PRINTF("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_##_x)); + + AR5K_PRINT("MAC registers:\n"); + AR5K_PRINT_REGISTER(CR); + AR5K_PRINT_REGISTER(CFG); + AR5K_PRINT_REGISTER(IER); + AR5K_PRINT_REGISTER(TXCFG); + AR5K_PRINT_REGISTER(RXCFG); + AR5K_PRINT_REGISTER(MIBC); + AR5K_PRINT_REGISTER(TOPS); + AR5K_PRINT_REGISTER(RXNOFRM); + AR5K_PRINT_REGISTER(RPGTO); + AR5K_PRINT_REGISTER(RFCNT); + AR5K_PRINT_REGISTER(MISC); + AR5K_PRINT_REGISTER(PISR); + AR5K_PRINT_REGISTER(SISR0); + AR5K_PRINT_REGISTER(SISR1); + AR5K_PRINT_REGISTER(SISR3); + AR5K_PRINT_REGISTER(SISR4); + AR5K_PRINT_REGISTER(DCM_ADDR); + AR5K_PRINT_REGISTER(DCM_DATA); + AR5K_PRINT_REGISTER(DCCFG); + AR5K_PRINT_REGISTER(CCFG); + AR5K_PRINT_REGISTER(CCFG_CUP); + AR5K_PRINT_REGISTER(CPC0); + AR5K_PRINT_REGISTER(CPC1); + AR5K_PRINT_REGISTER(CPC2); + AR5K_PRINT_REGISTER(CPCORN); + AR5K_PRINT_REGISTER(QCU_TXE); + AR5K_PRINT_REGISTER(QCU_TXD); + AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); + AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); + AR5K_PRINT_REGISTER(DCU_FP); + AR5K_PRINT_REGISTER(DCU_TXP); + AR5K_PRINT_REGISTER(DCU_TX_FILTER); + AR5K_PRINT_REGISTER(RC); + AR5K_PRINT_REGISTER(SCR); + AR5K_PRINT_REGISTER(INTPEND); + AR5K_PRINT_REGISTER(PCICFG); + AR5K_PRINT_REGISTER(GPIOCR); + AR5K_PRINT_REGISTER(GPIODO); + AR5K_PRINT_REGISTER(SREV); + AR5K_PRINT_REGISTER(EEPROM_BASE); + AR5K_PRINT_REGISTER(EEPROM_DATA); + AR5K_PRINT_REGISTER(EEPROM_CMD); + AR5K_PRINT_REGISTER(EEPROM_CFG); + AR5K_PRINT_REGISTER(PCU_MIN); + AR5K_PRINT_REGISTER(STA_ID0); + AR5K_PRINT_REGISTER(STA_ID1); + AR5K_PRINT_REGISTER(BSS_ID0); + AR5K_PRINT_REGISTER(SLOT_TIME); + AR5K_PRINT_REGISTER(TIME_OUT); + AR5K_PRINT_REGISTER(RSSI_THR); + AR5K_PRINT_REGISTER(BEACON); + AR5K_PRINT_REGISTER(CFP_PERIOD); + AR5K_PRINT_REGISTER(TIMER0); + AR5K_PRINT_REGISTER(TIMER2); + AR5K_PRINT_REGISTER(TIMER3); + AR5K_PRINT_REGISTER(CFP_DUR); + AR5K_PRINT_REGISTER(MCAST_FILTER0); + AR5K_PRINT_REGISTER(MCAST_FILTER1); + AR5K_PRINT_REGISTER(DIAG_SW); + AR5K_PRINT_REGISTER(TSF_U32); + AR5K_PRINT_REGISTER(ADDAC_TEST); + AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); + AR5K_PRINT_REGISTER(LAST_TSTP); + AR5K_PRINT_REGISTER(NAV); + AR5K_PRINT_REGISTER(RTS_OK); + AR5K_PRINT_REGISTER(ACK_FAIL); + AR5K_PRINT_REGISTER(FCS_FAIL); + AR5K_PRINT_REGISTER(BEACON_CNT); + AR5K_PRINT_REGISTER(TSF_PARM); + AR5K_PRINT_REGISTER(RATE_DUR_0); + AR5K_PRINT_REGISTER(KEYTABLE_0); + AR5K_PRINT("\n"); + + AR5K_PRINT("PHY registers:\n"); + AR5K_PRINT_REGISTER(PHY_TURBO); + AR5K_PRINT_REGISTER(PHY_AGC); + AR5K_PRINT_REGISTER(PHY_TIMING_3); + AR5K_PRINT_REGISTER(PHY_CHIP_ID); + AR5K_PRINT_REGISTER(PHY_AGCCTL); + AR5K_PRINT_REGISTER(PHY_NF); + AR5K_PRINT_REGISTER(PHY_SCR); + AR5K_PRINT_REGISTER(PHY_SLMT); + AR5K_PRINT_REGISTER(PHY_SCAL); + AR5K_PRINT_REGISTER(PHY_RX_DELAY); + AR5K_PRINT_REGISTER(PHY_IQ); + AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); + AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1); + AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2); + AR5K_PRINT_REGISTER(PHY_FC); + AR5K_PRINT_REGISTER(PHY_RADAR); + AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); + AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); + AR5K_PRINT("\n"); +#endif +} + +AR5K_BOOL /*what about VEOL cap ?*/ +ath5k_hw_has_veol(struct ath_hal *hal) +{ + return (TRUE); +} + +void /*Unimplemented*/ +ath5k_hw_get_tx_inter_queue(struct ath_hal *hal, u_int32_t *i) +{ + AR5K_TRACE; + /* XXX */ + return; +} + +void /*Added AR5K_NODE_STATS argument*/ +ath5k_hw_set_rx_signal(struct ath_hal *hal, const AR5K_NODE_STATS *stats) +{ + AR5K_TRACE; + /* Signal state monitoring is not yet supported */ +} + +AR5K_BOOL /*Added arguments*/ +ath5k_hw_get_diag_state(struct ath_hal *hal, int request, +const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize) +{ + AR5K_TRACE; + /* + * We'll ignore this right now. This seems to be some kind of an obscure + * debugging interface for the binary-only HAL. + */ + return (FALSE); +} + +AR5K_BOOL /*TODO:Is this realy needed ? We have get_isr that will return 0xfff.. on removal*/ +ath5k_hw_detect_card_present(struct ath_hal *hal) +{ + u_int16_t magic; + AR5K_TRACE; + /* + * Checking the EEPROM's magic value could be an indication + * if the card is still present. I didn't find another suitable + * way to do this. + */ + if (ath5k_hw_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) + return (FALSE); + + return (magic == AR5K_EEPROM_MAGIC_VALUE ? TRUE : FALSE); +} + +AR5K_STATUS +ath5k_hw_get_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, + u_int32_t capability, u_int32_t *result) +{ + AR5K_TRACE; + + switch (cap_type) { + case AR5K_CAP_REG_DMN: + if (result){ + *result = ath5k_get_regdomain(hal); + goto yes; + } + case AR5K_CAP_CIPHER: + switch (capability) { + case AR5K_CIPHER_WEP: + goto yes; + default: + goto no; + } + case AR5K_CAP_NUM_TXQUEUES: + if (result) { + *result = AR5K_NUM_TX_QUEUES; + goto yes; + } + case AR5K_CAP_VEOL: + goto yes; + case AR5K_CAP_COMPRESSION: + if(hal->ah_version == AR5K_AR5212){ + goto yes; + }else{ + goto no; + } + case AR5K_CAP_BURST: + goto yes; + case AR5K_CAP_TPC: + goto yes; + case AR5K_CAP_BSSIDMASK: + if(hal->ah_version == AR5K_AR5212){ + goto yes; + }else{ + goto no; + } + case AR5K_CAP_XR: + if(hal->ah_version == AR5K_AR5212){ + goto yes; + }else{ + goto no; + } + default: + goto no; + } + + no: + return (AR5K_EINVAL); + yes: + return AR5K_OK; + +} + +AR5K_BOOL +ath5k_hw_set_capability(struct ath_hal *hal, AR5K_CAPABILITY_TYPE cap_type, + u_int32_t capability, u_int32_t setting, AR5K_STATUS *status) +{ + + AR5K_TRACE; + if (status) { + *status = AR5K_OK; + } + return (FALSE); +} + +AR5K_BOOL +ath5k_hw_query_pspoll_support(struct ath_hal *hal) +{ + AR5K_TRACE; + /* nope */ + return (FALSE); +} + +AR5K_BOOL +ath5k_hw_init_pspoll(struct ath_hal *hal) +{ + AR5K_TRACE; + /* + * Not used + */ + return (FALSE); +} + +AR5K_BOOL +ath5k_hw_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, + u_int16_t assoc_id) +{ + AR5K_TRACE; + return (FALSE); +} + +AR5K_BOOL +ath5k_hw_disable_pspoll(struct ath_hal *hal) +{ + AR5K_TRACE; + return (FALSE); +} + +const char * /*O.K. - TODO:Get rid of this*/ +ath5k_printver(enum ath5k_srev_type type, u_int32_t val) +{ + struct ath5k_srev_name names[] = AR5K_SREV_NAME; + const char *name = "xxxx"; + int i; + + for (i = 0; i < AR5K_ELEMENTS(names); i++) { + if (type == AR5K_VERSION_DEV) { + if (names[i].sr_type == type && + names[i].sr_val == val) { + name = names[i].sr_name; + break; + } + continue; + } + if (names[i].sr_type != type || + names[i].sr_val == AR5K_SREV_UNKNOWN) + continue; + if ((val & 0xff) < names[i + 1].sr_val) { + name = names[i].sr_name; + break; + } + } + + return (name); +} + +void /*O.K. - TODO: Implement this in if_ath.c (ath_intr)*/ +ath5k_radar_alert(struct ath_hal *hal) +{ + /* + * Limit ~1/s + */ + +// if (hal->ah_radar.r_last_channel.freq == +// hal->ah_current_channel.freq && +// tick < (hal->ah_radar.r_last_alert + hz)) + return; + +/* hal->ah_radar.r_last_channel.freq = + hal->ah_current_channel.freq; + hal->ah_radar.r_last_channel.channel_flags = + hal->ah_current_channel.channel_flags; + hal->ah_radar.r_last_alert = tick; + + AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", + hal->ah_radar.r_last_alert, hal->ah_current_channel.freq);*/ +} + +/* + * Fill the hal struct, left here for combatibility + */ +void /*Functions added*/ +ath5k_hw_fill(struct ath_hal *hal) +{ + if(hal->ah_version == AR5K_AR5212){ + hal->ah_magic = AR5K_EEPROM_MAGIC_5212; + }else if(hal->ah_version == AR5K_AR5211){ + hal->ah_magic = AR5K_EEPROM_MAGIC_5211; + } + + /* + * Init/Exit functions + */ + AR5K_HAL_FUNCTION(hal, hw, get_rate_table); + AR5K_HAL_FUNCTION(hal, hw, detach); + + /* + * Reset functions + */ + AR5K_HAL_FUNCTION(hal, hw, reset); + AR5K_HAL_FUNCTION(hal, hw, set_opmode); + AR5K_HAL_FUNCTION(hal, hw, calibrate); + + /* + * TX functions + */ + AR5K_HAL_FUNCTION(hal, hw, update_tx_triglevel); + AR5K_HAL_FUNCTION(hal, hw, setup_tx_queue); + AR5K_HAL_FUNCTION(hal, hw, setup_tx_queueprops); + AR5K_HAL_FUNCTION(hal, hw, release_tx_queue); + AR5K_HAL_FUNCTION(hal, hw, reset_tx_queue); + AR5K_HAL_FUNCTION(hal, hw, get_tx_buf); + AR5K_HAL_FUNCTION(hal, hw, put_tx_buf); + AR5K_HAL_FUNCTION(hal, hw, tx_start); + AR5K_HAL_FUNCTION(hal, hw, stop_tx_dma); + if(hal->ah_version == AR5K_AR5212){ + AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_desc); + AR5K_HAL_FUNCTION(hal, ar5212, setup_xtx_desc); + AR5K_HAL_FUNCTION(hal, ar5212, fill_tx_desc); + AR5K_HAL_FUNCTION(hal, ar5212, proc_tx_desc); + }else if(hal->ah_version == AR5K_AR5211){ + AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc); + AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc); + AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc); + AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc); + } + AR5K_HAL_FUNCTION(hal, hw, has_veol); + + /* + * RX functions + */ + AR5K_HAL_FUNCTION(hal, hw, get_rx_buf); + AR5K_HAL_FUNCTION(hal, hw, put_rx_buf); + AR5K_HAL_FUNCTION(hal, hw, start_rx); + AR5K_HAL_FUNCTION(hal, hw, stop_rx_dma); + AR5K_HAL_FUNCTION(hal, hw, start_rx_pcu); + AR5K_HAL_FUNCTION(hal, hw, stop_pcu_recv); + AR5K_HAL_FUNCTION(hal, hw, set_mcast_filter); + AR5K_HAL_FUNCTION(hal, hw, set_mcast_filterindex); + AR5K_HAL_FUNCTION(hal, hw, clear_mcast_filter_idx); + AR5K_HAL_FUNCTION(hal, hw, get_rx_filter); + AR5K_HAL_FUNCTION(hal, hw, set_rx_filter); + AR5K_HAL_FUNCTION(hal, hw, setup_rx_desc); + if(hal->ah_version == AR5K_AR5212){ + AR5K_HAL_FUNCTION(hal, ar5212, proc_rx_desc); + }else if(hal->ah_version == AR5K_AR5211){ + AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc); + } + AR5K_HAL_FUNCTION(hal, hw, set_rx_signal); + + /* + * Misc functions + */ + AR5K_HAL_FUNCTION(hal, hw, dump_state); + AR5K_HAL_FUNCTION(hal, hw, get_diag_state); + AR5K_HAL_FUNCTION(hal, hw, get_lladdr); + AR5K_HAL_FUNCTION(hal, hw, set_lladdr); + AR5K_HAL_FUNCTION(hal, hw, set_regdomain); + AR5K_HAL_FUNCTION(hal, hw, set_ledstate); + AR5K_HAL_FUNCTION(hal, hw, set_associd); + AR5K_HAL_FUNCTION(hal, hw, set_gpio_input); + AR5K_HAL_FUNCTION(hal, hw, set_gpio_output); + AR5K_HAL_FUNCTION(hal, hw, get_gpio); + AR5K_HAL_FUNCTION(hal, hw, set_gpio); + AR5K_HAL_FUNCTION(hal, hw, set_gpio_intr); + AR5K_HAL_FUNCTION(hal, hw, get_tsf32); + AR5K_HAL_FUNCTION(hal, hw, get_tsf64); + AR5K_HAL_FUNCTION(hal, hw, reset_tsf); + AR5K_HAL_FUNCTION(hal, hw, get_regdomain); + AR5K_HAL_FUNCTION(hal, hw, detect_card_present); + AR5K_HAL_FUNCTION(hal, hw, update_mib_counters); + AR5K_HAL_FUNCTION(hal, hw, get_rf_gain); + AR5K_HAL_FUNCTION(hal, hw, set_slot_time); + AR5K_HAL_FUNCTION(hal, hw, get_slot_time); + AR5K_HAL_FUNCTION(hal, hw, set_ack_timeout); + AR5K_HAL_FUNCTION(hal, hw, get_ack_timeout); + AR5K_HAL_FUNCTION(hal, hw, set_cts_timeout); + AR5K_HAL_FUNCTION(hal, hw, get_cts_timeout); + + /* + * Key table (WEP) functions + */ + AR5K_HAL_FUNCTION(hal, hw, is_cipher_supported); + AR5K_HAL_FUNCTION(hal, hw, get_keycache_size); + AR5K_HAL_FUNCTION(hal, hw, reset_key); + AR5K_HAL_FUNCTION(hal, hw, is_key_valid); + AR5K_HAL_FUNCTION(hal, hw, set_key); + AR5K_HAL_FUNCTION(hal, hw, set_key_lladdr); + + /* + * Power management functions + */ + AR5K_HAL_FUNCTION(hal, hw, set_power); + AR5K_HAL_FUNCTION(hal, hw, get_power_mode); + AR5K_HAL_FUNCTION(hal, hw, query_pspoll_support); + AR5K_HAL_FUNCTION(hal, hw, init_pspoll); + AR5K_HAL_FUNCTION(hal, hw, enable_pspoll); + AR5K_HAL_FUNCTION(hal, hw, disable_pspoll); + + /* + * Beacon functions + */ + AR5K_HAL_FUNCTION(hal, hw, init_beacon); + AR5K_HAL_FUNCTION(hal, hw, set_beacon_timers); + AR5K_HAL_FUNCTION(hal, hw, reset_beacon); + AR5K_HAL_FUNCTION(hal, hw, wait_for_beacon); + + /* + * Interrupt functions + */ + AR5K_HAL_FUNCTION(hal, hw, is_intr_pending); + AR5K_HAL_FUNCTION(hal, hw, get_isr); + AR5K_HAL_FUNCTION(hal, hw, get_intr); + AR5K_HAL_FUNCTION(hal, hw, set_intr); + + /* + * Chipset functions (ar5k-specific, non-HAL) + */ + AR5K_HAL_FUNCTION(hal, hw, get_capabilities); + AR5K_HAL_FUNCTION(hal, hw, radar_alert); + + /* + * EEPROM access + */ + AR5K_HAL_FUNCTION(hal, hw, eeprom_is_busy); + AR5K_HAL_FUNCTION(hal, hw, eeprom_read); + AR5K_HAL_FUNCTION(hal, hw, eeprom_write); + + /* Functions not found in OpenBSD */ + AR5K_HAL_FUNCTION(hal, hw, get_tx_queueprops); + AR5K_HAL_FUNCTION(hal, hw, get_capability); + AR5K_HAL_FUNCTION(hal, hw, num_tx_pending); + AR5K_HAL_FUNCTION(hal, hw, phy_disable); + AR5K_HAL_FUNCTION(hal, hw, set_pcu_config); + AR5K_HAL_FUNCTION(hal, hw, set_txpower_limit); + AR5K_HAL_FUNCTION(hal, hw, set_def_antenna); + AR5K_HAL_FUNCTION(hal, hw, get_def_antenna); + AR5K_HAL_FUNCTION(hal, hw, set_bssid_mask); + /*Totaly unimplemented*/ + AR5K_HAL_FUNCTION(hal, hw, set_capability); + AR5K_HAL_FUNCTION(hal, hw, proc_mib_event); + AR5K_HAL_FUNCTION(hal, hw, get_tx_inter_queue); + +} Index: README =================================================================== --- README (revision 2185) +++ README (revision 2232) @@ -1,13 +1,14 @@ -Linux OpenHAL 20061412 +Linux OpenHAL 20072703 ====================== /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\ * This is a port of the ar5k hal for atheros device drivers that is * - * source-compatible with the Madwifi driver for linux * - * (before the BSD - HEAD merge). * + * source-compatible with the Madwifi driver for linux. * * * * Code ported, modified for combatibility and some bugs were fixed by * * Nick "Mick Flemm" Kossifidis (Athens Wireless Metropolitan Network) * - * so ar5k can work propertly on Linux. * + * and Pavel Roskin so ar5k can work propertly * + * on Linux. * + * * * Currently only the 5212 code has been tested due to lack of hardware. * * * * Some code from John Bicket's port (roofnet project) was taken, you can * @@ -91,8 +92,7 @@ WARNING: Don't delete the empty files included (ah_desc.h etc) -Note: Currenty works for MadWiFi versions before HEAD - BSD merge -(that means it works with 07/11/05 snapshot). +Note: Currenty works for MadWiFi-old Use ===== Index: ath5kreg.h =================================================================== --- ath5kreg.h (revision 0) +++ ath5kreg.h (revision 2232) @@ -0,0 +1,1875 @@ +/*- + * Copyright (c) 2007 Nick Kossifidis + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +/* + * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k + * maintained by Reyk Floeter + * + * I tried to document those registers by looking at ar5k code, some + * 802.11 (802.11e mostly) papers and by reading various public available + * Atheros presentations and papers like these: + * + * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf + * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf + * + * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf + */ + + + +/*====MAC DMA REGISTERS====*/ + +/* + * AR5210-Specific TXDP registers + * 5210 has only 2 transmit queues so no DCU/QCU, just + * 2 transmit descriptor pointers... + */ +#define AR5K_NOQCU_TXDP0 0x0000 /*Queue 0 - data*/ +#define AR5K_NOQCU_TXDP1 0x0004 /*Queue 1 - beacons*/ + +/* + * Mac Control Register + */ +#define AR5K_CR 0x0008 /*Register Address*/ +#define AR5K_CR_TXE0 0x00000001 /*TX Enable for queue 0 on 5210*/ +#define AR5K_CR_TXE1 0x00000002 /*TX Enable for queue 1 on 5210*/ +#define AR5K_CR_RXE 0x00000004 /*RX Enable*/ +#define AR5K_CR_TXD0 0x00000008 /*TX Disable for queue 0 on 5210*/ +#define AR5K_CR_TXD1 0x00000010 /*TX Disable for queue 1 on 5210*/ +#define AR5K_CR_RXD 0x00000020 /*RX Disable*/ +#define AR5K_CR_SWI 0x00000040 + +/* + * RX Descriptor Pointer register + */ +#define AR5K_RXDP 0x000c + +/* + * Configuration and status register + */ +#define AR5K_CFG 0x0014 /*Register Address*/ +#define AR5K_CFG_SWTD 0x00000001 /*Bitswap TX descriptor (for big endian archs)*/ +#define AR5K_CFG_SWTB 0x00000002 /*Bitswap TX buffer (?)*/ +#define AR5K_CFG_SWRD 0x00000004 /*Bitswap RX descriptor*/ +#define AR5K_CFG_SWRB 0x00000008 /*Bitswap RX buffer (?)*/ +#define AR5K_CFG_SWRG 0x00000010 +#define AR5K_CFG_ADHOC 0x00000020 /*not found on 5210*/ +#define AR5K_CFG_PHY_OK 0x00000100 /*not found on 5210*/ +#define AR5K_CFG_EEBS 0x00000200 /*EEPROM is busy*/ +#define AR5K_CFG_CLKGD 0x00000400 +#define AR5K_CFG_TXCNT 0x00007800 /*5210 only*/ +#define AR5K_CFG_TXCNT_S 11 +#define AR5K_CFG_TXFSTAT 0x00008000 /*5210 only*/ +#define AR5K_CFG_TXFSTRT 0x00010000 /*5210 only*/ +#define AR5K_CFG_PCI_THRES 0x00060000 /*not found on 5210*/ +#define AR5K_CFG_PCI_THRES_S 17 + +/* + * Interrupt enable register + */ +#define AR5K_IER 0x0024 /*Register Address*/ +#define AR5K_IER_DISABLE 0x00000000 /*Disable card interrupts*/ +#define AR5K_IER_ENABLE 0x00000001 /*Enable card interrupts*/ + + +/* + * 0x0028 is Beacon Control Register on 5210 + * and first RTS duration register on 5211 + */ + +/* + * Beacon control register -5210 only- + */ +#define AR5K_BCR 0x0028 /*Register Address*/ +#define AR5K_BCR_AP 0x00000000 /*AP mode*/ +#define AR5K_BCR_ADHOC 0x00000001 /*Ad-Hoc mode*/ +#define AR5K_BCR_BDMAE 0x00000002 /*DMA enable*/ +#define AR5K_BCR_TQ1FV 0x00000004 /*Use Queue1 for CAB traffic*/ +#define AR5K_BCR_TQ1V 0x00000008 /*Use Queue1 for Beacon traffic*/ +#define AR5K_BCR_BCGET 0x00000010 + +/* + * First RTS duration register -5211 only- + */ +#define AR5K_RTSD0 0x0028 /*Register Address*/ +#define AR5K_RTSD0_6 0x000000ff /*6Mb RTS duration mask (?)*/ +#define AR5K_RTSD0_6_S 0 /*6Mb RTS duration shift (?)*/ +#define AR5K_RTSD0_9 0x0000ff00 /*9Mb*/ +#define AR5K_RTSD0_9_S 8 +#define AR5K_RTSD0_12 0x00ff0000 /*12Mb*/ +#define AR5K_RTSD0_12_S 16 +#define AR5K_RTSD0_18 0xff000000 /*16Mb*/ +#define AR5K_RTSD0_18_S 24 + + +/* + * 0x002c is Beacon Status Register on 5210 + * and second RTS duration register on 5211 + */ + +/* + * Beacon status register -5210 only- + * + * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR + * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning + * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). + * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i + * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what + * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. + */ +#define AR5K_BSR 0x002c /*Register Address*/ +#define AR5K_BSR_BDLYSW 0x00000001 /*SW Beacon delay (?)*/ +#define AR5K_BSR_BDLYDMA 0x00000002 /*DMA Beacon delay (?)*/ +#define AR5K_BSR_TXQ1F 0x00000004 +#define AR5K_BSR_ATIMDLY 0x00000008 /*ATIM delay (?)*/ +#define AR5K_BSR_SNPADHOC 0x00000100 /*Ad-hoc mode set (?)*/ +#define AR5K_BSR_SNPBDMAE 0x00000200 /*Beacon DMA enabled (?)*/ +#define AR5K_BSR_SNPTQ1FV 0x00000400 /*Queue1 is used for CAB traffic (?)*/ +#define AR5K_BSR_SNPTQ1V 0x00000800 /*Queue1 is used for Beacon traffic (?)*/ +#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /*BCR snapshots are valid (?)*/ +#define AR5K_BSR_SWBA_CNT 0x00ff0000 + +/* + * Second RTS duration register -5211 only- + */ +#define AR5K_RTSD1 0x002c /*Register Address*/ +#define AR5K_RTSD1_24 0x000000ff /*24Mb*/ +#define AR5K_RTSD1_24_S 0 +#define AR5K_RTSD1_36 0x0000ff00 /*36Mb*/ +#define AR5K_RTSD1_36_S 8 +#define AR5K_RTSD1_48 0x00ff0000 /*48Mb*/ +#define AR5K_RTSD1_48_S 16 +#define AR5K_RTSD1_54 0xff000000 /*54Mb*/ +#define AR5K_RTSD1_54_S 24 + + +/* + * Transmit configuration register + */ +#define AR5K_TXCFG 0x0030 /*Register Address*/ +#define AR5K_TXCFG_SDMAMR 0x00000007 /*DMA size*/ +#define AR5K_TXCFG_SDMAMR_S 0 +#define AR5K_TXCFG_B_MODE 0x00000008 /*Set b mode for 5111 (enable 2111)*/ +#define AR5K_TXCFG_TXFSTP 0x00000008 /*TX DMA Stop -5210 only-*/ +#define AR5K_TXCFG_TXFULL 0x000003f0 /*TX Triger level mask*/ +#define AR5K_TXCFG_TXFULL_S 4 +#define AR5K_TXCFG_TXFULL_0B 0x00000000 +#define AR5K_TXCFG_TXFULL_64B 0x00000010 +#define AR5K_TXCFG_TXFULL_128B 0x00000020 +#define AR5K_TXCFG_TXFULL_192B 0x00000030 +#define AR5K_TXCFG_TXFULL_256B 0x00000040 +#define AR5K_TXCFG_TXCONT_EN 0x00000080 +#define AR5K_TXCFG_DMASIZE 0x00000100 /*flag for passing DMA size -non 5210*/ +#define AR5K_TXCFG_JUMBO_TXE 0x00000400 /*enable jumbo frames transmition (?) -non 5210*/ +#define AR5K_TXCFG_RTSRND 0x00001000 /*non 5210*/ +#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /*non 5210*/ +#define AR5K_TXCFG_RDY_DIS 0x00004000 /*non 5210*/ + +/* + * Receive configuration register + */ +#define AR5K_RXCFG 0x0034 /*Register Address*/ +#define AR5K_RXCFG_SDMAMW 0x00000007 /*DMA size*/ +#define AR5K_RXCFG_SDMAMW_S 0 +#define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /*default antenna*/ +#define AR5K_RXCFG_ZLFDMA 0x00000010 /*zero-length DMA*/ +#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /*enable jumbo frames recieve (?) -non 5210*/ +#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /*wrap jumbo frames (?) -non 5210*/ + +/* + * Receive jumbo descriptor last address register + * Only found in 5211 (?) + */ +#define AR5K_RXJLA 0x0038 + +/* + * MIB control register + */ +#define AR5K_MIBC 0x0040 /*Register Address*/ +#define AR5K_MIBC_COW 0x00000001 +#define AR5K_MIBC_FMC 0x00000002 /*Freeze Mib Counters (?)*/ +#define AR5K_MIBC_CMC 0x00000004 /*Clean Mib Counters (?)*/ +#define AR5K_MIBC_MCS 0x00000008 + +/* + * Timeout prescale register + */ +#define AR5K_TOPS 0x0044 +#define AR5K_TOPS_M 0x0000ffff /*non 5210*/ + +/* + * Receive timeout register (no frame received) + */ +#define AR5K_RXNOFRM 0x0048 +#define AR5K_RXNOFRM_M 0x000003ff /*non 5210*/ + +/* + * Transmit timeout register (no frame sent) + */ +#define AR5K_TXNOFRM 0x004c +#define AR5K_TXNOFRM_M 0x000003ff /*non 5210*/ +#define AR5K_TXNOFRM_QCU 0x000ffc00 /*non 5210*/ + +/* + * Receive frame gap timeout register + */ +#define AR5K_RPGTO 0x0050 +#define AR5K_RPGTO_M 0x000003ff /*non 5210*/ + +/* + * Receive frame count limit register + */ +#define AR5K_RFCNT 0x0054 +#define AR5K_RFCNT_M 0x0000001f /*non 5210*/ +#define AR5K_RFCNT_RFCL 0x0000000f /*5210*/ + +/* + * Misc settings register + */ +#define AR5K_MISC 0x0058 /*Register Address*/ +#define AR5K_MISC_DMA_OBS_M 0x000001e0 +#define AR5K_MISC_DMA_OBS_S 5 +#define AR5K_MISC_MISC_OBS_M 0x00000e00 +#define AR5K_MISC_MISC_OBS_S 9 +#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 +#define AR5K_MISC_MAC_OBS_LSB_S 12 +#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 +#define AR5K_MISC_MAC_OBS_MSB_S 15 +#define AR5K_MISC_LED_DECAY 0x001c0000 /*5210*/ +#define AR5K_MISC_LED_BLINK 0x00e00000 /*5210*/ + +/* + * QCU/DCU clock gating register (5311) + */ +#define AR5K_QCUDCU_CLKGT 0x005c /*Register Address (?)*/ +#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /*Mask for QCU clock*/ +#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /*Mask for DCU clock*/ + +/* + * Interrupt Status Registers + * + * For 5210 there is only one status register but for + * 5211/5212 we have one primary and 4 secondary registers. + * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. + * Most of these bits are common for all chipsets. + */ +#define AR5K_ISR 0x001c /*Register Address (5210)*/ +#define AR5K_PISR 0x0080 /*Register Address (5211/5212)*/ +#define AR5K_ISR_RXOK 0x00000001 /*Frame successfuly recieved*/ +#define AR5K_ISR_RXDESC 0x00000002 /*RX descriptor request*/ +#define AR5K_ISR_RXERR 0x00000004 /*Receive error*/ +#define AR5K_ISR_RXNOFRM 0x00000008 /*No frame received (receive timeout)*/ +#define AR5K_ISR_RXEOL 0x00000010 /*Empty RX descriptor*/ +#define AR5K_ISR_RXORN 0x00000020 /*Receive FIFO overrun*/ +#define AR5K_ISR_TXOK 0x00000040 /*Frame successfuly transmited*/ +#define AR5K_ISR_TXDESC 0x00000080 /*TX descriptor request*/ +#define AR5K_ISR_TXERR 0x00000100 /*Transmit error*/ +#define AR5K_ISR_TXNOFRM 0x00000200 /*No frame transmited (transmit timeout)*/ +#define AR5K_ISR_TXEOL 0x00000400 /*Empty TX descriptor*/ +#define AR5K_ISR_TXURN 0x00000800 /*Transmit FIFO underrun*/ +#define AR5K_ISR_MIB 0x00001000 /*Update MIB counters*/ +#define AR5K_ISR_SWI 0x00002000 +#define AR5K_ISR_RXPHY 0x00004000 /*PHY error*/ +#define AR5K_ISR_RXKCM 0x00008000 +#define AR5K_ISR_SWBA 0x00010000 /*Software beacon alert*/ +#define AR5K_ISR_BRSSI 0x00020000 +#define AR5K_ISR_BMISS 0x00040000 /*Beacon missed*/ +#define AR5K_ISR_HIUERR 0x00080000 /*Host Interface Unit error -non 5210*/ +#define AR5K_ISR_BNR 0x00100000 /*Beacon not ready -non 5210*/ +#define AR5K_ISR_MCABT 0x00100000 /*5210*/ +#define AR5K_ISR_RXCHIRP 0x00200000 /*5212 only*/ +#define AR5K_ISR_SSERR 0x00200000 /*5210 only*/ +#define AR5K_ISR_DPERR 0x00400000 /*5210 only*/ +#define AR5K_ISR_TIM 0x00800000 /*non 5210*/ +#define AR5K_ISR_BCNMISC 0x00800000 /*5212 only*/ +#define AR5K_ISR_GPIO 0x01000000 /*GPIO (rf kill)*/ +#define AR5K_ISR_QCBRORN 0x02000000 /*CBR overrun (?) -non 5210*/ +#define AR5K_ISR_QCBRURN 0x04000000 /*CBR underrun (?) -non 5210*/ +#define AR5K_ISR_QTRIG 0x08000000 /*non 5210*/ + +/* + * Secondary status registers (5211/5212) (0 - 4) + * + * I guess from the names that these give the status for each + * queue, that's why only masks are defined here, haven't got + * any info about them (couldn't find them anywhere in ar5k code). + */ +#define AR5K_SISR0 0x0084 /*Register Address (5211/5212)*/ +#define AR5K_SISR0_QCU_TXOK 0x000003ff /*Mask for QCU_TXOK*/ +#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /*Mask for QCU_TXDESC*/ + +#define AR5K_SISR1 0x0088 /*Register Address (5211/5212)*/ +#define AR5K_SISR1_QCU_TXERR 0x000003ff /*Mask for QCU_TXERR*/ +#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /*Mask for QCU_TXEOL*/ + +#define AR5K_SISR2 0x008c /*Register Address (5211/5212)*/ +#define AR5K_SISR2_QCU_TXURN 0x000003ff /*Mask for QCU_TXURN*/ +#define AR5K_SISR2_MCABT 0x00100000 +#define AR5K_SISR2_SSERR 0x00200000 +#define AR5K_SISR2_DPERR 0x00400000 +#define AR5K_SISR2_TIM 0x01000000 /*5212 only*/ +#define AR5K_SISR2_CAB_END 0x02000000 /*5212 only*/ +#define AR5K_SISR2_DTIM_SYNC 0x04000000 /*5212 only*/ +#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /*5212 only*/ +#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /*5212 only*/ +#define AR5K_SISR2_DTIM 0x20000000 /*5212 only*/ + +#define AR5K_SISR3 0x0090 /*Register Address (5211/5212)*/ +#define AR5K_SISR3_QCBRORN 0x000003ff /*Mask for QCBRORN*/ +#define AR5K_SISR3_QCBRURN 0x03ff0000 /*Mask for QCBRURN*/ + +#define AR5K_SISR4 0x0094 /*Register Address (5211/5212)*/ +#define AR5K_SISR4_QTRIG 0x000003ff /*Mask for QTRIG*/ + +/* + * Shadow read-and-clear interrupt status registers (5211/5212) + */ +#define AR5K_RAC_PISR 0x00c0 /*Read and clear PISR*/ +#define AR5K_RAC_SISR0 0x00c4 /*Read and clear SISR0*/ +#define AR5K_RAC_SISR1 0x00c8 /*Read and clear SISR1*/ +#define AR5K_RAC_SISR2 0x00cc /*Read and clear SISR2*/ +#define AR5K_RAC_SISR3 0x00d0 /*Read and clear SISR3*/ +#define AR5K_RAC_SISR4 0x00d4 /*Read and clear SISR4*/ + +/* + * Interrupt Mask Registers + * + * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary + * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. + */ +#define AR5K_IMR 0x0020 /*Register Address (5210)*/ +#define AR5K_PIMR 0x00a0 /*Register Address (5211/5212)*/ +#define AR5K_IMR_RXOK 0x00000001 /*Frame successfuly recieved*/ +#define AR5K_IMR_RXDESC 0x00000002 /*RX descriptor request*/ +#define AR5K_IMR_RXERR 0x00000004 /*Receive error*/ +#define AR5K_IMR_RXNOFRM 0x00000008 /*No frame received (receive timeout)*/ +#define AR5K_IMR_RXEOL 0x00000010 /*Empty RX descriptor*/ +#define AR5K_IMR_RXORN 0x00000020 /*Receive FIFO overrun*/ +#define AR5K_IMR_TXOK 0x00000040 /*Frame successfuly transmited*/ +#define AR5K_IMR_TXDESC 0x00000080 /*TX descriptor request*/ +#define AR5K_IMR_TXERR 0x00000100 /*Transmit error*/ +#define AR5K_IMR_TXNOFRM 0x00000200 /*No frame transmited (transmit timeout)*/ +#define AR5K_IMR_TXEOL 0x00000400 /*Empty TX descriptor*/ +#define AR5K_IMR_TXURN 0x00000800 /*Transmit FIFO underrun*/ +#define AR5K_IMR_MIB 0x00001000 /*Update MIB counters*/ +#define AR5K_IMR_SWI 0x00002000 +#define AR5K_IMR_RXPHY 0x00004000 /*PHY error*/ +#define AR5K_IMR_RXKCM 0x00008000 +#define AR5K_IMR_SWBA 0x00010000 /*Software beacon alert*/ +#define AR5K_IMR_BRSSI 0x00020000 +#define AR5K_IMR_BMISS 0x00040000 /*Beacon missed*/ +#define AR5K_IMR_HIUERR 0x00080000 /*Host Interface Unit error -non 5210*/ +#define AR5K_IMR_BNR 0x00100000 /*Beacon not ready -non 5210*/ +#define AR5K_IMR_MCABT 0x00100000 /*5210*/ +#define AR5K_IMR_RXCHIRP 0x00200000 /*5212 only*/ +#define AR5K_IMR_SSERR 0x00200000 /*5210 only*/ +#define AR5K_IMR_DPERR 0x00400000 /*5210 only*/ +#define AR5K_IMR_TIM 0x00800000 /*non 5210*/ +#define AR5K_IMR_BCNMISC 0x00800000 /*5212 only*/ +#define AR5K_IMR_GPIO 0x01000000 /*GPIO (rf kill)*/ +#define AR5K_IMR_QCBRORN 0x02000000 /*CBR overrun (?) -non 5210*/ +#define AR5K_IMR_QCBRURN 0x04000000 /*CBR underrun (?) -non 5210*/ +#define AR5K_IMR_QTRIG 0x08000000 /*non 5210*/ + +/* + * Secondary interrupt mask registers (5211/5212) (0 - 4) + */ +#define AR5K_SIMR0 0x00a4 /*Register Address (5211/5212)*/ +#define AR5K_SIMR0_QCU_TXOK 0x000003ff /*Mask for QCU_TXOK*/ +#define AR5K_SIMR0_QCU_TXOK_S 0 +#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /*Mask for QCU_TXDESC*/ +#define AR5K_SIMR0_QCU_TXDESC_S 16 + +#define AR5K_SIMR1 0x00a8 /*Register Address (5211/5212)*/ +#define AR5K_SIMR1_QCU_TXERR 0x000003ff /*Mask for QCU_TXERR*/ +#define AR5K_SIMR1_QCU_TXERR_S 0 +#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /*Mask for QCU_TXEOL*/ +#define AR5K_SIMR1_QCU_TXEOL_S 16 + +#define AR5K_SIMR2 0x00ac /*Register Address (5211/5212)*/ +#define AR5K_SIMR2_QCU_TXURN 0x000003ff /*Mask for QCU_TXURN*/ +#define AR5K_SIMR2_QCU_TXURN_S 0 +#define AR5K_SIMR2_MCABT 0x00100000 +#define AR5K_SIMR2_SSERR 0x00200000 +#define AR5K_SIMR2_DPERR 0x00400000 +#define AR5K_SIMR2_TIM 0x01000000 /*5212 only*/ +#define AR5K_SIMR2_CAB_END 0x02000000 /*5212 only*/ +#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /*5212 only*/ +#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /*5212 only*/ +#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /*5212 only*/ +#define AR5K_SIMR2_DTIM 0x20000000 /*5212 only*/ + +#define AR5K_SIMR3 0x00b0 /*Register Address (5211/5212)*/ +#define AR5K_SIMR3_QCBRORN 0x000003ff /*Mask for QCBRORN*/ +#define AR5K_SIMR3_QCBRORN_S 0 +#define AR5K_SIMR3_QCBRURN 0x03ff0000 /*Mask for QCBRURN*/ +#define AR5K_SIMR3_QCBRURN_S 16 + +#define AR5K_SIMR4 0x00b4 /*Register Address (5211/5212)*/ +#define AR5K_SIMR4_QTRIG 0x000003ff /*Mask for QTRIG*/ +#define AR5K_SIMR4_QTRIG_S 0 + + +/* + * Decompression mask registers (5212) + */ +#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (?)*/ +#define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/ + +/* + * Decompression configuration registers (5212) + */ +#define AR5K_DCCFG 0x0420 + +/* + * Compression configuration registers (5212) + */ +#define AR5K_CCFG 0x0600 +#define AR5K_CCFG_CUP 0x0604 + +/* + * Compression performance counter registers (5212) + */ +#define AR5K_CPC0 0x0610 /*Compression performance counter 0*/ +#define AR5K_CPC1 0x0614 /*Compression performance counter 1*/ +#define AR5K_CPC2 0x0618 /*Compression performance counter 2*/ +#define AR5K_CPC3 0x061c /*Compression performance counter 3*/ +#define AR5K_CPCORN 0x0620 /*Compression performance overrun (?)*/ + + +/* + * Queue control unit (QCU) registers (5211/5212) + * + * Card has 12 TX Queues but i see that only 0-9 are used (?) + * both in binary HAL (see ah.h) and ar5k. Each queue has it's own + * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) + * configuration register (0x08c0 - 0x08ec), a ready time configuration + * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - + * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some + * global registers, QCU transmit enable/disable and "one shot arm (?)" + * set/clear, which contain status for all queues (we shift by 1 for each + * queue). To access these registers easily we define some macros here + * that are used inside HAL. For more infos check out *_tx_queue functs. + * + * TODO: Boundary checking on macros (here?) + */ + +/* + * Generic QCU Register access macros + */ +#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) +#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) +#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) + +/* + * QCU Transmit descriptor pointer registers + */ +#define AR5K_QCU_TXDP_BASE 0x0800 /*Register Address - Queue0 TXDP*/ +#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) + +/* + * QCU Transmit enable register + */ +#define AR5K_QCU_TXE 0x0840 +#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) +#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) + +/* + * QCU Transmit disable register + */ +#define AR5K_QCU_TXD 0x0880 +#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) +#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) + +/* + * QCU Constant Bit Rate configuration registers + */ +#define AR5K_QCU_CBRCFG_BASE 0x08c0 /*Register Address - Queue0 CBRCFG*/ +#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /*CBR Interval mask*/ +#define AR5K_QCU_CBRCFG_INTVAL_S 0 +#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /*CBR overrun threshold mask*/ +#define AR5K_QCU_CBRCFG_ORN_THRES_S 24 +#define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) + +/* + * QCU Ready time configuration registers + */ +#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /*Register Address - Queue0 RDYTIMECFG*/ +#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /*Ready time interval mask*/ +#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 +#define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /*Ready time duration mask*/ +#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /*Ready time enable mask*/ +#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) + +/* + * QCU one shot arm set registers + */ +#define AR5K_QCU_ONESHOTARM_SET 0x0940 /*Register Address -QCU "one shot arm set (?)"*/ +#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff + +/* + * QCU one shot arm clear registers + */ +#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /*Register Address -QCU "one shot arm clear (?)"*/ +#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff + +/* + * QCU misc registers + */ +#define AR5K_QCU_MISC_BASE 0x09c0 /*Register Address -Queue0 MISC*/ +#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /*Frame sheduling mask*/ +#define AR5K_QCU_MISC_FRSHED_ASAP 0 /*ASAP*/ +#define AR5K_QCU_MISC_FRSHED_CBR 1 /*Constant Bit Rate*/ +#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /*DMA Beacon alert (GaTed ?)*/ +#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 +#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /*Beacon sent gated (?)*/ +#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /*Oneshot enable*/ +#define AR5K_QCU_MISC_CBREXP 0x00000020 /*CBR expired (normal queue)*/ +#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /*CBR expired (beacon queue)*/ +#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /*Beacons enabled*/ +#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /*CBR threshold enabled (?)*/ +#define AR5K_QCU_MISC_TXE 0x00000200 /*TXE reset when RDYTIME enalbed (?)*/ +#define AR5K_QCU_MISC_CBR 0x00000400 /*CBR threshold reset (?)*/ +#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /*DCU reset (?)*/ +#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) + + +/* + * QCU status registers + */ +#define AR5K_QCU_STS_BASE 0x0a00 /*Register Address - Queue0 STS*/ +#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /*Frames pending counter*/ +#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /*CBR expired counter (?)*/ +#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) + +/* + * QCU ready time shutdown register + */ +#define AR5K_QCU_RDYTIMESHDN 0x0a40 +#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff + +/* + * QCU compression buffer base registers (5212 only) + */ +#define AR5K_QCU_CBB_SELECT 0x0b00 +#define AR5K_QCU_CBB_ADDR 0x0b04 + +/* + * QCU compression buffer configuration register (5212 only) + */ +#define AR5K_QCU_CBCFG 0x0b08 + + + +/* + * Distributed Coordination Function (DCF) control unit (DCU) + * registers (5211/5212) + * + * These registers control the various characteristics of each queue + * for 802.11e (WME) combatibility so they go together with + * QCU registers in pairs. For each queue we have a QCU mask register, + * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), + * a retry limit register (0x1080 - 0x10ac), a channel time register + * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and + * a sequence number register (0x1140 - 0x116c). It seems that "global" + * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). + * We use the same macros here for easier register access. + * + */ + +/* + * DCU QCU mask registers + */ +#define AR5K_DCU_QCUMASK_BASE 0x1000 /*Register Address -Queue0 DCU_QCUMASK*/ +#define AR5K_DCU_QCUMASK_M 0x000003ff +#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) + +/* + * DCU local Inter Frame Space settings register + */ +#define AR5K_DCU_LCL_IFS_BASE 0x1040 /*Register Address -Queue0 DCU_LCL_IFS*/ +#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /*Minimum Contention Window*/ +#define AR5K_DCU_LCL_IFS_CW_MIN_S 0 +#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /*Maximum Contention Window*/ +#define AR5K_DCU_LCL_IFS_CW_MAX_S 10 +#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /*Arbitrated Interframe Space*/ +#define AR5K_DCU_LCL_IFS_AIFS_S 20 +#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) + +/* + * DCU retry limit registers + */ +#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /*Register Address -Queue0 DCU_RETRY_LMT*/ +#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /*Short retry limit mask*/ +#define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 +#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /*Long retry limit mask*/ +#define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 +#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /*Station short retry limit mask (?)*/ +#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 +#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /*Station long retry limit mask (?)*/ +#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 +#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) + +/* + * DCU channel time registers + */ +#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /*Register Address -Queue0 DCU_CHAN_TIME*/ +#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /*Channel time duration*/ +#define AR5K_DCU_CHAN_TIME_DUR_S 0 +#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /*Enable channel time*/ +#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) + +/* + * DCU misc registers + * + * For some of the registers i couldn't find in the code + * (only backoff stuff is there realy) i tried to match the + * names with 802.11e parameters etc, so i guess VIRTCOL here + * means Virtual Collision and HCFPOLL means Hybrid Coordination + * factor Poll (CF- Poll). ARBLOCK_CTL_GLOBAL is used for beacon + * queue and CAB queue but i couldn't find any more infos. + */ +#define AR5K_DCU_MISC_BASE 0x1100 /*Register Address -Queue0 DCU_MISC*/ +#define AR5K_DCU_MISC_BACKOFF 0x000007ff /*Mask for backoff setting (?)*/ +#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /*Enable backoff while bursting*/ +#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /*CF - Poll (?)*/ +#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /*Persistent backoff (?)*/ +#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /*Enable frame pre-fetch (?)*/ +#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /*Mask for Virtual Collision (?)*/ +#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 +#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 +#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 +#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /*Beacon enable (?)*/ +#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 +#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 +#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 +#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 +#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 +#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 +#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /*Disable sequence number increment (?)*/ +#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /*Disable post-frame backoff (?)*/ +#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /*Virtual Collision policy (?)*/ +#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 +#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /*Sequence number control (?)*/ +#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) + +/* + * DCU frame sequence number registers + */ +#define AR5K_DCU_SEQNUM_BASE 0x1140 +#define AR5K_DCU_SEQNUM_M 0x00000fff +#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) + +/* + * DCU global IFS SIFS registers + */ +#define AR5K_DCU_GBL_IFS_SIFS 0x1030 +#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff + +/* + * DCU global IFS slot interval registers + */ +#define AR5K_DCU_GBL_IFS_SLOT 0x1070 +#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff + +/* + * DCU global IFS EIFS registers + */ +#define AR5K_DCU_GBL_IFS_EIFS 0x10b0 +#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff + +/* + * DCU global IFS misc registers + */ +#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /*Register Address*/ +#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 +#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /*Turbo mode (?)*/ +#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /*SIFS Duration mask (?)*/ +#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 +#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 + +/* + * DCU frame prefetch control register + */ +#define AR5K_DCU_FP 0x1230 + +/* + * DCU transmit pause control/status register + */ +#define AR5K_DCU_TXP 0x1270 /*Register Address*/ +#define AR5K_DCU_TXP_M 0x000003ff /*Tx pause mask (?)*/ +#define AR5K_DCU_TXP_STATUS 0x00010000 /*Tx pause status (?)*/ + +/* + * DCU transmit filter register + */ +#define AR5K_DCU_TX_FILTER 0x1038 + +/* + * DCU clear transmit filter register + */ +#define AR5K_DCU_TX_FILTER_CLR 0x143c + +/* + * DCU set transmit filter register + */ +#define AR5K_DCU_TX_FILTER_SET 0x147c + +/* + * Reset control register + * + * 4 and 8 are not used in 5211/5212 and + * 2 means "baseband reset" on 5211/5212. + */ +#define AR5K_RESET_CTL 0x4000 /*Register Address*/ +#define AR5K_RESET_CTL_PCU 0x00000001 /*Protocol Control Unit reset*/ +#define AR5K_RESET_CTL_DMA 0x00000002 /*DMA (Rx/Tx) reset -5210 only*/ +#define AR5K_RESET_CTL_BASEBAND 0x00000002 /*Baseband reset (5211/5212)*/ +#define AR5K_RESET_CTL_MAC 0x00000004 /*MAC reset (PCU+Baseband ?) -5210 only*/ +#define AR5K_RESET_CTL_PHY 0x00000008 /*PHY reset -5210 only*/ +#define AR5K_RESET_CTL_PCI 0x00000010 /*PCI Core reset (interrupts etc)*/ +#define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \ + AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY) + +/* + * Sleep control register + */ +#define AR5K_SLEEP_CTL 0x4004 /*Register Address*/ +#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /*Sleep duration mask*/ +#define AR5K_SLEEP_CTL_SLDUR_S 0 +#define AR5K_SLEEP_CTL_SLE 0x00030000 /*Sleep enable mask*/ +#define AR5K_SLEEP_CTL_SLE_S 16 +#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /*Force chip awake*/ +#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /*Force chip sleep*/ +#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 +#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /*non 5210*/ + +/* + * Interrupt pending register + */ +#define AR5K_INTPEND 0x4008 +#define AR5K_INTPEND_M 0x00000001 + +/* + * Sleep force register + */ +#define AR5K_SFR 0x400c +#define AR5K_SFR_M 0x00000001 + +/* + * PCI configuration register + * + * (5210) = prop is also pressent at 5210 else it's only + * for 5211/5212. Also some props are only present at 5210. + */ +#define AR5K_PCICFG 0x4010 /*Register Address*/ +#define AR5K_PCICFG_EEAE 0x00000001 /*Eeprom access enable -5210 only*/ +#define AR5K_PCICFG_CLKRUNEN 0x00000004 /*CLKRUN enable*/ +#define AR5K_PCICFG_EESIZE 0x00000018 /*Mask for EEPROM size*/ +#define AR5K_PCICFG_EESIZE_S 3 +#define AR5K_PCICFG_EESIZE_4K 0 /*4K*/ +#define AR5K_PCICFG_EESIZE_8K 1 /*8K*/ +#define AR5K_PCICFG_EESIZE_16K 2 /*16K*/ +#define AR5K_PCICFG_EESIZE_FAIL 3 /*Failed to get size (?)*/ +#define AR5K_PCICFG_LED 0x00000060 /*Led status*/ +#define AR5K_PCICFG_LED_NONE 0x00000000 /*Default*/ +#define AR5K_PCICFG_LED_PEND 0x00000020 /*Scan / Auth pending (5210)*/ +#define AR5K_PCICFG_LED_ASSOC 0x00000040 /*Associated (5210)*/ +#define AR5K_PCICFG_BUS_SEL 0x00000380 /*Mask for "bus select" (?)*/ +#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /*Disable CBE fix (?)*/ +#define AR5K_PCICFG_SL_INTEN 0x00000800 /*Enable interrupts when asleep (?) (5210)*/ +#define AR5K_PCICFG_LED_BCTL 0x00001000 /*Led blink (?) -5210 only*/ +#define AR5K_PCICFG_SL_INPEN 0x00002800 /*Sleep even whith pending interrupts (?) (5210)*/ +#define AR5K_PCICFG_SPWR_DN 0x00010000 /*Mask for power status (5210)*/ +#define AR5K_PCICFG_LEDMODE 0x000e0000 /*Ledmode*/ +#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /*Blink on standard traffic*/ +#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /*Default mode (blink on any traffic)*/ +#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /*Some other blinking mode (?)*/ +#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /*Random blinking (?)*/ +#define AR5K_PCICFG_LEDBLINK 0x00700000 +#define AR5K_PCICFG_LEDBLINK_S 20 +#define AR5K_PCICFG_LEDSLOW 0x00800000 /*Slow led blink rate (?)*/ +#define AR5K_PCICFG_LEDSTATE \ + (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ + AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) + +/* + * "General Purpose Input/Output" (GPIO) control register + * + * I'm not sure about this but after looking at the code + * for all chipsets here is what i got. + * + * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) + * Mode 0 -> always input + * Mode 1 -> output when GPIODO for this GPIO is set to 0 + * Mode 2 -> output when GPIODO for this GPIO is set to 1 + * Mode 3 -> always output + * + * For more infos check out get_gpio/set_gpio and + * set_gpio_input/set_gpio_output functs. + * For more infos on gpio interrupt check out set_gpio_intr. + */ +#define AR5K_NUM_GPIO 6 + +#define AR5K_GPIOCR 0x4014 /*Register Address*/ +#define AR5K_GPIOCR_INT_ENA 0x00008000 /*Enable GPIO interrupt*/ +#define AR5K_GPIOCR_INT_SELL 0x00000000 /*Generate interrupt when pin is off (?)*/ +#define AR5K_GPIOCR_INT_SELH 0x00010000 /*Generate interrupt when pin is on*/ +#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /*Mode 0 for pin n*/ +#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /*Mode 1 for pin n*/ +#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /*Mode 2 for pin n*/ +#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /*Mode 3 for pin n*/ +#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /*Interrupt for GPIO pin n*/ + +/* + * "General Purpose Input/Output" (GPIO) data output register + */ +#define AR5K_GPIODO 0x4018 + +/* + * "General Purpose Input/Output" (GPIO) data input register + */ +#define AR5K_GPIODI 0x401c +#define AR5K_GPIODI_M 0x0000002f + + +/* + * Silicon revision register + */ +#define AR5K_SREV 0x4020 /*Register Address*/ +#define AR5K_SREV_REV 0x0000000f /*Mask for revision*/ +#define AR5K_SREV_REV_S 0 +#define AR5K_SREV_VER 0x000000ff /*Mask for version*/ +#define AR5K_SREV_VER_S 4 + + + +/*====EEPROM REGISTERS====*/ + +/* + * EEPROM access registers + * + * Here we got a difference between 5210/5211-12 + * read data register for 5210 is at 0x6800 and + * status register is at 0x6c00. There is also + * no eeprom command register on 5210 and the + * offsets are different. + * + * To read eeprom data for a specific offset: + * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) + * read AR5K_EEPROM_BASE +(4 * offset) + * check the eeprom status register + * and read eeprom data register. + * + * 5211 - write offset to AR5K_EEPROM_BASE + * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD + * check the eeprom status register + * and read eeprom data register. + * + * To write eeprom data for a specific offset: + * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) + * write data to AR5K_EEPROM_BASE +(4 * offset) + * check the eeprom status register + * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD + * 5212 write offset to AR5K_EEPROM_BASE + * write data to data register + * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD + * check the eeprom status register + * + * For more infos check eeprom_* functs and the ar5k.c + * file posted in madwifi-devel mailing list. + * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 + * + */ +#define AR5K_EEPROM_BASE 0x6000 + +/* + * Common ar5xxx EEPROM data offset (set these on AR5K_EEPROM_BASE) + */ +#define AR5K_EEPROM_MAGIC 0x003d +#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 +#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ +#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ +#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ + +#define AR5K_EEPROM_PROTECT 0x003f +#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 +#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 +#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 +#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 +#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 +#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 +#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 +#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 +#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 +#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 +#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 +#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 +#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 +#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 +#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 +#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 +#define AR5K_EEPROM_REG_DOMAIN 0x00bf +#define AR5K_EEPROM_INFO_BASE 0x00c0 +#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) +#define AR5K_EEPROM_INFO_CKSUM 0xffff +#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) + +#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) +#define AR5K_EEPROM_VERSION_3_0 0x3000 +#define AR5K_EEPROM_VERSION_3_1 0x3001 +#define AR5K_EEPROM_VERSION_3_2 0x3002 +#define AR5K_EEPROM_VERSION_3_3 0x3003 +#define AR5K_EEPROM_VERSION_3_4 0x3004 +#define AR5K_EEPROM_VERSION_4_0 0x4000 +#define AR5K_EEPROM_VERSION_4_1 0x4001 +#define AR5K_EEPROM_VERSION_4_2 0x4002 +#define AR5K_EEPROM_VERSION_4_3 0x4003 +#define AR5K_EEPROM_VERSION_4_6 0x4006 +#define AR5K_EEPROM_VERSION_4_7 0x3007 + +#define AR5K_EEPROM_MODE_11A 0 +#define AR5K_EEPROM_MODE_11B 1 +#define AR5K_EEPROM_MODE_11G 2 + +#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) +#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) +#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) +#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) +#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) +#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) +#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) +#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) +#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) + +#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c +#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 +#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 +#define AR5K_EEPROM_RFKILL_POLARITY_S 1 + +/* Newer EEPROMs are using a different offset */ +#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ + (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) + +#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) +#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) +#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) + +#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) +#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) +#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) +#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) + +/* Since 3.1 */ +#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec +#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed + +/* Misc values available since EEPROM 4.0 */ +#define AR5K_EEPROM_MISC0 0x00c4 +#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) +#define AR5K_EEPROM_MISC1 0x00c5 +#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) + +/* + * EEPROM data register + */ +#define AR5K_EEPROM_DATA_5211 0x6004 +#define AR5K_EEPROM_DATA_5210 0x6800 +#define AR5K_EEPROM_DATA (hal->ah_version == AR5K_AR5210 ? \ + AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) + +/* + * EEPROM command register + */ +#define AR5K_EEPROM_CMD 0x6008 /*Register Addres*/ +#define AR5K_EEPROM_CMD_READ 0x00000001 /*EEPROM read*/ +#define AR5K_EEPROM_CMD_WRITE 0x00000002 /*EEPROM write*/ +#define AR5K_EEPROM_CMD_RESET 0x00000004 /*EEPROM reset*/ + +/* + * EEPROM status register + */ +#define AR5K_EEPROM_STAT_5210 0x6c00 /*Register Address -5210*/ +#define AR5K_EEPROM_STAT_5211 0x600c /*Register Address -5211/5212*/ +#define AR5K_EEPROM_STATUS (hal->ah_version == AR5K_AR5210 ? \ + AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) +#define AR5K_EEPROM_STAT_RDERR 0x00000001 /*EEPROM read failed*/ +#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /*EEPROM read successful*/ +#define AR5K_EEPROM_STAT_WRERR 0x00000004 /*EEPROM write failed*/ +#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /*EEPROM write successful*/ + +/* + * EEPROM config register (?) + */ +#define AR5K_EEPROM_CFG 0x6010 + + + +/* + * Protocol Control Unit (PCU) registers + */ +/*Used for checking initial register writes during channel reset (see reset func)*/ +#define AR5K_PCU_MIN 0x8000 +#define AR5K_PCU_MAX 0x8fff + +/* + * First station id register (MAC address in lower 32 bits) + */ +#define AR5K_STA_ID0 0x8000 + +/* + * Second station id register (MAC address in upper 16 bits) + */ +#define AR5K_STA_ID1 0x8004 /*Register Address*/ +#define AR5K_STA_ID1_AP 0x00010000 /*Set AP mode*/ +#define AR5K_STA_ID1_ADHOC 0x00020000 /*Set Ad-Hoc mode*/ +#define AR5K_STA_ID1_PWR_SV 0x00040000 /*Power save reporting (?)*/ +#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /*No key search*/ +#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /*No uapsd polling -5210 only*/ +#define AR5K_STA_ID1_PCF_5211 0x00100000 /*Enable PCF on 5211/5212*/ +#define AR5K_STA_ID1_PCF_5210 0x00200000 /*Enable PCF on 5210*/ +#define AR5K_STA_ID1_PCF (hal->ah_version == AR5K_AR5210 ? \ + AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) +#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /*Use default antenna on 5211/5212*/ +#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /*Update antenna from descriptor*/ +#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /*Use default antenna for RTS (?)*/ +#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /*Use 6Mbit/s for ACK/CTS (?)*/ +#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /*Use 11b base rate (for ACK/CTS ?) -non 5210*/ + +/* + * First BSSID register (MAC address, lower 32bits) + */ +#define AR5K_BSS_ID0 0x8008 + +/* + * Second BSSID register (MAC address in upper 16 bits) + * + * AID: Association ID + */ +#define AR5K_BSS_ID1 0x800c +#define AR5K_BSS_ID1_AID 0xffff0000 +#define AR5K_BSS_ID1_AID_S 16 + +/* + * Backoff slot time register + */ +#define AR5K_SLOT_TIME 0x8010 + +/* + * ACK/CTS timeout register + */ +#define AR5K_TIME_OUT 0x8014 /*Register Address*/ +#define AR5K_TIME_OUT_ACK 0x00001fff /*ACK timeout mask*/ +#define AR5K_TIME_OUT_ACK_S 0 +#define AR5K_TIME_OUT_CTS 0x1fff0000 /*CTS timeout mask*/ +#define AR5K_TIME_OUT_CTS_S 16 + +/* + * RSSI threshold register + */ +#define AR5K_RSSI_THR 0x8018 /*Register Address*/ +#define AR5K_RSSI_THR_M 0x000000ff /*Mask for RSSI threshold -non 5210*/ +#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /*Mask for Beacon Missed threshold -5210*/ +#define AR5K_RSSI_THR_BMISS_5210_S 8 +#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /*Mask for Beacon Missed threshold -5211/5212*/ +#define AR5K_RSSI_THR_BMISS_5211_S 8 +#define AR5K_RSSI_THR_BMISS (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) +#define AR5K_RSSI_THR_BMISS_S 8 + +/* + * 5210 has more PCU registers because there is no QCU/DCU + * so queue parameters are set here, this way a lot common + * registers have different address for 5210. To make things + * easier we define a macro based on hal->ah_version for common + * registers with different addresses and common flags. + */ + +/* + * Retry limit register + * + * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) + */ +#define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address*/ +#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /*Short retry limit mask*/ +#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 +#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /*Long retry mask*/ +#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 +#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /*Station short retry limit mask*/ +#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 +#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /*Station long retry limit mask*/ +#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 +#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /*Minimum contention window mask*/ +#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 + +/* + * Transmit latency register + */ +#define AR5K_USEC_5210 0x8020 /*Register Address (5210)*/ +#define AR5K_USEC_5211 0x801c /*Register Address (5211/5212)*/ +#define AR5K_USEC (hal->ah_version == AR5K_AR5210 ? \ + AR5K_USEC_5210 : AR5K_USEC_5211) +#define AR5K_USEC_1 0x0000007f +#define AR5K_USEC_1_S 0 +#define AR5K_USEC_32 0x00003f80 +#define AR5K_USEC_32_S 7 +#define AR5K_USEC_TX_LATENCY_5211 0x007fc000 +#define AR5K_USEC_TX_LATENCY_5211_S 14 +#define AR5K_USEC_RX_LATENCY_5211 0x1f800000 +#define AR5K_USEC_RX_LATENCY_5211_S 23 +#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /*also for 5311*/ +#define AR5K_USEC_TX_LATENCY_5210_S 14 +#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /*also for 5311*/ +#define AR5K_USEC_RX_LATENCY_5210_S 20 + +/* + * PCU beacon control register + */ +#define AR5K_BEACON_5210 0x8024 +#define AR5K_BEACON_5211 0x8020 +#define AR5K_BEACON (hal->ah_version == AR5K_AR5210 ? \ + AR5K_BEACON_5210 : AR5K_BEACON_5211) +#define AR5K_BEACON_PERIOD 0x0000ffff +#define AR5K_BEACON_PERIOD_S 0 +#define AR5K_BEACON_TIM 0x007f0000 +#define AR5K_BEACON_TIM_S 16 +#define AR5K_BEACON_ENABLE 0x00800000 +#define AR5K_BEACON_RESET_TSF 0x01000000 + +/* + * CFP period register + */ +#define AR5K_CFP_PERIOD_5210 0x8028 +#define AR5K_CFP_PERIOD_5211 0x8024 +#define AR5K_CFP_PERIOD (hal->ah_version == AR5K_AR5210 ? \ + AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) + +/* + * Next beacon time register + */ +#define AR5K_TIMER0_5210 0x802c +#define AR5K_TIMER0_5211 0x8028 +#define AR5K_TIMER0 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER0_5210 : AR5K_TIMER0_5211) + +/* + * Next DMA beacon alert register + */ +#define AR5K_TIMER1_5210 0x8030 +#define AR5K_TIMER1_5211 0x802c +#define AR5K_TIMER1 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER1_5210 : AR5K_TIMER1_5211) + +/* + * Next software beacon alert register + */ +#define AR5K_TIMER2_5210 0x8034 +#define AR5K_TIMER2_5211 0x8030 +#define AR5K_TIMER2 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER2_5210 : AR5K_TIMER2_5211) + +/* + * Next ATIM window time register + */ +#define AR5K_TIMER3_5210 0x8038 +#define AR5K_TIMER3_5211 0x8034 +#define AR5K_TIMER3 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER3_5210 : AR5K_TIMER3_5211) + + +/* + * 5210 First inter frame spacing register (IFS) + */ +#define AR5K_IFS0 0x8040 +#define AR5K_IFS0_SIFS 0x000007ff +#define AR5K_IFS0_SIFS_S 0 +#define AR5K_IFS0_DIFS 0x007ff800 +#define AR5K_IFS0_DIFS_S 11 + +/* + * 5210 Second inter frame spacing register (IFS) + */ +#define AR5K_IFS1 0x8044 +#define AR5K_IFS1_PIFS 0x00000fff +#define AR5K_IFS1_PIFS_S 0 +#define AR5K_IFS1_EIFS 0x03fff000 +#define AR5K_IFS1_EIFS_S 12 +#define AR5K_IFS1_CS_EN 0x04000000 + + +/* + * CFP duration register + */ +#define AR5K_CFP_DUR_5210 0x8048 +#define AR5K_CFP_DUR_5211 0x8038 +#define AR5K_CFP_DUR (hal->ah_version == AR5K_AR5210 ? \ + AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) + +/* + * Receive filter register + * TODO: Get these out of ar5xxx.h on ath5k + */ +#define AR5K_RX_FILTER_5210 0x804c /*Register Address (521)*/ +#define AR5K_RX_FILTER_5211 0x803c /*Register Address (5211/5212)*/ +#define AR5K_RX_FILTER (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) +#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ +#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ +#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ +#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ +#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ +#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ +#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame -5212 only*/ +#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests -5212 only*/ +#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors */ +#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors*/ +#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /*5211 only*/ +#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /*5211 only*/ +#define AR5K_RX_FILTER_PHYERR (hal->ah_version == AR5K_AR5211 ? \ + AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212) +#define AR5K_RX_FILTER_RADARERR (hal->ah_version == AR5K_AR5211 ? \ + AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212) +/* + * Multicast filter register (lower 32 bits) + */ +#define AR5K_MCAST_FILTER0_5210 0x8050 +#define AR5K_MCAST_FILTER0_5211 0x8040 +#define AR5K_MCAST_FILTER0 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) + +/* + * Multicast filter register (higher 16 bits) + */ +#define AR5K_MCAST_FILTER1_5210 0x8054 +#define AR5K_MCAST_FILTER1_5211 0x8044 +#define AR5K_MCAST_FILTER1 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) + + +/* + * Transmit mask register (lower 32 bits) (5210) + */ +#define AR5K_TX_MASK0 0x8058 + +/* + * Transmit mask register (higher 16 bits) (5210) + */ +#define AR5K_TX_MASK1 0x805c + +/* + * Clear transmit mask (5210) + */ +#define AR5K_CLR_TMASK 0x8060 + +/* + * Trigger level register (before transmission) (5210) + */ +#define AR5K_TRIG_LVL 0x8064 + + +/* + * PCU control register + * + * Only DIS_RX is used in the code, the rest i guess are + * for tweaking/diagnostics. + */ +#define AR5K_DIAG_SW_5210 0x8068 /*Register Address (5210)*/ +#define AR5K_DIAG_SW_5211 0x8048 /*Register Address (5211/5212)*/ +#define AR5K_DIAG_SW (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) +#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 +#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /*Disable ACKs (?)*/ +#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /*Disable CTSs (?)*/ +#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /*Disable encryption (?)*/ +#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /*Disable decryption (?)*/ +#define AR5K_DIAG_SW_DIS_TX 0x00000020 /*Disable transmit -5210 only*/ +#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /*Disable recieve*/ +#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 +#define AR5K_DIAG_SW_DIS_RX (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) +#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /*Loopback (i guess it goes with DIS_TX) -5210 only*/ +#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 +#define AR5K_DIAG_SW_LOOP_BACK (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) +#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 +#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 +#define AR5K_DIAG_SW_CORR_FCS (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) +#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 +#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 +#define AR5K_DIAG_SW_CHAN_INFO (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) +#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /*Scrambler seed (?)*/ +#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 +#define AR5K_DIAG_SW_EN_SCRAM_SEED (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) +#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /*non 5210*/ +#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /*5210 only*/ +#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /*Scrambler seed mask (?)*/ +#define AR5K_DIAG_SW_SCRAM_SEED_S 10 +#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /*Disable seqnum increment (?)-5210 only*/ +#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 +#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 +#define AR5K_DIAG_SW_FRAME_NV0 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) +#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 +#define AR5K_DIAG_SW_OBSPT_S 18 + +/* + * TSF (clock) register (lower 32 bits) + */ +#define AR5K_TSF_L32_5210 0x806c +#define AR5K_TSF_L32_5211 0x804c +#define AR5K_TSF_L32 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) + +/* + * TSF (clock) register (higher 32 bits) + */ +#define AR5K_TSF_U32_5210 0x8070 +#define AR5K_TSF_U32_5211 0x8050 +#define AR5K_TSF_U32 (hal->ah_version == AR5K_AR5210 ? \ + AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) + +/* + * Last beacon timestamp register + */ +#define AR5K_LAST_TSTP 0x8080 + +/* + * ADDAC test register (5211/5212) + */ +#define AR5K_ADDAC_TEST 0x8054 + +/* + * Default antenna register (5211/5212) + */ +#define AR5K_DEFAULT_ANTENNA 0x8058 + + + +/* + * Retry count register (5210) + */ +#define AR5K_RETRY_CNT 0x8084 /*Register Address (5210)*/ +#define AR5K_RETRY_CNT_SSH 0x0000003f /*Station short retry count (?)*/ +#define AR5K_RETRY_CNT_SLG 0x00000fc0 /*Station long retry count (?)*/ + +/* + * Back-off status register (5210) + */ +#define AR5K_BACKOFF 0x8088 /*Register Address (5210)*/ +#define AR5K_BACKOFF_CW 0x000003ff /*Backoff Contention Window (?)*/ +#define AR5K_BACKOFF_CNT 0x03ff0000 /*Backoff count (?)*/ + + + +/* + * NAV register (current) + */ +#define AR5K_NAV_5210 0x808c +#define AR5K_NAV_5211 0x8084 +#define AR5K_NAV (hal->ah_version == AR5K_AR5210 ? \ + AR5K_NAV_5210 : AR5K_NAV_5211) + +/* + * RTS success register + */ +#define AR5K_RTS_OK_5210 0x8090 +#define AR5K_RTS_OK_5211 0x8088 +#define AR5K_RTS_OK (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) + +/* + * RTS failure register + */ +#define AR5K_RTS_FAIL_5210 0x8094 +#define AR5K_RTS_FAIL_5211 0x808c +#define AR5K_RTS_FAIL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) + +/* + * ACK failure register + */ +#define AR5K_ACK_FAIL_5210 0x8098 +#define AR5K_ACK_FAIL_5211 0x8090 +#define AR5K_ACK_FAIL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) + +/* + * FCS failure register + */ +#define AR5K_FCS_FAIL_5210 0x809c +#define AR5K_FCS_FAIL_5211 0x8094 +#define AR5K_FCS_FAIL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) + +/* + * Beacon count register + */ +#define AR5K_BEACON_CNT_5210 0x80a0 +#define AR5K_BEACON_CNT_5211 0x8098 +#define AR5K_BEACON_CNT (hal->ah_version == AR5K_AR5210 ? \ + AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) + + +/*===5212 Specific PCU registers===*/ + +/* + * XR (eXtended Range) mode register + */ +#define AR5K_XRMODE 0x80c0 +#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f +#define AR5K_XRMODE_POLL_TYPE_S 0 +#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c +#define AR5K_XRMODE_POLL_SUBTYPE_S 2 +#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 +#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 +#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 +#define AR5K_XRMODE_FRAME_HOLD_S 20 + +/* + * XR delay register + */ +#define AR5K_XRDELAY 0x80c4 +#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff +#define AR5K_XRDELAY_SLOT_DELAY_S 0 +#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 +#define AR5K_XRDELAY_CHIRP_DELAY_S 16 + +/* + * XR timeout register + */ +#define AR5K_XRTIMEOUT 0x80c8 +#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff +#define AR5K_XRTIMEOUT_CHIRP_S 0 +#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 +#define AR5K_XRTIMEOUT_POLL_S 16 + +/* + * XR chirp register + */ +#define AR5K_XRCHIRP 0x80cc +#define AR5K_XRCHIRP_SEND 0x00000001 +#define AR5K_XRCHIRP_GAP 0xffff0000 + +/* + * XR stomp register + */ +#define AR5K_XRSTOMP 0x80d0 +#define AR5K_XRSTOMP_TX 0x00000001 +#define AR5K_XRSTOMP_RX_ABORT 0x00000002 +#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 + +/* + * First enhanced sleep register + */ +#define AR5K_SLEEP0 0x80d4 +#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff +#define AR5K_SLEEP0_NEXT_DTIM_S 0 +#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 +#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 +#define AR5K_SLEEP0_CABTO 0xff000000 +#define AR5K_SLEEP0_CABTO_S 24 + +/* + * Second enhanced sleep register + */ +#define AR5K_SLEEP1 0x80d8 +#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff +#define AR5K_SLEEP1_NEXT_TIM_S 0 +#define AR5K_SLEEP1_BEACON_TO 0xff000000 +#define AR5K_SLEEP1_BEACON_TO_S 24 + +/* + * Third enhanced sleep register + */ +#define AR5K_SLEEP2 0x80dc +#define AR5K_SLEEP2_TIM_PER 0x0000ffff +#define AR5K_SLEEP2_TIM_PER_S 0 +#define AR5K_SLEEP2_DTIM_PER 0xffff0000 +#define AR5K_SLEEP2_DTIM_PER_S 16 + +/* + * BSSID mask registers + */ +#define AR5K_BSS_IDM0 0x80e0 +#define AR5K_BSS_IDM1 0x80e4 + +/* + * TX power control (TPC) register + */ +#define AR5K_TXPC 0x80e8 +#define AR5K_TXPC_ACK_M 0x0000003f +#define AR5K_TXPC_ACK_S 0 +#define AR5K_TXPC_CTS_M 0x00003f00 +#define AR5K_TXPC_CTS_S 8 +#define AR5K_TXPC_CHIRP_M 0x003f0000 +#define AR5K_TXPC_CHIRP_S 22 + +/* + * Profile count registers + */ +#define AR5K_PROFCNT_TX 0x80ec +#define AR5K_PROFCNT_RX 0x80f0 +#define AR5K_PROFCNT_RXCLR 0x80f4 +#define AR5K_PROFCNT_CYCLE 0x80f8 + +/* + * TSF parameter register + */ +#define AR5K_TSF_PARM 0x8104 +#define AR5K_TSF_PARM_INC_M 0x000000ff +#define AR5K_TSF_PARM_INC_S 0 + +/* + * PHY error filter register + */ +#define AR5K_PHY_ERR_FIL 0x810c +#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 +#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 +#define AR5K_PHY_ERR_FIL_CCK 0x02000000 + +/* + * Rate duration register + */ +#define AR5K_RATE_DUR_BASE 0x8700 +#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) + +/*===5212===*/ + +/* + * Key table (WEP) register + */ +#define AR5K_KEYTABLE_0_5210 0x9000 +#define AR5K_KEYTABLE_0_5211 0x8800 +#define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) +#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) * 32)) +#define AR5K_KEYTABLE(_n) (hal->ah_version == AR5K_AR5210 ? \ + AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) +#define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) +#define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5) +#define AR5K_KEYTABLE_TYPE_40 0x00000000 +#define AR5K_KEYTABLE_TYPE_104 0x00000001 +#define AR5K_KEYTABLE_TYPE_128 0x00000003 +#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /*5212*/ +#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /*!5210*/ +#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /*5212*/ +#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /*!5210*/ +#define AR5K_KEYTABLE_ANTENNA 0x00000008 /*5212*/ +#define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) +#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) +#define AR5K_KEYTABLE_VALID 0x00008000 + +#define AR5K_KEYTABLE_SIZE_5210 64 +#define AR5K_KEYTABLE_SIZE_5211 128 +#define AR5K_KEYTABLE_SIZE (hal->ah_version == AR5K_AR5210 ? \ + AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) +#define AR5K_KEYCACHE_SIZE 8 + + + +/*===PHY REGISTERS===*/ + +/* + * PHY register + */ +#define AR5K_PHY_BASE 0x9800 +#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) +#define AR5K_PHY_SHIFT_2GHZ 0x00004007 +#define AR5K_PHY_SHIFT_5GHZ 0x00000007 + +/* + * PHY frame control register (5210) /turbo mode register (5211/5212) + * + * There is another frame control register for 5211/5212 + * at address 0x9944 (see below) but the 2 first flags + * are common here between 5210 frame control register + * and 5211/5212 turbo mode register, so this also works as + * a "turbo mode register" for 5210. We treat this one as + * a frame control register for 5210 below. + */ +#define AR5K_PHY_TURBO 0x9804 +#define AR5K_PHY_TURBO_MODE 0x00000001 +#define AR5K_PHY_TURBO_SHORT 0x00000002 + +/* + * PHY agility command register + */ +#define AR5K_PHY_AGC 0x9808 +#define AR5K_PHY_AGC_DISABLE 0x08000000 + +/* + * PHY timing register (5212) + */ +#define AR5K_PHY_TIMING_3 0x9814 +#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 +#define AR5K_PHY_TIMING_3_DSC_MAN_S 17 +#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 +#define AR5K_PHY_TIMING_3_DSC_EXP_S 13 + +/* + * PHY chip revision register + */ +#define AR5K_PHY_CHIP_ID 0x9818 + +/* + * PHY activation register + */ +#define AR5K_PHY_ACT 0x981c +#define AR5K_PHY_ACT_ENABLE 0x00000001 +#define AR5K_PHY_ACT_DISABLE 0x00000002 + +/* + * PHY signal register (5210) + */ +#define AR5K_PHY_SIG 0x9858 +#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 +#define AR5K_PHY_SIG_FIRSTEP_S 12 +#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 +#define AR5K_PHY_SIG_FIRPWR_S 18 + +/* + * PHY coarse agility control register (5210) + */ +#define AR5K_PHY_AGCCOARSE 0x985c +#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 +#define AR5K_PHY_AGCCOARSE_LO_S 7 +#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 +#define AR5K_PHY_AGCCOARSE_HI_S 15 + +/* + * PHY agility control register + */ +#define AR5K_PHY_AGCCTL 0x9860 +#define AR5K_PHY_AGCCTL_CAL 0x00000001 +#define AR5K_PHY_AGCCTL_NF 0x00000002 + +/* + * PHY noise floor status register + */ +#define AR5K_PHY_NF 0x9864 +#define AR5K_PHY_NF_M 0x000001ff +#define AR5K_PHY_NF_ACTIVE 0x00000100 +#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) +#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) +#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) + +/* + * PHY ADC saturation register (5210) + */ +#define AR5K_PHY_ADCSAT 0x9868 +#define AR5K_PHY_ADCSAT_ICNT 0x0001f800 +#define AR5K_PHY_ADCSAT_ICNT_S 11 +#define AR5K_PHY_ADCSAT_THR 0x000007e0 +#define AR5K_PHY_ADCSAT_THR_S 5 + +/* + * PHY sleep registers (5212) + */ +#define AR5K_PHY_SCR 0x9870 +#define AR5K_PHY_SCR_32MHZ 0x0000001f +#define AR5K_PHY_SLMT 0x9874 +#define AR5K_PHY_SLMT_32MHZ 0x0000007f +#define AR5K_PHY_SCAL 0x9878 +#define AR5K_PHY_SCAL_32MHZ 0x0000000e + +/* + * PHY PLL control register (!5210) + */ +#define AR5K_PHY_PLL 0x987c +#define AR5K_PHY_PLL_20MHZ 0x13 /*5211 only*/ +#define AR5K_PHY_PLL_40MHZ_5211 0x18 +#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa +#define AR5K_PHY_PLL_40MHZ (hal->ah_version == AR5K_AR5211 ? \ + AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) +#define AR5K_PHY_PLL_44MHZ_5211 0x19 +#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab +#define AR5K_PHY_PLL_44MHZ (hal->ah_version == AR5K_AR5211 ? \ + AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) +#define AR5K_PHY_PLL_AR5111 0x00000000 +#define AR5K_PHY_PLL_AR5112 0x00000040 + +/* + * PHY RF stage register (5210) + */ +#define AR5K_PHY_RFSTG 0x98d4 +#define AR5K_PHY_RFSTG_DISABLE 0x00000021 + +/* + * PHY receiver delay register (!5210) + */ +#define AR5K_PHY_RX_DELAY 0x9914 +#define AR5K_PHY_RX_DELAY_M 0x00003fff + +/* + * PHY timing IQ control register (!5210) + */ +#define AR5K_PHY_IQ 0x9920 +#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f +#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 +#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 +#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 +#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 +#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 +#define AR5K_PHY_IQ_RUN 0x00010000 + + +/* + * PHY PAPD probe register (!5210) + */ +#define AR5K_PHY_PAPD_PROBE 0x9930 +#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 +#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 +#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 +#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /*5212 only*/ +#define AR5K_PHY_PAPD_PROBE_TYPE_S 23 +#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 +#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 +#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 +#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 +#define AR5K_PHY_PAPD_PROBE_GAINF_S 25 + + +/* + * PHY TX power registers (5212) + */ +#define AR5K_PHY_TXPOWER_RATE1 0x9934 +#define AR5K_PHY_TXPOWER_RATE2 0x9938 +#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c +#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 +#define AR5K_PHY_TXPOWER_RATE3 0xa234 +#define AR5K_PHY_TXPOWER_RATE4 0xa238 + +/* + * PHY frame control register (!5210) + */ +#define AR5K_PHY_FRAME_CTL_5210 0x9804 +#define AR5K_PHY_FRAME_CTL_5211 0x9944 +#define AR5K_PHY_FRAME_CTL (hal->ah_version == AR5K_AR5210 ? \ + AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) +/*---non 5210---*/ +#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 +#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 +/*---5210 only---*/ +#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 +#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 +#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 +#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 +#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 +#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 + +/* + * PHY radar detection enable register (!5210) + */ +#define AR5K_PHY_RADAR 0x9954 +#define AR5K_PHY_RADAR_DISABLE 0x00000000 +#define AR5K_PHY_RADAR_ENABLE 0x00000001 + +/* + * PHY antenna switch table registers (!5210) + */ +#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 +#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 + +/* + * PHY clock sleep registers (5212) + */ +#define AR5K_PHY_SCLOCK 0x99f0 +#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c +#define AR5K_PHY_SDELAY 0x99f4 +#define AR5K_PHY_SDELAY_32MHZ 0x000000ff +#define AR5K_PHY_SPENDING 0x99f8 +#define AR5K_PHY_SPENDING_AR5111 0x00000018 +#define AR5K_PHY_SPENDING_AR5112 0x00000014 + +/* + * Misc PHY/radio registers (5210/5211) + */ +#define AR5K_BB_GAIN_BASE 0x9b00 +#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) +#define AR5K_RF_GAIN_BASE 0x9a00 +#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) + +/* + * PHY timing IQ calibration result register (!5210) + */ +#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 +#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 +#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 + +/* + * PHY current RSSI register (!5210) + */ +#define AR5K_PHY_CURRENT_RSSI 0x9c1c + +/* + * PHY PCDAC TX power register (5212) + */ +#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 +#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) + +/* + * PHY mode register (!5210) + */ +#define AR5K_PHY_MODE 0x0a200 +#define AR5K_PHY_MODE_MOD 0x00000001 +#define AR5K_PHY_MODE_MOD_OFDM 0 +#define AR5K_PHY_MODE_MOD_CCK 1 +#define AR5K_PHY_MODE_FREQ 0x00000002 +#define AR5K_PHY_MODE_FREQ_5GHZ 0 +#define AR5K_PHY_MODE_FREQ_2GHZ 2 +#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /*5212 only*/ +#define AR5K_PHY_MODE_RAD 0x00000008 /*5212 only*/ +#define AR5K_PHY_MODE_RAD_AR5111 0 +#define AR5K_PHY_MODE_RAD_AR5112 8 +#define AR5K_PHY_MODE_XR 0x00000010 /*5212 only*/ + +/* + * PHY CCK transmit control register (5212) + */ +#define AR5K_PHY_CCKTXCTL 0xa204 +#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 +#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 + +/* + * PHY 2GHz gain register (5212) + */ +#define AR5K_PHY_GAIN_2GHZ 0xa20c +#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 +#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 Index: ath5k_hw.h =================================================================== --- ath5k_hw.h (revision 0) +++ ath5k_hw.h (revision 2232) @@ -0,0 +1,1937 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + +/* + * Gain settings + */ +typedef enum { + AR5K_RFGAIN_INACTIVE = 0, + AR5K_RFGAIN_READ_REQUESTED, + AR5K_RFGAIN_NEED_CHANGE, +} AR5K_RFGAIN; + +#define AR5K_GAIN_CRN_FIX_BITS_5111 4 +#define AR5K_GAIN_CRN_FIX_BITS_5112 7 +#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 +#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 +#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 +#define AR5K_GAIN_CCK_PROBE_CORR 5 +#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 +#define AR5K_GAIN_STEP_COUNT 10 +#define AR5K_GAIN_PARAM_TX_CLIP 0 +#define AR5K_GAIN_PARAM_PD_90 1 +#define AR5K_GAIN_PARAM_PD_84 2 +#define AR5K_GAIN_PARAM_GAIN_SEL 3 +#define AR5K_GAIN_PARAM_MIX_ORN 0 +#define AR5K_GAIN_PARAM_PD_138 1 +#define AR5K_GAIN_PARAM_PD_137 2 +#define AR5K_GAIN_PARAM_PD_136 3 +#define AR5K_GAIN_PARAM_PD_132 4 +#define AR5K_GAIN_PARAM_PD_131 5 +#define AR5K_GAIN_PARAM_PD_130 6 +#define AR5K_GAIN_CHECK_ADJUST(_g) \ + ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) + +struct ath5k_gain_opt_step { + int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; + int32_t gos_gain; +}; + +struct ath5k_gain_opt { + u_int32_t go_default; + u_int32_t go_steps_count; + const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; +}; + +struct ath5k_gain { + u_int32_t g_step_idx; + u_int32_t g_current; + u_int32_t g_target; + u_int32_t g_low; + u_int32_t g_high; + u_int32_t g_f_corr; + u_int32_t g_active; + const struct ath5k_gain_opt_step *g_step; +}; + +/* + * Gain optimization tables... + */ +#define AR5K_AR5111_GAIN_OPT { \ + 4, \ + 9, \ + { \ + { { 4, 1, 1, 1 }, 6 }, \ + { { 4, 0, 1, 1 }, 4 }, \ + { { 3, 1, 1, 1 }, 3 }, \ + { { 4, 0, 0, 1 }, 1 }, \ + { { 4, 1, 1, 0 }, 0 }, \ + { { 4, 0, 1, 0 }, -2 }, \ + { { 3, 1, 1, 0 }, -3 }, \ + { { 4, 0, 0, 0 }, -4 }, \ + { { 2, 1, 1, 0 }, -6 } \ + } \ +} + +#define AR5K_AR5112_GAIN_OPT { \ + 1, \ + 8, \ + { \ + { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \ + { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \ + { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \ + { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \ + { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \ + { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \ + { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \ + { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \ + } \ +} + +/* Some EEPROM defines */ +#define AR5K_EEPROM_EEP_SCALE 100 +#define AR5K_EEPROM_EEP_DELTA 10 +#define AR5K_EEPROM_N_MODES 3 +#define AR5K_EEPROM_N_5GHZ_CHAN 10 +#define AR5K_EEPROM_N_2GHZ_CHAN 3 +#define AR5K_EEPROM_MAX_CHAN 10 +#define AR5K_EEPROM_N_PCDAC 11 +#define AR5K_EEPROM_N_TEST_FREQ 8 +#define AR5K_EEPROM_N_EDGES 8 +#define AR5K_EEPROM_N_INTERCEPTS 11 +#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) +#define AR5K_EEPROM_PCDAC_M 0x3f +#define AR5K_EEPROM_PCDAC_START 1 +#define AR5K_EEPROM_PCDAC_STOP 63 +#define AR5K_EEPROM_PCDAC_STEP 1 +#define AR5K_EEPROM_NON_EDGE_M 0x40 +#define AR5K_EEPROM_CHANNEL_POWER 8 +#define AR5K_EEPROM_N_OBDB 4 +#define AR5K_EEPROM_OBDB_DIS 0xffff +#define AR5K_EEPROM_CHANNEL_DIS 0xff +#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) +#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) +#define AR5K_EEPROM_MAX_CTLS 32 +#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 +#define AR5K_EEPROM_N_XPD0_POINTS 4 +#define AR5K_EEPROM_N_XPD3_POINTS 3 +#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 +#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 +#define AR5K_EEPROM_POWER_M 0x3f +#define AR5K_EEPROM_POWER_MIN 0 +#define AR5K_EEPROM_POWER_MAX 3150 +#define AR5K_EEPROM_POWER_STEP 50 +#define AR5K_EEPROM_POWER_TABLE_SIZE 64 +#define AR5K_EEPROM_N_POWER_LOC_11B 4 +#define AR5K_EEPROM_N_POWER_LOC_11G 6 +#define AR5K_EEPROM_I_GAIN 10 +#define AR5K_EEPROM_CCK_OFDM_DELTA 15 +#define AR5K_EEPROM_N_IQ_CAL 2 + +struct ath5k_eeprom_info { + u_int16_t ee_magic; + u_int16_t ee_protect; + u_int16_t ee_regdomain; + u_int16_t ee_version; + u_int16_t ee_header; + u_int16_t ee_ant_gain; + u_int16_t ee_misc0; + u_int16_t ee_misc1; + u_int16_t ee_cck_ofdm_gain_delta; + u_int16_t ee_cck_ofdm_power_delta; + u_int16_t ee_scaled_cck_delta; + u_int16_t ee_tx_clip; + u_int16_t ee_pwd_84; + u_int16_t ee_pwd_90; + u_int16_t ee_gain_select; + + u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES]; + u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES]; + u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES]; + u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES]; + u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES]; + u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES]; + u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; + u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; + u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; + u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; + u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; + u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES]; + u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES]; + u_int16_t ee_xpd[AR5K_EEPROM_N_MODES]; + u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES]; + u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES]; + u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; + u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; + u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; + u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; + + u_int16_t ee_ctls; + u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS]; + + int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; + int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; + int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; +}; + +/* + * AR5k register access + */ + +/*Swap RX/TX Descriptor for big endian archs*/ +#if BYTE_ORDER == BIG_ENDIAN +#define AR5K_INIT_CFG ( \ + AR5K_CFG_SWTD | AR5K_CFG_SWRD \ +) +#else +#define AR5K_INIT_CFG 0x00000000 +#endif + +#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg) + +#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg) + +#define AR5K_REG_SM(_val, _flags) \ + (((_val) << _flags##_S) & (_flags)) + +#define AR5K_REG_MS(_val, _flags) \ + (((_val) & (_flags)) >> _flags##_S) + +#define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ + AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ + (((_val) << _flags##_S) & (_flags))) + +#define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \ + AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags)) + +#define AR5K_REG_ENABLE_BITS(_reg, _flags) \ + AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) + +#define AR5K_REG_DISABLE_BITS(_reg, _flags) \ + AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) + +#define AR5K_PHY_WRITE(_reg, _val) \ + AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val) + +#define AR5K_PHY_READ(_reg) \ + AR5K_REG_READ(hal->ah_phy + ((_reg) << 2)) + +#define AR5K_REG_WAIT(_i) \ + if (_i % 64) \ + AR5K_DELAY(1); + +#define AR5K_EEPROM_READ(_o, _v) { \ + if ((ret = hal->ah_eeprom_read(hal, (_o), \ + &(_v))) != 0) \ + return (ret); \ +} + +#define AR5K_EEPROM_READ_HDR(_o, _v) \ + AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ + +/* Read status of selected queue */ +#define AR5K_REG_READ_Q(_reg, _queue) \ + (AR5K_REG_READ(_reg) & (1 << _queue)) \ + +#define AR5K_REG_WRITE_Q(_reg, _queue) \ + AR5K_REG_WRITE(_reg, (1 << _queue)) + +#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ + _reg |= 1 << _queue; \ +} while (0) + +#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ + _reg &= ~(1 << _queue); \ +} while (0) + +/* + * Unaligned little endian access + */ +#define AR5K_LE_READ_2(_p) \ + (((const u_int8_t *)(_p))[0] | (((const u_int8_t *)(_p))[1] << 8)) +#define AR5K_LE_READ_4(_p) \ + (((const u_int8_t *)(_p))[0] | \ + (((const u_int8_t *)(_p))[1] << 8) | \ + (((const u_int8_t *)(_p))[2] << 16) | \ + (((const u_int8_t *)(_p))[3] << 24)) +#define AR5K_LE_WRITE_2(_p, _val) \ + ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ + (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff))) +#define AR5K_LE_WRITE_4(_p, _val) \ + ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ + (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \ + (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \ + (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff))) + +#define AR5K_LOW_ID(_a)( \ +(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ +) + +#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) + +/* + * Initial register values + */ + +/* + * Common initial register values + */ +#define AR5K_INIT_MODE CHANNEL_B + +#define AR5K_INIT_TX_LATENCY 502 +#define AR5K_INIT_USEC 39 +#define AR5K_INIT_USEC_TURBO 79 +#define AR5K_INIT_USEC_32 31 +#define AR5K_INIT_CARR_SENSE_EN 1 +#define AR5K_INIT_PROG_IFS 920 +#define AR5K_INIT_PROG_IFS_TURBO 960 +#define AR5K_INIT_EIFS 3440 +#define AR5K_INIT_EIFS_TURBO 6880 +#define AR5K_INIT_SLOT_TIME 396 +#define AR5K_INIT_SLOT_TIME_TURBO 480 +#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 +#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 +#define AR5K_INIT_SIFS 560 +#define AR5K_INIT_SIFS_TURBO 480 +#define AR5K_INIT_SH_RETRY 10 +#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY +#define AR5K_INIT_SSH_RETRY 32 +#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY +#define AR5K_INIT_TX_RETRY 10 +#define AR5K_INIT_TOPS 8 +#define AR5K_INIT_RXNOFRM 8 +#define AR5K_INIT_RPGTO 0 +#define AR5K_INIT_TXNOFRM 0 +#define AR5K_INIT_BEACON_PERIOD 65535 +#define AR5K_INIT_TIM_OFFSET 0 +#define AR5K_INIT_BEACON_EN 0 +#define AR5K_INIT_RESET_TSF 0 + +#define AR5K_INIT_TRANSMIT_LATENCY ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC) \ +) +#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC_TURBO) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ + (AR5K_INIT_PROG_IFS) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ + (AR5K_INIT_PROG_IFS_TURBO) \ +) +#define AR5K_INIT_BEACON_CONTROL ( \ + (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ + (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ +) + +/* + * Non - common initial register values + */ +struct ath5k_ini { + u_int16_t ini_register; + u_int32_t ini_value; + + enum { + AR5K_INI_WRITE = 0, + AR5K_INI_READ = 1, + } ini_mode; +}; + +#define AR5K_INI_VAL_11A 0 +#define AR5K_INI_VAL_11A_TURBO 1 +#define AR5K_INI_VAL_11B 2 +#define AR5K_INI_VAL_11G 3 +#define AR5K_INI_VAL_11G_TURBO 4 +#define AR5K_INI_VAL_XR 0 +#define AR5K_INI_VAL_MAX 5 + +#define AR5K_INI_PHY_5111 0 +#define AR5K_INI_PHY_5112 1 +#define AR5K_INI_PHY_511X 1 + +#define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS +#define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS + +struct ath5k_ini_rf { + u_int8_t rf_bank; + u_int16_t rf_register; + u_int32_t rf_value[5]; +}; + +#define AR5K_AR5111_INI_RF { \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0, 0x989c, \ + { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ + { 0, 0x989c, \ + { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ + { 0, 0x98d4, \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d4, \ + { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ + { 3, 0x98d8, \ + { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ + { 6, 0x989c, \ + { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ + { 6, 0x989c, \ + { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ + { 6, 0x989c, \ + { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ + { 6, 0x989c, \ + { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ + { 6, 0x989c, \ + { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ + { 6, 0x98d4, \ + { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ + { 7, 0x989c, \ + { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ + { 7, 0x989c, \ + { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ + { 7, 0x989c, \ + { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ + { 7, 0x989c, \ + { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ + { 7, 0x989c, \ + { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ + { 7, 0x989c, \ + { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ + { 7, 0x989c, \ + { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ + { 7, 0x98cc, \ + { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ +} + +#define AR5K_AR5112_INI_RF { \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ + { 6, 0x989c, \ + { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ + { 6, 0x989c, \ + { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ + { 6, 0x989c, \ + { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ + { 6, 0x989c, \ + { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ + { 6, 0x989c, \ + { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ + { 6, 0x989c, \ + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ + { 6, 0x989c, \ + { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ + { 6, 0x989c, \ + { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ + { 6, 0x989c, \ + { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ + { 6, 0x989c, \ + { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ + { 6, 0x989c, \ + { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ + { 6, 0x989c, \ + { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ + { 6, 0x989c, \ + { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ + { 6, 0x989c, \ + { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ + { 6, 0x989c, \ + { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ + { 6, 0x989c, \ + { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ + { 6, 0x98d0, \ + { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ + { 7, 0x989c, \ + { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ + } + +#define AR5K_AR5112A_INI_RF { \ + { 1, 0x98d4, \ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ + { 2, 0x98d0, \ + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ + { 3, 0x98dc, \ + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ + { 6, 0x989c, \ + { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ + { 6, 0x989c, \ + { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ + { 6, 0x989c, \ + { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ + { 6, 0x989c, \ + { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ + { 6, 0x989c, \ + { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ + { 6, 0x989c, \ + { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ + { 6, 0x989c, \ + { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ + { 6, 0x989c, \ + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ + { 6, 0x989c, \ + { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ + { 6, 0x989c, \ + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ + { 6, 0x989c, \ + { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ + { 6, 0x989c, \ + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ + { 6, 0x989c, \ + { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ + { 6, 0x989c, \ + { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ + { 6, 0x989c, \ + { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ + { 6, 0x989c, \ + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ + { 6, 0x989c, \ + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ + { 6, 0x989c, \ + { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ + { 6, 0x989c, \ + { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ + { 6, 0x989c, \ + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ + { 6, 0x989c, \ + { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ + { 6, 0x989c, \ + { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ + { 6, 0x989c, \ + { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ + { 6, 0x989c, \ + { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ + { 6, 0x989c, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ + { 6, 0x989c, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 6, 0x989c, \ + { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ + { 6, 0x989c, \ + { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ + { 6, 0x989c, \ + { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ + { 6, 0x989c, \ + { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ + { 6, 0x989c, \ + { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ + { 6, 0x98d8, \ + { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ + { 7, 0x989c, \ + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ + { 7, 0x989c, \ + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ + { 7, 0x989c, \ + { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ + { 7, 0x989c, \ + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ + { 7, 0x989c, \ + { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ + { 7, 0x989c, \ + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ + { 7, 0x989c, \ + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ + { 7, 0x989c, \ + { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ + { 7, 0x989c, \ + { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ + { 7, 0x989c, \ + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ + { 7, 0x989c, \ + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ + { 7, 0x989c, \ + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ + { 7, 0x98c4, \ + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ +} + +struct ath5k_ini_rfgain { + u_int16_t rfg_register; + u_int32_t rfg_value[2][2]; + +#define AR5K_INI_RFGAIN_5GHZ 0 +#define AR5K_INI_RFGAIN_2GHZ 1 +}; + +#define AR5K_INI_RFGAIN { \ + { 0x9a00, { \ + { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ + { 0x9a04, { \ + { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ + { 0x9a08, { \ + { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ + { 0x9a0c, { \ + { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ + { 0x9a10, { \ + { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ + { 0x9a14, { \ + { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ + { 0x9a18, { \ + { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ + { 0x9a1c, { \ + { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ + { 0x9a20, { \ + { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ + { 0x9a24, { \ + { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ + { 0x9a28, { \ + { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ + { 0x9a2c, { \ + { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ + { 0x9a30, { \ + { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ + { 0x9a34, { \ + { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ + { 0x9a38, { \ + { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ + { 0x9a3c, { \ + { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ + { 0x9a40, { \ + { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ + { 0x9a44, { \ + { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ + { 0x9a48, { \ + { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ + { 0x9a4c, { \ + { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ + { 0x9a50, { \ + { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ + { 0x9a54, { \ + { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ + { 0x9a58, { \ + { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ + { 0x9a5c, { \ + { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ + { 0x9a60, { \ + { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ + { 0x9a64, { \ + { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ + { 0x9a68, { \ + { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ + { 0x9a6c, { \ + { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ + { 0x9a70, { \ + { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ + { 0x9a74, { \ + { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ + { 0x9a78, { \ + { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ + { 0x9a7c, { \ + { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ + { 0x9a80, { \ + { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ + { 0x9a84, { \ + { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ + { 0x9a88, { \ + { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ + { 0x9a8c, { \ + { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ + { 0x9a90, { \ + { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ + { 0x9a94, { \ + { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ + { 0x9a98, { \ + { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ + { 0x9a9c, { \ + { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ + { 0x9aa0, { \ + { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ + { 0x9aa4, { \ + { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ + { 0x9aa8, { \ + { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ + { 0x9aac, { \ + { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ + { 0x9ab0, { \ + { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ + { 0x9ab4, { \ + { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ + { 0x9ab8, { \ + { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ + { 0x9abc, { \ + { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ + { 0x9ac0, { \ + { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ + { 0x9ac4, { \ + { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ + { 0x9ac8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ + { 0x9acc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ + { 0x9ad0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ + { 0x9ad4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ + { 0x9ad8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9adc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9ae8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9aec, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af0, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af4, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9af8, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ + { 0x9afc, { \ + { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ +} + +/* + * Internal RX/TX descriptor structures + * (rX: reserved fields possibily used by future versions of the ar5k chipset) + */ + +struct ath5k_rx_desc { + /* + * RX control word 0 + */ + u_int32_t rx_control_0; + +#define AR5K_DESC_RX_CTL0 0x00000000 + + /* + * RX control word 1 + */ + u_int32_t rx_control_1; + +#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff +#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 +} __packed; + +struct ath5k_ar5211_rx_status { + /* + * RX status word 0 + */ + u_int32_t rx_status_0; + +#define AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN 0x00000fff +#define AR5K_AR5211_DESC_RX_STATUS0_MORE 0x00001000 +#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000 +#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000 +#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19 +#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x38000000 +#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 27 + + /* + * RX status word 1 + */ + u_int32_t rx_status_1; + +#define AR5K_AR5211_DESC_RX_STATUS1_DONE 0x00000001 +#define AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_AR5211_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008 +#define AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010 +#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR 0x000000e0 +#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR_S 5 +#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX 0x00007e00 +#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_S 9 +#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 +#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15 +#define AR5K_AR5211_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000 +} __packed; + +struct ath5k_ar5212_rx_status { + /* + * RX status word 0 + */ + u_int32_t rx_status_0; + +#define AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN 0x00000fff +#define AR5K_AR5212_DESC_RX_STATUS0_MORE 0x00001000 +#define AR5K_AR5212_DESC_RX_STATUS0_DECOMP_CRC_ERROR 0x00002000 +#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE 0x000f8000 +#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x0ff00000 +#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 20 +#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA 0xf0000000 +#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 28 + + /* + * RX status word 1 + */ + u_int32_t rx_status_1; + +#define AR5K_AR5212_DESC_RX_STATUS1_DONE 0x00000001 +#define AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000008 +#define AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR 0x00000010 +#define AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR 0x00000020 +#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX 0x0000fe00 +#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_S 9 +#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 +#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 16 +#define AR5K_AR5212_DESC_RX_STATUS1_KEY_CACHE_MISS 0x80000000 +} __packed; + +struct ath5k_ar5212_rx_error { + /* + * RX error word 0 + */ + u_int32_t rx_error_0; + +#define AR5K_AR5212_DESC_RX_ERROR0 0x00000000 + + /* + * RX error word 1 + */ + u_int32_t rx_error_1; + +#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE 0x0000ff00 +#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE_S 8 +} __packed; + +#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 +#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 +#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 +#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 +#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 +#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 +#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 +#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 + +struct ath5k_ar5211_tx_desc { + /* + * TX control word 0 + */ + u_int32_t tx_control_0; + +#define AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN 0x00000fff +#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE 0x003c0000 +#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE_S 18 +#define AR5K_AR5211_DESC_TX_CTL0_RTSENA 0x00400000 +#define AR5K_AR5211_DESC_TX_CTL0_VEOL 0x00800000 +#define AR5K_AR5211_DESC_TX_CTL0_CLRDMASK 0x01000000 +#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000 +#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_AR5211_DESC_TX_CTL0_INTREQ 0x20000000 +#define AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 + + /* + * TX control word 1 + */ + u_int32_t tx_control_1; + +#define AR5K_AR5211_DESC_TX_CTL1_BUF_LEN 0x00000fff +#define AR5K_AR5211_DESC_TX_CTL1_MORE 0x00001000 +#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 +#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE 0x00700000 +#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE_S 20 +#define AR5K_AR5211_DESC_TX_CTL1_NOACK 0x00800000 +} __packed; + +struct ath5k_ar5212_tx_desc { + /* + * TX control word 0 + */ + u_int32_t tx_control_0; + +#define AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN 0x00000fff +#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER 0x003f0000 +#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER_S 16 +#define AR5K_AR5212_DESC_TX_CTL0_RTSENA 0x00400000 +#define AR5K_AR5212_DESC_TX_CTL0_VEOL 0x00800000 +#define AR5K_AR5212_DESC_TX_CTL0_CLRDMASK 0x01000000 +#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000 +#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_AR5212_DESC_TX_CTL0_INTREQ 0x20000000 +#define AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 +#define AR5K_AR5212_DESC_TX_CTL0_CTSENA 0x80000000 + + /* + * TX control word 1 + */ + u_int32_t tx_control_1; + +#define AR5K_AR5212_DESC_TX_CTL1_BUF_LEN 0x00000fff +#define AR5K_AR5212_DESC_TX_CTL1_MORE 0x00001000 +#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 +#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE 0x00f00000 +#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE_S 20 +#define AR5K_AR5212_DESC_TX_CTL1_NOACK 0x01000000 +#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC 0x06000000 +#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC_S 25 +#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN 0x18000000 +#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN_S 27 +#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN 0x60000000 +#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN_S 29 + + /* + * TX control word 2 + */ + u_int32_t tx_control_2; + +#define AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION 0x00007fff +#define AR5K_AR5212_DESC_TX_CTL2_DURATION_UPDATE_ENABLE 0x00008000 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0 0x000f0000 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0_S 16 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1 0x00f00000 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1_S 20 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2 0x0f000000 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2_S 24 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3 0xf0000000 +#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3_S 28 + + /* + * TX control word 3 + */ + u_int32_t tx_control_3; + +#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0 0x0000001f +#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1 0x000003e0 +#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1_S 5 +#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2 0x00007c00 +#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2_S 10 +#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3 0x000f8000 +#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3_S 15 +#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE 0x01f00000 +#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE_S 20 +} __packed; + +struct ath5k_tx_status { + /* + * TX status word 0 + */ + u_int32_t tx_status_0; + +#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 +#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 +#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 +#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 + + /* + * TX status word 1 + */ + u_int32_t tx_status_1; + +#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 +#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe +#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 +#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 +#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 +} __packed; + + +/* + * Initial register values which have to be loaded into the + * card at boot time and after each reset. + */ + +#define AR5K_AR5211_INI { \ + { 0x000c, 0x00000000 }, \ + { 0x0028, 0x84849c9c }, \ + { 0x002c, 0x7c7c7c7c }, \ + { 0x0034, 0x00000005 }, \ + { 0x0040, 0x00000000 }, \ + { 0x0044, 0x00000008 }, \ + { 0x0048, 0x00000008 }, \ + { 0x004c, 0x00000010 }, \ + { 0x0050, 0x00000000 }, \ + { 0x0054, 0x0000001f }, \ + { 0x0800, 0x00000000 }, \ + { 0x0804, 0x00000000 }, \ + { 0x0808, 0x00000000 }, \ + { 0x080c, 0x00000000 }, \ + { 0x0810, 0x00000000 }, \ + { 0x0814, 0x00000000 }, \ + { 0x0818, 0x00000000 }, \ + { 0x081c, 0x00000000 }, \ + { 0x0820, 0x00000000 }, \ + { 0x0824, 0x00000000 }, \ + { 0x1230, 0x00000000 }, \ + { 0x8004, 0x00000000 }, \ + { 0x8008, 0x00000000 }, \ + { 0x800c, 0x00000000 }, \ + { 0x8018, 0x00000000 }, \ + { 0x8024, 0x00000000 }, \ + { 0x8028, 0x00000030 }, \ + { 0x802c, 0x0007ffff }, \ + { 0x8030, 0x01ffffff }, \ + { 0x8034, 0x00000031 }, \ + { 0x8038, 0x00000000 }, \ + { 0x803c, 0x00000000 }, \ + { 0x8040, 0x00000000 }, \ + { 0x8044, 0x00000002 }, \ + { 0x8048, 0x00000000 }, \ + { 0x8054, 0x00000000 }, \ + { 0x8058, 0x00000000 }, \ + /* PHY registers */ \ + { 0x9808, 0x00000000 }, \ + { 0x980c, 0x2d849093 }, \ + { 0x9810, 0x7d32e000 }, \ + { 0x9814, 0x00000f6b }, \ + { 0x981c, 0x00000000 }, \ + { 0x982c, 0x00026ffe }, \ + { 0x9830, 0x00000000 }, \ + { 0x983c, 0x00020100 }, \ + { 0x9840, 0x206a017a }, \ + { 0x984c, 0x1284613c }, \ + { 0x9854, 0x00000859 }, \ + { 0x9868, 0x409a4190 }, \ + { 0x986c, 0x050cb081 }, \ + { 0x9870, 0x0000000f }, \ + { 0x9874, 0x00000080 }, \ + { 0x9878, 0x0000000c }, \ + { 0x9900, 0x00000000 }, \ + { 0x9904, 0x00000000 }, \ + { 0x9908, 0x00000000 }, \ + { 0x990c, 0x00800000 }, \ + { 0x9910, 0x00000001 }, \ + { 0x991c, 0x0000092a }, \ + { 0x9920, 0x00000000 }, \ + { 0x9924, 0x00058a05 }, \ + { 0x9928, 0x00000001 }, \ + { 0x992c, 0x00000000 }, \ + { 0x9930, 0x00000000 }, \ + { 0x9934, 0x00000000 }, \ + { 0x9938, 0x00000000 }, \ + { 0x993c, 0x0000003f }, \ + { 0x9940, 0x00000004 }, \ + { 0x9948, 0x00000000 }, \ + { 0x994c, 0x00000000 }, \ + { 0x9950, 0x00000000 }, \ + { 0x9954, 0x5d50f14c }, \ + { 0x9958, 0x00000018 }, \ + { 0x995c, 0x004b6a8e }, \ + { 0xa184, 0x06ff05ff }, \ + { 0xa188, 0x07ff07ff }, \ + { 0xa18c, 0x08ff08ff }, \ + { 0xa190, 0x09ff09ff }, \ + { 0xa194, 0x0aff0aff }, \ + { 0xa198, 0x0bff0bff }, \ + { 0xa19c, 0x0cff0cff }, \ + { 0xa1a0, 0x0dff0dff }, \ + { 0xa1a4, 0x0fff0eff }, \ + { 0xa1a8, 0x12ff12ff }, \ + { 0xa1ac, 0x14ff13ff }, \ + { 0xa1b0, 0x16ff15ff }, \ + { 0xa1b4, 0x19ff17ff }, \ + { 0xa1b8, 0x1bff1aff }, \ + { 0xa1bc, 0x1eff1dff }, \ + { 0xa1c0, 0x23ff20ff }, \ + { 0xa1c4, 0x27ff25ff }, \ + { 0xa1c8, 0x2cff29ff }, \ + { 0xa1cc, 0x31ff2fff }, \ + { 0xa1d0, 0x37ff34ff }, \ + { 0xa1d4, 0x3aff3aff }, \ + { 0xa1d8, 0x3aff3aff }, \ + { 0xa1dc, 0x3aff3aff }, \ + { 0xa1e0, 0x3aff3aff }, \ + { 0xa1e4, 0x3aff3aff }, \ + { 0xa1e8, 0x3aff3aff }, \ + { 0xa1ec, 0x3aff3aff }, \ + { 0xa1f0, 0x3aff3aff }, \ + { 0xa1f4, 0x3aff3aff }, \ + { 0xa1f8, 0x3aff3aff }, \ + { 0xa1fc, 0x3aff3aff }, \ + /* BB gain table (64bytes) */ \ + { 0x9b00, 0x00000000 }, \ + { 0x9b04, 0x00000020 }, \ + { 0x9b08, 0x00000010 }, \ + { 0x9b0c, 0x00000030 }, \ + { 0x9b10, 0x00000008 }, \ + { 0x9b14, 0x00000028 }, \ + { 0x9b18, 0x00000004 }, \ + { 0x9b1c, 0x00000024 }, \ + { 0x9b20, 0x00000014 }, \ + { 0x9b24, 0x00000034 }, \ + { 0x9b28, 0x0000000c }, \ + { 0x9b2c, 0x0000002c }, \ + { 0x9b30, 0x00000002 }, \ + { 0x9b34, 0x00000022 }, \ + { 0x9b38, 0x00000012 }, \ + { 0x9b3c, 0x00000032 }, \ + { 0x9b40, 0x0000000a }, \ + { 0x9b44, 0x0000002a }, \ + { 0x9b48, 0x00000006 }, \ + { 0x9b4c, 0x00000026 }, \ + { 0x9b50, 0x00000016 }, \ + { 0x9b54, 0x00000036 }, \ + { 0x9b58, 0x0000000e }, \ + { 0x9b5c, 0x0000002e }, \ + { 0x9b60, 0x00000001 }, \ + { 0x9b64, 0x00000021 }, \ + { 0x9b68, 0x00000011 }, \ + { 0x9b6c, 0x00000031 }, \ + { 0x9b70, 0x00000009 }, \ + { 0x9b74, 0x00000029 }, \ + { 0x9b78, 0x00000005 }, \ + { 0x9b7c, 0x00000025 }, \ + { 0x9b80, 0x00000015 }, \ + { 0x9b84, 0x00000035 }, \ + { 0x9b88, 0x0000000d }, \ + { 0x9b8c, 0x0000002d }, \ + { 0x9b90, 0x00000003 }, \ + { 0x9b94, 0x00000023 }, \ + { 0x9b98, 0x00000013 }, \ + { 0x9b9c, 0x00000033 }, \ + { 0x9ba0, 0x0000000b }, \ + { 0x9ba4, 0x0000002b }, \ + { 0x9ba8, 0x0000002b }, \ + { 0x9bac, 0x0000002b }, \ + { 0x9bb0, 0x0000002b }, \ + { 0x9bb4, 0x0000002b }, \ + { 0x9bb8, 0x0000002b }, \ + { 0x9bbc, 0x0000002b }, \ + { 0x9bc0, 0x0000002b }, \ + { 0x9bc4, 0x0000002b }, \ + { 0x9bc8, 0x0000002b }, \ + { 0x9bcc, 0x0000002b }, \ + { 0x9bd0, 0x0000002b }, \ + { 0x9bd4, 0x0000002b }, \ + { 0x9bd8, 0x0000002b }, \ + { 0x9bdc, 0x0000002b }, \ + { 0x9be0, 0x0000002b }, \ + { 0x9be4, 0x0000002b }, \ + { 0x9be8, 0x0000002b }, \ + { 0x9bec, 0x0000002b }, \ + { 0x9bf0, 0x0000002b }, \ + { 0x9bf4, 0x0000002b }, \ + { 0x9bf8, 0x00000002 }, \ + { 0x9bfc, 0x00000016 }, \ + /* PHY activation */ \ + { 0x98d4, 0x00000020 }, \ + { 0x98d8, 0x00601068 }, \ +} + +struct ath5k_ar5212_ini { + u_int8_t ini_flags; + u_int16_t ini_register; + u_int32_t ini_value; + +#define AR5K_INI_FLAG_511X 0x00 +#define AR5K_INI_FLAG_5111 0x01 +#define AR5K_INI_FLAG_5112 0x02 +#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) +}; + +#define AR5K_AR5212_INI { \ + { AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 }, \ + { AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 }, \ + { AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 }, \ + { AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 }, \ + { AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f }, \ + { AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x081c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0820, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x0824, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1230, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1270, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1038, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1078, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1138, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1178, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1238, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1278, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1338, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1378, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1438, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1478, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x14b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x14f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1538, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1578, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x15b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x15f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1638, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1678, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x16b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x16f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1738, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x1778, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x17b8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x17f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x103c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x107c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x10fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x113c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x117c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x11fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x123c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x127c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x12fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x133c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x137c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13bc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x13fc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x143c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x147c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8004, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8008, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x800c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8018, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8020, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8024, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8028, 0x00000030 }, \ + { AR5K_INI_FLAG_BOTH, 0x802c, 0x0007ffff }, \ + { AR5K_INI_FLAG_BOTH, 0x8030, 0x01ffffff }, \ + { AR5K_INI_FLAG_BOTH, 0x8034, 0x00000031 }, \ + { AR5K_INI_FLAG_BOTH, 0x8038, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x803c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8048, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8054, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8058, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x805c, 0xffffc7ff }, \ + { AR5K_INI_FLAG_BOTH, 0x8080, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8084, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8088, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x808c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8090, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8094, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8098, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80c0, 0x2a82301a }, \ + { AR5K_INI_FLAG_BOTH, 0x80c4, 0x05dc01e0 }, \ + { AR5K_INI_FLAG_BOTH, 0x80c8, 0x1f402710 }, \ + { AR5K_INI_FLAG_BOTH, 0x80cc, 0x01f40000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80d0, 0x00001e1c }, \ + { AR5K_INI_FLAG_BOTH, 0x80d4, 0x0002aaaa }, \ + { AR5K_INI_FLAG_BOTH, 0x80d8, 0x02005555 }, \ + { AR5K_INI_FLAG_BOTH, 0x80dc, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80e0, 0xffffffff }, \ + { AR5K_INI_FLAG_BOTH, 0x80e4, 0x0000ffff }, \ + { AR5K_INI_FLAG_BOTH, 0x80e8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80ec, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80f0, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80f4, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80f8, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x80fc, 0x00000088 }, \ + { AR5K_INI_FLAG_BOTH, 0x8700, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8704, 0x0000008c }, \ + { AR5K_INI_FLAG_BOTH, 0x8708, 0x000000e4 }, \ + { AR5K_INI_FLAG_BOTH, 0x870c, 0x000002d5 }, \ + { AR5K_INI_FLAG_BOTH, 0x8710, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8714, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8718, 0x000000a0 }, \ + { AR5K_INI_FLAG_BOTH, 0x871c, 0x000001c9 }, \ + { AR5K_INI_FLAG_BOTH, 0x8720, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8724, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8728, 0x00000030 }, \ + { AR5K_INI_FLAG_BOTH, 0x872c, 0x0000003c }, \ + { AR5K_INI_FLAG_BOTH, 0x8730, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8734, 0x0000002c }, \ + { AR5K_INI_FLAG_BOTH, 0x8738, 0x00000030 }, \ + { AR5K_INI_FLAG_BOTH, 0x873c, 0x0000003c }, \ + { AR5K_INI_FLAG_BOTH, 0x8740, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8744, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8748, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x874c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8750, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8754, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8758, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x875c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8760, 0x000000d5 }, \ + { AR5K_INI_FLAG_BOTH, 0x8764, 0x000000df }, \ + { AR5K_INI_FLAG_BOTH, 0x8768, 0x00000102 }, \ + { AR5K_INI_FLAG_BOTH, 0x876c, 0x0000013a }, \ + { AR5K_INI_FLAG_BOTH, 0x8770, 0x00000075 }, \ + { AR5K_INI_FLAG_BOTH, 0x8774, 0x0000007f }, \ + { AR5K_INI_FLAG_BOTH, 0x8778, 0x000000a2 }, \ + { AR5K_INI_FLAG_BOTH, 0x877c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8100, 0x00010002 }, \ + { AR5K_INI_FLAG_BOTH, 0x8104, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x8108, 0x000000c0 }, \ + { AR5K_INI_FLAG_BOTH, 0x810c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x8110, 0x00000168 }, \ + { AR5K_INI_FLAG_BOTH, 0x8114, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x87c0, 0x03020100 }, \ + { AR5K_INI_FLAG_BOTH, 0x87c4, 0x07060504 }, \ + { AR5K_INI_FLAG_BOTH, 0x87c8, 0x0b0a0908 }, \ + { AR5K_INI_FLAG_BOTH, 0x87cc, 0x0f0e0d0c }, \ + { AR5K_INI_FLAG_BOTH, 0x87d0, 0x13121110 }, \ + { AR5K_INI_FLAG_BOTH, 0x87d4, 0x17161514 }, \ + { AR5K_INI_FLAG_BOTH, 0x87d8, 0x1b1a1918 }, \ + { AR5K_INI_FLAG_BOTH, 0x87dc, 0x1f1e1d1c }, \ + { AR5K_INI_FLAG_BOTH, 0x87e0, 0x03020100 }, \ + { AR5K_INI_FLAG_BOTH, 0x87e4, 0x07060504 }, \ + { AR5K_INI_FLAG_BOTH, 0x87e8, 0x0b0a0908 }, \ + { AR5K_INI_FLAG_BOTH, 0x87ec, 0x0f0e0d0c }, \ + { AR5K_INI_FLAG_BOTH, 0x87f0, 0x13121110 }, \ + { AR5K_INI_FLAG_BOTH, 0x87f4, 0x17161514 }, \ + { AR5K_INI_FLAG_BOTH, 0x87f8, 0x1b1a1918 }, \ + { AR5K_INI_FLAG_BOTH, 0x87fc, 0x1f1e1d1c }, \ + /* PHY registers */ \ + { AR5K_INI_FLAG_BOTH, 0x9808, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x980c, 0xad848e19 }, \ + { AR5K_INI_FLAG_BOTH, 0x9810, 0x7d28e000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9814, 0x9c0a9f6b }, \ + { AR5K_INI_FLAG_BOTH, 0x981c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x982c, 0x00022ffe }, \ + { AR5K_INI_FLAG_BOTH, 0x983c, 0x00020100 }, \ + { AR5K_INI_FLAG_BOTH, 0x9840, 0x206a017a }, \ + { AR5K_INI_FLAG_BOTH, 0x984c, 0x1284613c }, \ + { AR5K_INI_FLAG_BOTH, 0x9854, 0x00000859 }, \ + { AR5K_INI_FLAG_BOTH, 0x9900, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9904, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a }, \ + { AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 }, \ + { AR5K_INI_FLAG_BOTH, 0x9934, 0x1e1f2022 }, \ + { AR5K_INI_FLAG_BOTH, 0x9938, 0x0a0b0c0d }, \ + { AR5K_INI_FLAG_BOTH, 0x993c, 0x0000003f }, \ + { AR5K_INI_FLAG_BOTH, 0x9940, 0x00000004 }, \ + { AR5K_INI_FLAG_BOTH, 0x9948, 0x9280b212 }, \ + { AR5K_INI_FLAG_BOTH, 0x9954, 0x5d50e188 }, \ + { AR5K_INI_FLAG_BOTH, 0x9958, 0x000000ff }, \ + { AR5K_INI_FLAG_BOTH, 0x995c, 0x004b6a8e }, \ + { AR5K_INI_FLAG_BOTH, 0x9968, 0x000003ce }, \ + { AR5K_INI_FLAG_BOTH, 0x9970, 0x192fb515 }, \ + { AR5K_INI_FLAG_BOTH, 0x9974, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9978, 0x00000001 }, \ + { AR5K_INI_FLAG_BOTH, 0x997c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0xa184, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa188, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa18c, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa190, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa194, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa198, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa19c, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1a0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1a4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1a8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1ac, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1b0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1b4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1b8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1bc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1c0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1c4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1c8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1cc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1d0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1d4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1d8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1dc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1e0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1e4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1e8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1ec, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1f0, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff }, \ + { AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 }, \ + { AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 }, \ + { AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 }, \ + { AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a }, \ + { AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 }, \ + { AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 }, \ + { AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 }, \ + { AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0xa234, 0x20202020 }, \ + { AR5K_INI_FLAG_BOTH, 0xa238, 0x20202020 }, \ + { AR5K_INI_FLAG_BOTH, 0xa23c, 0x13c889af }, \ + { AR5K_INI_FLAG_BOTH, 0xa240, 0x38490a20 }, \ + { AR5K_INI_FLAG_BOTH, 0xa244, 0x00007bb6 }, \ + { AR5K_INI_FLAG_BOTH, 0xa248, 0x0fff3ffc }, \ + { AR5K_INI_FLAG_BOTH, 0x9b00, 0x00000000 }, \ + { AR5K_INI_FLAG_BOTH, 0x9b28, 0x0000000c }, \ + { AR5K_INI_FLAG_BOTH, 0x9b38, 0x00000012 }, \ + { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \ + { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \ + { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \ + /* AR5111 specific */ \ + { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \ + { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \ + { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \ + { AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a }, \ + { AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 }, \ + { AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 }, \ + { AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 }, \ + { AR5K_INI_FLAG_5111, 0x9b10, 0x00000008 }, \ + { AR5K_INI_FLAG_5111, 0x9b14, 0x00000028 }, \ + { AR5K_INI_FLAG_5111, 0x9b18, 0x00000004 }, \ + { AR5K_INI_FLAG_5111, 0x9b1c, 0x00000024 }, \ + { AR5K_INI_FLAG_5111, 0x9b20, 0x00000014 }, \ + { AR5K_INI_FLAG_5111, 0x9b24, 0x00000034 }, \ + { AR5K_INI_FLAG_5111, 0x9b2c, 0x0000002c }, \ + { AR5K_INI_FLAG_5111, 0x9b30, 0x00000002 }, \ + { AR5K_INI_FLAG_5111, 0x9b34, 0x00000022 }, \ + { AR5K_INI_FLAG_5111, 0x9b3c, 0x00000032 }, \ + { AR5K_INI_FLAG_5111, 0x9b40, 0x0000000a }, \ + { AR5K_INI_FLAG_5111, 0x9b44, 0x0000002a }, \ + { AR5K_INI_FLAG_5111, 0x9b48, 0x00000006 }, \ + { AR5K_INI_FLAG_5111, 0x9b4c, 0x00000026 }, \ + { AR5K_INI_FLAG_5111, 0x9b50, 0x00000016 }, \ + { AR5K_INI_FLAG_5111, 0x9b54, 0x00000036 }, \ + { AR5K_INI_FLAG_5111, 0x9b58, 0x0000000e }, \ + { AR5K_INI_FLAG_5111, 0x9b5c, 0x0000002e }, \ + { AR5K_INI_FLAG_5111, 0x9b60, 0x00000001 }, \ + { AR5K_INI_FLAG_5111, 0x9b68, 0x00000011 }, \ + { AR5K_INI_FLAG_5111, 0x9b6c, 0x00000031 }, \ + { AR5K_INI_FLAG_5111, 0x9b70, 0x00000009 }, \ + { AR5K_INI_FLAG_5111, 0x9b74, 0x00000029 }, \ + { AR5K_INI_FLAG_5111, 0x9b78, 0x00000005 }, \ + { AR5K_INI_FLAG_5111, 0x9b7c, 0x00000025 }, \ + { AR5K_INI_FLAG_5111, 0x9b80, 0x00000015 }, \ + { AR5K_INI_FLAG_5111, 0x9b84, 0x00000035 }, \ + { AR5K_INI_FLAG_5111, 0x9b88, 0x0000000d }, \ + { AR5K_INI_FLAG_5111, 0x9b90, 0x00000003 }, \ + { AR5K_INI_FLAG_5111, 0x9b94, 0x00000023 }, \ + { AR5K_INI_FLAG_5111, 0x9b98, 0x00000013 }, \ + { AR5K_INI_FLAG_5111, 0x9ba0, 0x0000000b }, \ + { AR5K_INI_FLAG_5111, 0x9ba4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9ba8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bac, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bb0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bb4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bb8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bbc, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bc0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bc4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bc8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bcc, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bd0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bd4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bd8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bdc, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9be0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9be4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9be8, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bec, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bf0, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \ + { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \ + { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \ + /* AR5112 specific */ \ + { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \ + { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \ + { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \ + { AR5K_INI_FLAG_5112, 0x9b0c, 0x00000003 }, \ + { AR5K_INI_FLAG_5112, 0x9b10, 0x00000004 }, \ + { AR5K_INI_FLAG_5112, 0x9b14, 0x00000005 }, \ + { AR5K_INI_FLAG_5112, 0x9b18, 0x00000008 }, \ + { AR5K_INI_FLAG_5112, 0x9b1c, 0x00000009 }, \ + { AR5K_INI_FLAG_5112, 0x9b20, 0x0000000a }, \ + { AR5K_INI_FLAG_5112, 0x9b24, 0x0000000b }, \ + { AR5K_INI_FLAG_5112, 0x9b2c, 0x0000000d }, \ + { AR5K_INI_FLAG_5112, 0x9b30, 0x00000010 }, \ + { AR5K_INI_FLAG_5112, 0x9b34, 0x00000011 }, \ + { AR5K_INI_FLAG_5112, 0x9b3c, 0x00000013 }, \ + { AR5K_INI_FLAG_5112, 0x9b40, 0x00000014 }, \ + { AR5K_INI_FLAG_5112, 0x9b44, 0x00000015 }, \ + { AR5K_INI_FLAG_5112, 0x9b48, 0x00000018 }, \ + { AR5K_INI_FLAG_5112, 0x9b4c, 0x00000019 }, \ + { AR5K_INI_FLAG_5112, 0x9b50, 0x0000001a }, \ + { AR5K_INI_FLAG_5112, 0x9b54, 0x0000001b }, \ + { AR5K_INI_FLAG_5112, 0x9b58, 0x0000001c }, \ + { AR5K_INI_FLAG_5112, 0x9b5c, 0x0000001d }, \ + { AR5K_INI_FLAG_5112, 0x9b60, 0x00000020 }, \ + { AR5K_INI_FLAG_5112, 0x9b68, 0x00000022 }, \ + { AR5K_INI_FLAG_5112, 0x9b6c, 0x00000023 }, \ + { AR5K_INI_FLAG_5112, 0x9b70, 0x00000024 }, \ + { AR5K_INI_FLAG_5112, 0x9b74, 0x00000025 }, \ + { AR5K_INI_FLAG_5112, 0x9b78, 0x00000028 }, \ + { AR5K_INI_FLAG_5112, 0x9b7c, 0x00000029 }, \ + { AR5K_INI_FLAG_5112, 0x9b80, 0x0000002a }, \ + { AR5K_INI_FLAG_5112, 0x9b84, 0x0000002b }, \ + { AR5K_INI_FLAG_5112, 0x9b88, 0x0000002c }, \ + { AR5K_INI_FLAG_5112, 0x9b90, 0x00000030 }, \ + { AR5K_INI_FLAG_5112, 0x9b94, 0x00000031 }, \ + { AR5K_INI_FLAG_5112, 0x9b98, 0x00000032 }, \ + { AR5K_INI_FLAG_5112, 0x9ba0, 0x00000034 }, \ + { AR5K_INI_FLAG_5112, 0x9ba4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9ba8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bac, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bb0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bb4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bb8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bbc, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bc0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bc4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bc8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bcc, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bd0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bd4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bd8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bdc, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9be0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9be4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9be8, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bec, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bf0, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bf4, 0x00000035 }, \ + { AR5K_INI_FLAG_5112, 0x9bf8, 0x00000010 }, \ + { AR5K_INI_FLAG_5112, 0x9bfc, 0x0000001a }, \ +} + +struct ath5k_ar5211_ini_mode { + u_int16_t mode_register; + u_int32_t mode_value[4]; +}; + +#define AR5K_AR5211_INI_MODE { \ + { 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \ + { 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ + { 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, \ + { 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, \ + { 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, \ + { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, \ + { 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, \ + { 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, \ + { 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, \ + { 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, \ + { 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, \ + { 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, \ + { 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ + { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, \ + { 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, \ + { 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, \ + { 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \ + { 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, \ + { 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, \ + { 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, \ + { 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ + { 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, \ + { 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, \ + { 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, \ + { 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, \ + { 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, \ +} + +struct ath5k_ar5212_ini_mode { + u_int16_t mode_register; + u_int8_t mode_flags; + u_int32_t mode_value[2][5]; +}; + +#define AR5K_AR5212_INI_MODE { \ + { 0x0030, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \ + } }, \ + { 0x1040, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1044, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1048, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x104c, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1050, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1054, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1058, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x105c, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1060, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1064, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ + } }, \ + { 0x1030, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } \ + } }, \ + { 0x1070, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } \ + } }, \ + { 0x10b0, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } \ + } }, \ + { 0x10f0, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } \ + } }, \ + { 0x8014, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } \ + } }, \ + { 0x9804, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } \ + } }, \ + { 0x9820, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } \ + } }, \ + { 0x9834, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ + } }, \ + { 0x9838, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } \ + } }, \ + { 0x9844, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 } \ + } }, \ + { 0x9850, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } \ + } }, \ + { 0x9858, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } \ + } }, \ + { 0x9860, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 } \ + } }, \ + { 0x9864, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } \ + } }, \ + { 0x9868, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } \ + } }, \ + { 0x9918, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } \ + } }, \ + { 0x9924, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } \ + } }, \ + { 0xa180, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff } \ + } }, \ + { 0xa230, AR5K_INI_FLAG_511X, { \ + { 0, }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } \ + } }, \ + { 0x801c, AR5K_INI_FLAG_BOTH, { \ + { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x128d8fab, 0x09880fcf }, \ + { 0x128d93a7, 0x098813cf, 0x04e01395, 0x128d93ab, 0x098813cf } \ + } }, \ + { 0x9824, AR5K_INI_FLAG_BOTH, { \ + { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e }, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ + } }, \ + { 0x9828, AR5K_INI_FLAG_BOTH, { \ + { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 }, \ + { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } \ + } }, \ + { 0x9848, AR5K_INI_FLAG_BOTH, { \ + { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 }, \ + { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } \ + } }, \ + { 0x985c, AR5K_INI_FLAG_BOTH, { \ + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e }, \ + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } \ + } }, \ + { 0x986c, AR5K_INI_FLAG_BOTH, { \ + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 }, \ + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } \ + } }, \ + { 0x9914, AR5K_INI_FLAG_BOTH, { \ + { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 }, \ + { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } \ + } }, \ + { 0x9944, AR5K_INI_FLAG_BOTH, { \ + { 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 }, \ + { 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 } \ + } }, \ + { 0xa204, AR5K_INI_FLAG_5112, { \ + { 0, }, \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } \ + } }, \ + { 0xa208, AR5K_INI_FLAG_5112, { \ + { 0, }, \ + { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } \ + } }, \ + { 0xa20c, AR5K_INI_FLAG_5112, { \ + { 0, }, \ + { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } \ + } }, \ +} + +struct ath5k_ar5211_ini_rf { + u_int16_t rf_register; + u_int32_t rf_value[2]; +}; + +#define AR5K_AR5211_INI_RF { \ + { 0x0000a204, { 0x00000000, 0x00000000 } }, \ + { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \ + { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \ + { 0x0000a210, { 0x0199a003, 0x0199a003 } }, \ + { 0x0000a214, { 0x044cd610, 0x044cd610 } }, \ + { 0x0000a218, { 0x13800040, 0x13800040 } }, \ + { 0x0000a21c, { 0x1be00060, 0x1be00060 } }, \ + { 0x0000a220, { 0x0c53800a, 0x0c53800a } }, \ + { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \ + { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \ + { 0x0000a22c, { 0x00000020, 0x00000020 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00380000, 0x00380000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \ + { 0x000098d4, { 0x00000000, 0x00000004 } }, \ + \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x10000000, 0x10000000 } }, \ + { 0x0000989c, { 0x04000000, 0x04000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x00000000 } }, \ + { 0x0000989c, { 0x00000000, 0x0a000000 } }, \ + { 0x0000989c, { 0x00380080, 0x02380080 } }, \ + { 0x0000989c, { 0x00020006, 0x00000006 } }, \ + { 0x0000989c, { 0x00000092, 0x00000092 } }, \ + { 0x0000989c, { 0x000000a0, 0x000000a0 } }, \ + { 0x0000989c, { 0x00040007, 0x00040007 } }, \ + { 0x000098d4, { 0x0000001a, 0x0000001a } }, \ + { 0x0000989c, { 0x00000048, 0x00000048 } }, \ + { 0x0000989c, { 0x00000010, 0x00000010 } }, \ + { 0x0000989c, { 0x00000008, 0x00000008 } }, \ + { 0x0000989c, { 0x0000000f, 0x0000000f } }, \ + { 0x0000989c, { 0x000000f2, 0x00000062 } }, \ + { 0x0000989c, { 0x0000904f, 0x0000904c } }, \ + { 0x0000989c, { 0x0000125a, 0x0000129a } }, \ + { 0x000098cc, { 0x0000000e, 0x0000000f } }, \ +} Index: ath5k.h =================================================================== --- ath5k.h (revision 0) +++ ath5k.h (revision 2232) @@ -0,0 +1,1241 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter + * Copyright (c) 2006-2007 Nick Kossifidis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id$ + */ + +/* + * HAL interface for Atheros Wireless LAN devices. + * + * ar5k is a free replacement of the binary-only HAL used by some drivers + * for Atheros chipsets. While using a different ABI, it tries to be + * source-compatible with the original (non-free) HAL interface. + * + * Many thanks to various contributors who supported the development of + * ar5k with hard work and useful information. And, of course, for all the + * people who encouraged me to continue this work which has been based + * on my initial approach found on http://team.vantronix.net/ar5k/. + */ + +#ifndef _AR5K_H +#define _AR5K_H + +/*Os dependent definitions*/ +#include "ah_osdep.h" +#include "ath5k_hw.h" + +/*Regulatory domain & Channel definitions*/ +#include "ieee80211_regdomain.h" + +/*Options*/ +#include "opt_ah.h" + +/* + *Translation for MadWiFi combatibility + *(damn this is changed AGAIN in if_ath.pci :P) + */ +#include "translation.h" + +/*Use with MadWiFi/net80211*/ +#include "stack_net80211.h" + + +/****************************\ + GENERIC DRIVER DEFINITIONS +\****************************/ + +/* + * C doesn't support boolean ;-( + * TODO: See if there is a bool definition somewere else + * in the kernel, we shouldn't redefine it if it does... + */ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif +typedef u_int8_t AR5K_BOOL; + +/* + * Error codes reported from HAL to the driver + */ +typedef enum { + AR5K_OK = 0, /* Everything went O.K.*/ + AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/ + AR5K_EIO = 2, /* Hardware I/O Error*/ + AR5K_EELOCKED = 3, /* Unable to access EEPROM*/ + AR5K_EEBADSUM = 4, /* Invalid EEPROM checksum*/ + AR5K_EEREAD = 5, /* Unable to get device caps from EEPROM */ + AR5K_EEBADMAC = 6, /* Unable to read MAC address from EEPROM */ + AR5K_EINVAL = 7, /* Invalid parameter to function */ + AR5K_ENOTSUPP = 8, /* Hardware revision not supported */ + AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */ +} AR5K_STATUS; + +/* + * Some tuneable values (these should be changeable by the user) + */ +#define AR5K_TUNE_DMA_BEACON_RESP 2 +#define AR5K_TUNE_SW_BEACON_RESP 10 +#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 +#define AR5K_TUNE_RADAR_ALERT FALSE +#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 +#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1) +#define AR5K_TUNE_RSSI_THRES 1792 +#define AR5K_TUNE_REGISTER_TIMEOUT 20000 +#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 +#define AR5K_TUNE_BEACON_INTERVAL 100 +#define AR5K_TUNE_AIFS 2 +#define AR5K_TUNE_AIFS_11B 2 +#define AR5K_TUNE_AIFS_XR 0 +#define AR5K_TUNE_CWMIN 15 +#define AR5K_TUNE_CWMIN_11B 31 +#define AR5K_TUNE_CWMIN_XR 3 +#define AR5K_TUNE_CWMAX 1023 +#define AR5K_TUNE_CWMAX_11B 1023 +#define AR5K_TUNE_CWMAX_XR 7 +#define AR5K_TUNE_NOISE_FLOOR -72 +#define AR5K_TUNE_MAX_TXPOWER 60 +#define AR5K_TUNE_DEFAULT_TXPOWER 30 +#define AR5K_TUNE_TPC_TXPOWER TRUE +#define AR5K_TUNE_ANT_DIVERSITY TRUE +#define AR5K_TUNE_HWTXTRIES 4 + +/* token to use for aifs, cwmin, cwmax in MadWiFi */ +#define AR5K_TXQ_USEDEFAULT ((u_int32_t) -1) + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ +static const u_char etherbroadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +//#define etherbroadcastaddr 0xff + + + + +/*****************************\ + GENERIC CHIPSET DEFINITIONS +\*****************************/ + +/* MAC Chips*/ +enum ath5k_version { + AR5K_AR5210 = 0, + AR5K_AR5211 = 1, + AR5K_AR5212 = 2, +}; + +/*PHY Chips*/ +enum ath5k_radio { + AR5K_AR5110 = 0, + AR5K_AR5111 = 1, + AR5K_AR5112 = 2, +}; + +/* + * Common silicon revision/version values + */ +enum ath5k_srev_type { + AR5K_VERSION_VER, + AR5K_VERSION_REV, + AR5K_VERSION_RAD, + AR5K_VERSION_DEV +}; + +struct ath5k_srev_name { + const char *sr_name; + enum ath5k_srev_type sr_type; + u_int sr_val; +}; + +#define AR5K_SREV_NAME { \ + { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ + { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ + { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ + { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ + { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ + { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ + { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ + { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ + { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ + { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ + { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ + { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ + { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ + { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ + { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ + { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ + { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \ + { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \ + { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \ + { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ +} + +#define AR5K_SREV_UNKNOWN 0xffff + +#define AR5K_SREV_VER_AR5210 0x00 +#define AR5K_SREV_VER_AR5311 0x10 +#define AR5K_SREV_VER_AR5311A 0x20 +#define AR5K_SREV_VER_AR5311B 0x30 +#define AR5K_SREV_VER_AR5211 0x40 +#define AR5K_SREV_VER_AR5212 0x50 +#define AR5K_SREV_VER_AR5213 0x55 +#define AR5K_SREV_VER_UNSUPP 0x60 + +#define AR5K_SREV_RAD_5110 0x00 +#define AR5K_SREV_RAD_5111 0x10 +#define AR5K_SREV_RAD_5111A 0x15 +#define AR5K_SREV_RAD_2111 0x20 +#define AR5K_SREV_RAD_5112 0x30 +#define AR5K_SREV_RAD_5112A 0x35 +#define AR5K_SREV_RAD_2112 0x40 +#define AR5K_SREV_RAD_2112A 0x45 +#define AR5K_SREV_RAD_UNSUPP 0x50 + + + + +/****************\ + TX DEFINITIONS +\****************/ + +/* + * Tx Descriptor + */ +struct ath_tx_status { + u_int16_t ts_seqnum; + u_int16_t ts_tstamp; + u_int8_t ts_status; + u_int8_t ts_rate; + int8_t ts_rssi; + u_int8_t ts_shortretry; + u_int8_t ts_longretry; + u_int8_t ts_virtcol; + u_int8_t ts_antenna; +}; + +#define AR5K_TXSTAT_ALTRATE 0x80 +#define AR5K_TXERR_XRETRY 0x01 +#define AR5K_TXERR_FILT 0x02 +#define AR5K_TXERR_FIFO 0x04 + +/* + * Queue types used to classify tx queues. + */ +typedef enum { + AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see ath_hal_releasetxqueue*/ + AR5K_TX_QUEUE_DATA, /*A normal data queue*/ + AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/ + AR5K_TX_QUEUE_BEACON, /*The beacon queue*/ + AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/ + AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ +} AR5K_TX_QUEUE; + +#define AR5K_NUM_TX_QUEUES 10 + +/* + * Queue syb-types to classify normal data queues. + * These are the 4 Access Categories as defined in + * WME spec. 0 is the lowest priority and 4 is the + * highest. Normal data that hasn't been classified + * goes to the Best Effort AC. + */ +typedef enum { + AR5K_WME_AC_BK = 0, /*Background traffic*/ + AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ + AR5K_WME_AC_VI, /*Video traffic*/ + AR5K_WME_AC_VO, /*Voice traffic*/ +} AR5K_TX_QUEUE_SUBTYPE; + +/* + * Queue ID numbers as returned by the HAL, each number + * represents a hw queue. If hw does not support hw queues + * (eg 5210/5211) all data goes in one queue. These match + * d80211 definitions (net80211/MadWiFi don't use them). + */ +typedef enum { + AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ + AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ + AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ + AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ + AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ + AR5K_TX_QUEUE_ID_UAPSD = 8, + AR5K_TX_QUEUE_ID_XR_DATA = 9, +} AR5K_TX_QUEUE_ID; + + +/* + * Flags to set hw queue's parameters... + */ +#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and TXERR interrupts -not used- */ +#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC interrupt -not implemented- */ +#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random post-backoff */ +#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw compression -not implemented-*/ +#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready time expiry policy (?)*/ +#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable backoff while bursting */ +#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable backoff while bursting */ +#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL interrupt -not implemented-*/ + +/* + * A struct to hold tx queue's parameters + */ +typedef struct { + AR5K_TX_QUEUE tqi_type; /* See AR5K_TX_QUEUE */ + AR5K_TX_QUEUE_SUBTYPE tqi_subtype; /* See AR5K_TX_QUEUE_SUBTYPE */ + u_int16_t tqi_flags; /* Tx queue flags (see above) */ + u_int32_t tqi_aifs; /* Arbitrated Interframe Space */ + int32_t tqi_cw_min; /* Minimum Contention Window */ + int32_t tqi_cw_max; /* Maximum Contention Window */ + u_int32_t tqi_cbr_period; /* Constant bit rate period */ + u_int32_t tqi_cbr_overflow_limit; + u_int32_t tqi_burst_time; + u_int32_t tqi_ready_time; /* Not used */ + u_int32_t tqi_comp_buffer;/* Compression Buffer's phys addr */ +} AR5K_TXQ_INFO; + +/* + * Transmit packet types. + * These are not fully used inside OpenHAL yet + */ +typedef enum { + AR5K_PKT_TYPE_NORMAL = 0, + AR5K_PKT_TYPE_ATIM = 1, + AR5K_PKT_TYPE_PSPOLL = 2, + AR5K_PKT_TYPE_BEACON = 3, + AR5K_PKT_TYPE_PROBE_RESP = 4, + AR5K_PKT_TYPE_PIFS = 5, +} AR5K_PKT_TYPE; + +/* + * TX power and TPC settings + */ +#define AR5K_TXPOWER_OFDM(_r, _v) ( \ + ((0 & 1) << ((_v) + 6)) | \ + (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ +) + +#define AR5K_TXPOWER_CCK(_r, _v) ( \ + (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ +) + +/* + * Used to compute TX times + */ +#define AR5K_CCK_SIFS_TIME 10 +#define AR5K_CCK_PREAMBLE_BITS 144 +#define AR5K_CCK_PLCP_BITS 48 + +#define AR5K_OFDM_SIFS_TIME 16 +#define AR5K_OFDM_PREAMBLE_TIME 20 +#define AR5K_OFDM_PLCP_BITS 22 +#define AR5K_OFDM_SYMBOL_TIME 4 + +#define AR5K_TURBO_SIFS_TIME 8 +#define AR5K_TURBO_PREAMBLE_TIME 14 +#define AR5K_TURBO_PLCP_BITS 22 +#define AR5K_TURBO_SYMBOL_TIME 4 + +#define AR5K_XR_SIFS_TIME 16 +#define AR5K_XR_PLCP_BITS 22 +#define AR5K_XR_SYMBOL_TIME 4 + +/* CCK */ +#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) + +#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ + ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ + (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) + +#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ + AR5K_CCK_PHY_TIME(_sp) + \ + ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ + AR5K_CCK_SIFS_TIME + +/* OFDM */ +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_OFDM_SYMBOL_TIME) / 1000) + +#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ + AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ + (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) + +/* TURBO */ +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ + AR5K_TURBO_SYMBOL_TIME) / 1000) + +#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ + AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ + AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ + (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) + +/* eXtendent Range (?)*/ +#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) + +#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ + AR5K_XR_SYMBOL_TIME) / 1000) + +#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) + +#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) + +#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ + AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ + (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) + +/* + * DMA size definitions (2^n+2) + */ +typedef enum { + AR5K_DMASIZE_4B = 0, + AR5K_DMASIZE_8B, + AR5K_DMASIZE_16B, + AR5K_DMASIZE_32B, + AR5K_DMASIZE_64B, + AR5K_DMASIZE_128B, + AR5K_DMASIZE_256B, + AR5K_DMASIZE_512B +} ath5k_dmasize_t; + + + +/****************\ + RX DEFINITIONS +\****************/ + +/* + * Rx Descriptor + */ +struct ath_rx_status { + u_int16_t rs_datalen; + u_int16_t rs_tstamp; + u_int8_t rs_status; + u_int8_t rs_phyerr; + int8_t rs_rssi; + u_int8_t rs_keyix; + u_int8_t rs_rate; + u_int8_t rs_antenna; + u_int8_t rs_more; +}; + +#define AR5K_RXERR_CRC 0x01 +#define AR5K_RXERR_PHY 0x02 +#define AR5K_RXERR_FIFO 0x04 +#define AR5K_RXERR_DECRYPT 0x08 +#define AR5K_RXERR_MIC 0x10 +#define AR5K_RXKEYIX_INVALID ((u_int8_t) - 1) +#define AR5K_TXKEYIX_INVALID ((u_int32_t) - 1) + +/* + * RX filters + * Most of them are not yet used inside OpenHAL + */ +#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ +#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ +#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ +#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ +#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ +#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ +#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame */ +#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests */ +#define AR5K_RX_FILTER_PHYERROR 0x00000100 /* Don't filter phy errors */ +#define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter phy radar errors*/ + +typedef struct { + u_int32_t ackrcv_bad; + u_int32_t rts_bad; + u_int32_t rts_good; + u_int32_t fcs_bad; + u_int32_t beacons; +} AR5K_MIB_STATS; + + + + +/**************************\ + BEACON TIMERS DEFINITIONS +\**************************/ + +#define AR5K_BEACON_PERIOD 0x0000ffff +#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ +#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ + +/* + * Per-station beacon timer state. + */ +typedef struct { + u_int32_t bs_next_beacon; + u_int32_t bs_next_dtim; + u_int32_t bs_interval; /*in TU's -see net80211/ieee80211_var.h- + can also include the above flags*/ + u_int8_t bs_dtim_period; + u_int8_t bs_cfp_period; + u_int16_t bs_cfp_max_duration; /*if non-zero hw is setup to coexist with + a Point Coordination Function capable AP*/ + u_int16_t bs_cfp_du_remain; + u_int16_t bs_tim_offset; + u_int16_t bs_sleep_duration; + u_int16_t bs_bmiss_threshold; + u_int32_t bs_cfp_next; +} AR5K_BEACON_STATE; + + + + +/********************\ + COMMON DEFINITIONS +\********************/ + +/* + * Atheros descriptor + */ +struct ath_desc { + u_int32_t ds_link; + u_int32_t ds_data; + u_int32_t ds_ctl0; + u_int32_t ds_ctl1; + u_int32_t ds_hw[4]; + + union { + struct ath_rx_status rx; + struct ath_tx_status tx; + } ds_us; + +#define ds_rxstat ds_us.rx +#define ds_txstat ds_us.tx + +} __packed; + +#define AR5K_RXDESC_INTREQ 0x0020 + +#define AR5K_TXDESC_CLRDMASK 0x0001 +#define AR5K_TXDESC_NOACK 0x0002 +#define AR5K_TXDESC_RTSENA 0x0004 +#define AR5K_TXDESC_CTSENA 0x0008 +#define AR5K_TXDESC_INTREQ 0x0010 +#define AR5K_TXDESC_VEOL 0x0020 + +/* + * 802.11 operating modes... + */ +#define AR5K_MODE_11A 0x01 +#define AR5K_MODE_11B 0x02 +#define AR5K_MODE_11G 0x04 +#define AR5K_MODE_TURBO 0x08 +#define AR5K_MODE_108G 0x16 +#define AR5K_MODE_XR 0x32 +#define AR5K_MODE_ALL (AR5K_MODE_11A| \ + AR5K_MODE_11B| \ + AR5K_MODE_11G| \ + AR5K_MODE_TURBO|\ + AR5K_MODE_108G| \ + AR5K_MODE_XR) + +/* + * Channel definitions + */ +typedef struct { + u_int16_t freq; /* setting in Mhz */ + u_int16_t channel_flags; + u_int8_t private_flags; /* not used in OpenHAL yet*/ +} AR5K_CHANNEL; + +#define AR5K_SLOT_TIME_9 396 +#define AR5K_SLOT_TIME_20 880 +#define AR5K_SLOT_TIME_MAX 0xffff + +/* channel_flags */ +#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ +#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation)*/ +#define CHANNEL_XR 0x0800 /* XR channel */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) +//#ifdef notdef +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN) +//#else +//#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +//#endif +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_108G CHANNEL_TG +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) + +#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\ + CHANNEL_5GHZ | CHANNEL_TURBO) + +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) +#define CHANNEL_MODES CHANNEL_ALL + +/* + * Used internaly in OpenHAL (ar5211.c/ar5212.c + * for reset_tx_queue). Also see struct AR5K_CHANNEL. + */ +#define IS_CHAN_XR(_c) \ + ((_c.channel_flags & CHANNEL_XR) != 0) + +#define IS_CHAN_B(_c) \ + ((_c.channel_flags & CHANNEL_B) != 0) + +typedef enum { + AR5K_CHIP_5GHZ = CHANNEL_5GHZ, + AR5K_CHIP_2GHZ = CHANNEL_2GHZ, +} AR5K_CHIP; + +/* + * The following structure will be used to map 2GHz channels to + * 5GHz Atheros channels. + */ +struct ath5k_athchan_2ghz { + u_int32_t a2_flags; + u_int16_t a2_athchan; +}; + +/* + * Rate definitions + */ + +#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/ + +typedef struct { + u_int8_t valid; /* Valid for rate control */ + u_int32_t modulation; + u_int16_t rate_kbps; + u_int8_t rate_code; /* Rate mapping for h/w descriptors */ + u_int8_t dot11_rate; + u_int8_t control_rate; + u_int16_t lp_ack_duration;/* long preamble ACK duration */ + u_int16_t sp_ack_duration;/* short preamble ACK duration*/ +} AR5K_RATE; + +typedef struct { + u_int16_t rate_count; + u_int8_t rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */ + AR5K_RATE rates[AR5K_MAX_RATES]; +} AR5K_RATE_TABLE; + +/* + * Rate tables... + */ +#define AR5K_RATES_11A { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_11B { 4, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \ +} + +#define AR5K_RATES_11G { 12, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 3, 2, 1, 0, 255, 255, 255, 255 }, { \ + { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \ + { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \ + { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \ + { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \ + { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \ + { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +#define AR5K_RATES_TURBO { 8, { \ + 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ + 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \ + { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \ + { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \ + { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \ + { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \ + { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \ + { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \ + { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \ +} + +#define AR5K_RATES_XR { 12, { \ + 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ + 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ + 255, 255, 255, 255, 255, 255, 255, 255 }, { \ + { 1, MODULATION_XR, 500, 7, 129, 0 }, \ + { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ + { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ + { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ + { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \ + { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \ + { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \ + { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \ + { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \ + { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \ + { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \ + { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \ +} + +/* + * Crypto definitions + */ + +/* key types */ +typedef enum { + AR5K_CIPHER_WEP = 0, + AR5K_CIPHER_AES_OCB = 1, + AR5K_CIPHER_AES_CCM = 2, + AR5K_CIPHER_CKIP = 3, + AR5K_CIPHER_TKIP = 4, + AR5K_CIPHER_CLR = 5, /* no encryption */ + AR5K_CIPHER_MIC = 127 /* used for Message + Integrity Code */ +} AR5K_CIPHER; + +#define AR5K_KEYVAL_LENGTH_40 5 +#define AR5K_KEYVAL_LENGTH_104 13 +#define AR5K_KEYVAL_LENGTH_128 16 +#define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128 + +typedef struct { + int wk_len; /* key's length */ + u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX]; + u_int8_t wk_type; /* see above */ + u_int8_t wk_mic[8]; /* TKIP MIC key */ +} AR5K_KEYVAL; + + + +/***********************\ + HW RELATED DEFINITIONS +\***********************/ + +/* + * Misc definitions + */ +#define AR5K_RSSI_EP_MULTIPLIER (1<<7) + +#define AR5K_ASSERT_ENTRY(_e, _s) do { \ + if (_e >= _s) \ + return (FALSE); \ +} while (0) + + +typedef struct { + u_int32_t ns_avgbrssi; /* average beacon rssi */ + u_int32_t ns_avgrssi; /* average data rssi */ + u_int32_t ns_avgtxrssi; /* average tx rssi */ +} AR5K_NODE_STATS; + +typedef enum { + AR5K_ANT_VARIABLE = 0, /* variable by programming */ + AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ + AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ + AR5K_ANT_MAX = 3, +} AR5K_ANT_SETTING; + +/* + * HAL interrupt abstraction + */ + +/* + * These are maped to take advantage of some common bits + * between the MAC chips, to be able to set intr properties + * easier. Some of them are not used yet inside OpenHAL. + */ +typedef enum { + AR5K_INT_RX = 0x00000001, + AR5K_INT_RXDESC = 0x00000002, + AR5K_INT_RXNOFRM = 0x00000008, + AR5K_INT_RXEOL = 0x00000010, + AR5K_INT_RXORN = 0x00000020, + AR5K_INT_TX = 0x00000040, + AR5K_INT_TXDESC = 0x00000080, + AR5K_INT_TXURN = 0x00000800, + AR5K_INT_MIB = 0x00001000, + AR5K_INT_RXPHY = 0x00004000, + AR5K_INT_RXKCM = 0x00008000, + AR5K_INT_SWBA = 0x00010000, + AR5K_INT_BMISS = 0x00040000, + AR5K_INT_BNR = 0x00100000, + AR5K_INT_GPIO = 0x01000000, + AR5K_INT_FATAL = 0x40000000, + AR5K_INT_GLOBAL = 0x80000000, + + /*A sum of all the common bits*/ + AR5K_INT_COMMON = AR5K_INT_RXNOFRM + | AR5K_INT_RXDESC + | AR5K_INT_RXEOL + | AR5K_INT_RXORN + | AR5K_INT_TXURN + | AR5K_INT_TXDESC + | AR5K_INT_MIB + | AR5K_INT_RXPHY + | AR5K_INT_RXKCM + | AR5K_INT_SWBA + | AR5K_INT_BMISS + | AR5K_INT_GPIO, + AR5K_INT_NOCARD = 0xffffffff /*Declare that the card + has been removed*/ +} AR5K_INT; + +/* + * Power management + */ +typedef enum { + AR5K_PM_UNDEFINED = 0, + AR5K_PM_AUTO, + AR5K_PM_AWAKE, + AR5K_PM_FULL_SLEEP, + AR5K_PM_NETWORK_SLEEP, +} AR5K_POWER_MODE; + + +/* + * LED states + */ +typedef int AR5K_LED_STATE; + +/* + * These match net80211 definitions (not used in + * d80211). + */ +#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ +#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ +#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ +#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ +#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ + +/* GPIO-controlled software LED */ +#define AR5K_SOFTLED_PIN 0 +#define AR5K_SOFTLED_ON 0 +#define AR5K_SOFTLED_OFF 1 + +/* + * Chipset capabilities -see ath_hal_getcapability- + * get_capability function is not yet fully implemented + * in OpenHAL so most of these don't work yet... + */ +typedef enum { + AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ + AR5K_CAP_CIPHER = 1, /* Can handle encryption */ + AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ + AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ + AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ + AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ + AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ + AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ + AR5K_CAP_COMPRESSION = 8, /* Supports compression */ + AR5K_CAP_BURST = 9, /* Supports packet bursting */ + AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ + AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ + AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ + AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ + AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ + AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ + AR5K_CAP_XR = 16, /* Supports XR mode */ + AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ + AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ + AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ + AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ +} AR5K_CAPABILITY_TYPE; + +typedef struct { + /* + * Supported PHY modes + * (ie. CHANNEL_A, CHANNEL_B, ...) + */ + u_int16_t cap_mode; + + /* + * Frequency range (without regulation restrictions) + */ + struct { + u_int16_t range_2ghz_min; + u_int16_t range_2ghz_max; + u_int16_t range_5ghz_min; + u_int16_t range_5ghz_max; + } cap_range; + + /* + * Active regulation domain settings + */ + struct { + ieee80211_regdomain_t reg_current; + ieee80211_regdomain_t reg_hw; + } cap_regdomain; + + /* + * Values stored in the EEPROM (some of them...) + */ + struct ath5k_eeprom_info cap_eeprom; + + /* + * Queue information + */ + struct { + u_int8_t q_tx_num; + } cap_queues; +} ath5k_capabilities_t; + + +/***************************************\ + HARDWARE ABSTRACTION LAYER STRUCTURE +\***************************************/ + +/* + * Regulation stuff + */ +typedef enum ieee80211_countrycode AR5K_CTRY_CODE; + +/* Default regulation domain if stored value EEPROM value is invalid */ +#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ +#define AR5K_TUNE_CTRY CTRY_DEFAULT + +/* + * Misc defines + */ + +#define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0])) + +typedef struct ath_hal * (ath5k_attach_t) + (u_int16_t, AR5K_SOFTC, AR5K_BUS_TAG, AR5K_BUS_HANDLE, AR5K_STATUS *); + +typedef AR5K_BOOL (ath5k_rfgain_t) + (struct ath_hal *, AR5K_CHANNEL *, u_int); + +/* + * HAL Functions that have different implementations for each chipset... + */ +#define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ath5k_##_n##_##_f +#define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ + _t const AR5K_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, u_int mode); \ + _t void (_a _n##_detach)(struct ath_hal *); \ + /* Reset functions */ \ + _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, AR5K_OPMODE, AR5K_CHANNEL *, \ + AR5K_BOOL change_channel, AR5K_STATUS *status); \ + _t void (_a _n##_set_opmode)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ + /* Transmit functions */ \ + _t AR5K_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, AR5K_BOOL level); \ + _t int (_a _n##_setup_tx_queue)(struct ath_hal *, AR5K_TX_QUEUE, AR5K_TXQ_INFO *); \ + _t AR5K_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ + const AR5K_TXQ_INFO *); \ + _t AR5K_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ + _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, u_int32_t phys_addr); \ + _t AR5K_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ + _t AR5K_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, \ + u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index,\ + u_int antenna_mode, u_int flags, u_int rtscts_rate, \ + u_int rtscts_duration); \ + _t AR5K_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, \ + u_int tx_tries2,u_int tx_rate3, u_int tx_tries3); \ + _t AR5K_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, struct ath_desc *, u_int segLen, \ + AR5K_BOOL firstSeg, AR5K_BOOL lastSeg, const struct ath_desc *);\ + _t AR5K_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, struct ath_desc *); \ + _t AR5K_BOOL (_a _n##_has_veol)(struct ath_hal *); \ + /* Receive Functions */ \ + _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \ + _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \ + _t void (_a _n##_start_rx)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \ + _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \ + _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \ + _t void (_a _n##_set_mcast_filter)(struct ath_hal*, u_int32_t filter0, \ + u_int32_t filter1); \ + _t AR5K_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, u_int32_t index); \ + _t AR5K_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*,u_int32_t index); \ + _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \ + _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \ + _t AR5K_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int32_t size, u_int flags); \ + _t AR5K_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, struct ath_desc *, \ + u_int32_t phyAddr, struct ath_desc *next); \ + _t void (_a _n##_set_rx_signal)(struct ath_hal *, const AR5K_NODE_STATS *); \ + /* Misc Functions */ \ + _t void (_a _n##_dump_state)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int request,const void *args, \ + u_int32_t argsize, void **result, u_int32_t *resultsize); \ + _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \ + _t AR5K_BOOL (_a _n##_set_lladdr)(struct ath_hal *, const u_int8_t*); \ + _t AR5K_BOOL (_a _n##_set_regdomain)(struct ath_hal*, u_int16_t, AR5K_STATUS *); \ + _t void (_a _n##_set_ledstate)(struct ath_hal*, AR5K_LED_STATE); \ + _t void (_a _n##_set_associd)(struct ath_hal*, const u_int8_t *bssid, \ + u_int16_t assocId); \ + _t AR5K_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, u_int32_t gpio); \ + _t AR5K_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, u_int32_t gpio); \ + _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \ + _t AR5K_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, u_int32_t val); \ + _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \ + _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \ + _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \ + _t void (_a _n##_reset_tsf)(struct ath_hal*); \ + _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \ + _t void (_a _n##_update_mib_counters)(struct ath_hal*, AR5K_MIB_STATS*); \ + _t AR5K_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \ + _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ + _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \ + _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \ + /* Key Cache Functions */ \ + _t AR5K_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, AR5K_CIPHER); \ + _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_reset_key)(struct ath_hal*, u_int16_t); \ + _t AR5K_BOOL (_a _n##_is_key_valid)(struct ath_hal *, u_int16_t); \ + _t AR5K_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, const AR5K_KEYVAL *, \ + const u_int8_t *, int); \ + _t AR5K_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, u_int16_t, const u_int8_t *); \ + /* Power Management Functions */ \ + _t AR5K_BOOL (_a _n##_set_power)(struct ath_hal*, AR5K_POWER_MODE mode, \ + AR5K_BOOL set_chip, u_int16_t sleep_duration); \ + _t AR5K_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \ + _t AR5K_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, u_int16_t); \ + _t AR5K_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \ + /* Beacon Management Functions */ \ + _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, u_int32_t intval); \ + _t void (_a _n##_set_beacon_timers)(struct ath_hal *, const AR5K_BEACON_STATE *); \ + _t void (_a _n##_reset_beacon)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, AR5K_BUS_ADDR); \ + /* Interrupt functions */ \ + _t AR5K_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_get_isr)(struct ath_hal *, u_int32_t *); \ + _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \ + _t AR5K_INT (_a _n##_set_intr)(struct ath_hal *, AR5K_INT); \ + /* Chipset functions (ar5k-specific, non-HAL) */ \ + _t AR5K_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \ + _t void (_a _n##_radar_alert)(struct ath_hal *, AR5K_BOOL enable); \ + _t AR5K_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \ + _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, u_int16_t *data); \ + _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, u_int16_t data); \ + /* Functions not found in OpenBSD */ \ + _t AR5K_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, AR5K_TXQ_INFO *); \ + _t AR5K_STATUS (_a _n##_get_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, \ + u_int32_t, u_int32_t *); \ + _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ + _t AR5K_BOOL (_a _n##_phy_disable)(struct ath_hal *); \ + _t void (_a _n##_set_pcu_config)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ + _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \ + _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \ + _t AR5K_BOOL (_a _n ##_set_bssid_mask)(struct ath_hal *, const u_int8_t*); \ + /*Totaly unimplemented*/ \ + _t AR5K_BOOL (_a _n##_set_capability)(struct ath_hal *, AR5K_CAPABILITY_TYPE, u_int32_t,\ + u_int32_t,AR5K_STATUS *) ; \ + _t void (_a _n##_proc_mib_event)(struct ath_hal *, const AR5K_NODE_STATS *) ; \ + _t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *); + + +#define AR5K_MAX_GPIO 10 +#define AR5K_MAX_RF_BANKS 8 + +struct ath_hal { + u_int32_t ah_magic; + u_int16_t ah_device; + u_int16_t ah_sub_vendor; + + AR5K_SOFTC ah_sc; + bus_space_tag_t ah_st; + bus_space_handle_t ah_sh; + AR5K_CTRY_CODE ah_country_code; + + AR5K_INT ah_imr; + + AR5K_OPMODE ah_op_mode; + AR5K_POWER_MODE ah_power_mode; + AR5K_CHANNEL ah_current_channel; + AR5K_BOOL ah_turbo; + AR5K_BOOL ah_calibration; + AR5K_BOOL ah_running; + AR5K_BOOL ah_single_chip; + AR5K_RFGAIN ah_rf_gain; + + AR5K_RATE_TABLE ah_rt_11a; + AR5K_RATE_TABLE ah_rt_11b; + AR5K_RATE_TABLE ah_rt_11g; + AR5K_RATE_TABLE ah_rt_turbo; + AR5K_RATE_TABLE ah_rt_xr; + + u_int32_t ah_mac_srev; + u_int16_t ah_mac_version; + u_int16_t ah_mac_revision; + u_int16_t ah_phy_revision; + u_int16_t ah_radio_5ghz_revision; + u_int16_t ah_radio_2ghz_revision; + + enum ath5k_version ah_version; + enum ath5k_radio ah_radio; + u_int32_t ah_phy; + + AR5K_BOOL ah_5ghz; + AR5K_BOOL ah_2ghz; + +#define ah_regdomain ah_capabilities.cap_regdomain.reg_current +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_modes ah_capabilities.cap_mode +#define ah_ee_version ah_capabilities.cap_eeprom.ee_version + + u_int32_t ah_atim_window; + u_int32_t ah_aifs; + u_int32_t ah_cw_min; + u_int32_t ah_cw_max; + AR5K_BOOL ah_software_retry; + u_int32_t ah_limit_tx_retries; + + u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + AR5K_BOOL ah_ant_diversity; + + u_int8_t ah_sta_id[IEEE80211_ADDR_LEN]; + u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; + + u_int32_t ah_gpio[AR5K_MAX_GPIO]; + int ah_gpio_npins; + + ath5k_capabilities_t ah_capabilities; + + AR5K_TXQ_INFO ah_txq[AR5K_NUM_TX_QUEUES]; + u_int32_t ah_txq_interrupts; + + u_int32_t *ah_rf_banks; + size_t ah_rf_banks_size; + struct ath5k_gain ah_gain; + u_int32_t ah_offset[AR5K_MAX_RF_BANKS]; + + struct { + u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; + u_int16_t txp_rates[AR5K_MAX_RATES]; + int16_t txp_min, txp_max; + AR5K_BOOL txp_tpc; + int16_t txp_ofdm; + } ah_txpower; + + struct { + AR5K_BOOL r_enabled; + int r_last_alert; + AR5K_CHANNEL r_last_channel; + } ah_radar; + + /* + * Function pointers + */ + AR5K_HAL_FUNCTIONS(, ah, *) + +}; + +/* + * Prototypes + */ + +const char *ath_hal_probe(u_int16_t, u_int16_t); +struct ath_hal *ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG, + AR5K_BUS_HANDLE, AR5K_STATUS *); +u_int16_t ath_hal_computetxtime(struct ath_hal *, const AR5K_RATE_TABLE *, + u_int32_t, u_int16_t, AR5K_BOOL); +u_int ath_hal_mhz2ieee(u_int, u_int); +u_int ath_hal_ieee2mhz(u_int, u_int); +AR5K_BOOL ath_hal_init_channels(struct ath_hal *, AR5K_CHANNEL *, + u_int, u_int *, AR5K_CTRY_CODE, u_int16_t, + AR5K_BOOL, AR5K_BOOL); +const char *ath5k_printver(enum ath5k_srev_type, u_int32_t); +void ath5k_radar_alert(struct ath_hal *); +ieee80211_regdomain_t ath5k_regdomain_to_ieee(u_int16_t); +u_int16_t ath5k_regdomain_from_ieee(ieee80211_regdomain_t); +u_int16_t ath5k_get_regdomain(struct ath_hal *); +u_int32_t ath5k_bitswap(u_int32_t, u_int); +inline u_int ath5k_clocktoh(u_int, AR5K_BOOL); +inline u_int ath5k_htoclock(u_int, AR5K_BOOL); +void ath5k_rt_copy(AR5K_RATE_TABLE *, const AR5K_RATE_TABLE *); +AR5K_BOOL ath5k_register_timeout(struct ath_hal *, u_int32_t, u_int32_t, + u_int32_t, AR5K_BOOL); +int ath5k_eeprom_init(struct ath_hal *); +int ath5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); +AR5K_BOOL ath5k_eeprom_regulation_domain(struct ath_hal *, AR5K_BOOL, + ieee80211_regdomain_t *); +int ath5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); +int ath5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); +u_int16_t ath5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); + +AR5K_BOOL ath5k_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ath5k_ar5110_channel(struct ath_hal *, AR5K_CHANNEL *); +u_int32_t ath5k_ar5110_chan2athchan(AR5K_CHANNEL *); +AR5K_BOOL ath5k_ar5111_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ath5k_ar5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); +AR5K_BOOL ath5k_ar5112_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ath5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); + +AR5K_BOOL ath5k_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +AR5K_BOOL ath5k_ar5111_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +AR5K_BOOL ath5k_ar5112_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +void ath5k_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int, u_int); +u_int ath5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, + u_int32_t, u_int32_t, AR5K_BOOL); +u_int32_t ath5k_rfregs_gainf_corr(struct ath_hal *); +AR5K_BOOL ath5k_rfregs_gain_readback(struct ath_hal *); +int32_t ath5k_rfregs_gain_adjust(struct ath_hal *); +AR5K_BOOL ath5k_rfgain(struct ath_hal *, u_int, u_int); +void ath5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); + +/*added*/ +extern u_int ath_hal_getwirelessmodes(struct ath_hal*, AR5K_CTRY_CODE); +void ath_hal_detach(struct ath_hal *ah); +struct ath_hal * _ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, AR5K_BUS_TAG t, + AR5K_BUS_HANDLE h, void* s); +#endif /* _AR5K_H */ Index: ah_osdep.c =================================================================== --- ah_osdep.c (revision 2185) +++ ah_osdep.c (revision 2232) @@ -41,7 +41,7 @@ MODULE_AUTHOR("Nick Kossifidis"); MODULE_DESCRIPTION("OpenHAL"); -MODULE_SUPPORTED_DEVICE(""); +MODULE_SUPPORTED_DEVICE("Atheros AR5xxx WLAN cards"); #ifdef MODULE_LICENSE MODULE_LICENSE("Dual BSD/GPL"); #endif @@ -53,7 +53,7 @@ AR5K_BUS_TAG t, AR5K_BUS_HANDLE h, void* s) { AR5K_STATUS status; - struct ath_hal *ah = ath_hal_attach(devid, sc, t, h, &status); + struct ath_hal *ah = ath5k_hw_init(devid, sc, t, h, &status); *(AR5K_STATUS *)s = status; if (ah) Index: ah_osdep.h =================================================================== --- ah_osdep.h (revision 2185) +++ ah_osdep.h (revision 2232) @@ -74,8 +74,8 @@ #define bcopy(_a, _b, _c) memcpy(_b, _a, _c) #define bzero(_a, _b) memset(_a, 0, _b) -#define AR5K_REG_WRITE(_reg, _val) (writel(_val, hal->ah_sh + (_reg))) +//#define AR5K_REG_WRITE(_reg, _val) (writel(_val, hal->ah_sh + (_reg))) // bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val)) -#define AR5K_REG_READ(_reg) (readl(hal->ah_sh + (_reg))) +//#define AR5K_REG_READ(_reg) (readl(hal->ah_sh + (_reg))) // bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg)) Index: ieee80211_regdomain.c =================================================================== --- ieee80211_regdomain.c (revision 2185) +++ ieee80211_regdomain.c (revision 2232) @@ -20,7 +20,7 @@ * Basic regulation domain extensions for the IEEE 802.11 stack */ -#include "ar5xxx.h" +#include "ah_osdep.h" #include "ieee80211_regdomain.h" Index: Makefile =================================================================== --- Makefile (revision 2185) +++ Makefile (revision 2232) @@ -5,7 +5,7 @@ TOP = $(obj)/.. obj-m += ath_hal.o -ath_hal-objs := ah_osdep.o ar5xxx.o ar5212.o ar5211.o ar5210.o ieee80211_regdomain.o +ath_hal-objs := ah_osdep.o ath5k_hw.o ieee80211_regdomain.o include $(TOP)/Makefile.inc Index: ah.h =================================================================== --- ah.h (revision 2185) +++ ah.h (revision 2232) @@ -1,6 +1 @@ -#ifndef _AR5K_AH_H -#define _AR5K_AH_H - -#include "ar5xxx.h" - -#endif +#include "ath5k.h"