Index: translation.h =================================================================== --- translation.h (revision 2284) +++ translation.h (revision 2363) @@ -31,7 +31,7 @@ */ //reset //set_opmode -#define ah_perCalibration ah_calibrate +#define ah_perCalibration ah_phy_calibrate #define ah_phyDisable ah_phy_disable /* Index: ath5k_hw.c =================================================================== --- ath5k_hw.c (revision 2284) +++ ath5k_hw.c (revision 2363) @@ -76,7 +76,7 @@ /*Prototypes*/ AR5K_BOOL ath5k_hw_nic_reset(struct ath_hal *, u_int32_t); -AR5K_BOOL ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t); +AR5K_BOOL ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t, AR5K_BOOL); u_int16_t ath5k_hw_radio_revision(struct ath_hal *, AR5K_CHIP); void ath5k_hw_fill(struct ath_hal *); AR5K_BOOL ath5k_hw_txpower(struct ath_hal *, AR5K_CHANNEL *, u_int); @@ -99,19 +99,20 @@ static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI; static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE; static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF; +static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI; /* * Initial gain optimization values */ -static const struct ath5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT; -static const struct ath5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT; +static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT; +static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT; /* * Initial register for the radio chipsets */ -static const struct ath5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF; -static const struct ath5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF; -static const struct ath5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF; +static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF; +static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF; +static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF; static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; /* @@ -441,7 +442,7 @@ ath5k_hw_fill(hal); /* Bring device out of sleep and reset it's units */ - if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE) != TRUE) + if (ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, TRUE) != TRUE) goto failed; /* Get MAC, PHY and RADIO revisions */ @@ -453,16 +454,25 @@ 0x00ffffffff; hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal, AR5K_CHIP_5GHZ); - hal->ah_radio_2ghz_revision = - ath5k_hw_radio_revision(hal, AR5K_CHIP_2GHZ); + if(hal->ah_version == AR5K_AR5210){ + hal->ah_radio_2ghz_revision = 0; + } else { + hal->ah_radio_2ghz_revision = + ath5k_hw_radio_revision(hal, AR5K_CHIP_2GHZ); + } + /* Single chip radio */ if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) hal->ah_radio_2ghz_revision = 0; /* Identify the radio chip*/ - hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ? - AR5K_AR5111 : AR5K_AR5112; + if(hal->ah_version == AR5K_AR5210){ + hal->ah_radio = AR5K_RF5110; + } else { + hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ? + AR5K_RF5111 : AR5K_RF5112; + } hal->ah_phy = AR5K_PHY(0); @@ -519,18 +529,18 @@ /* Initialize the gain optimization values */ /*For RF5111*/ - if (hal->ah_radio == AR5K_AR5111) { - hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default; + if (hal->ah_radio == AR5K_RF5111) { + hal->ah_gain.g_step_idx = rf5111_gain_opt.go_default; hal->ah_gain.g_step = - &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; + &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; hal->ah_gain.g_low = 20; hal->ah_gain.g_high = 35; hal->ah_gain.g_active = 1; /*For RF5112*/ - } else if (hal->ah_radio == AR5K_AR5112) { - hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default; + } else if (hal->ah_radio == AR5K_RF5112) { + hal->ah_gain.g_step_idx = rf5112_gain_opt.go_default; hal->ah_gain.g_step = - &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; + &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; hal->ah_gain.g_low = 20; hal->ah_gain.g_high = 85; hal->ah_gain.g_active = 1; @@ -549,7 +559,7 @@ * Bring up MAC + PHY Chips */ AR5K_BOOL -ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags) +ath5k_hw_nic_wakeup(struct ath_hal *hal, u_int16_t flags, AR5K_BOOL initial) { u_int32_t turbo, mode, clock; @@ -559,65 +569,102 @@ AR5K_TRACE; - /* - * Get channel mode flags - */ + if (hal->ah_version != AR5K_AR5210){ + /* + * Get channel mode flags + */ - if (hal->ah_radio >= AR5K_AR5112) { - mode = AR5K_PHY_MODE_RAD_AR5112; - clock = AR5K_PHY_PLL_AR5112; - } else { - mode = AR5K_PHY_MODE_RAD_AR5111; /*Zero -backwards combatible*/ - clock = AR5K_PHY_PLL_AR5111; /*Zero -backwards combatible*/ - } + if (hal->ah_radio >= AR5K_RF5112) { + mode = AR5K_PHY_MODE_RAD_RF5112; + clock = AR5K_PHY_PLL_RF5112; + } else { + mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ + clock = AR5K_PHY_PLL_RF5111; /*Zero*/ + } - if (flags & CHANNEL_2GHZ) { - mode |= AR5K_PHY_MODE_FREQ_2GHZ; - clock |= AR5K_PHY_PLL_44MHZ; - } else if (flags & CHANNEL_5GHZ) { - mode |= AR5K_PHY_MODE_FREQ_5GHZ; - clock |= AR5K_PHY_PLL_40MHZ; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); - } + if (flags & CHANNEL_2GHZ) { + mode |= AR5K_PHY_MODE_FREQ_2GHZ; + clock |= AR5K_PHY_PLL_44MHZ; + } else if (flags & CHANNEL_5GHZ) { + mode |= AR5K_PHY_MODE_FREQ_5GHZ; + clock |= AR5K_PHY_PLL_40MHZ; + } else { + AR5K_PRINT("invalid radio frequency mode\n"); + return (FALSE); + } - if (flags & CHANNEL_CCK) { - mode |= AR5K_PHY_MODE_MOD_CCK; - } else if (flags & CHANNEL_OFDM) { - mode |= AR5K_PHY_MODE_MOD_OFDM; - } else if (flags & CHANNEL_DYN) { - /* Dynamic OFDM/CCK is not supported by the AR5211 */ - if (hal->ah_version == AR5K_AR5211){ + if (flags & CHANNEL_CCK) { mode |= AR5K_PHY_MODE_MOD_CCK; - }else{ - mode |= AR5K_PHY_MODE_MOD_DYN; + } else if (flags & CHANNEL_OFDM) { + mode |= AR5K_PHY_MODE_MOD_OFDM; + } else if (flags & CHANNEL_DYN) { + /* Dynamic OFDM/CCK is not supported by the AR5211 */ + if (hal->ah_version == AR5K_AR5211){ + mode |= AR5K_PHY_MODE_MOD_CCK; + }else{ + mode |= AR5K_PHY_MODE_MOD_DYN; + } + } else { + AR5K_PRINT("invalid radio frequency mode\n"); + return (FALSE); } - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); - } - if (flags & CHANNEL_TURBO) { - turbo = AR5K_PHY_TURBO_MODE | - AR5K_PHY_TURBO_SHORT; + if (flags & CHANNEL_TURBO) { + turbo = AR5K_PHY_TURBO_MODE | + AR5K_PHY_TURBO_SHORT; + } } /* * Reset and wakeup the device */ + else { + if(initial == TRUE){ + /* ...reset hardware */ + if (ath5k_hw_nic_reset(hal, + AR5K_RESET_CTL_PCI) == FALSE) { + AR5K_PRINT("failed to reset the PCI chipset\n"); + return (FALSE); + } + + AR5K_DELAY(1000); + } + + /* ...wakeup */ + if (ath5k_hw_set_power(hal, + AR5K_PM_AWAKE, TRUE, 0) == FALSE) { + AR5K_PRINT("failed to resume the MAC Chip\n"); + return (FALSE); + } + + /* ...enable Atheros turbo mode if requested */ + if (flags & CHANNEL_TURBO) + AR5K_REG_WRITE(AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE); + + /* ...reset chipset */ + if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP) == FALSE) { + AR5K_PRINT("failed to reset the AR5210 chipset\n"); + return (FALSE); + } + + AR5K_DELAY(1000); + } + /* ...reset chipset and PCI device */ if (hal->ah_single_chip == FALSE && ath5k_hw_nic_reset(hal,AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI) == FALSE) { - AR5K_PRINT("failed to reset the MAC + PCI Chipset\n"); + AR5K_PRINT("failed to reset the MAC Chip + PCI\n"); return (FALSE); } + if (hal->ah_version == AR5K_AR5210) + AR5K_DELAY(2300); + /* ...wakeup */ if (ath5k_hw_set_power(hal, AR5K_PM_AWAKE, TRUE, 0) == FALSE) { - AR5K_PRINT("failed to resume the MAC Chip (again)\n"); + AR5K_PRINT("failed to resume the MAC Chip\n"); return (FALSE); } @@ -627,12 +674,14 @@ return (FALSE); } - /* ...set the PHY operating mode */ - AR5K_REG_WRITE(AR5K_PHY_PLL, clock); - AR5K_DELAY(300); + if (hal->ah_version != AR5K_AR5210){ + /* ...set the PHY operating mode */ + AR5K_REG_WRITE(AR5K_PHY_PLL, clock); + AR5K_DELAY(300); - AR5K_REG_WRITE(AR5K_PHY_MODE, mode); - AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); + AR5K_REG_WRITE(AR5K_PHY_MODE, mode); + AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); + } return (TRUE); } @@ -670,10 +719,17 @@ for (i = 0; i < 8; i++) AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000); - srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff; - ret = ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + if(hal->ah_version == AR5K_AR5210){ + srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf; + ret = (u_int16_t) ath5k_hw_bitswap(srev, 4) + 1; + } else { + srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff; + + ret = (u_int16_t) ath5k_hw_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); + } + /* Reset to the 5GHz mode */ AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); @@ -682,6 +738,7 @@ /* * Get the rate table for a specific operation mode + * TODO:Limit this per chipset */ const AR5K_RATE_TABLE * ath5k_hw_get_rate_table(struct ath_hal *hal, u_int mode) @@ -740,25 +797,31 @@ { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int8_t mac[IEEE80211_ADDR_LEN]; - u_int32_t data, s_seq, s_ant, s_led[3]; + u_int32_t data, noise_floor, s_seq, s_ant, s_led[3]; u_int i, phy, mode, freq, off, ee_mode, ant[2]; const AR5K_RATE_TABLE *rt; AR5K_TRACE; *status = AR5K_OK; + s_seq = 0; + s_ant = 1; + ee_mode = 0; + freq = 0; + mode = 0; + phy = 0; /* * Save some registers before a reset */ - if (change_channel == TRUE) { - /*Sequence number for queue 0 -do this for all queues ?*/ - s_seq = AR5K_REG_READ(AR5K_QUEUE_DFS_SEQNUM(0)); - /*Default antenna*/ - s_ant = AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); - } else { - s_seq = 0; - s_ant = 1; + /*DCU/Antenna selection not available on 5210*/ + if(hal->ah_version != AR5K_AR5210){ + if (change_channel == TRUE) { + /*Sequence number for queue 0 -do this for all queues ?*/ + s_seq = AR5K_REG_READ(AR5K_QUEUE_DFS_SEQNUM(0)); + /*Default antenna*/ + s_ant = AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + } } /*GPIOs*/ @@ -769,7 +832,9 @@ if (change_channel == TRUE && hal->ah_rf_banks != NULL) ath5k_hw_get_rf_gain(hal); - if (ath5k_hw_nic_wakeup(hal, channel->channel_flags) == FALSE) { + + /*Wakeup the device*/ + if (ath5k_hw_nic_wakeup(hal, channel->channel_flags, FALSE) == FALSE) { *status = AR5K_EIO; return (FALSE); } @@ -779,72 +844,78 @@ */ hal->ah_op_mode = op_mode; - if (hal->ah_radio == AR5K_AR5111) { - phy = AR5K_INI_PHY_5111; - } else if (hal->ah_radio == AR5K_AR5112) { - phy = AR5K_INI_PHY_5112; - } else { - AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); - *status = AR5K_EINVAL; - return (FALSE); - } + /* + * 5111/5112 Settings + * 5210 only comes with RF5110 + */ + if(hal->ah_version != AR5K_AR5210){ + if (hal->ah_radio == AR5K_RF5111) { + phy = AR5K_INI_PHY_5111; + } else if (hal->ah_radio == AR5K_RF5112) { + phy = AR5K_INI_PHY_5112; + } else { + AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); + *status = AR5K_EINVAL; + return (FALSE); + } - switch (channel->channel_flags & CHANNEL_MODES) { - case CHANNEL_A: - mode = AR5K_INI_VAL_11A; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - case CHANNEL_B: - mode = AR5K_INI_VAL_11B; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11B; - break; - case CHANNEL_G: - mode = AR5K_INI_VAL_11G; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11G; - break; - case CHANNEL_T: - mode = AR5K_INI_VAL_11A_TURBO; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - /*Is this ok on 5211 too ?*/ - case CHANNEL_TG: - mode = AR5K_INI_VAL_11G_TURBO; - freq = AR5K_INI_RFGAIN_2GHZ; - ee_mode = AR5K_EEPROM_MODE_11G; - break; - case CHANNEL_XR: - if(hal->ah_version == AR5K_AR5211){ - AR5K_PRINTF("XR mode not available on 5211"); + switch (channel->channel_flags & CHANNEL_MODES) { + case CHANNEL_A: + mode = AR5K_INI_VAL_11A; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + case CHANNEL_B: + mode = AR5K_INI_VAL_11B; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11B; + break; + case CHANNEL_G: + mode = AR5K_INI_VAL_11G; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_T: + mode = AR5K_INI_VAL_11A_TURBO; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + /*Is this ok on 5211 too ?*/ + case CHANNEL_TG: + mode = AR5K_INI_VAL_11G_TURBO; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_XR: + if(hal->ah_version == AR5K_AR5211){ + AR5K_PRINTF("XR mode not available on 5211"); + return (FALSE); + } + mode = AR5K_INI_VAL_XR; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + default: + AR5K_PRINTF("invalid channel: %d\n", channel->freq); + *status = AR5K_EINVAL; return (FALSE); } - mode = AR5K_INI_VAL_XR; - freq = AR5K_INI_RFGAIN_5GHZ; - ee_mode = AR5K_EEPROM_MODE_11A; - break; - default: - AR5K_PRINTF("invalid channel: %d\n", channel->freq); - *status = AR5K_EINVAL; - return (FALSE); - } - /* PHY access enable */ - AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); + /* PHY access enable */ + AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); - /* - * Write initial RF registers on 5211 - * do we need that ? Is ath5k_rfregs going to work for 5211 (5111) ? - */ - if(hal->ah_version == AR5K_AR5211){ - ath5k_ar5211_rfregs(hal, channel, freq, ee_mode); + /* + * Write initial RF registers on 5211 + * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ? + */ + if(hal->ah_version == AR5K_AR5211){ + ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode); + } } /* * Write initial mode settings - * TODO:Clean/merge arrays + * TODO:Do this in a common way */ /*For 5212*/ if(hal->ah_version == AR5K_AR5212){ @@ -852,10 +923,10 @@ if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) off = AR5K_INI_PHY_511X; else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && - hal->ah_radio == AR5K_AR5111) + hal->ah_radio == AR5K_RF5111) off = AR5K_INI_PHY_5111; else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 && - hal->ah_radio == AR5K_AR5112) + hal->ah_radio == AR5K_RF5112) off = AR5K_INI_PHY_5112; else continue; @@ -876,7 +947,7 @@ /* * Write initial register settings - * TODO:Clean/merge arrays + * TODO:Do this in a common way */ /*For 5212*/ if(hal->ah_version == AR5K_AR5212){ @@ -886,9 +957,9 @@ ar5212_ini[i].ini_register <= AR5K_PCU_MAX) continue; - if ((hal->ah_radio == AR5K_AR5111 && + if ((hal->ah_radio == AR5K_RF5111 && ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) || - (hal->ah_radio == AR5K_AR5112 && + (hal->ah_radio == AR5K_RF5112 && ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { AR5K_REG_WAIT(i); AR5K_REG_WRITE((u_int32_t)ar5212_ini[i].ini_register, @@ -909,195 +980,229 @@ ar5211_ini[i].ini_value); } } + /*For 5210*/ + if(hal->ah_version == AR5K_AR5210) + for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) { + if (change_channel == TRUE && + ar5210_ini[i].ini_register >= AR5K_PCU_MIN && + ar5210_ini[i].ini_register <= AR5K_PCU_MAX) + continue; + switch (ar5210_ini[i].ini_mode) { + case AR5K_INI_READ: + /* Cleared on read */ + AR5K_REG_READ(ar5210_ini[i].ini_register); + break; + + case AR5K_INI_WRITE: + default: + AR5K_REG_WRITE(ar5210_ini[i].ini_register, + ar5210_ini[i].ini_value); + } + } + /* - * Write initial RF gain settings - * This should work for all chipsets + * 5211/5212 Specific */ - if (ath5k_rfgain(hal, phy, freq) == FALSE) { - *status = AR5K_EIO; - return (FALSE); - } + if(hal->ah_version != AR5K_AR5210){ + /* + * Write initial RF gain settings + * This should work for both 5111/5112 + */ + if (ath5k_hw_rfgain(hal, phy, freq) == FALSE) { + *status = AR5K_EIO; + return (FALSE); + } - AR5K_DELAY(1000); + AR5K_DELAY(1000); - /* - * Set rate duration table on 5212 - */ - if(hal->ah_version == AR5K_AR5212){ + /* + * Set rate duration table on 5212 + */ + if(hal->ah_version == AR5K_AR5212){ - /*For 802.11b*/ - if (!(channel->channel_flags & CHANNEL_B)) { + /*For 802.11b*/ + if (!(channel->channel_flags & CHANNEL_B)) { - /*Get rate table for this operation mode*/ - rt = ath5k_hw_get_rate_table(hal, AR5K_MODE_11B); + /*Get rate table for this operation mode*/ + rt = ath5k_hw_get_rate_table(hal, AR5K_MODE_11B); - /*Write rate duration table*/ - for (i = 0; i < rt->rate_count; i++) { - data = AR5K_RATE_DUR(rt->rates[i].rate_code); - AR5K_REG_WRITE(data, - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); - if (HAS_SHPREAMBLE(i)) { - AR5K_REG_WRITE(data + - (AR5K_SET_SHORT_PREAMBLE << 2), + /*Write rate duration table*/ + for (i = 0; i < rt->rate_count; i++) { + data = AR5K_RATE_DUR(rt->rates[i].rate_code); + AR5K_REG_WRITE(data, ath_hal_computetxtime(hal, rt, 14, rt->rates[i].control_rate, FALSE)); + if (HAS_SHPREAMBLE(i)) { + AR5K_REG_WRITE(data + + (AR5K_SET_SHORT_PREAMBLE << 2), + ath_hal_computetxtime(hal, rt, 14, + rt->rates[i].control_rate, FALSE)); + } } - } + + } else { + /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ - } else { - /*For 802.11a/g Turbo/XR mode (AR5K_MODE_XR here is O.K. for both a/g - OFDM)*/ + /*Get rate table for this operation mode*/ + rt = ath5k_hw_get_rate_table(hal, + channel->channel_flags & CHANNEL_TURBO ? + AR5K_MODE_TURBO : AR5K_MODE_XR); - /*Get rate table for this operation mode*/ - rt = ath5k_hw_get_rate_table(hal, - channel->channel_flags & CHANNEL_TURBO ? - AR5K_MODE_TURBO : AR5K_MODE_XR); + /*Write rate duration table*/ + for (i = 0; i < rt->rate_count; i++) { + AR5K_REG_WRITE(AR5K_RATE_DUR(rt->rates[i].rate_code), + ath_hal_computetxtime(hal, rt, 14, + rt->rates[i].control_rate, FALSE)); + } - /*Write rate duration table*/ - for (i = 0; i < rt->rate_count; i++) { - AR5K_REG_WRITE(AR5K_RATE_DUR(rt->rates[i].rate_code), - ath_hal_computetxtime(hal, rt, 14, - rt->rates[i].control_rate, FALSE)); } + } + /* Fix for first revision of the RF5112 RF chipset */ + if (hal->ah_radio >= AR5K_RF5112 && + hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { + AR5K_REG_WRITE(AR5K_PHY_CCKTXCTL, + AR5K_PHY_CCKTXCTL_WORLD); + if (channel->channel_flags & CHANNEL_OFDM) + data = 0xffb81020; + else + data = 0xffb80d20; + AR5K_REG_WRITE(AR5K_PHY_FRAME_CTL, data); } - } - /* Fix for first revision of the AR5112 RF chipset */ - if (hal->ah_radio >= AR5K_AR5112 && - hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { - AR5K_REG_WRITE(AR5K_PHY_CCKTXCTL, - AR5K_PHY_CCKTXCTL_WORLD); - if (channel->channel_flags & CHANNEL_OFDM) - data = 0xffb81020; - else - data = 0xffb80d20; - AR5K_REG_WRITE(AR5K_PHY_FRAME_CTL, data); - } + /* + * Set TX power (XXX use txpower from net80211) + */ + if (ath5k_hw_txpower(hal, channel, + AR5K_TUNE_DEFAULT_TXPOWER) == FALSE) { + *status = AR5K_EIO; + return (FALSE); + } - /* - * Set TX power (XXX use txpower from net80211) - */ - if (ath5k_hw_txpower(hal, channel, - AR5K_TUNE_DEFAULT_TXPOWER) == FALSE) { - *status = AR5K_EIO; - return (FALSE); - } + /* + * Write RF registers + * TODO:Does this work on 5211 (5111) ? + */ + if (ath5k_hw_rfregs(hal, channel, mode) == FALSE) { + *status = AR5K_EINPROGRESS; + return (FALSE); + } - /* - * Write RF registers - * TODO:Does this work on 5211 (5111) ? - */ - if (ath5k_rfregs(hal, channel, mode) == FALSE) { - *status = AR5K_EINPROGRESS; - return (FALSE); - } + /* + * Configure additional registers + */ - /* - * Configure additional registers - */ + /* Write OFDM timings on 5212*/ + if(hal->ah_version == AR5K_AR5212){ + if (channel->channel_flags & CHANNEL_OFDM) { + u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, + ds_coef_man, clock; - /* Write OFDM timings on 5212*/ - if(hal->ah_version == AR5K_AR5212){ - if (channel->channel_flags & CHANNEL_OFDM) { - u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, - ds_coef_man, clock; + clock = channel->channel_flags & CHANNEL_T ? 80 : 40; + coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; - clock = channel->channel_flags & CHANNEL_T ? 80 : 40; - coef_scaled = ((5 * (clock << 24)) / 2) / channel->freq; + for (coef_exp = 31; coef_exp > 0; coef_exp--) + if ((coef_scaled >> coef_exp) & 0x1) + break; - for (coef_exp = 31; coef_exp > 0; coef_exp--) - if ((coef_scaled >> coef_exp) & 0x1) - break; + if (!coef_exp) { + *status = AR5K_EINVAL; + return (FALSE); + } - if (!coef_exp) { - *status = AR5K_EINVAL; - return (FALSE); + coef_exp = 14 - (coef_exp - 24); + coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); + ds_coef_man = coef_man >> (24 - coef_exp); + ds_coef_exp = coef_exp - 16; + + AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); + AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); } + } - coef_exp = 14 - (coef_exp - 24); - coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); - ds_coef_man = coef_man >> (24 - coef_exp); - ds_coef_exp = coef_exp - 16; - - AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, - AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); - AR5K_REG_WRITE_BITS(AR5K_PHY_TIMING_3, - AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); + /*Enable/disable 802.11b mode on 5111 + (enable 2111 frequency converter + CCK)*/ + if (hal->ah_radio == AR5K_RF5111) { + if (channel->channel_flags & CHANNEL_B) + AR5K_REG_ENABLE_BITS(AR5K_TXCFG, + AR5K_TXCFG_B_MODE); + else + AR5K_REG_DISABLE_BITS(AR5K_TXCFG, + AR5K_TXCFG_B_MODE); } - } - /*Enable/disable 802.11b mode on 5111 - (enable 2111 frequency converter + CCK)*/ - if (hal->ah_radio == AR5K_AR5111) { - if (channel->channel_flags & CHANNEL_B) - AR5K_REG_ENABLE_BITS(AR5K_TXCFG, - AR5K_TXCFG_B_MODE); - else - AR5K_REG_DISABLE_BITS(AR5K_TXCFG, - AR5K_TXCFG_B_MODE); - } + /* Set antenna mode */ + AR5K_REG_MASKED_BITS(AR5K_PHY(0x44), + hal->ah_antenna[ee_mode][0], 0xfffffc06); - /* Set antenna mode */ - AR5K_REG_MASKED_BITS(AR5K_PHY(0x44), - hal->ah_antenna[ee_mode][0], 0xfffffc06); + if (freq == AR5K_INI_RFGAIN_2GHZ) + ant[0] = ant[1] = AR5K_ANT_FIXED_B; + else + ant[0] = ant[1] = AR5K_ANT_FIXED_A; - if (freq == AR5K_INI_RFGAIN_2GHZ) - ant[0] = ant[1] = AR5K_ANT_FIXED_B; - else - ant[0] = ant[1] = AR5K_ANT_FIXED_A; + AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_0, + hal->ah_antenna[ee_mode][ant[0]]); + AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_1, + hal->ah_antenna[ee_mode][ant[1]]); - AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_0, - hal->ah_antenna[ee_mode][ant[0]]); - AR5K_REG_WRITE(AR5K_PHY_ANT_SWITCH_TABLE_1, - hal->ah_antenna[ee_mode][ant[1]]); + /* Commit values from EEPROM */ + if (hal->ah_radio == AR5K_RF5111) + AR5K_REG_WRITE_BITS(AR5K_PHY_FRAME_CTL, + AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); - /* Commit values from EEPROM */ - if (hal->ah_radio == AR5K_AR5111) - AR5K_REG_WRITE_BITS(AR5K_PHY_FRAME_CTL, - AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); + AR5K_REG_WRITE(AR5K_PHY(0x5a), + AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); - AR5K_REG_WRITE(AR5K_PHY(0x5a), - AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x11), + (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x12), + (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x14), + (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | + ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x11), - (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x12), - (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x14), - (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | - ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); + AR5K_REG_WRITE(AR5K_PHY(0x0d), + (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | + (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | + (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | + (ee->ee_tx_frm2xpa_enable[ee_mode])); - AR5K_REG_WRITE(AR5K_PHY(0x0d), - (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | - (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | - (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | - (ee->ee_tx_frm2xpa_enable[ee_mode])); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x0a), + ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x19), + (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); + AR5K_REG_MASKED_BITS(AR5K_PHY(0x49), 4, 0xffffff01); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x0a), - ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x19), - (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); - AR5K_REG_MASKED_BITS(AR5K_PHY(0x49), 4, 0xffffff01); + AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, + AR5K_PHY_IQ_CORR_ENABLE | + (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | + ee->ee_q_cal[ee_mode]); - AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, - AR5K_PHY_IQ_CORR_ENABLE | - (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | - ee->ee_q_cal[ee_mode]); + if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { + AR5K_REG_WRITE_BITS(AR5K_PHY_GAIN_2GHZ, + AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, + ee->ee_margin_tx_rx[ee_mode]); + } - if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { - AR5K_REG_WRITE_BITS(AR5K_PHY_GAIN_2GHZ, - AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, - ee->ee_margin_tx_rx[ee_mode]); + } else { + AR5K_DELAY(1000); + /* Disable phy and wait */ + AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); + AR5K_DELAY(1000); } /* * Restore saved values */ - AR5K_REG_WRITE(AR5K_QUEUE_DFS_SEQNUM(0), s_seq); - AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, s_ant); + /*DCU/Antenna selection not available on 5210*/ + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_QUEUE_DFS_SEQNUM(0), s_seq); + AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, s_ant); + } AR5K_REG_ENABLE_BITS(AR5K_PCICFG, s_led[0]); AR5K_REG_WRITE(AR5K_GPIOCR, s_led[1]); AR5K_REG_WRITE(AR5K_GPIODO, s_led[2]); @@ -1108,21 +1213,27 @@ bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); ath5k_hw_set_associd(hal, mac, 0); ath5k_hw_set_opmode(hal); - AR5K_REG_WRITE(AR5K_PISR, 0xffffffff); - AR5K_REG_WRITE(AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES); + /*PISR/SISR Not available on 5210*/ + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_PISR, 0xffffffff); + AR5K_REG_WRITE(AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES); + } /* * Set Rx/Tx DMA Configuration + *(passing dma size not available on 5210) */ - AR5K_REG_WRITE_BITS(AR5K_TXCFG, AR5K_TXCFG_SDMAMR, - AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); - AR5K_REG_WRITE_BITS(AR5K_RXCFG, AR5K_RXCFG_SDMAMW, - AR5K_DMASIZE_512B); + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_WRITE_BITS(AR5K_TXCFG, AR5K_TXCFG_SDMAMR, + AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); + AR5K_REG_WRITE_BITS(AR5K_RXCFG, AR5K_RXCFG_SDMAMW, + AR5K_DMASIZE_512B); + } /* * Set channel and calibrate the PHY */ - if (ath5k_channel(hal, channel) == FALSE) { + if (ath5k_hw_channel(hal, channel) == FALSE) { *status = AR5K_EIO; return (FALSE); } @@ -1132,20 +1243,64 @@ */ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); - data = AR5K_REG_READ(AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; - data = (channel->channel_flags & CHANNEL_CCK) ? - ((data << 2) / 22) : (data / 10); + /* + * 5111/5112 Specific + */ + if(hal->ah_version != AR5K_AR5210){ + data = AR5K_REG_READ(AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M; + data = (channel->channel_flags & CHANNEL_CCK) ? + ((data << 2) / 22) : (data / 10); - AR5K_DELAY(100 + data); + AR5K_DELAY(100 + data); + } else { + AR5K_DELAY(1000); + } /* - * Start calibration + * Enable calibration and wait until completion */ AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF | - AR5K_PHY_AGCCTL_CAL); + AR5K_PHY_AGCCTL_CAL); + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) { + AR5K_PRINTF("calibration timeout (%uMHz)\n", + channel->freq); + return (FALSE); + } + /* + * Enable noise floor calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF); + + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF, 0, FALSE) == FALSE) { + AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", + channel->freq); + return (FALSE); + } + + /* Wait until the noise floor is calibrated */ + for (i = 20; i > 0; i--) { + AR5K_DELAY(1000); + noise_floor = AR5K_REG_READ(AR5K_PHY_NF); + + if (AR5K_PHY_NF_RVAL(noise_floor) & + AR5K_PHY_NF_ACTIVE) + noise_floor = AR5K_PHY_NF_AVAL(noise_floor); + + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) + break; + } + + if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { + AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", + channel->freq); + return (FALSE); + } + hal->ah_calibration = FALSE; if (!(channel->channel_flags & CHANNEL_B)) { @@ -1160,7 +1315,10 @@ * Reset queues and start beacon timers at the end of the reset routine */ for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { - AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i); + /*No QCU on 5210*/ + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i); + } if (ath5k_hw_reset_tx_queue(hal, i) == FALSE) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); *status = AR5K_EINVAL; @@ -1168,8 +1326,10 @@ } } - /* Pre-enable interrupts */ - ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); + /* Pre-enable interrupts on 5211/5212*/ + if(hal->ah_version != AR5K_AR5210){ + ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL); + } /* * Set RF kill flags if supported by the device (read from the EEPROM) @@ -1194,8 +1354,8 @@ AR5K_REG_WRITE(AR5K_PHY_SCAL, AR5K_PHY_SCAL_32MHZ); AR5K_REG_WRITE(AR5K_PHY_SCLOCK, AR5K_PHY_SCLOCK_32MHZ); AR5K_REG_WRITE(AR5K_PHY_SDELAY, AR5K_PHY_SDELAY_32MHZ); - AR5K_REG_WRITE(AR5K_PHY_SPENDING, hal->ah_radio == AR5K_AR5111 ? - AR5K_PHY_SPENDING_AR5111 : AR5K_PHY_SPENDING_AR5112); + AR5K_REG_WRITE(AR5K_PHY_SPENDING, hal->ah_radio == AR5K_RF5111 ? + AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112); } /* @@ -1229,16 +1389,21 @@ /* Wait at least 128 PCI clocks */ AR5K_DELAY(15); - val &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + if(hal->ah_version == AR5K_AR5210){ + val &= AR5K_RESET_CTL_CHIP; + mask &= AR5K_RESET_CTL_CHIP; + } else { + val &= + AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; - mask &= - AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + mask &= + AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + } ret = ath5k_hw_register_timeout(hal, AR5K_RESET_CTL, mask, val, FALSE); /* - * Reset configuration register (for hw bitswap) + * Reset configuration register (for hw byte-swap) */ if ((val & AR5K_RESET_CTL_PCU) == 0) AR5K_REG_WRITE(AR5K_CFG, AR5K_INIT_CFG); @@ -1406,16 +1571,49 @@ AR5K_BOOL ath5k_hw_tx_start(struct ath_hal *hal, u_int queue) { + u_int32_t tx_queue; + AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - /* Return if queue is disabled */ - if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) - return (FALSE); + if(hal->ah_version == AR5K_AR5210){ - /* Start queue */ - AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); + tx_queue = AR5K_REG_READ(AR5K_CR); + /* + * Set the queue by type on 5210 + */ + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; + break; + case AR5K_TX_QUEUE_BEACON: + tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; + AR5K_REG_WRITE(AR5K_BSR, + AR5K_BCR_TQ1V | + AR5K_BCR_BDMAE); + break; + case AR5K_TX_QUEUE_CAB: + tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; + AR5K_REG_WRITE(AR5K_BSR, + AR5K_BCR_TQ1FV | + AR5K_BCR_TQ1V | + AR5K_BCR_BDMAE); + break; + default: + return (FALSE); + } + /* Start queue */ + AR5K_REG_WRITE(AR5K_CR, tx_queue); + } else { + /* Return if queue is disabled */ + if (AR5K_REG_READ_Q(AR5K_QCU_TXD, queue)) + return (FALSE); + + /* Start queue */ + AR5K_REG_WRITE_Q(AR5K_QCU_TXE, queue); + } + return (TRUE); } @@ -1427,25 +1625,50 @@ ath5k_hw_stop_tx_dma(struct ath_hal *hal, u_int queue) { int i = 100, pending; - + u_int32_t tx_queue; + AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - /* - * Schedule TX disable and wait until queue is empty - */ - AR5K_REG_WRITE_Q(AR5K_QCU_TXD, queue); + if(hal->ah_version == AR5K_AR5210){ + tx_queue = AR5K_REG_READ(AR5K_CR); - /*Check for pending frames*/ - do { - pending = AR5K_REG_READ(AR5K_QUEUE_STATUS(queue)) & - AR5K_QCU_STS_FRMPENDCNT; - AR5K_DELAY(100); - } while (--i && pending); + /* + * Set by queue type + */ + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + /* XXX Fix me... */ + tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; + AR5K_REG_WRITE(AR5K_BSR, 0); + break; + default: + return (FALSE); + } - /* Clear register */ - AR5K_REG_WRITE(AR5K_QCU_TXD, 0); + /* Stop queue */ + AR5K_REG_WRITE(AR5K_CR, tx_queue); + } else { + /* + * Schedule TX disable and wait until queue is empty + */ + AR5K_REG_WRITE_Q(AR5K_QCU_TXD, queue); + /*Check for pending frames*/ + do { + pending = AR5K_REG_READ(AR5K_QUEUE_STATUS(queue)) & + AR5K_QCU_STS_FRMPENDCNT; + AR5K_DELAY(100); + } while (--i && pending); + + /* Clear register */ + AR5K_REG_WRITE(AR5K_QCU_TXD, 0); + } + /*TODO: Check for success else return false*/ return (TRUE); } @@ -1457,13 +1680,31 @@ u_int32_t ath5k_hw_get_tx_buf(struct ath_hal *hal, u_int queue) { + u_int16_t tx_reg; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* * Get the transmit queue descriptor pointer from the selected queue */ - return (AR5K_REG_READ(AR5K_QUEUE_TXDP(queue))); + /*5210 doesn't have QCU*/ + if(hal->ah_version == AR5K_AR5210){ + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_reg = AR5K_NOQCU_TXDP0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + tx_reg = AR5K_NOQCU_TXDP1; + break; + default: + return (0xffffffff); + } + } else { + tx_reg = AR5K_QUEUE_TXDP(queue); + } + + return (AR5K_REG_READ(tx_reg)); } /* @@ -1473,18 +1714,41 @@ AR5K_BOOL ath5k_hw_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) { + u_int16_t tx_reg; AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); /* - * Set the transmit queue descriptor pointer for the selected queue - * (this won't work if the queue is still active) + * Set the transmit queue descriptor pointer register by type + * on 5210 */ - if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) - return (FALSE); + if(hal->ah_version == AR5K_AR5210){ + switch (hal->ah_txq[queue].tqi_type) { + case AR5K_TX_QUEUE_DATA: + tx_reg = AR5K_NOQCU_TXDP0; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + tx_reg = AR5K_NOQCU_TXDP1; + break; + default: + return (FALSE); + } + } else { + /* + * Set the transmit queue descriptor pointer for + * the selected queue on QCU for 5211+ + * (this won't work if the queue is still active) + */ + if (AR5K_REG_READ_Q(AR5K_QCU_TXE, queue)) + return (FALSE); - AR5K_REG_WRITE(AR5K_QUEUE_TXDP(queue), phys_addr); + tx_reg = AR5K_QUEUE_TXDP(queue); + } + /* Set descriptor pointer */ + AR5K_REG_WRITE(tx_reg, phys_addr); + return (TRUE); } @@ -1505,20 +1769,25 @@ /*TODO: Boundary check on trigger_level*/ trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_TXCFG), - AR5K_TXCFG_TXFULL); + AR5K_TXCFG_TXFULL); if (increase == FALSE) { if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) goto done; } else trigger_level += - ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); + ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); /* * Update trigger level on success */ - AR5K_REG_WRITE_BITS(AR5K_TXCFG, - AR5K_TXCFG_TXFULL, trigger_level); + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_TRIG_LVL, trigger_level); + } else { + AR5K_REG_WRITE_BITS(AR5K_TXCFG, + AR5K_TXCFG_TXFULL, trigger_level); + } + status = TRUE; done: @@ -1553,7 +1822,19 @@ u_int32_t data; AR5K_TRACE; + /* + * Read interrupt status from the Interrupt Status register + * on 5210 + */ + if(hal->ah_version == AR5K_AR5210){ + if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) { + *interrupt_mask = data; + return (FALSE); + } + } + + /* * Read interrupt status from the Read-And-Clear shadow register */ data = AR5K_REG_READ(AR5K_RAC_PISR); @@ -1572,13 +1853,15 @@ if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR)) *interrupt_mask |= AR5K_INT_TX; - /*HIU = Host Interface Unit (PCI etc)*/ - if (data & (AR5K_ISR_HIUERR)) - *interrupt_mask |= AR5K_INT_FATAL; + if(hal->ah_version != AR5K_AR5210){ + /*HIU = Host Interface Unit (PCI etc)*/ + if (data & (AR5K_ISR_HIUERR)) + *interrupt_mask |= AR5K_INT_FATAL; - /*Beacon Not Ready*/ - if (data & (AR5K_ISR_BNR)) - *interrupt_mask |= AR5K_INT_BNR; + /*Beacon Not Ready*/ + if (data & (AR5K_ISR_BNR)) + *interrupt_mask |= AR5K_INT_BNR; + } /* * Special interrupt handling (not caught by the driver) @@ -1587,6 +1870,16 @@ hal->ah_radar.r_enabled == TRUE) ath5k_radar_alert(hal); + /* + * XXX: BMISS interrupts may occur after association + * i found this on 5210 code but it needs testing + */ + //*interrupt_mask &= ~AR5K_INT_BMISS; + + /* + * In case we didn't handle anything, + * print the register value. + */ if (*interrupt_mask == 0) AR5K_PRINTF("0x%08x\n", data); @@ -1628,24 +1921,26 @@ if (new_mask & AR5K_INT_RX) int_mask |= - AR5K_IMR_RXOK | - AR5K_IMR_RXERR | - AR5K_IMR_RXORN | - AR5K_IMR_RXDESC; + AR5K_IMR_RXOK | + AR5K_IMR_RXERR | + AR5K_IMR_RXORN | + AR5K_IMR_RXDESC; if (new_mask & AR5K_INT_TX) int_mask |= - AR5K_IMR_TXOK | - AR5K_IMR_TXERR | - AR5K_IMR_TXDESC | - AR5K_IMR_TXURN; + AR5K_IMR_TXOK | + AR5K_IMR_TXERR | + AR5K_IMR_TXDESC | + AR5K_IMR_TXURN; - if (new_mask & AR5K_INT_FATAL) { - int_mask |= AR5K_IMR_HIUERR; - AR5K_REG_ENABLE_BITS(AR5K_SIMR2, - AR5K_SIMR2_MCABT | - AR5K_SIMR2_SSERR | - AR5K_SIMR2_DPERR); + if(hal->ah_version != AR5K_AR5210){ + if (new_mask & AR5K_INT_FATAL) { + int_mask |= AR5K_IMR_HIUERR; + AR5K_REG_ENABLE_BITS(AR5K_SIMR2, + AR5K_SIMR2_MCABT | + AR5K_SIMR2_SSERR | + AR5K_SIMR2_DPERR); + } } AR5K_REG_WRITE(AR5K_PIMR, int_mask); @@ -1674,17 +1969,31 @@ /*Disable interupts*/ AR5K_REG_WRITE(AR5K_IER, AR5K_IER_DISABLE); - /*Set AR5K_PHY_RADAR register*/ - if (enable == TRUE) { - AR5K_REG_WRITE(AR5K_PHY_RADAR, - AR5K_PHY_RADAR_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_PIMR, - AR5K_IMR_RXPHY); + /* + * Set the RXPHY interrupt to be able to detect + * possible radar activity. + */ + if(hal->ah_version == AR5K_AR5210){ + if (enable == TRUE) { + AR5K_REG_ENABLE_BITS(AR5K_IMR, + AR5K_IMR_RXPHY); + } else { + AR5K_REG_DISABLE_BITS(AR5K_IMR, + AR5K_IMR_RXPHY); + } } else { - AR5K_REG_WRITE(AR5K_PHY_RADAR, - AR5K_PHY_RADAR_DISABLE); - AR5K_REG_DISABLE_BITS(AR5K_PIMR, - AR5K_IMR_RXPHY); + /*Also set AR5K_PHY_RADAR register on 5111/5112*/ + if (enable == TRUE) { + AR5K_REG_WRITE(AR5K_PHY_RADAR, + AR5K_PHY_RADAR_ENABLE); + AR5K_REG_ENABLE_BITS(AR5K_PIMR, + AR5K_IMR_RXPHY); + } else { + AR5K_REG_WRITE(AR5K_PHY_RADAR, + AR5K_PHY_RADAR_DISABLE); + AR5K_REG_DISABLE_BITS(AR5K_PIMR, + AR5K_IMR_RXPHY); + } } /*Re-enable interrupts*/ @@ -1706,7 +2015,7 @@ { AR5K_TRACE; return (AR5K_REG_READ(AR5K_CFG) & AR5K_CFG_EEBS ? - TRUE : FALSE); + TRUE : FALSE); } /* @@ -1715,17 +2024,22 @@ int ath5k_hw_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) { - u_int32_t status, i; + u_int32_t status, timeout; AR5K_TRACE; /* * Initialize EEPROM access */ - AR5K_REG_WRITE(AR5K_EEPROM_BASE, (u_int8_t)offset); - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, - AR5K_EEPROM_CMD_READ); + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE); + (void)AR5K_REG_READ(AR5K_EEPROM_BASE + (4 * offset)); + } else { + AR5K_REG_WRITE(AR5K_EEPROM_BASE, (u_int8_t)offset); + AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_READ); + } - for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { + for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_RDDONE) { if (status & AR5K_EEPROM_STAT_RDERR) @@ -1746,45 +2060,48 @@ int ath5k_hw_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) { +#if 0 u_int32_t status, timeout; AR5K_TRACE; - /* Enable eeprom access */ - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, - AR5K_EEPROM_CMD_RESET); /* + * Initialize eeprom access + */ + + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE); + } else { + AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_RESET); + } + + /* * Write data to data register - * Disable this, it's not needed for - * normal operation, uncomment it if you - * need it. */ - /* - AR5K_REG_WRITE(AR5K_EEPROM_DATA, data); - */ - AR5K_PRINTF("EEPROM Write is disabled!"); - /* Write offset to base register */ - AR5K_REG_WRITE(AR5K_EEPROM_BASE, (u_int8_t)offset - 1); + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_EEPROM_BASE + (4 * offset), data); + } else { + AR5K_REG_WRITE(AR5K_EEPROM_BASE, (u_int8_t)offset - 1); + AR5K_REG_WRITE(AR5K_EEPROM_DATA, data); + AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, AR5K_EEPROM_CMD_WRITE); + } - /* Issue write command */ - AR5K_REG_ENABLE_BITS(AR5K_EEPROM_CMD, - AR5K_EEPROM_CMD_WRITE); - /* * Check status */ - for (timeout = 10000; timeout > 0; timeout--) { - AR5K_DELAY(1); + for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { status = AR5K_REG_READ(AR5K_EEPROM_STATUS); if (status & AR5K_EEPROM_STAT_WRDONE) { if (status & AR5K_EEPROM_STAT_WRERR) return (EIO); return (0); } + AR5K_DELAY(15); } - +#endif + AR5K_PRINTF("EEPROM Write is disabled!"); return (ETIMEDOUT); } @@ -2253,47 +2570,65 @@ /* Capabilities stored in the EEPROM */ ee_header = hal->ah_capabilities.cap_eeprom.ee_header; - /* - * XXX The tranceiver supports frequencies from 4920 to 6100GHz - * XXX and from 2312 to 2732GHz. There are problems with the current - * XXX ieee80211 implementation because the IEEE channel mapping - * XXX does not support negative channel numbers (2312MHz is channel - * XXX -19). Of course, this doesn't matter because these channels - * XXX are out of range but some regulation domains like MKK (Japan) - * XXX will support frequencies somewhere around 4.8GHz. - */ + if(hal->ah_version == AR5K_AR5210){ + /* + * Set radio capabilities + * (The AR5110 only supports the middle 5GHz band) + */ + hal->ah_capabilities.cap_range.range_5ghz_min = 5120; + hal->ah_capabilities.cap_range.range_5ghz_max = 5430; + hal->ah_capabilities.cap_range.range_2ghz_min = 0; + hal->ah_capabilities.cap_range.range_2ghz_max = 0; - /* - * Set radio capabilities - */ - - if (AR5K_EEPROM_HDR_11A(ee_header)) { - hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ - hal->ah_capabilities.cap_range.range_5ghz_max = 6100; - /* Set supported modes */ - hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO | - (hal->ah_version == AR5K_AR5212 ? AR5K_MODE_XR : 0); - } + hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO; + } else { + /* + * XXX The tranceiver supports frequencies from 4920 to 6100GHz + * XXX and from 2312 to 2732GHz. There are problems with the current + * XXX ieee80211 implementation because the IEEE channel mapping + * XXX does not support negative channel numbers (2312MHz is channel + * XXX -19). Of course, this doesn't matter because these channels + * XXX are out of range but some regulation domains like MKK (Japan) + * XXX will support frequencies somewhere around 4.8GHz. + */ - /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ - if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { - hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ - hal->ah_capabilities.cap_range.range_2ghz_max = 2732; + /* + * Set radio capabilities + */ - if (AR5K_EEPROM_HDR_11B(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; + if (AR5K_EEPROM_HDR_11A(ee_header)) { + hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ + hal->ah_capabilities.cap_range.range_5ghz_max = 6100; + + /* Set supported modes */ + hal->ah_capabilities.cap_mode = AR5K_MODE_11A | AR5K_MODE_TURBO | + (hal->ah_version == AR5K_AR5212 ? AR5K_MODE_XR : 0); + } + + /* Enable 802.11b if a 2GHz capable radio (2111/5112) is connected */ + if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { + hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ + hal->ah_capabilities.cap_range.range_2ghz_max = 2732; + + if (AR5K_EEPROM_HDR_11B(ee_header)) + hal->ah_capabilities.cap_mode |= AR5K_MODE_11B; #if 0 - if (AR5K_EEPROM_HDR_11G(ee_header)) - hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; + if (AR5K_EEPROM_HDR_11G(ee_header)) + hal->ah_capabilities.cap_mode |= AR5K_MODE_11G; #endif + } } /* GPIO */ hal->ah_gpio_npins = AR5K_NUM_GPIO; /* Set number of supported TX queues */ - hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; + if(hal->ah_version == AR5K_AR5210){ + hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU; + } else { + hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; + } return (TRUE); } @@ -2311,26 +2646,36 @@ void ath5k_hw_set_opmode(struct ath_hal *hal) { - u_int32_t pcu_reg, low_id, high_id; + u_int32_t pcu_reg, beacon_reg, low_id, high_id; pcu_reg = 0; + beacon_reg = 0; AR5K_TRACE; switch (hal->ah_op_mode) { case AR5K_M_IBSS: pcu_reg |= AR5K_STA_ID1_ADHOC | - AR5K_STA_ID1_DESC_ANTENNA; + AR5K_STA_ID1_DESC_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); + + beacon_reg |= AR5K_BCR_ADHOC; break; case AR5K_M_HOSTAP: pcu_reg |= AR5K_STA_ID1_AP | - AR5K_STA_ID1_RTS_DEF_ANTENNA; + AR5K_STA_ID1_RTS_DEF_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); + + beacon_reg |= AR5K_BCR_AP; break; case AR5K_M_STA: + pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_PWR_SV :0); case AR5K_M_MONITOR: - pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA; + pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | + (hal->ah_version == AR5K_AR5210 ?AR5K_STA_ID1_NO_PSPOLL :0); break; default: @@ -2339,13 +2684,19 @@ /* * Set PCU registers - * TODO: Test this on big endian */ low_id = AR5K_LOW_ID(hal->ah_sta_id); high_id = AR5K_HIGH_ID(hal->ah_sta_id); AR5K_REG_WRITE(AR5K_STA_ID0, low_id); AR5K_REG_WRITE(AR5K_STA_ID1, pcu_reg | high_id); + /* + * Set Beacon Control Register on 5210 + */ + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_BCR, beacon_reg); + } + return; } @@ -2425,12 +2776,8 @@ return; } - AR5K_REG_WRITE(AR5K_BEACON, - (AR5K_REG_READ(AR5K_BEACON) & - ~AR5K_BEACON_TIM) | - (((tim_offset ? tim_offset + 4 : 0) << - AR5K_BEACON_TIM_S) & - AR5K_BEACON_TIM)); + AR5K_REG_WRITE_BITS(AR5K_BEACON, AR5K_BEACON_TIM, + tim_offset ? tim_offset + 4 : 0); ath5k_hw_enable_pspoll(hal, NULL, 0); } @@ -2559,7 +2906,7 @@ if (data & AR5K_PHY_ERR_FIL_RADAR) filter |= AR5K_RX_FILTER_PHYRADAR; if (data & (AR5K_PHY_ERR_FIL_OFDM | - AR5K_PHY_ERR_FIL_CCK)) + AR5K_PHY_ERR_FIL_CCK)) filter |= AR5K_RX_FILTER_PHYERR; } @@ -2586,10 +2933,13 @@ } /* - * Got that from roofnet... - * Don't filter control frames & set promiscuous mode + * The AR5210 uses promiscous mode to detect radar activity */ - data |= AR5K_RX_FILTER_PROM | AR5K_RX_FILTER_CONTROL; + if((hal->ah_version == AR5K_AR5210) && + (filter & AR5K_RX_FILTER_PHYRADAR)){ + filter &= ~AR5K_RX_FILTER_PHYRADAR; + filter |= AR5K_RX_FILTER_PROM; + } /*Zero length DMA*/ if (data) { @@ -2662,8 +3012,13 @@ */ switch (hal->ah_op_mode) { case AR5K_M_STA: - timer1 = 0x0000ffff; - timer2 = 0x0007ffff; + if(hal->ah_version == AR5K_AR5210){ + timer1 = 0xffffffff; + timer2 = 0xffffffff; + } else { + timer1 = 0x0000ffff; + timer2 = 0x0007ffff; + } break; default: @@ -2677,7 +3032,7 @@ (hal->ah_atim_window ? hal->ah_atim_window : 1); /* - * Enable all timers and set the beacon register + * Set the beacon register and enable all timers. * (next beacon, DMA beacon, software beacon, ATIM window time) */ AR5K_REG_WRITE(AR5K_TIMER0, next_beacon); @@ -2692,13 +3047,20 @@ /* * Set beacon timers - * TODO: should be changed through *state - review AR5K_BEACON_STATE struct */ void ath5k_hw_set_beacon_timers(struct ath_hal *hal, const AR5K_BEACON_STATE *state) { u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; + /* + * TODO: should be changed through *state + * review AR5K_BEACON_STATE struct + * + * XXX: These are used for cfp period bellow, are they + * ok ? Is it O.K. for tsf here to be 0 or should we use + * get_tsf ? + */ u_int32_t dtim_count = 0; /* XXX */ u_int32_t cfp_count = 0; /* XXX */ u_int32_t tsf = 0; /* XXX */ @@ -2716,8 +3078,8 @@ */ if (state->bs_cfp_period > 0) { /* - * Enable CFP (Contention Free Period) mode and set the CFP - * and timer registers + * Enable PCF mode and set the CFP + * (Contention Free Period) and timer registers */ cfp_period = state->bs_cfp_period * state->bs_dtim_period * state->bs_interval; @@ -2747,14 +3109,15 @@ * Start the beacon timers */ AR5K_REG_WRITE(AR5K_BEACON, - (AR5K_REG_READ(AR5K_BEACON) &~ - (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | - AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, - AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, - AR5K_BEACON_PERIOD)); + (AR5K_REG_READ(AR5K_BEACON) &~ + (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | + AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, + AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, + AR5K_BEACON_PERIOD)); /* * Write new beacon miss threshold, if it appears to be valid + * XXX: < or <= ? */ if ((AR5K_RSSI_THR_BMISS >> AR5K_RSSI_THR_BMISS_S) < state->bs_bmiss_threshold) @@ -2765,6 +3128,8 @@ /* * Set sleep control register + * XXX: Didn't find this in 5210 code but since this register + * exists also in ar5k's 5210 headers i leave it as common code. */ AR5K_REG_WRITE_BITS(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, (state->bs_sleep_duration - 3) << 3); @@ -2823,27 +3188,55 @@ * Disable some beacon register values */ AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, - AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); + AR5K_STA_ID1_DEFAULT_ANTENNA | + AR5K_STA_ID1_PCF); AR5K_REG_WRITE(AR5K_BEACON, AR5K_BEACON_PERIOD); } /* * Wait for beacon queue to finish + * TODO: This function's name is misleading, rename */ AR5K_BOOL ath5k_hw_wait_for_beacon(struct ath_hal *hal, AR5K_BUS_ADDR phys_addr) { AR5K_BOOL ret; + int i; AR5K_TRACE; - ret = ath5k_hw_register_timeout(hal, - AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), - AR5K_QCU_STS_FRMPENDCNT, 0, FALSE); + /* 5210 doesn't have QCU*/ + if(hal->ah_version == AR5K_AR5210){ + /* + * Wait for beaconn queue to finish by checking + * Control Register and Beacon Status Register. + */ + for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && + (AR5K_REG_READ(AR5K_BSR) & AR5K_BSR_TXQ1F) != 0 && + (AR5K_REG_READ(AR5K_CR) & AR5K_CR_TXE1 ) != 0; i--); - if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) - return (FALSE); + /* Timeout... */ + if (i <= 0) { + /* + * Re-schedule the beacon queue + */ + AR5K_REG_WRITE(AR5K_NOQCU_TXDP1, (u_int32_t)phys_addr); + AR5K_REG_WRITE(AR5K_BCR, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE); + return (FALSE); + } + ret= TRUE; + + } else { + /*5211/5212*/ + ret = ath5k_hw_register_timeout(hal, + AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), + AR5K_QCU_STS_FRMPENDCNT, 0, FALSE); + + if (AR5K_REG_READ_Q(AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) + return (FALSE); + } + return (ret); } @@ -2981,9 +3374,11 @@ for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) AR5K_REG_WRITE(AR5K_KEYTABLE_OFF(entry, i), 0); - /* Set NULL encryption */ - AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), - AR5K_KEYTABLE_TYPE_NULL); + /* Set NULL encryption on non-5210*/ + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry), + AR5K_KEYTABLE_TYPE_NULL); + } return (FALSE); /*????*/ } @@ -3095,7 +3490,7 @@ */ int ath5k_hw_setup_tx_queue(struct ath_hal *hal, AR5K_TX_QUEUE queue_type, - AR5K_TXQ_INFO *queue_info) + AR5K_TXQ_INFO *queue_info) { u_int queue; AR5K_TRACE; @@ -3103,20 +3498,47 @@ /* * Get queue by type */ - if (queue_type == AR5K_TX_QUEUE_DATA) { - for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; - hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; - queue++) - if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) + /*5210 only has 2 queues*/ + if(hal->ah_version == AR5K_AR5210){ + switch (queue_type) { + case AR5K_TX_QUEUE_DATA: + queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; + break; + case AR5K_TX_QUEUE_BEACON: + case AR5K_TX_QUEUE_CAB: + queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; + break; + default: return (-1); - } else if (queue_type == AR5K_TX_QUEUE_UAPSD) { - queue = AR5K_TX_QUEUE_ID_UAPSD; - } else if (queue_type == AR5K_TX_QUEUE_BEACON) { - queue = AR5K_TX_QUEUE_ID_BEACON; - } else if (queue_type == AR5K_TX_QUEUE_CAB) { - queue = AR5K_TX_QUEUE_ID_CAB; - } else - return (-1); + } + } else { + switch(queue_type){ + case AR5K_TX_QUEUE_DATA: + for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; + hal->ah_txq[queue].tqi_type != AR5K_TX_QUEUE_INACTIVE; + queue++){ + if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) + return (-1); + } + break; + case AR5K_TX_QUEUE_UAPSD: + queue = AR5K_TX_QUEUE_ID_UAPSD; + break; + case AR5K_TX_QUEUE_BEACON: + queue = AR5K_TX_QUEUE_ID_BEACON; + break; + case AR5K_TX_QUEUE_CAB: + queue = AR5K_TX_QUEUE_ID_CAB; + break; + case AR5K_TX_QUEUE_XR_DATA: + if(hal->ah_version != AR5K_AR5212) + AR5K_PRINTF("XR data queues only supported in 5212!"); + queue = AR5K_TX_QUEUE_ID_XR_DATA; + break; + default: + return (-1); + } + } /* * Setup internal queue structure @@ -3130,7 +3552,11 @@ != TRUE) return (-1); } - + /* + * We use ah_txq_interrupts to hold a temp value for + * the Secondary interrupt mask registers on 5211+ + * check out ath5k_hw_reset_tx_queue + */ AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); return (queue); @@ -3138,11 +3564,10 @@ /* * Setup a transmit queue - * TODO: Shouldn't we set DFS params here (see reset_tx_queue) ? */ AR5K_BOOL ath5k_hw_setup_tx_queueprops(struct ath_hal *hal, int queue, - const AR5K_TXQ_INFO *queue_info) + const AR5K_TXQ_INFO *queue_info) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3152,12 +3577,13 @@ bcopy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + /*XXX: Is this supported on 5210 ?*/ if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) hal->ah_txq[queue].tqi_flags |= - AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; + AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; return (TRUE); } @@ -3184,6 +3610,7 @@ /* This queue will be skipped in further operations */ hal->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; + /*For SIMR setup*/ AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); return (FALSE); /*???*/ @@ -3196,7 +3623,10 @@ ath5k_hw_reset_tx_queue(struct ath_hal *hal, u_int queue) { u_int32_t cw_min, cw_max, retry_lg, retry_sh; - AR5K_TXQ_INFO *tq; + AR5K_TXQ_INFO *tq = &hal->ah_txq[queue]; + int i; + struct ath5k_ar5210_ini_mode ar5210_mode[] = + AR5K_AR5210_INI_MODE(hal->ah_aifs + tq->tqi_aifs); AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3206,25 +3636,53 @@ if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) return (TRUE); + if(hal->ah_version == AR5K_AR5210){ + /* Only handle data queues, others will be ignored */ + if (tq->tqi_type != AR5K_TX_QUEUE_DATA) + return (TRUE); + + /* + * Write initial mode register settings + */ + for (i = 0; i < AR5K_ELEMENTS(ar5210_mode); i++) + AR5K_REG_WRITE((u_int32_t)ar5210_mode[i].mode_register, + hal->ah_turbo == TRUE ? + ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base); + } + /* - * Set registers by channel mode + * Calculate cwmin/max by channel mode */ cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; hal->ah_aifs = AR5K_TUNE_AIFS; /*XR is only supported on 5212*/ - if (IS_CHAN_XR(hal->ah_current_channel) && (hal->ah_version == AR5K_AR5212)) { + if (IS_CHAN_XR(hal->ah_current_channel) + && (hal->ah_version == AR5K_AR5212)) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; hal->ah_aifs = AR5K_TUNE_AIFS_XR; - } else if (IS_CHAN_B(hal->ah_current_channel)) { + /*B mode is not supported on 5210*/ + } else if (IS_CHAN_B(hal->ah_current_channel) + && (hal->ah_version != AR5K_AR5210)) { cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; hal->ah_aifs = AR5K_TUNE_AIFS_11B; } + cw_min = 1; + while (cw_min < hal->ah_cw_min) + cw_min = (cw_min << 1) | 1; + + cw_min = tq->tqi_cw_min < 0 ? + (cw_min >> (-tq->tqi_cw_min)) : + ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); + cw_max = tq->tqi_cw_max < 0 ? + (cw_max >> (-tq->tqi_cw_max)) : + ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); + /* - * Set retry limits + * Calculate and set retry limits */ if (hal->ah_software_retry == TRUE) { /* XXX Need to test this */ @@ -3237,150 +3695,159 @@ retry_sh = AR5K_INIT_SH_RETRY; } - AR5K_REG_WRITE(AR5K_QUEUE_DFS_RETRY_LIMIT(queue), - AR5K_REG_SM(AR5K_INIT_SLG_RETRY, - AR5K_DCU_RETRY_LMT_SLG_RETRY) | - AR5K_REG_SM(AR5K_INIT_SSH_RETRY, - AR5K_DCU_RETRY_LMT_SSH_RETRY) | - AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | - AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY)); + /*No QCU/DCU [5210]*/ + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_NODCU_RETRY_LMT, + (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) + | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, + AR5K_NODCU_RETRY_LMT_SLG_RETRY) + | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, + AR5K_NODCU_RETRY_LMT_SSH_RETRY) + | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) + | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY)); + } else { + /*QCU/DCU [5211+]*/ + AR5K_REG_WRITE(AR5K_QUEUE_DFS_RETRY_LIMIT(queue), + AR5K_REG_SM(AR5K_INIT_SLG_RETRY, + AR5K_DCU_RETRY_LMT_SLG_RETRY) | + AR5K_REG_SM(AR5K_INIT_SSH_RETRY, + AR5K_DCU_RETRY_LMT_SSH_RETRY) | + AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | + AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY)); - /* - * Set initial content window (cw_min/cw_max) - * and arbitrated interframe space (aifs)... - */ - cw_min = 1; + /*===Rest is also for QCU/DCU only [5211+]===*/ - while (cw_min < hal->ah_cw_min) - cw_min = (cw_min << 1) | 1; + /* + * Set initial content window (cw_min/cw_max) + * and arbitrated interframe space (aifs)... + */ + AR5K_REG_WRITE(AR5K_QUEUE_DFS_LOCAL_IFS(queue), + AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | + AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | + AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, + AR5K_DCU_LCL_IFS_AIFS)); - cw_min = tq->tqi_cw_min < 0 ? - (cw_min >> (-tq->tqi_cw_min)) : - ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); - cw_max = tq->tqi_cw_max < 0 ? - (cw_max >> (-tq->tqi_cw_max)) : - ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); + /* + * Set misc registers + */ + AR5K_REG_WRITE(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_DCU_EARLY); - AR5K_REG_WRITE(AR5K_QUEUE_DFS_LOCAL_IFS(queue), - AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | - AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | - AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, - AR5K_DCU_LCL_IFS_AIFS)); - - /* - * Set misc registers - */ - AR5K_REG_WRITE(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_DCU_EARLY); - - if (tq->tqi_cbr_period) { - AR5K_REG_WRITE(AR5K_QUEUE_CBRCFG(queue), - AR5K_REG_SM(tq->tqi_cbr_period, - AR5K_QCU_CBRCFG_INTVAL) | - AR5K_REG_SM(tq->tqi_cbr_overflow_limit, - AR5K_QCU_CBRCFG_ORN_THRES)); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_FRSHED_CBR); - if (tq->tqi_cbr_overflow_limit) + if (tq->tqi_cbr_period) { + AR5K_REG_WRITE(AR5K_QUEUE_CBRCFG(queue), + AR5K_REG_SM(tq->tqi_cbr_period, + AR5K_QCU_CBRCFG_INTVAL) | + AR5K_REG_SM(tq->tqi_cbr_overflow_limit, + AR5K_QCU_CBRCFG_ORN_THRES)); AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_CBR_THRES_ENABLE); - } + AR5K_QCU_MISC_FRSHED_CBR); + if (tq->tqi_cbr_overflow_limit) + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_CBR_THRES_ENABLE); + } - if (tq->tqi_ready_time) { - AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), - AR5K_REG_SM(tq->tqi_ready_time, - AR5K_QCU_RDYTIMECFG_INTVAL) | - AR5K_QCU_RDYTIMECFG_ENABLE); - } + if (tq->tqi_ready_time) { + AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), + AR5K_REG_SM(tq->tqi_ready_time, + AR5K_QCU_RDYTIMECFG_INTVAL) | + AR5K_QCU_RDYTIMECFG_ENABLE); + } - if (tq->tqi_burst_time) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_CHANNEL_TIME(queue), - AR5K_REG_SM(tq->tqi_burst_time, - AR5K_DCU_CHAN_TIME_DUR) | - AR5K_DCU_CHAN_TIME_ENABLE); + if (tq->tqi_burst_time) { + AR5K_REG_WRITE(AR5K_QUEUE_DFS_CHANNEL_TIME(queue), + AR5K_REG_SM(tq->tqi_burst_time, + AR5K_DCU_CHAN_TIME_DUR) | + AR5K_DCU_CHAN_TIME_ENABLE); - if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_TXE); + if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_TXE); + } } - } - if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), - AR5K_DCU_MISC_POST_FR_BKOFF_DIS); - } + if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { + AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), + AR5K_DCU_MISC_POST_FR_BKOFF_DIS); + } - if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { - AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), - AR5K_DCU_MISC_BACKOFF_FRAG); - } + if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { + AR5K_REG_WRITE(AR5K_QUEUE_DFS_MISC(queue), + AR5K_DCU_MISC_BACKOFF_FRAG); + } - /* - * Set registers by queue type - */ - switch (tq->tqi_type) { - case AR5K_TX_QUEUE_BEACON: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_FRSHED_DBA_GT | - AR5K_QCU_MISC_CBREXP_BCN | - AR5K_QCU_MISC_BCN_ENABLE); + /* + * Set registers by queue type + */ + switch (tq->tqi_type) { + case AR5K_TX_QUEUE_BEACON: + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_DBA_GT | + AR5K_QCU_MISC_CBREXP_BCN | + AR5K_QCU_MISC_BCN_ENABLE); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), - (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL) | - AR5K_DCU_MISC_POST_FR_BKOFF_DIS | - AR5K_DCU_MISC_BCN_ENABLE); + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << + AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL) | + AR5K_DCU_MISC_POST_FR_BKOFF_DIS | + AR5K_DCU_MISC_BCN_ENABLE); - AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), - ((AR5K_TUNE_BEACON_INTERVAL - - (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - - AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | - AR5K_QCU_RDYTIMECFG_ENABLE); - break; + AR5K_REG_WRITE(AR5K_QUEUE_RDYTIMECFG(queue), + ((AR5K_TUNE_BEACON_INTERVAL - + (AR5K_TUNE_SW_BEACON_RESP - + AR5K_TUNE_DMA_BEACON_RESP) - + AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | + AR5K_QCU_RDYTIMECFG_ENABLE); + break; - case AR5K_TX_QUEUE_CAB: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_FRSHED_DBA_GT | - AR5K_QCU_MISC_CBREXP | - AR5K_QCU_MISC_CBREXP_BCN); + case AR5K_TX_QUEUE_CAB: + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_DBA_GT | + AR5K_QCU_MISC_CBREXP | + AR5K_QCU_MISC_CBREXP_BCN); - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), - (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL)); - break; + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), + (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << + AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL)); + break; - case AR5K_TX_QUEUE_UAPSD: - AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), - AR5K_QCU_MISC_CBREXP); - break; + case AR5K_TX_QUEUE_UAPSD: + AR5K_REG_ENABLE_BITS(AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_CBREXP); + break; - case AR5K_TX_QUEUE_DATA: - default: - break; - } + case AR5K_TX_QUEUE_DATA: + default: + break; + } - /* - * Enable tx queue in the secondary interrupt mask registers - */ - AR5K_REG_WRITE(AR5K_SIMR0, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXOK) | - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXDESC)); - AR5K_REG_WRITE(AR5K_SIMR1, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR1_QCU_TXERR)); - AR5K_REG_WRITE(AR5K_SIMR2, - AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); + /* + * Enable tx queue in the secondary interrupt mask registers + */ + AR5K_REG_WRITE(AR5K_SIMR0, + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXOK) | + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR0_QCU_TXDESC)); + AR5K_REG_WRITE(AR5K_SIMR1, + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR1_QCU_TXERR)); + AR5K_REG_WRITE(AR5K_SIMR2, + AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_SIMR2_QCU_TXURN)); + } return (TRUE); } /* * Get number of pending frames - * for a specific queue + * for a specific queue [5211+] */ u_int32_t ath5k_hw_num_tx_pending(struct ath_hal *hal, u_int queue) { AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + + if(hal->ah_version == AR5K_AR5210){ + return(FALSE); + } + return (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT); } @@ -3394,7 +3861,12 @@ if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) return (FALSE); - AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_SLOT_TIME, + ath5k_hw_htoclock(slot_time, hal->ah_turbo)); + } else { + AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time); + } return (TRUE); } @@ -3406,7 +3878,12 @@ ath5k_hw_get_slot_time(struct ath_hal *hal) { AR5K_TRACE; - return (AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff); + if(hal->ah_version == AR5K_AR5210){ + return (ath5k_hw_clocktoh(AR5K_REG_READ(AR5K_SLOT_TIME) & + 0xffff, hal->ah_turbo)); + } else { + return (AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff); + } } @@ -3421,17 +3898,18 @@ */ /* - * Initialize the tx descriptor on 5211 + * Initialize the 2-word tx descriptor on 5210/5211 */ -static AR5K_BOOL -ath5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +AR5K_BOOL +ath5k_hw_setup_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { - struct ath5k_ar5211_tx_desc *tx_desc; + u_int32_t frame_type; + struct ath5k_hw_2w_tx_desc *tx_desc; - tx_desc = (struct ath5k_ar5211_tx_desc*)&desc->ds_ctl0; + tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; /* * Validate input @@ -3439,32 +3917,58 @@ if (tx_tries0 == 0) return (FALSE); - /* Initialize status descriptor */ + /* Initialize control descriptor */ tx_desc->tx_control_0 = 0; tx_desc->tx_control_1 = 0; - /* Setup status descriptor */ + /* Setup control descriptor */ + /*Verify packet length*/ if ((tx_desc->tx_control_0 = (packet_length & - AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) + AR5K_2W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) return (FALSE); + /* + * Verify header length + * XXX: I only found that on 5210 code, does it work on 5211 ? + */ + if(hal->ah_version == AR5K_AR5210){ + if ((tx_desc->tx_control_0 = (header_length & + AR5K_2W_TX_DESC_CTL0_HEADER_LEN)) != header_length) + return (FALSE); + } - tx_desc->tx_control_0 |= - AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | - AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); - tx_desc->tx_control_1 = - AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); + /*Diferences between 5210-5211*/ + if(hal->ah_version == AR5K_AR5210){ + switch(type){ + case AR5K_PKT_TYPE_BEACON: + case AR5K_PKT_TYPE_PROBE_RESP: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; + case AR5K_PKT_TYPE_PIFS: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; + default: + frame_type = type /*<< 2 ?*/; + } + tx_desc->tx_control_0 = + AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE)| + AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); + } else { + tx_desc->tx_control_0 |= + AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | + AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT); + tx_desc->tx_control_1 = + AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE); + } #define _TX_FLAGS(_c, _flag) \ - if (flags & AR5K_TXDESC_##_flag) \ + if (flags & AR5K_TXDESC_##_flag) \ tx_desc->tx_control_##_c |= \ - AR5K_AR5211_DESC_TX_CTL##_c##_##_flag + AR5K_2W_TX_DESC_CTL##_c##_##_flag _TX_FLAGS(0, CLRDMASK); _TX_FLAGS(0, VEOL); _TX_FLAGS(0, INTREQ); _TX_FLAGS(0, RTSENA); - _TX_FLAGS(1, NOACK); + _TX_FLAGS(1, NOACK); /*???*/ #undef _TX_FLAGS @@ -3473,29 +3977,38 @@ */ if (key_index != AR5K_TXKEYIX_INVALID) { tx_desc->tx_control_0 |= - AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; + AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; tx_desc->tx_control_1 |= - AR5K_REG_SM(key_index, - AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); + AR5K_REG_SM(key_index, + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); } + /* + * RTS/CTS Duration [5210 ?] + */ + if ((hal->ah_version == AR5K_AR5210) && + (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) { + tx_desc->tx_control_1 |= + rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION; + } + return (TRUE); } /* - * Initialize tx descriptor on 5212 + * Initialize the 4-word tx descriptor on 5212 */ static AR5K_BOOL -ath5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +ath5k_hw_setup_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int packet_length, u_int header_length, AR5K_PKT_TYPE type, u_int tx_power, u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate, u_int rtscts_duration) { - struct ath5k_ar5212_tx_desc *tx_desc; + struct ath5k_hw_4w_tx_desc *tx_desc; AR5K_TRACE; - tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; /* * Validate input @@ -3511,31 +4024,31 @@ /* Setup status descriptor */ if ((tx_desc->tx_control_0 = (packet_length & - AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length) + AR5K_4W_TX_DESC_CTL0_FRAME_LEN)) != packet_length) return (FALSE); tx_desc->tx_control_0 |= - AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) | - AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT); + AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | + AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); tx_desc->tx_control_1 = - AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE); + AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); tx_desc->tx_control_2 = - AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0); + AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); tx_desc->tx_control_3 = - tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; + tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; -#define _TX_FLAGS(_c, _flag) \ - if (flags & AR5K_TXDESC_##_flag) \ - tx_desc->tx_control_##_c |= \ - AR5K_AR5212_DESC_TX_CTL##_c##_##_flag +#define _TX_FLAGS(_c, _flag) \ + if (flags & AR5K_TXDESC_##_flag) \ + tx_desc->tx_control_##_c |= \ + AR5K_4W_TX_DESC_CTL##_c##_##_flag _TX_FLAGS(0, CLRDMASK); _TX_FLAGS(0, VEOL); _TX_FLAGS(0, INTREQ); _TX_FLAGS(0, RTSENA); _TX_FLAGS(0, CTSENA); - _TX_FLAGS(1, NOACK); + _TX_FLAGS(1, NOACK); /*???*/ #undef _TX_FLAGS @@ -3544,10 +4057,10 @@ */ if (key_index != AR5K_TXKEYIX_INVALID) { tx_desc->tx_control_0 |= - AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID; + AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; tx_desc->tx_control_1 |= - AR5K_REG_SM(key_index, - AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); + AR5K_REG_SM(key_index, + AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); } /* @@ -3558,137 +4071,122 @@ (flags & AR5K_TXDESC_CTSENA)) return (FALSE); tx_desc->tx_control_2 |= - rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION; + rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION; tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate, - AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE); + AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); } return (TRUE); } /* - * Fill tx descriptor on 5211 + * Initialize a 4-word XR tx descriptor on 5212 */ -static AR5K_BOOL/*Added an argument *last_desc -need revision*/ -ath5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +static AR5K_BOOL +ath5k_hw_setup_xr_tx_desc(struct ath_hal *hal, struct ath_desc *desc, + u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, + u_int tx_rate3, u_int tx_tries3) +{ + struct ath5k_hw_4w_tx_desc *tx_desc; + + if(hal->ah_version == AR5K_AR5212){ + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + +#define _XTX_TRIES(_n) \ + if (tx_tries##_n) { \ + tx_desc->tx_control_2 |= \ + AR5K_REG_SM(tx_tries##_n, \ + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \ + tx_desc->tx_control_3 |= \ + AR5K_REG_SM(tx_rate##_n, \ + AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \ + } + + _XTX_TRIES(1); + _XTX_TRIES(2); + _XTX_TRIES(3); + +#undef _XTX_TRIES + + return (TRUE); + } + return(FALSE); +} + +/* + * Fill the 2-word tx descriptor on 5210/5211 + */ +AR5K_BOOL +ath5k_hw_fill_2word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) { - struct ath5k_ar5211_tx_desc *tx_desc; + struct ath5k_hw_2w_tx_desc *tx_desc; - tx_desc = (struct ath5k_ar5211_tx_desc*)&desc->ds_ctl0; + tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; /* Clear status descriptor */ bzero(desc->ds_hw, sizeof(desc->ds_hw)); /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & - AR5K_AR5211_DESC_TX_CTL1_BUF_LEN)) != segment_length) + AR5K_2W_TX_DESC_CTL1_BUF_LEN)) != segment_length) return (FALSE); if (first_segment != TRUE) - tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; + tx_desc->tx_control_0 &= ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN; if (last_segment != TRUE) - tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; + tx_desc->tx_control_1 |= AR5K_2W_TX_DESC_CTL1_MORE; return (TRUE); } /* - * Fill tx descriptor on 5212 + * Fill the 4-word tx descriptor on 5212 + * XXX: Added an argument *last_desc -need revision */ -static AR5K_BOOL /*Added an argument *last_desc -need revision*/ -ath5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, +static AR5K_BOOL +ath5k_hw_fill_4word_tx_desc(struct ath_hal *hal, struct ath_desc *desc, u_int segment_length, AR5K_BOOL first_segment, AR5K_BOOL last_segment, const struct ath_desc *last_desc) { - struct ath5k_ar5212_tx_desc *tx_desc; - struct ath5k_tx_status *tx_status; + struct ath5k_hw_4w_tx_desc *tx_desc; + struct ath5k_hw_tx_status *tx_status; AR5K_TRACE; - tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_tx_status*)&desc->ds_hw[2]; + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; /* Clear status descriptor */ - bzero(tx_status, sizeof(struct ath5k_tx_status)); + bzero(tx_status, sizeof(struct ath5k_hw_tx_status)); /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & - AR5K_AR5212_DESC_TX_CTL1_BUF_LEN)) != segment_length) + AR5K_4W_TX_DESC_CTL1_BUF_LEN)) != segment_length) return (FALSE); -/*Code from roofnet*/ -// if (segment_length> AR5K_AR5212_DESC_TX_CTL1_BUF_LEN){ -// return (FALSE); -//} -// tx_desc->tx_control_1 &= ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN; -// tx_desc->tx_control_1 |= (segment_length & AR5K_AR5212_DESC_TX_CTL1_BUF_LEN); -/* */ if (first_segment != TRUE) - tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN; + tx_desc->tx_control_0 &= ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN; if (last_segment != TRUE) - tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE; + tx_desc->tx_control_1 |= AR5K_4W_TX_DESC_CTL1_MORE; return (TRUE); } /* - * There is no XR in5211 + * Proccess the tx status descriptor on 5210/5211 */ -static AR5K_BOOL -ath5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - u_int tx_rate3, u_int tx_tries3) +AR5K_STATUS +ath5k_hw_proc_2word_tx_status(struct ath_hal *hal, struct ath_desc *desc) { - /*XR not supported on 5211*/ - return (FALSE); -} + struct ath5k_hw_tx_status *tx_status; + struct ath5k_hw_2w_tx_desc *tx_desc; -/* - * Initialize an XR tx descriptor on 5212 - */ -static AR5K_BOOL -ath5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, - u_int tx_rate3, u_int tx_tries3) -{ - struct ath5k_ar5212_tx_desc *tx_desc; + tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[0]; - tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; - -#define _XTX_TRIES(_n) \ - if (tx_tries##_n) { \ - tx_desc->tx_control_2 |= \ - AR5K_REG_SM(tx_tries##_n, \ - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n); \ - tx_desc->tx_control_3 |= \ - AR5K_REG_SM(tx_rate##_n, \ - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n); \ - } - - _XTX_TRIES(1); - _XTX_TRIES(2); - _XTX_TRIES(3); - -#undef _XTX_TRIES - - return (TRUE); -} - -/* - * Proccess a tx descriptor on 5211 - */ -static AR5K_STATUS -ath5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) -{ - struct ath5k_tx_status *tx_status; - struct ath5k_ar5211_tx_desc *tx_desc; - - tx_desc = (struct ath5k_ar5211_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_tx_status*)&desc->ds_hw[0]; - /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) return (AR5K_EINPROGRESS); @@ -3701,10 +4199,11 @@ AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT); + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT); + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); + /*TODO: desc->ds_us.tx.ts_virtcol + test*/ desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, AR5K_DESC_TX_STATUS1_SEQ_NUM); @@ -3715,20 +4214,20 @@ desc->ds_us.tx.ts_status = 0; desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0, - AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE); + AR5K_2W_TX_DESC_CTL0_XMIT_RATE); if ((tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { + AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; if (tx_status->tx_status_0 & - AR5K_DESC_TX_STATUS0_FILTERED) + AR5K_DESC_TX_STATUS0_FILTERED) desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; } @@ -3739,14 +4238,14 @@ * Proccess a tx descriptor on 5212 */ static AR5K_STATUS -ath5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) +ath5k_hw_proc_4word_tx_status(struct ath_hal *hal, struct ath_desc *desc) { - struct ath5k_tx_status *tx_status; - struct ath5k_ar5212_tx_desc *tx_desc; + struct ath5k_hw_tx_status *tx_status; + struct ath5k_hw_4w_tx_desc *tx_desc; AR5K_TRACE; - tx_desc = (struct ath5k_ar5212_tx_desc*)&desc->ds_ctl0; - tx_status = (struct ath5k_tx_status*)&desc->ds_hw[2]; + tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0; + tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; /* No frame has been send or error */ if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) @@ -3760,10 +4259,10 @@ AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT); + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, - AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT); + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, AR5K_DESC_TX_STATUS1_SEQ_NUM); @@ -3778,31 +4277,31 @@ AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { case 0: desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; + AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; break; case 1: desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1); + AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); desc->ds_us.tx.ts_longretry += AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1); + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); break; case 2: desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2); + AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); desc->ds_us.tx.ts_longretry += AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2); + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); break; case 3: desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, - AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3); + AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); desc->ds_us.tx.ts_longretry += AR5K_REG_MS(tx_desc->tx_control_2, - AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3); + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); break; } @@ -3833,7 +4332,7 @@ */ AR5K_BOOL ath5k_hw_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t size, u_int flags) + u_int32_t size, u_int flags) { struct ath5k_rx_desc *rx_desc; @@ -3842,8 +4341,8 @@ /* *Clear ds_hw - * If we don't clean the descriptor, while - * scanning we get too many results, + * If we don't clean the status descriptor, + * while scanning we get too many results, * most of them virtual, after some secs * of scanning system hangs. M.F. */ @@ -3865,48 +4364,48 @@ } /* - * Proccess an rx descriptor on 5211 + * Proccess the rx status descriptor on 5210/5211 */ -static AR5K_STATUS -ath5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) +AR5K_STATUS +ath5k_hw_proc_old_rx_status(struct ath_hal *hal, struct ath_desc *desc, + u_int32_t phys_addr, struct ath_desc *next) { - struct ath5k_ar5211_rx_status *rx_status; + struct ath5k_hw_old_rx_status *rx_status; - rx_status = (struct ath5k_ar5211_rx_status*)&desc->ds_hw[0]; + rx_status = (struct ath5k_hw_old_rx_status*)&desc->ds_hw[0]; /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) + if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) == 0) return (AR5K_EINPROGRESS); /* * Frame receive status */ desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN; + AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL); + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE); + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA; + AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_AR5211_DESC_RX_STATUS0_MORE; + AR5K_OLD_RX_DESC_STATUS0_MORE; desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); + AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); desc->ds_us.rx.rs_status = 0; /* * Key table status */ if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) { + AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) { desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); + AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); } else { desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; } @@ -3915,21 +4414,25 @@ * Receive/descriptor errors */ if ((rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { + AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) + AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { + AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN) + desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; + + if (rx_status->rx_status_1 & + AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) { desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; desc->ds_us.rx.rs_phyerr = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR); } if (rx_status->rx_status_1 & - AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) + AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; } @@ -3937,53 +4440,53 @@ } /* - * Proccess an rx descriptor on 5212 + * Proccess the rx status descriptor on 5212 */ static AR5K_STATUS -ath5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, - u_int32_t phys_addr, struct ath_desc *next) +ath5k_hw_proc_new_rx_status(struct ath_hal *hal, struct ath_desc *desc, + u_int32_t phys_addr, struct ath_desc *next) { - struct ath5k_ar5212_rx_status *rx_status; - struct ath5k_ar5212_rx_error *rx_err; + struct ath5k_hw_new_rx_status *rx_status; + struct ath5k_hw_rx_error *rx_err; AR5K_TRACE; - rx_status = (struct ath5k_ar5212_rx_status*)&desc->ds_hw[0]; + rx_status = (struct ath5k_hw_new_rx_status*)&desc->ds_hw[0]; /* Overlay on error */ - rx_err = (struct ath5k_ar5212_rx_error*)&desc->ds_hw[0]; + rx_err = (struct ath5k_hw_rx_error*)&desc->ds_hw[0]; /* No frame received / not ready */ - if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0) + if ((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) == 0) return (AR5K_EINPROGRESS); /* * Frame receive status */ desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & - AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN; + AR5K_NEW_RX_DESC_STATUS0_DATA_LEN; desc->ds_us.rx.rs_rssi = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL); + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); desc->ds_us.rx.rs_rate = - AR5K_REG_MS(rx_status->rx_status_0, - AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE); + AR5K_REG_MS(rx_status->rx_status_0, + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & - AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA; + AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA; desc->ds_us.rx.rs_more = rx_status->rx_status_0 & - AR5K_AR5212_DESC_RX_STATUS0_MORE; + AR5K_NEW_RX_DESC_STATUS0_MORE; desc->ds_us.rx.rs_tstamp = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); desc->ds_us.rx.rs_status = 0; /* * Key table status */ if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID) { + AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID) { desc->ds_us.rx.rs_keyix = - AR5K_REG_MS(rx_status->rx_status_1, - AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX); + AR5K_REG_MS(rx_status->rx_status_1, + AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX); } else { desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; } @@ -3992,25 +4495,25 @@ * Receive/descriptor errors */ if ((rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { + AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR) + AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) { + AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) { desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; desc->ds_us.rx.rs_phyerr = - AR5K_REG_MS(rx_err->rx_error_1, - AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE); + AR5K_REG_MS(rx_err->rx_error_1, + AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE); } if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) + AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; if (rx_status->rx_status_1 & - AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR) + AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; } @@ -4031,11 +4534,20 @@ ath5k_hw_set_ledstate(struct ath_hal *hal, AR5K_LED_STATE state) { u_int32_t led; + /*5210 has different led mode handling*/ + u_int32_t led_5210; AR5K_TRACE; - AR5K_REG_DISABLE_BITS(AR5K_PCICFG, - AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); + /*Reset led status*/ + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_DISABLE_BITS(AR5K_PCICFG, + AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); + } else { + AR5K_REG_DISABLE_BITS(AR5K_PCICFG, + AR5K_PCICFG_LED); + } + /* * Some blinking values, define at your wish */ @@ -4043,27 +4555,37 @@ case AR5K_LED_SCAN: case AR5K_LED_AUTH: led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_PEND; + AR5K_PCICFG_LED_PEND; + led_5210 = AR5K_PCICFG_LED_PEND| + AR5K_PCICFG_LED_BCTL; break; case AR5K_LED_INIT: led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_NONE; + AR5K_PCICFG_LED_NONE; + led_5210 = AR5K_PCICFG_LED_PEND; break; case AR5K_LED_ASSOC: case AR5K_LED_RUN: led = AR5K_PCICFG_LEDMODE_PROP | - AR5K_PCICFG_LED_ASSOC; + AR5K_PCICFG_LED_ASSOC; + led_5210 = AR5K_PCICFG_LED_ASSOC; break; default: led = AR5K_PCICFG_LEDMODE_PROM | - AR5K_PCICFG_LED_NONE; + AR5K_PCICFG_LED_NONE; + led_5210 = AR5K_PCICFG_LED_PEND; break; } - AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led); + /*Write new status to the register*/ + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led); + } else { + AR5K_REG_ENABLE_BITS(AR5K_PCICFG, led_5210); + } } /* @@ -4470,7 +4992,7 @@ * Set a channel on the radio chip */ AR5K_BOOL -ath5k_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +ath5k_hw_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { AR5K_BOOL ret; @@ -4490,12 +5012,12 @@ /* * Set the channel and wait */ - if (hal->ah_radio == AR5K_AR5110) - ret = ath5k_ar5110_channel(hal, channel); - else if (hal->ah_radio == AR5K_AR5111) - ret = ath5k_ar5111_channel(hal, channel); + if (hal->ah_radio == AR5K_RF5110) + ret = ath5k_hw_rf5110_channel(hal, channel); + else if (hal->ah_radio == AR5K_RF5111) + ret = ath5k_hw_rf5111_channel(hal, channel); else - ret = ath5k_ar5112_channel(hal, channel); + ret = ath5k_hw_rf5112_channel(hal, channel); if (ret == FALSE) return (ret); @@ -4509,10 +5031,10 @@ } /* - * Convertion needed for RF5210 + * Convertion needed for RF5110 */ u_int32_t -ath5k_ar5110_chan2athchan(AR5K_CHANNEL *channel) +ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *channel) { u_int32_t athchan; @@ -4533,14 +5055,14 @@ * Set channel on RF5110 */ AR5K_BOOL -ath5k_ar5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +ath5k_hw_rf5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int32_t data; /* * Set the channel and wait */ - data = ath5k_ar5110_chan2athchan(channel); + data = ath5k_hw_rf5110_chan2athchan(channel); AR5K_PHY_WRITE(0x27, data); AR5K_PHY_WRITE(0x30, 0); AR5K_DELAY(1000); @@ -4552,7 +5074,7 @@ * Convertion needed for 5111 */ AR5K_BOOL -ath5k_ar5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) +ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan) { int channel; @@ -4581,14 +5103,14 @@ * Set channel on 5111 */ AR5K_BOOL -ath5k_ar5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +ath5k_hw_rf5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int ieee_channel, ath_channel; u_int32_t data0, data1, clock; struct ath5k_athchan_2ghz ath_channel_2ghz; /* - * Set the channel on the AR5111 radio + * Set the channel on the RF5111 radio */ data0 = data1 = 0; ath_channel = ieee_channel = ath_hal_mhz2ieee(channel->freq, @@ -4596,7 +5118,7 @@ if (channel->channel_flags & CHANNEL_2GHZ) { /* Map 2GHz channel to 5GHz Atheros channel ID */ - if (ath5k_ar5111_chan2athchan(ieee_channel, + if (ath5k_hw_rf5111_chan2athchan(ieee_channel, &ath_channel_2ghz) == FALSE) return (FALSE); @@ -4625,7 +5147,7 @@ * Set channel on 5112 */ AR5K_BOOL -ath5k_ar5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) +ath5k_hw_rf5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel) { u_int32_t data, data0, data1, data2; u_int16_t c; @@ -4634,7 +5156,7 @@ c = channel->freq; /* - * Set the channel on the AR5112 or newer + * Set the channel on the RF5112 or newer */ if (c < 4800) { if (!((c - 2224) % 5)) { @@ -4673,8 +5195,172 @@ * Perform a PHY calibration */ AR5K_BOOL -ath5k_hw_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) +ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel){ + + AR5K_BOOL ret; + + if(hal->ah_radio == AR5K_RF5110){ + ret = ath5k_hw_rf5110_calibrate(hal,channel); + } else { + ret = ath5k_hw_rf511x_calibrate(hal,channel); + } + return (ret); +} +/* + * Perform a PHY calibration on RF5110 + */ +AR5K_BOOL +ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) { + AR5K_BOOL ret = TRUE; + u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor; + u_int i; + +#define AGC_DISABLE { \ + AR5K_REG_ENABLE_BITS(AR5K_PHY_AGC, \ + AR5K_PHY_AGC_DISABLE); \ + AR5K_DELAY(10); \ +} + +#define AGC_ENABLE { \ + AR5K_REG_DISABLE_BITS(AR5K_PHY_AGC, \ + AR5K_PHY_AGC_DISABLE); \ +} + + /* + * Disable beacons and RX/TX queues, wait + */ + AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW_5210, + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + beacon = AR5K_REG_READ(AR5K_BEACON_5210); + AR5K_REG_WRITE(AR5K_BEACON_5210, beacon & ~AR5K_BEACON_ENABLE); + + AR5K_DELAY(2300); + + /* + * Set the channel (with AGC turned off) + */ + AGC_DISABLE; + ret = ath5k_hw_channel(hal, channel); + + /* + * Activate PHY and wait + */ + AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); + AR5K_DELAY(1000); + + AGC_ENABLE; + + if (ret == FALSE) + return (ret); + + /* + * Calibrate the radio chip + */ + + /* Remember normal state */ + phy_sig = AR5K_REG_READ(AR5K_PHY_SIG); + phy_agc = AR5K_REG_READ(AR5K_PHY_AGCCOARSE); + phy_sat = AR5K_REG_READ(AR5K_PHY_ADCSAT); + + /* Update radio registers */ + AR5K_REG_WRITE(AR5K_PHY_SIG, + (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | + AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR)); + + AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, + (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | + AR5K_PHY_AGCCOARSE_LO)) | + AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | + AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO)); + + AR5K_REG_WRITE(AR5K_PHY_ADCSAT, + (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | + AR5K_PHY_ADCSAT_THR)) | + AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | + AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR)); + + AR5K_DELAY(20); + + AGC_DISABLE; + AR5K_REG_WRITE(AR5K_PHY_RFSTG, AR5K_PHY_RFSTG_DISABLE); + AGC_ENABLE; + + AR5K_DELAY(1000); + + /* + * Enable calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL); + + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) { + AR5K_PRINTF("calibration timeout (%uMHz)\n", + channel->freq); + ret = FALSE; + } + + /* Reset to normal state */ + AR5K_REG_WRITE(AR5K_PHY_SIG, phy_sig); + AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, phy_agc); + AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat); + + if (ret == FALSE) + return (FALSE); + + /* + * Enable noise floor calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF); + + if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF, 0, FALSE) == FALSE) { + AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", + channel->freq); + return (FALSE); + } + + /* Wait until the noise floor is calibrated */ + for (i = 20; i > 0; i--) { + AR5K_DELAY(1000); + noise_floor = AR5K_REG_READ(AR5K_PHY_NF); + + if (AR5K_PHY_NF_RVAL(noise_floor) & + AR5K_PHY_NF_ACTIVE) + noise_floor = AR5K_PHY_NF_AVAL(noise_floor); + + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) + break; + } + + if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { + AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", + channel->freq); + return (FALSE); + } + + + /* + * Re-enable RX/TX and beacons + */ + AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW_5210, + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + AR5K_REG_WRITE(AR5K_BEACON_5210, beacon); + +#undef AGC_ENABLE +#undef AGC_DISABLE + + return (TRUE); +} + +/* + * Perform a PHY calibration on RF5111/5112 + */ +AR5K_BOOL +ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel) +{ u_int32_t i_pwr, q_pwr; int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; AR5K_TRACE; @@ -4699,21 +5385,21 @@ /* Commit new IQ value */ AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ, - AR5K_PHY_IQ_CORR_ENABLE | - ((u_int32_t)q_coff) | - ((u_int32_t)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + AR5K_PHY_IQ_CORR_ENABLE | + ((u_int32_t)q_coff) | + ((u_int32_t)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); done: /* Start noise floor calibration */ AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL, - AR5K_PHY_AGCCTL_NF); + AR5K_PHY_AGCCTL_NF); /* Request RF gain */ if (channel->channel_flags & CHANNEL_5GHZ) { AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE, - AR5K_REG_SM(hal->ah_txpower.txp_max, - AR5K_PHY_PAPD_PROBE_TXPOWER) | - AR5K_PHY_PAPD_PROBE_TX_NEXT); + AR5K_REG_SM(hal->ah_txpower.txp_max, + AR5K_PHY_PAPD_PROBE_TXPOWER) | + AR5K_PHY_PAPD_PROBE_TX_NEXT); hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED; } @@ -4726,7 +5412,7 @@ AR5K_TRACE; /*Just a try M.F.*/ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); - return TRUE; + return (TRUE); } void /*TODO:Boundary check*/ @@ -4734,7 +5420,9 @@ { AR5K_TRACE; /*Just a try M.F.*/ - AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant); + if(hal->ah_version != AR5K_AR5210){ + AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant); + } return; } @@ -4743,11 +5431,14 @@ { AR5K_TRACE; /*Just a try M.F.*/ - return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + if(hal->ah_version != AR5K_AR5210){ + return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA); + } + return (FALSE); /*XXX: What do we return for 5210 ?*/ } u_int -ath5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, +ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, u_int32_t first, u_int32_t col, AR5K_BOOL set) { u_int32_t mask, entry, last, data, shift, position; @@ -4796,7 +5487,7 @@ } u_int32_t -ath5k_rfregs_gainf_corr(struct ath_hal *hal) +ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal) { u_int32_t mix, step; u_int32_t *rf; @@ -4807,10 +5498,10 @@ rf = hal->ah_rf_banks; hal->ah_gain.g_f_corr = 0; - if (ath5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1) + if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1) return (0); - step = ath5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE); + step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE); mix = hal->ah_gain.g_step->gos_param[0]; switch (mix) { @@ -4832,7 +5523,7 @@ } AR5K_BOOL -ath5k_rfregs_gain_readback(struct ath_hal *hal) +ath5k_hw_rfregs_gain_readback(struct ath_hal *hal) { u_int32_t step, mix, level[4]; u_int32_t *rf; @@ -4842,8 +5533,8 @@ rf = hal->ah_rf_banks; - if (hal->ah_radio == AR5K_AR5111) { - step = ath5k_rfregs_op(rf, hal->ah_offset[7], + if (hal->ah_radio == AR5K_RF5111) { + step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 6, 37, 0, FALSE); level[0] = 0; level[1] = (step == 0x3f) ? 0x32 : step + 4; @@ -4855,7 +5546,7 @@ hal->ah_gain.g_low = level[0] + (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); } else { - mix = ath5k_rfregs_op(rf, hal->ah_offset[7], + mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE); level[0] = level[2] = 0; @@ -4874,13 +5565,13 @@ } int32_t -ath5k_rfregs_gain_adjust(struct ath_hal *hal) +ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal) { int ret = 0; const struct ath5k_gain_opt *go; - go = hal->ah_radio == AR5K_AR5111 ? - &ar5111_gain_opt : &ar5112_gain_opt; + go = hal->ah_radio == AR5K_RF5111 ? + &rf5111_gain_opt : &rf5112_gain_opt; hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; @@ -4934,20 +5625,20 @@ * Initialize RF */ AR5K_BOOL -ath5k_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +ath5k_hw_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) { ath5k_rfgain_t *func = NULL; AR5K_BOOL ret; - if (hal->ah_radio == AR5K_AR5111) { - hal->ah_rf_banks_size = sizeof(ar5111_rf); - func = ath5k_ar5111_rfregs; - } else if (hal->ah_radio == AR5K_AR5112) { + if (hal->ah_radio == AR5K_RF5111) { + hal->ah_rf_banks_size = sizeof(rf5111_rf); + func = ath5k_hw_rf5111_rfregs; + } else if (hal->ah_radio == AR5K_RF5112) { if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) - hal->ah_rf_banks_size = sizeof(ar5112a_rf); + hal->ah_rf_banks_size = sizeof(rf5112a_rf); else - hal->ah_rf_banks_size = sizeof(ar5112_rf); - func = ath5k_ar5112_rfregs; + hal->ah_rf_banks_size = sizeof(rf5112_rf); + func = ath5k_hw_rf5112_rfregs; } else return (FALSE); @@ -4972,10 +5663,10 @@ * Initialize RF5111 */ AR5K_BOOL -ath5k_ar5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +ath5k_hw_rf5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - const u_int rf_size = AR5K_ELEMENTS(ar5111_rf); + const u_int rf_size = AR5K_ELEMENTS(rf5111_rf); u_int32_t *rf; int i, obdb = -1, bank = -1; u_int32_t ee_mode; @@ -4986,18 +5677,18 @@ /* Copy values to modify them */ for (i = 0; i < rf_size; i++) { - if (ar5111_rf[i].rf_bank >= - AR5K_AR5111_INI_RF_MAX_BANKS) { + if (rf5111_rf[i].rf_bank >= + AR5K_RF5111_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); return (FALSE); } - if (bank != ar5111_rf[i].rf_bank) { - bank = ar5111_rf[i].rf_bank; + if (bank != rf5111_rf[i].rf_bank) { + bank = rf5111_rf[i].rf_bank; hal->ah_offset[bank] = i; } - rf[i] = ar5111_rf[i].rf_value[mode]; + rf[i] = rf5111_rf[i].rf_value[mode]; } if (channel->channel_flags & CHANNEL_2GHZ) { @@ -5007,11 +5698,11 @@ ee_mode = AR5K_EEPROM_MODE_11G; obdb = 0; - if (!ath5k_rfregs_op(rf, hal->ah_offset[0], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], ee->ee_ob[ee_mode][obdb], 3, 119, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[0], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0], ee->ee_ob[ee_mode][obdb], 3, 122, 0, TRUE)) return (FALSE); @@ -5024,43 +5715,43 @@ (channel->freq >= 5260 ? 1 : (channel->freq > 4000 ? 0 : -1))); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_84, 1, 51, 3, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_pwd_90, 1, 45, 3, TRUE)) return (FALSE); } - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], !ee->ee_xpd[ee_mode], 1, 95, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_x_gain[ee_mode], 4, 96, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[7], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[7], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_xpd[ee_mode], 1, 4, 0, TRUE)) return (FALSE); /* Write RF values */ for (i = 0; i < rf_size; i++) { AR5K_REG_WAIT(i); - AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); + AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]); } return (TRUE); @@ -5070,7 +5761,7 @@ * Initialize RF5112 */ AR5K_BOOL -ath5k_ar5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) +ath5k_hw_rf5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int rf_size; @@ -5084,17 +5775,17 @@ rf = hal->ah_rf_banks; if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { - rf_ini = ar5112a_rf; - rf_size = AR5K_ELEMENTS(ar5112a_rf); + rf_ini = rf5112a_rf; + rf_size = AR5K_ELEMENTS(rf5112a_rf); } else { - rf_ini = ar5112_rf; - rf_size = AR5K_ELEMENTS(ar5112_rf); + rf_ini = rf5112_rf; + rf_size = AR5K_ELEMENTS(rf5112_rf); } /* Copy values to modify them */ for (i = 0; i < rf_size; i++) { if (rf_ini[i].rf_bank >= - AR5K_AR5112_INI_RF_MAX_BANKS) { + AR5K_RF5112_INI_RF_MAX_BANKS) { AR5K_PRINT("invalid bank\n"); return (FALSE); } @@ -5114,11 +5805,11 @@ ee_mode = AR5K_EEPROM_MODE_11G; obdb = 0; - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 287, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 290, 0, TRUE)) return (FALSE); } else { @@ -5129,33 +5820,33 @@ (channel->freq >= 5260 ? 1 : (channel->freq > 4000 ? 0 : -1))); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 279, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_ob[ee_mode][obdb], 3, 282, 0, TRUE)) return (FALSE); } #ifdef notyet - ath5k_rfregs_op(rf, hal->ah_offset[6], + ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_x_gain[ee_mode], 2, 270, 0, TRUE); - ath5k_rfregs_op(rf, hal->ah_offset[6], + ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_x_gain[ee_mode], 2, 257, 0, TRUE); #endif - if (!ath5k_rfregs_op(rf, hal->ah_offset[6], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6], ee->ee_xpd[ee_mode], 1, 302, 0, TRUE)) return (FALSE); - if (!ath5k_rfregs_op(rf, hal->ah_offset[7], + if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE)) return (FALSE); /* Write RF values */ for (i = 0; i < rf_size; i++) - AR5K_REG_WRITE(ar5112_rf[i].rf_register, rf[i]); + AR5K_REG_WRITE(rf5112_rf[i].rf_register, rf[i]); return (TRUE); } @@ -5166,7 +5857,7 @@ * doesn't ar5k_rfregs work ? */ void -ath5k_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, +ath5k_hw_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, u_int ee_mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; @@ -5178,22 +5869,22 @@ obdb = 0; if (freq == AR5K_INI_RFGAIN_2GHZ && - hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { - ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3); - db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3); + hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { + ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3); + db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3); rf[25].rf_value[freq] = - ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); + ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); rf[26].rf_value[freq] = - (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | - (rf[26].rf_value[freq] & ~0xf); + (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | + (rf[26].rf_value[freq] & ~0xf); } if (freq == AR5K_INI_RFGAIN_5GHZ) { /* For 11a and Turbo */ obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); + (channel->freq >= 5500 ? 2 : + (channel->freq >= 5260 ? 1 : + (channel->freq > 4000 ? 0 : -1))); } ob = ee->ee_ob[ee_mode][obdb]; @@ -5218,14 +5909,14 @@ for (i = 0; i < AR5K_ELEMENTS(rf); i++) { AR5K_REG_WAIT(i); AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, - rf[i].rf_value[freq]); + rf[i].rf_value[freq]); } hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; } AR5K_BOOL -ath5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq) +ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) { int i; @@ -5262,7 +5953,7 @@ AR5K_TRACE; if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active) - || (hal->ah_version == AR5K_AR5211)) + || (hal->ah_version <= AR5K_AR5211)) return (AR5K_RFGAIN_INACTIVE); if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED) @@ -5272,23 +5963,23 @@ if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { hal->ah_gain.g_current = - data >> AR5K_PHY_PAPD_PROBE_GAINF_S; + data >> AR5K_PHY_PAPD_PROBE_GAINF_S; type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR; - if (hal->ah_radio == AR5K_AR5112) { - ath5k_rfregs_gainf_corr(hal); + if (hal->ah_radio == AR5K_RF5112) { + ath5k_hw_rfregs_gainf_corr(hal); hal->ah_gain.g_current = - hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? - (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : - 0; + hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? + (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : + 0; } - if (ath5k_rfregs_gain_readback(hal) && - AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && - ath5k_rfregs_gain_adjust(hal)) + if (ath5k_hw_rfregs_gain_readback(hal) && + AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && + ath5k_hw_rfregs_gain_adjust(hal)) hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE; } @@ -5592,7 +6283,11 @@ } case AR5K_CAP_NUM_TXQUEUES: if (result) { - *result = AR5K_NUM_TX_QUEUES; + if(hal->ah_version == AR5K_AR5210){ + *result = AR5K_NUM_TX_QUEUES_NOQCU; + } else { + *result = AR5K_NUM_TX_QUEUES; + } goto yes; } case AR5K_CAP_VEOL: @@ -5646,7 +6341,9 @@ ath5k_hw_query_pspoll_support(struct ath_hal *hal) { AR5K_TRACE; - /* nope */ + if(hal->ah_version == AR5K_AR5210){ + return(TRUE); + } return (FALSE); } @@ -5665,6 +6362,12 @@ u_int16_t assoc_id) { AR5K_TRACE; + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_DISABLE_BITS(AR5K_STA_ID1, + AR5K_STA_ID1_NO_PSPOLL | + AR5K_STA_ID1_DEFAULT_ANTENNA); + return (TRUE); + } return (FALSE); } @@ -5672,6 +6375,12 @@ ath5k_hw_disable_pspoll(struct ath_hal *hal) { AR5K_TRACE; + if(hal->ah_version == AR5K_AR5210){ + AR5K_REG_ENABLE_BITS(AR5K_STA_ID1, + AR5K_STA_ID1_NO_PSPOLL | + AR5K_STA_ID1_DEFAULT_ANTENNA); + return (TRUE); + } return (FALSE); } @@ -5748,7 +6457,7 @@ */ AR5K_HAL_FUNCTION(hal, hw, reset); AR5K_HAL_FUNCTION(hal, hw, set_opmode); - AR5K_HAL_FUNCTION(hal, hw, calibrate); + AR5K_HAL_FUNCTION(hal, hw, phy_calibrate); /* * TX functions @@ -5763,15 +6472,15 @@ AR5K_HAL_FUNCTION(hal, hw, tx_start); AR5K_HAL_FUNCTION(hal, hw, stop_tx_dma); if(hal->ah_version == AR5K_AR5212){ - AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, setup_xtx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, fill_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5212, proc_tx_desc); - }else if(hal->ah_version == AR5K_AR5211){ - AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc); - AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc); + hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; + hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; + hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc; + hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; + }else if(hal->ah_version != AR5K_AR5212){ + hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; + hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; + hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc; + hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; } AR5K_HAL_FUNCTION(hal, hw, has_veol); @@ -5791,9 +6500,9 @@ AR5K_HAL_FUNCTION(hal, hw, set_rx_filter); AR5K_HAL_FUNCTION(hal, hw, setup_rx_desc); if(hal->ah_version == AR5K_AR5212){ - AR5K_HAL_FUNCTION(hal, ar5212, proc_rx_desc); - }else if(hal->ah_version == AR5K_AR5211){ - AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc); + hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; + }else if(hal->ah_version <= AR5K_AR5211){ + hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; } AR5K_HAL_FUNCTION(hal, hw, set_rx_signal); Index: ath5kreg.h =================================================================== --- ath5kreg.h (revision 2284) +++ ath5kreg.h (revision 2363) @@ -57,19 +57,19 @@ * 5210 has only 2 transmit queues so no DCU/QCU, just * 2 transmit descriptor pointers... */ -#define AR5K_NOQCU_TXDP0 0x0000 /*Queue 0 - data*/ -#define AR5K_NOQCU_TXDP1 0x0004 /*Queue 1 - beacons*/ +#define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ +#define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ /* * Mac Control Register */ -#define AR5K_CR 0x0008 /*Register Address*/ -#define AR5K_CR_TXE0 0x00000001 /*TX Enable for queue 0 on 5210*/ -#define AR5K_CR_TXE1 0x00000002 /*TX Enable for queue 1 on 5210*/ -#define AR5K_CR_RXE 0x00000004 /*RX Enable*/ -#define AR5K_CR_TXD0 0x00000008 /*TX Disable for queue 0 on 5210*/ -#define AR5K_CR_TXD1 0x00000010 /*TX Disable for queue 1 on 5210*/ -#define AR5K_CR_RXD 0x00000020 /*RX Disable*/ +#define AR5K_CR 0x0008 /* Register Address */ +#define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ +#define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ +#define AR5K_CR_RXE 0x00000004 /* RX Enable */ +#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ +#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ +#define AR5K_CR_RXD 0x00000020 /* RX Disable */ #define AR5K_CR_SWI 0x00000040 /* @@ -80,29 +80,29 @@ /* * Configuration and status register */ -#define AR5K_CFG 0x0014 /*Register Address*/ -#define AR5K_CFG_SWTD 0x00000001 /*Bitswap TX descriptor (for big endian archs)*/ -#define AR5K_CFG_SWTB 0x00000002 /*Bitswap TX buffer (?)*/ -#define AR5K_CFG_SWRD 0x00000004 /*Bitswap RX descriptor*/ -#define AR5K_CFG_SWRB 0x00000008 /*Bitswap RX buffer (?)*/ -#define AR5K_CFG_SWRG 0x00000010 -#define AR5K_CFG_ADHOC 0x00000020 /*not found on 5210*/ -#define AR5K_CFG_PHY_OK 0x00000100 /*not found on 5210*/ -#define AR5K_CFG_EEBS 0x00000200 /*EEPROM is busy*/ -#define AR5K_CFG_CLKGD 0x00000400 -#define AR5K_CFG_TXCNT 0x00007800 /*5210 only*/ +#define AR5K_CFG 0x0014 /* Register Address */ +#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ +#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer (?) */ +#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ +#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer (?) */ +#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register values (?) */ +#define AR5K_CFG_ADHOC 0x00000020 /* [5211+] */ +#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ +#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ +#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (?) */ +#define AR5K_CFG_TXCNT 0x00007800 /* [5210] */ #define AR5K_CFG_TXCNT_S 11 -#define AR5K_CFG_TXFSTAT 0x00008000 /*5210 only*/ -#define AR5K_CFG_TXFSTRT 0x00010000 /*5210 only*/ -#define AR5K_CFG_PCI_THRES 0x00060000 /*not found on 5210*/ +#define AR5K_CFG_TXFSTAT 0x00008000 /* [5210] */ +#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210 */ +#define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ #define AR5K_CFG_PCI_THRES_S 17 /* * Interrupt enable register */ -#define AR5K_IER 0x0024 /*Register Address*/ -#define AR5K_IER_DISABLE 0x00000000 /*Disable card interrupts*/ -#define AR5K_IER_ENABLE 0x00000001 /*Enable card interrupts*/ +#define AR5K_IER 0x0024 /* Register Address */ +#define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ +#define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ /* @@ -111,27 +111,27 @@ */ /* - * Beacon control register -5210 only- + * Beacon control register [5210] */ -#define AR5K_BCR 0x0028 /*Register Address*/ -#define AR5K_BCR_AP 0x00000000 /*AP mode*/ -#define AR5K_BCR_ADHOC 0x00000001 /*Ad-Hoc mode*/ -#define AR5K_BCR_BDMAE 0x00000002 /*DMA enable*/ -#define AR5K_BCR_TQ1FV 0x00000004 /*Use Queue1 for CAB traffic*/ -#define AR5K_BCR_TQ1V 0x00000008 /*Use Queue1 for Beacon traffic*/ +#define AR5K_BCR 0x0028 /* Register Address */ +#define AR5K_BCR_AP 0x00000000 /* AP mode */ +#define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ +#define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ +#define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ +#define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ #define AR5K_BCR_BCGET 0x00000010 /* - * First RTS duration register -5211 only- + * First RTS duration register [5211] */ -#define AR5K_RTSD0 0x0028 /*Register Address*/ -#define AR5K_RTSD0_6 0x000000ff /*6Mb RTS duration mask (?)*/ -#define AR5K_RTSD0_6_S 0 /*6Mb RTS duration shift (?)*/ -#define AR5K_RTSD0_9 0x0000ff00 /*9Mb*/ +#define AR5K_RTSD0 0x0028 /* Register Address */ +#define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ +#define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ +#define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ #define AR5K_RTSD0_9_S 8 -#define AR5K_RTSD0_12 0x00ff0000 /*12Mb*/ +#define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ #define AR5K_RTSD0_12_S 16 -#define AR5K_RTSD0_18 0xff000000 /*16Mb*/ +#define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ #define AR5K_RTSD0_18_S 24 @@ -141,7 +141,7 @@ */ /* - * Beacon status register -5210 only- + * Beacon status register [5210] * * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning @@ -150,41 +150,41 @@ * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. */ -#define AR5K_BSR 0x002c /*Register Address*/ -#define AR5K_BSR_BDLYSW 0x00000001 /*SW Beacon delay (?)*/ -#define AR5K_BSR_BDLYDMA 0x00000002 /*DMA Beacon delay (?)*/ -#define AR5K_BSR_TXQ1F 0x00000004 -#define AR5K_BSR_ATIMDLY 0x00000008 /*ATIM delay (?)*/ -#define AR5K_BSR_SNPADHOC 0x00000100 /*Ad-hoc mode set (?)*/ -#define AR5K_BSR_SNPBDMAE 0x00000200 /*Beacon DMA enabled (?)*/ -#define AR5K_BSR_SNPTQ1FV 0x00000400 /*Queue1 is used for CAB traffic (?)*/ -#define AR5K_BSR_SNPTQ1V 0x00000800 /*Queue1 is used for Beacon traffic (?)*/ -#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /*BCR snapshots are valid (?)*/ +#define AR5K_BSR 0x002c /* Register Address */ +#define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ +#define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ +#define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ +#define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ +#define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ +#define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ +#define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ +#define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ +#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ #define AR5K_BSR_SWBA_CNT 0x00ff0000 /* - * Second RTS duration register -5211 only- + * Second RTS duration register [5211] */ -#define AR5K_RTSD1 0x002c /*Register Address*/ -#define AR5K_RTSD1_24 0x000000ff /*24Mb*/ +#define AR5K_RTSD1 0x002c /* Register Address */ +#define AR5K_RTSD1_24 0x000000ff /* 24Mb */ #define AR5K_RTSD1_24_S 0 -#define AR5K_RTSD1_36 0x0000ff00 /*36Mb*/ +#define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ #define AR5K_RTSD1_36_S 8 -#define AR5K_RTSD1_48 0x00ff0000 /*48Mb*/ +#define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ #define AR5K_RTSD1_48_S 16 -#define AR5K_RTSD1_54 0xff000000 /*54Mb*/ +#define AR5K_RTSD1_54 0xff000000 /* 54Mb */ #define AR5K_RTSD1_54_S 24 /* * Transmit configuration register */ -#define AR5K_TXCFG 0x0030 /*Register Address*/ -#define AR5K_TXCFG_SDMAMR 0x00000007 /*DMA size*/ +#define AR5K_TXCFG 0x0030 /* Register Address */ +#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */ #define AR5K_TXCFG_SDMAMR_S 0 -#define AR5K_TXCFG_B_MODE 0x00000008 /*Set b mode for 5111 (enable 2111)*/ -#define AR5K_TXCFG_TXFSTP 0x00000008 /*TX DMA Stop -5210 only-*/ -#define AR5K_TXCFG_TXFULL 0x000003f0 /*TX Triger level mask*/ +#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ +#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ +#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ #define AR5K_TXCFG_TXFULL_S 4 #define AR5K_TXCFG_TXFULL_0B 0x00000000 #define AR5K_TXCFG_TXFULL_64B 0x00000010 @@ -192,22 +192,22 @@ #define AR5K_TXCFG_TXFULL_192B 0x00000030 #define AR5K_TXCFG_TXFULL_256B 0x00000040 #define AR5K_TXCFG_TXCONT_EN 0x00000080 -#define AR5K_TXCFG_DMASIZE 0x00000100 /*flag for passing DMA size -non 5210*/ -#define AR5K_TXCFG_JUMBO_TXE 0x00000400 /*enable jumbo frames transmition (?) -non 5210*/ -#define AR5K_TXCFG_RTSRND 0x00001000 /*non 5210*/ -#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /*non 5210*/ -#define AR5K_TXCFG_RDY_DIS 0x00004000 /*non 5210*/ +#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ +#define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ +#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ +#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ +#define AR5K_TXCFG_RDY_DIS 0x00004000 /* [5211+] */ /* * Receive configuration register */ -#define AR5K_RXCFG 0x0034 /*Register Address*/ -#define AR5K_RXCFG_SDMAMW 0x00000007 /*DMA size*/ +#define AR5K_RXCFG 0x0034 /* Register Address */ +#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */ #define AR5K_RXCFG_SDMAMW_S 0 -#define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /*default antenna*/ -#define AR5K_RXCFG_ZLFDMA 0x00000010 /*zero-length DMA*/ -#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /*enable jumbo frames recieve (?) -non 5210*/ -#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /*wrap jumbo frames (?) -non 5210*/ +#define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /* Default antenna */ +#define AR5K_RXCFG_ZLFDMA 0x00000010 /* Zero-length DMA */ +#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo frames reception (?) [5211+] */ +#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames (?) [5211+] */ /* * Receive jumbo descriptor last address register @@ -218,48 +218,48 @@ /* * MIB control register */ -#define AR5K_MIBC 0x0040 /*Register Address*/ +#define AR5K_MIBC 0x0040 /* Register Address */ #define AR5K_MIBC_COW 0x00000001 -#define AR5K_MIBC_FMC 0x00000002 /*Freeze Mib Counters (?)*/ -#define AR5K_MIBC_CMC 0x00000004 /*Clean Mib Counters (?)*/ +#define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ +#define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ #define AR5K_MIBC_MCS 0x00000008 /* * Timeout prescale register */ #define AR5K_TOPS 0x0044 -#define AR5K_TOPS_M 0x0000ffff /*non 5210*/ +#define AR5K_TOPS_M 0x0000ffff /* [5211+] (?) */ /* * Receive timeout register (no frame received) */ #define AR5K_RXNOFRM 0x0048 -#define AR5K_RXNOFRM_M 0x000003ff /*non 5210*/ +#define AR5K_RXNOFRM_M 0x000003ff /* [5211+] (?) */ /* * Transmit timeout register (no frame sent) */ #define AR5K_TXNOFRM 0x004c -#define AR5K_TXNOFRM_M 0x000003ff /*non 5210*/ -#define AR5K_TXNOFRM_QCU 0x000ffc00 /*non 5210*/ +#define AR5K_TXNOFRM_M 0x000003ff /* [5211+] (?) */ +#define AR5K_TXNOFRM_QCU 0x000ffc00 /* [5211+] (?) */ /* * Receive frame gap timeout register */ #define AR5K_RPGTO 0x0050 -#define AR5K_RPGTO_M 0x000003ff /*non 5210*/ +#define AR5K_RPGTO_M 0x000003ff /* [5211+] (?) */ /* * Receive frame count limit register */ #define AR5K_RFCNT 0x0054 -#define AR5K_RFCNT_M 0x0000001f /*non 5210*/ -#define AR5K_RFCNT_RFCL 0x0000000f /*5210*/ +#define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ +#define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ /* * Misc settings register */ -#define AR5K_MISC 0x0058 /*Register Address*/ +#define AR5K_MISC 0x0058 /* Register Address */ #define AR5K_MISC_DMA_OBS_M 0x000001e0 #define AR5K_MISC_DMA_OBS_S 5 #define AR5K_MISC_MISC_OBS_M 0x00000e00 @@ -268,15 +268,15 @@ #define AR5K_MISC_MAC_OBS_LSB_S 12 #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 #define AR5K_MISC_MAC_OBS_MSB_S 15 -#define AR5K_MISC_LED_DECAY 0x001c0000 /*5210*/ -#define AR5K_MISC_LED_BLINK 0x00e00000 /*5210*/ +#define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ +#define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ /* * QCU/DCU clock gating register (5311) */ -#define AR5K_QCUDCU_CLKGT 0x005c /*Register Address (?)*/ -#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /*Mask for QCU clock*/ -#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /*Mask for DCU clock*/ +#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ +#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ +#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ /* * Interrupt Status Registers @@ -286,83 +286,83 @@ * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. * Most of these bits are common for all chipsets. */ -#define AR5K_ISR 0x001c /*Register Address (5210)*/ -#define AR5K_PISR 0x0080 /*Register Address (5211/5212)*/ -#define AR5K_ISR_RXOK 0x00000001 /*Frame successfuly recieved*/ -#define AR5K_ISR_RXDESC 0x00000002 /*RX descriptor request*/ -#define AR5K_ISR_RXERR 0x00000004 /*Receive error*/ -#define AR5K_ISR_RXNOFRM 0x00000008 /*No frame received (receive timeout)*/ -#define AR5K_ISR_RXEOL 0x00000010 /*Empty RX descriptor*/ -#define AR5K_ISR_RXORN 0x00000020 /*Receive FIFO overrun*/ -#define AR5K_ISR_TXOK 0x00000040 /*Frame successfuly transmited*/ -#define AR5K_ISR_TXDESC 0x00000080 /*TX descriptor request*/ -#define AR5K_ISR_TXERR 0x00000100 /*Transmit error*/ -#define AR5K_ISR_TXNOFRM 0x00000200 /*No frame transmited (transmit timeout)*/ -#define AR5K_ISR_TXEOL 0x00000400 /*Empty TX descriptor*/ -#define AR5K_ISR_TXURN 0x00000800 /*Transmit FIFO underrun*/ -#define AR5K_ISR_MIB 0x00001000 /*Update MIB counters*/ -#define AR5K_ISR_SWI 0x00002000 -#define AR5K_ISR_RXPHY 0x00004000 /*PHY error*/ +#define AR5K_ISR 0x001c /* Register Address [5210] */ +#define AR5K_PISR 0x0080 /* Register Address [5211+] */ +#define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ +#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ +#define AR5K_ISR_RXERR 0x00000004 /* Receive error */ +#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ +#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ +#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ +#define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ +#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ +#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ +#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ +#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ +#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ +#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ +#define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ +#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ #define AR5K_ISR_RXKCM 0x00008000 -#define AR5K_ISR_SWBA 0x00010000 /*Software beacon alert*/ +#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ #define AR5K_ISR_BRSSI 0x00020000 -#define AR5K_ISR_BMISS 0x00040000 /*Beacon missed*/ -#define AR5K_ISR_HIUERR 0x00080000 /*Host Interface Unit error -non 5210*/ -#define AR5K_ISR_BNR 0x00100000 /*Beacon not ready -non 5210*/ -#define AR5K_ISR_MCABT 0x00100000 /*5210*/ -#define AR5K_ISR_RXCHIRP 0x00200000 /*5212 only*/ -#define AR5K_ISR_SSERR 0x00200000 /*5210 only*/ -#define AR5K_ISR_DPERR 0x00400000 /*5210 only*/ -#define AR5K_ISR_TIM 0x00800000 /*non 5210*/ -#define AR5K_ISR_BCNMISC 0x00800000 /*5212 only*/ -#define AR5K_ISR_GPIO 0x01000000 /*GPIO (rf kill)*/ -#define AR5K_ISR_QCBRORN 0x02000000 /*CBR overrun (?) -non 5210*/ -#define AR5K_ISR_QCBRURN 0x04000000 /*CBR underrun (?) -non 5210*/ -#define AR5K_ISR_QTRIG 0x08000000 /*non 5210*/ +#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ +#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ +#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ +#define AR5K_ISR_MCABT 0x00100000 /* [5210] */ +#define AR5K_ISR_RXCHIRP 0x00200000 /* [5212+] */ +#define AR5K_ISR_SSERR 0x00200000 /* [5210] */ +#define AR5K_ISR_DPERR 0x00400000 /* [5210] */ +#define AR5K_ISR_TIM 0x00800000 /* [5210] */ +#define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ +#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ +#define AR5K_ISR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ +#define AR5K_ISR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ +#define AR5K_ISR_QTRIG 0x08000000 /* [5211+] */ /* - * Secondary status registers (5211/5212) (0 - 4) + * Secondary status registers [5211+] (0 - 4) * * I guess from the names that these give the status for each * queue, that's why only masks are defined here, haven't got * any info about them (couldn't find them anywhere in ar5k code). */ -#define AR5K_SISR0 0x0084 /*Register Address (5211/5212)*/ -#define AR5K_SISR0_QCU_TXOK 0x000003ff /*Mask for QCU_TXOK*/ -#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /*Mask for QCU_TXDESC*/ +#define AR5K_SISR0 0x0084 /* Register Address [5211+] */ +#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ +#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ -#define AR5K_SISR1 0x0088 /*Register Address (5211/5212)*/ -#define AR5K_SISR1_QCU_TXERR 0x000003ff /*Mask for QCU_TXERR*/ -#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /*Mask for QCU_TXEOL*/ +#define AR5K_SISR1 0x0088 /* Register Address [5211+] */ +#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ +#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ -#define AR5K_SISR2 0x008c /*Register Address (5211/5212)*/ -#define AR5K_SISR2_QCU_TXURN 0x000003ff /*Mask for QCU_TXURN*/ +#define AR5K_SISR2 0x008c /* Register Address [5211+] */ +#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ #define AR5K_SISR2_MCABT 0x00100000 #define AR5K_SISR2_SSERR 0x00200000 #define AR5K_SISR2_DPERR 0x00400000 -#define AR5K_SISR2_TIM 0x01000000 /*5212 only*/ -#define AR5K_SISR2_CAB_END 0x02000000 /*5212 only*/ -#define AR5K_SISR2_DTIM_SYNC 0x04000000 /*5212 only*/ -#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /*5212 only*/ -#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /*5212 only*/ -#define AR5K_SISR2_DTIM 0x20000000 /*5212 only*/ +#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ +#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ +#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ +#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ +#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ +#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ -#define AR5K_SISR3 0x0090 /*Register Address (5211/5212)*/ -#define AR5K_SISR3_QCBRORN 0x000003ff /*Mask for QCBRORN*/ -#define AR5K_SISR3_QCBRURN 0x03ff0000 /*Mask for QCBRURN*/ +#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ +#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ +#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ -#define AR5K_SISR4 0x0094 /*Register Address (5211/5212)*/ -#define AR5K_SISR4_QTRIG 0x000003ff /*Mask for QTRIG*/ +#define AR5K_SISR4 0x0094 /* Register Address [5211+] */ +#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ /* - * Shadow read-and-clear interrupt status registers (5211/5212) + * Shadow read-and-clear interrupt status registers [5211+] */ -#define AR5K_RAC_PISR 0x00c0 /*Read and clear PISR*/ -#define AR5K_RAC_SISR0 0x00c4 /*Read and clear SISR0*/ -#define AR5K_RAC_SISR1 0x00c8 /*Read and clear SISR1*/ -#define AR5K_RAC_SISR2 0x00cc /*Read and clear SISR2*/ -#define AR5K_RAC_SISR3 0x00d0 /*Read and clear SISR3*/ -#define AR5K_RAC_SISR4 0x00d4 /*Read and clear SISR4*/ +#define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ +#define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ +#define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ +#define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ +#define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ +#define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ /* * Interrupt Mask Registers @@ -370,108 +370,108 @@ * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. */ -#define AR5K_IMR 0x0020 /*Register Address (5210)*/ -#define AR5K_PIMR 0x00a0 /*Register Address (5211/5212)*/ -#define AR5K_IMR_RXOK 0x00000001 /*Frame successfuly recieved*/ -#define AR5K_IMR_RXDESC 0x00000002 /*RX descriptor request*/ -#define AR5K_IMR_RXERR 0x00000004 /*Receive error*/ -#define AR5K_IMR_RXNOFRM 0x00000008 /*No frame received (receive timeout)*/ -#define AR5K_IMR_RXEOL 0x00000010 /*Empty RX descriptor*/ -#define AR5K_IMR_RXORN 0x00000020 /*Receive FIFO overrun*/ -#define AR5K_IMR_TXOK 0x00000040 /*Frame successfuly transmited*/ -#define AR5K_IMR_TXDESC 0x00000080 /*TX descriptor request*/ -#define AR5K_IMR_TXERR 0x00000100 /*Transmit error*/ -#define AR5K_IMR_TXNOFRM 0x00000200 /*No frame transmited (transmit timeout)*/ -#define AR5K_IMR_TXEOL 0x00000400 /*Empty TX descriptor*/ -#define AR5K_IMR_TXURN 0x00000800 /*Transmit FIFO underrun*/ -#define AR5K_IMR_MIB 0x00001000 /*Update MIB counters*/ +#define AR5K_IMR 0x0020 /* Register Address [5210] */ +#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ +#define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ +#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ +#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ +#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ +#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ +#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ +#define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ +#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ +#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ +#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ +#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ +#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ +#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ #define AR5K_IMR_SWI 0x00002000 -#define AR5K_IMR_RXPHY 0x00004000 /*PHY error*/ +#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ #define AR5K_IMR_RXKCM 0x00008000 -#define AR5K_IMR_SWBA 0x00010000 /*Software beacon alert*/ +#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ #define AR5K_IMR_BRSSI 0x00020000 -#define AR5K_IMR_BMISS 0x00040000 /*Beacon missed*/ -#define AR5K_IMR_HIUERR 0x00080000 /*Host Interface Unit error -non 5210*/ -#define AR5K_IMR_BNR 0x00100000 /*Beacon not ready -non 5210*/ -#define AR5K_IMR_MCABT 0x00100000 /*5210*/ -#define AR5K_IMR_RXCHIRP 0x00200000 /*5212 only*/ -#define AR5K_IMR_SSERR 0x00200000 /*5210 only*/ -#define AR5K_IMR_DPERR 0x00400000 /*5210 only*/ -#define AR5K_IMR_TIM 0x00800000 /*non 5210*/ -#define AR5K_IMR_BCNMISC 0x00800000 /*5212 only*/ -#define AR5K_IMR_GPIO 0x01000000 /*GPIO (rf kill)*/ -#define AR5K_IMR_QCBRORN 0x02000000 /*CBR overrun (?) -non 5210*/ -#define AR5K_IMR_QCBRURN 0x04000000 /*CBR underrun (?) -non 5210*/ -#define AR5K_IMR_QTRIG 0x08000000 /*non 5210*/ +#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ +#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ +#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ +#define AR5K_IMR_MCABT 0x00100000 /* [5210] */ +#define AR5K_IMR_RXCHIRP 0x00200000 /* [5212+]*/ +#define AR5K_IMR_SSERR 0x00200000 /* [5210] */ +#define AR5K_IMR_DPERR 0x00400000 /* [5210] */ +#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ +#define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ +#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ +#define AR5K_IMR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ +#define AR5K_IMR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ +#define AR5K_IMR_QTRIG 0x08000000 /* [5211+] */ /* - * Secondary interrupt mask registers (5211/5212) (0 - 4) + * Secondary interrupt mask registers [5211+] (0 - 4) */ -#define AR5K_SIMR0 0x00a4 /*Register Address (5211/5212)*/ -#define AR5K_SIMR0_QCU_TXOK 0x000003ff /*Mask for QCU_TXOK*/ +#define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ +#define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ #define AR5K_SIMR0_QCU_TXOK_S 0 -#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /*Mask for QCU_TXDESC*/ +#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ #define AR5K_SIMR0_QCU_TXDESC_S 16 -#define AR5K_SIMR1 0x00a8 /*Register Address (5211/5212)*/ -#define AR5K_SIMR1_QCU_TXERR 0x000003ff /*Mask for QCU_TXERR*/ +#define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ +#define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ #define AR5K_SIMR1_QCU_TXERR_S 0 -#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /*Mask for QCU_TXEOL*/ +#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ #define AR5K_SIMR1_QCU_TXEOL_S 16 -#define AR5K_SIMR2 0x00ac /*Register Address (5211/5212)*/ -#define AR5K_SIMR2_QCU_TXURN 0x000003ff /*Mask for QCU_TXURN*/ +#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ +#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ #define AR5K_SIMR2_QCU_TXURN_S 0 #define AR5K_SIMR2_MCABT 0x00100000 #define AR5K_SIMR2_SSERR 0x00200000 #define AR5K_SIMR2_DPERR 0x00400000 -#define AR5K_SIMR2_TIM 0x01000000 /*5212 only*/ -#define AR5K_SIMR2_CAB_END 0x02000000 /*5212 only*/ -#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /*5212 only*/ -#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /*5212 only*/ -#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /*5212 only*/ -#define AR5K_SIMR2_DTIM 0x20000000 /*5212 only*/ +#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ +#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ +#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ +#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ +#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ +#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ -#define AR5K_SIMR3 0x00b0 /*Register Address (5211/5212)*/ -#define AR5K_SIMR3_QCBRORN 0x000003ff /*Mask for QCBRORN*/ +#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ +#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ #define AR5K_SIMR3_QCBRORN_S 0 -#define AR5K_SIMR3_QCBRURN 0x03ff0000 /*Mask for QCBRURN*/ +#define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ #define AR5K_SIMR3_QCBRURN_S 16 -#define AR5K_SIMR4 0x00b4 /*Register Address (5211/5212)*/ -#define AR5K_SIMR4_QTRIG 0x000003ff /*Mask for QTRIG*/ +#define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ +#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ #define AR5K_SIMR4_QTRIG_S 0 /* - * Decompression mask registers (5212) + * Decompression mask registers [5212+] */ #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (?)*/ #define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/ /* - * Decompression configuration registers (5212) + * Decompression configuration registers [5212+] */ #define AR5K_DCCFG 0x0420 /* - * Compression configuration registers (5212) + * Compression configuration registers [5212+] */ #define AR5K_CCFG 0x0600 #define AR5K_CCFG_CUP 0x0604 /* - * Compression performance counter registers (5212) + * Compression performance counter registers [5212+] */ -#define AR5K_CPC0 0x0610 /*Compression performance counter 0*/ -#define AR5K_CPC1 0x0614 /*Compression performance counter 1*/ -#define AR5K_CPC2 0x0618 /*Compression performance counter 2*/ -#define AR5K_CPC3 0x061c /*Compression performance counter 3*/ -#define AR5K_CPCORN 0x0620 /*Compression performance overrun (?)*/ +#define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ +#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ +#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ +#define AR5K_CPC3 0x061c /* Compression performance counter 3 */ +#define AR5K_CPCORN 0x0620 /* Compression performance overrun (?) */ /* - * Queue control unit (QCU) registers (5211/5212) + * Queue control unit (QCU) registers [5211+] * * Card has 12 TX Queues but i see that only 0-9 are used (?) * both in binary HAL (see ah.h) and ar5k. Each queue has it's own @@ -497,7 +497,7 @@ /* * QCU Transmit descriptor pointer registers */ -#define AR5K_QCU_TXDP_BASE 0x0800 /*Register Address - Queue0 TXDP*/ +#define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) /* @@ -517,62 +517,62 @@ /* * QCU Constant Bit Rate configuration registers */ -#define AR5K_QCU_CBRCFG_BASE 0x08c0 /*Register Address - Queue0 CBRCFG*/ -#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /*CBR Interval mask*/ +#define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ +#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ #define AR5K_QCU_CBRCFG_INTVAL_S 0 -#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /*CBR overrun threshold mask*/ +#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ #define AR5K_QCU_CBRCFG_ORN_THRES_S 24 #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) /* * QCU Ready time configuration registers */ -#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /*Register Address - Queue0 RDYTIMECFG*/ -#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /*Ready time interval mask*/ +#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ +#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 -#define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /*Ready time duration mask*/ -#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /*Ready time enable mask*/ +#define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /* Ready time duration mask */ +#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) /* * QCU one shot arm set registers */ -#define AR5K_QCU_ONESHOTARM_SET 0x0940 /*Register Address -QCU "one shot arm set (?)"*/ +#define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff /* * QCU one shot arm clear registers */ -#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /*Register Address -QCU "one shot arm clear (?)"*/ +#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff /* * QCU misc registers */ -#define AR5K_QCU_MISC_BASE 0x09c0 /*Register Address -Queue0 MISC*/ -#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /*Frame sheduling mask*/ -#define AR5K_QCU_MISC_FRSHED_ASAP 0 /*ASAP*/ -#define AR5K_QCU_MISC_FRSHED_CBR 1 /*Constant Bit Rate*/ -#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /*DMA Beacon alert (GaTed ?)*/ -#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 -#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /*Beacon sent gated (?)*/ -#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /*Oneshot enable*/ -#define AR5K_QCU_MISC_CBREXP 0x00000020 /*CBR expired (normal queue)*/ -#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /*CBR expired (beacon queue)*/ -#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /*Beacons enabled*/ -#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /*CBR threshold enabled (?)*/ -#define AR5K_QCU_MISC_TXE 0x00000200 /*TXE reset when RDYTIME enalbed (?)*/ -#define AR5K_QCU_MISC_CBR 0x00000400 /*CBR threshold reset (?)*/ -#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /*DCU reset (?)*/ +#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ +#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ +#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ +#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ +#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ +#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ +#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ +#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ +#define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ +#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ +#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Beacons enabled */ +#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled (?) */ +#define AR5K_QCU_MISC_TXE 0x00000200 /* TXE reset when RDYTIME enalbed (?) */ +#define AR5K_QCU_MISC_CBR 0x00000400 /* CBR threshold reset (?) */ +#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU reset (?) */ #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) /* * QCU status registers */ -#define AR5K_QCU_STS_BASE 0x0a00 /*Register Address - Queue0 STS*/ -#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /*Frames pending counter*/ -#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /*CBR expired counter (?)*/ +#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ +#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ +#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter (?) */ #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) /* @@ -582,13 +582,13 @@ #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff /* - * QCU compression buffer base registers (5212 only) + * QCU compression buffer base registers [5212+] */ #define AR5K_QCU_CBB_SELECT 0x0b00 #define AR5K_QCU_CBB_ADDR 0x0b04 /* - * QCU compression buffer configuration register (5212 only) + * QCU compression buffer configuration register [5212+] */ #define AR5K_QCU_CBCFG 0x0b08 @@ -596,7 +596,7 @@ /* * Distributed Coordination Function (DCF) control unit (DCU) - * registers (5211/5212) + * registers [5211+] * * These registers control the various characteristics of each queue * for 802.11e (WME) combatibility so they go together with @@ -613,77 +613,83 @@ /* * DCU QCU mask registers */ -#define AR5K_DCU_QCUMASK_BASE 0x1000 /*Register Address -Queue0 DCU_QCUMASK*/ +#define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ #define AR5K_DCU_QCUMASK_M 0x000003ff #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) /* * DCU local Inter Frame Space settings register */ -#define AR5K_DCU_LCL_IFS_BASE 0x1040 /*Register Address -Queue0 DCU_LCL_IFS*/ -#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /*Minimum Contention Window*/ +#define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ +#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ #define AR5K_DCU_LCL_IFS_CW_MIN_S 0 -#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /*Maximum Contention Window*/ +#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ #define AR5K_DCU_LCL_IFS_CW_MAX_S 10 -#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /*Arbitrated Interframe Space*/ +#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ #define AR5K_DCU_LCL_IFS_AIFS_S 20 #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) /* * DCU retry limit registers */ -#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /*Register Address -Queue0 DCU_RETRY_LMT*/ -#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /*Short retry limit mask*/ +#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ +#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ #define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /*Long retry limit mask*/ +#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ #define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /*Station short retry limit mask (?)*/ +#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /*Station long retry limit mask (?)*/ +#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) /* * DCU channel time registers */ -#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /*Register Address -Queue0 DCU_CHAN_TIME*/ -#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /*Channel time duration*/ +#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ +#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ #define AR5K_DCU_CHAN_TIME_DUR_S 0 -#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /*Enable channel time*/ +#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) /* - * DCU misc registers + * DCU misc registers [5211+] * * For some of the registers i couldn't find in the code * (only backoff stuff is there realy) i tried to match the * names with 802.11e parameters etc, so i guess VIRTCOL here * means Virtual Collision and HCFPOLL means Hybrid Coordination - * factor Poll (CF- Poll). ARBLOCK_CTL_GLOBAL is used for beacon - * queue and CAB queue but i couldn't find any more infos. + * factor Poll (CF- Poll). Arbiter lockout control controls the + * behaviour on low priority queues when we have multiple queues + * with pending frames. Intra-frame lockout means we wait until + * the queue's current frame transmits (with post frame backoff and bursting) + * before we transmit anything else and global lockout means we + * wait for the whole queue to finish before higher priority queues + * can transmit (this is used on beacon and CAB queues). + * No lockout means there is no special handling. */ -#define AR5K_DCU_MISC_BASE 0x1100 /*Register Address -Queue0 DCU_MISC*/ -#define AR5K_DCU_MISC_BACKOFF 0x000007ff /*Mask for backoff setting (?)*/ -#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /*Enable backoff while bursting*/ -#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /*CF - Poll (?)*/ -#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /*Persistent backoff (?)*/ -#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /*Enable frame pre-fetch (?)*/ -#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /*Mask for Virtual Collision (?)*/ +#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ +#define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff setting (?) */ +#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ +#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll (?) */ +#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff (?) */ +#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch (?) */ +#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 #define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 #define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 -#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /*Beacon enable (?)*/ -#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 +#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Beacon enable (?) */ +#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 -#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 -#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 -#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 +#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 -#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /*Disable sequence number increment (?)*/ -#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /*Disable post-frame backoff (?)*/ -#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /*Virtual Collision policy (?)*/ +#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ +#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ +#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 -#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /*Sequence number control (?)*/ +#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) /* @@ -714,10 +720,10 @@ /* * DCU global IFS misc registers */ -#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /*Register Address*/ +#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 -#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /*Turbo mode (?)*/ -#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /*SIFS Duration mask (?)*/ +#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ +#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 @@ -729,9 +735,9 @@ /* * DCU transmit pause control/status register */ -#define AR5K_DCU_TXP 0x1270 /*Register Address*/ -#define AR5K_DCU_TXP_M 0x000003ff /*Tx pause mask (?)*/ -#define AR5K_DCU_TXP_STATUS 0x00010000 /*Tx pause status (?)*/ +#define AR5K_DCU_TXP 0x1270 /* Register Address */ +#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask (?) */ +#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status (?) */ /* * DCU transmit filter register @@ -754,28 +760,28 @@ * 4 and 8 are not used in 5211/5212 and * 2 means "baseband reset" on 5211/5212. */ -#define AR5K_RESET_CTL 0x4000 /*Register Address*/ -#define AR5K_RESET_CTL_PCU 0x00000001 /*Protocol Control Unit reset*/ -#define AR5K_RESET_CTL_DMA 0x00000002 /*DMA (Rx/Tx) reset -5210 only*/ -#define AR5K_RESET_CTL_BASEBAND 0x00000002 /*Baseband reset (5211/5212)*/ -#define AR5K_RESET_CTL_MAC 0x00000004 /*MAC reset (PCU+Baseband ?) -5210 only*/ -#define AR5K_RESET_CTL_PHY 0x00000008 /*PHY reset -5210 only*/ -#define AR5K_RESET_CTL_PCI 0x00000010 /*PCI Core reset (interrupts etc)*/ +#define AR5K_RESET_CTL 0x4000 /* Register Address */ +#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ +#define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ +#define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ +#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ +#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ +#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ #define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \ AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY) /* * Sleep control register */ -#define AR5K_SLEEP_CTL 0x4004 /*Register Address*/ -#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /*Sleep duration mask*/ +#define AR5K_SLEEP_CTL 0x4004 /* Register Address */ +#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ #define AR5K_SLEEP_CTL_SLDUR_S 0 -#define AR5K_SLEEP_CTL_SLE 0x00030000 /*Sleep enable mask*/ +#define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ #define AR5K_SLEEP_CTL_SLE_S 16 -#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /*Force chip awake*/ -#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /*Force chip sleep*/ +#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ +#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 -#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /*non 5210*/ +#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ /* * Interrupt pending register @@ -791,37 +797,34 @@ /* * PCI configuration register - * - * (5210) = prop is also pressent at 5210 else it's only - * for 5211/5212. Also some props are only present at 5210. */ -#define AR5K_PCICFG 0x4010 /*Register Address*/ -#define AR5K_PCICFG_EEAE 0x00000001 /*Eeprom access enable -5210 only*/ -#define AR5K_PCICFG_CLKRUNEN 0x00000004 /*CLKRUN enable*/ -#define AR5K_PCICFG_EESIZE 0x00000018 /*Mask for EEPROM size*/ +#define AR5K_PCICFG 0x4010 /* Register Address */ +#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ +#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ +#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ #define AR5K_PCICFG_EESIZE_S 3 -#define AR5K_PCICFG_EESIZE_4K 0 /*4K*/ -#define AR5K_PCICFG_EESIZE_8K 1 /*8K*/ -#define AR5K_PCICFG_EESIZE_16K 2 /*16K*/ -#define AR5K_PCICFG_EESIZE_FAIL 3 /*Failed to get size (?)*/ -#define AR5K_PCICFG_LED 0x00000060 /*Led status*/ -#define AR5K_PCICFG_LED_NONE 0x00000000 /*Default*/ -#define AR5K_PCICFG_LED_PEND 0x00000020 /*Scan / Auth pending (5210)*/ -#define AR5K_PCICFG_LED_ASSOC 0x00000040 /*Associated (5210)*/ -#define AR5K_PCICFG_BUS_SEL 0x00000380 /*Mask for "bus select" (?)*/ -#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /*Disable CBE fix (?)*/ -#define AR5K_PCICFG_SL_INTEN 0x00000800 /*Enable interrupts when asleep (?) (5210)*/ -#define AR5K_PCICFG_LED_BCTL 0x00001000 /*Led blink (?) -5210 only*/ -#define AR5K_PCICFG_SL_INPEN 0x00002800 /*Sleep even whith pending interrupts (?) (5210)*/ -#define AR5K_PCICFG_SPWR_DN 0x00010000 /*Mask for power status (5210)*/ -#define AR5K_PCICFG_LEDMODE 0x000e0000 /*Ledmode*/ -#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /*Blink on standard traffic*/ -#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /*Default mode (blink on any traffic)*/ -#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /*Some other blinking mode (?)*/ -#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /*Random blinking (?)*/ +#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ +#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ +#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ +#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size (?) [5211+] */ +#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ +#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ +#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ +#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ +#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ +#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ +#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ +#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ +#define AR5K_PCICFG_SL_INPEN 0x00002800 /* Sleep even whith pending interrupts (?) */ +#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ +#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ +#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ +#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ +#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ +#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ #define AR5K_PCICFG_LEDBLINK 0x00700000 #define AR5K_PCICFG_LEDBLINK_S 20 -#define AR5K_PCICFG_LEDSLOW 0x00800000 /*Slow led blink rate (?)*/ +#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ #define AR5K_PCICFG_LEDSTATE \ (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) @@ -844,15 +847,15 @@ */ #define AR5K_NUM_GPIO 6 -#define AR5K_GPIOCR 0x4014 /*Register Address*/ -#define AR5K_GPIOCR_INT_ENA 0x00008000 /*Enable GPIO interrupt*/ -#define AR5K_GPIOCR_INT_SELL 0x00000000 /*Generate interrupt when pin is off (?)*/ -#define AR5K_GPIOCR_INT_SELH 0x00010000 /*Generate interrupt when pin is on*/ -#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /*Mode 0 for pin n*/ -#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /*Mode 1 for pin n*/ -#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /*Mode 2 for pin n*/ -#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /*Mode 3 for pin n*/ -#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /*Interrupt for GPIO pin n*/ +#define AR5K_GPIOCR 0x4014 /* Register Address */ +#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ +#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is off (?) */ +#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is on */ +#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ +#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ +#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ +#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ +#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ /* * "General Purpose Input/Output" (GPIO) data output register @@ -869,10 +872,10 @@ /* * Silicon revision register */ -#define AR5K_SREV 0x4020 /*Register Address*/ -#define AR5K_SREV_REV 0x0000000f /*Mask for revision*/ +#define AR5K_SREV 0x4020 /* Register Address */ +#define AR5K_SREV_REV 0x0000000f /* Mask for revision */ #define AR5K_SREV_REV_S 0 -#define AR5K_SREV_VER 0x000000ff /*Mask for version*/ +#define AR5K_SREV_VER 0x000000ff /* Mask for version */ #define AR5K_SREV_VER_S 4 @@ -1016,22 +1019,22 @@ /* * EEPROM command register */ -#define AR5K_EEPROM_CMD 0x6008 /*Register Addres*/ -#define AR5K_EEPROM_CMD_READ 0x00000001 /*EEPROM read*/ -#define AR5K_EEPROM_CMD_WRITE 0x00000002 /*EEPROM write*/ -#define AR5K_EEPROM_CMD_RESET 0x00000004 /*EEPROM reset*/ +#define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ +#define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ +#define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ +#define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ /* * EEPROM status register */ -#define AR5K_EEPROM_STAT_5210 0x6c00 /*Register Address -5210*/ -#define AR5K_EEPROM_STAT_5211 0x600c /*Register Address -5211/5212*/ +#define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ +#define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ #define AR5K_EEPROM_STATUS (hal->ah_version == AR5K_AR5210 ? \ AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) -#define AR5K_EEPROM_STAT_RDERR 0x00000001 /*EEPROM read failed*/ -#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /*EEPROM read successful*/ -#define AR5K_EEPROM_STAT_WRERR 0x00000004 /*EEPROM write failed*/ -#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /*EEPROM write successful*/ +#define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ +#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ +#define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ +#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ /* * EEPROM config register (?) @@ -1043,7 +1046,10 @@ /* * Protocol Control Unit (PCU) registers */ -/*Used for checking initial register writes during channel reset (see reset func)*/ +/* + * Used for checking initial register writes + * during channel reset (see reset func) + */ #define AR5K_PCU_MIN 0x8000 #define AR5K_PCU_MAX 0x8fff @@ -1055,21 +1061,21 @@ /* * Second station id register (MAC address in upper 16 bits) */ -#define AR5K_STA_ID1 0x8004 /*Register Address*/ -#define AR5K_STA_ID1_AP 0x00010000 /*Set AP mode*/ -#define AR5K_STA_ID1_ADHOC 0x00020000 /*Set Ad-Hoc mode*/ -#define AR5K_STA_ID1_PWR_SV 0x00040000 /*Power save reporting (?)*/ -#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /*No key search*/ -#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /*No uapsd polling -5210 only*/ -#define AR5K_STA_ID1_PCF_5211 0x00100000 /*Enable PCF on 5211/5212*/ -#define AR5K_STA_ID1_PCF_5210 0x00200000 /*Enable PCF on 5210*/ +#define AR5K_STA_ID1 0x8004 /* Register Address */ +#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ +#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ +#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */ +#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ +#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ +#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ +#define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ #define AR5K_STA_ID1_PCF (hal->ah_version == AR5K_AR5210 ? \ AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) -#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /*Use default antenna on 5211/5212*/ -#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /*Update antenna from descriptor*/ -#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /*Use default antenna for RTS (?)*/ -#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /*Use 6Mbit/s for ACK/CTS (?)*/ -#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /*Use 11b base rate (for ACK/CTS ?) -non 5210*/ +#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ +#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ +#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */ +#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */ +#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ /* * First BSSID register (MAC address, lower 32bits) @@ -1093,20 +1099,20 @@ /* * ACK/CTS timeout register */ -#define AR5K_TIME_OUT 0x8014 /*Register Address*/ -#define AR5K_TIME_OUT_ACK 0x00001fff /*ACK timeout mask*/ +#define AR5K_TIME_OUT 0x8014 /* Register Address */ +#define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ #define AR5K_TIME_OUT_ACK_S 0 -#define AR5K_TIME_OUT_CTS 0x1fff0000 /*CTS timeout mask*/ +#define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ #define AR5K_TIME_OUT_CTS_S 16 /* * RSSI threshold register */ -#define AR5K_RSSI_THR 0x8018 /*Register Address*/ -#define AR5K_RSSI_THR_M 0x000000ff /*Mask for RSSI threshold -non 5210*/ -#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /*Mask for Beacon Missed threshold -5210*/ +#define AR5K_RSSI_THR 0x8018 /* Register Address */ +#define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ +#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ #define AR5K_RSSI_THR_BMISS_5210_S 8 -#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /*Mask for Beacon Missed threshold -5211/5212*/ +#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ #define AR5K_RSSI_THR_BMISS_5211_S 8 #define AR5K_RSSI_THR_BMISS (hal->ah_version == AR5K_AR5210 ? \ AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) @@ -1125,23 +1131,23 @@ * * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) */ -#define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address*/ -#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /*Short retry limit mask*/ +#define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address */ +#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /*Long retry mask*/ +#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /*Station short retry limit mask*/ +#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /*Station long retry limit mask*/ +#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 -#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /*Minimum contention window mask*/ +#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 /* * Transmit latency register */ -#define AR5K_USEC_5210 0x8020 /*Register Address (5210)*/ -#define AR5K_USEC_5211 0x801c /*Register Address (5211/5212)*/ +#define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ +#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ #define AR5K_USEC (hal->ah_version == AR5K_AR5210 ? \ AR5K_USEC_5210 : AR5K_USEC_5211) #define AR5K_USEC_1 0x0000007f @@ -1152,9 +1158,9 @@ #define AR5K_USEC_TX_LATENCY_5211_S 14 #define AR5K_USEC_RX_LATENCY_5211 0x1f800000 #define AR5K_USEC_RX_LATENCY_5211_S 23 -#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /*also for 5311*/ +#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ #define AR5K_USEC_TX_LATENCY_5210_S 14 -#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /*also for 5311*/ +#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ #define AR5K_USEC_RX_LATENCY_5210_S 20 /* @@ -1244,8 +1250,8 @@ * Receive filter register * TODO: Get these out of ar5xxx.h on ath5k */ -#define AR5K_RX_FILTER_5210 0x804c /*Register Address (521)*/ -#define AR5K_RX_FILTER_5211 0x803c /*Register Address (5211/5212)*/ +#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ +#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ #define AR5K_RX_FILTER (hal->ah_version == AR5K_AR5210 ? \ AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ @@ -1254,12 +1260,12 @@ #define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ #define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ #define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ -#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame -5212 only*/ -#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests -5212 only*/ -#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors */ -#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors*/ -#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /*5211 only*/ -#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /*5211 only*/ +#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ +#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ +#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ +#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ +#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ +#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ #define AR5K_RX_FILTER_PHYERR (hal->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212) #define AR5K_RX_FILTER_RADARERR (hal->ah_version == AR5K_AR5211 ? \ @@ -1282,22 +1288,22 @@ /* - * Transmit mask register (lower 32 bits) (5210) + * Transmit mask register (lower 32 bits) [5210] */ #define AR5K_TX_MASK0 0x8058 /* - * Transmit mask register (higher 16 bits) (5210) + * Transmit mask register (higher 16 bits) [5210] */ #define AR5K_TX_MASK1 0x805c /* - * Clear transmit mask (5210) + * Clear transmit mask [5210] */ #define AR5K_CLR_TMASK 0x8060 /* - * Trigger level register (before transmission) (5210) + * Trigger level register (before transmission) [5210] */ #define AR5K_TRIG_LVL 0x8064 @@ -1308,21 +1314,21 @@ * Only DIS_RX is used in the code, the rest i guess are * for tweaking/diagnostics. */ -#define AR5K_DIAG_SW_5210 0x8068 /*Register Address (5210)*/ -#define AR5K_DIAG_SW_5211 0x8048 /*Register Address (5211/5212)*/ +#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ +#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ #define AR5K_DIAG_SW (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 -#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /*Disable ACKs (?)*/ -#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /*Disable CTSs (?)*/ -#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /*Disable encryption (?)*/ -#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /*Disable decryption (?)*/ -#define AR5K_DIAG_SW_DIS_TX 0x00000020 /*Disable transmit -5210 only*/ -#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /*Disable recieve*/ +#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ +#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ +#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ +#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption (?) */ +#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ +#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 #define AR5K_DIAG_SW_DIS_RX (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) -#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /*Loopback (i guess it goes with DIS_TX) -5210 only*/ +#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 #define AR5K_DIAG_SW_LOOP_BACK (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) @@ -1334,15 +1340,15 @@ #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 #define AR5K_DIAG_SW_CHAN_INFO (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) -#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /*Scrambler seed (?)*/ +#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Scrambler seed (?) */ #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 #define AR5K_DIAG_SW_EN_SCRAM_SEED (hal->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) -#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /*non 5210*/ -#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /*5210 only*/ -#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /*Scrambler seed mask (?)*/ +#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ +#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ +#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ #define AR5K_DIAG_SW_SCRAM_SEED_S 10 -#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /*Disable seqnum increment (?)-5210 only*/ +#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 #define AR5K_DIAG_SW_FRAME_NV0 (hal->ah_version == AR5K_AR5210 ? \ @@ -1372,30 +1378,30 @@ #define AR5K_LAST_TSTP 0x8080 /* - * ADDAC test register (5211/5212) + * ADDAC test register [5211+] */ #define AR5K_ADDAC_TEST 0x8054 /* - * Default antenna register (5211/5212) + * Default antenna register [5211+] */ #define AR5K_DEFAULT_ANTENNA 0x8058 /* - * Retry count register (5210) + * Retry count register [5210] */ -#define AR5K_RETRY_CNT 0x8084 /*Register Address (5210)*/ -#define AR5K_RETRY_CNT_SSH 0x0000003f /*Station short retry count (?)*/ -#define AR5K_RETRY_CNT_SLG 0x00000fc0 /*Station long retry count (?)*/ +#define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ +#define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ +#define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ /* - * Back-off status register (5210) + * Back-off status register [5210] */ -#define AR5K_BACKOFF 0x8088 /*Register Address (5210)*/ -#define AR5K_BACKOFF_CW 0x000003ff /*Backoff Contention Window (?)*/ -#define AR5K_BACKOFF_CNT 0x03ff0000 /*Backoff count (?)*/ +#define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ +#define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ +#define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ @@ -1571,7 +1577,7 @@ #define AR5K_RATE_DUR_BASE 0x8700 #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) -/*===5212===*/ +/*===5212 end===*/ /* * Key table (WEP) register @@ -1587,11 +1593,11 @@ #define AR5K_KEYTABLE_TYPE_40 0x00000000 #define AR5K_KEYTABLE_TYPE_104 0x00000001 #define AR5K_KEYTABLE_TYPE_128 0x00000003 -#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /*5212*/ -#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /*!5210*/ -#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /*5212*/ -#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /*!5210*/ -#define AR5K_KEYTABLE_ANTENNA 0x00000008 /*5212*/ +#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */ +#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */ +#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */ +#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */ +#define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */ #define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) #define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) #define AR5K_KEYTABLE_VALID 0x00008000 @@ -1615,14 +1621,14 @@ #define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* - * PHY frame control register (5210) /turbo mode register (5211/5212) + * PHY frame control register [5110] /turbo mode register [5111+] * - * There is another frame control register for 5211/5212 + * There is another frame control register for [5111+] * at address 0x9944 (see below) but the 2 first flags - * are common here between 5210 frame control register - * and 5211/5212 turbo mode register, so this also works as - * a "turbo mode register" for 5210. We treat this one as - * a frame control register for 5210 below. + * are common here between 5110 frame control register + * and [5111+] turbo mode register, so this also works as + * a "turbo mode register" for 5110. We treat this one as + * a frame control register for 5110 below. */ #define AR5K_PHY_TURBO 0x9804 #define AR5K_PHY_TURBO_MODE 0x00000001 @@ -1635,7 +1641,7 @@ #define AR5K_PHY_AGC_DISABLE 0x08000000 /* - * PHY timing register (5212) + * PHY timing register [5112+] */ #define AR5K_PHY_TIMING_3 0x9814 #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 @@ -1656,7 +1662,7 @@ #define AR5K_PHY_ACT_DISABLE 0x00000002 /* - * PHY signal register (5210) + * PHY signal register [5110] */ #define AR5K_PHY_SIG 0x9858 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 @@ -1665,7 +1671,7 @@ #define AR5K_PHY_SIG_FIRPWR_S 18 /* - * PHY coarse agility control register (5210) + * PHY coarse agility control register [5110] */ #define AR5K_PHY_AGCCOARSE 0x985c #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 @@ -1676,9 +1682,9 @@ /* * PHY agility control register */ -#define AR5K_PHY_AGCCTL 0x9860 -#define AR5K_PHY_AGCCTL_CAL 0x00000001 -#define AR5K_PHY_AGCCTL_NF 0x00000002 +#define AR5K_PHY_AGCCTL 0x9860 /* Register address */ +#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ +#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ /* * PHY noise floor status register @@ -1691,7 +1697,7 @@ #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) /* - * PHY ADC saturation register (5210) + * PHY ADC saturation register [5110] */ #define AR5K_PHY_ADCSAT 0x9868 #define AR5K_PHY_ADCSAT_ICNT 0x0001f800 @@ -1700,7 +1706,7 @@ #define AR5K_PHY_ADCSAT_THR_S 5 /* - * PHY sleep registers (5212) + * PHY sleep registers [5112+] */ #define AR5K_PHY_SCR 0x9870 #define AR5K_PHY_SCR_32MHZ 0x0000001f @@ -1710,10 +1716,10 @@ #define AR5K_PHY_SCAL_32MHZ 0x0000000e /* - * PHY PLL control register (!5210) + * PHY PLL control register [5111+] */ #define AR5K_PHY_PLL 0x987c -#define AR5K_PHY_PLL_20MHZ 0x13 /*5211 only*/ +#define AR5K_PHY_PLL_20MHZ 0x13 /* [5111] */ #define AR5K_PHY_PLL_40MHZ_5211 0x18 #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa #define AR5K_PHY_PLL_40MHZ (hal->ah_version == AR5K_AR5211 ? \ @@ -1722,23 +1728,23 @@ #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab #define AR5K_PHY_PLL_44MHZ (hal->ah_version == AR5K_AR5211 ? \ AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) -#define AR5K_PHY_PLL_AR5111 0x00000000 -#define AR5K_PHY_PLL_AR5112 0x00000040 +#define AR5K_PHY_PLL_RF5111 0x00000000 +#define AR5K_PHY_PLL_RF5112 0x00000040 /* - * PHY RF stage register (5210) + * PHY RF stage register [5110] */ #define AR5K_PHY_RFSTG 0x98d4 #define AR5K_PHY_RFSTG_DISABLE 0x00000021 /* - * PHY receiver delay register (!5210) + * PHY receiver delay register [5111+] */ #define AR5K_PHY_RX_DELAY 0x9914 #define AR5K_PHY_RX_DELAY_M 0x00003fff /* - * PHY timing IQ control register (!5210) + * PHY timing IQ control register [5111+] */ #define AR5K_PHY_IQ 0x9920 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f @@ -1751,13 +1757,13 @@ /* - * PHY PAPD probe register (!5210) + * PHY PAPD probe register [5111+] */ #define AR5K_PHY_PAPD_PROBE 0x9930 #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 -#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /*5212 only*/ +#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ #define AR5K_PHY_PAPD_PROBE_TYPE_S 23 #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 #define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 @@ -1767,7 +1773,7 @@ /* - * PHY TX power registers (5212) + * PHY TX power registers [5112+] */ #define AR5K_PHY_TXPOWER_RATE1 0x9934 #define AR5K_PHY_TXPOWER_RATE2 0x9938 @@ -1777,16 +1783,16 @@ #define AR5K_PHY_TXPOWER_RATE4 0xa238 /* - * PHY frame control register (!5210) + * PHY frame control register [5111+] */ #define AR5K_PHY_FRAME_CTL_5210 0x9804 #define AR5K_PHY_FRAME_CTL_5211 0x9944 #define AR5K_PHY_FRAME_CTL (hal->ah_version == AR5K_AR5210 ? \ AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) -/*---non 5210---*/ +/*---[5111+]---*/ #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 -/*---5210 only---*/ +/*---[5110]---*/ #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 @@ -1795,31 +1801,31 @@ #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* - * PHY radar detection enable register (!5210) + * PHY radar detection enable register [5111+] */ #define AR5K_PHY_RADAR 0x9954 #define AR5K_PHY_RADAR_DISABLE 0x00000000 #define AR5K_PHY_RADAR_ENABLE 0x00000001 /* - * PHY antenna switch table registers (!5210) + * PHY antenna switch table registers [5110] */ #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 /* - * PHY clock sleep registers (5212) + * PHY clock sleep registers [5112+] */ #define AR5K_PHY_SCLOCK 0x99f0 #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c #define AR5K_PHY_SDELAY 0x99f4 #define AR5K_PHY_SDELAY_32MHZ 0x000000ff #define AR5K_PHY_SPENDING 0x99f8 -#define AR5K_PHY_SPENDING_AR5111 0x00000018 -#define AR5K_PHY_SPENDING_AR5112 0x00000014 +#define AR5K_PHY_SPENDING_RF5111 0x00000018 +#define AR5K_PHY_SPENDING_RF5112 0x00000014 /* - * Misc PHY/radio registers (5210/5211) + * Misc PHY/radio registers [5110 - 5111] */ #define AR5K_BB_GAIN_BASE 0x9b00 #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) @@ -1827,25 +1833,25 @@ #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) /* - * PHY timing IQ calibration result register (!5210) + * PHY timing IQ calibration result register [5111+] */ #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* - * PHY current RSSI register (!5210) + * PHY current RSSI register [5111+] */ #define AR5K_PHY_CURRENT_RSSI 0x9c1c /* - * PHY PCDAC TX power register (5212) + * PHY PCDAC TX power register [5112+] */ #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) /* - * PHY mode register (!5210) + * PHY mode register [5111+] */ #define AR5K_PHY_MODE 0x0a200 #define AR5K_PHY_MODE_MOD 0x00000001 @@ -1854,21 +1860,21 @@ #define AR5K_PHY_MODE_FREQ 0x00000002 #define AR5K_PHY_MODE_FREQ_5GHZ 0 #define AR5K_PHY_MODE_FREQ_2GHZ 2 -#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /*5212 only*/ -#define AR5K_PHY_MODE_RAD 0x00000008 /*5212 only*/ -#define AR5K_PHY_MODE_RAD_AR5111 0 -#define AR5K_PHY_MODE_RAD_AR5112 8 -#define AR5K_PHY_MODE_XR 0x00000010 /*5212 only*/ +#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* [5112+] */ +#define AR5K_PHY_MODE_RAD 0x00000008 /* [5112+] */ +#define AR5K_PHY_MODE_RAD_RF5111 0 +#define AR5K_PHY_MODE_RAD_RF5112 8 +#define AR5K_PHY_MODE_XR 0x00000010 /* [5112+] */ /* - * PHY CCK transmit control register (5212) + * PHY CCK transmit control register [5112+] */ #define AR5K_PHY_CCKTXCTL 0xa204 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 /* - * PHY 2GHz gain register (5212) + * PHY 2GHz gain register [5112+] */ #define AR5K_PHY_GAIN_2GHZ 0xa20c #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 Index: ath5k_hw.h =================================================================== --- ath5k_hw.h (revision 2284) +++ ath5k_hw.h (revision 2363) @@ -74,7 +74,7 @@ /* * Gain optimization tables... */ -#define AR5K_AR5111_GAIN_OPT { \ +#define AR5K_RF5111_GAIN_OPT { \ 4, \ 9, \ { \ @@ -90,7 +90,7 @@ } \ } -#define AR5K_AR5112_GAIN_OPT { \ +#define AR5K_RF5112_GAIN_OPT { \ 1, \ 8, \ { \ @@ -339,16 +339,7 @@ /* * Non - common initial register values */ -struct ath5k_ini { - u_int16_t ini_register; - u_int32_t ini_value; - enum { - AR5K_INI_WRITE = 0, - AR5K_INI_READ = 1, - } ini_mode; -}; - #define AR5K_INI_VAL_11A 0 #define AR5K_INI_VAL_11A_TURBO 1 #define AR5K_INI_VAL_11B 2 @@ -361,8 +352,8 @@ #define AR5K_INI_PHY_5112 1 #define AR5K_INI_PHY_511X 1 -#define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS -#define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS +#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS +#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS struct ath5k_ini_rf { u_int8_t rf_bank; @@ -370,7 +361,7 @@ u_int32_t rf_value[5]; }; -#define AR5K_AR5111_INI_RF { \ +#define AR5K_RF5111_INI_RF { \ { 0, 0x989c, \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ { 0, 0x989c, \ @@ -463,7 +454,7 @@ { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ } -#define AR5K_AR5112_INI_RF { \ +#define AR5K_RF5112_INI_RF { \ { 1, 0x98d4, \ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ { 2, 0x98d0, \ @@ -574,7 +565,7 @@ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } -#define AR5K_AR5112A_INI_RF { \ +#define AR5K_RF5112A_INI_RF { \ { 1, 0x98d4, \ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ { 2, 0x98d0, \ @@ -847,94 +838,94 @@ u_int32_t rx_control_1; #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff -#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 +#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 } __packed; -struct ath5k_ar5211_rx_status { +struct ath5k_hw_old_rx_status { /* * RX status word 0 */ u_int32_t rx_status_0; -#define AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN 0x00000fff -#define AR5K_AR5211_DESC_RX_STATUS0_MORE 0x00001000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x38000000 -#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 27 +#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 /* * RX status word 1 */ u_int32_t rx_status_1; -#define AR5K_AR5211_DESC_RX_STATUS1_DONE 0x00000001 -#define AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_AR5211_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008 -#define AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010 -#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR 0x000000e0 -#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR_S 5 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX 0x00007e00 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_S 9 -#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 -#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15 -#define AR5K_AR5211_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000 +#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 +#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 } __packed; -struct ath5k_ar5212_rx_status { +struct ath5k_hw_new_rx_status { /* * RX status word 0 */ u_int32_t rx_status_0; -#define AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN 0x00000fff -#define AR5K_AR5212_DESC_RX_STATUS0_MORE 0x00001000 -#define AR5K_AR5212_DESC_RX_STATUS0_DECOMP_CRC_ERROR 0x00002000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE 0x000f8000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x0ff00000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 20 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA 0xf0000000 -#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 28 +#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 /* * RX status word 1 */ u_int32_t rx_status_1; -#define AR5K_AR5212_DESC_RX_STATUS1_DONE 0x00000001 -#define AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000008 -#define AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR 0x00000010 -#define AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR 0x00000020 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX 0x0000fe00 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_S 9 -#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 -#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 16 -#define AR5K_AR5212_DESC_RX_STATUS1_KEY_CACHE_MISS 0x80000000 +#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 +#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010 +#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 } __packed; -struct ath5k_ar5212_rx_error { +struct ath5k_hw_rx_error { /* * RX error word 0 */ u_int32_t rx_error_0; -#define AR5K_AR5212_DESC_RX_ERROR0 0x00000000 +#define AR5K_RX_DESC_ERROR0 0x00000000 /* * RX error word 1 */ u_int32_t rx_error_1; -#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE 0x0000ff00 -#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE_S 8 +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 } __packed; #define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 @@ -946,107 +937,127 @@ #define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 #define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 -struct ath5k_ar5211_tx_desc { +struct ath5k_hw_2w_tx_desc { /* * TX control word 0 */ u_int32_t tx_control_0; -#define AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN 0x00000fff -#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE 0x003c0000 -#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE_S 18 -#define AR5K_AR5211_DESC_TX_CTL0_RTSENA 0x00400000 -#define AR5K_AR5211_DESC_TX_CTL0_VEOL 0x00800000 -#define AR5K_AR5211_DESC_TX_CTL0_CLRDMASK 0x01000000 -#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000 -#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_AR5211_DESC_TX_CTL0_INTREQ 0x20000000 -#define AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 +#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 +#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 /* * TX control word 1 */ u_int32_t tx_control_1; -#define AR5K_AR5211_DESC_TX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5211_DESC_TX_CTL1_MORE 0x00001000 -#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 -#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE 0x00700000 -#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE_S 20 -#define AR5K_AR5211_DESC_TX_CTL1_NOACK 0x00800000 +#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ } __packed; -struct ath5k_ar5212_tx_desc { +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 + +struct ath5k_hw_4w_tx_desc { /* * TX control word 0 */ u_int32_t tx_control_0; -#define AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN 0x00000fff -#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER 0x003f0000 -#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER_S 16 -#define AR5K_AR5212_DESC_TX_CTL0_RTSENA 0x00400000 -#define AR5K_AR5212_DESC_TX_CTL0_VEOL 0x00800000 -#define AR5K_AR5212_DESC_TX_CTL0_CLRDMASK 0x01000000 -#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000 -#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_AR5212_DESC_TX_CTL0_INTREQ 0x20000000 -#define AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 -#define AR5K_AR5212_DESC_TX_CTL0_CTSENA 0x80000000 +#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 +#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 +#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 +#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 /* * TX control word 1 */ u_int32_t tx_control_1; -#define AR5K_AR5212_DESC_TX_CTL1_BUF_LEN 0x00000fff -#define AR5K_AR5212_DESC_TX_CTL1_MORE 0x00001000 -#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 -#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE 0x00f00000 -#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE_S 20 -#define AR5K_AR5212_DESC_TX_CTL1_NOACK 0x01000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC 0x06000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC_S 25 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN 0x18000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN_S 27 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN 0x60000000 -#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN_S 29 +#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 /* * TX control word 2 */ u_int32_t tx_control_2; -#define AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION 0x00007fff -#define AR5K_AR5212_DESC_TX_CTL2_DURATION_UPDATE_ENABLE 0x00008000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0 0x000f0000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0_S 16 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1 0x00f00000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1_S 20 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2 0x0f000000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2_S 24 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3 0xf0000000 -#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3_S 28 +#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff +#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 /* * TX control word 3 */ u_int32_t tx_control_3; -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0 0x0000001f -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1 0x000003e0 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1_S 5 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2 0x00007c00 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2_S 10 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3 0x000f8000 -#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3_S 15 -#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE 0x01f00000 -#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE_S 20 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 } __packed; -struct ath5k_tx_status { +struct ath5k_hw_tx_status { /* * TX status word 0 */ @@ -1056,10 +1067,18 @@ #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 #define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 +/*??? #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 +*/ +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 +/*??? #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 +*/ +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 @@ -1087,6 +1106,271 @@ * card at boot time and after each reset. */ +struct ath5k_ini { + u_int16_t ini_register; + u_int32_t ini_value; + + enum { + AR5K_INI_WRITE = 0, + AR5K_INI_READ = 1, + } ini_mode; +}; + +#define AR5K_AR5210_INI { \ + /* PCU and MAC registers */ \ + { AR5K_NOQCU_TXDP0, 0 }, \ + { AR5K_NOQCU_TXDP1, 0 }, \ + { AR5K_RXDP, 0 }, \ + { AR5K_CR, 0 }, \ + { AR5K_ISR, 0, AR5K_INI_READ }, \ + { AR5K_IMR, 0 }, \ + { AR5K_IER, AR5K_IER_DISABLE }, \ + { AR5K_BSR, 0, AR5K_INI_READ }, \ + { AR5K_TXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_RXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_CFG, AR5K_INIT_CFG }, \ + { AR5K_TOPS, AR5K_INIT_TOPS }, \ + { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \ + { AR5K_RPGTO, AR5K_INIT_RPGTO }, \ + { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \ + { AR5K_SFR, 0 }, \ + { AR5K_MIBC, 0 }, \ + { AR5K_MISC, 0 }, \ + { AR5K_RX_FILTER_5210, 0 }, \ + { AR5K_MCAST_FILTER0_5210, 0 }, \ + { AR5K_MCAST_FILTER1_5210, 0 }, \ + { AR5K_TX_MASK0, 0 }, \ + { AR5K_TX_MASK1, 0 }, \ + { AR5K_CLR_TMASK, 0 }, \ + { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ + { AR5K_DIAG_SW_5210, 0 }, \ + { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ + { AR5K_TSF_L32_5210, 0 }, \ + { AR5K_TIMER0_5210, 0 }, \ + { AR5K_TIMER1_5210, 0xffffffff }, \ + { AR5K_TIMER2_5210, 0xffffffff }, \ + { AR5K_TIMER3_5210, 1 }, \ + { AR5K_CFP_DUR_5210, 0 }, \ + { AR5K_CFP_PERIOD_5210, 0 }, \ + /* PHY registers */ \ + { AR5K_PHY(0), 0x00000047 }, \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0x09848ea6 }, \ + { AR5K_PHY(4), 0x3d32e000 }, \ + { AR5K_PHY(5), 0x0000076b }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \ + { AR5K_PHY(8), 0x02020200 }, \ + { AR5K_PHY(9), 0x00000e0e }, \ + { AR5K_PHY(10), 0x0a020201 }, \ + { AR5K_PHY(11), 0x00036ffc }, \ + { AR5K_PHY(12), 0x00000000 }, \ + { AR5K_PHY(13), 0x00000e0e }, \ + { AR5K_PHY(14), 0x00000007 }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x89630000 }, \ + { AR5K_PHY(17), 0x1372169c }, \ + { AR5K_PHY(18), 0x0018b633 }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(20), 0x0de8b8e0 }, \ + { AR5K_PHY(21), 0x00074859 }, \ + { AR5K_PHY(22), 0x7e80beba }, \ + { AR5K_PHY(23), 0x313a665e }, \ + { AR5K_PHY_AGCCTL, 0x00001d08 }, \ + { AR5K_PHY(25), 0x0001ce00 }, \ + { AR5K_PHY(26), 0x409a4190 }, \ + { AR5K_PHY(28), 0x0000000f }, \ + { AR5K_PHY(29), 0x00000080 }, \ + { AR5K_PHY(30), 0x00000004 }, \ + { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \ + { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000003 }, \ + /* BB gain table (64bytes) */ \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(0x01), 0x00000020 }, \ + { AR5K_BB_GAIN(0x02), 0x00000010 }, \ + { AR5K_BB_GAIN(0x03), 0x00000030 }, \ + { AR5K_BB_GAIN(0x04), 0x00000008 }, \ + { AR5K_BB_GAIN(0x05), 0x00000028 }, \ + { AR5K_BB_GAIN(0x06), 0x00000028 }, \ + { AR5K_BB_GAIN(0x07), 0x00000004 }, \ + { AR5K_BB_GAIN(0x08), 0x00000024 }, \ + { AR5K_BB_GAIN(0x09), 0x00000014 }, \ + { AR5K_BB_GAIN(0x0a), 0x00000034 }, \ + { AR5K_BB_GAIN(0x0b), 0x0000000c }, \ + { AR5K_BB_GAIN(0x0c), 0x0000002c }, \ + { AR5K_BB_GAIN(0x0d), 0x00000002 }, \ + { AR5K_BB_GAIN(0x0e), 0x00000022 }, \ + { AR5K_BB_GAIN(0x0f), 0x00000012 }, \ + { AR5K_BB_GAIN(0x10), 0x00000032 }, \ + { AR5K_BB_GAIN(0x11), 0x0000000a }, \ + { AR5K_BB_GAIN(0x12), 0x0000002a }, \ + { AR5K_BB_GAIN(0x13), 0x00000001 }, \ + { AR5K_BB_GAIN(0x14), 0x00000021 }, \ + { AR5K_BB_GAIN(0x15), 0x00000011 }, \ + { AR5K_BB_GAIN(0x16), 0x00000031 }, \ + { AR5K_BB_GAIN(0x17), 0x00000009 }, \ + { AR5K_BB_GAIN(0x18), 0x00000029 }, \ + { AR5K_BB_GAIN(0x19), 0x00000005 }, \ + { AR5K_BB_GAIN(0x1a), 0x00000025 }, \ + { AR5K_BB_GAIN(0x1b), 0x00000015 }, \ + { AR5K_BB_GAIN(0x1c), 0x00000035 }, \ + { AR5K_BB_GAIN(0x1d), 0x0000000d }, \ + { AR5K_BB_GAIN(0x1e), 0x0000002d }, \ + { AR5K_BB_GAIN(0x1f), 0x00000003 }, \ + { AR5K_BB_GAIN(0x20), 0x00000023 }, \ + { AR5K_BB_GAIN(0x21), 0x00000013 }, \ + { AR5K_BB_GAIN(0x22), 0x00000033 }, \ + { AR5K_BB_GAIN(0x23), 0x0000000b }, \ + { AR5K_BB_GAIN(0x24), 0x0000002b }, \ + { AR5K_BB_GAIN(0x25), 0x00000007 }, \ + { AR5K_BB_GAIN(0x26), 0x00000027 }, \ + { AR5K_BB_GAIN(0x27), 0x00000017 }, \ + { AR5K_BB_GAIN(0x28), 0x00000037 }, \ + { AR5K_BB_GAIN(0x29), 0x0000000f }, \ + { AR5K_BB_GAIN(0x2a), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2b), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2c), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2d), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2e), 0x0000002f }, \ + { AR5K_BB_GAIN(0x2f), 0x0000002f }, \ + { AR5K_BB_GAIN(0x30), 0x0000002f }, \ + { AR5K_BB_GAIN(0x31), 0x0000002f }, \ + { AR5K_BB_GAIN(0x32), 0x0000002f }, \ + { AR5K_BB_GAIN(0x33), 0x0000002f }, \ + { AR5K_BB_GAIN(0x34), 0x0000002f }, \ + { AR5K_BB_GAIN(0x35), 0x0000002f }, \ + { AR5K_BB_GAIN(0x36), 0x0000002f }, \ + { AR5K_BB_GAIN(0x37), 0x0000002f }, \ + { AR5K_BB_GAIN(0x38), 0x0000002f }, \ + { AR5K_BB_GAIN(0x39), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3a), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3b), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3c), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3d), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3e), 0x0000002f }, \ + { AR5K_BB_GAIN(0x3f), 0x0000002f }, \ + /* RF gain table (64bytes) */ \ + { AR5K_RF_GAIN(0), 0x0000001d }, \ + { AR5K_RF_GAIN(0x01), 0x0000005d }, \ + { AR5K_RF_GAIN(0x02), 0x0000009d }, \ + { AR5K_RF_GAIN(0x03), 0x000000dd }, \ + { AR5K_RF_GAIN(0x04), 0x0000011d }, \ + { AR5K_RF_GAIN(0x05), 0x00000021 }, \ + { AR5K_RF_GAIN(0x06), 0x00000061 }, \ + { AR5K_RF_GAIN(0x07), 0x000000a1 }, \ + { AR5K_RF_GAIN(0x08), 0x000000e1 }, \ + { AR5K_RF_GAIN(0x09), 0x00000031 }, \ + { AR5K_RF_GAIN(0x0a), 0x00000071 }, \ + { AR5K_RF_GAIN(0x0b), 0x000000b1 }, \ + { AR5K_RF_GAIN(0x0c), 0x0000001c }, \ + { AR5K_RF_GAIN(0x0d), 0x0000005c }, \ + { AR5K_RF_GAIN(0x0e), 0x00000029 }, \ + { AR5K_RF_GAIN(0x0f), 0x00000069 }, \ + { AR5K_RF_GAIN(0x10), 0x000000a9 }, \ + { AR5K_RF_GAIN(0x11), 0x00000020 }, \ + { AR5K_RF_GAIN(0x12), 0x00000019 }, \ + { AR5K_RF_GAIN(0x13), 0x00000059 }, \ + { AR5K_RF_GAIN(0x14), 0x00000099 }, \ + { AR5K_RF_GAIN(0x15), 0x00000030 }, \ + { AR5K_RF_GAIN(0x16), 0x00000005 }, \ + { AR5K_RF_GAIN(0x17), 0x00000025 }, \ + { AR5K_RF_GAIN(0x18), 0x00000065 }, \ + { AR5K_RF_GAIN(0x19), 0x000000a5 }, \ + { AR5K_RF_GAIN(0x1a), 0x00000028 }, \ + { AR5K_RF_GAIN(0x1b), 0x00000068 }, \ + { AR5K_RF_GAIN(0x1c), 0x0000001f }, \ + { AR5K_RF_GAIN(0x1d), 0x0000001e }, \ + { AR5K_RF_GAIN(0x1e), 0x00000018 }, \ + { AR5K_RF_GAIN(0x1f), 0x00000058 }, \ + { AR5K_RF_GAIN(0x20), 0x00000098 }, \ + { AR5K_RF_GAIN(0x21), 0x00000003 }, \ + { AR5K_RF_GAIN(0x22), 0x00000004 }, \ + { AR5K_RF_GAIN(0x23), 0x00000044 }, \ + { AR5K_RF_GAIN(0x24), 0x00000084 }, \ + { AR5K_RF_GAIN(0x25), 0x00000013 }, \ + { AR5K_RF_GAIN(0x26), 0x00000012 }, \ + { AR5K_RF_GAIN(0x27), 0x00000052 }, \ + { AR5K_RF_GAIN(0x28), 0x00000092 }, \ + { AR5K_RF_GAIN(0x29), 0x000000d2 }, \ + { AR5K_RF_GAIN(0x2a), 0x0000002b }, \ + { AR5K_RF_GAIN(0x2b), 0x0000002a }, \ + { AR5K_RF_GAIN(0x2c), 0x0000006a }, \ + { AR5K_RF_GAIN(0x2d), 0x000000aa }, \ + { AR5K_RF_GAIN(0x2e), 0x0000001b }, \ + { AR5K_RF_GAIN(0x2f), 0x0000001a }, \ + { AR5K_RF_GAIN(0x30), 0x0000005a }, \ + { AR5K_RF_GAIN(0x31), 0x0000009a }, \ + { AR5K_RF_GAIN(0x32), 0x000000da }, \ + { AR5K_RF_GAIN(0x33), 0x00000006 }, \ + { AR5K_RF_GAIN(0x34), 0x00000006 }, \ + { AR5K_RF_GAIN(0x35), 0x00000006 }, \ + { AR5K_RF_GAIN(0x36), 0x00000006 }, \ + { AR5K_RF_GAIN(0x37), 0x00000006 }, \ + { AR5K_RF_GAIN(0x38), 0x00000006 }, \ + { AR5K_RF_GAIN(0x39), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3a), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3b), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3c), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3d), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3e), 0x00000006 }, \ + { AR5K_RF_GAIN(0x3f), 0x00000006 }, \ + /* PHY activation */ \ + { AR5K_PHY(53), 0x00000020 }, \ + { AR5K_PHY(51), 0x00000004 }, \ + { AR5K_PHY(50), 0x00060106 }, \ + { AR5K_PHY(39), 0x0000006d }, \ + { AR5K_PHY(48), 0x00000000 }, \ + { AR5K_PHY(52), 0x00000014 }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \ +} + +struct ath5k_ar5210_ini_mode{ + u_int16_t mode_register; + u_int32_t mode_base, mode_turbo; +}; + +#define AR5K_AR5210_INI_MODE(_aifs) { \ + { AR5K_SLOT_TIME, \ + AR5K_INIT_SLOT_TIME, \ + AR5K_INIT_SLOT_TIME_TURBO }, \ + { AR5K_SLOT_TIME, \ + AR5K_INIT_ACK_CTS_TIMEOUT, \ + AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \ + { AR5K_USEC_5210, \ + AR5K_INIT_TRANSMIT_LATENCY, \ + AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \ + { AR5K_IFS0, \ + ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ + << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS, \ + ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \ + << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \ + { AR5K_IFS1, \ + AR5K_INIT_PROTO_TIME_CNTRL, \ + AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ + { AR5K_PHY(17), \ + (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x1C, \ + (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ + { AR5K_PHY_FRAME_CTL_5210, \ + AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ + AR5K_PHY_FRAME_CTL_TXURN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ + AR5K_PHY_FRAME_CTL_PARITY_ERR | \ + AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x1020, \ + AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ + AR5K_PHY_FRAME_CTL_TXURN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ + AR5K_PHY_FRAME_CTL_PARITY_ERR | \ + /*PHY_TURBO is PHY_FRAME_CTL on 5210*/ \ + AR5K_PHY_TURBO_MODE | \ + AR5K_PHY_TURBO_SHORT | \ + AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x2020 }, \ +} + #define AR5K_AR5211_INI { \ { 0x000c, 0x00000000 }, \ { 0x0028, 0x84849c9c }, \ @@ -1523,7 +1807,7 @@ { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \ { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \ { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \ - /* AR5111 specific */ \ + /* RF5111 specific */ \ { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \ { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \ { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \ @@ -1586,7 +1870,7 @@ { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \ { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \ { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \ - /* AR5112 specific */ \ + /* RF5112 specific */ \ { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \ { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \ { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \ Index: ath5k.h =================================================================== --- ath5k.h (revision 2284) +++ ath5k.h (revision 2363) @@ -139,9 +139,9 @@ /*PHY Chips*/ enum ath5k_radio { - AR5K_AR5110 = 0, - AR5K_AR5111 = 1, - AR5K_AR5112 = 2, + AR5K_RF5110 = 0, + AR5K_RF5111 = 1, + AR5K_RF5112 = 2, }; /* @@ -243,7 +243,8 @@ AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery queue*/ } AR5K_TX_QUEUE; -#define AR5K_NUM_TX_QUEUES 10 +#define AR5K_NUM_TX_QUEUES 10 +#define AR5K_NUM_TX_QUEUES_NOQCU 2 /* * Queue syb-types to classify normal data queues. @@ -262,17 +263,19 @@ /* * Queue ID numbers as returned by the HAL, each number * represents a hw queue. If hw does not support hw queues - * (eg 5210/5211) all data goes in one queue. These match + * (eg 5210) all data goes in one queue. These match * d80211 definitions (net80211/MadWiFi don't use them). */ typedef enum { - AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ - AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ - AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ - AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ - AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ - AR5K_TX_QUEUE_ID_UAPSD = 8, - AR5K_TX_QUEUE_ID_XR_DATA = 9, + AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, + AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, + AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ + AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ + AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ + AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ + AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ + AR5K_TX_QUEUE_ID_UAPSD = 8, + AR5K_TX_QUEUE_ID_XR_DATA = 9, } AR5K_TX_QUEUE_ID; @@ -310,12 +313,12 @@ * These are not fully used inside OpenHAL yet */ typedef enum { - AR5K_PKT_TYPE_NORMAL = 0, - AR5K_PKT_TYPE_ATIM = 1, - AR5K_PKT_TYPE_PSPOLL = 2, - AR5K_PKT_TYPE_BEACON = 3, - AR5K_PKT_TYPE_PROBE_RESP = 4, - AR5K_PKT_TYPE_PIFS = 5, + AR5K_PKT_TYPE_NORMAL = 0, + AR5K_PKT_TYPE_ATIM = 1, + AR5K_PKT_TYPE_PSPOLL = 2, + AR5K_PKT_TYPE_BEACON = 3, + AR5K_PKT_TYPE_PROBE_RESP = 4, + AR5K_PKT_TYPE_PIFS = 5, } AR5K_PKT_TYPE; /* @@ -535,11 +538,11 @@ #define AR5K_RXDESC_INTREQ 0x0020 #define AR5K_TXDESC_CLRDMASK 0x0001 -#define AR5K_TXDESC_NOACK 0x0002 +#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ #define AR5K_TXDESC_RTSENA 0x0004 #define AR5K_TXDESC_CTSENA 0x0008 #define AR5K_TXDESC_INTREQ 0x0010 -#define AR5K_TXDESC_VEOL 0x0020 +#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ /* * 802.11 operating modes... @@ -964,7 +967,7 @@ _t AR5K_BOOL (_a _n##_reset)(struct ath_hal *, AR5K_OPMODE, AR5K_CHANNEL *, \ AR5K_BOOL change_channel, AR5K_STATUS *status); \ _t void (_a _n##_set_opmode)(struct ath_hal *); \ - _t AR5K_BOOL (_a _n##_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ + _t AR5K_BOOL (_a _n##_phy_calibrate)(struct ath_hal*, AR5K_CHANNEL *); \ /* Transmit functions */ \ _t AR5K_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, AR5K_BOOL level); \ _t int (_a _n##_setup_tx_queue)(struct ath_hal *, AR5K_TX_QUEUE, AR5K_TXQ_INFO *); \ @@ -1122,7 +1125,7 @@ u_int16_t ah_radio_2ghz_revision; enum ath5k_version ah_version; - enum ath5k_radio ah_radio; + enum ath5k_radio ah_radio; u_int32_t ah_phy; AR5K_BOOL ah_5ghz; @@ -1184,8 +1187,8 @@ * Prototypes */ -const char *ath_hal_probe(u_int16_t, u_int16_t); -struct ath_hal *ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG, +const char* ath_hal_probe(u_int16_t, u_int16_t); +struct ath_hal* ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc, AR5K_BUS_TAG, AR5K_BUS_HANDLE, AR5K_STATUS *); u_int16_t ath_hal_computetxtime(struct ath_hal *, const AR5K_RATE_TABLE *, u_int32_t, u_int16_t, AR5K_BOOL); @@ -1194,7 +1197,7 @@ AR5K_BOOL ath_hal_init_channels(struct ath_hal *, AR5K_CHANNEL *, u_int, u_int *, AR5K_CTRY_CODE, u_int16_t, AR5K_BOOL, AR5K_BOOL); -const char *ath5k_printver(enum ath5k_srev_type, u_int32_t); +const char* ath5k_printver(enum ath5k_srev_type, u_int32_t); void ath5k_radar_alert(struct ath_hal *); ieee80211_regdomain_t ath5k_regdomain_to_ieee(u_int16_t); u_int16_t ath5k_regdomain_from_ieee(ieee80211_regdomain_t); @@ -1213,24 +1216,28 @@ int ath5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); u_int16_t ath5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); -AR5K_BOOL ath5k_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_ar5110_channel(struct ath_hal *, AR5K_CHANNEL *); -u_int32_t ath5k_ar5110_chan2athchan(AR5K_CHANNEL *); -AR5K_BOOL ath5k_ar5111_channel(struct ath_hal *, AR5K_CHANNEL *); -AR5K_BOOL ath5k_ar5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); -AR5K_BOOL ath5k_ar5112_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ath5k_hw_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ath5k_hw_rf5110_channel(struct ath_hal *, AR5K_CHANNEL *); +u_int32_t ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *); +AR5K_BOOL ath5k_hw_rf5111_channel(struct ath_hal *, AR5K_CHANNEL *); +AR5K_BOOL ath5k_hw_rf5111_chan2athchan(u_int, struct ath5k_athchan_2ghz *); +AR5K_BOOL ath5k_hw_rf5112_channel(struct ath_hal *, AR5K_CHANNEL *); AR5K_BOOL ath5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); -AR5K_BOOL ath5k_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -AR5K_BOOL ath5k_ar5111_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -AR5K_BOOL ath5k_ar5112_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); -void ath5k_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int, u_int); -u_int ath5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, +AR5K_BOOL ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); +AR5K_BOOL ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); +AR5K_BOOL ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel); + +AR5K_BOOL ath5k_hw_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +AR5K_BOOL ath5k_hw_rf5111_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +AR5K_BOOL ath5k_hw_rf5112_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int); +void ath5k_hw_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL *, u_int, u_int); +u_int ath5k_hw_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, AR5K_BOOL); -u_int32_t ath5k_rfregs_gainf_corr(struct ath_hal *); -AR5K_BOOL ath5k_rfregs_gain_readback(struct ath_hal *); -int32_t ath5k_rfregs_gain_adjust(struct ath_hal *); -AR5K_BOOL ath5k_rfgain(struct ath_hal *, u_int, u_int); +u_int32_t ath5k_hw_rfregs_gainf_corr(struct ath_hal *); +AR5K_BOOL ath5k_hw_rfregs_gain_readback(struct ath_hal *); +int32_t ath5k_hw_rfregs_gain_adjust(struct ath_hal *); +AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); void ath5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); /*added*/