Index: ath5k_hw.c =================================================================== --- ath5k_hw.c (revision 2401) +++ ath5k_hw.c (revision 2419) @@ -1,4 +1,4 @@ -/* + /* * Copyright (c) 2004-2007 Reyk Floeter * Copyright (c) 2006-2007 Nick Kossifidis * @@ -275,9 +275,9 @@ inline void ath5k_hw_rtcopy(AR5K_RATE_TABLE *dst, const AR5K_RATE_TABLE *src) { - bzero(dst, sizeof(AR5K_RATE_TABLE)); + memset(dst, 0, sizeof(AR5K_RATE_TABLE)); dst->rate_count = src->rate_count; - bcopy(src->rates, dst->rates, sizeof(dst->rates)); + memcpy(dst->rates, src->rates, sizeof(dst->rates)); } /* @@ -332,7 +332,7 @@ break; else if ((data & flag) == val) break; - AR5K_DELAY(15); + udelay(15); } if (i <= 0) @@ -355,7 +355,7 @@ AR5K_BUS_HANDLE sh, AR5K_STATUS *status) { struct ath_hal *hal = NULL; - u_int8_t mac[IEEE80211_ADDR_LEN]; + u_int8_t mac[ETH_ALEN]; u_int8_t mac_version = 255; /*Initialize this to something else than ath5k_version*/ int i; u_int32_t srev; @@ -379,15 +379,14 @@ } /*If we passed the test malloc a hal struct*/ - if ((hal = malloc(sizeof(struct ath_hal), - M_DEVBUF, M_NOWAIT)) == NULL) { + if ((hal = kmalloc(sizeof(struct ath_hal), GFP_KERNEL)) == NULL) { *status = AR5K_ENOMEM; AR5K_PRINT("out of memory\n"); return (NULL); } /*Initialize it*/ - bzero(hal, sizeof(struct ath_hal)); + memset(hal, 0, sizeof(struct ath_hal)); hal->ah_sc = sc; hal->ah_st = st; @@ -474,10 +473,12 @@ hal->ah_phy = AR5K_PHY(0); - /*Is this bcopy O.K. ?*/ - bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); + /* Set MAC to bcast: ff:ff:ff:ff:ff:ff, this is using 'mac' as a + * temporary variable for setting our BSSID. Right bellow we update + * it with ath5k_hw_get_lladdr() */ + memset(mac, 0xff, ETH_ALEN); + ath5k_hw_set_associd(hal, mac, 0); - ath5k_hw_set_associd(hal, mac, 0); ath5k_hw_get_lladdr(hal, mac); ath5k_hw_set_opmode(hal); @@ -549,7 +550,7 @@ return (hal); failed: - free(hal, M_DEVBUF); + kfree(hal); return (NULL); } @@ -626,7 +627,7 @@ return (FALSE); } - AR5K_DELAY(1000); + udelay(1000); } /* ...wakeup */ @@ -646,7 +647,7 @@ return (FALSE); } - AR5K_DELAY(1000); + udelay(1000); } /* ...reset chipset and PCI device */ @@ -657,7 +658,7 @@ } if (hal->ah_version == AR5K_AR5210) - AR5K_DELAY(2300); + udelay(2300); /* ...wakeup */ if (ath5k_hw_set_power(hal, @@ -675,7 +676,7 @@ if (hal->ah_version != AR5K_AR5210){ /* ...set the PHY operating mode */ AR5K_REG_WRITE(AR5K_PHY_PLL, clock); - AR5K_DELAY(300); + udelay(300); AR5K_REG_WRITE(AR5K_PHY_MODE, mode); AR5K_REG_WRITE(AR5K_PHY_TURBO, turbo); @@ -710,7 +711,7 @@ return (0); } - AR5K_DELAY(2000); + udelay(2000); /* ...wait until PHY is ready and read the selected radio revision */ AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16); @@ -771,12 +772,12 @@ AR5K_TRACE; if (hal->ah_rf_banks != NULL) - free(hal->ah_rf_banks, M_DEVBUF); + kfree(hal->ah_rf_banks); /* * Free HAL structure, assume interrupts are down */ - free(hal, M_DEVBUF); + kfree(hal); } @@ -794,7 +795,7 @@ AR5K_BOOL change_channel, AR5K_STATUS *status) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - u_int8_t mac[IEEE80211_ADDR_LEN]; + u_int8_t mac[ETH_ALEN]; u_int32_t data, noise_floor, s_seq, s_ant, s_led[3]; u_int i, phy, mode, freq, off, ee_mode, ant[2]; const AR5K_RATE_TABLE *rt; @@ -1011,7 +1012,7 @@ return (FALSE); } - AR5K_DELAY(1000); + udelay(1000); /* * Set rate duration table on 5212 @@ -1186,10 +1187,10 @@ } } else { - AR5K_DELAY(1000); + udelay(1000); /* Disable phy and wait */ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE); - AR5K_DELAY(1000); + udelay(1000); } /* @@ -1207,12 +1208,18 @@ /* * Misc */ - bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); + memset(mac, 0xff, ETH_ALEN); ath5k_hw_set_associd(hal, mac, 0); ath5k_hw_set_opmode(hal); /*PISR/SISR Not available on 5210*/ if (hal->ah_version != AR5K_AR5210) { AR5K_REG_WRITE(AR5K_PISR, 0xffffffff); + /* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so + * direct write using AR5K_REG_WRITE seems wrong. Test with: + * AR5K_REG_WRITE_BITS(AR5K_RSSI_THR, + * AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES); + * with different variables and check results compared + * to AR5K_REG_WRITE() */ AR5K_REG_WRITE(AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES); } @@ -1248,9 +1255,9 @@ data = (channel->channel_flags & CHANNEL_CCK) ? ((data << 2) / 22) : (data / 10); - AR5K_DELAY(100 + data); + udelay(100 + data); } else { - AR5K_DELAY(1000); + udelay(1000); } /* @@ -1281,7 +1288,7 @@ /* Wait until the noise floor is calibrated */ for (i = 20; i > 0; i--) { - AR5K_DELAY(1000); + udelay(1000); noise_floor = AR5K_REG_READ(AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & @@ -1385,7 +1392,7 @@ AR5K_REG_WRITE(AR5K_RESET_CTL, val); /* Wait at least 128 PCI clocks */ - AR5K_DELAY(15); + udelay(15); if (hal->ah_version == AR5K_AR5210) { val &= AR5K_RESET_CTL_CHIP; @@ -1459,7 +1466,7 @@ break; /* Wait a bit and retry */ - AR5K_DELAY(200); + udelay(200); AR5K_REG_WRITE(AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLE_WAKE); } @@ -1532,7 +1539,7 @@ for (i = 2000; i > 0 && (AR5K_REG_READ(AR5K_CR) & AR5K_CR_RXE) != 0; i--) - AR5K_DELAY(10); + udelay(10); return (i > 0 ? TRUE : FALSE); } @@ -1660,7 +1667,7 @@ do { pending = AR5K_REG_READ(AR5K_QUEUE_STATUS(queue)) & AR5K_QCU_STS_FRMPENDCNT; - AR5K_DELAY(100); + udelay(100); } while (--i && pending); /* Clear register */ @@ -2047,7 +2054,7 @@ (AR5K_REG_READ(AR5K_EEPROM_DATA) & 0xffff); return (0); } - AR5K_DELAY(15); + udelay(15); } return (ETIMEDOUT); @@ -2097,7 +2104,7 @@ return (EIO); return (0); } - AR5K_DELAY(15); + udelay(15); } #endif AR5K_PRINTF("EEPROM Write is disabled!"); @@ -2477,10 +2484,10 @@ u_int32_t total, offset; u_int16_t data; int octet; - u_int8_t mac_d[IEEE80211_ADDR_LEN]; + u_int8_t mac_d[ETH_ALEN]; - bzero(mac, IEEE80211_ADDR_LEN); - bzero(&mac_d, IEEE80211_ADDR_LEN); + memset(mac, 0, ETH_ALEN); + memset(&mac_d, 0, ETH_ALEN); if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) return (AR5K_EIO); @@ -2496,7 +2503,7 @@ octet += 2; } - bcopy(mac_d, mac, IEEE80211_ADDR_LEN); + memcpy(mac, mac_d, ETH_ALEN); if ((!total) || total == (3 * 0xffff)) return (AR5K_EINVAL); @@ -2716,7 +2723,7 @@ ath5k_hw_get_lladdr(struct ath_hal *hal, u_int8_t *mac) { AR5K_TRACE; - bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); + memcpy(mac, hal->ah_sta_id, ETH_ALEN); } /* @@ -2729,7 +2736,7 @@ AR5K_TRACE; /* Set new station ID */ - bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); + memcpy(hal->ah_sta_id, mac, ETH_ALEN); low_id = AR5K_LOW_ID(mac); high_id = AR5K_HIGH_ID(mac); @@ -2766,7 +2773,7 @@ AR5K_REG_WRITE(AR5K_BSS_ID0, low_id); AR5K_REG_WRITE(AR5K_BSS_ID1, high_id | ((assoc_id & 0x3fff) << AR5K_BSS_ID1_AID_S)); - bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN); + memcpy(&hal->ah_bssid, bssid, ETH_ALEN); if (assoc_id == 0) { ath5k_hw_disable_pspoll(hal); @@ -3109,13 +3116,12 @@ /* * Write new beacon miss threshold, if it appears to be valid - * XXX: < or <= ? + * XXX: Figure out right values for min <= bs_bmiss_threshold <= max + * and return if its not in range. We can test this by reading value and + * setting value to a largest value and seeing which values register. */ - if ((AR5K_RSSI_THR_BMISS >> AR5K_RSSI_THR_BMISS_S) < - state->bs_bmiss_threshold) - return; - AR5K_REG_WRITE_BITS(AR5K_RSSI_THR_M, + AR5K_REG_WRITE_BITS(AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, state->bs_bmiss_threshold); /* @@ -3406,30 +3412,30 @@ AR5K_TRACE; AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - bzero(&key_v, sizeof(key_v)); + memset(&key_v, 0, sizeof(key_v)); switch (keyval->wk_len) { case AR5K_KEYVAL_LENGTH_40: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 1); + memcpy(&key_v[0], keyval->wk_key, 4); + memcpy(&key_v[1], keyval->wk_key + 4, 1); key_v[5] = AR5K_KEYTABLE_TYPE_40; break; case AR5K_KEYVAL_LENGTH_104: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 1); + memcpy(&key_v[0], keyval->wk_key, 4); + memcpy(&key_v[1], keyval->wk_key + 4, 2); + memcpy(&key_v[2], keyval->wk_key + 6, 4); + memcpy(&key_v[3], keyval->wk_key + 10, 2); + memcpy(&key_v[4], keyval->wk_key + 12, 1); key_v[5] = AR5K_KEYTABLE_TYPE_104; break; case AR5K_KEYVAL_LENGTH_128: - bcopy(keyval->wk_key, &key_v[0], 4); - bcopy(keyval->wk_key + 4, &key_v[1], 2); - bcopy(keyval->wk_key + 6, &key_v[2], 4); - bcopy(keyval->wk_key + 10, &key_v[3], 2); - bcopy(keyval->wk_key + 12, &key_v[4], 4); + memcpy(&key_v[0], keyval->wk_key, 4); + memcpy(&key_v[1], keyval->wk_key + 4, 2); + memcpy(&key_v[2], keyval->wk_key + 6, 4); + memcpy(&key_v[3], keyval->wk_key + 10, 2); + memcpy(&key_v[4], keyval->wk_key + 12, 4); key_v[5] = AR5K_KEYTABLE_TYPE_128; break; @@ -3449,20 +3455,22 @@ const u_int8_t *mac) { u_int32_t low_id, high_id; - const u_int8_t *mac_v; AR5K_TRACE; - /* - * Invalid entry (key table overflow) - */ + /* Invalid entry (key table overflow) */ AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); - /* MAC may be NULL if it's a broadcast key */ - mac_v = mac == NULL ? etherbroadcastaddr : mac; + /* MAC may be NULL if it's a broadcast key. In this case no need to + * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ + if(unlikely(mac == NULL)) { + low_id = 0xffffffff; + high_id = 0xffff | AR5K_KEYTABLE_VALID; + } + else { + low_id = AR5K_LOW_ID(mac); + high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID; + } - low_id = AR5K_LOW_ID(mac_v); - high_id = AR5K_HIGH_ID(mac_v) | AR5K_KEYTABLE_VALID; - AR5K_REG_WRITE(AR5K_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE(AR5K_KEYTABLE_MAC1(entry), high_id); @@ -3535,7 +3543,7 @@ /* * Setup internal queue structure */ - bzero(&hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + memset(&hal->ah_txq[queue], 0, sizeof(AR5K_TXQ_INFO)); hal->ah_txq[queue].tqi_type = queue_type; if (queue_info != NULL) { @@ -3567,7 +3575,7 @@ if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) return (FALSE); - bcopy(queue_info, &hal->ah_txq[queue], sizeof(AR5K_TXQ_INFO)); + memcpy(&hal->ah_txq[queue], queue_info, sizeof(AR5K_TXQ_INFO)); /*XXX: Is this supported on 5210 ?*/ if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && @@ -4115,7 +4123,7 @@ tx_desc = (struct ath5k_hw_2w_tx_desc*)&desc->ds_ctl0; /* Clear status descriptor */ - bzero(desc->ds_hw, sizeof(desc->ds_hw)); + memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & @@ -4148,7 +4156,7 @@ tx_status = (struct ath5k_hw_tx_status*)&desc->ds_hw[2]; /* Clear status descriptor */ - bzero(tx_status, sizeof(struct ath5k_hw_tx_status)); + memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status)); /* Validate segment length and initialize the descriptor */ if ((tx_desc->tx_control_1 = (segment_length & @@ -4335,7 +4343,7 @@ * most of them virtual, after some secs * of scanning system hangs. M.F. */ - bzero(desc->ds_hw, sizeof(desc->ds_hw)); + memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); /*Initialize rx descriptor*/ rx_desc->rx_control_0 = 0; @@ -4772,8 +4780,8 @@ AR5K_CHANNEL *all_channels; AR5K_CTRY_CODE country_current; - if ((all_channels = malloc(sizeof(AR5K_CHANNEL) * max_channels, - M_TEMP, M_NOWAIT)) == NULL) + if ((all_channels = kmalloc(sizeof(AR5K_CHANNEL) * max_channels, + GFP_KERNEL)) == NULL) return (FALSE); i = c = 0; @@ -4896,9 +4904,9 @@ } done: - bcopy(all_channels, channels, sizeof(AR5K_CHANNEL) * max_channels); + memcpy(channels, all_channels, sizeof(AR5K_CHANNEL) * max_channels); *channels_size = c; - free(all_channels, M_TEMP); + kfree(all_channels); return (TRUE); } @@ -5049,7 +5057,7 @@ data = ath5k_hw_rf5110_chan2athchan(channel); AR5K_PHY_WRITE(0x27, data); AR5K_PHY_WRITE(0x30, 0); - AR5K_DELAY(1000); + udelay(1000); return (TRUE); } @@ -5203,7 +5211,7 @@ #define AGC_DISABLE { \ AR5K_REG_ENABLE_BITS(AR5K_PHY_AGC, \ AR5K_PHY_AGC_DISABLE); \ - AR5K_DELAY(10); \ + udelay(10); \ } #define AGC_ENABLE { \ @@ -5219,7 +5227,7 @@ beacon = AR5K_REG_READ(AR5K_BEACON_5210); AR5K_REG_WRITE(AR5K_BEACON_5210, beacon & ~AR5K_BEACON_ENABLE); - AR5K_DELAY(2300); + udelay(2300); /* * Set the channel (with AGC turned off) @@ -5231,7 +5239,7 @@ * Activate PHY and wait */ AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE); - AR5K_DELAY(1000); + udelay(1000); AGC_ENABLE; @@ -5264,13 +5272,13 @@ AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR)); - AR5K_DELAY(20); + udelay(20); AGC_DISABLE; AR5K_REG_WRITE(AR5K_PHY_RFSTG, AR5K_PHY_RFSTG_DISABLE); AGC_ENABLE; - AR5K_DELAY(1000); + udelay(1000); /* * Enable calibration and wait until completion @@ -5308,7 +5316,7 @@ /* Wait until the noise floor is calibrated */ for (i = 20; i > 0; i--) { - AR5K_DELAY(1000); + udelay(1000); noise_floor = AR5K_REG_READ(AR5K_PHY_NF); if (AR5K_PHY_NF_RVAL(noise_floor) & @@ -5627,8 +5635,8 @@ if (hal->ah_rf_banks == NULL) { /* XXX do extra checks? */ - if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, - M_DEVBUF, M_NOWAIT)) == NULL) { + if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size, + GFP_KERNEL)) == NULL) { AR5K_PRINT("out of memory\n"); return (FALSE); } @@ -5848,7 +5856,7 @@ u_int32_t ob, db, obdb, xpds, xpdp, x_gain; u_int i; - bcopy(ar5211_rf, rf, sizeof(rf)); + memcpy(rf, ar5211_rf, sizeof(rf)); obdb = 0; if (freq == AR5K_INI_RFGAIN_2GHZ && @@ -6028,7 +6036,7 @@ } /* Reset TX power values */ - bzero(&hal->ah_txpower, sizeof(hal->ah_txpower)); + memset(&hal->ah_txpower, 0, sizeof(hal->ah_txpower)); hal->ah_txpower.txp_tpc = tpc; /* Initialize TX power table */ Index: ath5k_hw.h =================================================================== --- ath5k_hw.h (revision 2401) +++ ath5k_hw.h (revision 2419) @@ -198,7 +198,7 @@ */ /*Swap RX/TX Descriptor for big endian archs*/ -#if BYTE_ORDER == BIG_ENDIAN +#if defined(__BIG_ENDIAN) #define AR5K_INIT_CFG ( \ AR5K_CFG_SWTD | AR5K_CFG_SWRD \ ) @@ -216,6 +216,11 @@ #define AR5K_REG_MS(_val, _flags) \ (((_val) & (_flags)) >> _flags##_S) +/* Some registers can hold multiple values of interest. For this + * reason when we want to write to these registers we must first + * retrieve the values which we do not want to clear (lets call this + * old_data) and then set the register with this and our new_value: + * ( old_data | new_value) */ #define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ (((_val) << _flags##_S) & (_flags))) @@ -237,7 +242,7 @@ #define AR5K_REG_WAIT(_i) \ if (_i % 64) \ - AR5K_DELAY(1); + udelay(1); #define AR5K_EEPROM_READ(_o, _v) { \ if ((ret = hal->ah_eeprom_read(hal, (_o), \ Index: ath5k.h =================================================================== --- ath5k.h (revision 2401) +++ ath5k.h (revision 2419) @@ -118,26 +118,16 @@ /* token to use for aifs, cwmin, cwmax in MadWiFi */ #define AR5K_TXQ_USEDEFAULT ((u_int32_t) -1) -#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ -#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ -static const u_char etherbroadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; -//#define etherbroadcastaddr 0xff +/* GENERIC CHIPSET DEFINITIONS */ - - - -/*****************************\ - GENERIC CHIPSET DEFINITIONS -\*****************************/ - -/* MAC Chips*/ +/* MAC Chips */ enum ath5k_version { AR5K_AR5210 = 0, AR5K_AR5211 = 1, AR5K_AR5212 = 2, }; -/*PHY Chips*/ +/* PHY Chips */ enum ath5k_radio { AR5K_RF5110 = 0, AR5K_RF5111 = 1, @@ -1146,8 +1136,8 @@ u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; AR5K_BOOL ah_ant_diversity; - u_int8_t ah_sta_id[IEEE80211_ADDR_LEN]; - u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; + u_int8_t ah_sta_id[ETH_ALEN]; + u_int8_t ah_bssid[ETH_ALEN]; u_int32_t ah_gpio[AR5K_MAX_GPIO]; int ah_gpio_npins; Index: ah_osdep.h =================================================================== --- ah_osdep.h (revision 2401) +++ ah_osdep.h (revision 2419) @@ -46,22 +46,6 @@ #define bus_space_tag_t AR5K_BUS_TAG #define bus_space_handle_t AR5K_BUS_HANDLE - /* - * Linux uses __BIG_ENDIAN and __LITTLE_ENDIAN while BSD uses _foo - * and an explicit _BYTE_ORDER. Sorry, BSD got there first--define - * things in the BSD way... - */ -#define LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ -#define BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */ - -#if defined(__LITTLE_ENDIAN) -#define BYTE_ORDER LITTLE_ENDIAN -#elif defined(__BIG_ENDIAN) -#define BYTE_ORDER BIG_ENDIAN -#else -#error "Please fix asm/byteorder.h" -#endif - #define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) #define AR5K_PRINT(fmt) printk("%s: " fmt, __func__) #ifdef AR5K_DEBUG @@ -69,14 +53,3 @@ #else #define AR5K_TRACE #endif -#define AR5K_DELAY(_n) udelay(_n) -#define malloc(_a, _b, _c) kmalloc(_a, GFP_KERNEL) -#define free(_a, _b) kfree(_a) -#define bcopy(_a, _b, _c) memcpy(_b, _a, _c) -#define bzero(_a, _b) memset(_a, 0, _b) - -//#define AR5K_REG_WRITE(_reg, _val) (writel(_val, hal->ah_sh + (_reg))) -// bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val)) - -//#define AR5K_REG_READ(_reg) (readl(hal->ah_sh + (_reg))) -// bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg))