Index: ath5k_hw.c =================================================================== --- ath5k_hw.c (revision 2439) +++ ath5k_hw.c (revision 2441) @@ -1581,6 +1581,10 @@ AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + /* Return if queue is declared inactive */ + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (FALSE); + if (hal->ah_version == AR5K_AR5210) { tx_queue = AR5K_REG_READ(AR5K_CR); @@ -1635,6 +1639,10 @@ AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + /* Return if queue is declared inactive */ + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (FALSE); + if (hal->ah_version == AR5K_AR5210) { tx_queue = AR5K_REG_READ(AR5K_CR); @@ -2870,7 +2878,7 @@ } /* - * Clear Multicast filter + * Clear Multicast filter by index */ AR5K_BOOL ath5k_hw_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) @@ -3787,7 +3795,7 @@ AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL) | + AR5K_DCU_MISC_ARBLOCK_CTL_S) | AR5K_DCU_MISC_POST_FR_BKOFF_DIS | AR5K_DCU_MISC_BCN_ENABLE); @@ -3807,7 +3815,7 @@ AR5K_REG_ENABLE_BITS(AR5K_QUEUE_DFS_MISC(queue), (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << - AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL)); + AR5K_DCU_MISC_ARBLOCK_CTL_S)); break; case AR5K_TX_QUEUE_UAPSD: @@ -3844,6 +3852,11 @@ AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); + /* Return if queue is declared inactive */ + if (hal->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) + return (FALSE); + + /* XXX: How about AR5K_CFG_TXCNT ? */ if (hal->ah_version == AR5K_AR5210) return (FALSE); @@ -3964,7 +3977,7 @@ _TX_FLAGS(0, VEOL); _TX_FLAGS(0, INTREQ); _TX_FLAGS(0, RTSENA); - _TX_FLAGS(1, NOACK); /*???*/ + _TX_FLAGS(1, NOACK); #undef _TX_FLAGS @@ -4044,7 +4057,7 @@ _TX_FLAGS(0, INTREQ); _TX_FLAGS(0, RTSENA); _TX_FLAGS(0, CTSENA); - _TX_FLAGS(1, NOACK); /*???*/ + _TX_FLAGS(1, NOACK); #undef _TX_FLAGS Index: ath5kreg.h =================================================================== --- ath5kreg.h (revision 2439) +++ ath5kreg.h (revision 2441) @@ -90,10 +90,10 @@ #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (?) */ -#define AR5K_CFG_TXCNT 0x00007800 /* [5210] */ +#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ #define AR5K_CFG_TXCNT_S 11 -#define AR5K_CFG_TXFSTAT 0x00008000 /* [5210] */ -#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210 */ +#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ +#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ #define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ #define AR5K_CFG_PCI_THRES_S 17