Index: ath5k_hw.c =================================================================== --- ath5k_hw.c (revision 2502) +++ ath5k_hw.c (revision 2524) @@ -23,9 +23,10 @@ */ #include "ah_devid.h" +#include "ath5kreg.h" #include "ath5k.h" -#include "ath5kreg.h" + /* * Known pci ids */ @@ -79,6 +80,7 @@ u_int16_t ath5k_hw_radio_revision(struct ath_hal *, AR5K_CHIP); void ath5k_hw_fill(struct ath_hal *); AR5K_BOOL ath5k_hw_txpower(struct ath_hal *, AR5K_CHANNEL *, u_int); +const char * ath5k_hw_get_part_name(enum ath5k_srev_type, u_int32_t); AR5K_HAL_FUNCTIONS(extern, ath5k_hw,); @@ -93,11 +95,15 @@ /* * Initial register dumps */ -static const struct ath5k_ar5212_ini ar5212_ini[] = AR5K_AR5212_INI; +static const struct ath5k_ini ar5212_ini[] = AR5K_AR5212_INI; +static const struct ath5k_ini ar5212_rf5111_ini[] = AR5K_AR5212_RF5111_INI; +static const struct ath5k_ini ar5212_rf5112_ini[] = AR5K_AR5212_RF5112_INI; static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE; + static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI; static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE; static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF; + static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI; /* @@ -107,11 +113,13 @@ static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT; /* - * Initial register for the radio chipsets + * Initial register settings for the radio chipsets */ +/* RF Banks */ static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF; static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF; static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF; +/* Common (5111/5112) rf gain table */ static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; /* @@ -128,7 +136,7 @@ /* * Perform a lookup if the device is supported by the HAL * and return the chip name. - * TODO:Left here for combatibility, change it in at5k + * TODO:Left here for combatibility, change it in ath5k */ const char * ath_hal_probe(u_int16_t vendor, u_int16_t device) @@ -341,8 +349,37 @@ return (TRUE); } +/* + * Write initial register dump + */ +static void +ath5k_hw_ini_registers(struct ath_hal *hal, int size, + const struct ath5k_ini *ini_regs, AR5K_BOOL change_channel) +{ + int i; + /* Write initial registers */ + for (i = 0; i < size ; i++) { + if (change_channel == TRUE && + ini_regs[i].ini_register >= AR5K_PCU_MIN && + ini_regs[i].ini_register <= AR5K_PCU_MAX) + continue; + switch (ini_regs[i].ini_mode) { + case AR5K_INI_READ: + /* Cleared on read */ + AR5K_REG_READ(ini_regs[i].ini_register); + break; + case AR5K_INI_WRITE: + default: + AR5K_REG_WAIT(i); + AR5K_REG_WRITE(ini_regs[i].ini_register, + ini_regs[i].ini_value); + } + } +} + + /***************************************\ Attach/Detach Functions \***************************************/ @@ -356,12 +393,12 @@ { struct ath_hal *hal = NULL; u_int8_t mac[ETH_ALEN]; - u_int8_t mac_version = 255; /*Initialize this to something else than ath5k_version*/ + u_int8_t mac_version = 255; /* Initialize this to something else than ath5k_version */ int i; u_int32_t srev; *status = AR5K_EINVAL; - /*TODO:Use eeprom_magic to verify chipset*/ + /* TODO:Use eeprom_magic to verify chipset */ /* * Check if device is a known one @@ -371,14 +408,14 @@ mac_version = ath5k_known_products[i].mac_version; } - /*If there wasn't a match, the device is not supported*/ + /* If there wasn't a match, the device is not supported */ if (mac_version == 255) { *status = AR5K_ENOTSUPP; AR5K_PRINTF("device not supported: 0x%04x\n", device); return (NULL); } - /*If we passed the test malloc a hal struct*/ + /* If we passed the test malloc a hal struct */ if ((hal = kmalloc(sizeof(struct ath_hal), GFP_KERNEL)) == NULL) { *status = AR5K_ENOMEM; AR5K_PRINT("out of memory\n"); @@ -547,6 +584,12 @@ *status = AR5K_OK; + printk(KERN_INFO "ath_hal: Atheros HW found \n"); + printk(KERN_INFO "ath_hal: MAC version: %s\n", + ath5k_hw_get_part_name(AR5K_VERSION_VER,hal->ah_mac_srev)); + printk(KERN_INFO "ath_hal: PHY version: %s\n", + ath5k_hw_get_part_name(AR5K_VERSION_RAD,hal->ah_radio_5ghz_revision)); + return (hal); failed: @@ -597,7 +640,7 @@ } else if (flags & CHANNEL_G) { /* Dynamic OFDM/CCK is not supported by the AR5211 */ if (hal->ah_version == AR5K_AR5211) { - mode |= AR5K_PHY_MODE_MOD_OFDM; + mode |= AR5K_PHY_MODE_MOD_CCK; } else { mode |= AR5K_PHY_MODE_MOD_DYN; } @@ -944,61 +987,27 @@ } /* - * Write initial register settings - * TODO:Do this in a common way + * Initial register dump common for all modes */ - /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) { - if (change_channel == TRUE && - ar5212_ini[i].ini_register >= AR5K_PCU_MIN && - ar5212_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - - if ((hal->ah_radio == AR5K_RF5111 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5111) || - (hal->ah_radio == AR5K_RF5112 && - ar5212_ini[i].ini_flags & AR5K_INI_FLAG_5112)) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_ini[i].ini_register, - ar5212_ini[i].ini_value); - } + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5212_ini), + ar5212_ini, change_channel); + if (hal->ah_radio == AR5K_RF5112) { + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5212_rf5112_ini), + ar5212_rf5112_ini, change_channel); + } else if (hal->ah_radio == AR5K_RF5111) { + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5212_rf5111_ini), + ar5212_rf5111_ini, change_channel); } + } else if (hal->ah_version == AR5K_AR5211) { + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5211_ini), + ar5211_ini, change_channel); + } else if (hal->ah_version == AR5K_AR5210) { + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5210_ini), + ar5210_ini, change_channel); } - /*For 5211*/ - if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { - if (change_channel == TRUE && - ar5211_ini[i].ini_register >= AR5K_PCU_MIN && - ar5211_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, - ar5211_ini[i].ini_value); - } - } - /*For 5210*/ - if (hal->ah_version == AR5K_AR5210) - for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) { - if (change_channel == TRUE && - ar5210_ini[i].ini_register >= AR5K_PCU_MIN && - ar5210_ini[i].ini_register <= AR5K_PCU_MAX) - continue; - switch (ar5210_ini[i].ini_mode) { - case AR5K_INI_READ: - /* Cleared on read */ - AR5K_REG_READ(ar5210_ini[i].ini_register); - break; - - case AR5K_INI_WRITE: - default: - AR5K_REG_WRITE(ar5210_ini[i].ini_register, - ar5210_ini[i].ini_value); - } - } - /* * 5211/5212 Specific */ @@ -4797,9 +4806,11 @@ AR5K_CHANNEL *all_channels; AR5K_CTRY_CODE country_current; + /* Allocate and initialize channel array */ if ((all_channels = kmalloc(sizeof(AR5K_CHANNEL) * max_channels, GFP_KERNEL)) == NULL) return (FALSE); + memset(all_channels, 0, sizeof(AR5K_CHANNEL) * max_channels); i = c = 0; domain_current = hal->ah_regdomain; @@ -5068,8 +5079,8 @@ * Set the channel and wait */ data = ath5k_hw_rf5110_chan2athchan(channel); - AR5K_PHY_WRITE(0x27, data); - AR5K_PHY_WRITE(0x30, 0); + AR5K_REG_WRITE(AR5K_RF_BUFFER, data); + AR5K_REG_WRITE(AR5K_RF_BUFFER_CONTROL_0, 0); udelay(1000); return (TRUE); @@ -5142,8 +5153,8 @@ | (clock << 1) | (1 << 10) | 1; } - AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); - AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); + AR5K_REG_WRITE(AR5K_RF_BUFFER, (data1 & 0xff) | ((data0 & 0xff) << 8)); + AR5K_REG_WRITE(AR5K_RF_BUFFER_CONTROL_3, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); return (TRUE); } @@ -5190,8 +5201,8 @@ data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; - AR5K_PHY_WRITE(0x27, data & 0xff); - AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); + AR5K_REG_WRITE(AR5K_RF_BUFFER, data & 0xff); + AR5K_REG_WRITE(AR5K_RF_BUFFER_CONTROL_5, (data >> 8) & 0x7f); return (TRUE); } @@ -5695,6 +5706,7 @@ rf[i] = rf5111_rf[i].rf_value[mode]; } + /* Modify bank 0 */ if (channel->channel_flags & CHANNEL_2GHZ) { if (channel->channel_flags & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; @@ -5711,6 +5723,7 @@ return (FALSE); obdb = 1; + /* Modify bank 6 */ } else { /* For 11a, Turbo and XR */ ee_mode = AR5K_EEPROM_MODE_11A; @@ -5744,6 +5757,7 @@ obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE)) return (FALSE); + /* Modify bank 7 */ if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE)) return (FALSE); @@ -5802,6 +5816,7 @@ rf[i] = rf_ini[i].rf_value[mode]; } + /* Modify bank 6 */ if (channel->channel_flags & CHANNEL_2GHZ) { if (channel->channel_flags & CHANNEL_B) ee_mode = AR5K_EEPROM_MODE_11B; @@ -5844,6 +5859,7 @@ ee->ee_xpd[ee_mode], 1, 302, 0, TRUE)) return (FALSE); + /* Modify bank 7 */ if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7], ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE)) return (FALSE); @@ -6385,8 +6401,8 @@ return (FALSE); } -const char * /*O.K. - TODO:Get rid of this*/ -ath5k_printver(enum ath5k_srev_type type, u_int32_t val) +const char * +ath5k_hw_get_part_name(enum ath5k_srev_type type, u_int32_t val) { struct ath5k_srev_name names[] = AR5K_SREV_NAME; const char *name = "xxxx"; Index: ath5kreg.h =================================================================== --- ath5kreg.h (revision 2502) +++ ath5kreg.h (revision 2524) @@ -1663,7 +1663,7 @@ #define AR5K_PHY_ACT_DISABLE 0x00000002 /* - * PHY signal register [5110] + * PHY signal register */ #define AR5K_PHY_SIG 0x9858 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 @@ -1672,7 +1672,7 @@ #define AR5K_PHY_SIG_FIRPWR_S 18 /* - * PHY coarse agility control register [5110] + * PHY coarse agility control register */ #define AR5K_PHY_AGCCOARSE 0x985c #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 @@ -1717,7 +1717,7 @@ #define AR5K_PHY_SCAL_32MHZ 0x0000000e /* - * PHY PLL control register [5111+] + * PHY PLL (Phase Locked Loop) control register */ #define AR5K_PHY_PLL 0x987c #define AR5K_PHY_PLL_20MHZ 0x13 /* [5111] */ @@ -1733,8 +1733,59 @@ #define AR5K_PHY_PLL_RF5112 0x00000040 /* - * PHY RF stage register [5110] + * RF Buffer register + * + * There are some special control registers on the RF chip + * that hold various operation settings related mostly to + * the analog parts (channel, gain adjustment etc). + * + * We don't write on those registers directly but + * we send a data packet on the buffer register and + * then write on another special register to notify hw + * to apply the settings. This is done so that control registers + * can be dynamicaly programmed during operation and the settings + * are applied faster on the hw. + * + * We sent such data packets during rf initialization and channel change + * through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions. + * + * The data packets we send during initializadion are inside ath5k_ini_rf + * struct (see ath5k_hw.h) and each one is related to an "rf register bank". + * We use *rfregs functions to modify them acording to current operation + * mode and eeprom values and pass them all together to the chip. + * + * It's obvious from the code that 0x989c is the buffer register but + * for the other special registers that we write to after sending each + * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers + * for now. It's interesting that they are also used for some other operations. + * + * Also check out ath5k_hw.h and U.S. Patent 6677779 B1 (about buffer + * registers and control registers) */ + +#define AR5K_RF_BUFFER 0x989c +#define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */ +#define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */ +#define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */ + +#define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 & + * Channel set on 5111 & + * Used to read radio revision */ + +#define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* Bank 0,1,2,6 on 5111 & + * Bank 1 on 5112 & + * Used during activation on 5111 */ + +#define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 & + * Used during activation on 5111 & + * Channel on 5112 & + * Bank 6 on 5112*/ + +#define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */ + +/* + * PHY RF stage register [5210] + */ #define AR5K_PHY_RFSTG 0x98d4 #define AR5K_PHY_RFSTG_DISABLE 0x00000021 @@ -1745,7 +1796,7 @@ #define AR5K_PHY_RX_DELAY_M 0x00003fff /* - * PHY timing IQ control register [5111+] + * PHY timing I(nphase) Q(adrature) control register [5111+] */ #define AR5K_PHY_IQ 0x9920 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f @@ -1774,7 +1825,7 @@ /* - * PHY TX power registers [5112+] + * PHY TX rate power registers [5112+] */ #define AR5K_PHY_TXPOWER_RATE1 0x9934 #define AR5K_PHY_TXPOWER_RATE2 0x9938 @@ -1865,16 +1916,16 @@ /* * Misc PHY/radio registers [5110 - 5111] */ -#define AR5K_BB_GAIN_BASE 0x9b00 +#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) -#define AR5K_RF_GAIN_BASE 0x9a00 +#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) /* * PHY timing IQ calibration result register [5111+] */ -#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 -#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 +#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ +#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* @@ -1883,7 +1934,7 @@ #define AR5K_PHY_CURRENT_RSSI 0x9c1c /* - * PHY PCDAC TX power register [5112+] + * PHY PCDAC TX power register [511+ (?)] */ #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) Index: ath5k_hw.h =================================================================== --- ath5k_hw.h (revision 2502) +++ ath5k_hw.h (revision 2524) @@ -105,6 +105,10 @@ } \ } +/* + * HW SPECIFIC STRUCTS + */ + /* Some EEPROM defines */ #define AR5K_EEPROM_EEP_SCALE 100 #define AR5K_EEPROM_EEP_DELTA 10 @@ -145,6 +149,7 @@ #define AR5K_EEPROM_CCK_OFDM_DELTA 15 #define AR5K_EEPROM_N_IQ_CAL 2 +/* Struct to hold EEPROM calibration data */ struct ath5k_eeprom_info { u_int16_t ee_magic; u_int16_t ee_protect; @@ -194,9 +199,295 @@ }; /* - * AR5k register access + * Internal HW RX/TX descriptor structures + * (rX: reserved fields possibily used by future versions of the ar5k chipset) */ +/* + * Common rx control descriptor + */ +struct ath5k_rx_desc { + + /* RX control word 0 */ + u_int32_t rx_control_0; + +#define AR5K_DESC_RX_CTL0 0x00000000 + + /* RX control word 1 */ + u_int32_t rx_control_1; + +#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff +#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 + +} __packed; + +/* + * 5210/5211 rx status descriptor + */ +struct ath5k_hw_old_rx_status { + + /*`RX status word 0`*/ + u_int32_t rx_status_0; + +#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 +#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 + + /* RX status word 1 */ + u_int32_t rx_status_1; + +#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 +#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 +#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 +#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 +#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 + +} __packed; + +/* + * 5212 rx status descriptor + */ +struct ath5k_hw_new_rx_status { + + /* RX status word 0 */ + u_int32_t rx_status_0; + +#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 +#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 + + /* RX status word 1 */ + u_int32_t rx_status_1; + +#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 +#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010 +#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 +#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 +#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 +} __packed; + +/* + * 5212 rx error descriptor + */ +struct ath5k_hw_rx_error { + + /* RX error word 0 */ + u_int32_t rx_error_0; + +#define AR5K_RX_DESC_ERROR0 0x00000000 + + /* RX error word 1 */ + u_int32_t rx_error_1; + +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 + +} __packed; + +#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 +#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 +#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 +#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 +#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 +#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 +#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 +#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 + +/* + * 5210/5211 2-word tx control descriptor + */ +struct ath5k_hw_2w_tx_desc { + + /* TX control word 0 */ + u_int32_t tx_control_0; + +#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 +#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 + + /* TX control word 1 */ + u_int32_t tx_control_1; + +#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (hal->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ + +} __packed; + +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 + +/* + * 5212 4-word tx control descriptor + */ +struct ath5k_hw_4w_tx_desc { + + /* TX control word 0 */ + u_int32_t tx_control_0; + +#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 +#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 +#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 +#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 + + /* TX control word 1 */ + u_int32_t tx_control_1; + +#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 + + /* TX control word 2 */ + u_int32_t tx_control_2; + +#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff +#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 + + /* TX control word 3 */ + u_int32_t tx_control_3; + +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 + +} __packed; + + +/* + * Common tx status descriptor + */ +struct ath5k_hw_tx_status { + + /* TX status word 0 */ + u_int32_t tx_status_0; + +#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 +#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 +#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 +#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 +/*??? +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 +*/ +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 +/*??? +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 +*/ +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 + + /* TX status word 1 */ + u_int32_t tx_status_1; + +#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 +#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe +#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 +#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 +#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 + +} __packed; + + + +/* + * AR5K REGISTER ACCESS + */ + /*Swap RX/TX Descriptor for big endian archs*/ #if defined(__BIG_ENDIAN) #define AR5K_INIT_CFG ( \ @@ -342,9 +633,11 @@ ) /* - * Non - common initial register values + * Non-common initial register values which have to be loaded into the + * card at boot time and after each reset. */ +/* Register dumps are done per operation mode */ #define AR5K_INI_VAL_11A 0 #define AR5K_INI_VAL_11A_TURBO 1 #define AR5K_INI_VAL_11B 2 @@ -360,14 +653,18 @@ #define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS #define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS +/* Struct to hold initial RF register values */ struct ath5k_ini_rf { - u_int8_t rf_bank; - u_int16_t rf_register; - u_int32_t rf_value[5]; + u_int8_t rf_bank; /* check out ath5kreg.h */ + u_int16_t rf_register; /* register address */ + u_int32_t rf_value[5]; /* register value for + different modes (see avove) */ }; +/* RF5111 mode-specific init registers */ #define AR5K_RF5111_INI_RF { \ { 0, 0x989c, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ { 0, 0x989c, \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ @@ -459,8 +756,10 @@ { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ } +/* RF5112 mode-specific init registers */ #define AR5K_RF5112_INI_RF { \ { 1, 0x98d4, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ { 2, 0x98d0, \ { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ @@ -569,9 +868,11 @@ { 7, 0x98c4, \ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } - + +/* RF5112A mode-specific init registers */ #define AR5K_RF5112A_INI_RF { \ { 1, 0x98d4, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ { 2, 0x98d0, \ { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ @@ -685,9 +986,12 @@ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ } +/* + * Mode-specific RF Gain registers + */ struct ath5k_ini_rfgain { - u_int16_t rfg_register; - u_int32_t rfg_value[2][2]; + u_int16_t rfg_register; /* RF Gain register address */ + u_int32_t rfg_value[2][2]; /* [phy (see above)][freq (below)] */ #define AR5K_INI_RFGAIN_5GHZ 0 #define AR5K_INI_RFGAIN_2GHZ 1 @@ -695,6 +999,7 @@ #define AR5K_INI_RFGAIN { \ { 0x9a00, { \ + /* 5111 5Ghz 5111 2Ghz 5112 5Ghz 5112 2Ghz */ \ { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ { 0x9a04, { \ { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ @@ -824,291 +1129,9 @@ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ } -/* - * Internal RX/TX descriptor structures - * (rX: reserved fields possibily used by future versions of the ar5k chipset) - */ -struct ath5k_rx_desc { - /* - * RX control word 0 - */ - u_int32_t rx_control_0; - -#define AR5K_DESC_RX_CTL0 0x00000000 - - /* - * RX control word 1 - */ - u_int32_t rx_control_1; - -#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff -#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 -} __packed; - -struct ath5k_hw_old_rx_status { - /* - * RX status word 0 - */ - u_int32_t rx_status_0; - -#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff -#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 -#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 - - /* - * RX status word 1 - */ - u_int32_t rx_status_1; - -#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001 -#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 -#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 -#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 -#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9 -#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 -#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 -#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 -} __packed; - -struct ath5k_hw_new_rx_status { - /* - * RX status word 0 - */ - u_int32_t rx_status_0; - -#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff -#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000 -#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 -#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 - - /* - * RX status word 1 - */ - u_int32_t rx_status_1; - -#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001 -#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 -#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004 -#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 -#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010 -#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9 -#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 -#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 -#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 -} __packed; - -struct ath5k_hw_rx_error { - /* - * RX error word 0 - */ - u_int32_t rx_error_0; - -#define AR5K_RX_DESC_ERROR0 0x00000000 - - /* - * RX error word 1 - */ - u_int32_t rx_error_1; - -#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 -#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 -} __packed; - -#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 -#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 -#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 -#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 -#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 -#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 -#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 -#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 - -struct ath5k_hw_2w_tx_desc { - /* - * TX control word 0 - */ - u_int32_t tx_control_0; - -#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff -#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ -#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 -#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 -#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 -#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 -#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 -#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ -#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ -#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (hal->ah_version == AR5K_AR5210 ? \ - AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ - AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) -#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 -#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 - - /* - * TX control word 1 - */ - u_int32_t tx_control_1; - -#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff -#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (hal->ah_version == AR5K_AR5210 ? \ - AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ - AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) -#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 -#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ -#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ -} __packed; - -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c -#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 - -struct ath5k_hw_4w_tx_desc { - /* - * TX control word 0 - */ - u_int32_t tx_control_0; - -#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff -#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 -#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 -#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 -#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 -#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 -#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 -#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 -#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 -#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 -#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 - - /* - * TX control word 1 - */ - u_int32_t tx_control_1; - -#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff -#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 -#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 -#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 -#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 -#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 -#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 -#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 -#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 -#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 - - /* - * TX control word 2 - */ - u_int32_t tx_control_2; - -#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff -#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 -#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 - - /* - * TX control word 3 - */ - u_int32_t tx_control_3; - -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 -#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 -#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 -#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 -} __packed; - -struct ath5k_hw_tx_status { - /* - * TX status word 0 - */ - u_int32_t tx_status_0; - -#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 -#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 -#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 -#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 -/*??? -#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 -#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 -*/ -#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 -#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 -/*??? -#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 -#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 -*/ -#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 -#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 -#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 -#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 -#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 -#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 - - /* - * TX status word 1 - */ - u_int32_t tx_status_1; - -#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 -#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe -#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 -#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 -#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 -#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 -#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 -#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 -#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 -} __packed; - - /* - * Initial register values which have to be loaded into the - * card at boot time and after each reset. + * Mode-independet initial register writes */ struct ath5k_ini { @@ -1116,222 +1139,784 @@ u_int32_t ini_value; enum { - AR5K_INI_WRITE = 0, - AR5K_INI_READ = 1, + AR5K_INI_WRITE = 0, /* Default */ + AR5K_INI_READ = 1, /* Cleared on read */ } ini_mode; }; -#define AR5K_AR5210_INI { \ - /* PCU and MAC registers */ \ - { AR5K_NOQCU_TXDP0, 0 }, \ - { AR5K_NOQCU_TXDP1, 0 }, \ - { AR5K_RXDP, 0 }, \ - { AR5K_CR, 0 }, \ - { AR5K_ISR, 0, AR5K_INI_READ }, \ - { AR5K_IMR, 0 }, \ - { AR5K_IER, AR5K_IER_DISABLE }, \ - { AR5K_BSR, 0, AR5K_INI_READ }, \ - { AR5K_TXCFG, AR5K_DMASIZE_128B }, \ - { AR5K_RXCFG, AR5K_DMASIZE_128B }, \ - { AR5K_CFG, AR5K_INIT_CFG }, \ - { AR5K_TOPS, AR5K_INIT_TOPS }, \ - { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \ - { AR5K_RPGTO, AR5K_INIT_RPGTO }, \ - { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \ - { AR5K_SFR, 0 }, \ - { AR5K_MIBC, 0 }, \ - { AR5K_MISC, 0 }, \ - { AR5K_RX_FILTER_5210, 0 }, \ - { AR5K_MCAST_FILTER0_5210, 0 }, \ - { AR5K_MCAST_FILTER1_5210, 0 }, \ - { AR5K_TX_MASK0, 0 }, \ - { AR5K_TX_MASK1, 0 }, \ - { AR5K_CLR_TMASK, 0 }, \ - { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ - { AR5K_DIAG_SW_5210, 0 }, \ - { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ - { AR5K_TSF_L32_5210, 0 }, \ - { AR5K_TIMER0_5210, 0 }, \ - { AR5K_TIMER1_5210, 0xffffffff }, \ - { AR5K_TIMER2_5210, 0xffffffff }, \ - { AR5K_TIMER3_5210, 1 }, \ - { AR5K_CFP_DUR_5210, 0 }, \ - { AR5K_CFP_PERIOD_5210, 0 }, \ - /* PHY registers */ \ - { AR5K_PHY(0), 0x00000047 }, \ - { AR5K_PHY_AGC, 0x00000000 }, \ - { AR5K_PHY(3), 0x09848ea6 }, \ - { AR5K_PHY(4), 0x3d32e000 }, \ - { AR5K_PHY(5), 0x0000076b }, \ - { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \ - { AR5K_PHY(8), 0x02020200 }, \ - { AR5K_PHY(9), 0x00000e0e }, \ - { AR5K_PHY(10), 0x0a020201 }, \ - { AR5K_PHY(11), 0x00036ffc }, \ - { AR5K_PHY(12), 0x00000000 }, \ - { AR5K_PHY(13), 0x00000e0e }, \ - { AR5K_PHY(14), 0x00000007 }, \ - { AR5K_PHY(15), 0x00020100 }, \ - { AR5K_PHY(16), 0x89630000 }, \ - { AR5K_PHY(17), 0x1372169c }, \ - { AR5K_PHY(18), 0x0018b633 }, \ - { AR5K_PHY(19), 0x1284613c }, \ - { AR5K_PHY(20), 0x0de8b8e0 }, \ - { AR5K_PHY(21), 0x00074859 }, \ - { AR5K_PHY(22), 0x7e80beba }, \ - { AR5K_PHY(23), 0x313a665e }, \ - { AR5K_PHY_AGCCTL, 0x00001d08 }, \ - { AR5K_PHY(25), 0x0001ce00 }, \ - { AR5K_PHY(26), 0x409a4190 }, \ - { AR5K_PHY(28), 0x0000000f }, \ - { AR5K_PHY(29), 0x00000080 }, \ - { AR5K_PHY(30), 0x00000004 }, \ - { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \ - { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \ - { AR5K_PHY(65), 0x00000000 }, \ - { AR5K_PHY(66), 0x00000000 }, \ - { AR5K_PHY(67), 0x00800000 }, \ - { AR5K_PHY(68), 0x00000003 }, \ - /* BB gain table (64bytes) */ \ - { AR5K_BB_GAIN(0), 0x00000000 }, \ - { AR5K_BB_GAIN(0x01), 0x00000020 }, \ - { AR5K_BB_GAIN(0x02), 0x00000010 }, \ - { AR5K_BB_GAIN(0x03), 0x00000030 }, \ - { AR5K_BB_GAIN(0x04), 0x00000008 }, \ - { AR5K_BB_GAIN(0x05), 0x00000028 }, \ - { AR5K_BB_GAIN(0x06), 0x00000028 }, \ - { AR5K_BB_GAIN(0x07), 0x00000004 }, \ - { AR5K_BB_GAIN(0x08), 0x00000024 }, \ - { AR5K_BB_GAIN(0x09), 0x00000014 }, \ - { AR5K_BB_GAIN(0x0a), 0x00000034 }, \ - { AR5K_BB_GAIN(0x0b), 0x0000000c }, \ - { AR5K_BB_GAIN(0x0c), 0x0000002c }, \ - { AR5K_BB_GAIN(0x0d), 0x00000002 }, \ - { AR5K_BB_GAIN(0x0e), 0x00000022 }, \ - { AR5K_BB_GAIN(0x0f), 0x00000012 }, \ - { AR5K_BB_GAIN(0x10), 0x00000032 }, \ - { AR5K_BB_GAIN(0x11), 0x0000000a }, \ - { AR5K_BB_GAIN(0x12), 0x0000002a }, \ - { AR5K_BB_GAIN(0x13), 0x00000001 }, \ - { AR5K_BB_GAIN(0x14), 0x00000021 }, \ - { AR5K_BB_GAIN(0x15), 0x00000011 }, \ - { AR5K_BB_GAIN(0x16), 0x00000031 }, \ - { AR5K_BB_GAIN(0x17), 0x00000009 }, \ - { AR5K_BB_GAIN(0x18), 0x00000029 }, \ - { AR5K_BB_GAIN(0x19), 0x00000005 }, \ - { AR5K_BB_GAIN(0x1a), 0x00000025 }, \ - { AR5K_BB_GAIN(0x1b), 0x00000015 }, \ - { AR5K_BB_GAIN(0x1c), 0x00000035 }, \ - { AR5K_BB_GAIN(0x1d), 0x0000000d }, \ - { AR5K_BB_GAIN(0x1e), 0x0000002d }, \ - { AR5K_BB_GAIN(0x1f), 0x00000003 }, \ - { AR5K_BB_GAIN(0x20), 0x00000023 }, \ - { AR5K_BB_GAIN(0x21), 0x00000013 }, \ - { AR5K_BB_GAIN(0x22), 0x00000033 }, \ - { AR5K_BB_GAIN(0x23), 0x0000000b }, \ - { AR5K_BB_GAIN(0x24), 0x0000002b }, \ - { AR5K_BB_GAIN(0x25), 0x00000007 }, \ - { AR5K_BB_GAIN(0x26), 0x00000027 }, \ - { AR5K_BB_GAIN(0x27), 0x00000017 }, \ - { AR5K_BB_GAIN(0x28), 0x00000037 }, \ - { AR5K_BB_GAIN(0x29), 0x0000000f }, \ - { AR5K_BB_GAIN(0x2a), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2b), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2c), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2d), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2e), 0x0000002f }, \ - { AR5K_BB_GAIN(0x2f), 0x0000002f }, \ - { AR5K_BB_GAIN(0x30), 0x0000002f }, \ - { AR5K_BB_GAIN(0x31), 0x0000002f }, \ - { AR5K_BB_GAIN(0x32), 0x0000002f }, \ - { AR5K_BB_GAIN(0x33), 0x0000002f }, \ - { AR5K_BB_GAIN(0x34), 0x0000002f }, \ - { AR5K_BB_GAIN(0x35), 0x0000002f }, \ - { AR5K_BB_GAIN(0x36), 0x0000002f }, \ - { AR5K_BB_GAIN(0x37), 0x0000002f }, \ - { AR5K_BB_GAIN(0x38), 0x0000002f }, \ - { AR5K_BB_GAIN(0x39), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3a), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3b), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3c), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3d), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3e), 0x0000002f }, \ - { AR5K_BB_GAIN(0x3f), 0x0000002f }, \ - /* RF gain table (64bytes) */ \ - { AR5K_RF_GAIN(0), 0x0000001d }, \ - { AR5K_RF_GAIN(0x01), 0x0000005d }, \ - { AR5K_RF_GAIN(0x02), 0x0000009d }, \ - { AR5K_RF_GAIN(0x03), 0x000000dd }, \ - { AR5K_RF_GAIN(0x04), 0x0000011d }, \ - { AR5K_RF_GAIN(0x05), 0x00000021 }, \ - { AR5K_RF_GAIN(0x06), 0x00000061 }, \ - { AR5K_RF_GAIN(0x07), 0x000000a1 }, \ - { AR5K_RF_GAIN(0x08), 0x000000e1 }, \ - { AR5K_RF_GAIN(0x09), 0x00000031 }, \ - { AR5K_RF_GAIN(0x0a), 0x00000071 }, \ - { AR5K_RF_GAIN(0x0b), 0x000000b1 }, \ - { AR5K_RF_GAIN(0x0c), 0x0000001c }, \ - { AR5K_RF_GAIN(0x0d), 0x0000005c }, \ - { AR5K_RF_GAIN(0x0e), 0x00000029 }, \ - { AR5K_RF_GAIN(0x0f), 0x00000069 }, \ - { AR5K_RF_GAIN(0x10), 0x000000a9 }, \ - { AR5K_RF_GAIN(0x11), 0x00000020 }, \ - { AR5K_RF_GAIN(0x12), 0x00000019 }, \ - { AR5K_RF_GAIN(0x13), 0x00000059 }, \ - { AR5K_RF_GAIN(0x14), 0x00000099 }, \ - { AR5K_RF_GAIN(0x15), 0x00000030 }, \ - { AR5K_RF_GAIN(0x16), 0x00000005 }, \ - { AR5K_RF_GAIN(0x17), 0x00000025 }, \ - { AR5K_RF_GAIN(0x18), 0x00000065 }, \ - { AR5K_RF_GAIN(0x19), 0x000000a5 }, \ - { AR5K_RF_GAIN(0x1a), 0x00000028 }, \ - { AR5K_RF_GAIN(0x1b), 0x00000068 }, \ - { AR5K_RF_GAIN(0x1c), 0x0000001f }, \ - { AR5K_RF_GAIN(0x1d), 0x0000001e }, \ - { AR5K_RF_GAIN(0x1e), 0x00000018 }, \ - { AR5K_RF_GAIN(0x1f), 0x00000058 }, \ - { AR5K_RF_GAIN(0x20), 0x00000098 }, \ - { AR5K_RF_GAIN(0x21), 0x00000003 }, \ - { AR5K_RF_GAIN(0x22), 0x00000004 }, \ - { AR5K_RF_GAIN(0x23), 0x00000044 }, \ - { AR5K_RF_GAIN(0x24), 0x00000084 }, \ - { AR5K_RF_GAIN(0x25), 0x00000013 }, \ - { AR5K_RF_GAIN(0x26), 0x00000012 }, \ - { AR5K_RF_GAIN(0x27), 0x00000052 }, \ - { AR5K_RF_GAIN(0x28), 0x00000092 }, \ - { AR5K_RF_GAIN(0x29), 0x000000d2 }, \ - { AR5K_RF_GAIN(0x2a), 0x0000002b }, \ - { AR5K_RF_GAIN(0x2b), 0x0000002a }, \ - { AR5K_RF_GAIN(0x2c), 0x0000006a }, \ - { AR5K_RF_GAIN(0x2d), 0x000000aa }, \ - { AR5K_RF_GAIN(0x2e), 0x0000001b }, \ - { AR5K_RF_GAIN(0x2f), 0x0000001a }, \ - { AR5K_RF_GAIN(0x30), 0x0000005a }, \ - { AR5K_RF_GAIN(0x31), 0x0000009a }, \ - { AR5K_RF_GAIN(0x32), 0x000000da }, \ - { AR5K_RF_GAIN(0x33), 0x00000006 }, \ - { AR5K_RF_GAIN(0x34), 0x00000006 }, \ - { AR5K_RF_GAIN(0x35), 0x00000006 }, \ - { AR5K_RF_GAIN(0x36), 0x00000006 }, \ - { AR5K_RF_GAIN(0x37), 0x00000006 }, \ - { AR5K_RF_GAIN(0x38), 0x00000006 }, \ - { AR5K_RF_GAIN(0x39), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3a), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3b), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3c), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3d), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3e), 0x00000006 }, \ - { AR5K_RF_GAIN(0x3f), 0x00000006 }, \ - /* PHY activation */ \ - { AR5K_PHY(53), 0x00000020 }, \ - { AR5K_PHY(51), 0x00000004 }, \ - { AR5K_PHY(50), 0x00060106 }, \ - { AR5K_PHY(39), 0x0000006d }, \ - { AR5K_PHY(48), 0x00000000 }, \ - { AR5K_PHY(52), 0x00000014 }, \ - { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \ +/* Initial register settings for AR5210 */ +#define AR5K_AR5210_INI { \ + /* PCU and MAC registers */ \ + { AR5K_NOQCU_TXDP0, 0 }, \ + { AR5K_NOQCU_TXDP1, 0 }, \ + { AR5K_RXDP, 0 }, \ + { AR5K_CR, 0 }, \ + { AR5K_ISR, 0, AR5K_INI_READ }, \ + { AR5K_IMR, 0 }, \ + { AR5K_IER, AR5K_IER_DISABLE }, \ + { AR5K_BSR, 0, AR5K_INI_READ }, \ + { AR5K_TXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_RXCFG, AR5K_DMASIZE_128B }, \ + { AR5K_CFG, AR5K_INIT_CFG }, \ + { AR5K_TOPS, AR5K_INIT_TOPS }, \ + { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \ + { AR5K_RPGTO, AR5K_INIT_RPGTO }, \ + { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \ + { AR5K_SFR, 0 }, \ + { AR5K_MIBC, 0 }, \ + { AR5K_MISC, 0 }, \ + { AR5K_RX_FILTER_5210, 0 }, \ + { AR5K_MCAST_FILTER0_5210, 0 }, \ + { AR5K_MCAST_FILTER1_5210, 0 }, \ + { AR5K_TX_MASK0, 0 }, \ + { AR5K_TX_MASK1, 0 }, \ + { AR5K_CLR_TMASK, 0 }, \ + { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ + { AR5K_DIAG_SW_5210, 0 }, \ + { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ + { AR5K_TSF_L32_5210, 0 }, \ + { AR5K_TIMER0_5210, 0 }, \ + { AR5K_TIMER1_5210, 0xffffffff }, \ + { AR5K_TIMER2_5210, 0xffffffff }, \ + { AR5K_TIMER3_5210, 1 }, \ + { AR5K_CFP_DUR_5210, 0 }, \ + { AR5K_CFP_PERIOD_5210, 0 }, \ + /* PHY registers */ \ + { AR5K_PHY(0), 0x00000047 }, \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0x09848ea6 }, \ + { AR5K_PHY(4), 0x3d32e000 }, \ + { AR5K_PHY(5), 0x0000076b }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \ + { AR5K_PHY(8), 0x02020200 }, \ + { AR5K_PHY(9), 0x00000e0e }, \ + { AR5K_PHY(10), 0x0a020201 }, \ + { AR5K_PHY(11), 0x00036ffc }, \ + { AR5K_PHY(12), 0x00000000 }, \ + { AR5K_PHY(13), 0x00000e0e }, \ + { AR5K_PHY(14), 0x00000007 }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x89630000 }, \ + { AR5K_PHY(17), 0x1372169c }, \ + { AR5K_PHY(18), 0x0018b633 }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(20), 0x0de8b8e0 }, \ + { AR5K_PHY(21), 0x00074859 }, \ + { AR5K_PHY(22), 0x7e80beba }, \ + { AR5K_PHY(23), 0x313a665e }, \ + { AR5K_PHY_AGCCTL, 0x00001d08 },\ + { AR5K_PHY(25), 0x0001ce00 }, \ + { AR5K_PHY(26), 0x409a4190 }, \ + { AR5K_PHY(28), 0x0000000f }, \ + { AR5K_PHY(29), 0x00000080 }, \ + { AR5K_PHY(30), 0x00000004 }, \ + { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \ + { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000003 }, \ + /* BB gain table (64bytes) */ \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(1), 0x00000020 }, \ + { AR5K_BB_GAIN(2), 0x00000010 }, \ + { AR5K_BB_GAIN(3), 0x00000030 }, \ + { AR5K_BB_GAIN(4), 0x00000008 }, \ + { AR5K_BB_GAIN(5), 0x00000028 }, \ + { AR5K_BB_GAIN(6), 0x00000028 }, \ + { AR5K_BB_GAIN(7), 0x00000004 }, \ + { AR5K_BB_GAIN(8), 0x00000024 }, \ + { AR5K_BB_GAIN(9), 0x00000014 }, \ + { AR5K_BB_GAIN(10), 0x00000034 }, \ + { AR5K_BB_GAIN(11), 0x0000000c }, \ + { AR5K_BB_GAIN(12), 0x0000002c }, \ + { AR5K_BB_GAIN(13), 0x00000002 }, \ + { AR5K_BB_GAIN(14), 0x00000022 }, \ + { AR5K_BB_GAIN(15), 0x00000012 }, \ + { AR5K_BB_GAIN(16), 0x00000032 }, \ + { AR5K_BB_GAIN(17), 0x0000000a }, \ + { AR5K_BB_GAIN(18), 0x0000002a }, \ + { AR5K_BB_GAIN(19), 0x00000001 }, \ + { AR5K_BB_GAIN(20), 0x00000021 }, \ + { AR5K_BB_GAIN(21), 0x00000011 }, \ + { AR5K_BB_GAIN(22), 0x00000031 }, \ + { AR5K_BB_GAIN(23), 0x00000009 }, \ + { AR5K_BB_GAIN(24), 0x00000029 }, \ + { AR5K_BB_GAIN(25), 0x00000005 }, \ + { AR5K_BB_GAIN(26), 0x00000025 }, \ + { AR5K_BB_GAIN(27), 0x00000015 }, \ + { AR5K_BB_GAIN(28), 0x00000035 }, \ + { AR5K_BB_GAIN(29), 0x0000000d }, \ + { AR5K_BB_GAIN(30), 0x0000002d }, \ + { AR5K_BB_GAIN(31), 0x00000003 }, \ + { AR5K_BB_GAIN(32), 0x00000023 }, \ + { AR5K_BB_GAIN(33), 0x00000013 }, \ + { AR5K_BB_GAIN(34), 0x00000033 }, \ + { AR5K_BB_GAIN(35), 0x0000000b }, \ + { AR5K_BB_GAIN(36), 0x0000002b }, \ + { AR5K_BB_GAIN(37), 0x00000007 }, \ + { AR5K_BB_GAIN(38), 0x00000027 }, \ + { AR5K_BB_GAIN(39), 0x00000017 }, \ + { AR5K_BB_GAIN(40), 0x00000037 }, \ + { AR5K_BB_GAIN(41), 0x0000000f }, \ + { AR5K_BB_GAIN(42), 0x0000002f }, \ + { AR5K_BB_GAIN(43), 0x0000002f }, \ + { AR5K_BB_GAIN(44), 0x0000002f }, \ + { AR5K_BB_GAIN(45), 0x0000002f }, \ + { AR5K_BB_GAIN(46), 0x0000002f }, \ + { AR5K_BB_GAIN(47), 0x0000002f }, \ + { AR5K_BB_GAIN(48), 0x0000002f }, \ + { AR5K_BB_GAIN(49), 0x0000002f }, \ + { AR5K_BB_GAIN(50), 0x0000002f }, \ + { AR5K_BB_GAIN(51), 0x0000002f }, \ + { AR5K_BB_GAIN(52), 0x0000002f }, \ + { AR5K_BB_GAIN(53), 0x0000002f }, \ + { AR5K_BB_GAIN(54), 0x0000002f }, \ + { AR5K_BB_GAIN(55), 0x0000002f }, \ + { AR5K_BB_GAIN(56), 0x0000002f }, \ + { AR5K_BB_GAIN(57), 0x0000002f }, \ + { AR5K_BB_GAIN(58), 0x0000002f }, \ + { AR5K_BB_GAIN(59), 0x0000002f }, \ + { AR5K_BB_GAIN(60), 0x0000002f }, \ + { AR5K_BB_GAIN(61), 0x0000002f }, \ + { AR5K_BB_GAIN(62), 0x0000002f }, \ + { AR5K_BB_GAIN(63), 0x0000002f }, \ + /* RF gain table (64btes) */ \ + { AR5K_RF_GAIN(0), 0x0000001d }, \ + { AR5K_RF_GAIN(1), 0x0000005d }, \ + { AR5K_RF_GAIN(2), 0x0000009d }, \ + { AR5K_RF_GAIN(3), 0x000000dd }, \ + { AR5K_RF_GAIN(4), 0x0000011d }, \ + { AR5K_RF_GAIN(5), 0x00000021 }, \ + { AR5K_RF_GAIN(6), 0x00000061 }, \ + { AR5K_RF_GAIN(7), 0x000000a1 }, \ + { AR5K_RF_GAIN(8), 0x000000e1 }, \ + { AR5K_RF_GAIN(9), 0x00000031 }, \ + { AR5K_RF_GAIN(10), 0x00000071 }, \ + { AR5K_RF_GAIN(11), 0x000000b1 }, \ + { AR5K_RF_GAIN(12), 0x0000001c }, \ + { AR5K_RF_GAIN(13), 0x0000005c }, \ + { AR5K_RF_GAIN(14), 0x00000029 }, \ + { AR5K_RF_GAIN(15), 0x00000069 }, \ + { AR5K_RF_GAIN(16), 0x000000a9 }, \ + { AR5K_RF_GAIN(17), 0x00000020 }, \ + { AR5K_RF_GAIN(18), 0x00000019 }, \ + { AR5K_RF_GAIN(19), 0x00000059 }, \ + { AR5K_RF_GAIN(20), 0x00000099 }, \ + { AR5K_RF_GAIN(21), 0x00000030 }, \ + { AR5K_RF_GAIN(22), 0x00000005 }, \ + { AR5K_RF_GAIN(23), 0x00000025 }, \ + { AR5K_RF_GAIN(24), 0x00000065 }, \ + { AR5K_RF_GAIN(25), 0x000000a5 }, \ + { AR5K_RF_GAIN(26), 0x00000028 }, \ + { AR5K_RF_GAIN(27), 0x00000068 }, \ + { AR5K_RF_GAIN(28), 0x0000001f }, \ + { AR5K_RF_GAIN(29), 0x0000001e }, \ + { AR5K_RF_GAIN(30), 0x00000018 }, \ + { AR5K_RF_GAIN(31), 0x00000058 }, \ + { AR5K_RF_GAIN(32), 0x00000098 }, \ + { AR5K_RF_GAIN(33), 0x00000003 }, \ + { AR5K_RF_GAIN(34), 0x00000004 }, \ + { AR5K_RF_GAIN(35), 0x00000044 }, \ + { AR5K_RF_GAIN(36), 0x00000084 }, \ + { AR5K_RF_GAIN(37), 0x00000013 }, \ + { AR5K_RF_GAIN(38), 0x00000012 }, \ + { AR5K_RF_GAIN(39), 0x00000052 }, \ + { AR5K_RF_GAIN(40), 0x00000092 }, \ + { AR5K_RF_GAIN(41), 0x000000d2 }, \ + { AR5K_RF_GAIN(42), 0x0000002b }, \ + { AR5K_RF_GAIN(43), 0x0000002a }, \ + { AR5K_RF_GAIN(44), 0x0000006a }, \ + { AR5K_RF_GAIN(45), 0x000000aa }, \ + { AR5K_RF_GAIN(46), 0x0000001b }, \ + { AR5K_RF_GAIN(47), 0x0000001a }, \ + { AR5K_RF_GAIN(48), 0x0000005a }, \ + { AR5K_RF_GAIN(49), 0x0000009a }, \ + { AR5K_RF_GAIN(50), 0x000000da }, \ + { AR5K_RF_GAIN(51), 0x00000006 }, \ + { AR5K_RF_GAIN(52), 0x00000006 }, \ + { AR5K_RF_GAIN(53), 0x00000006 }, \ + { AR5K_RF_GAIN(54), 0x00000006 }, \ + { AR5K_RF_GAIN(55), 0x00000006 }, \ + { AR5K_RF_GAIN(56), 0x00000006 }, \ + { AR5K_RF_GAIN(57), 0x00000006 }, \ + { AR5K_RF_GAIN(58), 0x00000006 }, \ + { AR5K_RF_GAIN(59), 0x00000006 }, \ + { AR5K_RF_GAIN(60), 0x00000006 }, \ + { AR5K_RF_GAIN(61), 0x00000006 }, \ + { AR5K_RF_GAIN(62), 0x00000006 }, \ + { AR5K_RF_GAIN(63), 0x00000006 }, \ + /* PHY activation */ \ + { AR5K_PHY(53), 0x00000020 }, \ + { AR5K_PHY(51), 0x00000004 }, \ + { AR5K_PHY(50), 0x00060106 }, \ + { AR5K_PHY(39), 0x0000006d }, \ + { AR5K_PHY(48), 0x00000000 }, \ + { AR5K_PHY(52), 0x00000014 }, \ + { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \ } + +/* Initial register settings for AR5211 */ +#define AR5K_AR5211_INI { \ + { AR5K_RXDP, 0x00000000 }, \ + { AR5K_RTSD0, 0x84849c9c }, \ + { AR5K_RTSD1, 0x7c7c7c7c }, \ + { AR5K_RXCFG, 0x00000005 }, \ + { AR5K_MIBC, 0x00000000 }, \ + { AR5K_TOPS, 0x00000008 }, \ + { AR5K_RXNOFRM, 0x00000008 }, \ + { AR5K_TXNOFRM, 0x00000010 }, \ + { AR5K_RPGTO, 0x00000000 }, \ + { AR5K_RFCNT, 0x0000001f }, \ + { AR5K_QUEUE_TXDP(0), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(1), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(2), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(3), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(4), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(5), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(6), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(7), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(8), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(9), 0x00000000 }, \ + { AR5K_DCU_FP, 0x00000000 }, \ + { AR5K_STA_ID1, 0x00000000 }, \ + { AR5K_BSS_ID0, 0x00000000 }, \ + { AR5K_BSS_ID1, 0x00000000 }, \ + { AR5K_RSSI_THR, 0x00000000 }, \ + { AR5K_CFP_PERIOD_5211, 0x00000000 }, \ + { AR5K_TIMER0_5211, 0x00000030 }, \ + { AR5K_TIMER1_5211, 0x0007ffff }, \ + { AR5K_TIMER2_5211, 0x01ffffff }, \ + { AR5K_TIMER3_5211, 0x00000031 }, \ + { AR5K_CFP_DUR_5211, 0x00000000 }, \ + { AR5K_RX_FILTER_5211, 0x00000000 }, \ + { AR5K_MCAST_FILTER0_5211, 0x00000000 },\ + { AR5K_MCAST_FILTER1_5211, 0x00000002 },\ + { AR5K_DIAG_SW_5211, 0x00000000 }, \ + { AR5K_ADDAC_TEST, 0x00000000 }, \ + { AR5K_DEFAULT_ANTENNA, 0x00000000 }, \ + /* PHY registers */ \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0x2d849093 }, \ + { AR5K_PHY(4), 0x7d32e000 }, \ + { AR5K_PHY(5), 0x00000f6b }, \ + { AR5K_PHY_ACT, 0x00000000 }, \ + { AR5K_PHY(11), 0x00026ffe }, \ + { AR5K_PHY(12), 0x00000000 }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x206a017a }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(21), 0x00000859 }, \ + { AR5K_PHY(26), 0x409a4190 }, /* 0x9868 */ \ + { AR5K_PHY(27), 0x050cb081 }, \ + { AR5K_PHY(28), 0x0000000f }, \ + { AR5K_PHY(29), 0x00000080 }, \ + { AR5K_PHY(30), 0x0000000c }, \ + { AR5K_PHY(64), 0x00000000 }, \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000001 }, \ + { AR5K_PHY(71), 0x0000092a }, \ + { AR5K_PHY_IQ, 0x00000000 }, \ + { AR5K_PHY(73), 0x00058a05 }, \ + { AR5K_PHY(74), 0x00000001 }, \ + { AR5K_PHY(75), 0x00000000 }, \ + { AR5K_PHY_PAPD_PROBE, 0x00000000 }, \ + { AR5K_PHY(77), 0x00000000 }, /* 0x9934 */ \ + { AR5K_PHY(78), 0x00000000 }, /* 0x9938 */ \ + { AR5K_PHY(79), 0x0000003f }, /* 0x993c */ \ + { AR5K_PHY(80), 0x00000004 }, \ + { AR5K_PHY(82), 0x00000000 }, \ + { AR5K_PHY(83), 0x00000000 }, \ + { AR5K_PHY(84), 0x00000000 }, \ + { AR5K_PHY_RADAR, 0x5d50f14c }, \ + { AR5K_PHY(86), 0x00000018 }, \ + { AR5K_PHY(87), 0x004b6a8e }, \ + /* Power table (32bytes) */ \ + { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff }, \ + { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff }, \ + { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff }, \ + { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff }, \ + { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff }, \ + { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff }, \ + { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff }, \ + { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff }, \ + /* BB gain table (64bytes) */ \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(1), 0x00000020 }, \ + { AR5K_BB_GAIN(2), 0x00000010 }, \ + { AR5K_BB_GAIN(3), 0x00000030 }, \ + { AR5K_BB_GAIN(4), 0x00000008 }, \ + { AR5K_BB_GAIN(5), 0x00000028 }, \ + { AR5K_BB_GAIN(6), 0x00000004 }, \ + { AR5K_BB_GAIN(7), 0x00000024 }, \ + { AR5K_BB_GAIN(8), 0x00000014 }, \ + { AR5K_BB_GAIN(9), 0x00000034 }, \ + { AR5K_BB_GAIN(10), 0x0000000c }, \ + { AR5K_BB_GAIN(11), 0x0000002c }, \ + { AR5K_BB_GAIN(12), 0x00000002 }, \ + { AR5K_BB_GAIN(13), 0x00000022 }, \ + { AR5K_BB_GAIN(14), 0x00000012 }, \ + { AR5K_BB_GAIN(15), 0x00000032 }, \ + { AR5K_BB_GAIN(16), 0x0000000a }, \ + { AR5K_BB_GAIN(17), 0x0000002a }, \ + { AR5K_BB_GAIN(18), 0x00000006 }, \ + { AR5K_BB_GAIN(19), 0x00000026 }, \ + { AR5K_BB_GAIN(20), 0x00000016 }, \ + { AR5K_BB_GAIN(21), 0x00000036 }, \ + { AR5K_BB_GAIN(22), 0x0000000e }, \ + { AR5K_BB_GAIN(23), 0x0000002e }, \ + { AR5K_BB_GAIN(24), 0x00000001 }, \ + { AR5K_BB_GAIN(25), 0x00000021 }, \ + { AR5K_BB_GAIN(26), 0x00000011 }, \ + { AR5K_BB_GAIN(27), 0x00000031 }, \ + { AR5K_BB_GAIN(28), 0x00000009 }, \ + { AR5K_BB_GAIN(29), 0x00000029 }, \ + { AR5K_BB_GAIN(30), 0x00000005 }, \ + { AR5K_BB_GAIN(31), 0x00000025 }, \ + { AR5K_BB_GAIN(32), 0x00000015 }, \ + { AR5K_BB_GAIN(33), 0x00000035 }, \ + { AR5K_BB_GAIN(34), 0x0000000d }, \ + { AR5K_BB_GAIN(35), 0x0000002d }, \ + { AR5K_BB_GAIN(36), 0x00000003 }, \ + { AR5K_BB_GAIN(37), 0x00000023 }, \ + { AR5K_BB_GAIN(38), 0x00000013 }, \ + { AR5K_BB_GAIN(39), 0x00000033 }, \ + { AR5K_BB_GAIN(40), 0x0000000b }, \ + { AR5K_BB_GAIN(41), 0x0000002b }, \ + { AR5K_BB_GAIN(42), 0x0000002b }, \ + { AR5K_BB_GAIN(43), 0x0000002b }, \ + { AR5K_BB_GAIN(44), 0x0000002b }, \ + { AR5K_BB_GAIN(45), 0x0000002b }, \ + { AR5K_BB_GAIN(46), 0x0000002b }, \ + { AR5K_BB_GAIN(47), 0x0000002b }, \ + { AR5K_BB_GAIN(48), 0x0000002b }, \ + { AR5K_BB_GAIN(49), 0x0000002b }, \ + { AR5K_BB_GAIN(50), 0x0000002b }, \ + { AR5K_BB_GAIN(51), 0x0000002b }, \ + { AR5K_BB_GAIN(52), 0x0000002b }, \ + { AR5K_BB_GAIN(53), 0x0000002b }, \ + { AR5K_BB_GAIN(54), 0x0000002b }, \ + { AR5K_BB_GAIN(55), 0x0000002b }, \ + { AR5K_BB_GAIN(56), 0x0000002b }, \ + { AR5K_BB_GAIN(57), 0x0000002b }, \ + { AR5K_BB_GAIN(58), 0x0000002b }, \ + { AR5K_BB_GAIN(59), 0x0000002b }, \ + { AR5K_BB_GAIN(60), 0x0000002b }, \ + { AR5K_BB_GAIN(61), 0x0000002b }, \ + { AR5K_BB_GAIN(62), 0x00000002 }, \ + { AR5K_BB_GAIN(63), 0x00000016 }, \ + /* PHY activation */ \ + { AR5K_RF_BUFFER_CONTROL_4, 0x00000020 },\ + { AR5K_RF_BUFFER_CONTROL_5, 0x00601068 },\ +} + +/* Initial register settings for AR5212 */ +#define AR5K_AR5212_INI { \ + { AR5K_RXDP, 0x00000000 }, \ + { AR5K_RXCFG, 0x00000005 }, \ + { AR5K_MIBC, 0x00000000 }, \ + { AR5K_TOPS, 0x00000008 }, \ + { AR5K_RXNOFRM, 0x00000008 }, \ + { AR5K_TXNOFRM, 0x00000010 }, \ + { AR5K_RPGTO, 0x00000000 }, \ + { AR5K_RFCNT, 0x0000001f }, \ + { AR5K_QUEUE_TXDP(0), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(1), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(2), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(3), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(4), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(5), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(6), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(7), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(8), 0x00000000 }, \ + { AR5K_QUEUE_TXDP(9), 0x00000000 }, \ + { AR5K_DCU_FP, 0x00000000 }, \ + { AR5K_DCU_TXP, 0x00000000 }, \ + { AR5K_DCU_TX_FILTER, 0x00000000 }, \ + /* Unknown */ \ + { 0x1078, 0x00000000 }, \ + { 0x10b8, 0x00000000 }, \ + { 0x10f8, 0x00000000 }, \ + { 0x1138, 0x00000000 }, \ + { 0x1178, 0x00000000 }, \ + { 0x11b8, 0x00000000 }, \ + { 0x11f8, 0x00000000 }, \ + { 0x1238, 0x00000000 }, \ + { 0x1278, 0x00000000 }, \ + { 0x12b8, 0x00000000 }, \ + { 0x12f8, 0x00000000 }, \ + { 0x1338, 0x00000000 }, \ + { 0x1378, 0x00000000 }, \ + { 0x13b8, 0x00000000 }, \ + { 0x13f8, 0x00000000 }, \ + { 0x1438, 0x00000000 }, \ + { 0x1478, 0x00000000 }, \ + { 0x14b8, 0x00000000 }, \ + { 0x14f8, 0x00000000 }, \ + { 0x1538, 0x00000000 }, \ + { 0x1578, 0x00000000 }, \ + { 0x15b8, 0x00000000 }, \ + { 0x15f8, 0x00000000 }, \ + { 0x1638, 0x00000000 }, \ + { 0x1678, 0x00000000 }, \ + { 0x16b8, 0x00000000 }, \ + { 0x16f8, 0x00000000 }, \ + { 0x1738, 0x00000000 }, \ + { 0x1778, 0x00000000 }, \ + { 0x17b8, 0x00000000 }, \ + { 0x17f8, 0x00000000 }, \ + { 0x103c, 0x00000000 }, \ + { 0x107c, 0x00000000 }, \ + { 0x10bc, 0x00000000 }, \ + { 0x10fc, 0x00000000 }, \ + { 0x113c, 0x00000000 }, \ + { 0x117c, 0x00000000 }, \ + { 0x11bc, 0x00000000 }, \ + { 0x11fc, 0x00000000 }, \ + { 0x123c, 0x00000000 }, \ + { 0x127c, 0x00000000 }, \ + { 0x12bc, 0x00000000 }, \ + { 0x12fc, 0x00000000 }, \ + { 0x133c, 0x00000000 }, \ + { 0x137c, 0x00000000 }, \ + { 0x13bc, 0x00000000 }, \ + { 0x13fc, 0x00000000 }, \ + { 0x143c, 0x00000000 }, \ + { 0x147c, 0x00000000 }, \ + { AR5K_STA_ID1, 0x00000000 }, \ + { AR5K_BSS_ID0, 0x00000000 }, \ + { AR5K_BSS_ID1, 0x00000000 }, \ + { AR5K_RSSI_THR, 0x00000000 }, \ + { AR5K_BEACON_5211, 0x00000000 }, \ + { AR5K_CFP_PERIOD_5211, 0x00000000 }, \ + { AR5K_TIMER0_5211, 0x00000030 }, \ + { AR5K_TIMER1_5211, 0x0007ffff }, \ + { AR5K_TIMER2_5211, 0x01ffffff }, \ + { AR5K_TIMER3_5211, 0x00000031 }, \ + { AR5K_CFP_DUR_5211, 0x00000000 }, \ + { AR5K_RX_FILTER_5211, 0x00000000 }, \ + { AR5K_DIAG_SW_5211, 0x00000000 }, \ + { AR5K_ADDAC_TEST, 0x00000000 }, \ + { AR5K_DEFAULT_ANTENNA, 0x00000000 }, \ + { 0x805c, 0xffffc7ff }, \ + { 0x8080, 0x00000000 }, \ + { AR5K_NAV_5211, 0x00000000 }, \ + { AR5K_RTS_OK_5211, 0x00000000 }, \ + { AR5K_RTS_FAIL_5211, 0x00000000 }, \ + { AR5K_ACK_FAIL_5211, 0x00000000 }, \ + { AR5K_FCS_FAIL_5211, 0x00000000 }, \ + { AR5K_BEACON_CNT_5211, 0x00000000 }, \ + { AR5K_XRMODE, 0x2a82301a }, \ + { AR5K_XRDELAY, 0x05dc01e0 }, \ + { AR5K_XRTIMEOUT, 0x1f402710 }, \ + { AR5K_XRCHIRP, 0x01f40000 }, \ + { AR5K_XRSTOMP, 0x00001e1c }, \ + { AR5K_SLEEP0, 0x0002aaaa }, \ + { AR5K_SLEEP1, 0x02005555 }, \ + { AR5K_SLEEP2, 0x00000000 }, \ + { AR5K_BSS_IDM0, 0xffffffff }, \ + { AR5K_BSS_IDM1, 0x0000ffff }, \ + { AR5K_TXPC, 0x00000000 }, \ + { AR5K_PROFCNT_TX, 0x00000000 }, \ + { AR5K_PROFCNT_RX, 0x00000000 }, \ + { AR5K_PROFCNT_RXCLR, 0x00000000 }, \ + { AR5K_PROFCNT_CYCLE, 0x00000000 }, \ + { 0x80fc, 0x00000088 }, \ + { AR5K_RATE_DUR(0), 0x00000000 }, \ + { AR5K_RATE_DUR(1), 0x0000008c }, \ + { AR5K_RATE_DUR(2), 0x000000e4 }, \ + { AR5K_RATE_DUR(3), 0x000002d5 }, \ + { AR5K_RATE_DUR(4), 0x00000000 }, \ + { AR5K_RATE_DUR(5), 0x00000000 }, \ + { AR5K_RATE_DUR(6), 0x000000a0 }, \ + { AR5K_RATE_DUR(7), 0x000001c9 }, \ + { AR5K_RATE_DUR(8), 0x0000002c }, \ + { AR5K_RATE_DUR(9), 0x0000002c }, \ + { AR5K_RATE_DUR(10), 0x00000030 }, \ + { AR5K_RATE_DUR(11), 0x0000003c }, \ + { AR5K_RATE_DUR(12), 0x0000002c }, \ + { AR5K_RATE_DUR(13), 0x0000002c }, \ + { AR5K_RATE_DUR(14), 0x00000030 }, \ + { AR5K_RATE_DUR(15), 0x0000003c }, \ + { AR5K_RATE_DUR(16), 0x00000000 }, \ + { AR5K_RATE_DUR(17), 0x00000000 }, \ + { AR5K_RATE_DUR(18), 0x00000000 }, \ + { AR5K_RATE_DUR(19), 0x00000000 }, \ + { AR5K_RATE_DUR(20), 0x00000000 }, \ + { AR5K_RATE_DUR(21), 0x00000000 }, \ + { AR5K_RATE_DUR(22), 0x00000000 }, \ + { AR5K_RATE_DUR(23), 0x00000000 }, \ + { AR5K_RATE_DUR(24), 0x000000d5 }, \ + { AR5K_RATE_DUR(25), 0x000000df }, \ + { AR5K_RATE_DUR(26), 0x00000102 }, \ + { AR5K_RATE_DUR(27), 0x0000013a }, \ + { AR5K_RATE_DUR(28), 0x00000075 }, \ + { AR5K_RATE_DUR(29), 0x0000007f }, \ + { AR5K_RATE_DUR(30), 0x000000a2 }, \ + { AR5K_RATE_DUR(31), 0x00000000 }, \ + { 0x8100, 0x00010002}, \ + { AR5K_TSF_PARM, 0x00000001 }, \ + { 0x8108, 0x000000c0 }, \ + { AR5K_PHY_ERR_FIL, 0x00000000 }, \ + { 0x8110, 0x00000168 }, \ + { 0x8114, 0x00000000 }, \ + /* Some kind of table */ \ + { 0x87c0, 0x03020100 }, \ + { 0x87c4, 0x07060504 }, \ + { 0x87c8, 0x0b0a0908 }, \ + { 0x87cc, 0x0f0e0d0c }, \ + { 0x87d0, 0x13121110 }, \ + { 0x87d4, 0x17161514 }, \ + { 0x87d8, 0x1b1a1918 }, \ + { 0x87dc, 0x1f1e1d1c }, \ + { 0x87e0, 0x03020100 }, \ + { 0x87e4, 0x07060504 }, \ + { 0x87e8, 0x0b0a0908 }, \ + { 0x87ec, 0x0f0e0d0c }, \ + { 0x87f0, 0x13121110 }, \ + { 0x87f4, 0x17161514 }, \ + { 0x87f8, 0x1b1a1918 }, \ + { 0x87fc, 0x1f1e1d1c }, \ + /* PHY registers */ \ + { AR5K_PHY_AGC, 0x00000000 }, \ + { AR5K_PHY(3), 0xad848e19 }, \ + { AR5K_PHY(4), 0x7d28e000 }, \ + { AR5K_PHY_TIMING_3, 0x9c0a9f6b }, \ + { AR5K_PHY_ACT, 0x00000000 }, \ + { AR5K_PHY(11), 0x00022ffe }, \ + { AR5K_PHY(15), 0x00020100 }, \ + { AR5K_PHY(16), 0x206a017a }, \ + { AR5K_PHY(19), 0x1284613c }, \ + { AR5K_PHY(21), 0x00000859 }, \ + { AR5K_PHY(64), 0x00000000 }, \ + { AR5K_PHY(65), 0x00000000 }, \ + { AR5K_PHY(66), 0x00000000 }, \ + { AR5K_PHY(67), 0x00800000 }, \ + { AR5K_PHY(68), 0x00000001 }, \ + { AR5K_PHY(71), 0x0000092a }, \ + { AR5K_PHY_IQ, 0x05100000 }, \ + { AR5K_PHY(74), 0x00000001 }, \ + { AR5K_PHY(75), 0x00000004 }, \ + { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 }, \ + { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d }, \ + { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },\ + { AR5K_PHY(80), 0x00000004 }, \ + { AR5K_PHY(82), 0x9280b212 }, \ + { AR5K_PHY_RADAR, 0x5d50e188 }, \ + { AR5K_PHY(86), 0x000000ff }, \ + { AR5K_PHY(87), 0x004b6a8e }, \ + { AR5K_PHY(90), 0x000003ce }, \ + { AR5K_PHY(92), 0x192fb515 }, \ + { AR5K_PHY(93), 0x00000000 }, \ + { AR5K_PHY(94), 0x00000001 }, \ + { AR5K_PHY(95), 0x00000000 }, \ + /* Power table (32bytes) */ \ + { AR5K_PHY_PCDAC_TXPOWER(1), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(2), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(3), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(4), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(5), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(6), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(7), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(8), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(9), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(10), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(11), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(12), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(13), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(14), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(15), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(16), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(17), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(18), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(19), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(20), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(21), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(22), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(23), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(24), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(25), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(26), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(27), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(28), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(29), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(30), 0x10ff10ff }, \ + { AR5K_PHY_PCDAC_TXPOWER(31),0x10ff10ff }, \ + { AR5K_PHY(644), 0x0080a333 }, \ + { AR5K_PHY(645), 0x00206c10 }, \ + { AR5K_PHY(646), 0x009c4060 }, \ + { AR5K_PHY(647), 0x1483800a }, \ + { AR5K_PHY(648), 0x01831061 }, \ + { AR5K_PHY(649), 0x00000400 }, \ + { AR5K_PHY(650), 0x000001b5 }, \ + { AR5K_PHY(651), 0x00000000 }, \ + { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, \ + { AR5K_PHY_TXPOWER_RATE2, 0x20202020 }, \ + { AR5K_PHY(655), 0x13c889af }, \ + { AR5K_PHY(656), 0x38490a20 }, \ + { AR5K_PHY(657), 0x00007bb6 }, \ + { AR5K_PHY(658), 0x0fff3ffc }, \ + { AR5K_BB_GAIN(0), 0x00000000 }, \ + { AR5K_BB_GAIN(10), 0x0000000c }, \ + { AR5K_BB_GAIN(14), 0x00000012 }, \ + { AR5K_BB_GAIN(25), 0x00000021 }, \ + { AR5K_BB_GAIN(35), 0x0000002d }, \ + { AR5K_BB_GAIN(39), 0x00000033 }, \ +} + /* RF5111 specific BB Gain (for 5212/5111 combination) */ +#define AR5K_AR5212_RF5111_INI { \ + { AR5K_PHY_PAPD_PROBE, 0x00004883 }, \ + { AR5K_PHY_CCKTXCTL, 0x00000000 }, \ + { 0xa208, 0xd03e6788 }, \ + { AR5K_PHY_GAIN_2GHZ, 0x6448416a }, \ + { AR5K_BB_GAIN(1), 0x00000020 }, \ + { AR5K_BB_GAIN(2), 0x00000010 }, \ + { AR5K_BB_GAIN(3), 0x00000030 }, \ + { AR5K_BB_GAIN(4), 0x00000008 }, \ + { AR5K_BB_GAIN(5), 0x00000028 }, \ + { AR5K_BB_GAIN(6), 0x00000004 }, \ + { AR5K_BB_GAIN(7), 0x00000024 }, \ + { AR5K_BB_GAIN(8), 0x00000014 }, \ + { AR5K_BB_GAIN(9), 0x00000034 }, \ + { AR5K_BB_GAIN(11), 0x0000002c }, \ + { AR5K_BB_GAIN(12), 0x00000002 }, \ + { AR5K_BB_GAIN(13), 0x00000022 }, \ + { AR5K_BB_GAIN(15), 0x00000032 }, \ + { AR5K_BB_GAIN(16), 0x0000000a }, \ + { AR5K_BB_GAIN(17), 0x0000002a }, \ + { AR5K_BB_GAIN(18), 0x00000006 }, \ + { AR5K_BB_GAIN(19), 0x00000026 }, \ + { AR5K_BB_GAIN(20), 0x00000016 }, \ + { AR5K_BB_GAIN(21), 0x00000036 }, \ + { AR5K_BB_GAIN(22), 0x0000000e }, \ + { AR5K_BB_GAIN(23), 0x0000002e }, \ + { AR5K_BB_GAIN(24), 0x00000001 }, \ + { AR5K_BB_GAIN(26), 0x00000011 }, \ + { AR5K_BB_GAIN(27), 0x00000031 }, \ + { AR5K_BB_GAIN(28), 0x00000009 }, \ + { AR5K_BB_GAIN(29), 0x00000029 }, \ + { AR5K_BB_GAIN(30), 0x00000005 }, \ + { AR5K_BB_GAIN(31), 0x00000025 }, \ + { AR5K_BB_GAIN(32), 0x00000015 }, \ + { AR5K_BB_GAIN(33), 0x00000035 }, \ + { AR5K_BB_GAIN(34), 0x0000000d }, \ + { AR5K_BB_GAIN(36), 0x00000003 }, \ + { AR5K_BB_GAIN(37), 0x00000023 }, \ + { AR5K_BB_GAIN(39), 0x00000013 }, \ + { AR5K_BB_GAIN(40), 0x0000000b }, \ + { AR5K_BB_GAIN(41), 0x0000002b }, \ + { AR5K_BB_GAIN(42), 0x0000002b }, \ + { AR5K_BB_GAIN(43), 0x0000002b }, \ + { AR5K_BB_GAIN(44), 0x0000002b }, \ + { AR5K_BB_GAIN(45), 0x0000002b }, \ + { AR5K_BB_GAIN(46), 0x0000002b }, \ + { AR5K_BB_GAIN(47), 0x0000002b }, \ + { AR5K_BB_GAIN(48), 0x0000002b }, \ + { AR5K_BB_GAIN(49), 0x0000002b }, \ + { AR5K_BB_GAIN(50), 0x0000002b }, \ + { AR5K_BB_GAIN(51), 0x0000002b }, \ + { AR5K_BB_GAIN(52), 0x0000002b }, \ + { AR5K_BB_GAIN(53), 0x0000002b }, \ + { AR5K_BB_GAIN(54), 0x0000002b }, \ + { AR5K_BB_GAIN(55), 0x0000002b }, \ + { AR5K_BB_GAIN(56), 0x0000002b }, \ + { AR5K_BB_GAIN(57), 0x0000002b }, \ + { AR5K_BB_GAIN(58), 0x0000002b }, \ + { AR5K_BB_GAIN(59), 0x0000002b }, \ + { AR5K_BB_GAIN(60), 0x0000002b }, \ + { AR5K_BB_GAIN(61), 0x0000002b }, \ + { AR5K_BB_GAIN(62), 0x00000002 }, \ + { AR5K_BB_GAIN(63), 0x00000016 }, \ +} + /* RF5112 specific BB Gain (for 5212/5111 combination) */ +#define AR5K_AR5212_RF5112_INI { \ + { AR5K_PHY_PAPD_PROBE, 0x00004882 }, \ + { AR5K_BB_GAIN(1), 0x00000001 }, \ + { AR5K_BB_GAIN(2), 0x00000002 }, \ + { AR5K_BB_GAIN(3), 0x00000003 }, \ + { AR5K_BB_GAIN(4), 0x00000004 }, \ + { AR5K_BB_GAIN(5), 0x00000005 }, \ + { AR5K_BB_GAIN(6), 0x00000008 }, \ + { AR5K_BB_GAIN(7), 0x00000009 }, \ + { AR5K_BB_GAIN(8), 0x0000000a }, \ + { AR5K_BB_GAIN(9), 0x0000000b }, \ + { AR5K_BB_GAIN(11), 0x0000000d }, \ + { AR5K_BB_GAIN(12), 0x00000010 }, \ + { AR5K_BB_GAIN(13), 0x00000011 }, \ + { AR5K_BB_GAIN(15), 0x00000013 }, \ + { AR5K_BB_GAIN(16), 0x00000014 }, \ + { AR5K_BB_GAIN(17), 0x00000015 }, \ + { AR5K_BB_GAIN(18), 0x00000018 }, \ + { AR5K_BB_GAIN(19), 0x00000019 }, \ + { AR5K_BB_GAIN(20), 0x0000001a }, \ + { AR5K_BB_GAIN(21), 0x0000001b }, \ + { AR5K_BB_GAIN(22), 0x0000001c }, \ + { AR5K_BB_GAIN(23), 0x0000001d }, \ + { AR5K_BB_GAIN(24), 0x00000020 }, \ + { AR5K_BB_GAIN(26), 0x00000022 }, \ + { AR5K_BB_GAIN(27), 0x00000023 }, \ + { AR5K_BB_GAIN(28), 0x00000024 }, \ + { AR5K_BB_GAIN(29), 0x00000025 }, \ + { AR5K_BB_GAIN(30), 0x00000028 }, \ + { AR5K_BB_GAIN(31), 0x00000029 }, \ + { AR5K_BB_GAIN(32), 0x0000002a }, \ + { AR5K_BB_GAIN(33), 0x0000002b }, \ + { AR5K_BB_GAIN(34), 0x0000002c }, \ + { AR5K_BB_GAIN(36), 0x00000030 }, \ + { AR5K_BB_GAIN(37), 0x00000031 }, \ + { AR5K_BB_GAIN(38), 0x00000032 }, \ + { AR5K_BB_GAIN(40), 0x00000034 }, \ + { AR5K_BB_GAIN(41), 0x00000035 }, \ + { AR5K_BB_GAIN(42), 0x00000035 }, \ + { AR5K_BB_GAIN(43), 0x00000035 }, \ + { AR5K_BB_GAIN(44), 0x00000035 }, \ + { AR5K_BB_GAIN(45), 0x00000035 }, \ + { AR5K_BB_GAIN(46), 0x00000035 }, \ + { AR5K_BB_GAIN(47), 0x00000035 }, \ + { AR5K_BB_GAIN(48), 0x00000035 }, \ + { AR5K_BB_GAIN(49), 0x00000035 }, \ + { AR5K_BB_GAIN(50), 0x00000035 }, \ + { AR5K_BB_GAIN(51), 0x00000035 }, \ + { AR5K_BB_GAIN(52), 0x00000035 }, \ + { AR5K_BB_GAIN(53), 0x00000035 }, \ + { AR5K_BB_GAIN(54), 0x00000035 }, \ + { AR5K_BB_GAIN(55), 0x00000035 }, \ + { AR5K_BB_GAIN(56), 0x00000035 }, \ + { AR5K_BB_GAIN(57), 0x00000035 }, \ + { AR5K_BB_GAIN(58), 0x00000035 }, \ + { AR5K_BB_GAIN(59), 0x00000035 }, \ + { AR5K_BB_GAIN(60), 0x00000035 }, \ + { AR5K_BB_GAIN(61), 0x00000035 }, \ + { AR5K_BB_GAIN(62), 0x00000010 }, \ + { AR5K_BB_GAIN(63), 0x0000001a }, \ +} + struct ath5k_ar5210_ini_mode{ u_int16_t mode_register; u_int32_t mode_base, mode_turbo; @@ -1376,567 +1961,6 @@ AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x2020 }, \ } -#define AR5K_AR5211_INI { \ - { 0x000c, 0x00000000 }, \ - { 0x0028, 0x84849c9c }, \ - { 0x002c, 0x7c7c7c7c }, \ - { 0x0034, 0x00000005 }, \ - { 0x0040, 0x00000000 }, \ - { 0x0044, 0x00000008 }, \ - { 0x0048, 0x00000008 }, \ - { 0x004c, 0x00000010 }, \ - { 0x0050, 0x00000000 }, \ - { 0x0054, 0x0000001f }, \ - { 0x0800, 0x00000000 }, \ - { 0x0804, 0x00000000 }, \ - { 0x0808, 0x00000000 }, \ - { 0x080c, 0x00000000 }, \ - { 0x0810, 0x00000000 }, \ - { 0x0814, 0x00000000 }, \ - { 0x0818, 0x00000000 }, \ - { 0x081c, 0x00000000 }, \ - { 0x0820, 0x00000000 }, \ - { 0x0824, 0x00000000 }, \ - { 0x1230, 0x00000000 }, \ - { 0x8004, 0x00000000 }, \ - { 0x8008, 0x00000000 }, \ - { 0x800c, 0x00000000 }, \ - { 0x8018, 0x00000000 }, \ - { 0x8024, 0x00000000 }, \ - { 0x8028, 0x00000030 }, \ - { 0x802c, 0x0007ffff }, \ - { 0x8030, 0x01ffffff }, \ - { 0x8034, 0x00000031 }, \ - { 0x8038, 0x00000000 }, \ - { 0x803c, 0x00000000 }, \ - { 0x8040, 0x00000000 }, \ - { 0x8044, 0x00000002 }, \ - { 0x8048, 0x00000000 }, \ - { 0x8054, 0x00000000 }, \ - { 0x8058, 0x00000000 }, \ - /* PHY registers */ \ - { 0x9808, 0x00000000 }, \ - { 0x980c, 0x2d849093 }, \ - { 0x9810, 0x7d32e000 }, \ - { 0x9814, 0x00000f6b }, \ - { 0x981c, 0x00000000 }, \ - { 0x982c, 0x00026ffe }, \ - { 0x9830, 0x00000000 }, \ - { 0x983c, 0x00020100 }, \ - { 0x9840, 0x206a017a }, \ - { 0x984c, 0x1284613c }, \ - { 0x9854, 0x00000859 }, \ - { 0x9868, 0x409a4190 }, \ - { 0x986c, 0x050cb081 }, \ - { 0x9870, 0x0000000f }, \ - { 0x9874, 0x00000080 }, \ - { 0x9878, 0x0000000c }, \ - { 0x9900, 0x00000000 }, \ - { 0x9904, 0x00000000 }, \ - { 0x9908, 0x00000000 }, \ - { 0x990c, 0x00800000 }, \ - { 0x9910, 0x00000001 }, \ - { 0x991c, 0x0000092a }, \ - { 0x9920, 0x00000000 }, \ - { 0x9924, 0x00058a05 }, \ - { 0x9928, 0x00000001 }, \ - { 0x992c, 0x00000000 }, \ - { 0x9930, 0x00000000 }, \ - { 0x9934, 0x00000000 }, \ - { 0x9938, 0x00000000 }, \ - { 0x993c, 0x0000003f }, \ - { 0x9940, 0x00000004 }, \ - { 0x9948, 0x00000000 }, \ - { 0x994c, 0x00000000 }, \ - { 0x9950, 0x00000000 }, \ - { 0x9954, 0x5d50f14c }, \ - { 0x9958, 0x00000018 }, \ - { 0x995c, 0x004b6a8e }, \ - { 0xa184, 0x06ff05ff }, \ - { 0xa188, 0x07ff07ff }, \ - { 0xa18c, 0x08ff08ff }, \ - { 0xa190, 0x09ff09ff }, \ - { 0xa194, 0x0aff0aff }, \ - { 0xa198, 0x0bff0bff }, \ - { 0xa19c, 0x0cff0cff }, \ - { 0xa1a0, 0x0dff0dff }, \ - { 0xa1a4, 0x0fff0eff }, \ - { 0xa1a8, 0x12ff12ff }, \ - { 0xa1ac, 0x14ff13ff }, \ - { 0xa1b0, 0x16ff15ff }, \ - { 0xa1b4, 0x19ff17ff }, \ - { 0xa1b8, 0x1bff1aff }, \ - { 0xa1bc, 0x1eff1dff }, \ - { 0xa1c0, 0x23ff20ff }, \ - { 0xa1c4, 0x27ff25ff }, \ - { 0xa1c8, 0x2cff29ff }, \ - { 0xa1cc, 0x31ff2fff }, \ - { 0xa1d0, 0x37ff34ff }, \ - { 0xa1d4, 0x3aff3aff }, \ - { 0xa1d8, 0x3aff3aff }, \ - { 0xa1dc, 0x3aff3aff }, \ - { 0xa1e0, 0x3aff3aff }, \ - { 0xa1e4, 0x3aff3aff }, \ - { 0xa1e8, 0x3aff3aff }, \ - { 0xa1ec, 0x3aff3aff }, \ - { 0xa1f0, 0x3aff3aff }, \ - { 0xa1f4, 0x3aff3aff }, \ - { 0xa1f8, 0x3aff3aff }, \ - { 0xa1fc, 0x3aff3aff }, \ - /* BB gain table (64bytes) */ \ - { 0x9b00, 0x00000000 }, \ - { 0x9b04, 0x00000020 }, \ - { 0x9b08, 0x00000010 }, \ - { 0x9b0c, 0x00000030 }, \ - { 0x9b10, 0x00000008 }, \ - { 0x9b14, 0x00000028 }, \ - { 0x9b18, 0x00000004 }, \ - { 0x9b1c, 0x00000024 }, \ - { 0x9b20, 0x00000014 }, \ - { 0x9b24, 0x00000034 }, \ - { 0x9b28, 0x0000000c }, \ - { 0x9b2c, 0x0000002c }, \ - { 0x9b30, 0x00000002 }, \ - { 0x9b34, 0x00000022 }, \ - { 0x9b38, 0x00000012 }, \ - { 0x9b3c, 0x00000032 }, \ - { 0x9b40, 0x0000000a }, \ - { 0x9b44, 0x0000002a }, \ - { 0x9b48, 0x00000006 }, \ - { 0x9b4c, 0x00000026 }, \ - { 0x9b50, 0x00000016 }, \ - { 0x9b54, 0x00000036 }, \ - { 0x9b58, 0x0000000e }, \ - { 0x9b5c, 0x0000002e }, \ - { 0x9b60, 0x00000001 }, \ - { 0x9b64, 0x00000021 }, \ - { 0x9b68, 0x00000011 }, \ - { 0x9b6c, 0x00000031 }, \ - { 0x9b70, 0x00000009 }, \ - { 0x9b74, 0x00000029 }, \ - { 0x9b78, 0x00000005 }, \ - { 0x9b7c, 0x00000025 }, \ - { 0x9b80, 0x00000015 }, \ - { 0x9b84, 0x00000035 }, \ - { 0x9b88, 0x0000000d }, \ - { 0x9b8c, 0x0000002d }, \ - { 0x9b90, 0x00000003 }, \ - { 0x9b94, 0x00000023 }, \ - { 0x9b98, 0x00000013 }, \ - { 0x9b9c, 0x00000033 }, \ - { 0x9ba0, 0x0000000b }, \ - { 0x9ba4, 0x0000002b }, \ - { 0x9ba8, 0x0000002b }, \ - { 0x9bac, 0x0000002b }, \ - { 0x9bb0, 0x0000002b }, \ - { 0x9bb4, 0x0000002b }, \ - { 0x9bb8, 0x0000002b }, \ - { 0x9bbc, 0x0000002b }, \ - { 0x9bc0, 0x0000002b }, \ - { 0x9bc4, 0x0000002b }, \ - { 0x9bc8, 0x0000002b }, \ - { 0x9bcc, 0x0000002b }, \ - { 0x9bd0, 0x0000002b }, \ - { 0x9bd4, 0x0000002b }, \ - { 0x9bd8, 0x0000002b }, \ - { 0x9bdc, 0x0000002b }, \ - { 0x9be0, 0x0000002b }, \ - { 0x9be4, 0x0000002b }, \ - { 0x9be8, 0x0000002b }, \ - { 0x9bec, 0x0000002b }, \ - { 0x9bf0, 0x0000002b }, \ - { 0x9bf4, 0x0000002b }, \ - { 0x9bf8, 0x00000002 }, \ - { 0x9bfc, 0x00000016 }, \ - /* PHY activation */ \ - { 0x98d4, 0x00000020 }, \ - { 0x98d8, 0x00601068 }, \ -} - -struct ath5k_ar5212_ini { - u_int8_t ini_flags; - u_int16_t ini_register; - u_int32_t ini_value; - -#define AR5K_INI_FLAG_511X 0x00 -#define AR5K_INI_FLAG_5111 0x01 -#define AR5K_INI_FLAG_5112 0x02 -#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) -}; - -#define AR5K_AR5212_INI { \ - { AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 }, \ - { AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 }, \ - { AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 }, \ - { AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f }, \ - { AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x081c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0820, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x0824, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1230, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1270, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1078, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1138, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1178, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1238, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1278, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1338, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1378, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1438, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1478, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x14f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1538, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1578, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x15f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1638, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1678, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x16f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1738, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x1778, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17b8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x17f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x103c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x107c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x10fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x113c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x117c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x11fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x123c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x127c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x12fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x133c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x137c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13bc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x13fc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x143c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x147c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8004, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8008, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x800c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8018, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8020, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8024, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8028, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x802c, 0x0007ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8030, 0x01ffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x8034, 0x00000031 }, \ - { AR5K_INI_FLAG_BOTH, 0x8038, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x803c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8048, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8054, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8058, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x805c, 0xffffc7ff }, \ - { AR5K_INI_FLAG_BOTH, 0x8080, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8084, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8088, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x808c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8090, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8094, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8098, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c0, 0x2a82301a }, \ - { AR5K_INI_FLAG_BOTH, 0x80c4, 0x05dc01e0 }, \ - { AR5K_INI_FLAG_BOTH, 0x80c8, 0x1f402710 }, \ - { AR5K_INI_FLAG_BOTH, 0x80cc, 0x01f40000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80d0, 0x00001e1c }, \ - { AR5K_INI_FLAG_BOTH, 0x80d4, 0x0002aaaa }, \ - { AR5K_INI_FLAG_BOTH, 0x80d8, 0x02005555 }, \ - { AR5K_INI_FLAG_BOTH, 0x80dc, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80e0, 0xffffffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e4, 0x0000ffff }, \ - { AR5K_INI_FLAG_BOTH, 0x80e8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80ec, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f0, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f4, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80f8, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x80fc, 0x00000088 }, \ - { AR5K_INI_FLAG_BOTH, 0x8700, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8704, 0x0000008c }, \ - { AR5K_INI_FLAG_BOTH, 0x8708, 0x000000e4 }, \ - { AR5K_INI_FLAG_BOTH, 0x870c, 0x000002d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8710, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8714, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8718, 0x000000a0 }, \ - { AR5K_INI_FLAG_BOTH, 0x871c, 0x000001c9 }, \ - { AR5K_INI_FLAG_BOTH, 0x8720, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8724, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8728, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x872c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8730, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8734, 0x0000002c }, \ - { AR5K_INI_FLAG_BOTH, 0x8738, 0x00000030 }, \ - { AR5K_INI_FLAG_BOTH, 0x873c, 0x0000003c }, \ - { AR5K_INI_FLAG_BOTH, 0x8740, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8744, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8748, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x874c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8750, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8754, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8758, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x875c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8760, 0x000000d5 }, \ - { AR5K_INI_FLAG_BOTH, 0x8764, 0x000000df }, \ - { AR5K_INI_FLAG_BOTH, 0x8768, 0x00000102 }, \ - { AR5K_INI_FLAG_BOTH, 0x876c, 0x0000013a }, \ - { AR5K_INI_FLAG_BOTH, 0x8770, 0x00000075 }, \ - { AR5K_INI_FLAG_BOTH, 0x8774, 0x0000007f }, \ - { AR5K_INI_FLAG_BOTH, 0x8778, 0x000000a2 }, \ - { AR5K_INI_FLAG_BOTH, 0x877c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8100, 0x00010002 }, \ - { AR5K_INI_FLAG_BOTH, 0x8104, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x8108, 0x000000c0 }, \ - { AR5K_INI_FLAG_BOTH, 0x810c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x8110, 0x00000168 }, \ - { AR5K_INI_FLAG_BOTH, 0x8114, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87c8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87cc, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87d0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87d8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87dc, 0x1f1e1d1c }, \ - { AR5K_INI_FLAG_BOTH, 0x87e0, 0x03020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e4, 0x07060504 }, \ - { AR5K_INI_FLAG_BOTH, 0x87e8, 0x0b0a0908 }, \ - { AR5K_INI_FLAG_BOTH, 0x87ec, 0x0f0e0d0c }, \ - { AR5K_INI_FLAG_BOTH, 0x87f0, 0x13121110 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f4, 0x17161514 }, \ - { AR5K_INI_FLAG_BOTH, 0x87f8, 0x1b1a1918 }, \ - { AR5K_INI_FLAG_BOTH, 0x87fc, 0x1f1e1d1c }, \ - /* PHY registers */ \ - { AR5K_INI_FLAG_BOTH, 0x9808, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x980c, 0xad848e19 }, \ - { AR5K_INI_FLAG_BOTH, 0x9810, 0x7d28e000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9814, 0x9c0a9f6b }, \ - { AR5K_INI_FLAG_BOTH, 0x981c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x982c, 0x00022ffe }, \ - { AR5K_INI_FLAG_BOTH, 0x983c, 0x00020100 }, \ - { AR5K_INI_FLAG_BOTH, 0x9840, 0x206a017a }, \ - { AR5K_INI_FLAG_BOTH, 0x984c, 0x1284613c }, \ - { AR5K_INI_FLAG_BOTH, 0x9854, 0x00000859 }, \ - { AR5K_INI_FLAG_BOTH, 0x9900, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9904, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a }, \ - { AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9934, 0x1e1f2022 }, \ - { AR5K_INI_FLAG_BOTH, 0x9938, 0x0a0b0c0d }, \ - { AR5K_INI_FLAG_BOTH, 0x993c, 0x0000003f }, \ - { AR5K_INI_FLAG_BOTH, 0x9940, 0x00000004 }, \ - { AR5K_INI_FLAG_BOTH, 0x9948, 0x9280b212 }, \ - { AR5K_INI_FLAG_BOTH, 0x9954, 0x5d50e188 }, \ - { AR5K_INI_FLAG_BOTH, 0x9958, 0x000000ff }, \ - { AR5K_INI_FLAG_BOTH, 0x995c, 0x004b6a8e }, \ - { AR5K_INI_FLAG_BOTH, 0x9968, 0x000003ce }, \ - { AR5K_INI_FLAG_BOTH, 0x9970, 0x192fb515 }, \ - { AR5K_INI_FLAG_BOTH, 0x9974, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9978, 0x00000001 }, \ - { AR5K_INI_FLAG_BOTH, 0x997c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa184, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa188, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa18c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa190, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa194, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa198, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa19c, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1a8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ac, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1b8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1bc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1c8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1cc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1d8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1dc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1e8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1ec, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f0, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff }, \ - { AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 }, \ - { AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 }, \ - { AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 }, \ - { AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a }, \ - { AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 }, \ - { AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 }, \ - { AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 }, \ - { AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0xa234, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa238, 0x20202020 }, \ - { AR5K_INI_FLAG_BOTH, 0xa23c, 0x13c889af }, \ - { AR5K_INI_FLAG_BOTH, 0xa240, 0x38490a20 }, \ - { AR5K_INI_FLAG_BOTH, 0xa244, 0x00007bb6 }, \ - { AR5K_INI_FLAG_BOTH, 0xa248, 0x0fff3ffc }, \ - { AR5K_INI_FLAG_BOTH, 0x9b00, 0x00000000 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b28, 0x0000000c }, \ - { AR5K_INI_FLAG_BOTH, 0x9b38, 0x00000012 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \ - { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \ - { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \ - /* RF5111 specific */ \ - { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \ - { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \ - { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \ - { AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a }, \ - { AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 }, \ - { AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 }, \ - { AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 }, \ - { AR5K_INI_FLAG_5111, 0x9b10, 0x00000008 }, \ - { AR5K_INI_FLAG_5111, 0x9b14, 0x00000028 }, \ - { AR5K_INI_FLAG_5111, 0x9b18, 0x00000004 }, \ - { AR5K_INI_FLAG_5111, 0x9b1c, 0x00000024 }, \ - { AR5K_INI_FLAG_5111, 0x9b20, 0x00000014 }, \ - { AR5K_INI_FLAG_5111, 0x9b24, 0x00000034 }, \ - { AR5K_INI_FLAG_5111, 0x9b2c, 0x0000002c }, \ - { AR5K_INI_FLAG_5111, 0x9b30, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9b34, 0x00000022 }, \ - { AR5K_INI_FLAG_5111, 0x9b3c, 0x00000032 }, \ - { AR5K_INI_FLAG_5111, 0x9b40, 0x0000000a }, \ - { AR5K_INI_FLAG_5111, 0x9b44, 0x0000002a }, \ - { AR5K_INI_FLAG_5111, 0x9b48, 0x00000006 }, \ - { AR5K_INI_FLAG_5111, 0x9b4c, 0x00000026 }, \ - { AR5K_INI_FLAG_5111, 0x9b50, 0x00000016 }, \ - { AR5K_INI_FLAG_5111, 0x9b54, 0x00000036 }, \ - { AR5K_INI_FLAG_5111, 0x9b58, 0x0000000e }, \ - { AR5K_INI_FLAG_5111, 0x9b5c, 0x0000002e }, \ - { AR5K_INI_FLAG_5111, 0x9b60, 0x00000001 }, \ - { AR5K_INI_FLAG_5111, 0x9b68, 0x00000011 }, \ - { AR5K_INI_FLAG_5111, 0x9b6c, 0x00000031 }, \ - { AR5K_INI_FLAG_5111, 0x9b70, 0x00000009 }, \ - { AR5K_INI_FLAG_5111, 0x9b74, 0x00000029 }, \ - { AR5K_INI_FLAG_5111, 0x9b78, 0x00000005 }, \ - { AR5K_INI_FLAG_5111, 0x9b7c, 0x00000025 }, \ - { AR5K_INI_FLAG_5111, 0x9b80, 0x00000015 }, \ - { AR5K_INI_FLAG_5111, 0x9b84, 0x00000035 }, \ - { AR5K_INI_FLAG_5111, 0x9b88, 0x0000000d }, \ - { AR5K_INI_FLAG_5111, 0x9b90, 0x00000003 }, \ - { AR5K_INI_FLAG_5111, 0x9b94, 0x00000023 }, \ - { AR5K_INI_FLAG_5111, 0x9b98, 0x00000013 }, \ - { AR5K_INI_FLAG_5111, 0x9ba0, 0x0000000b }, \ - { AR5K_INI_FLAG_5111, 0x9ba4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9ba8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bac, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bb8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bbc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bc8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bcc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bd8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bdc, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9be8, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bec, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf0, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \ - { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \ - { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \ - /* RF5112 specific */ \ - { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \ - { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \ - { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \ - { AR5K_INI_FLAG_5112, 0x9b0c, 0x00000003 }, \ - { AR5K_INI_FLAG_5112, 0x9b10, 0x00000004 }, \ - { AR5K_INI_FLAG_5112, 0x9b14, 0x00000005 }, \ - { AR5K_INI_FLAG_5112, 0x9b18, 0x00000008 }, \ - { AR5K_INI_FLAG_5112, 0x9b1c, 0x00000009 }, \ - { AR5K_INI_FLAG_5112, 0x9b20, 0x0000000a }, \ - { AR5K_INI_FLAG_5112, 0x9b24, 0x0000000b }, \ - { AR5K_INI_FLAG_5112, 0x9b2c, 0x0000000d }, \ - { AR5K_INI_FLAG_5112, 0x9b30, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9b34, 0x00000011 }, \ - { AR5K_INI_FLAG_5112, 0x9b3c, 0x00000013 }, \ - { AR5K_INI_FLAG_5112, 0x9b40, 0x00000014 }, \ - { AR5K_INI_FLAG_5112, 0x9b44, 0x00000015 }, \ - { AR5K_INI_FLAG_5112, 0x9b48, 0x00000018 }, \ - { AR5K_INI_FLAG_5112, 0x9b4c, 0x00000019 }, \ - { AR5K_INI_FLAG_5112, 0x9b50, 0x0000001a }, \ - { AR5K_INI_FLAG_5112, 0x9b54, 0x0000001b }, \ - { AR5K_INI_FLAG_5112, 0x9b58, 0x0000001c }, \ - { AR5K_INI_FLAG_5112, 0x9b5c, 0x0000001d }, \ - { AR5K_INI_FLAG_5112, 0x9b60, 0x00000020 }, \ - { AR5K_INI_FLAG_5112, 0x9b68, 0x00000022 }, \ - { AR5K_INI_FLAG_5112, 0x9b6c, 0x00000023 }, \ - { AR5K_INI_FLAG_5112, 0x9b70, 0x00000024 }, \ - { AR5K_INI_FLAG_5112, 0x9b74, 0x00000025 }, \ - { AR5K_INI_FLAG_5112, 0x9b78, 0x00000028 }, \ - { AR5K_INI_FLAG_5112, 0x9b7c, 0x00000029 }, \ - { AR5K_INI_FLAG_5112, 0x9b80, 0x0000002a }, \ - { AR5K_INI_FLAG_5112, 0x9b84, 0x0000002b }, \ - { AR5K_INI_FLAG_5112, 0x9b88, 0x0000002c }, \ - { AR5K_INI_FLAG_5112, 0x9b90, 0x00000030 }, \ - { AR5K_INI_FLAG_5112, 0x9b94, 0x00000031 }, \ - { AR5K_INI_FLAG_5112, 0x9b98, 0x00000032 }, \ - { AR5K_INI_FLAG_5112, 0x9ba0, 0x00000034 }, \ - { AR5K_INI_FLAG_5112, 0x9ba4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9ba8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bac, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bb8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bbc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bc8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bcc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bd8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bdc, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9be8, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bec, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf0, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf4, 0x00000035 }, \ - { AR5K_INI_FLAG_5112, 0x9bf8, 0x00000010 }, \ - { AR5K_INI_FLAG_5112, 0x9bfc, 0x0000001a }, \ -} - struct ath5k_ar5211_ini_mode { u_int16_t mode_register; u_int32_t mode_value[4]; @@ -1986,6 +2010,11 @@ u_int32_t mode_value[2][5]; }; +#define AR5K_INI_FLAG_511X 0x00 +#define AR5K_INI_FLAG_5111 0x01 +#define AR5K_INI_FLAG_5112 0x02 +#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) + #define AR5K_AR5212_INI_MODE { \ { 0x0030, AR5K_INI_FLAG_511X, { \ { 0, }, \ @@ -2159,6 +2188,7 @@ }; #define AR5K_AR5211_INI_RF { \ +/* Static */ \ { 0x0000a204, { 0x00000000, 0x00000000 } }, \ { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \ { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \ @@ -2170,6 +2200,7 @@ { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \ { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \ { 0x0000a22c, { 0x00000020, 0x00000020 } }, \ +/* Bank 6 ? */ \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ @@ -2187,7 +2218,7 @@ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \ { 0x000098d4, { 0x00000000, 0x00000004 } }, \ - \ +/* Bank 7 ? */ \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \ { 0x0000989c, { 0x00000000, 0x00000000 } }, \