Index: ath5k_hw.c =================================================================== --- ath5k_hw.c (revision 2539) +++ ath5k_hw.c (revision 2595) @@ -95,37 +95,39 @@ /* * Initial register dumps */ + +/* + * MAC/PHY Settings + */ +/* Common for all modes */ static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI; static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI; -static const struct ath5k_ar5211_ini_mode ar5211_mode[] = AR5K_AR5211_INI_MODE; static const struct ath5k_ini ar5212_ini[] = AR5K_AR5212_INI; -static const struct ath5k_ar5212_ini_mode ar5212_mode[] = AR5K_AR5212_INI_MODE; - +/* Mode-specific settings */ +static const struct ath5k_ini_mode ar5211_ini_mode[] = AR5K_AR5211_INI_MODE; +static const struct ath5k_ini_mode ar5212_ini_mode[] = AR5K_AR5212_INI_MODE; +static const struct ath5k_ini_mode ar5212_rf5111_ini_mode[] = AR5K_AR5212_RF5111_INI_MODE; +static const struct ath5k_ini_mode ar5212_rf5112_ini_mode[] = AR5K_AR5212_RF5112_INI_MODE; /* RF Initial BB gain settings */ -static const struct ath5k_ini rf5111_bbgain_ini[] = AR5K_RF5111_BBGAIN_INI; -static const struct ath5k_ini rf5112_bbgain_ini[] = AR5K_RF5112_BBGAIN_INI; +static const struct ath5k_ini rf5111_ini_bbgain[] = AR5K_RF5111_INI_BBGAIN; +static const struct ath5k_ini rf5112_ini_bbgain[] = AR5K_RF5112_INI_BBGAIN; -/* This is going out soon */ -static const struct ath5k_ar5211_ini_rf ar5211_rf[] = AR5K_AR5211_INI_RF; - - /* - * Initial gain optimization values + * RF Settings */ -static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT; -static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT; - -/* - * Initial register settings for the radio chipsets - */ /* RF Banks */ static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF; static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF; static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF; -/* Common (5111/5112) rf gain table */ -static const struct ath5k_ini_rfgain ath5k_rfg[] = AR5K_INI_RFGAIN; +/* Initial mode-specific RF gain table for 5111/5112 */ +static const struct ath5k_ini_rfgain rf5111_ini_rfgain[] = AR5K_RF5111_INI_RFGAIN; +static const struct ath5k_ini_rfgain rf5112_ini_rfgain[] = AR5K_RF5112_INI_RFGAIN; +/* Initial gain optimization tables */ +static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT; +static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT; + /* * Enable to overwrite the country code (use "00" for debug) */ @@ -364,6 +366,8 @@ /* Write initial registers */ for (i = 0; i < size ; i++) { + /* On channel change there is + * no need to mess with PCU */ if (change_channel == TRUE && ini_regs[i].ini_register >= AR5K_PCU_MIN && ini_regs[i].ini_register <= AR5K_PCU_MAX) @@ -383,7 +387,20 @@ } } +static void +ath5k_hw_ini_mode_registers(struct ath_hal *hal, int size, + const struct ath5k_ini_mode *ini_mode, u_int8_t mode) +{ + int i; + for (i = 0; i < size; i++) { + AR5K_REG_WAIT(i); + AR5K_REG_WRITE((u_int32_t)ini_mode[i].mode_register, + ini_mode[i].mode_value[mode]); + } + +} + /***************************************\ Attach/Detach Functions \***************************************/ @@ -402,8 +419,6 @@ u_int32_t srev; *status = AR5K_EINVAL; - /* TODO:Use eeprom_magic to verify chipset */ - /* * Check if device is a known one */ @@ -531,7 +546,7 @@ * Get card capabilities, values, ... */ - if (ath5k_eeprom_init(hal) != 0) { + if (ath5k_hw_eeprom_init(hal) != 0) { *status = AR5K_EELOCKED; AR5K_PRINT("unable to init EEPROM\n"); goto failed; @@ -546,7 +561,7 @@ } /* Get MAC address */ - if ((*status = ath5k_eeprom_read_mac(hal, mac)) != 0) { + if ((*status = ath5k_hw_eeprom_read_mac(hal, mac)) != 0) { *status = AR5K_EEBADMAC; AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", device); @@ -593,6 +608,8 @@ ath5k_hw_get_part_name(AR5K_VERSION_VER,hal->ah_mac_srev)); printk(KERN_INFO "ath_hal: PHY version: %s\n", ath5k_hw_get_part_name(AR5K_VERSION_RAD,hal->ah_radio_5ghz_revision)); + printk(KERN_INFO "ath_hal: EEPROM version: %x.%x\n", + (hal->ah_ee_version & 0xF000) >> 12, hal->ah_ee_version & 0xFFF); return (hal); @@ -631,25 +648,34 @@ if (flags & CHANNEL_2GHZ) { mode |= AR5K_PHY_MODE_FREQ_2GHZ; clock |= AR5K_PHY_PLL_44MHZ; + + if (flags & CHANNEL_CCK) { + mode |= AR5K_PHY_MODE_MOD_CCK; + } else if (flags & CHANNEL_OFDM) { + /* XXX: Dynamic OFDM/CCK is not supported by the AR5211 + * so we set MOD_OFDM for plain g (no CCK headers) + * operation. We need to test this, 5211 might + * support ofdm-only g after all, there are also + * initial register values in the code for g + * mode (see ath5k_hw.h). */ + if (hal->ah_version == AR5K_AR5211) { + mode |= AR5K_PHY_MODE_MOD_OFDM; + } else { + mode |= AR5K_PHY_MODE_MOD_DYN; + } + } else { + AR5K_PRINT("invalid radio modulation mode\n"); + return (FALSE); + } } else if (flags & CHANNEL_5GHZ) { mode |= AR5K_PHY_MODE_FREQ_5GHZ; clock |= AR5K_PHY_PLL_40MHZ; - } else { - AR5K_PRINT("invalid radio frequency mode\n"); - return (FALSE); - } - - if (flags & CHANNEL_CCK) { - mode |= AR5K_PHY_MODE_MOD_CCK; - } else if (flags & CHANNEL_G) { - /* Dynamic OFDM/CCK is not supported by the AR5211 */ - if (hal->ah_version == AR5K_AR5211) { - mode |= AR5K_PHY_MODE_MOD_CCK; + if (flags & CHANNEL_OFDM) { + mode |= AR5K_PHY_MODE_MOD_OFDM; } else { - mode |= AR5K_PHY_MODE_MOD_DYN; + AR5K_PRINT("invalid radio modulation mode\n"); + return (FALSE); } - } else if (flags & CHANNEL_OFDM) { - mode |= AR5K_PHY_MODE_MOD_OFDM; } else { AR5K_PRINT("invalid radio frequency mode\n"); return (FALSE); @@ -784,7 +810,6 @@ /* * Get the rate table for a specific operation mode - * TODO:Limit this per chipset */ const AR5K_RATE_TABLE * ath5k_hw_get_rate_table(struct ath_hal *hal, u_int mode) @@ -844,7 +869,7 @@ struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int8_t mac[ETH_ALEN]; u_int32_t data, noise_floor, s_seq, s_ant, s_led[3]; - u_int i, phy, mode, freq, off, ee_mode, ant[2]; + u_int i, mode, freq, ee_mode, ant[2]; const AR5K_RATE_TABLE *rt; AR5K_TRACE; @@ -855,7 +880,6 @@ ee_mode = 0; freq = 0; mode = 0; - phy = 0; /* * Save some registers before a reset @@ -895,11 +919,8 @@ * 5210 only comes with RF5110 */ if (hal->ah_version != AR5K_AR5210) { - if (hal->ah_radio == AR5K_RF5111) - phy = AR5K_INI_PHY_5111; - else if (hal->ah_radio == AR5K_RF5112) - phy = AR5K_INI_PHY_5112; - else { + if ((hal->ah_radio != AR5K_RF5111) && + (hal->ah_radio != AR5K_RF5112)) { AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio); *status = AR5K_EINVAL; return (FALSE); @@ -916,6 +937,7 @@ freq = AR5K_INI_RFGAIN_2GHZ; ee_mode = AR5K_EEPROM_MODE_11B; break; + /*Is this ok on 5211 too ?*/ case CHANNEL_G: mode = AR5K_INI_VAL_11G; freq = AR5K_INI_RFGAIN_2GHZ; @@ -950,48 +972,32 @@ /* PHY access enable */ AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ); - /* - * Write initial RF registers on 5211 - * This is going out soon since it's handled by rf5111_rfregs... - */ - if (hal->ah_version == AR5K_AR5211) - ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode); } /* - * Write initial mode settings - * TODO:Do this in a common way + * Write initial mode-specific settings */ /*For 5212*/ if (hal->ah_version == AR5K_AR5212) { - for (i = 0; i < AR5K_ELEMENTS(ar5212_mode); i++) { - if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X) - off = AR5K_INI_PHY_511X; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5111 && - hal->ah_radio == AR5K_RF5111) - off = AR5K_INI_PHY_5111; - else if (ar5212_mode[i].mode_flags & AR5K_INI_FLAG_5112 && - hal->ah_radio == AR5K_RF5112) - off = AR5K_INI_PHY_5112; - else - continue; - - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5212_mode[i].mode_register, - ar5212_mode[i].mode_value[off][mode]); + ath5k_hw_ini_mode_registers(hal, AR5K_ELEMENTS(ar5212_ini_mode), + ar5212_ini_mode, mode); + if (hal->ah_radio == AR5K_RF5111) { + ath5k_hw_ini_mode_registers(hal, AR5K_ELEMENTS(ar5212_rf5111_ini_mode), + ar5212_rf5111_ini_mode, mode); + } else if (hal->ah_radio == AR5K_RF5112) { + ath5k_hw_ini_mode_registers(hal, AR5K_ELEMENTS(ar5212_rf5112_ini_mode), + ar5212_rf5112_ini_mode, mode); } } /*For 5211*/ if (hal->ah_version == AR5K_AR5211) { - for (i = 0; i < AR5K_ELEMENTS(ar5211_mode); i++) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, - ar5211_mode[i].mode_value[mode]); - } + ath5k_hw_ini_mode_registers(hal, AR5K_ELEMENTS(ar5211_ini_mode), + ar5211_ini_mode, mode); } + /* For 5210 mode settings check out ath5k_hw_reset_tx_queue */ /* - * Initial register dump common for all modes + * Write initial settings common for all modes */ if (hal->ah_version == AR5K_AR5212) { ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5212_ini), @@ -999,21 +1005,22 @@ if (hal->ah_radio == AR5K_RF5112) { AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE, AR5K_PHY_PAPD_PROBE_INI_5112); - ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(rf5112_bbgain_ini), - rf5112_bbgain_ini, change_channel); + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(rf5112_ini_bbgain), + rf5112_ini_bbgain, change_channel); } else if (hal->ah_radio == AR5K_RF5111) { - AR5K_REG_WRITE( AR5K_PHY_GAIN_2GHZ, AR5K_PHY_GAIN_2GHZ_INI_5111); + AR5K_REG_WRITE( AR5K_PHY_GAIN_2GHZ, + AR5K_PHY_GAIN_2GHZ_INI_5111); AR5K_REG_WRITE( AR5K_PHY_PAPD_PROBE, - AR5K_PHY_PAPD_PROBE_INI_5111 ); - ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(rf5111_bbgain_ini), - rf5111_bbgain_ini, change_channel); + AR5K_PHY_PAPD_PROBE_INI_5111 ); + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(rf5111_ini_bbgain), + rf5111_ini_bbgain, change_channel); } } else if (hal->ah_version == AR5K_AR5211) { ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5211_ini), ar5211_ini, change_channel); /* AR5211 only comes with 5111 */ - ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(rf5111_bbgain_ini), - rf5111_bbgain_ini, change_channel); + ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(rf5111_ini_bbgain), + rf5111_ini_bbgain, change_channel); } else if (hal->ah_version == AR5K_AR5210) { ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5210_ini), ar5210_ini, change_channel); @@ -1028,7 +1035,7 @@ * Write initial RF gain settings * This should work for both 5111/5112 */ - if (ath5k_hw_rfgain(hal, phy, freq) == FALSE) { + if (ath5k_hw_rfgain(hal, freq) == FALSE) { *status = AR5K_EIO; return (FALSE); } @@ -1142,8 +1149,8 @@ } } - /*Enable/disable 802.11b mode on 5111 - (enable 2111 frequency converter + CCK)*/ + /* Enable/disable 802.11b mode on 5111 + (enable 2111 frequency converter + CCK) */ if (hal->ah_radio == AR5K_RF5111) { if (channel->channel_flags & CHANNEL_B) AR5K_REG_ENABLE_BITS(AR5K_TXCFG, @@ -2140,8 +2147,11 @@ return (ETIMEDOUT); } +/* + * Translate binary channel representation in EEPROM to frequency + */ u_int16_t -ath5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) +ath5k_hw_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) { u_int16_t val; @@ -2169,7 +2179,7 @@ * Read antenna infos from eeprom */ int -ath5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) +ath5k_hw_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int32_t o = *offset; @@ -2225,10 +2235,10 @@ } /* - * Read supported modes from eeprom + * Read some mode-specific values from EEPROM for phy calibration */ int -ath5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) +ath5k_hw_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int32_t o = *offset; @@ -2312,7 +2322,7 @@ * Initialize eeprom & capabilities structs */ int -ath5k_eeprom_init(struct ath_hal *hal) +ath5k_hw_eeprom_init(struct ath_hal *hal) { struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; u_int32_t offset; @@ -2393,7 +2403,7 @@ offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + if ((ret = ath5k_hw_eeprom_read_ants(hal, &offset, mode)) != 0) return (ret); AR5K_EEPROM_READ(offset++, val); @@ -2410,7 +2420,7 @@ ee->ee_ob[mode][0] = (val >> 3) & 0x7; ee->ee_db[mode][0] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + if ((ret = ath5k_hw_eeprom_read_modes(hal, &offset, mode)) != 0) return (ret); if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { @@ -2424,7 +2434,7 @@ mode = AR5K_EEPROM_MODE_11B; offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + if ((ret = ath5k_hw_eeprom_read_ants(hal, &offset, mode)) != 0) return (ret); AR5K_EEPROM_READ(offset++, val); @@ -2432,19 +2442,19 @@ ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + if ((ret = ath5k_hw_eeprom_read_modes(hal, &offset, mode)) != 0) return (ret); if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_hw_eeprom_bin2freq(hal, val & 0xff, mode); ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + ath5k_hw_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_hw_eeprom_bin2freq(hal, val & 0xff, mode); } if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { @@ -2457,7 +2467,7 @@ mode = AR5K_EEPROM_MODE_11G; offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); - if ((ret = ath5k_eeprom_read_ants(hal, &offset, mode)) != 0) + if ((ret = ath5k_hw_eeprom_read_ants(hal, &offset, mode)) != 0) return (ret); AR5K_EEPROM_READ(offset++, val); @@ -2465,15 +2475,15 @@ ee->ee_ob[mode][1] = (val >> 4) & 0x7; ee->ee_db[mode][1] = val & 0x7; - if ((ret = ath5k_eeprom_read_modes(hal, &offset, mode)) != 0) + if ((ret = ath5k_hw_eeprom_read_modes(hal, &offset, mode)) != 0) return (ret); if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][0] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_hw_eeprom_bin2freq(hal, val & 0xff, mode); ee->ee_cal_pier[mode][1] = - ath5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); + ath5k_hw_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); AR5K_EEPROM_READ(offset++, val); ee->ee_turbo_max_power[mode] = val & 0x7f; @@ -2481,7 +2491,7 @@ AR5K_EEPROM_READ(offset++, val); ee->ee_cal_pier[mode][2] = - ath5k_eeprom_bin2freq(hal, val & 0xff, mode); + ath5k_hw_eeprom_bin2freq(hal, val & 0xff, mode); if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; @@ -2508,7 +2518,7 @@ * Read the MAC address from eeprom */ int -ath5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) +ath5k_hw_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) { u_int32_t total, offset; u_int16_t data; @@ -2544,7 +2554,7 @@ * Read/Write refulatory domain */ AR5K_BOOL -ath5k_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, +ath5k_hw_eeprom_regulation_domain(struct ath_hal *hal, AR5K_BOOL write, ieee80211_regdomain_t *regdomain) { u_int16_t ee_regdomain; @@ -2582,7 +2592,7 @@ ieee_regdomain = ath5k_regdomain_to_ieee(regdomain); - if (ath5k_eeprom_regulation_domain(hal, TRUE, + if (ath5k_hw_eeprom_regulation_domain(hal, TRUE, &ieee_regdomain) == TRUE) { *status = AR5K_OK; return (TRUE); @@ -3652,9 +3662,6 @@ { u_int32_t cw_min, cw_max, retry_lg, retry_sh; AR5K_TXQ_INFO *tq = &hal->ah_txq[queue]; - int i; - struct ath5k_ar5210_ini_mode ar5210_mode[] = - AR5K_AR5210_INI_MODE(hal->ah_aifs + tq->tqi_aifs); AR5K_TRACE; AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); @@ -3669,13 +3676,52 @@ if (tq->tqi_type != AR5K_TX_QUEUE_DATA) return (TRUE); - /* - * Write initial mode register settings - */ - for (i = 0; i < AR5K_ELEMENTS(ar5210_mode); i++) - AR5K_REG_WRITE((u_int32_t)ar5210_mode[i].mode_register, - hal->ah_turbo == TRUE ? - ar5210_mode[i].mode_turbo : ar5210_mode[i].mode_base); + /* Set Slot time */ + AR5K_REG_WRITE(AR5K_SLOT_TIME, + hal->ah_turbo == TRUE ? + AR5K_INIT_SLOT_TIME_TURBO : + AR5K_INIT_SLOT_TIME); + /* Set ACK_CTS timeout */ + AR5K_REG_WRITE(AR5K_SLOT_TIME, + hal->ah_turbo == TRUE ? + AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : + AR5K_INIT_ACK_CTS_TIMEOUT); + /* Set Transmit Latency */ + AR5K_REG_WRITE(AR5K_USEC_5210, + hal->ah_turbo == TRUE ? + AR5K_INIT_TRANSMIT_LATENCY_TURBO : + AR5K_INIT_TRANSMIT_LATENCY); + /* Set IFS0 */ + if (hal->ah_turbo == TRUE ){ + AR5K_REG_WRITE(AR5K_IFS0, + ((AR5K_INIT_SIFS_TURBO + \ + (hal->ah_aifs + tq->tqi_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \ + << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO); + } else { + AR5K_REG_WRITE(AR5K_IFS0, + ((AR5K_INIT_SIFS + \ + (hal->ah_aifs + tq->tqi_aifs) * AR5K_INIT_SLOT_TIME) \ + << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS); + } + /* Set IFS1 */ + AR5K_REG_WRITE(AR5K_IFS1, + hal->ah_turbo == TRUE ? + AR5K_INIT_PROTO_TIME_CNTRL_TURBO : + AR5K_INIT_PROTO_TIME_CNTRL); + /* Set PHY register 0x9844 (??) */ + AR5K_REG_WRITE(AR5K_PHY(17), + hal->ah_turbo == TRUE ? + ((AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x38) : + ((AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x1C) ); + /* Set Frame Control Register */ + AR5K_REG_WRITE(AR5K_PHY_FRAME_CTL_5210, + hal->ah_turbo == TRUE ? + (AR5K_PHY_FRAME_CTL_INI | \ + AR5K_PHY_TURBO_MODE | \ + AR5K_PHY_TURBO_SHORT | \ + 0x2020) : + (AR5K_PHY_FRAME_CTL_INI | 0x1020)); + } /* @@ -4983,7 +5029,7 @@ u_int16_t code; #endif - ath5k_eeprom_regulation_domain(hal, FALSE, &ieee_regdomain); + ath5k_hw_eeprom_regulation_domain(hal, FALSE, &ieee_regdomain); hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; #ifdef COUNTRYCODE @@ -5464,6 +5510,9 @@ return (FALSE); /*XXX: What do we return for 5210 ?*/ } +/* + * Used to modify RF Banks before writing them to AR5K_RF_BUFFER + */ u_int ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, u_int32_t first, u_int32_t col, AR5K_BOOL set) @@ -5686,7 +5735,7 @@ } /* - * Initialize RF5111 + * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111 */ AR5K_BOOL ath5k_hw_rf5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) @@ -5787,7 +5836,7 @@ } /* - * Initialize RF5112 + * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112 */ AR5K_BOOL ath5k_hw_rf5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode) @@ -5882,79 +5931,19 @@ return (TRUE); } -/* - * Initialize 5211 RF - * TODO: is this needed ? i mean 5211 has a 5111 RF - * doesn't ar5k_rfregs work ? - */ -void -ath5k_hw_ar5211_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int freq, - u_int ee_mode) -{ - struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; - struct ath5k_ar5211_ini_rf rf[AR5K_ELEMENTS(ar5211_rf)]; - u_int32_t ob, db, obdb, xpds, xpdp, x_gain; - u_int i; - - memcpy(rf, ar5211_rf, sizeof(rf)); - obdb = 0; - - if (freq == AR5K_INI_RFGAIN_2GHZ && - hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { - ob = ath5k_hw_bitswap(ee->ee_ob[ee_mode][0], 3); - db = ath5k_hw_bitswap(ee->ee_db[ee_mode][0], 3); - rf[25].rf_value[freq] = - ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); - rf[26].rf_value[freq] = - (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | - (rf[26].rf_value[freq] & ~0xf); - } - - if (freq == AR5K_INI_RFGAIN_5GHZ) { - /* For 11a and Turbo */ - obdb = channel->freq >= 5725 ? 3 : - (channel->freq >= 5500 ? 2 : - (channel->freq >= 5260 ? 1 : - (channel->freq > 4000 ? 0 : -1))); - } - - ob = ee->ee_ob[ee_mode][obdb]; - db = ee->ee_db[ee_mode][obdb]; - x_gain = ee->ee_x_gain[ee_mode]; - xpds = ee->ee_xpd[ee_mode]; - xpdp = !xpds; - - rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | - (((ath5k_hw_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); - rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | - ((ath5k_hw_bitswap(x_gain, 4) >> 1) & 0x7); - rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | - ((ath5k_hw_bitswap(ob, 3) << 7) & 0x80); - rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | - ((ath5k_hw_bitswap(ob, 3) >> 1) & 0x3); - rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | - ((ath5k_hw_bitswap(db, 3) << 2) & 0x1c); - rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | - ((xpds << 3) & 0x8); - - for (i = 0; i < AR5K_ELEMENTS(rf); i++) { - AR5K_REG_WAIT(i); - AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, - rf[i].rf_value[freq]); - } - - hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE; -} - AR5K_BOOL -ath5k_hw_rfgain(struct ath_hal *hal, u_int phy, u_int freq) +ath5k_hw_rfgain(struct ath_hal *hal, u_int freq) { int i; + struct ath5k_ini_rfgain *ath5k_rfg; - switch (phy) { - case AR5K_INI_PHY_5111: - case AR5K_INI_PHY_5112: + switch (hal->ah_radio) { + case AR5K_RF5111: + ath5k_rfg = (struct ath5k_ini_rfgain*) &rf5111_ini_rfgain; break; + case AR5K_RF5112: + ath5k_rfg = (struct ath5k_ini_rfgain*) &rf5112_ini_rfgain; + break; default: return (FALSE); } @@ -5970,7 +5959,7 @@ for (i = 0; i < AR5K_ELEMENTS(ath5k_rfg); i++) { AR5K_REG_WAIT(i); AR5K_REG_WRITE((u_int32_t)ath5k_rfg[i].rfg_register, - ath5k_rfg[i].rfg_value[phy][freq]); + ath5k_rfg[i].rfg_value[freq]); } return (TRUE); Index: ath5kreg.h =================================================================== --- ath5kreg.h (revision 2539) +++ ath5kreg.h (revision 2595) @@ -920,63 +920,66 @@ #define AR5K_EEPROM_BASE 0x6000 /* - * Common ar5xxx EEPROM data offset (set these on AR5K_EEPROM_BASE) + * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) */ -#define AR5K_EEPROM_MAGIC 0x003d -#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 +#define AR5K_EEPROM_MAGIC 0x003d /* Offset for EEPROM Magic number */ +#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM*/ #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ -#define AR5K_EEPROM_PROTECT 0x003f -#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 -#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 -#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 +#define AR5K_EEPROM_PROTECT 0x003f /* Offset for EEPROM protect status */ +#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */ +#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */ +#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */ #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 -#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 +#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */ #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 -#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 +#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (Regulatory domain) */ #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 -#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 +#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */ #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 -#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 +#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */ #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 -#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 +#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */ #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 -#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 +#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */ #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 -#define AR5K_EEPROM_REG_DOMAIN 0x00bf -#define AR5K_EEPROM_INFO_BASE 0x00c0 + +#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* Offset for EEPROM regulatory domain */ +#define AR5K_EEPROM_INFO_BASE 0x00c0 /* Offset for EEPROM header */ #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) #define AR5K_EEPROM_INFO_CKSUM 0xffff #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) -#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) -#define AR5K_EEPROM_VERSION_3_0 0x3000 -#define AR5K_EEPROM_VERSION_3_1 0x3001 -#define AR5K_EEPROM_VERSION_3_2 0x3002 -#define AR5K_EEPROM_VERSION_3_3 0x3003 -#define AR5K_EEPROM_VERSION_3_4 0x3004 -#define AR5K_EEPROM_VERSION_4_0 0x4000 -#define AR5K_EEPROM_VERSION_4_1 0x4001 -#define AR5K_EEPROM_VERSION_4_2 0x4002 +#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* Offset for EEPROM Version */ +#define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ +#define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ +#define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ +#define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ +#define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain ee_cck_ofdm_power_delta (eeprom_read_modes) */ +#define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc*, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */ +#define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */ +#define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */ #define AR5K_EEPROM_VERSION_4_3 0x4003 -#define AR5K_EEPROM_VERSION_4_6 0x4006 -#define AR5K_EEPROM_VERSION_4_7 0x3007 +#define AR5K_EEPROM_VERSION_4_4 0x4004 +#define AR5K_EEPROM_VERSION_4_5 0x4005 +#define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ +#define AR5K_EEPROM_VERSION_4_7 0x4007 #define AR5K_EEPROM_MODE_11A 0 #define AR5K_EEPROM_MODE_11B 1 #define AR5K_EEPROM_MODE_11G 2 -#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) -#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) -#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) -#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) -#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) -#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) +#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */ +#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) /* Device has a support */ +#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) /* Device has b support */ +#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) /* Device has g support */ +#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ +#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) -#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) -#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) +#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz (?) */ +#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 @@ -987,16 +990,16 @@ #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) -#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) -#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) -#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) +#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) /* Offset for Antenna Gain */ +#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) /* 5Ghz Antenna Gain */ +#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) /* 2Ghz Antenna Gain */ -#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) -#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) -#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) -#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) +#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) /* Offset for 11a calibration settings */ +#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) /* Offset for 11b calibration settings */ +#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) /* Offset for 11g calibration settings */ +#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Offset for Conformance test limits */ -/* Since 3.1 */ +/* [3.1 - 3.3] */ #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed @@ -1772,7 +1775,8 @@ * Channel set on 5111 & * Used to read radio revision */ -#define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* Bank 0,1,2,6 on 5111 & +#define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 + * Bank 0,1,2,6 on 5111 & * Bank 1 on 5112 & * Used during activation on 5111 */ @@ -1847,13 +1851,19 @@ /*---[5111+]---*/ #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 -/*---[5110]---*/ +/*---[5110/5111]---*/ #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 +#define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ + AR5K_PHY_FRAME_CTL_TXURN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ + AR5K_PHY_FRAME_CTL_PARITY_ERR | \ + AR5K_PHY_FRAME_CTL_TIMING_ERR /* * PHY radar detection register [5111+] Index: ath5k_hw.h =================================================================== --- ath5k_hw.h (revision 2539) +++ ath5k_hw.h (revision 2595) @@ -151,22 +151,25 @@ /* Struct to hold EEPROM calibration data */ struct ath5k_eeprom_info { - u_int16_t ee_magic; - u_int16_t ee_protect; - u_int16_t ee_regdomain; - u_int16_t ee_version; - u_int16_t ee_header; - u_int16_t ee_ant_gain; + u_int16_t ee_magic; /* Magic Number */ + u_int16_t ee_protect; /* Protection bits (ath5kreg.h) */ + u_int16_t ee_regdomain; /* Regulatory Domain */ + u_int16_t ee_version; /* EEPROM Revision */ + u_int16_t ee_header; /* EEPROM Header (ath5kreg.h,get_capabilities) */ + u_int16_t ee_ant_gain; /* Antenna Gain (ath5kreg.h) */ u_int16_t ee_misc0; u_int16_t ee_misc1; - u_int16_t ee_cck_ofdm_gain_delta; - u_int16_t ee_cck_ofdm_power_delta; + u_int16_t ee_cck_ofdm_gain_delta; /* CCK to OFDM gain delta */ + u_int16_t ee_cck_ofdm_power_delta;/* CCK to OFDM power delta */ u_int16_t ee_scaled_cck_delta; + + /* Used for tx thermal adjustment (eeprom_init, rfregs) */ u_int16_t ee_tx_clip; u_int16_t ee_pwd_84; u_int16_t ee_pwd_90; u_int16_t ee_gain_select; + /* RF Calibration settings (reset, rfregs) */ u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES]; u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES]; u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES]; @@ -186,13 +189,15 @@ u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES]; u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES]; u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; - u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; - u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; - u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; + u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; /* Unused */ + u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; /* Unused */ + u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; /* Empty ! */ + /* Conformance test limits (Unused) */ u_int16_t ee_ctls; u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS]; + /* Noise Floor Calibration settings */ int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; @@ -573,8 +578,10 @@ #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) + + /* - * Initial register values + * INITIAL REGISTER VALUES */ /* @@ -632,11 +639,18 @@ (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ ) + + /* * Non-common initial register values which have to be loaded into the * card at boot time and after each reset. */ + +/* + * RF REGISTERS + */ + /* Register dumps are done per operation mode */ #define AR5K_INI_VAL_11A 0 #define AR5K_INI_VAL_11A_TURBO 1 @@ -646,14 +660,11 @@ #define AR5K_INI_VAL_XR 0 #define AR5K_INI_VAL_MAX 5 -#define AR5K_INI_PHY_5111 0 -#define AR5K_INI_PHY_5112 1 -#define AR5K_INI_PHY_511X 1 - #define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS #define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS -/* Struct to hold initial RF register values */ + +/* Struct to hold initial RF register values (RF Banks)*/ struct ath5k_ini_rf { u_int8_t rf_bank; /* check out ath5kreg.h */ u_int16_t rf_register; /* register address */ @@ -987,153 +998,166 @@ } /* - * Mode-specific RF Gain registers + * Mode-specific RF Gain table (64bytes) for RF5111/5112 + * (RF5110 only comes with AR5210 and only supports a/turbo a + * mode so initial RF Gain values are included in AR5K_AR5210_INI) */ struct ath5k_ini_rfgain { u_int16_t rfg_register; /* RF Gain register address */ - u_int32_t rfg_value[2][2]; /* [phy (see above)][freq (below)] */ + u_int32_t rfg_value[2]; /* Register value [freq (see below)] */ #define AR5K_INI_RFGAIN_5GHZ 0 #define AR5K_INI_RFGAIN_2GHZ 1 }; -#define AR5K_INI_RFGAIN { \ - { 0x9a00, { \ - /* 5111 5Ghz 5111 2Ghz 5112 5Ghz 5112 2Ghz */ \ - { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \ - { 0x9a04, { \ - { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \ - { 0x9a08, { \ - { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \ - { 0x9a0c, { \ - { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \ - { 0x9a10, { \ - { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \ - { 0x9a14, { \ - { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \ - { 0x9a18, { \ - { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \ - { 0x9a1c, { \ - { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \ - { 0x9a20, { \ - { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \ - { 0x9a24, { \ - { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \ - { 0x9a28, { \ - { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \ - { 0x9a2c, { \ - { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \ - { 0x9a30, { \ - { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \ - { 0x9a34, { \ - { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \ - { 0x9a38, { \ - { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \ - { 0x9a3c, { \ - { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \ - { 0x9a40, { \ - { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \ - { 0x9a44, { \ - { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \ - { 0x9a48, { \ - { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \ - { 0x9a4c, { \ - { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \ - { 0x9a50, { \ - { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \ - { 0x9a54, { \ - { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \ - { 0x9a58, { \ - { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \ - { 0x9a5c, { \ - { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \ - { 0x9a60, { \ - { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \ - { 0x9a64, { \ - { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \ - { 0x9a68, { \ - { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \ - { 0x9a6c, { \ - { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \ - { 0x9a70, { \ - { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \ - { 0x9a74, { \ - { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \ - { 0x9a78, { \ - { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \ - { 0x9a7c, { \ - { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \ - { 0x9a80, { \ - { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \ - { 0x9a84, { \ - { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \ - { 0x9a88, { \ - { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \ - { 0x9a8c, { \ - { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \ - { 0x9a90, { \ - { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \ - { 0x9a94, { \ - { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \ - { 0x9a98, { \ - { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \ - { 0x9a9c, { \ - { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \ - { 0x9aa0, { \ - { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \ - { 0x9aa4, { \ - { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \ - { 0x9aa8, { \ - { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \ - { 0x9aac, { \ - { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \ - { 0x9ab0, { \ - { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \ - { 0x9ab4, { \ - { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \ - { 0x9ab8, { \ - { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \ - { 0x9abc, { \ - { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \ - { 0x9ac0, { \ - { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \ - { 0x9ac4, { \ - { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \ - { 0x9ac8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \ - { 0x9acc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \ - { 0x9ad0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \ - { 0x9ad4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \ - { 0x9ad8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9adc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9ae8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9aec, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af0, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af4, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9af8, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ - { 0x9afc, { \ - { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \ +/* Initial RF Gain settings for RF5111 */ +#define AR5K_RF5111_INI_RFGAIN { \ + /* 5Ghz 2Ghz */ \ + { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } }, \ + { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } }, \ + { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } }, \ + { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } }, \ + { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } }, \ + { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } }, \ + { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } }, \ + { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } }, \ + { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } }, \ + { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } }, \ + { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } }, \ + { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } }, \ + { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } }, \ + { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } }, \ + { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } }, \ + { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } }, \ + { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } }, \ + { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } }, \ + { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } }, \ + { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } }, \ + { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } }, \ + { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } }, \ + { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } }, \ + { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } }, \ + { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } }, \ + { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } }, \ + { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } }, \ + { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } }, \ + { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } }, \ + { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } }, \ + { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } }, \ + { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } }, \ + { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } }, \ + { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } }, \ + { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } }, \ + { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } }, \ + { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } }, \ + { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } }, \ + { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } }, \ + { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } }, \ + { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } }, \ + { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } }, \ + { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } }, \ + { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } }, \ + { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } }, \ + { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } }, \ + { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } }, \ + { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } }, \ + { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } }, \ + { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } }, \ + { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } }, \ + { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } }, \ } +/* Initial RF Gain settings for RF5112 */ +#define AR5K_RF5112_INI_RFGAIN { \ + /* 5Ghz 2Ghz */ \ + { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } }, \ + { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } }, \ + { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } }, \ + { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } }, \ + { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } }, \ + { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } }, \ + { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } }, \ + { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } }, \ + { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } }, \ + { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } }, \ + { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } }, \ + { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } }, \ + { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } }, \ + { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } }, \ + { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } }, \ + { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } }, \ + { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } }, \ + { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } }, \ + { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } }, \ + { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } }, \ + { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } }, \ + { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } }, \ + { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } }, \ + { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } }, \ + { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } }, \ + { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } }, \ + { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } }, \ + { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } }, \ + { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } }, \ + { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } }, \ + { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } }, \ + { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } }, \ + { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } }, \ + { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } }, \ + { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } }, \ + { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } }, \ + { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } }, \ + { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } }, \ + { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } }, \ + { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } }, \ + { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } }, \ + { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } }, \ + { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } }, \ + { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } }, \ + { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } }, \ + { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } }, \ + { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } }, \ + { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } }, \ + { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } }, \ + { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } }, \ + { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } }, \ + { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } }, \ + { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } }, \ + { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } }, \ + { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } }, \ + { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } }, \ +} + + /* - * Mode-independet initial register writes + * MAC/PHY REGISTERS */ +/* + * Mode-independed initial register writes + */ + struct ath5k_ini { u_int16_t ini_register; u_int32_t ini_value; @@ -1281,7 +1305,7 @@ { AR5K_BB_GAIN(61), 0x0000002f }, \ { AR5K_BB_GAIN(62), 0x0000002f }, \ { AR5K_BB_GAIN(63), 0x0000002f }, \ - /* RF gain table (64btes) */ \ + /* 5110 RF gain table (64btes) */ \ { AR5K_RF_GAIN(0), 0x0000001d }, \ { AR5K_RF_GAIN(1), 0x0000005d }, \ { AR5K_RF_GAIN(2), 0x0000009d }, \ @@ -1639,6 +1663,7 @@ { 0x87d4, 0x17161514 }, \ { 0x87d8, 0x1b1a1918 }, \ { 0x87dc, 0x1f1e1d1c }, \ + /* loop ? */ \ { 0x87e0, 0x03020100 }, \ { 0x87e4, 0x07060504 }, \ { 0x87e8, 0x0b0a0908 }, \ @@ -1729,8 +1754,14 @@ { AR5K_PHY_CCKTXCTL, 0x00000000 }, \ } -/* RF5111 Initial BB Gain settings */ -#define AR5K_RF5111_BBGAIN_INI { \ +/* + * Initial BaseBand Gain settings for RF5111/5112 + * (only AR5210 comes with RF5110 so initial + * BB Gain settings are included in AR5K_AR5210_INI) + */ + +/* RF5111 Initial BaseBand Gain settings */ +#define AR5K_RF5111_INI_BBGAIN { \ { AR5K_BB_GAIN(0), 0x00000000 }, \ { AR5K_BB_GAIN(1), 0x00000020 }, \ { AR5K_BB_GAIN(2), 0x00000010 }, \ @@ -1797,8 +1828,8 @@ { AR5K_BB_GAIN(63), 0x00000016 }, \ } -/* RF 5112 Initial BB Gain settings */ -#define AR5K_RF5112_BBGAIN_INI { \ +/* RF 5112 Initial BaseBand Gain settings */ +#define AR5K_RF5112_INI_BBGAIN { \ { AR5K_BB_GAIN(0), 0x00000000 }, \ { AR5K_BB_GAIN(1), 0x00000001 }, \ { AR5K_BB_GAIN(2), 0x00000002 }, \ @@ -1865,331 +1896,232 @@ { AR5K_BB_GAIN(63), 0x0000001a }, \ } -struct ath5k_ar5210_ini_mode{ - u_int16_t mode_register; - u_int32_t mode_base, mode_turbo; -}; -#define AR5K_AR5210_INI_MODE(_aifs) { \ - { AR5K_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME_TURBO }, \ - { AR5K_SLOT_TIME, \ - AR5K_INIT_ACK_CTS_TIMEOUT, \ - AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \ - { AR5K_USEC_5210, \ - AR5K_INIT_TRANSMIT_LATENCY, \ - AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \ - { AR5K_IFS0, \ - ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ - << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS, \ - ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \ - << AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \ - { AR5K_IFS1, \ - AR5K_INIT_PROTO_TIME_CNTRL, \ - AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ - { AR5K_PHY(17), \ - (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x1C, \ - (AR5K_REG_READ(AR5K_PHY(17)) & ~0x7F) | 0x38 }, \ - { AR5K_PHY_FRAME_CTL_5210, \ - AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ - AR5K_PHY_FRAME_CTL_TXURN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ - AR5K_PHY_FRAME_CTL_PARITY_ERR | \ - AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x1020, \ - AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ - AR5K_PHY_FRAME_CTL_TXURN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ - AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ - AR5K_PHY_FRAME_CTL_PARITY_ERR | \ - /*PHY_TURBO is PHY_FRAME_CTL on 5210*/ \ - AR5K_PHY_TURBO_MODE | \ - AR5K_PHY_TURBO_SHORT | \ - AR5K_PHY_FRAME_CTL_TIMING_ERR | 0x2020 }, \ -} +/* + * Mode specific initial register values + */ -struct ath5k_ar5211_ini_mode { +struct ath5k_ini_mode { u_int16_t mode_register; - u_int32_t mode_value[4]; + u_int32_t mode_value[5]; }; -#define AR5K_AR5211_INI_MODE { \ - { 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \ - { 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \ - { 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, \ - { 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, \ - { 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, \ - { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, \ - { 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, \ - { 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, \ - { 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, \ - { 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, \ - { 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, \ - { 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, \ - { 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ - { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, \ - { 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, \ - { 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, \ - { 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \ - { 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, \ - { 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, \ - { 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, \ - { 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ - { 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, \ - { 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, \ - { 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, \ - { 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, \ - { 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, \ +/* Initial mode-specific settings for AR5211 + * XXX: how about gTurbo ? RF5111 supports it, how about AR5211 ? */ +#define AR5K_AR5211_INI_MODE { \ + { AR5K_TXCFG, \ + /* mode a/XR mode aTurbo mode b mode g(OFDM?) mode gTurbo (N/A) */ \ + { 0x00000017, 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(0), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(1), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(2), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(3), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(4), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(5), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(6), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(7), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(8), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(9), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_DCU_GBL_IFS_SLOT, \ + { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168, 0x00000168 } }, \ + { AR5K_DCU_GBL_IFS_SIFS, \ + { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230, 0x00000230 } }, \ + { AR5K_DCU_GBL_IFS_EIFS, \ + { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98, 0x00000d98 } }, \ + { AR5K_DCU_GBL_IFS_MISC, \ + { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0, 0x0000a0e0 } }, \ + { AR5K_TIME_OUT, \ + { 0x04000400, 0x08000800, 0x20003000, 0x04000400, 0x04000400 } }, \ + { AR5K_USEC_5211, \ + { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7, 0x0e8d8fa7 } }, \ + { AR5K_PHY_TURBO, \ + { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 } }, \ + { 0x9820, \ + { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, \ + { 0x9824, \ + { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } }, \ + { 0x9828, \ + { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001, 0x0a020001 } }, \ + { 0x9834, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ + { 0x9838, \ + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, \ + { 0x9844, \ + { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c, 0x1372169c } }, \ + { 0x9848, \ + { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69, 0x0018ba69 } }, \ + { 0x9850, \ + { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \ + { AR5K_PHY_SIG, \ + { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e, 0x7e800d2e } }, \ + { AR5K_PHY_AGCCOARSE, \ + { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e, 0x31375d5e } }, \ + { AR5K_PHY_AGCCTL, \ + { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10, 0x0000bd10 } }, \ + { AR5K_PHY_NF, \ + { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ + { AR5K_PHY_RX_DELAY, \ + { 0x00002710, 0x00002710, 0x0000157c, 0x00002710, 0x00002710 } }, \ + { 0x9918, \ + { 0x00000190, 0x00000190, 0x00000084, 0x00000190, 0x00000190 } }, \ + { AR5K_PHY_FRAME_CTL_5211, \ + { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020, 0x6fe01020 } }, \ + { AR5K_PHY_PCDAC_TXPOWER(0), \ + { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff, 0x05ff19ff } }, \ + { AR5K_RF_BUFFER_CONTROL_4, \ + { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000010 } }, \ } -struct ath5k_ar5212_ini_mode { - u_int16_t mode_register; - u_int8_t mode_flags; - u_int32_t mode_value[2][5]; -}; +/* Initial mode-specific settings for AR5212 */ +#define AR5K_AR5212_INI_MODE { \ + { AR5K_TXCFG, \ + /* mode a/XR mode aTurbo mode b mode g (DYN) mode gTurbo */ \ + { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(0), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(1), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(2), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(3), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(4), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(5), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(6), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(7), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(8), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_QUEUE_DFS_LOCAL_IFS(9), \ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, \ + { AR5K_DCU_GBL_IFS_SIFS, \ + { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } }, \ + { AR5K_DCU_GBL_IFS_SLOT, \ + { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } }, \ + { AR5K_DCU_GBL_IFS_EIFS, \ + { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } }, \ + { AR5K_DCU_GBL_IFS_MISC, \ + { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } }, \ + { AR5K_TIME_OUT, \ + { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } }, \ +} -#define AR5K_INI_FLAG_511X 0x00 -#define AR5K_INI_FLAG_5111 0x01 -#define AR5K_INI_FLAG_5112 0x02 -#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112) - -#define AR5K_AR5212_INI_MODE { \ - { 0x0030, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 } \ - } }, \ - { 0x1040, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1044, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1048, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x104c, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1050, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1054, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1058, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x105c, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1060, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1064, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } \ - } }, \ - { 0x1030, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } \ - } }, \ - { 0x1070, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } \ - } }, \ - { 0x10b0, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } \ - } }, \ - { 0x10f0, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } \ - } }, \ - { 0x8014, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } \ - } }, \ - { 0x9804, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } \ - } }, \ - { 0x9820, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } \ - } }, \ - { 0x9834, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ - } }, \ - { 0x9838, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } \ - } }, \ - { 0x9844, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 } \ - } }, \ - { 0x9850, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } \ - } }, \ - { 0x9858, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } \ - } }, \ - { 0x9860, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 } \ - } }, \ - { 0x9864, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } \ - } }, \ - { 0x9868, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } \ - } }, \ - { 0x9918, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } \ - } }, \ - { 0x9924, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } \ - } }, \ - { 0xa180, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff } \ - } }, \ - { 0xa230, AR5K_INI_FLAG_511X, { \ - { 0, }, \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } \ - } }, \ - { 0x801c, AR5K_INI_FLAG_BOTH, { \ - { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x128d8fab, 0x09880fcf }, \ - { 0x128d93a7, 0x098813cf, 0x04e01395, 0x128d93ab, 0x098813cf } \ - } }, \ - { 0x9824, AR5K_INI_FLAG_BOTH, { \ - { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e }, \ - { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } \ - } }, \ - { 0x9828, AR5K_INI_FLAG_BOTH, { \ - { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 }, \ - { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } \ - } }, \ - { 0x9848, AR5K_INI_FLAG_BOTH, { \ - { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 }, \ - { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } \ - } }, \ - { 0x985c, AR5K_INI_FLAG_BOTH, { \ - { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e }, \ - { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } \ - } }, \ - { 0x986c, AR5K_INI_FLAG_BOTH, { \ - { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 }, \ - { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } \ - } }, \ - { 0x9914, AR5K_INI_FLAG_BOTH, { \ - { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 }, \ - { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } \ - } }, \ - { 0x9944, AR5K_INI_FLAG_BOTH, { \ - { 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 }, \ - { 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 } \ - } }, \ - { 0xa204, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } \ - } }, \ - { 0xa208, AR5K_INI_FLAG_BOTH, { \ - { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 }, \ - { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } \ - } }, \ - { 0xa20c, AR5K_INI_FLAG_5112, { \ - { 0, }, \ - { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } \ - } }, \ +/* Initial mode-specific settings for AR5212 + RF5111 */ +#define AR5K_AR5212_RF5111_INI_MODE { \ + { AR5K_USEC_5211, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ + { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x128d8fab, 0x09880fcf } }, \ + { AR5K_PHY_TURBO, \ + { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } }, \ + { 0x9820, \ + { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, \ + { 0x9824, \ + { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } }, \ + { 0x9828, \ + { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } }, \ + { 0x9834, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ + { 0x9838, \ + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, \ + { 0x9844, \ + { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 } }, \ + { 0x9848, \ + { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } }, \ + { 0x9850, \ + { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, \ + { AR5K_PHY_SIG, \ + { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } }, \ + { AR5K_PHY_AGCCOARSE, \ + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } }, \ + { AR5K_PHY_AGCCTL, \ + { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 } }, \ + { AR5K_PHY_NF, \ + { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ + { AR5K_PHY_ADCSAT, \ + { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } }, \ + { 0x986c, \ + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } }, \ + { AR5K_PHY_RX_DELAY, \ + { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } }, \ + { 0x9918, \ + { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } }, \ + { 0x9924, \ + { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } }, \ + { AR5K_PHY_FRAME_CTL_5211, \ + { 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 } }, \ + { AR5K_PHY_PCDAC_TXPOWER(0), \ + { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff } }, \ + { 0xa230, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } }, \ + { 0xa208, \ + { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, \ } -struct ath5k_ar5211_ini_rf { - u_int16_t rf_register; - u_int32_t rf_value[2]; -}; - -#define AR5K_AR5211_INI_RF { \ -/* Static -> moved on ar5211_ini */ \ - { 0x0000a204, { 0x00000000, 0x00000000 } }, \ - { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \ - { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \ - { 0x0000a210, { 0x0199a003, 0x0199a003 } }, \ - { 0x0000a214, { 0x044cd610, 0x044cd610 } }, \ - { 0x0000a218, { 0x13800040, 0x13800040 } }, \ - { 0x0000a21c, { 0x1be00060, 0x1be00060 } }, \ - { 0x0000a220, { 0x0c53800a, 0x0c53800a } }, \ - { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \ - { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \ - { 0x0000a22c, { 0x00000020, 0x00000020 } }, \ -/* Bank 6 ? */ \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00380000, 0x00380000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \ - { 0x000098d4, { 0x00000000, 0x00000004 } }, \ -/* Bank 7 ? */ \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x10000000, 0x10000000 } }, \ - { 0x0000989c, { 0x04000000, 0x04000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x00000000 } }, \ - { 0x0000989c, { 0x00000000, 0x0a000000 } }, \ - { 0x0000989c, { 0x00380080, 0x02380080 } }, \ - { 0x0000989c, { 0x00020006, 0x00000006 } }, \ - { 0x0000989c, { 0x00000092, 0x00000092 } }, \ - { 0x0000989c, { 0x000000a0, 0x000000a0 } }, \ - { 0x0000989c, { 0x00040007, 0x00040007 } }, \ - { 0x000098d4, { 0x0000001a, 0x0000001a } }, \ - { 0x0000989c, { 0x00000048, 0x00000048 } }, \ - { 0x0000989c, { 0x00000010, 0x00000010 } }, \ - { 0x0000989c, { 0x00000008, 0x00000008 } }, \ - { 0x0000989c, { 0x0000000f, 0x0000000f } }, \ - { 0x0000989c, { 0x000000f2, 0x00000062 } }, \ - { 0x0000989c, { 0x0000904f, 0x0000904c } }, \ - { 0x0000989c, { 0x0000125a, 0x0000129a } }, \ - { 0x000098cc, { 0x0000000e, 0x0000000f } }, \ +/* Initial mode-specific settings for AR5212 + RF5112 */ +#define AR5K_AR5212_RF5112_INI_MODE { \ + { AR5K_USEC_5211, \ + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ \ + { 0x128d93a7, 0x098813cf, 0x04e01395, 0x128d93ab, 0x098813cf } }, \ + { AR5K_PHY_TURBO, \ + { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } }, \ + { 0x9820, \ + { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, \ + { 0x9824, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ + { 0x9828, \ + { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, \ + { 0x9834, \ + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \ + { 0x9838, \ + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, \ + { 0x9844, \ + { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 } }, \ + { 0x9848, \ + { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } }, \ + { 0x9850, \ + { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, \ + { AR5K_PHY_SIG, \ + { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } }, \ + { AR5K_PHY_AGCCOARSE, \ + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } }, \ + { AR5K_PHY_AGCCTL, \ + { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 } }, \ + { AR5K_PHY_NF, \ + { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \ + { AR5K_PHY_ADCSAT, \ + { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } }, \ + { 0x986c, \ + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, \ + { AR5K_PHY_RX_DELAY, \ + { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, \ + { 0x9918, \ + { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } }, \ + { 0x9924, \ + { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } }, \ + { AR5K_PHY_FRAME_CTL_5211, \ + { 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 } }, \ + { AR5K_PHY_PCDAC_TXPOWER(0), \ + { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff } }, \ + { 0xa230, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } }, \ + { AR5K_PHY_CCKTXCTL, \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ + { 0xa208, \ + { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, \ + { AR5K_PHY_GAIN_2GHZ, \ + { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } }, \ } + Index: ath5k.h =================================================================== --- ath5k.h (revision 2539) +++ ath5k.h (revision 2595) @@ -1193,13 +1193,13 @@ void ath5k_rt_copy(AR5K_RATE_TABLE *, const AR5K_RATE_TABLE *); AR5K_BOOL ath5k_register_timeout(struct ath_hal *, u_int32_t, u_int32_t, u_int32_t, AR5K_BOOL); -int ath5k_eeprom_init(struct ath_hal *); -int ath5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); -AR5K_BOOL ath5k_eeprom_regulation_domain(struct ath_hal *, AR5K_BOOL, +int ath5k_hw_eeprom_init(struct ath_hal *); +int ath5k_hw_eeprom_read_mac(struct ath_hal *, u_int8_t *); +AR5K_BOOL ath5k_hw_eeprom_regulation_domain(struct ath_hal *, AR5K_BOOL, ieee80211_regdomain_t *); -int ath5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); -int ath5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); -u_int16_t ath5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); +int ath5k_hw_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); +int ath5k_hw_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); +u_int16_t ath5k_hw_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); AR5K_BOOL ath5k_hw_channel(struct ath_hal *, AR5K_CHANNEL *); AR5K_BOOL ath5k_hw_rf5110_channel(struct ath_hal *, AR5K_CHANNEL *); @@ -1222,7 +1222,7 @@ u_int32_t ath5k_hw_rfregs_gainf_corr(struct ath_hal *); AR5K_BOOL ath5k_hw_rfregs_gain_readback(struct ath_hal *); int32_t ath5k_hw_rfregs_gain_adjust(struct ath_hal *); -AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int, u_int); +AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int); void ath5k_txpower_table(struct ath_hal *, AR5K_CHANNEL *, int16_t); /*added*/