From 7d60b49d2d677fa625546148bfddbc969ac78fef Mon Sep 17 00:00:00 2001 From: Sujith Date: Fri, 6 Feb 2009 14:11:47 +0530 Subject: [PATCH] ath9k: Header file cleanup Split the core header files into manageable pieces. Signed-off-by: Sujith --- drivers/net/wireless/ath9k/ahb.c | 4 +- drivers/net/wireless/ath9k/ani.c | 5 +- drivers/net/wireless/ath9k/ani.h | 111 +++ drivers/net/wireless/ath9k/ath9k.h | 1653 ++++++++++++++--------------------- drivers/net/wireless/ath9k/beacon.c | 2 +- drivers/net/wireless/ath9k/calib.c | 5 +- drivers/net/wireless/ath9k/calib.h | 124 +++ drivers/net/wireless/ath9k/core.h | 821 ----------------- drivers/net/wireless/ath9k/debug.c | 4 +- drivers/net/wireless/ath9k/debug.h | 153 ++++ drivers/net/wireless/ath9k/eeprom.c | 5 +- drivers/net/wireless/ath9k/eeprom.h | 484 ++++++++++ drivers/net/wireless/ath9k/hw.c | 5 +- drivers/net/wireless/ath9k/hw.h | 1377 +++++++++++------------------- drivers/net/wireless/ath9k/mac.c | 5 +- drivers/net/wireless/ath9k/mac.h | 676 ++++++++++++++ drivers/net/wireless/ath9k/main.c | 4 +- drivers/net/wireless/ath9k/pci.c | 4 +- drivers/net/wireless/ath9k/phy.c | 5 +- drivers/net/wireless/ath9k/rc.c | 2 +- drivers/net/wireless/ath9k/rc.h | 17 +- drivers/net/wireless/ath9k/recv.c | 2 +- drivers/net/wireless/ath9k/reg.h | 1 + drivers/net/wireless/ath9k/regd.c | 4 +- drivers/net/wireless/ath9k/regd.h | 12 +- drivers/net/wireless/ath9k/xmit.c | 2 +- 26 files changed, 2733 insertions(+), 2754 deletions(-) create mode 100644 drivers/net/wireless/ath9k/ani.h create mode 100644 drivers/net/wireless/ath9k/calib.h delete mode 100644 drivers/net/wireless/ath9k/core.h create mode 100644 drivers/net/wireless/ath9k/debug.h create mode 100644 drivers/net/wireless/ath9k/eeprom.h create mode 100644 drivers/net/wireless/ath9k/mac.h diff --git a/drivers/net/wireless/ath9k/ahb.c b/drivers/net/wireless/ath9k/ahb.c index 7f2c3a0..361ace1 100644 --- a/drivers/net/wireless/ath9k/ahb.c +++ b/drivers/net/wireless/ath9k/ahb.c @@ -19,9 +19,7 @@ #include #include #include -#include "core.h" -#include "reg.h" -#include "hw.h" +#include "ath9k.h" /* return bus cachesize in 4B word units */ static void ath_ahb_read_cachesize(struct ath_softc *sc, int *csz) diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index 42197ff..d75bd6e 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c @@ -14,10 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" -#include "hw.h" -#include "reg.h" -#include "phy.h" +#include "ath9k.h" static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, struct ath9k_channel *chan) diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h new file mode 100644 index 0000000..cfb7fbc --- /dev/null +++ b/drivers/net/wireless/ath9k/ani.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef ANI_H +#define ANI_H + +#define HAL_PROCESS_ANI 0x00000001 +#define ATH9K_RSSI_EP_MULTIPLIER (1<<7) + +#define DO_ANI(ah) ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) + +#define HAL_EP_RND(x, mul) \ + ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) +#define BEACON_RSSI(ahp) \ + HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ + ATH9K_RSSI_EP_MULTIPLIER) + +#define ATH9K_ANI_OFDM_TRIG_HIGH 500 +#define ATH9K_ANI_OFDM_TRIG_LOW 200 +#define ATH9K_ANI_CCK_TRIG_HIGH 200 +#define ATH9K_ANI_CCK_TRIG_LOW 100 +#define ATH9K_ANI_NOISE_IMMUNE_LVL 4 +#define ATH9K_ANI_USE_OFDM_WEAK_SIG true +#define ATH9K_ANI_CCK_WEAK_SIG_THR false +#define ATH9K_ANI_SPUR_IMMUNE_LVL 7 +#define ATH9K_ANI_FIRSTEP_LVL 0 +#define ATH9K_ANI_RSSI_THR_HIGH 40 +#define ATH9K_ANI_RSSI_THR_LOW 7 +#define ATH9K_ANI_PERIOD 100 + +#define HAL_NOISE_IMMUNE_MAX 4 +#define HAL_SPUR_IMMUNE_MAX 7 +#define HAL_FIRST_STEP_MAX 2 + +enum ath9k_ani_cmd { + ATH9K_ANI_PRESENT = 0x1, + ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, + ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, + ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, + ATH9K_ANI_FIRSTEP_LEVEL = 0x10, + ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, + ATH9K_ANI_MODE = 0x40, + ATH9K_ANI_PHYERR_RESET = 0x80, + ATH9K_ANI_ALL = 0xff +}; + +struct ath9k_mib_stats { + u32 ackrcv_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 beacons; +}; + +struct ath9k_node_stats { + u32 ns_avgbrssi; + u32 ns_avgrssi; + u32 ns_avgtxrssi; + u32 ns_avgtxrate; +}; + +struct ar5416Stats { + u32 ast_ani_niup; + u32 ast_ani_nidown; + u32 ast_ani_spurup; + u32 ast_ani_spurdown; + u32 ast_ani_ofdmon; + u32 ast_ani_ofdmoff; + u32 ast_ani_cckhigh; + u32 ast_ani_ccklow; + u32 ast_ani_stepup; + u32 ast_ani_stepdown; + u32 ast_ani_ofdmerrs; + u32 ast_ani_cckerrs; + u32 ast_ani_reset; + u32 ast_ani_lzero; + u32 ast_ani_lneg; + struct ath9k_mib_stats ast_mibstats; + struct ath9k_node_stats ast_nodestats; +}; +#define ah_mibStats ah_stats.ast_mibstats + +void ath9k_ani_reset(struct ath_hal *ah); +void ath9k_hw_ani_monitor(struct ath_hal *ah, + const struct ath9k_node_stats *stats, + struct ath9k_channel *chan); +bool ath9k_hw_phycounters(struct ath_hal *ah); +void ath9k_enable_mib_counters(struct ath_hal *ah); +void ath9k_hw_disable_mib_counters(struct ath_hal *ah); +u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, u32 *rxc_pcnt, + u32 *rxf_pcnt, u32 *txf_pcnt); +void ath9k_hw_procmibevent(struct ath_hal *ah, + const struct ath9k_node_stats *stats); +void ath9k_hw_ani_setup(struct ath_hal *ah); +void ath9k_hw_ani_attach(struct ath_hal *ah); +void ath9k_hw_ani_detach(struct ath_hal *ah); + +#endif /* ANI_H */ diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 5289d28..3cb7bf8 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -17,1028 +17,683 @@ #ifndef ATH9K_H #define ATH9K_H -#include - -#define ATHEROS_VENDOR_ID 0x168c - -#define AR5416_DEVID_PCI 0x0023 -#define AR5416_DEVID_PCIE 0x0024 -#define AR9160_DEVID_PCI 0x0027 -#define AR9280_DEVID_PCI 0x0029 -#define AR9280_DEVID_PCIE 0x002a -#define AR9285_DEVID_PCIE 0x002b - -#define AR5416_AR9100_DEVID 0x000b - -#define AR_SUBVENDOR_ID_NOG 0x0e11 -#define AR_SUBVENDOR_ID_NEW_A 0x7065 - -#define ATH9K_TXERR_XRETRY 0x01 -#define ATH9K_TXERR_FILT 0x02 -#define ATH9K_TXERR_FIFO 0x04 -#define ATH9K_TXERR_XTXOP 0x08 -#define ATH9K_TXERR_TIMER_EXPIRED 0x10 - -#define ATH9K_TX_BA 0x01 -#define ATH9K_TX_PWRMGMT 0x02 -#define ATH9K_TX_DESC_CFG_ERR 0x04 -#define ATH9K_TX_DATA_UNDERRUN 0x08 -#define ATH9K_TX_DELIM_UNDERRUN 0x10 -#define ATH9K_TX_SW_ABORTED 0x40 -#define ATH9K_TX_SW_FILTERED 0x80 - -#define NBBY 8 - -struct ath_tx_status { - u32 ts_tstamp; - u16 ts_seqnum; - u8 ts_status; - u8 ts_ratecode; - u8 ts_rateindex; - int8_t ts_rssi; - u8 ts_shortretry; - u8 ts_longretry; - u8 ts_virtcol; - u8 ts_antenna; - u8 ts_flags; - int8_t ts_rssi_ctl0; - int8_t ts_rssi_ctl1; - int8_t ts_rssi_ctl2; - int8_t ts_rssi_ext0; - int8_t ts_rssi_ext1; - int8_t ts_rssi_ext2; - u8 pad[3]; - u32 ba_low; - u32 ba_high; - u32 evm0; - u32 evm1; - u32 evm2; -}; - -struct ath_rx_status { - u32 rs_tstamp; - u16 rs_datalen; - u8 rs_status; - u8 rs_phyerr; - int8_t rs_rssi; - u8 rs_keyix; - u8 rs_rate; - u8 rs_antenna; - u8 rs_more; - int8_t rs_rssi_ctl0; - int8_t rs_rssi_ctl1; - int8_t rs_rssi_ctl2; - int8_t rs_rssi_ext0; - int8_t rs_rssi_ext1; - int8_t rs_rssi_ext2; - u8 rs_isaggr; - u8 rs_moreaggr; - u8 rs_num_delims; - u8 rs_flags; - u32 evm0; - u32 evm1; - u32 evm2; -}; - -#define ATH9K_RXERR_CRC 0x01 -#define ATH9K_RXERR_PHY 0x02 -#define ATH9K_RXERR_FIFO 0x04 -#define ATH9K_RXERR_DECRYPT 0x08 -#define ATH9K_RXERR_MIC 0x10 - -#define ATH9K_RX_MORE 0x01 -#define ATH9K_RX_MORE_AGGR 0x02 -#define ATH9K_RX_GI 0x04 -#define ATH9K_RX_2040 0x08 -#define ATH9K_RX_DELIM_CRC_PRE 0x10 -#define ATH9K_RX_DELIM_CRC_POST 0x20 -#define ATH9K_RX_DECRYPT_BUSY 0x40 - -#define ATH9K_RXKEYIX_INVALID ((u8)-1) -#define ATH9K_TXKEYIX_INVALID ((u32)-1) - -struct ath_desc { - u32 ds_link; - u32 ds_data; - u32 ds_ctl0; - u32 ds_ctl1; - u32 ds_hw[20]; - union { - struct ath_tx_status tx; - struct ath_rx_status rx; - void *stats; - } ds_us; - void *ds_vdata; -} __packed; - -#define ds_txstat ds_us.tx -#define ds_rxstat ds_us.rx -#define ds_stat ds_us.stats - -#define ATH9K_TXDESC_CLRDMASK 0x0001 -#define ATH9K_TXDESC_NOACK 0x0002 -#define ATH9K_TXDESC_RTSENA 0x0004 -#define ATH9K_TXDESC_CTSENA 0x0008 -/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for - * the descriptor its marked on. We take a tx interrupt to reap - * descriptors when the h/w hits an EOL condition or - * when the descriptor is specifically marked to generate - * an interrupt with this flag. Descriptors should be - * marked periodically to insure timely replenishing of the - * supply needed for sending frames. Defering interrupts - * reduces system load and potentially allows more concurrent - * work to be done but if done to aggressively can cause - * senders to backup. When the hardware queue is left too - * large rate control information may also be too out of - * date. An Alternative for this is TX interrupt mitigation - * but this needs more testing. */ -#define ATH9K_TXDESC_INTREQ 0x0010 -#define ATH9K_TXDESC_VEOL 0x0020 -#define ATH9K_TXDESC_EXT_ONLY 0x0040 -#define ATH9K_TXDESC_EXT_AND_CTL 0x0080 -#define ATH9K_TXDESC_VMF 0x0100 -#define ATH9K_TXDESC_FRAG_IS_ON 0x0200 -#define ATH9K_TXDESC_CAB 0x0400 - -#define ATH9K_RXDESC_INTREQ 0x0020 - -enum wireless_mode { - ATH9K_MODE_11A = 0, - ATH9K_MODE_11B = 2, - ATH9K_MODE_11G = 3, - ATH9K_MODE_11NA_HT20 = 6, - ATH9K_MODE_11NG_HT20 = 7, - ATH9K_MODE_11NA_HT40PLUS = 8, - ATH9K_MODE_11NA_HT40MINUS = 9, - ATH9K_MODE_11NG_HT40PLUS = 10, - ATH9K_MODE_11NG_HT40MINUS = 11, - ATH9K_MODE_MAX -}; - -enum ath9k_hw_caps { - ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), - ATH9K_HW_CAP_MIC_AESCCM = BIT(1), - ATH9K_HW_CAP_MIC_CKIP = BIT(2), - ATH9K_HW_CAP_MIC_TKIP = BIT(3), - ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), - ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), - ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), - ATH9K_HW_CAP_VEOL = BIT(7), - ATH9K_HW_CAP_BSSIDMASK = BIT(8), - ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), - ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), - ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), - ATH9K_HW_CAP_HT = BIT(12), - ATH9K_HW_CAP_GTT = BIT(13), - ATH9K_HW_CAP_FASTCC = BIT(14), - ATH9K_HW_CAP_RFSILENT = BIT(15), - ATH9K_HW_CAP_WOW = BIT(16), - ATH9K_HW_CAP_CST = BIT(17), - ATH9K_HW_CAP_ENHANCEDPM = BIT(18), - ATH9K_HW_CAP_AUTOSLEEP = BIT(19), - ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), - ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), - ATH9K_HW_CAP_BT_COEX = BIT(22) -}; - -enum ath9k_capability_type { - ATH9K_CAP_CIPHER = 0, - ATH9K_CAP_TKIP_MIC, - ATH9K_CAP_TKIP_SPLIT, - ATH9K_CAP_PHYCOUNTERS, - ATH9K_CAP_DIVERSITY, - ATH9K_CAP_TXPOW, - ATH9K_CAP_PHYDIAG, - ATH9K_CAP_MCAST_KEYSRCH, - ATH9K_CAP_TSF_ADJUST, - ATH9K_CAP_WME_TKIPMIC, - ATH9K_CAP_RFSILENT, - ATH9K_CAP_ANT_CFG_2GHZ, - ATH9K_CAP_ANT_CFG_5GHZ -}; - -struct ath9k_hw_capabilities { - u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ - DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ - u16 total_queues; - u16 keycache_size; - u16 low_5ghz_chan, high_5ghz_chan; - u16 low_2ghz_chan, high_2ghz_chan; - u16 num_mr_retries; - u16 rts_aggr_limit; - u8 tx_chainmask; - u8 rx_chainmask; - u16 tx_triglevel_max; - u16 reg_cap; - u8 num_gpio_pins; - u8 num_antcfg_2ghz; - u8 num_antcfg_5ghz; -}; - -struct ath9k_ops_config { - int dma_beacon_response_time; - int sw_beacon_response_time; - int additional_swba_backoff; - int ack_6mb; - int cwm_ignore_extcca; - u8 pcie_powersave_enable; - u8 pcie_l1skp_enable; - u8 pcie_clock_req; - u32 pcie_waen; - int pcie_power_reset; - u8 pcie_restore; - u8 analog_shiftreg; - u8 ht_enable; - u32 ofdm_trig_low; - u32 ofdm_trig_high; - u32 cck_trig_high; - u32 cck_trig_low; - u32 enable_ani; - u8 noise_immunity_level; - u32 ofdm_weaksignal_det; - u32 cck_weaksignal_thr; - u8 spur_immunity_level; - u8 firstep_level; - int8_t rssi_thr_high; - int8_t rssi_thr_low; - u16 diversity_control; - u16 antenna_switch_swap; - int serialize_regmode; - int intr_mitigation; -#define SPUR_DISABLE 0 -#define SPUR_ENABLE_IOCTL 1 -#define SPUR_ENABLE_EEPROM 2 -#define AR_EEPROM_MODAL_SPURS 5 -#define AR_SPUR_5413_1 1640 -#define AR_SPUR_5413_2 1200 -#define AR_NO_SPUR 0x8000 -#define AR_BASE_FREQ_2GHZ 2300 -#define AR_BASE_FREQ_5GHZ 4900 -#define AR_SPUR_FEEQ_BOUND_HT40 19 -#define AR_SPUR_FEEQ_BOUND_HT20 10 - int spurmode; - u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; -}; - -enum ath9k_tx_queue { - ATH9K_TX_QUEUE_INACTIVE = 0, - ATH9K_TX_QUEUE_DATA, - ATH9K_TX_QUEUE_BEACON, - ATH9K_TX_QUEUE_CAB, - ATH9K_TX_QUEUE_UAPSD, - ATH9K_TX_QUEUE_PSPOLL -}; - -#define ATH9K_NUM_TX_QUEUES 10 - -enum ath9k_tx_queue_subtype { - ATH9K_WME_AC_BK = 0, - ATH9K_WME_AC_BE, - ATH9K_WME_AC_VI, - ATH9K_WME_AC_VO, - ATH9K_WME_UPSD -}; - -enum ath9k_tx_queue_flags { - TXQ_FLAG_TXOKINT_ENABLE = 0x0001, - TXQ_FLAG_TXERRINT_ENABLE = 0x0001, - TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, - TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, - TXQ_FLAG_TXURNINT_ENABLE = 0x0008, - TXQ_FLAG_BACKOFF_DISABLE = 0x0010, - TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, - TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, - TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, -}; - -#define ATH9K_TXQ_USEDEFAULT ((u32) -1) - -#define ATH9K_DECOMP_MASK_SIZE 128 -#define ATH9K_READY_TIME_LO_BOUND 50 -#define ATH9K_READY_TIME_HI_BOUND 96 - -enum ath9k_pkt_type { - ATH9K_PKT_TYPE_NORMAL = 0, - ATH9K_PKT_TYPE_ATIM, - ATH9K_PKT_TYPE_PSPOLL, - ATH9K_PKT_TYPE_BEACON, - ATH9K_PKT_TYPE_PROBE_RESP, - ATH9K_PKT_TYPE_CHIRP, - ATH9K_PKT_TYPE_GRP_POLL, -}; - -struct ath9k_tx_queue_info { - u32 tqi_ver; - enum ath9k_tx_queue tqi_type; - enum ath9k_tx_queue_subtype tqi_subtype; - enum ath9k_tx_queue_flags tqi_qflags; - u32 tqi_priority; - u32 tqi_aifs; - u32 tqi_cwmin; - u32 tqi_cwmax; - u16 tqi_shretry; - u16 tqi_lgretry; - u32 tqi_cbrPeriod; - u32 tqi_cbrOverflowLimit; - u32 tqi_burstTime; - u32 tqi_readyTime; - u32 tqi_physCompBuf; - u32 tqi_intFlags; -}; - -enum ath9k_rx_filter { - ATH9K_RX_FILTER_UCAST = 0x00000001, - ATH9K_RX_FILTER_MCAST = 0x00000002, - ATH9K_RX_FILTER_BCAST = 0x00000004, - ATH9K_RX_FILTER_CONTROL = 0x00000008, - ATH9K_RX_FILTER_BEACON = 0x00000010, - ATH9K_RX_FILTER_PROM = 0x00000020, - ATH9K_RX_FILTER_PROBEREQ = 0x00000080, - ATH9K_RX_FILTER_PSPOLL = 0x00004000, - ATH9K_RX_FILTER_PHYERR = 0x00000100, - ATH9K_RX_FILTER_PHYRADAR = 0x00002000, -}; - -enum ath9k_int { - ATH9K_INT_RX = 0x00000001, - ATH9K_INT_RXDESC = 0x00000002, - ATH9K_INT_RXNOFRM = 0x00000008, - ATH9K_INT_RXEOL = 0x00000010, - ATH9K_INT_RXORN = 0x00000020, - ATH9K_INT_TX = 0x00000040, - ATH9K_INT_TXDESC = 0x00000080, - ATH9K_INT_TIM_TIMER = 0x00000100, - ATH9K_INT_TXURN = 0x00000800, - ATH9K_INT_MIB = 0x00001000, - ATH9K_INT_RXPHY = 0x00004000, - ATH9K_INT_RXKCM = 0x00008000, - ATH9K_INT_SWBA = 0x00010000, - ATH9K_INT_BMISS = 0x00040000, - ATH9K_INT_BNR = 0x00100000, - ATH9K_INT_TIM = 0x00200000, - ATH9K_INT_DTIM = 0x00400000, - ATH9K_INT_DTIMSYNC = 0x00800000, - ATH9K_INT_GPIO = 0x01000000, - ATH9K_INT_CABEND = 0x02000000, - ATH9K_INT_CST = 0x10000000, - ATH9K_INT_GTT = 0x20000000, - ATH9K_INT_FATAL = 0x40000000, - ATH9K_INT_GLOBAL = 0x80000000, - ATH9K_INT_BMISC = ATH9K_INT_TIM | - ATH9K_INT_DTIM | - ATH9K_INT_DTIMSYNC | - ATH9K_INT_CABEND, - ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | - ATH9K_INT_RXDESC | - ATH9K_INT_RXEOL | - ATH9K_INT_RXORN | - ATH9K_INT_TXURN | - ATH9K_INT_TXDESC | - ATH9K_INT_MIB | - ATH9K_INT_RXPHY | - ATH9K_INT_RXKCM | - ATH9K_INT_SWBA | - ATH9K_INT_BMISS | - ATH9K_INT_GPIO, - ATH9K_INT_NOCARD = 0xffffffff -}; - -#define ATH9K_RATESERIES_RTS_CTS 0x0001 -#define ATH9K_RATESERIES_2040 0x0002 -#define ATH9K_RATESERIES_HALFGI 0x0004 - -struct ath9k_11n_rate_series { - u32 Tries; - u32 Rate; - u32 PktDuration; - u32 ChSel; - u32 RateFlags; -}; - -#define CHANNEL_CW_INT 0x00002 -#define CHANNEL_CCK 0x00020 -#define CHANNEL_OFDM 0x00040 -#define CHANNEL_2GHZ 0x00080 -#define CHANNEL_5GHZ 0x00100 -#define CHANNEL_PASSIVE 0x00200 -#define CHANNEL_DYN 0x00400 -#define CHANNEL_HALF 0x04000 -#define CHANNEL_QUARTER 0x08000 -#define CHANNEL_HT20 0x10000 -#define CHANNEL_HT40PLUS 0x20000 -#define CHANNEL_HT40MINUS 0x40000 - -#define CHANNEL_INTERFERENCE 0x01 -#define CHANNEL_DFS 0x02 -#define CHANNEL_4MS_LIMIT 0x04 -#define CHANNEL_DFS_CLEAR 0x08 -#define CHANNEL_DISALLOW_ADHOC 0x10 -#define CHANNEL_PER_11D_ADHOC 0x20 - -#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) -#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) -#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) -#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) -#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) -#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) -#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) -#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) -#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) -#define CHANNEL_ALL \ - (CHANNEL_OFDM| \ - CHANNEL_CCK| \ - CHANNEL_2GHZ | \ - CHANNEL_5GHZ | \ - CHANNEL_HT20 | \ - CHANNEL_HT40PLUS | \ - CHANNEL_HT40MINUS) - -struct ath9k_channel { - struct ieee80211_channel *chan; - u16 channel; - u32 channelFlags; - u32 chanmode; - int32_t CalValid; - bool oneTimeCalsDone; - int8_t iCoff; - int8_t qCoff; - int16_t rawNoiseFloor; -}; - -#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ - (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ - (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ - (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) -#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ - (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ - (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ - (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) -#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) -#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) -#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) -#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) -#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) -#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) - -/* These macros check chanmode and not channelFlags */ -#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) -#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ - ((_c)->chanmode == CHANNEL_G_HT20)) -#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ - ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ - ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ - ((_c)->chanmode == CHANNEL_G_HT40MINUS)) -#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) - -#define IS_CHAN_A_5MHZ_SPACED(_c) \ - ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ - (((_c)->channel % 20) != 0) && \ - (((_c)->channel % 10) != 0)) - -struct ath9k_keyval { - u8 kv_type; - u8 kv_pad; - u16 kv_len; - u8 kv_val[16]; - u8 kv_mic[8]; - u8 kv_txmic[8]; -}; - -enum ath9k_key_type { - ATH9K_KEY_TYPE_CLEAR, - ATH9K_KEY_TYPE_WEP, - ATH9K_KEY_TYPE_AES, - ATH9K_KEY_TYPE_TKIP, -}; - -enum ath9k_cipher { - ATH9K_CIPHER_WEP = 0, - ATH9K_CIPHER_AES_OCB = 1, - ATH9K_CIPHER_AES_CCM = 2, - ATH9K_CIPHER_CKIP = 3, - ATH9K_CIPHER_TKIP = 4, - ATH9K_CIPHER_CLR = 5, - ATH9K_CIPHER_MIC = 127 -}; - -#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 -#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 -#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 -#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 -#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 -#define AR_EEPROM_EEPCAP_MAXQCU_S 4 -#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 -#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 -#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 - -#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 -#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 -#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 -#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 -#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 -#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 - -#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 -#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 - -#define SD_NO_CTL 0xE0 -#define NO_CTL 0xff -#define CTL_MODE_M 7 -#define CTL_11A 0 -#define CTL_11B 1 -#define CTL_11G 2 -#define CTL_2GHT20 5 -#define CTL_5GHT20 6 -#define CTL_2GHT40 7 -#define CTL_5GHT40 8 - -#define AR_EEPROM_MAC(i) (0x1d+(i)) - -#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c -#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 -#define AR_EEPROM_RFSILENT_POLARITY 0x0002 -#define AR_EEPROM_RFSILENT_POLARITY_S 1 - -#define CTRY_DEBUG 0x1ff -#define CTRY_DEFAULT 0 - -enum reg_ext_bitmap { - REG_EXT_JAPAN_MIDBAND = 1, - REG_EXT_FCC_DFS_HT40 = 2, - REG_EXT_JAPAN_NONDFS_HT40 = 3, - REG_EXT_JAPAN_DFS_HT40 = 4 -}; - -struct ath9k_country_entry { - u16 countryCode; - u16 regDmnEnum; - u16 regDmn5G; - u16 regDmn2G; - u8 isMultidomain; - u8 iso[3]; -}; - -#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) -#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) - -#define SM(_v, _f) (((_v) << _f##_S) & _f) -#define MS(_v, _f) (((_v) & _f) >> _f##_S) -#define REG_RMW(_a, _r, _set, _clr) \ - REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) -#define REG_RMW_FIELD(_a, _r, _f, _v) \ - REG_WRITE(_a, _r, \ - (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) -#define REG_SET_BIT(_a, _r, _f) \ - REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) -#define REG_CLR_BIT(_a, _r, _f) \ - REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) - -#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 - -#define INIT_AIFS 2 -#define INIT_CWMIN 15 -#define INIT_CWMIN_11B 31 -#define INIT_CWMAX 1023 -#define INIT_SH_RETRY 10 -#define INIT_LG_RETRY 10 -#define INIT_SSH_RETRY 32 -#define INIT_SLG_RETRY 32 - -#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) - -#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) -#define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX - -#define IEEE80211_WEP_IVLEN 3 -#define IEEE80211_WEP_KIDLEN 1 -#define IEEE80211_WEP_CRCLEN 4 -#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ - (IEEE80211_WEP_IVLEN + \ - IEEE80211_WEP_KIDLEN + \ - IEEE80211_WEP_CRCLEN)) -#define MAX_RATE_POWER 63 - -enum ath9k_power_mode { - ATH9K_PM_AWAKE = 0, - ATH9K_PM_FULL_SLEEP, - ATH9K_PM_NETWORK_SLEEP, - ATH9K_PM_UNDEFINED -}; - -struct ath9k_mib_stats { - u32 ackrcv_bad; - u32 rts_bad; - u32 rts_good; - u32 fcs_bad; - u32 beacons; -}; +#include +#include +#include +#include +#include + +#include "hw.h" +#include "rc.h" +#include "debug.h" + +struct ath_node; + +/* Macro to expand scalars to 64-bit objects */ + +#define ito64(x) (sizeof(x) == 8) ? \ + (((unsigned long long int)(x)) & (0xff)) : \ + (sizeof(x) == 16) ? \ + (((unsigned long long int)(x)) & 0xffff) : \ + ((sizeof(x) == 32) ? \ + (((unsigned long long int)(x)) & 0xffffffff) : \ + (unsigned long long int)(x)) + +/* increment with wrap-around */ +#define INCR(_l, _sz) do { \ + (_l)++; \ + (_l) &= ((_sz) - 1); \ + } while (0) + +/* decrement with wrap-around */ +#define DECR(_l, _sz) do { \ + (_l)--; \ + (_l) &= ((_sz) - 1); \ + } while (0) + +#define A_MAX(a, b) ((a) > (b) ? (a) : (b)) + +#define ASSERT(exp) do { \ + if (unlikely(!(exp))) { \ + BUG(); \ + } \ + } while (0) + +#define TSF_TO_TU(_h,_l) \ + ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) + +#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<bf_status = 0; \ + (_bf)->bf_lastbf = NULL; \ + (_bf)->bf_next = NULL; \ + memset(&((_bf)->bf_state), 0, \ + sizeof(struct ath_buf_state)); \ + } while (0) + +/** + * enum buffer_type - Buffer type flags + * + * @BUF_HT: Send this buffer using HT capabilities + * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) + * @BUF_AGGR: Indicates whether the buffer can be aggregated + * (used in aggregation scheduling) + * @BUF_RETRY: Indicates whether the buffer is retried + * @BUF_XRETRY: To denote excessive retries of the buffer + */ +enum buffer_type { + BUF_HT = BIT(1), + BUF_AMPDU = BIT(2), + BUF_AGGR = BIT(3), + BUF_RETRY = BIT(4), + BUF_XRETRY = BIT(5), +}; + +struct ath_buf_state { + int bfs_nframes; /* # frames in aggregate */ + u16 bfs_al; /* length of aggregate */ + u16 bfs_frmlen; /* length of frame */ + int bfs_seqno; /* sequence number */ + int bfs_tidno; /* tid of this frame */ + int bfs_retries; /* current retries */ + u32 bf_type; /* BUF_* (enum buffer_type) */ + u32 bfs_keyix; + enum ath9k_key_type bfs_keytype; +}; + +#define bf_nframes bf_state.bfs_nframes +#define bf_al bf_state.bfs_al +#define bf_frmlen bf_state.bfs_frmlen +#define bf_retries bf_state.bfs_retries +#define bf_seqno bf_state.bfs_seqno +#define bf_tidno bf_state.bfs_tidno +#define bf_keyix bf_state.bfs_keyix +#define bf_keytype bf_state.bfs_keytype +#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) +#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) +#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) +#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) +#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) -enum ath9k_ant_setting { - ATH9K_ANT_VARIABLE = 0, - ATH9K_ANT_FIXED_A, - ATH9K_ANT_FIXED_B -}; +/* + * Abstraction of a contiguous buffer to transmit/receive. There is only + * a single hw descriptor encapsulated here. + */ +struct ath_buf { + struct list_head list; + struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or + an aggregate) */ + struct ath_buf *bf_next; /* next subframe in the aggregate */ + void *bf_mpdu; /* enclosing frame structure */ + struct ath_desc *bf_desc; /* virtual addr of desc */ + dma_addr_t bf_daddr; /* physical addr of desc */ + dma_addr_t bf_buf_addr; /* physical addr of data buffer */ + u32 bf_status; + u16 bf_flags; /* tx descriptor flags */ + struct ath_buf_state bf_state; /* buffer state */ + dma_addr_t bf_dmacontext; +}; + +#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) +#define ATH_BUFSTATUS_STALE 0x00000002 + +/* DMA state for tx/rx descriptors */ + +struct ath_descdma { + const char *dd_name; + struct ath_desc *dd_desc; /* descriptors */ + dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ + u32 dd_desc_len; /* size of dd_desc */ + struct ath_buf *dd_bufptr; /* associated buffers */ + dma_addr_t dd_dmacontext; +}; + +int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, + struct list_head *head, const char *name, + int nbuf, int ndesc); +void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, + struct list_head *head); + +/***********/ +/* RX / TX */ +/***********/ + +#define ATH_MAX_ANTENNA 3 +#define ATH_RXBUF 512 +#define WME_NUM_TID 16 +#define ATH_TXBUF 512 +#define ATH_TXMAXTRY 13 +#define ATH_11N_TXMAXTRY 10 +#define ATH_MGT_TXMAXTRY 4 +#define WME_BA_BMP_SIZE 64 +#define WME_MAX_BA WME_BA_BMP_SIZE +#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) + +#define TID_TO_WME_AC(_tid) \ + ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ + (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ + (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ + WME_AC_VO) + +#define WME_AC_BE 0 +#define WME_AC_BK 1 +#define WME_AC_VI 2 +#define WME_AC_VO 3 +#define WME_NUM_AC 4 + +#define ADDBA_EXCHANGE_ATTEMPTS 10 +#define ATH_AGGR_DELIM_SZ 4 +#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ +/* number of delimiters for encryption padding */ +#define ATH_AGGR_ENCRYPTDELIM 10 +/* minimum h/w qdepth to be sustained to maximize aggregation */ +#define ATH_AGGR_MIN_QDEPTH 2 +#define ATH_AMPDU_SUBFRAME_DEFAULT 32 +#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) +#define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX + +#define IEEE80211_SEQ_SEQ_SHIFT 4 +#define IEEE80211_SEQ_MAX 4096 +#define IEEE80211_MIN_AMPDU_BUF 0x8 +#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 +#define IEEE80211_WEP_IVLEN 3 +#define IEEE80211_WEP_KIDLEN 1 +#define IEEE80211_WEP_CRCLEN 4 +#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ + (IEEE80211_WEP_IVLEN + \ + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_CRCLEN)) + +/* return whether a bit at index _n in bitmap _bm is set + * _sz is the size of the bitmap */ +#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ + ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) + +/* return block-ack bitmap index given sequence and starting sequence */ +#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) + +/* returns delimiter padding required given the packet length */ +#define ATH_AGGR_GET_NDELIM(_len) \ + (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ + (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) + +#define BAW_WITHIN(_start, _bawsz, _seqno) \ + ((((_seqno) - (_start)) & 4095) < (_bawsz)) + +#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) +#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) +#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) +#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) + +enum ATH_AGGR_STATUS { + ATH_AGGR_DONE, + ATH_AGGR_BAW_CLOSED, + ATH_AGGR_LIMITED, +}; + +struct ath_txq { + u32 axq_qnum; /* hardware q number */ + u32 *axq_link; /* link ptr in last TX desc */ + struct list_head axq_q; /* transmit queue */ + spinlock_t axq_lock; + u32 axq_depth; /* queue depth */ + u8 axq_aggr_depth; /* aggregates queued */ + u32 axq_totalqueued; /* total ever queued */ + bool stopped; /* Is mac80211 queue stopped ? */ + struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ + + /* first desc of the last descriptor that contains CTS */ + struct ath_desc *axq_lastdsWithCTS; + + /* final desc of the gating desc that determines whether + lastdsWithCTS has been DMA'ed or not */ + struct ath_desc *axq_gatingds; + + struct list_head axq_acq; +}; + +#define AGGR_CLEANUP BIT(1) +#define AGGR_ADDBA_COMPLETE BIT(2) +#define AGGR_ADDBA_PROGRESS BIT(3) + +/* per TID aggregate tx state for a destination */ +struct ath_atx_tid { + struct list_head list; /* round-robin tid entry */ + struct list_head buf_q; /* pending buffers */ + struct ath_node *an; + struct ath_atx_ac *ac; + struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ + u16 seq_start; + u16 seq_next; + u16 baw_size; + int tidno; + int baw_head; /* first un-acked tx buffer */ + int baw_tail; /* next unused tx buffer slot */ + int sched; + int paused; + u8 state; + int addba_exchangeattempts; +}; + +/* per access-category aggregate tx state for a destination */ +struct ath_atx_ac { + int sched; /* dest-ac is scheduled */ + int qnum; /* H/W queue number associated + with this AC */ + struct list_head list; /* round-robin txq entry */ + struct list_head tid_q; /* queue of TIDs with buffers */ +}; + +/* per-frame tx control block */ +struct ath_tx_control { + struct ath_txq *txq; + int if_id; +}; + +/* per frame tx status block */ +struct ath_xmit_status { + int retries; /* number of retries to successufully + transmit this frame */ + int flags; /* status of transmit */ +#define ATH_TX_ERROR 0x01 +#define ATH_TX_XRETRY 0x02 +#define ATH_TX_BAR 0x04 +}; + +/* All RSSI values are noise floor adjusted */ +struct ath_tx_stat { + int rssi; + int rssictl[ATH_MAX_ANTENNA]; + int rssiextn[ATH_MAX_ANTENNA]; + int rateieee; + int rateKbps; + int ratecode; + int flags; + u32 airtime; /* time on air per final tx rate */ +}; + +struct aggr_rifs_param { + int param_max_frames; + int param_max_len; + int param_rl; + int param_al; + struct ath_rc_series *param_rcs; +}; + +struct ath_node { + struct ath_softc *an_sc; + struct ath_atx_tid tid[WME_NUM_TID]; + struct ath_atx_ac ac[WME_NUM_AC]; + u16 maxampdu; + u8 mpdudensity; +}; + +struct ath_tx { + u16 seq_no; + u32 txqsetup; + int hwq_map[ATH9K_WME_AC_VO+1]; + spinlock_t txbuflock; + struct list_head txbuf; + struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; + struct ath_descdma txdma; +}; + +struct ath_rx { + u8 defant; + u8 rxotherant; + u32 *rxlink; + int bufsize; + unsigned int rxfilter; + spinlock_t rxflushlock; + spinlock_t rxbuflock; + struct list_head rxbuf; + struct ath_descdma rxdma; +}; + +int ath_startrecv(struct ath_softc *sc); +bool ath_stoprecv(struct ath_softc *sc); +void ath_flushrecv(struct ath_softc *sc); +u32 ath_calcrxfilter(struct ath_softc *sc); +int ath_rx_init(struct ath_softc *sc, int nbufs); +void ath_rx_cleanup(struct ath_softc *sc); +int ath_rx_tasklet(struct ath_softc *sc, int flush); +struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); +void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); +int ath_tx_setup(struct ath_softc *sc, int haltype); +void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); +void ath_draintxq(struct ath_softc *sc, + struct ath_txq *txq, bool retry_tx); +void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); +void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); +void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); +int ath_tx_init(struct ath_softc *sc, int nbufs); +int ath_tx_cleanup(struct ath_softc *sc); +struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); +int ath_txq_update(struct ath_softc *sc, int qnum, + struct ath9k_tx_queue_info *q); +int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb, + struct ath_tx_control *txctl); +void ath_tx_tasklet(struct ath_softc *sc); +void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb); +bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); +int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, + u16 tid, u16 *ssn); +int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); +void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); + +/********/ +/* VAPs */ +/********/ -#define ATH9K_SLOT_TIME_6 6 -#define ATH9K_SLOT_TIME_9 9 -#define ATH9K_SLOT_TIME_20 20 +/* + * Define the scheme that we select MAC address for multiple + * BSS on the same radio. The very first VAP will just use the MAC + * address from the EEPROM. For the next 3 VAPs, we set the + * U/L bit (bit 1) in MAC address, and use the next two bits as the + * index of the VAP. + */ -enum ath9k_ht_macmode { - ATH9K_HT_MACMODE_20 = 0, - ATH9K_HT_MACMODE_2040 = 1, -}; +#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ + ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) -enum ath9k_ht_extprotspacing { - ATH9K_HT_EXTPROTSPACING_20 = 0, - ATH9K_HT_EXTPROTSPACING_25 = 1, +struct ath_vap { + int av_bslot; + enum nl80211_iftype av_opmode; + struct ath_buf *av_bcbuf; + struct ath_tx_control av_btxctl; }; -struct ath9k_ht_cwm { - enum ath9k_ht_macmode ht_macmode; - enum ath9k_ht_extprotspacing ht_extprotspacing; -}; +/*******************/ +/* Beacon Handling */ +/*******************/ -enum ath9k_ani_cmd { - ATH9K_ANI_PRESENT = 0x1, - ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, - ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, - ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, - ATH9K_ANI_FIRSTEP_LEVEL = 0x10, - ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, - ATH9K_ANI_MODE = 0x40, - ATH9K_ANI_PHYERR_RESET = 0x80, - ATH9K_ANI_ALL = 0xff -}; +/* + * Regardless of the number of beacons we stagger, (i.e. regardless of the + * number of BSSIDs) if a given beacon does not go out even after waiting this + * number of beacon intervals, the game's up. + */ +#define BSTUCK_THRESH (9 * ATH_BCBUF) +#define ATH_BCBUF 1 +#define ATH_DEFAULT_BINTVAL 100 /* TU */ +#define ATH_DEFAULT_BMISS_LIMIT 10 +#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) + +struct ath_beacon_config { + u16 beacon_interval; + u16 listen_interval; + u16 dtim_period; + u16 bmiss_timeout; + u8 dtim_count; + u8 tim_offset; + union { + u64 last_tsf; + u8 last_tstamp[8]; + } u; /* last received beacon/probe response timestamp of this BSS. */ +}; + +struct ath_beacon { + enum { + OK, /* no change needed */ + UPDATE, /* update pending */ + COMMIT /* beacon sent, commit change */ + } updateslot; /* slot time update fsm */ + + u32 beaconq; + u32 bmisscnt; + u32 ast_be_xmit; + u64 bc_tstamp; + int bslot[ATH_BCBUF]; + int slottime; + int slotupdate; + struct ath9k_tx_queue_info beacon_qi; + struct ath_descdma bdma; + struct ath_txq *cabq; + struct list_head bbuf; +}; + +void ath9k_beacon_tasklet(unsigned long data); +void ath_beacon_config(struct ath_softc *sc, int if_id); +int ath_beaconq_setup(struct ath_hal *ah); +int ath_beacon_alloc(struct ath_softc *sc, int if_id); +void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp); +void ath_beacon_sync(struct ath_softc *sc, int if_id); + +/*******/ +/* ANI */ +/*******/ -enum { - WLAN_RC_PHY_OFDM, - WLAN_RC_PHY_CCK, - WLAN_RC_PHY_HT_20_SS, - WLAN_RC_PHY_HT_20_DS, - WLAN_RC_PHY_HT_40_SS, - WLAN_RC_PHY_HT_40_DS, - WLAN_RC_PHY_HT_20_SS_HGI, - WLAN_RC_PHY_HT_20_DS_HGI, - WLAN_RC_PHY_HT_40_SS_HGI, - WLAN_RC_PHY_HT_40_DS_HGI, - WLAN_RC_PHY_MAX -}; +/* ANI values for STA only. + FIXME: Add appropriate values for AP later */ -enum ath9k_tp_scale { - ATH9K_TP_SCALE_MAX = 0, - ATH9K_TP_SCALE_50, - ATH9K_TP_SCALE_25, - ATH9K_TP_SCALE_12, - ATH9K_TP_SCALE_MIN -}; +#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */ +#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */ +#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */ +#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */ -enum ser_reg_mode { - SER_REG_MODE_OFF = 0, - SER_REG_MODE_ON = 1, - SER_REG_MODE_AUTO = 2, +struct ath_ani { + bool sc_caldone; + int16_t sc_noise_floor; + unsigned int sc_longcal_timer; + unsigned int sc_shortcal_timer; + unsigned int sc_resetcal_timer; + unsigned int sc_checkani_timer; + struct timer_list timer; }; -#define AR_PHY_CCA_MAX_GOOD_VALUE -85 -#define AR_PHY_CCA_MAX_HIGH_VALUE -62 -#define AR_PHY_CCA_MIN_BAD_VALUE -121 -#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3 -#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5 +/********************/ +/* LED Control */ +/********************/ -#define ATH9K_NF_CAL_HIST_MAX 5 -#define NUM_NF_READINGS 6 +#define ATH_LED_PIN 1 +#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ +#define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ -struct ath9k_nfcal_hist { - int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; - u8 currIndex; - int16_t privNF; - u8 invalidNFcount; +enum ath_led_type { + ATH_LED_RADIO, + ATH_LED_ASSOC, + ATH_LED_TX, + ATH_LED_RX }; -struct ath9k_beacon_state { - u32 bs_nexttbtt; - u32 bs_nextdtim; - u32 bs_intval; -#define ATH9K_BEACON_PERIOD 0x0000ffff -#define ATH9K_BEACON_ENA 0x00800000 -#define ATH9K_BEACON_RESET_TSF 0x01000000 - u32 bs_dtimperiod; - u16 bs_cfpperiod; - u16 bs_cfpmaxduration; - u32 bs_cfpnext; - u16 bs_timoffset; - u16 bs_bmissthreshold; - u32 bs_sleepduration; +struct ath_led { + struct ath_softc *sc; + struct led_classdev led_cdev; + enum ath_led_type led_type; + char name[32]; + bool registered; }; -struct ath9k_node_stats { - u32 ns_avgbrssi; - u32 ns_avgrssi; - u32 ns_avgtxrssi; - u32 ns_avgtxrate; -}; - -#define ATH9K_RSSI_EP_MULTIPLIER (1<<7) - -#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 -#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 -#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 -#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 -#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 -#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 +/* Rfkill */ +#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */ -enum { - ATH9K_RESET_POWER_ON, - ATH9K_RESET_WARM, - ATH9K_RESET_COLD, +struct ath_rfkill { + struct rfkill *rfkill; + struct delayed_work rfkill_poll; + char rfkill_name[32]; }; -#define AH_USE_EEPROM 0x1 - -struct ath_hal { - u32 ah_magic; - u16 ah_devid; - u16 ah_subvendorid; - u32 ah_macVersion; - u16 ah_macRev; - u16 ah_phyRev; - u16 ah_analog5GhzRev; - u16 ah_analog2GhzRev; - - void __iomem *ah_sh; - struct ath_softc *ah_sc; - - enum nl80211_iftype ah_opmode; - struct ath9k_ops_config ah_config; - struct ath9k_hw_capabilities ah_caps; - - u16 ah_countryCode; - u32 ah_flags; - int16_t ah_powerLimit; - u16 ah_maxPowerLevel; - u32 ah_tpScale; - u16 ah_currentRD; - u16 ah_currentRDExt; - u16 ah_currentRDInUse; - char alpha2[2]; - struct reg_dmn_pair_mapping *regpair; - enum ath9k_power_mode ah_power_mode; - enum ath9k_power_mode ah_restore_mode; - - struct ath9k_channel ah_channels[38]; - struct ath9k_channel *ah_curchan; - - bool ah_isPciExpress; - u16 ah_txTrigLevel; - u16 ah_rfsilent; - u32 ah_rfkill_gpio; - u32 ah_rfkill_polarity; - u32 ah_btactive_gpio; - u32 ah_wlanactive_gpio; - struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; - - bool sw_mgmt_crypto; -}; - -struct chan_centers { - u16 synth_center; - u16 ctl_center; - u16 ext_center; -}; +/********************/ +/* Main driver core */ +/********************/ -struct ath_rate_table; - -/* Helpers */ - -bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); -u32 ath9k_hw_reverse_bits(u32 val, u32 n); -bool ath9k_get_channel_edges(struct ath_hal *ah, - u16 flags, u16 *low, - u16 *high); -u16 ath9k_hw_computetxtime(struct ath_hal *ah, - struct ath_rate_table *rates, - u32 frameLen, u16 rateix, - bool shortPreamble); -void ath9k_hw_get_channel_centers(struct ath_hal *ah, - struct ath9k_channel *chan, - struct chan_centers *centers); - -/* Attach, Detach */ - -const char *ath9k_hw_probe(u16 vendorid, u16 devid); -void ath9k_hw_detach(struct ath_hal *ah); -struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, - void __iomem *mem, int *error); -void ath9k_hw_rfdetach(struct ath_hal *ah); - - -/* HW Reset */ - -int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, - bool bChannelChange); - -/* Key Cache Management */ - -bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); -bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac); -bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, - const struct ath9k_keyval *k, - const u8 *mac, int xorKey); -bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); - -/* Power Management */ - -bool ath9k_hw_setpower(struct ath_hal *ah, - enum ath9k_power_mode mode); -void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); - -/* Beacon timers */ - -void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period); -void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, - const struct ath9k_beacon_state *bs); -/* HW Capabilities */ - -bool ath9k_hw_fill_cap_info(struct ath_hal *ah); -bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, - u32 capability, u32 *result); -bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, - u32 capability, u32 setting, int *status); - -/* GPIO / RFKILL / Antennae */ +/* + * Default cache line size, in bytes. + * Used when PCI device not fully initialized by bootrom/BIOS +*/ +#define DEFAULT_CACHELINE 32 +#define ATH_DEFAULT_NOISE_FLOOR -95 +#define ATH_REGCLASSIDS_MAX 10 +#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ +#define ATH_MAX_SW_RETRIES 10 +#define ATH_CHAN_MAX 255 +#define IEEE80211_WEP_NKID 4 /* number of key ids */ -void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); -u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); -void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, - u32 ah_signal_type); -void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); -#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) -void ath9k_enable_rfkill(struct ath_hal *ah); +/* + * The key cache is used for h/w cipher state and also for + * tracking station state such as the current tx antenna. + * We also setup a mapping table between key cache slot indices + * and station state to short-circuit node lookups on rx. + * Different parts have different size key caches. We handle + * up to ATH_KEYMAX entries (could dynamically allocate state). + */ +#define ATH_KEYMAX 128 /* max key cache size we handle */ + +#define ATH_IF_ID_ANY 0xff +#define ATH_TXPOWER_MAX 100 /* .5 dBm units */ +#define ATH_RSSI_DUMMY_MARKER 0x127 +#define ATH_RATE_DUMMY_MARKER 0 + +#define SC_OP_INVALID BIT(0) +#define SC_OP_BEACONS BIT(1) +#define SC_OP_RXAGGR BIT(2) +#define SC_OP_TXAGGR BIT(3) +#define SC_OP_CHAINMASK_UPDATE BIT(4) +#define SC_OP_FULL_RESET BIT(5) +#define SC_OP_NO_RESET BIT(6) +#define SC_OP_PREAMBLE_SHORT BIT(7) +#define SC_OP_PROTECT_ENABLE BIT(8) +#define SC_OP_RXFLUSH BIT(9) +#define SC_OP_LED_ASSOCIATED BIT(10) +#define SC_OP_RFKILL_REGISTERED BIT(11) +#define SC_OP_RFKILL_SW_BLOCKED BIT(12) +#define SC_OP_RFKILL_HW_BLOCKED BIT(13) +#define SC_OP_WAIT_FOR_BEACON BIT(14) +#define SC_OP_LED_ON BIT(15) + +struct ath_bus_ops { + void (*read_cachesize)(struct ath_softc *sc, int *csz); + void (*cleanup)(struct ath_softc *sc); + bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data); +}; + +struct ath_softc { + struct ieee80211_hw *hw; + struct device *dev; + struct tasklet_struct intr_tq; + struct tasklet_struct bcon_tasklet; + struct ath_hal *sc_ah; + void __iomem *mem; + int irq; + spinlock_t sc_resetlock; + struct mutex mutex; + + u8 sc_curbssid[ETH_ALEN]; + u8 sc_myaddr[ETH_ALEN]; + u8 sc_bssidmask[ETH_ALEN]; + u32 sc_intrstatus; + u32 sc_flags; /* SC_OP_* */ + u16 sc_curtxpow; + u16 sc_curaid; + u16 sc_cachelsz; + u8 sc_nbcnvaps; + u16 sc_nvaps; + u8 sc_tx_chainmask; + u8 sc_rx_chainmask; + u32 sc_keymax; + DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); + u8 sc_splitmic; + atomic_t ps_usecount; + enum ath9k_int sc_imask; + enum ath9k_ht_extprotspacing sc_ht_extprotspacing; + enum ath9k_ht_macmode tx_chan_width; + + struct ath_config sc_config; + struct ath_rx rx; + struct ath_tx tx; + struct ath_beacon beacon; + struct ieee80211_vif *sc_vaps[ATH_BCBUF]; + struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; + struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; + struct ath_rate_table *cur_rate_table; + struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; + + struct ath_led radio_led; + struct ath_led assoc_led; + struct ath_led tx_led; + struct ath_led rx_led; + struct delayed_work ath_led_blink_work; + int led_on_duration; + int led_off_duration; + int led_on_cnt; + int led_off_cnt; + + struct ath_rfkill rf_kill; + struct ath_ani sc_ani; + struct ath9k_node_stats sc_halstats; +#ifdef CONFIG_ATH9K_DEBUG + struct ath9k_debug sc_debug; +#endif + struct ath_bus_ops *bus_ops; +}; + +int ath_reset(struct ath_softc *sc, bool retry_tx); +int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); +int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); +int ath_cabq_update(struct ath_softc *); + +static inline void ath_read_cachesize(struct ath_softc *sc, int *csz) +{ + sc->bus_ops->read_cachesize(sc, csz); +} + +static inline void ath_bus_cleanup(struct ath_softc *sc) +{ + sc->bus_ops->cleanup(sc); +} + +extern struct ieee80211_ops ath9k_ops; + +irqreturn_t ath_isr(int irq, void *dev); +void ath_cleanup(struct ath_softc *sc); +int ath_attach(u16 devid, struct ath_softc *sc); +void ath_detach(struct ath_softc *sc); +const char *ath_mac_bb_name(u32 mac_bb_version); +const char *ath_rf_name(u16 rf_version); + +#ifdef CONFIG_PCI +int ath_pci_init(void); +void ath_pci_exit(void); +#else +static inline int ath_pci_init(void) { return 0; }; +static inline void ath_pci_exit(void) {}; #endif -u32 ath9k_hw_getdefantenna(struct ath_hal *ah); -void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); -bool ath9k_hw_setantennaswitch(struct ath_hal *ah, - enum ath9k_ant_setting settings, - struct ath9k_channel *chan, - u8 *tx_chainmask, - u8 *rx_chainmask, - u8 *antenna_cfgd); - -/* General Operation */ - -u32 ath9k_hw_getrxfilter(struct ath_hal *ah); -void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); -bool ath9k_hw_phy_disable(struct ath_hal *ah); -bool ath9k_hw_disable(struct ath_hal *ah); -bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); -void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac); -bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); -void ath9k_hw_setopmode(struct ath_hal *ah); -void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); -void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask); -bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask); -void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId); -u64 ath9k_hw_gettsf64(struct ath_hal *ah); -void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64); -void ath9k_hw_reset_tsf(struct ath_hal *ah); -bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting); -bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); -void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); - -/* Regulatory */ -u16 ath9k_regd_get_rd(struct ath_hal *ah); -bool ath9k_is_world_regd(struct ath_hal *ah); -const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah); -const struct ieee80211_regdomain *ath9k_default_world_regdomain(void); - -void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby); -void ath9k_reg_apply_radar_flags(struct wiphy *wiphy); - -int ath9k_regd_init(struct ath_hal *ah); -bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah); -u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); -int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request); - -/* ANI */ - -void ath9k_ani_reset(struct ath_hal *ah); -void ath9k_hw_ani_monitor(struct ath_hal *ah, - const struct ath9k_node_stats *stats, - struct ath9k_channel *chan); -bool ath9k_hw_phycounters(struct ath_hal *ah); -void ath9k_enable_mib_counters(struct ath_hal *ah); -void ath9k_hw_disable_mib_counters(struct ath_hal *ah); -u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, - u32 *rxc_pcnt, - u32 *rxf_pcnt, - u32 *txf_pcnt); -void ath9k_hw_procmibevent(struct ath_hal *ah, - const struct ath9k_node_stats *stats); -void ath9k_hw_ani_setup(struct ath_hal *ah); -void ath9k_hw_ani_attach(struct ath_hal *ah); -void ath9k_hw_ani_detach(struct ath_hal *ah); - -/* Calibration */ - -bool ath9k_hw_reset_calvalid(struct ath_hal *ah); -void ath9k_hw_start_nfcal(struct ath_hal *ah); -void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); -int16_t ath9k_hw_getnf(struct ath_hal *ah, - struct ath9k_channel *chan); -void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); -s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan); -bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, - u8 rxchainmask, bool longcal, - bool *isCalDone); -bool ath9k_hw_init_cal(struct ath_hal *ah, - struct ath9k_channel *chan); - - -/* EEPROM */ - -int ath9k_hw_set_txpower(struct ath_hal *ah, - struct ath9k_channel *chan, - u16 cfgCtl, - u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit); -void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); -bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, - struct ath9k_channel *chan, - int16_t *ratesArray, - u16 cfgCtl, - u8 AntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit); -bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, - struct ath9k_channel *chan, - int16_t *pTxPowerIndexOffset); -bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, - struct ath9k_channel *chan); -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, - struct ath9k_channel *chan); -u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, - enum ieee80211_band freq_band); -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); -int ath9k_hw_eeprom_attach(struct ath_hal *ah); - -/* Interrupt Handling */ - -bool ath9k_hw_intrpend(struct ath_hal *ah); -bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); -enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); - -/* MAC (PCU/QCU) */ - -u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); -bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp); -bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); -u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); -bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel); -bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); -bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, - u32 segLen, bool firstSeg, - bool lastSeg, const struct ath_desc *ds0); -void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); -int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, - u32 pktLen, enum ath9k_pkt_type type, u32 txPower, - u32 keyIx, enum ath9k_key_type keyType, u32 flags); -void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, - struct ath_desc *lastds, - u32 durUpdateEn, u32 rtsctsRate, - u32 rtsctsDuration, - struct ath9k_11n_rate_series series[], - u32 nseries, u32 flags); -void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, - u32 aggrLen); -void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, - u32 numDelims); -void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, - u32 burstDuration); -void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, - u32 vmf); -void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); -bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, - const struct ath9k_tx_queue_info *qinfo); -bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, - struct ath9k_tx_queue_info *qinfo); -int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, - const struct ath9k_tx_queue_info *qinfo); -bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); -bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); -int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, - u32 pa, struct ath_desc *nds, u64 tsf); -bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, - u32 size, u32 flags); -bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); -void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); -void ath9k_hw_rxena(struct ath_hal *ah); -void ath9k_hw_startpcureceive(struct ath_hal *ah); -void ath9k_hw_stoppcurecv(struct ath_hal *ah); -bool ath9k_hw_stopdmarecv(struct ath_hal *ah); -void ath9k_hw_btcoex_enable(struct ath_hal *ah); +#ifdef CONFIG_ATHEROS_AR71XX +int ath_ahb_init(void); +void ath_ahb_exit(void); +#else +static inline int ath_ahb_init(void) { return 0; }; +static inline void ath_ahb_exit(void) {}; #endif + +static inline void ath9k_ps_wakeup(struct ath_softc *sc) +{ + if (atomic_inc_return(&sc->ps_usecount) == 1) + if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) { + sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode; + ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); + } +} + +static inline void ath9k_ps_restore(struct ath_softc *sc) +{ + if (atomic_dec_and_test(&sc->ps_usecount)) + if (sc->hw->conf.flags & IEEE80211_CONF_PS) + ath9k_hw_setpower(sc->sc_ah, + sc->sc_ah->ah_restore_mode); +} +#endif /* ATH9K_H */ diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 61d37be..1f92ad7 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -14,7 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" +#include "ath9k.h" /* * This function will modify certain transmit queue properties depending on diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 69ff01c..016302c 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -14,10 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" -#include "hw.h" -#include "reg.h" -#include "phy.h" +#include "ath9k.h" /* We can tune this as we go by monitoring really low values */ #define ATH9K_NF_TOO_LOW -60 diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h new file mode 100644 index 0000000..ac7d88f --- /dev/null +++ b/drivers/net/wireless/ath9k/calib.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef CALIB_H +#define CALIB_H + +extern const struct hal_percal_data iq_cal_multi_sample; +extern const struct hal_percal_data iq_cal_single_sample; +extern const struct hal_percal_data adc_gain_cal_multi_sample; +extern const struct hal_percal_data adc_gain_cal_single_sample; +extern const struct hal_percal_data adc_dc_cal_multi_sample; +extern const struct hal_percal_data adc_dc_cal_single_sample; +extern const struct hal_percal_data adc_init_dc_cal; + +#define AR_PHY_CCA_MAX_GOOD_VALUE -85 +#define AR_PHY_CCA_MAX_HIGH_VALUE -62 +#define AR_PHY_CCA_MIN_BAD_VALUE -121 +#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3 +#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5 + +#define NUM_NF_READINGS 6 +#define ATH9K_NF_CAL_HIST_MAX 5 + +struct ar5416IniArray { + u32 *ia_array; + u32 ia_rows; + u32 ia_columns; +}; + +#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ + (iniarray)->ia_array = (u32 *)(array); \ + (iniarray)->ia_rows = (rows); \ + (iniarray)->ia_columns = (columns); \ + } while (0) + +#define INI_RA(iniarray, row, column) \ + (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) + +#define INIT_CAL(_perCal) do { \ + (_perCal)->calState = CAL_WAITING; \ + (_perCal)->calNext = NULL; \ + } while (0) + +#define INSERT_CAL(_ahp, _perCal) \ + do { \ + if ((_ahp)->ah_cal_list_last == NULL) { \ + (_ahp)->ah_cal_list = \ + (_ahp)->ah_cal_list_last = (_perCal); \ + ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ + } else { \ + ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ + (_ahp)->ah_cal_list_last = (_perCal); \ + (_perCal)->calNext = (_ahp)->ah_cal_list; \ + } \ + } while (0) + +enum hal_cal_types { + ADC_DC_INIT_CAL = 0x1, + ADC_GAIN_CAL = 0x2, + ADC_DC_CAL = 0x4, + IQ_MISMATCH_CAL = 0x8 +}; + +enum hal_cal_state { + CAL_INACTIVE, + CAL_WAITING, + CAL_RUNNING, + CAL_DONE +}; + +#define MIN_CAL_SAMPLES 1 +#define MAX_CAL_SAMPLES 64 +#define INIT_LOG_COUNT 5 +#define PER_MIN_LOG_COUNT 2 +#define PER_MAX_LOG_COUNT 10 + +struct hal_percal_data { + enum hal_cal_types calType; + u32 calNumSamples; + u32 calCountMax; + void (*calCollect) (struct ath_hal *); + void (*calPostProc) (struct ath_hal *, u8); +}; + +struct hal_cal_list { + const struct hal_percal_data *calData; + enum hal_cal_state calState; + struct hal_cal_list *calNext; +}; + +struct ath9k_nfcal_hist { + int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; + u8 currIndex; + int16_t privNF; + u8 invalidNFcount; +}; + +bool ath9k_hw_reset_calvalid(struct ath_hal *ah); +void ath9k_hw_start_nfcal(struct ath_hal *ah); +void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); +int16_t ath9k_hw_getnf(struct ath_hal *ah, + struct ath9k_channel *chan); +void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); +s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan); +bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, + u8 rxchainmask, bool longcal, + bool *isCalDone); +bool ath9k_hw_init_cal(struct ath_hal *ah, + struct ath9k_channel *chan); + +#endif /* CALIB_H */ diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h deleted file mode 100644 index 64fc5c2..0000000 --- a/drivers/net/wireless/ath9k/core.h +++ /dev/null @@ -1,821 +0,0 @@ -/* - * Copyright (c) 2008 Atheros Communications Inc. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef CORE_H -#define CORE_H - -#include -#include -#include -#include -#include - -#include "ath9k.h" -#include "rc.h" - -struct ath_node; - -/* Macro to expand scalars to 64-bit objects */ - -#define ito64(x) (sizeof(x) == 8) ? \ - (((unsigned long long int)(x)) & (0xff)) : \ - (sizeof(x) == 16) ? \ - (((unsigned long long int)(x)) & 0xffff) : \ - ((sizeof(x) == 32) ? \ - (((unsigned long long int)(x)) & 0xffffffff) : \ - (unsigned long long int)(x)) - -/* increment with wrap-around */ -#define INCR(_l, _sz) do { \ - (_l)++; \ - (_l) &= ((_sz) - 1); \ - } while (0) - -/* decrement with wrap-around */ -#define DECR(_l, _sz) do { \ - (_l)--; \ - (_l) &= ((_sz) - 1); \ - } while (0) - -#define A_MAX(a, b) ((a) > (b) ? (a) : (b)) - -#define ASSERT(exp) do { \ - if (unlikely(!(exp))) { \ - BUG(); \ - } \ - } while (0) - -#define TSF_TO_TU(_h,_l) \ - ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) - -#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<bf_status = 0; \ - (_bf)->bf_lastbf = NULL; \ - (_bf)->bf_next = NULL; \ - memset(&((_bf)->bf_state), 0, \ - sizeof(struct ath_buf_state)); \ - } while (0) - -/** - * enum buffer_type - Buffer type flags - * - * @BUF_HT: Send this buffer using HT capabilities - * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) - * @BUF_AGGR: Indicates whether the buffer can be aggregated - * (used in aggregation scheduling) - * @BUF_RETRY: Indicates whether the buffer is retried - * @BUF_XRETRY: To denote excessive retries of the buffer - */ -enum buffer_type { - BUF_HT = BIT(1), - BUF_AMPDU = BIT(2), - BUF_AGGR = BIT(3), - BUF_RETRY = BIT(4), - BUF_XRETRY = BIT(5), -}; - -struct ath_buf_state { - int bfs_nframes; /* # frames in aggregate */ - u16 bfs_al; /* length of aggregate */ - u16 bfs_frmlen; /* length of frame */ - int bfs_seqno; /* sequence number */ - int bfs_tidno; /* tid of this frame */ - int bfs_retries; /* current retries */ - u32 bf_type; /* BUF_* (enum buffer_type) */ - u32 bfs_keyix; - enum ath9k_key_type bfs_keytype; -}; - -#define bf_nframes bf_state.bfs_nframes -#define bf_al bf_state.bfs_al -#define bf_frmlen bf_state.bfs_frmlen -#define bf_retries bf_state.bfs_retries -#define bf_seqno bf_state.bfs_seqno -#define bf_tidno bf_state.bfs_tidno -#define bf_keyix bf_state.bfs_keyix -#define bf_keytype bf_state.bfs_keytype -#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) -#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) -#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) -#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) -#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) - -/* - * Abstraction of a contiguous buffer to transmit/receive. There is only - * a single hw descriptor encapsulated here. - */ -struct ath_buf { - struct list_head list; - struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or - an aggregate) */ - struct ath_buf *bf_next; /* next subframe in the aggregate */ - void *bf_mpdu; /* enclosing frame structure */ - struct ath_desc *bf_desc; /* virtual addr of desc */ - dma_addr_t bf_daddr; /* physical addr of desc */ - dma_addr_t bf_buf_addr; /* physical addr of data buffer */ - u32 bf_status; - u16 bf_flags; /* tx descriptor flags */ - struct ath_buf_state bf_state; /* buffer state */ - dma_addr_t bf_dmacontext; -}; - -#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) -#define ATH_BUFSTATUS_STALE 0x00000002 - -/* DMA state for tx/rx descriptors */ - -struct ath_descdma { - const char *dd_name; - struct ath_desc *dd_desc; /* descriptors */ - dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ - u32 dd_desc_len; /* size of dd_desc */ - struct ath_buf *dd_bufptr; /* associated buffers */ - dma_addr_t dd_dmacontext; -}; - -int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, - struct list_head *head, const char *name, - int nbuf, int ndesc); -void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, - struct list_head *head); - -/***********/ -/* RX / TX */ -/***********/ - -#define ATH_MAX_ANTENNA 3 -#define ATH_RXBUF 512 -#define WME_NUM_TID 16 -#define ATH_TXBUF 512 -#define ATH_TXMAXTRY 13 -#define ATH_11N_TXMAXTRY 10 -#define ATH_MGT_TXMAXTRY 4 -#define WME_BA_BMP_SIZE 64 -#define WME_MAX_BA WME_BA_BMP_SIZE -#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) - -#define TID_TO_WME_AC(_tid) \ - ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ - (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ - (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ - WME_AC_VO) - -#define WME_AC_BE 0 -#define WME_AC_BK 1 -#define WME_AC_VI 2 -#define WME_AC_VO 3 -#define WME_NUM_AC 4 - -#define ADDBA_EXCHANGE_ATTEMPTS 10 -#define ATH_AGGR_DELIM_SZ 4 -#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ -/* number of delimiters for encryption padding */ -#define ATH_AGGR_ENCRYPTDELIM 10 -/* minimum h/w qdepth to be sustained to maximize aggregation */ -#define ATH_AGGR_MIN_QDEPTH 2 -#define ATH_AMPDU_SUBFRAME_DEFAULT 32 -#define IEEE80211_SEQ_SEQ_SHIFT 4 -#define IEEE80211_SEQ_MAX 4096 -#define IEEE80211_MIN_AMPDU_BUF 0x8 -#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 - -/* return whether a bit at index _n in bitmap _bm is set - * _sz is the size of the bitmap */ -#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ - ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) - -/* return block-ack bitmap index given sequence and starting sequence */ -#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) - -/* returns delimiter padding required given the packet length */ -#define ATH_AGGR_GET_NDELIM(_len) \ - (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ - (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) - -#define BAW_WITHIN(_start, _bawsz, _seqno) \ - ((((_seqno) - (_start)) & 4095) < (_bawsz)) - -#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) -#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) -#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) -#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) - -enum ATH_AGGR_STATUS { - ATH_AGGR_DONE, - ATH_AGGR_BAW_CLOSED, - ATH_AGGR_LIMITED, -}; - -struct ath_txq { - u32 axq_qnum; /* hardware q number */ - u32 *axq_link; /* link ptr in last TX desc */ - struct list_head axq_q; /* transmit queue */ - spinlock_t axq_lock; - u32 axq_depth; /* queue depth */ - u8 axq_aggr_depth; /* aggregates queued */ - u32 axq_totalqueued; /* total ever queued */ - bool stopped; /* Is mac80211 queue stopped ? */ - struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ - - /* first desc of the last descriptor that contains CTS */ - struct ath_desc *axq_lastdsWithCTS; - - /* final desc of the gating desc that determines whether - lastdsWithCTS has been DMA'ed or not */ - struct ath_desc *axq_gatingds; - - struct list_head axq_acq; -}; - -#define AGGR_CLEANUP BIT(1) -#define AGGR_ADDBA_COMPLETE BIT(2) -#define AGGR_ADDBA_PROGRESS BIT(3) - -/* per TID aggregate tx state for a destination */ -struct ath_atx_tid { - struct list_head list; /* round-robin tid entry */ - struct list_head buf_q; /* pending buffers */ - struct ath_node *an; - struct ath_atx_ac *ac; - struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ - u16 seq_start; - u16 seq_next; - u16 baw_size; - int tidno; - int baw_head; /* first un-acked tx buffer */ - int baw_tail; /* next unused tx buffer slot */ - int sched; - int paused; - u8 state; - int addba_exchangeattempts; -}; - -/* per access-category aggregate tx state for a destination */ -struct ath_atx_ac { - int sched; /* dest-ac is scheduled */ - int qnum; /* H/W queue number associated - with this AC */ - struct list_head list; /* round-robin txq entry */ - struct list_head tid_q; /* queue of TIDs with buffers */ -}; - -/* per-frame tx control block */ -struct ath_tx_control { - struct ath_txq *txq; - int if_id; -}; - -/* per frame tx status block */ -struct ath_xmit_status { - int retries; /* number of retries to successufully - transmit this frame */ - int flags; /* status of transmit */ -#define ATH_TX_ERROR 0x01 -#define ATH_TX_XRETRY 0x02 -#define ATH_TX_BAR 0x04 -}; - -/* All RSSI values are noise floor adjusted */ -struct ath_tx_stat { - int rssi; - int rssictl[ATH_MAX_ANTENNA]; - int rssiextn[ATH_MAX_ANTENNA]; - int rateieee; - int rateKbps; - int ratecode; - int flags; - u32 airtime; /* time on air per final tx rate */ -}; - -struct aggr_rifs_param { - int param_max_frames; - int param_max_len; - int param_rl; - int param_al; - struct ath_rc_series *param_rcs; -}; - -struct ath_node { - struct ath_softc *an_sc; - struct ath_atx_tid tid[WME_NUM_TID]; - struct ath_atx_ac ac[WME_NUM_AC]; - u16 maxampdu; - u8 mpdudensity; -}; - -struct ath_tx { - u16 seq_no; - u32 txqsetup; - int hwq_map[ATH9K_WME_AC_VO+1]; - spinlock_t txbuflock; - struct list_head txbuf; - struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; - struct ath_descdma txdma; -}; - -struct ath_rx { - u8 defant; - u8 rxotherant; - u32 *rxlink; - int bufsize; - unsigned int rxfilter; - spinlock_t rxflushlock; - spinlock_t rxbuflock; - struct list_head rxbuf; - struct ath_descdma rxdma; -}; - -int ath_startrecv(struct ath_softc *sc); -bool ath_stoprecv(struct ath_softc *sc); -void ath_flushrecv(struct ath_softc *sc); -u32 ath_calcrxfilter(struct ath_softc *sc); -int ath_rx_init(struct ath_softc *sc, int nbufs); -void ath_rx_cleanup(struct ath_softc *sc); -int ath_rx_tasklet(struct ath_softc *sc, int flush); -struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); -void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); -int ath_tx_setup(struct ath_softc *sc, int haltype); -void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); -void ath_draintxq(struct ath_softc *sc, - struct ath_txq *txq, bool retry_tx); -void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); -void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); -void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); -int ath_tx_init(struct ath_softc *sc, int nbufs); -int ath_tx_cleanup(struct ath_softc *sc); -struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); -int ath_txq_update(struct ath_softc *sc, int qnum, - struct ath9k_tx_queue_info *q); -int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb, - struct ath_tx_control *txctl); -void ath_tx_tasklet(struct ath_softc *sc); -void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb); -bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); -int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, - u16 tid, u16 *ssn); -int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); -void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); - -/********/ -/* VAPs */ -/********/ - -/* - * Define the scheme that we select MAC address for multiple - * BSS on the same radio. The very first VAP will just use the MAC - * address from the EEPROM. For the next 3 VAPs, we set the - * U/L bit (bit 1) in MAC address, and use the next two bits as the - * index of the VAP. - */ - -#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ - ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) - -struct ath_vap { - int av_bslot; - enum nl80211_iftype av_opmode; - struct ath_buf *av_bcbuf; - struct ath_tx_control av_btxctl; -}; - -/*******************/ -/* Beacon Handling */ -/*******************/ - -/* - * Regardless of the number of beacons we stagger, (i.e. regardless of the - * number of BSSIDs) if a given beacon does not go out even after waiting this - * number of beacon intervals, the game's up. - */ -#define BSTUCK_THRESH (9 * ATH_BCBUF) -#define ATH_BCBUF 1 -#define ATH_DEFAULT_BINTVAL 100 /* TU */ -#define ATH_DEFAULT_BMISS_LIMIT 10 -#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) - -struct ath_beacon_config { - u16 beacon_interval; - u16 listen_interval; - u16 dtim_period; - u16 bmiss_timeout; - u8 dtim_count; - u8 tim_offset; - union { - u64 last_tsf; - u8 last_tstamp[8]; - } u; /* last received beacon/probe response timestamp of this BSS. */ -}; - -struct ath_beacon { - enum { - OK, /* no change needed */ - UPDATE, /* update pending */ - COMMIT /* beacon sent, commit change */ - } updateslot; /* slot time update fsm */ - - u32 beaconq; - u32 bmisscnt; - u32 ast_be_xmit; - u64 bc_tstamp; - int bslot[ATH_BCBUF]; - int slottime; - int slotupdate; - struct ath9k_tx_queue_info beacon_qi; - struct ath_descdma bdma; - struct ath_txq *cabq; - struct list_head bbuf; -}; - -void ath9k_beacon_tasklet(unsigned long data); -void ath_beacon_config(struct ath_softc *sc, int if_id); -int ath_beaconq_setup(struct ath_hal *ah); -int ath_beacon_alloc(struct ath_softc *sc, int if_id); -void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp); -void ath_beacon_sync(struct ath_softc *sc, int if_id); - -/*******/ -/* ANI */ -/*******/ - -/* ANI values for STA only. - FIXME: Add appropriate values for AP later */ - -#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */ -#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */ -#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */ -#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */ - -struct ath_ani { - bool sc_caldone; - int16_t sc_noise_floor; - unsigned int sc_longcal_timer; - unsigned int sc_shortcal_timer; - unsigned int sc_resetcal_timer; - unsigned int sc_checkani_timer; - struct timer_list timer; -}; - -/********************/ -/* LED Control */ -/********************/ - -#define ATH_LED_PIN 1 -#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ -#define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ - -enum ath_led_type { - ATH_LED_RADIO, - ATH_LED_ASSOC, - ATH_LED_TX, - ATH_LED_RX -}; - -struct ath_led { - struct ath_softc *sc; - struct led_classdev led_cdev; - enum ath_led_type led_type; - char name[32]; - bool registered; -}; - -/* Rfkill */ -#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */ - -struct ath_rfkill { - struct rfkill *rfkill; - struct delayed_work rfkill_poll; - char rfkill_name[32]; -}; - -/********************/ -/* Main driver core */ -/********************/ - -/* - * Default cache line size, in bytes. - * Used when PCI device not fully initialized by bootrom/BIOS -*/ -#define DEFAULT_CACHELINE 32 -#define ATH_DEFAULT_NOISE_FLOOR -95 -#define ATH_REGCLASSIDS_MAX 10 -#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ -#define ATH_MAX_SW_RETRIES 10 -#define ATH_CHAN_MAX 255 -#define IEEE80211_WEP_NKID 4 /* number of key ids */ - -/* - * The key cache is used for h/w cipher state and also for - * tracking station state such as the current tx antenna. - * We also setup a mapping table between key cache slot indices - * and station state to short-circuit node lookups on rx. - * Different parts have different size key caches. We handle - * up to ATH_KEYMAX entries (could dynamically allocate state). - */ -#define ATH_KEYMAX 128 /* max key cache size we handle */ - -#define ATH_IF_ID_ANY 0xff -#define ATH_TXPOWER_MAX 100 /* .5 dBm units */ -#define ATH_RSSI_DUMMY_MARKER 0x127 -#define ATH_RATE_DUMMY_MARKER 0 - -#define SC_OP_INVALID BIT(0) -#define SC_OP_BEACONS BIT(1) -#define SC_OP_RXAGGR BIT(2) -#define SC_OP_TXAGGR BIT(3) -#define SC_OP_CHAINMASK_UPDATE BIT(4) -#define SC_OP_FULL_RESET BIT(5) -#define SC_OP_NO_RESET BIT(6) -#define SC_OP_PREAMBLE_SHORT BIT(7) -#define SC_OP_PROTECT_ENABLE BIT(8) -#define SC_OP_RXFLUSH BIT(9) -#define SC_OP_LED_ASSOCIATED BIT(10) -#define SC_OP_RFKILL_REGISTERED BIT(11) -#define SC_OP_RFKILL_SW_BLOCKED BIT(12) -#define SC_OP_RFKILL_HW_BLOCKED BIT(13) -#define SC_OP_WAIT_FOR_BEACON BIT(14) -#define SC_OP_LED_ON BIT(15) - -struct ath_bus_ops { - void (*read_cachesize)(struct ath_softc *sc, int *csz); - void (*cleanup)(struct ath_softc *sc); - bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data); -}; - -struct ath_softc { - struct ieee80211_hw *hw; - struct device *dev; - struct tasklet_struct intr_tq; - struct tasklet_struct bcon_tasklet; - struct ath_hal *sc_ah; - void __iomem *mem; - int irq; - spinlock_t sc_resetlock; - struct mutex mutex; - - u8 sc_curbssid[ETH_ALEN]; - u8 sc_myaddr[ETH_ALEN]; - u8 sc_bssidmask[ETH_ALEN]; - u32 sc_intrstatus; - u32 sc_flags; /* SC_OP_* */ - u16 sc_curtxpow; - u16 sc_curaid; - u16 sc_cachelsz; - u8 sc_nbcnvaps; - u16 sc_nvaps; - u8 sc_tx_chainmask; - u8 sc_rx_chainmask; - u32 sc_keymax; - DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); - u8 sc_splitmic; - atomic_t ps_usecount; - enum ath9k_int sc_imask; - enum ath9k_ht_extprotspacing sc_ht_extprotspacing; - enum ath9k_ht_macmode tx_chan_width; - - struct ath_config sc_config; - struct ath_rx rx; - struct ath_tx tx; - struct ath_beacon beacon; - struct ieee80211_vif *sc_vaps[ATH_BCBUF]; - struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; - struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; - struct ath_rate_table *cur_rate_table; - struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; - - struct ath_led radio_led; - struct ath_led assoc_led; - struct ath_led tx_led; - struct ath_led rx_led; - struct delayed_work ath_led_blink_work; - int led_on_duration; - int led_off_duration; - int led_on_cnt; - int led_off_cnt; - - struct ath_rfkill rf_kill; - struct ath_ani sc_ani; - struct ath9k_node_stats sc_halstats; -#ifdef CONFIG_ATH9K_DEBUG - struct ath9k_debug sc_debug; -#endif - struct ath_bus_ops *bus_ops; -}; - -int ath_reset(struct ath_softc *sc, bool retry_tx); -int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); -int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); -int ath_cabq_update(struct ath_softc *); - -static inline void ath_read_cachesize(struct ath_softc *sc, int *csz) -{ - sc->bus_ops->read_cachesize(sc, csz); -} - -static inline void ath_bus_cleanup(struct ath_softc *sc) -{ - sc->bus_ops->cleanup(sc); -} - -extern struct ieee80211_ops ath9k_ops; - -irqreturn_t ath_isr(int irq, void *dev); -void ath_cleanup(struct ath_softc *sc); -int ath_attach(u16 devid, struct ath_softc *sc); -void ath_detach(struct ath_softc *sc); -const char *ath_mac_bb_name(u32 mac_bb_version); -const char *ath_rf_name(u16 rf_version); - -#ifdef CONFIG_PCI -int ath_pci_init(void); -void ath_pci_exit(void); -#else -static inline int ath_pci_init(void) { return 0; }; -static inline void ath_pci_exit(void) {}; -#endif - -#ifdef CONFIG_ATHEROS_AR71XX -int ath_ahb_init(void); -void ath_ahb_exit(void); -#else -static inline int ath_ahb_init(void) { return 0; }; -static inline void ath_ahb_exit(void) {}; -#endif - -static inline void ath9k_ps_wakeup(struct ath_softc *sc) -{ - if (atomic_inc_return(&sc->ps_usecount) == 1) - if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) { - sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode; - ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); - } -} - -static inline void ath9k_ps_restore(struct ath_softc *sc) -{ - if (atomic_dec_and_test(&sc->ps_usecount)) - if (sc->hw->conf.flags & IEEE80211_CONF_PS) - ath9k_hw_setpower(sc->sc_ah, - sc->sc_ah->ah_restore_mode); -} -#endif /* CORE_H */ diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c index 2de1b8a..c9b47b3 100644 --- a/drivers/net/wireless/ath9k/debug.c +++ b/drivers/net/wireless/ath9k/debug.c @@ -14,9 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" -#include "reg.h" -#include "hw.h" +#include "ath9k.h" static unsigned int ath9k_debug = DBG_DEFAULT; module_param_named(debug, ath9k_debug, uint, 0); diff --git a/drivers/net/wireless/ath9k/debug.h b/drivers/net/wireless/ath9k/debug.h new file mode 100644 index 0000000..61e9698 --- /dev/null +++ b/drivers/net/wireless/ath9k/debug.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef DEBUG_H +#define DEBUG_H + +enum ATH_DEBUG { + ATH_DBG_RESET = 0x00000001, + ATH_DBG_REG_IO = 0x00000002, + ATH_DBG_QUEUE = 0x00000004, + ATH_DBG_EEPROM = 0x00000008, + ATH_DBG_CALIBRATE = 0x00000010, + ATH_DBG_CHANNEL = 0x00000020, + ATH_DBG_INTERRUPT = 0x00000040, + ATH_DBG_REGULATORY = 0x00000080, + ATH_DBG_ANI = 0x00000100, + ATH_DBG_POWER_MGMT = 0x00000200, + ATH_DBG_XMIT = 0x00000400, + ATH_DBG_BEACON = 0x00001000, + ATH_DBG_CONFIG = 0x00002000, + ATH_DBG_KEYCACHE = 0x00004000, + ATH_DBG_FATAL = 0x00008000, + ATH_DBG_ANY = 0xffffffff +}; + +#define DBG_DEFAULT (ATH_DBG_FATAL) + +#ifdef CONFIG_ATH9K_DEBUG + +/** + * struct ath_interrupt_stats - Contains statistics about interrupts + * @total: Total no. of interrupts generated so far + * @rxok: RX with no errors + * @rxeol: RX with no more RXDESC available + * @rxorn: RX FIFO overrun + * @txok: TX completed at the requested rate + * @txurn: TX FIFO underrun + * @mib: MIB regs reaching its threshold + * @rxphyerr: RX with phy errors + * @rx_keycache_miss: RX with key cache misses + * @swba: Software Beacon Alert + * @bmiss: Beacon Miss + * @bnr: Beacon Not Ready + * @cst: Carrier Sense TImeout + * @gtt: Global TX Timeout + * @tim: RX beacon TIM occurrence + * @cabend: RX End of CAB traffic + * @dtimsync: DTIM sync lossage + * @dtim: RX Beacon with DTIM + */ +struct ath_interrupt_stats { + u32 total; + u32 rxok; + u32 rxeol; + u32 rxorn; + u32 txok; + u32 txeol; + u32 txurn; + u32 mib; + u32 rxphyerr; + u32 rx_keycache_miss; + u32 swba; + u32 bmiss; + u32 bnr; + u32 cst; + u32 gtt; + u32 tim; + u32 cabend; + u32 dtimsync; + u32 dtim; +}; + +struct ath_legacy_rc_stats { + u32 success; +}; + +struct ath_11n_rc_stats { + u32 success; + u32 retries; + u32 xretries; +}; + +struct ath_stats { + struct ath_interrupt_stats istats; + struct ath_legacy_rc_stats legacy_rcstats[12]; /* max(11a,11b,11g) */ + struct ath_11n_rc_stats n_rcstats[16]; /* 0..15 MCS rates */ +}; + +struct ath9k_debug { + int debug_mask; + struct dentry *debugfs_root; + struct dentry *debugfs_phy; + struct dentry *debugfs_dma; + struct dentry *debugfs_interrupt; + struct dentry *debugfs_rcstat; + struct ath_stats stats; +}; + +void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...); +int ath9k_init_debug(struct ath_softc *sc); +void ath9k_exit_debug(struct ath_softc *sc); +void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); +void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb); +void ath_debug_stat_retries(struct ath_softc *sc, int rix, + int xretries, int retries); + +#else + +static inline void DPRINTF(struct ath_softc *sc, int dbg_mask, + const char *fmt, ...) +{ +} + +static inline int ath9k_init_debug(struct ath_softc *sc) +{ + return 0; +} + +static inline void ath9k_exit_debug(struct ath_softc *sc) +{ +} + +static inline void ath_debug_stat_interrupt(struct ath_softc *sc, + enum ath9k_int status) +{ +} + +static inline void ath_debug_stat_rc(struct ath_softc *sc, + struct sk_buff *skb) +{ +} + +static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix, + int xretries, int retries) +{ +} + +#endif /* CONFIG_ATH9K_DEBUG */ + +#endif /* DEBUG_H */ diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 5038907..aa62409 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -14,10 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" -#include "hw.h" -#include "reg.h" -#include "phy.h" +#include "ath9k.h" static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, u32 reg, u32 mask, diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h new file mode 100644 index 0000000..9eb7774 --- /dev/null +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef EEPROM_H +#define EEPROM_H + +#define AH_USE_EEPROM 0x1 + +#ifdef __BIG_ENDIAN +#define AR5416_EEPROM_MAGIC 0x5aa5 +#else +#define AR5416_EEPROM_MAGIC 0xa55a +#endif + +#define CTRY_DEBUG 0x1ff +#define CTRY_DEFAULT 0 + +#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 +#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 +#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 +#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 +#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 +#define AR_EEPROM_EEPCAP_MAXQCU_S 4 +#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 +#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 +#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 + +#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 +#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 +#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 +#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 +#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 +#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 + +#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 +#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 + +#define AR5416_EEPROM_MAGIC_OFFSET 0x0 +#define AR5416_EEPROM_S 2 +#define AR5416_EEPROM_OFFSET 0x2000 +#define AR5416_EEPROM_MAX 0xae0 + +#define AR5416_EEPROM_START_ADDR \ + (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 + +#define SD_NO_CTL 0xE0 +#define NO_CTL 0xff +#define CTL_MODE_M 7 +#define CTL_11A 0 +#define CTL_11B 1 +#define CTL_11G 2 +#define CTL_2GHT20 5 +#define CTL_5GHT20 6 +#define CTL_2GHT40 7 +#define CTL_5GHT40 8 + +#define EXT_ADDITIVE (0x8000) +#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) +#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) +#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) + +#define SUB_NUM_CTL_MODES_AT_5G_40 2 +#define SUB_NUM_CTL_MODES_AT_2G_40 3 + +#define AR_EEPROM_MAC(i) (0x1d+(i)) +#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) +#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) +#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) + +#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c +#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 +#define AR_EEPROM_RFSILENT_POLARITY 0x0002 +#define AR_EEPROM_RFSILENT_POLARITY_S 1 + +#define EEP_RFSILENT_ENABLED 0x0001 +#define EEP_RFSILENT_ENABLED_S 0 +#define EEP_RFSILENT_POLARITY 0x0002 +#define EEP_RFSILENT_POLARITY_S 1 +#define EEP_RFSILENT_GPIO_SEL 0x001c +#define EEP_RFSILENT_GPIO_SEL_S 2 + +#define AR5416_OPFLAGS_11A 0x01 +#define AR5416_OPFLAGS_11G 0x02 +#define AR5416_OPFLAGS_N_5G_HT40 0x04 +#define AR5416_OPFLAGS_N_2G_HT40 0x08 +#define AR5416_OPFLAGS_N_5G_HT20 0x10 +#define AR5416_OPFLAGS_N_2G_HT20 0x20 + +#define AR5416_EEP_NO_BACK_VER 0x1 +#define AR5416_EEP_VER 0xE +#define AR5416_EEP_VER_MINOR_MASK 0x0FFF +#define AR5416_EEP_MINOR_VER_2 0x2 +#define AR5416_EEP_MINOR_VER_3 0x3 +#define AR5416_EEP_MINOR_VER_7 0x7 +#define AR5416_EEP_MINOR_VER_9 0x9 +#define AR5416_EEP_MINOR_VER_16 0x10 +#define AR5416_EEP_MINOR_VER_17 0x11 +#define AR5416_EEP_MINOR_VER_19 0x13 +#define AR5416_EEP_MINOR_VER_20 0x14 + +#define AR5416_NUM_5G_CAL_PIERS 8 +#define AR5416_NUM_2G_CAL_PIERS 4 +#define AR5416_NUM_5G_20_TARGET_POWERS 8 +#define AR5416_NUM_5G_40_TARGET_POWERS 8 +#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 +#define AR5416_NUM_2G_20_TARGET_POWERS 4 +#define AR5416_NUM_2G_40_TARGET_POWERS 4 +#define AR5416_NUM_CTLS 24 +#define AR5416_NUM_BAND_EDGES 8 +#define AR5416_NUM_PD_GAINS 4 +#define AR5416_PD_GAINS_IN_MASK 4 +#define AR5416_PD_GAIN_ICEPTS 5 +#define AR5416_EEPROM_MODAL_SPURS 5 +#define AR5416_MAX_RATE_POWER 63 +#define AR5416_NUM_PDADC_VALUES 128 +#define AR5416_BCHAN_UNUSED 0xFF +#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 +#define AR5416_MAX_CHAINS 3 +#define AR5416_PWR_TABLE_OFFSET -5 + +/* Rx gain type values */ +#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 +#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 +#define AR5416_EEP_RXGAIN_ORIG 2 + +/* Tx gain type values */ +#define AR5416_EEP_TXGAIN_ORIGINAL 0 +#define AR5416_EEP_TXGAIN_HIGH_POWER 1 + +#define AR5416_EEP4K_START_LOC 64 +#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 +#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 +#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 +#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 +#define AR5416_EEP4K_NUM_CTLS 12 +#define AR5416_EEP4K_NUM_BAND_EDGES 4 +#define AR5416_EEP4K_NUM_PD_GAINS 2 +#define AR5416_EEP4K_PD_GAINS_IN_MASK 4 +#define AR5416_EEP4K_PD_GAIN_ICEPTS 5 +#define AR5416_EEP4K_MAX_CHAINS 1 + +enum eeprom_param { + EEP_NFTHRESH_5, + EEP_NFTHRESH_2, + EEP_MAC_MSW, + EEP_MAC_MID, + EEP_MAC_LSW, + EEP_REG_0, + EEP_REG_1, + EEP_OP_CAP, + EEP_OP_MODE, + EEP_RF_SILENT, + EEP_OB_5, + EEP_DB_5, + EEP_OB_2, + EEP_DB_2, + EEP_MINOR_REV, + EEP_TX_MASK, + EEP_RX_MASK, + EEP_RXGAIN_TYPE, + EEP_TXGAIN_TYPE, + EEP_DAC_HPWR_5G, +}; + +enum ar5416_rates { + rate6mb, rate9mb, rate12mb, rate18mb, + rate24mb, rate36mb, rate48mb, rate54mb, + rate1l, rate2l, rate2s, rate5_5l, + rate5_5s, rate11l, rate11s, rateXr, + rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, + rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, + rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, + rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, + rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, + Ar5416RateSize +}; + +enum ath9k_hal_freq_band { + ATH9K_HAL_FREQ_BAND_5GHZ = 0, + ATH9K_HAL_FREQ_BAND_2GHZ = 1 +}; + +struct base_eep_header { + u16 length; + u16 checksum; + u16 version; + u8 opCapFlags; + u8 eepMisc; + u16 regDmn[2]; + u8 macAddr[6]; + u8 rxMask; + u8 txMask; + u16 rfSilent; + u16 blueToothOptions; + u16 deviceCap; + u32 binBuildNumber; + u8 deviceType; + u8 pwdclkind; + u8 futureBase_1[2]; + u8 rxGainType; + u8 dacHiPwrMode_5G; + u8 futureBase_2; + u8 dacLpMode; + u8 txGainType; + u8 rcChainMask; + u8 desiredScaleCCK; + u8 futureBase_3[23]; +} __packed; + +struct base_eep_header_4k { + u16 length; + u16 checksum; + u16 version; + u8 opCapFlags; + u8 eepMisc; + u16 regDmn[2]; + u8 macAddr[6]; + u8 rxMask; + u8 txMask; + u16 rfSilent; + u16 blueToothOptions; + u16 deviceCap; + u32 binBuildNumber; + u8 deviceType; + u8 futureBase[1]; +} __packed; + + +struct spur_chan { + u16 spurChan; + u8 spurRangeLow; + u8 spurRangeHigh; +} __packed; + +struct modal_eep_header { + u32 antCtrlChain[AR5416_MAX_CHAINS]; + u32 antCtrlCommon; + u8 antennaGainCh[AR5416_MAX_CHAINS]; + u8 switchSettling; + u8 txRxAttenCh[AR5416_MAX_CHAINS]; + u8 rxTxMarginCh[AR5416_MAX_CHAINS]; + u8 adcDesiredSize; + u8 pgaDesiredSize; + u8 xlnaGainCh[AR5416_MAX_CHAINS]; + u8 txEndToXpaOff; + u8 txEndToRxOn; + u8 txFrameToXpaOn; + u8 thresh62; + u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; + u8 xpdGain; + u8 xpd; + u8 iqCalICh[AR5416_MAX_CHAINS]; + u8 iqCalQCh[AR5416_MAX_CHAINS]; + u8 pdGainOverlap; + u8 ob; + u8 db; + u8 xpaBiasLvl; + u8 pwrDecreaseFor2Chain; + u8 pwrDecreaseFor3Chain; + u8 txFrameToDataStart; + u8 txFrameToPaOn; + u8 ht40PowerIncForPdadc; + u8 bswAtten[AR5416_MAX_CHAINS]; + u8 bswMargin[AR5416_MAX_CHAINS]; + u8 swSettleHt40; + u8 xatten2Db[AR5416_MAX_CHAINS]; + u8 xatten2Margin[AR5416_MAX_CHAINS]; + u8 ob_ch1; + u8 db_ch1; + u8 useAnt1:1, + force_xpaon:1, + local_bias:1, + femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1; + u8 miscBits; + u16 xpaBiasLvlFreq[3]; + u8 futureModal[6]; + + struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; +} __packed; + +struct modal_eep_4k_header { + u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; + u32 antCtrlCommon; + u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; + u8 switchSettling; + u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; + u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; + u8 adcDesiredSize; + u8 pgaDesiredSize; + u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; + u8 txEndToXpaOff; + u8 txEndToRxOn; + u8 txFrameToXpaOn; + u8 thresh62; + u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; + u8 xpdGain; + u8 xpd; + u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; + u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; + u8 pdGainOverlap; + u8 ob_01; + u8 db1_01; + u8 xpaBiasLvl; + u8 txFrameToDataStart; + u8 txFrameToPaOn; + u8 ht40PowerIncForPdadc; + u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; + u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; + u8 swSettleHt40; + u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; + u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; + u8 db2_01; + u8 version; + u16 ob_234; + u16 db1_234; + u16 db2_234; + u8 futureModal[4]; + + struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; +} __packed; + + +struct cal_data_per_freq { + u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; + u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; +} __packed; + +struct cal_data_per_freq_4k { + u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; + u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; +} __packed; + +struct cal_target_power_leg { + u8 bChannel; + u8 tPow2x[4]; +} __packed; + +struct cal_target_power_ht { + u8 bChannel; + u8 tPow2x[8]; +} __packed; + + +#ifdef __BIG_ENDIAN_BITFIELD +struct cal_ctl_edges { + u8 bChannel; + u8 flag:2, tPower:6; +} __packed; +#else +struct cal_ctl_edges { + u8 bChannel; + u8 tPower:6, flag:2; +} __packed; +#endif + +struct cal_ctl_data { + struct cal_ctl_edges + ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; +} __packed; + +struct cal_ctl_data_4k { + struct cal_ctl_edges + ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; +} __packed; + +struct ar5416_eeprom_def { + struct base_eep_header baseEepHeader; + u8 custData[64]; + struct modal_eep_header modalHeader[2]; + u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; + u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; + struct cal_data_per_freq + calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; + struct cal_data_per_freq + calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; + struct cal_target_power_leg + calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; + struct cal_target_power_leg + calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; + struct cal_target_power_leg + calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; + u8 ctlIndex[AR5416_NUM_CTLS]; + struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; + u8 padding; +} __packed; + +struct ar5416_eeprom_4k { + struct base_eep_header_4k baseEepHeader; + u8 custData[20]; + struct modal_eep_4k_header modalHeader; + u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; + struct cal_data_per_freq_4k + calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; + struct cal_target_power_leg + calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; + struct cal_target_power_leg + calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; + u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; + struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; + u8 padding; +} __packed; + +enum reg_ext_bitmap { + REG_EXT_JAPAN_MIDBAND = 1, + REG_EXT_FCC_DFS_HT40 = 2, + REG_EXT_JAPAN_NONDFS_HT40 = 3, + REG_EXT_JAPAN_DFS_HT40 = 4 +}; + +struct ath9k_country_entry { + u16 countryCode; + u16 regDmnEnum; + u16 regDmn5G; + u16 regDmn2G; + u8 isMultidomain; + u8 iso[3]; +}; + +enum hal_eep_map { + EEP_MAP_DEFAULT = 0x0, + EEP_MAP_4KBITS, + EEP_MAP_MAX +}; + +#define ar5416_get_eep_ver(_ahp) \ + (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep_rev(_ahp) \ + (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) +#define ar5416_get_ntxchains(_txchainmask) \ + (((_txchainmask >> 2) & 1) + \ + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) + +#define ar5416_get_eep4k_ver(_ahp) \ + (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep4k_rev(_ahp) \ + (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) + +int ath9k_hw_set_txpower(struct ath_hal *ah, struct ath9k_channel *chan, + u16 cfgCtl, u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, u8 powerLimit); +void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); +bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, + struct ath9k_channel *chan, int16_t *ratesArray, + u16 cfgCtl, u8 AntennaReduction, + u8 twiceMaxRegulatoryPower, u8 powerLimit); +bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, + struct ath9k_channel *chan, + int16_t *pTxPowerIndexOffset); +bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, + struct ath9k_channel *chan); +u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, + struct ath9k_channel *chan); +u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, + enum ieee80211_band freq_band); +u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); +u32 ath9k_hw_get_eeprom(struct ath_hal *ah, enum eeprom_param param); +int ath9k_hw_eeprom_attach(struct ath_hal *ah); + +#endif /* EEPROM_H */ diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 00ed44a..075ddc5 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -17,10 +17,7 @@ #include #include -#include "core.h" -#include "hw.h" -#include "reg.h" -#include "phy.h" +#include "ath9k.h" #include "initvals.h" static int btcoex_enable; diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 087c571..2b72e75 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -19,337 +19,392 @@ #include #include +#include + +#include "mac.h" +#include "ani.h" +#include "eeprom.h" +#include "calib.h" +#include "regd.h" +#include "reg.h" +#include "phy.h" + +#define ATHEROS_VENDOR_ID 0x168c +#define AR5416_DEVID_PCI 0x0023 +#define AR5416_DEVID_PCIE 0x0024 +#define AR9160_DEVID_PCI 0x0027 +#define AR9280_DEVID_PCI 0x0029 +#define AR9280_DEVID_PCIE 0x002a +#define AR9285_DEVID_PCIE 0x002b +#define AR5416_AR9100_DEVID 0x000b +#define AR_SUBVENDOR_ID_NOG 0x0e11 +#define AR_SUBVENDOR_ID_NEW_A 0x7065 +#define AR5416_MAGIC 0x19641014 + +/* Register read/write primitives */ +#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) +#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) + +#define SM(_v, _f) (((_v) << _f##_S) & _f) +#define MS(_v, _f) (((_v) & _f) >> _f##_S) +#define REG_RMW(_a, _r, _set, _clr) \ + REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) +#define REG_RMW_FIELD(_a, _r, _f, _v) \ + REG_WRITE(_a, _r, \ + (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) +#define REG_SET_BIT(_a, _r, _f) \ + REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) +#define REG_CLR_BIT(_a, _r, _f) \ + REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) -extern const struct hal_percal_data iq_cal_multi_sample; -extern const struct hal_percal_data iq_cal_single_sample; -extern const struct hal_percal_data adc_gain_cal_multi_sample; -extern const struct hal_percal_data adc_gain_cal_single_sample; -extern const struct hal_percal_data adc_dc_cal_multi_sample; -extern const struct hal_percal_data adc_dc_cal_single_sample; -extern const struct hal_percal_data adc_init_dc_cal; - -struct ar5416_desc { - u32 ds_link; - u32 ds_data; - u32 ds_ctl0; - u32 ds_ctl1; - union { - struct { - u32 ctl2; - u32 ctl3; - u32 ctl4; - u32 ctl5; - u32 ctl6; - u32 ctl7; - u32 ctl8; - u32 ctl9; - u32 ctl10; - u32 ctl11; - u32 status0; - u32 status1; - u32 status2; - u32 status3; - u32 status4; - u32 status5; - u32 status6; - u32 status7; - u32 status8; - u32 status9; - } tx; - struct { - u32 status0; - u32 status1; - u32 status2; - u32 status3; - u32 status4; - u32 status5; - u32 status6; - u32 status7; - u32 status8; - } rx; - } u; -} __packed; - -#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) -#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) - -#define ds_ctl2 u.tx.ctl2 -#define ds_ctl3 u.tx.ctl3 -#define ds_ctl4 u.tx.ctl4 -#define ds_ctl5 u.tx.ctl5 -#define ds_ctl6 u.tx.ctl6 -#define ds_ctl7 u.tx.ctl7 -#define ds_ctl8 u.tx.ctl8 -#define ds_ctl9 u.tx.ctl9 -#define ds_ctl10 u.tx.ctl10 -#define ds_ctl11 u.tx.ctl11 - -#define ds_txstatus0 u.tx.status0 -#define ds_txstatus1 u.tx.status1 -#define ds_txstatus2 u.tx.status2 -#define ds_txstatus3 u.tx.status3 -#define ds_txstatus4 u.tx.status4 -#define ds_txstatus5 u.tx.status5 -#define ds_txstatus6 u.tx.status6 -#define ds_txstatus7 u.tx.status7 -#define ds_txstatus8 u.tx.status8 -#define ds_txstatus9 u.tx.status9 - -#define ds_rxstatus0 u.rx.status0 -#define ds_rxstatus1 u.rx.status1 -#define ds_rxstatus2 u.rx.status2 -#define ds_rxstatus3 u.rx.status3 -#define ds_rxstatus4 u.rx.status4 -#define ds_rxstatus5 u.rx.status5 -#define ds_rxstatus6 u.rx.status6 -#define ds_rxstatus7 u.rx.status7 -#define ds_rxstatus8 u.rx.status8 - -#define AR_FrameLen 0x00000fff -#define AR_VirtMoreFrag 0x00001000 -#define AR_TxCtlRsvd00 0x0000e000 -#define AR_XmitPower 0x003f0000 -#define AR_XmitPower_S 16 -#define AR_RTSEnable 0x00400000 -#define AR_VEOL 0x00800000 -#define AR_ClrDestMask 0x01000000 -#define AR_TxCtlRsvd01 0x1e000000 -#define AR_TxIntrReq 0x20000000 -#define AR_DestIdxValid 0x40000000 -#define AR_CTSEnable 0x80000000 - -#define AR_BufLen 0x00000fff -#define AR_TxMore 0x00001000 -#define AR_DestIdx 0x000fe000 -#define AR_DestIdx_S 13 -#define AR_FrameType 0x00f00000 -#define AR_FrameType_S 20 -#define AR_NoAck 0x01000000 -#define AR_InsertTS 0x02000000 -#define AR_CorruptFCS 0x04000000 -#define AR_ExtOnly 0x08000000 -#define AR_ExtAndCtl 0x10000000 -#define AR_MoreAggr 0x20000000 -#define AR_IsAggr 0x40000000 - -#define AR_BurstDur 0x00007fff -#define AR_BurstDur_S 0 -#define AR_DurUpdateEna 0x00008000 -#define AR_XmitDataTries0 0x000f0000 -#define AR_XmitDataTries0_S 16 -#define AR_XmitDataTries1 0x00f00000 -#define AR_XmitDataTries1_S 20 -#define AR_XmitDataTries2 0x0f000000 -#define AR_XmitDataTries2_S 24 -#define AR_XmitDataTries3 0xf0000000 -#define AR_XmitDataTries3_S 28 - -#define AR_XmitRate0 0x000000ff -#define AR_XmitRate0_S 0 -#define AR_XmitRate1 0x0000ff00 -#define AR_XmitRate1_S 8 -#define AR_XmitRate2 0x00ff0000 -#define AR_XmitRate2_S 16 -#define AR_XmitRate3 0xff000000 -#define AR_XmitRate3_S 24 - -#define AR_PacketDur0 0x00007fff -#define AR_PacketDur0_S 0 -#define AR_RTSCTSQual0 0x00008000 -#define AR_PacketDur1 0x7fff0000 -#define AR_PacketDur1_S 16 -#define AR_RTSCTSQual1 0x80000000 - -#define AR_PacketDur2 0x00007fff -#define AR_PacketDur2_S 0 -#define AR_RTSCTSQual2 0x00008000 -#define AR_PacketDur3 0x7fff0000 -#define AR_PacketDur3_S 16 -#define AR_RTSCTSQual3 0x80000000 - -#define AR_AggrLen 0x0000ffff -#define AR_AggrLen_S 0 -#define AR_TxCtlRsvd60 0x00030000 -#define AR_PadDelim 0x03fc0000 -#define AR_PadDelim_S 18 -#define AR_EncrType 0x0c000000 -#define AR_EncrType_S 26 -#define AR_TxCtlRsvd61 0xf0000000 - -#define AR_2040_0 0x00000001 -#define AR_GI0 0x00000002 -#define AR_ChainSel0 0x0000001c -#define AR_ChainSel0_S 2 -#define AR_2040_1 0x00000020 -#define AR_GI1 0x00000040 -#define AR_ChainSel1 0x00000380 -#define AR_ChainSel1_S 7 -#define AR_2040_2 0x00000400 -#define AR_GI2 0x00000800 -#define AR_ChainSel2 0x00007000 -#define AR_ChainSel2_S 12 -#define AR_2040_3 0x00008000 -#define AR_GI3 0x00010000 -#define AR_ChainSel3 0x000e0000 -#define AR_ChainSel3_S 17 -#define AR_RTSCTSRate 0x0ff00000 -#define AR_RTSCTSRate_S 20 -#define AR_TxCtlRsvd70 0xf0000000 - -#define AR_TxRSSIAnt00 0x000000ff -#define AR_TxRSSIAnt00_S 0 -#define AR_TxRSSIAnt01 0x0000ff00 -#define AR_TxRSSIAnt01_S 8 -#define AR_TxRSSIAnt02 0x00ff0000 -#define AR_TxRSSIAnt02_S 16 -#define AR_TxStatusRsvd00 0x3f000000 -#define AR_TxBaStatus 0x40000000 -#define AR_TxStatusRsvd01 0x80000000 - -#define AR_FrmXmitOK 0x00000001 -#define AR_ExcessiveRetries 0x00000002 -#define AR_FIFOUnderrun 0x00000004 -#define AR_Filtered 0x00000008 -#define AR_RTSFailCnt 0x000000f0 -#define AR_RTSFailCnt_S 4 -#define AR_DataFailCnt 0x00000f00 -#define AR_DataFailCnt_S 8 -#define AR_VirtRetryCnt 0x0000f000 -#define AR_VirtRetryCnt_S 12 -#define AR_TxDelimUnderrun 0x00010000 -#define AR_TxDataUnderrun 0x00020000 -#define AR_DescCfgErr 0x00040000 -#define AR_TxTimerExpired 0x00080000 -#define AR_TxStatusRsvd10 0xfff00000 - -#define AR_SendTimestamp ds_txstatus2 -#define AR_BaBitmapLow ds_txstatus3 -#define AR_BaBitmapHigh ds_txstatus4 - -#define AR_TxRSSIAnt10 0x000000ff -#define AR_TxRSSIAnt10_S 0 -#define AR_TxRSSIAnt11 0x0000ff00 -#define AR_TxRSSIAnt11_S 8 -#define AR_TxRSSIAnt12 0x00ff0000 -#define AR_TxRSSIAnt12_S 16 -#define AR_TxRSSICombined 0xff000000 -#define AR_TxRSSICombined_S 24 - -#define AR_TxEVM0 ds_txstatus5 -#define AR_TxEVM1 ds_txstatus6 -#define AR_TxEVM2 ds_txstatus7 - -#define AR_TxDone 0x00000001 -#define AR_SeqNum 0x00001ffe -#define AR_SeqNum_S 1 -#define AR_TxStatusRsvd80 0x0001e000 -#define AR_TxOpExceeded 0x00020000 -#define AR_TxStatusRsvd81 0x001c0000 -#define AR_FinalTxIdx 0x00600000 -#define AR_FinalTxIdx_S 21 -#define AR_TxStatusRsvd82 0x01800000 -#define AR_PowerMgmt 0x02000000 -#define AR_TxStatusRsvd83 0xfc000000 +#define DO_DELAY(x) do { \ + if ((++(x) % 64) == 0) \ + udelay(1); \ + } while (0) -#define AR_RxCTLRsvd00 0xffffffff +#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ + int r; \ + for (r = 0; r < ((iniarray)->ia_rows); r++) { \ + REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ + INI_RA((iniarray), r, (column))); \ + DO_DELAY(regWr); \ + } \ + } while (0) -#define AR_BufLen 0x00000fff -#define AR_RxCtlRsvd00 0x00001000 -#define AR_RxIntrReq 0x00002000 -#define AR_RxCtlRsvd01 0xffffc000 +#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 +#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 +#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 +#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 +#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 +#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 -#define AR_RxRSSIAnt00 0x000000ff -#define AR_RxRSSIAnt00_S 0 -#define AR_RxRSSIAnt01 0x0000ff00 -#define AR_RxRSSIAnt01_S 8 -#define AR_RxRSSIAnt02 0x00ff0000 -#define AR_RxRSSIAnt02_S 16 -#define AR_RxRate 0xff000000 -#define AR_RxRate_S 24 -#define AR_RxStatusRsvd00 0xff000000 +#define AR_GPIOD_MASK 0x00001FFF +#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) -#define AR_DataLen 0x00000fff -#define AR_RxMore 0x00001000 -#define AR_NumDelim 0x003fc000 -#define AR_NumDelim_S 14 -#define AR_RxStatusRsvd10 0xff800000 +#define BASE_ACTIVATE_DELAY 100 +#define RTC_PLL_SETTLE_DELAY 1000 +#define COEF_SCALE_S 24 +#define HT40_CHANNEL_CENTER_SHIFT 10 -#define AR_RcvTimestamp ds_rxstatus2 +#define ATH9K_ANTENNA0_CHAINMASK 0x1 +#define ATH9K_ANTENNA1_CHAINMASK 0x2 + +#define ATH9K_NUM_DMA_DEBUG_REGS 8 +#define ATH9K_NUM_QUEUES 10 + +#define MAX_RATE_POWER 63 +#define AH_TIMEOUT 100000 +#define AH_TIME_QUANTUM 10 +#define AR_KEYTABLE_SIZE 128 +#define POWER_UP_TIME 200000 +#define SPUR_RSSI_THRESH 40 + +#define CAB_TIMEOUT_VAL 10 +#define BEACON_TIMEOUT_VAL 10 +#define MIN_BEACON_TIMEOUT_VAL 1 +#define SLEEP_SLOP 3 + +#define INIT_CONFIG_STATUS 0x00000000 +#define INIT_RSSI_THR 0x00000700 +#define INIT_BCON_CNTRL_REG 0x00000000 + +#define TU_TO_USEC(_tu) ((_tu) << 10) + +enum wireless_mode { + ATH9K_MODE_11A = 0, + ATH9K_MODE_11B = 2, + ATH9K_MODE_11G = 3, + ATH9K_MODE_11NA_HT20 = 6, + ATH9K_MODE_11NG_HT20 = 7, + ATH9K_MODE_11NA_HT40PLUS = 8, + ATH9K_MODE_11NA_HT40MINUS = 9, + ATH9K_MODE_11NG_HT40PLUS = 10, + ATH9K_MODE_11NG_HT40MINUS = 11, + ATH9K_MODE_MAX +}; -#define AR_GI 0x00000001 -#define AR_2040 0x00000002 -#define AR_Parallel40 0x00000004 -#define AR_Parallel40_S 2 -#define AR_RxStatusRsvd30 0x000000f8 -#define AR_RxAntenna 0xffffff00 -#define AR_RxAntenna_S 8 +enum ath9k_hw_caps { + ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), + ATH9K_HW_CAP_MIC_AESCCM = BIT(1), + ATH9K_HW_CAP_MIC_CKIP = BIT(2), + ATH9K_HW_CAP_MIC_TKIP = BIT(3), + ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), + ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), + ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), + ATH9K_HW_CAP_VEOL = BIT(7), + ATH9K_HW_CAP_BSSIDMASK = BIT(8), + ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), + ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), + ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), + ATH9K_HW_CAP_HT = BIT(12), + ATH9K_HW_CAP_GTT = BIT(13), + ATH9K_HW_CAP_FASTCC = BIT(14), + ATH9K_HW_CAP_RFSILENT = BIT(15), + ATH9K_HW_CAP_WOW = BIT(16), + ATH9K_HW_CAP_CST = BIT(17), + ATH9K_HW_CAP_ENHANCEDPM = BIT(18), + ATH9K_HW_CAP_AUTOSLEEP = BIT(19), + ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), + ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), + ATH9K_HW_CAP_BT_COEX = BIT(22) +}; -#define AR_RxRSSIAnt10 0x000000ff -#define AR_RxRSSIAnt10_S 0 -#define AR_RxRSSIAnt11 0x0000ff00 -#define AR_RxRSSIAnt11_S 8 -#define AR_RxRSSIAnt12 0x00ff0000 -#define AR_RxRSSIAnt12_S 16 -#define AR_RxRSSICombined 0xff000000 -#define AR_RxRSSICombined_S 24 +enum ath9k_capability_type { + ATH9K_CAP_CIPHER = 0, + ATH9K_CAP_TKIP_MIC, + ATH9K_CAP_TKIP_SPLIT, + ATH9K_CAP_PHYCOUNTERS, + ATH9K_CAP_DIVERSITY, + ATH9K_CAP_TXPOW, + ATH9K_CAP_PHYDIAG, + ATH9K_CAP_MCAST_KEYSRCH, + ATH9K_CAP_TSF_ADJUST, + ATH9K_CAP_WME_TKIPMIC, + ATH9K_CAP_RFSILENT, + ATH9K_CAP_ANT_CFG_2GHZ, + ATH9K_CAP_ANT_CFG_5GHZ +}; -#define AR_RxEVM0 ds_rxstatus4 -#define AR_RxEVM1 ds_rxstatus5 -#define AR_RxEVM2 ds_rxstatus6 +struct ath9k_hw_capabilities { + u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ + DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ + u16 total_queues; + u16 keycache_size; + u16 low_5ghz_chan, high_5ghz_chan; + u16 low_2ghz_chan, high_2ghz_chan; + u16 num_mr_retries; + u16 rts_aggr_limit; + u8 tx_chainmask; + u8 rx_chainmask; + u16 tx_triglevel_max; + u16 reg_cap; + u8 num_gpio_pins; + u8 num_antcfg_2ghz; + u8 num_antcfg_5ghz; +}; -#define AR_RxDone 0x00000001 -#define AR_RxFrameOK 0x00000002 -#define AR_CRCErr 0x00000004 -#define AR_DecryptCRCErr 0x00000008 -#define AR_PHYErr 0x00000010 -#define AR_MichaelErr 0x00000020 -#define AR_PreDelimCRCErr 0x00000040 -#define AR_RxStatusRsvd70 0x00000080 -#define AR_RxKeyIdxValid 0x00000100 -#define AR_KeyIdx 0x0000fe00 -#define AR_KeyIdx_S 9 -#define AR_PHYErrCode 0x0000ff00 -#define AR_PHYErrCode_S 8 -#define AR_RxMoreAggr 0x00010000 -#define AR_RxAggr 0x00020000 -#define AR_PostDelimCRCErr 0x00040000 -#define AR_RxStatusRsvd71 0x3ff80000 -#define AR_DecryptBusyErr 0x40000000 -#define AR_KeyMiss 0x80000000 +struct ath9k_ops_config { + int dma_beacon_response_time; + int sw_beacon_response_time; + int additional_swba_backoff; + int ack_6mb; + int cwm_ignore_extcca; + u8 pcie_powersave_enable; + u8 pcie_l1skp_enable; + u8 pcie_clock_req; + u32 pcie_waen; + int pcie_power_reset; + u8 pcie_restore; + u8 analog_shiftreg; + u8 ht_enable; + u32 ofdm_trig_low; + u32 ofdm_trig_high; + u32 cck_trig_high; + u32 cck_trig_low; + u32 enable_ani; + u8 noise_immunity_level; + u32 ofdm_weaksignal_det; + u32 cck_weaksignal_thr; + u8 spur_immunity_level; + u8 firstep_level; + int8_t rssi_thr_high; + int8_t rssi_thr_low; + u16 diversity_control; + u16 antenna_switch_swap; + int serialize_regmode; + int intr_mitigation; +#define SPUR_DISABLE 0 +#define SPUR_ENABLE_IOCTL 1 +#define SPUR_ENABLE_EEPROM 2 +#define AR_EEPROM_MODAL_SPURS 5 +#define AR_SPUR_5413_1 1640 +#define AR_SPUR_5413_2 1200 +#define AR_NO_SPUR 0x8000 +#define AR_BASE_FREQ_2GHZ 2300 +#define AR_BASE_FREQ_5GHZ 4900 +#define AR_SPUR_FEEQ_BOUND_HT40 19 +#define AR_SPUR_FEEQ_BOUND_HT20 10 + int spurmode; + u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; +}; -#define AR5416_MAGIC 0x19641014 +enum ath9k_int { + ATH9K_INT_RX = 0x00000001, + ATH9K_INT_RXDESC = 0x00000002, + ATH9K_INT_RXNOFRM = 0x00000008, + ATH9K_INT_RXEOL = 0x00000010, + ATH9K_INT_RXORN = 0x00000020, + ATH9K_INT_TX = 0x00000040, + ATH9K_INT_TXDESC = 0x00000080, + ATH9K_INT_TIM_TIMER = 0x00000100, + ATH9K_INT_TXURN = 0x00000800, + ATH9K_INT_MIB = 0x00001000, + ATH9K_INT_RXPHY = 0x00004000, + ATH9K_INT_RXKCM = 0x00008000, + ATH9K_INT_SWBA = 0x00010000, + ATH9K_INT_BMISS = 0x00040000, + ATH9K_INT_BNR = 0x00100000, + ATH9K_INT_TIM = 0x00200000, + ATH9K_INT_DTIM = 0x00400000, + ATH9K_INT_DTIMSYNC = 0x00800000, + ATH9K_INT_GPIO = 0x01000000, + ATH9K_INT_CABEND = 0x02000000, + ATH9K_INT_CST = 0x10000000, + ATH9K_INT_GTT = 0x20000000, + ATH9K_INT_FATAL = 0x40000000, + ATH9K_INT_GLOBAL = 0x80000000, + ATH9K_INT_BMISC = ATH9K_INT_TIM | + ATH9K_INT_DTIM | + ATH9K_INT_DTIMSYNC | + ATH9K_INT_CABEND, + ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | + ATH9K_INT_RXDESC | + ATH9K_INT_RXEOL | + ATH9K_INT_RXORN | + ATH9K_INT_TXURN | + ATH9K_INT_TXDESC | + ATH9K_INT_MIB | + ATH9K_INT_RXPHY | + ATH9K_INT_RXKCM | + ATH9K_INT_SWBA | + ATH9K_INT_BMISS | + ATH9K_INT_GPIO, + ATH9K_INT_NOCARD = 0xffffffff +}; -#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \ - MS(ads->ds_rxstatus0, AR_RxRate) : \ - (ads->ds_rxstatus3 >> 2) & 0xFF) +#define CHANNEL_CW_INT 0x00002 +#define CHANNEL_CCK 0x00020 +#define CHANNEL_OFDM 0x00040 +#define CHANNEL_2GHZ 0x00080 +#define CHANNEL_5GHZ 0x00100 +#define CHANNEL_PASSIVE 0x00200 +#define CHANNEL_DYN 0x00400 +#define CHANNEL_HALF 0x04000 +#define CHANNEL_QUARTER 0x08000 +#define CHANNEL_HT20 0x10000 +#define CHANNEL_HT40PLUS 0x20000 +#define CHANNEL_HT40MINUS 0x40000 + +#define CHANNEL_INTERFERENCE 0x01 +#define CHANNEL_DFS 0x02 +#define CHANNEL_4MS_LIMIT 0x04 +#define CHANNEL_DFS_CLEAR 0x08 +#define CHANNEL_DISALLOW_ADHOC 0x10 +#define CHANNEL_PER_11D_ADHOC 0x20 + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) +#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) +#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) +#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) +#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) +#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) +#define CHANNEL_ALL \ + (CHANNEL_OFDM| \ + CHANNEL_CCK| \ + CHANNEL_2GHZ | \ + CHANNEL_5GHZ | \ + CHANNEL_HT20 | \ + CHANNEL_HT40PLUS | \ + CHANNEL_HT40MINUS) + +struct ath9k_channel { + struct ieee80211_channel *chan; + u16 channel; + u32 channelFlags; + u32 chanmode; + int32_t CalValid; + bool oneTimeCalsDone; + int8_t iCoff; + int8_t qCoff; + int16_t rawNoiseFloor; +}; -#define set11nTries(_series, _index) \ - (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) +#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ + (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ + (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ + (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) +#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ + (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ + (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ + (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) +#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) +#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) +#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) +#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) +#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) +#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) +#define IS_CHAN_A_5MHZ_SPACED(_c) \ + ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ + (((_c)->channel % 20) != 0) && \ + (((_c)->channel % 10) != 0)) + +/* These macros check chanmode and not channelFlags */ +#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) +#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ + ((_c)->chanmode == CHANNEL_G_HT20)) +#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ + ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ + ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ + ((_c)->chanmode == CHANNEL_G_HT40MINUS)) +#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) + +enum ath9k_power_mode { + ATH9K_PM_AWAKE = 0, + ATH9K_PM_FULL_SLEEP, + ATH9K_PM_NETWORK_SLEEP, + ATH9K_PM_UNDEFINED +}; -#define set11nRate(_series, _index) \ - (SM((_series)[_index].Rate, AR_XmitRate##_index)) +enum ath9k_ant_setting { + ATH9K_ANT_VARIABLE = 0, + ATH9K_ANT_FIXED_A, + ATH9K_ANT_FIXED_B +}; -#define set11nPktDurRTSCTS(_series, _index) \ - (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ - ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ - AR_RTSCTSQual##_index : 0)) +enum ath9k_tp_scale { + ATH9K_TP_SCALE_MAX = 0, + ATH9K_TP_SCALE_50, + ATH9K_TP_SCALE_25, + ATH9K_TP_SCALE_12, + ATH9K_TP_SCALE_MIN +}; -#define set11nRateFlags(_series, _index) \ - (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ - AR_2040_##_index : 0) \ - |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ - AR_GI##_index : 0) \ - |SM((_series)[_index].ChSel, AR_ChainSel##_index)) +enum ser_reg_mode { + SER_REG_MODE_OFF = 0, + SER_REG_MODE_ON = 1, + SER_REG_MODE_AUTO = 2, +}; -#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100) +struct ath9k_beacon_state { + u32 bs_nexttbtt; + u32 bs_nextdtim; + u32 bs_intval; +#define ATH9K_BEACON_PERIOD 0x0000ffff +#define ATH9K_BEACON_ENA 0x00800000 +#define ATH9K_BEACON_RESET_TSF 0x01000000 + u32 bs_dtimperiod; + u16 bs_cfpperiod; + u16 bs_cfpmaxduration; + u32 bs_cfpnext; + u16 bs_timoffset; + u16 bs_bmissthreshold; + u32 bs_sleepduration; +}; -#define INIT_CONFIG_STATUS 0x00000000 -#define INIT_RSSI_THR 0x00000700 -#define INIT_BCON_CNTRL_REG 0x00000000 +struct chan_centers { + u16 synth_center; + u16 ctl_center; + u16 ext_center; +}; -#define MIN_TX_FIFO_THRESHOLD 0x1 -#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) -#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD +enum { + ATH9K_RESET_POWER_ON, + ATH9K_RESET_WARM, + ATH9K_RESET_COLD, +}; struct ar5416AniState { struct ath9k_channel c; @@ -378,447 +433,52 @@ struct ar5416AniState { int16_t cckErrRssi[2]; }; -#define HAL_PROCESS_ANI 0x00000001 -#define DO_ANI(ah) \ - ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) - -struct ar5416Stats { - u32 ast_ani_niup; - u32 ast_ani_nidown; - u32 ast_ani_spurup; - u32 ast_ani_spurdown; - u32 ast_ani_ofdmon; - u32 ast_ani_ofdmoff; - u32 ast_ani_cckhigh; - u32 ast_ani_ccklow; - u32 ast_ani_stepup; - u32 ast_ani_stepdown; - u32 ast_ani_ofdmerrs; - u32 ast_ani_cckerrs; - u32 ast_ani_reset; - u32 ast_ani_lzero; - u32 ast_ani_lneg; - struct ath9k_mib_stats ast_mibstats; - struct ath9k_node_stats ast_nodestats; +struct ath_hal { + u32 ah_magic; + u16 ah_devid; + u16 ah_subvendorid; + u32 ah_macVersion; + u16 ah_macRev; + u16 ah_phyRev; + u16 ah_analog5GhzRev; + u16 ah_analog2GhzRev; + + void __iomem *ah_sh; + struct ath_softc *ah_sc; + + enum nl80211_iftype ah_opmode; + struct ath9k_ops_config ah_config; + struct ath9k_hw_capabilities ah_caps; + + u16 ah_countryCode; + u32 ah_flags; + int16_t ah_powerLimit; + u16 ah_maxPowerLevel; + u32 ah_tpScale; + u16 ah_currentRD; + u16 ah_currentRDExt; + u16 ah_currentRDInUse; + char alpha2[2]; + struct reg_dmn_pair_mapping *regpair; + enum ath9k_power_mode ah_power_mode; + enum ath9k_power_mode ah_restore_mode; + + struct ath9k_channel ah_channels[38]; + struct ath9k_channel *ah_curchan; + + bool ah_isPciExpress; + u16 ah_txTrigLevel; + u16 ah_rfsilent; + u32 ah_rfkill_gpio; + u32 ah_rfkill_polarity; + u32 ah_btactive_gpio; + u32 ah_wlanactive_gpio; + + struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; + + bool sw_mgmt_crypto; }; -#define AR5416_OPFLAGS_11A 0x01 -#define AR5416_OPFLAGS_11G 0x02 -#define AR5416_OPFLAGS_N_5G_HT40 0x04 -#define AR5416_OPFLAGS_N_2G_HT40 0x08 -#define AR5416_OPFLAGS_N_5G_HT20 0x10 -#define AR5416_OPFLAGS_N_2G_HT20 0x20 - -#define EEP_RFSILENT_ENABLED 0x0001 -#define EEP_RFSILENT_ENABLED_S 0 -#define EEP_RFSILENT_POLARITY 0x0002 -#define EEP_RFSILENT_POLARITY_S 1 -#define EEP_RFSILENT_GPIO_SEL 0x001c -#define EEP_RFSILENT_GPIO_SEL_S 2 - -#define AR5416_EEP_NO_BACK_VER 0x1 -#define AR5416_EEP_VER 0xE -#define AR5416_EEP_VER_MINOR_MASK 0x0FFF -#define AR5416_EEP_MINOR_VER_2 0x2 -#define AR5416_EEP_MINOR_VER_3 0x3 -#define AR5416_EEP_MINOR_VER_7 0x7 -#define AR5416_EEP_MINOR_VER_9 0x9 -#define AR5416_EEP_MINOR_VER_16 0x10 -#define AR5416_EEP_MINOR_VER_17 0x11 -#define AR5416_EEP_MINOR_VER_19 0x13 -#define AR5416_EEP_MINOR_VER_20 0x14 - -#define AR5416_NUM_5G_CAL_PIERS 8 -#define AR5416_NUM_2G_CAL_PIERS 4 -#define AR5416_NUM_5G_20_TARGET_POWERS 8 -#define AR5416_NUM_5G_40_TARGET_POWERS 8 -#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 -#define AR5416_NUM_2G_20_TARGET_POWERS 4 -#define AR5416_NUM_2G_40_TARGET_POWERS 4 -#define AR5416_NUM_CTLS 24 -#define AR5416_NUM_BAND_EDGES 8 -#define AR5416_NUM_PD_GAINS 4 -#define AR5416_PD_GAINS_IN_MASK 4 -#define AR5416_PD_GAIN_ICEPTS 5 -#define AR5416_EEPROM_MODAL_SPURS 5 -#define AR5416_MAX_RATE_POWER 63 -#define AR5416_NUM_PDADC_VALUES 128 -#define AR5416_BCHAN_UNUSED 0xFF -#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 -#define AR5416_MAX_CHAINS 3 -#define AR5416_PWR_TABLE_OFFSET -5 - -/* Rx gain type values */ -#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 -#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 -#define AR5416_EEP_RXGAIN_ORIG 2 - -/* Tx gain type values */ -#define AR5416_EEP_TXGAIN_ORIGINAL 0 -#define AR5416_EEP_TXGAIN_HIGH_POWER 1 - -#define AR5416_EEP4K_START_LOC 64 -#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 -#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 -#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 -#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 -#define AR5416_EEP4K_NUM_CTLS 12 -#define AR5416_EEP4K_NUM_BAND_EDGES 4 -#define AR5416_EEP4K_NUM_PD_GAINS 2 -#define AR5416_EEP4K_PD_GAINS_IN_MASK 4 -#define AR5416_EEP4K_PD_GAIN_ICEPTS 5 -#define AR5416_EEP4K_MAX_CHAINS 1 - -enum eeprom_param { - EEP_NFTHRESH_5, - EEP_NFTHRESH_2, - EEP_MAC_MSW, - EEP_MAC_MID, - EEP_MAC_LSW, - EEP_REG_0, - EEP_REG_1, - EEP_OP_CAP, - EEP_OP_MODE, - EEP_RF_SILENT, - EEP_OB_5, - EEP_DB_5, - EEP_OB_2, - EEP_DB_2, - EEP_MINOR_REV, - EEP_TX_MASK, - EEP_RX_MASK, - EEP_RXGAIN_TYPE, - EEP_TXGAIN_TYPE, - EEP_DAC_HPWR_5G, -}; - -enum ar5416_rates { - rate6mb, rate9mb, rate12mb, rate18mb, - rate24mb, rate36mb, rate48mb, rate54mb, - rate1l, rate2l, rate2s, rate5_5l, - rate5_5s, rate11l, rate11s, rateXr, - rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, - rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, - rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, - rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, - rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, - Ar5416RateSize -}; - -enum ath9k_hal_freq_band { - ATH9K_HAL_FREQ_BAND_5GHZ = 0, - ATH9K_HAL_FREQ_BAND_2GHZ = 1 -}; - -struct base_eep_header { - u16 length; - u16 checksum; - u16 version; - u8 opCapFlags; - u8 eepMisc; - u16 regDmn[2]; - u8 macAddr[6]; - u8 rxMask; - u8 txMask; - u16 rfSilent; - u16 blueToothOptions; - u16 deviceCap; - u32 binBuildNumber; - u8 deviceType; - u8 pwdclkind; - u8 futureBase_1[2]; - u8 rxGainType; - u8 dacHiPwrMode_5G; - u8 futureBase_2; - u8 dacLpMode; - u8 txGainType; - u8 rcChainMask; - u8 desiredScaleCCK; - u8 futureBase_3[23]; -} __packed; - -struct base_eep_header_4k { - u16 length; - u16 checksum; - u16 version; - u8 opCapFlags; - u8 eepMisc; - u16 regDmn[2]; - u8 macAddr[6]; - u8 rxMask; - u8 txMask; - u16 rfSilent; - u16 blueToothOptions; - u16 deviceCap; - u32 binBuildNumber; - u8 deviceType; - u8 futureBase[1]; -} __packed; - - -struct spur_chan { - u16 spurChan; - u8 spurRangeLow; - u8 spurRangeHigh; -} __packed; - -struct modal_eep_header { - u32 antCtrlChain[AR5416_MAX_CHAINS]; - u32 antCtrlCommon; - u8 antennaGainCh[AR5416_MAX_CHAINS]; - u8 switchSettling; - u8 txRxAttenCh[AR5416_MAX_CHAINS]; - u8 rxTxMarginCh[AR5416_MAX_CHAINS]; - u8 adcDesiredSize; - u8 pgaDesiredSize; - u8 xlnaGainCh[AR5416_MAX_CHAINS]; - u8 txEndToXpaOff; - u8 txEndToRxOn; - u8 txFrameToXpaOn; - u8 thresh62; - u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; - u8 xpdGain; - u8 xpd; - u8 iqCalICh[AR5416_MAX_CHAINS]; - u8 iqCalQCh[AR5416_MAX_CHAINS]; - u8 pdGainOverlap; - u8 ob; - u8 db; - u8 xpaBiasLvl; - u8 pwrDecreaseFor2Chain; - u8 pwrDecreaseFor3Chain; - u8 txFrameToDataStart; - u8 txFrameToPaOn; - u8 ht40PowerIncForPdadc; - u8 bswAtten[AR5416_MAX_CHAINS]; - u8 bswMargin[AR5416_MAX_CHAINS]; - u8 swSettleHt40; - u8 xatten2Db[AR5416_MAX_CHAINS]; - u8 xatten2Margin[AR5416_MAX_CHAINS]; - u8 ob_ch1; - u8 db_ch1; - u8 useAnt1:1, - force_xpaon:1, - local_bias:1, - femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1; - u8 miscBits; - u16 xpaBiasLvlFreq[3]; - u8 futureModal[6]; - - struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; -} __packed; - -struct modal_eep_4k_header { - u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; - u32 antCtrlCommon; - u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; - u8 switchSettling; - u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; - u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; - u8 adcDesiredSize; - u8 pgaDesiredSize; - u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; - u8 txEndToXpaOff; - u8 txEndToRxOn; - u8 txFrameToXpaOn; - u8 thresh62; - u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; - u8 xpdGain; - u8 xpd; - u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; - u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; - u8 pdGainOverlap; - u8 ob_01; - u8 db1_01; - u8 xpaBiasLvl; - u8 txFrameToDataStart; - u8 txFrameToPaOn; - u8 ht40PowerIncForPdadc; - u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; - u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; - u8 swSettleHt40; - u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; - u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; - u8 db2_01; - u8 version; - u16 ob_234; - u16 db1_234; - u16 db2_234; - u8 futureModal[4]; - - struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; -} __packed; - - -struct cal_data_per_freq { - u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; - u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; -} __packed; - -struct cal_data_per_freq_4k { - u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; - u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; -} __packed; - -struct cal_target_power_leg { - u8 bChannel; - u8 tPow2x[4]; -} __packed; - -struct cal_target_power_ht { - u8 bChannel; - u8 tPow2x[8]; -} __packed; - - -#ifdef __BIG_ENDIAN_BITFIELD -struct cal_ctl_edges { - u8 bChannel; - u8 flag:2, tPower:6; -} __packed; -#else -struct cal_ctl_edges { - u8 bChannel; - u8 tPower:6, flag:2; -} __packed; -#endif - -struct cal_ctl_data { - struct cal_ctl_edges - ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; -} __packed; - -struct cal_ctl_data_4k { - struct cal_ctl_edges - ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; -} __packed; - -struct ar5416_eeprom_def { - struct base_eep_header baseEepHeader; - u8 custData[64]; - struct modal_eep_header modalHeader[2]; - u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; - u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; - struct cal_data_per_freq - calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; - struct cal_data_per_freq - calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; - struct cal_target_power_leg - calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; - struct cal_target_power_ht - calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; - struct cal_target_power_ht - calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; - struct cal_target_power_leg - calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; - struct cal_target_power_leg - calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; - struct cal_target_power_ht - calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; - struct cal_target_power_ht - calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; - u8 ctlIndex[AR5416_NUM_CTLS]; - struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; - u8 padding; -} __packed; - -struct ar5416_eeprom_4k { - struct base_eep_header_4k baseEepHeader; - u8 custData[20]; - struct modal_eep_4k_header modalHeader; - u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; - struct cal_data_per_freq_4k - calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; - struct cal_target_power_leg - calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; - struct cal_target_power_leg - calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; - struct cal_target_power_ht - calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; - struct cal_target_power_ht - calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; - u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; - struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; - u8 padding; -} __packed; - -struct ar5416IniArray { - u32 *ia_array; - u32 ia_rows; - u32 ia_columns; -}; - -#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ - (iniarray)->ia_array = (u32 *)(array); \ - (iniarray)->ia_rows = (rows); \ - (iniarray)->ia_columns = (columns); \ - } while (0) - -#define INI_RA(iniarray, row, column) \ - (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) - -#define INIT_CAL(_perCal) do { \ - (_perCal)->calState = CAL_WAITING; \ - (_perCal)->calNext = NULL; \ - } while (0) - -#define INSERT_CAL(_ahp, _perCal) \ - do { \ - if ((_ahp)->ah_cal_list_last == NULL) { \ - (_ahp)->ah_cal_list = \ - (_ahp)->ah_cal_list_last = (_perCal); \ - ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ - } else { \ - ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ - (_ahp)->ah_cal_list_last = (_perCal); \ - (_perCal)->calNext = (_ahp)->ah_cal_list; \ - } \ - } while (0) - -enum hal_cal_types { - ADC_DC_INIT_CAL = 0x1, - ADC_GAIN_CAL = 0x2, - ADC_DC_CAL = 0x4, - IQ_MISMATCH_CAL = 0x8 -}; - -enum hal_cal_state { - CAL_INACTIVE, - CAL_WAITING, - CAL_RUNNING, - CAL_DONE -}; - -#define MIN_CAL_SAMPLES 1 -#define MAX_CAL_SAMPLES 64 -#define INIT_LOG_COUNT 5 -#define PER_MIN_LOG_COUNT 2 -#define PER_MAX_LOG_COUNT 10 - -struct hal_percal_data { - enum hal_cal_types calType; - u32 calNumSamples; - u32 calCountMax; - void (*calCollect) (struct ath_hal *); - void (*calPostProc) (struct ath_hal *, u8); -}; - -struct hal_cal_list { - const struct hal_percal_data *calData; - enum hal_cal_state calState; - struct hal_cal_list *calNext; -}; - -/* - * Enum to indentify the eeprom mappings - */ -enum hal_eep_map { - EEP_MAP_DEFAULT = 0x0, - EEP_MAP_4KBITS, - EEP_MAP_MAX -}; - - struct ath_hal_5416 { struct ath_hal ah; union { @@ -952,142 +612,85 @@ struct ath_hal_5416 { }; #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) -#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) - -#define ar5416RfDetach(ah) do { \ - if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \ - AH5416(ah)->ah_rfHal.rfDetach(ah); \ - } while (0) - -#define ath9k_hw_use_flash(_ah) \ - (!(_ah->ah_flags & AH_USE_EEPROM)) - - -#define DO_DELAY(x) do { \ - if ((++(x) % 64) == 0) \ - udelay(1); \ - } while (0) - -#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ - int r; \ - for (r = 0; r < ((iniarray)->ia_rows); r++) { \ - REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ - INI_RA((iniarray), r, (column))); \ - DO_DELAY(regWr); \ - } \ - } while (0) - -#define BASE_ACTIVATE_DELAY 100 -#define RTC_PLL_SETTLE_DELAY 1000 -#define COEF_SCALE_S 24 -#define HT40_CHANNEL_CENTER_SHIFT 10 - -#define AR5416_EEPROM_MAGIC_OFFSET 0x0 - -#define AR5416_EEPROM_S 2 -#define AR5416_EEPROM_OFFSET 0x2000 -#define AR5416_EEPROM_START_ADDR \ - (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 -#define AR5416_EEPROM_MAX 0xae0 -#define ar5416_get_eep_ver(_ahp) \ - (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep_rev(_ahp) \ - (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) -#define ar5416_get_ntxchains(_txchainmask) \ - (((_txchainmask >> 2) & 1) + \ - ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) - -/* EEPROM 4K bit map definations */ -#define ar5416_get_eep4k_ver(_ahp) \ - (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep4k_rev(_ahp) \ - (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) - - -#ifdef __BIG_ENDIAN -#define AR5416_EEPROM_MAGIC 0x5aa5 -#else -#define AR5416_EEPROM_MAGIC 0xa55a +/* Attach, Detach, Reset */ +const char *ath9k_hw_probe(u16 vendorid, u16 devid); +void ath9k_hw_detach(struct ath_hal *ah); +struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, + void __iomem *mem, int *error); +void ath9k_hw_rfdetach(struct ath_hal *ah); +int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, + bool bChannelChange); +bool ath9k_hw_fill_cap_info(struct ath_hal *ah); +bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, + u32 capability, u32 *result); +bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, + u32 capability, u32 setting, int *status); + +/* Key Cache Management */ +bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); +bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac); +bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, + const struct ath9k_keyval *k, + const u8 *mac, int xorKey); +bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); + +/* GPIO / RFKILL / Antennae */ +void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); +u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); +void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, + u32 ah_signal_type); +void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); +#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) +void ath9k_enable_rfkill(struct ath_hal *ah); #endif - -#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) - -#define ATH9K_ANTENNA0_CHAINMASK 0x1 -#define ATH9K_ANTENNA1_CHAINMASK 0x2 - -#define ATH9K_NUM_DMA_DEBUG_REGS 8 -#define ATH9K_NUM_QUEUES 10 - -#define HAL_NOISE_IMMUNE_MAX 4 -#define HAL_SPUR_IMMUNE_MAX 7 -#define HAL_FIRST_STEP_MAX 2 - -#define ATH9K_ANI_OFDM_TRIG_HIGH 500 -#define ATH9K_ANI_OFDM_TRIG_LOW 200 -#define ATH9K_ANI_CCK_TRIG_HIGH 200 -#define ATH9K_ANI_CCK_TRIG_LOW 100 -#define ATH9K_ANI_NOISE_IMMUNE_LVL 4 -#define ATH9K_ANI_USE_OFDM_WEAK_SIG true -#define ATH9K_ANI_CCK_WEAK_SIG_THR false -#define ATH9K_ANI_SPUR_IMMUNE_LVL 7 -#define ATH9K_ANI_FIRSTEP_LVL 0 -#define ATH9K_ANI_RSSI_THR_HIGH 40 -#define ATH9K_ANI_RSSI_THR_LOW 7 -#define ATH9K_ANI_PERIOD 100 - -#define AR_GPIOD_MASK 0x00001FFF -#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) - -#define HAL_EP_RND(x, mul) \ - ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) -#define BEACON_RSSI(ahp) \ - HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ - ATH9K_RSSI_EP_MULTIPLIER) - -#define ah_mibStats ah_stats.ast_mibstats - -#define AH_TIMEOUT 100000 -#define AH_TIME_QUANTUM 10 - -#define AR_KEYTABLE_SIZE 128 -#define POWER_UP_TIME 200000 - -#define EXT_ADDITIVE (0x8000) -#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) -#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) -#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) - -#define SUB_NUM_CTL_MODES_AT_5G_40 2 -#define SUB_NUM_CTL_MODES_AT_2G_40 3 -#define SPUR_RSSI_THRESH 40 - -#define TU_TO_USEC(_tu) ((_tu) << 10) - -#define CAB_TIMEOUT_VAL 10 -#define BEACON_TIMEOUT_VAL 10 -#define MIN_BEACON_TIMEOUT_VAL 1 -#define SLEEP_SLOP 3 - -#define CCK_SIFS_TIME 10 -#define CCK_PREAMBLE_BITS 144 -#define CCK_PLCP_BITS 48 - -#define OFDM_SIFS_TIME 16 -#define OFDM_PREAMBLE_TIME 20 -#define OFDM_PLCP_BITS 22 -#define OFDM_SYMBOL_TIME 4 - -#define OFDM_SIFS_TIME_HALF 32 -#define OFDM_PREAMBLE_TIME_HALF 40 -#define OFDM_PLCP_BITS_HALF 22 -#define OFDM_SYMBOL_TIME_HALF 8 - -#define OFDM_SIFS_TIME_QUARTER 64 -#define OFDM_PREAMBLE_TIME_QUARTER 80 -#define OFDM_PLCP_BITS_QUARTER 22 -#define OFDM_SYMBOL_TIME_QUARTER 16 - -u32 ath9k_hw_get_eeprom(struct ath_hal *ah, - enum eeprom_param param); +u32 ath9k_hw_getdefantenna(struct ath_hal *ah); +void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); +bool ath9k_hw_setantennaswitch(struct ath_hal *ah, + enum ath9k_ant_setting settings, + struct ath9k_channel *chan, + u8 *tx_chainmask, u8 *rx_chainmask, + u8 *antenna_cfgd); + +/* General Operation */ +bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); +u32 ath9k_hw_reverse_bits(u32 val, u32 n); +bool ath9k_get_channel_edges(struct ath_hal *ah, u16 flags, u16 *low, u16 *high); +u16 ath9k_hw_computetxtime(struct ath_hal *ah, struct ath_rate_table *rates, + u32 frameLen, u16 rateix, bool shortPreamble); +void ath9k_hw_get_channel_centers(struct ath_hal *ah, + struct ath9k_channel *chan, + struct chan_centers *centers); +u32 ath9k_hw_getrxfilter(struct ath_hal *ah); +void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); +bool ath9k_hw_phy_disable(struct ath_hal *ah); +bool ath9k_hw_disable(struct ath_hal *ah); +bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); +void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac); +bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); +void ath9k_hw_setopmode(struct ath_hal *ah); +void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); +void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask); +bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask); +void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId); +u64 ath9k_hw_gettsf64(struct ath_hal *ah); +void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64); +void ath9k_hw_reset_tsf(struct ath_hal *ah); +bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting); +bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); +void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); +void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period); +void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, + const struct ath9k_beacon_state *bs); +bool ath9k_hw_setpower(struct ath_hal *ah, + enum ath9k_power_mode mode); +void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); + +/* Interrupt Handling */ +bool ath9k_hw_intrpend(struct ath_hal *ah); +bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); +enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); + +void ath9k_hw_btcoex_enable(struct ath_hal *ah); #endif diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index 2427c44..b375a29 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c @@ -14,10 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" -#include "hw.h" -#include "reg.h" -#include "phy.h" +#include "ath9k.h" static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, struct ath9k_tx_queue_info *qi) diff --git a/drivers/net/wireless/ath9k/mac.h b/drivers/net/wireless/ath9k/mac.h new file mode 100644 index 0000000..9012af2 --- /dev/null +++ b/drivers/net/wireless/ath9k/mac.h @@ -0,0 +1,676 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef MAC_H +#define MAC_H + +#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \ + MS(ads->ds_rxstatus0, AR_RxRate) : \ + (ads->ds_rxstatus3 >> 2) & 0xFF) + +#define set11nTries(_series, _index) \ + (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) + +#define set11nRate(_series, _index) \ + (SM((_series)[_index].Rate, AR_XmitRate##_index)) + +#define set11nPktDurRTSCTS(_series, _index) \ + (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ + ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ + AR_RTSCTSQual##_index : 0)) + +#define set11nRateFlags(_series, _index) \ + (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ + AR_2040_##_index : 0) \ + |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ + AR_GI##_index : 0) \ + |SM((_series)[_index].ChSel, AR_ChainSel##_index)) + +#define CCK_SIFS_TIME 10 +#define CCK_PREAMBLE_BITS 144 +#define CCK_PLCP_BITS 48 + +#define OFDM_SIFS_TIME 16 +#define OFDM_PREAMBLE_TIME 20 +#define OFDM_PLCP_BITS 22 +#define OFDM_SYMBOL_TIME 4 + +#define OFDM_SIFS_TIME_HALF 32 +#define OFDM_PREAMBLE_TIME_HALF 40 +#define OFDM_PLCP_BITS_HALF 22 +#define OFDM_SYMBOL_TIME_HALF 8 + +#define OFDM_SIFS_TIME_QUARTER 64 +#define OFDM_PREAMBLE_TIME_QUARTER 80 +#define OFDM_PLCP_BITS_QUARTER 22 +#define OFDM_SYMBOL_TIME_QUARTER 16 + +#define INIT_AIFS 2 +#define INIT_CWMIN 15 +#define INIT_CWMIN_11B 31 +#define INIT_CWMAX 1023 +#define INIT_SH_RETRY 10 +#define INIT_LG_RETRY 10 +#define INIT_SSH_RETRY 32 +#define INIT_SLG_RETRY 32 + +#define ATH9K_SLOT_TIME_6 6 +#define ATH9K_SLOT_TIME_9 9 +#define ATH9K_SLOT_TIME_20 20 + +#define ATH9K_TXERR_XRETRY 0x01 +#define ATH9K_TXERR_FILT 0x02 +#define ATH9K_TXERR_FIFO 0x04 +#define ATH9K_TXERR_XTXOP 0x08 +#define ATH9K_TXERR_TIMER_EXPIRED 0x10 + +#define ATH9K_TX_BA 0x01 +#define ATH9K_TX_PWRMGMT 0x02 +#define ATH9K_TX_DESC_CFG_ERR 0x04 +#define ATH9K_TX_DATA_UNDERRUN 0x08 +#define ATH9K_TX_DELIM_UNDERRUN 0x10 +#define ATH9K_TX_SW_ABORTED 0x40 +#define ATH9K_TX_SW_FILTERED 0x80 + +#define MIN_TX_FIFO_THRESHOLD 0x1 +#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) +#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD + +struct ath_tx_status { + u32 ts_tstamp; + u16 ts_seqnum; + u8 ts_status; + u8 ts_ratecode; + u8 ts_rateindex; + int8_t ts_rssi; + u8 ts_shortretry; + u8 ts_longretry; + u8 ts_virtcol; + u8 ts_antenna; + u8 ts_flags; + int8_t ts_rssi_ctl0; + int8_t ts_rssi_ctl1; + int8_t ts_rssi_ctl2; + int8_t ts_rssi_ext0; + int8_t ts_rssi_ext1; + int8_t ts_rssi_ext2; + u8 pad[3]; + u32 ba_low; + u32 ba_high; + u32 evm0; + u32 evm1; + u32 evm2; +}; + +struct ath_rx_status { + u32 rs_tstamp; + u16 rs_datalen; + u8 rs_status; + u8 rs_phyerr; + int8_t rs_rssi; + u8 rs_keyix; + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; + int8_t rs_rssi_ctl0; + int8_t rs_rssi_ctl1; + int8_t rs_rssi_ctl2; + int8_t rs_rssi_ext0; + int8_t rs_rssi_ext1; + int8_t rs_rssi_ext2; + u8 rs_isaggr; + u8 rs_moreaggr; + u8 rs_num_delims; + u8 rs_flags; + u32 evm0; + u32 evm1; + u32 evm2; +}; + +#define ATH9K_RXERR_CRC 0x01 +#define ATH9K_RXERR_PHY 0x02 +#define ATH9K_RXERR_FIFO 0x04 +#define ATH9K_RXERR_DECRYPT 0x08 +#define ATH9K_RXERR_MIC 0x10 + +#define ATH9K_RX_MORE 0x01 +#define ATH9K_RX_MORE_AGGR 0x02 +#define ATH9K_RX_GI 0x04 +#define ATH9K_RX_2040 0x08 +#define ATH9K_RX_DELIM_CRC_PRE 0x10 +#define ATH9K_RX_DELIM_CRC_POST 0x20 +#define ATH9K_RX_DECRYPT_BUSY 0x40 + +#define ATH9K_RXKEYIX_INVALID ((u8)-1) +#define ATH9K_TXKEYIX_INVALID ((u32)-1) + +struct ath_desc { + u32 ds_link; + u32 ds_data; + u32 ds_ctl0; + u32 ds_ctl1; + u32 ds_hw[20]; + union { + struct ath_tx_status tx; + struct ath_rx_status rx; + void *stats; + } ds_us; + void *ds_vdata; +} __packed; + +#define ds_txstat ds_us.tx +#define ds_rxstat ds_us.rx +#define ds_stat ds_us.stats + +#define ATH9K_TXDESC_CLRDMASK 0x0001 +#define ATH9K_TXDESC_NOACK 0x0002 +#define ATH9K_TXDESC_RTSENA 0x0004 +#define ATH9K_TXDESC_CTSENA 0x0008 +/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for + * the descriptor its marked on. We take a tx interrupt to reap + * descriptors when the h/w hits an EOL condition or + * when the descriptor is specifically marked to generate + * an interrupt with this flag. Descriptors should be + * marked periodically to insure timely replenishing of the + * supply needed for sending frames. Defering interrupts + * reduces system load and potentially allows more concurrent + * work to be done but if done to aggressively can cause + * senders to backup. When the hardware queue is left too + * large rate control information may also be too out of + * date. An Alternative for this is TX interrupt mitigation + * but this needs more testing. */ +#define ATH9K_TXDESC_INTREQ 0x0010 +#define ATH9K_TXDESC_VEOL 0x0020 +#define ATH9K_TXDESC_EXT_ONLY 0x0040 +#define ATH9K_TXDESC_EXT_AND_CTL 0x0080 +#define ATH9K_TXDESC_VMF 0x0100 +#define ATH9K_TXDESC_FRAG_IS_ON 0x0200 +#define ATH9K_TXDESC_CAB 0x0400 + +#define ATH9K_RXDESC_INTREQ 0x0020 + +struct ar5416_desc { + u32 ds_link; + u32 ds_data; + u32 ds_ctl0; + u32 ds_ctl1; + union { + struct { + u32 ctl2; + u32 ctl3; + u32 ctl4; + u32 ctl5; + u32 ctl6; + u32 ctl7; + u32 ctl8; + u32 ctl9; + u32 ctl10; + u32 ctl11; + u32 status0; + u32 status1; + u32 status2; + u32 status3; + u32 status4; + u32 status5; + u32 status6; + u32 status7; + u32 status8; + u32 status9; + } tx; + struct { + u32 status0; + u32 status1; + u32 status2; + u32 status3; + u32 status4; + u32 status5; + u32 status6; + u32 status7; + u32 status8; + } rx; + } u; +} __packed; + +#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) +#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) + +#define ds_ctl2 u.tx.ctl2 +#define ds_ctl3 u.tx.ctl3 +#define ds_ctl4 u.tx.ctl4 +#define ds_ctl5 u.tx.ctl5 +#define ds_ctl6 u.tx.ctl6 +#define ds_ctl7 u.tx.ctl7 +#define ds_ctl8 u.tx.ctl8 +#define ds_ctl9 u.tx.ctl9 +#define ds_ctl10 u.tx.ctl10 +#define ds_ctl11 u.tx.ctl11 + +#define ds_txstatus0 u.tx.status0 +#define ds_txstatus1 u.tx.status1 +#define ds_txstatus2 u.tx.status2 +#define ds_txstatus3 u.tx.status3 +#define ds_txstatus4 u.tx.status4 +#define ds_txstatus5 u.tx.status5 +#define ds_txstatus6 u.tx.status6 +#define ds_txstatus7 u.tx.status7 +#define ds_txstatus8 u.tx.status8 +#define ds_txstatus9 u.tx.status9 + +#define ds_rxstatus0 u.rx.status0 +#define ds_rxstatus1 u.rx.status1 +#define ds_rxstatus2 u.rx.status2 +#define ds_rxstatus3 u.rx.status3 +#define ds_rxstatus4 u.rx.status4 +#define ds_rxstatus5 u.rx.status5 +#define ds_rxstatus6 u.rx.status6 +#define ds_rxstatus7 u.rx.status7 +#define ds_rxstatus8 u.rx.status8 + +#define AR_FrameLen 0x00000fff +#define AR_VirtMoreFrag 0x00001000 +#define AR_TxCtlRsvd00 0x0000e000 +#define AR_XmitPower 0x003f0000 +#define AR_XmitPower_S 16 +#define AR_RTSEnable 0x00400000 +#define AR_VEOL 0x00800000 +#define AR_ClrDestMask 0x01000000 +#define AR_TxCtlRsvd01 0x1e000000 +#define AR_TxIntrReq 0x20000000 +#define AR_DestIdxValid 0x40000000 +#define AR_CTSEnable 0x80000000 + +#define AR_BufLen 0x00000fff +#define AR_TxMore 0x00001000 +#define AR_DestIdx 0x000fe000 +#define AR_DestIdx_S 13 +#define AR_FrameType 0x00f00000 +#define AR_FrameType_S 20 +#define AR_NoAck 0x01000000 +#define AR_InsertTS 0x02000000 +#define AR_CorruptFCS 0x04000000 +#define AR_ExtOnly 0x08000000 +#define AR_ExtAndCtl 0x10000000 +#define AR_MoreAggr 0x20000000 +#define AR_IsAggr 0x40000000 + +#define AR_BurstDur 0x00007fff +#define AR_BurstDur_S 0 +#define AR_DurUpdateEna 0x00008000 +#define AR_XmitDataTries0 0x000f0000 +#define AR_XmitDataTries0_S 16 +#define AR_XmitDataTries1 0x00f00000 +#define AR_XmitDataTries1_S 20 +#define AR_XmitDataTries2 0x0f000000 +#define AR_XmitDataTries2_S 24 +#define AR_XmitDataTries3 0xf0000000 +#define AR_XmitDataTries3_S 28 + +#define AR_XmitRate0 0x000000ff +#define AR_XmitRate0_S 0 +#define AR_XmitRate1 0x0000ff00 +#define AR_XmitRate1_S 8 +#define AR_XmitRate2 0x00ff0000 +#define AR_XmitRate2_S 16 +#define AR_XmitRate3 0xff000000 +#define AR_XmitRate3_S 24 + +#define AR_PacketDur0 0x00007fff +#define AR_PacketDur0_S 0 +#define AR_RTSCTSQual0 0x00008000 +#define AR_PacketDur1 0x7fff0000 +#define AR_PacketDur1_S 16 +#define AR_RTSCTSQual1 0x80000000 + +#define AR_PacketDur2 0x00007fff +#define AR_PacketDur2_S 0 +#define AR_RTSCTSQual2 0x00008000 +#define AR_PacketDur3 0x7fff0000 +#define AR_PacketDur3_S 16 +#define AR_RTSCTSQual3 0x80000000 + +#define AR_AggrLen 0x0000ffff +#define AR_AggrLen_S 0 +#define AR_TxCtlRsvd60 0x00030000 +#define AR_PadDelim 0x03fc0000 +#define AR_PadDelim_S 18 +#define AR_EncrType 0x0c000000 +#define AR_EncrType_S 26 +#define AR_TxCtlRsvd61 0xf0000000 + +#define AR_2040_0 0x00000001 +#define AR_GI0 0x00000002 +#define AR_ChainSel0 0x0000001c +#define AR_ChainSel0_S 2 +#define AR_2040_1 0x00000020 +#define AR_GI1 0x00000040 +#define AR_ChainSel1 0x00000380 +#define AR_ChainSel1_S 7 +#define AR_2040_2 0x00000400 +#define AR_GI2 0x00000800 +#define AR_ChainSel2 0x00007000 +#define AR_ChainSel2_S 12 +#define AR_2040_3 0x00008000 +#define AR_GI3 0x00010000 +#define AR_ChainSel3 0x000e0000 +#define AR_ChainSel3_S 17 +#define AR_RTSCTSRate 0x0ff00000 +#define AR_RTSCTSRate_S 20 +#define AR_TxCtlRsvd70 0xf0000000 + +#define AR_TxRSSIAnt00 0x000000ff +#define AR_TxRSSIAnt00_S 0 +#define AR_TxRSSIAnt01 0x0000ff00 +#define AR_TxRSSIAnt01_S 8 +#define AR_TxRSSIAnt02 0x00ff0000 +#define AR_TxRSSIAnt02_S 16 +#define AR_TxStatusRsvd00 0x3f000000 +#define AR_TxBaStatus 0x40000000 +#define AR_TxStatusRsvd01 0x80000000 + +#define AR_FrmXmitOK 0x00000001 +#define AR_ExcessiveRetries 0x00000002 +#define AR_FIFOUnderrun 0x00000004 +#define AR_Filtered 0x00000008 +#define AR_RTSFailCnt 0x000000f0 +#define AR_RTSFailCnt_S 4 +#define AR_DataFailCnt 0x00000f00 +#define AR_DataFailCnt_S 8 +#define AR_VirtRetryCnt 0x0000f000 +#define AR_VirtRetryCnt_S 12 +#define AR_TxDelimUnderrun 0x00010000 +#define AR_TxDataUnderrun 0x00020000 +#define AR_DescCfgErr 0x00040000 +#define AR_TxTimerExpired 0x00080000 +#define AR_TxStatusRsvd10 0xfff00000 + +#define AR_SendTimestamp ds_txstatus2 +#define AR_BaBitmapLow ds_txstatus3 +#define AR_BaBitmapHigh ds_txstatus4 + +#define AR_TxRSSIAnt10 0x000000ff +#define AR_TxRSSIAnt10_S 0 +#define AR_TxRSSIAnt11 0x0000ff00 +#define AR_TxRSSIAnt11_S 8 +#define AR_TxRSSIAnt12 0x00ff0000 +#define AR_TxRSSIAnt12_S 16 +#define AR_TxRSSICombined 0xff000000 +#define AR_TxRSSICombined_S 24 + +#define AR_TxEVM0 ds_txstatus5 +#define AR_TxEVM1 ds_txstatus6 +#define AR_TxEVM2 ds_txstatus7 + +#define AR_TxDone 0x00000001 +#define AR_SeqNum 0x00001ffe +#define AR_SeqNum_S 1 +#define AR_TxStatusRsvd80 0x0001e000 +#define AR_TxOpExceeded 0x00020000 +#define AR_TxStatusRsvd81 0x001c0000 +#define AR_FinalTxIdx 0x00600000 +#define AR_FinalTxIdx_S 21 +#define AR_TxStatusRsvd82 0x01800000 +#define AR_PowerMgmt 0x02000000 +#define AR_TxStatusRsvd83 0xfc000000 + +#define AR_RxCTLRsvd00 0xffffffff + +#define AR_BufLen 0x00000fff +#define AR_RxCtlRsvd00 0x00001000 +#define AR_RxIntrReq 0x00002000 +#define AR_RxCtlRsvd01 0xffffc000 + +#define AR_RxRSSIAnt00 0x000000ff +#define AR_RxRSSIAnt00_S 0 +#define AR_RxRSSIAnt01 0x0000ff00 +#define AR_RxRSSIAnt01_S 8 +#define AR_RxRSSIAnt02 0x00ff0000 +#define AR_RxRSSIAnt02_S 16 +#define AR_RxRate 0xff000000 +#define AR_RxRate_S 24 +#define AR_RxStatusRsvd00 0xff000000 + +#define AR_DataLen 0x00000fff +#define AR_RxMore 0x00001000 +#define AR_NumDelim 0x003fc000 +#define AR_NumDelim_S 14 +#define AR_RxStatusRsvd10 0xff800000 + +#define AR_RcvTimestamp ds_rxstatus2 + +#define AR_GI 0x00000001 +#define AR_2040 0x00000002 +#define AR_Parallel40 0x00000004 +#define AR_Parallel40_S 2 +#define AR_RxStatusRsvd30 0x000000f8 +#define AR_RxAntenna 0xffffff00 +#define AR_RxAntenna_S 8 + +#define AR_RxRSSIAnt10 0x000000ff +#define AR_RxRSSIAnt10_S 0 +#define AR_RxRSSIAnt11 0x0000ff00 +#define AR_RxRSSIAnt11_S 8 +#define AR_RxRSSIAnt12 0x00ff0000 +#define AR_RxRSSIAnt12_S 16 +#define AR_RxRSSICombined 0xff000000 +#define AR_RxRSSICombined_S 24 + +#define AR_RxEVM0 ds_rxstatus4 +#define AR_RxEVM1 ds_rxstatus5 +#define AR_RxEVM2 ds_rxstatus6 + +#define AR_RxDone 0x00000001 +#define AR_RxFrameOK 0x00000002 +#define AR_CRCErr 0x00000004 +#define AR_DecryptCRCErr 0x00000008 +#define AR_PHYErr 0x00000010 +#define AR_MichaelErr 0x00000020 +#define AR_PreDelimCRCErr 0x00000040 +#define AR_RxStatusRsvd70 0x00000080 +#define AR_RxKeyIdxValid 0x00000100 +#define AR_KeyIdx 0x0000fe00 +#define AR_KeyIdx_S 9 +#define AR_PHYErrCode 0x0000ff00 +#define AR_PHYErrCode_S 8 +#define AR_RxMoreAggr 0x00010000 +#define AR_RxAggr 0x00020000 +#define AR_PostDelimCRCErr 0x00040000 +#define AR_RxStatusRsvd71 0x3ff80000 +#define AR_DecryptBusyErr 0x40000000 +#define AR_KeyMiss 0x80000000 + +enum ath9k_tx_queue { + ATH9K_TX_QUEUE_INACTIVE = 0, + ATH9K_TX_QUEUE_DATA, + ATH9K_TX_QUEUE_BEACON, + ATH9K_TX_QUEUE_CAB, + ATH9K_TX_QUEUE_UAPSD, + ATH9K_TX_QUEUE_PSPOLL +}; + +#define ATH9K_NUM_TX_QUEUES 10 + +enum ath9k_tx_queue_subtype { + ATH9K_WME_AC_BK = 0, + ATH9K_WME_AC_BE, + ATH9K_WME_AC_VI, + ATH9K_WME_AC_VO, + ATH9K_WME_UPSD +}; + +enum ath9k_tx_queue_flags { + TXQ_FLAG_TXOKINT_ENABLE = 0x0001, + TXQ_FLAG_TXERRINT_ENABLE = 0x0001, + TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, + TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, + TXQ_FLAG_TXURNINT_ENABLE = 0x0008, + TXQ_FLAG_BACKOFF_DISABLE = 0x0010, + TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, + TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, + TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, +}; + +#define ATH9K_TXQ_USEDEFAULT ((u32) -1) +#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 + +#define ATH9K_DECOMP_MASK_SIZE 128 +#define ATH9K_READY_TIME_LO_BOUND 50 +#define ATH9K_READY_TIME_HI_BOUND 96 + +enum ath9k_pkt_type { + ATH9K_PKT_TYPE_NORMAL = 0, + ATH9K_PKT_TYPE_ATIM, + ATH9K_PKT_TYPE_PSPOLL, + ATH9K_PKT_TYPE_BEACON, + ATH9K_PKT_TYPE_PROBE_RESP, + ATH9K_PKT_TYPE_CHIRP, + ATH9K_PKT_TYPE_GRP_POLL, +}; + +struct ath9k_tx_queue_info { + u32 tqi_ver; + enum ath9k_tx_queue tqi_type; + enum ath9k_tx_queue_subtype tqi_subtype; + enum ath9k_tx_queue_flags tqi_qflags; + u32 tqi_priority; + u32 tqi_aifs; + u32 tqi_cwmin; + u32 tqi_cwmax; + u16 tqi_shretry; + u16 tqi_lgretry; + u32 tqi_cbrPeriod; + u32 tqi_cbrOverflowLimit; + u32 tqi_burstTime; + u32 tqi_readyTime; + u32 tqi_physCompBuf; + u32 tqi_intFlags; +}; + +enum ath9k_rx_filter { + ATH9K_RX_FILTER_UCAST = 0x00000001, + ATH9K_RX_FILTER_MCAST = 0x00000002, + ATH9K_RX_FILTER_BCAST = 0x00000004, + ATH9K_RX_FILTER_CONTROL = 0x00000008, + ATH9K_RX_FILTER_BEACON = 0x00000010, + ATH9K_RX_FILTER_PROM = 0x00000020, + ATH9K_RX_FILTER_PROBEREQ = 0x00000080, + ATH9K_RX_FILTER_PSPOLL = 0x00004000, + ATH9K_RX_FILTER_PHYERR = 0x00000100, + ATH9K_RX_FILTER_PHYRADAR = 0x00002000, +}; + +#define ATH9K_RATESERIES_RTS_CTS 0x0001 +#define ATH9K_RATESERIES_2040 0x0002 +#define ATH9K_RATESERIES_HALFGI 0x0004 + +struct ath9k_11n_rate_series { + u32 Tries; + u32 Rate; + u32 PktDuration; + u32 ChSel; + u32 RateFlags; +}; + +struct ath9k_keyval { + u8 kv_type; + u8 kv_pad; + u16 kv_len; + u8 kv_val[16]; + u8 kv_mic[8]; + u8 kv_txmic[8]; +}; + +enum ath9k_key_type { + ATH9K_KEY_TYPE_CLEAR, + ATH9K_KEY_TYPE_WEP, + ATH9K_KEY_TYPE_AES, + ATH9K_KEY_TYPE_TKIP, +}; + +enum ath9k_cipher { + ATH9K_CIPHER_WEP = 0, + ATH9K_CIPHER_AES_OCB = 1, + ATH9K_CIPHER_AES_CCM = 2, + ATH9K_CIPHER_CKIP = 3, + ATH9K_CIPHER_TKIP = 4, + ATH9K_CIPHER_CLR = 5, + ATH9K_CIPHER_MIC = 127 +}; + +enum ath9k_ht_macmode { + ATH9K_HT_MACMODE_20 = 0, + ATH9K_HT_MACMODE_2040 = 1, +}; + +enum ath9k_ht_extprotspacing { + ATH9K_HT_EXTPROTSPACING_20 = 0, + ATH9K_HT_EXTPROTSPACING_25 = 1, +}; + +struct ath_hal; +struct ath9k_channel; +struct ath_rate_table; + +u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); +bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp); +bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); +u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); +bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel); +bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); +bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, + u32 segLen, bool firstSeg, + bool lastSeg, const struct ath_desc *ds0); +void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); +int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); +void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, + u32 pktLen, enum ath9k_pkt_type type, u32 txPower, + u32 keyIx, enum ath9k_key_type keyType, u32 flags); +void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, + struct ath_desc *lastds, + u32 durUpdateEn, u32 rtsctsRate, + u32 rtsctsDuration, + struct ath9k_11n_rate_series series[], + u32 nseries, u32 flags); +void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, + u32 aggrLen); +void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, + u32 numDelims); +void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); +void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); +void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, + u32 burstDuration); +void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, + u32 vmf); +void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); +bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, + const struct ath9k_tx_queue_info *qinfo); +bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, + struct ath9k_tx_queue_info *qinfo); +int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, + const struct ath9k_tx_queue_info *qinfo); +bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); +bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); +int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, + u32 pa, struct ath_desc *nds, u64 tsf); +bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, + u32 size, u32 flags); +bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); +void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); +void ath9k_hw_rxena(struct ath_hal *ah); +void ath9k_hw_startpcureceive(struct ath_hal *ah); +void ath9k_hw_stoppcurecv(struct ath_hal *ah); +bool ath9k_hw_stopdmarecv(struct ath_hal *ah); + +#endif /* MAC_H */ diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index 4095fec..2ed0bd2 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -15,9 +15,7 @@ */ #include -#include "core.h" -#include "reg.h" -#include "hw.h" +#include "ath9k.h" #define ATH_PCI_VERSION "0.1" diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index 05612bf..aa3ac20 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -16,9 +16,7 @@ #include #include -#include "core.h" -#include "reg.h" -#include "hw.h" +#include "ath9k.h" static struct pci_device_id ath_pci_id_table[] __devinitdata = { { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index 766982a..ea29941 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -14,10 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" -#include "hw.h" -#include "reg.h" -#include "phy.h" +#include "ath9k.h" void ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex, diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c index 69a4ca4..060a7cf 100644 --- a/drivers/net/wireless/ath9k/rc.c +++ b/drivers/net/wireless/ath9k/rc.c @@ -15,7 +15,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" +#include "ath9k.h" static struct ath_rate_table ar5416_11na_ratetable = { 42, diff --git a/drivers/net/wireless/ath9k/rc.h b/drivers/net/wireless/ath9k/rc.h index a987cb9..d688ec5 100644 --- a/drivers/net/wireless/ath9k/rc.h +++ b/drivers/net/wireless/ath9k/rc.h @@ -19,13 +19,12 @@ #ifndef RC_H #define RC_H -#include "ath9k.h" - struct ath_softc; #define ATH_RATE_MAX 30 #define RATE_TABLE_SIZE 64 #define MAX_TX_RATE_PHY 48 +#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* VALID_ALL - valid for 20/40/Legacy, * VALID - Legacy only, @@ -39,6 +38,20 @@ struct ath_softc; #define VALID_2040 (VALID_20|VALID_40) #define VALID_ALL (VALID_2040|VALID) +enum { + WLAN_RC_PHY_OFDM, + WLAN_RC_PHY_CCK, + WLAN_RC_PHY_HT_20_SS, + WLAN_RC_PHY_HT_20_DS, + WLAN_RC_PHY_HT_40_SS, + WLAN_RC_PHY_HT_40_DS, + WLAN_RC_PHY_HT_20_SS_HGI, + WLAN_RC_PHY_HT_20_DS_HGI, + WLAN_RC_PHY_HT_40_SS_HGI, + WLAN_RC_PHY_HT_40_DS_HGI, + WLAN_RC_PHY_MAX +}; + #define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \ || (_phy == WLAN_RC_PHY_HT_40_DS) \ || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index 630fa57..69dd5e2 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -14,7 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" +#include "ath9k.h" /* * Setup and link descriptors. diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h index c967b79..45b9fbf 100644 --- a/drivers/net/wireless/ath9k/reg.h +++ b/drivers/net/wireless/ath9k/reg.h @@ -160,6 +160,7 @@ #define AR_SREV_VERSION_9100 0x014 +#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100) #define AR_SREV_5416_V20_OR_LATER(_ah) \ (AR_SREV_9100((_ah)) || AR_SREV_5416_20_OR_LATER(_ah)) #define AR_SREV_5416_V22_OR_LATER(_ah) \ diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c index fe08a4f..819feb9 100644 --- a/drivers/net/wireless/ath9k/regd.c +++ b/drivers/net/wireless/ath9k/regd.c @@ -16,9 +16,7 @@ #include #include -#include "core.h" -#include "hw.h" -#include "regd.h" +#include "ath9k.h" #include "regd_common.h" /* diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h index ba2d2df..d1c4457 100644 --- a/drivers/net/wireless/ath9k/regd.h +++ b/drivers/net/wireless/ath9k/regd.h @@ -17,8 +17,6 @@ #ifndef REGD_H #define REGD_H -#include "ath9k.h" - #define COUNTRY_ERD_FLAG 0x8000 #define WORLDWIDE_ROAMING_FLAG 0x4000 @@ -229,6 +227,16 @@ enum CountryCode { CTRY_BELGIUM2 = 5002 }; +u16 ath9k_regd_get_rd(struct ath_hal *ah); +bool ath9k_is_world_regd(struct ath_hal *ah); +const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah); +const struct ieee80211_regdomain *ath9k_default_world_regdomain(void); +void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby); +void ath9k_reg_apply_radar_flags(struct wiphy *wiphy); +int ath9k_regd_init(struct ath_hal *ah); +bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah); +u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); +int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request); void ath9k_regd_get_current_country(struct ath_hal *ah, struct ath9k_country_entry *ctry); diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c index d5f15e7..7a3ea92 100644 --- a/drivers/net/wireless/ath9k/xmit.c +++ b/drivers/net/wireless/ath9k/xmit.c @@ -14,7 +14,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include "core.h" +#include "ath9k.h" #define BITS_PER_BYTE 8 #define OFDM_PLCP_BITS 22 -- 1.5.6.3 From 29e1e40bd5d24258db12c54f90a8a43bd87facf3 Mon Sep 17 00:00:00 2001 From: Sujith Date: Sun, 8 Feb 2009 13:36:26 +0530 Subject: [PATCH] ath9k: Convert ANI channel to a pointer This patch converts the ANI channel reference to a pointer, this facilitates moving struct ar5416AniState to ani.h Signed-off-by: Sujith --- drivers/net/wireless/ath9k/ani.c | 8 ++++---- drivers/net/wireless/ath9k/ani.h | 27 +++++++++++++++++++++++++++ drivers/net/wireless/ath9k/hw.h | 27 --------------------------- 3 files changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index d75bd6e..9cebf0e 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c @@ -23,11 +23,11 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, int i; for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { - if (ahp->ah_ani[i].c.channel == chan->channel) + if (ahp->ah_ani[i].c && + ahp->ah_ani[i].c->channel == chan->channel) return i; - if (ahp->ah_ani[i].c.channel == 0) { - ahp->ah_ani[i].c.channel = chan->channel; - ahp->ah_ani[i].c.channelFlags = chan->channelFlags; + if (ahp->ah_ani[i].c == NULL) { + ahp->ah_ani[i].c = chan; return i; } } diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h index cfb7fbc..78880e5 100644 --- a/drivers/net/wireless/ath9k/ani.h +++ b/drivers/net/wireless/ath9k/ani.h @@ -72,6 +72,33 @@ struct ath9k_node_stats { u32 ns_avgtxrate; }; +struct ar5416AniState { + struct ath9k_channel *c; + u8 noiseImmunityLevel; + u8 spurImmunityLevel; + u8 firstepLevel; + u8 ofdmWeakSigDetectOff; + u8 cckWeakSigThreshold; + u32 listenTime; + u32 ofdmTrigHigh; + u32 ofdmTrigLow; + int32_t cckTrigHigh; + int32_t cckTrigLow; + int32_t rssiThrLow; + int32_t rssiThrHigh; + u32 noiseFloor; + u32 txFrameCount; + u32 rxFrameCount; + u32 cycleCount; + u32 ofdmPhyErrCount; + u32 cckPhyErrCount; + u32 ofdmPhyErrBase; + u32 cckPhyErrBase; + int16_t pktRssi[2]; + int16_t ofdmErrRssi[2]; + int16_t cckErrRssi[2]; +}; + struct ar5416Stats { u32 ast_ani_niup; u32 ast_ani_nidown; diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 2b72e75..b353b1f 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -406,33 +406,6 @@ enum { ATH9K_RESET_COLD, }; -struct ar5416AniState { - struct ath9k_channel c; - u8 noiseImmunityLevel; - u8 spurImmunityLevel; - u8 firstepLevel; - u8 ofdmWeakSigDetectOff; - u8 cckWeakSigThreshold; - u32 listenTime; - u32 ofdmTrigHigh; - u32 ofdmTrigLow; - int32_t cckTrigHigh; - int32_t cckTrigLow; - int32_t rssiThrLow; - int32_t rssiThrHigh; - u32 noiseFloor; - u32 txFrameCount; - u32 rxFrameCount; - u32 cycleCount; - u32 ofdmPhyErrCount; - u32 cckPhyErrCount; - u32 ofdmPhyErrBase; - u32 cckPhyErrBase; - int16_t pktRssi[2]; - int16_t ofdmErrRssi[2]; - int16_t cckErrRssi[2]; -}; - struct ath_hal { u32 ah_magic; u16 ah_devid; -- 1.5.6.3 From cba9dca6b9bf80b9ea7585fe45a21fd7cd11948c Mon Sep 17 00:00:00 2001 From: Sujith Date: Sun, 8 Feb 2009 14:01:43 +0530 Subject: [PATCH] ath9k: Remove all the sc_ prefixes This patch removes the useless sc_ prefixes for all variables. Also, refer to interfaces as VIFs and not as VAPs anymore. Signed-off-by: Sujith --- drivers/net/wireless/ath9k/ath9k.h | 144 ++++++++--------- drivers/net/wireless/ath9k/beacon.c | 56 ++++---- drivers/net/wireless/ath9k/debug.c | 130 ++++++++-------- drivers/net/wireless/ath9k/hw.c | 6 +- drivers/net/wireless/ath9k/main.c | 302 +++++++++++++++++----------------- drivers/net/wireless/ath9k/recv.c | 18 +- drivers/net/wireless/ath9k/xmit.c | 16 +- 7 files changed, 330 insertions(+), 342 deletions(-) diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 3cb7bf8..d60b2e7 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -104,13 +104,13 @@ enum buffer_type { }; struct ath_buf_state { - int bfs_nframes; /* # frames in aggregate */ - u16 bfs_al; /* length of aggregate */ - u16 bfs_frmlen; /* length of frame */ - int bfs_seqno; /* sequence number */ - int bfs_tidno; /* tid of this frame */ - int bfs_retries; /* current retries */ - u32 bf_type; /* BUF_* (enum buffer_type) */ + int bfs_nframes; + u16 bfs_al; + u16 bfs_frmlen; + int bfs_seqno; + int bfs_tidno; + int bfs_retries; + u32 bf_type; u32 bfs_keyix; enum ath9k_key_type bfs_keytype; }; @@ -129,10 +129,6 @@ struct ath_buf_state { #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) -/* - * Abstraction of a contiguous buffer to transmit/receive. There is only - * a single hw descriptor encapsulated here. - */ struct ath_buf { struct list_head list; struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or @@ -143,22 +139,20 @@ struct ath_buf { dma_addr_t bf_daddr; /* physical addr of desc */ dma_addr_t bf_buf_addr; /* physical addr of data buffer */ u32 bf_status; - u16 bf_flags; /* tx descriptor flags */ - struct ath_buf_state bf_state; /* buffer state */ + u16 bf_flags; + struct ath_buf_state bf_state; dma_addr_t bf_dmacontext; }; #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) #define ATH_BUFSTATUS_STALE 0x00000002 -/* DMA state for tx/rx descriptors */ - struct ath_descdma { const char *dd_name; - struct ath_desc *dd_desc; /* descriptors */ - dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ - u32 dd_desc_len; /* size of dd_desc */ - struct ath_buf *dd_bufptr; /* associated buffers */ + struct ath_desc *dd_desc; + dma_addr_t dd_desc_paddr; + u32 dd_desc_len; + struct ath_buf *dd_bufptr; dma_addr_t dd_dmacontext; }; @@ -246,15 +240,15 @@ enum ATH_AGGR_STATUS { }; struct ath_txq { - u32 axq_qnum; /* hardware q number */ - u32 *axq_link; /* link ptr in last TX desc */ - struct list_head axq_q; /* transmit queue */ + u32 axq_qnum; + u32 *axq_link; + struct list_head axq_q; spinlock_t axq_lock; - u32 axq_depth; /* queue depth */ - u8 axq_aggr_depth; /* aggregates queued */ - u32 axq_totalqueued; /* total ever queued */ - bool stopped; /* Is mac80211 queue stopped ? */ - struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ + u32 axq_depth; + u8 axq_aggr_depth; + u32 axq_totalqueued; + bool stopped; + struct ath_buf *axq_linkbuf; /* first desc of the last descriptor that contains CTS */ struct ath_desc *axq_lastdsWithCTS; @@ -270,45 +264,39 @@ struct ath_txq { #define AGGR_ADDBA_COMPLETE BIT(2) #define AGGR_ADDBA_PROGRESS BIT(3) -/* per TID aggregate tx state for a destination */ struct ath_atx_tid { - struct list_head list; /* round-robin tid entry */ - struct list_head buf_q; /* pending buffers */ + struct list_head list; + struct list_head buf_q; struct ath_node *an; struct ath_atx_ac *ac; - struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ + struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; u16 seq_start; u16 seq_next; u16 baw_size; int tidno; - int baw_head; /* first un-acked tx buffer */ - int baw_tail; /* next unused tx buffer slot */ + int baw_head; /* first un-acked tx buffer */ + int baw_tail; /* next unused tx buffer slot */ int sched; int paused; u8 state; int addba_exchangeattempts; }; -/* per access-category aggregate tx state for a destination */ struct ath_atx_ac { - int sched; /* dest-ac is scheduled */ - int qnum; /* H/W queue number associated - with this AC */ - struct list_head list; /* round-robin txq entry */ - struct list_head tid_q; /* queue of TIDs with buffers */ + int sched; + int qnum; + struct list_head list; + struct list_head tid_q; }; -/* per-frame tx control block */ struct ath_tx_control { struct ath_txq *txq; int if_id; }; -/* per frame tx status block */ struct ath_xmit_status { - int retries; /* number of retries to successufully - transmit this frame */ - int flags; /* status of transmit */ + int retries; + int flags; #define ATH_TX_ERROR 0x01 #define ATH_TX_XRETRY 0x02 #define ATH_TX_BAR 0x04 @@ -396,21 +384,21 @@ int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); /********/ -/* VAPs */ +/* VIFs */ /********/ /* * Define the scheme that we select MAC address for multiple - * BSS on the same radio. The very first VAP will just use the MAC - * address from the EEPROM. For the next 3 VAPs, we set the + * BSS on the same radio. The very first VIF will just use the MAC + * address from the EEPROM. For the next 3 VIFs, we set the * U/L bit (bit 1) in MAC address, and use the next two bits as the - * index of the VAP. + * index of the VIF. */ -#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ +#define ATH_SET_VIF_BSSID_MASK(bssid_mask) \ ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) -struct ath_vap { +struct ath_vif { int av_bslot; enum nl80211_iftype av_opmode; struct ath_buf *av_bcbuf; @@ -469,7 +457,7 @@ void ath9k_beacon_tasklet(unsigned long data); void ath_beacon_config(struct ath_softc *sc, int if_id); int ath_beaconq_setup(struct ath_hal *ah); int ath_beacon_alloc(struct ath_softc *sc, int if_id); -void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp); +void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); void ath_beacon_sync(struct ath_softc *sc, int if_id); /*******/ @@ -485,12 +473,12 @@ void ath_beacon_sync(struct ath_softc *sc, int if_id); #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */ struct ath_ani { - bool sc_caldone; - int16_t sc_noise_floor; - unsigned int sc_longcal_timer; - unsigned int sc_shortcal_timer; - unsigned int sc_resetcal_timer; - unsigned int sc_checkani_timer; + bool caldone; + int16_t noise_floor; + unsigned int longcal_timer; + unsigned int shortcal_timer; + unsigned int resetcal_timer; + unsigned int checkani_timer; struct timer_list timer; }; @@ -591,31 +579,31 @@ struct ath_softc { spinlock_t sc_resetlock; struct mutex mutex; - u8 sc_curbssid[ETH_ALEN]; - u8 sc_myaddr[ETH_ALEN]; - u8 sc_bssidmask[ETH_ALEN]; - u32 sc_intrstatus; + u8 curbssid[ETH_ALEN]; + u8 macaddr[ETH_ALEN]; + u8 bssidmask[ETH_ALEN]; + u32 intrstatus; u32 sc_flags; /* SC_OP_* */ - u16 sc_curtxpow; - u16 sc_curaid; - u16 sc_cachelsz; - u8 sc_nbcnvaps; - u16 sc_nvaps; - u8 sc_tx_chainmask; - u8 sc_rx_chainmask; - u32 sc_keymax; - DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); - u8 sc_splitmic; + u16 curtxpow; + u16 curaid; + u16 cachelsz; + u8 nbcnvifs; + u16 nvifs; + u8 tx_chainmask; + u8 rx_chainmask; + u32 keymax; + DECLARE_BITMAP(keymap, ATH_KEYMAX); + u8 splitmic; atomic_t ps_usecount; - enum ath9k_int sc_imask; - enum ath9k_ht_extprotspacing sc_ht_extprotspacing; + enum ath9k_int imask; + enum ath9k_ht_extprotspacing ht_extprotspacing; enum ath9k_ht_macmode tx_chan_width; - struct ath_config sc_config; + struct ath_config config; struct ath_rx rx; struct ath_tx tx; struct ath_beacon beacon; - struct ieee80211_vif *sc_vaps[ATH_BCBUF]; + struct ieee80211_vif *vifs[ATH_BCBUF]; struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; struct ath_rate_table *cur_rate_table; @@ -632,10 +620,10 @@ struct ath_softc { int led_off_cnt; struct ath_rfkill rf_kill; - struct ath_ani sc_ani; - struct ath9k_node_stats sc_halstats; + struct ath_ani ani; + struct ath9k_node_stats nodestats; #ifdef CONFIG_ATH9K_DEBUG - struct ath9k_debug sc_debug; + struct ath9k_debug debug; #endif struct ath_bus_ops *bus_ops; }; diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 1f92ad7..139bba7 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -63,7 +63,7 @@ static void ath_bstuck_process(struct ath_softc *sc) * Beacons are always sent out at the lowest rate, and are not retried. */ static void ath_beacon_setup(struct ath_softc *sc, - struct ath_vap *avp, struct ath_buf *bf) + struct ath_vif *avp, struct ath_buf *bf) { struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; struct ath_hal *ah = sc->sc_ah; @@ -96,7 +96,7 @@ static void ath_beacon_setup(struct ath_softc *sc, * SWBA's * XXX assumes two antenna */ - antenna = ((sc->beacon.ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1); + antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1); } ds->ds_data = bf->bf_buf_addr; @@ -132,24 +132,24 @@ static void ath_beacon_setup(struct ath_softc *sc, memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); series[0].Tries = 1; series[0].Rate = rate; - series[0].ChSel = sc->sc_tx_chainmask; + series[0].ChSel = sc->tx_chainmask; series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration, series, 4, 0); } -/* Generate beacon frame and queue cab data for a vap */ +/* Generate beacon frame and queue cab data for a VIF */ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) { struct ath_buf *bf; - struct ath_vap *avp; + struct ath_vif *avp; struct sk_buff *skb; struct ath_txq *cabq; struct ieee80211_vif *vif; struct ieee80211_tx_info *info; int cabq_depth; - vif = sc->sc_vaps[if_id]; + vif = sc->vifs[if_id]; ASSERT(vif); avp = (void *)vif->drv_priv; @@ -204,10 +204,10 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) /* * if the CABQ traffic from previous DTIM is pending and the current * beacon is also a DTIM. - * 1) if there is only one vap let the cab traffic continue. - * 2) if there are more than one vap and we are using staggered + * 1) if there is only one vif let the cab traffic continue. + * 2) if there are more than one vif and we are using staggered * beacons, then drain the cabq by dropping all the frames in - * the cabq so that the current vaps cab traffic can be scheduled. + * the cabq so that the current vifs cab traffic can be scheduled. */ spin_lock_bh(&cabq->axq_lock); cabq_depth = cabq->axq_depth; @@ -219,7 +219,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) * the lock again which is a common function and that * acquires txq lock inside. */ - if (sc->sc_nvaps > 1) { + if (sc->nvifs > 1) { ath_draintxq(sc, cabq, false); DPRINTF(sc, ATH_DBG_BEACON, "flush previous cabq traffic\n"); @@ -250,10 +250,10 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) struct ieee80211_vif *vif; struct ath_hal *ah = sc->sc_ah; struct ath_buf *bf; - struct ath_vap *avp; + struct ath_vif *avp; struct sk_buff *skb; - vif = sc->sc_vaps[if_id]; + vif = sc->vifs[if_id]; ASSERT(vif); avp = (void *)vif->drv_priv; @@ -291,13 +291,13 @@ int ath_beaconq_setup(struct ath_hal *ah) int ath_beacon_alloc(struct ath_softc *sc, int if_id) { struct ieee80211_vif *vif; - struct ath_vap *avp; + struct ath_vif *avp; struct ieee80211_hdr *hdr; struct ath_buf *bf; struct sk_buff *skb; __le64 tstamp; - vif = sc->sc_vaps[if_id]; + vif = sc->vifs[if_id]; ASSERT(vif); avp = (void *)vif->drv_priv; @@ -314,7 +314,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { int slot; /* - * Assign the vap to a beacon xmit slot. As + * Assign the vif to a beacon xmit slot. As * above, this cannot fail to find one. */ avp->av_bslot = 0; @@ -335,7 +335,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) } BUG_ON(sc->beacon.bslot[avp->av_bslot] != ATH_IF_ID_ANY); sc->beacon.bslot[avp->av_bslot] = if_id; - sc->sc_nbcnvaps++; + sc->nbcnvifs++; } } @@ -384,8 +384,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) * timestamp then convert to TSF units and handle * byte swapping before writing it in the frame. * The hardware will then add this each time a beacon - * frame is sent. Note that we align vap's 1..N - * and leave vap 0 untouched. This means vap 0 + * frame is sent. Note that we align vif's 1..N + * and leave vif 0 untouched. This means vap 0 * has a timestamp in one beacon interval while the * others get a timestamp aligned to the next interval. */ @@ -416,14 +416,14 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) return 0; } -void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) +void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp) { if (avp->av_bcbuf != NULL) { struct ath_buf *bf; if (avp->av_bslot != -1) { sc->beacon.bslot[avp->av_bslot] = ATH_IF_ID_ANY; - sc->sc_nbcnvaps--; + sc->nbcnvifs--; } bf = avp->av_bcbuf; @@ -597,7 +597,7 @@ void ath9k_beacon_tasklet(unsigned long data) ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr); ath9k_hw_txstart(ah, sc->beacon.beaconq); - sc->beacon.ast_be_xmit += bc; /* XXX per-vap? */ + sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */ } } @@ -621,12 +621,12 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) struct ieee80211_vif *vif; struct ath_hal *ah = sc->sc_ah; struct ath_beacon_config conf; - struct ath_vap *avp; + struct ath_vif *avp; enum nl80211_iftype opmode; u32 nexttbtt, intval; if (if_id != ATH_IF_ID_ANY) { - vif = sc->sc_vaps[if_id]; + vif = sc->vifs[if_id]; ASSERT(vif); avp = (void *)vif->drv_priv; opmode = avp->av_opmode; @@ -781,8 +781,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ath9k_hw_set_interrupts(ah, 0); ath9k_hw_set_sta_beacon_timers(ah, &bs); - sc->sc_imask |= ATH9K_INT_BMISS; - ath9k_hw_set_interrupts(ah, sc->sc_imask); + sc->imask |= ATH9K_INT_BMISS; + ath9k_hw_set_interrupts(ah, sc->imask); } else { u64 tsf; u32 tsftu; @@ -819,7 +819,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) */ intval |= ATH9K_BEACON_ENA; if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) - sc->sc_imask |= ATH9K_INT_SWBA; + sc->imask |= ATH9K_INT_SWBA; ath_beaconq_config(sc); } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { /* @@ -827,12 +827,12 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) * SWBA interrupts to prepare beacon frames. */ intval |= ATH9K_BEACON_ENA; - sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */ + sc->imask |= ATH9K_INT_SWBA; /* beacon prepare */ ath_beaconq_config(sc); } ath9k_hw_beaconinit(ah, nexttbtt, intval); sc->beacon.bmisscnt = 0; - ath9k_hw_set_interrupts(ah, sc->sc_imask); + ath9k_hw_set_interrupts(ah, sc->imask); /* * When using a self-linked beacon descriptor in * ibss mode load it once here. diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c index c9b47b3..daca5ce 100644 --- a/drivers/net/wireless/ath9k/debug.c +++ b/drivers/net/wireless/ath9k/debug.c @@ -24,7 +24,7 @@ void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...) if (!sc) return; - if (sc->sc_debug.debug_mask & dbg_mask) { + if (sc->debug.debug_mask & dbg_mask) { va_list args; va_start(args, fmt); @@ -130,41 +130,41 @@ static const struct file_operations fops_dma = { void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status) { if (status) - sc->sc_debug.stats.istats.total++; + sc->debug.stats.istats.total++; if (status & ATH9K_INT_RX) - sc->sc_debug.stats.istats.rxok++; + sc->debug.stats.istats.rxok++; if (status & ATH9K_INT_RXEOL) - sc->sc_debug.stats.istats.rxeol++; + sc->debug.stats.istats.rxeol++; if (status & ATH9K_INT_RXORN) - sc->sc_debug.stats.istats.rxorn++; + sc->debug.stats.istats.rxorn++; if (status & ATH9K_INT_TX) - sc->sc_debug.stats.istats.txok++; + sc->debug.stats.istats.txok++; if (status & ATH9K_INT_TXURN) - sc->sc_debug.stats.istats.txurn++; + sc->debug.stats.istats.txurn++; if (status & ATH9K_INT_MIB) - sc->sc_debug.stats.istats.mib++; + sc->debug.stats.istats.mib++; if (status & ATH9K_INT_RXPHY) - sc->sc_debug.stats.istats.rxphyerr++; + sc->debug.stats.istats.rxphyerr++; if (status & ATH9K_INT_RXKCM) - sc->sc_debug.stats.istats.rx_keycache_miss++; + sc->debug.stats.istats.rx_keycache_miss++; if (status & ATH9K_INT_SWBA) - sc->sc_debug.stats.istats.swba++; + sc->debug.stats.istats.swba++; if (status & ATH9K_INT_BMISS) - sc->sc_debug.stats.istats.bmiss++; + sc->debug.stats.istats.bmiss++; if (status & ATH9K_INT_BNR) - sc->sc_debug.stats.istats.bnr++; + sc->debug.stats.istats.bnr++; if (status & ATH9K_INT_CST) - sc->sc_debug.stats.istats.cst++; + sc->debug.stats.istats.cst++; if (status & ATH9K_INT_GTT) - sc->sc_debug.stats.istats.gtt++; + sc->debug.stats.istats.gtt++; if (status & ATH9K_INT_TIM) - sc->sc_debug.stats.istats.tim++; + sc->debug.stats.istats.tim++; if (status & ATH9K_INT_CABEND) - sc->sc_debug.stats.istats.cabend++; + sc->debug.stats.istats.cabend++; if (status & ATH9K_INT_DTIMSYNC) - sc->sc_debug.stats.istats.dtimsync++; + sc->debug.stats.istats.dtimsync++; if (status & ATH9K_INT_DTIM) - sc->sc_debug.stats.istats.dtim++; + sc->debug.stats.istats.dtim++; } static ssize_t read_file_interrupt(struct file *file, char __user *user_buf, @@ -175,41 +175,41 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf, unsigned int len = 0; len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "RX", sc->sc_debug.stats.istats.rxok); + "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "RXEOL", sc->sc_debug.stats.istats.rxeol); + "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "RXORN", sc->sc_debug.stats.istats.rxorn); + "%8s: %10u\n", "RXORN", sc->debug.stats.istats.rxorn); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "TX", sc->sc_debug.stats.istats.txok); + "%8s: %10u\n", "TX", sc->debug.stats.istats.txok); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "TXURN", sc->sc_debug.stats.istats.txurn); + "%8s: %10u\n", "TXURN", sc->debug.stats.istats.txurn); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "MIB", sc->sc_debug.stats.istats.mib); + "%8s: %10u\n", "MIB", sc->debug.stats.istats.mib); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "RXPHY", sc->sc_debug.stats.istats.rxphyerr); + "%8s: %10u\n", "RXPHY", sc->debug.stats.istats.rxphyerr); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "RXKCM", sc->sc_debug.stats.istats.rx_keycache_miss); + "%8s: %10u\n", "RXKCM", sc->debug.stats.istats.rx_keycache_miss); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "SWBA", sc->sc_debug.stats.istats.swba); + "%8s: %10u\n", "SWBA", sc->debug.stats.istats.swba); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "BMISS", sc->sc_debug.stats.istats.bmiss); + "%8s: %10u\n", "BMISS", sc->debug.stats.istats.bmiss); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "BNR", sc->sc_debug.stats.istats.bnr); + "%8s: %10u\n", "BNR", sc->debug.stats.istats.bnr); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "CST", sc->sc_debug.stats.istats.cst); + "%8s: %10u\n", "CST", sc->debug.stats.istats.cst); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "GTT", sc->sc_debug.stats.istats.gtt); + "%8s: %10u\n", "GTT", sc->debug.stats.istats.gtt); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "TIM", sc->sc_debug.stats.istats.tim); + "%8s: %10u\n", "TIM", sc->debug.stats.istats.tim); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "CABEND", sc->sc_debug.stats.istats.cabend); + "%8s: %10u\n", "CABEND", sc->debug.stats.istats.cabend); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "DTIMSYNC", sc->sc_debug.stats.istats.dtimsync); + "%8s: %10u\n", "DTIMSYNC", sc->debug.stats.istats.dtimsync); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "DTIM", sc->sc_debug.stats.istats.dtim); + "%8s: %10u\n", "DTIM", sc->debug.stats.istats.dtim); len += snprintf(buf + len, sizeof(buf) - len, - "%8s: %10u\n", "TOTAL", sc->sc_debug.stats.istats.total); + "%8s: %10u\n", "TOTAL", sc->debug.stats.istats.total); return simple_read_from_buffer(user_buf, count, ppos, buf, len); } @@ -231,7 +231,7 @@ static void ath_debug_stat_11n_rc(struct ath_softc *sc, struct sk_buff *skb) final_ts_idx = tx_info_priv->tx.ts_rateindex; idx = sc->cur_rate_table->info[rates[final_ts_idx].idx].dot11rate; - sc->sc_debug.stats.n_rcstats[idx].success++; + sc->debug.stats.n_rcstats[idx].success++; } static void ath_debug_stat_legacy_rc(struct ath_softc *sc, struct sk_buff *skb) @@ -245,7 +245,7 @@ static void ath_debug_stat_legacy_rc(struct ath_softc *sc, struct sk_buff *skb) final_ts_idx = tx_info_priv->tx.ts_rateindex; idx = rates[final_ts_idx].idx; - sc->sc_debug.stats.legacy_rcstats[idx].success++; + sc->debug.stats.legacy_rcstats[idx].success++; } void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb) @@ -263,8 +263,8 @@ void ath_debug_stat_retries(struct ath_softc *sc, int rix, if (conf_is_ht(&sc->hw->conf)) { int idx = sc->cur_rate_table->info[rix].dot11rate; - sc->sc_debug.stats.n_rcstats[idx].xretries += xretries; - sc->sc_debug.stats.n_rcstats[idx].retries += retries; + sc->debug.stats.n_rcstats[idx].xretries += xretries; + sc->debug.stats.n_rcstats[idx].retries += retries; } } @@ -283,9 +283,9 @@ static ssize_t ath_read_file_stat_11n_rc(struct file *file, for (i = 0; i <= 15; i++) { len += snprintf(buf + len, sizeof(buf) - len, "%5s%3d: %8u %8u %8u\n", "MCS", i, - sc->sc_debug.stats.n_rcstats[i].success, - sc->sc_debug.stats.n_rcstats[i].retries, - sc->sc_debug.stats.n_rcstats[i].xretries); + sc->debug.stats.n_rcstats[i].success, + sc->debug.stats.n_rcstats[i].retries, + sc->debug.stats.n_rcstats[i].xretries); } return simple_read_from_buffer(user_buf, count, ppos, buf, len); @@ -305,7 +305,7 @@ static ssize_t ath_read_file_stat_legacy_rc(struct file *file, for (i = 0; i < sc->cur_rate_table->rate_cnt; i++) { len += snprintf(buf + len, sizeof(buf) - len, "%5u: %12u\n", sc->cur_rate_table->info[i].ratekbps / 1000, - sc->sc_debug.stats.legacy_rcstats[i].success); + sc->debug.stats.legacy_rcstats[i].success); } return simple_read_from_buffer(user_buf, count, ppos, buf, len); @@ -330,34 +330,34 @@ static const struct file_operations fops_rcstat = { int ath9k_init_debug(struct ath_softc *sc) { - sc->sc_debug.debug_mask = ath9k_debug; + sc->debug.debug_mask = ath9k_debug; - sc->sc_debug.debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); - if (!sc->sc_debug.debugfs_root) + sc->debug.debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); + if (!sc->debug.debugfs_root) goto err; - sc->sc_debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy), - sc->sc_debug.debugfs_root); - if (!sc->sc_debug.debugfs_phy) + sc->debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy), + sc->debug.debugfs_root); + if (!sc->debug.debugfs_phy) goto err; - sc->sc_debug.debugfs_dma = debugfs_create_file("dma", S_IRUGO, - sc->sc_debug.debugfs_phy, sc, &fops_dma); - if (!sc->sc_debug.debugfs_dma) + sc->debug.debugfs_dma = debugfs_create_file("dma", S_IRUGO, + sc->debug.debugfs_phy, sc, &fops_dma); + if (!sc->debug.debugfs_dma) goto err; - sc->sc_debug.debugfs_interrupt = debugfs_create_file("interrupt", + sc->debug.debugfs_interrupt = debugfs_create_file("interrupt", S_IRUGO, - sc->sc_debug.debugfs_phy, + sc->debug.debugfs_phy, sc, &fops_interrupt); - if (!sc->sc_debug.debugfs_interrupt) + if (!sc->debug.debugfs_interrupt) goto err; - sc->sc_debug.debugfs_rcstat = debugfs_create_file("rcstat", + sc->debug.debugfs_rcstat = debugfs_create_file("rcstat", S_IRUGO, - sc->sc_debug.debugfs_phy, + sc->debug.debugfs_phy, sc, &fops_rcstat); - if (!sc->sc_debug.debugfs_rcstat) + if (!sc->debug.debugfs_rcstat) goto err; return 0; @@ -368,9 +368,9 @@ err: void ath9k_exit_debug(struct ath_softc *sc) { - debugfs_remove(sc->sc_debug.debugfs_rcstat); - debugfs_remove(sc->sc_debug.debugfs_interrupt); - debugfs_remove(sc->sc_debug.debugfs_dma); - debugfs_remove(sc->sc_debug.debugfs_phy); - debugfs_remove(sc->sc_debug.debugfs_root); + debugfs_remove(sc->debug.debugfs_rcstat); + debugfs_remove(sc->debug.debugfs_interrupt); + debugfs_remove(sc->debug.debugfs_dma); + debugfs_remove(sc->debug.debugfs_phy); + debugfs_remove(sc->debug.debugfs_root); } diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 075ddc5..1a6c5ac 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -2158,9 +2158,9 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, u32 macStaId1; int i, rx_chainmask, r; - ahp->ah_extprotspacing = sc->sc_ht_extprotspacing; - ahp->ah_txchainmask = sc->sc_tx_chainmask; - ahp->ah_rxchainmask = sc->sc_rx_chainmask; + ahp->ah_extprotspacing = sc->ht_extprotspacing; + ahp->ah_txchainmask = sc->tx_chainmask; + ahp->ah_rxchainmask = sc->rx_chainmask; if (AR_SREV_9285(ah)) { ahp->ah_txchainmask &= 0x1; diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index 2ed0bd2..dacf97a 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -140,11 +140,11 @@ static void ath_update_txpow(struct ath_softc *sc) struct ath_hal *ah = sc->sc_ah; u32 txpow; - if (sc->sc_curtxpow != sc->sc_config.txpowlimit) { - ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit); + if (sc->curtxpow != sc->config.txpowlimit) { + ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); /* read back in case value is clamped */ ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); - sc->sc_curtxpow = txpow; + sc->curtxpow = txpow; } } @@ -294,7 +294,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) ath_cache_conf_rate(sc, &hw->conf); ath_update_txpow(sc); - ath9k_hw_set_interrupts(ah, sc->sc_imask); + ath9k_hw_set_interrupts(ah, sc->imask); ath9k_ps_restore(sc); return 0; } @@ -327,42 +327,42 @@ static void ath_ani_calibrate(unsigned long data) return; /* Long calibration runs independently of short calibration. */ - if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) { + if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { longcal = true; DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies); - sc->sc_ani.sc_longcal_timer = timestamp; + sc->ani.longcal_timer = timestamp; } - /* Short calibration applies only while sc_caldone is false */ - if (!sc->sc_ani.sc_caldone) { - if ((timestamp - sc->sc_ani.sc_shortcal_timer) >= + /* Short calibration applies only while caldone is false */ + if (!sc->ani.caldone) { + if ((timestamp - sc->ani.shortcal_timer) >= ATH_SHORT_CALINTERVAL) { shortcal = true; DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); - sc->sc_ani.sc_shortcal_timer = timestamp; - sc->sc_ani.sc_resetcal_timer = timestamp; + sc->ani.shortcal_timer = timestamp; + sc->ani.resetcal_timer = timestamp; } } else { - if ((timestamp - sc->sc_ani.sc_resetcal_timer) >= + if ((timestamp - sc->ani.resetcal_timer) >= ATH_RESTART_CALINTERVAL) { - sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah); - if (sc->sc_ani.sc_caldone) - sc->sc_ani.sc_resetcal_timer = timestamp; + sc->ani.caldone = ath9k_hw_reset_calvalid(ah); + if (sc->ani.caldone) + sc->ani.resetcal_timer = timestamp; } } /* Verify whether we must check ANI */ - if ((timestamp - sc->sc_ani.sc_checkani_timer) >= + if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { aniflag = true; - sc->sc_ani.sc_checkani_timer = timestamp; + sc->ani.checkani_timer = timestamp; } /* Skip all processing if there's nothing to do. */ if (longcal || shortcal || aniflag) { /* Call ANI routine if necessary */ if (aniflag) - ath9k_hw_ani_monitor(ah, &sc->sc_halstats, + ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->ah_curchan); /* Perform calibration if necessary */ @@ -370,10 +370,10 @@ static void ath_ani_calibrate(unsigned long data) bool iscaldone = false; if (ath9k_hw_calibrate(ah, ah->ah_curchan, - sc->sc_rx_chainmask, longcal, + sc->rx_chainmask, longcal, &iscaldone)) { if (longcal) - sc->sc_ani.sc_noise_floor = + sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, ah->ah_curchan); @@ -381,14 +381,14 @@ static void ath_ani_calibrate(unsigned long data) "calibrate chan %u/%x nf: %d\n", ah->ah_curchan->channel, ah->ah_curchan->channelFlags, - sc->sc_ani.sc_noise_floor); + sc->ani.noise_floor); } else { DPRINTF(sc, ATH_DBG_ANY, "calibrate chan %u/%x failed\n", ah->ah_curchan->channel, ah->ah_curchan->channelFlags); } - sc->sc_ani.sc_caldone = iscaldone; + sc->ani.caldone = iscaldone; } } @@ -400,10 +400,10 @@ static void ath_ani_calibrate(unsigned long data) cal_interval = ATH_LONG_CALINTERVAL; if (sc->sc_ah->ah_config.enable_ani) cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); - if (!sc->sc_ani.sc_caldone) + if (!sc->ani.caldone) cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL); - mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval)); + mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); } /* @@ -417,15 +417,15 @@ static void ath_update_chainmask(struct ath_softc *sc, int is_ht) sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; if (is_ht || (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { - sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; - sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; + sc->tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; + sc->rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; } else { - sc->sc_tx_chainmask = 1; - sc->sc_rx_chainmask = 1; + sc->tx_chainmask = 1; + sc->rx_chainmask = 1; } DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", - sc->sc_tx_chainmask, sc->sc_rx_chainmask); + sc->tx_chainmask, sc->rx_chainmask); } static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) @@ -453,7 +453,7 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) static void ath9k_tasklet(unsigned long data) { struct ath_softc *sc = (struct ath_softc *)data; - u32 status = sc->sc_intrstatus; + u32 status = sc->intrstatus; if (status & ATH9K_INT_FATAL) { /* need a chip reset */ @@ -473,7 +473,7 @@ static void ath9k_tasklet(unsigned long data) } /* re-enable hardware interrupt */ - ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask); + ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); } irqreturn_t ath_isr(int irq, void *dev) @@ -504,7 +504,7 @@ irqreturn_t ath_isr(int irq, void *dev) */ ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ - status &= sc->sc_imask; /* discard unasked-for bits */ + status &= sc->imask; /* discard unasked-for bits */ /* * If there are no status bits set, then this interrupt was not @@ -513,7 +513,7 @@ irqreturn_t ath_isr(int irq, void *dev) if (!status) return IRQ_NONE; - sc->sc_intrstatus = status; + sc->intrstatus = status; if (status & ATH9K_INT_FATAL) { /* need a chip reset */ @@ -560,8 +560,8 @@ irqreturn_t ath_isr(int irq, void *dev) * it will clear whatever condition caused * the interrupt. */ - ath9k_hw_procmibevent(ah, &sc->sc_halstats); - ath9k_hw_set_interrupts(ah, sc->sc_imask); + ath9k_hw_procmibevent(ah, &sc->nodestats); + ath9k_hw_set_interrupts(ah, sc->imask); } if (status & ATH9K_INT_TIM_TIMER) { if (!(ah->ah_caps.hw_caps & @@ -581,7 +581,7 @@ irqreturn_t ath_isr(int irq, void *dev) if (sched) { /* turn off every interrupt except SWBA */ - ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA)); + ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA)); tasklet_schedule(&sc->intr_tq); } @@ -656,7 +656,7 @@ static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key, memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); return ath_keyset(sc, keyix, hk, addr); } - if (!sc->sc_splitmic) { + if (!sc->splitmic) { /* * data key goes at first index, * the hal handles the MIC keys at index+64. @@ -686,13 +686,13 @@ static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc) { int i; - for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) { - if (test_bit(i, sc->sc_keymap) || - test_bit(i + 64, sc->sc_keymap)) + for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { + if (test_bit(i, sc->keymap) || + test_bit(i + 64, sc->keymap)) continue; /* At least one part of TKIP key allocated */ - if (sc->sc_splitmic && - (test_bit(i + 32, sc->sc_keymap) || - test_bit(i + 64 + 32, sc->sc_keymap))) + if (sc->splitmic && + (test_bit(i + 32, sc->keymap) || + test_bit(i + 64 + 32, sc->keymap))) continue; /* At least one part of TKIP key allocated */ /* Found a free slot for a TKIP key */ @@ -706,55 +706,55 @@ static int ath_reserve_key_cache_slot(struct ath_softc *sc) int i; /* First, try to find slots that would not be available for TKIP. */ - if (sc->sc_splitmic) { - for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) { - if (!test_bit(i, sc->sc_keymap) && - (test_bit(i + 32, sc->sc_keymap) || - test_bit(i + 64, sc->sc_keymap) || - test_bit(i + 64 + 32, sc->sc_keymap))) + if (sc->splitmic) { + for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) { + if (!test_bit(i, sc->keymap) && + (test_bit(i + 32, sc->keymap) || + test_bit(i + 64, sc->keymap) || + test_bit(i + 64 + 32, sc->keymap))) return i; - if (!test_bit(i + 32, sc->sc_keymap) && - (test_bit(i, sc->sc_keymap) || - test_bit(i + 64, sc->sc_keymap) || - test_bit(i + 64 + 32, sc->sc_keymap))) + if (!test_bit(i + 32, sc->keymap) && + (test_bit(i, sc->keymap) || + test_bit(i + 64, sc->keymap) || + test_bit(i + 64 + 32, sc->keymap))) return i + 32; - if (!test_bit(i + 64, sc->sc_keymap) && - (test_bit(i , sc->sc_keymap) || - test_bit(i + 32, sc->sc_keymap) || - test_bit(i + 64 + 32, sc->sc_keymap))) + if (!test_bit(i + 64, sc->keymap) && + (test_bit(i , sc->keymap) || + test_bit(i + 32, sc->keymap) || + test_bit(i + 64 + 32, sc->keymap))) return i + 64; - if (!test_bit(i + 64 + 32, sc->sc_keymap) && - (test_bit(i, sc->sc_keymap) || - test_bit(i + 32, sc->sc_keymap) || - test_bit(i + 64, sc->sc_keymap))) + if (!test_bit(i + 64 + 32, sc->keymap) && + (test_bit(i, sc->keymap) || + test_bit(i + 32, sc->keymap) || + test_bit(i + 64, sc->keymap))) return i + 64 + 32; } } else { - for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) { - if (!test_bit(i, sc->sc_keymap) && - test_bit(i + 64, sc->sc_keymap)) + for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { + if (!test_bit(i, sc->keymap) && + test_bit(i + 64, sc->keymap)) return i; - if (test_bit(i, sc->sc_keymap) && - !test_bit(i + 64, sc->sc_keymap)) + if (test_bit(i, sc->keymap) && + !test_bit(i + 64, sc->keymap)) return i + 64; } } /* No partially used TKIP slots, pick any available slot */ - for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) { + for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) { /* Do not allow slots that could be needed for TKIP group keys * to be used. This limitation could be removed if we know that * TKIP will not be used. */ if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) continue; - if (sc->sc_splitmic) { + if (sc->splitmic) { if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) continue; if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) continue; } - if (!test_bit(i, sc->sc_keymap)) + if (!test_bit(i, sc->keymap)) return i; /* Found a free slot for a key */ } @@ -801,7 +801,7 @@ static int ath_key_config(struct ath_softc *sc, return -EOPNOTSUPP; mac = sta->addr; - vif = sc->sc_vaps[0]; + vif = sc->vifs[0]; if (vif->type != NL80211_IFTYPE_AP) { /* Only keyidx 0 should be used with unicast key, but * allow this for client mode for now. */ @@ -829,12 +829,12 @@ static int ath_key_config(struct ath_softc *sc, if (!ret) return -EIO; - set_bit(idx, sc->sc_keymap); + set_bit(idx, sc->keymap); if (key->alg == ALG_TKIP) { - set_bit(idx + 64, sc->sc_keymap); - if (sc->sc_splitmic) { - set_bit(idx + 32, sc->sc_keymap); - set_bit(idx + 64 + 32, sc->sc_keymap); + set_bit(idx + 64, sc->keymap); + if (sc->splitmic) { + set_bit(idx + 32, sc->keymap); + set_bit(idx + 64 + 32, sc->keymap); } } @@ -847,14 +847,14 @@ static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) if (key->hw_key_idx < IEEE80211_WEP_NKID) return; - clear_bit(key->hw_key_idx, sc->sc_keymap); + clear_bit(key->hw_key_idx, sc->keymap); if (key->alg != ALG_TKIP) return; - clear_bit(key->hw_key_idx + 64, sc->sc_keymap); - if (sc->sc_splitmic) { - clear_bit(key->hw_key_idx + 32, sc->sc_keymap); - clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap); + clear_bit(key->hw_key_idx + 64, sc->keymap); + if (sc->splitmic) { + clear_bit(key->hw_key_idx + 32, sc->keymap); + clear_bit(key->hw_key_idx + 64 + 32, sc->keymap); } } @@ -876,7 +876,7 @@ static void setup_ht_cap(struct ath_softc *sc, /* set up supported mcs set */ memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); - switch(sc->sc_rx_chainmask) { + switch(sc->rx_chainmask) { case 1: ht_info->mcs.rx_mask[0] = 0xff; break; @@ -896,17 +896,17 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc, struct ieee80211_vif *vif, struct ieee80211_bss_conf *bss_conf) { - struct ath_vap *avp = (void *)vif->drv_priv; + struct ath_vif *avp = (void *)vif->drv_priv; if (bss_conf->assoc) { DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", - bss_conf->aid, sc->sc_curbssid); + bss_conf->aid, sc->curbssid); /* New association, store aid */ if (avp->av_opmode == NL80211_IFTYPE_STATION) { - sc->sc_curaid = bss_conf->aid; - ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, - sc->sc_curaid); + sc->curaid = bss_conf->aid; + ath9k_hw_write_associd(sc->sc_ah, sc->curbssid, + sc->curaid); } /* Configure the beacon */ @@ -914,18 +914,18 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc, sc->sc_flags |= SC_OP_BEACONS; /* Reset rssi stats */ - sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; - sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; - sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; - sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER; + sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; + sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; + sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; + sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER; /* Start ANI */ - mod_timer(&sc->sc_ani.timer, + mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); } else { DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n"); - sc->sc_curaid = 0; + sc->curaid = 0; } } @@ -1120,7 +1120,7 @@ static void ath_radio_enable(struct ath_softc *sc) ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */ /* Re-Enable interrupts */ - ath9k_hw_set_interrupts(ah, sc->sc_imask); + ath9k_hw_set_interrupts(ah, sc->imask); /* Enable LED */ ath9k_hw_cfg_output(ah, ATH_LED_PIN, @@ -1369,7 +1369,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) */ ath_read_cachesize(sc, &csz); /* XXX assert csz is non-zero */ - sc->sc_cachelsz = csz << 2; /* convert to bytes */ + sc->cachelsz = csz << 2; /* convert to bytes */ ah = ath9k_hw_attach(devid, sc, sc->mem, &status); if (ah == NULL) { @@ -1381,19 +1381,19 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->sc_ah = ah; /* Get the hardware key cache size. */ - sc->sc_keymax = ah->ah_caps.keycache_size; - if (sc->sc_keymax > ATH_KEYMAX) { + sc->keymax = ah->ah_caps.keycache_size; + if (sc->keymax > ATH_KEYMAX) { DPRINTF(sc, ATH_DBG_KEYCACHE, "Warning, using only %u entries in %u key cache\n", - ATH_KEYMAX, sc->sc_keymax); - sc->sc_keymax = ATH_KEYMAX; + ATH_KEYMAX, sc->keymax); + sc->keymax = ATH_KEYMAX; } /* * Reset the key cache since some parts do not * reset the contents on initial power up. */ - for (i = 0; i < sc->sc_keymax; i++) + for (i = 0; i < sc->keymax; i++) ath9k_hw_keyreset(ah, (u16) i); if (ath9k_regd_init(sc->sc_ah)) @@ -1429,7 +1429,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) goto bad2; } - sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME; + sc->config.cabqReadytime = ATH_CABQ_READY_TIME; ath_cabq_update(sc); for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++) @@ -1466,8 +1466,8 @@ static int ath_init(u16 devid, struct ath_softc *sc) /* Initializes the noise floor to a reasonable default value. * Later on this will be updated during ANI processing. */ - sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR; - setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc); + sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR; + setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc); if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, ATH9K_CIPHER_TKIP, NULL)) { @@ -1493,14 +1493,14 @@ static int ath_init(u16 devid, struct ath_softc *sc) ATH9K_CIPHER_MIC, NULL) && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, 0, NULL)) - sc->sc_splitmic = 1; + sc->splitmic = 1; /* turn on mcast key search if possible */ if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1, 1, NULL); - sc->sc_config.txpowlimit = ATH_TXPOWER_MAX; + sc->config.txpowlimit = ATH_TXPOWER_MAX; /* 11n Capabilities */ if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { @@ -1508,17 +1508,17 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->sc_flags |= SC_OP_RXAGGR; } - sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask; - sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask; + sc->tx_chainmask = ah->ah_caps.tx_chainmask; + sc->rx_chainmask = ah->ah_caps.rx_chainmask; ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); sc->rx.defant = ath9k_hw_getdefantenna(ah); - ath9k_hw_getmac(ah, sc->sc_myaddr); + ath9k_hw_getmac(ah, sc->macaddr); if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { - ath9k_hw_getbssidmask(ah, sc->sc_bssidmask); - ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask); - ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); + ath9k_hw_getbssidmask(ah, sc->bssidmask); + ATH_SET_VIF_BSSID_MASK(sc->bssidmask); + ath9k_hw_setbssidmask(ah, sc->bssidmask); } sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ @@ -1528,7 +1528,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->beacon.bslot[i] = ATH_IF_ID_ANY; /* save MISC configurations */ - sc->sc_config.swBeaconProcess = 1; + sc->config.swBeaconProcess = 1; /* setup channels and rates */ @@ -1577,7 +1577,7 @@ int ath_attach(u16 devid, struct ath_softc *sc) /* get mac address from hardware and set in mac80211 */ - SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr); + SET_IEEE80211_PERM_ADDR(hw, sc->macaddr); hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | @@ -1601,7 +1601,7 @@ int ath_attach(u16 devid, struct ath_softc *sc) hw->max_rates = 4; hw->max_rate_tries = ATH_11N_TXMAXTRY; hw->sta_data_size = sizeof(struct ath_node); - hw->vif_data_size = sizeof(struct ath_vap); + hw->vif_data_size = sizeof(struct ath_vif); hw->rate_control_algorithm = "ath9k_rate_control"; @@ -1704,7 +1704,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx) if (sc->sc_flags & SC_OP_BEACONS) ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */ - ath9k_hw_set_interrupts(ah, sc->sc_imask); + ath9k_hw_set_interrupts(ah, sc->imask); if (retry_tx) { int i; @@ -1987,23 +1987,23 @@ static int ath9k_start(struct ieee80211_hw *hw) } /* Setup our intr mask. */ - sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX + sc->imask = ATH9K_INT_RX | ATH9K_INT_TX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) - sc->sc_imask |= ATH9K_INT_GTT; + sc->imask |= ATH9K_INT_GTT; if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) - sc->sc_imask |= ATH9K_INT_CST; + sc->imask |= ATH9K_INT_CST; ath_cache_conf_rate(sc, &hw->conf); sc->sc_flags &= ~SC_OP_INVALID; /* Disable BMISS interrupt when we're not associated */ - sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); - ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask); + sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); + ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); ieee80211_wake_queues(sc->hw); @@ -2112,12 +2112,12 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, struct ieee80211_if_init_conf *conf) { struct ath_softc *sc = hw->priv; - struct ath_vap *avp = (void *)conf->vif->drv_priv; + struct ath_vif *avp = (void *)conf->vif->drv_priv; enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; - /* Support only vap for now */ + /* Support only vif for now */ - if (sc->sc_nvaps) + if (sc->nvifs) return -ENOBUFS; mutex_lock(&sc->mutex); @@ -2138,17 +2138,17 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, return -EOPNOTSUPP; } - DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode); + DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); - /* Set the VAP opmode */ + /* Set the VIF opmode */ avp->av_opmode = ic_opmode; avp->av_bslot = -1; if (ic_opmode == NL80211_IFTYPE_AP) ath9k_hw_set_tsfadjust(sc->sc_ah, 1); - sc->sc_vaps[0] = conf->vif; - sc->sc_nvaps++; + sc->vifs[0] = conf->vif; + sc->nvifs++; /* Set the device opmode */ sc->sc_ah->ah_opmode = ic_opmode; @@ -2160,7 +2160,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, if (ath9k_hw_phycounters(sc->sc_ah) && ((conf->type == NL80211_IFTYPE_STATION) || (conf->type == NL80211_IFTYPE_ADHOC))) - sc->sc_imask |= ATH9K_INT_MIB; + sc->imask |= ATH9K_INT_MIB; /* * Some hardware processes the TIM IE and fires an * interrupt when the TIM bit is set. For hardware @@ -2169,15 +2169,15 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, */ if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && (conf->type == NL80211_IFTYPE_STATION) && - !sc->sc_config.swBeaconProcess) - sc->sc_imask |= ATH9K_INT_TIM; + !sc->config.swBeaconProcess) + sc->imask |= ATH9K_INT_TIM; - ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask); + ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); if (conf->type == NL80211_IFTYPE_AP) { /* TODO: is this a suitable place to start ANI for AP mode? */ /* Start ANI */ - mod_timer(&sc->sc_ani.timer, + mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); } @@ -2190,14 +2190,14 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw, struct ieee80211_if_init_conf *conf) { struct ath_softc *sc = hw->priv; - struct ath_vap *avp = (void *)conf->vif->drv_priv; + struct ath_vif *avp = (void *)conf->vif->drv_priv; DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); mutex_lock(&sc->mutex); /* Stop ANI */ - del_timer_sync(&sc->sc_ani.timer); + del_timer_sync(&sc->ani.timer); /* Reclaim beacon resources */ if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || @@ -2208,8 +2208,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw, sc->sc_flags &= ~SC_OP_BEACONS; - sc->sc_vaps[0] = NULL; - sc->sc_nvaps--; + sc->vifs[0] = NULL; + sc->nvifs--; mutex_unlock(&sc->mutex); } @@ -2223,10 +2223,10 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) if (changed & IEEE80211_CONF_CHANGE_PS) { if (conf->flags & IEEE80211_CONF_PS) { - if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) { - sc->sc_imask |= ATH9K_INT_TIM_TIMER; + if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) { + sc->imask |= ATH9K_INT_TIM_TIMER; ath9k_hw_set_interrupts(sc->sc_ah, - sc->sc_imask); + sc->imask); } ath9k_hw_setrxabort(sc->sc_ah, 1); ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); @@ -2234,10 +2234,10 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); ath9k_hw_setrxabort(sc->sc_ah, 0); sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; - if (sc->sc_imask & ATH9K_INT_TIM_TIMER) { - sc->sc_imask &= ~ATH9K_INT_TIM_TIMER; + if (sc->imask & ATH9K_INT_TIM_TIMER) { + sc->imask &= ~ATH9K_INT_TIM_TIMER; ath9k_hw_set_interrupts(sc->sc_ah, - sc->sc_imask); + sc->imask); } } } @@ -2262,7 +2262,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) } if (changed & IEEE80211_CONF_CHANGE_POWER) - sc->sc_config.txpowlimit = 2 * conf->power_level; + sc->config.txpowlimit = 2 * conf->power_level; mutex_unlock(&sc->mutex); @@ -2275,7 +2275,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, { struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; - struct ath_vap *avp = (void *)vif->drv_priv; + struct ath_vif *avp = (void *)vif->drv_priv; u32 rfilt = 0; int error, i; @@ -2285,7 +2285,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, ah->ah_opmode != NL80211_IFTYPE_AP) { ah->ah_opmode = NL80211_IFTYPE_STATION; ath9k_hw_setopmode(ah); - ath9k_hw_write_associd(ah, sc->sc_myaddr, 0); + ath9k_hw_write_associd(ah, sc->macaddr, 0); /* Request full reset to get hw opmode changed properly */ sc->sc_flags |= SC_OP_FULL_RESET; } @@ -2296,17 +2296,17 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_ADHOC: /* Set BSSID */ - memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN); - sc->sc_curaid = 0; - ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, - sc->sc_curaid); + memcpy(sc->curbssid, conf->bssid, ETH_ALEN); + sc->curaid = 0; + ath9k_hw_write_associd(sc->sc_ah, sc->curbssid, + sc->curaid); /* Set aggregation protection mode parameters */ - sc->sc_config.ath_aggr_prot = 0; + sc->config.ath_aggr_prot = 0; DPRINTF(sc, ATH_DBG_CONFIG, "RX filter 0x%x bssid %pM aid 0x%x\n", - rfilt, sc->sc_curbssid, sc->sc_curaid); + rfilt, sc->curbssid, sc->curaid); /* need to reconfigure the beacon */ sc->sc_flags &= ~SC_OP_BEACONS ; @@ -2346,7 +2346,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i)) ath9k_hw_keysetmac(sc->sc_ah, (u16)i, - sc->sc_curbssid); + sc->curbssid); } /* Only legacy IBSS for now */ diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index 69dd5e2..e8e4a32 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -97,11 +97,11 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len) * Unfortunately this means we may get 8 KB here from the * kernel... and that is actually what is observed on some * systems :( */ - skb = dev_alloc_skb(len + sc->sc_cachelsz - 1); + skb = dev_alloc_skb(len + sc->cachelsz - 1); if (skb != NULL) { - off = ((unsigned long) skb->data) % sc->sc_cachelsz; + off = ((unsigned long) skb->data) % sc->cachelsz; if (off != 0) - skb_reserve(skb, sc->sc_cachelsz - off); + skb_reserve(skb, sc->cachelsz - off); } else { DPRINTF(sc, ATH_DBG_FATAL, "skbuff alloc of size %u failed\n", len); @@ -210,7 +210,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); rx_status->band = sc->hw->conf.channel->band; rx_status->freq = sc->hw->conf.channel->center_freq; - rx_status->noise = sc->sc_ani.sc_noise_floor; + rx_status->noise = sc->ani.noise_floor; rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi; rx_status->antenna = ds->ds_rxstat.rs_antenna; @@ -242,13 +242,13 @@ static void ath_opmode_init(struct ath_softc *sc) /* configure bssid mask */ if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) - ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); + ath9k_hw_setbssidmask(ah, sc->bssidmask); /* configure operational mode */ ath9k_hw_setopmode(ah); /* Handle any link-level address change. */ - ath9k_hw_setmac(ah, sc->sc_myaddr); + ath9k_hw_setmac(ah, sc->macaddr); /* calculate and install multicast filter */ mfilt[0] = mfilt[1] = ~0; @@ -267,11 +267,11 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) spin_lock_init(&sc->rx.rxbuflock); sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, - min(sc->sc_cachelsz, + min(sc->cachelsz, (u16)64)); DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", - sc->sc_cachelsz, sc->rx.bufsize); + sc->cachelsz, sc->rx.bufsize); /* Initialize rx descriptors */ @@ -593,7 +593,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) && !decrypt_error && skb->len >= hdrlen + 4) { keyix = skb->data[hdrlen + 3] >> 6; - if (test_bit(keyix, sc->sc_keymap)) + if (test_bit(keyix, sc->keymap)) rx_status.flag |= RX_FLAG_DECRYPTED; } if (ah->sw_mgmt_crypto && diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c index 7a3ea92..7773760 100644 --- a/drivers/net/wireless/ath9k/xmit.c +++ b/drivers/net/wireless/ath9k/xmit.c @@ -970,14 +970,14 @@ int ath_cabq_update(struct ath_softc *sc) /* * Ensure the readytime % is within the bounds. */ - if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) - sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; - else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) - sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; + if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) + sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; + else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) + sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf); qi.tqi_readyTime = - (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100; + (conf.beacon_interval * sc->config.cabqReadytime) / 100; ath_txq_update(sc, qnum, &qi); return 0; @@ -1471,7 +1471,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) flags = ATH9K_TXDESC_RTSENA; /* FIXME: Handle aggregation protection */ - if (sc->sc_config.ath_aggr_prot && + if (sc->config.ath_aggr_prot && (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { flags = ATH9K_TXDESC_RTSENA; } @@ -1486,7 +1486,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) rix = rates[i].idx; series[i].Tries = rates[i].count; - series[i].ChSel = sc->sc_tx_chainmask; + series[i].ChSel = sc->tx_chainmask; if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) series[i].Rate = rt->info[rix].ratecode | @@ -1513,7 +1513,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) !is_pspoll, ctsrate, 0, series, 4, flags); - if (sc->sc_config.ath_aggr_prot && flags) + if (sc->config.ath_aggr_prot && flags) ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); } -- 1.5.6.3 From 4a91e4b6fe6a4f727d83c9db1e8abff735f54d7a Mon Sep 17 00:00:00 2001 From: Sujith Date: Sun, 8 Feb 2009 15:55:06 +0530 Subject: [PATCH] ath9k: Store HW version information in a separate structure This patch moves all the HW version/revision specific information into a separate structure. Signed-off-by: Sujith --- drivers/net/wireless/ath9k/ahb.c | 8 ++-- drivers/net/wireless/ath9k/eeprom.c | 4 +- drivers/net/wireless/ath9k/hw.c | 62 ++++++++++++++++++----------------- drivers/net/wireless/ath9k/hw.h | 21 +++++++----- drivers/net/wireless/ath9k/pci.c | 8 ++-- drivers/net/wireless/ath9k/reg.h | 54 +++++++++++++++++------------- 6 files changed, 84 insertions(+), 73 deletions(-) diff --git a/drivers/net/wireless/ath9k/ahb.c b/drivers/net/wireless/ath9k/ahb.c index 361ace1..d254b35 100644 --- a/drivers/net/wireless/ath9k/ahb.c +++ b/drivers/net/wireless/ath9k/ahb.c @@ -132,10 +132,10 @@ static int ath_ahb_probe(struct platform_device *pdev) "%s: Atheros AR%s MAC/BB Rev:%x, " "AR%s RF Rev:%x, mem=0x%lx, irq=%d\n", wiphy_name(hw->wiphy), - ath_mac_bb_name(ah->ah_macVersion), - ah->ah_macRev, - ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)), - ah->ah_phyRev, + ath_mac_bb_name(ah->hw_version.macVersion), + ah->hw_version.macRev, + ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)), + ah->hw_version.phyRev, (unsigned long)mem, irq); return 0; diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index aa62409..420a060 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -1989,7 +1989,7 @@ static void ath9k_hw_set_def_addac(struct ath_hal *ah, struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; u8 biaslevel; - if (ah->ah_macVersion != AR_SREV_VERSION_9160) + if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) return; if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) @@ -2043,7 +2043,7 @@ static void ath9k_hw_set_4k_addac(struct ath_hal *ah, struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; u8 biaslevel; - if (ah->ah_macVersion != AR_SREV_VERSION_9160) + if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) return; if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 1a6c5ac..164a543 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -229,16 +229,17 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah) if (val == 0xFF) { val = REG_READ(ah, AR_SREV); - ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; - ah->ah_macRev = MS(val, AR_SREV_REVISION2); + ah->hw_version.macVersion = + (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; + ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; } else { if (!AR_SREV_9100(ah)) - ah->ah_macVersion = MS(val, AR_SREV_VERSION); + ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); - ah->ah_macRev = val & AR_SREV_REVISION; + ah->hw_version.macRev = val & AR_SREV_REVISION; - if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) + if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ah->ah_isPciExpress = true; } } @@ -407,14 +408,14 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, ah = &ahp->ah; ah->ah_sc = sc; ah->ah_sh = mem; - ah->ah_magic = AR5416_MAGIC; + ah->hw_version.magic = AR5416_MAGIC; ah->ah_countryCode = CTRY_DEFAULT; - ah->ah_devid = devid; - ah->ah_subvendorid = 0; + ah->hw_version.devid = devid; + ah->hw_version.subvendorid = 0; ah->ah_flags = 0; if ((devid == AR5416_AR9100_DEVID)) - ah->ah_macVersion = AR_SREV_VERSION_9100; + ah->hw_version.macVersion = AR_SREV_VERSION_9100; if (!AR_SREV_9100(ah)) ah->ah_flags = AH_USE_EEPROM; @@ -473,11 +474,11 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah) DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "5G Radio Chip Rev 0x%02X is not " "supported by this driver\n", - ah->ah_analog5GhzRev); + ah->hw_version.analog5GhzRev); return -EOPNOTSUPP; } - ah->ah_analog5GhzRev = val; + ah->hw_version.analog5GhzRev = val; return 0; } @@ -615,7 +616,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { - if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) { + if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) { ah->ah_config.serialize_regmode = SER_REG_MODE_ON; } else { @@ -628,13 +629,14 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, "serialize_regmode is %d\n", ah->ah_config.serialize_regmode); - if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && - (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && - (ah->ah_macVersion != AR_SREV_VERSION_9160) && + if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && + (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && + (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Mac Chip Rev 0x%02x.%x is not supported by " - "this driver\n", ah->ah_macVersion, ah->ah_macRev); + "this driver\n", ah->hw_version.macVersion, + ah->hw_version.macRev); ecode = -EOPNOTSUPP; goto bad; } @@ -644,7 +646,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ahp->ah_suppCals = IQ_MISMATCH_CAL; ah->ah_isPciExpress = false; } - ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID); + ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); if (AR_SREV_9160_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) { @@ -680,7 +682,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, DPRINTF(ah->ah_sc, ATH_DBG_RESET, "This Mac Chip Rev 0x%02x.%x is \n", - ah->ah_macVersion, ah->ah_macRev); + ah->hw_version.macVersion, ah->hw_version.macRev); if (AR_SREV_9285_12_OR_LATER(ah)) { INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2, @@ -830,7 +832,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, if (AR_SREV_9280_20(ah)) ath9k_hw_init_txgain_ini(ah); - if (ah->ah_devid == AR9280_DEVID_PCI) { + if (ah->hw_version.devid == AR9280_DEVID_PCI) { for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); @@ -990,7 +992,7 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah) REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); case 0x3: - if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) { + if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) { REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); break; @@ -1181,7 +1183,7 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, { struct base_eep_header *pBase = &(pEepData->baseEepHeader); - switch (ah->ah_devid) { + switch (ah->hw_version.devid) { case AR9280_DEVID_PCI: if (reg == 0x7894) { DPRINTF(ah->ah_sc, ATH_DBG_ANY, @@ -2438,7 +2440,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, "AES-CCM not supported by mac rev 0x%x\n", - ah->ah_macRev); + ah->hw_version.macRev); return false; } keyType = AR_KEYTABLE_TYPE_CCM; @@ -2687,7 +2689,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) } udelay(1000); } else if (AR_SREV_9280(ah) && - (ah->ah_macRev == AR_SREV_REVISION_9280_10)) { + (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); @@ -3142,7 +3144,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); if (ah->ah_opmode != NL80211_IFTYPE_AP && - ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { + ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65) ah->ah_currentRD += 5; else if (ah->ah_currentRD == 0x41) @@ -3195,7 +3197,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; } - if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0))) + if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; pCap->low_2ghz_chan = 2312; @@ -3276,11 +3278,11 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) } #endif - if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || - (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || - (ah->ah_macVersion == AR_SREV_VERSION_9160) || - (ah->ah_macVersion == AR_SREV_VERSION_9100) || - (ah->ah_macVersion == AR_SREV_VERSION_9280)) + if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || + (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) || + (ah->hw_version.macVersion == AR_SREV_VERSION_9160) || + (ah->hw_version.macVersion == AR_SREV_VERSION_9100) || + (ah->hw_version.macVersion == AR_SREV_VERSION_9280)) pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; else pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index b353b1f..afa64bd 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -406,16 +406,19 @@ enum { ATH9K_RESET_COLD, }; -struct ath_hal { - u32 ah_magic; - u16 ah_devid; - u16 ah_subvendorid; - u32 ah_macVersion; - u16 ah_macRev; - u16 ah_phyRev; - u16 ah_analog5GhzRev; - u16 ah_analog2GhzRev; +struct ath9k_hw_version { + u32 magic; + u16 devid; + u16 subvendorid; + u32 macVersion; + u16 macRev; + u16 phyRev; + u16 analog5GhzRev; + u16 analog2GhzRev; +}; +struct ath_hal { + struct ath9k_hw_version hw_version; void __iomem *ah_sh; struct ath_softc *ah_sc; diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index aa3ac20..192c8c4 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -190,10 +190,10 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) "%s: Atheros AR%s MAC/BB Rev:%x " "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n", wiphy_name(hw->wiphy), - ath_mac_bb_name(ah->ah_macVersion), - ah->ah_macRev, - ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)), - ah->ah_phyRev, + ath_mac_bb_name(ah->hw_version.macVersion), + ah->hw_version.macRev, + ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)), + ah->hw_version.phyRev, (unsigned long)mem, pdev->irq); return 0; diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h index 45b9fbf..17ed190 100644 --- a/drivers/net/wireless/ath9k/reg.h +++ b/drivers/net/wireless/ath9k/reg.h @@ -160,7 +160,7 @@ #define AR_SREV_VERSION_9100 0x014 -#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100) +#define AR_SREV_9100(ah) ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100) #define AR_SREV_5416_V20_OR_LATER(_ah) \ (AR_SREV_9100((_ah)) || AR_SREV_5416_20_OR_LATER(_ah)) #define AR_SREV_5416_V22_OR_LATER(_ah) \ @@ -747,44 +747,50 @@ #define AR_SREV_REVISION_9285_12 2 #define AR_SREV_9100_OR_LATER(_ah) \ - (((_ah)->ah_macVersion >= AR_SREV_VERSION_5416_PCIE)) + (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_5416_PCIE)) #define AR_SREV_5416_20_OR_LATER(_ah) \ - (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160) || \ - ((_ah)->ah_macRev >= AR_SREV_REVISION_5416_20)) + (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160) || \ + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) #define AR_SREV_5416_22_OR_LATER(_ah) \ - (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160) || \ - ((_ah)->ah_macRev >= AR_SREV_REVISION_5416_22)) + (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160) || \ + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) #define AR_SREV_9160(_ah) \ - (((_ah)->ah_macVersion == AR_SREV_VERSION_9160)) + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) #define AR_SREV_9160_10_OR_LATER(_ah) \ - (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160)) + (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160)) #define AR_SREV_9160_11(_ah) \ - (AR_SREV_9160(_ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9160_11)) + (AR_SREV_9160(_ah) && \ + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11)) #define AR_SREV_9280(_ah) \ - (((_ah)->ah_macVersion == AR_SREV_VERSION_9280)) + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) #define AR_SREV_9280_10_OR_LATER(_ah) \ - (((_ah)->ah_macVersion >= AR_SREV_VERSION_9280)) + (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280)) #define AR_SREV_9280_20(_ah) \ - (((_ah)->ah_macVersion == AR_SREV_VERSION_9280) && \ - ((_ah)->ah_macRev >= AR_SREV_REVISION_9280_20)) + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \ + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20)) #define AR_SREV_9280_20_OR_LATER(_ah) \ - (((_ah)->ah_macVersion > AR_SREV_VERSION_9280) || \ - (((_ah)->ah_macVersion == AR_SREV_VERSION_9280) && \ - ((_ah)->ah_macRev >= AR_SREV_REVISION_9280_20))) + (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9280) || \ + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \ + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20))) -#define AR_SREV_9285(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_9285)) +#define AR_SREV_9285(_ah) \ + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285)) #define AR_SREV_9285_10_OR_LATER(_ah) \ - (((_ah)->ah_macVersion >= AR_SREV_VERSION_9285)) + (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285)) #define AR_SREV_9285_11(_ah) \ - (AR_SREV_9280(ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9285_11)) + (AR_SREV_9280(ah) && \ + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_11)) #define AR_SREV_9285_11_OR_LATER(_ah) \ - (((_ah)->ah_macVersion > AR_SREV_VERSION_9285) || \ - (AR_SREV_9285(ah) && ((_ah)->ah_macRev >= AR_SREV_REVISION_9285_11))) + (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \ + (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \ + AR_SREV_REVISION_9285_11))) #define AR_SREV_9285_12(_ah) \ - (AR_SREV_9280(ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9285_12)) + (AR_SREV_9280(ah) && \ + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_12)) #define AR_SREV_9285_12_OR_LATER(_ah) \ - (((_ah)->ah_macVersion > AR_SREV_VERSION_9285) || \ - (AR_SREV_9285(ah) && ((_ah)->ah_macRev >= AR_SREV_REVISION_9285_12))) + (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \ + (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \ + AR_SREV_REVISION_9285_12))) #define AR_RADIO_SREV_MAJOR 0xf0 #define AR_RAD5133_SREV_MAJOR 0xc0 -- 1.5.6.3 From a74d06dd8e357a4dc4e3af40cfc72afb090930c1 Mon Sep 17 00:00:00 2001 From: Sujith Date: Sun, 8 Feb 2009 16:11:12 +0530 Subject: [PATCH] ath9k: Move regulatory information to a separate structure Signed-off-by: Sujith --- drivers/net/wireless/ath9k/eeprom.c | 16 ++++++------ drivers/net/wireless/ath9k/hw.c | 37 ++++++++++++++------------- drivers/net/wireless/ath9k/hw.h | 12 +------- drivers/net/wireless/ath9k/main.c | 2 +- drivers/net/wireless/ath9k/regd.c | 48 +++++++++++++++++----------------- drivers/net/wireless/ath9k/regd.h | 12 ++++++++ 6 files changed, 66 insertions(+), 61 deletions(-) diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 420a060..d58d8a3 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -1232,9 +1232,9 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; - if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) { + if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { maxRegAllowedPower -= - (tpScaleReductionTable[(ah->ah_tpScale)] * 2); + (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); } scaledPower = min(powerLimit, maxRegAllowedPower); @@ -1510,9 +1510,9 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; - if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) { + if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { maxRegAllowedPower -= - (tpScaleReductionTable[(ah->ah_tpScale)] * 2); + (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); } scaledPower = min(powerLimit, maxRegAllowedPower); @@ -1823,10 +1823,10 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah, i = rateHt20_0; if (AR_SREV_9280_10_OR_LATER(ah)) - ah->ah_maxPowerLevel = + ah->regulatory.max_power_level = ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; else - ah->ah_maxPowerLevel = ratesArray[i]; + ah->regulatory.max_power_level = ratesArray[i]; return 0; } @@ -1951,10 +1951,10 @@ static int ath9k_hw_4k_set_txpower(struct ath_hal *ah, i = rateHt20_0; if (AR_SREV_9280_10_OR_LATER(ah)) - ah->ah_maxPowerLevel = + ah->regulatory.max_power_level = ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; else - ah->ah_maxPowerLevel = ratesArray[i]; + ah->regulatory.max_power_level = ratesArray[i]; return 0; } diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 164a543..9eafada 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -409,7 +409,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, ah->ah_sc = sc; ah->ah_sh = mem; ah->hw_version.magic = AR5416_MAGIC; - ah->ah_countryCode = CTRY_DEFAULT; + ah->regulatory.country_code = CTRY_DEFAULT; ah->hw_version.devid = devid; ah->hw_version.subvendorid = 0; @@ -419,8 +419,8 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, if (!AR_SREV_9100(ah)) ah->ah_flags = AH_USE_EEPROM; - ah->ah_powerLimit = MAX_RATE_POWER; - ah->ah_tpScale = ATH9K_TP_SCALE_MAX; + ah->regulatory.power_limit = MAX_RATE_POWER; + ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; ahp->ah_atimWindow = 0; ahp->ah_diversityControl = ah->ah_config.diversity_control; ahp->ah_antennaSwitchSwap = @@ -1337,7 +1337,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, channel->max_antenna_gain * 2, channel->max_power * 2, min((u32) MAX_RATE_POWER, - (u32) ah->ah_powerLimit)); + (u32) ah->regulatory.power_limit)); if (status != 0) { DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "error init'ing transmit power\n"); @@ -1668,7 +1668,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah, channel->max_antenna_gain * 2, channel->max_power * 2, min((u32) MAX_RATE_POWER, - (u32) ah->ah_powerLimit)) != 0) { + (u32) ah->regulatory.power_limit)) != 0) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "error init'ing transmit power\n"); return false; @@ -3136,21 +3136,22 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0); - ah->ah_currentRD = eeval; + ah->regulatory.current_rd = eeval; eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1); - ah->ah_currentRDExt = eeval; + ah->regulatory.current_rd_ext = eeval; capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); if (ah->ah_opmode != NL80211_IFTYPE_AP && ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { - if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65) - ah->ah_currentRD += 5; - else if (ah->ah_currentRD == 0x41) - ah->ah_currentRD = 0x43; + if (ah->regulatory.current_rd == 0x64 || + ah->regulatory.current_rd == 0x65) + ah->regulatory.current_rd += 5; + else if (ah->regulatory.current_rd == 0x41) + ah->regulatory.current_rd = 0x43; DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, - "regdomain mapped to 0x%x\n", ah->ah_currentRD); + "regdomain mapped to 0x%x\n", ah->regulatory.current_rd); } eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); @@ -3292,7 +3293,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) else pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; - if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) { + if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { pCap->reg_cap = AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | @@ -3392,13 +3393,13 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, case 0: return 0; case 1: - *result = ah->ah_powerLimit; + *result = ah->regulatory.power_limit; return 0; case 2: - *result = ah->ah_maxPowerLevel; + *result = ah->regulatory.max_power_level; return 0; case 3: - *result = ah->ah_tpScale; + *result = ah->regulatory.tp_scale; return 0; } return false; @@ -3655,14 +3656,14 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) struct ath9k_channel *chan = ah->ah_curchan; struct ieee80211_channel *channel = chan->chan; - ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER); + ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); if (ath9k_hw_set_txpower(ah, chan, ath9k_regd_get_ctl(ah, chan), channel->max_antenna_gain * 2, channel->max_power * 2, min((u32) MAX_RATE_POWER, - (u32) ah->ah_powerLimit)) != 0) + (u32) ah->regulatory.power_limit)) != 0) return false; return true; diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index afa64bd..3fdf962 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -425,17 +425,9 @@ struct ath_hal { enum nl80211_iftype ah_opmode; struct ath9k_ops_config ah_config; struct ath9k_hw_capabilities ah_caps; - - u16 ah_countryCode; + struct ath9k_regulatory regulatory; u32 ah_flags; - int16_t ah_powerLimit; - u16 ah_maxPowerLevel; - u32 ah_tpScale; - u16 ah_currentRD; - u16 ah_currentRDExt; - u16 ah_currentRDInUse; - char alpha2[2]; - struct reg_dmn_pair_mapping *regpair; + enum ath9k_power_mode ah_power_mode; enum ath9k_power_mode ah_restore_mode; diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index dacf97a..a1c76ec 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -1659,7 +1659,7 @@ int ath_attach(u16 devid, struct ath_softc *sc) error = ieee80211_register_hw(hw); if (!ath9k_is_world_regd(sc->sc_ah)) - regulatory_hint(hw->wiphy, sc->sc_ah->alpha2); + regulatory_hint(hw->wiphy, sc->sc_ah->regulatory.alpha2); /* Initialize LED control */ ath_init_leds(sc); diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c index 819feb9..32dd0cb 100644 --- a/drivers/net/wireless/ath9k/regd.c +++ b/drivers/net/wireless/ath9k/regd.c @@ -108,7 +108,7 @@ static const struct ieee80211_regdomain ath9k_world_regdom_67_68_6A = { static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah) { - return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG; + return ah->regulatory.current_rd & ~WORLDWIDE_ROAMING_FLAG; } u16 ath9k_regd_get_rd(struct ath_hal *ah) @@ -129,7 +129,7 @@ const struct ieee80211_regdomain *ath9k_default_world_regdomain(void) const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah) { - switch (ah->regpair->regDmnEnum) { + switch (ah->regulatory.regpair->regDmnEnum) { case 0x60: case 0x61: case 0x62: @@ -284,7 +284,7 @@ void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby) struct ath_softc *sc = hw->priv; struct ath_hal *ah = sc->sc_ah; - switch (ah->regpair->regDmnEnum) { + switch (ah->regulatory.regpair->regDmnEnum) { case 0x60: case 0x63: case 0x66: @@ -413,30 +413,30 @@ int ath9k_regd_init(struct ath_hal *ah) return -EINVAL; } - ah->ah_countryCode = ath9k_regd_get_default_country(ah); + ah->regulatory.country_code = ath9k_regd_get_default_country(ah); - if (ah->ah_countryCode == CTRY_DEFAULT && + if (ah->regulatory.country_code == CTRY_DEFAULT && ath9k_regd_get_eepromRD(ah) == CTRY_DEFAULT) - ah->ah_countryCode = CTRY_UNITED_STATES; + ah->regulatory.country_code = CTRY_UNITED_STATES; - if (ah->ah_countryCode == CTRY_DEFAULT) { + if (ah->regulatory.country_code == CTRY_DEFAULT) { regdmn = ath9k_regd_get_eepromRD(ah); country = NULL; } else { - country = ath9k_regd_find_country(ah->ah_countryCode); + country = ath9k_regd_find_country(ah->regulatory.country_code); if (country == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Country is NULL!!!!, cc= %d\n", - ah->ah_countryCode); + ah->regulatory.country_code); return -EINVAL; } else regdmn = country->regDmnEnum; } - ah->ah_currentRDInUse = regdmn; - ah->regpair = ath9k_get_regpair(regdmn); + ah->regulatory.current_rd_inuse = regdmn; + ah->regulatory.regpair = ath9k_get_regpair(regdmn); - if (!ah->regpair) { + if (!ah->regulatory.regpair) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "No regulatory domain pair found, cannot continue\n"); return -EINVAL; @@ -446,18 +446,18 @@ int ath9k_regd_init(struct ath_hal *ah) country = ath9k_regd_find_country_by_rd(regdmn); if (country) { - ah->alpha2[0] = country->isoName[0]; - ah->alpha2[1] = country->isoName[1]; + ah->regulatory.alpha2[0] = country->isoName[0]; + ah->regulatory.alpha2[1] = country->isoName[1]; } else { - ah->alpha2[0] = '0'; - ah->alpha2[1] = '0'; + ah->regulatory.alpha2[0] = '0'; + ah->regulatory.alpha2[1] = '0'; } DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Country alpha2 being used: %c%c\n" - "Regpair detected: 0x%0x\n", - ah->alpha2[0], ah->alpha2[1], - ah->regpair->regDmnEnum); + "Regulatory.Regpair detected: 0x%0x\n", + ah->regulatory.alpha2[0], ah->regulatory.alpha2[1], + ah->regulatory.regpair->regDmnEnum); return 0; } @@ -466,8 +466,8 @@ u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan) { u32 ctl = NO_CTL; - if (!ah->regpair || - (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah))) { + if (!ah->regulatory.regpair || + (ah->regulatory.country_code == CTRY_DEFAULT && isWwrSKU(ah))) { if (IS_CHAN_B(chan)) ctl = SD_NO_CTL | CTL_11B; else if (IS_CHAN_G(chan)) @@ -478,11 +478,11 @@ u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan) } if (IS_CHAN_B(chan)) - ctl = ah->regpair->reg_2ghz_ctl | CTL_11B; + ctl = ah->regulatory.regpair->reg_2ghz_ctl | CTL_11B; else if (IS_CHAN_G(chan)) - ctl = ah->regpair->reg_5ghz_ctl | CTL_11G; + ctl = ah->regulatory.regpair->reg_5ghz_ctl | CTL_11G; else - ctl = ah->regpair->reg_5ghz_ctl | CTL_11A; + ctl = ah->regulatory.regpair->reg_5ghz_ctl | CTL_11A; return ctl; } diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h index d1c4457..65abdf4 100644 --- a/drivers/net/wireless/ath9k/regd.h +++ b/drivers/net/wireless/ath9k/regd.h @@ -45,6 +45,18 @@ struct country_code_to_enum_rd { const char *isoName; }; +struct ath9k_regulatory { + char alpha2[2]; + u16 country_code; + u16 max_power_level; + u32 tp_scale; + u16 current_rd; + u16 current_rd_ext; + u16 current_rd_inuse; + int16_t power_limit; + struct reg_dmn_pair_mapping *regpair; +}; + enum CountryCode { CTRY_ALBANIA = 8, CTRY_ALGERIA = 12, -- 1.5.6.3 From 0179f8baa3fa5b54905fc3d7237f3071c9fab457 Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 08:48:01 +0530 Subject: [PATCH] ath9k: Remove duplicate variables A few variables (bssid, bssidmask, curaid) were duplicated in struct ath_softc and in ath_hal, remove them. Signed-off-by: Sujith --- drivers/net/wireless/ath9k/ath9k.h | 1 - drivers/net/wireless/ath9k/hw.c | 71 ++++++++++-------------------------- drivers/net/wireless/ath9k/hw.h | 14 ++----- drivers/net/wireless/ath9k/main.c | 24 +++++++------ drivers/net/wireless/ath9k/recv.c | 4 +- 5 files changed, 38 insertions(+), 76 deletions(-) diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index d60b2e7..03e4d0b 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -580,7 +580,6 @@ struct ath_softc { struct mutex mutex; u8 curbssid[ETH_ALEN]; - u8 macaddr[ETH_ALEN]; u8 bssidmask[ETH_ALEN]; u32 intrstatus; u32 sc_flags; /* SC_OP_* */ diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 9eafada..5d72875 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -392,8 +392,6 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, void __iomem *mem, int *status) { - static const u8 defbssidmask[ETH_ALEN] = - { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; struct ath_hal_5416 *ahp; struct ath_hal *ah; @@ -432,7 +430,6 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, ahp->ah_acktimeout = (u32) -1; ahp->ah_ctstimeout = (u32) -1; ahp->ah_globaltxtimeout = (u32) -1; - memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN); ahp->ah_gBeaconRate = 0; @@ -488,19 +485,18 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah) u32 sum; int i; u16 eeval; - struct ath_hal_5416 *ahp = AH5416(ah); sum = 0; for (i = 0; i < 3; i++) { eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i)); sum += eeval; - ahp->ah_macaddr[2 * i] = eeval >> 8; - ahp->ah_macaddr[2 * i + 1] = eeval & 0xff; + ah->macaddr[2 * i] = eeval >> 8; + ah->macaddr[2 * i + 1] = eeval & 0xff; } if (sum == 0 || sum == 0xffff * 3) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "mac address read failed: %pM\n", - ahp->ah_macaddr); + ah->macaddr); return -EADDRNOTAVAIL; } @@ -2251,8 +2247,8 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, ath9k_hw_decrease_chain_power(ah, chan); - REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr)); - REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4) + REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr)); + REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4) | macStaId1 | AR_STA_ID1_RTS_USE_DEF | (ah->ah_config. @@ -2260,14 +2256,14 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, | ahp->ah_staId1Defaults); ath9k_hw_set_operating_mode(ah, ah->ah_opmode); - REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); - REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); + REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); + REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); - REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid)); - REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) | - ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S)); + REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); + REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) | + ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); REG_WRITE(ah, AR_ISR, ~0); @@ -3669,20 +3665,9 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) return true; } -void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac) -{ - struct ath_hal_5416 *ahp = AH5416(ah); - - memcpy(mac, ahp->ah_macaddr, ETH_ALEN); -} - -bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) +void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) { - struct ath_hal_5416 *ahp = AH5416(ah); - - memcpy(ahp->ah_macaddr, mac, ETH_ALEN); - - return true; + memcpy(ah->macaddr, mac, ETH_ALEN); } void ath9k_hw_setopmode(struct ath_hal *ah) @@ -3696,35 +3681,17 @@ void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1) REG_WRITE(ah, AR_MCAST_FIL1, filter1); } -void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask) +void ath9k_hw_setbssidmask(struct ath_softc *sc) { - struct ath_hal_5416 *ahp = AH5416(ah); - - memcpy(mask, ahp->ah_bssidmask, ETH_ALEN); + REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); + REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); } -bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask) +void ath9k_hw_write_associd(struct ath_softc *sc) { - struct ath_hal_5416 *ahp = AH5416(ah); - - memcpy(ahp->ah_bssidmask, mask, ETH_ALEN); - - REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); - REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); - - return true; -} - -void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId) -{ - struct ath_hal_5416 *ahp = AH5416(ah); - - memcpy(ahp->ah_bssid, bssid, ETH_ALEN); - ahp->ah_assocId = assocId; - - REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid)); - REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) | - ((assocId & 0x3fff) << AR_BSS_ID1_AID_S)); + REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); + REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) | + ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); } u64 ath9k_hw_gettsf64(struct ath_hal *ah) diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 3fdf962..f4bf702 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -427,6 +427,7 @@ struct ath_hal { struct ath9k_hw_capabilities ah_caps; struct ath9k_regulatory regulatory; u32 ah_flags; + u8 macaddr[ETH_ALEN]; enum ath9k_power_mode ah_power_mode; enum ath9k_power_mode ah_restore_mode; @@ -457,11 +458,6 @@ struct ath_hal_5416 { struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; void __iomem *ah_cal_mem; - u8 ah_macaddr[ETH_ALEN]; - u8 ah_bssid[ETH_ALEN]; - u8 ah_bssidmask[ETH_ALEN]; - u16 ah_assocId; - int16_t ah_curchanRadIndex; u32 ah_maskReg; u32 ah_txOkInterruptMask; @@ -633,13 +629,11 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); bool ath9k_hw_phy_disable(struct ath_hal *ah); bool ath9k_hw_disable(struct ath_hal *ah); bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); -void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac); -bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); +void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); void ath9k_hw_setopmode(struct ath_hal *ah); void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); -void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask); -bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask); -void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId); +void ath9k_hw_setbssidmask(struct ath_softc *sc); +void ath9k_hw_write_associd(struct ath_softc *sc); u64 ath9k_hw_gettsf64(struct ath_hal *ah); void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64); void ath9k_hw_reset_tsf(struct ath_hal *ah); diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index a1c76ec..bafefbe 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -905,8 +905,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc, /* New association, store aid */ if (avp->av_opmode == NL80211_IFTYPE_STATION) { sc->curaid = bss_conf->aid; - ath9k_hw_write_associd(sc->sc_ah, sc->curbssid, - sc->curaid); + ath9k_hw_write_associd(sc); } /* Configure the beacon */ @@ -1514,11 +1513,10 @@ static int ath_init(u16 devid, struct ath_softc *sc) ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); sc->rx.defant = ath9k_hw_getdefantenna(ah); - ath9k_hw_getmac(ah, sc->macaddr); if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { - ath9k_hw_getbssidmask(ah, sc->bssidmask); + memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); ATH_SET_VIF_BSSID_MASK(sc->bssidmask); - ath9k_hw_setbssidmask(ah, sc->bssidmask); + ath9k_hw_setbssidmask(sc); } sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ @@ -1577,7 +1575,7 @@ int ath_attach(u16 devid, struct ath_softc *sc) /* get mac address from hardware and set in mac80211 */ - SET_IEEE80211_PERM_ADDR(hw, sc->macaddr); + SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr); hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | @@ -2285,7 +2283,9 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, ah->ah_opmode != NL80211_IFTYPE_AP) { ah->ah_opmode = NL80211_IFTYPE_STATION; ath9k_hw_setopmode(ah); - ath9k_hw_write_associd(ah, sc->macaddr, 0); + memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); + sc->curaid = 0; + ath9k_hw_write_associd(sc); /* Request full reset to get hw opmode changed properly */ sc->sc_flags |= SC_OP_FULL_RESET; } @@ -2298,8 +2298,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, /* Set BSSID */ memcpy(sc->curbssid, conf->bssid, ETH_ALEN); sc->curaid = 0; - ath9k_hw_write_associd(sc->sc_ah, sc->curbssid, - sc->curaid); + ath9k_hw_write_associd(sc); /* Set aggregation protection mode parameters */ sc->config.ath_aggr_prot = 0; @@ -2382,8 +2381,11 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw, ath9k_hw_setrxfilter(sc->sc_ah, rfilt); if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { - if (*total_flags & FIF_BCN_PRBRESP_PROMISC) - ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0); + if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { + memcpy(sc->curbssid, ath_bcast_mac, ETH_ALEN); + sc->curaid = 0; + ath9k_hw_write_associd(sc); + } } DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter); diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index e8e4a32..c51c085 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -242,13 +242,13 @@ static void ath_opmode_init(struct ath_softc *sc) /* configure bssid mask */ if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) - ath9k_hw_setbssidmask(ah, sc->bssidmask); + ath9k_hw_setbssidmask(sc); /* configure operational mode */ ath9k_hw_setopmode(ah); /* Handle any link-level address change. */ - ath9k_hw_setmac(ah, sc->macaddr); + ath9k_hw_setmac(ah, sc->sc_ah->macaddr); /* calculate and install multicast filter */ mfilt[0] = mfilt[1] = ~0; -- 1.5.6.3 From 8e33b66a930f7d0c279785f6d9bef05511705743 Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 09:56:52 +0530 Subject: [PATCH] ath9k: Merge ath_hal and ath_hal_5416 structures Finally, merge these structures and have a single HW specific data structure. Signed-off-by: Sujith --- drivers/net/wireless/ath9k/ahb.c | 4 +- drivers/net/wireless/ath9k/ani.c | 232 ++++++------- drivers/net/wireless/ath9k/ani.h | 22 +- drivers/net/wireless/ath9k/ath9k.h | 6 +- drivers/net/wireless/ath9k/beacon.c | 12 +- drivers/net/wireless/ath9k/calib.c | 175 ++++----- drivers/net/wireless/ath9k/calib.h | 20 +- drivers/net/wireless/ath9k/debug.c | 2 +- drivers/net/wireless/ath9k/eeprom.c | 251 ++++++-------- drivers/net/wireless/ath9k/eeprom.h | 36 +- drivers/net/wireless/ath9k/hw.c | 675 ++++++++++++++++------------------- drivers/net/wireless/ath9k/hw.h | 134 ++++---- drivers/net/wireless/ath9k/mac.c | 144 ++++---- drivers/net/wireless/ath9k/mac.h | 64 ++-- drivers/net/wireless/ath9k/main.c | 22 +- drivers/net/wireless/ath9k/pci.c | 4 +- drivers/net/wireless/ath9k/phy.c | 194 +++++------ drivers/net/wireless/ath9k/phy.h | 14 +- drivers/net/wireless/ath9k/recv.c | 10 +- drivers/net/wireless/ath9k/regd.c | 18 +- drivers/net/wireless/ath9k/regd.h | 14 +- drivers/net/wireless/ath9k/xmit.c | 12 +- 22 files changed, 956 insertions(+), 1109 deletions(-) diff --git a/drivers/net/wireless/ath9k/ahb.c b/drivers/net/wireless/ath9k/ahb.c index d254b35..391c9fd 100644 --- a/drivers/net/wireless/ath9k/ahb.c +++ b/drivers/net/wireless/ath9k/ahb.c @@ -32,7 +32,7 @@ static void ath_ahb_cleanup(struct ath_softc *sc) iounmap(sc->mem); } -static bool ath_ahb_eeprom_read(struct ath_hal *ah, u32 off, u16 *data) +static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) { struct ath_softc *sc = ah->ah_sc; struct platform_device *pdev = to_platform_device(sc->dev); @@ -65,7 +65,7 @@ static int ath_ahb_probe(struct platform_device *pdev) struct resource *res; int irq; int ret = 0; - struct ath_hal *ah; + struct ath_hw *ah; if (!pdev->dev.platform_data) { dev_err(&pdev->dev, "no platform data specified\n"); diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index 9cebf0e..6bd2d57 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c @@ -16,18 +16,17 @@ #include "ath9k.h" -static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, +static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; - for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { - if (ahp->ah_ani[i].c && - ahp->ah_ani[i].c->channel == chan->channel) + for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { + if (ah->ah_ani[i].c && + ah->ah_ani[i].c->channel == chan->channel) return i; - if (ahp->ah_ani[i].c == NULL) { - ahp->ah_ani[i].c = chan; + if (ah->ah_ani[i].c == NULL) { + ah->ah_ani[i].c = chan; return i; } } @@ -38,41 +37,40 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, return 0; } -static bool ath9k_hw_ani_control(struct ath_hal *ah, +static bool ath9k_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416AniState *aniState = ahp->ah_curani; + struct ar5416AniState *aniState = ah->ah_curani; - switch (cmd & ahp->ah_ani_function) { + switch (cmd & ah->ah_ani_function) { case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ u32 level = param; - if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { + if (level >= ARRAY_SIZE(ah->ah_totalSizeDesired)) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "level out of range (%u > %u)\n", level, - (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); + (unsigned)ARRAY_SIZE(ah->ah_totalSizeDesired)); return false; } REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_TOT_DES, - ahp->ah_totalSizeDesired[level]); + ah->ah_totalSizeDesired[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_LOW, - ahp->ah_coarseLow[level]); + ah->ah_coarseLow[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_HIGH, - ahp->ah_coarseHigh[level]); + ah->ah_coarseHigh[level]); REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, - ahp->ah_firpwr[level]); + ah->ah_firpwr[level]); if (level > aniState->noiseImmunityLevel) - ahp->ah_stats.ast_ani_niup++; + ah->ah_stats.ast_ani_niup++; else if (level < aniState->noiseImmunityLevel) - ahp->ah_stats.ast_ani_nidown++; + ah->ah_stats.ast_ani_nidown++; aniState->noiseImmunityLevel = level; break; } @@ -126,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, if (!on != aniState->ofdmWeakSigDetectOff) { if (on) - ahp->ah_stats.ast_ani_ofdmon++; + ah->ah_stats.ast_ani_ofdmon++; else - ahp->ah_stats.ast_ani_ofdmoff++; + ah->ah_stats.ast_ani_ofdmoff++; aniState->ofdmWeakSigDetectOff = !on; } break; @@ -142,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, weakSigThrCck[high]); if (high != aniState->cckWeakSigThreshold) { if (high) - ahp->ah_stats.ast_ani_cckhigh++; + ah->ah_stats.ast_ani_cckhigh++; else - ahp->ah_stats.ast_ani_ccklow++; + ah->ah_stats.ast_ani_ccklow++; aniState->cckWeakSigThreshold = high; } break; @@ -164,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, AR_PHY_FIND_SIG_FIRSTEP, firstep[level]); if (level > aniState->firstepLevel) - ahp->ah_stats.ast_ani_stepup++; + ah->ah_stats.ast_ani_stepup++; else if (level < aniState->firstepLevel) - ahp->ah_stats.ast_ani_stepdown++; + ah->ah_stats.ast_ani_stepdown++; aniState->firstepLevel = level; break; } @@ -187,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, AR_PHY_TIMING5_CYCPWR_THR1, cycpwrThr1[level]); if (level > aniState->spurImmunityLevel) - ahp->ah_stats.ast_ani_spurup++; + ah->ah_stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) - ahp->ah_stats.ast_ani_spurdown++; + ah->ah_stats.ast_ani_spurdown++; aniState->spurImmunityLevel = level; break; } @@ -220,7 +218,7 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, return true; } -static void ath9k_hw_update_mibstats(struct ath_hal *ah, +static void ath9k_hw_update_mibstats(struct ath_hw *ah, struct ath9k_mib_stats *stats) { stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); @@ -230,18 +228,17 @@ static void ath9k_hw_update_mibstats(struct ath_hal *ah, stats->beacons += REG_READ(ah, AR_BEACON_CNT); } -static void ath9k_ani_restart(struct ath_hal *ah) +static void ath9k_ani_restart(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; aniState->listenTime = 0; - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { aniState->ofdmPhyErrBase = 0; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -267,15 +264,14 @@ static void ath9k_ani_restart(struct ath_hal *ah) REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); } aniState->ofdmPhyErrCount = 0; aniState->cckPhyErrCount = 0; } -static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) +static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; struct ar5416AniState *aniState; int32_t rssi; @@ -283,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, @@ -306,7 +302,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) } return; } - rssi = BEACON_RSSI(ahp); + rssi = BEACON_RSSI(ah); if (rssi > aniState->rssiThrHigh) { if (!aniState->ofdmWeakSigDetectOff) { if (ath9k_hw_ani_control(ah, @@ -345,9 +341,8 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) } } -static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) +static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; struct ar5416AniState *aniState; int32_t rssi; @@ -355,7 +350,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel + 1)) { @@ -369,7 +364,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) } return; } - rssi = BEACON_RSSI(ahp); + rssi = BEACON_RSSI(ah); if (rssi > aniState->rssiThrLow) { if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, @@ -383,13 +378,12 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) } } -static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) +static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; int32_t rssi; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (ah->ah_opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel > 0) { @@ -398,7 +392,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) return; } } else { - rssi = BEACON_RSSI(ahp); + rssi = BEACON_RSSI(ah); if (rssi > aniState->rssiThrHigh) { /* XXX: Handle me */ } else if (rssi > aniState->rssiThrLow) { @@ -437,9 +431,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) } } -static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) +static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; u32 txFrameCount, rxFrameCount, cycleCount; int32_t listenTime; @@ -448,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) rxFrameCount = REG_READ(ah, AR_RFCNT); cycleCount = REG_READ(ah, AR_CCCNT); - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { listenTime = 0; - ahp->ah_stats.ast_ani_lzero++; + ah->ah_stats.ast_ani_lzero++; } else { int32_t ccdelta = cycleCount - aniState->cycleCount; int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; @@ -466,9 +459,8 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) return listenTime; } -void ath9k_ani_reset(struct ath_hal *ah) +void ath9k_ani_reset(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; struct ath9k_channel *chan = ah->ah_curchan; int index; @@ -477,14 +469,14 @@ void ath9k_ani_reset(struct ath_hal *ah) return; index = ath9k_hw_get_ani_channel_idx(ah, chan); - aniState = &ahp->ah_ani[index]; - ahp->ah_curani = aniState; + aniState = &ah->ah_ani[index]; + ah->ah_curani = aniState; if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Reset ANI state opmode %u\n", ah->ah_opmode); - ahp->ah_stats.ast_ani_reset++; + ah->ah_stats.ast_ani_reset++; ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); @@ -498,13 +490,13 @@ void ath9k_ani_reset(struct ath_hal *ah) ATH9K_RX_FILTER_PHYERR); if (ah->ah_opmode == NL80211_IFTYPE_AP) { - ahp->ah_curani->ofdmTrigHigh = + ah->ah_curani->ofdmTrigHigh = ah->ah_config.ofdm_trig_high; - ahp->ah_curani->ofdmTrigLow = + ah->ah_curani->ofdmTrigLow = ah->ah_config.ofdm_trig_low; - ahp->ah_curani->cckTrigHigh = + ah->ah_curani->cckTrigHigh = ah->ah_config.cck_trig_high; - ahp->ah_curani->cckTrigLow = + ah->ah_curani->cckTrigLow = ah->ah_config.cck_trig_low; } ath9k_ani_restart(ah); @@ -526,7 +518,7 @@ void ath9k_ani_reset(struct ath_hal *ah) if (aniState->firstepLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel); - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & ~ATH9K_RX_FILTER_PHYERR); ath9k_ani_restart(ah); @@ -540,34 +532,33 @@ void ath9k_ani_reset(struct ath_hal *ah) } } -void ath9k_hw_ani_monitor(struct ath_hal *ah, +void ath9k_hw_ani_monitor(struct ath_hw *ah, const struct ath9k_node_stats *stats, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; int32_t listenTime; if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; - ahp->ah_stats.ast_nodestats = *stats; + aniState = ah->ah_curani; + ah->ah_stats.ast_nodestats = *stats; listenTime = ath9k_hw_ani_get_listen_time(ah); if (listenTime < 0) { - ahp->ah_stats.ast_ani_lneg++; + ah->ah_stats.ast_ani_lneg++; ath9k_ani_restart(ah); return; } aniState->listenTime += listenTime; - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { u32 phyCnt1, phyCnt2; u32 ofdmPhyErrCnt, cckPhyErrCnt; - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); @@ -600,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, } ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ahp->ah_stats.ast_ani_ofdmerrs += + ah->ah_stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ahp->ah_stats.ast_ani_cckerrs += + ah->ah_stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; } - if (aniState->listenTime > 5 * ahp->ah_aniPeriod) { + if (aniState->listenTime > 5 * ah->ah_aniPeriod) { if (aniState->ofdmPhyErrCount <= aniState->listenTime * aniState->ofdmTrigLow / 1000 && aniState->cckPhyErrCount <= aniState->listenTime * aniState->cckTrigLow / 1000) ath9k_hw_ani_lower_immunity(ah); ath9k_ani_restart(ah); - } else if (aniState->listenTime > ahp->ah_aniPeriod) { + } else if (aniState->listenTime > ah->ah_aniPeriod) { if (aniState->ofdmPhyErrCount > aniState->listenTime * aniState->ofdmTrigHigh / 1000) { ath9k_hw_ani_ofdm_err_trigger(ah); @@ -631,20 +622,16 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, } } -bool ath9k_hw_phycounters(struct ath_hal *ah) +bool ath9k_hw_phycounters(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ahp->ah_hasHwPhyCounters ? true : false; + return ah->ah_hasHwPhyCounters ? true : false; } -void ath9k_enable_mib_counters(struct ath_hal *ah) +void ath9k_enable_mib_counters(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); REG_WRITE(ah, AR_FILT_OFDM, 0); REG_WRITE(ah, AR_FILT_CCK, 0); @@ -655,21 +642,19 @@ void ath9k_enable_mib_counters(struct ath_hal *ah) REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); } -void ath9k_hw_disable_mib_counters(struct ath_hal *ah) +void ath9k_hw_disable_mib_counters(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); REG_WRITE(ah, AR_FILT_OFDM, 0); REG_WRITE(ah, AR_FILT_CCK, 0); } -u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, +u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, u32 *rxf_pcnt, u32 *txf_pcnt) @@ -714,10 +699,9 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, * any of the MIB counters overflow/trigger so don't assume we're * here because a PHY error counter triggered. */ -void ath9k_hw_procmibevent(struct ath_hal *ah, +void ath9k_hw_procmibevent(struct ath_hw *ah, const struct ath9k_node_stats *stats) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 phyCnt1, phyCnt2; /* Reset these counters regardless */ @@ -727,8 +711,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); /* Clear the mib counters and save them in the stats */ - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); - ahp->ah_stats.ast_nodestats = *stats; + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); + ah->ah_stats.ast_nodestats = *stats; if (!DO_ANI(ah)) return; @@ -738,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { - struct ar5416AniState *aniState = ahp->ah_curani; + struct ar5416AniState *aniState = ah->ah_curani; u32 ofdmPhyErrCnt, cckPhyErrCnt; /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ahp->ah_stats.ast_ani_ofdmerrs += + ah->ah_stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ahp->ah_stats.ast_ani_cckerrs += + ah->ah_stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; @@ -767,9 +751,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, } } -void ath9k_hw_ani_setup(struct ath_hal *ah) +void ath9k_hw_ani_setup(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; @@ -778,66 +761,63 @@ void ath9k_hw_ani_setup(struct ath_hal *ah) const int firpwr[] = { -78, -78, -78, -78, -80 }; for (i = 0; i < 5; i++) { - ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; - ahp->ah_coarseHigh[i] = coarseHigh[i]; - ahp->ah_coarseLow[i] = coarseLow[i]; - ahp->ah_firpwr[i] = firpwr[i]; + ah->ah_totalSizeDesired[i] = totalSizeDesired[i]; + ah->ah_coarseHigh[i] = coarseHigh[i]; + ah->ah_coarseLow[i] = coarseLow[i]; + ah->ah_firpwr[i] = firpwr[i]; } } -void ath9k_hw_ani_attach(struct ath_hal *ah) +void ath9k_hw_ani_attach(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); - ahp->ah_hasHwPhyCounters = 1; - - memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani)); - for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { - ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; - ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; - ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; - ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; - ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; - ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; - ahp->ah_ani[i].ofdmWeakSigDetectOff = + ah->ah_hasHwPhyCounters = 1; + + memset(ah->ah_ani, 0, sizeof(ah->ah_ani)); + for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { + ah->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; + ah->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; + ah->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; + ah->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; + ah->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; + ah->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; + ah->ah_ani[i].ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; - ahp->ah_ani[i].cckWeakSigThreshold = + ah->ah_ani[i].cckWeakSigThreshold = ATH9K_ANI_CCK_WEAK_SIG_THR; - ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; - ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; - if (ahp->ah_hasHwPhyCounters) { - ahp->ah_ani[i].ofdmPhyErrBase = + ah->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; + ah->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; + if (ah->ah_hasHwPhyCounters) { + ah->ah_ani[i].ofdmPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; - ahp->ah_ani[i].cckPhyErrBase = + ah->ah_ani[i].cckPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; } } - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n", - ahp->ah_ani[0].ofdmPhyErrBase); + ah->ah_ani[0].ofdmPhyErrBase); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", - ahp->ah_ani[0].cckPhyErrBase); + ah->ah_ani[0].cckPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_1, ah->ah_ani[0].ofdmPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_2, ah->ah_ani[0].cckPhyErrBase); ath9k_enable_mib_counters(ah); } - ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; + ah->ah_aniPeriod = ATH9K_ANI_PERIOD; if (ah->ah_config.enable_ani) - ahp->ah_procPhyErr |= HAL_PROCESS_ANI; + ah->ah_procPhyErr |= HAL_PROCESS_ANI; } -void ath9k_hw_ani_detach(struct ath_hal *ah) +void ath9k_hw_ani_detach(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { ath9k_hw_disable_mib_counters(ah); REG_WRITE(ah, AR_PHY_ERR_1, 0); REG_WRITE(ah, AR_PHY_ERR_2, 0); diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h index 78880e5..7e9ca95 100644 --- a/drivers/net/wireless/ath9k/ani.h +++ b/drivers/net/wireless/ath9k/ani.h @@ -20,7 +20,7 @@ #define HAL_PROCESS_ANI 0x00000001 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) -#define DO_ANI(ah) ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) +#define DO_ANI(ah) (((ah)->ah_procPhyErr & HAL_PROCESS_ANI)) #define HAL_EP_RND(x, mul) \ ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) @@ -120,19 +120,19 @@ struct ar5416Stats { }; #define ah_mibStats ah_stats.ast_mibstats -void ath9k_ani_reset(struct ath_hal *ah); -void ath9k_hw_ani_monitor(struct ath_hal *ah, +void ath9k_ani_reset(struct ath_hw *ah); +void ath9k_hw_ani_monitor(struct ath_hw *ah, const struct ath9k_node_stats *stats, struct ath9k_channel *chan); -bool ath9k_hw_phycounters(struct ath_hal *ah); -void ath9k_enable_mib_counters(struct ath_hal *ah); -void ath9k_hw_disable_mib_counters(struct ath_hal *ah); -u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, u32 *rxc_pcnt, +bool ath9k_hw_phycounters(struct ath_hw *ah); +void ath9k_enable_mib_counters(struct ath_hw *ah); +void ath9k_hw_disable_mib_counters(struct ath_hw *ah); +u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, u32 *rxf_pcnt, u32 *txf_pcnt); -void ath9k_hw_procmibevent(struct ath_hal *ah, +void ath9k_hw_procmibevent(struct ath_hw *ah, const struct ath9k_node_stats *stats); -void ath9k_hw_ani_setup(struct ath_hal *ah); -void ath9k_hw_ani_attach(struct ath_hal *ah); -void ath9k_hw_ani_detach(struct ath_hal *ah); +void ath9k_hw_ani_setup(struct ath_hw *ah); +void ath9k_hw_ani_attach(struct ath_hw *ah); +void ath9k_hw_ani_detach(struct ath_hw *ah); #endif /* ANI_H */ diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 03e4d0b..91140b7 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -455,7 +455,7 @@ struct ath_beacon { void ath9k_beacon_tasklet(unsigned long data); void ath_beacon_config(struct ath_softc *sc, int if_id); -int ath_beaconq_setup(struct ath_hal *ah); +int ath_beaconq_setup(struct ath_hw *ah); int ath_beacon_alloc(struct ath_softc *sc, int if_id); void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); void ath_beacon_sync(struct ath_softc *sc, int if_id); @@ -565,7 +565,7 @@ struct ath_rfkill { struct ath_bus_ops { void (*read_cachesize)(struct ath_softc *sc, int *csz); void (*cleanup)(struct ath_softc *sc); - bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data); + bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data); }; struct ath_softc { @@ -573,7 +573,7 @@ struct ath_softc { struct device *dev; struct tasklet_struct intr_tq; struct tasklet_struct bcon_tasklet; - struct ath_hal *sc_ah; + struct ath_hw *sc_ah; void __iomem *mem; int irq; spinlock_t sc_resetlock; diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 139bba7..19ec4e8 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -23,7 +23,7 @@ */ static int ath_beaconq_config(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath9k_tx_queue_info qi; ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); @@ -66,7 +66,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp, struct ath_buf *bf) { struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_desc *ds; struct ath9k_11n_rate_series series[4]; struct ath_rate_table *rt; @@ -248,7 +248,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) { struct ieee80211_vif *vif; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf; struct ath_vif *avp; struct sk_buff *skb; @@ -276,7 +276,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); } -int ath_beaconq_setup(struct ath_hal *ah) +int ath_beaconq_setup(struct ath_hw *ah) { struct ath9k_tx_queue_info qi; @@ -444,7 +444,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp) void ath9k_beacon_tasklet(unsigned long data) { struct ath_softc *sc = (struct ath_softc *)data; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf = NULL; int slot, if_id; u32 bfaddr; @@ -619,7 +619,7 @@ void ath9k_beacon_tasklet(unsigned long data) void ath_beacon_config(struct ath_softc *sc, int if_id) { struct ieee80211_vif *vif; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_beacon_config conf; struct ath_vif *avp; enum nl80211_iftype opmode; diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 016302c..8c44d5a 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -23,7 +23,7 @@ * is incorrect and we should use the static NF value. Later we can try to * find out why they are reporting these values */ -static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf) +static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) { if (nf > ATH9K_NF_TOO_LOW) { DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, @@ -86,7 +86,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h, return; } -static void ath9k_hw_do_getnf(struct ath_hal *ah, +static void ath9k_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]) { int16_t nf; @@ -166,7 +166,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah, } } -static bool getNoiseFloorThresh(struct ath_hal *ah, +static bool getNoiseFloorThresh(struct ath_hw *ah, enum ieee80211_band band, int16_t *nft) { @@ -185,7 +185,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah, return true; } -static void ath9k_hw_setup_calibration(struct ath_hal *ah, +static void ath9k_hw_setup_calibration(struct ath_hw *ah, struct hal_cal_list *currCal) { REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), @@ -219,10 +219,9 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah, AR_PHY_TIMING_CTRL4_DO_CAL); } -static void ath9k_hw_reset_calibration(struct ath_hal *ah, +static void ath9k_hw_reset_calibration(struct ath_hw *ah, struct hal_cal_list *currCal) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; ath9k_hw_setup_calibration(ah, currCal); @@ -230,23 +229,21 @@ static void ath9k_hw_reset_calibration(struct ath_hal *ah, currCal->calState = CAL_RUNNING; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_Meas0.sign[i] = 0; - ahp->ah_Meas1.sign[i] = 0; - ahp->ah_Meas2.sign[i] = 0; - ahp->ah_Meas3.sign[i] = 0; + ah->ah_Meas0.sign[i] = 0; + ah->ah_Meas1.sign[i] = 0; + ah->ah_Meas2.sign[i] = 0; + ah->ah_Meas3.sign[i] = 0; } - ahp->ah_CalSamples = 0; + ah->ah_CalSamples = 0; } -static void ath9k_hw_per_calibration(struct ath_hal *ah, +static void ath9k_hw_per_calibration(struct ath_hw *ah, struct ath9k_channel *ichan, u8 rxchainmask, struct hal_cal_list *currCal, bool *isCalDone) { - struct ath_hal_5416 *ahp = AH5416(ah); - *isCalDone = false; if (currCal->calState == CAL_RUNNING) { @@ -254,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah, AR_PHY_TIMING_CTRL4_DO_CAL)) { currCal->calData->calCollect(ah); - ahp->ah_CalSamples++; + ah->ah_CalSamples++; - if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) { + if (ah->ah_CalSamples >= currCal->calData->calNumSamples) { int i, numChains = 0; for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (rxchainmask & (1 << i)) @@ -277,13 +274,12 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah, } /* Assumes you are talking about the currently configured channel */ -static bool ath9k_hw_iscal_supported(struct ath_hal *ah, +static bool ath9k_hw_iscal_supported(struct ath_hw *ah, enum hal_cal_types calType) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - switch (calType & ahp->ah_suppCals) { + switch (calType & ah->ah_suppCals) { case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ return true; case ADC_GAIN_CAL: @@ -296,90 +292,86 @@ static bool ath9k_hw_iscal_supported(struct ath_hal *ah, return false; } -static void ath9k_hw_iqcal_collect(struct ath_hal *ah) +static void ath9k_hw_iqcal_collect(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_totalPowerMeasI[i] += + ah->ah_totalPowerMeasI[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ahp->ah_totalPowerMeasQ[i] += + ah->ah_totalPowerMeasQ[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ahp->ah_totalIqCorrMeas[i] += + ah->ah_totalIqCorrMeas[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", - ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i], - ahp->ah_totalPowerMeasQ[i], - ahp->ah_totalIqCorrMeas[i]); + ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i], + ah->ah_totalPowerMeasQ[i], + ah->ah_totalIqCorrMeas[i]); } } -static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) +static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_totalAdcIOddPhase[i] += + ah->ah_totalAdcIOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ahp->ah_totalAdcIEvenPhase[i] += + ah->ah_totalAdcIEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ahp->ah_totalAdcQOddPhase[i] += + ah->ah_totalAdcQOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ahp->ah_totalAdcQEvenPhase[i] += + ah->ah_totalAdcQEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ahp->ah_CalSamples, i, - ahp->ah_totalAdcIOddPhase[i], - ahp->ah_totalAdcIEvenPhase[i], - ahp->ah_totalAdcQOddPhase[i], - ahp->ah_totalAdcQEvenPhase[i]); + ah->ah_CalSamples, i, + ah->ah_totalAdcIOddPhase[i], + ah->ah_totalAdcIEvenPhase[i], + ah->ah_totalAdcQOddPhase[i], + ah->ah_totalAdcQEvenPhase[i]); } } -static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah) +static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_totalAdcDcOffsetIOddPhase[i] += + ah->ah_totalAdcDcOffsetIOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ahp->ah_totalAdcDcOffsetIEvenPhase[i] += + ah->ah_totalAdcDcOffsetIEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ahp->ah_totalAdcDcOffsetQOddPhase[i] += + ah->ah_totalAdcDcOffsetQOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ahp->ah_totalAdcDcOffsetQEvenPhase[i] += + ah->ah_totalAdcDcOffsetQEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ahp->ah_CalSamples, i, - ahp->ah_totalAdcDcOffsetIOddPhase[i], - ahp->ah_totalAdcDcOffsetIEvenPhase[i], - ahp->ah_totalAdcDcOffsetQOddPhase[i], - ahp->ah_totalAdcDcOffsetQEvenPhase[i]); + ah->ah_CalSamples, i, + ah->ah_totalAdcDcOffsetIOddPhase[i], + ah->ah_totalAdcDcOffsetIEvenPhase[i], + ah->ah_totalAdcDcOffsetQOddPhase[i], + ah->ah_totalAdcDcOffsetQEvenPhase[i]); } } -static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) +static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 powerMeasQ, powerMeasI, iqCorrMeas; u32 qCoffDenom, iCoffDenom; int32_t qCoff, iCoff; int iqCorrNeg, i; for (i = 0; i < numChains; i++) { - powerMeasI = ahp->ah_totalPowerMeasI[i]; - powerMeasQ = ahp->ah_totalPowerMeasQ[i]; - iqCorrMeas = ahp->ah_totalIqCorrMeas[i]; + powerMeasI = ah->ah_totalPowerMeasI[i]; + powerMeasQ = ah->ah_totalPowerMeasQ[i]; + iqCorrMeas = ah->ah_totalIqCorrMeas[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting IQ Cal and Correction for Chain %d\n", @@ -387,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Orignal: Chn %diq_corr_meas = 0x%08x\n", - i, ahp->ah_totalIqCorrMeas[i]); + i, ah->ah_totalIqCorrMeas[i]); iqCorrNeg = 0; @@ -445,17 +437,16 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); } -static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) +static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; u32 qGainMismatch, iGainMismatch, val, i; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i]; - iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i]; - qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i]; - qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i]; + iOddMeasOffset = ah->ah_totalAdcIOddPhase[i]; + iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i]; + qOddMeasOffset = ah->ah_totalAdcQOddPhase[i]; + qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC Gain Cal for Chain %d\n", i); @@ -503,21 +494,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); } -static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) +static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 iOddMeasOffset, iEvenMeasOffset, val, i; int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; const struct hal_percal_data *calData = - ahp->ah_cal_list_curr->calData; + ah->ah_cal_list_curr->calData; u32 numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i]; - iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i]; - qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i]; - qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i]; + iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i]; + iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i]; + qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i]; + qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC DC Offset Cal for Chain %d\n", i); @@ -562,11 +552,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) } /* This is done for the currently configured channel */ -bool ath9k_hw_reset_calvalid(struct ath_hal *ah) +bool ath9k_hw_reset_calvalid(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - struct hal_cal_list *currCal = ahp->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->ah_cal_list_curr; if (!ah->ah_curchan) return true; @@ -597,7 +586,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hal *ah) return false; } -void ath9k_hw_start_nfcal(struct ath_hal *ah) +void ath9k_hw_start_nfcal(struct ath_hw *ah) { REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); @@ -606,7 +595,7 @@ void ath9k_hw_start_nfcal(struct ath_hal *ah) REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); } -void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) +void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) { struct ath9k_nfcal_hist *h; int i, j; @@ -662,7 +651,7 @@ void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) } } -int16_t ath9k_hw_getnf(struct ath_hal *ah, +int16_t ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) { int16_t nf, nfThresh; @@ -698,7 +687,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah, return chan->rawNoiseFloor; } -void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) +void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah) { int i, j; @@ -712,10 +701,9 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) AR_PHY_CCA_MAX_GOOD_VALUE; } } - return; } -s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) +s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) { s16 nf; @@ -730,12 +718,11 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) return nf; } -bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, +bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct hal_cal_list *currCal = ahp->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->ah_cal_list_curr; *isCalDone = true; @@ -745,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, isCalDone); if (*isCalDone) { - ahp->ah_cal_list_curr = currCal = currCal->calNext; + ah->ah_cal_list_curr = currCal = currCal->calNext; if (currCal->calState == CAL_WAITING) { *isCalDone = false; @@ -766,7 +753,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, return true; } -static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah) +static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah) { u32 regVal; @@ -861,11 +848,9 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah) } -bool ath9k_hw_init_cal(struct ath_hal *ah, +bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - REG_WRITE(ah, AR_PHY_AGC_CONTROL, REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); @@ -884,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hal *ah, REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); - ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL; + ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL; if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { - INIT_CAL(&ahp->ah_adcGainCalData); - INSERT_CAL(ahp, &ahp->ah_adcGainCalData); + INIT_CAL(&ah->ah_adcGainCalData); + INSERT_CAL(ah, &ah->ah_adcGainCalData); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC Gain Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { - INIT_CAL(&ahp->ah_adcDcCalData); - INSERT_CAL(ahp, &ahp->ah_adcDcCalData); + INIT_CAL(&ah->ah_adcDcCalData); + INSERT_CAL(ah, &ah->ah_adcDcCalData); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC DC Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { - INIT_CAL(&ahp->ah_iqCalData); - INSERT_CAL(ahp, &ahp->ah_iqCalData); + INIT_CAL(&ah->ah_iqCalData); + INSERT_CAL(ah, &ah->ah_iqCalData); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling IQ Calibration.\n"); } - ahp->ah_cal_list_curr = ahp->ah_cal_list; + ah->ah_cal_list_curr = ah->ah_cal_list; - if (ahp->ah_cal_list_curr) - ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr); + if (ah->ah_cal_list_curr) + ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr); } chan->CalValid = 0; diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h index ac7d88f..e2c6140 100644 --- a/drivers/net/wireless/ath9k/calib.h +++ b/drivers/net/wireless/ath9k/calib.h @@ -91,8 +91,8 @@ struct hal_percal_data { enum hal_cal_types calType; u32 calNumSamples; u32 calCountMax; - void (*calCollect) (struct ath_hal *); - void (*calPostProc) (struct ath_hal *, u8); + void (*calCollect) (struct ath_hw *); + void (*calPostProc) (struct ath_hw *, u8); }; struct hal_cal_list { @@ -108,17 +108,17 @@ struct ath9k_nfcal_hist { u8 invalidNFcount; }; -bool ath9k_hw_reset_calvalid(struct ath_hal *ah); -void ath9k_hw_start_nfcal(struct ath_hal *ah); -void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); -int16_t ath9k_hw_getnf(struct ath_hal *ah, +bool ath9k_hw_reset_calvalid(struct ath_hw *ah); +void ath9k_hw_start_nfcal(struct ath_hw *ah); +void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan); +int16_t ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan); -void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); -s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan); -bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, +void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah); +s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan); +bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone); -bool ath9k_hw_init_cal(struct ath_hal *ah, +bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan); #endif /* CALIB_H */ diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c index daca5ce..800ad59 100644 --- a/drivers/net/wireless/ath9k/debug.c +++ b/drivers/net/wireless/ath9k/debug.c @@ -44,7 +44,7 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { struct ath_softc *sc = file->private_data; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; char buf[1024]; unsigned int len = 0; u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index d58d8a3..94e7993 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -16,7 +16,7 @@ #include "ath9k.h" -static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, +static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val) { @@ -88,18 +88,17 @@ static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, return false; } -static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data) +static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) { struct ath_softc *sc = ah->ah_sc; return sc->bus_ops->eeprom_read(ah, off, data); } -static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah) +static bool ath9k_hw_fill_4k_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; u16 *eep_data; int addr, eep_start_loc = 0; @@ -124,11 +123,10 @@ static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah) #undef SIZE_EEPROM_4K } -static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah) +static bool ath9k_hw_fill_def_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; u16 *eep_data; int addr, ar5416_eep_start_loc = 0x100; @@ -147,23 +145,20 @@ static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah) #undef SIZE_EEPROM_DEF } -static bool (*ath9k_fill_eeprom[]) (struct ath_hal *) = { +static bool (*ath9k_fill_eeprom[]) (struct ath_hw *) = { ath9k_hw_fill_def_eeprom, ath9k_hw_fill_4k_eeprom }; -static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah) +static inline bool ath9k_hw_fill_eeprom(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_fill_eeprom[ahp->ah_eep_map](ah); + return ath9k_fill_eeprom[ah->ah_eep_map](ah); } -static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) +static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416_eeprom_def *eep = - (struct ar5416_eeprom_def *) &ahp->ah_eeprom.def; + (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -187,7 +182,7 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) if (magic2 == AR5416_EEPROM_MAGIC) { size = sizeof(struct ar5416_eeprom_def); need_swap = true; - eepdata = (u16 *) (&ahp->ah_eeprom); + eepdata = (u16 *) (&ah->ah_eeprom); for (addr = 0; addr < size / sizeof(u16); addr++) { temp = swab16(*eepdata); @@ -214,16 +209,16 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ahp->ah_eeprom.def.baseEepHeader.length); + el = swab16(ah->ah_eeprom.def.baseEepHeader.length); else - el = ahp->ah_eeprom.def.baseEepHeader.length; + el = ah->ah_eeprom.def.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ahp->ah_eeprom); + eepdata = (u16 *)(&ah->ah_eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -277,23 +272,22 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) } } - if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || - ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) { + if (sum != 0xffff || ar5416_get_eep_ver(ah) != AR5416_EEP_VER || + ar5416_get_eep_rev(ah) < AR5416_EEP_NO_BACK_VER) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep_ver(ahp)); + sum, ar5416_get_eep_ver(ah)); return -EINVAL; } return 0; } -static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) +static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah) { #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416_eeprom_4k *eep = - (struct ar5416_eeprom_4k *) &ahp->ah_eeprom.map4k; + (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -317,7 +311,7 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) if (magic2 == AR5416_EEPROM_MAGIC) { need_swap = true; - eepdata = (u16 *) (&ahp->ah_eeprom); + eepdata = (u16 *) (&ah->ah_eeprom); for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { temp = swab16(*eepdata); @@ -344,16 +338,16 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ahp->ah_eeprom.map4k.baseEepHeader.length); + el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); else - el = ahp->ah_eeprom.map4k.baseEepHeader.length; + el = ah->ah_eeprom.map4k.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ahp->ah_eeprom); + eepdata = (u16 *)(&ah->ah_eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -403,11 +397,11 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) } } - if (sum != 0xffff || ar5416_get_eep4k_ver(ahp) != AR5416_EEP_VER || - ar5416_get_eep4k_rev(ahp) < AR5416_EEP_NO_BACK_VER) { + if (sum != 0xffff || ar5416_get_eep4k_ver(ah) != AR5416_EEP_VER || + ar5416_get_eep4k_rev(ah) < AR5416_EEP_NO_BACK_VER) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep4k_ver(ahp)); + sum, ar5416_get_eep4k_ver(ah)); return -EINVAL; } @@ -415,16 +409,14 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) #undef EEPROM_4K_SIZE } -static int (*ath9k_check_eeprom[]) (struct ath_hal *) = { +static int (*ath9k_check_eeprom[]) (struct ath_hw *) = { ath9k_hw_check_def_eeprom, ath9k_hw_check_4k_eeprom }; -static inline int ath9k_hw_check_eeprom(struct ath_hal *ah) +static inline int ath9k_hw_check_eeprom(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_check_eeprom[ahp->ah_eep_map](ah); + return ath9k_check_eeprom[ah->ah_eep_map](ah); } static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, @@ -456,7 +448,7 @@ static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, return true; } -static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah, +static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_data_per_freq_4k *pRawDataSet, u8 *bChans, u16 availPiers, @@ -624,7 +616,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah, #undef TMP_VAL_VPD_TABLE } -static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah, +static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_data_per_freq *pRawDataSet, u8 *bChans, u16 availPiers, @@ -789,7 +781,7 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah, return; } -static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, +static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, @@ -844,7 +836,7 @@ static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, } } -static void ath9k_hw_get_target_powers(struct ath_hal *ah, +static void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, @@ -927,12 +919,11 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq, return twiceMaxEdgePower; } -static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah, +static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; struct cal_data_per_freq *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -988,7 +979,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -1054,12 +1045,11 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah, return true; } -static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah, +static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; struct cal_data_per_freq_4k *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -1108,7 +1098,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -1171,7 +1161,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah, return true; } -static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, +static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, @@ -1182,8 +1172,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -1213,7 +1202,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ahp->ah_txchainmask; + tx_chainmask = ah->ah_txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -1322,7 +1311,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, else freq = centers.ctl_center; - if (ar5416_get_eep_ver(ahp) == 14 && ar5416_get_eep_rev(ahp) <= 2) + if (ar5416_get_eep_ver(ah) == 14 && ar5416_get_eep_rev(ah) <= 2) twiceMaxEdgePower = AR5416_MAX_RATE_POWER; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, @@ -1462,7 +1451,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, return true; } -static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, +static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, @@ -1470,8 +1459,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, u16 twiceMaxRegulatoryPower, u16 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -1499,7 +1487,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ahp->ah_txchainmask; + tx_chainmask = ah->ah_txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -1560,8 +1548,8 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, else freq = centers.ctl_center; - if (ar5416_get_eep_ver(ahp) == 14 && - ar5416_get_eep_rev(ahp) <= 2) + if (ar5416_get_eep_ver(ah) == 14 && + ar5416_get_eep_rev(ah) <= 2) twiceMaxEdgePower = AR5416_MAX_RATE_POWER; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, @@ -1698,15 +1686,14 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, return true; } -static int ath9k_hw_def_set_txpower(struct ath_hal *ah, +static int ath9k_hw_def_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; struct modal_eep_header *pModal = &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); int16_t ratesArray[Ar5416RateSize]; @@ -1831,15 +1818,14 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah, return 0; } -static int ath9k_hw_4k_set_txpower(struct ath_hal *ah, +static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; struct modal_eep_4k_header *pModal = &pEepData->modalHeader; int16_t ratesArray[Ar5416RateSize]; int16_t txPowerIndexOffset = 0; @@ -1959,40 +1945,37 @@ static int ath9k_hw_4k_set_txpower(struct ath_hal *ah, return 0; } -static int (*ath9k_set_txpower[]) (struct ath_hal *, +static int (*ath9k_set_txpower[]) (struct ath_hw *, struct ath9k_channel *, u16, u8, u8, u8) = { ath9k_hw_def_set_txpower, ath9k_hw_4k_set_txpower }; -int ath9k_hw_set_txpower(struct ath_hal *ah, +int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_set_txpower[ahp->ah_eep_map](ah, chan, cfgCtl, - twiceAntennaReduction, twiceMaxRegulatoryPower, - powerLimit); + return ath9k_set_txpower[ah->ah_eep_map](ah, chan, cfgCtl, + twiceAntennaReduction, twiceMaxRegulatoryPower, + powerLimit); } -static void ath9k_hw_set_def_addac(struct ath_hal *ah, +static void ath9k_hw_set_def_addac(struct ath_hw *ah, struct ath9k_channel *chan) { #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) struct modal_eep_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) return; - if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) + if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) return; pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); @@ -2026,60 +2009,54 @@ static void ath9k_hw_set_def_addac(struct ath_hal *ah, } if (IS_CHAN_2GHZ(chan)) { - INI_RA(&ahp->ah_iniAddac, 7, 1) = (INI_RA(&ahp->ah_iniAddac, + INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } else { - INI_RA(&ahp->ah_iniAddac, 6, 1) = (INI_RA(&ahp->ah_iniAddac, + INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel << 6; } #undef XPA_LVL_FREQ } -static void ath9k_hw_set_4k_addac(struct ath_hal *ah, +static void ath9k_hw_set_4k_addac(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) return; - if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) + if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) return; pModal = &eep->modalHeader; if (pModal->xpaBiasLvl != 0xff) { biaslevel = pModal->xpaBiasLvl; - INI_RA(&ahp->ah_iniAddac, 7, 1) = - (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; + INI_RA(&ah->ah_iniAddac, 7, 1) = + (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } } -static void (*ath9k_set_addac[]) (struct ath_hal *, struct ath9k_channel *) = { +static void (*ath9k_set_addac[]) (struct ath_hw *, struct ath9k_channel *) = { ath9k_hw_set_def_addac, ath9k_hw_set_4k_addac }; -void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan) +void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - - ath9k_set_addac[ahp->ah_eep_map](ah, chan); + ath9k_set_addac[ah->ah_eep_map](ah, chan); } - - /* XXX: Clean me up, make me more legible */ -static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, +static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) struct modal_eep_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; int i, regChainOffset; u8 txRxAttenLocal; @@ -2097,7 +2074,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, } if (AR_SREV_5416_V20_OR_LATER(ah) && - (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && (i != 0)) regChainOffset = (i == 1) ? 0x2000 : 0x1000; else @@ -2318,12 +2295,11 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, #undef AR5416_VER_MASK } -static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah, +static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; int regChainOffset; u8 txRxAttenLocal; u8 ob[5], db1[5], db2[5]; @@ -2505,66 +2481,59 @@ static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah, return true; } -static bool (*ath9k_eeprom_set_board_values[])(struct ath_hal *, +static bool (*ath9k_eeprom_set_board_values[])(struct ath_hw *, struct ath9k_channel *) = { ath9k_hw_eeprom_set_def_board_values, ath9k_hw_eeprom_set_4k_board_values }; -bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, +bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_eeprom_set_board_values[ahp->ah_eep_map](ah, chan); + return ath9k_eeprom_set_board_values[ah->ah_eep_map](ah, chan); } -static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hal *ah, +static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); return pModal->antCtrlCommon & 0xFFFF; } -static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hal *ah, +static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; return pModal->antCtrlCommon & 0xFFFF; } -static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hal *, +static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hw *, struct ath9k_channel *) = { ath9k_hw_get_def_eeprom_antenna_cfg, ath9k_hw_get_4k_eeprom_antenna_cfg }; -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, +u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_get_eeprom_antenna_cfg[ahp->ah_eep_map](ah, chan); + return ath9k_get_eeprom_antenna_cfg[ah->ah_eep_map](ah, chan); } -static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hal *ah, +static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { return 1; } -static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah, +static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); struct base_eep_header *pBase = &eep->baseEepHeader; @@ -2579,27 +2548,24 @@ static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah, return num_ant_config; } -static u8 (*ath9k_get_num_ant_config[])(struct ath_hal *, +static u8 (*ath9k_get_num_ant_config[])(struct ath_hw *, enum ieee80211_band) = { ath9k_hw_get_def_num_ant_config, ath9k_hw_get_4k_num_ant_config }; -u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, +u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_get_num_ant_config[ahp->ah_eep_map](ah, freq_band); + return ath9k_get_num_ant_config[ah->ah_eep_map](ah, freq_band); } -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) +u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz) { #define EEP_MAP4K_SPURCHAN \ - (ahp->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) + (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) #define EEP_DEF_SPURCHAN \ - (ahp->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) - struct ath_hal_5416 *ahp = AH5416(ah); + (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -2615,7 +2581,7 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) "Getting spur val from new loc. %d\n", spur_val); break; case SPUR_ENABLE_EEPROM: - if (ahp->ah_eep_map == EEP_MAP_4KBITS) + if (ah->ah_eep_map == EEP_MAP_4KBITS) spur_val = EEP_MAP4K_SPURCHAN; else spur_val = EEP_DEF_SPURCHAN; @@ -2628,11 +2594,10 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) #undef EEP_MAP4K_SPURCHAN } -static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah, +static u32 ath9k_hw_get_eeprom_4k(struct ath_hw *ah, enum eeprom_param param) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; struct base_eep_header_4k *pBase = &eep->baseEepHeader; @@ -2670,12 +2635,11 @@ static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah, } } -static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah, +static u32 ath9k_hw_get_eeprom_def(struct ath_hw *ah, enum eeprom_param param) { #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; struct modal_eep_header *pModal = eep->modalHeader; struct base_eep_header *pBase = &eep->baseEepHeader; @@ -2729,28 +2693,25 @@ static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah, #undef AR5416_VER_MASK } -static u32 (*ath9k_get_eeprom[])(struct ath_hal *, enum eeprom_param) = { +static u32 (*ath9k_get_eeprom[])(struct ath_hw *, enum eeprom_param) = { ath9k_hw_get_eeprom_def, ath9k_hw_get_eeprom_4k }; -u32 ath9k_hw_get_eeprom(struct ath_hal *ah, +u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_get_eeprom[ahp->ah_eep_map](ah, param); + return ath9k_get_eeprom[ah->ah_eep_map](ah, param); } -int ath9k_hw_eeprom_attach(struct ath_hal *ah) +int ath9k_hw_eeprom_attach(struct ath_hw *ah) { int status; - struct ath_hal_5416 *ahp = AH5416(ah); if (AR_SREV_9285(ah)) - ahp->ah_eep_map = EEP_MAP_4KBITS; + ah->ah_eep_map = EEP_MAP_4KBITS; else - ahp->ah_eep_map = EEP_MAP_DEFAULT; + ah->ah_eep_map = EEP_MAP_DEFAULT; if (!ath9k_hw_fill_eeprom(ah)) return -EIO; diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 9eb7774..81a7a70 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -447,38 +447,38 @@ enum hal_eep_map { EEP_MAP_MAX }; -#define ar5416_get_eep_ver(_ahp) \ - (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep_rev(_ahp) \ - (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) +#define ar5416_get_eep_ver(_ah) \ + (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep_rev(_ah) \ + (((_ah)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) #define ar5416_get_ntxchains(_txchainmask) \ (((_txchainmask >> 2) & 1) + \ ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) -#define ar5416_get_eep4k_ver(_ahp) \ - (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep4k_rev(_ahp) \ - (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) +#define ar5416_get_eep4k_ver(_ah) \ + (((_ah)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep4k_rev(_ah) \ + (((_ah)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) -int ath9k_hw_set_txpower(struct ath_hal *ah, struct ath9k_channel *chan, +int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit); -void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); -bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, +void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan); +bool ath9k_hw_set_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, u8 AntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit); -bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, +bool ath9k_hw_set_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset); -bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, +bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan); -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, +u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan); -u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, +u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band); -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); -u32 ath9k_hw_get_eeprom(struct ath_hal *ah, enum eeprom_param param); -int ath9k_hw_eeprom_attach(struct ath_hal *ah); +u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz); +u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param); +int ath9k_hw_eeprom_attach(struct ath_hw *ah); #endif /* EEPROM_H */ diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 5d72875..ba908e9 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -28,41 +28,45 @@ MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support"); #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 -static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type); -static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, +static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); +static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode); -static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, +static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value); -static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); -static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); +static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); +static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); /********************/ /* Helper Functions */ /********************/ -static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks) +static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (!ah->ah_curchan) /* should really check for CCK instead */ return clks / ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; + return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM; } -static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks) +static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (conf_is_ht40(conf)) return ath9k_hw_mac_usec(ah, clks) / 2; else return ath9k_hw_mac_usec(ah, clks); } -static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) +static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (!ah->ah_curchan) /* should really check for CCK instead */ return usecs *ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) @@ -70,16 +74,17 @@ static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; } -static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs) +static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (conf_is_ht40(conf)) return ath9k_hw_mac_clks(ah, usecs) * 2; else return ath9k_hw_mac_clks(ah, usecs); } -bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val) +bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val) { int i; @@ -109,7 +114,7 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n) return retval; } -bool ath9k_get_channel_edges(struct ath_hal *ah, +bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high) { @@ -128,7 +133,7 @@ bool ath9k_get_channel_edges(struct ath_hal *ah, return false; } -u16 ath9k_hw_computetxtime(struct ath_hal *ah, +u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates, u32 frameLen, u16 rateix, bool shortPreamble) @@ -184,12 +189,11 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah, return txTime; } -void ath9k_hw_get_channel_centers(struct ath_hal *ah, +void ath9k_hw_get_channel_centers(struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers) { int8_t extoff; - struct ath_hal_5416 *ahp = AH5416(ah); if (!IS_CHAN_HT40(chan)) { centers->ctl_center = centers->ext_center = @@ -212,16 +216,15 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah, centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); centers->ext_center = centers->synth_center + (extoff * - ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? + ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? HT40_CHANNEL_CENTER_SHIFT : 15)); - } /******************/ /* Chip Revisions */ /******************/ -static void ath9k_hw_read_revisions(struct ath_hal *ah) +static void ath9k_hw_read_revisions(struct ath_hw *ah) { u32 val; @@ -244,7 +247,7 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah) } } -static int ath9k_hw_get_radiorev(struct ath_hal *ah) +static int ath9k_hw_get_radiorev(struct ath_hw *ah) { u32 val; int i; @@ -263,7 +266,7 @@ static int ath9k_hw_get_radiorev(struct ath_hal *ah) /* HW Attach, Detach, Init Routines */ /************************************/ -static void ath9k_hw_disablepcie(struct ath_hal *ah) +static void ath9k_hw_disablepcie(struct ath_hw *ah) { if (AR_SREV_9100(ah)) return; @@ -281,7 +284,7 @@ static void ath9k_hw_disablepcie(struct ath_hal *ah) REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); } -static bool ath9k_hw_chip_test(struct ath_hal *ah) +static bool ath9k_hw_chip_test(struct ath_hw *ah) { u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; u32 regHold[2]; @@ -323,6 +326,7 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah) REG_WRITE(ah, regAddr[i], regHold[i]); } udelay(100); + return true; } @@ -347,7 +351,7 @@ static const char *ath9k_hw_devname(u16 devid) return NULL; } -static void ath9k_hw_set_defaults(struct ath_hal *ah) +static void ath9k_hw_set_defaults(struct ath_hw *ah) { int i; @@ -387,25 +391,20 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah) ah->ah_config.intr_mitigation = 1; } -static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, - struct ath_softc *sc, - void __iomem *mem, - int *status) +static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, + int *status) { - struct ath_hal_5416 *ahp; - struct ath_hal *ah; + struct ath_hw *ah; - ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); - if (ahp == NULL) { + ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); + if (ah == NULL) { DPRINTF(sc, ATH_DBG_FATAL, "Cannot allocate memory for state block\n"); *status = -ENOMEM; return NULL; } - ah = &ahp->ah; ah->ah_sc = sc; - ah->ah_sh = mem; ah->hw_version.magic = AR5416_MAGIC; ah->regulatory.country_code = CTRY_DEFAULT; ah->hw_version.devid = devid; @@ -419,24 +418,24 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, ah->regulatory.power_limit = MAX_RATE_POWER; ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; - ahp->ah_atimWindow = 0; - ahp->ah_diversityControl = ah->ah_config.diversity_control; - ahp->ah_antennaSwitchSwap = + ah->ah_atimWindow = 0; + ah->ah_diversityControl = ah->ah_config.diversity_control; + ah->ah_antennaSwitchSwap = ah->ah_config.antenna_switch_swap; - ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; - ahp->ah_beaconInterval = 100; - ahp->ah_enable32kHzClock = DONT_USE_32KHZ; - ahp->ah_slottime = (u32) -1; - ahp->ah_acktimeout = (u32) -1; - ahp->ah_ctstimeout = (u32) -1; - ahp->ah_globaltxtimeout = (u32) -1; + ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; + ah->ah_beaconInterval = 100; + ah->ah_enable32kHzClock = DONT_USE_32KHZ; + ah->ah_slottime = (u32) -1; + ah->ah_acktimeout = (u32) -1; + ah->ah_ctstimeout = (u32) -1; + ah->ah_globaltxtimeout = (u32) -1; - ahp->ah_gBeaconRate = 0; + ah->ah_gBeaconRate = 0; - return ahp; + return ah; } -static int ath9k_hw_rfattach(struct ath_hal *ah) +static int ath9k_hw_rfattach(struct ath_hw *ah) { bool rfStatus = false; int ecode = 0; @@ -451,7 +450,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah) return 0; } -static int ath9k_hw_rf_claim(struct ath_hal *ah) +static int ath9k_hw_rf_claim(struct ath_hw *ah) { u32 val; @@ -480,7 +479,7 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah) return 0; } -static int ath9k_hw_init_macaddr(struct ath_hal *ah) +static int ath9k_hw_init_macaddr(struct ath_hw *ah) { u32 sum; int i; @@ -503,55 +502,55 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah) return 0; } -static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah) +static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) { u32 rxgain_type; - struct ath_hal_5416 *ahp = AH5416(ah); if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_backoff_13db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_backoff_23db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); else - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); - } else - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + } else { + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); + } } -static void ath9k_hw_init_txgain_ini(struct ath_hal *ah) +static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) { u32 txgain_type; - struct ath_hal_5416 *ahp = AH5416(ah); if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) - INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->ah_iniModesTxGain, ar9280Modes_high_power_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); else - INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->ah_iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); - } else - INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, + } else { + INIT_INI_ARRAY(&ah->ah_iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); + } } -static int ath9k_hw_post_attach(struct ath_hal *ah) +static int ath9k_hw_post_attach(struct ath_hw *ah) { int ecode; @@ -580,33 +579,30 @@ static int ath9k_hw_post_attach(struct ath_hal *ah) return 0; } -static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, - void __iomem *mem, int *status) +static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, + int *status) { - struct ath_hal_5416 *ahp; - struct ath_hal *ah; + struct ath_hw *ah; int ecode; u32 i, j; - ahp = ath9k_hw_newstate(devid, sc, mem, status); - if (ahp == NULL) + ah = ath9k_hw_newstate(devid, sc, status); + if (ah == NULL) return NULL; - ah = &ahp->ah; - ath9k_hw_set_defaults(ah); if (ah->ah_config.intr_mitigation != 0) - ahp->ah_intrMitigation = true; + ah->ah_intrMitigation = true; if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n"); + DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); ecode = -EIO; goto bad; } if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); + DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); ecode = -EIO; goto bad; } @@ -621,15 +617,14 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } } - DPRINTF(ah->ah_sc, ATH_DBG_RESET, - "serialize_regmode is %d\n", + DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n", ah->ah_config.serialize_regmode); if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "Mac Chip Rev 0x%02x.%x is not supported by " "this driver\n", ah->hw_version.macVersion, ah->hw_version.macRev); @@ -638,176 +633,176 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } if (AR_SREV_9100(ah)) { - ahp->ah_iqCalData.calData = &iq_cal_multi_sample; - ahp->ah_suppCals = IQ_MISMATCH_CAL; + ah->ah_iqCalData.calData = &iq_cal_multi_sample; + ah->ah_suppCals = IQ_MISMATCH_CAL; ah->ah_isPciExpress = false; } ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); if (AR_SREV_9160_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) { - ahp->ah_iqCalData.calData = &iq_cal_single_sample; - ahp->ah_adcGainCalData.calData = + ah->ah_iqCalData.calData = &iq_cal_single_sample; + ah->ah_adcGainCalData.calData = &adc_gain_cal_single_sample; - ahp->ah_adcDcCalData.calData = + ah->ah_adcDcCalData.calData = &adc_dc_cal_single_sample; - ahp->ah_adcDcCalInitData.calData = + ah->ah_adcDcCalInitData.calData = &adc_init_dc_cal; } else { - ahp->ah_iqCalData.calData = &iq_cal_multi_sample; - ahp->ah_adcGainCalData.calData = + ah->ah_iqCalData.calData = &iq_cal_multi_sample; + ah->ah_adcGainCalData.calData = &adc_gain_cal_multi_sample; - ahp->ah_adcDcCalData.calData = + ah->ah_adcDcCalData.calData = &adc_dc_cal_multi_sample; - ahp->ah_adcDcCalInitData.calData = + ah->ah_adcDcCalInitData.calData = &adc_init_dc_cal; } - ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; + ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; } if (AR_SREV_9160(ah)) { ah->ah_config.enable_ani = 1; - ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | + ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | ATH9K_ANI_FIRSTEP_LEVEL); } else { - ahp->ah_ani_function = ATH9K_ANI_ALL; + ah->ah_ani_function = ATH9K_ANI_ALL; if (AR_SREV_9280_10_OR_LATER(ah)) { - ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; + ah->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; } } - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "This Mac Chip Rev 0x%02x.%x is \n", ah->hw_version.macVersion, ah->hw_version.macRev); if (AR_SREV_9285_12_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2, ARRAY_SIZE(ar9285Modes_9285_1_2), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2, ARRAY_SIZE(ar9285Common_9285_1_2), 2); if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 2); } } else if (AR_SREV_9285_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285, ARRAY_SIZE(ar9285Modes_9285), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285, ARRAY_SIZE(ar9285Common_9285), 2); if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); } } else if (AR_SREV_9280_20_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2, ARRAY_SIZE(ar9280Modes_9280_2), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2, ARRAY_SIZE(ar9280Common_9280_2), 2); if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9280PciePhy_clkreq_off_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); } else { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9280PciePhy_clkreq_always_on_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); } - INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, + INIT_INI_ARRAY(&ah->ah_iniModesAdditional, ar9280Modes_fast_clock_9280_2, ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); } else if (AR_SREV_9280_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280, ARRAY_SIZE(ar9280Modes_9280), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280, ARRAY_SIZE(ar9280Common_9280), 2); } else if (AR_SREV_9160_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, + INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160, ARRAY_SIZE(ar5416Modes_9160), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160, ARRAY_SIZE(ar5416Common_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, + INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160, ARRAY_SIZE(ar5416Bank0_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, + INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160, ARRAY_SIZE(ar5416BB_RfGain_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, + INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160, ARRAY_SIZE(ar5416Bank1_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, + INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160, ARRAY_SIZE(ar5416Bank2_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, + INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160, ARRAY_SIZE(ar5416Bank3_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, + INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160, ARRAY_SIZE(ar5416Bank6_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, + INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160, ARRAY_SIZE(ar5416Bank6TPC_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, + INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160, ARRAY_SIZE(ar5416Bank7_9160), 2); if (AR_SREV_9160_11(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniAddac, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_91601_1, ARRAY_SIZE(ar5416Addac_91601_1), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160, ARRAY_SIZE(ar5416Addac_9160), 2); } } else if (AR_SREV_9100_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, + INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100, ARRAY_SIZE(ar5416Modes_9100), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100, ARRAY_SIZE(ar5416Common_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, + INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100, ARRAY_SIZE(ar5416Bank0_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, + INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100, ARRAY_SIZE(ar5416BB_RfGain_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, + INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100, ARRAY_SIZE(ar5416Bank1_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, + INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100, ARRAY_SIZE(ar5416Bank2_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, + INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100, ARRAY_SIZE(ar5416Bank3_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, + INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100, ARRAY_SIZE(ar5416Bank6_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, + INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100, ARRAY_SIZE(ar5416Bank6TPC_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, + INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100, ARRAY_SIZE(ar5416Bank7_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100, ARRAY_SIZE(ar5416Addac_9100), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, + INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes, ARRAY_SIZE(ar5416Modes), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common, ARRAY_SIZE(ar5416Common), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, + INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0, ARRAY_SIZE(ar5416Bank0), 2); - INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, + INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain, ARRAY_SIZE(ar5416BB_RfGain), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, + INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1, ARRAY_SIZE(ar5416Bank1), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, + INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2, ARRAY_SIZE(ar5416Bank2), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, + INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3, ARRAY_SIZE(ar5416Bank3), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, + INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6, ARRAY_SIZE(ar5416Bank6), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, + INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC, ARRAY_SIZE(ar5416Bank6TPC), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, + INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7, ARRAY_SIZE(ar5416Bank7), 2); - INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac, ARRAY_SIZE(ar5416Addac), 2); } @@ -829,22 +824,22 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ath9k_hw_init_txgain_ini(ah); if (ah->hw_version.devid == AR9280_DEVID_PCI) { - for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); + for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->ah_iniModes, i, 0); - for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { - u32 val = INI_RA(&ahp->ah_iniModes, i, j); + for (j = 1; j < ah->ah_iniModes.ia_columns; j++) { + u32 val = INI_RA(&ah->ah_iniModes, i, j); - INI_RA(&ahp->ah_iniModes, i, j) = + INI_RA(&ah->ah_iniModes, i, j) = ath9k_hw_ini_fixup(ah, - &ahp->ah_eeprom.def, + &ah->ah_eeprom.def, reg, val); } } } if (!ath9k_hw_fill_cap_info(ah)) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n"); ecode = -EINVAL; goto bad; @@ -852,7 +847,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ecode = ath9k_hw_init_macaddr(ah); if (ecode != 0) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "failed initializing mac address\n"); goto bad; } @@ -866,15 +861,15 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, return ah; bad: - if (ahp) - ath9k_hw_detach((struct ath_hal *) ahp); + if (ah) + ath9k_hw_detach(ah); if (status) *status = ecode; return NULL; } -static void ath9k_hw_init_bb(struct ath_hal *ah, +static void ath9k_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan) { u32 synthDelay; @@ -890,7 +885,7 @@ static void ath9k_hw_init_bb(struct ath_hal *ah, udelay(synthDelay + BASE_ACTIVATE_DELAY); } -static void ath9k_hw_init_qos(struct ath_hal *ah) +static void ath9k_hw_init_qos(struct ath_hw *ah) { REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); @@ -907,7 +902,7 @@ static void ath9k_hw_init_qos(struct ath_hal *ah) REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); } -static void ath9k_hw_init_pll(struct ath_hal *ah, +static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan) { u32 pll; @@ -975,13 +970,12 @@ static void ath9k_hw_init_pll(struct ath_hal *ah, REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); } -static void ath9k_hw_init_chain_masks(struct ath_hal *ah) +static void ath9k_hw_init_chain_masks(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int rx_chainmask, tx_chainmask; - rx_chainmask = ahp->ah_rxchainmask; - tx_chainmask = ahp->ah_txchainmask; + rx_chainmask = ah->ah_rxchainmask; + tx_chainmask = ah->ah_txchainmask; switch (rx_chainmask) { case 0x5: @@ -1013,28 +1007,26 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah) REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); } -static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, +static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, enum nl80211_iftype opmode) { - struct ath_hal_5416 *ahp = AH5416(ah); - - ahp->ah_maskReg = AR_IMR_TXERR | + ah->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | AR_IMR_RXORN | AR_IMR_BCNMISC; - if (ahp->ah_intrMitigation) - ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; + if (ah->ah_intrMitigation) + ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; else - ahp->ah_maskReg |= AR_IMR_RXOK; + ah->ah_maskReg |= AR_IMR_RXOK; - ahp->ah_maskReg |= AR_IMR_TXOK; + ah->ah_maskReg |= AR_IMR_TXOK; if (opmode == NL80211_IFTYPE_AP) - ahp->ah_maskReg |= AR_IMR_MIB; + ah->ah_maskReg |= AR_IMR_MIB; - REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); + REG_WRITE(ah, AR_IMR, ah->ah_maskReg); REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); if (!AR_SREV_9100(ah)) { @@ -1044,72 +1036,64 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, } } -static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) +static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); - ahp->ah_acktimeout = (u32) -1; + ah->ah_acktimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); - ahp->ah_acktimeout = us; + ah->ah_acktimeout = us; return true; } } -static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) +static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); - ahp->ah_ctstimeout = (u32) -1; + ah->ah_ctstimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); - ahp->ah_ctstimeout = us; + ah->ah_ctstimeout = us; return true; } } -static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu) +static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (tu > 0xFFFF) { DPRINTF(ah->ah_sc, ATH_DBG_XMIT, "bad global tx timeout %u\n", tu); - ahp->ah_globaltxtimeout = (u32) -1; + ah->ah_globaltxtimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); - ahp->ah_globaltxtimeout = tu; + ah->ah_globaltxtimeout = tu; return true; } } -static void ath9k_hw_init_user_settings(struct ath_hal *ah) +static void ath9k_hw_init_user_settings(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); + DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n", + ah->ah_miscMode); - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n", - ahp->ah_miscMode); - - if (ahp->ah_miscMode != 0) + if (ah->ah_miscMode != 0) REG_WRITE(ah, AR_PCU_MISC, - REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); - if (ahp->ah_slottime != (u32) -1) - ath9k_hw_setslottime(ah, ahp->ah_slottime); - if (ahp->ah_acktimeout != (u32) -1) - ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); - if (ahp->ah_ctstimeout != (u32) -1) - ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); - if (ahp->ah_globaltxtimeout != (u32) -1) - ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout); + REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode); + if (ah->ah_slottime != (u32) -1) + ath9k_hw_setslottime(ah, ah->ah_slottime); + if (ah->ah_acktimeout != (u32) -1) + ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout); + if (ah->ah_ctstimeout != (u32) -1) + ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout); + if (ah->ah_globaltxtimeout != (u32) -1) + ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout); } const char *ath9k_hw_probe(u16 vendorid, u16 devid) @@ -1118,7 +1102,7 @@ const char *ath9k_hw_probe(u16 vendorid, u16 devid) ath9k_hw_devname(devid) : NULL; } -void ath9k_hw_detach(struct ath_hal *ah) +void ath9k_hw_detach(struct ath_hw *ah) { if (!AR_SREV_9100(ah)) ath9k_hw_ani_detach(ah); @@ -1128,10 +1112,9 @@ void ath9k_hw_detach(struct ath_hal *ah) kfree(ah); } -struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, - void __iomem *mem, int *error) +struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error) { - struct ath_hal *ah = NULL; + struct ath_hw *ah = NULL; switch (devid) { case AR5416_DEVID_PCI: @@ -1141,7 +1124,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, case AR9280_DEVID_PCI: case AR9280_DEVID_PCIE: case AR9285_DEVID_PCIE: - ah = ath9k_hw_do_attach(devid, sc, mem, error); + ah = ath9k_hw_do_attach(devid, sc, error); break; default: *error = -ENXIO; @@ -1155,7 +1138,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, /* INI */ /*******/ -static void ath9k_hw_override_ini(struct ath_hal *ah, +static void ath9k_hw_override_ini(struct ath_hw *ah, struct ath9k_channel *chan) { /* @@ -1173,7 +1156,7 @@ static void ath9k_hw_override_ini(struct ath_hal *ah, REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); } -static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, +static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value) { @@ -1207,24 +1190,21 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, return value; } -static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, +static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value) { - struct ath_hal_5416 *ahp = AH5416(ah); - - if (ahp->ah_eep_map == EEP_MAP_4KBITS) + if (ah->ah_eep_map == EEP_MAP_4KBITS) return value; else return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); } -static int ath9k_hw_process_ini(struct ath_hal *ah, +static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { int i, regWrites = 0; - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_channel *channel = chan->chan; u32 modesIndex, freqIndex; int status; @@ -1257,35 +1237,33 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, } REG_WRITE(ah, AR_PHY(0), 0x00000007); - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); - ath9k_hw_set_addac(ah, chan); if (AR_SREV_5416_V22_OR_LATER(ah)) { - REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites); } else { struct ar5416IniArray temp; u32 addacSize = - sizeof(u32) * ahp->ah_iniAddac.ia_rows * - ahp->ah_iniAddac.ia_columns; + sizeof(u32) * ah->ah_iniAddac.ia_rows * + ah->ah_iniAddac.ia_columns; - memcpy(ahp->ah_addac5416_21, - ahp->ah_iniAddac.ia_array, addacSize); + memcpy(ah->ah_addac5416_21, + ah->ah_iniAddac.ia_array, addacSize); - (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0; + (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0; - temp.ia_array = ahp->ah_addac5416_21; - temp.ia_columns = ahp->ah_iniAddac.ia_columns; - temp.ia_rows = ahp->ah_iniAddac.ia_rows; + temp.ia_array = ah->ah_addac5416_21; + temp.ia_columns = ah->ah_iniAddac.ia_columns; + temp.ia_rows = ah->ah_iniAddac.ia_rows; REG_WRITE_ARRAY(&temp, 1, regWrites); } REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); - for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); - u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); + for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->ah_iniModes, i, 0); + u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex); REG_WRITE(ah, reg, val); @@ -1298,14 +1276,14 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, } if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites); if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites); - for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { - u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0); - u32 val = INI_RA(&ahp->ah_iniCommon, i, 1); + for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) { + u32 reg = INI_RA(&ah->ah_iniCommon, i, 0); + u32 val = INI_RA(&ah->ah_iniCommon, i, 1); REG_WRITE(ah, reg, val); @@ -1320,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { - REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, + REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex, regWrites); } @@ -1353,7 +1331,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, /* Reset and Channel Switching Routines */ /****************************************/ -static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) +static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) { u32 rfMode = 0; @@ -1373,12 +1351,12 @@ static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) REG_WRITE(ah, AR_PHY_MODE, rfMode); } -static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah) +static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) { REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); } -static inline void ath9k_hw_set_dma(struct ath_hal *ah) +static inline void ath9k_hw_set_dma(struct ath_hw *ah) { u32 regval; @@ -1404,7 +1382,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah) } } -static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) +static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) { u32 val; @@ -1428,7 +1406,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) } } -static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, +static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent) @@ -1447,7 +1425,7 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, *coef_exponent = coef_exp - 16; } -static void ath9k_hw_set_delta_slope(struct ath_hal *ah, +static void ath9k_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan) { u32 coef_scaled, ds_coef_exp, ds_coef_man; @@ -1481,7 +1459,7 @@ static void ath9k_hw_set_delta_slope(struct ath_hal *ah, AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); } -static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) +static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) { u32 rst_flags; u32 tmpReg; @@ -1529,7 +1507,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) return true; } -static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) +static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) { REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); @@ -1550,7 +1528,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); } -static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) +static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) { REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); @@ -1568,12 +1546,11 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) } } -static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, +static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { u32 phymode; u32 enableDacFifo = 0; - struct ath_hal_5416 *ahp = AH5416(ah); if (AR_SREV_9285_10_OR_LATER(ah)) enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & @@ -1589,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, (chan->chanmode == CHANNEL_G_HT40PLUS)) phymode |= AR_PHY_FC_DYN2040_PRI_CH; - if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) + if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) phymode |= AR_PHY_FC_DYN2040_EXT_CH; } REG_WRITE(ah, AR_PHY_TURBO, phymode); @@ -1600,27 +1577,23 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); } -static bool ath9k_hw_chip_reset(struct ath_hal *ah, +static bool ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) return false; if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) return false; - ahp->ah_chipFullSleep = false; - + ah->ah_chipFullSleep = false; ath9k_hw_init_pll(ah, chan); - ath9k_hw_set_rfmode(ah, chan); return true; } -static bool ath9k_hw_channel_change(struct ath_hal *ah, +static bool ath9k_hw_channel_change(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { @@ -1694,7 +1667,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah, return true; } -static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) +static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) { int bb_spur = AR_NO_SPUR; int freq; @@ -1944,7 +1917,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); } -static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) +static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) { int bb_spur = AR_NO_SPUR; int bin, cur_bin; @@ -2145,27 +2118,26 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); } -int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, +int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, bool bChannelChange) { u32 saveLedState; struct ath_softc *sc = ah->ah_sc; - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_channel *curchan = ah->ah_curchan; u32 saveDefAntenna; u32 macStaId1; int i, rx_chainmask, r; - ahp->ah_extprotspacing = sc->ht_extprotspacing; - ahp->ah_txchainmask = sc->tx_chainmask; - ahp->ah_rxchainmask = sc->rx_chainmask; + ah->ah_extprotspacing = sc->ht_extprotspacing; + ah->ah_txchainmask = sc->tx_chainmask; + ah->ah_rxchainmask = sc->rx_chainmask; if (AR_SREV_9285(ah)) { - ahp->ah_txchainmask &= 0x1; - ahp->ah_rxchainmask &= 0x1; + ah->ah_txchainmask &= 0x1; + ah->ah_rxchainmask &= 0x1; } else if (AR_SREV_9280(ah)) { - ahp->ah_txchainmask &= 0x3; - ahp->ah_rxchainmask &= 0x3; + ah->ah_txchainmask &= 0x3; + ah->ah_rxchainmask &= 0x3; } if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) @@ -2175,7 +2147,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, ath9k_hw_getnf(ah, curchan); if (bChannelChange && - (ahp->ah_chipFullSleep != true) && + (ah->ah_chipFullSleep != true) && (ah->ah_curchan != NULL) && (chan->channel != ah->ah_curchan->channel) && ((chan->channelFlags & CHANNEL_ALL) == @@ -2253,7 +2225,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, | AR_STA_ID1_RTS_USE_DEF | (ah->ah_config. ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) - | ahp->ah_staId1Defaults); + | ah->ah_staId1Defaults); ath9k_hw_set_operating_mode(ah, ah->ah_opmode); REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); @@ -2280,7 +2252,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, for (i = 0; i < AR_NUM_DCU; i++) REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); - ahp->ah_intrTxqs = 0; + ah->ah_intrTxqs = 0; for (i = 0; i < ah->ah_caps.total_queues; i++) ath9k_hw_resettxqueue(ah, i); @@ -2300,7 +2272,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_OBS, 8); - if (ahp->ah_intrMitigation) { + if (ah->ah_intrMitigation) { REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); @@ -2311,7 +2283,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, if (!ath9k_hw_init_cal(ah, chan)) return -EIO;; - rx_chainmask = ahp->ah_rxchainmask; + rx_chainmask = ah->ah_rxchainmask; if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); @@ -2345,7 +2317,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, /* Key Cache Management */ /************************/ -bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) +bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) { u32 keyType; @@ -2382,7 +2354,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) return true; } -bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) +bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) { u32 macHi, macLo; @@ -2410,7 +2382,7 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) return true; } -bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, +bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, const struct ath9k_keyval *k, const u8 *mac, int xorKey) { @@ -2420,7 +2392,6 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, u32 xorMask = xorKey ? (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 | ATH9K_KEY_XOR) : 0; - struct ath_hal_5416 *ahp = AH5416(ah); if (entry >= pCap->keycache_size) { DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, @@ -2491,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); (void) ath9k_hw_keysetmac(ah, entry, mac); - if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { + if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { u32 mic0, mic1, mic2, mic3, mic4; mic0 = get_unaligned_le32(k->kv_mic + 0); @@ -2541,7 +2512,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, return true; } -bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) +bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) { if (entry < ah->ah_caps.keycache_size) { u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); @@ -2555,7 +2526,7 @@ bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) /* Power Management (Chipset) */ /******************************/ -static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) +static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) { @@ -2569,7 +2540,7 @@ static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) } } -static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) +static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) { @@ -2585,8 +2556,7 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) } } -static bool ath9k_hw_set_power_awake(struct ath_hal *ah, - int setChip) +static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) { u32 val; int i; @@ -2627,17 +2597,15 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah, return true; } -bool ath9k_hw_setpower(struct ath_hal *ah, - enum ath9k_power_mode mode) +bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) { - struct ath_hal_5416 *ahp = AH5416(ah); + int status = true, setChip = true; static const char *modes[] = { "AWAKE", "FULL-SLEEP", "NETWORK SLEEP", "UNDEFINED" }; - int status = true, setChip = true; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", modes[ah->ah_power_mode], modes[mode], @@ -2649,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah, break; case ATH9K_PM_FULL_SLEEP: ath9k_set_power_sleep(ah, setChip); - ahp->ah_chipFullSleep = true; + ah->ah_chipFullSleep = true; break; case ATH9K_PM_NETWORK_SLEEP: ath9k_set_power_network_sleep(ah, setChip); @@ -2664,9 +2632,8 @@ bool ath9k_hw_setpower(struct ath_hal *ah, return status; } -void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) +void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) { - struct ath_hal_5416 *ahp = AH5416(ah); u8 i; if (ah->ah_isPciExpress != true) @@ -2679,9 +2646,9 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) return; if (AR_SREV_9280_20_OR_LATER(ah)) { - for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { - REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), - INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); + for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) { + REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0), + INI_RA(&ah->ah_iniPcieSerdes, i, 1)); } udelay(1000); } else if (AR_SREV_9280(ah) && @@ -2730,14 +2697,13 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) else REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); } - } /**********************/ /* Interrupt Handling */ /**********************/ -bool ath9k_hw_intrpend(struct ath_hal *ah) +bool ath9k_hw_intrpend(struct ath_hw *ah) { u32 host_isr; @@ -2756,14 +2722,13 @@ bool ath9k_hw_intrpend(struct ath_hal *ah) return false; } -bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) +bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) { u32 isr = 0; u32 mask2 = 0; struct ath9k_hw_capabilities *pCap = &ah->ah_caps; u32 sync_cause = 0; bool fatal_int = false; - struct ath_hal_5416 *ahp = AH5416(ah); if (!AR_SREV_9100(ah)) { if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { @@ -2811,7 +2776,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) *masked = isr & ATH9K_INT_COMMON; - if (ahp->ah_intrMitigation) { + if (ah->ah_intrMitigation) { if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) *masked |= ATH9K_INT_RX; } @@ -2826,12 +2791,12 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) *masked |= ATH9K_INT_TX; s0_s = REG_READ(ah, AR_ISR_S0_S); - ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); - ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); + ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); + ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); s1_s = REG_READ(ah, AR_ISR_S1_S); - ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); - ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); + ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); + ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); } if (isr & AR_ISR_RXORN) { @@ -2888,15 +2853,14 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) return true; } -enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah) +enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah) { - return AH5416(ah)->ah_maskReg; + return ah->ah_maskReg; } -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) { - struct ath_hal_5416 *ahp = AH5416(ah); - u32 omask = ahp->ah_maskReg; + u32 omask = ah->ah_maskReg; u32 mask, mask2; struct ath9k_hw_capabilities *pCap = &ah->ah_caps; @@ -2919,18 +2883,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) mask2 = 0; if (ints & ATH9K_INT_TX) { - if (ahp->ah_txOkInterruptMask) + if (ah->ah_txOkInterruptMask) mask |= AR_IMR_TXOK; - if (ahp->ah_txDescInterruptMask) + if (ah->ah_txDescInterruptMask) mask |= AR_IMR_TXDESC; - if (ahp->ah_txErrInterruptMask) + if (ah->ah_txErrInterruptMask) mask |= AR_IMR_TXERR; - if (ahp->ah_txEolInterruptMask) + if (ah->ah_txEolInterruptMask) mask |= AR_IMR_TXEOL; } if (ints & ATH9K_INT_RX) { mask |= AR_IMR_RXERR; - if (ahp->ah_intrMitigation) + if (ah->ah_intrMitigation) mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; else mask |= AR_IMR_RXOK | AR_IMR_RXDESC; @@ -2968,7 +2932,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); REG_WRITE(ah, AR_IMR_S2, mask | mask2); - ahp->ah_maskReg = ints; + ah->ah_maskReg = ints; if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { if (ints & ATH9K_INT_TIM_TIMER) @@ -3002,12 +2966,11 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) /* Beacon Handling */ /*******************/ -void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) +void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) { - struct ath_hal_5416 *ahp = AH5416(ah); int flags = 0; - ahp->ah_beaconInterval = beacon_period; + ah->ah_beaconInterval = beacon_period; switch (ah->ah_opmode) { case NL80211_IFTYPE_STATION: @@ -3022,7 +2985,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); REG_WRITE(ah, AR_NEXT_NDP_TIMER, TU_TO_USEC(next_beacon + - (ahp->ah_atimWindow ? ahp-> + (ah->ah_atimWindow ? ah-> ah_atimWindow : 1))); flags |= AR_NDP_TIMER_EN; case NL80211_IFTYPE_AP: @@ -3060,7 +3023,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) REG_SET_BIT(ah, AR_TIMER_MODE, flags); } -void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, +void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs) { u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; @@ -3124,9 +3087,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, /* HW Capabilities */ /*******************/ -bool ath9k_hw_fill_cap_info(struct ath_hal *ah) +bool ath9k_hw_fill_cap_info(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; u16 capField = 0, eeval; @@ -3195,7 +3157,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) } if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) - ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; + ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; pCap->low_2ghz_chan = 2312; pCap->high_2ghz_chan = 2732; @@ -3317,10 +3279,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) return true; } -bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 *result) { - struct ath_hal_5416 *ahp = AH5416(ah); const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; switch (type) { @@ -3341,17 +3302,17 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, case 0: return true; case 1: - return (ahp->ah_staId1Defaults & + return (ah->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) ? true : false; } case ATH9K_CAP_TKIP_SPLIT: - return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? + return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? false : true; case ATH9K_CAP_WME_TKIPMIC: return 0; case ATH9K_CAP_PHYCOUNTERS: - return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; + return ah->ah_hasHwPhyCounters ? 0 : -ENXIO; case ATH9K_CAP_DIVERSITY: return (REG_READ(ah, AR_PHY_CCK_DETECT) & AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? @@ -3366,14 +3327,14 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { return false; } else { - return (ahp->ah_staId1Defaults & + return (ah->ah_staId1Defaults & AR_STA_ID1_MCAST_KSRCH) ? true : false; } } return false; case ATH9K_CAP_TSF_ADJUST: - return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? + return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ? true : false; case ATH9K_CAP_RFSILENT: if (capability == 3) @@ -3404,19 +3365,18 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, } } -bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 setting, int *status) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 v; switch (type) { case ATH9K_CAP_TKIP_MIC: if (setting) - ahp->ah_staId1Defaults |= + ah->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; else - ahp->ah_staId1Defaults &= + ah->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; return true; case ATH9K_CAP_DIVERSITY: @@ -3429,15 +3389,15 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, return true; case ATH9K_CAP_MCAST_KEYSRCH: if (setting) - ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; + ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; else - ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; + ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; return true; case ATH9K_CAP_TSF_ADJUST: if (setting) - ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; else - ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; return true; default: return false; @@ -3448,7 +3408,7 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, /* GPIO / RFKILL / Antennae */ /****************************/ -static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, +static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) { int addr; @@ -3476,7 +3436,7 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, } } -void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) +void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) { u32 gpio_shift; @@ -3490,7 +3450,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) (AR_GPIO_OE_OUT_DRV << gpio_shift)); } -u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) +u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) { #define MS_REG_READ(x, y) \ (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) @@ -3506,7 +3466,7 @@ u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) return MS_REG_READ(AR, gpio) != 0; } -void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, +void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, u32 ah_signal_type) { u32 gpio_shift; @@ -3521,14 +3481,14 @@ void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, (AR_GPIO_OE_OUT_DRV << gpio_shift)); } -void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val) +void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) { REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), AR_GPIO_BIT(gpio)); } #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) -void ath9k_enable_rfkill(struct ath_hal *ah) +void ath9k_enable_rfkill(struct ath_hw *ah) { REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); @@ -3541,24 +3501,23 @@ void ath9k_enable_rfkill(struct ath_hal *ah) } #endif -u32 ath9k_hw_getdefantenna(struct ath_hal *ah) +u32 ath9k_hw_getdefantenna(struct ath_hw *ah) { return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; } -void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) +void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) { REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); } -bool ath9k_hw_setantennaswitch(struct ath_hal *ah, +bool ath9k_hw_setantennaswitch(struct ath_hw *ah, enum ath9k_ant_setting settings, struct ath9k_channel *chan, u8 *tx_chainmask, u8 *rx_chainmask, u8 *antenna_cfgd) { - struct ath_hal_5416 *ahp = AH5416(ah); static u8 tx_chainmask_cfg, rx_chainmask_cfg; if (AR_SREV_9280(ah)) { @@ -3591,7 +3550,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah, break; } } else { - ahp->ah_diversityControl = settings; + ah->ah_diversityControl = settings; } return true; @@ -3601,7 +3560,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah, /* General Operation */ /*********************/ -u32 ath9k_hw_getrxfilter(struct ath_hal *ah) +u32 ath9k_hw_getrxfilter(struct ath_hw *ah) { u32 bits = REG_READ(ah, AR_RX_FILTER); u32 phybits = REG_READ(ah, AR_PHY_ERR); @@ -3614,7 +3573,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hal *ah) return bits; } -void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) +void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) { u32 phybits; @@ -3634,12 +3593,12 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); } -bool ath9k_hw_phy_disable(struct ath_hal *ah) +bool ath9k_hw_phy_disable(struct ath_hw *ah) { return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); } -bool ath9k_hw_disable(struct ath_hal *ah) +bool ath9k_hw_disable(struct ath_hw *ah) { if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) return false; @@ -3647,7 +3606,7 @@ bool ath9k_hw_disable(struct ath_hal *ah) return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); } -bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) +bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) { struct ath9k_channel *chan = ah->ah_curchan; struct ieee80211_channel *channel = chan->chan; @@ -3665,17 +3624,17 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) return true; } -void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) +void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) { memcpy(ah->macaddr, mac, ETH_ALEN); } -void ath9k_hw_setopmode(struct ath_hal *ah) +void ath9k_hw_setopmode(struct ath_hw *ah) { ath9k_hw_set_operating_mode(ah, ah->ah_opmode); } -void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1) +void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) { REG_WRITE(ah, AR_MCAST_FIL0, filter0); REG_WRITE(ah, AR_MCAST_FIL1, filter1); @@ -3694,7 +3653,7 @@ void ath9k_hw_write_associd(struct ath_softc *sc) ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); } -u64 ath9k_hw_gettsf64(struct ath_hal *ah) +u64 ath9k_hw_gettsf64(struct ath_hw *ah) { u64 tsf; @@ -3704,14 +3663,14 @@ u64 ath9k_hw_gettsf64(struct ath_hal *ah) return tsf; } -void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64) +void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) { REG_WRITE(ah, AR_TSF_L32, 0x00000000); REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); } -void ath9k_hw_reset_tsf(struct ath_hal *ah) +void ath9k_hw_reset_tsf(struct ath_hw *ah) { int count; @@ -3728,34 +3687,30 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah) REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); } -bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) +bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (setting) - ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; else - ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; return true; } -bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) +bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); - ahp->ah_slottime = (u32) -1; + ah->ah_slottime = (u32) -1; return false; } else { REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); - ahp->ah_slottime = us; + ah->ah_slottime = us; return true; } } -void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) +void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) { u32 macmode; @@ -3772,7 +3727,7 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) /* Bluetooth Coexistence */ /***************************/ -void ath9k_hw_btcoex_enable(struct ath_hal *ah) +void ath9k_hw_btcoex_enable(struct ath_hw *ah) { /* connect bt_active to baseband */ REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index f4bf702..84914e2 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -42,8 +42,8 @@ #define AR5416_MAGIC 0x19641014 /* Register read/write primitives */ -#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) -#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) +#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sc->mem + _reg) +#define REG_READ(_ah, _reg) ioread32(_ah->ah_sc->mem + _reg) #define SM(_v, _f) (((_v) << _f##_S) & _f) #define MS(_v, _f) (((_v) & _f) >> _f##_S) @@ -417,46 +417,38 @@ struct ath9k_hw_version { u16 analog2GhzRev; }; -struct ath_hal { - struct ath9k_hw_version hw_version; - void __iomem *ah_sh; +struct ath_hw { struct ath_softc *ah_sc; - - enum nl80211_iftype ah_opmode; + struct ath9k_hw_version hw_version; struct ath9k_ops_config ah_config; struct ath9k_hw_capabilities ah_caps; struct ath9k_regulatory regulatory; - u32 ah_flags; - u8 macaddr[ETH_ALEN]; - - enum ath9k_power_mode ah_power_mode; - enum ath9k_power_mode ah_restore_mode; - struct ath9k_channel ah_channels[38]; struct ath9k_channel *ah_curchan; + union { + struct ar5416_eeprom_def def; + struct ar5416_eeprom_4k map4k; + } ah_eeprom; + + bool sw_mgmt_crypto; bool ah_isPciExpress; + u8 macaddr[ETH_ALEN]; u16 ah_txTrigLevel; u16 ah_rfsilent; u32 ah_rfkill_gpio; u32 ah_rfkill_polarity; u32 ah_btactive_gpio; u32 ah_wlanactive_gpio; + u32 ah_flags; + enum nl80211_iftype ah_opmode; - struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; - - bool sw_mgmt_crypto; -}; + enum ath9k_power_mode ah_power_mode; + enum ath9k_power_mode ah_restore_mode; -struct ath_hal_5416 { - struct ath_hal ah; - union { - struct ar5416_eeprom_def def; - struct ar5416_eeprom_4k map4k; - } ah_eeprom; + struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; struct ar5416Stats ah_stats; struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; - void __iomem *ah_cal_mem; int16_t ah_curchanRadIndex; u32 ah_maskReg; @@ -574,85 +566,83 @@ struct ath_hal_5416 { /* To indicate EEPROM mapping used */ enum hal_eep_map ah_eep_map; }; -#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) /* Attach, Detach, Reset */ const char *ath9k_hw_probe(u16 vendorid, u16 devid); -void ath9k_hw_detach(struct ath_hal *ah); -struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, - void __iomem *mem, int *error); -void ath9k_hw_rfdetach(struct ath_hal *ah); -int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, +void ath9k_hw_detach(struct ath_hw *ah); +struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error); +void ath9k_hw_rfdetach(struct ath_hw *ah); +int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, bool bChannelChange); -bool ath9k_hw_fill_cap_info(struct ath_hal *ah); -bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_fill_cap_info(struct ath_hw *ah); +bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 *result); -bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 setting, int *status); /* Key Cache Management */ -bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); -bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac); -bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, +bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); +bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac); +bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, const struct ath9k_keyval *k, const u8 *mac, int xorKey); -bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); +bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry); /* GPIO / RFKILL / Antennae */ -void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); -u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); -void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, +void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); +u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); +void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, u32 ah_signal_type); -void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); +void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) -void ath9k_enable_rfkill(struct ath_hal *ah); +void ath9k_enable_rfkill(struct ath_hw *ah); #endif -u32 ath9k_hw_getdefantenna(struct ath_hal *ah); -void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); -bool ath9k_hw_setantennaswitch(struct ath_hal *ah, +u32 ath9k_hw_getdefantenna(struct ath_hw *ah); +void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); +bool ath9k_hw_setantennaswitch(struct ath_hw *ah, enum ath9k_ant_setting settings, struct ath9k_channel *chan, u8 *tx_chainmask, u8 *rx_chainmask, u8 *antenna_cfgd); /* General Operation */ -bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); +bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val); u32 ath9k_hw_reverse_bits(u32 val, u32 n); -bool ath9k_get_channel_edges(struct ath_hal *ah, u16 flags, u16 *low, u16 *high); -u16 ath9k_hw_computetxtime(struct ath_hal *ah, struct ath_rate_table *rates, +bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); +u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates, u32 frameLen, u16 rateix, bool shortPreamble); -void ath9k_hw_get_channel_centers(struct ath_hal *ah, +void ath9k_hw_get_channel_centers(struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers); -u32 ath9k_hw_getrxfilter(struct ath_hal *ah); -void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); -bool ath9k_hw_phy_disable(struct ath_hal *ah); -bool ath9k_hw_disable(struct ath_hal *ah); -bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); -void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); -void ath9k_hw_setopmode(struct ath_hal *ah); -void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); +u32 ath9k_hw_getrxfilter(struct ath_hw *ah); +void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); +bool ath9k_hw_phy_disable(struct ath_hw *ah); +bool ath9k_hw_disable(struct ath_hw *ah); +bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); +void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); +void ath9k_hw_setopmode(struct ath_hw *ah); +void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); void ath9k_hw_setbssidmask(struct ath_softc *sc); void ath9k_hw_write_associd(struct ath_softc *sc); -u64 ath9k_hw_gettsf64(struct ath_hal *ah); -void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64); -void ath9k_hw_reset_tsf(struct ath_hal *ah); -bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting); -bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); -void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); -void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period); -void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, +u64 ath9k_hw_gettsf64(struct ath_hw *ah); +void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); +void ath9k_hw_reset_tsf(struct ath_hw *ah); +bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); +bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); +void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); +void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); +void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs); -bool ath9k_hw_setpower(struct ath_hal *ah, +bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); -void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); +void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore); /* Interrupt Handling */ -bool ath9k_hw_intrpend(struct ath_hal *ah); -bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); -enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); +bool ath9k_hw_intrpend(struct ath_hw *ah); +bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked); +enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah); +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints); -void ath9k_hw_btcoex_enable(struct ath_hal *ah); +void ath9k_hw_btcoex_enable(struct ath_hw *ah); #endif diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index b375a29..ac20714 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c @@ -16,40 +16,38 @@ #include "ath9k.h" -static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, +static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, struct ath9k_tx_queue_info *qi) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", - ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask, - ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask, - ahp->ah_txUrnInterruptMask); + ah->ah_txOkInterruptMask, ah->ah_txErrInterruptMask, + ah->ah_txDescInterruptMask, ah->ah_txEolInterruptMask, + ah->ah_txUrnInterruptMask); REG_WRITE(ah, AR_IMR_S0, - SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) - | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); + SM(ah->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) + | SM(ah->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); REG_WRITE(ah, AR_IMR_S1, - SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) - | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); + SM(ah->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) + | SM(ah->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); REG_RMW_FIELD(ah, AR_IMR_S2, - AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); + AR_IMR_S2_QCU_TXURN, ah->ah_txUrnInterruptMask); } -u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) +u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) { return REG_READ(ah, AR_QTXDP(q)); } -bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp) +bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) { REG_WRITE(ah, AR_QTXDP(q), txdp); return true; } -bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) +bool ath9k_hw_txstart(struct ath_hw *ah, u32 q) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); @@ -58,7 +56,7 @@ bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) return true; } -u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) +u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) { u32 npend; @@ -72,16 +70,15 @@ u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) return npend; } -bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel) +bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 txcfg, curLevel, newLevel; enum ath9k_int omask; if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) return false; - omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~ATH9K_INT_GLOBAL); + omask = ath9k_hw_set_interrupts(ah, ah->ah_maskReg & ~ATH9K_INT_GLOBAL); txcfg = REG_READ(ah, AR_TXCFG); curLevel = MS(txcfg, AR_FTRIG); @@ -102,12 +99,11 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel) return newLevel != curLevel; } -bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) +bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) { #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ #define ATH9K_TIME_QUANTUM 100 /* usec */ - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; u32 tsfLow, j, wait; @@ -118,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -180,7 +176,7 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) #undef ATH9K_TIME_QUANTUM } -bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 segLen, bool firstSeg, bool lastSeg, const struct ath_desc *ds0) { @@ -208,7 +204,7 @@ bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, return true; } -void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds) +void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -219,7 +215,7 @@ void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds) ads->ds_txstatus8 = ads->ds_txstatus9 = 0; } -int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds) +int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -294,14 +290,13 @@ int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds) return 0; } -void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags) { struct ar5416_desc *ads = AR5416DESC(ds); - struct ath_hal_5416 *ahp = AH5416(ah); - txPower += ahp->ah_txPowerIndexOffset; + txPower += ah->ah_txPowerIndexOffset; if (txPower > 63) txPower = 63; @@ -330,7 +325,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, } } -void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, struct ath_desc *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration, @@ -385,7 +380,7 @@ void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, last_ads->ds_ctl3 = ads->ds_ctl3; } -void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, u32 aggrLen) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -395,7 +390,7 @@ void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); } -void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, u32 numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -409,7 +404,7 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl6 = ctl6; } -void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) +void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -418,14 +413,14 @@ void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) ads->ds_ctl6 &= ~AR_PadDelim; } -void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds) +void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); } -void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, u32 burstDuration) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -434,7 +429,7 @@ void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); } -void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, u32 vmf) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -445,19 +440,16 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl0 &= ~AR_VirtMoreFrag; } -void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs) +void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs) { - struct ath_hal_5416 *ahp = AH5416(ah); - - *txqs &= ahp->ah_intrTxqs; - ahp->ah_intrTxqs &= ~(*txqs); + *txqs &= ah->ah_intrTxqs; + ah->ah_intrTxqs &= ~(*txqs); } -bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, +bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo) { u32 cw; - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; @@ -466,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -522,10 +514,9 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, return true; } -bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, +bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; @@ -534,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -558,10 +549,9 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, return true; } -int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, +int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_tx_queue_info *qi; struct ath9k_hw_capabilities *pCap = &ah->ah_caps; int q; @@ -581,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, break; case ATH9K_TX_QUEUE_DATA: for (q = 0; q < pCap->total_queues; q++) - if (ahp->ah_txq[q].tqi_type == + if (ah->ah_txq[q].tqi_type == ATH9K_TX_QUEUE_INACTIVE) break; if (q == pCap->total_queues) { @@ -597,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "tx queue %u already active\n", q); @@ -624,9 +614,8 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, return q; } -bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) +bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; @@ -634,7 +623,7 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return false; @@ -643,19 +632,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; - ahp->ah_txOkInterruptMask &= ~(1 << q); - ahp->ah_txErrInterruptMask &= ~(1 << q); - ahp->ah_txDescInterruptMask &= ~(1 << q); - ahp->ah_txEolInterruptMask &= ~(1 << q); - ahp->ah_txUrnInterruptMask &= ~(1 << q); + ah->ah_txOkInterruptMask &= ~(1 << q); + ah->ah_txErrInterruptMask &= ~(1 << q); + ah->ah_txDescInterruptMask &= ~(1 << q); + ah->ah_txEolInterruptMask &= ~(1 << q); + ah->ah_txUrnInterruptMask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; } -bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) +bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_channel *chan = ah->ah_curchan; struct ath9k_tx_queue_info *qi; @@ -666,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return true; @@ -784,31 +772,31 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) } if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) - ahp->ah_txOkInterruptMask |= 1 << q; + ah->ah_txOkInterruptMask |= 1 << q; else - ahp->ah_txOkInterruptMask &= ~(1 << q); + ah->ah_txOkInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) - ahp->ah_txErrInterruptMask |= 1 << q; + ah->ah_txErrInterruptMask |= 1 << q; else - ahp->ah_txErrInterruptMask &= ~(1 << q); + ah->ah_txErrInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) - ahp->ah_txDescInterruptMask |= 1 << q; + ah->ah_txDescInterruptMask |= 1 << q; else - ahp->ah_txDescInterruptMask &= ~(1 << q); + ah->ah_txDescInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) - ahp->ah_txEolInterruptMask |= 1 << q; + ah->ah_txEolInterruptMask |= 1 << q; else - ahp->ah_txEolInterruptMask &= ~(1 << q); + ah->ah_txEolInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) - ahp->ah_txUrnInterruptMask |= 1 << q; + ah->ah_txUrnInterruptMask |= 1 << q; else - ahp->ah_txUrnInterruptMask &= ~(1 << q); + ah->ah_txUrnInterruptMask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; } -int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, +int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pa, struct ath_desc *nds, u64 tsf) { struct ar5416_desc ads; @@ -873,7 +861,7 @@ int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, return 0; } -bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -890,7 +878,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, return true; } -bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) +bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) { u32 reg; @@ -917,17 +905,17 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) return true; } -void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp) +void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) { REG_WRITE(ah, AR_RXDP, rxdp); } -void ath9k_hw_rxena(struct ath_hal *ah) +void ath9k_hw_rxena(struct ath_hw *ah) { REG_WRITE(ah, AR_CR, AR_CR_RXE); } -void ath9k_hw_startpcureceive(struct ath_hal *ah) +void ath9k_hw_startpcureceive(struct ath_hw *ah) { ath9k_enable_mib_counters(ah); @@ -936,14 +924,14 @@ void ath9k_hw_startpcureceive(struct ath_hal *ah) REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); } -void ath9k_hw_stoppcurecv(struct ath_hal *ah) +void ath9k_hw_stoppcurecv(struct ath_hw *ah) { REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); ath9k_hw_disable_mib_counters(ah); } -bool ath9k_hw_stopdmarecv(struct ath_hal *ah) +bool ath9k_hw_stopdmarecv(struct ath_hw *ah) { REG_WRITE(ah, AR_CR, AR_CR_RXD); diff --git a/drivers/net/wireless/ath9k/mac.h b/drivers/net/wireless/ath9k/mac.h index 9012af2..74b660a 100644 --- a/drivers/net/wireless/ath9k/mac.h +++ b/drivers/net/wireless/ath9k/mac.h @@ -619,58 +619,58 @@ enum ath9k_ht_extprotspacing { ATH9K_HT_EXTPROTSPACING_25 = 1, }; -struct ath_hal; +struct ath_hw; struct ath9k_channel; struct ath_rate_table; -u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); -bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp); -bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); -u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); -bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel); -bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); -bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, +u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); +bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); +bool ath9k_hw_txstart(struct ath_hw *ah, u32 q); +u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); +bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); +bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q); +bool ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 segLen, bool firstSeg, bool lastSeg, const struct ath_desc *ds0); -void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); -int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds); +int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds); +void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags); -void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, struct ath_desc *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration, struct ath9k_11n_rate_series series[], u32 nseries, u32 flags); -void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, u32 aggrLen); -void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, u32 numDelims); -void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds); +void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds); +void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, u32 burstDuration); -void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, u32 vmf); -void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); -bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, +void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); +bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo); -bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, +bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo); -int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, +int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo); -bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); -bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); -int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); +bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); +int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pa, struct ath_desc *nds, u64 tsf); -bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags); -bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); -void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); -void ath9k_hw_rxena(struct ath_hal *ah); -void ath9k_hw_startpcureceive(struct ath_hal *ah); -void ath9k_hw_stoppcurecv(struct ath_hal *ah); -bool ath9k_hw_stopdmarecv(struct ath_hal *ah); +bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); +void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); +void ath9k_hw_rxena(struct ath_hw *ah); +void ath9k_hw_startpcureceive(struct ath_hw *ah); +void ath9k_hw_stoppcurecv(struct ath_hw *ah); +bool ath9k_hw_stopdmarecv(struct ath_hw *ah); #endif /* MAC_H */ diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index bafefbe..a50f989 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -137,7 +137,7 @@ static void ath_cache_conf_rate(struct ath_softc *sc, static void ath_update_txpow(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; u32 txpow; if (sc->curtxpow != sc->config.txpowlimit) { @@ -234,7 +234,7 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band) */ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; bool fastcc = true, stopped; struct ieee80211_hw *hw = sc->hw; struct ieee80211_channel *channel = hw->conf.channel; @@ -309,7 +309,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) static void ath_ani_calibrate(unsigned long data) { struct ath_softc *sc; - struct ath_hal *ah; + struct ath_hw *ah; bool longcal = false; bool shortcal = false; bool aniflag = false; @@ -479,7 +479,7 @@ static void ath9k_tasklet(unsigned long data) irqreturn_t ath_isr(int irq, void *dev) { struct ath_softc *sc = dev; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; enum ath9k_int status; bool sched = false; @@ -1091,7 +1091,7 @@ fail: static void ath_radio_enable(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_channel *channel = sc->hw->conf.channel; int r; @@ -1132,7 +1132,7 @@ static void ath_radio_enable(struct ath_softc *sc) static void ath_radio_disable(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_channel *channel = sc->hw->conf.channel; int r; @@ -1167,7 +1167,7 @@ static void ath_radio_disable(struct ath_softc *sc) static bool ath_is_rfkill_set(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == ah->ah_rfkill_polarity; @@ -1345,7 +1345,7 @@ void ath_detach(struct ath_softc *sc) static int ath_init(u16 devid, struct ath_softc *sc) { - struct ath_hal *ah = NULL; + struct ath_hw *ah = NULL; int status; int error = 0, i; int csz = 0; @@ -1370,7 +1370,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) /* XXX assert csz is non-zero */ sc->cachelsz = csz << 2; /* convert to bytes */ - ah = ath9k_hw_attach(devid, sc, sc->mem, &status); + ah = ath9k_hw_attach(devid, sc, &status); if (ah == NULL) { DPRINTF(sc, ATH_DBG_FATAL, "Unable to attach hardware; HAL status %d\n", status); @@ -1671,7 +1671,7 @@ detach: int ath_reset(struct ath_softc *sc, bool retry_tx) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_hw *hw = sc->hw; int r; @@ -2272,7 +2272,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, struct ieee80211_if_conf *conf) { struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_vif *avp = (void *)vif->drv_priv; u32 rfilt = 0; int error, i; diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index 192c8c4..eac8db7 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -56,7 +56,7 @@ static void ath_pci_cleanup(struct ath_softc *sc) pci_disable_device(pdev); } -static bool ath_pci_eeprom_read(struct ath_hal *ah, u32 off, u16 *data) +static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) { (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); @@ -87,7 +87,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) u8 csz; u32 val; int ret = 0; - struct ath_hal *ah; + struct ath_hw *ah; if (pci_enable_device(pdev)) return -EIO; diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index ea29941..da4165b 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -17,16 +17,14 @@ #include "ath9k.h" void -ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex, +ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, int regWrites) { - struct ath_hal_5416 *ahp = AH5416(ah); - - REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites); } bool -ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) +ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { u32 channelSel = 0; u32 bModeSynth = 0; @@ -93,14 +91,13 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) REG_WRITE(ah, AR_PHY(0x37), reg32); ah->ah_curchan = chan; - - AH5416(ah)->ah_curchanRadIndex = -1; + ah->ah_curchanRadIndex = -1; return true; } bool -ath9k_hw_ar9280_set_channel(struct ath_hal *ah, +ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { u16 bMode, fracMode, aModeRefSel = 0; @@ -164,8 +161,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah, REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); ah->ah_curchan = chan; - - AH5416(ah)->ah_curchanRadIndex = -1; + ah->ah_curchanRadIndex = -1; return true; } @@ -198,11 +194,9 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, } bool -ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, +ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex) { - struct ath_hal_5416 *ahp = AH5416(ah); - u32 eepMinorRev; u32 ob5GHz = 0, db5GHz = 0; u32 ob2GHz = 0, db2GHz = 0; @@ -213,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV); - RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1); + RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); - RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1); + RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1); - RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1); + RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1); - RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3, + RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3, modesIndex); { int i; - for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) { - ahp->ah_analogBank6Data[i] = - INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex); + for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) { + ah->ah_analogBank6Data[i] = + INI_RA(&ah->ah_iniBank6TPC, i, modesIndex); } } @@ -233,137 +227,132 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, if (IS_CHAN_2GHZ(chan)) { ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2); db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob2GHz, 3, 197, 0); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, db2GHz, 3, 194, 0); } else { ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5); db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob5GHz, 3, 203, 0); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, db5GHz, 3, 200, 0); } } - RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1); + RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data, regWrites); return true; } void -ath9k_hw_rfdetach(struct ath_hal *ah) +ath9k_hw_rfdetach(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - if (ahp->ah_analogBank0Data != NULL) { - kfree(ahp->ah_analogBank0Data); - ahp->ah_analogBank0Data = NULL; + if (ah->ah_analogBank0Data != NULL) { + kfree(ah->ah_analogBank0Data); + ah->ah_analogBank0Data = NULL; } - if (ahp->ah_analogBank1Data != NULL) { - kfree(ahp->ah_analogBank1Data); - ahp->ah_analogBank1Data = NULL; + if (ah->ah_analogBank1Data != NULL) { + kfree(ah->ah_analogBank1Data); + ah->ah_analogBank1Data = NULL; } - if (ahp->ah_analogBank2Data != NULL) { - kfree(ahp->ah_analogBank2Data); - ahp->ah_analogBank2Data = NULL; + if (ah->ah_analogBank2Data != NULL) { + kfree(ah->ah_analogBank2Data); + ah->ah_analogBank2Data = NULL; } - if (ahp->ah_analogBank3Data != NULL) { - kfree(ahp->ah_analogBank3Data); - ahp->ah_analogBank3Data = NULL; + if (ah->ah_analogBank3Data != NULL) { + kfree(ah->ah_analogBank3Data); + ah->ah_analogBank3Data = NULL; } - if (ahp->ah_analogBank6Data != NULL) { - kfree(ahp->ah_analogBank6Data); - ahp->ah_analogBank6Data = NULL; + if (ah->ah_analogBank6Data != NULL) { + kfree(ah->ah_analogBank6Data); + ah->ah_analogBank6Data = NULL; } - if (ahp->ah_analogBank6TPCData != NULL) { - kfree(ahp->ah_analogBank6TPCData); - ahp->ah_analogBank6TPCData = NULL; + if (ah->ah_analogBank6TPCData != NULL) { + kfree(ah->ah_analogBank6TPCData); + ah->ah_analogBank6TPCData = NULL; } - if (ahp->ah_analogBank7Data != NULL) { - kfree(ahp->ah_analogBank7Data); - ahp->ah_analogBank7Data = NULL; + if (ah->ah_analogBank7Data != NULL) { + kfree(ah->ah_analogBank7Data); + ah->ah_analogBank7Data = NULL; } - if (ahp->ah_addac5416_21 != NULL) { - kfree(ahp->ah_addac5416_21); - ahp->ah_addac5416_21 = NULL; + if (ah->ah_addac5416_21 != NULL) { + kfree(ah->ah_addac5416_21); + ah->ah_addac5416_21 = NULL; } - if (ahp->ah_bank6Temp != NULL) { - kfree(ahp->ah_bank6Temp); - ahp->ah_bank6Temp = NULL; + if (ah->ah_bank6Temp != NULL) { + kfree(ah->ah_bank6Temp); + ah->ah_bank6Temp = NULL; } } -bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) +bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (!AR_SREV_9280_10_OR_LATER(ah)) { - - ahp->ah_analogBank0Data = + ah->ah_analogBank0Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank0.ia_rows), GFP_KERNEL); - ahp->ah_analogBank1Data = + ah->ah_iniBank0.ia_rows), GFP_KERNEL); + ah->ah_analogBank1Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank1.ia_rows), GFP_KERNEL); - ahp->ah_analogBank2Data = + ah->ah_iniBank1.ia_rows), GFP_KERNEL); + ah->ah_analogBank2Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank2.ia_rows), GFP_KERNEL); - ahp->ah_analogBank3Data = + ah->ah_iniBank2.ia_rows), GFP_KERNEL); + ah->ah_analogBank3Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank3.ia_rows), GFP_KERNEL); - ahp->ah_analogBank6Data = + ah->ah_iniBank3.ia_rows), GFP_KERNEL); + ah->ah_analogBank6Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank6.ia_rows), GFP_KERNEL); - ahp->ah_analogBank6TPCData = + ah->ah_iniBank6.ia_rows), GFP_KERNEL); + ah->ah_analogBank6TPCData = kzalloc((sizeof(u32) * - ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL); - ahp->ah_analogBank7Data = + ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL); + ah->ah_analogBank7Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank7.ia_rows), GFP_KERNEL); - - if (ahp->ah_analogBank0Data == NULL - || ahp->ah_analogBank1Data == NULL - || ahp->ah_analogBank2Data == NULL - || ahp->ah_analogBank3Data == NULL - || ahp->ah_analogBank6Data == NULL - || ahp->ah_analogBank6TPCData == NULL - || ahp->ah_analogBank7Data == NULL) { + ah->ah_iniBank7.ia_rows), GFP_KERNEL); + + if (ah->ah_analogBank0Data == NULL + || ah->ah_analogBank1Data == NULL + || ah->ah_analogBank2Data == NULL + || ah->ah_analogBank3Data == NULL + || ah->ah_analogBank6Data == NULL + || ah->ah_analogBank6TPCData == NULL + || ah->ah_analogBank7Data == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate RF banks\n"); *status = -ENOMEM; return false; } - ahp->ah_addac5416_21 = + ah->ah_addac5416_21 = kzalloc((sizeof(u32) * - ahp->ah_iniAddac.ia_rows * - ahp->ah_iniAddac.ia_columns), GFP_KERNEL); - if (ahp->ah_addac5416_21 == NULL) { + ah->ah_iniAddac.ia_rows * + ah->ah_iniAddac.ia_columns), GFP_KERNEL); + if (ah->ah_addac5416_21 == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate ah_addac5416_21\n"); *status = -ENOMEM; return false; } - ahp->ah_bank6Temp = + ah->ah_bank6Temp = kzalloc((sizeof(u32) * - ahp->ah_iniBank6.ia_rows), GFP_KERNEL); - if (ahp->ah_bank6Temp == NULL) { + ah->ah_iniBank6.ia_rows), GFP_KERNEL); + if (ah->ah_bank6Temp == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate ah_bank6Temp\n"); *status = -ENOMEM; @@ -375,23 +364,22 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) } void -ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) +ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) { int i, regWrites = 0; - struct ath_hal_5416 *ahp = AH5416(ah); u32 bank6SelMask; - u32 *bank6Temp = ahp->ah_bank6Temp; + u32 *bank6Temp = ah->ah_bank6Temp; - switch (ahp->ah_diversityControl) { + switch (ah->ah_diversityControl) { case ATH9K_ANT_FIXED_A: bank6SelMask = - (ahp-> + (ah-> ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : REDUCE_CHAIN_1; break; case ATH9K_ANT_FIXED_B: bank6SelMask = - (ahp-> + (ah-> ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : REDUCE_CHAIN_0; break; @@ -403,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) break; } - for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++) - bank6Temp[i] = ahp->ah_analogBank6Data[i]; + for (i = 0; i < ah->ah_iniBank6.ia_rows; i++) + bank6Temp[i] = ah->ah_analogBank6Data[i]; REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); @@ -418,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites); + REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites); REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); #ifdef ALTER_SWITCH diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h index 3a406a5..71a7f5a 100644 --- a/drivers/net/wireless/ath9k/phy.h +++ b/drivers/net/wireless/ath9k/phy.h @@ -17,19 +17,19 @@ #ifndef PHY_H #define PHY_H -bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah, +bool ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan); -bool ath9k_hw_set_channel(struct ath_hal *ah, +bool ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan); -void ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, +void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, int regWrites); -bool ath9k_hw_set_rf_regs(struct ath_hal *ah, +bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex); -void ath9k_hw_decrease_chain_power(struct ath_hal *ah, +void ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan); -bool ath9k_hw_init_rf(struct ath_hal *ah, +bool ath9k_hw_init_rf(struct ath_hw *ah, int *status); #define AR_PHY_BASE 0x9800 @@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, #define ATH9K_KEY_XOR 0xaa #define ATH9K_IS_MIC_ENABLED(ah) \ - (AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) + ((ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) #define ANTSWAP_AB 0x0001 #define REDUCE_CHAIN_0 0x00000050 diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index c51c085..7c011b1 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -26,7 +26,7 @@ */ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_desc *ds; struct sk_buff *skb; @@ -233,7 +233,7 @@ rx_next: static void ath_opmode_init(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; u32 rfilt, mfilt[2]; /* configure rx filter */ @@ -391,7 +391,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc) int ath_startrecv(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf, *tbf; spin_lock_bh(&sc->rx.rxbuflock); @@ -421,7 +421,7 @@ start_recv: bool ath_stoprecv(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; bool stopped; ath9k_hw_stoppcurecv(ah); @@ -452,7 +452,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) struct ath_desc *ds; struct sk_buff *skb = NULL, *requeue_skb; struct ieee80211_rx_status rx_status; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_hdr *hdr; int hdrlen, padsize, retval; bool decrypt_error = false; diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c index 32dd0cb..8c2b56a 100644 --- a/drivers/net/wireless/ath9k/regd.c +++ b/drivers/net/wireless/ath9k/regd.c @@ -106,17 +106,17 @@ static const struct ieee80211_regdomain ath9k_world_regdom_67_68_6A = { } }; -static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah) +static u16 ath9k_regd_get_eepromRD(struct ath_hw *ah) { return ah->regulatory.current_rd & ~WORLDWIDE_ROAMING_FLAG; } -u16 ath9k_regd_get_rd(struct ath_hal *ah) +u16 ath9k_regd_get_rd(struct ath_hw *ah) { return ath9k_regd_get_eepromRD(ah); } -bool ath9k_is_world_regd(struct ath_hal *ah) +bool ath9k_is_world_regd(struct ath_hw *ah) { return isWwrSKU(ah); } @@ -127,7 +127,7 @@ const struct ieee80211_regdomain *ath9k_default_world_regdomain(void) return &ath9k_world_regdom_64; } -const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah) +const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hw *ah) { switch (ah->regulatory.regpair->regDmnEnum) { case 0x60: @@ -282,7 +282,7 @@ void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby) { struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; switch (ah->regulatory.regpair->regDmnEnum) { case 0x60: @@ -322,7 +322,7 @@ int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) return 0; } -bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah) +bool ath9k_regd_is_eeprom_valid(struct ath_hw *ah) { u16 rd = ath9k_regd_get_eepromRD(ah); int i; @@ -371,7 +371,7 @@ ath9k_regd_find_country_by_rd(int regdmn) } /* Returns the map of the EEPROM set RD to a country code */ -static u16 ath9k_regd_get_default_country(struct ath_hal *ah) +static u16 ath9k_regd_get_default_country(struct ath_hw *ah) { u16 rd; @@ -402,7 +402,7 @@ ath9k_get_regpair(int regdmn) return NULL; } -int ath9k_regd_init(struct ath_hal *ah) +int ath9k_regd_init(struct ath_hw *ah) { struct country_code_to_enum_rd *country = NULL; int regdmn; @@ -462,7 +462,7 @@ int ath9k_regd_init(struct ath_hal *ah) return 0; } -u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan) +u32 ath9k_regd_get_ctl(struct ath_hw *ah, struct ath9k_channel *chan) { u32 ctl = NO_CTL; diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h index 65abdf4..39420de 100644 --- a/drivers/net/wireless/ath9k/regd.h +++ b/drivers/net/wireless/ath9k/regd.h @@ -239,17 +239,17 @@ enum CountryCode { CTRY_BELGIUM2 = 5002 }; -u16 ath9k_regd_get_rd(struct ath_hal *ah); -bool ath9k_is_world_regd(struct ath_hal *ah); -const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah); +u16 ath9k_regd_get_rd(struct ath_hw *ah); +bool ath9k_is_world_regd(struct ath_hw *ah); +const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hw *ah); const struct ieee80211_regdomain *ath9k_default_world_regdomain(void); void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby); void ath9k_reg_apply_radar_flags(struct wiphy *wiphy); -int ath9k_regd_init(struct ath_hal *ah); -bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah); -u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); +int ath9k_regd_init(struct ath_hw *ah); +bool ath9k_regd_is_eeprom_valid(struct ath_hw *ah); +u32 ath9k_regd_get_ctl(struct ath_hw *ah, struct ath9k_channel *chan); int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request); -void ath9k_regd_get_current_country(struct ath_hal *ah, +void ath9k_regd_get_current_country(struct ath_hw *ah, struct ath9k_country_entry *ctry); #endif diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c index 7773760..3fff334 100644 --- a/drivers/net/wireless/ath9k/xmit.c +++ b/drivers/net/wireless/ath9k/xmit.c @@ -809,7 +809,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc, struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath9k_tx_queue_info qi; int qnum; @@ -926,7 +926,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_tx_queue_info *qinfo) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; int error = 0; struct ath9k_tx_queue_info qi; @@ -1047,7 +1047,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_txq *txq; int i, npend = 0; @@ -1165,7 +1165,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype) static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, struct list_head *head) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf; /* @@ -1580,7 +1580,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, struct list_head bf_head; struct ath_desc *ds; struct ath_atx_tid *tid; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; int frm_type; frm_type = get_hw_packet_type(skb); @@ -1879,7 +1879,7 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf, *lastbf, *bf_held = NULL; struct list_head bf_head; struct ath_desc *ds; -- 1.5.6.3 From abe2569a10d0e99a8600d72689d8916b79e887a3 Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 10:21:33 +0530 Subject: [PATCH] ath9k: Add callbacks hooks for EEPROM operations This is preparatory work for removing the individual function pointer assignments in eeprom.c Signed-off-by: Sujith --- drivers/net/wireless/ath9k/eeprom.h | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 81a7a70..47c8eea 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -447,6 +447,23 @@ enum hal_eep_map { EEP_MAP_MAX }; +struct eeprom_ops { + int (*check_eeprom)(struct ath_hw *hw); + u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); + bool (*fill_eeprom)(struct ath_hw *hw); + int (*get_eeprom_ver)(struct ath_hw *hw); + int (*get_eeprom_rev)(struct ath_hw *hw); + u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band); + u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw, + struct ath9k_channel *chan); + bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); + void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); + int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, + u16 cfgCtl, u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, u8 powerLimit); + u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); +}; + #define ar5416_get_eep_ver(_ah) \ (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) #define ar5416_get_eep_rev(_ah) \ -- 1.5.6.3 From 3e1dcc9173632311140157ef49118cf2cc22467c Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 10:30:56 +0530 Subject: [PATCH] ath9k: Cleanup EEPROM operations This patch removes the various function pointer assignments and unifies them in a single ops structure. Signed-off-by: Sujith --- drivers/net/wireless/ath9k/calib.c | 4 +- drivers/net/wireless/ath9k/eeprom.c | 2828 +++++++++++++++++------------------ drivers/net/wireless/ath9k/eeprom.h | 30 +- drivers/net/wireless/ath9k/hw.c | 72 +- drivers/net/wireless/ath9k/hw.h | 1 + drivers/net/wireless/ath9k/phy.c | 10 +- 6 files changed, 1453 insertions(+), 1492 deletions(-) diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 8c44d5a..7e70a81 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -172,10 +172,10 @@ static bool getNoiseFloorThresh(struct ath_hw *ah, { switch (band) { case IEEE80211_BAND_5GHZ: - *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5); + *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5); break; case IEEE80211_BAND_2GHZ: - *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2); + *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2); break; default: BUG_ON(1); diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 94e7993..2e604e1 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -95,195 +95,216 @@ static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) return sc->bus_ops->eeprom_read(ah, off, data); } -static bool ath9k_hw_fill_4k_eeprom(struct ath_hw *ah) +static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, + u8 *pVpdList, u16 numIntercepts, + u8 *pRetVpdList) { -#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - u16 *eep_data; - int addr, eep_start_loc = 0; - - eep_start_loc = 64; + u16 i, k; + u8 currPwr = pwrMin; + u16 idxL = 0, idxR = 0; - if (!ath9k_hw_use_flash(ah)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Reading from EEPROM, not flash\n"); + for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { + ath9k_hw_get_lower_upper_index(currPwr, pPwrList, + numIntercepts, &(idxL), + &(idxR)); + if (idxR < 1) + idxR = 1; + if (idxL == numIntercepts - 1) + idxL = (u16) (numIntercepts - 2); + if (pPwrList[idxL] == pPwrList[idxR]) + k = pVpdList[idxL]; + else + k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / + (pPwrList[idxR] - pPwrList[idxL])); + pRetVpdList[i] = (u8) k; + currPwr += 2; } - eep_data = (u16 *)eep; - - for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { - if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Unable to read eeprom region \n"); - return false; - } - eep_data++; - } return true; -#undef SIZE_EEPROM_4K } -static bool ath9k_hw_fill_def_eeprom(struct ath_hw *ah) +static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, + struct ath9k_channel *chan, + struct cal_target_power_leg *powInfo, + u16 numChannels, + struct cal_target_power_leg *pNewPower, + u16 numRates, bool isExtTarget) { -#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - u16 *eep_data; - int addr, ar5416_eep_start_loc = 0x100; + struct chan_centers centers; + u16 clo, chi; + int i; + int matchIndex = -1, lowIndex = -1; + u16 freq; - eep_data = (u16 *)eep; + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; - for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { - if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, - eep_data)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Unable to read eeprom region\n"); - return false; + if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, + IS_CHAN_2GHZ(chan))) { + matchIndex = 0; + } else { + for (i = 0; (i < numChannels) && + (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { + if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) { + matchIndex = i; + break; + } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) && + (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, + IS_CHAN_2GHZ(chan)))) { + lowIndex = i - 1; + break; + } } - eep_data++; + if ((matchIndex == -1) && (lowIndex == -1)) + matchIndex = i - 1; } - return true; -#undef SIZE_EEPROM_DEF -} -static bool (*ath9k_fill_eeprom[]) (struct ath_hw *) = { - ath9k_hw_fill_def_eeprom, - ath9k_hw_fill_4k_eeprom -}; + if (matchIndex != -1) { + *pNewPower = powInfo[matchIndex]; + } else { + clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, + IS_CHAN_2GHZ(chan)); + chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, + IS_CHAN_2GHZ(chan)); -static inline bool ath9k_hw_fill_eeprom(struct ath_hw *ah) -{ - return ath9k_fill_eeprom[ah->ah_eep_map](ah); + for (i = 0; i < numRates; i++) { + pNewPower->tPow2x[i] = + (u8)ath9k_hw_interpolate(freq, clo, chi, + powInfo[lowIndex].tPow2x[i], + powInfo[lowIndex + 1].tPow2x[i]); + } + } } -static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) +static void ath9k_hw_get_target_powers(struct ath_hw *ah, + struct ath9k_channel *chan, + struct cal_target_power_ht *powInfo, + u16 numChannels, + struct cal_target_power_ht *pNewPower, + u16 numRates, bool isHt40Target) { - struct ar5416_eeprom_def *eep = - (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; - u16 *eepdata, temp, magic, magic2; - u32 sum = 0, el; - bool need_swap = false; - int i, addr, size; - - if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, - &magic)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Reading Magic # failed\n"); - return false; - } - - if (!ath9k_hw_use_flash(ah)) { + struct chan_centers centers; + u16 clo, chi; + int i; + int matchIndex = -1, lowIndex = -1; + u16 freq; - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Read Magic = 0x%04X\n", magic); + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + freq = isHt40Target ? centers.synth_center : centers.ctl_center; - if (magic != AR5416_EEPROM_MAGIC) { - magic2 = swab16(magic); + if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { + matchIndex = 0; + } else { + for (i = 0; (i < numChannels) && + (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { + if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) { + matchIndex = i; + break; + } else + if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) && + (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, + IS_CHAN_2GHZ(chan)))) { + lowIndex = i - 1; + break; + } + } + if ((matchIndex == -1) && (lowIndex == -1)) + matchIndex = i - 1; + } - if (magic2 == AR5416_EEPROM_MAGIC) { - size = sizeof(struct ar5416_eeprom_def); - need_swap = true; - eepdata = (u16 *) (&ah->ah_eeprom); + if (matchIndex != -1) { + *pNewPower = powInfo[matchIndex]; + } else { + clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, + IS_CHAN_2GHZ(chan)); + chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, + IS_CHAN_2GHZ(chan)); - for (addr = 0; addr < size / sizeof(u16); addr++) { - temp = swab16(*eepdata); - *eepdata = temp; - eepdata++; + for (i = 0; i < numRates; i++) { + pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq, + clo, chi, + powInfo[lowIndex].tPow2x[i], + powInfo[lowIndex + 1].tPow2x[i]); + } + } +} - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "0x%04X ", *eepdata); +static u16 ath9k_hw_get_max_edge_power(u16 freq, + struct cal_ctl_edges *pRdEdgesPower, + bool is2GHz, int num_band_edges) +{ + u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + int i; - if (((addr + 1) % 6) == 0) - DPRINTF(ah->ah_sc, - ATH_DBG_EEPROM, "\n"); - } - } else { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Invalid EEPROM Magic. " - "endianness mismatch.\n"); - return -EINVAL; + for (i = 0; (i < num_band_edges) && + (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { + if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { + twiceMaxEdgePower = pRdEdgesPower[i].tPower; + break; + } else if ((i > 0) && + (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, + is2GHz))) { + if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, + is2GHz) < freq && + pRdEdgesPower[i - 1].flag) { + twiceMaxEdgePower = + pRdEdgesPower[i - 1].tPower; } + break; } } - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", - need_swap ? "True" : "False"); + return twiceMaxEdgePower; +} - if (need_swap) - el = swab16(ah->ah_eeprom.def.baseEepHeader.length); - else - el = ah->ah_eeprom.def.baseEepHeader.length; +/****************************************/ +/* EEPROM Operations for 4K sized cards */ +/****************************************/ - if (el > sizeof(struct ar5416_eeprom_def)) - el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); - else - el = el / sizeof(u16); +static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) +{ + return ((ah->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF); +} - eepdata = (u16 *)(&ah->ah_eeprom); +static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) +{ + return ((ah->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF); +} - for (i = 0; i < el; i++) - sum ^= *eepdata++; +static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) +{ +#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + u16 *eep_data; + int addr, eep_start_loc = 0; - if (need_swap) { - u32 integer, j; - u16 word; + eep_start_loc = 64; + if (!ath9k_hw_use_flash(ah)) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "EEPROM Endianness is not native.. Changing \n"); - - word = swab16(eep->baseEepHeader.length); - eep->baseEepHeader.length = word; - - word = swab16(eep->baseEepHeader.checksum); - eep->baseEepHeader.checksum = word; - - word = swab16(eep->baseEepHeader.version); - eep->baseEepHeader.version = word; - - word = swab16(eep->baseEepHeader.regDmn[0]); - eep->baseEepHeader.regDmn[0] = word; - - word = swab16(eep->baseEepHeader.regDmn[1]); - eep->baseEepHeader.regDmn[1] = word; - - word = swab16(eep->baseEepHeader.rfSilent); - eep->baseEepHeader.rfSilent = word; - - word = swab16(eep->baseEepHeader.blueToothOptions); - eep->baseEepHeader.blueToothOptions = word; - - word = swab16(eep->baseEepHeader.deviceCap); - eep->baseEepHeader.deviceCap = word; - - for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { - struct modal_eep_header *pModal = - &eep->modalHeader[j]; - integer = swab32(pModal->antCtrlCommon); - pModal->antCtrlCommon = integer; + "Reading from EEPROM, not flash\n"); + } - for (i = 0; i < AR5416_MAX_CHAINS; i++) { - integer = swab32(pModal->antCtrlChain[i]); - pModal->antCtrlChain[i] = integer; - } + eep_data = (u16 *)eep; - for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { - word = swab16(pModal->spurChans[i].spurChan); - pModal->spurChans[i].spurChan = word; - } + for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { + if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Unable to read eeprom region \n"); + return false; } + eep_data++; } - - if (sum != 0xffff || ar5416_get_eep_ver(ah) != AR5416_EEP_VER || - ar5416_get_eep_rev(ah) < AR5416_EEP_NO_BACK_VER) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep_ver(ah)); - return -EINVAL; - } - - return 0; + return true; +#undef SIZE_EEPROM_4K } -static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah) +static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) { #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) struct ar5416_eeprom_4k *eep = @@ -397,11 +418,11 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah) } } - if (sum != 0xffff || ar5416_get_eep4k_ver(ah) != AR5416_EEP_VER || - ar5416_get_eep4k_rev(ah) < AR5416_EEP_NO_BACK_VER) { + if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || + ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep4k_ver(ah)); + sum, ah->eep_ops->get_eeprom_ver(ah)); return -EINVAL; } @@ -409,43 +430,45 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah) #undef EEPROM_4K_SIZE } -static int (*ath9k_check_eeprom[]) (struct ath_hw *) = { - ath9k_hw_check_def_eeprom, - ath9k_hw_check_4k_eeprom -}; - -static inline int ath9k_hw_check_eeprom(struct ath_hw *ah) -{ - return ath9k_check_eeprom[ah->ah_eep_map](ah); -} - -static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, - u8 *pVpdList, u16 numIntercepts, - u8 *pRetVpdList) +static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, + enum eeprom_param param) { - u16 i, k; - u8 currPwr = pwrMin; - u16 idxL = 0, idxR = 0; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct modal_eep_4k_header *pModal = &eep->modalHeader; + struct base_eep_header_4k *pBase = &eep->baseEepHeader; - for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { - ath9k_hw_get_lower_upper_index(currPwr, pPwrList, - numIntercepts, &(idxL), - &(idxR)); - if (idxR < 1) - idxR = 1; - if (idxL == numIntercepts - 1) - idxL = (u16) (numIntercepts - 2); - if (pPwrList[idxL] == pPwrList[idxR]) - k = pVpdList[idxL]; - else - k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + - (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / - (pPwrList[idxR] - pPwrList[idxL])); - pRetVpdList[i] = (u8) k; - currPwr += 2; + switch (param) { + case EEP_NFTHRESH_2: + return pModal[1].noiseFloorThreshCh[0]; + case AR_EEPROM_MAC(0): + return pBase->macAddr[0] << 8 | pBase->macAddr[1]; + case AR_EEPROM_MAC(1): + return pBase->macAddr[2] << 8 | pBase->macAddr[3]; + case AR_EEPROM_MAC(2): + return pBase->macAddr[4] << 8 | pBase->macAddr[5]; + case EEP_REG_0: + return pBase->regDmn[0]; + case EEP_REG_1: + return pBase->regDmn[1]; + case EEP_OP_CAP: + return pBase->deviceCap; + case EEP_OP_MODE: + return pBase->opCapFlags; + case EEP_RF_SILENT: + return pBase->rfSilent; + case EEP_OB_2: + return pModal->ob_01; + case EEP_DB_2: + return pModal->db1_01; + case EEP_MINOR_REV: + return pBase->version & AR5416_EEP_VER_MINOR_MASK; + case EEP_TX_MASK: + return pBase->txMask; + case EEP_RX_MASK: + return pBase->rxMask; + default: + return 0; } - - return true; } static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, @@ -616,435 +639,6 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, #undef TMP_VAL_VPD_TABLE } -static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, - struct ath9k_channel *chan, - struct cal_data_per_freq *pRawDataSet, - u8 *bChans, u16 availPiers, - u16 tPdGainOverlap, int16_t *pMinCalPower, - u16 *pPdGainBoundaries, u8 *pPDADCValues, - u16 numXpdGains) -{ - int i, j, k; - int16_t ss; - u16 idxL = 0, idxR = 0, numPiers; - static u8 vpdTableL[AR5416_NUM_PD_GAINS] - [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - static u8 vpdTableR[AR5416_NUM_PD_GAINS] - [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - static u8 vpdTableI[AR5416_NUM_PD_GAINS] - [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - - u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; - u8 minPwrT4[AR5416_NUM_PD_GAINS]; - u8 maxPwrT4[AR5416_NUM_PD_GAINS]; - int16_t vpdStep; - int16_t tmpVal; - u16 sizeCurrVpdTable, maxIndex, tgtIndex; - bool match; - int16_t minDelta = 0; - struct chan_centers centers; - - ath9k_hw_get_channel_centers(ah, chan, ¢ers); - - for (numPiers = 0; numPiers < availPiers; numPiers++) { - if (bChans[numPiers] == AR5416_BCHAN_UNUSED) - break; - } - - match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center, - IS_CHAN_2GHZ(chan)), - bChans, numPiers, &idxL, &idxR); - - if (match) { - for (i = 0; i < numXpdGains; i++) { - minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; - maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], - pRawDataSet[idxL].pwrPdg[i], - pRawDataSet[idxL].vpdPdg[i], - AR5416_PD_GAIN_ICEPTS, - vpdTableI[i]); - } - } else { - for (i = 0; i < numXpdGains; i++) { - pVpdL = pRawDataSet[idxL].vpdPdg[i]; - pPwrL = pRawDataSet[idxL].pwrPdg[i]; - pVpdR = pRawDataSet[idxR].vpdPdg[i]; - pPwrR = pRawDataSet[idxR].pwrPdg[i]; - - minPwrT4[i] = max(pPwrL[0], pPwrR[0]); - - maxPwrT4[i] = - min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], - pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); - - - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], - pPwrL, pVpdL, - AR5416_PD_GAIN_ICEPTS, - vpdTableL[i]); - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], - pPwrR, pVpdR, - AR5416_PD_GAIN_ICEPTS, - vpdTableR[i]); - - for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { - vpdTableI[i][j] = - (u8)(ath9k_hw_interpolate((u16) - FREQ2FBIN(centers. - synth_center, - IS_CHAN_2GHZ - (chan)), - bChans[idxL], bChans[idxR], - vpdTableL[i][j], vpdTableR[i][j])); - } - } - } - - *pMinCalPower = (int16_t)(minPwrT4[0] / 2); - - k = 0; - - for (i = 0; i < numXpdGains; i++) { - if (i == (numXpdGains - 1)) - pPdGainBoundaries[i] = - (u16)(maxPwrT4[i] / 2); - else - pPdGainBoundaries[i] = - (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); - - pPdGainBoundaries[i] = - min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); - - if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { - minDelta = pPdGainBoundaries[0] - 23; - pPdGainBoundaries[0] = 23; - } else { - minDelta = 0; - } - - if (i == 0) { - if (AR_SREV_9280_10_OR_LATER(ah)) - ss = (int16_t)(0 - (minPwrT4[i] / 2)); - else - ss = 0; - } else { - ss = (int16_t)((pPdGainBoundaries[i - 1] - - (minPwrT4[i] / 2)) - - tPdGainOverlap + 1 + minDelta); - } - vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); - - while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { - tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); - pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); - ss++; - } - - sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); - tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - - (minPwrT4[i] / 2)); - maxIndex = (tgtIndex < sizeCurrVpdTable) ? - tgtIndex : sizeCurrVpdTable; - - while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { - pPDADCValues[k++] = vpdTableI[i][ss++]; - } - - vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - - vpdTableI[i][sizeCurrVpdTable - 2]); - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); - - if (tgtIndex > maxIndex) { - while ((ss <= tgtIndex) && - (k < (AR5416_NUM_PDADC_VALUES - 1))) { - tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + - (ss - maxIndex + 1) * vpdStep)); - pPDADCValues[k++] = (u8)((tmpVal > 255) ? - 255 : tmpVal); - ss++; - } - } - } - - while (i < AR5416_PD_GAINS_IN_MASK) { - pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; - i++; - } - - while (k < AR5416_NUM_PDADC_VALUES) { - pPDADCValues[k] = pPDADCValues[k - 1]; - k++; - } - - return; -} - -static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, - struct ath9k_channel *chan, - struct cal_target_power_leg *powInfo, - u16 numChannels, - struct cal_target_power_leg *pNewPower, - u16 numRates, bool isExtTarget) -{ - struct chan_centers centers; - u16 clo, chi; - int i; - int matchIndex = -1, lowIndex = -1; - u16 freq; - - ath9k_hw_get_channel_centers(ah, chan, ¢ers); - freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; - - if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, - IS_CHAN_2GHZ(chan))) { - matchIndex = 0; - } else { - for (i = 0; (i < numChannels) && - (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { - if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) { - matchIndex = i; - break; - } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) && - (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, - IS_CHAN_2GHZ(chan)))) { - lowIndex = i - 1; - break; - } - } - if ((matchIndex == -1) && (lowIndex == -1)) - matchIndex = i - 1; - } - - if (matchIndex != -1) { - *pNewPower = powInfo[matchIndex]; - } else { - clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, - IS_CHAN_2GHZ(chan)); - chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, - IS_CHAN_2GHZ(chan)); - - for (i = 0; i < numRates; i++) { - pNewPower->tPow2x[i] = - (u8)ath9k_hw_interpolate(freq, clo, chi, - powInfo[lowIndex].tPow2x[i], - powInfo[lowIndex + 1].tPow2x[i]); - } - } -} - -static void ath9k_hw_get_target_powers(struct ath_hw *ah, - struct ath9k_channel *chan, - struct cal_target_power_ht *powInfo, - u16 numChannels, - struct cal_target_power_ht *pNewPower, - u16 numRates, bool isHt40Target) -{ - struct chan_centers centers; - u16 clo, chi; - int i; - int matchIndex = -1, lowIndex = -1; - u16 freq; - - ath9k_hw_get_channel_centers(ah, chan, ¢ers); - freq = isHt40Target ? centers.synth_center : centers.ctl_center; - - if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { - matchIndex = 0; - } else { - for (i = 0; (i < numChannels) && - (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { - if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) { - matchIndex = i; - break; - } else - if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) && - (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, - IS_CHAN_2GHZ(chan)))) { - lowIndex = i - 1; - break; - } - } - if ((matchIndex == -1) && (lowIndex == -1)) - matchIndex = i - 1; - } - - if (matchIndex != -1) { - *pNewPower = powInfo[matchIndex]; - } else { - clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, - IS_CHAN_2GHZ(chan)); - chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, - IS_CHAN_2GHZ(chan)); - - for (i = 0; i < numRates; i++) { - pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq, - clo, chi, - powInfo[lowIndex].tPow2x[i], - powInfo[lowIndex + 1].tPow2x[i]); - } - } -} - -static u16 ath9k_hw_get_max_edge_power(u16 freq, - struct cal_ctl_edges *pRdEdgesPower, - bool is2GHz, int num_band_edges) -{ - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; - int i; - - for (i = 0; (i < num_band_edges) && - (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { - if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { - twiceMaxEdgePower = pRdEdgesPower[i].tPower; - break; - } else if ((i > 0) && - (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, - is2GHz))) { - if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, - is2GHz) < freq && - pRdEdgesPower[i - 1].flag) { - twiceMaxEdgePower = - pRdEdgesPower[i - 1].tPower; - } - break; - } - } - - return twiceMaxEdgePower; -} - -static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *pTxPowerIndexOffset) -{ - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; - struct cal_data_per_freq *pRawDataset; - u8 *pCalBChans = NULL; - u16 pdGainOverlap_t2; - static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; - u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; - u16 numPiers, i, j; - int16_t tMinCalPower; - u16 numXpdGain, xpdMask; - u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; - u32 reg32, regOffset, regChainOffset; - int16_t modalIdx; - - modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; - xpdMask = pEepData->modalHeader[modalIdx].xpdGain; - - if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_2) { - pdGainOverlap_t2 = - pEepData->modalHeader[modalIdx].pdGainOverlap; - } else { - pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), - AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); - } - - if (IS_CHAN_2GHZ(chan)) { - pCalBChans = pEepData->calFreqPier2G; - numPiers = AR5416_NUM_2G_CAL_PIERS; - } else { - pCalBChans = pEepData->calFreqPier5G; - numPiers = AR5416_NUM_5G_CAL_PIERS; - } - - numXpdGain = 0; - - for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { - if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { - if (numXpdGain >= AR5416_NUM_PD_GAINS) - break; - xpdGainValues[numXpdGain] = - (u16)(AR5416_PD_GAINS_IN_MASK - i); - numXpdGain++; - } - } - - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, - (numXpdGain - 1) & 0x3); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, - xpdGainValues[0]); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, - xpdGainValues[1]); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, - xpdGainValues[2]); - - for (i = 0; i < AR5416_MAX_CHAINS; i++) { - if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && - (i != 0)) { - regChainOffset = (i == 1) ? 0x2000 : 0x1000; - } else - regChainOffset = i * 0x1000; - - if (pEepData->baseEepHeader.txMask & (1 << i)) { - if (IS_CHAN_2GHZ(chan)) - pRawDataset = pEepData->calPierData2G[i]; - else - pRawDataset = pEepData->calPierData5G[i]; - - ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan, - pRawDataset, pCalBChans, - numPiers, pdGainOverlap_t2, - &tMinCalPower, gainBoundaries, - pdadcValues, numXpdGain); - - if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { - REG_WRITE(ah, - AR_PHY_TPCRG5 + regChainOffset, - SM(pdGainOverlap_t2, - AR_PHY_TPCRG5_PD_GAIN_OVERLAP) - | SM(gainBoundaries[0], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) - | SM(gainBoundaries[1], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) - | SM(gainBoundaries[2], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) - | SM(gainBoundaries[3], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); - } - - regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; - for (j = 0; j < 32; j++) { - reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | - ((pdadcValues[4 * j + 1] & 0xFF) << 8) | - ((pdadcValues[4 * j + 2] & 0xFF) << 16)| - ((pdadcValues[4 * j + 3] & 0xFF) << 24); - REG_WRITE(ah, regOffset, reg32); - - DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, - "PDADC (%d,%4x): %4.4x %8.8x\n", - i, regChainOffset, regOffset, - reg32); - DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, - "PDADC: Chain %d | PDADC %3d " - "Value %3d | PDADC %3d Value %3d | " - "PDADC %3d Value %3d | PDADC %3d " - "Value %3d |\n", - i, 4 * j, pdadcValues[4 * j], - 4 * j + 1, pdadcValues[4 * j + 1], - 4 * j + 2, pdadcValues[4 * j + 2], - 4 * j + 3, - pdadcValues[4 * j + 3]); - - regOffset += 4; - } - } - } - - *pTxPowerIndexOffset = 0; - - return true; -} - static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) @@ -1161,296 +755,6 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, return true; } -static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *ratesArray, - u16 cfgCtl, - u16 AntennaReduction, - u16 twiceMaxRegulatoryPower, - u16 powerLimit) -{ -#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ -#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ - - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; - static const u16 tpScaleReductionTable[5] = - { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; - - int i; - int16_t twiceLargestAntenna; - struct cal_ctl_data *rep; - struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { - 0, { 0, 0, 0, 0} - }; - struct cal_target_power_leg targetPowerOfdmExt = { - 0, { 0, 0, 0, 0} }, targetPowerCckExt = { - 0, { 0, 0, 0, 0 } - }; - struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { - 0, {0, 0, 0, 0} - }; - u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; - u16 ctlModesFor11a[] = - { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; - u16 ctlModesFor11g[] = - { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, - CTL_2GHT40 - }; - u16 numCtlModes, *pCtlMode, ctlMode, freq; - struct chan_centers centers; - int tx_chainmask; - u16 twiceMinEdgePower; - - tx_chainmask = ah->ah_txchainmask; - - ath9k_hw_get_channel_centers(ah, chan, ¢ers); - - twiceLargestAntenna = max( - pEepData->modalHeader - [IS_CHAN_2GHZ(chan)].antennaGainCh[0], - pEepData->modalHeader - [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); - - twiceLargestAntenna = max((u8)twiceLargestAntenna, - pEepData->modalHeader - [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); - - twiceLargestAntenna = (int16_t)min(AntennaReduction - - twiceLargestAntenna, 0); - - maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; - - if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { - maxRegAllowedPower -= - (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); - } - - scaledPower = min(powerLimit, maxRegAllowedPower); - - switch (ar5416_get_ntxchains(tx_chainmask)) { - case 1: - break; - case 2: - scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; - break; - case 3: - scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; - break; - } - - scaledPower = max((u16)0, scaledPower); - - if (IS_CHAN_2GHZ(chan)) { - numCtlModes = ARRAY_SIZE(ctlModesFor11g) - - SUB_NUM_CTL_MODES_AT_2G_40; - pCtlMode = ctlModesFor11g; - - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPowerCck, - AR5416_NUM_2G_CCK_TARGET_POWERS, - &targetPowerCck, 4, false); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower2G, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerOfdm, 4, false); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower2GHT20, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerHt20, 8, false); - - if (IS_CHAN_HT40(chan)) { - numCtlModes = ARRAY_SIZE(ctlModesFor11g); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower2GHT40, - AR5416_NUM_2G_40_TARGET_POWERS, - &targetPowerHt40, 8, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPowerCck, - AR5416_NUM_2G_CCK_TARGET_POWERS, - &targetPowerCckExt, 4, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower2G, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerOfdmExt, 4, true); - } - } else { - numCtlModes = ARRAY_SIZE(ctlModesFor11a) - - SUB_NUM_CTL_MODES_AT_5G_40; - pCtlMode = ctlModesFor11a; - - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower5G, - AR5416_NUM_5G_20_TARGET_POWERS, - &targetPowerOfdm, 4, false); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower5GHT20, - AR5416_NUM_5G_20_TARGET_POWERS, - &targetPowerHt20, 8, false); - - if (IS_CHAN_HT40(chan)) { - numCtlModes = ARRAY_SIZE(ctlModesFor11a); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower5GHT40, - AR5416_NUM_5G_40_TARGET_POWERS, - &targetPowerHt40, 8, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower5G, - AR5416_NUM_5G_20_TARGET_POWERS, - &targetPowerOfdmExt, 4, true); - } - } - - for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { - bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || - (pCtlMode[ctlMode] == CTL_2GHT40); - if (isHt40CtlMode) - freq = centers.synth_center; - else if (pCtlMode[ctlMode] & EXT_ADDITIVE) - freq = centers.ext_center; - else - freq = centers.ctl_center; - - if (ar5416_get_eep_ver(ah) == 14 && ar5416_get_eep_rev(ah) <= 2) - twiceMaxEdgePower = AR5416_MAX_RATE_POWER; - - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " - "EXT_ADDITIVE %d\n", - ctlMode, numCtlModes, isHt40CtlMode, - (pCtlMode[ctlMode] & EXT_ADDITIVE)); - - for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " - "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " - "chan %d\n", - i, cfgCtl, pCtlMode[ctlMode], - pEepData->ctlIndex[i], chan->channel); - - if ((((cfgCtl & ~CTL_MODE_M) | - (pCtlMode[ctlMode] & CTL_MODE_M)) == - pEepData->ctlIndex[i]) || - (((cfgCtl & ~CTL_MODE_M) | - (pCtlMode[ctlMode] & CTL_MODE_M)) == - ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { - rep = &(pEepData->ctlData[i]); - - twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, - rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], - IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); - - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " MATCH-EE_IDX %d: ch %d is2 %d " - "2xMinEdge %d chainmask %d chains %d\n", - i, freq, IS_CHAN_2GHZ(chan), - twiceMinEdgePower, tx_chainmask, - ar5416_get_ntxchains - (tx_chainmask)); - if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { - twiceMaxEdgePower = min(twiceMaxEdgePower, - twiceMinEdgePower); - } else { - twiceMaxEdgePower = twiceMinEdgePower; - break; - } - } - } - - minCtlPower = min(twiceMaxEdgePower, scaledPower); - - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " SEL-Min ctlMode %d pCtlMode %d " - "2xMaxEdge %d sP %d minCtlPwr %d\n", - ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, - scaledPower, minCtlPower); - - switch (pCtlMode[ctlMode]) { - case CTL_11B: - for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { - targetPowerCck.tPow2x[i] = - min((u16)targetPowerCck.tPow2x[i], - minCtlPower); - } - break; - case CTL_11A: - case CTL_11G: - for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { - targetPowerOfdm.tPow2x[i] = - min((u16)targetPowerOfdm.tPow2x[i], - minCtlPower); - } - break; - case CTL_5GHT20: - case CTL_2GHT20: - for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { - targetPowerHt20.tPow2x[i] = - min((u16)targetPowerHt20.tPow2x[i], - minCtlPower); - } - break; - case CTL_11B_EXT: - targetPowerCckExt.tPow2x[0] = min((u16) - targetPowerCckExt.tPow2x[0], - minCtlPower); - break; - case CTL_11A_EXT: - case CTL_11G_EXT: - targetPowerOfdmExt.tPow2x[0] = min((u16) - targetPowerOfdmExt.tPow2x[0], - minCtlPower); - break; - case CTL_5GHT40: - case CTL_2GHT40: - for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { - targetPowerHt40.tPow2x[i] = - min((u16)targetPowerHt40.tPow2x[i], - minCtlPower); - } - break; - default: - break; - } - } - - ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = - ratesArray[rate18mb] = ratesArray[rate24mb] = - targetPowerOfdm.tPow2x[0]; - ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; - ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; - ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; - ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; - - for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) - ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; - - if (IS_CHAN_2GHZ(chan)) { - ratesArray[rate1l] = targetPowerCck.tPow2x[0]; - ratesArray[rate2s] = ratesArray[rate2l] = - targetPowerCck.tPow2x[1]; - ratesArray[rate5_5s] = ratesArray[rate5_5l] = - targetPowerCck.tPow2x[2]; - ; - ratesArray[rate11s] = ratesArray[rate11l] = - targetPowerCck.tPow2x[3]; - ; - } - if (IS_CHAN_HT40(chan)) { - for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { - ratesArray[rateHt40_0 + i] = - targetPowerHt40.tPow2x[i]; - } - ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; - ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; - ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; - if (IS_CHAN_2GHZ(chan)) { - ratesArray[rateExtCck] = - targetPowerCckExt.tPow2x[0]; - } - } - return true; -} - static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, @@ -1548,8 +852,8 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, else freq = centers.ctl_center; - if (ar5416_get_eep_ver(ah) == 14 && - ar5416_get_eep_rev(ah) <= 2) + if (ah->eep_ops->get_eeprom_ver(ah) == 14 && + ah->eep_ops->get_eeprom_rev(ah) <= 2) twiceMaxEdgePower = AR5416_MAX_RATE_POWER; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, @@ -1686,16 +990,15 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, return true; } -static int ath9k_hw_def_set_txpower(struct ath_hw *ah, - struct ath9k_channel *chan, - u16 cfgCtl, - u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit) +static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, + struct ath9k_channel *chan, + u16 cfgCtl, + u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, + u8 powerLimit) { - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; - struct modal_eep_header *pModal = - &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct modal_eep_4k_header *pModal = &pEepData->modalHeader; int16_t ratesArray[Ar5416RateSize]; int16_t txPowerIndexOffset = 0; u8 ht40PowerIncForPdadc = 2; @@ -1708,7 +1011,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; } - if (!ath9k_hw_set_def_power_per_rate_table(ah, chan, + if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan, &ratesArray[0], cfgCtl, twiceAntennaReduction, twiceMaxRegulatoryPower, @@ -1719,7 +1022,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, return -EIO; } - if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) { + if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ath9k_hw_set_txpower: unable to set power table\n"); return -EIO; @@ -1798,10 +1101,6 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); } - REG_WRITE(ah, AR_PHY_POWER_TX_SUB, - ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) - | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); - i = rate6mb; if (IS_CHAN_HT40(chan)) @@ -1818,241 +1117,497 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, return 0; } -static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, - struct ath9k_channel *chan, - u16 cfgCtl, - u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit) +static void ath9k_hw_4k_set_addac(struct ath_hw *ah, + struct ath9k_channel *chan) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; - struct modal_eep_4k_header *pModal = &pEepData->modalHeader; - int16_t ratesArray[Ar5416RateSize]; - int16_t txPowerIndexOffset = 0; - u8 ht40PowerIncForPdadc = 2; - int i; + struct modal_eep_4k_header *pModal; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + u8 biaslevel; - memset(ratesArray, 0, sizeof(ratesArray)); + if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) + return; - if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_2) { - ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; + if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) + return; + + pModal = &eep->modalHeader; + + if (pModal->xpaBiasLvl != 0xff) { + biaslevel = pModal->xpaBiasLvl; + INI_RA(&ah->ah_iniAddac, 7, 1) = + (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } +} - if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan, - &ratesArray[0], cfgCtl, - twiceAntennaReduction, - twiceMaxRegulatoryPower, - powerLimit)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "ath9k_hw_set_txpower: unable to set " - "tx power per rate table\n"); - return -EIO; +static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, + struct ath9k_channel *chan) +{ + struct modal_eep_4k_header *pModal; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + int regChainOffset; + u8 txRxAttenLocal; + u8 ob[5], db1[5], db2[5]; + u8 ant_div_control1, ant_div_control2; + u32 regVal; + + + pModal = &eep->modalHeader; + + txRxAttenLocal = 23; + + REG_WRITE(ah, AR_PHY_SWITCH_COM, + ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); + + regChainOffset = 0; + REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, + pModal->antCtrlChain[0]); + + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, + (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & + ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | + SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | + SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); + + if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_3) { + txRxAttenLocal = pModal->txRxAttenCh[0]; + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, + pModal->xatten2Margin[0]); + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); } - if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) { + REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); + REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); + + if (AR_SREV_9285_11(ah)) + REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); + + /* Initialize Ant Diversity settings from EEPROM */ + if (pModal->version == 3) { + ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf); + ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf); + regVal = REG_READ(ah, 0x99ac); + regVal &= (~(0x7f000000)); + regVal |= ((ant_div_control1 & 0x1) << 24); + regVal |= (((ant_div_control1 >> 1) & 0x1) << 29); + regVal |= (((ant_div_control1 >> 2) & 0x1) << 30); + regVal |= ((ant_div_control2 & 0x3) << 25); + regVal |= (((ant_div_control2 >> 2) & 0x3) << 27); + REG_WRITE(ah, 0x99ac, regVal); + regVal = REG_READ(ah, 0x99ac); + regVal = REG_READ(ah, 0xa208); + regVal &= (~(0x1 << 13)); + regVal |= (((ant_div_control1 >> 3) & 0x1) << 13); + REG_WRITE(ah, 0xa208, regVal); + regVal = REG_READ(ah, 0xa208); + } + + if (pModal->version >= 2) { + ob[0] = (pModal->ob_01 & 0xf); + ob[1] = (pModal->ob_01 >> 4) & 0xf; + ob[2] = (pModal->ob_234 & 0xf); + ob[3] = ((pModal->ob_234 >> 4) & 0xf); + ob[4] = ((pModal->ob_234 >> 8) & 0xf); + + db1[0] = (pModal->db1_01 & 0xf); + db1[1] = ((pModal->db1_01 >> 4) & 0xf); + db1[2] = (pModal->db1_234 & 0xf); + db1[3] = ((pModal->db1_234 >> 4) & 0xf); + db1[4] = ((pModal->db1_234 >> 8) & 0xf); + + db2[0] = (pModal->db2_01 & 0xf); + db2[1] = ((pModal->db2_01 >> 4) & 0xf); + db2[2] = (pModal->db2_234 & 0xf); + db2[3] = ((pModal->db2_234 >> 4) & 0xf); + db2[4] = ((pModal->db2_234 >> 8) & 0xf); + + } else if (pModal->version == 1) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "ath9k_hw_set_txpower: unable to set power table\n"); - return -EIO; + "EEPROM Model version is set to 1 \n"); + ob[0] = (pModal->ob_01 & 0xf); + ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf; + db1[0] = (pModal->db1_01 & 0xf); + db1[1] = db1[2] = db1[3] = + db1[4] = ((pModal->db1_01 >> 4) & 0xf); + db2[0] = (pModal->db2_01 & 0xf); + db2[1] = db2[2] = db2[3] = + db2[4] = ((pModal->db2_01 >> 4) & 0xf); + } else { + int i; + for (i = 0; i < 5; i++) { + ob[i] = pModal->ob_01; + db1[i] = pModal->db1_01; + db2[i] = pModal->db1_01; + } } - for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { - ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); - if (ratesArray[i] > AR5416_MAX_RATE_POWER) - ratesArray[i] = AR5416_MAX_RATE_POWER; + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]); + + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]); + + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]); + + + if (AR_SREV_9285_11(ah)) + REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); + + REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, + pModal->switchSettling); + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, + pModal->adcDesiredSize); + + REG_WRITE(ah, AR_PHY_RF_CTL4, + SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | + SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | + SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | + SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); + + REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, + pModal->txEndToRxOn); + REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, + pModal->thresh62); + REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, + pModal->thresh62); + + if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_2) { + REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, + pModal->txFrameToDataStart); + REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, + pModal->txFrameToPaOn); } - if (AR_SREV_9280_10_OR_LATER(ah)) { - for (i = 0; i < Ar5416RateSize; i++) - ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; + if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_3) { + if (IS_CHAN_HT40(chan)) + REG_RMW_FIELD(ah, AR_PHY_SETTLING, + AR_PHY_SETTLING_SWITCH, + pModal->swSettleHt40); } - REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, - ATH9K_POW_SM(ratesArray[rate18mb], 24) - | ATH9K_POW_SM(ratesArray[rate12mb], 16) - | ATH9K_POW_SM(ratesArray[rate9mb], 8) - | ATH9K_POW_SM(ratesArray[rate6mb], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, - ATH9K_POW_SM(ratesArray[rate54mb], 24) - | ATH9K_POW_SM(ratesArray[rate48mb], 16) - | ATH9K_POW_SM(ratesArray[rate36mb], 8) - | ATH9K_POW_SM(ratesArray[rate24mb], 0)); + return true; +} - if (IS_CHAN_2GHZ(chan)) { - REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, - ATH9K_POW_SM(ratesArray[rate2s], 24) - | ATH9K_POW_SM(ratesArray[rate2l], 16) - | ATH9K_POW_SM(ratesArray[rateXr], 8) - | ATH9K_POW_SM(ratesArray[rate1l], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, - ATH9K_POW_SM(ratesArray[rate11s], 24) - | ATH9K_POW_SM(ratesArray[rate11l], 16) - | ATH9K_POW_SM(ratesArray[rate5_5s], 8) - | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); - } +static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, + struct ath9k_channel *chan) +{ + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct modal_eep_4k_header *pModal = &eep->modalHeader; - REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, - ATH9K_POW_SM(ratesArray[rateHt20_3], 24) - | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) - | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) - | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, - ATH9K_POW_SM(ratesArray[rateHt20_7], 24) - | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) - | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) - | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); + return pModal->antCtrlCommon & 0xFFFF; +} - if (IS_CHAN_HT40(chan)) { - REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, - ATH9K_POW_SM(ratesArray[rateHt40_3] + - ht40PowerIncForPdadc, 24) - | ATH9K_POW_SM(ratesArray[rateHt40_2] + - ht40PowerIncForPdadc, 16) - | ATH9K_POW_SM(ratesArray[rateHt40_1] + - ht40PowerIncForPdadc, 8) - | ATH9K_POW_SM(ratesArray[rateHt40_0] + - ht40PowerIncForPdadc, 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, - ATH9K_POW_SM(ratesArray[rateHt40_7] + - ht40PowerIncForPdadc, 24) - | ATH9K_POW_SM(ratesArray[rateHt40_6] + - ht40PowerIncForPdadc, 16) - | ATH9K_POW_SM(ratesArray[rateHt40_5] + - ht40PowerIncForPdadc, 8) - | ATH9K_POW_SM(ratesArray[rateHt40_4] + - ht40PowerIncForPdadc, 0)); +static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah, + enum ieee80211_band freq_band) +{ + return 1; +} - REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, - ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) - | ATH9K_POW_SM(ratesArray[rateExtCck], 16) - | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) - | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); - } +u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) +{ +#define EEP_MAP4K_SPURCHAN \ + (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) - i = rate6mb; + u16 spur_val = AR_NO_SPUR; - if (IS_CHAN_HT40(chan)) - i = rateHt40_0; - else if (IS_CHAN_HT20(chan)) - i = rateHt20_0; + DPRINTF(ah->ah_sc, ATH_DBG_ANI, + "Getting spur idx %d is2Ghz. %d val %x\n", + i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); - if (AR_SREV_9280_10_OR_LATER(ah)) - ah->regulatory.max_power_level = - ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; - else - ah->regulatory.max_power_level = ratesArray[i]; + switch (ah->ah_config.spurmode) { + case SPUR_DISABLE: + break; + case SPUR_ENABLE_IOCTL: + spur_val = ah->ah_config.spurchans[i][is2GHz]; + DPRINTF(ah->ah_sc, ATH_DBG_ANI, + "Getting spur val from new loc. %d\n", spur_val); + break; + case SPUR_ENABLE_EEPROM: + spur_val = EEP_MAP4K_SPURCHAN; + break; + } - return 0; + return spur_val; + +#undef EEP_MAP4K_SPURCHAN } -static int (*ath9k_set_txpower[]) (struct ath_hw *, - struct ath9k_channel *, - u16, u8, u8, u8) = { - ath9k_hw_def_set_txpower, - ath9k_hw_4k_set_txpower +struct eeprom_ops eep_4k_ops = { + .check_eeprom = ath9k_hw_4k_check_eeprom, + .get_eeprom = ath9k_hw_4k_get_eeprom, + .fill_eeprom = ath9k_hw_4k_fill_eeprom, + .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, + .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, + .get_num_ant_config = ath9k_hw_4k_get_num_ant_config, + .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg, + .set_board_values = ath9k_hw_4k_set_board_values, + .set_addac = ath9k_hw_4k_set_addac, + .set_txpower = ath9k_hw_4k_set_txpower, + .get_spur_channel = ath9k_hw_4k_get_spur_channel }; -int ath9k_hw_set_txpower(struct ath_hw *ah, - struct ath9k_channel *chan, - u16 cfgCtl, - u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit) +/************************************************/ +/* EEPROM Operations for non-4K (Default) cards */ +/************************************************/ + +static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) { - return ath9k_set_txpower[ah->ah_eep_map](ah, chan, cfgCtl, - twiceAntennaReduction, twiceMaxRegulatoryPower, - powerLimit); + return ((ah->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF); } -static void ath9k_hw_set_def_addac(struct ath_hw *ah, - struct ath9k_channel *chan) +static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) { -#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) - struct modal_eep_header *pModal; + return ((ah->ah_eeprom.def.baseEepHeader.version) & 0xFFF); +} + +static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) +{ +#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - u8 biaslevel; + u16 *eep_data; + int addr, ar5416_eep_start_loc = 0x100; - if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) - return; + eep_data = (u16 *)eep; - if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) - return; + for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { + if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, + eep_data)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Unable to read eeprom region\n"); + return false; + } + eep_data++; + } + return true; +#undef SIZE_EEPROM_DEF +} - pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); +static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) +{ + struct ar5416_eeprom_def *eep = + (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; + u16 *eepdata, temp, magic, magic2; + u32 sum = 0, el; + bool need_swap = false; + int i, addr, size; - if (pModal->xpaBiasLvl != 0xff) { - biaslevel = pModal->xpaBiasLvl; - } else { - u16 resetFreqBin, freqBin, freqCount = 0; - struct chan_centers centers; + if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, + &magic)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Reading Magic # failed\n"); + return false; + } - ath9k_hw_get_channel_centers(ah, chan, ¢ers); + if (!ath9k_hw_use_flash(ah)) { - resetFreqBin = FREQ2FBIN(centers.synth_center, - IS_CHAN_2GHZ(chan)); - freqBin = XPA_LVL_FREQ(0) & 0xff; - biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14); + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Read Magic = 0x%04X\n", magic); - freqCount++; + if (magic != AR5416_EEPROM_MAGIC) { + magic2 = swab16(magic); - while (freqCount < 3) { - if (XPA_LVL_FREQ(freqCount) == 0x0) - break; + if (magic2 == AR5416_EEPROM_MAGIC) { + size = sizeof(struct ar5416_eeprom_def); + need_swap = true; + eepdata = (u16 *) (&ah->ah_eeprom); - freqBin = XPA_LVL_FREQ(freqCount) & 0xff; - if (resetFreqBin >= freqBin) - biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14); - else - break; - freqCount++; + for (addr = 0; addr < size / sizeof(u16); addr++) { + temp = swab16(*eepdata); + *eepdata = temp; + eepdata++; + + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "0x%04X ", *eepdata); + + if (((addr + 1) % 6) == 0) + DPRINTF(ah->ah_sc, + ATH_DBG_EEPROM, "\n"); + } + } else { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Invalid EEPROM Magic. " + "endianness mismatch.\n"); + return -EINVAL; + } } } - if (IS_CHAN_2GHZ(chan)) { - INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, - 7, 1) & (~0x18)) | biaslevel << 3; - } else { - INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, - 6, 1) & (~0xc0)) | biaslevel << 6; - } -#undef XPA_LVL_FREQ -} + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", + need_swap ? "True" : "False"); -static void ath9k_hw_set_4k_addac(struct ath_hw *ah, - struct ath9k_channel *chan) -{ - struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - u8 biaslevel; + if (need_swap) + el = swab16(ah->ah_eeprom.def.baseEepHeader.length); + else + el = ah->ah_eeprom.def.baseEepHeader.length; - if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) - return; + if (el > sizeof(struct ar5416_eeprom_def)) + el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); + else + el = el / sizeof(u16); - if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) - return; + eepdata = (u16 *)(&ah->ah_eeprom); - pModal = &eep->modalHeader; + for (i = 0; i < el; i++) + sum ^= *eepdata++; - if (pModal->xpaBiasLvl != 0xff) { - biaslevel = pModal->xpaBiasLvl; - INI_RA(&ah->ah_iniAddac, 7, 1) = - (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; + if (need_swap) { + u32 integer, j; + u16 word; + + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "EEPROM Endianness is not native.. Changing \n"); + + word = swab16(eep->baseEepHeader.length); + eep->baseEepHeader.length = word; + + word = swab16(eep->baseEepHeader.checksum); + eep->baseEepHeader.checksum = word; + + word = swab16(eep->baseEepHeader.version); + eep->baseEepHeader.version = word; + + word = swab16(eep->baseEepHeader.regDmn[0]); + eep->baseEepHeader.regDmn[0] = word; + + word = swab16(eep->baseEepHeader.regDmn[1]); + eep->baseEepHeader.regDmn[1] = word; + + word = swab16(eep->baseEepHeader.rfSilent); + eep->baseEepHeader.rfSilent = word; + + word = swab16(eep->baseEepHeader.blueToothOptions); + eep->baseEepHeader.blueToothOptions = word; + + word = swab16(eep->baseEepHeader.deviceCap); + eep->baseEepHeader.deviceCap = word; + + for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { + struct modal_eep_header *pModal = + &eep->modalHeader[j]; + integer = swab32(pModal->antCtrlCommon); + pModal->antCtrlCommon = integer; + + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + integer = swab32(pModal->antCtrlChain[i]); + pModal->antCtrlChain[i] = integer; + } + + for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { + word = swab16(pModal->spurChans[i].spurChan); + pModal->spurChans[i].spurChan = word; + } + } } -} -static void (*ath9k_set_addac[]) (struct ath_hw *, struct ath9k_channel *) = { - ath9k_hw_set_def_addac, - ath9k_hw_set_4k_addac -}; + if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || + ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Bad EEPROM checksum 0x%x or revision 0x%04x\n", + sum, ah->eep_ops->get_eeprom_ver(ah)); + return -EINVAL; + } -void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) + return 0; +} + +static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, + enum eeprom_param param) { - ath9k_set_addac[ah->ah_eep_map](ah, chan); +#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct modal_eep_header *pModal = eep->modalHeader; + struct base_eep_header *pBase = &eep->baseEepHeader; + + switch (param) { + case EEP_NFTHRESH_5: + return pModal[0].noiseFloorThreshCh[0]; + case EEP_NFTHRESH_2: + return pModal[1].noiseFloorThreshCh[0]; + case AR_EEPROM_MAC(0): + return pBase->macAddr[0] << 8 | pBase->macAddr[1]; + case AR_EEPROM_MAC(1): + return pBase->macAddr[2] << 8 | pBase->macAddr[3]; + case AR_EEPROM_MAC(2): + return pBase->macAddr[4] << 8 | pBase->macAddr[5]; + case EEP_REG_0: + return pBase->regDmn[0]; + case EEP_REG_1: + return pBase->regDmn[1]; + case EEP_OP_CAP: + return pBase->deviceCap; + case EEP_OP_MODE: + return pBase->opCapFlags; + case EEP_RF_SILENT: + return pBase->rfSilent; + case EEP_OB_5: + return pModal[0].ob; + case EEP_DB_5: + return pModal[0].db; + case EEP_OB_2: + return pModal[1].ob; + case EEP_DB_2: + return pModal[1].db; + case EEP_MINOR_REV: + return AR5416_VER_MASK; + case EEP_TX_MASK: + return pBase->txMask; + case EEP_RX_MASK: + return pBase->rxMask; + case EEP_RXGAIN_TYPE: + return pBase->rxGainType; + case EEP_TXGAIN_TYPE: + return pBase->txGainType; + case EEP_DAC_HPWR_5G: + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) + return pBase->dacHiPwrMode_5G; + else + return 0; + default: + return 0; + } +#undef AR5416_VER_MASK } /* XXX: Clean me up, make me more legible */ -static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah, - struct ath9k_channel *chan) +static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, + struct ath9k_channel *chan) { #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) struct modal_eep_header *pModal; @@ -2065,7 +1620,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah, txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; REG_WRITE(ah, AR_PHY_SWITCH_COM, - ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); + ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_9280(ah)) { @@ -2295,242 +1850,775 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah, #undef AR5416_VER_MASK } -static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hw *ah, - struct ath9k_channel *chan) +static void ath9k_hw_def_set_addac(struct ath_hw *ah, + struct ath9k_channel *chan) { - struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - int regChainOffset; - u8 txRxAttenLocal; - u8 ob[5], db1[5], db2[5]; - u8 ant_div_control1, ant_div_control2; - u32 regVal; +#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) + struct modal_eep_header *pModal; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + u8 biaslevel; + if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) + return; - pModal = &eep->modalHeader; + if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) + return; - txRxAttenLocal = 23; + pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); - REG_WRITE(ah, AR_PHY_SWITCH_COM, - ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); + if (pModal->xpaBiasLvl != 0xff) { + biaslevel = pModal->xpaBiasLvl; + } else { + u16 resetFreqBin, freqBin, freqCount = 0; + struct chan_centers centers; - regChainOffset = 0; - REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, - pModal->antCtrlChain[0]); + ath9k_hw_get_channel_centers(ah, chan, ¢ers); - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, - (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & - ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | - SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | - SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); + resetFreqBin = FREQ2FBIN(centers.synth_center, + IS_CHAN_2GHZ(chan)); + freqBin = XPA_LVL_FREQ(0) & 0xff; + biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14); - if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_3) { - txRxAttenLocal = pModal->txRxAttenCh[0]; - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, - pModal->xatten2Margin[0]); - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); - } + freqCount++; - REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, - AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); - REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, - AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); + while (freqCount < 3) { + if (XPA_LVL_FREQ(freqCount) == 0x0) + break; - if (AR_SREV_9285_11(ah)) - REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); + freqBin = XPA_LVL_FREQ(freqCount) & 0xff; + if (resetFreqBin >= freqBin) + biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14); + else + break; + freqCount++; + } + } - /* Initialize Ant Diversity settings from EEPROM */ - if (pModal->version == 3) { - ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf); - ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf); - regVal = REG_READ(ah, 0x99ac); - regVal &= (~(0x7f000000)); - regVal |= ((ant_div_control1 & 0x1) << 24); - regVal |= (((ant_div_control1 >> 1) & 0x1) << 29); - regVal |= (((ant_div_control1 >> 2) & 0x1) << 30); - regVal |= ((ant_div_control2 & 0x3) << 25); - regVal |= (((ant_div_control2 >> 2) & 0x3) << 27); - REG_WRITE(ah, 0x99ac, regVal); - regVal = REG_READ(ah, 0x99ac); - regVal = REG_READ(ah, 0xa208); - regVal &= (~(0x1 << 13)); - regVal |= (((ant_div_control1 >> 3) & 0x1) << 13); - REG_WRITE(ah, 0xa208, regVal); - regVal = REG_READ(ah, 0xa208); + if (IS_CHAN_2GHZ(chan)) { + INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, + 7, 1) & (~0x18)) | biaslevel << 3; + } else { + INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, + 6, 1) & (~0xc0)) | biaslevel << 6; } +#undef XPA_LVL_FREQ +} - if (pModal->version >= 2) { - ob[0] = (pModal->ob_01 & 0xf); - ob[1] = (pModal->ob_01 >> 4) & 0xf; - ob[2] = (pModal->ob_234 & 0xf); - ob[3] = ((pModal->ob_234 >> 4) & 0xf); - ob[4] = ((pModal->ob_234 >> 8) & 0xf); +static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, + struct ath9k_channel *chan, + struct cal_data_per_freq *pRawDataSet, + u8 *bChans, u16 availPiers, + u16 tPdGainOverlap, int16_t *pMinCalPower, + u16 *pPdGainBoundaries, u8 *pPDADCValues, + u16 numXpdGains) +{ + int i, j, k; + int16_t ss; + u16 idxL = 0, idxR = 0, numPiers; + static u8 vpdTableL[AR5416_NUM_PD_GAINS] + [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; + static u8 vpdTableR[AR5416_NUM_PD_GAINS] + [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; + static u8 vpdTableI[AR5416_NUM_PD_GAINS] + [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - db1[0] = (pModal->db1_01 & 0xf); - db1[1] = ((pModal->db1_01 >> 4) & 0xf); - db1[2] = (pModal->db1_234 & 0xf); - db1[3] = ((pModal->db1_234 >> 4) & 0xf); - db1[4] = ((pModal->db1_234 >> 8) & 0xf); + u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; + u8 minPwrT4[AR5416_NUM_PD_GAINS]; + u8 maxPwrT4[AR5416_NUM_PD_GAINS]; + int16_t vpdStep; + int16_t tmpVal; + u16 sizeCurrVpdTable, maxIndex, tgtIndex; + bool match; + int16_t minDelta = 0; + struct chan_centers centers; - db2[0] = (pModal->db2_01 & 0xf); - db2[1] = ((pModal->db2_01 >> 4) & 0xf); - db2[2] = (pModal->db2_234 & 0xf); - db2[3] = ((pModal->db2_234 >> 4) & 0xf); - db2[4] = ((pModal->db2_234 >> 8) & 0xf); + ath9k_hw_get_channel_centers(ah, chan, ¢ers); - } else if (pModal->version == 1) { + for (numPiers = 0; numPiers < availPiers; numPiers++) { + if (bChans[numPiers] == AR5416_BCHAN_UNUSED) + break; + } - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "EEPROM Model version is set to 1 \n"); - ob[0] = (pModal->ob_01 & 0xf); - ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf; - db1[0] = (pModal->db1_01 & 0xf); - db1[1] = db1[2] = db1[3] = - db1[4] = ((pModal->db1_01 >> 4) & 0xf); - db2[0] = (pModal->db2_01 & 0xf); - db2[1] = db2[2] = db2[3] = - db2[4] = ((pModal->db2_01 >> 4) & 0xf); + match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center, + IS_CHAN_2GHZ(chan)), + bChans, numPiers, &idxL, &idxR); + + if (match) { + for (i = 0; i < numXpdGains; i++) { + minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; + maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], + pRawDataSet[idxL].pwrPdg[i], + pRawDataSet[idxL].vpdPdg[i], + AR5416_PD_GAIN_ICEPTS, + vpdTableI[i]); + } } else { - int i; - for (i = 0; i < 5; i++) { - ob[i] = pModal->ob_01; - db1[i] = pModal->db1_01; - db2[i] = pModal->db1_01; + for (i = 0; i < numXpdGains; i++) { + pVpdL = pRawDataSet[idxL].vpdPdg[i]; + pPwrL = pRawDataSet[idxL].pwrPdg[i]; + pVpdR = pRawDataSet[idxR].vpdPdg[i]; + pPwrR = pRawDataSet[idxR].pwrPdg[i]; + + minPwrT4[i] = max(pPwrL[0], pPwrR[0]); + + maxPwrT4[i] = + min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], + pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); + + + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], + pPwrL, pVpdL, + AR5416_PD_GAIN_ICEPTS, + vpdTableL[i]); + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], + pPwrR, pVpdR, + AR5416_PD_GAIN_ICEPTS, + vpdTableR[i]); + + for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { + vpdTableI[i][j] = + (u8)(ath9k_hw_interpolate((u16) + FREQ2FBIN(centers. + synth_center, + IS_CHAN_2GHZ + (chan)), + bChans[idxL], bChans[idxR], + vpdTableL[i][j], vpdTableR[i][j])); + } } } - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]); + *pMinCalPower = (int16_t)(minPwrT4[0] / 2); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]); + k = 0; - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]); + for (i = 0; i < numXpdGains; i++) { + if (i == (numXpdGains - 1)) + pPdGainBoundaries[i] = + (u16)(maxPwrT4[i] / 2); + else + pPdGainBoundaries[i] = + (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); + pPdGainBoundaries[i] = + min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); - if (AR_SREV_9285_11(ah)) - REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); + if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { + minDelta = pPdGainBoundaries[0] - 23; + pPdGainBoundaries[0] = 23; + } else { + minDelta = 0; + } - REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, - pModal->switchSettling); - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, - pModal->adcDesiredSize); + if (i == 0) { + if (AR_SREV_9280_10_OR_LATER(ah)) + ss = (int16_t)(0 - (minPwrT4[i] / 2)); + else + ss = 0; + } else { + ss = (int16_t)((pPdGainBoundaries[i - 1] - + (minPwrT4[i] / 2)) - + tPdGainOverlap + 1 + minDelta); + } + vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); + vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); - REG_WRITE(ah, AR_PHY_RF_CTL4, - SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | - SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | - SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | - SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); + while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { + tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); + pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); + ss++; + } - REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, - pModal->txEndToRxOn); - REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, - pModal->thresh62); - REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, - pModal->thresh62); + sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); + tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - + (minPwrT4[i] / 2)); + maxIndex = (tgtIndex < sizeCurrVpdTable) ? + tgtIndex : sizeCurrVpdTable; - if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_2) { - REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, - pModal->txFrameToDataStart); - REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, - pModal->txFrameToPaOn); - } + while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { + pPDADCValues[k++] = vpdTableI[i][ss++]; + } - if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_3) { - if (IS_CHAN_HT40(chan)) - REG_RMW_FIELD(ah, AR_PHY_SETTLING, - AR_PHY_SETTLING_SWITCH, - pModal->swSettleHt40); + vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - + vpdTableI[i][sizeCurrVpdTable - 2]); + vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); + + if (tgtIndex > maxIndex) { + while ((ss <= tgtIndex) && + (k < (AR5416_NUM_PDADC_VALUES - 1))) { + tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + + (ss - maxIndex + 1) * vpdStep)); + pPDADCValues[k++] = (u8)((tmpVal > 255) ? + 255 : tmpVal); + ss++; + } + } } - return true; -} + while (i < AR5416_PD_GAINS_IN_MASK) { + pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; + i++; + } -static bool (*ath9k_eeprom_set_board_values[])(struct ath_hw *, - struct ath9k_channel *) = { - ath9k_hw_eeprom_set_def_board_values, - ath9k_hw_eeprom_set_4k_board_values -}; + while (k < AR5416_NUM_PDADC_VALUES) { + pPDADCValues[k] = pPDADCValues[k - 1]; + k++; + } -bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, - struct ath9k_channel *chan) -{ - return ath9k_eeprom_set_board_values[ah->ah_eep_map](ah, chan); + return; } -static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan) +static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, + struct ath9k_channel *chan, + int16_t *pTxPowerIndexOffset) { - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - struct modal_eep_header *pModal = - &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct cal_data_per_freq *pRawDataset; + u8 *pCalBChans = NULL; + u16 pdGainOverlap_t2; + static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; + u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; + u16 numPiers, i, j; + int16_t tMinCalPower; + u16 numXpdGain, xpdMask; + u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; + u32 reg32, regOffset, regChainOffset; + int16_t modalIdx; - return pModal->antCtrlCommon & 0xFFFF; + modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; + xpdMask = pEepData->modalHeader[modalIdx].xpdGain; + + if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_2) { + pdGainOverlap_t2 = + pEepData->modalHeader[modalIdx].pdGainOverlap; + } else { + pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), + AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); + } + + if (IS_CHAN_2GHZ(chan)) { + pCalBChans = pEepData->calFreqPier2G; + numPiers = AR5416_NUM_2G_CAL_PIERS; + } else { + pCalBChans = pEepData->calFreqPier5G; + numPiers = AR5416_NUM_5G_CAL_PIERS; + } + + numXpdGain = 0; + + for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { + if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { + if (numXpdGain >= AR5416_NUM_PD_GAINS) + break; + xpdGainValues[numXpdGain] = + (u16)(AR5416_PD_GAINS_IN_MASK - i); + numXpdGain++; + } + } + + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, + (numXpdGain - 1) & 0x3); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, + xpdGainValues[0]); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, + xpdGainValues[1]); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, + xpdGainValues[2]); + + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + if (AR_SREV_5416_V20_OR_LATER(ah) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && + (i != 0)) { + regChainOffset = (i == 1) ? 0x2000 : 0x1000; + } else + regChainOffset = i * 0x1000; + + if (pEepData->baseEepHeader.txMask & (1 << i)) { + if (IS_CHAN_2GHZ(chan)) + pRawDataset = pEepData->calPierData2G[i]; + else + pRawDataset = pEepData->calPierData5G[i]; + + ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan, + pRawDataset, pCalBChans, + numPiers, pdGainOverlap_t2, + &tMinCalPower, gainBoundaries, + pdadcValues, numXpdGain); + + if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { + REG_WRITE(ah, + AR_PHY_TPCRG5 + regChainOffset, + SM(pdGainOverlap_t2, + AR_PHY_TPCRG5_PD_GAIN_OVERLAP) + | SM(gainBoundaries[0], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) + | SM(gainBoundaries[1], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) + | SM(gainBoundaries[2], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) + | SM(gainBoundaries[3], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); + } + + regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; + for (j = 0; j < 32; j++) { + reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | + ((pdadcValues[4 * j + 1] & 0xFF) << 8) | + ((pdadcValues[4 * j + 2] & 0xFF) << 16)| + ((pdadcValues[4 * j + 3] & 0xFF) << 24); + REG_WRITE(ah, regOffset, reg32); + + DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, + "PDADC (%d,%4x): %4.4x %8.8x\n", + i, regChainOffset, regOffset, + reg32); + DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, + "PDADC: Chain %d | PDADC %3d " + "Value %3d | PDADC %3d Value %3d | " + "PDADC %3d Value %3d | PDADC %3d " + "Value %3d |\n", + i, 4 * j, pdadcValues[4 * j], + 4 * j + 1, pdadcValues[4 * j + 1], + 4 * j + 2, pdadcValues[4 * j + 2], + 4 * j + 3, + pdadcValues[4 * j + 3]); + + regOffset += 4; + } + } + } + + *pTxPowerIndexOffset = 0; + + return true; } -static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan) +static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, + struct ath9k_channel *chan, + int16_t *ratesArray, + u16 cfgCtl, + u16 AntennaReduction, + u16 twiceMaxRegulatoryPower, + u16 powerLimit) { - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - struct modal_eep_4k_header *pModal = &eep->modalHeader; +#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ +#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ - return pModal->antCtrlCommon & 0xFFFF; -} + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + static const u16 tpScaleReductionTable[5] = + { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; -static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hw *, - struct ath9k_channel *) = { - ath9k_hw_get_def_eeprom_antenna_cfg, - ath9k_hw_get_4k_eeprom_antenna_cfg -}; + int i; + int16_t twiceLargestAntenna; + struct cal_ctl_data *rep; + struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { + 0, { 0, 0, 0, 0} + }; + struct cal_target_power_leg targetPowerOfdmExt = { + 0, { 0, 0, 0, 0} }, targetPowerCckExt = { + 0, { 0, 0, 0, 0 } + }; + struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { + 0, {0, 0, 0, 0} + }; + u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; + u16 ctlModesFor11a[] = + { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; + u16 ctlModesFor11g[] = + { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, + CTL_2GHT40 + }; + u16 numCtlModes, *pCtlMode, ctlMode, freq; + struct chan_centers centers; + int tx_chainmask; + u16 twiceMinEdgePower; -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan) -{ - return ath9k_get_eeprom_antenna_cfg[ah->ah_eep_map](ah, chan); + tx_chainmask = ah->ah_txchainmask; + + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + + twiceLargestAntenna = max( + pEepData->modalHeader + [IS_CHAN_2GHZ(chan)].antennaGainCh[0], + pEepData->modalHeader + [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); + + twiceLargestAntenna = max((u8)twiceLargestAntenna, + pEepData->modalHeader + [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); + + twiceLargestAntenna = (int16_t)min(AntennaReduction - + twiceLargestAntenna, 0); + + maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; + + if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { + maxRegAllowedPower -= + (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); + } + + scaledPower = min(powerLimit, maxRegAllowedPower); + + switch (ar5416_get_ntxchains(tx_chainmask)) { + case 1: + break; + case 2: + scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; + break; + case 3: + scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; + break; + } + + scaledPower = max((u16)0, scaledPower); + + if (IS_CHAN_2GHZ(chan)) { + numCtlModes = ARRAY_SIZE(ctlModesFor11g) - + SUB_NUM_CTL_MODES_AT_2G_40; + pCtlMode = ctlModesFor11g; + + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPowerCck, + AR5416_NUM_2G_CCK_TARGET_POWERS, + &targetPowerCck, 4, false); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower2G, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerOfdm, 4, false); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower2GHT20, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerHt20, 8, false); + + if (IS_CHAN_HT40(chan)) { + numCtlModes = ARRAY_SIZE(ctlModesFor11g); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower2GHT40, + AR5416_NUM_2G_40_TARGET_POWERS, + &targetPowerHt40, 8, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPowerCck, + AR5416_NUM_2G_CCK_TARGET_POWERS, + &targetPowerCckExt, 4, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower2G, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerOfdmExt, 4, true); + } + } else { + numCtlModes = ARRAY_SIZE(ctlModesFor11a) - + SUB_NUM_CTL_MODES_AT_5G_40; + pCtlMode = ctlModesFor11a; + + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower5G, + AR5416_NUM_5G_20_TARGET_POWERS, + &targetPowerOfdm, 4, false); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower5GHT20, + AR5416_NUM_5G_20_TARGET_POWERS, + &targetPowerHt20, 8, false); + + if (IS_CHAN_HT40(chan)) { + numCtlModes = ARRAY_SIZE(ctlModesFor11a); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower5GHT40, + AR5416_NUM_5G_40_TARGET_POWERS, + &targetPowerHt40, 8, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower5G, + AR5416_NUM_5G_20_TARGET_POWERS, + &targetPowerOfdmExt, 4, true); + } + } + + for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { + bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || + (pCtlMode[ctlMode] == CTL_2GHT40); + if (isHt40CtlMode) + freq = centers.synth_center; + else if (pCtlMode[ctlMode] & EXT_ADDITIVE) + freq = centers.ext_center; + else + freq = centers.ctl_center; + + if (ah->eep_ops->get_eeprom_ver(ah) == 14 && + ah->eep_ops->get_eeprom_rev(ah) <= 2) + twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " + "EXT_ADDITIVE %d\n", + ctlMode, numCtlModes, isHt40CtlMode, + (pCtlMode[ctlMode] & EXT_ADDITIVE)); + + for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " + "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " + "chan %d\n", + i, cfgCtl, pCtlMode[ctlMode], + pEepData->ctlIndex[i], chan->channel); + + if ((((cfgCtl & ~CTL_MODE_M) | + (pCtlMode[ctlMode] & CTL_MODE_M)) == + pEepData->ctlIndex[i]) || + (((cfgCtl & ~CTL_MODE_M) | + (pCtlMode[ctlMode] & CTL_MODE_M)) == + ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { + rep = &(pEepData->ctlData[i]); + + twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, + rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], + IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); + + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " MATCH-EE_IDX %d: ch %d is2 %d " + "2xMinEdge %d chainmask %d chains %d\n", + i, freq, IS_CHAN_2GHZ(chan), + twiceMinEdgePower, tx_chainmask, + ar5416_get_ntxchains + (tx_chainmask)); + if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { + twiceMaxEdgePower = min(twiceMaxEdgePower, + twiceMinEdgePower); + } else { + twiceMaxEdgePower = twiceMinEdgePower; + break; + } + } + } + + minCtlPower = min(twiceMaxEdgePower, scaledPower); + + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " SEL-Min ctlMode %d pCtlMode %d " + "2xMaxEdge %d sP %d minCtlPwr %d\n", + ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, + scaledPower, minCtlPower); + + switch (pCtlMode[ctlMode]) { + case CTL_11B: + for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { + targetPowerCck.tPow2x[i] = + min((u16)targetPowerCck.tPow2x[i], + minCtlPower); + } + break; + case CTL_11A: + case CTL_11G: + for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { + targetPowerOfdm.tPow2x[i] = + min((u16)targetPowerOfdm.tPow2x[i], + minCtlPower); + } + break; + case CTL_5GHT20: + case CTL_2GHT20: + for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { + targetPowerHt20.tPow2x[i] = + min((u16)targetPowerHt20.tPow2x[i], + minCtlPower); + } + break; + case CTL_11B_EXT: + targetPowerCckExt.tPow2x[0] = min((u16) + targetPowerCckExt.tPow2x[0], + minCtlPower); + break; + case CTL_11A_EXT: + case CTL_11G_EXT: + targetPowerOfdmExt.tPow2x[0] = min((u16) + targetPowerOfdmExt.tPow2x[0], + minCtlPower); + break; + case CTL_5GHT40: + case CTL_2GHT40: + for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { + targetPowerHt40.tPow2x[i] = + min((u16)targetPowerHt40.tPow2x[i], + minCtlPower); + } + break; + default: + break; + } + } + + ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = + ratesArray[rate18mb] = ratesArray[rate24mb] = + targetPowerOfdm.tPow2x[0]; + ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; + ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; + ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; + ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; + + for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) + ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; + + if (IS_CHAN_2GHZ(chan)) { + ratesArray[rate1l] = targetPowerCck.tPow2x[0]; + ratesArray[rate2s] = ratesArray[rate2l] = + targetPowerCck.tPow2x[1]; + ratesArray[rate5_5s] = ratesArray[rate5_5l] = + targetPowerCck.tPow2x[2]; + ; + ratesArray[rate11s] = ratesArray[rate11l] = + targetPowerCck.tPow2x[3]; + ; + } + if (IS_CHAN_HT40(chan)) { + for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { + ratesArray[rateHt40_0 + i] = + targetPowerHt40.tPow2x[i]; + } + ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; + ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; + ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; + if (IS_CHAN_2GHZ(chan)) { + ratesArray[rateExtCck] = + targetPowerCckExt.tPow2x[0]; + } + } + return true; } -static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hw *ah, - enum ieee80211_band freq_band) +static int ath9k_hw_def_set_txpower(struct ath_hw *ah, + struct ath9k_channel *chan, + u16 cfgCtl, + u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, + u8 powerLimit) { - return 1; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct modal_eep_header *pModal = + &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); + int16_t ratesArray[Ar5416RateSize]; + int16_t txPowerIndexOffset = 0; + u8 ht40PowerIncForPdadc = 2; + int i; + + memset(ratesArray, 0, sizeof(ratesArray)); + + if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_2) { + ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; + } + + if (!ath9k_hw_set_def_power_per_rate_table(ah, chan, + &ratesArray[0], cfgCtl, + twiceAntennaReduction, + twiceMaxRegulatoryPower, + powerLimit)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "ath9k_hw_set_txpower: unable to set " + "tx power per rate table\n"); + return -EIO; + } + + if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "ath9k_hw_set_txpower: unable to set power table\n"); + return -EIO; + } + + for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { + ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); + if (ratesArray[i] > AR5416_MAX_RATE_POWER) + ratesArray[i] = AR5416_MAX_RATE_POWER; + } + + if (AR_SREV_9280_10_OR_LATER(ah)) { + for (i = 0; i < Ar5416RateSize; i++) + ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; + } + + REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, + ATH9K_POW_SM(ratesArray[rate18mb], 24) + | ATH9K_POW_SM(ratesArray[rate12mb], 16) + | ATH9K_POW_SM(ratesArray[rate9mb], 8) + | ATH9K_POW_SM(ratesArray[rate6mb], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, + ATH9K_POW_SM(ratesArray[rate54mb], 24) + | ATH9K_POW_SM(ratesArray[rate48mb], 16) + | ATH9K_POW_SM(ratesArray[rate36mb], 8) + | ATH9K_POW_SM(ratesArray[rate24mb], 0)); + + if (IS_CHAN_2GHZ(chan)) { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, + ATH9K_POW_SM(ratesArray[rate2s], 24) + | ATH9K_POW_SM(ratesArray[rate2l], 16) + | ATH9K_POW_SM(ratesArray[rateXr], 8) + | ATH9K_POW_SM(ratesArray[rate1l], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, + ATH9K_POW_SM(ratesArray[rate11s], 24) + | ATH9K_POW_SM(ratesArray[rate11l], 16) + | ATH9K_POW_SM(ratesArray[rate5_5s], 8) + | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); + } + + REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, + ATH9K_POW_SM(ratesArray[rateHt20_3], 24) + | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) + | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) + | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, + ATH9K_POW_SM(ratesArray[rateHt20_7], 24) + | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) + | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) + | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); + + if (IS_CHAN_HT40(chan)) { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, + ATH9K_POW_SM(ratesArray[rateHt40_3] + + ht40PowerIncForPdadc, 24) + | ATH9K_POW_SM(ratesArray[rateHt40_2] + + ht40PowerIncForPdadc, 16) + | ATH9K_POW_SM(ratesArray[rateHt40_1] + + ht40PowerIncForPdadc, 8) + | ATH9K_POW_SM(ratesArray[rateHt40_0] + + ht40PowerIncForPdadc, 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, + ATH9K_POW_SM(ratesArray[rateHt40_7] + + ht40PowerIncForPdadc, 24) + | ATH9K_POW_SM(ratesArray[rateHt40_6] + + ht40PowerIncForPdadc, 16) + | ATH9K_POW_SM(ratesArray[rateHt40_5] + + ht40PowerIncForPdadc, 8) + | ATH9K_POW_SM(ratesArray[rateHt40_4] + + ht40PowerIncForPdadc, 0)); + + REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, + ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) + | ATH9K_POW_SM(ratesArray[rateExtCck], 16) + | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) + | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); + } + + REG_WRITE(ah, AR_PHY_POWER_TX_SUB, + ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) + | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); + + i = rate6mb; + + if (IS_CHAN_HT40(chan)) + i = rateHt40_0; + else if (IS_CHAN_HT20(chan)) + i = rateHt20_0; + + if (AR_SREV_9280_10_OR_LATER(ah)) + ah->regulatory.max_power_level = + ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; + else + ah->regulatory.max_power_level = ratesArray[i]; + + return 0; } -static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah, +static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; @@ -2548,24 +2636,21 @@ static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah, return num_ant_config; } -static u8 (*ath9k_get_num_ant_config[])(struct ath_hw *, - enum ieee80211_band) = { - ath9k_hw_get_def_num_ant_config, - ath9k_hw_get_4k_num_ant_config -}; - -u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, - enum ieee80211_band freq_band) +static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, + struct ath9k_channel *chan) { - return ath9k_get_num_ant_config[ah->ah_eep_map](ah, freq_band); + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct modal_eep_header *pModal = + &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); + + return pModal->antCtrlCommon & 0xFFFF; } -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz) +u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) { -#define EEP_MAP4K_SPURCHAN \ - (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) #define EEP_DEF_SPURCHAN \ (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) + u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -2581,142 +2666,45 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz) "Getting spur val from new loc. %d\n", spur_val); break; case SPUR_ENABLE_EEPROM: - if (ah->ah_eep_map == EEP_MAP_4KBITS) - spur_val = EEP_MAP4K_SPURCHAN; - else - spur_val = EEP_DEF_SPURCHAN; + spur_val = EEP_DEF_SPURCHAN; break; - } return spur_val; -#undef EEP_DEF_SPURCHAN -#undef EEP_MAP4K_SPURCHAN -} - -static u32 ath9k_hw_get_eeprom_4k(struct ath_hw *ah, - enum eeprom_param param) -{ - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - struct modal_eep_4k_header *pModal = &eep->modalHeader; - struct base_eep_header_4k *pBase = &eep->baseEepHeader; - - switch (param) { - case EEP_NFTHRESH_2: - return pModal[1].noiseFloorThreshCh[0]; - case AR_EEPROM_MAC(0): - return pBase->macAddr[0] << 8 | pBase->macAddr[1]; - case AR_EEPROM_MAC(1): - return pBase->macAddr[2] << 8 | pBase->macAddr[3]; - case AR_EEPROM_MAC(2): - return pBase->macAddr[4] << 8 | pBase->macAddr[5]; - case EEP_REG_0: - return pBase->regDmn[0]; - case EEP_REG_1: - return pBase->regDmn[1]; - case EEP_OP_CAP: - return pBase->deviceCap; - case EEP_OP_MODE: - return pBase->opCapFlags; - case EEP_RF_SILENT: - return pBase->rfSilent; - case EEP_OB_2: - return pModal->ob_01; - case EEP_DB_2: - return pModal->db1_01; - case EEP_MINOR_REV: - return pBase->version & AR5416_EEP_VER_MINOR_MASK; - case EEP_TX_MASK: - return pBase->txMask; - case EEP_RX_MASK: - return pBase->rxMask; - default: - return 0; - } -} -static u32 ath9k_hw_get_eeprom_def(struct ath_hw *ah, - enum eeprom_param param) -{ -#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - struct modal_eep_header *pModal = eep->modalHeader; - struct base_eep_header *pBase = &eep->baseEepHeader; - - switch (param) { - case EEP_NFTHRESH_5: - return pModal[0].noiseFloorThreshCh[0]; - case EEP_NFTHRESH_2: - return pModal[1].noiseFloorThreshCh[0]; - case AR_EEPROM_MAC(0): - return pBase->macAddr[0] << 8 | pBase->macAddr[1]; - case AR_EEPROM_MAC(1): - return pBase->macAddr[2] << 8 | pBase->macAddr[3]; - case AR_EEPROM_MAC(2): - return pBase->macAddr[4] << 8 | pBase->macAddr[5]; - case EEP_REG_0: - return pBase->regDmn[0]; - case EEP_REG_1: - return pBase->regDmn[1]; - case EEP_OP_CAP: - return pBase->deviceCap; - case EEP_OP_MODE: - return pBase->opCapFlags; - case EEP_RF_SILENT: - return pBase->rfSilent; - case EEP_OB_5: - return pModal[0].ob; - case EEP_DB_5: - return pModal[0].db; - case EEP_OB_2: - return pModal[1].ob; - case EEP_DB_2: - return pModal[1].db; - case EEP_MINOR_REV: - return AR5416_VER_MASK; - case EEP_TX_MASK: - return pBase->txMask; - case EEP_RX_MASK: - return pBase->rxMask; - case EEP_RXGAIN_TYPE: - return pBase->rxGainType; - case EEP_TXGAIN_TYPE: - return pBase->txGainType; - case EEP_DAC_HPWR_5G: - if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) - return pBase->dacHiPwrMode_5G; - else - return 0; - default: - return 0; - } -#undef AR5416_VER_MASK +#undef EEP_DEF_SPURCHAN } -static u32 (*ath9k_get_eeprom[])(struct ath_hw *, enum eeprom_param) = { - ath9k_hw_get_eeprom_def, - ath9k_hw_get_eeprom_4k +struct eeprom_ops eep_def_ops = { + .check_eeprom = ath9k_hw_def_check_eeprom, + .get_eeprom = ath9k_hw_def_get_eeprom, + .fill_eeprom = ath9k_hw_def_fill_eeprom, + .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver, + .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev, + .get_num_ant_config = ath9k_hw_def_get_num_ant_config, + .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg, + .set_board_values = ath9k_hw_def_set_board_values, + .set_addac = ath9k_hw_def_set_addac, + .set_txpower = ath9k_hw_def_set_txpower, + .get_spur_channel = ath9k_hw_def_get_spur_channel }; -u32 ath9k_hw_get_eeprom(struct ath_hw *ah, - enum eeprom_param param) -{ - return ath9k_get_eeprom[ah->ah_eep_map](ah, param); -} - int ath9k_hw_eeprom_attach(struct ath_hw *ah) { int status; - if (AR_SREV_9285(ah)) + if (AR_SREV_9285(ah)) { ah->ah_eep_map = EEP_MAP_4KBITS; - else + ah->eep_ops = &eep_4k_ops; + } else { ah->ah_eep_map = EEP_MAP_DEFAULT; + ah->eep_ops = &eep_def_ops; + } - if (!ath9k_hw_fill_eeprom(ah)) + if (!ah->eep_ops->fill_eeprom(ah)) return -EIO; - status = ath9k_hw_check_eeprom(ah); + status = ah->eep_ops->check_eeprom(ah); return status; } diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 47c8eea..7a4266f 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -464,38 +464,10 @@ struct eeprom_ops { u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); }; -#define ar5416_get_eep_ver(_ah) \ - (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep_rev(_ah) \ - (((_ah)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) #define ar5416_get_ntxchains(_txchainmask) \ - (((_txchainmask >> 2) & 1) + \ + (((_txchainmask >> 2) & 1) + \ ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) -#define ar5416_get_eep4k_ver(_ah) \ - (((_ah)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep4k_rev(_ah) \ - (((_ah)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) - -int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, - u16 cfgCtl, u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, u8 powerLimit); -void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan); -bool ath9k_hw_set_power_per_rate_table(struct ath_hw *ah, - struct ath9k_channel *chan, int16_t *ratesArray, - u16 cfgCtl, u8 AntennaReduction, - u8 twiceMaxRegulatoryPower, u8 powerLimit); -bool ath9k_hw_set_power_cal_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *pTxPowerIndexOffset); -bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, - struct ath9k_channel *chan); -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan); -u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, - enum ieee80211_band freq_band); -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz); -u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param); int ath9k_hw_eeprom_attach(struct ath_hw *ah); #endif /* EEPROM_H */ diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index ba908e9..f744d8c 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -487,7 +487,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah) sum = 0; for (i = 0; i < 3; i++) { - eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i)); + eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); sum += eeval; ah->macaddr[2 * i] = eeval >> 8; ah->macaddr[2 * i + 1] = eeval & 0xff; @@ -506,8 +506,8 @@ static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) { u32 rxgain_type; - if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { - rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { + rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) INIT_INI_ARRAY(&ah->ah_iniModesRxGain, @@ -532,8 +532,8 @@ static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) { u32 txgain_type; - if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { - txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { + txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) INIT_INI_ARRAY(&ah->ah_iniModesTxGain, @@ -1238,7 +1238,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, REG_WRITE(ah, AR_PHY(0), 0x00000007); REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); - ath9k_hw_set_addac(ah, chan); + ah->eep_ops->set_addac(ah, chan); if (AR_SREV_5416_V22_OR_LATER(ah)) { REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites); @@ -1306,12 +1306,12 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ath9k_hw_set_regs(ah, chan, macmode); ath9k_hw_init_chain_masks(ah); - status = ath9k_hw_set_txpower(ah, chan, - ath9k_regd_get_ctl(ah, chan), - channel->max_antenna_gain * 2, - channel->max_power * 2, - min((u32) MAX_RATE_POWER, - (u32) ah->regulatory.power_limit)); + status = ah->eep_ops->set_txpower(ah, chan, + ath9k_regd_get_ctl(ah, chan), + channel->max_antenna_gain * 2, + channel->max_power * 2, + min((u32) MAX_RATE_POWER, + (u32) ah->regulatory.power_limit)); if (status != 0) { DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "error init'ing transmit power\n"); @@ -1632,12 +1632,12 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah, } } - if (ath9k_hw_set_txpower(ah, chan, - ath9k_regd_get_ctl(ah, chan), - channel->max_antenna_gain * 2, - channel->max_power * 2, - min((u32) MAX_RATE_POWER, - (u32) ah->regulatory.power_limit)) != 0) { + if (ah->eep_ops->set_txpower(ah, chan, + ath9k_regd_get_ctl(ah, chan), + channel->max_antenna_gain * 2, + channel->max_power * 2, + min((u32) MAX_RATE_POWER, + (u32) ah->regulatory.power_limit)) != 0) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "error init'ing transmit power\n"); return false; @@ -1703,7 +1703,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { - cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); if (is2GHz) cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; @@ -1946,7 +1946,7 @@ static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan memset(&mask_p, 0, sizeof(int8_t) * 123); for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { - cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); if (AR_NO_SPUR == cur_bb_spur) break; cur_bb_spur = cur_bb_spur - (chan->channel * 10); @@ -2211,7 +2211,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, else ath9k_hw_spur_mitigate(ah, chan); - if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { + if (!ah->eep_ops->set_board_values(ah, chan)) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "error setting board options\n"); return -EIO; @@ -3092,14 +3092,14 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) struct ath9k_hw_capabilities *pCap = &ah->ah_caps; u16 capField = 0, eeval; - eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0); + eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); ah->regulatory.current_rd = eeval; - eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1); + eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); ah->regulatory.current_rd_ext = eeval; - capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); + capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); if (ah->ah_opmode != NL80211_IFTYPE_AP && ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { @@ -3112,7 +3112,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) "regdomain mapped to 0x%x\n", ah->regulatory.current_rd); } - eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); + eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); if (eeval & AR5416_OPFLAGS_11A) { @@ -3146,11 +3146,11 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) } } - pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK); + pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); if ((ah->ah_isPciExpress) || (eeval & AR5416_OPFLAGS_11A)) { pCap->rx_chainmask = - ath9k_hw_get_eeprom(ah, EEP_RX_MASK); + ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); } else { pCap->rx_chainmask = (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; @@ -3226,7 +3226,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT); + ah->ah_rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { ah->ah_rfkill_gpio = MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); @@ -3266,9 +3266,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; pCap->num_antcfg_5ghz = - ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); + ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); pCap->num_antcfg_2ghz = - ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); + ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) { pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; @@ -3613,12 +3613,12 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); - if (ath9k_hw_set_txpower(ah, chan, - ath9k_regd_get_ctl(ah, chan), - channel->max_antenna_gain * 2, - channel->max_power * 2, - min((u32) MAX_RATE_POWER, - (u32) ah->regulatory.power_limit)) != 0) + if (ah->eep_ops->set_txpower(ah, chan, + ath9k_regd_get_ctl(ah, chan), + channel->max_antenna_gain * 2, + channel->max_power * 2, + min((u32) MAX_RATE_POWER, + (u32) ah->regulatory.power_limit)) != 0) return false; return true; diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 84914e2..f8f46db 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -430,6 +430,7 @@ struct ath_hw { struct ar5416_eeprom_def def; struct ar5416_eeprom_4k map4k; } ah_eeprom; + const struct eeprom_ops *eep_ops; bool sw_mgmt_crypto; bool ah_isPciExpress; diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index da4165b..5a42969 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -205,7 +205,7 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, if (AR_SREV_9280_10_OR_LATER(ah)) return true; - eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV); + eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); @@ -225,15 +225,15 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, if (eepMinorRev >= 2) { if (IS_CHAN_2GHZ(chan)) { - ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2); - db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2); + ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); + db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob2GHz, 3, 197, 0); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, db2GHz, 3, 194, 0); } else { - ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5); - db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5); + ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); + db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob5GHz, 3, 203, 0); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, -- 1.5.6.3 From 6b914484c7140584ab4a0eb4807482489b0778fb Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 12:24:27 +0530 Subject: [PATCH] ath9k: Remove all the useless ah_ variable prefixes Signed-off-by: Sujith --- drivers/net/wireless/ath9k/ani.c | 186 ++++++------ drivers/net/wireless/ath9k/ani.h | 6 +- drivers/net/wireless/ath9k/ath9k.h | 6 +- drivers/net/wireless/ath9k/beacon.c | 26 +- drivers/net/wireless/ath9k/calib.c | 122 ++++---- drivers/net/wireless/ath9k/calib.h | 14 +- drivers/net/wireless/ath9k/eeprom.c | 102 +++--- drivers/net/wireless/ath9k/eeprom.h | 2 +- drivers/net/wireless/ath9k/hw.c | 602 +++++++++++++++++----------------- drivers/net/wireless/ath9k/hw.h | 216 ++++++------- drivers/net/wireless/ath9k/mac.c | 94 +++--- drivers/net/wireless/ath9k/main.c | 92 +++--- drivers/net/wireless/ath9k/pci.c | 4 +- drivers/net/wireless/ath9k/phy.c | 176 +++++----- drivers/net/wireless/ath9k/phy.h | 2 +- drivers/net/wireless/ath9k/rc.c | 12 +- drivers/net/wireless/ath9k/recv.c | 18 +- drivers/net/wireless/ath9k/xmit.c | 6 +- 18 files changed, 841 insertions(+), 845 deletions(-) diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index 6bd2d57..d4df7e6 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c @@ -21,12 +21,12 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, { int i; - for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { - if (ah->ah_ani[i].c && - ah->ah_ani[i].c->channel == chan->channel) + for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { + if (ah->ani[i].c && + ah->ani[i].c->channel == chan->channel) return i; - if (ah->ah_ani[i].c == NULL) { - ah->ah_ani[i].c = chan; + if (ah->ani[i].c == NULL) { + ah->ani[i].c = chan; return i; } } @@ -40,37 +40,37 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, static bool ath9k_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param) { - struct ar5416AniState *aniState = ah->ah_curani; + struct ar5416AniState *aniState = ah->curani; - switch (cmd & ah->ah_ani_function) { + switch (cmd & ah->ani_function) { case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ u32 level = param; - if (level >= ARRAY_SIZE(ah->ah_totalSizeDesired)) { + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "level out of range (%u > %u)\n", level, - (unsigned)ARRAY_SIZE(ah->ah_totalSizeDesired)); + (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); return false; } REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_TOT_DES, - ah->ah_totalSizeDesired[level]); + ah->totalSizeDesired[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_LOW, - ah->ah_coarseLow[level]); + ah->coarse_low[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_HIGH, - ah->ah_coarseHigh[level]); + ah->coarse_high[level]); REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, - ah->ah_firpwr[level]); + ah->firpwr[level]); if (level > aniState->noiseImmunityLevel) - ah->ah_stats.ast_ani_niup++; + ah->stats.ast_ani_niup++; else if (level < aniState->noiseImmunityLevel) - ah->ah_stats.ast_ani_nidown++; + ah->stats.ast_ani_nidown++; aniState->noiseImmunityLevel = level; break; } @@ -124,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, if (!on != aniState->ofdmWeakSigDetectOff) { if (on) - ah->ah_stats.ast_ani_ofdmon++; + ah->stats.ast_ani_ofdmon++; else - ah->ah_stats.ast_ani_ofdmoff++; + ah->stats.ast_ani_ofdmoff++; aniState->ofdmWeakSigDetectOff = !on; } break; @@ -140,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, weakSigThrCck[high]); if (high != aniState->cckWeakSigThreshold) { if (high) - ah->ah_stats.ast_ani_cckhigh++; + ah->stats.ast_ani_cckhigh++; else - ah->ah_stats.ast_ani_ccklow++; + ah->stats.ast_ani_ccklow++; aniState->cckWeakSigThreshold = high; } break; @@ -162,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, AR_PHY_FIND_SIG_FIRSTEP, firstep[level]); if (level > aniState->firstepLevel) - ah->ah_stats.ast_ani_stepup++; + ah->stats.ast_ani_stepup++; else if (level < aniState->firstepLevel) - ah->ah_stats.ast_ani_stepdown++; + ah->stats.ast_ani_stepdown++; aniState->firstepLevel = level; break; } @@ -185,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, AR_PHY_TIMING5_CYCPWR_THR1, cycpwrThr1[level]); if (level > aniState->spurImmunityLevel) - ah->ah_stats.ast_ani_spurup++; + ah->stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) - ah->ah_stats.ast_ani_spurdown++; + ah->stats.ast_ani_spurdown++; aniState->spurImmunityLevel = level; break; } @@ -235,10 +235,10 @@ static void ath9k_ani_restart(struct ath_hw *ah) if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; + aniState = ah->curani; aniState->listenTime = 0; - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { aniState->ofdmPhyErrBase = 0; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -279,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; + aniState = ah->curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, @@ -295,7 +295,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) } } - if (ah->ah_opmode == NL80211_IFTYPE_AP) { + if (ah->opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1); @@ -350,14 +350,14 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; + aniState = ah->curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel + 1)) { return; } } - if (ah->ah_opmode == NL80211_IFTYPE_AP) { + if (ah->opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1); @@ -383,9 +383,9 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) struct ar5416AniState *aniState; int32_t rssi; - aniState = ah->ah_curani; + aniState = ah->curani; - if (ah->ah_opmode == NL80211_IFTYPE_AP) { + if (ah->opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel > 0) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel - 1)) @@ -441,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) rxFrameCount = REG_READ(ah, AR_RFCNT); cycleCount = REG_READ(ah, AR_CCCNT); - aniState = ah->ah_curani; + aniState = ah->curani; if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { listenTime = 0; - ah->ah_stats.ast_ani_lzero++; + ah->stats.ast_ani_lzero++; } else { int32_t ccdelta = cycleCount - aniState->cycleCount; int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; @@ -462,21 +462,21 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) void ath9k_ani_reset(struct ath_hw *ah) { struct ar5416AniState *aniState; - struct ath9k_channel *chan = ah->ah_curchan; + struct ath9k_channel *chan = ah->curchan; int index; if (!DO_ANI(ah)) return; index = ath9k_hw_get_ani_channel_idx(ah, chan); - aniState = &ah->ah_ani[index]; - ah->ah_curani = aniState; + aniState = &ah->ani[index]; + ah->curani = aniState; - if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION - && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { + if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION + && ah->opmode != NL80211_IFTYPE_ADHOC) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, - "Reset ANI state opmode %u\n", ah->ah_opmode); - ah->ah_stats.ast_ani_reset++; + "Reset ANI state opmode %u\n", ah->opmode); + ah->stats.ast_ani_reset++; ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); @@ -489,15 +489,15 @@ void ath9k_ani_reset(struct ath_hw *ah) ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | ATH9K_RX_FILTER_PHYERR); - if (ah->ah_opmode == NL80211_IFTYPE_AP) { - ah->ah_curani->ofdmTrigHigh = - ah->ah_config.ofdm_trig_high; - ah->ah_curani->ofdmTrigLow = - ah->ah_config.ofdm_trig_low; - ah->ah_curani->cckTrigHigh = - ah->ah_config.cck_trig_high; - ah->ah_curani->cckTrigLow = - ah->ah_config.cck_trig_low; + if (ah->opmode == NL80211_IFTYPE_AP) { + ah->curani->ofdmTrigHigh = + ah->config.ofdm_trig_high; + ah->curani->ofdmTrigLow = + ah->config.ofdm_trig_low; + ah->curani->cckTrigHigh = + ah->config.cck_trig_high; + ah->curani->cckTrigLow = + ah->config.cck_trig_low; } ath9k_ani_restart(ah); return; @@ -518,7 +518,7 @@ void ath9k_ani_reset(struct ath_hw *ah) if (aniState->firstepLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel); - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & ~ATH9K_RX_FILTER_PHYERR); ath9k_ani_restart(ah); @@ -542,19 +542,19 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; - ah->ah_stats.ast_nodestats = *stats; + aniState = ah->curani; + ah->stats.ast_nodestats = *stats; listenTime = ath9k_hw_ani_get_listen_time(ah); if (listenTime < 0) { - ah->ah_stats.ast_ani_lneg++; + ah->stats.ast_ani_lneg++; ath9k_ani_restart(ah); return; } aniState->listenTime += listenTime; - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { u32 phyCnt1, phyCnt2; u32 ofdmPhyErrCnt, cckPhyErrCnt; @@ -591,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, } ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ah->ah_stats.ast_ani_ofdmerrs += + ah->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ah->ah_stats.ast_ani_cckerrs += + ah->stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; } - if (aniState->listenTime > 5 * ah->ah_aniPeriod) { + if (aniState->listenTime > 5 * ah->aniperiod) { if (aniState->ofdmPhyErrCount <= aniState->listenTime * aniState->ofdmTrigLow / 1000 && aniState->cckPhyErrCount <= aniState->listenTime * aniState->cckTrigLow / 1000) ath9k_hw_ani_lower_immunity(ah); ath9k_ani_restart(ah); - } else if (aniState->listenTime > ah->ah_aniPeriod) { + } else if (aniState->listenTime > ah->aniperiod) { if (aniState->ofdmPhyErrCount > aniState->listenTime * aniState->ofdmTrigHigh / 1000) { ath9k_hw_ani_ofdm_err_trigger(ah); @@ -624,7 +624,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, bool ath9k_hw_phycounters(struct ath_hw *ah) { - return ah->ah_hasHwPhyCounters ? true : false; + return ah->has_hw_phycounters ? true : false; } void ath9k_enable_mib_counters(struct ath_hw *ah) @@ -712,7 +712,7 @@ void ath9k_hw_procmibevent(struct ath_hw *ah, /* Clear the mib counters and save them in the stats */ ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); - ah->ah_stats.ast_nodestats = *stats; + ah->stats.ast_nodestats = *stats; if (!DO_ANI(ah)) return; @@ -722,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hw *ah, phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { - struct ar5416AniState *aniState = ah->ah_curani; + struct ar5416AniState *aniState = ah->curani; u32 ofdmPhyErrCnt, cckPhyErrCnt; /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ah->ah_stats.ast_ani_ofdmerrs += + ah->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ah->ah_stats.ast_ani_cckerrs += + ah->stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; @@ -761,10 +761,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah) const int firpwr[] = { -78, -78, -78, -78, -80 }; for (i = 0; i < 5; i++) { - ah->ah_totalSizeDesired[i] = totalSizeDesired[i]; - ah->ah_coarseHigh[i] = coarseHigh[i]; - ah->ah_coarseLow[i] = coarseLow[i]; - ah->ah_firpwr[i] = firpwr[i]; + ah->totalSizeDesired[i] = totalSizeDesired[i]; + ah->coarse_high[i] = coarseHigh[i]; + ah->coarse_low[i] = coarseLow[i]; + ah->firpwr[i] = firpwr[i]; } } @@ -774,50 +774,50 @@ void ath9k_hw_ani_attach(struct ath_hw *ah) DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); - ah->ah_hasHwPhyCounters = 1; - - memset(ah->ah_ani, 0, sizeof(ah->ah_ani)); - for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { - ah->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; - ah->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; - ah->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; - ah->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; - ah->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; - ah->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; - ah->ah_ani[i].ofdmWeakSigDetectOff = + ah->has_hw_phycounters = 1; + + memset(ah->ani, 0, sizeof(ah->ani)); + for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { + ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; + ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; + ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; + ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; + ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; + ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; + ah->ani[i].ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; - ah->ah_ani[i].cckWeakSigThreshold = + ah->ani[i].cckWeakSigThreshold = ATH9K_ANI_CCK_WEAK_SIG_THR; - ah->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; - ah->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; - if (ah->ah_hasHwPhyCounters) { - ah->ah_ani[i].ofdmPhyErrBase = + ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; + ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; + if (ah->has_hw_phycounters) { + ah->ani[i].ofdmPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; - ah->ah_ani[i].cckPhyErrBase = + ah->ani[i].cckPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; } } - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n", - ah->ah_ani[0].ofdmPhyErrBase); + ah->ani[0].ofdmPhyErrBase); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", - ah->ah_ani[0].cckPhyErrBase); + ah->ani[0].cckPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_1, ah->ah_ani[0].ofdmPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_2, ah->ah_ani[0].cckPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); ath9k_enable_mib_counters(ah); } - ah->ah_aniPeriod = ATH9K_ANI_PERIOD; - if (ah->ah_config.enable_ani) - ah->ah_procPhyErr |= HAL_PROCESS_ANI; + ah->aniperiod = ATH9K_ANI_PERIOD; + if (ah->config.enable_ani) + ah->proc_phyerr |= HAL_PROCESS_ANI; } void ath9k_hw_ani_detach(struct ath_hw *ah) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { ath9k_hw_disable_mib_counters(ah); REG_WRITE(ah, AR_PHY_ERR_1, 0); REG_WRITE(ah, AR_PHY_ERR_2, 0); diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h index 7e9ca95..7315761 100644 --- a/drivers/net/wireless/ath9k/ani.h +++ b/drivers/net/wireless/ath9k/ani.h @@ -20,12 +20,12 @@ #define HAL_PROCESS_ANI 0x00000001 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) -#define DO_ANI(ah) (((ah)->ah_procPhyErr & HAL_PROCESS_ANI)) +#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI)) #define HAL_EP_RND(x, mul) \ ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) #define BEACON_RSSI(ahp) \ - HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ + HAL_EP_RND(ahp->stats.ast_nodestats.ns_avgbrssi, \ ATH9K_RSSI_EP_MULTIPLIER) #define ATH9K_ANI_OFDM_TRIG_HIGH 500 @@ -118,7 +118,7 @@ struct ar5416Stats { struct ath9k_mib_stats ast_mibstats; struct ath9k_node_stats ast_nodestats; }; -#define ah_mibStats ah_stats.ast_mibstats +#define ah_mibStats stats.ast_mibstats void ath9k_ani_reset(struct ath_hw *ah); void ath9k_hw_ani_monitor(struct ath_hw *ah, diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 91140b7..0b0f82c 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -670,8 +670,8 @@ static inline void ath_ahb_exit(void) {}; static inline void ath9k_ps_wakeup(struct ath_softc *sc) { if (atomic_inc_return(&sc->ps_usecount) == 1) - if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) { - sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode; + if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) { + sc->sc_ah->restore_mode = sc->sc_ah->power_mode; ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); } } @@ -681,6 +681,6 @@ static inline void ath9k_ps_restore(struct ath_softc *sc) if (atomic_dec_and_test(&sc->ps_usecount)) if (sc->hw->conf.flags & IEEE80211_CONF_PS) ath9k_hw_setpower(sc->sc_ah, - sc->sc_ah->ah_restore_mode); + sc->sc_ah->restore_mode); } #endif /* ATH9K_H */ diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 19ec4e8..2e2ef35 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -27,7 +27,7 @@ static int ath_beaconq_config(struct ath_softc *sc) struct ath9k_tx_queue_info qi; ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* Always burst out beacon and CAB traffic. */ qi.tqi_aifs = 1; qi.tqi_cwmin = 0; @@ -82,8 +82,8 @@ static void ath_beacon_setup(struct ath_softc *sc, flags = ATH9K_TXDESC_NOACK; - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && - (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC && + (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) { ds->ds_link = bf->bf_daddr; /* self-linked */ flags |= ATH9K_TXDESC_VEOL; /* Let hardware handle antenna switching. */ @@ -310,8 +310,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) struct ath_buf, list); list_del(&avp->av_bcbuf->list); - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || - !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP || + !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) { int slot; /* * Assign the vif to a beacon xmit slot. As @@ -631,7 +631,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) avp = (void *)vif->drv_priv; opmode = avp->av_opmode; } else { - opmode = sc->sc_ah->ah_opmode; + opmode = sc->sc_ah->opmode; } memset(&conf, 0, sizeof(struct ath_beacon_config)); @@ -647,7 +647,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp); /* XXX conditionalize multi-bss support? */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* * For multi-bss ap support beacons are either staggered * evenly over N slots or burst together. For the former @@ -670,7 +670,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) nexttbtt, intval, conf.beacon_interval); /* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) { struct ath9k_beacon_state bs; u64 tsf; u32 tsftu; @@ -789,7 +789,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ath9k_hw_set_interrupts(ah, 0); if (nexttbtt == intval) intval |= ATH9K_BEACON_RESET_TSF; - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) { /* * Pull nexttbtt forward to reflect the current * TSF @@ -818,10 +818,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) * deal with things. */ intval |= ATH9K_BEACON_ENA; - if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) + if (!(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) sc->imask |= ATH9K_INT_SWBA; ath_beaconq_config(sc); - } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* * In AP mode we enable the beacon timers and * SWBA interrupts to prepare beacon frames. @@ -837,8 +837,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) * When using a self-linked beacon descriptor in * ibss mode load it once here. */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && - (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) + if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC && + (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) ath_beacon_start_adhoc(sc, 0); } } diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 7e70a81..1fc3a08 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -229,13 +229,13 @@ static void ath9k_hw_reset_calibration(struct ath_hw *ah, currCal->calState = CAL_RUNNING; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_Meas0.sign[i] = 0; - ah->ah_Meas1.sign[i] = 0; - ah->ah_Meas2.sign[i] = 0; - ah->ah_Meas3.sign[i] = 0; + ah->meas0.sign[i] = 0; + ah->meas1.sign[i] = 0; + ah->meas2.sign[i] = 0; + ah->meas3.sign[i] = 0; } - ah->ah_CalSamples = 0; + ah->cal_samples = 0; } static void ath9k_hw_per_calibration(struct ath_hw *ah, @@ -251,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hw *ah, AR_PHY_TIMING_CTRL4_DO_CAL)) { currCal->calData->calCollect(ah); - ah->ah_CalSamples++; + ah->cal_samples++; - if (ah->ah_CalSamples >= currCal->calData->calNumSamples) { + if (ah->cal_samples >= currCal->calData->calNumSamples) { int i, numChains = 0; for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (rxchainmask & (1 << i)) @@ -279,7 +279,7 @@ static bool ath9k_hw_iscal_supported(struct ath_hw *ah, { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - switch (calType & ah->ah_suppCals) { + switch (calType & ah->supp_cals) { case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ return true; case ADC_GAIN_CAL: @@ -297,17 +297,17 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah) int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_totalPowerMeasI[i] += + ah->totalPowerMeasI[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ah->ah_totalPowerMeasQ[i] += + ah->totalPowerMeasQ[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ah->ah_totalIqCorrMeas[i] += + ah->totalIqCorrMeas[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", - ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i], - ah->ah_totalPowerMeasQ[i], - ah->ah_totalIqCorrMeas[i]); + ah->cal_samples, i, ah->totalPowerMeasI[i], + ah->totalPowerMeasQ[i], + ah->totalIqCorrMeas[i]); } } @@ -316,23 +316,23 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_totalAdcIOddPhase[i] += + ah->totalAdcIOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ah->ah_totalAdcIEvenPhase[i] += + ah->totalAdcIEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ah->ah_totalAdcQOddPhase[i] += + ah->totalAdcQOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ah->ah_totalAdcQEvenPhase[i] += + ah->totalAdcQEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ah->ah_CalSamples, i, - ah->ah_totalAdcIOddPhase[i], - ah->ah_totalAdcIEvenPhase[i], - ah->ah_totalAdcQOddPhase[i], - ah->ah_totalAdcQEvenPhase[i]); + ah->cal_samples, i, + ah->totalAdcIOddPhase[i], + ah->totalAdcIEvenPhase[i], + ah->totalAdcQOddPhase[i], + ah->totalAdcQEvenPhase[i]); } } @@ -341,23 +341,23 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_totalAdcDcOffsetIOddPhase[i] += + ah->totalAdcDcOffsetIOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ah->ah_totalAdcDcOffsetIEvenPhase[i] += + ah->totalAdcDcOffsetIEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ah->ah_totalAdcDcOffsetQOddPhase[i] += + ah->totalAdcDcOffsetQOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ah->ah_totalAdcDcOffsetQEvenPhase[i] += + ah->totalAdcDcOffsetQEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ah->ah_CalSamples, i, - ah->ah_totalAdcDcOffsetIOddPhase[i], - ah->ah_totalAdcDcOffsetIEvenPhase[i], - ah->ah_totalAdcDcOffsetQOddPhase[i], - ah->ah_totalAdcDcOffsetQEvenPhase[i]); + ah->cal_samples, i, + ah->totalAdcDcOffsetIOddPhase[i], + ah->totalAdcDcOffsetIEvenPhase[i], + ah->totalAdcDcOffsetQOddPhase[i], + ah->totalAdcDcOffsetQEvenPhase[i]); } } @@ -369,9 +369,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) int iqCorrNeg, i; for (i = 0; i < numChains; i++) { - powerMeasI = ah->ah_totalPowerMeasI[i]; - powerMeasQ = ah->ah_totalPowerMeasQ[i]; - iqCorrMeas = ah->ah_totalIqCorrMeas[i]; + powerMeasI = ah->totalPowerMeasI[i]; + powerMeasQ = ah->totalPowerMeasQ[i]; + iqCorrMeas = ah->totalIqCorrMeas[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting IQ Cal and Correction for Chain %d\n", @@ -379,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Orignal: Chn %diq_corr_meas = 0x%08x\n", - i, ah->ah_totalIqCorrMeas[i]); + i, ah->totalIqCorrMeas[i]); iqCorrNeg = 0; @@ -443,10 +443,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) u32 qGainMismatch, iGainMismatch, val, i; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ah->ah_totalAdcIOddPhase[i]; - iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i]; - qOddMeasOffset = ah->ah_totalAdcQOddPhase[i]; - qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i]; + iOddMeasOffset = ah->totalAdcIOddPhase[i]; + iEvenMeasOffset = ah->totalAdcIEvenPhase[i]; + qOddMeasOffset = ah->totalAdcQOddPhase[i]; + qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC Gain Cal for Chain %d\n", i); @@ -499,15 +499,15 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) u32 iOddMeasOffset, iEvenMeasOffset, val, i; int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; const struct hal_percal_data *calData = - ah->ah_cal_list_curr->calData; + ah->cal_list_curr->calData; u32 numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i]; - iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i]; - qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i]; - qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i]; + iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i]; + iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i]; + qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; + qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC DC Offset Cal for Chain %d\n", i); @@ -555,9 +555,9 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) bool ath9k_hw_reset_calvalid(struct ath_hw *ah) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - struct hal_cal_list *currCal = ah->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->cal_list_curr; - if (!ah->ah_curchan) + if (!ah->curchan) return true; if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) @@ -580,7 +580,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) "Resetting Cal %d state for channel %u\n", currCal->calData->calType, conf->channel->center_freq); - ah->ah_curchan->CalValid &= ~currCal->calData->calType; + ah->curchan->CalValid &= ~currCal->calData->calType; currCal->calState = CAL_WAITING; return false; @@ -722,7 +722,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone) { - struct hal_cal_list *currCal = ah->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->cal_list_curr; *isCalDone = true; @@ -732,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, isCalDone); if (*isCalDone) { - ah->ah_cal_list_curr = currCal = currCal->calNext; + ah->cal_list_curr = currCal = currCal->calNext; if (currCal->calState == CAL_WAITING) { *isCalDone = false; @@ -743,7 +743,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, if (longcal) { ath9k_hw_getnf(ah, chan); - ath9k_hw_loadnf(ah, ah->ah_curchan); + ath9k_hw_loadnf(ah, ah->curchan); ath9k_hw_start_nfcal(ah); if (chan->channelFlags & CHANNEL_CW_INT) @@ -869,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); - ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL; + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { - INIT_CAL(&ah->ah_adcGainCalData); - INSERT_CAL(ah, &ah->ah_adcGainCalData); + INIT_CAL(&ah->adcgain_caldata); + INSERT_CAL(ah, &ah->adcgain_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC Gain Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { - INIT_CAL(&ah->ah_adcDcCalData); - INSERT_CAL(ah, &ah->ah_adcDcCalData); + INIT_CAL(&ah->adcdc_caldata); + INSERT_CAL(ah, &ah->adcdc_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC DC Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { - INIT_CAL(&ah->ah_iqCalData); - INSERT_CAL(ah, &ah->ah_iqCalData); + INIT_CAL(&ah->iq_caldata); + INSERT_CAL(ah, &ah->iq_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling IQ Calibration.\n"); } - ah->ah_cal_list_curr = ah->ah_cal_list; + ah->cal_list_curr = ah->cal_list; - if (ah->ah_cal_list_curr) - ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr); + if (ah->cal_list_curr) + ath9k_hw_reset_calibration(ah, ah->cal_list_curr); } chan->CalValid = 0; diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h index e2c6140..d2448f0 100644 --- a/drivers/net/wireless/ath9k/calib.h +++ b/drivers/net/wireless/ath9k/calib.h @@ -56,14 +56,14 @@ struct ar5416IniArray { #define INSERT_CAL(_ahp, _perCal) \ do { \ - if ((_ahp)->ah_cal_list_last == NULL) { \ - (_ahp)->ah_cal_list = \ - (_ahp)->ah_cal_list_last = (_perCal); \ - ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ + if ((_ahp)->cal_list_last == NULL) { \ + (_ahp)->cal_list = \ + (_ahp)->cal_list_last = (_perCal); \ + ((_ahp)->cal_list_last)->calNext = (_perCal); \ } else { \ - ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ - (_ahp)->ah_cal_list_last = (_perCal); \ - (_perCal)->calNext = (_ahp)->ah_cal_list; \ + ((_ahp)->cal_list_last)->calNext = (_perCal); \ + (_ahp)->cal_list_last = (_perCal); \ + (_perCal)->calNext = (_ahp)->cal_list; \ } \ } while (0) diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 2e604e1..c0359ad 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -27,7 +27,7 @@ static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, REG_WRITE(ah, reg, regVal); - if (ah->ah_config.analog_shiftreg) + if (ah->config.analog_shiftreg) udelay(100); return; @@ -268,18 +268,18 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq, static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) { - return ((ah->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF); + return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF); } static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) { - return ((ah->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF); + return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF); } static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; u16 *eep_data; int addr, eep_start_loc = 0; @@ -308,7 +308,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) { #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) struct ar5416_eeprom_4k *eep = - (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; + (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -332,7 +332,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) if (magic2 == AR5416_EEPROM_MAGIC) { need_swap = true; - eepdata = (u16 *) (&ah->ah_eeprom); + eepdata = (u16 *) (&ah->eeprom); for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { temp = swab16(*eepdata); @@ -359,16 +359,16 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); + el = swab16(ah->eeprom.map4k.baseEepHeader.length); else - el = ah->ah_eeprom.map4k.baseEepHeader.length; + el = ah->eeprom.map4k.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ah->ah_eeprom); + eepdata = (u16 *)(&ah->eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -433,7 +433,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; struct base_eep_header_4k *pBase = &eep->baseEepHeader; @@ -643,7 +643,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; struct cal_data_per_freq_4k *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -692,7 +692,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && + (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -763,7 +763,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, u16 twiceMaxRegulatoryPower, u16 powerLimit) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -791,7 +791,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ah->ah_txchainmask; + tx_chainmask = ah->txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -997,7 +997,7 @@ static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; struct modal_eep_4k_header *pModal = &pEepData->modalHeader; int16_t ratesArray[Ar5416RateSize]; int16_t txPowerIndexOffset = 0; @@ -1121,7 +1121,7 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) @@ -1134,8 +1134,8 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah, if (pModal->xpaBiasLvl != 0xff) { biaslevel = pModal->xpaBiasLvl; - INI_RA(&ah->ah_iniAddac, 7, 1) = - (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; + INI_RA(&ah->iniAddac, 7, 1) = + (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } } @@ -1143,7 +1143,7 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; int regChainOffset; u8 txRxAttenLocal; u8 ob[5], db1[5], db2[5]; @@ -1328,7 +1328,7 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; return pModal->antCtrlCommon & 0xFFFF; @@ -1343,19 +1343,19 @@ static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah, u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) { #define EEP_MAP4K_SPURCHAN \ - (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) + (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur idx %d is2Ghz. %d val %x\n", - i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); + i, is2GHz, ah->config.spurchans[i][is2GHz]); - switch (ah->ah_config.spurmode) { + switch (ah->config.spurmode) { case SPUR_DISABLE: break; case SPUR_ENABLE_IOCTL: - spur_val = ah->ah_config.spurchans[i][is2GHz]; + spur_val = ah->config.spurchans[i][is2GHz]; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur val from new loc. %d\n", spur_val); break; @@ -1389,18 +1389,18 @@ struct eeprom_ops eep_4k_ops = { static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) { - return ((ah->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF); + return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF); } static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) { - return ((ah->ah_eeprom.def.baseEepHeader.version) & 0xFFF); + return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF); } static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; u16 *eep_data; int addr, ar5416_eep_start_loc = 0x100; @@ -1422,7 +1422,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) { struct ar5416_eeprom_def *eep = - (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; + (struct ar5416_eeprom_def *) &ah->eeprom.def; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -1446,7 +1446,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) if (magic2 == AR5416_EEPROM_MAGIC) { size = sizeof(struct ar5416_eeprom_def); need_swap = true; - eepdata = (u16 *) (&ah->ah_eeprom); + eepdata = (u16 *) (&ah->eeprom); for (addr = 0; addr < size / sizeof(u16); addr++) { temp = swab16(*eepdata); @@ -1473,16 +1473,16 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ah->ah_eeprom.def.baseEepHeader.length); + el = swab16(ah->eeprom.def.baseEepHeader.length); else - el = ah->ah_eeprom.def.baseEepHeader.length; + el = ah->eeprom.def.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ah->ah_eeprom); + eepdata = (u16 *)(&ah->eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -1551,7 +1551,7 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; struct modal_eep_header *pModal = eep->modalHeader; struct base_eep_header *pBase = &eep->baseEepHeader; @@ -1611,7 +1611,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, { #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) struct modal_eep_header *pModal; - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; int i, regChainOffset; u8 txRxAttenLocal; @@ -1629,7 +1629,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, } if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) + (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) regChainOffset = (i == 1) ? 0x2000 : 0x1000; else @@ -1855,7 +1855,7 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah, { #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) struct modal_eep_header *pModal; - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) @@ -1895,10 +1895,10 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah, } if (IS_CHAN_2GHZ(chan)) { - INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, + INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } else { - INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, + INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac, 6, 1) & (~0xc0)) | biaslevel << 6; } #undef XPA_LVL_FREQ @@ -2073,7 +2073,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; struct cal_data_per_freq *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -2129,7 +2129,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && + (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -2206,7 +2206,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -2236,7 +2236,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ah->ah_txchainmask; + tx_chainmask = ah->txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -2493,7 +2493,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; struct modal_eep_header *pModal = &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); int16_t ratesArray[Ar5416RateSize]; @@ -2621,7 +2621,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); struct base_eep_header *pBase = &eep->baseEepHeader; @@ -2639,7 +2639,7 @@ static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); @@ -2649,19 +2649,19 @@ static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) { #define EEP_DEF_SPURCHAN \ - (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) + (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur idx %d is2Ghz. %d val %x\n", - i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); + i, is2GHz, ah->config.spurchans[i][is2GHz]); - switch (ah->ah_config.spurmode) { + switch (ah->config.spurmode) { case SPUR_DISABLE: break; case SPUR_ENABLE_IOCTL: - spur_val = ah->ah_config.spurchans[i][is2GHz]; + spur_val = ah->config.spurchans[i][is2GHz]; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur val from new loc. %d\n", spur_val); break; @@ -2694,10 +2694,10 @@ int ath9k_hw_eeprom_attach(struct ath_hw *ah) int status; if (AR_SREV_9285(ah)) { - ah->ah_eep_map = EEP_MAP_4KBITS; + ah->eep_map = EEP_MAP_4KBITS; ah->eep_ops = &eep_4k_ops; } else { - ah->ah_eep_map = EEP_MAP_DEFAULT; + ah->eep_map = EEP_MAP_DEFAULT; ah->eep_ops = &eep_def_ops; } diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 7a4266f..99863b5 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -441,7 +441,7 @@ struct ath9k_country_entry { u8 iso[3]; }; -enum hal_eep_map { +enum ath9k_eep_map { EEP_MAP_DEFAULT = 0x0, EEP_MAP_4KBITS, EEP_MAP_MAX diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index f744d8c..72ca1c8 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -45,7 +45,7 @@ static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - if (!ah->ah_curchan) /* should really check for CCK instead */ + if (!ah->curchan) /* should really check for CCK instead */ return clks / ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; @@ -67,7 +67,7 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - if (!ah->ah_curchan) /* should really check for CCK instead */ + if (!ah->curchan) /* should really check for CCK instead */ return usecs *ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; @@ -118,7 +118,7 @@ bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; if (flags & CHANNEL_5GHZ) { *low = pCap->low_5ghz_chan; @@ -155,15 +155,15 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah, txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); break; case WLAN_RC_PHY_OFDM: - if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { + if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; numBits = OFDM_PLCP_BITS + (frameLen << 3); numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); txTime = OFDM_SIFS_TIME_QUARTER + OFDM_PREAMBLE_TIME_QUARTER + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); - } else if (ah->ah_curchan && - IS_CHAN_HALF_RATE(ah->ah_curchan)) { + } else if (ah->curchan && + IS_CHAN_HALF_RATE(ah->curchan)) { bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; numBits = OFDM_PLCP_BITS + (frameLen << 3); numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); @@ -216,7 +216,7 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah, centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); centers->ext_center = centers->synth_center + (extoff * - ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? + ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? HT40_CHANNEL_CENTER_SHIFT : 15)); } @@ -235,7 +235,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah) ah->hw_version.macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); - ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; + ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; } else { if (!AR_SREV_9100(ah)) ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); @@ -243,7 +243,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah) ah->hw_version.macRev = val & AR_SREV_REVISION; if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) - ah->ah_isPciExpress = true; + ah->is_pciexpress = true; } } @@ -355,40 +355,40 @@ static void ath9k_hw_set_defaults(struct ath_hw *ah) { int i; - ah->ah_config.dma_beacon_response_time = 2; - ah->ah_config.sw_beacon_response_time = 10; - ah->ah_config.additional_swba_backoff = 0; - ah->ah_config.ack_6mb = 0x0; - ah->ah_config.cwm_ignore_extcca = 0; - ah->ah_config.pcie_powersave_enable = 0; - ah->ah_config.pcie_l1skp_enable = 0; - ah->ah_config.pcie_clock_req = 0; - ah->ah_config.pcie_power_reset = 0x100; - ah->ah_config.pcie_restore = 0; - ah->ah_config.pcie_waen = 0; - ah->ah_config.analog_shiftreg = 1; - ah->ah_config.ht_enable = 1; - ah->ah_config.ofdm_trig_low = 200; - ah->ah_config.ofdm_trig_high = 500; - ah->ah_config.cck_trig_high = 200; - ah->ah_config.cck_trig_low = 100; - ah->ah_config.enable_ani = 1; - ah->ah_config.noise_immunity_level = 4; - ah->ah_config.ofdm_weaksignal_det = 1; - ah->ah_config.cck_weaksignal_thr = 0; - ah->ah_config.spur_immunity_level = 2; - ah->ah_config.firstep_level = 0; - ah->ah_config.rssi_thr_high = 40; - ah->ah_config.rssi_thr_low = 7; - ah->ah_config.diversity_control = 0; - ah->ah_config.antenna_switch_swap = 0; + ah->config.dma_beacon_response_time = 2; + ah->config.sw_beacon_response_time = 10; + ah->config.additional_swba_backoff = 0; + ah->config.ack_6mb = 0x0; + ah->config.cwm_ignore_extcca = 0; + ah->config.pcie_powersave_enable = 0; + ah->config.pcie_l1skp_enable = 0; + ah->config.pcie_clock_req = 0; + ah->config.pcie_power_reset = 0x100; + ah->config.pcie_restore = 0; + ah->config.pcie_waen = 0; + ah->config.analog_shiftreg = 1; + ah->config.ht_enable = 1; + ah->config.ofdm_trig_low = 200; + ah->config.ofdm_trig_high = 500; + ah->config.cck_trig_high = 200; + ah->config.cck_trig_low = 100; + ah->config.enable_ani = 1; + ah->config.noise_immunity_level = 4; + ah->config.ofdm_weaksignal_det = 1; + ah->config.cck_weaksignal_thr = 0; + ah->config.spur_immunity_level = 2; + ah->config.firstep_level = 0; + ah->config.rssi_thr_high = 40; + ah->config.rssi_thr_low = 7; + ah->config.diversity_control = 0; + ah->config.antenna_switch_swap = 0; for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { - ah->ah_config.spurchans[i][0] = AR_NO_SPUR; - ah->ah_config.spurchans[i][1] = AR_NO_SPUR; + ah->config.spurchans[i][0] = AR_NO_SPUR; + ah->config.spurchans[i][1] = AR_NO_SPUR; } - ah->ah_config.intr_mitigation = 1; + ah->config.intr_mitigation = 1; } static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, @@ -418,19 +418,19 @@ static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, ah->regulatory.power_limit = MAX_RATE_POWER; ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; - ah->ah_atimWindow = 0; - ah->ah_diversityControl = ah->ah_config.diversity_control; - ah->ah_antennaSwitchSwap = - ah->ah_config.antenna_switch_swap; - ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; - ah->ah_beaconInterval = 100; - ah->ah_enable32kHzClock = DONT_USE_32KHZ; - ah->ah_slottime = (u32) -1; - ah->ah_acktimeout = (u32) -1; - ah->ah_ctstimeout = (u32) -1; - ah->ah_globaltxtimeout = (u32) -1; - - ah->ah_gBeaconRate = 0; + ah->atim_window = 0; + ah->diversity_control = ah->config.diversity_control; + ah->antenna_switch_swap = + ah->config.antenna_switch_swap; + ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; + ah->beacon_interval = 100; + ah->enable_32kHz_clock = DONT_USE_32KHZ; + ah->slottime = (u32) -1; + ah->acktimeout = (u32) -1; + ah->ctstimeout = (u32) -1; + ah->globaltxtimeout = (u32) -1; + + ah->gbeacon_rate = 0; return ah; } @@ -510,19 +510,19 @@ static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_backoff_13db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_backoff_23db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); else - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); } else { - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); } @@ -536,15 +536,15 @@ static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) - INIT_INI_ARRAY(&ah->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->iniModesTxGain, ar9280Modes_high_power_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); else - INIT_INI_ARRAY(&ah->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); } else { - INIT_INI_ARRAY(&ah->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); } @@ -592,8 +592,8 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ath9k_hw_set_defaults(ah); - if (ah->ah_config.intr_mitigation != 0) - ah->ah_intrMitigation = true; + if (ah->config.intr_mitigation != 0) + ah->intr_mitigation = true; if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); @@ -607,18 +607,18 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, goto bad; } - if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { + if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) { - ah->ah_config.serialize_regmode = + ah->config.serialize_regmode = SER_REG_MODE_ON; } else { - ah->ah_config.serialize_regmode = + ah->config.serialize_regmode = SER_REG_MODE_OFF; } } DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n", - ah->ah_config.serialize_regmode); + ah->config.serialize_regmode); if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && @@ -633,41 +633,41 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } if (AR_SREV_9100(ah)) { - ah->ah_iqCalData.calData = &iq_cal_multi_sample; - ah->ah_suppCals = IQ_MISMATCH_CAL; - ah->ah_isPciExpress = false; + ah->iq_caldata.calData = &iq_cal_multi_sample; + ah->supp_cals = IQ_MISMATCH_CAL; + ah->is_pciexpress = false; } ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); if (AR_SREV_9160_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) { - ah->ah_iqCalData.calData = &iq_cal_single_sample; - ah->ah_adcGainCalData.calData = + ah->iq_caldata.calData = &iq_cal_single_sample; + ah->adcgain_caldata.calData = &adc_gain_cal_single_sample; - ah->ah_adcDcCalData.calData = + ah->adcdc_caldata.calData = &adc_dc_cal_single_sample; - ah->ah_adcDcCalInitData.calData = + ah->adcdc_calinitdata.calData = &adc_init_dc_cal; } else { - ah->ah_iqCalData.calData = &iq_cal_multi_sample; - ah->ah_adcGainCalData.calData = + ah->iq_caldata.calData = &iq_cal_multi_sample; + ah->adcgain_caldata.calData = &adc_gain_cal_multi_sample; - ah->ah_adcDcCalData.calData = + ah->adcdc_caldata.calData = &adc_dc_cal_multi_sample; - ah->ah_adcDcCalInitData.calData = + ah->adcdc_calinitdata.calData = &adc_init_dc_cal; } - ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; + ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; } if (AR_SREV_9160(ah)) { - ah->ah_config.enable_ani = 1; - ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | + ah->config.enable_ani = 1; + ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | ATH9K_ANI_FIRSTEP_LEVEL); } else { - ah->ah_ani_function = ATH9K_ANI_ALL; + ah->ani_function = ATH9K_ANI_ALL; if (AR_SREV_9280_10_OR_LATER(ah)) { - ah->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; + ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; } } @@ -676,137 +676,137 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ah->hw_version.macVersion, ah->hw_version.macRev); if (AR_SREV_9285_12_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2, + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, ARRAY_SIZE(ar9285Modes_9285_1_2), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2, + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, ARRAY_SIZE(ar9285Common_9285_1_2), 2); - if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + if (ah->config.pcie_clock_req) { + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 2); } } else if (AR_SREV_9285_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285, + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, ARRAY_SIZE(ar9285Modes_9285), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285, + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, ARRAY_SIZE(ar9285Common_9285), 2); - if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + if (ah->config.pcie_clock_req) { + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); } } else if (AR_SREV_9280_20_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2, + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, ARRAY_SIZE(ar9280Modes_9280_2), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2, + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, ARRAY_SIZE(ar9280Common_9280_2), 2); - if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + if (ah->config.pcie_clock_req) { + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9280PciePhy_clkreq_off_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); } else { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9280PciePhy_clkreq_always_on_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); } - INIT_INI_ARRAY(&ah->ah_iniModesAdditional, + INIT_INI_ARRAY(&ah->iniModesAdditional, ar9280Modes_fast_clock_9280_2, ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); } else if (AR_SREV_9280_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280, + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, ARRAY_SIZE(ar9280Modes_9280), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280, + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, ARRAY_SIZE(ar9280Common_9280), 2); } else if (AR_SREV_9160_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160, + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, ARRAY_SIZE(ar5416Modes_9160), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160, + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, ARRAY_SIZE(ar5416Common_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160, + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, ARRAY_SIZE(ar5416Bank0_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160, + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, ARRAY_SIZE(ar5416BB_RfGain_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160, + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, ARRAY_SIZE(ar5416Bank1_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160, + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, ARRAY_SIZE(ar5416Bank2_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160, + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, ARRAY_SIZE(ar5416Bank3_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160, + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, ARRAY_SIZE(ar5416Bank6_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160, + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, ARRAY_SIZE(ar5416Bank6TPC_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160, + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, ARRAY_SIZE(ar5416Bank7_9160), 2); if (AR_SREV_9160_11(ah)) { - INIT_INI_ARRAY(&ah->ah_iniAddac, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_91601_1, ARRAY_SIZE(ar5416Addac_91601_1), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, ARRAY_SIZE(ar5416Addac_9160), 2); } } else if (AR_SREV_9100_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100, + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, ARRAY_SIZE(ar5416Modes_9100), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100, + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, ARRAY_SIZE(ar5416Common_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100, + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, ARRAY_SIZE(ar5416Bank0_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100, + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, ARRAY_SIZE(ar5416BB_RfGain_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100, + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, ARRAY_SIZE(ar5416Bank1_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100, + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, ARRAY_SIZE(ar5416Bank2_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100, + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, ARRAY_SIZE(ar5416Bank3_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100, + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, ARRAY_SIZE(ar5416Bank6_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100, + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, ARRAY_SIZE(ar5416Bank6TPC_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100, + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, ARRAY_SIZE(ar5416Bank7_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, ARRAY_SIZE(ar5416Addac_9100), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes, + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, ARRAY_SIZE(ar5416Modes), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common, + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, ARRAY_SIZE(ar5416Common), 2); - INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0, + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, ARRAY_SIZE(ar5416Bank0), 2); - INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain, + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, ARRAY_SIZE(ar5416BB_RfGain), 3); - INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1, + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, ARRAY_SIZE(ar5416Bank1), 2); - INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2, + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, ARRAY_SIZE(ar5416Bank2), 2); - INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3, + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, ARRAY_SIZE(ar5416Bank3), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6, + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, ARRAY_SIZE(ar5416Bank6), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC, + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, ARRAY_SIZE(ar5416Bank6TPC), 3); - INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7, + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, ARRAY_SIZE(ar5416Bank7), 2); - INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, ARRAY_SIZE(ar5416Addac), 2); } - if (ah->ah_isPciExpress) + if (ah->is_pciexpress) ath9k_hw_configpcipowersave(ah, 0); else ath9k_hw_disablepcie(ah); @@ -824,15 +824,15 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ath9k_hw_init_txgain_ini(ah); if (ah->hw_version.devid == AR9280_DEVID_PCI) { - for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ah->ah_iniModes, i, 0); + for (i = 0; i < ah->iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->iniModes, i, 0); - for (j = 1; j < ah->ah_iniModes.ia_columns; j++) { - u32 val = INI_RA(&ah->ah_iniModes, i, j); + for (j = 1; j < ah->iniModes.ia_columns; j++) { + u32 val = INI_RA(&ah->iniModes, i, j); - INI_RA(&ah->ah_iniModes, i, j) = + INI_RA(&ah->iniModes, i, j) = ath9k_hw_ini_fixup(ah, - &ah->ah_eeprom.def, + &ah->eeprom.def, reg, val); } } @@ -853,9 +853,9 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } if (AR_SREV_9285(ah)) - ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); + ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); else - ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); + ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); ath9k_init_nfcal_hist_buffer(ah); @@ -974,8 +974,8 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah) { int rx_chainmask, tx_chainmask; - rx_chainmask = ah->ah_rxchainmask; - tx_chainmask = ah->ah_txchainmask; + rx_chainmask = ah->rxchainmask; + tx_chainmask = ah->txchainmask; switch (rx_chainmask) { case 0x5: @@ -1010,23 +1010,23 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah) static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, enum nl80211_iftype opmode) { - ah->ah_maskReg = AR_IMR_TXERR | + ah->mask_reg = AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | AR_IMR_RXORN | AR_IMR_BCNMISC; - if (ah->ah_intrMitigation) - ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; + if (ah->intr_mitigation) + ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; else - ah->ah_maskReg |= AR_IMR_RXOK; + ah->mask_reg |= AR_IMR_RXOK; - ah->ah_maskReg |= AR_IMR_TXOK; + ah->mask_reg |= AR_IMR_TXOK; if (opmode == NL80211_IFTYPE_AP) - ah->ah_maskReg |= AR_IMR_MIB; + ah->mask_reg |= AR_IMR_MIB; - REG_WRITE(ah, AR_IMR, ah->ah_maskReg); + REG_WRITE(ah, AR_IMR, ah->mask_reg); REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); if (!AR_SREV_9100(ah)) { @@ -1040,12 +1040,12 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) { if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); - ah->ah_acktimeout = (u32) -1; + ah->acktimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); - ah->ah_acktimeout = us; + ah->acktimeout = us; return true; } } @@ -1054,12 +1054,12 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) { if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); - ah->ah_ctstimeout = (u32) -1; + ah->ctstimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); - ah->ah_ctstimeout = us; + ah->ctstimeout = us; return true; } } @@ -1069,31 +1069,31 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) if (tu > 0xFFFF) { DPRINTF(ah->ah_sc, ATH_DBG_XMIT, "bad global tx timeout %u\n", tu); - ah->ah_globaltxtimeout = (u32) -1; + ah->globaltxtimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); - ah->ah_globaltxtimeout = tu; + ah->globaltxtimeout = tu; return true; } } static void ath9k_hw_init_user_settings(struct ath_hw *ah) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n", - ah->ah_miscMode); + DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", + ah->misc_mode); - if (ah->ah_miscMode != 0) + if (ah->misc_mode != 0) REG_WRITE(ah, AR_PCU_MISC, - REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode); - if (ah->ah_slottime != (u32) -1) - ath9k_hw_setslottime(ah, ah->ah_slottime); - if (ah->ah_acktimeout != (u32) -1) - ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout); - if (ah->ah_ctstimeout != (u32) -1) - ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout); - if (ah->ah_globaltxtimeout != (u32) -1) - ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout); + REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); + if (ah->slottime != (u32) -1) + ath9k_hw_setslottime(ah, ah->slottime); + if (ah->acktimeout != (u32) -1) + ath9k_hw_set_ack_timeout(ah, ah->acktimeout); + if (ah->ctstimeout != (u32) -1) + ath9k_hw_set_cts_timeout(ah, ah->ctstimeout); + if (ah->globaltxtimeout != (u32) -1) + ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); } const char *ath9k_hw_probe(u16 vendorid, u16 devid) @@ -1194,7 +1194,7 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value) { - if (ah->ah_eep_map == EEP_MAP_4KBITS) + if (ah->eep_map == EEP_MAP_4KBITS) return value; else return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); @@ -1241,34 +1241,34 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ah->eep_ops->set_addac(ah, chan); if (AR_SREV_5416_V22_OR_LATER(ah)) { - REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites); + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); } else { struct ar5416IniArray temp; u32 addacSize = - sizeof(u32) * ah->ah_iniAddac.ia_rows * - ah->ah_iniAddac.ia_columns; + sizeof(u32) * ah->iniAddac.ia_rows * + ah->iniAddac.ia_columns; - memcpy(ah->ah_addac5416_21, - ah->ah_iniAddac.ia_array, addacSize); + memcpy(ah->addac5416_21, + ah->iniAddac.ia_array, addacSize); - (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0; + (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; - temp.ia_array = ah->ah_addac5416_21; - temp.ia_columns = ah->ah_iniAddac.ia_columns; - temp.ia_rows = ah->ah_iniAddac.ia_rows; + temp.ia_array = ah->addac5416_21; + temp.ia_columns = ah->iniAddac.ia_columns; + temp.ia_rows = ah->iniAddac.ia_rows; REG_WRITE_ARRAY(&temp, 1, regWrites); } REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); - for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ah->ah_iniModes, i, 0); - u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex); + for (i = 0; i < ah->iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->iniModes, i, 0); + u32 val = INI_RA(&ah->iniModes, i, modesIndex); REG_WRITE(ah, reg, val); if (reg >= 0x7800 && reg < 0x78a0 - && ah->ah_config.analog_shiftreg) { + && ah->config.analog_shiftreg) { udelay(100); } @@ -1276,19 +1276,19 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, } if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); - for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) { - u32 reg = INI_RA(&ah->ah_iniCommon, i, 0); - u32 val = INI_RA(&ah->ah_iniCommon, i, 1); + for (i = 0; i < ah->iniCommon.ia_rows; i++) { + u32 reg = INI_RA(&ah->iniCommon, i, 0); + u32 val = INI_RA(&ah->iniCommon, i, 1); REG_WRITE(ah, reg, val); if (reg >= 0x7800 && reg < 0x78a0 - && ah->ah_config.analog_shiftreg) { + && ah->config.analog_shiftreg) { udelay(100); } @@ -1298,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { - REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex, + REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites); } @@ -1366,7 +1366,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah) regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); - REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); + REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); @@ -1566,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, (chan->chanmode == CHANNEL_G_HT40PLUS)) phymode |= AR_PHY_FC_DYN2040_PRI_CH; - if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) + if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25) phymode |= AR_PHY_FC_DYN2040_EXT_CH; } REG_WRITE(ah, AR_PHY_TURBO, phymode); @@ -1586,7 +1586,7 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah, if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) return false; - ah->ah_chipFullSleep = false; + ah->chip_fullsleep = false; ath9k_hw_init_pll(ah, chan); ath9k_hw_set_rfmode(ah, chan); @@ -1701,7 +1701,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel ath9k_hw_get_channel_centers(ah, chan, ¢ers); freq = centers.synth_center; - ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; + ah->config.spurmode = SPUR_ENABLE_EEPROM; for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); @@ -2123,21 +2123,21 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, { u32 saveLedState; struct ath_softc *sc = ah->ah_sc; - struct ath9k_channel *curchan = ah->ah_curchan; + struct ath9k_channel *curchan = ah->curchan; u32 saveDefAntenna; u32 macStaId1; int i, rx_chainmask, r; - ah->ah_extprotspacing = sc->ht_extprotspacing; - ah->ah_txchainmask = sc->tx_chainmask; - ah->ah_rxchainmask = sc->rx_chainmask; + ah->extprotspacing = sc->ht_extprotspacing; + ah->txchainmask = sc->tx_chainmask; + ah->rxchainmask = sc->rx_chainmask; if (AR_SREV_9285(ah)) { - ah->ah_txchainmask &= 0x1; - ah->ah_rxchainmask &= 0x1; + ah->txchainmask &= 0x1; + ah->rxchainmask &= 0x1; } else if (AR_SREV_9280(ah)) { - ah->ah_txchainmask &= 0x3; - ah->ah_rxchainmask &= 0x3; + ah->txchainmask &= 0x3; + ah->rxchainmask &= 0x3; } if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) @@ -2147,16 +2147,16 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ath9k_hw_getnf(ah, curchan); if (bChannelChange && - (ah->ah_chipFullSleep != true) && - (ah->ah_curchan != NULL) && - (chan->channel != ah->ah_curchan->channel) && + (ah->chip_fullsleep != true) && + (ah->curchan != NULL) && + (chan->channel != ah->curchan->channel) && ((chan->channelFlags & CHANNEL_ALL) == - (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && + (ah->curchan->channelFlags & CHANNEL_ALL)) && (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && - !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) { + !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) { if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { - ath9k_hw_loadnf(ah, ah->ah_curchan); + ath9k_hw_loadnf(ah, ah->curchan); ath9k_hw_start_nfcal(ah); return 0; } @@ -2223,10 +2223,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4) | macStaId1 | AR_STA_ID1_RTS_USE_DEF - | (ah->ah_config. + | (ah->config. ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) - | ah->ah_staId1Defaults); - ath9k_hw_set_operating_mode(ah, ah->ah_opmode); + | ah->sta_id1_defaults); + ath9k_hw_set_operating_mode(ah, ah->opmode); REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); @@ -2252,15 +2252,15 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, for (i = 0; i < AR_NUM_DCU; i++) REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); - ah->ah_intrTxqs = 0; - for (i = 0; i < ah->ah_caps.total_queues; i++) + ah->intr_txqs = 0; + for (i = 0; i < ah->caps.total_queues; i++) ath9k_hw_resettxqueue(ah, i); - ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); + ath9k_hw_init_interrupt_masks(ah, ah->opmode); ath9k_hw_init_qos(ah); #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) ath9k_enable_rfkill(ah); #endif ath9k_hw_init_user_settings(ah); @@ -2272,7 +2272,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_OBS, 8); - if (ah->ah_intrMitigation) { + if (ah->intr_mitigation) { REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); @@ -2283,7 +2283,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, if (!ath9k_hw_init_cal(ah, chan)) return -EIO;; - rx_chainmask = ah->ah_rxchainmask; + rx_chainmask = ah->rxchainmask; if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); @@ -2321,7 +2321,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) { u32 keyType; - if (entry >= ah->ah_caps.keycache_size) { + if (entry >= ah->caps.keycache_size) { DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, "entry %u out of range\n", entry); return false; @@ -2348,7 +2348,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) } - if (ah->ah_curchan == NULL) + if (ah->curchan == NULL) return true; return true; @@ -2358,7 +2358,7 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) { u32 macHi, macLo; - if (entry >= ah->ah_caps.keycache_size) { + if (entry >= ah->caps.keycache_size) { DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, "entry %u out of range\n", entry); return false; @@ -2386,7 +2386,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, const struct ath9k_keyval *k, const u8 *mac, int xorKey) { - const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + const struct ath9k_hw_capabilities *pCap = &ah->caps; u32 key0, key1, key2, key3, key4; u32 keyType; u32 xorMask = xorKey ? @@ -2462,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); (void) ath9k_hw_keysetmac(ah, entry, mac); - if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { + if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { u32 mic0, mic1, mic2, mic3, mic4; mic0 = get_unaligned_le32(k->kv_mic + 0); @@ -2506,7 +2506,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, (void) ath9k_hw_keysetmac(ah, entry, mac); } - if (ah->ah_curchan == NULL) + if (ah->curchan == NULL) return true; return true; @@ -2514,7 +2514,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) { - if (entry < ah->ah_caps.keycache_size) { + if (entry < ah->caps.keycache_size) { u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); if (val & AR_KEYTABLE_VALID) return true; @@ -2544,7 +2544,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { REG_WRITE(ah, AR_RTC_FORCE_WAKE, @@ -2608,7 +2608,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) }; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", - modes[ah->ah_power_mode], modes[mode], + modes[ah->power_mode], modes[mode], setChip ? "set chip " : ""); switch (mode) { @@ -2617,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) break; case ATH9K_PM_FULL_SLEEP: ath9k_set_power_sleep(ah, setChip); - ah->ah_chipFullSleep = true; + ah->chip_fullsleep = true; break; case ATH9K_PM_NETWORK_SLEEP: ath9k_set_power_network_sleep(ah, setChip); @@ -2627,7 +2627,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) "Unknown power mode %u\n", mode); return false; } - ah->ah_power_mode = mode; + ah->power_mode = mode; return status; } @@ -2636,19 +2636,19 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) { u8 i; - if (ah->ah_isPciExpress != true) + if (ah->is_pciexpress != true) return; - if (ah->ah_config.pcie_powersave_enable == 2) + if (ah->config.pcie_powersave_enable == 2) return; if (restore) return; if (AR_SREV_9280_20_OR_LATER(ah)) { - for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) { - REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0), - INI_RA(&ah->ah_iniPcieSerdes, i, 1)); + for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { + REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), + INI_RA(&ah->iniPcieSerdes, i, 1)); } udelay(1000); } else if (AR_SREV_9280(ah) && @@ -2660,7 +2660,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); - if (ah->ah_config.pcie_clock_req) + if (ah->config.pcie_clock_req) REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); else REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); @@ -2687,8 +2687,8 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); - if (ah->ah_config.pcie_waen) { - REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); + if (ah->config.pcie_waen) { + REG_WRITE(ah, AR_WA, ah->config.pcie_waen); } else { if (AR_SREV_9285(ah)) REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); @@ -2726,7 +2726,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) { u32 isr = 0; u32 mask2 = 0; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; u32 sync_cause = 0; bool fatal_int = false; @@ -2776,7 +2776,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) *masked = isr & ATH9K_INT_COMMON; - if (ah->ah_intrMitigation) { + if (ah->intr_mitigation) { if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) *masked |= ATH9K_INT_RX; } @@ -2791,12 +2791,12 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) *masked |= ATH9K_INT_TX; s0_s = REG_READ(ah, AR_ISR_S0_S); - ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); - ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); s1_s = REG_READ(ah, AR_ISR_S1_S); - ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); - ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); } if (isr & AR_ISR_RXORN) { @@ -2855,14 +2855,14 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah) { - return ah->ah_maskReg; + return ah->mask_reg; } enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) { - u32 omask = ah->ah_maskReg; + u32 omask = ah->mask_reg; u32 mask, mask2; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); @@ -2883,18 +2883,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) mask2 = 0; if (ints & ATH9K_INT_TX) { - if (ah->ah_txOkInterruptMask) + if (ah->txok_interrupt_mask) mask |= AR_IMR_TXOK; - if (ah->ah_txDescInterruptMask) + if (ah->txdesc_interrupt_mask) mask |= AR_IMR_TXDESC; - if (ah->ah_txErrInterruptMask) + if (ah->txerr_interrupt_mask) mask |= AR_IMR_TXERR; - if (ah->ah_txEolInterruptMask) + if (ah->txeol_interrupt_mask) mask |= AR_IMR_TXEOL; } if (ints & ATH9K_INT_RX) { mask |= AR_IMR_RXERR; - if (ah->ah_intrMitigation) + if (ah->intr_mitigation) mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; else mask |= AR_IMR_RXOK | AR_IMR_RXDESC; @@ -2932,7 +2932,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); REG_WRITE(ah, AR_IMR_S2, mask | mask2); - ah->ah_maskReg = ints; + ah->mask_reg = ints; if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { if (ints & ATH9K_INT_TIM_TIMER) @@ -2970,9 +2970,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) { int flags = 0; - ah->ah_beaconInterval = beacon_period; + ah->beacon_interval = beacon_period; - switch (ah->ah_opmode) { + switch (ah->opmode) { case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_MONITOR: REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); @@ -2985,18 +2985,18 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); REG_WRITE(ah, AR_NEXT_NDP_TIMER, TU_TO_USEC(next_beacon + - (ah->ah_atimWindow ? ah-> - ah_atimWindow : 1))); + (ah->atim_window ? ah-> + atim_window : 1))); flags |= AR_NDP_TIMER_EN; case NL80211_IFTYPE_AP: REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, TU_TO_USEC(next_beacon - - ah->ah_config. + ah->config. dma_beacon_response_time)); REG_WRITE(ah, AR_NEXT_SWBA, TU_TO_USEC(next_beacon - - ah->ah_config. + ah->config. sw_beacon_response_time)); flags |= AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; @@ -3004,7 +3004,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) default: DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: unsupported opmode: %d\n", - __func__, ah->ah_opmode); + __func__, ah->opmode); return; break; } @@ -3027,7 +3027,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs) { u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); @@ -3089,7 +3089,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, bool ath9k_hw_fill_cap_info(struct ath_hw *ah) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; u16 capField = 0, eeval; eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); @@ -3101,7 +3101,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); - if (ah->ah_opmode != NL80211_IFTYPE_AP && + if (ah->opmode != NL80211_IFTYPE_AP && ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { if (ah->regulatory.current_rd == 0x64 || ah->regulatory.current_rd == 0x65) @@ -3117,7 +3117,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) if (eeval & AR5416_OPFLAGS_11A) { set_bit(ATH9K_MODE_11A, pCap->wireless_modes); - if (ah->ah_config.ht_enable) { + if (ah->config.ht_enable) { if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) set_bit(ATH9K_MODE_11NA_HT20, pCap->wireless_modes); @@ -3133,7 +3133,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) if (eeval & AR5416_OPFLAGS_11G) { set_bit(ATH9K_MODE_11B, pCap->wireless_modes); set_bit(ATH9K_MODE_11G, pCap->wireless_modes); - if (ah->ah_config.ht_enable) { + if (ah->config.ht_enable) { if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) set_bit(ATH9K_MODE_11NG_HT20, pCap->wireless_modes); @@ -3147,7 +3147,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) } pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); - if ((ah->ah_isPciExpress) + if ((ah->is_pciexpress) || (eeval & AR5416_OPFLAGS_11A)) { pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); @@ -3157,7 +3157,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) } if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) - ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; + ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; pCap->low_2ghz_chan = 2312; pCap->high_2ghz_chan = 2732; @@ -3175,7 +3175,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; - if (ah->ah_config.ht_enable) + if (ah->config.ht_enable) pCap->hw_caps |= ATH9K_HW_CAP_HT; else pCap->hw_caps &= ~ATH9K_HW_CAP_HT; @@ -3226,12 +3226,12 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - ah->ah_rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); - if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { - ah->ah_rfkill_gpio = - MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); - ah->ah_rfkill_polarity = - MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); + ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); + if (ah->rfsilent & EEP_RFSILENT_ENABLED) { + ah->rfkill_gpio = + MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); + ah->rfkill_polarity = + MS(ah->rfsilent, EEP_RFSILENT_POLARITY); pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; } @@ -3272,8 +3272,8 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) { pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; - ah->ah_btactive_gpio = 6; - ah->ah_wlanactive_gpio = 5; + ah->btactive_gpio = 6; + ah->wlanactive_gpio = 5; } return true; @@ -3282,7 +3282,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 *result) { - const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + const struct ath9k_hw_capabilities *pCap = &ah->caps; switch (type) { case ATH9K_CAP_CIPHER: @@ -3302,17 +3302,17 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, case 0: return true; case 1: - return (ah->ah_staId1Defaults & + return (ah->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE) ? true : false; } case ATH9K_CAP_TKIP_SPLIT: - return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? + return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? false : true; case ATH9K_CAP_WME_TKIPMIC: return 0; case ATH9K_CAP_PHYCOUNTERS: - return ah->ah_hasHwPhyCounters ? 0 : -ENXIO; + return ah->has_hw_phycounters ? 0 : -ENXIO; case ATH9K_CAP_DIVERSITY: return (REG_READ(ah, AR_PHY_CCK_DETECT) & AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? @@ -3327,14 +3327,14 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { return false; } else { - return (ah->ah_staId1Defaults & + return (ah->sta_id1_defaults & AR_STA_ID1_MCAST_KSRCH) ? true : false; } } return false; case ATH9K_CAP_TSF_ADJUST: - return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ? + return (ah->misc_mode & AR_PCU_TX_ADD_TSF) ? true : false; case ATH9K_CAP_RFSILENT: if (capability == 3) @@ -3373,10 +3373,10 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, switch (type) { case ATH9K_CAP_TKIP_MIC: if (setting) - ah->ah_staId1Defaults |= + ah->sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; else - ah->ah_staId1Defaults &= + ah->sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; return true; case ATH9K_CAP_DIVERSITY: @@ -3389,15 +3389,15 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, return true; case ATH9K_CAP_MCAST_KEYSRCH: if (setting) - ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; + ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; else - ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; + ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; return true; case ATH9K_CAP_TSF_ADJUST: if (setting) - ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->misc_mode |= AR_PCU_TX_ADD_TSF; else - ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; return true; default: return false; @@ -3440,7 +3440,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) { u32 gpio_shift; - ASSERT(gpio < ah->ah_caps.num_gpio_pins); + ASSERT(gpio < ah->caps.num_gpio_pins); gpio_shift = gpio << 1; @@ -3455,7 +3455,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) #define MS_REG_READ(x, y) \ (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) - if (gpio >= ah->ah_caps.num_gpio_pins) + if (gpio >= ah->caps.num_gpio_pins) return 0xffffffff; if (AR_SREV_9285_10_OR_LATER(ah)) @@ -3496,7 +3496,7 @@ void ath9k_enable_rfkill(struct ath_hw *ah) REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, AR_GPIO_INPUT_MUX2_RFSILENT); - ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); } #endif @@ -3534,7 +3534,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hw *ah, *antenna_cfgd = true; break; case ATH9K_ANT_FIXED_B: - if (ah->ah_caps.tx_chainmask > + if (ah->caps.tx_chainmask > ATH9K_ANTENNA1_CHAINMASK) { *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; } @@ -3550,7 +3550,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hw *ah, break; } } else { - ah->ah_diversityControl = settings; + ah->diversity_control = settings; } return true; @@ -3608,7 +3608,7 @@ bool ath9k_hw_disable(struct ath_hw *ah) bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) { - struct ath9k_channel *chan = ah->ah_curchan; + struct ath9k_channel *chan = ah->curchan; struct ieee80211_channel *channel = chan->chan; ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); @@ -3631,7 +3631,7 @@ void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) void ath9k_hw_setopmode(struct ath_hw *ah) { - ath9k_hw_set_operating_mode(ah, ah->ah_opmode); + ath9k_hw_set_operating_mode(ah, ah->opmode); } void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) @@ -3690,9 +3690,9 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah) bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) { if (setting) - ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->misc_mode |= AR_PCU_TX_ADD_TSF; else - ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; return true; } @@ -3701,11 +3701,11 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) { if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); - ah->ah_slottime = (u32) -1; + ah->slottime = (u32) -1; return false; } else { REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); - ah->ah_slottime = us; + ah->slottime = us; return true; } } @@ -3715,7 +3715,7 @@ void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) u32 macmode; if (mode == ATH9K_HT_MACMODE_2040 && - !ah->ah_config.cwm_ignore_extcca) + !ah->config.cwm_ignore_extcca) macmode = AR_2040_JOINED_RX_CLEAR; else macmode = 0; @@ -3740,12 +3740,12 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah) /* Set input mux for bt_active to gpio pin */ REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, AR_GPIO_INPUT_MUX1_BT_ACTIVE, - ah->ah_btactive_gpio); + ah->btactive_gpio); /* Configure the desired gpio port for input */ - ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio); + ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio); /* Configure the desired GPIO port for TX_FRAME output */ - ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio, + ath9k_hw_cfg_output(ah, ah->wlanactive_gpio, AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); } diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index f8f46db..8211163 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -420,152 +420,148 @@ struct ath9k_hw_version { struct ath_hw { struct ath_softc *ah_sc; struct ath9k_hw_version hw_version; - struct ath9k_ops_config ah_config; - struct ath9k_hw_capabilities ah_caps; + struct ath9k_ops_config config; + struct ath9k_hw_capabilities caps; struct ath9k_regulatory regulatory; - struct ath9k_channel ah_channels[38]; - struct ath9k_channel *ah_curchan; + struct ath9k_channel channels[38]; + struct ath9k_channel *curchan; union { struct ar5416_eeprom_def def; struct ar5416_eeprom_4k map4k; - } ah_eeprom; + } eeprom; const struct eeprom_ops *eep_ops; + enum ath9k_eep_map eep_map; bool sw_mgmt_crypto; - bool ah_isPciExpress; + bool is_pciexpress; u8 macaddr[ETH_ALEN]; - u16 ah_txTrigLevel; - u16 ah_rfsilent; - u32 ah_rfkill_gpio; - u32 ah_rfkill_polarity; - u32 ah_btactive_gpio; - u32 ah_wlanactive_gpio; + u16 tx_trig_level; + u16 rfsilent; + u32 rfkill_gpio; + u32 rfkill_polarity; + u32 btactive_gpio; + u32 wlanactive_gpio; u32 ah_flags; - enum nl80211_iftype ah_opmode; - enum ath9k_power_mode ah_power_mode; - enum ath9k_power_mode ah_restore_mode; + enum nl80211_iftype opmode; + enum ath9k_power_mode power_mode; + enum ath9k_power_mode restore_mode; struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; - struct ar5416Stats ah_stats; - struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; - - int16_t ah_curchanRadIndex; - u32 ah_maskReg; - u32 ah_txOkInterruptMask; - u32 ah_txErrInterruptMask; - u32 ah_txDescInterruptMask; - u32 ah_txEolInterruptMask; - u32 ah_txUrnInterruptMask; - bool ah_chipFullSleep; - u32 ah_atimWindow; - u16 ah_antennaSwitchSwap; - enum ath9k_ant_setting ah_diversityControl; + struct ar5416Stats stats; + struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; + + int16_t curchan_rad_index; + u32 mask_reg; + u32 txok_interrupt_mask; + u32 txerr_interrupt_mask; + u32 txdesc_interrupt_mask; + u32 txeol_interrupt_mask; + u32 txurn_interrupt_mask; + bool chip_fullsleep; + u32 atim_window; + u16 antenna_switch_swap; + enum ath9k_ant_setting diversity_control; /* Calibration */ - enum hal_cal_types ah_suppCals; - struct hal_cal_list ah_iqCalData; - struct hal_cal_list ah_adcGainCalData; - struct hal_cal_list ah_adcDcCalInitData; - struct hal_cal_list ah_adcDcCalData; - struct hal_cal_list *ah_cal_list; - struct hal_cal_list *ah_cal_list_last; - struct hal_cal_list *ah_cal_list_curr; -#define ah_totalPowerMeasI ah_Meas0.unsign -#define ah_totalPowerMeasQ ah_Meas1.unsign -#define ah_totalIqCorrMeas ah_Meas2.sign -#define ah_totalAdcIOddPhase ah_Meas0.unsign -#define ah_totalAdcIEvenPhase ah_Meas1.unsign -#define ah_totalAdcQOddPhase ah_Meas2.unsign -#define ah_totalAdcQEvenPhase ah_Meas3.unsign -#define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign -#define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign -#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign -#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign + enum hal_cal_types supp_cals; + struct hal_cal_list iq_caldata; + struct hal_cal_list adcgain_caldata; + struct hal_cal_list adcdc_calinitdata; + struct hal_cal_list adcdc_caldata; + struct hal_cal_list *cal_list; + struct hal_cal_list *cal_list_last; + struct hal_cal_list *cal_list_curr; +#define totalPowerMeasI meas0.unsign +#define totalPowerMeasQ meas1.unsign +#define totalIqCorrMeas meas2.sign +#define totalAdcIOddPhase meas0.unsign +#define totalAdcIEvenPhase meas1.unsign +#define totalAdcQOddPhase meas2.unsign +#define totalAdcQEvenPhase meas3.unsign +#define totalAdcDcOffsetIOddPhase meas0.sign +#define totalAdcDcOffsetIEvenPhase meas1.sign +#define totalAdcDcOffsetQOddPhase meas2.sign +#define totalAdcDcOffsetQEvenPhase meas3.sign union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas0; + } meas0; union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas1; + } meas1; union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas2; + } meas2; union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas3; - u16 ah_CalSamples; + } meas3; + u16 cal_samples; - u32 ah_staId1Defaults; - u32 ah_miscMode; + u32 sta_id1_defaults; + u32 misc_mode; enum { AUTO_32KHZ, USE_32KHZ, DONT_USE_32KHZ, - } ah_enable32kHzClock; + } enable_32kHz_clock; /* RF */ - u32 *ah_analogBank0Data; - u32 *ah_analogBank1Data; - u32 *ah_analogBank2Data; - u32 *ah_analogBank3Data; - u32 *ah_analogBank6Data; - u32 *ah_analogBank6TPCData; - u32 *ah_analogBank7Data; - u32 *ah_addac5416_21; - u32 *ah_bank6Temp; - - int16_t ah_txPowerIndexOffset; - u32 ah_beaconInterval; - u32 ah_slottime; - u32 ah_acktimeout; - u32 ah_ctstimeout; - u32 ah_globaltxtimeout; - u8 ah_gBeaconRate; - u32 ah_gpioSelect; - u32 ah_polarity; - u32 ah_gpioBit; + u32 *analogBank0Data; + u32 *analogBank1Data; + u32 *analogBank2Data; + u32 *analogBank3Data; + u32 *analogBank6Data; + u32 *analogBank6TPCData; + u32 *analogBank7Data; + u32 *addac5416_21; + u32 *bank6Temp; + + int16_t txpower_indexoffset; + u32 beacon_interval; + u32 slottime; + u32 acktimeout; + u32 ctstimeout; + u32 globaltxtimeout; + u8 gbeacon_rate; /* ANI */ - u32 ah_procPhyErr; - bool ah_hasHwPhyCounters; - u32 ah_aniPeriod; - struct ar5416AniState *ah_curani; - struct ar5416AniState ah_ani[255]; - int ah_totalSizeDesired[5]; - int ah_coarseHigh[5]; - int ah_coarseLow[5]; - int ah_firpwr[5]; - enum ath9k_ani_cmd ah_ani_function; - - u32 ah_intrTxqs; - bool ah_intrMitigation; - enum ath9k_ht_extprotspacing ah_extprotspacing; - u8 ah_txchainmask; - u8 ah_rxchainmask; - - struct ar5416IniArray ah_iniModes; - struct ar5416IniArray ah_iniCommon; - struct ar5416IniArray ah_iniBank0; - struct ar5416IniArray ah_iniBB_RfGain; - struct ar5416IniArray ah_iniBank1; - struct ar5416IniArray ah_iniBank2; - struct ar5416IniArray ah_iniBank3; - struct ar5416IniArray ah_iniBank6; - struct ar5416IniArray ah_iniBank6TPC; - struct ar5416IniArray ah_iniBank7; - struct ar5416IniArray ah_iniAddac; - struct ar5416IniArray ah_iniPcieSerdes; - struct ar5416IniArray ah_iniModesAdditional; - struct ar5416IniArray ah_iniModesRxGain; - struct ar5416IniArray ah_iniModesTxGain; - /* To indicate EEPROM mapping used */ - enum hal_eep_map ah_eep_map; + u32 proc_phyerr; + bool has_hw_phycounters; + u32 aniperiod; + struct ar5416AniState *curani; + struct ar5416AniState ani[255]; + int totalSizeDesired[5]; + int coarse_high[5]; + int coarse_low[5]; + int firpwr[5]; + enum ath9k_ani_cmd ani_function; + + u32 intr_txqs; + bool intr_mitigation; + enum ath9k_ht_extprotspacing extprotspacing; + u8 txchainmask; + u8 rxchainmask; + + struct ar5416IniArray iniModes; + struct ar5416IniArray iniCommon; + struct ar5416IniArray iniBank0; + struct ar5416IniArray iniBB_RfGain; + struct ar5416IniArray iniBank1; + struct ar5416IniArray iniBank2; + struct ar5416IniArray iniBank3; + struct ar5416IniArray iniBank6; + struct ar5416IniArray iniBank6TPC; + struct ar5416IniArray iniBank7; + struct ar5416IniArray iniAddac; + struct ar5416IniArray iniPcieSerdes; + struct ar5416IniArray iniModesAdditional; + struct ar5416IniArray iniModesRxGain; + struct ar5416IniArray iniModesTxGain; }; /* Attach, Detach, Reset */ diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index ac20714..f32c622 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c @@ -21,18 +21,18 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, { DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", - ah->ah_txOkInterruptMask, ah->ah_txErrInterruptMask, - ah->ah_txDescInterruptMask, ah->ah_txEolInterruptMask, - ah->ah_txUrnInterruptMask); + ah->txok_interrupt_mask, ah->txerr_interrupt_mask, + ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, + ah->txurn_interrupt_mask); REG_WRITE(ah, AR_IMR_S0, - SM(ah->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) - | SM(ah->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); + SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) + | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); REG_WRITE(ah, AR_IMR_S1, - SM(ah->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) - | SM(ah->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); + SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) + | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); REG_RMW_FIELD(ah, AR_IMR_S2, - AR_IMR_S2_QCU_TXURN, ah->ah_txUrnInterruptMask); + AR_IMR_S2_QCU_TXURN, ah->txurn_interrupt_mask); } u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) @@ -75,10 +75,10 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) u32 txcfg, curLevel, newLevel; enum ath9k_int omask; - if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) + if (ah->tx_trig_level >= MAX_TX_FIFO_THRESHOLD) return false; - omask = ath9k_hw_set_interrupts(ah, ah->ah_maskReg & ~ATH9K_INT_GLOBAL); + omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL); txcfg = REG_READ(ah, AR_TXCFG); curLevel = MS(txcfg, AR_FTRIG); @@ -94,7 +94,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) ath9k_hw_set_interrupts(ah, omask); - ah->ah_txTrigLevel = newLevel; + ah->tx_trig_level = newLevel; return newLevel != curLevel; } @@ -104,7 +104,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ #define ATH9K_TIME_QUANTUM 100 /* usec */ - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; u32 tsfLow, j, wait; u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; @@ -114,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -296,7 +296,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, { struct ar5416_desc *ads = AR5416DESC(ds); - txPower += ah->ah_txPowerIndexOffset; + txPower += ah->txpower_indexoffset; if (txPower > 63) txPower = 63; @@ -442,15 +442,15 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs) { - *txqs &= ah->ah_intrTxqs; - ah->ah_intrTxqs &= ~(*txqs); + *txqs &= ah->intr_txqs; + ah->intr_txqs &= ~(*txqs); } bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo) { u32 cw; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; if (q >= pCap->total_queues) { @@ -458,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -517,7 +517,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; if (q >= pCap->total_queues) { @@ -525,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -553,7 +553,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo) { struct ath9k_tx_queue_info *qi; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; int q; switch (type) { @@ -571,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, break; case ATH9K_TX_QUEUE_DATA: for (q = 0; q < pCap->total_queues; q++) - if (ah->ah_txq[q].tqi_type == + if (ah->txq[q].tqi_type == ATH9K_TX_QUEUE_INACTIVE) break; if (q == pCap->total_queues) { @@ -587,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "tx queue %u already active\n", q); @@ -616,14 +616,14 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; if (q >= pCap->total_queues) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return false; @@ -632,11 +632,11 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; - ah->ah_txOkInterruptMask &= ~(1 << q); - ah->ah_txErrInterruptMask &= ~(1 << q); - ah->ah_txDescInterruptMask &= ~(1 << q); - ah->ah_txEolInterruptMask &= ~(1 << q); - ah->ah_txUrnInterruptMask &= ~(1 << q); + ah->txok_interrupt_mask &= ~(1 << q); + ah->txerr_interrupt_mask &= ~(1 << q); + ah->txdesc_interrupt_mask &= ~(1 << q); + ah->txeol_interrupt_mask &= ~(1 << q); + ah->txurn_interrupt_mask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; @@ -644,8 +644,8 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; - struct ath9k_channel *chan = ah->ah_curchan; + struct ath9k_hw_capabilities *pCap = &ah->caps; + struct ath9k_channel *chan = ah->curchan; struct ath9k_tx_queue_info *qi; u32 cwMin, chanCwMin, value; @@ -654,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return true; @@ -742,9 +742,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) | AR_Q_MISC_CBR_INCR_DIS1 | AR_Q_MISC_CBR_INCR_DIS0); value = (qi->tqi_readyTime - - (ah->ah_config.sw_beacon_response_time - - ah->ah_config.dma_beacon_response_time) - - ah->ah_config.additional_swba_backoff) * 1024; + (ah->config.sw_beacon_response_time - + ah->config.dma_beacon_response_time) - + ah->config.additional_swba_backoff) * 1024; REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN); REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) @@ -772,25 +772,25 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) } if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) - ah->ah_txOkInterruptMask |= 1 << q; + ah->txok_interrupt_mask |= 1 << q; else - ah->ah_txOkInterruptMask &= ~(1 << q); + ah->txok_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) - ah->ah_txErrInterruptMask |= 1 << q; + ah->txerr_interrupt_mask |= 1 << q; else - ah->ah_txErrInterruptMask &= ~(1 << q); + ah->txerr_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) - ah->ah_txDescInterruptMask |= 1 << q; + ah->txdesc_interrupt_mask |= 1 << q; else - ah->ah_txDescInterruptMask &= ~(1 << q); + ah->txdesc_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) - ah->ah_txEolInterruptMask |= 1 << q; + ah->txeol_interrupt_mask |= 1 << q; else - ah->ah_txEolInterruptMask &= ~(1 << q); + ah->txeol_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) - ah->ah_txUrnInterruptMask |= 1 << q; + ah->txurn_interrupt_mask |= 1 << q; else - ah->ah_txUrnInterruptMask &= ~(1 << q); + ah->txurn_interrupt_mask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; @@ -865,7 +865,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags) { struct ar5416_desc *ads = AR5416DESC(ds); - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; ads->ds_ctl1 = size & AR_BufLen; if (flags & ATH9K_RXDESC_INTREQ) diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index a50f989..fc3460f 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -267,7 +267,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) DPRINTF(sc, ATH_DBG_CONFIG, "(%u MHz) -> (%u MHz), chanwidth: %d\n", - sc->sc_ah->ah_curchan->channel, + sc->sc_ah->curchan->channel, channel->center_freq, sc->tx_chan_width); spin_lock_bh(&sc->sc_resetlock); @@ -363,30 +363,30 @@ static void ath_ani_calibrate(unsigned long data) /* Call ANI routine if necessary */ if (aniflag) ath9k_hw_ani_monitor(ah, &sc->nodestats, - ah->ah_curchan); + ah->curchan); /* Perform calibration if necessary */ if (longcal || shortcal) { bool iscaldone = false; - if (ath9k_hw_calibrate(ah, ah->ah_curchan, + if (ath9k_hw_calibrate(ah, ah->curchan, sc->rx_chainmask, longcal, &iscaldone)) { if (longcal) sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, - ah->ah_curchan); + ah->curchan); DPRINTF(sc, ATH_DBG_ANI, "calibrate chan %u/%x nf: %d\n", - ah->ah_curchan->channel, - ah->ah_curchan->channelFlags, + ah->curchan->channel, + ah->curchan->channelFlags, sc->ani.noise_floor); } else { DPRINTF(sc, ATH_DBG_ANY, "calibrate chan %u/%x failed\n", - ah->ah_curchan->channel, - ah->ah_curchan->channelFlags); + ah->curchan->channel, + ah->curchan->channelFlags); } sc->ani.caldone = iscaldone; } @@ -398,7 +398,7 @@ static void ath_ani_calibrate(unsigned long data) * short calibration and long calibration. */ cal_interval = ATH_LONG_CALINTERVAL; - if (sc->sc_ah->ah_config.enable_ani) + if (sc->sc_ah->config.enable_ani) cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); if (!sc->ani.caldone) cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL); @@ -416,9 +416,9 @@ static void ath_update_chainmask(struct ath_softc *sc, int is_ht) { sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; if (is_ht || - (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { - sc->tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; - sc->rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; + (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { + sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; + sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask; } else { sc->tx_chainmask = 1; sc->rx_chainmask = 1; @@ -564,7 +564,7 @@ irqreturn_t ath_isr(int irq, void *dev) ath9k_hw_set_interrupts(ah, sc->imask); } if (status & ATH9K_INT_TIM_TIMER) { - if (!(ah->ah_caps.hw_caps & + if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { /* Clear RxAbort bit so that we can * receive frames */ @@ -1098,7 +1098,7 @@ static void ath_radio_enable(struct ath_softc *sc) ath9k_ps_wakeup(sc); spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, ah->ah_curchan, false); + r = ath9k_hw_reset(ah, ah->curchan, false); if (r) { DPRINTF(sc, ATH_DBG_FATAL, @@ -1151,7 +1151,7 @@ static void ath_radio_disable(struct ath_softc *sc) ath_flushrecv(sc); /* flush recv queue */ spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, ah->ah_curchan, false); + r = ath9k_hw_reset(ah, ah->curchan, false); if (r) { DPRINTF(sc, ATH_DBG_FATAL, "Unable to reset channel %u (%uMhz) " @@ -1169,8 +1169,8 @@ static bool ath_is_rfkill_set(struct ath_softc *sc) { struct ath_hw *ah = sc->sc_ah; - return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == - ah->ah_rfkill_polarity; + return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) == + ah->rfkill_polarity; } /* h/w rfkill poll function */ @@ -1267,7 +1267,7 @@ static int ath_init_sw_rfkill(struct ath_softc *sc) /* Deinitialize rfkill */ static void ath_deinit_rfkill(struct ath_softc *sc) { - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) { @@ -1279,7 +1279,7 @@ static void ath_deinit_rfkill(struct ath_softc *sc) static int ath_start_rfkill_poll(struct ath_softc *sc) { - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll, 0); @@ -1380,7 +1380,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->sc_ah = ah; /* Get the hardware key cache size. */ - sc->keymax = ah->ah_caps.keycache_size; + sc->keymax = ah->caps.keycache_size; if (sc->keymax > ATH_KEYMAX) { DPRINTF(sc, ATH_DBG_KEYCACHE, "Warning, using only %u entries in %u key cache\n", @@ -1399,7 +1399,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) goto bad; /* default to MONITOR mode */ - sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR; + sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; /* Setup rate tables */ @@ -1502,18 +1502,18 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->config.txpowlimit = ATH_TXPOWER_MAX; /* 11n Capabilities */ - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { + if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) { sc->sc_flags |= SC_OP_TXAGGR; sc->sc_flags |= SC_OP_RXAGGR; } - sc->tx_chainmask = ah->ah_caps.tx_chainmask; - sc->rx_chainmask = ah->ah_caps.rx_chainmask; + sc->tx_chainmask = ah->caps.tx_chainmask; + sc->rx_chainmask = ah->caps.rx_chainmask; ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); sc->rx.defant = ath9k_hw_getdefantenna(ah); - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { + if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); ATH_SET_VIF_BSSID_MASK(sc->bssidmask); ath9k_hw_setbssidmask(sc); @@ -1537,7 +1537,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->sbands[IEEE80211_BAND_2GHZ].n_channels = ARRAY_SIZE(ath9k_2ghz_chantable); - if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) { + if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) { sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; sc->sbands[IEEE80211_BAND_5GHZ].bitrates = sc->rates[IEEE80211_BAND_5GHZ]; @@ -1546,7 +1546,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) ARRAY_SIZE(ath9k_5ghz_chantable); } - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX) ath9k_hw_btcoex_enable(sc->sc_ah); return 0; @@ -1603,14 +1603,14 @@ int ath_attach(u16 devid, struct ath_softc *sc) hw->rate_control_algorithm = "ath9k_rate_control"; - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); - if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) + if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); } hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ]; - if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) + if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &sc->sbands[IEEE80211_BAND_5GHZ]; @@ -1625,7 +1625,7 @@ int ath_attach(u16 devid, struct ath_softc *sc) #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) /* Initialze h/w Rfkill */ - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll); /* Initialize s/w rfkill */ @@ -1681,7 +1681,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx) ath_flushrecv(sc); spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false); + r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); if (r) DPRINTF(sc, ATH_DBG_FATAL, "Unable to reset hardware; reset status %u\n", r); @@ -1755,7 +1755,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, * descriptors that cross the 4K page boundary. Assume * one skipped descriptor per 4K page. */ - if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { u32 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); u32 dma_len; @@ -1795,7 +1795,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, bf->bf_desc = ds; bf->bf_daddr = DS2PHYS(dd, ds); - if (!(sc->sc_ah->ah_caps.hw_caps & + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { /* * Skip descriptor addresses which can cause 4KB @@ -1939,7 +1939,7 @@ static int ath9k_start(struct ieee80211_hw *hw) pos = curchan->hw_value; - init_channel = &sc->sc_ah->ah_channels[pos]; + init_channel = &sc->sc_ah->channels[pos]; ath9k_update_ichannel(sc, init_channel); /* Reset SERDES registers */ @@ -1989,10 +1989,10 @@ static int ath9k_start(struct ieee80211_hw *hw) | ATH9K_INT_RXEOL | ATH9K_INT_RXORN | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT) sc->imask |= ATH9K_INT_GTT; - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) sc->imask |= ATH9K_INT_CST; ath_cache_conf_rate(sc, &hw->conf); @@ -2092,7 +2092,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) sc->rx.rxlink = NULL; #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); #endif /* disable HAL and put h/w to sleep */ @@ -2149,7 +2149,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, sc->nvifs++; /* Set the device opmode */ - sc->sc_ah->ah_opmode = ic_opmode; + sc->sc_ah->opmode = ic_opmode; /* * Enable MIB interrupts when there are hardware phy counters. @@ -2165,7 +2165,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, * that does, if not overridden by configuration, * enable the TIM interrupt when operating as station. */ - if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && + if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && (conf->type == NL80211_IFTYPE_STATION) && !sc->config.swBeaconProcess) sc->imask |= ATH9K_INT_TIM; @@ -2198,8 +2198,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw, del_timer_sync(&sc->ani.timer); /* Reclaim beacon resources */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || - sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP || + sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) { ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); ath_beacon_return(sc, avp); } @@ -2248,11 +2248,11 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) curchan->center_freq); /* XXX: remove me eventualy */ - ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]); + ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]); ath_update_chainmask(sc, conf_is_ht(conf)); - if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) { + if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) { DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); mutex_unlock(&sc->mutex); return -EINVAL; @@ -2280,8 +2280,8 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, /* TODO: Need to decide which hw opmode to use for multi-interface * cases */ if (vif->type == NL80211_IFTYPE_AP && - ah->ah_opmode != NL80211_IFTYPE_AP) { - ah->ah_opmode = NL80211_IFTYPE_STATION; + ah->opmode != NL80211_IFTYPE_AP) { + ah->opmode = NL80211_IFTYPE_STATION; ath9k_hw_setopmode(ah); memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); sc->curaid = 0; diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index eac8db7..c28afe4 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -228,7 +228,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); #endif @@ -269,7 +269,7 @@ static int ath_pci_resume(struct pci_dev *pdev) * check the h/w rfkill state on resume * and start the rfkill poll timer */ - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll, 0); #endif diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index 5a42969..52aa2a7 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -20,7 +20,7 @@ void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, int regWrites) { - REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites); + REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); } bool @@ -90,8 +90,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) REG_WRITE(ah, AR_PHY(0x37), reg32); - ah->ah_curchan = chan; - ah->ah_curchanRadIndex = -1; + ah->curchan = chan; + ah->curchan_rad_index = -1; return true; } @@ -160,8 +160,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah, REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); - ah->ah_curchan = chan; - ah->ah_curchanRadIndex = -1; + ah->curchan = chan; + ah->curchan_rad_index = -1; return true; } @@ -207,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); - RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); + RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); - RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1); + RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); - RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1); + RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); - RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3, + RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, modesIndex); { int i; - for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) { - ah->ah_analogBank6Data[i] = - INI_RA(&ah->ah_iniBank6TPC, i, modesIndex); + for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) { + ah->analogBank6Data[i] = + INI_RA(&ah->iniBank6TPC, i, modesIndex); } } @@ -227,33 +227,33 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, if (IS_CHAN_2GHZ(chan)) { ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, ob2GHz, 3, 197, 0); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, db2GHz, 3, 194, 0); } else { ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, ob5GHz, 3, 203, 0); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, db5GHz, 3, 200, 0); } } - RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1); + RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data, + REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data, + REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data, + REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data, + REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data, + REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data, + REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, regWrites); return true; @@ -262,99 +262,99 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, void ath9k_hw_rfdetach(struct ath_hw *ah) { - if (ah->ah_analogBank0Data != NULL) { - kfree(ah->ah_analogBank0Data); - ah->ah_analogBank0Data = NULL; + if (ah->analogBank0Data != NULL) { + kfree(ah->analogBank0Data); + ah->analogBank0Data = NULL; } - if (ah->ah_analogBank1Data != NULL) { - kfree(ah->ah_analogBank1Data); - ah->ah_analogBank1Data = NULL; + if (ah->analogBank1Data != NULL) { + kfree(ah->analogBank1Data); + ah->analogBank1Data = NULL; } - if (ah->ah_analogBank2Data != NULL) { - kfree(ah->ah_analogBank2Data); - ah->ah_analogBank2Data = NULL; + if (ah->analogBank2Data != NULL) { + kfree(ah->analogBank2Data); + ah->analogBank2Data = NULL; } - if (ah->ah_analogBank3Data != NULL) { - kfree(ah->ah_analogBank3Data); - ah->ah_analogBank3Data = NULL; + if (ah->analogBank3Data != NULL) { + kfree(ah->analogBank3Data); + ah->analogBank3Data = NULL; } - if (ah->ah_analogBank6Data != NULL) { - kfree(ah->ah_analogBank6Data); - ah->ah_analogBank6Data = NULL; + if (ah->analogBank6Data != NULL) { + kfree(ah->analogBank6Data); + ah->analogBank6Data = NULL; } - if (ah->ah_analogBank6TPCData != NULL) { - kfree(ah->ah_analogBank6TPCData); - ah->ah_analogBank6TPCData = NULL; + if (ah->analogBank6TPCData != NULL) { + kfree(ah->analogBank6TPCData); + ah->analogBank6TPCData = NULL; } - if (ah->ah_analogBank7Data != NULL) { - kfree(ah->ah_analogBank7Data); - ah->ah_analogBank7Data = NULL; + if (ah->analogBank7Data != NULL) { + kfree(ah->analogBank7Data); + ah->analogBank7Data = NULL; } - if (ah->ah_addac5416_21 != NULL) { - kfree(ah->ah_addac5416_21); - ah->ah_addac5416_21 = NULL; + if (ah->addac5416_21 != NULL) { + kfree(ah->addac5416_21); + ah->addac5416_21 = NULL; } - if (ah->ah_bank6Temp != NULL) { - kfree(ah->ah_bank6Temp); - ah->ah_bank6Temp = NULL; + if (ah->bank6Temp != NULL) { + kfree(ah->bank6Temp); + ah->bank6Temp = NULL; } } bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) { if (!AR_SREV_9280_10_OR_LATER(ah)) { - ah->ah_analogBank0Data = + ah->analogBank0Data = kzalloc((sizeof(u32) * - ah->ah_iniBank0.ia_rows), GFP_KERNEL); - ah->ah_analogBank1Data = + ah->iniBank0.ia_rows), GFP_KERNEL); + ah->analogBank1Data = kzalloc((sizeof(u32) * - ah->ah_iniBank1.ia_rows), GFP_KERNEL); - ah->ah_analogBank2Data = + ah->iniBank1.ia_rows), GFP_KERNEL); + ah->analogBank2Data = kzalloc((sizeof(u32) * - ah->ah_iniBank2.ia_rows), GFP_KERNEL); - ah->ah_analogBank3Data = + ah->iniBank2.ia_rows), GFP_KERNEL); + ah->analogBank3Data = kzalloc((sizeof(u32) * - ah->ah_iniBank3.ia_rows), GFP_KERNEL); - ah->ah_analogBank6Data = + ah->iniBank3.ia_rows), GFP_KERNEL); + ah->analogBank6Data = kzalloc((sizeof(u32) * - ah->ah_iniBank6.ia_rows), GFP_KERNEL); - ah->ah_analogBank6TPCData = + ah->iniBank6.ia_rows), GFP_KERNEL); + ah->analogBank6TPCData = kzalloc((sizeof(u32) * - ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL); - ah->ah_analogBank7Data = + ah->iniBank6TPC.ia_rows), GFP_KERNEL); + ah->analogBank7Data = kzalloc((sizeof(u32) * - ah->ah_iniBank7.ia_rows), GFP_KERNEL); - - if (ah->ah_analogBank0Data == NULL - || ah->ah_analogBank1Data == NULL - || ah->ah_analogBank2Data == NULL - || ah->ah_analogBank3Data == NULL - || ah->ah_analogBank6Data == NULL - || ah->ah_analogBank6TPCData == NULL - || ah->ah_analogBank7Data == NULL) { + ah->iniBank7.ia_rows), GFP_KERNEL); + + if (ah->analogBank0Data == NULL + || ah->analogBank1Data == NULL + || ah->analogBank2Data == NULL + || ah->analogBank3Data == NULL + || ah->analogBank6Data == NULL + || ah->analogBank6TPCData == NULL + || ah->analogBank7Data == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate RF banks\n"); *status = -ENOMEM; return false; } - ah->ah_addac5416_21 = + ah->addac5416_21 = kzalloc((sizeof(u32) * - ah->ah_iniAddac.ia_rows * - ah->ah_iniAddac.ia_columns), GFP_KERNEL); - if (ah->ah_addac5416_21 == NULL) { + ah->iniAddac.ia_rows * + ah->iniAddac.ia_columns), GFP_KERNEL); + if (ah->addac5416_21 == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, - "Cannot allocate ah_addac5416_21\n"); + "Cannot allocate addac5416_21\n"); *status = -ENOMEM; return false; } - ah->ah_bank6Temp = + ah->bank6Temp = kzalloc((sizeof(u32) * - ah->ah_iniBank6.ia_rows), GFP_KERNEL); - if (ah->ah_bank6Temp == NULL) { + ah->iniBank6.ia_rows), GFP_KERNEL); + if (ah->bank6Temp == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, - "Cannot allocate ah_bank6Temp\n"); + "Cannot allocate bank6Temp\n"); *status = -ENOMEM; return false; } @@ -368,19 +368,19 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) { int i, regWrites = 0; u32 bank6SelMask; - u32 *bank6Temp = ah->ah_bank6Temp; + u32 *bank6Temp = ah->bank6Temp; - switch (ah->ah_diversityControl) { + switch (ah->diversity_control) { case ATH9K_ANT_FIXED_A: bank6SelMask = (ah-> - ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : + antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : REDUCE_CHAIN_1; break; case ATH9K_ANT_FIXED_B: bank6SelMask = (ah-> - ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : + antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : REDUCE_CHAIN_0; break; case ATH9K_ANT_VARIABLE: @@ -391,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) break; } - for (i = 0; i < ah->ah_iniBank6.ia_rows; i++) - bank6Temp[i] = ah->ah_analogBank6Data[i]; + for (i = 0; i < ah->iniBank6.ia_rows; i++) + bank6Temp[i] = ah->analogBank6Data[i]; REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); @@ -406,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites); + REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites); REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); #ifdef ALTER_SWITCH diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h index 71a7f5a..837a598 100644 --- a/drivers/net/wireless/ath9k/phy.h +++ b/drivers/net/wireless/ath9k/phy.h @@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, #define ATH9K_KEY_XOR 0xaa #define ATH9K_IS_MIC_ENABLED(ah) \ - ((ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) + ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE) #define ANTSWAP_AB 0x0001 #define REDUCE_CHAIN_0 0x00000050 diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c index 060a7cf..a4e8631 100644 --- a/drivers/net/wireless/ath9k/rc.c +++ b/drivers/net/wireless/ath9k/rc.c @@ -1394,13 +1394,13 @@ static void ath_rc_init(struct ath_softc *sc, u8 i, j, k, hi = 0, hthi = 0; /* FIXME: Adhoc */ - if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) || - (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)) { + if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) || + (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) { bool is_cw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40; rate_table = ath_choose_rate_table(sc, sband->band, sta->ht_cap.ht_supported, is_cw_40); - } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* cur_rate_table would be set on init through config() */ rate_table = sc->cur_rate_table; } @@ -1412,7 +1412,7 @@ static void ath_rc_init(struct ath_softc *sc, if (sta->ht_cap.ht_supported) { ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG; - if (sc->sc_ah->ah_caps.tx_chainmask != 1) + if (sc->sc_ah->caps.tx_chainmask != 1) ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG; if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG; @@ -1519,7 +1519,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband, */ if (tx_info_priv->tx.ts_flags & (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) && - ((sc->sc_ah->ah_txTrigLevel) >= ath_rc_priv->tx_triglevel_max)) { + ((sc->sc_ah->tx_trig_level) >= ath_rc_priv->tx_triglevel_max)) { tx_status = 1; is_underrun = 1; } @@ -1628,7 +1628,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp } rate_priv->rssi_down_time = jiffies_to_msecs(jiffies); - rate_priv->tx_triglevel_max = sc->sc_ah->ah_caps.tx_triglevel_max; + rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max; return rate_priv; } diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index 7c011b1..08f676a 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -135,7 +135,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, * discard the frame. Enable this if you want to see * error frames in Monitor mode. */ - if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_MONITOR) + if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR) goto rx_next; } else if (ds->ds_rxstat.rs_status != 0) { if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) @@ -161,7 +161,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, * decryption and MIC failures. For monitor mode, * we also ignore the CRC error. */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) { if (ds->ds_rxstat.rs_status & ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | ATH9K_RXERR_CRC)) @@ -241,7 +241,7 @@ static void ath_opmode_init(struct ath_softc *sc) ath9k_hw_setrxfilter(ah, rfilt); /* configure bssid mask */ - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) + if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) ath9k_hw_setbssidmask(sc); /* configure operational mode */ @@ -360,13 +360,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc) | ATH9K_RX_FILTER_MCAST; /* If not a STA, enable processing of Probe Requests */ - if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_STATION) + if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) rfilt |= ATH9K_RX_FILTER_PROBEREQ; /* Can't set HOSTAP into promiscous mode */ - if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) && + if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || - (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) { + (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) { rfilt |= ATH9K_RX_FILTER_PROM; /* ??? To prevent from sending ACK */ rfilt &= ~ATH9K_RX_FILTER_UCAST; @@ -375,13 +375,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc) if (sc->rx.rxfilter & FIF_CONTROL) rfilt |= ATH9K_RX_FILTER_CONTROL; - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION || - sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION || + sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) rfilt |= ATH9K_RX_FILTER_BEACON; /* If in HOSTAP mode, want to enable reception of PSPOLL frames & beacon frames */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); return rfilt; diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c index 3fff334..3f70b1e 100644 --- a/drivers/net/wireless/ath9k/xmit.c +++ b/drivers/net/wireless/ath9k/xmit.c @@ -308,7 +308,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, * when perform internal reset in this routine. * Only enable reset in STA mode for now. */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) needreset = 1; } } @@ -1072,7 +1072,7 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true); + r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); if (r) DPRINTF(sc, ATH_DBG_FATAL, "Unable to reset hardware; reset status %u\n", @@ -1477,7 +1477,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) } /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ - if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->ah_caps.rts_aggr_limit)) + if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) flags &= ~(ATH9K_TXDESC_RTSENA); for (i = 0; i < 4; i++) { -- 1.5.6.3 From db91ae8b168e3b8990bd6cde45a0e10f906c4762 Mon Sep 17 00:00:00 2001 From: Luis R. Rodriguez Date: Tue, 10 Feb 2009 14:44:37 -0800 Subject: [PATCH] ath9k: add comments for ath9k_hw_configpcipowersave() This is used for ASPM. Signed-off-by: Luis R. Rodriguez --- drivers/net/wireless/ath9k/hw.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 72ca1c8..cfcaaf8 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -2632,6 +2632,15 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) return status; } +/* + * Helper for ASPM support. + * + * Disable PLL when in L0s as well as receiver clock when in L1. + * This power saving option must be enabled through the SerDes. + * + * Programming the SerDes must go through the same 288 bit serial shift + * register as the other analog registers. Hence the 9 writes. + */ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) { u8 i; @@ -2639,13 +2648,20 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) if (ah->is_pciexpress != true) return; + /* Do not touch SerDes registers */ if (ah->config.pcie_powersave_enable == 2) return; + /* Nothing to do on restore for 11N */ if (restore) return; if (AR_SREV_9280_20_OR_LATER(ah)) { + /* + * AR9280 2.0 or later chips use SerDes values from the + * initvals.h initialized depending on chipset during + * ath9k_hw_do_attach() + */ for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), INI_RA(&ah->iniPcieSerdes, i, 1)); @@ -2656,10 +2672,12 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); + /* RX shut off when elecidle is asserted */ REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); + /* Shut off CLKREQ active in L1 */ if (ah->config.pcie_clock_req) REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); else @@ -2669,29 +2687,46 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); + /* Load the new settings */ REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); udelay(1000); } else { REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); + + /* RX shut off when elecidle is asserted */ REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); + + /* + * Ignore ah->ah_config.pcie_clock_req setting for + * pre-AR9280 11n + */ REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); + + /* Load the new settings */ REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); } + /* set bit 19 to allow forcing of pcie core into L1 state */ REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); + /* Several PCIe massages to ensure proper behaviour */ if (ah->config.pcie_waen) { REG_WRITE(ah, AR_WA, ah->config.pcie_waen); } else { if (AR_SREV_9285(ah)) REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); + /* + * On AR9280 chips bit 22 of 0x4004 needs to be set to + * otherwise card may disappear. + */ else if (AR_SREV_9280(ah)) REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); else -- 1.5.6.3 From 5e92848803c8f6fac6aae218c8f149ec15e319a3 Mon Sep 17 00:00:00 2001 From: Luis R. Rodriguez Date: Tue, 10 Feb 2009 14:50:57 -0800 Subject: [PATCH] ath9k: add udelay() for AR5416 on ath9k_hw_configpcipowersave() We need the udelay() for all families, including AR5416. Signed-off-by: Luis R. Rodriguez --- drivers/net/wireless/ath9k/hw.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index cfcaaf8..cad8e39 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -2666,7 +2666,6 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), INI_RA(&ah->iniPcieSerdes, i, 1)); } - udelay(1000); } else if (AR_SREV_9280(ah) && (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); @@ -2690,7 +2689,6 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) /* Load the new settings */ REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); - udelay(1000); } else { REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); @@ -2714,6 +2712,8 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); } + udelay(1000); + /* set bit 19 to allow forcing of pcie core into L1 state */ REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); -- 1.5.6.3 From 342d1a74cc310c7010d8b14da4456abc7d4682bf Mon Sep 17 00:00:00 2001 From: Luis R. Rodriguez Date: Tue, 10 Feb 2009 21:37:40 -0800 Subject: [PATCH] ath9k: implement IO serialization All 802.11n PCI devices (Cardbus, PCI, mini-PCI) require serialization of IO when on non-uniprocessor systems. PCI express devices not not require this. Signed-off-by: Luis R. Rodriguez --- drivers/net/wireless/ath9k/ath9k.h | 1 + drivers/net/wireless/ath9k/hw.c | 49 ++++++++++++++++++++++++++++++++++++ drivers/net/wireless/ath9k/hw.h | 8 ++++- drivers/net/wireless/ath9k/main.c | 1 + 4 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 0b0f82c..559e695 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -577,6 +577,7 @@ struct ath_softc { void __iomem *mem; int irq; spinlock_t sc_resetlock; + spinlock_t sc_serial_rw; struct mutex mutex; u8 curbssid[ETH_ALEN]; diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index cad8e39..bdbdefd 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -37,6 +37,36 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); +/* + * Read and write, they both share the same lock. The exception is when + * in an the ISR -- in that case we don't need serialization as it should + * be "interrupting" everything and IRS are not reentrant. + */ + +void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val) +{ + if (!in_irq() && ah->config.serialize_regmode == SER_REG_MODE_ON) { + unsigned long flags; + spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); + iowrite32(val, ah->ah_sc->mem + reg_offset); + spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); + } else + iowrite32(val, ah->ah_sc->mem + reg_offset); +} + +unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset) +{ + u32 val; + if (!in_irq() && ah->config.serialize_regmode == SER_REG_MODE_ON) { + unsigned long flags; + spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); + val = ioread32(ah->ah_sc->mem + reg_offset); + spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); + } else + val = ioread32(ah->ah_sc->mem + reg_offset); + return val; +} + /********************/ /* Helper Functions */ /********************/ @@ -389,6 +419,25 @@ static void ath9k_hw_set_defaults(struct ath_hw *ah) } ah->config.intr_mitigation = 1; + + /* + * We need this for PCI devices only (Cardbus, PCI, miniPCI) + * _and_ if on non-uniprocessor systems (Multiprocessor/HT). + * This means we use it for all AR5416 devices, and the few + * minor PCI AR9280 devices out there. + * + * Serialization is required because these devices do not handle + * well the case of two concurrent reads/writes due to the latency + * involved. During one read/write another read/write can be issued + * on another CPU while the previous read/write may still be working + * on our hardware, if we hit this case the hardware poops in a loop. + * We prevent this by serializing reads and writes. + * + * This issue is not present on PCI-Express devices or pre-AR5416 + * devices (legacy, 802.11abg). + */ + if (num_possible_cpus() > 1) + ah->config.serialize_regmode = SER_REG_MODE_AUTO; } static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 8211163..0dfa18b 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -42,8 +42,8 @@ #define AR5416_MAGIC 0x19641014 /* Register read/write primitives */ -#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sc->mem + _reg) -#define REG_READ(_ah, _reg) ioread32(_ah->ah_sc->mem + _reg) +#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32(_ah, _reg, _val) +#define REG_READ(_ah, _reg) ath9k_ioread32(_ah, _reg) #define SM(_v, _f) (((_v) << _f##_S) & _f) #define MS(_v, _f) (((_v) & _f) >> _f##_S) @@ -564,6 +564,10 @@ struct ath_hw { struct ar5416IniArray iniModesTxGain; }; +/* Read and write */ +void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val); +unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset); + /* Attach, Detach, Reset */ const char *ath9k_hw_probe(u16 vendorid, u16 devid); void ath9k_hw_detach(struct ath_hw *ah); diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index fc3460f..b554712 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -1357,6 +1357,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) printk(KERN_ERR "Unable to create debugfs files\n"); spin_lock_init(&sc->sc_resetlock); + spin_lock_init(&sc->sc_serial_rw); mutex_init(&sc->mutex); tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, -- 1.5.6.3 From c929e0aad310d71446ac7a75e6ca030c27aae03a Mon Sep 17 00:00:00 2001 From: Luis R. Rodriguez Date: Tue, 10 Feb 2009 21:57:18 -0800 Subject: [PATCH] ath9k: AR9280 PCI devices must serialize IO as well Signed-off-by: Luis R. Rodriguez --- drivers/net/wireless/ath9k/hw.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index bdbdefd..2bf0bc2 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -656,8 +656,15 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, goto bad; } + /* + * All PCI devices should be put here. + * XXX: remove ah->is_pciexpress and use pdev->is_pcie, then + * we can just check for !pdev->is_pcie here, but + * consideration must be taken for handling AHB as well. + */ if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { - if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) { + if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || + (AR_SREV_9280(ah) && !ah->is_pciexpress)) { ah->config.serialize_regmode = SER_REG_MODE_ON; } else { -- 1.5.6.3 From 2fe8896dc2514e2c15e647de5b28f38b957c8300 Mon Sep 17 00:00:00 2001 From: Luis R. Rodriguez Date: Tue, 10 Feb 2009 23:33:57 -0800 Subject: [PATCH] ath9k: add cpu notifier to enhance device configuration Upon CPU Hotplug the number of CPUs can change and we can tweak our driver configuration as such. Keep in mind CPU hotplug also occurs during suspend/resume. Since we have a notifier now we can rely on num_present_cpus() rather than num_possible_cpus() to enable/disable serialization. Signed-off-by: Luis R. Rodriguez --- drivers/net/wireless/ath9k/ath9k.h | 6 ++++ drivers/net/wireless/ath9k/hw.c | 49 ++++++++++++++++++++++------------- drivers/net/wireless/ath9k/hw.h | 3 ++ drivers/net/wireless/ath9k/main.c | 29 +++++++++++++++++++++ drivers/net/wireless/ath9k/pci.c | 3 ++ 5 files changed, 72 insertions(+), 18 deletions(-) diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 559e695..b00b13f 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -22,6 +22,7 @@ #include #include #include +#include #include "hw.h" #include "rc.h" @@ -568,9 +569,14 @@ struct ath_bus_ops { bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data); }; +int ath9k_cpu_callback(struct notifier_block *nfb, + unsigned long action, void *hcpu); + struct ath_softc { struct ieee80211_hw *hw; struct device *dev; + /* This should or _needs_ to be __cpuinit (?) */ + struct notifier_block cpu_notifer; struct tasklet_struct intr_tq; struct tasklet_struct bcon_tasklet; struct ath_hw *sc_ah; diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 2bf0bc2..b7bee01 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -16,6 +16,7 @@ #include #include +#include #include "ath9k.h" #include "initvals.h" @@ -381,6 +382,35 @@ static const char *ath9k_hw_devname(u16 devid) return NULL; } +/* + * We can slap on to here things we need to tune depending + * on the number of CPUs. This will happen on CPU hotplug + * which is also used for suspend/resume. + */ +void ath9k_hw_config_for_cpus(struct ath_hw *ah) +{ + /* + * We need this for PCI devices only (Cardbus, PCI, miniPCI) + * _and_ if on non-uniprocessor systems (Multiprocessor/HT). + * This means we use it for all AR5416 devices, and the few + * minor PCI AR9280 devices out there. + * + * Serialization is required because these devices do not handle + * well the case of two concurrent reads/writes due to the latency + * involved. During one read/write another read/write can be issued + * on another CPU while the previous read/write may still be working + * on our hardware, if we hit this case the hardware poops in a loop. + * We prevent this by serializing reads and writes. + * + * This issue is not present on PCI-Express devices or pre-AR5416 + * devices (legacy, 802.11abg). + */ + if (num_present_cpus() > 1) + ah->config.serialize_regmode = SER_REG_MODE_AUTO; + else + ah->config.serialize_regmode = SER_REG_MODE_OFF; +} + static void ath9k_hw_set_defaults(struct ath_hw *ah) { int i; @@ -420,24 +450,7 @@ static void ath9k_hw_set_defaults(struct ath_hw *ah) ah->config.intr_mitigation = 1; - /* - * We need this for PCI devices only (Cardbus, PCI, miniPCI) - * _and_ if on non-uniprocessor systems (Multiprocessor/HT). - * This means we use it for all AR5416 devices, and the few - * minor PCI AR9280 devices out there. - * - * Serialization is required because these devices do not handle - * well the case of two concurrent reads/writes due to the latency - * involved. During one read/write another read/write can be issued - * on another CPU while the previous read/write may still be working - * on our hardware, if we hit this case the hardware poops in a loop. - * We prevent this by serializing reads and writes. - * - * This issue is not present on PCI-Express devices or pre-AR5416 - * devices (legacy, 802.11abg). - */ - if (num_possible_cpus() > 1) - ah->config.serialize_regmode = SER_REG_MODE_AUTO; + ath9k_hw_config_for_cpus(ah); } static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 0dfa18b..b6c94bd 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -568,6 +568,9 @@ struct ath_hw { void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val); unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset); +/* Lets us tweak the device per CPU changes */ +void ath9k_hw_config_for_cpus(struct ath_hw *ah); + /* Attach, Detach, Reset */ const char *ath9k_hw_probe(u16 vendorid, u16 devid); void ath9k_hw_detach(struct ath_hw *ah); diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index b554712..6dfb695 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -2611,6 +2611,35 @@ struct ieee80211_ops ath9k_ops = { .ampdu_action = ath9k_ampdu_action, }; +int ath9k_cpu_callback(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + struct ath_softc *sc = container_of(nfb, struct ath_softc, cpu_notifer); + int old_serial_mode; + + old_serial_mode = sc->sc_ah->config.serialize_regmode; + + switch (action) { + case CPU_ONLINE: + case CPU_ONLINE_FROZEN: + ath9k_hw_config_for_cpus(sc->sc_ah); + break; + case CPU_DEAD: + case CPU_DEAD_FROZEN: + ath9k_hw_config_for_cpus(sc->sc_ah); + break; + } + + if (unlikely(old_serial_mode != sc->sc_ah->config.serialize_regmode)) { + DPRINTF(sc, ATH_DBG_RESET, + "serialize_regmode has changed due to CPU " + "count to %d\n", + sc->sc_ah->config.serialize_regmode); + } + + return NOTIFY_OK; +} + static struct { u32 version; const char * name; diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index c28afe4..4fe7d9c 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -174,6 +174,9 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto bad3; } + sc->cpu_notifer.notifier_call = ath9k_cpu_callback; + register_hotcpu_notifier(&sc->cpu_notifer); + /* setup interrupt service routine */ if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) { -- 1.5.6.3