Kindle 3 kernel diff
.gitignore | 66
Documentation/DocBook/.gitignore | 6
Documentation/filesystems/ext4.txt | 133
Documentation/filesystems/proc.txt | 23
Documentation/filesystems/ubifs.txt | 173
MAINTAINERS | 12
Makefile | 10
arch/.gitignore | 2
arch/Kconfig | 5
arch/arm/Kconfig | 44
arch/arm/Kconfig.debug | 8
arch/arm/Makefile | 6
arch/arm/boot/.gitignore | 5
arch/arm/boot/compressed/.gitignore | 2
arch/arm/boot/compressed/Makefile | 6
arch/arm/boot/compressed/head.S | 16
arch/arm/boot/compressed/vmlinux.lds | 56
arch/arm/common/time-acorn.c | 2
arch/arm/kernel/Makefile | 7
arch/arm/kernel/armksyms.c | 5
arch/arm/kernel/dma.c | 2
arch/arm/kernel/early_console.c | 40
arch/arm/kernel/entry-common.S | 164
arch/arm/kernel/fiq.c | 4
arch/arm/kernel/ftrace.c | 116
arch/arm/kernel/irq.c | 10
arch/arm/kernel/kgdb.c | 206
arch/arm/kernel/process.c | 29
arch/arm/kernel/ptrace.c | 57
arch/arm/kernel/setup.c | 57
arch/arm/kernel/signal.c | 8
arch/arm/kernel/smp.c | 2
arch/arm/kernel/time.c | 38
arch/arm/kernel/traps.c | 121
arch/arm/kernel/vmlinux.lds.S | 15
arch/arm/lib/Makefile | 1
arch/arm/lib/stacktrace.c | 7
arch/arm/mach-at91/gpio.c | 8
arch/arm/mach-footbridge/netwinder-hw.c | 2
arch/arm/mach-footbridge/netwinder-leds.c | 2
arch/arm/mach-integrator/core.c | 2
arch/arm/mach-integrator/pci_v3.c | 2
arch/arm/mach-ixp4xx/common-pci.c | 2
arch/arm/mach-mx21/Kconfig | 17
arch/arm/mach-mx21/Makefile | 12
arch/arm/mach-mx21/Makefile.boot | 3
arch/arm/mach-mx21/board-mx21ads.h | 145
arch/arm/mach-mx21/clock.c | 664
arch/arm/mach-mx21/crm_regs.h | 163
arch/arm/mach-mx21/devices.c | 278
arch/arm/mach-mx21/dma.c | 491
arch/arm/mach-mx21/gpio_mux.c | 302
arch/arm/mach-mx21/gpio_mux.h | 78
arch/arm/mach-mx21/mm.c | 55
arch/arm/mach-mx21/mx21_pins.h | 233
arch/arm/mach-mx21/mx21ads.c | 353
arch/arm/mach-mx21/mx21ads_gpio.c | 384
arch/arm/mach-mx21/serial.c | 200
arch/arm/mach-mx21/serial.h | 139
arch/arm/mach-mx21/system.c | 65
arch/arm/mach-mx21/time.c | 168
arch/arm/mach-mx27/Kconfig | 43
arch/arm/mach-mx27/Makefile | 18
arch/arm/mach-mx27/Makefile.boot | 3
arch/arm/mach-mx27/board-mx27ads.h | 385
arch/arm/mach-mx27/clock.c | 1549
arch/arm/mach-mx27/cpu.c | 33
arch/arm/mach-mx27/crm_regs.h | 283
arch/arm/mach-mx27/devices.c | 697
arch/arm/mach-mx27/dma.c | 553
arch/arm/mach-mx27/dptc.c | 49
arch/arm/mach-mx27/gpio_mux.c | 308
arch/arm/mach-mx27/gpio_mux.h | 78
arch/arm/mach-mx27/mm.c | 62
arch/arm/mach-mx27/mx27_pins.h | 207
arch/arm/mach-mx27/mx27ads.c | 823
arch/arm/mach-mx27/mx27ads_gpio.c | 1226
arch/arm/mach-mx27/mxc_pm.c | 458
arch/arm/mach-mx27/pm.c | 102
arch/arm/mach-mx27/serial.c | 275
arch/arm/mach-mx27/serial.h | 170
arch/arm/mach-mx27/system.c | 60
arch/arm/mach-mx27/time.c | 240
arch/arm/mach-mx27/usb.h | 116
arch/arm/mach-mx27/usb_dr.c | 126
arch/arm/mach-mx27/usb_h1.c | 53
arch/arm/mach-mx27/usb_h2.c | 53
arch/arm/mach-mx3/Kconfig | 90
arch/arm/mach-mx3/Makefile | 16
arch/arm/mach-mx3/board-mx31ads.h | 326
arch/arm/mach-mx3/board-mx3_3stack.h | 150
arch/arm/mach-mx3/clock.c | 1380
arch/arm/mach-mx3/cpu.c | 78
arch/arm/mach-mx3/crm_regs.h | 394
arch/arm/mach-mx3/devices.c | 858
arch/arm/mach-mx3/dma.c | 745
arch/arm/mach-mx3/dptc.c | 103
arch/arm/mach-mx3/dvfs_v2.c | 530
arch/arm/mach-mx3/iomux.c | 259
arch/arm/mach-mx3/iomux.h | 185
arch/arm/mach-mx3/mm.c | 48
arch/arm/mach-mx3/mx31_pins.h | 429
arch/arm/mach-mx3/mx31ads.c | 1004
arch/arm/mach-mx3/mx31ads_gpio.c | 1561
arch/arm/mach-mx3/mx3_3stack.c | 1081
arch/arm/mach-mx3/mx3_3stack_gpio.c | 1298
arch/arm/mach-mx3/mxc_pm.c | 446
arch/arm/mach-mx3/pm.c | 113
arch/arm/mach-mx3/sdma_script_code.h | 581
arch/arm/mach-mx3/sdma_script_code_pass2.h | 434
arch/arm/mach-mx3/serial.c | 267
arch/arm/mach-mx3/serial.h | 158
arch/arm/mach-mx3/system.c | 103
arch/arm/mach-mx3/time.c | 148
arch/arm/mach-mx3/usb.h | 122
arch/arm/mach-mx3/usb_dr.c | 128
arch/arm/mach-mx3/usb_h1.c | 53
arch/arm/mach-mx3/usb_h2.c | 75
arch/arm/mach-mx35/Kconfig | 148
arch/arm/mach-mx35/Makefile | 24
arch/arm/mach-mx35/Makefile.boot | 9
arch/arm/mach-mx35/board-mx35_3stack.h | 210
arch/arm/mach-mx35/board-mx35evb.h | 151
arch/arm/mach-mx35/boardid.c | 207
arch/arm/mach-mx35/boardid.h | 20
arch/arm/mach-mx35/boot_globals.c | 777
arch/arm/mach-mx35/bootdata.c | 809
arch/arm/mach-mx35/clock.c | 2021
arch/arm/mach-mx35/cpu.c | 80
arch/arm/mach-mx35/cpufreq.c | 306
arch/arm/mach-mx35/crm_regs.h | 444
arch/arm/mach-mx35/devices.c | 712
arch/arm/mach-mx35/dma.c | 1046
arch/arm/mach-mx35/dvfs.c | 788
arch/arm/mach-mx35/iomux.c | 474
arch/arm/mach-mx35/iomux.h | 293
arch/arm/mach-mx35/mm.c | 92
arch/arm/mach-mx35/mx35_3stack.c | 773
arch/arm/mach-mx35/mx35_3stack_cpld.c | 159
arch/arm/mach-mx35/mx35_3stack_gpio.c | 1353
arch/arm/mach-mx35/mx35_3stack_irq.c | 371
arch/arm/mach-mx35/mx35_accessory.c | 458
arch/arm/mach-mx35/mx35_luigi.c | 1004
arch/arm/mach-mx35/mx35_luigi_gpio.c | 2180
arch/arm/mach-mx35/mx35_pins.h | 338
arch/arm/mach-mx35/mx35evb.c | 396
arch/arm/mach-mx35/mx35evb_cpld.c | 82
arch/arm/mach-mx35/mx35evb_gpio.c | 276
arch/arm/mach-mx35/pm.c | 383
arch/arm/mach-mx35/sdma_script_code.h | 254
arch/arm/mach-mx35/sdma_script_code_v2.h | 234
arch/arm/mach-mx35/serial.c | 180
arch/arm/mach-mx35/serial.h | 132
arch/arm/mach-mx35/system.c | 640
arch/arm/mach-mx35/usb.h | 104
arch/arm/mach-mx35/usb_dr.c | 222
arch/arm/mach-mx35/usb_h2.c | 62
arch/arm/mach-mx35/wifi.c | 197
arch/arm/mach-mx37/Kconfig | 89
arch/arm/mach-mx37/Makefile | 19
arch/arm/mach-mx37/Makefile.boot | 3
arch/arm/mach-mx37/board-mx37_3stack.h | 121
arch/arm/mach-mx37/clock.c | 3008 +
arch/arm/mach-mx37/cpu.c | 71
arch/arm/mach-mx37/crm_regs.h | 611
arch/arm/mach-mx37/devices.c | 941
arch/arm/mach-mx37/dma.c | 666
arch/arm/mach-mx37/dptc.c | 69
arch/arm/mach-mx37/iomux.c | 204
arch/arm/mach-mx37/iomux.h | 226
arch/arm/mach-mx37/lpmodes.c | 408
arch/arm/mach-mx37/mm.c | 82
arch/arm/mach-mx37/mx37_3stack.c | 962
arch/arm/mach-mx37/mx37_3stack_cpld.c | 231
arch/arm/mach-mx37/mx37_3stack_gpio.c | 1018
arch/arm/mach-mx37/mx37_3stack_pmic_wm8350.c | 411
arch/arm/mach-mx37/mx37_pins.h | 256
arch/arm/mach-mx37/pm.c | 72
arch/arm/mach-mx37/sdma_script_code.h | 203
arch/arm/mach-mx37/serial.c | 169
arch/arm/mach-mx37/serial.h | 127
arch/arm/mach-mx37/system.c | 192
arch/arm/mach-mx37/usb.h | 112
arch/arm/mach-mx37/usb_dr.c | 120
arch/arm/mach-mx51/Kconfig | 85
arch/arm/mach-mx51/Makefile | 19
arch/arm/mach-mx51/Makefile.boot | 3
arch/arm/mach-mx51/board-mx51_3stack.h | 128
arch/arm/mach-mx51/clock.c | 3123 +
arch/arm/mach-mx51/cpu.c | 60
arch/arm/mach-mx51/crm_regs.h | 677
arch/arm/mach-mx51/devices.c | 916
arch/arm/mach-mx51/dma.c | 666
arch/arm/mach-mx51/iomux.c | 248
arch/arm/mach-mx51/iomux.h | 236
arch/arm/mach-mx51/lpmodes.c | 204
arch/arm/mach-mx51/mm.c | 84
arch/arm/mach-mx51/mx51_3stack.c | 1207
arch/arm/mach-mx51/mx51_3stack_gpio.c | 1926
arch/arm/mach-mx51/mx51_pins.h | 361
arch/arm/mach-mx51/pm.c | 146
arch/arm/mach-mx51/sdma_script_code.h | 170
arch/arm/mach-mx51/serial.c | 169
arch/arm/mach-mx51/serial.h | 127
arch/arm/mach-mx51/suspend.S | 152
arch/arm/mach-mx51/system.c | 191
arch/arm/mach-mx51/usb.h | 116
arch/arm/mach-mx51/usb_dr.c | 140
arch/arm/mach-mx51/usb_h1.c | 54
arch/arm/mach-mx51/usb_h2.c | 57
arch/arm/mach-mx51/wfi.S | 434
arch/arm/mach-sa1100/badge4.c | 11
arch/arm/mach-shark/leds.c | 2
arch/arm/mm/Kconfig | 6
arch/arm/mm/abort-ev6.S | 5
arch/arm/mm/cache-l2x0.c | 186
arch/arm/mm/cache-v6.S | 57
arch/arm/mm/consistent.c | 2
arch/arm/mm/context.c | 2
arch/arm/mm/copypage-v4mc.c | 6
arch/arm/mm/copypage-v6.c | 2
arch/arm/mm/copypage-xscale.c | 6
arch/arm/mm/fault.c | 49
arch/arm/mm/flush.c | 29
arch/arm/mm/mmu.c | 3
arch/arm/mm/proc-v6.S | 63
arch/arm/mm/tlb-v6.S | 3
arch/arm/oprofile/Makefile | 1
arch/arm/oprofile/common.c | 45
arch/arm/oprofile/evtmon_regs.h | 84
arch/arm/oprofile/op_model_arm11.c | 477
arch/arm/oprofile/op_model_arm11_core.c | 44
arch/arm/oprofile/op_model_arm11_core.h | 13
arch/arm/oprofile/op_model_arm11_evtmon.c | 188
arch/arm/oprofile/op_model_v6.c | 19
arch/arm/oprofile/op_model_xscale.c | 3
arch/arm/plat-mxc/Kconfig | 145
arch/arm/plat-mxc/Makefile | 55
arch/arm/plat-mxc/clock.c | 683
arch/arm/plat-mxc/cpu_common.c | 85
arch/arm/plat-mxc/cpufreq.c | 595
arch/arm/plat-mxc/dma_mx2.c | 1316
arch/arm/plat-mxc/dptc.c | 610
arch/arm/plat-mxc/dvfs_core.c | 584
arch/arm/plat-mxc/entry-pm.S | 315
arch/arm/plat-mxc/gpio.c | 909
arch/arm/plat-mxc/io.c | 41
arch/arm/plat-mxc/irq.c | 361
arch/arm/plat-mxc/isp1301xc.c | 290
arch/arm/plat-mxc/isp1504xc.c | 278
arch/arm/plat-mxc/leds.c | 111
arch/arm/plat-mxc/mc13783_xc.c | 299
arch/arm/plat-mxc/pwm.c | 282
arch/arm/plat-mxc/sdma/Makefile | 18
arch/arm/plat-mxc/sdma/dma_sdma.c | 697
arch/arm/plat-mxc/sdma/iapi/Makefile | 5
arch/arm/plat-mxc/sdma/iapi/include/epm.h | 187
arch/arm/plat-mxc/sdma/iapi/include/iapi.h | 49
arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h | 128
arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h | 136
arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h | 78
arch/arm/plat-mxc/sdma/iapi/include/iapiLowDsp.h | 50
arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h | 60
arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h | 52
arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h | 41
arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h | 96
arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h | 426
arch/arm/plat-mxc/sdma/iapi/src/Makefile | 18
arch/arm/plat-mxc/sdma/iapi/src/iapiDefaults.c | 110
arch/arm/plat-mxc/sdma/iapi/src/iapiHigh.c | 2801 +
arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c | 150
arch/arm/plat-mxc/sdma/iapi/src/iapiLowDsp.c | 79
arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c | 519
arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c | 623
arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c | 52
arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c | 64
arch/arm/plat-mxc/sdma/sdma.c | 1484
arch/arm/plat-mxc/sdma/sdma_malloc.c | 388
arch/arm/plat-mxc/serialxc.c | 64
arch/arm/plat-mxc/snoop.c | 133
arch/arm/plat-mxc/spba.c | 133
arch/arm/plat-mxc/time.c | 265
arch/arm/plat-mxc/tzic.c | 179
arch/arm/plat-mxc/usb_common.c | 867
arch/arm/plat-mxc/utmixc.c | 120
arch/arm/plat-mxc/wdog.c | 153
arch/arm/plat-omap/clock.c | 3
arch/arm/tools/mach-types | 4
arch/arm/vfp/entry.S | 23
arch/arm/vfp/vfp.h | 2
arch/arm/vfp/vfphw.S | 14
arch/arm/vfp/vfpmodule.c | 123
arch/avr32/kernel/process.c | 2
arch/blackfin/boot/.gitignore | 1
arch/blackfin/kernel/process.c | 2
arch/ia64/Kconfig | 64
arch/ia64/kernel/.gitignore | 1
arch/ia64/kernel/asm-offsets.c | 2
arch/ia64/kernel/entry.S | 18
arch/ia64/kernel/fsys.S | 21
arch/ia64/kernel/iosapic.c | 33
arch/ia64/kernel/mca.c | 2
arch/ia64/kernel/perfmon.c | 6
arch/ia64/kernel/process.c | 10
arch/ia64/kernel/sal.c | 2
arch/ia64/kernel/salinfo.c | 6
arch/ia64/kernel/signal.c | 8
arch/ia64/kernel/smp.c | 16
arch/ia64/kernel/smpboot.c | 3
arch/ia64/kernel/time.c | 74
arch/ia64/kernel/traps.c | 10
arch/ia64/kernel/unwind.c | 4
arch/ia64/kernel/unwind_i.h | 2
arch/ia64/mm/init.c | 2
arch/ia64/mm/tlb.c | 2
arch/m68knommu/Kconfig | 20
arch/m68knommu/Makefile | 11
arch/m68knommu/configs/m5208evb_defconfig | 610
arch/m68knommu/configs/m5249evb_defconfig | 497
arch/m68knommu/configs/m5275evb_defconfig | 627
arch/m68knommu/configs/m5307c3_defconfig | 580
arch/m68knommu/configs/m5407c3_defconfig | 641
arch/m68knommu/kernel/Makefile | 5
arch/m68knommu/kernel/irq.c | 11
arch/m68knommu/kernel/process.c | 8
arch/m68knommu/kernel/stacktrace.c | 69
arch/m68knommu/kernel/time.c | 40
arch/m68knommu/kernel/traps.c | 38
arch/m68knommu/platform/coldfire/Makefile | 2
arch/m68knommu/platform/coldfire/dma_timer.c | 84
arch/m68knommu/platform/coldfire/entry.S | 48
arch/m68knommu/platform/coldfire/irq_chip.c | 110
arch/m68knommu/platform/coldfire/pit.c | 95
arch/mips/Kconfig | 21
arch/mips/boot/.gitignore | 4
arch/mips/kernel/asm-offsets.c | 3
arch/mips/kernel/entry.S | 20
arch/mips/kernel/gdb-stub.c | 2
arch/mips/kernel/i8253.c | 2
arch/mips/kernel/i8259.c | 2
arch/mips/kernel/module.c | 2
arch/mips/kernel/process.c | 2
arch/mips/kernel/scall32-o32.S | 2
arch/mips/kernel/scall64-64.S | 2
arch/mips/kernel/scall64-n32.S | 2
arch/mips/kernel/scall64-o32.S | 2
arch/mips/kernel/signal.c | 4
arch/mips/kernel/signal32.c | 4
arch/mips/kernel/smp.c | 27
arch/mips/kernel/traps.c | 2
arch/mips/mm/fault.c | 2
arch/mips/mm/highmem.c | 5
arch/mips/mm/init.c | 2
arch/mips/sibyte/sb1250/irq.c | 6
arch/mips/sibyte/sb1250/smp.c | 2
arch/mips/sibyte/swarm/setup.c | 6
arch/mn10300/Kconfig | 11
arch/mn10300/boot/.gitignore | 1
arch/powerpc/.gitignore | 1
arch/powerpc/Kconfig | 19
arch/powerpc/Kconfig.debug | 4
arch/powerpc/boot/.gitignore | 38
arch/powerpc/boot/dtc-src/.gitignore | 3
arch/powerpc/kernel/Makefile | 13
arch/powerpc/kernel/cputable.c | 4
arch/powerpc/kernel/entry_32.S | 131
arch/powerpc/kernel/entry_64.S | 115
arch/powerpc/kernel/ftrace.c | 159
arch/powerpc/kernel/idle.c | 2
arch/powerpc/kernel/io.c | 3
arch/powerpc/kernel/irq.c | 157
arch/powerpc/kernel/pmc.c | 2
arch/powerpc/kernel/ppc_ksyms.c | 1
arch/powerpc/kernel/process.c | 22
arch/powerpc/kernel/prom.c | 2
arch/powerpc/kernel/rtas.c | 2
arch/powerpc/kernel/setup_32.c | 18
arch/powerpc/kernel/smp.c | 12
arch/powerpc/kernel/stacktrace.c | 37
arch/powerpc/kernel/time.c | 2
arch/powerpc/kernel/traps.c | 12
arch/powerpc/kernel/vdso32/.gitignore | 2
arch/powerpc/kernel/vdso64/.gitignore | 2
arch/powerpc/lib/locks.c | 6
arch/powerpc/mm/fault.c | 2
arch/powerpc/mm/hash_native_64.c | 2
arch/powerpc/mm/init_32.c | 2
arch/powerpc/mm/tlb_64.c | 50
arch/powerpc/platforms/cell/beat_htab.c | 2
arch/powerpc/platforms/cell/beat_interrupt.c | 2
arch/powerpc/platforms/cell/smp.c | 2
arch/powerpc/platforms/cell/spufs/.gitignore | 2
arch/powerpc/platforms/chrp/smp.c | 2
arch/powerpc/platforms/chrp/time.c | 5
arch/powerpc/platforms/iseries/setup.c | 4
arch/powerpc/platforms/powermac/Makefile | 5
arch/powerpc/platforms/powermac/feature.c | 2
arch/powerpc/platforms/powermac/nvram.c | 2
arch/powerpc/platforms/powermac/pic.c | 2
arch/powerpc/platforms/pseries/eeh.c | 2
arch/powerpc/platforms/pseries/iommu.c | 14
arch/powerpc/platforms/pseries/smp.c | 2
arch/powerpc/platforms/pseries/xics.c | 11
arch/powerpc/sysdev/i8259.c | 2
arch/powerpc/sysdev/ipic.c | 2
arch/powerpc/sysdev/mpic.c | 2
arch/powerpc/xmon/xmon.c | 2
arch/ppc/.gitignore | 1
arch/ppc/8260_io/enet.c | 2
arch/ppc/8260_io/fcc_enet.c | 2
arch/ppc/8xx_io/commproc.c | 2
arch/ppc/8xx_io/enet.c | 2
arch/ppc/8xx_io/fec.c | 2
arch/ppc/Kconfig | 19
arch/ppc/boot/Makefile | 9
arch/ppc/boot/images/.gitignore | 6
arch/ppc/boot/lib/.gitignore | 3
arch/ppc/boot/utils/.gitignore | 3
arch/ppc/kernel/entry.S | 4
arch/ppc/kernel/smp.c | 12
arch/ppc/kernel/traps.c | 6
arch/ppc/lib/locks.c | 38
arch/ppc/mm/init.c | 2
arch/ppc/platforms/hdpu.c | 2
arch/ppc/platforms/sbc82xx.c | 2
arch/ppc/syslib/cpm2_common.c | 2
arch/ppc/syslib/open_pic.c | 2
arch/ppc/syslib/open_pic2.c | 2
arch/s390/kernel/process.c | 2
arch/sh/boot/.gitignore | 1
arch/sh/kernel/process_32.c | 2
arch/sh/kernel/vsyscall/.gitignore | 1
arch/sh/lib64/.gitignore | 1
arch/sparc/mm/highmem.c | 4
arch/sparc64/Kconfig | 2
arch/sparc64/Kconfig.debug | 2
arch/sparc64/boot/.gitignore | 4
arch/sparc64/kernel/Makefile | 1
arch/sparc64/kernel/ftrace.c | 94
arch/sparc64/kernel/process.c | 2
arch/sparc64/lib/mcount.S | 58
arch/um/kernel/process.c | 2
arch/x86/Kconfig | 19
arch/x86/Kconfig.debug | 1
arch/x86/boot/.gitignore | 8
arch/x86/boot/compressed/.gitignore | 1
arch/x86/boot/tools/.gitignore | 1
arch/x86/ia32/ia32entry.S | 9
arch/x86/kernel/.gitignore | 3
arch/x86/kernel/Makefile | 8
arch/x86/kernel/acpi/realmode/.gitignore | 3
arch/x86/kernel/alternative.c | 4
arch/x86/kernel/apic_32.c | 3
arch/x86/kernel/apic_64.c | 1
arch/x86/kernel/cpu/mtrr/generic.c | 2
arch/x86/kernel/crash.c | 8
arch/x86/kernel/early_printk.c | 8
arch/x86/kernel/entry_32.S | 94
arch/x86/kernel/entry_64.S | 109
arch/x86/kernel/ftrace.c | 173
arch/x86/kernel/head64.c | 6
arch/x86/kernel/head_32.S | 1
arch/x86/kernel/i386_ksyms_32.c | 8
arch/x86/kernel/i8253.c | 2
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drivers/mxc/security/dryice.c | 1121
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drivers/mxc/security/rng/shw_driver.c | 2335 +
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drivers/mxc/security/sahara2/km_adaptor.c | 849
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drivers/mxc/security/sahara2/sah_status_manager.c | 710
drivers/mxc/security/sahara2/sf_util.c | 1396
drivers/mxc/security/scc2_driver.c | 2261 +
drivers/mxc/security/scc2_internals.h | 527
drivers/mxc/ssi/Kconfig | 12
drivers/mxc/ssi/Makefile | 7
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drivers/mxc/ssi/ssi.c | 1238
drivers/mxc/ssi/ssi.h | 574
drivers/mxc/ssi/ssi_types.h | 367
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drivers/mxc/vpu/mxc_vl2cc.c | 123
drivers/mxc/vpu/mxc_vpu.c | 762
drivers/net/3c527.c | 2
drivers/net/3c59x.c | 16
drivers/net/8139too.c | 6
drivers/net/Kconfig | 54
drivers/net/Makefile | 1
drivers/net/can/Kconfig | 9
drivers/net/can/Makefile | 1
drivers/net/can/flexcan/Makefile | 3
drivers/net/can/flexcan/dev.c | 619
drivers/net/can/flexcan/drv.c | 624
drivers/net/can/flexcan/flexcan.h | 223
drivers/net/can/flexcan/mbm.c | 347
drivers/net/cs89x0.c | 17
drivers/net/fec.c | 779
drivers/net/fec.h | 18
drivers/net/hamradio/6pack.c | 2
drivers/net/hamradio/mkiss.c | 2
drivers/net/ibm_emac/ibm_emac_core.c | 11
drivers/net/ibm_emac/ibm_emac_core.h | 2
drivers/net/irda/Kconfig | 4
drivers/net/irda/Makefile | 1
drivers/net/irda/mxc_ir.c | 1777
drivers/net/irda/mxc_ir.h | 133
drivers/net/loopback.c | 6
drivers/net/ppp_async.c | 22
drivers/net/ppp_generic.c | 1
drivers/net/smc911x.h | 10
drivers/net/smsc911x.c | 2253 +
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drivers/net/sungem.c | 4
drivers/net/tulip/tulip_core.c | 1
drivers/net/usb/usbnet.c | 2
drivers/net/wan/.gitignore | 1
drivers/net/wan/Kconfig | 4
drivers/net/wan/Makefile | 5
drivers/net/wan/mwan-core.c | 34
drivers/net/wan/mwan.c | 727
drivers/net/wireless/Kconfig | 1
drivers/net/wireless/Makefile | 1
drivers/net/wireless/ar6000/Kconfig | 14
drivers/net/wireless/ar6000/Makefile | 22
drivers/net/wireless/ar6000/ar6000_drv.c | 3309 +
drivers/net/wireless/ar6000/ar6000_raw_if.c | 443
drivers/net/wireless/ar6000/ar6k.c | 1006
drivers/net/wireless/ar6000/ar6k_events.c | 650
drivers/net/wireless/ar6000/bmi.c | 778
drivers/net/wireless/ar6000/common_drv.c | 851
drivers/net/wireless/ar6000/credit_dist.c | 357
drivers/net/wireless/ar6000/engine.c | 278
drivers/net/wireless/ar6000/hif.c | 718
drivers/net/wireless/ar6000/htc.c | 580
drivers/net/wireless/ar6000/htc_recv.c | 766
drivers/net/wireless/ar6000/htc_send.c | 593
drivers/net/wireless/ar6000/htc_services.c | 412
drivers/net/wireless/ar6000/include/AR6000/ar6k.h | 199
drivers/net/wireless/ar6000/include/AR6002/AR6002_regdump.h | 59
drivers/net/wireless/ar6000/include/AR6002/AR6K_version.h | 52
drivers/net/wireless/ar6000/include/AR6002/addrs.h | 63
drivers/net/wireless/ar6000/include/AR6002/hw/mbox_host_reg.h | 409
drivers/net/wireless/ar6000/include/a_config.h | 41
drivers/net/wireless/ar6000/include/a_debug.h | 53
drivers/net/wireless/ar6000/include/a_drv.h | 42
drivers/net/wireless/ar6000/include/a_drv_api.h | 198
drivers/net/wireless/ar6000/include/a_osapi.h | 47
drivers/net/wireless/ar6000/include/a_types.h | 42
drivers/net/wireless/ar6000/include/ar6000_api.h | 42
drivers/net/wireless/ar6000/include/ar6000_diag.h | 42
drivers/net/wireless/ar6000/include/ar6k.h | 199
drivers/net/wireless/ar6000/include/athdefs.h | 102
drivers/net/wireless/ar6000/include/athdrv.h | 35
drivers/net/wireless/ar6000/include/athendpack.h | 44
drivers/net/wireless/ar6000/include/athstartpack.h | 44
drivers/net/wireless/ar6000/include/bmi.h | 115
drivers/net/wireless/ar6000/include/bmi_internal.h | 50
drivers/net/wireless/ar6000/include/bmi_msg.h | 234
drivers/net/wireless/ar6000/include/common_drv.h | 79
drivers/net/wireless/ar6000/include/dbglog.h | 128
drivers/net/wireless/ar6000/include/dbglog_api.h | 52
drivers/net/wireless/ar6000/include/dl_list.h | 118
drivers/net/wireless/ar6000/include/dset_api.h | 65
drivers/net/wireless/ar6000/include/gpio.h | 49
drivers/net/wireless/ar6000/include/gpio_api.h | 59
drivers/net/wireless/ar6000/include/hif.h | 317
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drivers/net/wireless/ar6000/include/host_version.h | 52
drivers/net/wireless/ar6000/include/htc.h | 204
drivers/net/wireless/ar6000/include/htc_api.h | 474
drivers/net/wireless/ar6000/include/htc_internal.h | 176
drivers/net/wireless/ar6000/include/htc_packet.h | 160
drivers/net/wireless/ar6000/include/htc_services.h | 52
drivers/net/wireless/ar6000/include/ieee80211.h | 344
drivers/net/wireless/ar6000/include/ieee80211_node.h | 85
drivers/net/wireless/ar6000/include/regdump.h | 49
drivers/net/wireless/ar6000/include/roaming.h | 41
drivers/net/wireless/ar6000/include/targaddrs.h | 175
drivers/net/wireless/ar6000/include/testcmd.h | 163
drivers/net/wireless/ar6000/include/wlan_api.h | 110
drivers/net/wireless/ar6000/include/wmi.h | 1871
drivers/net/wireless/ar6000/include/wmi_api.h | 289
drivers/net/wireless/ar6000/include/wmi_host.h | 77
drivers/net/wireless/ar6000/include/wmix.h | 279
drivers/net/wireless/ar6000/ioctl.c | 2756 +
drivers/net/wireless/ar6000/netbuf.c | 229
drivers/net/wireless/ar6000/os/linux/include/ar6000_drv.h | 377
drivers/net/wireless/ar6000/os/linux/include/ar6xapi_linux.h | 143
drivers/net/wireless/ar6000/os/linux/include/athdrv_linux.h | 1053
drivers/net/wireless/ar6000/os/linux/include/athtypes_linux.h | 49
drivers/net/wireless/ar6000/os/linux/include/config_linux.h | 54
drivers/net/wireless/ar6000/os/linux/include/debug_linux.h | 90
drivers/net/wireless/ar6000/os/linux/include/engine.h | 97
drivers/net/wireless/ar6000/os/linux/include/ieee80211_ioctl.h | 165
drivers/net/wireless/ar6000/os/linux/include/osapi_linux.h | 331
drivers/net/wireless/ar6000/wireless_ext.c | 2313 +
drivers/net/wireless/ar6000/wlan_node.c | 467
drivers/net/wireless/ar6000/wlan_recv_beacon.c | 185
drivers/net/wireless/ar6000/wlan_utils.c | 61
drivers/net/wireless/ar6000/wmi.c | 4780 ++
drivers/net/wireless/ath6k/AR6002_regdump.h | 59
drivers/net/wireless/ath6k/AR6K_version.h | 52
drivers/net/wireless/ath6k/AR6K_version.h.NEW | 38
drivers/net/wireless/ath6k/Kconfig | 14
drivers/net/wireless/ath6k/Makefile | 20
drivers/net/wireless/ath6k/README.txt | 3
drivers/net/wireless/ath6k/a_config.h | 45
drivers/net/wireless/ath6k/a_debug.h | 59
drivers/net/wireless/ath6k/a_drv.h | 46
drivers/net/wireless/ath6k/a_drv_api.h | 207
drivers/net/wireless/ath6k/a_osapi.h | 56
drivers/net/wireless/ath6k/a_pyxis.h | 60
drivers/net/wireless/ath6k/a_types.h | 46
drivers/net/wireless/ath6k/addrs.h | 85
drivers/net/wireless/ath6k/analog_intf_reg.h | 87
drivers/net/wireless/ath6k/analog_reg.h | 1955
drivers/net/wireless/ath6k/apb_map.h | 36
drivers/net/wireless/ath6k/ar6000_api.h | 46
drivers/net/wireless/ath6k/ar6000_diag.h | 42
drivers/net/wireless/ath6k/ar6000_drv.c | 4300 +
drivers/net/wireless/ath6k/ar6000_drv.h | 444
drivers/net/wireless/ath6k/ar6000_raw_if.c | 443
drivers/net/wireless/ath6k/ar6k.c | 1033
drivers/net/wireless/ath6k/ar6k.h | 206
drivers/net/wireless/ath6k/ar6k_events.c | 665
drivers/net/wireless/ath6k/ar6kap_common.h | 40
drivers/net/wireless/ath6k/ar6xapi_linux.h | 158
drivers/net/wireless/ath6k/athbtfilter.h | 131
drivers/net/wireless/ath6k/athdefs.h | 84
drivers/net/wireless/ath6k/athdrv.h | 35
drivers/net/wireless/ath6k/athdrv_linux.h | 1091
drivers/net/wireless/ath6k/athendpack.h | 49
drivers/net/wireless/ath6k/athstartpack.h | 48
drivers/net/wireless/ath6k/athtypes_linux.h | 56
drivers/net/wireless/ath6k/bmi.c | 879
drivers/net/wireless/ath6k/bmi.h | 115
drivers/net/wireless/ath6k/bmi_internal.h | 51
drivers/net/wireless/ath6k/bmi_msg.h | 235
drivers/net/wireless/ath6k/cnxmgmt.h | 33
drivers/net/wireless/ath6k/common_drv.c | 663
drivers/net/wireless/ath6k/common_drv.h | 79
drivers/net/wireless/ath6k/config_linux.h | 51
drivers/net/wireless/ath6k/credit_dist.c | 373
drivers/net/wireless/ath6k/dbglog.h | 126
drivers/net/wireless/ath6k/dbglog_api.h | 52
drivers/net/wireless/ath6k/dbglog_id.h | 491
drivers/net/wireless/ath6k/debug_linux.h | 89
drivers/net/wireless/ath6k/discovery.h | 74
drivers/net/wireless/ath6k/dl_list.h | 119
drivers/net/wireless/ath6k/dset_api.h | 65
drivers/net/wireless/ath6k/dset_internal.h | 55
drivers/net/wireless/ath6k/dsetid.h | 126
drivers/net/wireless/ath6k/eeprom.c | 586
drivers/net/wireless/ath6k/engine.c | 278
drivers/net/wireless/ath6k/engine.h | 75
drivers/net/wireless/ath6k/gpio.h | 49
drivers/net/wireless/ath6k/gpio_api.h | 59
drivers/net/wireless/ath6k/gpio_reg.h | 1000
drivers/net/wireless/ath6k/hif.c | 737
drivers/net/wireless/ath6k/hif.h | 323
drivers/net/wireless/ath6k/hif_internal.h | 89
drivers/net/wireless/ath6k/host_version.h | 52
drivers/net/wireless/ath6k/htc.c | 525
drivers/net/wireless/ath6k/htc.h | 204
drivers/net/wireless/ath6k/htc_api.h | 463
drivers/net/wireless/ath6k/htc_debug.h | 69
drivers/net/wireless/ath6k/htc_internal.h | 177
drivers/net/wireless/ath6k/htc_packet.h | 162
drivers/net/wireless/ath6k/htc_recv.c | 785
drivers/net/wireless/ath6k/htc_send.c | 612
drivers/net/wireless/ath6k/htc_services.c | 412
drivers/net/wireless/ath6k/htc_services.h | 52
drivers/net/wireless/ath6k/ieee80211.h | 404
drivers/net/wireless/ath6k/ieee80211_ioctl.h | 173
drivers/net/wireless/ath6k/ieee80211_node.h | 85
drivers/net/wireless/ath6k/ini_dset.h | 90
drivers/net/wireless/ath6k/ioctl.c | 3381 +
drivers/net/wireless/ath6k/mbox_host_reg.h | 409
drivers/net/wireless/ath6k/mbox_reg.h | 504
drivers/net/wireless/ath6k/netbuf.c | 229
drivers/net/wireless/ath6k/osapi_linux.h | 333
drivers/net/wireless/ath6k/regDb.h | 30
drivers/net/wireless/ath6k/reg_dbschema.h | 211
drivers/net/wireless/ath6k/reg_dbvalues.h | 476
drivers/net/wireless/ath6k/regdump.h | 49
drivers/net/wireless/ath6k/roaming.h | 41
drivers/net/wireless/ath6k/rtc_reg.h | 1186
drivers/net/wireless/ath6k/si_reg.h | 209
drivers/net/wireless/ath6k/targaddrs.h | 202
drivers/net/wireless/ath6k/testcmd.h | 165
drivers/net/wireless/ath6k/uart_reg.h | 350
drivers/net/wireless/ath6k/vmc_reg.h | 99
drivers/net/wireless/ath6k/wireless_ext.c | 2077
drivers/net/wireless/ath6k/wlan_api.h | 119
drivers/net/wireless/ath6k/wlan_defs.h | 55
drivers/net/wireless/ath6k/wlan_dset.h | 34
drivers/net/wireless/ath6k/wlan_node.c | 470
drivers/net/wireless/ath6k/wlan_recv_beacon.c | 203
drivers/net/wireless/ath6k/wlan_utils.c | 61
drivers/net/wireless/ath6k/wmi.c | 5805 ++
drivers/net/wireless/ath6k/wmi.h | 2263 +
drivers/net/wireless/ath6k/wmi_api.h | 367
drivers/net/wireless/ath6k/wmi_filter_linux.h | 246
drivers/net/wireless/ath6k/wmi_host.h | 80
drivers/net/wireless/ath6k/wmix.h | 279
drivers/net/wireless/ath6k22.133/AR6002_regdump.h | 59
drivers/net/wireless/ath6k22.133/AR6K_version.h | 52
drivers/net/wireless/ath6k22.133/Makefile | 37
drivers/net/wireless/ath6k22.133/a_config.h | 46
drivers/net/wireless/ath6k22.133/a_debug.h | 59
drivers/net/wireless/ath6k22.133/a_drv.h | 46
drivers/net/wireless/ath6k22.133/a_drv_api.h | 211
drivers/net/wireless/ath6k22.133/a_osapi.h | 56
drivers/net/wireless/ath6k22.133/a_pyxis.h | 59
drivers/net/wireless/ath6k22.133/a_types.h | 46
drivers/net/wireless/ath6k22.133/addrs.h | 85
drivers/net/wireless/ath6k22.133/analog_intf_reg.h | 87
drivers/net/wireless/ath6k22.133/analog_reg.h | 1955
drivers/net/wireless/ath6k22.133/apb_map.h | 36
drivers/net/wireless/ath6k22.133/ar6000_api.h | 46
drivers/net/wireless/ath6k22.133/ar6000_diag.h | 42
drivers/net/wireless/ath6k22.133/ar6000_drv.c | 4917 ++
drivers/net/wireless/ath6k22.133/ar6000_drv.h | 451
drivers/net/wireless/ath6k22.133/ar6000_raw_if.c | 442
drivers/net/wireless/ath6k22.133/ar6k.c | 1033
drivers/net/wireless/ath6k22.133/ar6k.h | 206
drivers/net/wireless/ath6k22.133/ar6k_events.c | 665
drivers/net/wireless/ath6k22.133/ar6kap_common.h | 40
drivers/net/wireless/ath6k22.133/ar6xapi_linux.h | 159
drivers/net/wireless/ath6k22.133/athbtfilter.h | 131
drivers/net/wireless/ath6k22.133/athdefs.h | 84
drivers/net/wireless/ath6k22.133/athdrv.h | 35
drivers/net/wireless/ath6k22.133/athdrv_linux.h | 1089
drivers/net/wireless/ath6k22.133/athendpack.h | 49
drivers/net/wireless/ath6k22.133/athstartpack.h | 48
drivers/net/wireless/ath6k22.133/athtypes_linux.h | 56
drivers/net/wireless/ath6k22.133/bmi.c | 879
drivers/net/wireless/ath6k22.133/bmi.h | 115
drivers/net/wireless/ath6k22.133/bmi_internal.h | 51
drivers/net/wireless/ath6k22.133/bmi_msg.h | 235
drivers/net/wireless/ath6k22.133/cnxmgmt.h | 33
drivers/net/wireless/ath6k22.133/common_drv.c | 663
drivers/net/wireless/ath6k22.133/common_drv.h | 79
drivers/net/wireless/ath6k22.133/config_linux.h | 51
drivers/net/wireless/ath6k22.133/credit_dist.c | 373
drivers/net/wireless/ath6k22.133/dbglog.h | 126
drivers/net/wireless/ath6k22.133/dbglog_api.h | 52
drivers/net/wireless/ath6k22.133/dbglog_id.h | 505
drivers/net/wireless/ath6k22.133/debug_linux.h | 91
drivers/net/wireless/ath6k22.133/discovery.h | 74
drivers/net/wireless/ath6k22.133/dl_list.h | 119
drivers/net/wireless/ath6k22.133/dset_api.h | 65
drivers/net/wireless/ath6k22.133/dset_internal.h | 55
drivers/net/wireless/ath6k22.133/dsetid.h | 126
drivers/net/wireless/ath6k22.133/eeprom.c | 588
drivers/net/wireless/ath6k22.133/engine.c | 278
drivers/net/wireless/ath6k22.133/engine.h | 75
drivers/net/wireless/ath6k22.133/gpio.h | 49
drivers/net/wireless/ath6k22.133/gpio_api.h | 59
drivers/net/wireless/ath6k22.133/gpio_reg.h | 1000
drivers/net/wireless/ath6k22.133/hif.c | 753
drivers/net/wireless/ath6k22.133/hif.h | 323
drivers/net/wireless/ath6k22.133/hif_internal.h | 90
drivers/net/wireless/ath6k22.133/host_version.h | 52
drivers/net/wireless/ath6k22.133/htc.c | 525
drivers/net/wireless/ath6k22.133/htc.h | 204
drivers/net/wireless/ath6k22.133/htc_api.h | 463
drivers/net/wireless/ath6k22.133/htc_debug.h | 69
drivers/net/wireless/ath6k22.133/htc_internal.h | 179
drivers/net/wireless/ath6k22.133/htc_packet.h | 162
drivers/net/wireless/ath6k22.133/htc_recv.c | 785
drivers/net/wireless/ath6k22.133/htc_send.c | 612
drivers/net/wireless/ath6k22.133/htc_services.c | 412
drivers/net/wireless/ath6k22.133/htc_services.h | 52
drivers/net/wireless/ath6k22.133/ieee80211.h | 405
drivers/net/wireless/ath6k22.133/ieee80211_ioctl.h | 173
drivers/net/wireless/ath6k22.133/ieee80211_node.h | 90
drivers/net/wireless/ath6k22.133/ini_dset.h | 90
drivers/net/wireless/ath6k22.133/ioctl.c | 3484 +
drivers/net/wireless/ath6k22.133/mbox_host_reg.h | 409
drivers/net/wireless/ath6k22.133/mbox_reg.h | 504
drivers/net/wireless/ath6k22.133/miscdrv.h | 44
drivers/net/wireless/ath6k22.133/netbuf.c | 229
drivers/net/wireless/ath6k22.133/osapi_linux.h | 333
drivers/net/wireless/ath6k22.133/regDb.h | 30
drivers/net/wireless/ath6k22.133/regTableData.h | 456
drivers/net/wireless/ath6k22.133/reg_dbschema.h | 211
drivers/net/wireless/ath6k22.133/reg_dbvalues.h | 477
drivers/net/wireless/ath6k22.133/regdump.h | 49
drivers/net/wireless/ath6k22.133/roaming.h | 41
drivers/net/wireless/ath6k22.133/rtc_reg.h | 1186
drivers/net/wireless/ath6k22.133/si_reg.h | 209
drivers/net/wireless/ath6k22.133/targaddrs.h | 202
drivers/net/wireless/ath6k22.133/testcmd.h | 165
drivers/net/wireless/ath6k22.133/uart_reg.h | 350
drivers/net/wireless/ath6k22.133/vmc_reg.h | 99
drivers/net/wireless/ath6k22.133/wireless_ext.c | 2340 +
drivers/net/wireless/ath6k22.133/wlan_api.h | 119
drivers/net/wireless/ath6k22.133/wlan_defs.h | 55
drivers/net/wireless/ath6k22.133/wlan_dset.h | 34
drivers/net/wireless/ath6k22.133/wlan_node.c | 470
drivers/net/wireless/ath6k22.133/wlan_recv_beacon.c | 207
drivers/net/wireless/ath6k22.133/wlan_utils.c | 61
drivers/net/wireless/ath6k22.133/wmi.c | 5879 ++
drivers/net/wireless/ath6k22.133/wmi.h | 2256 +
drivers/net/wireless/ath6k22.133/wmi_api.h | 368
drivers/net/wireless/ath6k22.133/wmi_filter_linux.h | 250
drivers/net/wireless/ath6k22.133/wmi_host.h | 82
drivers/net/wireless/ath6k22.133/wmix.h | 279
drivers/net/wireless/ath6k22/AR6002_regdump.h | 59
drivers/net/wireless/ath6k22/AR6K_version.h | 52
drivers/net/wireless/ath6k22/Makefile | 20
drivers/net/wireless/ath6k22/a_config.h | 45
drivers/net/wireless/ath6k22/a_debug.h | 59
drivers/net/wireless/ath6k22/a_drv.h | 46
drivers/net/wireless/ath6k22/a_drv_api.h | 211
drivers/net/wireless/ath6k22/a_osapi.h | 56
drivers/net/wireless/ath6k22/a_pyxis.h | 60
drivers/net/wireless/ath6k22/a_types.h | 46
drivers/net/wireless/ath6k22/addrs.h | 85
drivers/net/wireless/ath6k22/analog_intf_reg.h | 87
drivers/net/wireless/ath6k22/analog_reg.h | 1955
drivers/net/wireless/ath6k22/apb_map.h | 36
drivers/net/wireless/ath6k22/ar6000_api.h | 46
drivers/net/wireless/ath6k22/ar6000_diag.h | 42
drivers/net/wireless/ath6k22/ar6000_drv.c | 4475 ++
drivers/net/wireless/ath6k22/ar6000_drv.h | 447
drivers/net/wireless/ath6k22/ar6000_raw_if.c | 443
drivers/net/wireless/ath6k22/ar6k.c | 1033
drivers/net/wireless/ath6k22/ar6k.h | 206
drivers/net/wireless/ath6k22/ar6k_events.c | 665
drivers/net/wireless/ath6k22/ar6kap_common.h | 40
drivers/net/wireless/ath6k22/ar6xapi_linux.h | 159
drivers/net/wireless/ath6k22/athbtfilter.h | 131
drivers/net/wireless/ath6k22/athdefs.h | 84
drivers/net/wireless/ath6k22/athdrv.h | 35
drivers/net/wireless/ath6k22/athdrv_linux.h | 1091
drivers/net/wireless/ath6k22/athendpack.h | 49
drivers/net/wireless/ath6k22/athstartpack.h | 48
drivers/net/wireless/ath6k22/athtypes_linux.h | 56
drivers/net/wireless/ath6k22/bmi.c | 879
drivers/net/wireless/ath6k22/bmi.h | 115
drivers/net/wireless/ath6k22/bmi_internal.h | 51
drivers/net/wireless/ath6k22/bmi_msg.h | 235
drivers/net/wireless/ath6k22/cnxmgmt.h | 33
drivers/net/wireless/ath6k22/common_drv.c | 663
drivers/net/wireless/ath6k22/common_drv.h | 79
drivers/net/wireless/ath6k22/config_linux.h | 51
drivers/net/wireless/ath6k22/credit_dist.c | 373
drivers/net/wireless/ath6k22/dbglog.h | 126
drivers/net/wireless/ath6k22/dbglog_api.h | 52
drivers/net/wireless/ath6k22/dbglog_id.h | 505
drivers/net/wireless/ath6k22/debug_linux.h | 92
drivers/net/wireless/ath6k22/discovery.h | 74
drivers/net/wireless/ath6k22/dl_list.h | 119
drivers/net/wireless/ath6k22/dset_api.h | 65
drivers/net/wireless/ath6k22/dset_internal.h | 55
drivers/net/wireless/ath6k22/dsetid.h | 126
drivers/net/wireless/ath6k22/eeprom.c | 588
drivers/net/wireless/ath6k22/engine.c | 278
drivers/net/wireless/ath6k22/engine.h | 75
drivers/net/wireless/ath6k22/gpio.h | 49
drivers/net/wireless/ath6k22/gpio_api.h | 59
drivers/net/wireless/ath6k22/gpio_reg.h | 1000
drivers/net/wireless/ath6k22/hif.c | 739
drivers/net/wireless/ath6k22/hif.h | 323
drivers/net/wireless/ath6k22/hif_internal.h | 89
drivers/net/wireless/ath6k22/host_version.h | 52
drivers/net/wireless/ath6k22/htc.c | 525
drivers/net/wireless/ath6k22/htc.h | 204
drivers/net/wireless/ath6k22/htc_api.h | 463
drivers/net/wireless/ath6k22/htc_debug.h | 69
drivers/net/wireless/ath6k22/htc_internal.h | 177
drivers/net/wireless/ath6k22/htc_packet.h | 162
drivers/net/wireless/ath6k22/htc_recv.c | 785
drivers/net/wireless/ath6k22/htc_send.c | 612
drivers/net/wireless/ath6k22/htc_services.c | 412
drivers/net/wireless/ath6k22/htc_services.h | 52
drivers/net/wireless/ath6k22/ieee80211.h | 404
drivers/net/wireless/ath6k22/ieee80211_ioctl.h | 173
drivers/net/wireless/ath6k22/ieee80211_node.h | 85
drivers/net/wireless/ath6k22/ini_dset.h | 90
drivers/net/wireless/ath6k22/ioctl.c | 3466 +
drivers/net/wireless/ath6k22/mbox_host_reg.h | 409
drivers/net/wireless/ath6k22/mbox_reg.h | 504
drivers/net/wireless/ath6k22/miscdrv.h | 44
drivers/net/wireless/ath6k22/netbuf.c | 229
drivers/net/wireless/ath6k22/osapi_linux.h | 333
drivers/net/wireless/ath6k22/regDb.h | 30
drivers/net/wireless/ath6k22/regdump.h | 49
drivers/net/wireless/ath6k22/roaming.h | 41
drivers/net/wireless/ath6k22/rtc_reg.h | 1186
drivers/net/wireless/ath6k22/si_reg.h | 209
drivers/net/wireless/ath6k22/targaddrs.h | 202
drivers/net/wireless/ath6k22/testcmd.h | 165
drivers/net/wireless/ath6k22/uart_reg.h | 350
drivers/net/wireless/ath6k22/vmc_reg.h | 99
drivers/net/wireless/ath6k22/wireless_ext.c | 2240 +
drivers/net/wireless/ath6k22/wlan_api.h | 119
drivers/net/wireless/ath6k22/wlan_defs.h | 55
drivers/net/wireless/ath6k22/wlan_dset.h | 34
drivers/net/wireless/ath6k22/wlan_node.c | 470
drivers/net/wireless/ath6k22/wlan_recv_beacon.c | 207
drivers/net/wireless/ath6k22/wlan_utils.c | 61
drivers/net/wireless/ath6k22/wmi.c | 5873 ++
drivers/net/wireless/ath6k22/wmi.h | 2255 +
drivers/net/wireless/ath6k22/wmi_api.h | 367
drivers/net/wireless/ath6k22/wmi_filter_linux.h | 250
drivers/net/wireless/ath6k22/wmi_host.h | 82
drivers/net/wireless/ath6k22/wmix.h | 279
drivers/of/base.c | 2
drivers/oprofile/oprofilefs.c | 2
drivers/pci/.gitignore | 4
drivers/pci/access.c | 2
drivers/pci/hotplug/ibmphp_hpc.c | 2
drivers/pci/msi.c | 16
drivers/pci/pci.c | 36
drivers/pci/probe.c | 4
drivers/pcmcia/Kconfig | 8
drivers/pcmcia/Makefile | 1
drivers/pcmcia/mx31ads-pcmcia.c | 1293
drivers/pcmcia/mx31ads-pcmcia.h | 157
drivers/power/Kconfig | 5
drivers/power/Makefile | 1
drivers/power/luigi_battery.c | 754
drivers/regulator/Kconfig | 77
drivers/regulator/Makefile | 16
drivers/regulator/max8660/Makefile | 1
drivers/regulator/max8660/reg-max8660.c | 899
drivers/regulator/mc13783/Makefile | 5
drivers/regulator/mc13783/reg-mc13783.c | 3235 +
drivers/regulator/mc13892/Makefile | 5
drivers/regulator/mc13892/reg-mc13892.c | 2025
drivers/regulator/mc34704/Makefile | 5
drivers/regulator/mc34704/reg-mc34704.c | 291
drivers/regulator/mc9sdz60/Makefile | 1
drivers/regulator/mc9sdz60/reg-mc9sdz60.c | 203
drivers/regulator/reg-core.c | 844
drivers/regulator/wm8350/Makefile | 5
drivers/regulator/wm8350/reg-wm8350-bus.c | 1525
drivers/regulator/wm8350/reg-wm8350-i2c.c | 185
drivers/regulator/wm8350/reg-wm8350.c | 1014
drivers/rtc/Kconfig | 29
drivers/rtc/Makefile | 4
drivers/rtc/rtc-imxdi.c | 567
drivers/rtc/rtc-lib.c | 5
drivers/rtc/rtc-mc13892.c | 266
drivers/rtc/rtc-mxc.c | 989
drivers/rtc/rtc-mxc_v2.c | 762
drivers/scsi/.gitignore | 1
drivers/scsi/aacraid/aacraid.h | 4
drivers/scsi/aic7xxx/.gitignore | 6
drivers/serial/8250.c | 36
drivers/serial/Kconfig | 25
drivers/serial/Makefile | 2
drivers/serial/mcfserial.c | 121
drivers/serial/mxc_uart.c | 2078
drivers/serial/mxc_uart_early.c | 252
drivers/serial/mxc_uart_reg.h | 128
drivers/spi/Kconfig | 28
drivers/spi/Makefile | 1
drivers/spi/mxc_spi.c | 1252
drivers/usb/Kconfig | 2
drivers/usb/Makefile | 3
drivers/usb/core/Kconfig | 7
drivers/usb/core/devio.c | 5
drivers/usb/core/driver.c | 23
drivers/usb/core/hcd.c | 25
drivers/usb/core/hub.c | 8
drivers/usb/core/message.c | 13
drivers/usb/gadget/Kconfig | 118
drivers/usb/gadget/Makefile | 4
drivers/usb/gadget/arcotg_udc.c | 4945 ++
drivers/usb/gadget/arcotg_udc.h | 686
drivers/usb/gadget/epautoconf.c | 6
drivers/usb/gadget/ether.c | 15
drivers/usb/gadget/file_storage.c | 147
drivers/usb/gadget/gadget_chips.h | 8
drivers/usb/gadget/inode.c | 115
drivers/usb/gadget/serial.c | 2
drivers/usb/host/Kconfig | 107
drivers/usb/host/ehci-arc.c | 772
drivers/usb/host/ehci-fsl.h | 14
drivers/usb/host/ehci-hcd.c | 650
drivers/usb/host/ehci-hub.c | 46
drivers/usb/host/ehci-mem-iram.c | 506
drivers/usb/host/ehci-q-iram.c | 1345
drivers/usb/host/ehci-q.c | 2
drivers/usb/host/ehci-sched.c | 68
drivers/usb/host/ehci.h | 24
drivers/usb/host/isp1760-hcd.c | 4
drivers/usb/otg/Kconfig | 5
drivers/usb/otg/Makefile | 7
drivers/usb/otg/fsl_otg.c | 1200
drivers/usb/otg/fsl_otg.h | 410
drivers/usb/otg/otg_fsm.c | 371
drivers/usb/otg/otg_fsm.h | 151
drivers/usb/serial/option.c | 122
drivers/usb/serial/usb-serial.c | 12
drivers/usb/storage/usb.h | 2
drivers/usb/usblan/Kconfig | 24
drivers/usb/usblan/Makefile | 8
drivers/usb/usblan/usblan-compat.h | 286
drivers/usb/usblan/usblan.c | 3045 +
drivers/usb/usblan/usblan.h | 84
drivers/video/Kconfig | 9
drivers/video/Makefile | 3
drivers/video/backlight/Kconfig | 33
drivers/video/backlight/Makefile | 6
drivers/video/backlight/mxc_ipu_bl.c | 155
drivers/video/backlight/mxc_lcdc_bl.c | 160
drivers/video/backlight/mxc_mc13892_bl.c | 171
drivers/video/backlight/mxc_pmic_bl.c | 197
drivers/video/backlight/wm8350_bl.c | 303
drivers/video/console/fbcon.c | 5
drivers/video/console/vgacon.c | 2
drivers/video/eink/Kconfig | 62
drivers/video/eink/Makefile | 12
drivers/video/eink/auo/auo.c | 850
drivers/video/eink/auo/auo.h | 54
drivers/video/eink/auo/auo_def.h | 244
drivers/video/eink/auo/auo_hal.c | 496
drivers/video/eink/auo/auo_mxc.c | 42
drivers/video/eink/broadsheet/broadsheet.c | 4992 ++
drivers/video/eink/broadsheet/broadsheet.h | 335
drivers/video/eink/broadsheet/broadsheet_commands.c | 155
drivers/video/eink/broadsheet/broadsheet_commands.h | 55
drivers/video/eink/broadsheet/broadsheet_def.h | 591
drivers/video/eink/broadsheet/broadsheet_eeprom.c | 223
drivers/video/eink/broadsheet/broadsheet_eeprom.h | 44
drivers/video/eink/broadsheet/broadsheet_hal.c | 1495
drivers/video/eink/broadsheet/broadsheet_mxc.c | 101
drivers/video/eink/broadsheet/broadsheet_papyrus.c | 505
drivers/video/eink/broadsheet/broadsheet_papyrus.h | 72
drivers/video/eink/broadsheet/broadsheet_pmic.c | 302
drivers/video/eink/broadsheet/broadsheet_waveform.c | 434
drivers/video/eink/broadsheet/broadsheet_waveform.h | 105
drivers/video/eink/broadsheet/platform_waveform.c | 130
drivers/video/eink/broadsheet/platform_waveform.h | 52
drivers/video/eink/emulator/emulator_hal.c | 217
drivers/video/eink/hal/Makefile | 34
drivers/video/eink/hal/einkfb_hal.h | 616
drivers/video/eink/hal/einkfb_hal_builtin_base.c | 30
drivers/video/eink/hal/einkfb_hal_events.c | 181
drivers/video/eink/hal/einkfb_hal_io.c | 554
drivers/video/eink/hal/einkfb_hal_main.c | 952
drivers/video/eink/hal/einkfb_hal_mem.c | 185
drivers/video/eink/hal/einkfb_hal_pm.c | 505
drivers/video/eink/hal/einkfb_hal_proc.c | 783
drivers/video/eink/hal/einkfb_hal_util.c | 1505
drivers/video/eink/legacy/Makefile | 3
drivers/video/eink/legacy/einkfb_shim.c | 2334 +
drivers/video/eink/legacy/einkfb_shim.h | 133
drivers/video/eink/legacy/einkfb_shim_mario.c | 535
drivers/video/eink/legacy/einksp.h | 3822 +
drivers/video/eink/legacy/einksp_mario.h | 3826 +
drivers/video/fb_defio.c | 12
drivers/video/logo/.gitignore | 7
drivers/video/mxc/Kconfig | 82
drivers/video/mxc/Makefile | 21
drivers/video/mxc/ch7024.c | 866
drivers/video/mxc/fs453.c | 494
drivers/video/mxc/fs453.h | 134
drivers/video/mxc/mx2fb.c | 1347
drivers/video/mxc/mx2fb.h | 141
drivers/video/mxc/mx2fb_epson.c | 2173
drivers/video/mxc/mxc_ipuv3_fb.c | 1061
drivers/video/mxc/mxcfb.c | 1481
drivers/video/mxc/mxcfb_claa_wvga.c | 234
drivers/video/mxc/mxcfb_epson.c | 1158
drivers/video/mxc/mxcfb_epson_qvga.c | 1146
drivers/video/mxc/mxcfb_epson_vga.c | 357
drivers/video/mxc/mxcfb_modedb.c | 69
drivers/video/mxc/mxcfb_sharp_128x128.c | 1167
drivers/video/mxc/mxcfb_toshiba_qvga.c | 1202
drivers/video/mxc/tve.c | 709
drivers/w1/masters/Kconfig | 6
drivers/w1/masters/Makefile | 2
drivers/w1/masters/mxc_w1.c | 432
drivers/w1/slaves/Kconfig | 22
drivers/w1/slaves/Makefile | 3
drivers/w1/slaves/w1_ds2438.c | 585
drivers/w1/slaves/w1_ds2438.h | 119
drivers/w1/slaves/w1_ds2751.c | 317
drivers/w1/w1_family.h | 2
drivers/watchdog/Kconfig | 12
drivers/watchdog/Makefile | 1
drivers/watchdog/mxc_wdt.c | 465
drivers/watchdog/mxc_wdt.h | 38
fs/Kconfig | 101
fs/Makefile | 1
fs/aio.c | 4
fs/block_dev.c | 36
fs/buffer.c | 55
fs/dcache.c | 5
fs/debugfs/inode.c | 114
fs/dnotify.c | 2
fs/drop_caches.c | 2
fs/exec.c | 5
fs/ext3/inode.c | 23
fs/ext4/acl.c | 182
fs/ext4/balloc.c | 221
fs/ext4/dir.c | 37
fs/ext4/ext4.h | 64
fs/ext4/ext4_extents.h | 5
fs/ext4/ext4_i.h | 10
fs/ext4/ext4_jbd2.h | 29
fs/ext4/ext4_sb.h | 5
fs/ext4/extents.c | 277
fs/ext4/file.c | 20
fs/ext4/fsync.c | 4
fs/ext4/group.h | 2
fs/ext4/ialloc.c | 171
fs/ext4/inode.c | 1927
fs/ext4/mballoc.c | 744
fs/ext4/mballoc.h | 10
fs/ext4/migrate.c | 3
fs/ext4/namei.c | 45
fs/ext4/resize.c | 134
fs/ext4/super.c | 451
fs/ext4/xattr.c | 4
fs/ext4/xattr_trusted.c | 4
fs/ext4/xattr_user.c | 4
fs/fat/Kconfig | 98
fs/fat/inode.c | 11
fs/fat/misc.c | 12
fs/file.c | 5
fs/file_table.c | 34
fs/fs-writeback.c | 22
fs/gfs2/glock.c | 2
fs/gfs2/glops.c | 4
fs/gfs2/meta_io.c | 2
fs/hugetlbfs/inode.c | 2
fs/inode.c | 12
fs/ioprio.c | 3
fs/jbd/commit.c | 6
fs/jbd/journal.c | 3
fs/jbd/transaction.c | 6
fs/jbd2/checkpoint.c | 1
fs/jbd2/commit.c | 304
fs/jbd2/journal.c | 54
fs/jbd2/transaction.c | 365
fs/jffs2/dir.c | 4
fs/jffs2/fs.c | 8
fs/jffs2/os-linux.h | 2
fs/jffs2/scan.c | 24
fs/libfs.c | 2
fs/mpage.c | 14
fs/namespace.c | 22
fs/nfs/inode.c | 6
fs/nfs/iostat.h | 4
fs/ntfs/aops.c | 13
fs/pipe.c | 22
fs/proc/Makefile | 2
fs/proc/array.c | 27
fs/proc/generic.c | 2
fs/proc/proc_misc.c | 138
fs/proc/softirqs.c | 49
fs/proc/task_mmu.c | 4
fs/select.c | 18
fs/super.c | 14
fs/sysfs/file.c | 13
fs/ubifs/Kconfig | 72
fs/ubifs/Makefile | 9
fs/ubifs/budget.c | 814
fs/ubifs/commit.c | 677
fs/ubifs/compress.c | 251
fs/ubifs/debug.c | 2347 +
fs/ubifs/debug.h | 404
fs/ubifs/dir.c | 1240
fs/ubifs/file.c | 1549
fs/ubifs/find.c | 977
fs/ubifs/gc.c | 849
fs/ubifs/io.c | 934
fs/ubifs/ioctl.c | 204
fs/ubifs/journal.c | 1382
fs/ubifs/key.h | 553
fs/ubifs/log.c | 807
fs/ubifs/lprops.c | 1325
fs/ubifs/lpt.c | 2275 +
fs/ubifs/lpt_commit.c | 1813
fs/ubifs/master.c | 387
fs/ubifs/misc.h | 340
fs/ubifs/orphan.c | 962
fs/ubifs/recovery.c | 1520
fs/ubifs/replay.c | 1075
fs/ubifs/sb.c | 630
fs/ubifs/scan.c | 362
fs/ubifs/shrinker.c | 322
fs/ubifs/super.c | 2033
fs/ubifs/tnc.c | 3262 +
fs/ubifs/tnc_commit.c | 1102
fs/ubifs/tnc_misc.c | 494
fs/ubifs/ubifs-media.h | 751
fs/ubifs/ubifs.h | 1716
fs/ubifs/xattr.c | 571
fs/xfs/linux-2.6/mrlock.h | 2
fs/xfs/linux-2.6/sema.h | 9
fs/xfs/linux-2.6/xfs_buf.h | 4
fs/xfs/linux-2.6/xfs_fs_subr.c | 4
fs/xfs/linux-2.6/xfs_lrw.c | 7
fs/xfs/linux-2.6/xfs_vnode.h | 2
fs/xfs/xfs_mount.h | 2
include/acpi/acglobal.h | 7
include/acpi/acpiosxf.h | 2
include/asm-arm/.gitignore | 2
include/asm-arm/arch-ep93xx/timex.h | 6
include/asm-arm/arch-mxc/arc_otg.h | 339
include/asm-arm/arch-mxc/audio_controls.h | 220
include/asm-arm/arch-mxc/board_id.h | 39
include/asm-arm/arch-mxc/boot_globals.h | 461
include/asm-arm/arch-mxc/clock.h | 91
include/asm-arm/arch-mxc/controller_common.c | 115
include/asm-arm/arch-mxc/controller_common.h | 239
include/asm-arm/arch-mxc/controller_common_display.c | 79
include/asm-arm/arch-mxc/controller_common_mxc.c | 459
include/asm-arm/arch-mxc/dam.h | 258
include/asm-arm/arch-mxc/debug-macro.S | 57
include/asm-arm/arch-mxc/dma.h | 279
include/asm-arm/arch-mxc/dptc.h | 186
include/asm-arm/arch-mxc/dvfs_dptc_struct.h | 169
include/asm-arm/arch-mxc/entry-macro.S | 31
include/asm-arm/arch-mxc/fsl_usb.h | 79
include/asm-arm/arch-mxc/fsl_usb_gadget.h | 40
include/asm-arm/arch-mxc/gpio.h | 167
include/asm-arm/arch-mxc/hardware.h | 136
include/asm-arm/arch-mxc/hw_events.h | 65
include/asm-arm/arch-mxc/ide.h | 55
include/asm-arm/arch-mxc/iim.h | 71
include/asm-arm/arch-mxc/imx_adc.h | 275
include/asm-arm/arch-mxc/io.h | 27
include/asm-arm/arch-mxc/ipu.h | 1108
include/asm-arm/arch-mxc/ipu_regs.h | 396
include/asm-arm/arch-mxc/irqs.h | 18
include/asm-arm/arch-mxc/memory.h | 54
include/asm-arm/arch-mxc/mmc.h | 35
include/asm-arm/arch-mxc/mtd-xip.h | 52
include/asm-arm/arch-mxc/mx21.h | 303
include/asm-arm/arch-mxc/mx27.h | 336
include/asm-arm/arch-mxc/mx2_dma.h | 261
include/asm-arm/arch-mxc/mx31.h | 215
include/asm-arm/arch-mxc/mx35.h | 475
include/asm-arm/arch-mxc/mx37.h | 509
include/asm-arm/arch-mxc/mx51.h | 521
include/asm-arm/arch-mxc/mxc.h | 486
include/asm-arm/arch-mxc/mxc_dptc.h | 111
include/asm-arm/arch-mxc/mxc_gpc.h | 74
include/asm-arm/arch-mxc/mxc_pm.h | 252
include/asm-arm/arch-mxc/mxc_scc.h | 45
include/asm-arm/arch-mxc/mxc_security_api.h | 700
include/asm-arm/arch-mxc/mxc_uart.h | 275
include/asm-arm/arch-mxc/mxc_vpu.h | 92
include/asm-arm/arch-mxc/pcmcia.h | 218
include/asm-arm/arch-mxc/pm_api.h | 353
include/asm-arm/arch-mxc/pmic_audio.h | 2315 +
include/asm-arm/arch-mxc/pmic_convity.h | 873
include/asm-arm/arch-mxc/pmic_power.h | 1358
include/asm-arm/arch-mxc/sdma.h | 559
include/asm-arm/arch-mxc/spba.h | 66
include/asm-arm/arch-mxc/system.h | 23
include/asm-arm/arch-mxc/timex.h | 1
include/asm-arm/arch-mxc/uncompress.h | 2
include/asm-arm/arch-mxc/uncompress1.h | 80
include/asm-arm/arch-pxa/timex.h | 6
include/asm-arm/arch/arc_otg.h | 339
include/asm-arm/arch/audio_controls.h | 220
include/asm-arm/arch/board-mx31ads.h | 112
include/asm-arm/arch/board_id.h | 39
include/asm-arm/arch/boot_globals.h | 461
include/asm-arm/arch/clock.h | 91
include/asm-arm/arch/common.h | 20
include/asm-arm/arch/controller_common.c | 115
include/asm-arm/arch/controller_common.h | 239
include/asm-arm/arch/controller_common_display.c | 79
include/asm-arm/arch/controller_common_mxc.c | 459
include/asm-arm/arch/dam.h | 258
include/asm-arm/arch/debug-macro.S | 57
include/asm-arm/arch/dma.h | 291
include/asm-arm/arch/dptc.h | 186
include/asm-arm/arch/dvfs_dptc_struct.h | 169
include/asm-arm/arch/entry-macro.S | 70
include/asm-arm/arch/fsl_usb.h | 79
include/asm-arm/arch/fsl_usb_gadget.h | 40
include/asm-arm/arch/gpio.h | 167
include/asm-arm/arch/hardware.h | 151
include/asm-arm/arch/hw_events.h | 65
include/asm-arm/arch/ide.h | 55
include/asm-arm/arch/iim.h | 71
include/asm-arm/arch/imx_adc.h | 275
include/asm-arm/arch/io.h | 47
include/asm-arm/arch/ipu.h | 1108
include/asm-arm/arch/ipu_regs.h | 396
include/asm-arm/arch/irqs.h | 39
include/asm-arm/arch/memory.h | 79
include/asm-arm/arch/mmc.h | 35
include/asm-arm/arch/mtd-xip.h | 52
include/asm-arm/arch/mx21.h | 303
include/asm-arm/arch/mx27.h | 336
include/asm-arm/arch/mx2_dma.h | 261
include/asm-arm/arch/mx31.h | 460
include/asm-arm/arch/mx35.h | 475
include/asm-arm/arch/mx37.h | 509
include/asm-arm/arch/mx51.h | 521
include/asm-arm/arch/mxc.h | 442
include/asm-arm/arch/mxc_dptc.h | 111
include/asm-arm/arch/mxc_gpc.h | 74
include/asm-arm/arch/mxc_pm.h | 252
include/asm-arm/arch/mxc_scc.h | 45
include/asm-arm/arch/mxc_security_api.h | 700
include/asm-arm/arch/mxc_uart.h | 275
include/asm-arm/arch/mxc_vpu.h | 92
include/asm-arm/arch/pcmcia.h | 218
include/asm-arm/arch/pm_api.h | 353
include/asm-arm/arch/pmic_audio.h | 2315 +
include/asm-arm/arch/pmic_convity.h | 873
include/asm-arm/arch/pmic_power.h | 1358
include/asm-arm/arch/sdma.h | 559
include/asm-arm/arch/spba.h | 66
include/asm-arm/arch/system.h | 37
include/asm-arm/arch/timex.h | 26
include/asm-arm/arch/uncompress.h | 80
include/asm-arm/arch/uncompress1.h | 80
include/asm-arm/arch/vmalloc.h | 26
include/asm-arm/cacheflush.h | 12
include/asm-arm/dma.h | 2
include/asm-arm/elf.h | 5
include/asm-arm/ftrace.h | 14
include/asm-arm/futex.h | 125
include/asm-arm/hardware/cache-l2x0.h | 3
include/asm-arm/ide.h | 5
include/asm-arm/kgdb.h | 107
include/asm-arm/mach-types.h |22189 ++++++++++
include/asm-arm/mach/keypad.h | 28
include/asm-arm/mach/time.h | 2
include/asm-arm/page.h | 4
include/asm-arm/pgalloc.h | 4
include/asm-arm/pgtable.h | 11
include/asm-arm/ptrace.h | 2
include/asm-arm/setup.h | 12
include/asm-arm/system.h | 5
include/asm-arm/thread_info.h | 2
include/asm-arm/timex.h | 10
include/asm-arm/tlb.h | 9
include/asm-arm/traps.h | 2
include/asm-arm/unistd.h | 9
include/asm-arm/user.h | 9
include/asm-arm26/irq_regs.h | 1
include/asm-blackfin/.gitignore | 1
include/asm-frv/highmem.h | 2
include/asm-generic/bug.h | 16
include/asm-generic/cmpxchg-local.h | 8
include/asm-generic/percpu.h | 18
include/asm-generic/tlb.h | 9
include/asm-generic/vmlinux.lds.h | 57
include/asm-ia64/irqflags.h | 95
include/asm-ia64/mmu_context.h | 2
include/asm-ia64/processor.h | 6
include/asm-ia64/rtc.h | 7
include/asm-ia64/rwsem.h | 32
include/asm-ia64/sal.h | 2
include/asm-ia64/spinlock.h | 26
include/asm-ia64/spinlock_types.h | 4
include/asm-ia64/system.h | 69
include/asm-ia64/tlb.h | 10
include/asm-m68knommu/bitops.h | 30
include/asm-m68knommu/byteorder.h | 16
include/asm-m68knommu/commproc.h | 19
include/asm-m68knommu/m523xsim.h | 147
include/asm-m68knommu/m528xsim.h | 63
include/asm-m68knommu/m532xsim.h | 86
include/asm-m68knommu/system.h | 18
include/asm-mips/asmmacro.h | 8
include/asm-mips/atomic.h | 25
include/asm-mips/bitops.h | 5
include/asm-mips/hw_irq.h | 1
include/asm-mips/i8259.h | 2
include/asm-mips/io.h | 1
include/asm-mips/linkage.h | 5
include/asm-mips/m48t35.h | 2
include/asm-mips/mach-tx49xx/cpu-feature-overrides.h | 7
include/asm-mips/rwsem.h | 176
include/asm-mips/spinlock.h | 18
include/asm-mips/spinlock_types.h | 4
include/asm-mips/system.h | 3
include/asm-mips/time.h | 2
include/asm-mips/timeofday.h | 5
include/asm-mips/uaccess.h | 12
include/asm-mn10300/.gitignore | 2
include/asm-parisc/cacheflush.h | 4
include/asm-powerpc/ftrace.h | 14
include/asm-powerpc/hw_irq.h | 38
include/asm-powerpc/irq.h | 19
include/asm-powerpc/mpic.h | 2
include/asm-powerpc/pgtable-ppc64.h | 9
include/asm-powerpc/pmac_feature.h | 2
include/asm-powerpc/rtas.h | 2
include/asm-powerpc/rwsem.h | 40
include/asm-powerpc/spinlock.h | 50
include/asm-powerpc/spinlock_types.h | 4
include/asm-powerpc/tlb.h | 6
include/asm-powerpc/tlbflush.h | 31
include/asm-ppc/highmem.h | 4
include/asm-sh/.gitignore | 3
include/asm-sparc64/ftrace.h | 14
include/asm-x86/acpi.h | 4
include/asm-x86/alternative.h | 2
include/asm-x86/apic.h | 2
include/asm-x86/atomic_32.h | 4
include/asm-x86/calling.h | 50
include/asm-x86/ftrace.h | 24
include/asm-x86/highmem.h | 27
include/asm-x86/hw_irq_64.h | 2
include/asm-x86/i8253.h | 2
include/asm-x86/i8259.h | 2
include/asm-x86/irqflags.h | 24
include/asm-x86/mach-default/irq_vectors.h | 2
include/asm-x86/nmi.h | 3
include/asm-x86/page_64.h | 9
include/asm-x86/pgalloc.h | 1
include/asm-x86/rwsem.h | 51
include/asm-x86/smp.h | 4
include/asm-x86/spinlock.h | 32
include/asm-x86/spinlock_types.h | 4
include/asm-x86/timer.h | 8
include/asm-x86/tlbflush.h | 24
include/asm-x86/unistd_32.h | 2
include/asm-x86/unistd_64.h | 2
include/asm-x86/vgtod.h | 2
include/asm-x86/vsyscall.h | 3
include/asm-x86/xor_32.h | 19
include/linux/bit_spinlock.h | 4
include/linux/bottom_half.h | 9
include/linux/buffer_head.h | 6
include/linux/compiler.h | 2
include/linux/completion.h | 1
include/linux/console.h | 12
include/linux/debugfs.h | 4
include/linux/einkfb.h | 467
include/linux/etherdevice.h | 5
include/linux/fs.h | 46
include/linux/fsl_devices.h | 66
include/linux/ftrace.h | 330
include/linux/futex.h | 1
include/linux/genhd.h | 15
include/linux/hardirq.h | 80
include/linux/hrtimer.h | 16
include/linux/init.h | 2
include/linux/init_task.h | 26
include/linux/input.h | 26
include/linux/interrupt.h | 104
include/linux/ioport.h | 6
include/linux/ioprio.h | 2
include/linux/ipu.h | 1187
include/linux/irq.h | 27
include/linux/irqflags.h | 54
include/linux/irqnr.h | 23
include/linux/jbd.h | 21
include/linux/jbd2.h | 73
include/linux/kernel.h | 13
include/linux/kernel_stat.h | 14
include/linux/kobject.h | 4
include/linux/kprobes.h | 7
include/linux/list.h | 66
include/linux/lock_list.h | 74
include/linux/lockdep.h | 45
include/linux/mm.h | 32
include/linux/mm_types.h | 3
include/linux/mmc/card.h | 5
include/linux/mmc/core.h | 3
include/linux/mmc/host.h | 19
include/linux/mmc/mmc.h | 1
include/linux/mmc/pm.h | 31
include/linux/mmc/sdio.h | 2
include/linux/mmc/sdio_func.h | 5
include/linux/mmiotrace.h | 85
include/linux/module.h | 17
include/linux/mpage.h | 10
include/linux/mtd/nand.h | 4
include/linux/mtd/ubi.h | 5
include/linux/mutex.h | 79
include/linux/mxc_asrc.h | 206
include/linux/mxc_mlb.h | 51
include/linux/mxc_pf.h | 125
include/linux/mxc_scc2_driver.h | 973
include/linux/mxc_scc_driver.h | 1031
include/linux/mxc_si4702.h | 39
include/linux/mxc_v4l2.h | 42
include/linux/mxcfb.h | 75
include/linux/netdevice.h | 20
include/linux/netfilter/xt_TCPMSS.h | 10
include/linux/netfilter/xt_tcpmss.h | 9
include/linux/netfilter_ipv4/ipt_CONNMARK.h | 19
include/linux/netfilter_ipv4/ipt_MARK.h | 18
include/linux/netfilter_ipv4/ipt_TOS.h | 12
include/linux/netfilter_ipv4/ipt_TTL.h | 21
include/linux/netfilter_ipv4/ipt_connmark.h | 7
include/linux/netfilter_ipv4/ipt_mark.h | 9
include/linux/netfilter_ipv4/ipt_tos.h | 13
include/linux/netfilter_ipv4/ipt_ttl.h | 21
include/linux/netfilter_ipv6/ip6t_HL.h | 22
include/linux/netfilter_ipv6/ip6t_hl.h | 22
include/linux/netpoll.h | 2
include/linux/oprofile.h | 2
include/linux/page-flags.h | 5
include/linux/pagemap.h | 198
include/linux/pagevec.h | 2
include/linux/parport.h | 2
include/linux/pci.h | 6
include/linux/pci_regs.h | 1
include/linux/percpu.h | 40
include/linux/percpu_counter.h | 14
include/linux/percpu_list.h | 119
include/linux/pickop.h | 32
include/linux/platform_lab126.h | 67
include/linux/plist.h | 19
include/linux/pmic_adc.h | 455
include/linux/pmic_battery.h | 419
include/linux/pmic_external.h | 1137
include/linux/pmic_light.h | 1082
include/linux/pmic_rtc.h | 153
include/linux/pmic_status.h | 82
include/linux/posix-timers.h | 2
include/linux/preempt.h | 53
include/linux/profile.h | 13
include/linux/proportions.h | 6
include/linux/pwm.h | 31
include/linux/quicklist.h | 27
include/linux/radix-tree.h | 121
include/linux/rcuclassic.h | 6
include/linux/rcupdate.h | 66
include/linux/rcupreempt.h | 87
include/linux/regulator/mcu_max8660-bus.h | 102
include/linux/regulator/regulator-drv.h | 107
include/linux/regulator/regulator-platform.h | 102
include/linux/regulator/regulator.h | 332
include/linux/regulator/wm8350/wm8350-audio.h | 638
include/linux/regulator/wm8350/wm8350-bus.h | 118
include/linux/regulator/wm8350/wm8350-comparator.h | 183
include/linux/regulator/wm8350/wm8350-gpio.h | 345
include/linux/regulator/wm8350/wm8350-pmic.h | 805
include/linux/regulator/wm8350/wm8350-rtc.h | 282
include/linux/regulator/wm8350/wm8350-supply.h | 159
include/linux/regulator/wm8350/wm8350-wdt.h | 29
include/linux/regulator/wm8350/wm8350.h | 1863
include/linux/rt_lock.h | 313
include/linux/rtmutex.h | 35
include/linux/rwsem-spinlock.h | 35
include/linux/rwsem.h | 108
include/linux/sched.h | 293
include/linux/sched_prio.h | 23
include/linux/semaphore.h | 78
include/linux/seqlock.h | 316
include/linux/serial_core.h | 3
include/linux/smp.h | 23
include/linux/smp_lock.h | 2
include/linux/soundcard.h | 7
include/linux/spinlock.h | 609
include/linux/spinlock_api_smp.h | 91
include/linux/spinlock_api_up.h | 76
include/linux/spinlock_types.h | 61
include/linux/spinlock_types_up.h | 6
include/linux/spinlock_up.h | 8
include/linux/srcu.h | 22
include/linux/stacktrace.h | 3
include/linux/swap.h | 2
include/linux/sysfs.h | 7
include/linux/tick.h | 5
include/linux/time.h | 2
include/linux/timer.h | 4
include/linux/tracepoint.h | 127
include/linux/tty.h | 2
include/linux/uaccess.h | 33
include/linux/usb.h | 3
include/linux/usb/fsl_xcvr.h | 44
include/linux/usb/gadget.h | 1
include/linux/vmstat.h | 10
include/linux/wireless.h | 2
include/linux/workqueue.h | 35
include/linux/writeback.h | 3
include/llog.h | 527
include/mtd/mtd-abi.h | 3
include/mtd/ubi-user.h | 76
include/net/dn_dev.h | 6
include/net/mwan.h | 34
include/net/netfilter/nf_conntrack.h | 4
include/net/netfilter/nf_conntrack_ecache.h | 13
include/sound/driver.h | 52
include/sound/soc-dapm.h | 51
include/sound/soc.h | 31
include/trace/sched.h | 60
init/Kconfig | 18
init/Makefile | 3
init/do_mounts.c | 3
init/main.c | 88
ipc/mqueue.c | 5
ipc/msg.c | 25
ipc/sem.c | 6
ipc/shm.c | 4
kernel/.gitignore | 6
kernel/Kconfig.hz | 2
kernel/Kconfig.preempt | 107
kernel/Makefile | 26
kernel/cgroup.c | 2
kernel/cpu.c | 9
kernel/exit.c | 20
kernel/fork.c | 199
kernel/futex.c | 29
kernel/hrtimer.c | 122
kernel/irq/Makefile | 1
kernel/irq/autoprobe.c | 1
kernel/irq/chip.c | 50
kernel/irq/handle.c | 80
kernel/irq/internals.h | 6
kernel/irq/manage.c | 348
kernel/irq/migration.c | 14
kernel/irq/pm.c | 81
kernel/irq/proc.c | 129
kernel/irq/spurious.c | 25
kernel/itimer.c | 1
kernel/kprobes.c | 2
kernel/lockdep.c | 162
kernel/lockdep_internals.h | 4
kernel/lockdep_proc.c | 4
kernel/module.c | 81
kernel/notifier.c | 4
kernel/panic.c | 56
kernel/pm_qos_params.c | 25
kernel/posix-cpu-timers.c | 207
kernel/posix-timers.c | 3
kernel/power/poweroff.c | 1
kernel/printk.c | 84
kernel/profile.c | 14
kernel/rcuclassic.c | 10
kernel/rcupdate.c | 20
kernel/rcupreempt-boost.c | 600
kernel/rcupreempt.c | 424
kernel/rcupreempt_trace.c | 14
kernel/rcutorture.c | 138
kernel/relay.c | 14
kernel/rt.c | 528
kernel/rtmutex-debug.c | 111
kernel/rtmutex-debug.h | 12
kernel/rtmutex.c | 2028
kernel/rtmutex_common.h | 83
kernel/rwlock_torture.c | 845
kernel/rwsem.c | 44
kernel/sched.c | 936
kernel/sched_clock.c | 13
kernel/sched_cpupri.c | 174
kernel/sched_cpupri.h | 36
kernel/sched_debug.c | 13
kernel/sched_fair.c | 28
kernel/sched_rt.c | 360
kernel/semaphore.c | 46
kernel/signal.c | 4
kernel/softirq.c | 600
kernel/softlockup.c | 23
kernel/spinlock.c | 264
kernel/srcu.c | 86
kernel/stacktrace.c | 14
kernel/stop_machine.c | 8
kernel/sys.c | 11
kernel/sysctl.c | 106
kernel/time/clockevents.c | 5
kernel/time/clocksource.c | 2
kernel/time/tick-broadcast.c | 2
kernel/time/tick-common.c | 3
kernel/time/tick-internal.h | 2
kernel/time/tick-sched.c | 22
kernel/time/timekeeping.c | 4
kernel/time/timer_stats.c | 6
kernel/timer.c | 226
kernel/trace/Kconfig | 199
kernel/trace/Makefile | 32
kernel/trace/ftrace.c | 1961
kernel/trace/preempt-trace.c | 30
kernel/trace/trace.c | 3989 +
kernel/trace/trace.h | 512
kernel/trace/trace_events.c | 655
kernel/trace/trace_functions.c | 81
kernel/trace/trace_hist.c | 657
kernel/trace/trace_hist.h | 39
kernel/trace/trace_irqsoff.c | 515
kernel/trace/trace_mmiotrace.c | 295
kernel/trace/trace_sched_switch.c | 214
kernel/trace/trace_sched_wakeup.c | 383
kernel/trace/trace_selftest.c | 575
kernel/trace/trace_selftest_dynamic.c | 7
kernel/trace/trace_stack.c | 305
kernel/trace/trace_sysprof.c | 363
kernel/tracepoint.c | 476
kernel/user.c | 8
kernel/workqueue.c | 334
lib/.gitignore | 6
lib/Kconfig.debug | 50
lib/Makefile | 14
lib/dec_and_lock.c | 4
lib/kernel_lock.c | 129
lib/kobject_uevent.c | 176
lib/lock_list.c | 161
lib/locking-selftest.c | 35
lib/percpu_counter.c | 7
lib/plist.c | 70
lib/radix-tree.c | 766
lib/ratelimit.c | 2
lib/rwsem-spinlock.c | 29
lib/rwsem.c | 6
lib/spinlock_debug.c | 64
localversion | 1
mm/bounce.c | 4
mm/filemap.c | 236
mm/highmem.c | 521
mm/memory.c | 65
mm/migrate.c | 28
mm/mmap.c | 10
mm/page-writeback.c | 52
mm/page_alloc.c | 133
mm/quicklist.c | 15
mm/readahead.c | 4
mm/shmem.c | 8
mm/slab.c | 517
mm/swap.c | 93
mm/swap_state.c | 26
mm/swapfile.c | 14
mm/truncate.c | 8
mm/vmscan.c | 24
mm/vmstat.c | 38
net/core/dev.c | 41
net/core/flow.c | 22
net/core/netpoll.c | 62
net/core/sock.c | 7
net/decnet/dn_dev.c | 44
net/ethernet/eth.c | 22
net/ipv4/icmp.c | 5
net/ipv4/netfilter/arp_tables.c | 4
net/ipv4/netfilter/ip_tables.c | 2
net/ipv4/netfilter/ipt_ECN.c | 146
net/ipv4/netfilter/ipt_TTL.c | 102
net/ipv4/netfilter/ipt_ecn.c | 135
net/ipv4/netfilter/ipt_ttl.c | 66
net/ipv4/route.c | 6
net/ipv4/tcp.c | 4
net/ipv4/tcp_ipv4.c | 152
net/ipv6/netfilter/ip6_tables.c | 2
net/ipv6/netfilter/ip6t_HL.c | 100
net/ipv6/netfilter/ip6t_hl.c | 71
net/irda/irttp.c | 1
net/netfilter/nf_conntrack_core.c | 18
net/netfilter/nf_conntrack_ecache.c | 16
net/netfilter/xt_CONNMARK.c | 261
net/netfilter/xt_TCPMSS.c | 340
net/netfilter/xt_connmark.c | 204
net/netfilter/xt_tcpmss.c | 113
net/sched/sch_generic.c | 14
scripts/.gitignore | 9
scripts/Makefile | 6
scripts/Makefile.build | 9
scripts/Makefile.lib | 3
scripts/basic/.gitignore | 3
scripts/genksyms/.gitignore | 4
scripts/kconfig/.gitignore | 19
scripts/kconfig/lxdialog/.gitignore | 4
scripts/mkcompile_h | 4
scripts/mod/.gitignore | 4
scripts/recordmcount.pl | 395
scripts/testlpp.c | 159
security/selinux/hooks.c | 9
sound/arm/Kconfig | 54
sound/arm/Makefile | 11
sound/arm/mxc-alsa-common.h | 68
sound/arm/mxc-alsa-mixer.c | 410
sound/arm/mxc-alsa-pmic.c | 3786 +
sound/arm/mxc-alsa-pmic.h | 110
sound/arm/mxc-alsa-spdif.c | 2264 +
sound/core/pcm_lib.c | 1
sound/oss/.gitignore | 4
sound/soc/Kconfig | 1
sound/soc/Makefile | 4
sound/soc/codecs/Kconfig | 29
sound/soc/codecs/Makefile | 14
sound/soc/codecs/ak4647.c | 811
sound/soc/codecs/ak4647.h | 95
sound/soc/codecs/bluetooth.c | 133
sound/soc/codecs/sgtl5000.c | 1044
sound/soc/codecs/sgtl5000.h | 403
sound/soc/codecs/wm8350.c | 1536
sound/soc/codecs/wm8350.h | 49
sound/soc/codecs/wm8580.c | 1240
sound/soc/codecs/wm8580.h | 45
sound/soc/codecs/wm8903.c | 1880
sound/soc/codecs/wm8903.h | 1453
sound/soc/codecs/wm8960.c | 1804
sound/soc/codecs/wm8960.h | 132
sound/soc/imx/Kconfig | 84
sound/soc/imx/Makefile | 30
sound/soc/imx/imx-3stack-ak4647.c | 527
sound/soc/imx/imx-3stack-bt.c | 335
sound/soc/imx/imx-3stack-bt.h | 23
sound/soc/imx/imx-3stack-sgtl5000.c | 896
sound/soc/imx/imx-3stack-wm8350.c | 658
sound/soc/imx/imx-3stack-wm8580.c | 543
sound/soc/imx/imx-3stack-wm8903.c | 560
sound/soc/imx/imx-esai.c | 950
sound/soc/imx/imx-esai.h | 23
sound/soc/imx/imx-pcm.c | 715
sound/soc/imx/imx-pcm.h | 78
sound/soc/imx/imx-ssi.c | 869
sound/soc/imx/imx-ssi.h | 219
sound/soc/imx/imx31-pcm.h | 72
sound/soc/imx/imx35-pcm.c | 609
sound/soc/imx/imx35-pcm.h | 72
sound/soc/imx/mx35luigi_wm8960.c | 388
sound/soc/imx/mxc_fiq_ssi.S | 129
sound/soc/imx/mxc_pcm.c | 601
sound/soc/imx/mxc_pcm.h | 73
sound/soc/imx/mxc_pcm_fiq.c | 313
sound/soc/imx/mxc_ssi_ksym.c | 19
sound/soc/imx/ssi_fiq.h | 8
sound/soc/soc-core.c | 144
sound/soc/soc-dapm.c | 197
sound/soc/soc-helper.c | 71
usr/.gitignore | 8
2243 files changed, 644909 insertions(+), 8840 deletions(-)
diff -urN linux-2.6.26/.gitignore linux-2.6.26-lab126/.gitignore
--- linux-2.6.26/.gitignore 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/.gitignore 1969-12-31 19:00:00.000000000 -0500
@@ -1,66 +0,0 @@
-#
-# NOTE! Don't add files that are generated in specific
-# subdirectories here. Add them in the ".gitignore" file
-# in that subdirectory instead.
-#
-# NOTE! Please use 'git-ls-files -i --exclude-standard'
-# command after changing this file, to see if there are
-# any tracked files which get ignored after the change.
-#
-# Normal rules
-#
-.*
-*.o
-*.o.*
-*.a
-*.s
-*.ko
-*.so
-*.so.dbg
-*.mod.c
-*.i
-*.lst
-*.symtypes
-*.order
-*.elf
-*.bin
-*.gz
-
-#
-# Top-level generic files
-#
-tags
-TAGS
-vmlinux
-System.map
-Module.markers
-Module.symvers
-!.gitignore
-!.mailmap
-
-#
-# Generated include files
-#
-include/asm
-include/asm-*/asm-offsets.h
-include/config
-include/linux/autoconf.h
-include/linux/compile.h
-include/linux/version.h
-include/linux/utsrelease.h
-include/linux/bounds.h
-
-# stgit generated dirs
-patches-*
-
-# quilt's files
-patches
-series
-
-# cscope files
-cscope.*
-ncscope.*
-
-*.orig
-*~
-\#*#
diff -urN linux-2.6.26/Documentation/DocBook/.gitignore linux-2.6.26-lab126/Documentation/DocBook/.gitignore
--- linux-2.6.26/Documentation/DocBook/.gitignore 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/Documentation/DocBook/.gitignore 1969-12-31 19:00:00.000000000 -0500
@@ -1,6 +0,0 @@
-*.xml
-*.ps
-*.pdf
-*.html
-*.9.gz
-*.9
diff -urN linux-2.6.26/Documentation/filesystems/ext4.txt linux-2.6.26-lab126/Documentation/filesystems/ext4.txt
--- linux-2.6.26/Documentation/filesystems/ext4.txt 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/Documentation/filesystems/ext4.txt 2010-08-10 04:13:43.000000000 -0400
@@ -13,72 +13,99 @@
1. Quick usage instructions:
===========================
- - Grab updated e2fsprogs from
- ftp://ftp.kernel.org/pub/linux/kernel/people/tytso/e2fsprogs-interim/
- This is a patchset on top of e2fsprogs-1.39, which can be found at
+ - Compile and install the latest version of e2fsprogs (as of this
+ writing version 1.41) from:
+
+ http://sourceforge.net/project/showfiles.php?group_id=2406
+
+ or
+
ftp://ftp.kernel.org/pub/linux/kernel/people/tytso/e2fsprogs/
- - It's still mke2fs -j /dev/hda1
+ or grab the latest git repository from:
+
+ git://git.kernel.org/pub/scm/fs/ext2/e2fsprogs.git
+
+ - Note that it is highly important to install the mke2fs.conf file
+ that comes with the e2fsprogs 1.41.x sources in /etc/mke2fs.conf. If
+ you have edited the /etc/mke2fs.conf file installed on your system,
+ you will need to merge your changes with the version from e2fsprogs
+ 1.41.x.
+
+ - Create a new filesystem using the ext4dev filesystem type:
+
+ # mke2fs -t ext4dev /dev/hda1
+
+ Or configure an existing ext3 filesystem to support extents and set
+ the test_fs flag to indicate that it's ok for an in-development
+ filesystem to touch this filesystem:
- - mount /dev/hda1 /wherever -t ext4dev
+ # tune2fs -O extents -E test_fs /dev/hda1
- - To enable extents,
+ If the filesystem was created with 128 byte inodes, it can be
+ converted to use 256 byte for greater efficiency via:
- mount /dev/hda1 /wherever -t ext4dev -o extents
+ # tune2fs -I 256 /dev/hda1
- - The filesystem is compatible with the ext3 driver until you add a file
- which has extents (ie: `mount -o extents', then create a file).
+ (Note: we currently do not have tools to convert an ext4dev
+ filesystem back to ext3; so please do not do try this on production
+ filesystems.)
- NOTE: The "extents" mount flag is temporary. It will soon go away and
- extents will be enabled by the "-o extents" flag to mke2fs or tune2fs
+ - Mounting:
+
+ # mount -t ext4dev /dev/hda1 /wherever
- When comparing performance with other filesystems, remember that
- ext3/4 by default offers higher data integrity guarantees than most. So
- when comparing with a metadata-only journalling filesystem, use `mount -o
- data=writeback'. And you might as well use `mount -o nobh' too along
- with it. Making the journal larger than the mke2fs default often helps
- performance with metadata-intensive workloads.
+ ext3/4 by default offers higher data integrity guarantees than most.
+ So when comparing with a metadata-only journalling filesystem, such
+ as ext3, use `mount -o data=writeback'. And you might as well use
+ `mount -o nobh' too along with it. Making the journal larger than
+ the mke2fs default often helps performance with metadata-intensive
+ workloads.
2. Features
===========
2.1 Currently available
-* ability to use filesystems > 16TB
+* ability to use filesystems > 16TB (e2fsprogs support not available yet)
* extent format reduces metadata overhead (RAM, IO for access, transactions)
* extent format more robust in face of on-disk corruption due to magics,
* internal redunancy in tree
-
-2.1 Previously available, soon to be enabled by default by "mkefs.ext4":
-
-* dir_index and resize inode will be on by default
-* large inodes will be used by default for fast EAs, nsec timestamps, etc
+* improved file allocation (multi-block alloc)
+* fix 32000 subdirectory limit
+* nsec timestamps for mtime, atime, ctime, create time
+* inode version field on disk (NFSv4, Lustre)
+* reduced e2fsck time via uninit_bg feature
+* journal checksumming for robustness, performance
+* persistent file preallocation (e.g for streaming media, databases)
+* ability to pack bitmaps and inode tables into larger virtual groups via the
+ flex_bg feature
+* large file support
+* Inode allocation using large virtual block groups via flex_bg
+* delayed allocation
+* large block (up to pagesize) support
+* efficent new ordered mode in JBD2 and ext4(avoid using buffer head to force
+ the ordering)
2.2 Candidate features for future inclusion
-There are several under discussion, whether they all make it in is
-partly a function of how much time everyone has to work on them:
+* Online defrag (patches available but not well tested)
+* reduced mke2fs time via lazy itable initialization in conjuction with
+ the uninit_bg feature (capability to do this is available in e2fsprogs
+ but a kernel thread to do lazy zeroing of unused inode table blocks
+ after filesystem is first mounted is required for safety)
+
+There are several others under discussion, whether they all make it in is
+partly a function of how much time everyone has to work on them. Features like
+metadata checksumming have been discussed and planned for a bit but no patches
+exist yet so I'm not sure they're in the near-term roadmap.
-* improved file allocation (multi-block alloc, delayed alloc; basically done)
-* fix 32000 subdirectory limit (patch exists, needs some e2fsck work)
-* nsec timestamps for mtime, atime, ctime, create time (patch exists,
- needs some e2fsck work)
-* inode version field on disk (NFSv4, Lustre; prototype exists)
-* reduced mke2fs/e2fsck time via uninitialized groups (prototype exists)
-* journal checksumming for robustness, performance (prototype exists)
-* persistent file preallocation (e.g for streaming media, databases)
+The big performance win will come with mballoc, delalloc and flex_bg
+grouping of bitmaps and inode tables. Some test results available here:
-Features like metadata checksumming have been discussed and planned for
-a bit but no patches exist yet so I'm not sure they're in the near-term
-roadmap.
-
-The big performance win will come with mballoc and delalloc. CFS has
-been using mballoc for a few years already with Lustre, and IBM + Bull
-did a lot of benchmarking on it. The reason it isn't in the first set of
-patches is partly a manageability issue, and partly because it doesn't
-directly affect the on-disk format (outside of much better allocation)
-so it isn't critical to get into the first round of changes. I believe
-Alex is working on a new set of patches right now.
+ - http://www.bullopensource.org/ext4/20080530/ffsb-write-2.6.26-rc2.html
+ - http://www.bullopensource.org/ext4/20080530/ffsb-readwrite-2.6.26-rc2.html
3. Options
==========
@@ -222,9 +249,11 @@
to use for allocation size and alignment. For RAID5/6
systems this should be the number of data
disks * RAID chunk size in file system blocks.
-
+delalloc (*) Deferring block allocation until write-out time.
+nodelalloc Disable delayed allocation. Blocks are allocation
+ when data is copied from user to page cache.
Data Mode
----------
+=========
There are 3 different data modes:
* writeback mode
@@ -236,10 +265,10 @@
* ordered mode
In data=ordered mode, ext4 only officially journals metadata, but it logically
-groups metadata and data blocks into a single unit called a transaction. When
-it's time to write the new metadata out to disk, the associated data blocks
-are written first. In general, this mode performs slightly slower than
-writeback but significantly faster than journal mode.
+groups metadata information related to data changes with the data blocks into a
+single unit called a transaction. When it's time to write the new metadata
+out to disk, the associated data blocks are written first. In general,
+this mode performs slightly slower than writeback but significantly faster than journal mode.
* journal mode
data=journal mode provides full data and metadata journaling. All new data is
@@ -247,7 +276,8 @@
In the event of a crash, the journal can be replayed, bringing both data and
metadata into a consistent state. This mode is the slowest except when data
needs to be read from and written to disk at the same time where it
-outperforms all others modes.
+outperforms all others modes. Curently ext4 does not have delayed
+allocation support if this data journalling mode is selected.
References
==========
@@ -256,7 +286,8 @@
programs: http://e2fsprogs.sourceforge.net/
- http://ext2resize.sourceforge.net
useful links: http://fedoraproject.org/wiki/ext3-devel
http://www.bullopensource.org/ext4/
+ http://ext4.wiki.kernel.org/index.php/Main_Page
+ http://fedoraproject.org/wiki/Features/Ext4
diff -urN linux-2.6.26/Documentation/filesystems/proc.txt linux-2.6.26-lab126/Documentation/filesystems/proc.txt
--- linux-2.6.26/Documentation/filesystems/proc.txt 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/Documentation/filesystems/proc.txt 2010-08-10 04:13:43.000000000 -0400
@@ -288,6 +288,7 @@
rtc Real time clock
scsi SCSI info (see text)
slabinfo Slab pool info
+ softirqs softirq usage
stat Overall statistics
swaps Swap space utilization
sys See chapter 2
@@ -550,6 +551,22 @@
VmallocUsed: amount of vmalloc area which is used
VmallocChunk: largest contigious block of vmalloc area which is free
+..............................................................................
+softirqs:
+
+Provides counts of softirq handlers serviced since boot time.
+
+> cat /proc/softirqs
+ CPU0 CPU1 CPU2 CPU3
+ HI: 0 0 0 0
+ TIMER: 27166 27120 27097 27034
+ NET_TX: 0 0 0 17
+ NET_RX: 42 0 0 39
+ BLOCK: 0 0 107 1121
+ TASKLET: 0 0 0 290
+ SCHED: 27035 26983 26971 26746
+ HRTIMER: 0 0 0 0
+ RCU: 1678 1769 2178 2250
1.3 IDE devices in /proc/ide
----------------------------
@@ -837,6 +854,7 @@
processes 2915
procs_running 1
procs_blocked 0
+ softirq 183433 0 21755 12 39 1137 231 21459 2263
The very first "cpu" line aggregates the numbers in all of the other "cpuN"
lines. These numbers identify the amount of time the CPU has spent performing
@@ -872,6 +890,11 @@
The "procs_blocked" line gives the number of processes currently blocked,
waiting for I/O to complete.
+The "softirq" line gives counts of softirqs serviced since boot time, for each
+of the possible system softirqs. The first column is the total of all
+softirqs serviced; each subsequent column is the total for that particular
+softirq.
+
1.9 Ext4 file system parameters
------------------------------
Ext4 file system have one directory per partition under /proc/fs/ext4/
diff -urN linux-2.6.26/Documentation/filesystems/ubifs.txt linux-2.6.26-lab126/Documentation/filesystems/ubifs.txt
--- linux-2.6.26/Documentation/filesystems/ubifs.txt 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/Documentation/filesystems/ubifs.txt 2010-08-10 04:13:43.000000000 -0400
@@ -0,0 +1,173 @@
+Introduction
+=============
+
+UBIFS file-system stands for UBI File System. UBI stands for "Unsorted
+Block Images". UBIFS is a flash file system, which means it is designed
+to work with flash devices. It is important to understand, that UBIFS
+is completely different to any traditional file-system in Linux, like
+Ext2, XFS, JFS, etc. UBIFS represents a separate class of file-systems
+which work with MTD devices, not block devices. The other Linux
+file-system of this class is JFFS2.
+
+To make it more clear, here is a small comparison of MTD devices and
+block devices.
+
+1 MTD devices represent flash devices and they consist of eraseblocks of
+ rather large size, typically about 128KiB. Block devices consist of
+ small blocks, typically 512 bytes.
+2 MTD devices support 3 main operations - read from some offset within an
+ eraseblock, write to some offset within an eraseblock, and erase a whole
+ eraseblock. Block devices support 2 main operations - read a whole
+ block and write a whole block.
+3 The whole eraseblock has to be erased before it becomes possible to
+ re-write its contents. Blocks may be just re-written.
+4 Eraseblocks become worn out after some number of erase cycles -
+ typically 100K-1G for SLC NAND and NOR flashes, and 1K-10K for MLC
+ NAND flashes. Blocks do not have the wear-out property.
+5 Eraseblocks may become bad (only on NAND flashes) and software should
+ deal with this. Blocks on hard drives typically do not become bad,
+ because hardware has mechanisms to substitute bad blocks, at least in
+ modern LBA disks.
+
+It should be quite obvious why UBIFS is very different to traditional
+file-systems.
+
+UBIFS works on top of UBI. UBI is a separate software layer which may be
+found in drivers/mtd/ubi. UBI is basically a volume management and
+wear-leveling layer. It provides so called UBI volumes which is a higher
+level abstraction than a MTD device. The programming model of UBI devices
+is very similar to MTD devices - they still consist of large eraseblocks,
+they have read/write/erase operations, but UBI devices are devoid of
+limitations like wear and bad blocks (items 4 and 5 in the above list).
+
+In a sense, UBIFS is a next generation of JFFS2 file-system, but it is
+very different and incompatible to JFFS2. The following are the main
+differences.
+
+* JFFS2 works on top of MTD devices, UBIFS depends on UBI and works on
+ top of UBI volumes.
+* JFFS2 does not have on-media index and has to build it while mounting,
+ which requires full media scan. UBIFS maintains the FS indexing
+ information on the flash media and does not require full media scan,
+ so it mounts many times faster than JFFS2.
+* JFFS2 is a write-through file-system, while UBIFS supports write-back,
+ which makes UBIFS much faster on writes.
+
+Similarly to JFFS2, UBIFS supports on-the-flight compression which makes
+it possible to fit quite a lot of data to the flash.
+
+Similarly to JFFS2, UBIFS is tolerant of unclean reboots and power-cuts.
+It does not need stuff like ckfs.ext2. UBIFS automatically replays its
+journal and recovers from crashes, ensuring that the on-flash data
+structures are consistent.
+
+UBIFS scales logarithmically (most of the data structures it uses are
+trees), so the mount time and memory consumption do not linearly depend
+on the flash size, like in case of JFFS2. This is because UBIFS
+maintains the FS index on the flash media. However, UBIFS depends on
+UBI, which scales linearly. So overall UBI/UBIFS stack scales linearly.
+Nevertheless, UBI/UBIFS scales considerably better than JFFS2.
+
+The authors of UBIFS believe, that it is possible to develop UBI2 which
+would scale logarithmically as well. UBI2 would support the same API as UBI,
+but it would be binary incompatible to UBI. So UBIFS would not need to be
+changed to use UBI2
+
+
+Mount options
+=============
+
+(*) == default.
+
+norm_unmount (*) commit on unmount; the journal is committed
+ when the file-system is unmounted so that the
+ next mount does not have to replay the journal
+ and it becomes very fast;
+fast_unmount do not commit on unmount; this option makes
+ unmount faster, but the next mount slower
+ because of the need to replay the journal.
+bulk_read read more in one go to take advantage of flash
+ media that read faster sequentially
+no_bulk_read (*) do not bulk-read
+no_chk_data_crc skip checking of CRCs on data nodes in order to
+ improve read performance. Use this option only
+ if the flash media is highly reliable. The effect
+ of this option is that corruption of the contents
+ of a file can go unnoticed.
+chk_data_crc (*) do not skip checking CRCs on data nodes
+
+
+Quick usage instructions
+========================
+
+The UBI volume to mount is specified using "ubiX_Y" or "ubiX:NAME" syntax,
+where "X" is UBI device number, "Y" is UBI volume number, and "NAME" is
+UBI volume name.
+
+Mount volume 0 on UBI device 0 to /mnt/ubifs:
+$ mount -t ubifs ubi0_0 /mnt/ubifs
+
+Mount "rootfs" volume of UBI device 0 to /mnt/ubifs ("rootfs" is volume
+name):
+$ mount -t ubifs ubi0:rootfs /mnt/ubifs
+
+The following is an example of the kernel boot arguments to attach mtd0
+to UBI and mount volume "rootfs":
+ubi.mtd=0 root=ubi0:rootfs rootfstype=ubifs
+
+
+Module Parameters for Debugging
+===============================
+
+When UBIFS has been compiled with debugging enabled, there are 3 module
+parameters that are available to control aspects of testing and debugging.
+The parameters are unsigned integers where each bit controls an option.
+The parameters are:
+
+debug_msgs Selects which debug messages to display, as follows:
+
+ Message Type Flag value
+
+ General messages 1
+ Journal messages 2
+ Mount messages 4
+ Commit messages 8
+ LEB search messages 16
+ Budgeting messages 32
+ Garbage collection messages 64
+ Tree Node Cache (TNC) messages 128
+ LEB properties (lprops) messages 256
+ Input/output messages 512
+ Log messages 1024
+ Scan messages 2048
+ Recovery messages 4096
+
+debug_chks Selects extra checks that UBIFS can do while running:
+
+ Check Flag value
+
+ General checks 1
+ Check Tree Node Cache (TNC) 2
+ Check indexing tree size 4
+ Check orphan area 8
+ Check old indexing tree 16
+ Check LEB properties (lprops) 32
+ Check leaf nodes and inodes 64
+
+debug_tsts Selects a mode of testing, as follows:
+
+ Test mode Flag value
+
+ Force in-the-gaps method 2
+ Failure mode for recovery testing 4
+
+For example, set debug_msgs to 5 to display General messages and Mount
+messages.
+
+
+References
+==========
+
+UBIFS documentation and FAQ/HOWTO at the MTD web site:
+http://www.linux-mtd.infradead.org/doc/ubifs.html
+http://www.linux-mtd.infradead.org/faq/ubifs.html
diff -urN linux-2.6.26/MAINTAINERS linux-2.6.26-lab126/MAINTAINERS
--- linux-2.6.26/MAINTAINERS 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/MAINTAINERS 2010-08-10 04:17:28.000000000 -0400
@@ -2307,6 +2307,16 @@
W: http://www.linux-mtd.infradead.org/doc/jffs2.html
S: Maintained
+UBI FILE SYSTEM (UBIFS)
+P: Artem Bityutskiy
+M: dedekind@infradead.org
+P: Adrian Hunter
+M: ext-adrian.hunter@nokia.com
+L: linux-mtd@lists.infradead.org
+T: git git://git.infradead.org/~dedekind/ubifs-2.6.git
+W: http://www.linux-mtd.infradead.org/doc/ubifs.html
+S: Maintained
+
JFS FILESYSTEM
P: Dave Kleikamp
M: shaggy@austin.ibm.com
@@ -2751,7 +2761,7 @@
M: dedekind@infradead.org
W: http://www.linux-mtd.infradead.org/
L: linux-mtd@lists.infradead.org
-T: git git://git.infradead.org/~dedekind/ubi-2.6.git
+T: git git://git.infradead.org/ubi-2.6.git
S: Maintained
MICROTEK X6 SCANNER
diff -urN linux-2.6.26/Makefile linux-2.6.26-lab126/Makefile
--- linux-2.6.26/Makefile 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/Makefile 2010-08-10 04:17:28.000000000 -0400
@@ -336,8 +336,10 @@
KBUILD_AFLAGS := -D__ASSEMBLY__
# Read KERNELRELEASE from include/config/kernel.release (if it exists)
-KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null)
-KERNELVERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+#KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null)
+#KERNELVERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+KERNELRELEASE = 2.6.26-rt-lab126
+KERNELVERSION = 2.6.26-rt-lab126
export VERSION PATCHLEVEL SUBLEVEL KERNELRELEASE KERNELVERSION
export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC
@@ -528,6 +530,10 @@
KBUILD_AFLAGS += -gdwarf-2
endif
+ifdef CONFIG_FTRACE
+KBUILD_CFLAGS += -pg
+endif
+
# We trigger additional mismatches with less inlining
ifdef CONFIG_DEBUG_SECTION_MISMATCH
KBUILD_CFLAGS += $(call cc-option, -fno-inline-functions-called-once)
diff -urN linux-2.6.26/arch/.gitignore linux-2.6.26-lab126/arch/.gitignore
--- linux-2.6.26/arch/.gitignore 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/.gitignore 1969-12-31 19:00:00.000000000 -0500
@@ -1,2 +0,0 @@
-i386
-x86_64
diff -urN linux-2.6.26/arch/Kconfig linux-2.6.26-lab126/arch/Kconfig
--- linux-2.6.26/arch/Kconfig 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/Kconfig 2010-08-10 04:15:13.000000000 -0400
@@ -16,6 +16,11 @@
config HAVE_OPROFILE
def_bool n
+config PROFILE_NMI
+ bool
+ depends on OPROFILE
+ default y
+
config KPROBES
bool "Kprobes"
depends on KALLSYMS && MODULES
diff -urN linux-2.6.26/arch/arm/Kconfig linux-2.6.26-lab126/arch/arm/Kconfig
--- linux-2.6.26/arch/arm/Kconfig 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/Kconfig 2010-08-10 04:14:16.000000000 -0400
@@ -12,8 +12,11 @@
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
select HAVE_OPROFILE
+ select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
select HAVE_KRETPROBES if (HAVE_KPROBES)
+ select HAVE_FTRACE if (!XIP_KERNEL)
+ select HAVE_DYNAMIC_FTRACE if (HAVE_FTRACE)
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
@@ -33,6 +36,10 @@
bool
default n
+config GENERIC_CMOS_UPDATE
+ bool
+ default y
+
config GENERIC_CLOCKEVENTS
bool
default n
@@ -42,6 +49,10 @@
depends on GENERIC_CLOCKEVENTS
default y if SMP && !LOCAL_TIMERS
+config STACKTRACE_SUPPORT
+ bool
+ default y
+
config MMU
bool
default y
@@ -368,6 +379,8 @@
config ARCH_MXC
bool "Freescale MXC/iMX-based"
select ARCH_MTD_XIP
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
help
Support for Freescale MXC/iMX-based family of processors
@@ -690,18 +703,7 @@
accounting to be spread across the timer interval, preventing a
"thundering herd" at every timer tick.
-config PREEMPT
- bool "Preemptible Kernel (EXPERIMENTAL)"
- depends on EXPERIMENTAL
- help
- This option reduces the latency of the kernel when reacting to
- real-time or interactive events by allowing a low priority process to
- be preempted even if it is in kernel mode executing a system call.
- This allows applications to run more reliably even when the system is
- under load.
-
- Say Y here if you are building a kernel for a desktop, embedded
- or real-time system. Say N if you are unsure.
+source kernel/Kconfig.preempt
config NO_IDLE_HZ
bool "Dynamic tick timer"
@@ -795,7 +797,7 @@
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
- ARCH_KS8695 || MACH_RD88F5182
+ ARCH_KS8695 || MACH_RD88F5182 || ARCH_MXC
help
If you say Y here, the LEDs on your machine will be used
to provide useful information about your current system status.
@@ -954,7 +956,7 @@
endmenu
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || ARCH_MXC)
menu "CPU Frequency scaling"
@@ -996,6 +998,12 @@
default y
select CPU_FREQ_DEFAULT_GOV_USERSPACE
+config CPU_FREQ_IMX
+ tristate "CPUfreq driver for i.MX CPUs"
+ depends on ARCH_MXC && CPU_FREQ && REGULATOR
+ help
+ This enables the CPUfreq driver for i.MX CPUs.
+
endmenu
endif
@@ -1105,6 +1113,8 @@
source "drivers/mtd/Kconfig"
endif
+source "drivers/regulator/Kconfig"
+
source "drivers/parport/Kconfig"
source "drivers/pnp/Kconfig"
@@ -1141,6 +1151,8 @@
source "drivers/i2c/Kconfig"
+source "drivers/i2c-slave/Kconfig"
+
source "drivers/spi/Kconfig"
source "drivers/gpio/Kconfig"
@@ -1181,6 +1193,10 @@
source "drivers/uio/Kconfig"
+if ARCH_MXC
+source "drivers/mxc/Kconfig"
+endif
+
endmenu
source "fs/Kconfig"
diff -urN linux-2.6.26/arch/arm/Kconfig.debug linux-2.6.26-lab126/arch/arm/Kconfig.debug
--- linux-2.6.26/arch/arm/Kconfig.debug 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/Kconfig.debug 2010-08-10 04:14:16.000000000 -0400
@@ -59,6 +59,14 @@
in the kernel. This is helpful if you are debugging code that
executes before the console is initialized.
+config DEBUG_LL_EARLY_CONSOLE
+ bool "Kernel early console"
+ depends on DEBUG_LL
+ help
+ Say Y here if you want to have an early console using the Kernel
+ low-level debugging functions. Add earlyconsole to your kernel
+ parameters to enable this console.
+
config DEBUG_ICEDCC
bool "Kernel low-level debugging via EmbeddedICE DCC channel"
depends on DEBUG_LL
diff -urN linux-2.6.26/arch/arm/Makefile linux-2.6.26-lab126/arch/arm/Makefile
--- linux-2.6.26/arch/arm/Makefile 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/Makefile 2010-08-10 04:14:16.000000000 -0400
@@ -138,6 +138,12 @@
machine-$(CONFIG_ARCH_KS8695) := ks8695
incdir-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX3) := mx3
+ machine-$(CONFIG_ARCH_MX35) := mx35
+ machine-$(CONFIG_ARCH_MX37) := mx37
+ machine-$(CONFIG_ARCH_MX51) := mx51
+ machine-$(CONFIG_ARCH_MX27) := mx27
+ machine-$(CONFIG_ARCH_MX25) := mx25
+ machine-$(CONFIG_ARCH_MX21) := mx21
machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_MSM7X00A) := msm
diff -urN linux-2.6.26/arch/arm/boot/.gitignore linux-2.6.26-lab126/arch/arm/boot/.gitignore
--- linux-2.6.26/arch/arm/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500
@@ -1,5 +0,0 @@
-Image
-zImage
-xipImage
-bootpImage
-uImage
diff -urN linux-2.6.26/arch/arm/boot/compressed/.gitignore linux-2.6.26-lab126/arch/arm/boot/compressed/.gitignore
--- linux-2.6.26/arch/arm/boot/compressed/.gitignore 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/boot/compressed/.gitignore 1969-12-31 19:00:00.000000000 -0500
@@ -1,2 +0,0 @@
-piggy.gz
-font.c
diff -urN linux-2.6.26/arch/arm/boot/compressed/Makefile linux-2.6.26-lab126/arch/arm/boot/compressed/Makefile
--- linux-2.6.26/arch/arm/boot/compressed/Makefile 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/boot/compressed/Makefile 2010-08-10 04:14:03.000000000 -0400
@@ -69,6 +69,12 @@
targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
head.o misc.o $(OBJS)
+
+ifeq ($(CONFIG_FTRACE),y)
+ORIG_CFLAGS := $(KBUILD_CFLAGS)
+KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
+endif
+
EXTRA_CFLAGS := -fpic -fno-builtin
EXTRA_AFLAGS :=
diff -urN linux-2.6.26/arch/arm/boot/compressed/head.S linux-2.6.26-lab126/arch/arm/boot/compressed/head.S
--- linux-2.6.26/arch/arm/boot/compressed/head.S 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/boot/compressed/head.S 2010-08-10 04:14:03.000000000 -0400
@@ -711,6 +711,9 @@
__armv7_mmu_cache_off:
mrc p15, 0, r0, c1, c0
bic r0, r0, #0x000d
+#if defined(CONFIG_ARCH_MX51)
+ bic r0, r0, #0x1000
+#endif
mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
mov r12, lr
bl __armv7_mmu_cache_flush
@@ -941,6 +944,19 @@
#endif
.ltorg
+#ifdef CONFIG_MCOUNT
+/* CONFIG_MCOUNT causes boot header to be built with -pg requiring this
+ * trampoline
+ */
+ .text
+ .align 0
+ .type mcount %function
+ .global mcount
+mcount:
+ mov pc, lr @ just return
+#endif
+
+
reloc_end:
.align
diff -urN linux-2.6.26/arch/arm/boot/compressed/vmlinux.lds linux-2.6.26-lab126/arch/arm/boot/compressed/vmlinux.lds
--- linux-2.6.26/arch/arm/boot/compressed/vmlinux.lds 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/boot/compressed/vmlinux.lds 2010-08-10 04:14:03.000000000 -0400
@@ -0,0 +1,56 @@
+/*
+ * linux/arch/arm/boot/compressed/vmlinux.lds.in
+ *
+ * Copyright (C) 2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0;
+ _text = .;
+
+ .text : {
+ _start = .;
+ *(.start)
+ *(.text)
+ *(.text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata)
+ *(.rodata.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.piggydata)
+ . = ALIGN(4);
+ }
+
+ _etext = .;
+
+ _got_start = .;
+ .got : { *(.got) }
+ _got_end = .;
+ .got.plt : { *(.got.plt) }
+ .data : { *(.data) }
+ _edata = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+
+ .stack (NOLOAD) : { *(.stack) }
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+}
+
diff -urN linux-2.6.26/arch/arm/common/time-acorn.c linux-2.6.26-lab126/arch/arm/common/time-acorn.c
--- linux-2.6.26/arch/arm/common/time-acorn.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/common/time-acorn.c 2010-08-10 04:14:12.000000000 -0400
@@ -75,7 +75,7 @@
static struct irqaction ioc_timer_irq = {
.name = "timer",
- .flags = IRQF_DISABLED,
+ .flags = IRQF_DISABLED | IRQF_NODELAY,
.handler = ioc_timer_interrupt
};
diff -urN linux-2.6.26/arch/arm/kernel/Makefile linux-2.6.26-lab126/arch/arm/kernel/Makefile
--- linux-2.6.26/arch/arm/kernel/Makefile 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/Makefile 2010-08-10 04:14:06.000000000 -0400
@@ -4,6 +4,10 @@
AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
+ifdef CONFIG_DYNAMIC_FTRACE
+CFLAGS_REMOVE_ftrace.o = -pg
+endif
+
# Object file lists.
obj-y := compat.o entry-armv.o entry-common.o irq.o \
@@ -18,11 +22,13 @@
obj-$(CONFIG_ISA_DMA) += dma-isa.o
obj-$(CONFIG_PCI) += bios32.o isa.o
obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o
obj-$(CONFIG_ATAGS_PROC) += atags.o
obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
obj-$(CONFIG_ARM_THUMBEE) += thumbee.o
+obj-$(CONFIG_KGDB) += kgdb.o
obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
@@ -38,5 +44,6 @@
head-y := head$(MMUEXT).o
obj-$(CONFIG_DEBUG_LL) += debug.o
+obj-$(CONFIG_DEBUG_LL_EARLY_CONSOLE) += early_console.o
extra-y := $(head-y) init_task.o vmlinux.lds
diff -urN linux-2.6.26/arch/arm/kernel/armksyms.c linux-2.6.26-lab126/arch/arm/kernel/armksyms.c
--- linux-2.6.26/arch/arm/kernel/armksyms.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/armksyms.c 2010-08-10 04:14:06.000000000 -0400
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
/*
* libgcc functions - functions that are used internally by the
@@ -181,3 +182,7 @@
#endif
EXPORT_SYMBOL(copy_page);
+
+#ifdef CONFIG_FTRACE
+EXPORT_SYMBOL(mcount);
+#endif
diff -urN linux-2.6.26/arch/arm/kernel/dma.c linux-2.6.26-lab126/arch/arm/kernel/dma.c
--- linux-2.6.26/arch/arm/kernel/dma.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/dma.c 2010-08-10 04:14:06.000000000 -0400
@@ -20,7 +20,7 @@
#include
-DEFINE_SPINLOCK(dma_spin_lock);
+DEFINE_RAW_SPINLOCK(dma_spin_lock);
EXPORT_SYMBOL(dma_spin_lock);
static dma_t dma_chan[MAX_DMA_CHANNELS];
diff -urN linux-2.6.26/arch/arm/kernel/early_console.c linux-2.6.26-lab126/arch/arm/kernel/early_console.c
--- linux-2.6.26/arch/arm/kernel/early_console.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/kernel/early_console.c 2010-08-10 04:14:06.000000000 -0400
@@ -0,0 +1,40 @@
+/*
+ * linux/arch/arm/kernel/early_printk.c
+ *
+ * Copyright 2008-2009 Amazon.com Technologies Inc., All Rights Reserved.
+ * Manish Lachwani (lachwani@lab126.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+
+extern void printch(int);
+
+static void early_console_write(struct console *con, const char *s, unsigned n)
+{
+ while (*s && n-- > 0) {
+ if (*s == '\n')
+ printch('\r');
+ printch(*s);
+ s++;
+ }
+}
+
+static struct console early_serial_console = {
+ .name = "earlycons",
+ .write = early_console_write,
+ .flags = CON_PRINTBUFFER | CON_BOOT,
+ .index = -1,
+};
+
+static int __init setup_early_console(char *buf)
+{
+ register_console(&early_serial_console);
+ return 0;
+}
+
+early_param("earlyconsole", setup_early_console);
diff -urN linux-2.6.26/arch/arm/kernel/entry-common.S linux-2.6.26-lab126/arch/arm/kernel/entry-common.S
--- linux-2.6.26/arch/arm/kernel/entry-common.S 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/entry-common.S 2010-08-10 04:14:06.000000000 -0400
@@ -3,12 +3,15 @@
*
* Copyright (C) 2000 Russell King
*
+ * FUNCTION_TRACE/mcount support (C) 2005 Timesys john.cooper@timesys.com
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include
+#include
#include
#include "entry-header.S"
@@ -54,7 +57,8 @@
b ret_slow_syscall @ Check work again
work_resched:
- bl schedule
+ bl __schedule
+
/*
* "slow" syscall return path. "why" tells us if this was a real syscall.
*/
@@ -99,6 +103,56 @@
#undef CALL
#define CALL(x) .long x
+#ifdef CONFIG_FTRACE
+#ifdef CONFIG_DYNAMIC_FTRACE
+ENTRY(mcount)
+ stmdb sp!, {r0-r3, lr}
+ mov r0, lr
+ sub r0, r0, #MCOUNT_INSN_SIZE
+
+ .globl mcount_call
+mcount_call:
+ bl ftrace_stub
+ ldmia sp!, {r0-r3, pc}
+
+ENTRY(ftrace_caller)
+ stmdb sp!, {r0-r3, lr}
+ ldr r1, [fp, #-4]
+ mov r0, lr
+ sub r0, r0, #MCOUNT_INSN_SIZE
+
+ .globl ftrace_call
+ftrace_call:
+ bl ftrace_stub
+ ldmia sp!, {r0-r3, pc}
+
+#else
+
+ENTRY(mcount)
+ stmdb sp!, {r0-r3, lr}
+ ldr r0, =ftrace_trace_function
+ ldr r2, [r0]
+ adr r0, ftrace_stub
+ cmp r0, r2
+ bne trace
+ ldmia sp!, {r0-r3, pc}
+
+trace:
+ ldr r1, [fp, #-4]
+ mov r0, lr
+ sub r0, r0, #MCOUNT_INSN_SIZE
+ mov lr, pc
+ mov pc, r2
+ ldmia sp!, {r0-r3, pc}
+
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
+ .globl ftrace_stub
+ftrace_stub:
+ mov pc, lr
+
+#endif /* CONFIG_FTRACE */
+
/*=============================================================================
* SWI handler
*-----------------------------------------------------------------------------
@@ -399,6 +453,114 @@
#include "calls.S"
#undef ABI
#undef OBSOLETE
+#endif
+
+#ifdef CONFIG_FRAME_POINTER
+
+#ifdef CONFIG_MCOUNT
+/*
+ * At the point where we are in mcount() we maintain the
+ * frame of the prologue code and keep the call to mcount()
+ * out of the stack frame list:
+
+ saved pc <---\ caller of instrumented routine
+ saved lr |
+ ip/prev_sp |
+ fp -----^ |
+ : |
+ |
+ -> saved pc | instrumented routine
+ | saved lr |
+ | ip/prev_sp |
+ | fp ---------/
+ | :
+ |
+ | mcount
+ | saved pc
+ | saved lr
+ | ip/prev sp
+ -- fp
+ r3
+ r2
+ r1
+ sp-> r0
+ :
+ */
+
+ .text
+ .align 0
+ .type mcount %function
+ .global mcount
+
+/* gcc -pg generated FUNCTION_PROLOGUE references mcount()
+ * and has already created the stack frame invocation for
+ * the routine we have been called to instrument. We create
+ * a complete frame nevertheless, as we want to use the same
+ * call to mcount() from c code.
+ */
+mcount:
+
+ ldr ip, =mcount_enabled @ leave early, if disabled
+ ldr ip, [ip]
+ cmp ip, #0
+ moveq pc, lr
+
+ mov ip, sp
+ stmdb sp!, {r0 - r3, fp, ip, lr, pc} @ create stack frame
+
+ mov r2, =mcount_trace_function
+
+ ldr r1, [fp, #-4] @ get lr (the return address
+ @ of the caller of the
+ @ instrumented function)
+ mov r0, lr @ get lr - (the return address
+ @ of the instrumented function)
+
+ sub fp, ip, #4 @ point fp at this frame
+
+ bl r2
+1:
+ ldmdb fp, {r0 - r3, fp, sp, pc} @ pop entry frame and return
+
+#endif
+
+/* ARM replacement for unsupported gcc __builtin_return_address(n)
+ * where 0 < n. n == 0 is supported here as well.
+ *
+ * Walk up the stack frame until the desired frame is found or a NULL
+ * fp is encountered, return NULL in the latter case.
+ *
+ * Note: it is possible under code optimization for the stack invocation
+ * of an ancestor function (level N) to be removed before calling a
+ * descendant function (level N+1). No easy means is available to deduce
+ * this scenario with the result being [for example] caller_addr(0) when
+ * called from level N+1 returning level N-1 rather than the expected
+ * level N. This optimization issue appears isolated to the case of
+ * a call to a level N+1 routine made at the tail end of a level N
+ * routine -- the level N frame is deleted and a simple branch is made
+ * to the level N+1 routine.
+ */
+
+ .text
+ .align 0
+ .type arm_return_addr %function
+ .global arm_return_addr
+
+arm_return_addr:
+ mov ip, r0
+ mov r0, fp
+3:
+ cmp r0, #0
+ beq 1f @ frame list hit end, bail
+ cmp ip, #0
+ beq 2f @ reached desired frame
+ ldr r0, [r0, #-12] @ else continue, get next fp
+ sub ip, ip, #1
+ b 3b
+2:
+ ldr r0, [r0, #-4] @ get target return address
+1:
+ mov pc, lr
#endif
diff -urN linux-2.6.26/arch/arm/kernel/fiq.c linux-2.6.26-lab126/arch/arm/kernel/fiq.c
--- linux-2.6.26/arch/arm/kernel/fiq.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/fiq.c 2010-08-10 04:14:06.000000000 -0400
@@ -89,7 +89,7 @@
* disable irqs for the duration. Note - these functions are almost
* entirely coded in assembly.
*/
-void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs)
+void notrace __attribute__((naked)) set_fiq_regs(struct pt_regs *regs)
{
register unsigned long tmp;
asm volatile (
@@ -107,7 +107,7 @@
: "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE));
}
-void __attribute__((naked)) get_fiq_regs(struct pt_regs *regs)
+void notrace __attribute__((naked)) get_fiq_regs(struct pt_regs *regs)
{
register unsigned long tmp;
asm volatile (
diff -urN linux-2.6.26/arch/arm/kernel/ftrace.c linux-2.6.26-lab126/arch/arm/kernel/ftrace.c
--- linux-2.6.26/arch/arm/kernel/ftrace.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/kernel/ftrace.c 2010-08-10 04:14:06.000000000 -0400
@@ -0,0 +1,116 @@
+/*
+ * Dynamic function tracing support.
+ *
+ * Copyright (C) 2008 Abhishek Sagar
+ *
+ * For licencing details, see COPYING.
+ *
+ * Defines low-level handling of mcount calls when the kernel
+ * is compiled with the -pg flag. When using dynamic ftrace, the
+ * mcount call-sites get patched lazily with NOP till they are
+ * enabled. All code mutation routines here take effect atomically.
+ */
+
+#include
+
+#include
+#include
+
+#define PC_OFFSET 8
+#define BL_OPCODE 0xeb000000
+#define BL_OFFSET_MASK 0x00ffffff
+
+static unsigned long bl_insn;
+static const unsigned long NOP = 0xe1a00000; /* mov r0, r0 */
+
+unsigned char *ftrace_nop_replace(void)
+{
+ return (char *)&NOP;
+}
+
+/* construct a branch (BL) instruction to addr */
+unsigned char *ftrace_call_replace(unsigned long pc, unsigned long addr)
+{
+ long offset;
+
+ offset = (long)addr - (long)(pc + PC_OFFSET);
+ if (unlikely(offset < -33554432 || offset > 33554428)) {
+ /* Can't generate branches that far (from ARM ARM). Ftrace
+ * doesn't generate branches outside of kernel text.
+ */
+ WARN_ON_ONCE(1);
+ return NULL;
+ }
+ offset = (offset >> 2) & BL_OFFSET_MASK;
+ bl_insn = BL_OPCODE | offset;
+ return (unsigned char *)&bl_insn;
+}
+
+int ftrace_modify_code(unsigned long pc, unsigned char *old_code,
+ unsigned char *new_code)
+{
+ unsigned long err = 0, replaced = 0, old, new;
+
+ old = *(unsigned long *)old_code;
+ new = *(unsigned long *)new_code;
+
+ __asm__ __volatile__ (
+ "1: ldr %1, [%2] \n"
+ " cmp %1, %4 \n"
+ "2: streq %3, [%2] \n"
+ " cmpne %1, %3 \n"
+ " movne %0, #2 \n"
+ "3:\n"
+
+ ".section .fixup, \"ax\"\n"
+ "4: mov %0, #1 \n"
+ " b 3b \n"
+ ".previous\n"
+
+ ".section __ex_table, \"a\"\n"
+ " .long 1b, 4b \n"
+ " .long 2b, 4b \n"
+ ".previous\n"
+
+ : "=r"(err), "=r"(replaced)
+ : "r"(pc), "r"(new), "r"(old), "0"(err), "1"(replaced)
+ : "memory");
+
+ if (!err && (replaced == old))
+ flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
+
+ return err;
+}
+
+int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+ int ret;
+ unsigned long pc, old;
+ unsigned char *new;
+
+ pc = (unsigned long)&ftrace_call;
+ memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE);
+ new = ftrace_call_replace(pc, (unsigned long)func);
+ ret = ftrace_modify_code(pc, (unsigned char *)&old, new);
+ return ret;
+}
+
+int ftrace_mcount_set(unsigned long *data)
+{
+ unsigned long pc, old;
+ unsigned long *addr = data;
+ unsigned char *new;
+
+ pc = (unsigned long)&mcount_call;
+ memcpy(&old, &mcount_call, MCOUNT_INSN_SIZE);
+ new = ftrace_call_replace(pc, *addr);
+ *addr = ftrace_modify_code(pc, (unsigned char *)&old, new);
+ return 0;
+}
+
+/* run from kstop_machine */
+int __init ftrace_dyn_arch_init(void *data)
+{
+ ftrace_mcount_set(data);
+ return 0;
+}
diff -urN linux-2.6.26/arch/arm/kernel/irq.c linux-2.6.26-lab126/arch/arm/kernel/irq.c
--- linux-2.6.26/arch/arm/kernel/irq.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/irq.c 2010-08-10 04:14:06.000000000 -0400
@@ -37,6 +37,8 @@
#include
#include
+#include
+
#include
#include
@@ -85,7 +87,7 @@
unlock:
spin_unlock_irqrestore(&irq_desc[i].lock, flags);
} else if (i == NR_IRQS) {
-#ifdef CONFIG_ARCH_ACORN
+#ifdef CONFIG_FIQ
show_fiq_list(p, v);
#endif
#ifdef CONFIG_SMP
@@ -100,7 +102,7 @@
/* Handle bad interrupts */
static struct irq_desc bad_irq_desc = {
.handle_irq = handle_bad_irq,
- .lock = SPIN_LOCK_UNLOCKED
+ .lock = RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock)
};
/*
@@ -108,11 +110,13 @@
* come via this function. Instead, they should provide their
* own 'handler'
*/
-asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
+asmlinkage void __exception notrace asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
struct irq_desc *desc = irq_desc + irq;
+ trace_event_irq(irq, user_mode(regs), instruction_pointer(regs));
+
/*
* Some hardware gives randomly wrong interrupts. Rather
* than crashing, do something sensible.
diff -urN linux-2.6.26/arch/arm/kernel/kgdb.c linux-2.6.26-lab126/arch/arm/kernel/kgdb.c
--- linux-2.6.26/arch/arm/kernel/kgdb.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/kernel/kgdb.c 2010-08-10 04:14:06.000000000 -0400
@@ -0,0 +1,206 @@
+/*
+ * arch/arm/kernel/kgdb.c
+ *
+ * ARM KGDB support
+ *
+ * Copyright (c) 2002-2004 MontaVista Software, Inc
+ * Copyright (c) 2008 Wind River Systems, Inc.
+ *
+ * Authors: George Davis
+ * Deepak Saxena
+ *
+ * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved.
+ * Manish Lachwani (lachwani@lab126.com)
+ */
+
+#include
+#include
+
+/* Make a local copy of the registers passed into the handler (bletch) */
+void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs)
+{
+ int regno;
+
+ /* Initialize all to zero. */
+ for (regno = 0; regno < GDB_MAX_REGS; regno++)
+ gdb_regs[regno] = 0;
+
+ gdb_regs[_R0] = kernel_regs->ARM_r0;
+ gdb_regs[_R1] = kernel_regs->ARM_r1;
+ gdb_regs[_R2] = kernel_regs->ARM_r2;
+ gdb_regs[_R3] = kernel_regs->ARM_r3;
+ gdb_regs[_R4] = kernel_regs->ARM_r4;
+ gdb_regs[_R5] = kernel_regs->ARM_r5;
+ gdb_regs[_R6] = kernel_regs->ARM_r6;
+ gdb_regs[_R7] = kernel_regs->ARM_r7;
+ gdb_regs[_R8] = kernel_regs->ARM_r8;
+ gdb_regs[_R9] = kernel_regs->ARM_r9;
+ gdb_regs[_R10] = kernel_regs->ARM_r10;
+ gdb_regs[_FP] = kernel_regs->ARM_fp;
+ gdb_regs[_IP] = kernel_regs->ARM_ip;
+ gdb_regs[_SPT] = kernel_regs->ARM_sp;
+ gdb_regs[_LR] = kernel_regs->ARM_lr;
+ gdb_regs[_PC] = kernel_regs->ARM_pc;
+ gdb_regs[_CPSR] = kernel_regs->ARM_cpsr;
+}
+
+/* Copy local gdb registers back to kgdb regs, for later copy to kernel */
+void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs)
+{
+ kernel_regs->ARM_r0 = gdb_regs[_R0];
+ kernel_regs->ARM_r1 = gdb_regs[_R1];
+ kernel_regs->ARM_r2 = gdb_regs[_R2];
+ kernel_regs->ARM_r3 = gdb_regs[_R3];
+ kernel_regs->ARM_r4 = gdb_regs[_R4];
+ kernel_regs->ARM_r5 = gdb_regs[_R5];
+ kernel_regs->ARM_r6 = gdb_regs[_R6];
+ kernel_regs->ARM_r7 = gdb_regs[_R7];
+ kernel_regs->ARM_r8 = gdb_regs[_R8];
+ kernel_regs->ARM_r9 = gdb_regs[_R9];
+ kernel_regs->ARM_r10 = gdb_regs[_R10];
+ kernel_regs->ARM_fp = gdb_regs[_FP];
+ kernel_regs->ARM_ip = gdb_regs[_IP];
+ kernel_regs->ARM_sp = gdb_regs[_SPT];
+ kernel_regs->ARM_lr = gdb_regs[_LR];
+ kernel_regs->ARM_pc = gdb_regs[_PC];
+ kernel_regs->ARM_cpsr = gdb_regs[_CPSR];
+}
+
+void
+sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
+{
+ struct pt_regs *thread_regs;
+ int regno;
+
+ /* Just making sure... */
+ if (task == NULL)
+ return;
+
+ /* Initialize to zero */
+ for (regno = 0; regno < GDB_MAX_REGS; regno++)
+ gdb_regs[regno] = 0;
+
+ /* Otherwise, we have only some registers from switch_to() */
+ thread_regs = task_pt_regs(task);
+ gdb_regs[_R0] = thread_regs->ARM_r0;
+ gdb_regs[_R1] = thread_regs->ARM_r1;
+ gdb_regs[_R2] = thread_regs->ARM_r2;
+ gdb_regs[_R3] = thread_regs->ARM_r3;
+ gdb_regs[_R4] = thread_regs->ARM_r4;
+ gdb_regs[_R5] = thread_regs->ARM_r5;
+ gdb_regs[_R6] = thread_regs->ARM_r6;
+ gdb_regs[_R7] = thread_regs->ARM_r7;
+ gdb_regs[_R8] = thread_regs->ARM_r8;
+ gdb_regs[_R9] = thread_regs->ARM_r9;
+ gdb_regs[_R10] = thread_regs->ARM_r10;
+ gdb_regs[_FP] = thread_regs->ARM_fp;
+ gdb_regs[_IP] = thread_regs->ARM_ip;
+ gdb_regs[_SPT] = thread_regs->ARM_sp;
+ gdb_regs[_LR] = thread_regs->ARM_lr;
+ gdb_regs[_PC] = thread_regs->ARM_pc;
+ gdb_regs[_CPSR] = thread_regs->ARM_cpsr;
+}
+
+static int compiled_break;
+
+int kgdb_arch_handle_exception(int exception_vector, int signo,
+ int err_code, char *remcom_in_buffer,
+ char *remcom_out_buffer,
+ struct pt_regs *linux_regs)
+{
+ unsigned long addr;
+ char *ptr;
+
+ switch (remcom_in_buffer[0]) {
+ case 'D':
+ case 'k':
+ case 'c':
+ kgdb_contthread = NULL;
+
+ /*
+ * Try to read optional parameter, pc unchanged if no parm.
+ * If this was a compiled breakpoint, we need to move
+ * to the next instruction or we will just breakpoint
+ * over and over again.
+ */
+ ptr = &remcom_in_buffer[1];
+ if (kgdb_hex2long(&ptr, &addr))
+ linux_regs->ARM_pc = addr;
+ else if (compiled_break == 1)
+ linux_regs->ARM_pc += 4;
+
+ compiled_break = 0;
+
+ return 0;
+ }
+
+ return -1;
+}
+
+static int kgdb_brk_fn(struct pt_regs *regs, unsigned int instr)
+{
+ kgdb_handle_exception(1, SIGTRAP, 0, regs);
+
+ return 0;
+}
+
+static int kgdb_compiled_brk_fn(struct pt_regs *regs, unsigned int instr)
+{
+ compiled_break = 1;
+ kgdb_handle_exception(1, SIGTRAP, 0, regs);
+
+ return 0;
+}
+
+static struct undef_hook kgdb_brkpt_hook = {
+ .instr_mask = 0xffffffff,
+ .instr_val = KGDB_BREAKINST,
+ .fn = kgdb_brk_fn
+};
+
+static struct undef_hook kgdb_compiled_brkpt_hook = {
+ .instr_mask = 0xffffffff,
+ .instr_val = KGDB_COMPILED_BREAK,
+ .fn = kgdb_compiled_brk_fn
+};
+
+/**
+ * kgdb_arch_init - Perform any architecture specific initalization.
+ *
+ * This function will handle the initalization of any architecture
+ * specific callbacks.
+ */
+int kgdb_arch_init(void)
+{
+ register_undef_hook(&kgdb_brkpt_hook);
+ register_undef_hook(&kgdb_compiled_brkpt_hook);
+
+ return 0;
+}
+
+/**
+ * kgdb_arch_exit - Perform any architecture specific uninitalization.
+ *
+ * This function will handle the uninitalization of any architecture
+ * specific callbacks, for dynamic registration and unregistration.
+ */
+void kgdb_arch_exit(void)
+{
+ unregister_undef_hook(&kgdb_brkpt_hook);
+ unregister_undef_hook(&kgdb_compiled_brkpt_hook);
+}
+
+/*
+ * Register our undef instruction hooks with ARM undef core.
+ * We regsiter a hook specifically looking for the KGB break inst
+ * and we handle the normal undef case within the do_undefinstr
+ * handler.
+ */
+struct kgdb_arch arch_kgdb_ops = {
+#ifndef __ARMEB__
+ .gdb_bpt_instr = {0xfe, 0xde, 0xff, 0xe7}
+#else /* ! __ARMEB__ */
+ .gdb_bpt_instr = {0xe7, 0xff, 0xde, 0xfe}
+#endif
+};
+
diff -urN linux-2.6.26/arch/arm/kernel/process.c linux-2.6.26-lab126/arch/arm/kernel/process.c
--- linux-2.6.26/arch/arm/kernel/process.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/process.c 2010-08-10 04:14:06.000000000 -0400
@@ -36,6 +36,8 @@
#include
#include
+DEFINE_RAW_SPINLOCK(futex_atomic_lock);
+
static const char *processor_modes[] = {
"USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
"UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -164,14 +166,16 @@
if (!idle)
idle = default_idle;
leds_event(led_idle_start);
- tick_nohz_stop_sched_tick();
+ tick_nohz_stop_sched_tick(1);
while (!need_resched())
idle();
leds_event(led_idle_end);
tick_nohz_restart_sched_tick();
- preempt_enable_no_resched();
- schedule();
+ local_irq_disable();
+ __preempt_enable_no_resched();
+ __schedule();
preempt_disable();
+ local_irq_enable();
}
}
@@ -185,17 +189,17 @@
__setup("reboot=", reboot_setup);
-void machine_halt(void)
-{
-}
-
-
void machine_power_off(void)
{
if (pm_power_off)
pm_power_off();
}
+void machine_halt(void)
+{
+ machine_power_off();
+}
+
void machine_restart(char * __unused)
{
arm_pm_restart(reboot_mode);
@@ -352,6 +356,15 @@
}
/*
+ * Fill in the task's elfregs structure for a core dump.
+ */
+int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs)
+{
+ elf_core_copy_regs(elfregs, task_pt_regs(t));
+ return 1;
+}
+
+/*
* fill in the fpe structure for a core dump...
*/
int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
diff -urN linux-2.6.26/arch/arm/kernel/ptrace.c linux-2.6.26-lab126/arch/arm/kernel/ptrace.c
--- linux-2.6.26/arch/arm/kernel/ptrace.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/ptrace.c 2010-08-10 04:14:06.000000000 -0400
@@ -655,6 +655,54 @@
}
#endif
+#ifdef CONFIG_VFP
+/*
+ * Get the child VFP state.
+ */
+static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
+{
+ struct thread_info *thread = task_thread_info(tsk);
+ union vfp_state *vfp = &thread->vfpstate;
+ struct user_vfp __user *ufp = data;
+
+ vfp_sync_state(thread);
+
+ /* copy the floating point registers */
+ if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
+ sizeof(vfp->hard.fpregs)))
+ return -EFAULT;
+
+ /* copy the status and control register */
+ if (put_user(vfp->hard.fpscr, &ufp->fpscr))
+ return -EFAULT;
+
+ return 0;
+}
+
+/*
+ * Set the child VFP state.
+ */
+static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
+{
+ struct thread_info *thread = task_thread_info(tsk);
+ union vfp_state *vfp = &thread->vfpstate;
+ struct user_vfp __user *ufp = data;
+
+ vfp_sync_state(thread);
+
+ /* copy the floating point registers */
+ if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
+ sizeof(vfp->hard.fpregs)))
+ return -EFAULT;
+
+ /* copy the status and control register */
+ if (get_user(vfp->hard.fpscr, &ufp->fpscr))
+ return -EFAULT;
+
+ return 0;
+}
+#endif
+
long arch_ptrace(struct task_struct *child, long request, long addr, long data)
{
int ret;
@@ -777,6 +825,15 @@
break;
#endif
+#ifdef CONFIG_VFP
+ case PTRACE_GETVFPREGS:
+ ret = ptrace_getvfpregs(child, (void __user *)data);
+ break;
+
+ case PTRACE_SETVFPREGS:
+ ret = ptrace_setvfpregs(child, (void __user *)data);
+ break;
+#endif
default:
ret = ptrace_request(child, request, addr, data);
break;
diff -urN linux-2.6.26/arch/arm/kernel/setup.c linux-2.6.26-lab126/arch/arm/kernel/setup.c
--- linux-2.6.26/arch/arm/kernel/setup.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/setup.c 2010-08-10 04:14:06.000000000 -0400
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include "compat.h"
#include "atags.h"
@@ -68,6 +69,12 @@
unsigned int __atags_pointer __initdata;
+unsigned char system_rev16[REVISION16_SIZE];
+EXPORT_SYMBOL(system_rev16);
+
+unsigned char system_serial16[SERIAL16_SIZE];
+EXPORT_SYMBOL(system_serial16);
+
unsigned int system_rev;
EXPORT_SYMBOL(system_rev);
@@ -717,9 +724,30 @@
__tagtable(ATAG_REVISION, parse_tag_revision);
+static int __init parse_tag_serial16(const struct tag *tag)
+{
+ memcpy(system_serial16, tag->u.id16.data, SERIAL16_SIZE);
+#if 0
+ printk(KERN_DEBUG "ATAGS:serial16:str=\"%.*s\"\n", SERIAL16_SIZE, system_serial16);
+#endif
+ return 0;
+}
+
+__tagtable(ATAG_SERIAL16, parse_tag_serial16);
+
+static int __init parse_tag_revision16(const struct tag *tag)
+{
+ memcpy(system_rev16, tag->u.id16.data, REVISION16_SIZE);
+ printk(KERN_DEBUG "ATAGS:rev16:str=\"%.*s\"\n", REVISION16_SIZE, system_rev16);
+ return 0;
+}
+__tagtable(ATAG_REVISION16, parse_tag_revision16);
+
static int __init parse_tag_cmdline(const struct tag *tag)
{
+#if 0
strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE);
+#endif
return 0;
}
@@ -737,6 +765,7 @@
for (t = &__tagtable_begin; t < &__tagtable_end; t++)
if (tag->hdr.tag == t->tag) {
+ // printk(KERN_DEBUG "ATAGS:tag=0x%08x size=%d\n", tag->hdr.tag, tag->hdr.size);
t->parse(tag);
break;
}
@@ -750,11 +779,12 @@
*/
static void __init parse_tags(const struct tag *t)
{
- for (; t->hdr.size; t = tag_next(t))
+ for (; (t->hdr.tag != ATAG_NONE) && t->hdr.size; t = tag_next(t)) {
if (!parse_tag(t))
printk(KERN_WARNING
"Ignoring unrecognised tag 0x%08x\n",
t->hdr.tag);
+ }
}
/*
@@ -853,6 +883,7 @@
conswitchp = &dummy_con;
#endif
#endif
+ early_trap_init();
}
@@ -980,8 +1011,28 @@
seq_printf(m, "Hardware\t: %s\n", machine_name);
seq_printf(m, "Revision\t: %04x\n", system_rev);
- seq_printf(m, "Serial\t\t: %08x%08x\n",
- system_serial_high, system_serial_low);
+
+ /* if 16-byte serial was initialized, print that. */
+ if (system_serial16[0]) {
+ char serial_num[SERIAL16_SIZE + 1];
+
+ memset(serial_num, '\0', sizeof(serial_num));
+ strncpy(serial_num, system_serial16, SERIAL16_SIZE);
+ seq_printf(m, "Serial\t\t: \"%s\"\n", serial_num);
+ } else {
+ /* no 16-byte serial, use the 64-bit one. */
+ seq_printf(m, "Serial\t\t: %08x%08x\n",
+ system_serial_high, system_serial_low);
+ }
+
+ /* if 16-byte revision was initialized, print that. */
+ if (system_rev16[0]) {
+ char board_id[REVISION16_SIZE + 1];
+
+ memset(board_id, '\0', sizeof(board_id));
+ strncpy(board_id, system_rev16, REVISION16_SIZE);
+ seq_printf(m, "BoardId\t\t: \"%s\"\n", board_id);
+ }
return 0;
}
diff -urN linux-2.6.26/arch/arm/kernel/signal.c linux-2.6.26-lab126/arch/arm/kernel/signal.c
--- linux-2.6.26/arch/arm/kernel/signal.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/signal.c 2010-08-10 04:14:06.000000000 -0400
@@ -623,6 +623,14 @@
siginfo_t info;
int signr;
+#ifdef CONFIG_PREEMPT_RT
+ /*
+ * Fully-preemptible kernel does not need interrupts disabled:
+ */
+ local_irq_enable();
+ preempt_check_resched();
+#endif
+
/*
* We want the common case to go fast, which
* is why we may in certain cases get here from
diff -urN linux-2.6.26/arch/arm/kernel/smp.c linux-2.6.26-lab126/arch/arm/kernel/smp.c
--- linux-2.6.26/arch/arm/kernel/smp.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/smp.c 2010-08-10 04:14:06.000000000 -0400
@@ -542,7 +542,7 @@
cpu_clear(cpu, data->unfinished);
}
-static DEFINE_SPINLOCK(stop_lock);
+static DEFINE_RAW_SPINLOCK(stop_lock);
/*
* ipi_cpu_stop - handle IPI from smp_send_stop()
diff -urN linux-2.6.26/arch/arm/kernel/time.c linux-2.6.26-lab126/arch/arm/kernel/time.c
--- linux-2.6.26/arch/arm/kernel/time.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/time.c 2010-08-10 04:14:06.000000000 -0400
@@ -70,7 +70,7 @@
/*
* hook for setting the RTC's idea of the current time.
*/
-int (*set_rtc)(void);
+int (*set_rtc)(struct timespec now);
#ifndef CONFIG_GENERIC_TIME
static unsigned long dummy_gettimeoffset(void)
@@ -79,34 +79,12 @@
}
#endif
-static unsigned long next_rtc_update;
-
-/*
- * If we have an externally synchronized linux clock, then update
- * CMOS clock accordingly every ~11 minutes. set_rtc() has to be
- * called as close as possible to 500 ms before the new second
- * starts.
- */
-static inline void do_set_rtc(void)
+int update_persistent_clock(struct timespec now)
{
- if (!ntp_synced() || set_rtc == NULL)
- return;
-
- if (next_rtc_update &&
- time_before((unsigned long)xtime.tv_sec, next_rtc_update))
- return;
+ if (set_rtc == NULL)
+ return -1;
- if (xtime.tv_nsec < 500000000 - ((unsigned) tick_nsec >> 1) &&
- xtime.tv_nsec >= 500000000 + ((unsigned) tick_nsec >> 1))
- return;
-
- if (set_rtc())
- /*
- * rtc update failed. Try again in 60s
- */
- next_rtc_update = xtime.tv_sec + 60;
- else
- next_rtc_update = xtime.tv_sec + 660;
+ return set_rtc(now);
}
#ifdef CONFIG_LEDS
@@ -293,9 +271,10 @@
*/
void save_time_delta(struct timespec *delta, struct timespec *rtc)
{
+ struct timespec now = current_kernel_time();
set_normalized_timespec(delta,
- xtime.tv_sec - rtc->tv_sec,
- xtime.tv_nsec - rtc->tv_nsec);
+ now.tv_sec - rtc->tv_sec,
+ now.tv_nsec - rtc->tv_nsec);
}
EXPORT_SYMBOL(save_time_delta);
@@ -324,7 +303,6 @@
{
profile_tick(CPU_PROFILING);
do_leds();
- do_set_rtc();
write_seqlock(&xtime_lock);
do_timer(1);
write_sequnlock(&xtime_lock);
diff -urN linux-2.6.26/arch/arm/kernel/traps.c linux-2.6.26-lab126/arch/arm/kernel/traps.c
--- linux-2.6.26/arch/arm/kernel/traps.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/traps.c 2010-08-10 04:14:06.000000000 -0400
@@ -29,10 +29,15 @@
#include
#include
+#ifdef CONFIG_MACH_LUIGI_LAB126
+#include
+#endif
+
#include "ptrace.h"
#include "signal.h"
static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
+extern void mxc_wd_reset(void);
#ifdef CONFIG_DEBUG_USER
unsigned int user_debug;
@@ -45,6 +50,14 @@
__setup("user_debug=", user_debug_setup);
#endif
+#ifdef CONFIG_MACH_LUIGI_LAB126
+char bug_buffer[100];
+static int bug_buffer_filled = 0;
+
+int kernel_oops_counter = 0;
+EXPORT_SYMBOL(kernel_oops_counter);
+#endif
+
static void dump_mem(const char *str, unsigned long bottom, unsigned long top);
void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame)
@@ -205,13 +218,45 @@
#define S_SMP ""
#endif
+char die_buffer[OOPS_SAVE_SIZE];
+char *die_start;
+unsigned die_len;
+static unsigned die_oops_enable;
+
+void insert_oops_chars(char c)
+{
+ if (!die_oops_enable)
+ return;
+
+ die_buffer[die_len++] = c;
+}
+EXPORT_SYMBOL(insert_oops_chars);
+
static void __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
{
struct task_struct *tsk = thread->task;
static int die_counter;
+#ifdef CONFIG_MACH_LUIGI_LAB126
+ die_len = 0; /* Initialize */
+ die_start = die_buffer;
+ kernel_oops_counter++;
+
+ die_buffer[die_len++] = 'O';
+ die_buffer[die_len++] = 'O';
+ die_buffer[die_len++] = 'P';
+ die_buffer[die_len++] = 'S';
+ die_buffer[die_len++] = ':';
+ die_start += die_len;
+
+ if (bug_buffer_filled == 1) {
+ die_len += sprintf(die_start, "%s\n", bug_buffer);
+ die_start += die_len;
+ }
+#endif
printk("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
str, err, ++die_counter);
+ sysfs_printk_last_file();
print_modules();
__show_regs(regs);
printk("Process %s (pid: %d, stack limit = 0x%p)\n",
@@ -225,7 +270,11 @@
}
}
-DEFINE_SPINLOCK(die_lock);
+DEFINE_RAW_SPINLOCK(die_lock);
+
+#ifdef CONFIG_MACH_LUIGI_LAB126
+extern void *oops_start;
+#endif
/*
* This function is protected against re-entrancy.
@@ -233,24 +282,39 @@
NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
{
struct thread_info *thread = current_thread_info();
-
+#ifdef CONFIG_MACH_LUIGI_LAB126
+ void *die_oops_start = oops_start;
+ memset(die_oops_start, 0, OOPS_SAVE_SIZE);
+ die_oops_enable = 1;
+#endif
oops_enter();
- console_verbose();
spin_lock_irq(&die_lock);
+ console_verbose();
bust_spinlocks(1);
__die(str, err, thread, regs);
+#ifdef CONFIG_MACH_LUIGI_LAB126
+ die_oops_enable = 0;
+ die_buffer[die_len++] = '\0';
+#endif
bust_spinlocks(0);
add_taint(TAINT_DIE);
+#ifdef CONFIG_MACH_LUIGI_LAB126
+ memcpy((void *)die_oops_start, (void *)die_buffer, OOPS_SAVE_SIZE);
+#endif
spin_unlock_irq(&die_lock);
+ oops_exit();
+#ifdef CONFIG_MACH_LUIGI_LAB126
+ if (bug_buffer_filled)
+ mxc_wd_reset();
+#endif
if (in_interrupt())
panic("Fatal exception in interrupt");
if (panic_on_oops)
panic("Fatal exception");
- oops_exit();
do_exit(SIGSEGV);
}
@@ -268,7 +332,7 @@
}
static LIST_HEAD(undef_hook);
-static DEFINE_SPINLOCK(undef_lock);
+static DEFINE_RAW_SPINLOCK(undef_lock);
void register_undef_hook(struct undef_hook *hook)
{
@@ -288,14 +352,27 @@
spin_unlock_irqrestore(&undef_lock, flags);
}
+static int call_arm_undef_hook(struct pt_regs *regs, unsigned int instr)
+{
+ struct undef_hook *hook;
+ unsigned long flags;
+ int (*fn)(struct pt_regs *regs, unsigned int instr) = NULL;
+
+ spin_lock_irqsave(&undef_lock, flags);
+ list_for_each_entry(hook, &undef_hook, node)
+ if ((instr & hook->instr_mask) == hook->instr_val &&
+ (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val)
+ fn = hook->fn;
+ spin_unlock_irqrestore(&undef_lock, flags);
+ return fn ? fn(regs, instr) : 1;
+}
+
asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
{
unsigned int correction = thumb_mode(regs) ? 2 : 4;
unsigned int instr;
- struct undef_hook *hook;
siginfo_t info;
void __user *pc;
- unsigned long flags;
/*
* According to the ARM ARM, PC is 2 or 4 bytes ahead,
@@ -325,17 +402,8 @@
}
#endif
- spin_lock_irqsave(&undef_lock, flags);
- list_for_each_entry(hook, &undef_hook, node) {
- if ((instr & hook->instr_mask) == hook->instr_val &&
- (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val) {
- if (hook->fn(regs, instr) == 0) {
- spin_unlock_irqrestore(&undef_lock, flags);
- return;
- }
- }
- }
- spin_unlock_irqrestore(&undef_lock, flags);
+ if (call_arm_undef_hook(regs, instr) == 0)
+ return;
#ifdef CONFIG_DEBUG_USER
if (user_debug & UDBG_UNDEFINED) {
@@ -357,6 +425,7 @@
{
printk("Hmm. Unexpected FIQ received, but trying to continue\n");
printk("You may have a hardware problem...\n");
+ print_preempt_trace(current);
}
/*
@@ -556,7 +625,7 @@
if not implemented, rather than raising SIGILL. This
way the calling program can gracefully determine whether
a feature is supported. */
- if (no <= 0x7ff)
+ if ((no & 0xffff) <= 0x7ff)
return -ENOSYS;
break;
}
@@ -660,7 +729,16 @@
void __attribute__((noreturn)) __bug(const char *file, int line)
{
+#ifdef CONFIG_MACH_LUIGI_LAB126
+ unsigned tlen;
+ char *start = bug_buffer;
+
+ tlen = sprintf(start, "kernel BUG at %s:%d!\n", file, line);
+ printk(KERN_CRIT"%s\n", bug_buffer);
+ bug_buffer_filled = 1;
+#else
printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line);
+#endif
*(int *)0 = 0;
/* Avoid "noreturn function does return" */
@@ -708,6 +786,11 @@
void __init trap_init(void)
{
+ return;
+}
+
+void __init early_trap_init(void)
+{
unsigned long vectors = CONFIG_VECTORS_BASE;
extern char __stubs_start[], __stubs_end[];
extern char __vectors_start[], __vectors_end[];
diff -urN linux-2.6.26/arch/arm/kernel/vmlinux.lds.S linux-2.6.26-lab126/arch/arm/kernel/vmlinux.lds.S
--- linux-2.6.26/arch/arm/kernel/vmlinux.lds.S 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/kernel/vmlinux.lds.S 2010-08-10 04:14:06.000000000 -0400
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
OUTPUT_ARCH(arm)
ENTRY(stext)
@@ -63,7 +64,7 @@
usr/built-in.o(.init.ramfs)
__initramfs_end = .;
#endif
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__per_cpu_start = .;
*(.data.percpu)
*(.data.percpu.shared_aligned)
@@ -71,7 +72,7 @@
#ifndef CONFIG_XIP_KERNEL
__init_begin = _stext;
INIT_DATA
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__init_end = .;
#endif
}
@@ -106,7 +107,7 @@
*(.got) /* Global offset table */
}
- RODATA
+ RO_DATA(PAGE_SIZE)
_etext = .; /* End of text and rodata section */
@@ -128,17 +129,17 @@
*(.data.init_task)
#ifdef CONFIG_XIP_KERNEL
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__init_begin = .;
INIT_DATA
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__init_end = .;
#endif
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__nosave_begin = .;
*(.data.nosave)
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__nosave_end = .;
/*
diff -urN linux-2.6.26/arch/arm/lib/Makefile linux-2.6.26-lab126/arch/arm/lib/Makefile
--- linux-2.6.26/arch/arm/lib/Makefile 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/lib/Makefile 2010-08-10 04:14:10.000000000 -0400
@@ -41,6 +41,7 @@
lib-$(CONFIG_ARCH_CLPS7500) += io-acorn.o
lib-$(CONFIG_ARCH_L7200) += io-acorn.o
lib-$(CONFIG_ARCH_SHARK) += io-shark.o
+lib-$(CONFIG_STACKTRACE) += stacktrace.o
$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S
diff -urN linux-2.6.26/arch/arm/lib/stacktrace.c linux-2.6.26-lab126/arch/arm/lib/stacktrace.c
--- linux-2.6.26/arch/arm/lib/stacktrace.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/lib/stacktrace.c 2010-08-10 04:14:10.000000000 -0400
@@ -0,0 +1,7 @@
+#include
+#include
+
+void save_stack_trace(struct stack_trace *trace)
+{
+}
+
diff -urN linux-2.6.26/arch/arm/mach-at91/gpio.c linux-2.6.26-lab126/arch/arm/mach-at91/gpio.c
--- linux-2.6.26/arch/arm/mach-at91/gpio.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-at91/gpio.c 2010-08-10 04:14:04.000000000 -0400
@@ -368,12 +368,18 @@
}
}
+static void gpio_irq_ack_noop(unsigned int irq)
+{
+ /* Dummy function. */
+}
+
static struct irq_chip gpio_irqchip = {
.name = "GPIO",
.mask = gpio_irq_mask,
.unmask = gpio_irq_unmask,
.set_type = gpio_irq_type,
.set_wake = gpio_irq_set_wake,
+ .ack = gpio_irq_ack_noop,
};
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
@@ -522,7 +528,7 @@
* shorter, and the AIC handles interrupts sanely.
*/
set_irq_chip(pin, &gpio_irqchip);
- set_irq_handler(pin, handle_simple_irq);
+ set_irq_handler(pin, handle_edge_irq);
set_irq_flags(pin, IRQF_VALID);
}
diff -urN linux-2.6.26/arch/arm/mach-footbridge/netwinder-hw.c linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-hw.c
--- linux-2.6.26/arch/arm/mach-footbridge/netwinder-hw.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-hw.c 2010-08-10 04:14:13.000000000 -0400
@@ -67,7 +67,7 @@
/*
* This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE
*/
-DEFINE_SPINLOCK(gpio_lock);
+DEFINE_RAW_SPINLOCK(gpio_lock);
static unsigned int current_gpio_op;
static unsigned int current_gpio_io;
diff -urN linux-2.6.26/arch/arm/mach-footbridge/netwinder-leds.c linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-leds.c
--- linux-2.6.26/arch/arm/mach-footbridge/netwinder-leds.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-leds.c 2010-08-10 04:14:13.000000000 -0400
@@ -32,7 +32,7 @@
static char hw_led_state;
static DEFINE_SPINLOCK(leds_lock);
-extern spinlock_t gpio_lock;
+extern raw_spinlock_t gpio_lock;
static void netwinder_leds_event(led_event_t evt)
{
diff -urN linux-2.6.26/arch/arm/mach-integrator/core.c linux-2.6.26-lab126/arch/arm/mach-integrator/core.c
--- linux-2.6.26/arch/arm/mach-integrator/core.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-integrator/core.c 2010-08-10 04:14:04.000000000 -0400
@@ -164,7 +164,7 @@
#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET
-static DEFINE_SPINLOCK(cm_lock);
+static DEFINE_RAW_SPINLOCK(cm_lock);
/**
* cm_control - update the CM_CTRL register.
diff -urN linux-2.6.26/arch/arm/mach-integrator/pci_v3.c linux-2.6.26-lab126/arch/arm/mach-integrator/pci_v3.c
--- linux-2.6.26/arch/arm/mach-integrator/pci_v3.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-integrator/pci_v3.c 2010-08-10 04:14:04.000000000 -0400
@@ -162,7 +162,7 @@
* 7:2 register number
*
*/
-static DEFINE_SPINLOCK(v3_lock);
+static DEFINE_RAW_SPINLOCK(v3_lock);
#define PCI_BUS_NONMEM_START 0x00000000
#define PCI_BUS_NONMEM_SIZE SZ_256M
diff -urN linux-2.6.26/arch/arm/mach-ixp4xx/common-pci.c linux-2.6.26-lab126/arch/arm/mach-ixp4xx/common-pci.c
--- linux-2.6.26/arch/arm/mach-ixp4xx/common-pci.c 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-ixp4xx/common-pci.c 2010-08-10 04:14:16.000000000 -0400
@@ -53,7 +53,7 @@
* these transactions are atomic or we will end up
* with corrupt data on the bus or in a driver.
*/
-static DEFINE_SPINLOCK(ixp4xx_pci_lock);
+static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
/*
* Read from PCI config space
diff -urN linux-2.6.26/arch/arm/mach-mx21/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx21/Kconfig
--- linux-2.6.26/arch/arm/mach-mx21/Kconfig 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/Kconfig 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,17 @@
+menu "MX21 Options"
+ depends on ARCH_MX21
+
+config MX21_OPTIONS
+ bool
+ default y
+ select CPU_ARM926T
+ select MXC_EMMA
+
+config MACH_MX21ADS
+ bool "Support MX21 ADS platforms"
+ default y
+ help
+ Include support for MX21 ADS platform. This includes specific
+ configurations for the board and its peripherals.
+
+endmenu
diff -urN linux-2.6.26/arch/arm/mach-mx21/Makefile linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile
--- linux-2.6.26/arch/arm/mach-mx21/Makefile 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,12 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y := mm.o time.o dma.o gpio_mux.o clock.o devices.o serial.o system.o
+obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o mx21ads_gpio.o
+
+# power management
+obj-$(CONFIG_PM) += pm.o mxc_pm.o
+obj-$(CONFIG_DPM) += dpm.o
diff -urN linux-2.6.26/arch/arm/mach-mx21/Makefile.boot linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile.boot
--- linux-2.6.26/arch/arm/mach-mx21/Makefile.boot 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile.boot 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,3 @@
+ zreladdr-y := 0xC0008000
+params_phys-y := 0xC0000100
+initrd_phys-y := 0xC0800000
diff -urN linux-2.6.26/arch/arm/mach-mx21/board-mx21ads.h linux-2.6.26-lab126/arch/arm/mach-mx21/board-mx21ads.h
--- linux-2.6.26/arch/arm/mach-mx21/board-mx21ads.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/board-mx21ads.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
+
+/*!
+ * @defgroup BRDCFG Board Configuration Options
+ * @ingroup MSL
+ */
+
+/*!
+ * @file arch-mxc/board-mx21ads.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX21 ADS Platform.
+ *
+ * @ingroup BRDCFG
+ */
+
+/*
+ * Include Files
+ */
+#include
+
+/* Start of physical RAM */
+#define PHYS_OFFSET UL(0xC0000000)
+
+/* Size of contiguous memory for DMA and other h/w blocks */
+#define CONSISTENT_DMA_SIZE SZ_8M
+
+/*!
+ * @name MXC UART EVB board level configurations
+ */
+/*! @{ */
+/*!
+ * Specify the max baudrate for the MXC UARTs for your board, do not specify a max
+ * baudrate greater than 1500000. This is used while specifying the UART Power
+ * management constraints.
+ */
+#define MAX_UART_BAUDRATE 1500000
+/*!
+ * Specifies if the Irda transmit path is inverting
+ */
+#define MXC_IRDA_TX_INV 0
+/*!
+ * Specifies if the Irda receive path is inverting
+ */
+#define MXC_IRDA_RX_INV 0
+/* UART 1 configuration */
+/*!
+ * This define specifies if the UART port is configured to be in DTE or
+ * DCE mode. There exists a define like this for each UART port. Valid
+ * values that can be used are \b MODE_DTE or \b MODE_DCE.
+ */
+#define UART1_MODE MODE_DCE
+/*!
+ * This define specifies if the UART is to be used for IRDA. There exists a
+ * define like this for each UART port. Valid values that can be used are
+ * \b IRDA or \b NO_IRDA.
+ */
+#define UART1_IR NO_IRDA
+/*!
+ * This define is used to enable or disable a particular UART port. If
+ * disabled, the UART will not be registered in the file system and the user
+ * will not be able to access it. There exists a define like this for each UART
+ * port. Specify a value of 1 to enable the UART and 0 to disable it.
+ */
+#define UART1_ENABLED 1
+/*! @} */
+/* UART 2 configuration */
+#define UART2_MODE MODE_DCE
+#define UART2_IR NO_IRDA
+#define UART2_ENABLED 1
+/* UART 3 configuration */
+#define UART3_MODE MODE_DTE
+#define UART3_IR IRDA
+#define UART3_ENABLED 1
+/* UART 4 configuration */
+#define UART4_MODE MODE_DTE
+#define UART4_IR NO_IRDA
+#define UART4_ENABLED 1 /* Enable UART 4 */
+
+#define MXC_LL_EXTUART_PADDR (CS1_BASE_ADDR + 0x200000)
+#define MXC_LL_EXTUART_VADDR CS1_IO_ADDRESS(MXC_LL_EXTUART_PADDR)
+#define MXC_LL_EXTUART_16BIT_BUS
+
+#define MXC_LL_UART_PADDR UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+
+/*!
+ * @name Memory Size parameters
+ */
+/*! @{ */
+/*!
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE SZ_64M
+/*!
+ * Size of display buffer memory
+ */
+#define MXCLCDC_MEM_SIZE SZ_8M
+/*!
+ * Size of memory available to kernel
+ */
+#define MEM_SIZE (SDRAM_MEM_SIZE - MXCLCDC_MEM_SIZE)
+/*! @} */
+
+/*! @{ */
+/*!
+ * @name Keypad Configurations
+ */
+/*! @{ */
+/*!
+ * Maximum number of rows (0 to 7)
+ */
+#define MAXROW 6
+/*!
+ * Maximum number of columns (0 to 7)
+ */
+#define MAXCOL 6
+/*! @} */
+
+/*!
+ * @name Defines Base address and IRQ used for CS8900A Ethernet Controller on MXC Boards
+ */
+/*! @{*/
+/*! This is System IRQ used by CS8900A for interrupt generation taken from platform.h */
+#define CS8900AIRQ IOMUX_TO_IRQ(MX21_PIN_UART3_RTS)
+/*! This is I/O Base address used to access registers of CS8900A on MXC ADS */
+#define CS8900A_BASE_ADDRESS (IO_ADDRESS(CS1_BASE_ADDR))
+/*! @} */
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx21/clock.c linux-2.6.26-lab126/arch/arm/mach-mx21/clock.c
--- linux-2.6.26/arch/arm/mach-mx21/clock.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/clock.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,664 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file clock.c
+ * @brief API for setting up and retrieving clocks.
+ *
+ * This file contains API for setting up and retrieving clocks.
+ *
+ * @ingroup CLOCKS
+ */
+
+#include
+#include
+#include
+#include
+#include "crm_regs.h"
+/*!
+ * Spinlock to protect CRM register accesses
+ */
+static DEFINE_SPINLOCK(mxc_crm_lock);
+
+/*!
+ * g_emma_clock_map is defined to control the emma_clock .
+ * emma_clock will be disabled until emma_prp_clk and emma_pp_clk are closed.
+ */
+#define MXC_CLK_EMMA_PRP 0
+#define MXC_CLK_EMMA_PP 1
+static int g_emma_clock_map = 0;
+
+#define MXC_REG_BIT_MOD(r, off, en) (r = (r & (~(1 << off))) | (en << off))
+
+/*!
+ * This function enables the emma clock.
+ * @param source each bit of source indicate the clock status of mdoule
+ * which is using emma clk
+ * @return none
+ */
+static void inline __enable_emma_clk(unsigned long source)
+{
+ unsigned long reg;
+
+ if (g_emma_clock_map == 0) {
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0);
+ MXC_REG_BIT_MOD(reg, CCM_PCCR0_EMMA_OFFSET, 1);
+ MXC_REG_BIT_MOD(reg, CCM_PCCR0_HCLK_EMMA_OFFSET, 1);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0);
+ }
+ g_emma_clock_map |= (1 << source);
+}
+
+/*!
+ * This function disables the emma clock.
+ * @param source each bit of source indicate the clock status of mdoule
+ * which is using emma clk
+ * @return none
+ */
+static void inline __disable_emma_clk(unsigned long source)
+{
+ unsigned long reg;
+
+ g_emma_clock_map &= ~(1 << source);
+ if (g_emma_clock_map == 0) {
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0);
+ MXC_REG_BIT_MOD(reg, CCM_PCCR0_EMMA_OFFSET, 0);
+ MXC_REG_BIT_MOD(reg, CCM_PCCR0_HCLK_EMMA_OFFSET, 0);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0);
+ }
+}
+
+/*!
+ * This function returns the PLL output value in Hz based on pll.
+ * @param pll PLL as defined in enum plls
+ * @return PLL value in Hz.
+ */
+unsigned long mxc_pll_clock(enum plls pll)
+{
+ unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+ unsigned long ref_clk = 0, pll_out = 0;
+ volatile unsigned long reg, cscr;
+
+ cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ if (pll == MCUPLL) {
+ if ((cscr & CCM_CSCR_MCU) != 0) {
+ ref_clk = CKIH_CLK_FREQ;
+ } else {
+ ref_clk = CKIL_CLK_FREQ;
+ }
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_MPCTL0);
+ pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
+ mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+ mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+ mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+ } else if (pll == SERIALPLL) {
+ if ((cscr & CCM_CSCR_SP) != 0) {
+ ref_clk = CKIH_CLK_FREQ;
+ } else {
+ ref_clk = CKIL_CLK_FREQ;
+ }
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_SPCTL0);
+ pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+ mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+ mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+ mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+ } else {
+ printk(KERN_ERR "Wrong PLL: %d\n", pll);
+ BUG(); /* oops */
+ }
+
+ mfi = (mfi <= 5) ? 5 : mfi;
+ pll_out = (2 * ref_clk * mfi + ((2 * ref_clk / (mfd + 1)) * mfn)) /
+ (pdf + 1);
+ return pll_out;
+}
+
+/*!
+ * This function returns the mcu main clock frequency
+ *
+ * @return mcu main clock value in Hz.
+ */
+static unsigned long mxc_mcu_main_clock(void)
+{
+ return mxc_pll_clock(MCUPLL);
+}
+
+/*!
+ * This function returns the main clock values in Hz.
+ *
+ * @param clk as defined in enum mxc_clocks
+ *
+ * @return clock value in Hz
+ */
+unsigned long mxc_get_clocks(enum mxc_clocks clk)
+{
+ unsigned long pll, spll, ret_val = 0, hclk;
+ unsigned long presc_pdf, ipg_pdf, nfc_pdf, usb_pdf;
+ volatile unsigned long cscr =
+ __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ volatile unsigned long pcdr0 =
+ __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ volatile unsigned long pcdr1 =
+ __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+
+ unsigned long fclk, ipgclk, perclk1, perclk2, perclk3, perclk4;
+ unsigned long bclk_pdf;
+ unsigned long perclk1_pdf, perclk2_pdf, perclk3_pdf, perclk4_pdf;
+ unsigned long clk_src;
+ unsigned long ssi1_pdf = 0;
+ unsigned long ssi2_pdf = 0;
+ presc_pdf = (cscr & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+ bclk_pdf = (cscr & CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET;
+ ipg_pdf = (cscr & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+ perclk1_pdf =
+ (pcdr1 & CCM_PCDR1_PERDIV1_MASK) >> CCM_PCDR1_PERDIV1_OFFSET;
+ perclk2_pdf =
+ (pcdr1 & CCM_PCDR1_PERDIV2_MASK) >> CCM_PCDR1_PERDIV2_OFFSET;
+ perclk3_pdf =
+ (pcdr1 & CCM_PCDR1_PERDIV3_MASK) >> CCM_PCDR1_PERDIV3_OFFSET;
+ perclk4_pdf =
+ (pcdr1 & CCM_PCDR1_PERDIV4_MASK) >> CCM_PCDR1_PERDIV4_OFFSET;
+
+ pll = mxc_mcu_main_clock();
+ spll = mxc_pll_clock(SERIALPLL);
+ fclk = pll / (presc_pdf + 1);
+ hclk = fclk / (bclk_pdf + 1);
+ ipgclk = hclk / (ipg_pdf + 1);
+ perclk1 = pll / (perclk1_pdf + 1);
+ perclk2 = pll / (perclk2_pdf + 1);
+ perclk3 = pll / (perclk3_pdf + 1);
+ perclk4 = pll / (perclk4_pdf + 1);
+ switch (clk) {
+ case CPU_CLK:
+ ret_val = fclk;
+ break;
+ case AHB_CLK:
+ ret_val = hclk;
+ break;
+ case PERCLK1:
+ case UART6_BAUD:
+ case UART5_BAUD:
+ case UART4_BAUD:
+ case UART3_BAUD:
+ case UART2_BAUD:
+ case UART1_BAUD:
+ case GPT6_CLK:
+ case GPT5_CLK:
+ case GPT4_CLK:
+ case GPT3_CLK:
+ case GPT2_CLK:
+ case GPT1_CLK:
+ case PWM_CLK:
+ ret_val = perclk1;
+ break;
+ case PERCLK2:
+ case SDHC2_CLK:
+ case SDHC1_CLK:
+ case CSPI3_CLK:
+ case CSPI2_CLK:
+ case CSPI1_CLK:
+ ret_val = perclk2;
+ break;
+ case PERCLK3:
+ case LCDC_CLK:
+ ret_val = perclk3;
+ break;
+ case PERCLK4:
+ case CSI_BAUD:
+ ret_val = perclk4;
+ break;
+ case USB_CLK:
+ usb_pdf = (cscr & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+ ret_val = spll / (usb_pdf + 1);
+ break;
+ case SSI1_BAUD:
+ ssi1_pdf = (pcdr0 & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
+ CCM_PCDR0_SSI1BAUDDIV_OFFSET;
+ clk_src = (cscr & CCM_CSCR_SSI1) >> CCM_CSCR_SSI1_OFFSET;
+ if (clk_src)
+ ret_val = pll / (ssi1_pdf + 1);
+ else
+ ret_val = spll / (ssi1_pdf + 1);
+ break;
+ case SSI2_BAUD:
+ ssi1_pdf = (pcdr0 & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+ CCM_PCDR0_SSI2BAUDDIV_OFFSET;
+ clk_src = (cscr & CCM_CSCR_SSI2) >> CCM_CSCR_SSI2_OFFSET;
+ if (clk_src)
+ ret_val = pll / (ssi2_pdf + 1);
+ else
+ ret_val = spll / (ssi2_pdf + 1);
+ break;
+ case NFC_CLK:
+ nfc_pdf = (pcdr0 & CCM_PCDR0_NFCDIV_MASK) >>
+ CCM_PCDR0_NFCDIV_OFFSET;
+ ret_val = hclk / (nfc_pdf + 1);
+ break;
+ default:
+ ret_val = ipgclk;
+ break;
+ }
+ return ret_val;
+}
+
+/*!
+ * This function returns the parent clock values in Hz.
+ *
+ * @param clk as defined in enum mxc_clocks
+ *
+ * @return clock value in Hz
+ */
+unsigned long mxc_get_clocks_parent(enum mxc_clocks clk)
+{
+ unsigned long ret_val = 0;
+
+ switch (clk) {
+ case CSI_BAUD:
+ ret_val = mxc_mcu_main_clock();
+ break;
+ default:
+ break;
+ }
+ return ret_val;
+}
+
+/*!
+ * This function sets the PLL source for a clock.
+ *
+ * @param clk as defined in enum mxc_clocks
+ * @param pll_num the PLL that you wish to use as source for this clock
+ */
+void mxc_set_clocks_pll(enum mxc_clocks clk, enum plls pll_num)
+{
+ volatile unsigned long cscr;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mxc_crm_lock, flags);
+ cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+
+ switch (clk) {
+ case SSI1_BAUD:
+ cscr = (cscr & (~CCM_CSCR_SSI1)) |
+ (pll_num << CCM_CSCR_SSI1_OFFSET);
+ break;
+ case SSI2_BAUD:
+ cscr = (cscr & (~CCM_CSCR_SSI2)) |
+ (pll_num << CCM_CSCR_SSI2_OFFSET);
+ break;
+ default:
+ pr_info("Can't choose its clock source: %d\n", clk);
+ break;
+ }
+ __raw_writel(cscr, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ spin_unlock_irqrestore(&mxc_crm_lock, flags);
+ return;
+}
+
+/*!
+ * This function sets the divider value for a clock.
+ *
+ * @param clk as defined in enum mxc_clocks
+ * @param div the division factor to be used for the clock (For SSI & CSI, pass
+ * in 2 times the expected division value to account for FP vals on certain
+ * platforms)
+ */
+void mxc_set_clocks_div(enum mxc_clocks clk, unsigned int div)
+{
+ volatile unsigned long reg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mxc_crm_lock, flags);
+
+ switch (clk) {
+ case SSI2_BAUD:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ reg = (reg & (~CCM_PCDR0_SSI2BAUDDIV_MASK)) |
+ ((div - 1) << CCM_PCDR0_SSI2BAUDDIV_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ break;
+ case SSI1_BAUD:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ reg = (reg & (~CCM_PCDR0_SSI1BAUDDIV_MASK)) |
+ ((div - 1) << CCM_PCDR0_SSI1BAUDDIV_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ break;
+ case NFC_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ reg = (reg & (~CCM_PCDR0_NFCDIV_MASK)) |
+ ((div - 1) << CCM_PCDR0_NFCDIV_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ break;
+ case PERCLK1:
+ case UART4_BAUD:
+ case UART3_BAUD:
+ case UART2_BAUD:
+ case UART1_BAUD:
+ case GPT3_CLK:
+ case GPT2_CLK:
+ case GPT1_CLK:
+ case PWM_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ reg = (reg & (~CCM_PCDR1_PERDIV1_MASK)) |
+ ((div - 1) << CCM_PCDR1_PERDIV1_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ break;
+ case PERCLK2:
+ case SDHC2_CLK:
+ case SDHC1_CLK:
+ case CSPI3_CLK:
+ case CSPI2_CLK:
+ case CSPI1_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ reg = (reg & (~CCM_PCDR1_PERDIV2_MASK)) |
+ ((div - 1) << CCM_PCDR1_PERDIV2_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ break;
+ case PERCLK3:
+ case LCDC_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ reg = (reg & (~CCM_PCDR1_PERDIV3_MASK)) |
+ ((div - 1) << CCM_PCDR1_PERDIV3_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ break;
+ case PERCLK4:
+ case CSI_BAUD:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ reg = (reg & (~CCM_PCDR1_PERDIV4_MASK)) |
+ ((div - 1) << CCM_PCDR1_PERDIV4_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1);
+ break;
+ case USB_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ reg = (reg & (~CCM_CSCR_USB_MASK)) |
+ ((div - 1) << CCM_CSCR_USB_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ break;
+ case IPG_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ reg = (reg & (~CCM_CSCR_IPDIV)) |
+ ((div - 1) << CCM_CSCR_IPDIV_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ break;
+ case CPU_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ reg = (reg & (~CCM_CSCR_PRESC_MASK)) |
+ ((div - 1) << CCM_CSCR_PRESC_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ break;
+ case AHB_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ reg = (reg & (~CCM_CSCR_BCLK_MASK)) |
+ ((div - 1) << CCM_CSCR_BCLK_OFFSET);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock_irqrestore(&mxc_crm_lock, flags);
+}
+
+static void __mxc_clks_config(enum mxc_clocks clk, int enable)
+{
+ unsigned long flags, reg_up = 0;
+ volatile unsigned long reg0, reg1;
+
+ spin_lock_irqsave(&mxc_crm_lock, flags);
+
+ reg0 = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0);
+ reg1 = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR1);
+
+ switch (clk) {
+ case CSI_BAUD:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_PERCLK4_OFFSET, enable);
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_CSI_OFFSET, enable);
+ break;
+ case DMA_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_DMA_OFFSET, enable);
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_DMA_OFFSET, enable);
+ break;
+ case BROM_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_BROM_OFFSET, enable);
+ break;
+ case EMMA_PRP_CLK:
+ __enable_emma_clk(MXC_CLK_EMMA_PRP);
+ goto clk_cfg_out;
+ break;
+ case EMMA_PP_CLK:
+ __enable_emma_clk(MXC_CLK_EMMA_PP);
+ goto clk_cfg_out;
+ break;
+ case LCDC_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_LCDC_OFFSET, enable);
+ break;
+ case SLCDC_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SLCDC_OFFSET, enable);
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_SLCDC_OFFSET, enable);
+ break;
+ case USB_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_USBOTG_OFFSET, enable);
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_USBOTG_OFFSET, enable);
+ break;
+ case SSI1_BAUD:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI1_BAUD_OFFSET, enable);
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI1_OFFSET, enable);
+ break;
+ case SSI2_BAUD:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI2_BAUD_OFFSET, enable);
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI2_OFFSET, enable);
+ break;
+ case NFC_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_NFC_OFFSET, enable);
+ break;
+ case UART1_BAUD:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART1_OFFSET, enable);
+ break;
+ case UART2_BAUD:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART2_OFFSET, enable);
+ break;
+ case UART3_BAUD:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART3_OFFSET, enable);
+ break;
+ case UART4_BAUD:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART4_OFFSET, enable);
+ break;
+ case WDOG_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_WDT_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case CSPI3_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_CSPI3_OFFSET, enable);
+ break;
+ case CSPI2_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_CSPI2_OFFSET, enable);
+ break;
+ case CSPI1_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_CSPI1_OFFSET, enable);
+ break;
+ case GPIO_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_GPIO_OFFSET, enable);
+ break;
+ case GPT3_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_GPT3_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case GPT2_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_GPT2_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case GPT1_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_GPT1_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case I2C1_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_I2C_OFFSET, enable);
+ break;
+ case KPP_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_KPP_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case OWIRE_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_OWIRE_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case PWM_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_PWM_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case RTC_CLK:
+ MXC_REG_BIT_MOD(reg1, CCM_PCCR1_RTC_OFFSET, enable);
+ reg_up = 1;
+ break;
+ case SDHC2_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SDHC2_OFFSET, enable);
+ break;
+ case SDHC1_CLK:
+ MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SDHC1_OFFSET, enable);
+ break;
+ default:
+ goto clk_cfg_out;
+ }
+ if (reg_up == 0) {
+ __raw_writel(reg0, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0);
+ } else if (reg_up == 1) {
+ __raw_writel(reg1, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR1);
+ } else {
+ __raw_writel(reg0, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0);
+ __raw_writel(reg1, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR1);
+ }
+
+ clk_cfg_out:
+ spin_unlock_irqrestore(&mxc_crm_lock, flags);
+}
+
+/*!
+ * This function is called to enable the individual module clocks
+ *
+ * @param clk as defined in enum mxc_clocks
+ */
+
+void mxc_clks_enable(enum mxc_clocks clk)
+{
+ __mxc_clks_config(clk, 1);
+}
+
+/*!
+ * This function is called to disable the individual module clocks
+ *
+ * @param clk as defined in enum mxc_clocks
+ */
+void mxc_clks_disable(enum mxc_clocks clk)
+{
+ __mxc_clks_config(clk, 0);
+}
+
+/*!
+ * This function is used to modify PLL registers to generate the required
+ * frequency.
+ *
+ * @param pll_num the PLL that you wish to modify
+ * @param mfi multiplication factor integer part
+ * @param pdf pre-division factor
+ * @param mfd multiplication factor denominator
+ * @param mfn multiplication factor numerator
+ */
+void mxc_pll_set(enum plls pll_num, unsigned int mfi, unsigned int pdf,
+ unsigned int mfd, unsigned int mfn)
+{
+ volatile unsigned long cscr;
+ unsigned long flags;
+ unsigned long new_pll = 0;
+
+ spin_lock_irqsave(&mxc_crm_lock, flags);
+
+ if (pll_num == MCUPLL) {
+ /* Change the Pll value */
+ new_pll = (mfi << CCM_MPCTL0_MFI_OFFSET) |
+ (mfn << CCM_MPCTL0_MFN_OFFSET) |
+ (mfd << CCM_MPCTL0_MFD_OFFSET) |
+ (pdf << CCM_MPCTL0_PD_OFFSET);
+
+ __raw_writel(new_pll, IO_ADDRESS(CCM_BASE_ADDR) + CCM_MPCTL0);
+ /* Swap to reference clock and disable PLL */
+ cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ cscr |= CCM_CSCR_MPLLRES;
+ __raw_writel(cscr, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ } else {
+ if (pll_num == SERIALPLL) {
+ /* Change the Pll value */
+ new_pll = (mfi << CCM_SPCTL0_MFI_OFFSET) |
+ (mfn << CCM_SPCTL0_MFN_OFFSET) |
+ (mfd << CCM_SPCTL0_MFD_OFFSET) |
+ (pdf << CCM_SPCTL0_PD_OFFSET);
+
+ __raw_writel(new_pll,
+ IO_ADDRESS(CCM_BASE_ADDR) + CCM_SPCTL0);
+ /* Swap to reference clock and disable PLL */
+ cscr =
+ __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ cscr |= CCM_CSCR_SPLLRES;
+ __raw_writel(cscr,
+ IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ }
+ }
+
+ spin_unlock_irqrestore(&mxc_crm_lock, flags);
+}
+
+/*!
+ * Configure clock output on CKO pins
+ *
+ * @param output clock output pin
+ * @param clk clock source to output
+ * @param div CLKO divider
+ *
+ */
+void mxc_set_clock_output(enum mxc_clk_out output, enum mxc_clocks clk, int div)
+{
+ unsigned long flags;
+ volatile unsigned long reg;
+
+ if (output != CKO) {
+ return;
+ }
+
+ spin_lock_irqsave(&mxc_crm_lock, flags);
+
+ switch (clk) {
+ case CKIH_CLK:
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CCSR);
+ reg = (reg & (~0x1f)) | 0x2;
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CCSR);
+
+ reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+ reg = (reg & (~0x03c00000)) | 0x02000000 | ((div - 1) << 22);
+ __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0);
+
+ break;
+ default:
+ break;
+ };
+
+ spin_unlock_irqrestore(&mxc_crm_lock, flags);
+ return;
+}
+
+EXPORT_SYMBOL(mxc_pll_set);
+EXPORT_SYMBOL(mxc_pll_clock);
+EXPORT_SYMBOL(mxc_get_clocks);
+EXPORT_SYMBOL(mxc_set_clocks_pll);
+EXPORT_SYMBOL(mxc_set_clocks_div);
+EXPORT_SYMBOL(mxc_clks_disable);
+EXPORT_SYMBOL(mxc_clks_enable);
+EXPORT_SYMBOL(mxc_set_clock_output);
+EXPORT_SYMBOL(mxc_get_clocks_parent);
diff -urN linux-2.6.26/arch/arm/mach-mx21/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx21/crm_regs.h
--- linux-2.6.26/arch/arm/mach-mx21/crm_regs.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/crm_regs.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ARCH_ARM_MACH_MX21_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX21_CRM_REGS_H__
+
+#include
+
+/* Register offsets */
+#define CCM_CSCR 0x0
+#define CCM_MPCTL0 0x4
+#define CCM_MPCTL1 0x8
+#define CCM_SPCTL0 0xC
+#define CCM_SPCTL1 0x10
+#define CCM_OSC26MCTL 0x14
+#define CCM_PCDR0 0x18
+#define CCM_PCDR1 0x1C
+#define CCM_PCCR0 0x20
+#define CCM_PCCR1 0x24
+#define CCM_CCSR 0x28
+#define CCM_PMCTL 0x2C
+#define CCM_PMCOUNT 0x30
+#define CCM_WKGDCTL 0x34
+
+#define CCM_CSCR_PRESC_OFFSET 29
+#define CCM_CSCR_PRESC_MASK (0x7 << 29)
+#define CCM_CSCR_USB_OFFSET 26
+#define CCM_CSCR_USB_MASK (0x7 << 26)
+#define CCM_CSCR_SD_OFFSET 24
+#define CCM_CSCR_SD_MASK (0x3 << 24)
+#define CCM_CSCR_SPLLRES (1 << 22)
+#define CCM_CSCR_MPLLRES (1 << 21)
+#define CCM_CSCR_SSI2 (1 << 20)
+#define CCM_CSCR_SSI2_OFFSET 20
+#define CCM_CSCR_SSI1 (1 << 19)
+#define CCM_CSCR_SSI1_OFFSET 19
+#define CCM_CSCR_SP (1 << 17)
+#define CCM_CSCR_MCU (1 << 16)
+#define CCM_CSCR_BCLK_OFFSET 10
+#define CCM_CSCR_BCLK_MASK (0xF << 10)
+#define CCM_CSCR_IPDIV_OFFSET 9
+#define CCM_CSCR_IPDIV (1 << 9)
+#define CCM_CSCR_OSC26MDIV (1 << 4)
+#define CCM_CSCR_OSC26M (1 << 3)
+#define CCM_CSCR_FPM (1 << 2)
+#define CCM_CSCR_SPEN (1 << 1)
+#define CCM_CSCR_MPEN (1 << 0)
+
+#define CCM_MPCTL0_CPLM (1 << 31)
+#define CCM_MPCTL0_PD_OFFSET 26
+#define CCM_MPCTL0_PD_MASK (0xF << 26)
+#define CCM_MPCTL0_MFD_OFFSET 16
+#define CCM_MPCTL0_MFD_MASK (0x3FF << 16)
+#define CCM_MPCTL0_MFI_OFFSET 10
+#define CCM_MPCTL0_MFI_MASK (0xF << 10)
+#define CCM_MPCTL0_MFN_OFFSET 0
+#define CCM_MPCTL0_MFN_MASK 0x3FF
+
+#define CCM_MPCTL1_LF (1 << 15)
+#define CCM_MPCTL1_BRMO (1 << 6)
+
+#define CCM_SPCTL0_CPLM (1 << 31)
+#define CCM_SPCTL0_PD_OFFSET 26
+#define CCM_SPCTL0_PD_MASK (0xF << 26)
+#define CCM_SPCTL0_MFD_OFFSET 16
+#define CCM_SPCTL0_MFD_MASK (0x3FF << 16)
+#define CCM_SPCTL0_MFI_OFFSET 10
+#define CCM_SPCTL0_MFI_MASK (0xF << 10)
+#define CCM_SPCTL0_MFN_OFFSET 0
+#define CCM_SPCTL0_MFN_MASK 0x3FF
+
+#define CCM_SPCTL1_LF (1 << 15)
+#define CCM_SPCTL1_BRMO (1 << 6)
+
+#define CCM_OSC26MCTL_PEAK_OFFSET 16
+#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
+#define CCM_OSC26MCTL_AGC_OFFSET 8
+#define CCM_OSC26MCTL_AGC_MASK (0x3F << 8)
+
+#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
+#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3F << 26)
+#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
+#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3F << 16)
+#define CCM_PCDR0_NFCDIV_OFFSET 12
+#define CCM_PCDR0_NFCDIV_MASK (0xF << 12)
+#define CCM_PCDR0_CLKO48MDIV_OFFSET 5
+#define CCM_PCDR0_CLKO48MDIV_MASK (0x7 << 5)
+#define CCM_PCDR0_FIRIDIV_OFFSET 0
+#define CCM_PCDR0_FIRIDIV_MASK 0x1F
+
+#define CCM_PCDR1_PERDIV4_OFFSET 24
+#define CCM_PCDR1_PERDIV4_MASK (0x3F << 24)
+#define CCM_PCDR1_PERDIV3_OFFSET 16
+#define CCM_PCDR1_PERDIV3_MASK (0x3F << 16)
+#define CCM_PCDR1_PERDIV2_OFFSET 8
+#define CCM_PCDR1_PERDIV2_MASK (0x3F << 8)
+#define CCM_PCDR1_PERDIV1_OFFSET 0
+#define CCM_PCDR1_PERDIV1_MASK 0x3F
+
+#define CCM_PCCR0_HCLK_CSI_OFFSET 31
+#define CCM_PCCR0_HCLK_DMA_OFFSET 30
+#define CCM_PCCR0_HCLK_BROM_OFFSET 28
+#define CCM_PCCR0_HCLK_EMMA_OFFSET 27
+#define CCM_PCCR0_HCLK_LCDC_OFFSET 26
+#define CCM_PCCR0_HCLK_SLCDC_OFFSET 25
+#define CCM_PCCR0_HCLK_USBOTG_OFFSET 24
+#define CCM_PCCR0_HCLK_BMI_OFFSET 23
+#define CCM_PCCR0_PERCLK4_OFFSET 22
+#define CCM_PCCR0_SLCDC_OFFSET 21
+#define CCM_PCCR0_FIRI_BAUD_OFFSET 20
+#define CCM_PCCR0_NFC_OFFSET 19
+#define CCM_PCCR0_PERCLK3_OFFSET 18
+#define CCM_PCCR0_SSI1_BAUD_OFFSET 17
+#define CCM_PCCR0_SSI2_BAUD_OFFSET 16
+#define CCM_PCCR0_EMMA_OFFSET 15
+#define CCM_PCCR0_USBOTG_OFFSET 14
+#define CCM_PCCR0_DMA_OFFSET 13
+#define CCM_PCCR0_I2C_OFFSET 12
+#define CCM_PCCR0_GPIO_OFFSET 11
+#define CCM_PCCR0_SDHC2_OFFSET 10
+#define CCM_PCCR0_SDHC1_OFFSET 9
+#define CCM_PCCR0_FIRI_OFFSET 8
+#define CCM_PCCR0_SSI2_OFFSET 7
+#define CCM_PCCR0_SSI1_OFFSET 6
+#define CCM_PCCR0_CSPI2_OFFSET 5
+#define CCM_PCCR0_CSPI1_OFFSET 4
+#define CCM_PCCR0_UART4_OFFSET 3
+#define CCM_PCCR0_UART3_OFFSET 2
+#define CCM_PCCR0_UART2_OFFSET 1
+#define CCM_PCCR0_UART1_OFFSET 0
+
+#define CCM_PCCR1_OWIRE_OFFSET 31
+#define CCM_PCCR1_KPP_OFFSET 30
+#define CCM_PCCR1_RTC_OFFSET 29
+#define CCM_PCCR1_PWM_OFFSET 28
+#define CCM_PCCR1_GPT3_OFFSET 27
+#define CCM_PCCR1_GPT2_OFFSET 26
+#define CCM_PCCR1_GPT1_OFFSET 25
+#define CCM_PCCR1_WDT_OFFSET 24
+#define CCM_PCCR1_CSPI3_OFFSET 23
+#define CCM_PCCR1_RTIC_OFFSET 22
+#define CCM_PCCR1_RNGA_OFFSET 21
+
+#define CCM_CCSR_32KSR (1 << 15)
+#define CCM_CCSR_CLKOSEL_OFFSET 0
+#define CCM_CCSR_CLKOSEL_MASK 0x1f
+
+#define CKIH_CLK_FREQ 26000000 /* 26M reference clk */
+#define CKIL_CLK_FREQ (32768 * 512) /* 32.768k oscillator in */
+
+#define SYS_FMCR 0x8 /* Functional Muxing Control Reg */
+
+#endif /* __ARCH_ARM_MACH_MX21_CRM_REGS_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx21/devices.c linux-2.6.26-lab126/arch/arm/mach-mx21/devices.c
--- linux-2.6.26/arch/arm/mach-mx21/devices.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/devices.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,278 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+ /*!
+ * @file devices.c
+ * @brief device configurations including nor/nand/watchdog for mx27.
+ *
+ * @ingroup MSL
+ */
+
+/* FIXME: SDHC is not supported yet! */
+
+static void mxc_nop_release(struct device *dev)
+{
+ /* Nothing */
+}
+
+#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE)
+
+static struct resource wdt_resources[] = {
+ {
+ .start = WDOG_BASE_ADDR,
+ .end = WDOG_BASE_ADDR + 0x30,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device mxc_wdt_device = {
+ .name = "mxc_wdt",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ },
+ .num_resources = ARRAY_SIZE(wdt_resources),
+ .resource = wdt_resources,
+};
+
+static void mxc_init_wdt(void)
+{
+ mxc_clks_enable(WDOG_CLK);
+ (void)platform_device_register(&mxc_wdt_device);
+}
+#else
+static inline void mxc_init_wdt(void)
+{
+}
+#endif
+
+/* MMC device data */
+
+#if defined(CONFIG_MMC_MXC) || defined(CONFIG_MMC_MXC_MODULE)
+
+extern unsigned int sdhc_get_card_det_status(struct device *dev);
+extern int sdhc_init_card_det(int id);
+
+static struct mxc_mmc_platform_data mmc_data = {
+ .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30,
+ .min_clk = 150000,
+ .max_clk = 25000000,
+ .card_inserted_state = 0,
+ .status = sdhc_get_card_det_status,
+};
+
+/*!
+ * Resource definition for the SDHC1
+ */
+static struct resource mxcsdhc1_resources[] = {
+ [0] = {
+ .start = SDHC1_BASE_ADDR,
+ .end = SDHC1_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_SDHC1,
+ .end = INT_SDHC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = MXC_SDIO1_CARD_IRQ,
+ .end = MXC_SDIO1_CARD_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*!
+ * Resource definition for the SDHC2
+ */
+static struct resource mxcsdhc2_resources[] = {
+ [0] = {
+ .start = SDHC2_BASE_ADDR,
+ .end = SDHC2_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_SDHC2,
+ .end = INT_SDHC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = MXC_SDIO2_CARD_IRQ,
+ .end = MXC_SDIO2_CARD_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Device Definition for MXC SDHC1 */
+static struct platform_device mxcsdhc1_device = {
+ .name = "mxcmci",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mmc_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
+ .resource = mxcsdhc1_resources,
+};
+
+/*! Device Definition for MXC SDHC2 */
+static struct platform_device mxcsdhc2_device = {
+ .name = "mxcmci",
+ .id = 1,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mmc_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcsdhc2_resources),
+ .resource = mxcsdhc2_resources,
+};
+
+static inline void mxc_init_mmc(void)
+{
+ int cd_irq;
+
+ /*cd_irq = sdhc_init_card_det(0);
+ if (cd_irq) {
+ mxcsdhc1_device.resource[2].start = cd_irq;
+ mxcsdhc1_device.resource[2].end = cd_irq;
+ } */
+ cd_irq = sdhc_init_card_det(1);
+ if (cd_irq) {
+ mxcsdhc2_device.resource[2].start = cd_irq;
+ mxcsdhc2_device.resource[2].end = cd_irq;
+ }
+
+ /*(void)platform_device_register(&mxcsdhc1_device); */
+ (void)platform_device_register(&mxcsdhc2_device);
+}
+#else
+static inline void mxc_init_mmc(void)
+{
+}
+#endif
+
+/* I2C controller and device data */
+#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE)
+
+/*!
+ * Resource definition for the I2C1
+ */
+static struct resource mxci2c1_resources[] = {
+ [0] = {
+ .start = I2C_BASE_ADDR,
+ .end = I2C_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_I2C,
+ .end = INT_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Platform Data for MXC I2C */
+static struct mxc_i2c_platform_data mxci2c1_data = {
+ .clk = I2C_CLK,
+ .i2c_clk = 100000,
+};
+
+/*! Device Definition for MXC I2C1 */
+static struct platform_device mxci2c1_device = {
+ .name = "mxc_i2c",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxci2c1_data,
+ },
+ .num_resources = ARRAY_SIZE(mxci2c1_resources),
+ .resource = mxci2c1_resources,
+};
+
+static inline void mxc_init_i2c(void)
+{
+ if (platform_device_register(&mxci2c1_device) < 0)
+ dev_err(&mxci2c1_device.dev, "Unable to register I2C device\n");
+}
+#else
+static inline void mxc_init_i2c(void)
+{
+}
+#endif
+
+struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = {
+ {
+ .num = 0,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR),
+ .irq = INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_BASE,
+ },
+ {
+ .num = 1,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x100,
+ .irq = INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN,
+ },
+ {
+ .num = 2,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x200,
+ .irq = INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 2,
+ },
+ {
+ .num = 3,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x300,
+ .irq = INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 3,
+ },
+ {
+ .num = 4,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x400,
+ .irq = INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 4,
+ },
+ {
+ .num = 5,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x500,
+ .irq = INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 5,
+ },
+};
+
+static int __init mxc_init_devices(void)
+{
+ mxc_init_wdt();
+ mxc_init_mmc();
+ mxc_init_i2c();
+ return 0;
+}
+
+arch_initcall(mxc_init_devices);
diff -urN linux-2.6.26/arch/arm/mach-mx21/dma.c linux-2.6.26-lab126/arch/arm/mach-mx21/dma.c
--- linux-2.6.26/arch/arm/mach-mx21/dma.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/dma.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ *@file dma_data.c
+ *@brief This file contains the private definition .
+ * @ingroup DMA
+ */
+
+#include
+#include
+#include
+
+/*!
+ * @brief the structure stored device_id and dma_info pointer
+ */
+typedef struct dma_info_entry_s {
+ mxc_dma_device_t device;
+ /* if there are two dma_info , first is for reading, another is for writing */
+ mx2_dma_info_t *info[2];
+} dma_info_entry_t;
+
+/*!
+ * @brief dma_info from memory to memory for dma testing
+ */
+static mx2_dma_info_t ram2ram_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 0
+};
+
+/*!
+ * @brief dma_info from 2D memory to 2D memory for dma testing
+ */
+static mx2_dma_info_t ram2d2ram2d_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .rto_en = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 1,.msel = 0,.W = 0x80,.X = 0x40,.Y = 0x10
+};
+
+/*!
+ * @brief dma_info from memory to 2D memory for dma testing
+ */
+static mx2_dma_info_t ram2ram2d_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x80,.Y = 0x10
+};
+
+/*!
+ * @brief dma_info from 2D memory to memory for dma testing
+ */
+static mx2_dma_info_t ram2d2ram_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x100,.Y = 0x10
+};
+
+/*!
+ * @brief dma_info with dma chaining feature for dma testing
+ */
+static mx2_dma_info_t hw_chaining_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 1,.repeat = 1,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info without dma chaining feature for dma testing
+ */
+static mx2_dma_info_t sw_chaining_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART1 recieveing
+ */
+static mx2_dma_info_t uart1_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 1,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 26,.busuntils = 8,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART1_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART1 transmitting
+ */
+static mx2_dma_info_t uart1_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 27,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT,
+ .per_address = (UART1_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART2 recieveing
+ */
+static mx2_dma_info_t uart2_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 24,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART2_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART2 transmitting
+ */
+static mx2_dma_info_t uart2_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 25,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT,
+ .per_address = (UART2_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART3 recieveing
+ */
+static mx2_dma_info_t uart3_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 22,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART3_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART3 transmitting
+ */
+static mx2_dma_info_t uart3_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 23,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT,
+ .per_address = (UART3_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART4 recieveing
+ */
+static mx2_dma_info_t uart4_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 20,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART4_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART4transmitting
+ */
+static mx2_dma_info_t uart4_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 1,.request = 21,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT,
+ .per_address = (UART4_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi1_16bit_rx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI1_RX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SSI1_BASE_ADDR + 0x08),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi1_16bit_tx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI1_TX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_16,
+ .per_address = (SSI1_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi2_16bit_rx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI2_RX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SSI2_BASE_ADDR + 0x08),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi2_16bit_tx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI2_TX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_16,
+ .per_address = (SSI2_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc1_width1_dma_rx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 16,.request = DMA_REQ_SDHC1,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC1_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc1_width1_dma_tx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 16,.request = DMA_REQ_SDHC1,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC1_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc1_width4_dma_rx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 0,.request = DMA_REQ_SDHC1,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC1_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc1_width4_dma_tx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 0,.request = DMA_REQ_SDHC1,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC1_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc2_width1_dma_rx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 16,.request = DMA_REQ_SDHC2,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC2_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc2_width1_dma_tx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 16,.request = DMA_REQ_SDHC2,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC2_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc2_width4_dma_rx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 0,.request = DMA_REQ_SDHC2,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC2_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc2_width4_dma_tx_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .cb_end = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .AcRpt = 0,.repeat = 0,.ren = 1,
+ .burstLength = 0,.request = DMA_REQ_SDHC2,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC2_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma info array which is actived
+ * DEVICE_ID RX/(RX&TX) TX
+ */
+static dma_info_entry_t active_dma_info[] = {
+ {MXC_DMA_TEST_RAM2RAM, {&ram2ram_dma_info, NULL}},
+ {MXC_DMA_TEST_RAM2D2RAM2D, {&ram2d2ram2d_dma_info, NULL}},
+ {MXC_DMA_TEST_RAM2RAM2D, {&ram2ram2d_dma_info, NULL}},
+ {MXC_DMA_TEST_RAM2D2RAM, {&ram2d2ram_dma_info, NULL}},
+ {MXC_DMA_TEST_HW_CHAINING, {&hw_chaining_dma_info, NULL}},
+ {MXC_DMA_TEST_SW_CHAINING, {&sw_chaining_dma_info, NULL}},
+ {MXC_DMA_UART1_RX, {&uart1_rx_dma_info, NULL}},
+ {MXC_DMA_UART1_TX, {NULL, &uart1_tx_dma_info}},
+ {MXC_DMA_UART2_RX, {&uart2_rx_dma_info, NULL}},
+ {MXC_DMA_UART2_TX, {NULL, &uart2_tx_dma_info}},
+ {MXC_DMA_UART3_RX, {&uart3_rx_dma_info, NULL}},
+ {MXC_DMA_UART3_TX, {NULL, &uart3_tx_dma_info}},
+ {MXC_DMA_UART4_RX, {&uart4_rx_dma_info, NULL}},
+ {MXC_DMA_UART4_TX, {NULL, &uart4_tx_dma_info}},
+ {MXC_DMA_SSI1_16BIT_RX0, {&ssi1_16bit_rx0_dma_info, NULL}},
+ {MXC_DMA_SSI1_16BIT_TX0, {NULL, &ssi1_16bit_tx0_dma_info}},
+ {MXC_DMA_SSI2_16BIT_RX0, {&ssi2_16bit_rx0_dma_info, NULL}},
+ {MXC_DMA_SSI2_16BIT_TX0, {NULL, &ssi2_16bit_tx0_dma_info}},
+ {MXC_DMA_MMC1_WIDTH_1,
+ {&mmc1_width1_dma_rx_info, &mmc1_width1_dma_tx_info}},
+ {MXC_DMA_MMC1_WIDTH_4,
+ {&mmc1_width4_dma_rx_info, &mmc1_width4_dma_tx_info}},
+ {MXC_DMA_MMC2_WIDTH_1,
+ {&mmc2_width1_dma_rx_info, &mmc2_width1_dma_tx_info}},
+ {MXC_DMA_MMC2_WIDTH_4,
+ {&mmc2_width4_dma_rx_info, &mmc2_width4_dma_tx_info}},
+};
+
+/*!
+ * @brief the number of actived dma info
+ */
+static int dma_info_entrys =
+ sizeof(active_dma_info) / sizeof(active_dma_info[0]);
+
+/*!
+ * @brief get the dma info by channel_id
+ */
+mx2_dma_info_t **mxc_dma_get_info(mxc_dma_device_t channel_id)
+{
+ dma_info_entry_t *p = active_dma_info;
+ int i;
+ for (i = 0; i < dma_info_entrys; i++, p++) {
+ if (p->device == channel_id)
+ return p->info;
+ }
+ return NULL;
+}
+
+/*!
+ * @brief: scan dma parameter list . And collect information about which channels are dynamic .
+ */
+void mxc_dma_load_info(mxc_dma_channel_t * dma)
+{
+ int i, idx;
+ dma_info_entry_t *p = active_dma_info;
+
+ BUG_ON(dma == NULL);
+ BUG_ON(p == NULL);
+
+ for (i = 0; i < MXC_DMA_CHANNELS; i++) {
+ dma[i].dynamic = 1;
+ }
+
+ for (i = 0; i < dma_info_entrys; i++, p++) {
+ BUG_ON((p->info[0] == NULL) && (p->info[1] == NULL));
+
+ idx =
+ (p->info[0]) ? p->info[0]->dma_chan : p->info[1]->dma_chan;
+
+ BUG_ON(((idx >= MAX_DMA_CHANNELS)
+ && (idx != MXC_DMA_DYNAMIC_CHANNEL)));
+ if ((idx < 0) || (idx == MXC_DMA_DYNAMIC_CHANNEL))
+ continue;
+ dma[idx].dynamic = 0;
+ }
+}
+
+EXPORT_SYMBOL(mxc_dma_get_info);
+EXPORT_SYMBOL(mxc_dma_load_info);
diff -urN linux-2.6.26/arch/arm/mach-mx21/gpio_mux.c linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.c
--- linux-2.6.26/arch/arm/mach-mx21/gpio_mux.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ *@file gpio_mux.c
+ *@brief This file contains the IOMUX implementation details.
+ * @ingroup GPIO
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include "gpio_mux.h"
+
+/*!
+ * This structure defines the offset of registers in gpio module.
+ */
+enum gpio_reg {
+ GPIO_GIUS = 0x20,
+ GPIO_GPR = 0x38,
+ GPIO_PUEN = 0x40,
+ GPIO_DDIR = 0x00,
+ GPIO_OCR1 = 0x04,
+ GPIO_OCR2 = 0x08,
+ GPIO_ICONFA1 = 0x0C,
+ GPIO_ICONFA2 = 0x10,
+ GPIO_ICONFB1 = 0x14,
+ GPIO_ICONFB2 = 0x18,
+};
+
+/*!
+ * This enumeration data type defines the configuration for input mode.
+ */
+typedef enum {
+ GPIO_INPUT_GPIO = 0x00,
+ GPIO_INPUT_INTR = 0x01,
+ GPIO_INPUT_LOW = 0x02,
+ GPIO_INPUT_HIGH = 0x03
+} gpio_input_cfg_t;
+
+/*!
+ * This enumeration data type defines the configuration for output mode.
+ */
+typedef enum {
+ GPIO_OUTPUT_A = 0x00,
+ GPIO_OUTPUT_B = 0x01,
+ GPIO_OUTPUT_C = 0x02,
+ GPIO_OUTPUT_DR = 0x03
+} gpio_output_cfg_t;
+
+extern struct mxc_gpio_port mxc_gpio_ports[];
+
+/*!
+ * defines a spinlock to protected the accessing to gpio pin.
+ */
+DEFINE_SPINLOCK(gpio_mux_lock);
+
+/*!
+ * This function enable or disable the pullup feature to the pin.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param en 0 if disable pullup, otherwise enable it.
+ * @return none
+ */
+static inline void _gpio_set_puen(struct mxc_gpio_port *port, u32 index,
+ bool en)
+{
+ u32 reg;
+
+ reg = __raw_readl(port->base + GPIO_PUEN);
+ if (en) {
+ reg |= 1 << index;
+ } else {
+ reg &= ~(1 << index);
+ }
+ __raw_writel(reg, port->base + GPIO_PUEN);
+}
+
+/*!
+ * This function set the input configuration A.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param config a mode as define in \b #gpio_input_cfg_t
+ * @return none
+ */
+static inline void _gpio_set_iconfa(struct mxc_gpio_port *port, u32 index,
+ gpio_input_cfg_t config)
+{
+ u32 reg, val;
+ u32 mask;
+
+ mask = 0x3 << ((index % 16) << 1);
+
+ if (index >= 16) {
+ reg = port->base + GPIO_ICONFA2;
+ val = config << ((index - 16) * 2);
+ } else {
+ reg = port->base + GPIO_ICONFA1;
+ val = config << (index * 2);
+ }
+ val |= __raw_readl(reg) & ~(mask);
+ __raw_writel(val, reg);
+}
+
+/*!
+ * This function set the input configuration B.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param config a mode as define in \b #gpio_input_cfg_t
+ * @return none
+ */
+static inline void _gpio_set_iconfb(struct mxc_gpio_port *port, u32 index,
+ gpio_input_cfg_t config)
+{
+ u32 reg, val;
+ u32 mask;
+
+ mask = 0x3 << ((index % 16) << 1);
+
+ if (index >= 16) {
+ reg = port->base + GPIO_ICONFB2;
+ val = config << ((index - 16) * 2);
+ } else {
+ reg = port->base + GPIO_ICONFB1;
+ val = config << (index * 2);
+ }
+ val |= __raw_readl(reg) & (~mask);
+ __raw_writel(val, reg);
+}
+
+/*!
+ * This function set the output configuration.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param config a mode as define in \b #gpio_output_cfg_t
+ * @return none
+ */
+static inline void _gpio_set_ocr(struct mxc_gpio_port *port, u32 index,
+ gpio_output_cfg_t config)
+{
+ u32 reg, val;
+ u32 mask;
+
+ mask = 0x3 << ((index % 16) << 1);
+ if (index >= 16) {
+ reg = port->base + GPIO_OCR2;
+ val = config << ((index - 16) * 2);
+ } else {
+ reg = port->base + GPIO_OCR1;
+ val = config << (index * 2);
+ }
+ val |= __raw_readl(reg) & (~mask);
+ __raw_writel(val, reg);
+}
+
+/*!
+ *@brief gpio_config_mux - just configure the mode of the gpio pin.
+ *@param pin a pin number as defined in \b #iomux_pin_name_t
+ *@param mode a module as define in \b #gpio_mux_mode_t;
+ * GPIO_MUX_PRIMARY set pin to work as primary function.
+ * GPIO_MUX_ALT set pin to work as alternate function.
+ * GPIO_MUX_GPIO set pin to work as output function based the data register
+ * GPIO_MUX_INPUT1 set pin to work as input function connected with A_OUT
+ * GPIO_MUX_INPUT2 set pin to work as input function connected with B_OUT
+ * GPIO_MUX_OUTPUT1 set pin to work as output function connected with A_IN
+ * GPIO_MUX_OUTPUT2 set pin to work as output function connected with B_IN
+ * GPIO_MUX_OUTPUT3 set pin to work as output function connected with C_IN
+ *@return 0 if successful, Non-zero otherwise
+ */
+
+int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode)
+{
+ unsigned long lock_flags;
+ u32 gius_reg, gpr_reg;
+ struct mxc_gpio_port *port;
+ u32 index, gpio = IOMUX_TO_GPIO(pin);
+
+ port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]);
+ index = GPIO_TO_INDEX(gpio);
+
+ pr_debug("%s: Configuring PORT %c, bit %d\n",
+ __FUNCTION__, port->num + 'A', index);
+
+ spin_lock_irqsave(&gpio_mux_lock, lock_flags);
+
+ gius_reg = __raw_readl(port->base + GPIO_GIUS);
+ gpr_reg = __raw_readl(port->base + GPIO_GPR);
+
+ switch (mode) {
+ case GPIO_MUX_PRIMARY:
+ gius_reg &= ~(1L << index);
+ gpr_reg &= ~(1L << index);
+ break;
+ case GPIO_MUX_ALT:
+ gius_reg &= ~(1L << index);
+ gpr_reg |= (1L << index);
+ break;
+ case GPIO_MUX_GPIO:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_DR);
+ break;
+ case GPIO_MUX_INPUT1:
+ gius_reg |= (1L << index);
+ _gpio_set_iconfa(port, index, GPIO_INPUT_GPIO);
+ break;
+ case GPIO_MUX_INPUT2:
+ gius_reg |= (1L << index);
+ _gpio_set_iconfb(port, index, GPIO_INPUT_GPIO);
+ break;
+ case GPIO_MUX_OUTPUT1:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_A);
+ break;
+ case GPIO_MUX_OUTPUT2:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_B);
+ break;
+ case GPIO_MUX_OUTPUT3:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_C);
+ break;
+ default:
+ spin_unlock_irqrestore(&gpio_mux_lock, lock_flags);
+ return -1;
+ }
+
+ __raw_writel(gius_reg, port->base + GPIO_GIUS);
+ __raw_writel(gpr_reg, port->base + GPIO_GPR);
+
+ spin_unlock_irqrestore(&gpio_mux_lock, lock_flags);
+ return 0;
+}
+
+/*!
+ * This function is just used to enable or disable the pull up feature .
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param en 0 if disable, Non-zero enable
+ * @return 0 if successful, Non-zero otherwise
+ */
+int gpio_set_puen(iomux_pin_name_t pin, bool en)
+{
+ unsigned long lock_flags;
+
+ struct mxc_gpio_port *port;
+ u32 index, gpio = IOMUX_TO_GPIO(pin);
+
+ port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]);
+ index = GPIO_TO_INDEX(gpio);
+
+ pr_debug("%s: Configuring output mode of PORT %c, bit %d\n",
+ __FUNCTION__, port->num + 'A', index);
+
+ spin_lock_irqsave(&gpio_mux_lock, lock_flags);
+
+ _gpio_set_puen(port, index, en);
+ spin_unlock_irqrestore(&gpio_mux_lock, lock_flags);
+ return 0;
+
+}
+
+/*!
+ * This function is just used to request a pin and configure it.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param mode a module as define in \b #gpio_mux_mode_t;
+ * @return 0 if successful, Non-zero otherwise
+ */
+int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode)
+{
+ int ret;
+ ret = mxc_request_gpio(pin);
+ if (ret == 0) {
+ ret = gpio_config_mux(pin, mode);
+ if (ret) {
+ mxc_free_gpio(pin);
+ }
+ }
+ return ret;
+}
+
+/*!
+ * This function is just used to release a pin.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @return none
+ */
+void gpio_free_mux(iomux_pin_name_t pin)
+{
+ mxc_free_gpio(pin);
+}
diff -urN linux-2.6.26/arch/arm/mach-mx21/gpio_mux.h linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.h
--- linux-2.6.26/arch/arm/mach-mx21/gpio_mux.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ *@file gpio_mux.h
+ *@brief This file contains the private definition .
+ * @ingroup GPIO_MX27
+ */
+
+#ifndef __ARCH_ARM_MACH_MX21_GPIO_MUX_H__
+#define __ARCH_ARM_MACH_MX21_GPIO_MUX_H__
+
+#include "mx21_pins.h"
+
+/*!
+ * This enumeration data type defines the modes of the pin .
+ * GPIO_MUX_PRIMARY is the primary mode.
+ * GPIO_MUX_ALT is the alternate mode.
+ * GPIO_MUX_GPIO is the output mode and the signal source is data register.
+ * GPIO_MUX_INPUT1 is the input mode and the signal destination is A_OUT.
+ * GPIO_MUX_INPUT2 is the input mode and the signal destination is B_OUT.
+ * GPIO_MUX_OUTPUT1 is the output mode and the signal destination is A_IN.
+ * GPIO_MUX_OUTPUT2 is the output mode and the signal destination is B_IN.
+ * GPIO_MUX_OUTPUT3 is the output mode and the signal destination is C_IN.
+ */
+typedef enum {
+ GPIO_MUX_PRIMARY,
+ GPIO_MUX_ALT,
+ GPIO_MUX_GPIO,
+ GPIO_MUX_INPUT1,
+ GPIO_MUX_INPUT2,
+ GPIO_MUX_OUTPUT1,
+ GPIO_MUX_OUTPUT2,
+ GPIO_MUX_OUTPUT3,
+} gpio_mux_mode_t;
+
+/*!
+ * This function is just used to request a pin and configure it.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param mode a module as define in \b #gpio_mux_mode_t;
+ * @return 0 if successful, Non-zero otherwise
+ */
+extern int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
+
+/*!
+ * This function is just used to configure a pin .
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param mode a module as define in \b #gpio_mux_mode_t;
+ * @return 0 if successful, Non-zero otherwise
+ */
+extern int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
+
+/*!
+ * This function is just used to enable or disable the pull up feature .
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param en 0 if disable, Non-zero enable
+ * @return 0 if successful, Non-zero otherwise
+ */
+extern int gpio_set_puen(iomux_pin_name_t pin, bool en);
+
+/*!
+ * This function is just used to release a pin.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @return none
+ */
+extern void gpio_free_mux(iomux_pin_name_t pin);
+
+#endif /* __ARCH_ARM_MACH_MX21_GPIO_MUX_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx21/mm.c linux-2.6.26-lab126/arch/arm/mach-mx21/mm.c
--- linux-2.6.26/arch/arm/mach-mx21/mm.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/mm.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mm.c
+ *
+ * @brief This file creates static mapping between physical to virtual memory.
+ *
+ * @ingroup Memory
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+
+static struct map_desc mxc_io_desc[] __initdata = {
+ {
+ .virtual = AIPI_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(AIPI_BASE_ADDR),
+ .length = AIPI_SIZE,
+ .type = MT_DEVICE},
+ {
+ .virtual = SAHB1_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(SAHB1_BASE_ADDR),
+ .length = SAHB1_SIZE,
+ .type = MT_DEVICE},
+ {
+ .virtual = X_MEMC_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
+ .length = X_MEMC_SIZE,
+ .type = MT_DEVICE},
+ {
+ .virtual = CS1_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(CS1_BASE_ADDR),
+ .length = CS1_SIZE,
+ .type = MT_DEVICE}
+};
+
+void __init mxc_map_io(void)
+{
+ iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff -urN linux-2.6.26/arch/arm/mach-mx21/mx21_pins.h linux-2.6.26-lab126/arch/arm/mach-mx21/mx21_pins.h
--- linux-2.6.26/arch/arm/mach-mx21/mx21_pins.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/mx21_pins.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MXC_MX21_PINS_H__
+#define __ASM_ARCH_MXC_MX21_PINS_H__
+
+#ifndef __ASSEMBLY__
+
+/*!
+ * @name IOMUX/PAD Bit field definitions
+ */
+
+/*! @{ */
+
+/*!
+ * In order to identify pins more effectively, each mux-controlled pin's
+ * enumerated value is constructed in the following way:
+ *
+ * -------------------------------------------------------------------
+ * 31-29 | 28 - 24 |23 - 21| 20 | 19 - 18 | 17 - 10| 9 - 8 | 7 - 0
+ * -------------------------------------------------------------------
+ * IO_P | IO_I | RSVD | PAD_F | PAD_I | MUX_F | MUX_I
+ * -------------------------------------------------------------------
+ *
+ * Bit 0 to 7 contains MUX_I used to identify the register
+ * offset (0-based. base is IOMUX_module_base + 0xC) defined in the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Bit 8 to 9 is MUX_F which
+ * contains the offset value defined WITHIN the same register (each IOMUX
+ * control register contains four 8-bit fields for four different pins). The
+ * similar field definitions are used for the pad control register.
+ * For example, the MX21_PIN_A0 is defined in the enumeration:
+ * ( 73 << MUX_I) | (0 << MUX_F)|( 98 << PAD_I) | (0 << PAD_F)
+ * It means the mux control register is at register offset 73. So the absolute
+ * address is: 0xC+73*4=0x130 0 << MUX_F means the control bits are at the
+ * least significant bits within the register. The pad control register offset
+ * is: 0x154+98*4=0x2DC and also occupy the least significant bits within the
+ * register.
+ */
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register index (0-based)
+ */
+#define MUX_I 0
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * field within IOMUX control register for control bits
+ * (legal values are 0, 1, 2, 3)
+ */
+#define MUX_F 8
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register index (0-based)
+ */
+#define PAD_I 10
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * field within PAD control register for control bits
+ * (legal values are 0, 1, 2)
+ */
+#define PAD_F 18
+
+#define _MX21_BUILD_PIN(gp,gi) (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I))
+
+/*! @} End IOMUX/PAD Bit field definitions */
+
+/*!
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+ MX21_PIN_LSCLK = _MX21_BUILD_PIN(0, 5),
+ MX21_PIN_LD0 = _MX21_BUILD_PIN(0, 6),
+ MX21_PIN_LD1 = _MX21_BUILD_PIN(0, 7),
+ MX21_PIN_LD2 = _MX21_BUILD_PIN(0, 8),
+ MX21_PIN_LD3 = _MX21_BUILD_PIN(0, 9),
+ MX21_PIN_LD4 = _MX21_BUILD_PIN(0, 10),
+ MX21_PIN_LD5 = _MX21_BUILD_PIN(0, 11),
+ MX21_PIN_LD6 = _MX21_BUILD_PIN(0, 12),
+ MX21_PIN_LD7 = _MX21_BUILD_PIN(0, 13),
+ MX21_PIN_LD8 = _MX21_BUILD_PIN(0, 14),
+ MX21_PIN_LD9 = _MX21_BUILD_PIN(0, 15),
+ MX21_PIN_LD10 = _MX21_BUILD_PIN(0, 16),
+ MX21_PIN_LD11 = _MX21_BUILD_PIN(0, 17),
+ MX21_PIN_LD12 = _MX21_BUILD_PIN(0, 18),
+ MX21_PIN_LD13 = _MX21_BUILD_PIN(0, 19),
+ MX21_PIN_LD14 = _MX21_BUILD_PIN(0, 20),
+ MX21_PIN_LD15 = _MX21_BUILD_PIN(0, 21),
+ MX21_PIN_LD16 = _MX21_BUILD_PIN(0, 22),
+ MX21_PIN_LD17 = _MX21_BUILD_PIN(0, 23),
+ MX21_PIN_REV = _MX21_BUILD_PIN(0, 24),
+ MX21_PIN_CLS = _MX21_BUILD_PIN(0, 25),
+ MX21_PIN_PS = _MX21_BUILD_PIN(0, 26),
+ MX21_PIN_SPL_SPR = _MX21_BUILD_PIN(0, 27),
+ MX21_PIN_HSYNC = _MX21_BUILD_PIN(0, 28),
+ MX21_PIN_VSYNC = _MX21_BUILD_PIN(0, 29),
+ MX21_PIN_CONTRAST = _MX21_BUILD_PIN(0, 30),
+ MX21_PIN_OE_ACD = _MX21_BUILD_PIN(0, 31),
+
+ MX21_PIN_SD2_D0 = _MX21_BUILD_PIN(1, 4),
+ MX21_PIN_SD2_D1 = _MX21_BUILD_PIN(1, 5),
+ MX21_PIN_SD2_D2 = _MX21_BUILD_PIN(1, 6),
+ MX21_PIN_SD2_D3 = _MX21_BUILD_PIN(1, 7),
+ MX21_PIN_SD2_CMD = _MX21_BUILD_PIN(1, 8),
+ MX21_PIN_SD2_CLK = _MX21_BUILD_PIN(1, 9),
+ MX21_PIN_CSI_D0 = _MX21_BUILD_PIN(1, 10),
+ MX21_PIN_CSI_D1 = _MX21_BUILD_PIN(1, 11),
+ MX21_PIN_CSI_D2 = _MX21_BUILD_PIN(1, 12),
+ MX21_PIN_CSI_D3 = _MX21_BUILD_PIN(1, 13),
+ MX21_PIN_CSI_D4 = _MX21_BUILD_PIN(1, 14),
+ MX21_PIN_CSI_MCLK = _MX21_BUILD_PIN(1, 15),
+ MX21_PIN_CSI_PIXCLK = _MX21_BUILD_PIN(1, 16),
+ MX21_PIN_CSI_D5 = _MX21_BUILD_PIN(1, 17),
+ MX21_PIN_CSI_D6 = _MX21_BUILD_PIN(1, 18),
+ MX21_PIN_CSI_D7 = _MX21_BUILD_PIN(1, 19),
+ MX21_PIN_CSI_VSYNC = _MX21_BUILD_PIN(1, 20),
+ MX21_PIN_CSI_HSYNC = _MX21_BUILD_PIN(1, 21),
+ MX21_PIN_USB_BYP = _MX21_BUILD_PIN(1, 22),
+ MX21_PIN_USB_PWR = _MX21_BUILD_PIN(1, 23),
+ MX21_PIN_USB_OC = _MX21_BUILD_PIN(1, 24),
+ MX21_PIN_USBH_ON = _MX21_BUILD_PIN(1, 25),
+ MX21_PIN_USBH1_FS = _MX21_BUILD_PIN(1, 26),
+ MX21_PIN_USBH1_OE = _MX21_BUILD_PIN(1, 27),
+ MX21_PIN_USBH1_TXDM = _MX21_BUILD_PIN(1, 28),
+ MX21_PIN_USBH1_TXDP = _MX21_BUILD_PIN(1, 29),
+ MX21_PIN_USBH1_RXDM = _MX21_BUILD_PIN(1, 30),
+ MX21_PIN_USBH1_RXDP = _MX21_BUILD_PIN(1, 31),
+
+ MX21_PIN_USBG_SDA = _MX21_BUILD_PIN(2, 5),
+ MX21_PIN_USBG_SCL = _MX21_BUILD_PIN(2, 5),
+ MX21_PIN_USBG_ON = _MX21_BUILD_PIN(2, 7),
+ MX21_PIN_USBG_FS = _MX21_BUILD_PIN(2, 8),
+ MX21_PIN_USBG_OE = _MX21_BUILD_PIN(2, 9),
+ MX21_PIN_USBG_TXDM = _MX21_BUILD_PIN(2, 10),
+ MX21_PIN_USBG_TXDP = _MX21_BUILD_PIN(2, 11),
+ MX21_PIN_USBG_RXDM = _MX21_BUILD_PIN(2, 12),
+ MX21_PIN_USBG_RXDP = _MX21_BUILD_PIN(2, 13),
+ MX21_PIN_TOUT = _MX21_BUILD_PIN(2, 14),
+ MX21_PIN_TIN = _MX21_BUILD_PIN(2, 15),
+ MX21_PIN_SAP_FS = _MX21_BUILD_PIN(2, 16),
+ MX21_PIN_SAP_RXD = _MX21_BUILD_PIN(2, 17),
+ MX21_PIN_SAP_TXD = _MX21_BUILD_PIN(2, 18),
+ MX21_PIN_SAP_CLK = _MX21_BUILD_PIN(2, 19),
+ MX21_PIN_SSI1_FS = _MX21_BUILD_PIN(2, 20),
+ MX21_PIN_SSI1_RXD = _MX21_BUILD_PIN(2, 21),
+ MX21_PIN_SSI1_TXD = _MX21_BUILD_PIN(2, 22),
+ MX21_PIN_SSI1_CLK = _MX21_BUILD_PIN(2, 23),
+ MX21_PIN_SSI2_FS = _MX21_BUILD_PIN(2, 24),
+ MX21_PIN_SSI2_RXD = _MX21_BUILD_PIN(2, 25),
+ MX21_PIN_SSI2_TXD = _MX21_BUILD_PIN(2, 26),
+ MX21_PIN_SSI2_CLK = _MX21_BUILD_PIN(2, 27),
+ MX21_PIN_SSI3_FS = _MX21_BUILD_PIN(2, 28),
+ MX21_PIN_SSI3_RXD = _MX21_BUILD_PIN(2, 29),
+ MX21_PIN_SSI3_TXD = _MX21_BUILD_PIN(2, 30),
+ MX21_PIN_SSI3_CLK = _MX21_BUILD_PIN(2, 31),
+
+ MX21_PIN_I2C_DATA = _MX21_BUILD_PIN(3, 17),
+ MX21_PIN_I2C_CLK = _MX21_BUILD_PIN(3, 18),
+ MX21_PIN_CSPI2_SS2 = _MX21_BUILD_PIN(3, 19),
+ MX21_PIN_CSPI2_SS1 = _MX21_BUILD_PIN(3, 20),
+ MX21_PIN_CSPI2_SS0 = _MX21_BUILD_PIN(3, 21),
+ MX21_PIN_CSPI2_SCLK = _MX21_BUILD_PIN(3, 22),
+ MX21_PIN_CSPI2_MISO = _MX21_BUILD_PIN(3, 23),
+ MX21_PIN_CSPI2_MOSI = _MX21_BUILD_PIN(3, 24),
+ MX21_PIN_CSPI1_RDY = _MX21_BUILD_PIN(3, 25),
+ MX21_PIN_CSPI1_SS2 = _MX21_BUILD_PIN(3, 26),
+ MX21_PIN_CSPI1_SS1 = _MX21_BUILD_PIN(3, 27),
+ MX21_PIN_CSPI1_SS0 = _MX21_BUILD_PIN(3, 28),
+ MX21_PIN_CSPI1_SCLK = _MX21_BUILD_PIN(3, 29),
+ MX21_PIN_CSPI1_MISO = _MX21_BUILD_PIN(3, 30),
+ MX21_PIN_CSPI1_MOSI = _MX21_BUILD_PIN(3, 31),
+
+ MX21_PIN_WB2 = _MX21_BUILD_PIN(4, 0),
+ MX21_PIN_WB1 = _MX21_BUILD_PIN(4, 1),
+ MX21_PIN_WB0 = _MX21_BUILD_PIN(4, 2),
+ MX21_PIN_UART2_CTS = _MX21_BUILD_PIN(4, 3),
+ MX21_PIN_UART2_RTS = _MX21_BUILD_PIN(4, 4),
+ MX21_PIN_PWMO = _MX21_BUILD_PIN(4, 5),
+ MX21_PIN_UART2_TXD = _MX21_BUILD_PIN(4, 6),
+ MX21_PIN_UART2_RXD = _MX21_BUILD_PIN(4, 7),
+ MX21_PIN_UART3_TXD = _MX21_BUILD_PIN(4, 8),
+ MX21_PIN_UART3_RXD = _MX21_BUILD_PIN(4, 9),
+ MX21_PIN_UART3_CTS = _MX21_BUILD_PIN(4, 10),
+ MX21_PIN_UART3_RTS = _MX21_BUILD_PIN(4, 11),
+ MX21_PIN_UART1_TXD = _MX21_BUILD_PIN(4, 12),
+ MX21_PIN_UART1_RXD = _MX21_BUILD_PIN(4, 13),
+ MX21_PIN_UART1_CTS = _MX21_BUILD_PIN(4, 14),
+ MX21_PIN_UART1_RTS = _MX21_BUILD_PIN(4, 15),
+ MX21_PIN_RTCK = _MX21_BUILD_PIN(4, 16),
+ MX21_PIN_RESET_OUT = _MX21_BUILD_PIN(4, 17),
+ MX21_PIN_SD1_D0 = _MX21_BUILD_PIN(4, 18),
+ MX21_PIN_SD1_D1 = _MX21_BUILD_PIN(4, 19),
+ MX21_PIN_SD1_D2 = _MX21_BUILD_PIN(4, 20),
+ MX21_PIN_SD1_D3 = _MX21_BUILD_PIN(4, 21),
+ MX21_PIN_SD1_CMD = _MX21_BUILD_PIN(4, 22),
+ MX21_PIN_SD1_CLK = _MX21_BUILD_PIN(4, 23),
+
+ MX21_PIN_NFRB = _MX21_BUILD_PIN(5, 0),
+ MX21_PIN_NFCE = _MX21_BUILD_PIN(5, 1),
+ MX21_PIN_NFWP = _MX21_BUILD_PIN(5, 2),
+ MX21_PIN_NFCLE = _MX21_BUILD_PIN(5, 3),
+ MX21_PIN_NFALE = _MX21_BUILD_PIN(5, 4),
+ MX21_PIN_NFRE = _MX21_BUILD_PIN(5, 5),
+ MX21_PIN_NFWE = _MX21_BUILD_PIN(5, 6),
+ MX21_PIN_NFIO0 = _MX21_BUILD_PIN(5, 7),
+ MX21_PIN_NFIO1 = _MX21_BUILD_PIN(5, 8),
+ MX21_PIN_NFIO2 = _MX21_BUILD_PIN(5, 9),
+ MX21_PIN_NFIO3 = _MX21_BUILD_PIN(5, 10),
+ MX21_PIN_NFIO4 = _MX21_BUILD_PIN(5, 11),
+ MX21_PIN_NFIO5 = _MX21_BUILD_PIN(5, 12),
+ MX21_PIN_NFIO6 = _MX21_BUILD_PIN(5, 13),
+ MX21_PIN_NFIO7 = _MX21_BUILD_PIN(5, 14),
+ MX21_PIN_CLKO = _MX21_BUILD_PIN(5, 15),
+ MX21_PIN_PF16 = _MX21_BUILD_PIN(5, 16),
+ MX21_PIN_CS4 = _MX21_BUILD_PIN(5, 21),
+ MX21_PIN_CS5 = _MX21_BUILD_PIN(5, 22),
+};
+
+#endif
+#endif
diff -urN linux-2.6.26/arch/arm/mach-mx21/mx21ads.c linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads.c
--- linux-2.6.26/arch/arm/mach-mx21/mx21ads.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
+#include
+#include
+#include
+
+#include
+#endif
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "gpio_mux.h"
+
+/*!
+ * @file mx21ads.c
+ * @brief This file contains the board specific initialization routines.
+ *
+ * @ingroup System
+ */
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern void mxc_cpu_init(void) __init;
+extern void gpio_nand_active(void);
+extern struct sys_timer mxc_timer;
+
+static void mxc_nop_release(struct device *dev)
+{
+ /* Nothing */
+}
+
+#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE)
+
+/*!
+ * This array is used for mapping mx27 ADS keypad scancodes to input keyboard
+ * keycodes.
+ */
+static u16 mxckpd_keycodes[(MAXROW * MAXCOL)] = {
+ KEY_KP9, KEY_LEFTSHIFT, KEY_0, KEY_KPASTERISK, KEY_RECORD, KEY_POWER,
+ KEY_KP8, KEY_9, KEY_8, KEY_7, KEY_KP5, KEY_VOLUMEDOWN,
+ KEY_KP7, KEY_6, KEY_5, KEY_4, KEY_KP4, KEY_VOLUMEUP,
+ KEY_KP6, KEY_3, KEY_2, KEY_1, KEY_KP3, KEY_DOWN,
+ KEY_BACK, KEY_RIGHT, KEY_ENTER, KEY_LEFT, KEY_HOME, KEY_KP2,
+ KEY_END, KEY_F2, KEY_UP, KEY_F1, KEY_F4, KEY_KP1,
+};
+
+static struct keypad_data evb_6_by_6_keypad = {
+ .rowmax = 6,
+ .colmax = 6,
+ .irq = INT_KPP,
+ .learning = 0,
+ .delay = 2,
+ .matrix = mxckpd_keycodes,
+};
+
+static struct resource mxc_kpp_resources[] = {
+ [0] = {
+ .start = INT_KPP,
+ .end = INT_KPP,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+/* mxc keypad driver */
+static struct platform_device mxc_keypad_device = {
+ .name = "mxc_keypad",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_kpp_resources),
+ .resource = mxc_kpp_resources,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &evb_6_by_6_keypad,
+ },
+};
+
+static void mxc_init_keypad(void)
+{
+ printk("mx27ads.c: registering mxc keypad device...");
+ (void)platform_device_register(&mxc_keypad_device);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+/* MTD NOR flash */
+
+#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE)
+
+static struct mtd_partition mxc_nor_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 512 * 1024,
+ .offset = 0x00000000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "nor.Kernel",
+ .size = 2 * 1024 * 1024,
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0},
+ {
+ .name = "nor.userfs",
+ .size = 14 * 1024 * 1024,
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0},
+ {
+ .name = "nor.rootfs",
+ .size = 12 * 1024 * 1024,
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = MTD_WRITEABLE},
+ {
+ .name = "FIS directory",
+ .size = 12 * 1024,
+ .offset = 0x01FE0000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "Redboot config",
+ .size = MTDPART_SIZ_FULL,
+ .offset = 0x01FFF000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+};
+
+static struct flash_platform_data mxc_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 4,
+ .parts = mxc_nor_partitions,
+ .nr_parts = ARRAY_SIZE(mxc_nor_partitions),
+};
+
+static struct resource mxc_flash_resource = {
+ .start = 0xC8000000,
+ .end = 0xC8000000 + 0x02000000 - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device mxc_nor_mtd_device = {
+ .name = "mxc_nor_flash",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &mxc_flash_resource,
+};
+
+static void mxc_init_nor_mtd(void)
+{
+ (void)platform_device_register(&mxc_nor_mtd_device);
+}
+#else
+static void mxc_init_nor_mtd(void)
+{
+}
+#endif
+
+/* MTD NAND flash */
+
+#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE)
+
+static struct mtd_partition mxc_nand_partitions[4] = {
+ {
+ .name = "nand.bootloader",
+ .offset = 0,
+ .size = 1024 * 1024},
+ {
+ .name = "nand.kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 5 * 1024 * 1024},
+ {
+ .name = "nand.rootfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 22 * 1024 * 1024},
+ {
+ .name = "nand.userfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL},
+};
+
+static struct flash_platform_data mxc_nand_data = {
+ .parts = mxc_nand_partitions,
+ .nr_parts = ARRAY_SIZE(mxc_nand_partitions),
+ .width = 1,
+};
+
+static struct platform_device mxc_nand_mtd_device = {
+ .name = "mxc_nand_flash",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_nand_data,
+ },
+};
+
+static void mxc_init_nand_mtd(void)
+{
+ gpio_nand_active();
+ (void)platform_device_register(&mxc_nand_mtd_device);
+}
+#else
+static inline void mxc_init_nand_mtd(void)
+{
+}
+#endif
+
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+static const char fb_default_mode[] = "Sharp-QVGA";
+
+/* mxc lcd driver */
+static struct platform_device mxc_fb_device = {
+ .name = "mxc_sdc_fb",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &fb_default_mode,
+ .coherent_dma_mask = 0xFFFFFFFF,
+ },
+};
+
+static void mxc_init_fb(void)
+{
+ (void)platform_device_register(&mxc_fb_device);
+}
+#else
+static inline void mxc_init_fb(void)
+{
+}
+#endif
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+/*!
+ * The serial port definition structure. The fields contain:
+ * {UART, CLK, PORT, IRQ, FLAGS}
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+ {
+ .membase = (void __iomem *)(CS1_BASE_ADDR_VIRT + 0x00200000),
+ .mapbase = (unsigned long)(CS1_BASE_ADDR + 0x00200000),
+ .irq = IOMUX_TO_IRQ(MX21_PIN_TIN),
+ .uartclk = 3686400,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ },
+};
+
+/*!
+ * REVISIT: document me
+ */
+static struct platform_device serial_device = {
+ .name = "serial8250",
+ .id = 0,
+ .dev = {
+ .platform_data = &serial_platform_data[0],
+ },
+};
+
+/*!
+ * REVISIT: document me
+ */
+static int __init mxc_init_extuart(void)
+{
+ gpio_config_mux(MX21_PIN_TIN, GPIO_MUX_GPIO);
+ set_irq_type(serial_platform_data[0].irq, IRQT_RISING);
+ return platform_device_register(&serial_device);
+}
+#else
+static inline int mxc_init_extuart(void)
+{
+ return 0;
+}
+#endif
+
+void mxc_init_enet(void)
+{
+ gpio_config_mux(MX21_PIN_UART3_RTS, GPIO_MUX_GPIO);
+ set_irq_type(CS8900AIRQ, IRQT_RISING);
+}
+
+static void mxc_board_init(void)
+{
+ mxc_gpio_init();
+
+ mxc_init_keypad();
+ mxc_init_enet();
+ mxc_init_nor_mtd();
+ mxc_init_nand_mtd();
+ mxc_init_extuart();
+ mxc_init_fb();
+}
+
+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+}
+
+/* *INDENT-OFF* */
+MACHINE_START(MX21ADS, "Freescale i.MX21 ADS")
+ /* maintainer: Freescale Semiconductor, Inc. */
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+ .phys_io = CS1_BASE_ADDR,
+ .io_pg_offst = ((CS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#else
+ .phys_io = AIPI_BASE_ADDR,
+ .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#endif
+ .boot_params = PHYS_OFFSET + 0x100,
+ .fixup = fixup_mxc_board,
+ .map_io = mxc_map_io,
+ .init_irq = mxc_init_irq,
+ .init_machine = mxc_board_init,
+ .timer = &mxc_timer,
+MACHINE_END
diff -urN linux-2.6.26/arch/arm/mach-mx21/mx21ads_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads_gpio.c
--- linux-2.6.26/arch/arm/mach-mx21/mx21ads_gpio.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads_gpio.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,384 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "gpio_mux.h"
+#include "crm_regs.h"
+
+static int g_uart_actived[4] = { 0, 0, 0, 0 };
+
+/*!
+ * @file mx21ads_gpio.c
+ *
+ * @brief This file contains all the GPIO setup functions for the board.
+ *
+ * @ingroup GPIO
+ */
+
+/*!
+ * Setup GPIO for a UART port to be active
+ *
+ * @param port a UART port
+ * @param no_irda indicates if the port is used for SIR
+ */
+void gpio_uart_active(int port, int no_irda)
+{
+ if (port < 0 || port >= MXC_UART_NR) {
+ pr_info("Wrong GPIO port number: %d\n", port);
+ BUG();
+ }
+
+ if (g_uart_actived[port]) {
+ pr_info("UART %d GPIO have been actived multi-times\n",
+ port + 1);
+ return;
+ }
+ g_uart_actived[port] = 1;
+
+ switch (port) {
+ case 0:
+ gpio_request_mux(MX21_PIN_UART1_TXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_UART1_RXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_UART1_CTS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_UART1_RTS, GPIO_MUX_PRIMARY);
+ break;
+ case 1:
+ gpio_request_mux(MX21_PIN_UART2_TXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_UART2_RXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_UART2_CTS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_UART2_RTS, GPIO_MUX_PRIMARY);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a UART port to be inactive
+ *
+ * @param port a UART port
+ * @param no_irda indicates if the port is used for SIR
+ */
+void gpio_uart_inactive(int port, int no_irda)
+{
+ if (port < 0 || port >= MXC_UART_NR) {
+ pr_info("Wrong GPIO port number: %d\n", port);
+ BUG();
+ }
+
+ if (g_uart_actived[port] == 0) {
+ pr_info("UART %d GPIO have not been actived \n", port + 1);
+ return;
+ }
+ g_uart_actived[port] = 0;
+
+ switch (port) {
+ case 0:
+ gpio_free_mux(MX21_PIN_UART1_TXD);
+ gpio_free_mux(MX21_PIN_UART1_RXD);
+ gpio_free_mux(MX21_PIN_UART1_CTS);
+ gpio_free_mux(MX21_PIN_UART1_RTS);
+ break;
+ case 1:
+ gpio_free_mux(MX21_PIN_UART2_TXD);
+ gpio_free_mux(MX21_PIN_UART2_RXD);
+ gpio_free_mux(MX21_PIN_UART2_CTS);
+ gpio_free_mux(MX21_PIN_UART2_RTS);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ * Configure the IOMUX GPR register to receive shared SDMA UART events
+ *
+ * @param port a UART port
+ */
+void config_uartdma_event(int port)
+{
+ return;
+}
+
+/************************************************************************/
+/* for i2c gpio */
+/* PD17,PD18 -- Primary */
+/************************************************************************/
+#define GPIO_I2C (( 1<<17 ) |( 1<<18) )
+/*!
+* Setup GPIO for an I2C device to be active
+*
+* @param i2c_num an I2C device
+*/
+void gpio_i2c_active(int i2c_num)
+{
+ switch (i2c_num) {
+ case 0:
+ gpio_request_mux(MX21_PIN_I2C_CLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_I2C_DATA, GPIO_MUX_PRIMARY);
+ break;
+ default:
+ printk("gpio_i2c_active no compatible I2C adapter\n");
+ break;
+ }
+}
+
+/*!
+ * * Setup GPIO for an I2C device to be inactive
+ * *
+ * * @param i2c_num an I2C device
+ */
+void gpio_i2c_inactive(int i2c_num)
+{
+ switch (i2c_num) {
+ case 0:
+ gpio_free_mux(MX21_PIN_I2C_CLK);
+ gpio_free_mux(MX21_PIN_I2C_DATA);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a CSPI device to be active
+ *
+ * @param cspi_mod an CSPI device
+ */
+void gpio_spi_active(int cspi_mod)
+{
+ switch (cspi_mod) {
+ case 0:
+ /* SPI1 */
+ gpio_request_mux(MX21_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY);
+ break;
+ case 1:
+ /* SPI2 */
+ gpio_request_mux(MX21_PIN_CSPI2_SS2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI2_SS1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI2_SS0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI2_MISO, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CSPI2_MOSI, GPIO_MUX_PRIMARY);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a CSPI device to be inactive
+ *
+ * @param cspi_mod a CSPI device
+ */
+void gpio_spi_inactive(int cspi_mod)
+{
+ switch (cspi_mod) {
+ case 0:
+ /* SPI1 */
+ gpio_free_mux(MX21_PIN_CSPI1_RDY);
+ gpio_free_mux(MX21_PIN_CSPI1_SS2);
+ gpio_free_mux(MX21_PIN_CSPI1_SS1);
+ gpio_free_mux(MX21_PIN_CSPI1_SS0);
+ gpio_free_mux(MX21_PIN_CSPI1_MISO);
+ gpio_free_mux(MX21_PIN_CSPI1_MOSI);
+ break;
+ case 1:
+ /* SPI2 */
+ gpio_free_mux(MX21_PIN_CSPI2_SS2);
+ gpio_free_mux(MX21_PIN_CSPI2_SS1);
+ gpio_free_mux(MX21_PIN_CSPI2_SS0);
+ gpio_free_mux(MX21_PIN_CSPI2_MISO);
+ gpio_free_mux(MX21_PIN_CSPI2_MOSI);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a nand flash device to be active
+ *
+ */
+void gpio_nand_active(void)
+{
+ gpio_request_mux(MX21_PIN_NFALE, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFCE, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFCLE, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFRB, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFRE, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFWE, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFWP, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFIO1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFIO2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFIO3, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFIO4, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFIO5, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFIO6, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_NFIO7, GPIO_MUX_PRIMARY);
+}
+
+/*!
+ * Setup GPIO for a nand flash device to be inactive
+ *
+ */
+void gpio_nand_inactive(void)
+{
+ gpio_free_mux(MX21_PIN_NFALE);
+ gpio_free_mux(MX21_PIN_NFCE);
+ gpio_free_mux(MX21_PIN_NFCLE);
+ gpio_free_mux(MX21_PIN_NFRB);
+ gpio_free_mux(MX21_PIN_NFRE);
+ gpio_free_mux(MX21_PIN_NFWE);
+ gpio_free_mux(MX21_PIN_NFWP);
+ gpio_free_mux(MX21_PIN_NFIO1);
+ gpio_free_mux(MX21_PIN_NFIO2);
+ gpio_free_mux(MX21_PIN_NFIO3);
+ gpio_free_mux(MX21_PIN_NFIO4);
+ gpio_free_mux(MX21_PIN_NFIO5);
+ gpio_free_mux(MX21_PIN_NFIO6);
+ gpio_free_mux(MX21_PIN_NFIO7);
+}
+
+/*!
+ * Setup GPIO for LCDC device to be active
+ *
+ */
+void gpio_lcdc_active(void)
+{
+ gpio_request_mux(MX21_PIN_LSCLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD3, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD4, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD5, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD6, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD7, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD8, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD9, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD10, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD11, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD12, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD13, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD14, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD15, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD16, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_LD17, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_REV, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CLS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_PS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_SPL_SPR, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_HSYNC, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_VSYNC, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_CONTRAST, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX21_PIN_OE_ACD, GPIO_MUX_PRIMARY);
+}
+
+/*!
+ * Setup GPIO for LCDC device to be inactive
+ *
+ */
+void gpio_lcdc_inactive(void)
+{
+ gpio_free_mux(MX21_PIN_LSCLK);
+ gpio_free_mux(MX21_PIN_LD0);
+ gpio_free_mux(MX21_PIN_LD1);
+ gpio_free_mux(MX21_PIN_LD2);
+ gpio_free_mux(MX21_PIN_LD3);
+ gpio_free_mux(MX21_PIN_LD4);
+ gpio_free_mux(MX21_PIN_LD5);
+ gpio_free_mux(MX21_PIN_LD6);
+ gpio_free_mux(MX21_PIN_LD7);
+ gpio_free_mux(MX21_PIN_LD8);
+ gpio_free_mux(MX21_PIN_LD9);
+ gpio_free_mux(MX21_PIN_LD10);
+ gpio_free_mux(MX21_PIN_LD11);
+ gpio_free_mux(MX21_PIN_LD12);
+ gpio_free_mux(MX21_PIN_LD13);
+ gpio_free_mux(MX21_PIN_LD14);
+ gpio_free_mux(MX21_PIN_LD15);
+ gpio_free_mux(MX21_PIN_LD16);
+ gpio_free_mux(MX21_PIN_LD17);
+ gpio_free_mux(MX21_PIN_REV);
+ gpio_free_mux(MX21_PIN_CLS);
+ gpio_free_mux(MX21_PIN_PS);
+ gpio_free_mux(MX21_PIN_SPL_SPR);
+ gpio_free_mux(MX21_PIN_HSYNC);
+ gpio_free_mux(MX21_PIN_VSYNC);
+ gpio_free_mux(MX21_PIN_CONTRAST);
+ gpio_free_mux(MX21_PIN_OE_ACD);
+}
+
+/*!
+ * GPIO settings not required for keypad
+ *
+ */
+void gpio_keypad_active(void)
+{
+}
+
+/*!
+ * GPIO settings not required for keypad
+ *
+ */
+void gpio_keypad_inactive(void)
+{
+}
+
+void board_power_lcd(int on)
+{
+ volatile unsigned short reg;
+
+ reg = __raw_readw(CS1_BASE_ADDR_VIRT + 0x800000);
+ if (on == 0)
+ /* turn it off */
+ reg &= ~0x0200;
+ else
+ /* turn it on */
+ reg |= 0x0200;
+
+ __raw_writew(reg, CS1_BASE_ADDR_VIRT + 0x800000);
+}
+
+EXPORT_SYMBOL(gpio_uart_active);
+EXPORT_SYMBOL(gpio_uart_inactive);
+EXPORT_SYMBOL(config_uartdma_event);
+EXPORT_SYMBOL(gpio_i2c_active);
+EXPORT_SYMBOL(gpio_i2c_inactive);
+EXPORT_SYMBOL(gpio_spi_active);
+EXPORT_SYMBOL(gpio_spi_inactive);
+EXPORT_SYMBOL(gpio_nand_active);
+EXPORT_SYMBOL(gpio_nand_inactive);
+EXPORT_SYMBOL(gpio_lcdc_active);
+EXPORT_SYMBOL(gpio_lcdc_inactive);
+EXPORT_SYMBOL(gpio_keypad_active);
+EXPORT_SYMBOL(gpio_keypad_inactive);
+EXPORT_SYMBOL(board_power_lcd);
diff -urN linux-2.6.26/arch/arm/mach-mx21/serial.c linux-2.6.26-lab126/arch/arm/mach-mx21/serial.c
--- linux-2.6.26/arch/arm/mach-mx21/serial.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/serial.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,200 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+ * @file serial.c
+ *
+ * @brief This file contains the UART initiliazation.
+ *
+ * @ingroup System
+ */
+#include
+#include
+#include
+#include
+#include
+#include "serial.h"
+
+#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
+
+/*!
+ * This is an array where each element holds information about a UART port,
+ * like base address of the UART, interrupt numbers etc. This structure is
+ * passed to the serial_core.c file. Based on which UART is used, the core file
+ * passes back the appropriate port structure as an argument to the control
+ * functions.
+ */
+static uart_mxc_port mxc_ports[] = {
+ [0] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR),
+ .mapbase = UART1_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART1_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .ints_muxed = UART1_MUX_INTS,
+ .irqs = {UART1_INT2, UART1_INT3},
+ .mode = UART1_MODE,
+ .ir_mode = UART1_IR,
+ .enabled = UART1_ENABLED,
+ .hardware_flow = UART1_HW_FLOW,
+ .cts_threshold = UART1_UCR4_CTSTL,
+ .dma_enabled = UART1_DMA_ENABLE,
+ .dma_rxbuf_size = UART1_DMA_RXBUFSIZE,
+ .rx_threshold = UART1_UFCR_RXTL,
+ .tx_threshold = UART1_UFCR_TXTL,
+ .shared = UART1_SHARED_PERI,
+ .clock_id = UART1_BAUD,
+ .dma_tx_id = MXC_DMA_UART1_TX,
+ .dma_rx_id = MXC_DMA_UART1_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ },
+ [1] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR),
+ .mapbase = UART2_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART2_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .ints_muxed = UART2_MUX_INTS,
+ .irqs = {UART2_INT2, UART2_INT3},
+ .mode = UART2_MODE,
+ .ir_mode = UART2_IR,
+ .enabled = UART2_ENABLED,
+ .hardware_flow = UART2_HW_FLOW,
+ .cts_threshold = UART2_UCR4_CTSTL,
+ .dma_enabled = UART2_DMA_ENABLE,
+ .dma_rxbuf_size = UART2_DMA_RXBUFSIZE,
+ .rx_threshold = UART2_UFCR_RXTL,
+ .tx_threshold = UART2_UFCR_TXTL,
+ .shared = UART2_SHARED_PERI,
+ .clock_id = UART2_BAUD,
+ .dma_tx_id = MXC_DMA_UART2_TX,
+ .dma_rx_id = MXC_DMA_UART2_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ },
+ [2] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR),
+ .mapbase = UART3_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART3_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 2,
+ },
+ .ints_muxed = UART3_MUX_INTS,
+ .irqs = {UART3_INT2, UART3_INT3},
+ .mode = UART3_MODE,
+ .ir_mode = UART3_IR,
+ .enabled = UART3_ENABLED,
+ .hardware_flow = UART3_HW_FLOW,
+ .cts_threshold = UART3_UCR4_CTSTL,
+ .dma_enabled = UART3_DMA_ENABLE,
+ .dma_rxbuf_size = UART3_DMA_RXBUFSIZE,
+ .rx_threshold = UART3_UFCR_RXTL,
+ .tx_threshold = UART3_UFCR_TXTL,
+ .shared = UART3_SHARED_PERI,
+ .clock_id = UART3_BAUD,
+ .dma_tx_id = MXC_DMA_UART3_TX,
+ .dma_rx_id = MXC_DMA_UART3_RX,
+ .rxd_mux = MXC_UART_IR_RXDMUX,
+ },
+ [3] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART4_BASE_ADDR),
+ .mapbase = UART4_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART4_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 3,
+ },
+ .ints_muxed = UART4_MUX_INTS,
+ .irqs = {UART4_INT2, UART4_INT3},
+ .mode = UART4_MODE,
+ .ir_mode = UART4_IR,
+ .enabled = UART4_ENABLED,
+ .hardware_flow = UART4_HW_FLOW,
+ .cts_threshold = UART4_UCR4_CTSTL,
+ .dma_enabled = UART4_DMA_ENABLE,
+ .dma_rxbuf_size = UART4_DMA_RXBUFSIZE,
+ .rx_threshold = UART4_UFCR_RXTL,
+ .tx_threshold = UART4_UFCR_TXTL,
+ .shared = UART4_SHARED_PERI,
+ .clock_id = UART4_BAUD,
+ .dma_tx_id = MXC_DMA_UART4_TX,
+ .dma_rx_id = MXC_DMA_UART4_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ },
+};
+
+static struct platform_device mxc_uart_device1 = {
+ .name = "mxcintuart",
+ .id = 0,
+ .dev = {
+ .platform_data = &mxc_ports[0],
+ },
+};
+
+static struct platform_device mxc_uart_device2 = {
+ .name = "mxcintuart",
+ .id = 1,
+ .dev = {
+ .platform_data = &mxc_ports[1],
+ },
+};
+
+static struct platform_device mxc_uart_device3 = {
+ .name = "mxcintuart",
+ .id = 2,
+ .dev = {
+ .platform_data = &mxc_ports[2],
+ },
+};
+
+static struct platform_device mxc_uart_device4 = {
+ .name = "mxcintuart",
+ .id = 3,
+ .dev = {
+ .platform_data = &mxc_ports[3],
+ },
+};
+
+static int __init mxc_init_uart(void)
+{
+ /* Register all the MXC UART platform device structures */
+ platform_device_register(&mxc_uart_device1);
+ platform_device_register(&mxc_uart_device2);
+ platform_device_register(&mxc_uart_device3);
+
+#if UART4_ENABLED == 1
+ platform_device_register(&mxc_uart_device4);
+#endif /* UART4_ENABLED */
+
+ return 0;
+}
+
+#else
+static int __init mxc_init_uart(void)
+{
+ return 0;
+}
+#endif
+
+arch_initcall(mxc_init_uart);
diff -urN linux-2.6.26/arch/arm/mach-mx21/serial.h linux-2.6.26-lab126/arch/arm/mach-mx21/serial.h
--- linux-2.6.26/arch/arm/mach-mx21/serial.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/serial.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ARCH_ARM_MACH_MX21_SERIAL_H__
+#define __ARCH_ARM_MACH_MX21_SERIAL_H__
+
+#include
+
+/* UART 1 configuration */
+/*!
+ * This option allows to choose either an interrupt-driven software controlled
+ * hardware flow control (set this option to 0) or hardware-driven hardware
+ * flow control (set this option to 1).
+ */
+#define UART1_HW_FLOW 1
+/*!
+ * This specifies the threshold at which the CTS pin is deasserted by the
+ * RXFIFO. Set this value in Decimal to anything from 0 to 32 for
+ * hardware-driven hardware flow control. Read the HW spec while specifying
+ * this value. When using interrupt-driven software controlled hardware
+ * flow control set this option to -1.
+ */
+#define UART1_UCR4_CTSTL 16
+/*!
+ * This is option to enable (set this option to 1) or disable DMA data transfer
+ */
+#define UART1_DMA_ENABLE 0
+/*!
+ * Specify the size of the DMA receive buffer. The minimum buffer size is 512
+ * bytes. The buffer size should be a multiple of 256.
+ */
+#define UART1_DMA_RXBUFSIZE 1024
+/*!
+ * Specify the MXC UART's Receive Trigger Level. This controls the threshold at
+ * which a maskable interrupt is generated by the RxFIFO. Set this value in
+ * Decimal to anything from 0 to 32. Read the HW spec while specifying this
+ * value.
+ */
+#define UART1_UFCR_RXTL 16
+/*!
+ * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at
+ * which a maskable interrupt is generated by the TxFIFO. Set this value in
+ * Decimal to anything from 0 to 32. Read the HW spec while specifying this
+ * value.
+ */
+#define UART1_UFCR_TXTL 16
+/* UART 2 configuration */
+#define UART2_HW_FLOW 0
+#define UART2_UCR4_CTSTL -1
+#define UART2_DMA_ENABLE 0
+#define UART2_DMA_RXBUFSIZE 512
+#define UART2_UFCR_RXTL 16
+#define UART2_UFCR_TXTL 16
+/* UART 3 configuration */
+#define UART3_HW_FLOW 1
+#define UART3_UCR4_CTSTL 16
+#define UART3_DMA_ENABLE 0
+#define UART3_DMA_RXBUFSIZE 1024
+#define UART3_UFCR_RXTL 16
+#define UART3_UFCR_TXTL 16
+/* UART 4 configuration */
+#define UART4_HW_FLOW 1
+#define UART4_UCR4_CTSTL 16
+#define UART4_DMA_ENABLE 0
+#define UART4_DMA_RXBUFSIZE 512
+#define UART4_UFCR_RXTL 16
+#define UART4_UFCR_TXTL 16
+/*
+ * UART Chip level Configuration that a user may not have to edit. These
+ * configuration vary depending on how the UART module is integrated with
+ * the ARM core
+ */
+/*
+ * Is the MUXED interrupt output sent to the ARM core
+ */
+#define INTS_NOTMUXED 0
+#define INTS_MUXED 1
+/* UART 1 configuration */
+/*!
+ * This define specifies whether the muxed ANDed interrupt line or the
+ * individual interrupts from the UART port is integrated with the ARM core.
+ * There exists a define like this for each UART port. Valid values that can
+ * be used are \b INTS_NOTMUXED or \b INTS_MUXED.
+ */
+#define UART1_MUX_INTS INTS_MUXED
+/*!
+ * This define specifies the transmitter interrupt number or the interrupt
+ * number of the ANDed interrupt in case the interrupts are muxed. There exists
+ * a define like this for each UART port.
+ */
+#define UART1_INT1 INT_UART1
+/*!
+ * This define specifies the receiver interrupt number. If the interrupts of
+ * the UART are muxed, then we specify here a dummy value -1. There exists a
+ * define like this for each UART port.
+ */
+#define UART1_INT2 -1
+/*!
+ * This specifies the master interrupt number. If the interrupts of the UART
+ * are muxed, then we specify here a dummy value of -1. There exists a define
+ * like this for each UART port.
+ */
+#define UART1_INT3 -1
+/*!
+ * This specifies if the UART is a shared peripheral. It holds the shared
+ * peripheral number if it is shared or -1 if it is not shared. There exists
+ * a define like this for each UART port.
+ */
+#define UART1_SHARED_PERI -1
+/* UART 2 configuration */
+#define UART2_MUX_INTS INTS_MUXED
+#define UART2_INT1 INT_UART2
+#define UART2_INT2 -1
+#define UART2_INT3 -1
+#define UART2_SHARED_PERI -1
+/* UART 3 configuration */
+#define UART3_MUX_INTS INTS_MUXED
+#define UART3_INT1 INT_UART3
+#define UART3_INT2 -1
+#define UART3_INT3 -1
+#define UART3_SHARED_PERI -1
+/* UART 4 configuration */
+#define UART4_MUX_INTS INTS_MUXED
+#define UART4_INT1 INT_UART4
+#define UART4_INT2 -1
+#define UART4_INT3 -1
+#define UART4_SHARED_PERI -1
+
+#endif /* __ARCH_ARM_MACH_MX21_SERIAL_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx21/system.c linux-2.6.26-lab126/arch/arm/mach-mx21/system.c
--- linux-2.6.26/arch/arm/mach-mx21/system.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/system.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/*!
+ * @defgroup MSL Machine Specific Layer (MSL)
+ */
+
+/*!
+ * @defgroup System System-wide Misc Files for MSL
+ * @ingroup MSL
+ */
+
+/*!
+ * @file system.c
+ * @brief This file contains idle and reset functions.
+ *
+ * @ingroup System
+ */
+
+/*!
+ * This function puts the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks.
+ */
+ cpu_do_idle();
+}
+
+/*
+ * This function resets the system. It is called by machine_restart().
+ *
+ * @param mode indicates different kinds of resets
+ */
+void arch_reset(char mode)
+{
+ /* Assert Watchdog Reset signal */
+ mxc_wd_reset();
+}
diff -urN linux-2.6.26/arch/arm/mach-mx21/time.c linux-2.6.26-lab126/arch/arm/mach-mx21/time.c
--- linux-2.6.26/arch/arm/mach-mx21/time.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx21/time.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* System Timer Interrupt reconfigured to run in free-run mode.
+ * Author: Vitaly Wool
+ * Copyright 2004 MontaVista Software Inc.
+ */
+
+/*!
+ * @file time.c
+ * @brief This file contains OS tick implementations.
+ *
+ * This file contains OS tick implementations.
+ *
+ * @ingroup Timers
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#ifndef __noinstrument
+#define __noinstrument
+#endif
+
+/* OS tick defines */
+#define MXC_GPT_INT_TICK INT_GPT
+#define MXC_GPT_CLOCK_TICK GPT1_CLK
+#define MXC_GPT_TCMP_TICK MXC_GPT_TCMP(MXC_TIMER_GPT1)
+#define MXC_GPT_TSTAT_TICK MXC_GPT_TSTAT(MXC_TIMER_GPT1)
+#define MXC_GPT_TCTL_TICK MXC_GPT_TCTL(MXC_TIMER_GPT1)
+#define MXC_GPT_TPRER_TICK MXC_GPT_TPRER(MXC_TIMER_GPT1)
+#define MXC_GPT_TCN_TICK MXC_GPT_TCN(MXC_TIMER_GPT1)
+/* High resolution timer defines */
+#define MXC_GPT_INT_HRT INT_GPT2
+#define MXC_GPT_CLOCK_HRT GPT2_CLK
+#define MXC_GPT_TCMP_HRT MXC_GPT_TCMP(MXC_TIMER_GPT2)
+#define MXC_GPT_TSTAT_HRT MXC_GPT_TSTAT(MXC_TIMER_GPT2)
+#define MXC_GPT_TCTL_HRT MXC_GPT_TCTL(MXC_TIMER_GPT2)
+#define MXC_GPT_TPRER_HRT MXC_GPT_TPRER(MXC_TIMER_GPT2)
+#define MXC_GPT_TCN_HRT MXC_GPT_TCN(MXC_TIMER_GPT2)
+
+/*!
+ * This is the timer interrupt service routine to do required tasks.
+ *
+ * @param irq GPT interrupt source number (not used)
+ * @param dev_id this parameter is not used
+ * @param regs pointer to a structure containing the processor
+ * registers and state prior to servicing the interrupt
+ * @return always returns \b IRQ_HANDLED as defined in
+ * include/linux/interrupt.h.
+ */
+static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ unsigned int next_match;
+
+ write_seqlock(&xtime_lock);
+
+ do {
+ timer_tick(regs);
+ next_match = __raw_readl(MXC_GPT_TCMP_TICK) + LATCH;
+ __raw_writel(GPT_TSTAT_COMP, MXC_GPT_TSTAT_TICK);
+ __raw_writel(next_match, MXC_GPT_TCMP_TICK);
+ } while ((signed long)(next_match - __raw_readl(MXC_GPT_TCN_TICK)) <=
+ 0);
+
+ write_sequnlock(&xtime_lock);
+
+ return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to obtain the number of microseconds since the last
+ * timer interrupt. Note that interrupts is disabled by do_gettimeofday().
+ *
+ * @return the number of microseconds since the last timer interrupt.
+ */
+static unsigned long __noinstrument mxc_gettimeoffset(void)
+{
+ long ticks_to_match, elapsed, usec;
+
+ /* Get ticks before next timer match */
+ ticks_to_match =
+ __raw_readl(MXC_GPT_TCMP_TICK) - __raw_readl(MXC_GPT_TCN_TICK);
+
+ /* We need elapsed ticks since last match */
+ elapsed = LATCH - ticks_to_match;
+
+ /* Now convert them to usec */
+ usec = (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+
+ return usec;
+}
+
+/*!
+ * The OS tick timer interrupt structure.
+ */
+static struct irqaction timer_irq = {
+ .name = "MXC Timer Tick",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = mxc_timer_interrupt
+};
+
+/*!
+ * This function is used to initialize the GPT to produce an interrupt
+ * every 10 msec. It is called by the start_kernel() during system startup.
+ */
+void __init mxc_init_time(void)
+{
+ u32 reg, v;
+
+ mxc_clks_enable(MXC_GPT_CLOCK_TICK);
+ __raw_writel(0, MXC_GPT_TCTL_TICK);
+ __raw_writel(GPT_TCTL_SWR, MXC_GPT_TCTL_TICK);
+
+ while ((__raw_readl(MXC_GPT_TCTL_TICK) & GPT_TCTL_SWR) != 0)
+ mb();
+
+ reg = GPT_TCTL_FRR | GPT_TCTL_COMPEN | GPT_TCTL_SRC_PER1;
+
+ __raw_writel(reg, MXC_GPT_TCTL_TICK);
+
+ v = mxc_get_clocks(MXC_GPT_CLOCK_TICK);
+ __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_TPRER_TICK);
+
+ if ((v % CLOCK_TICK_RATE) != 0) {
+ pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
+ CLOCK_TICK_RATE);
+ }
+ pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
+ v / ((__raw_readl(MXC_GPT_TPRER_TICK) & 0x7FF) + 1));
+
+ reg = __raw_readl(MXC_GPT_TCN_TICK);
+ reg += LATCH;
+ __raw_writel(reg, MXC_GPT_TCMP_TICK);
+
+ setup_irq(MXC_GPT_INT_TICK, &timer_irq);
+
+ reg = __raw_readl(MXC_GPT_TCTL_TICK) | GPT_TCTL_TEN;
+ __raw_writel(reg, MXC_GPT_TCTL_TICK);
+
+#ifdef CONFIG_KFI
+ os_timer_initialized = 1;
+#endif
+}
+
+struct sys_timer mxc_timer = {
+ .init = mxc_init_time,
+ .offset = mxc_gettimeoffset,
+};
diff -urN linux-2.6.26/arch/arm/mach-mx27/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx27/Kconfig
--- linux-2.6.26/arch/arm/mach-mx27/Kconfig 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/Kconfig 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,43 @@
+menu "MX27 Options"
+ depends on ARCH_MX27
+
+config MX27_OPTIONS
+ bool
+ default y
+ select CPU_ARM926T
+ select MXC_EMMA
+ select USB_ARCH_HAS_EHCI
+
+config MACH_MX27ADS
+ bool "Support MX27ADS platforms"
+ default y
+ help
+ Include support for MX27ADS platform. This includes specific
+ configurations for the board and its peripherals.
+
+config ARCH_MXC_HAS_NFC_V1
+ bool "MXC NFC Hardware Version 1"
+ default y
+ help
+ This selects the Freescale MXC Nand Flash Controller Hardware Version 1
+ If unsure, say N.
+
+menu "Device options"
+
+config I2C_MXC_SELECT1
+ bool "Enable I2C1 module"
+ default y
+ depends on I2C_MXC
+ help
+ Enable MX31 I2C1 module.
+
+config I2C_MXC_SELECT2
+ bool "Enable I2C2 module"
+ default n
+ depends on I2C_MXC
+ help
+ Enable MX31 I2C2 module.
+
+endmenu
+
+endmenu
diff -urN linux-2.6.26/arch/arm/mach-mx27/Makefile linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile
--- linux-2.6.26/arch/arm/mach-mx27/Makefile 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,18 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y := mm.o time.o dma.o gpio_mux.o clock.o devices.o serial.o system.o cpu.o dptc.o
+obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o mx27ads_gpio.o
+
+# power management
+obj-$(CONFIG_PM) += pm.o mxc_pm.o
+
+obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o
+obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o
+
+ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),)
+ obj-y += usb_dr.o
+endif
diff -urN linux-2.6.26/arch/arm/mach-mx27/Makefile.boot linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile.boot
--- linux-2.6.26/arch/arm/mach-mx27/Makefile.boot 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile.boot 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,3 @@
+ zreladdr-y := 0xA0008000
+params_phys-y := 0xA0000100
+initrd_phys-y := 0xA0800000
diff -urN linux-2.6.26/arch/arm/mach-mx27/board-mx27ads.h linux-2.6.26-lab126/arch/arm/mach-mx27/board-mx27ads.h
--- linux-2.6.26/arch/arm/mach-mx27/board-mx27ads.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/board-mx27ads.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,385 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+
+/*!
+ * @defgroup BRDCFG_MX27 Board Configuration Options
+ * @ingroup MSL_MX27
+ */
+
+/*!
+ * @file mach-mx27/board-mx27ads.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX27 ADS Platform.
+ *
+ * @ingroup BRDCFG_MX27
+ */
+
+/*
+ * Include Files
+ */
+#include
+
+/*!
+ * @name MXC UART EVB board level configurations
+ */
+/*! @{ */
+/*!
+ * Specifies if the Irda transmit path is inverting
+ */
+#define MXC_IRDA_TX_INV 0
+/*!
+ * Specifies if the Irda receive path is inverting
+ */
+#define MXC_IRDA_RX_INV 0
+/* UART 1 configuration */
+/*!
+ * This define specifies if the UART port is configured to be in DTE or
+ * DCE mode. There exists a define like this for each UART port. Valid
+ * values that can be used are \b MODE_DTE or \b MODE_DCE.
+ */
+#define UART1_MODE MODE_DCE
+/*!
+ * This define specifies if the UART is to be used for IRDA. There exists a
+ * define like this for each UART port. Valid values that can be used are
+ * \b IRDA or \b NO_IRDA.
+ */
+#define UART1_IR NO_IRDA
+/*!
+ * This define is used to enable or disable a particular UART port. If
+ * disabled, the UART will not be registered in the file system and the user
+ * will not be able to access it. There exists a define like this for each UART
+ * port. Specify a value of 1 to enable the UART and 0 to disable it.
+ */
+#define UART1_ENABLED 1
+/*! @} */
+/* UART 2 configuration */
+#define UART2_MODE MODE_DCE
+#define UART2_IR NO_IRDA
+#define UART2_ENABLED 1
+/* UART 3 configuration */
+#define UART3_MODE MODE_DCE
+#define UART3_IR IRDA
+#define UART3_ENABLED 1
+/* UART 4 configuration */
+#define UART4_MODE MODE_DTE
+#define UART4_IR NO_IRDA
+#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */
+/* UART 5 configuration */
+#define UART5_MODE MODE_DTE
+#define UART5_IR NO_IRDA
+#define UART5_ENABLED 1
+/* UART 6 configuration */
+#define UART6_MODE MODE_DTE
+#define UART6_IR NO_IRDA
+#define UART6_ENABLED 1
+
+#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
+#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
+#define MXC_LL_EXTUART_16BIT_BUS
+
+#define MXC_LL_UART_PADDR UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+
+/*!
+ * @name PBC Controller parameters
+ */
+/*! @{ */
+/*!
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
+#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
+
+/*!
+ * PBC Interupt name definitions
+ */
+#define PBC_GPIO1_0 0
+#define PBC_GPIO1_1 1
+#define PBC_GPIO1_2 2
+#define PBC_GPIO1_3 3
+#define PBC_GPIO1_4 4
+#define PBC_GPIO1_5 5
+
+#define PBC_INTR_MAX_NUM 6
+#define PBC_INTR_SHARED_MAX_NUM 8
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH 0
+
+/* Offsets for the PBC Controller register */
+/*!
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
+/*!
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
+/*!PBC_ADDR_SH
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
+/*!
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
+/*!
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
+/*!
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
+/*!
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
+/*!
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
+/*!
+ * UART 4 Expanding Signal Status.
+ */
+#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
+/*!
+ * UART 4 Expanding Signal Control Set.
+ */
+#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
+/*!
+ * UART 4 Expanding Signal Control Clear.
+ */
+#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
+/*!
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
+/*!
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
+/*!
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
+
+/* PBC Board Version Register bit definition */
+#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
+#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
+#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
+#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
+#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
+#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
+
+/* PBC Board Control Register 2 bit definitions */
+#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
+#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
+#define PBC_BCTRL2_ATAFEC_EN 0X0010
+#define PBC_BCTRL2_ATAFEC_SEL 0X0020
+#define PBC_BCTRL2_ATA_EN 0X0040
+#define PBC_BCTRL2_IRDA_SD 0X0080
+#define PBC_BCTRL2_IRDA_EN 0X0100
+#define PBC_BCTRL2_CCTL10 0X0200
+#define PBC_BCTRL2_CCTL11 0X0400
+
+/* PBC Board Control Register 3 bit definitions */
+#define PBC_BCTRL3_HSH_EN 0X0020
+#define PBC_BCTRL3_FSH_MOD 0X0040
+#define PBC_BCTRL3_OTG_HS_EN 0X0080
+#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
+#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
+#define PBC_BCTRL3_USB_OTG_ON 0X0800
+#define PBC_BCTRL3_USB_FSH_ON 0X1000
+
+/* PBC Board Control Register 4 bit definitions */
+#define PBC_BCTRL4_REGEN_SEL 0X0001
+#define PBC_BCTRL4_USER_OFF 0X0002
+#define PBC_BCTRL4_VIB_EN 0X0004
+#define PBC_BCTRL4_PWRGT1_EN 0X0008
+#define PBC_BCTRL4_PWRGT2_EN 0X0010
+#define PBC_BCTRL4_STDBY_PRI 0X0020
+
+#ifndef __ASSEMBLY__
+/*!
+ * Enumerations for SD cards and memory stick card. This corresponds to
+ * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
+ */
+enum mxc_card_no {
+ MXC_CARD_SD2 = 0,
+ MXC_CARD_SD3,
+ MXC_CARD_MS,
+ MXC_CARD_SD1,
+ MXC_CARD_MIN = MXC_CARD_SD2,
+ MXC_CARD_MAX = MXC_CARD_SD1,
+};
+#endif
+
+#define MXC_CPLD_VER_1_50 0x01
+
+/*!
+ * PBC BSTAT Register bit definitions
+ */
+#define PBC_BSTAT_PRI_INT 0X0001
+#define PBC_BSTAT_USB_BYP 0X0002
+#define PBC_BSTAT_ATA_IOCS16 0X0004
+#define PBC_BSTAT_ATA_CBLID 0X0008
+#define PBC_BSTAT_ATA_DASP 0X0010
+#define PBC_BSTAT_PWR_RDY 0X0020
+#define PBC_BSTAT_SD3_WP 0X0100
+#define PBC_BSTAT_SD2_WP 0X0200
+#define PBC_BSTAT_SD1_WP 0X0400
+#define PBC_BSTAT_SD3_DET 0X0800
+#define PBC_BSTAT_SD2_DET 0X1000
+#define PBC_BSTAT_SD1_DET 0X2000
+#define PBC_BSTAT_MS_DET 0X4000
+#define PBC_BSTAT_SD3_DET_BIT 11
+#define PBC_BSTAT_SD2_DET_BIT 12
+#define PBC_BSTAT_SD1_DET_BIT 13
+#define PBC_BSTAT_MS_DET_BIT 14
+#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
+ ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
+ ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
+ ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : 0x0))))
+
+/*!
+ * PBC UART Control Register bit definitions
+ */
+#define PBC_UCTRL_DCE_DCD 0X0001
+#define PBC_UCTRL_DCE_DSR 0X0002
+#define PBC_UCTRL_DCE_RI 0X0004
+#define PBC_UCTRL_DTE_DTR 0X0100
+
+/*!
+ * PBC UART Status Register bit definitions
+ */
+#define PBC_USTAT_DTE_DCD 0X0001
+#define PBC_USTAT_DTE_DSR 0X0002
+#define PBC_USTAT_DTE_RI 0X0004
+#define PBC_USTAT_DCE_DTR 0X0100
+
+/*!
+ * PBC Interupt mask register bit definitions
+ */
+#define PBC_INTR_SD3_R_EN_BIT 4
+#define PBC_INTR_SD2_R_EN_BIT 0
+#define PBC_INTR_SD1_R_EN_BIT 6
+#define PBC_INTR_MS_R_EN_BIT 5
+#define PBC_INTR_SD3_EN_BIT 13
+#define PBC_INTR_SD2_EN_BIT 12
+#define PBC_INTR_MS_EN_BIT 14
+#define PBC_INTR_SD1_EN_BIT 15
+
+#define PBC_INTR_SD2_R_EN 0x0001
+#define PBC_INTR_LOW_BAT 0X0002
+#define PBC_INTR_OTG_FSOVER 0X0004
+#define PBC_INTR_FSH_OVER 0X0008
+#define PBC_INTR_SD3_R_EN 0x0010
+#define PBC_INTR_MS_R_EN 0x0020
+#define PBC_INTR_SD1_R_EN 0x0040
+#define PBC_INTR_FEC_INT 0X0080
+#define PBC_INTR_ENET_INT 0X0100
+#define PBC_INTR_OTGFS_INT 0X0200
+#define PBC_INTR_XUART_INT 0X0400
+#define PBC_INTR_CCTL12 0X0800
+#define PBC_INTR_SD2_EN 0x1000
+#define PBC_INTR_SD3_EN 0x2000
+#define PBC_INTR_MS_EN 0x4000
+#define PBC_INTR_SD1_EN 0x8000
+
+/*! @} */
+
+#define CKIH_27MHZ_BIT_SET (1 << 3)
+
+/* For interrupts like xuart, enet etc */
+#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
+
+/*
+ * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
+ *
+ */
+#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
+
+/*! This is System IRQ used by CS8900A for interrupt generation taken from platform.h */
+#define CS8900AIRQ EXPIO_INT_ENET_INT
+/*! This is I/O Base address used to access registers of CS8900A on MXC ADS */
+#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
+
+#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
+
+/*!
+* This is used to detect if the CPLD version is for mx27 evb board rev-a
+*/
+#define PBC_CPLD_VERSION_IS_REVA() \
+ ((__raw_readw(PBC_VERSION_REG) & \
+ (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
+ == 0)
+
+#define MXC_BD_LED1 (1 << 5)
+#define MXC_BD_LED2 (1 << 6)
+#define MXC_BD_LED_ON(led) \
+ __raw_writew(led, PBC_BCTRL1_SET_REG)
+#define MXC_BD_LED_OFF(led) \
+ __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx27/clock.c linux-2.6.26-lab126/arch/arm/mach-mx27/clock.c
--- linux-2.6.26/arch/arm/mach-mx27/clock.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/clock.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,1549 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "crm_regs.h"
+
+#define CKIH_CLK_FREQ 26000000 /* 26M reference clk */
+#define CKIH_CLK_FREQ_27MHZ 27000000
+#define CKIL_CLK_FREQ 32768 /* 32.768k oscillator in */
+
+static struct clk ckil_clk;
+static struct clk mpll_clk;
+static struct clk mpll_main_clk[];
+static struct clk spll_clk;
+
+static int _clk_enable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(1 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_spll_enable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg |= CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+
+ while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) ;
+
+ return 0;
+}
+
+static void _clk_spll_disable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg &= ~CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+}
+
+static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_PCCR0);
+ reg |= mask0;
+ __raw_writel(reg, CCM_PCCR0);
+
+ reg = __raw_readl(CCM_PCCR1);
+ reg |= mask1;
+ __raw_writel(reg, CCM_PCCR1);
+
+}
+
+static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_PCCR0);
+ reg &= ~mask0;
+ __raw_writel(reg, CCM_PCCR0);
+
+ reg = __raw_readl(CCM_PCCR1);
+ reg &= ~mask1;
+ __raw_writel(reg, CCM_PCCR1);
+}
+
+static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_PCCR1);
+ reg |= mask1;
+ __raw_writel(reg, CCM_PCCR1);
+
+ reg = __raw_readl(CCM_PCCR0);
+ reg |= mask0;
+ __raw_writel(reg, CCM_PCCR0);
+}
+
+static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_PCCR1);
+ reg &= ~mask1;
+ __raw_writel(reg, CCM_PCCR1);
+
+ reg = __raw_readl(CCM_PCCR0);
+ reg &= ~mask0;
+ __raw_writel(reg, CCM_PCCR0);
+}
+
+static int _clk_dma_enable(struct clk *clk)
+{
+ _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+
+ return 0;
+}
+
+static void _clk_dma_disable(struct clk *clk)
+{
+ _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+}
+
+static int _clk_rtic_enable(struct clk *clk)
+{
+ _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+
+ return 0;
+}
+
+static void _clk_rtic_disable(struct clk *clk)
+{
+ _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+}
+
+static int _clk_emma_enable(struct clk *clk)
+{
+ _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+
+ return 0;
+}
+
+static void _clk_emma_disable(struct clk *clk)
+{
+ _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+}
+
+static int _clk_slcdc_enable(struct clk *clk)
+{
+ _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+
+ return 0;
+}
+
+static void _clk_slcdc_disable(struct clk *clk)
+{
+ _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+}
+
+static int _clk_fec_enable(struct clk *clk)
+{
+ _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+
+ return 0;
+}
+
+static void _clk_fec_disable(struct clk *clk)
+{
+ _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+}
+
+static int _clk_vpu_enable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_PCCR1);
+ reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
+ __raw_writel(reg, CCM_PCCR1);
+
+ return 0;
+}
+
+static void _clk_vpu_disable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_PCCR1);
+ reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
+ __raw_writel(reg, CCM_PCCR1);
+}
+
+static int _clk_sahara2_enable(struct clk *clk)
+{
+ _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+
+ return 0;
+}
+
+static void _clk_sahara2_disable(struct clk *clk)
+{
+ _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+}
+
+static int _clk_mstick1_enable(struct clk *clk)
+{
+ _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+
+ return 0;
+}
+
+static void _clk_mstick1_disable(struct clk *clk)
+{
+ _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+}
+
+#define CSCR() (__raw_readl(CCM_CSCR))
+#define PCDR0() (__raw_readl(CCM_PCDR0))
+#define PCDR1() (__raw_readl(CCM_PCDR1))
+
+static void _clk_pll_recalc(struct clk *clk)
+{
+ unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+ unsigned long ref_clk;
+ unsigned long reg;
+ unsigned long long temp;
+
+ ref_clk = clk->parent->rate;
+ if (clk->parent == &ckil_clk) {
+ ref_clk *= 1024;
+ }
+
+ if (clk == &mpll_clk) {
+ reg = __raw_readl(CCM_MPCTL0);
+ pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
+ mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+ mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+ mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+ } else if (clk == &spll_clk) {
+ reg = __raw_readl(CCM_SPCTL0);
+ /*TODO: This is TO2 Bug */
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) == 1) {
+ __raw_writel(reg, CCM_SPCTL0);
+ }
+ pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+ mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+ mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+ mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+ } else {
+ BUG(); /* oops */
+ }
+
+ mfi = (mfi <= 5) ? 5 : mfi;
+ temp = 2LL * ref_clk * mfn;
+ do_div(temp, mfd + 1);
+ temp = 2LL * ref_clk * mfi + temp;
+ do_div(temp, pdf + 1);
+
+ clk->rate = temp;
+}
+
+static void _clk_mpll_main_recalc(struct clk *clk)
+{
+ /* i.MX27 TO2:
+ * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2
+ * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3
+ */
+ switch (clk->id) {
+ case 0:
+ clk->rate = clk->parent->rate;
+ break;
+ case 1:
+ clk->rate = 2 * clk->parent->rate / 3;
+ }
+}
+
+static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
+{
+ int cscr = CSCR();
+
+ if (clk->parent == parent)
+ return 0;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ if (parent == &mpll_main_clk[0]) {
+ cscr |= CCM_CSCR_ARM_SRC;
+ } else {
+ if (parent == &mpll_main_clk[1]) {
+ cscr &= ~CCM_CSCR_ARM_SRC;
+ } else {
+ return -EINVAL;
+ }
+ }
+ __raw_writel(CCM_CSCR, cscr);
+ } else {
+ return -ENODEV;
+ }
+ clk->parent = parent;
+ return 0;
+}
+
+static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
+{
+ int div;
+ div = clk->parent->rate / rate;
+ if (clk->parent->rate % rate) {
+ div++;
+ }
+
+ if (div > 4) {
+ div = 4;
+ }
+ return clk->parent->rate / div;
+}
+
+static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+ int div, reg;
+ div = clk->parent->rate / rate;
+
+ if (div > 4 || div < 1 || ((clk->parent->rate / div) != rate)) {
+ return -EINVAL;
+ }
+ div--;
+
+ reg = (CSCR() & ~CCM_CSCR_ARM_MASK) | (div << CCM_CSCR_ARM_OFFSET);
+ __raw_writel(CCM_CSCR, reg);
+ clk->rate = rate;
+ return 0;
+}
+
+static void _clk_cpu_recalc(struct clk *clk)
+{
+ unsigned long div;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET;
+ } else {
+ div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+ }
+
+ clk->rate = clk->parent->rate / (div + 1);
+}
+
+static void _clk_ahb_recalc(struct clk *clk)
+{
+ unsigned long bclk_pdf;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK) >> CCM_CSCR_AHB_OFFSET;
+ } else {
+ bclk_pdf =
+ (CSCR() & CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET;
+ }
+ clk->rate = clk->parent->rate / (bclk_pdf + 1);
+}
+
+static void _clk_perclkx_recalc(struct clk *clk)
+{
+ unsigned long perclk_pdf;
+
+ if (clk->id < 0 || clk->id > 3)
+ return;
+
+ perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+
+ clk->rate = clk->parent->rate / (perclk_pdf + 1);
+}
+
+static unsigned long _clk_perclkx_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+
+ div = clk->parent->rate / rate;
+ if (clk->parent->rate % rate)
+ div++;
+
+ if (div > 64) {
+ div = 64;
+ }
+
+ return clk->parent->rate / div;
+}
+
+static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+
+ if (clk->id < 0 || clk->id > 3)
+ return -EINVAL;
+
+ div = clk->parent->rate / rate;
+ if (div > 64 || div < 1 || ((clk->parent->rate / div) != rate)) {
+ return -EINVAL;
+ }
+ div--;
+
+ reg =
+ __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
+ (clk->id << 3));
+ reg |= div << (clk->id << 3);
+ __raw_writel(reg, CCM_PCDR1);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+static void _clk_usb_recalc(struct clk *clk)
+{
+ unsigned long usb_pdf;
+
+ usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+
+ clk->rate = clk->parent->rate / (usb_pdf + 1);
+}
+
+static void _clk_ssi1_recalc(struct clk *clk)
+{
+ unsigned long ssi1_pdf;
+
+ ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
+ CCM_PCDR0_SSI1BAUDDIV_OFFSET;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ ssi1_pdf += 4;
+ } else {
+ ssi1_pdf = (ssi1_pdf < 2) ? 124 : ssi1_pdf;
+ }
+
+ clk->rate = 2 * clk->parent->rate / ssi1_pdf;
+}
+
+static void _clk_ssi2_recalc(struct clk *clk)
+{
+ unsigned long ssi2_pdf;
+
+ ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+ CCM_PCDR0_SSI2BAUDDIV_OFFSET;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ ssi2_pdf += 4;
+ } else {
+ ssi2_pdf = (ssi2_pdf < 2) ? 124 : ssi2_pdf;
+ }
+
+ clk->rate = 2 * clk->parent->rate / ssi2_pdf;
+}
+
+static void _clk_nfc_recalc(struct clk *clk)
+{
+ unsigned long nfc_pdf;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ nfc_pdf =
+ (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >>
+ CCM_PCDR0_NFCDIV2_OFFSET;
+ } else {
+ nfc_pdf =
+ (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
+ CCM_PCDR0_NFCDIV_OFFSET;
+ }
+
+ clk->rate = clk->parent->rate / (nfc_pdf + 1);
+}
+
+static void _clk_vpu_recalc(struct clk *clk)
+{
+ unsigned long vpu_pdf;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ vpu_pdf =
+ (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
+ CCM_PCDR0_VPUDIV2_OFFSET;
+ vpu_pdf += 4;
+ } else {
+ vpu_pdf =
+ (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
+ CCM_PCDR0_VPUDIV_OFFSET;
+ vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
+ }
+ clk->rate = 2 * clk->parent->rate / vpu_pdf;
+}
+
+static void _clk_ipg_recalc(struct clk *clk)
+{
+ unsigned long ipg_pdf;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ ipg_pdf = 1;
+ } else {
+ ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+ }
+
+ clk->rate = clk->parent->rate / (ipg_pdf + 1);
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+ return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret;
+ if ((ret = clk->parent->set_rate(clk->parent, rate)) == 0)
+ clk->rate = rate;
+ return ret;
+}
+
+static struct clk ckih_clk = {
+ .name = "ckih",
+ .rate = 0, /* determined at boot time (26 or 27 MHz) */
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk ckil_clk = {
+ .name = "ckil",
+ .rate = CKIL_CLK_FREQ,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk mpll_clk = {
+ .name = "mpll",
+ .parent = &ckih_clk,
+ .recalc = _clk_pll_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk mpll_main_clk[] = {
+ {
+ /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+ * It provide the clock source whose rate is same as MPLL
+ */
+ .name = "mpll_main",
+ .id = 0,
+ .parent = &mpll_clk,
+ .recalc = _clk_mpll_main_recalc,},
+ {
+ /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+ * It provide the clock source whose rate is same as MPLL
+ */
+ .name = "mpll_main",
+ .id = 1,
+ .parent = &mpll_clk,
+ .recalc = _clk_mpll_main_recalc,}
+};
+
+static struct clk spll_clk = {
+ .name = "spll",
+ .parent = &ckih_clk,
+ .recalc = _clk_pll_recalc,
+ .enable = _clk_spll_enable,
+ .disable = _clk_spll_disable,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk cpu_clk = {
+ .name = "cpu_clk",
+ .parent = &mpll_main_clk[1],
+ .set_parent = _clk_cpu_set_parent,
+ .round_rate = _clk_cpu_round_rate,
+ .set_rate = _clk_cpu_set_rate,
+ .recalc = _clk_cpu_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk ahb_clk = {
+ .name = "ahb_clk",
+ .parent = &mpll_main_clk[1],
+ .recalc = _clk_ahb_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk ipg_clk = {
+ .name = "ipg_clk",
+ .parent = &ahb_clk,
+ .recalc = _clk_ipg_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk per_clk[] = {
+ {
+ .name = "per_clk",
+ .id = 0,
+ .parent = &mpll_main_clk[1],
+ .recalc = _clk_perclkx_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
+ .disable = _clk_disable,
+ .flags = RATE_PROPAGATES,},
+ {
+ .name = "per_clk",
+ .id = 1,
+ .parent = &mpll_main_clk[1],
+ .recalc = _clk_perclkx_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
+ .disable = _clk_disable,
+ .flags = RATE_PROPAGATES,},
+ {
+ .name = "per_clk",
+ .id = 2,
+ .parent = &mpll_main_clk[1],
+ .round_rate = _clk_perclkx_round_rate,
+ .set_rate = _clk_perclkx_set_rate,
+ .recalc = _clk_perclkx_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
+ .disable = _clk_disable,
+ .flags = RATE_PROPAGATES,},
+ {
+ .name = "per_clk",
+ .id = 3,
+ .parent = &mpll_main_clk[1],
+ .round_rate = _clk_perclkx_round_rate,
+ .set_rate = _clk_perclkx_set_rate,
+ .recalc = _clk_perclkx_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
+ .disable = _clk_disable,
+ .flags = RATE_PROPAGATES,},
+};
+
+struct clk uart1_clk[] = {
+ {
+ .name = "uart_clk",
+ .id = 0,
+ .parent = &per_clk[0],
+ .secondary = &uart1_clk[1],},
+ {
+ .name = "uart_ipg_clk",
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_UART1_OFFSET,
+ .disable = _clk_disable,},
+};
+
+struct clk uart2_clk[] = {
+ {
+ .name = "uart_clk",
+ .id = 1,
+ .parent = &per_clk[0],
+ .secondary = &uart2_clk[1],},
+ {
+ .name = "uart_ipg_clk",
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_UART2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+struct clk uart3_clk[] = {
+ {
+ .name = "uart_clk",
+ .id = 2,
+ .parent = &per_clk[0],
+ .secondary = &uart3_clk[1],},
+ {
+ .name = "uart_ipg_clk",
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_UART3_OFFSET,
+ .disable = _clk_disable,},
+};
+
+struct clk uart4_clk[] = {
+ {
+ .name = "uart_clk",
+ .id = 3,
+ .parent = &per_clk[0],
+ .secondary = &uart4_clk[1],},
+ {
+ .name = "uart_ipg_clk",
+ .id = 3,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_UART4_OFFSET,
+ .disable = _clk_disable,},
+};
+
+struct clk uart5_clk[] = {
+ {
+ .name = "uart_clk",
+ .id = 4,
+ .parent = &per_clk[0],
+ .secondary = &uart5_clk[1],},
+ {
+ .name = "uart_ipg_clk",
+ .id = 4,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_UART5_OFFSET,
+ .disable = _clk_disable,},
+};
+
+struct clk uart6_clk[] = {
+ {
+ .name = "uart_clk",
+ .id = 5,
+ .parent = &per_clk[0],
+ .secondary = &uart6_clk[1],},
+ {
+ .name = "uart_ipg_clk",
+ .id = 5,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_UART6_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk gpt1_clk[] = {
+ {
+ .name = "gpt_clk",
+ .id = 0,
+ .parent = &per_clk[0],
+ .secondary = &gpt1_clk[1],},
+ {
+ .name = "gpt_ipg_clk",
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_GPT1_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk gpt2_clk[] = {
+ {
+ .name = "gpt_clk",
+ .id = 1,
+ .parent = &per_clk[0],
+ .secondary = &gpt2_clk[1],},
+ {
+ .name = "gpt_ipg_clk",
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_GPT2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk gpt3_clk[] = {
+ {
+ .name = "gpt_clk",
+ .id = 2,
+ .parent = &per_clk[0],
+ .secondary = &gpt3_clk[1],},
+ {
+ .name = "gpt_ipg_clk",
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_GPT3_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk gpt4_clk[] = {
+ {
+ .name = "gpt_clk",
+ .id = 3,
+ .parent = &per_clk[0],
+ .secondary = &gpt4_clk[1],},
+ {
+ .name = "gpt_ipg_clk",
+ .id = 3,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_GPT4_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk gpt5_clk[] = {
+ {
+ .name = "gpt_clk",
+ .id = 4,
+ .parent = &per_clk[0],
+ .secondary = &gpt5_clk[1],},
+ {
+ .name = "gpt_ipg_clk",
+ .id = 4,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_GPT5_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk gpt6_clk[] = {
+ {
+ .name = "gpt_clk",
+ .id = 5,
+ .parent = &per_clk[0],
+ .secondary = &gpt6_clk[1],},
+ {
+ .name = "gpt_ipg_clk",
+ .id = 5,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_GPT6_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk pwm_clk[] = {
+ {
+ .name = "pwm_clk",
+ .parent = &per_clk[0],
+ .secondary = &pwm_clk[1],},
+ {
+ .name = "pwm_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_PWM_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk sdhc1_clk[] = {
+ {
+ .name = "sdhc_clk",
+ .id = 0,
+ .parent = &per_clk[1],
+ .secondary = &sdhc1_clk[1],},
+ {
+ .name = "sdhc_ipg_clk",
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk sdhc2_clk[] = {
+ {
+ .name = "sdhc_clk",
+ .id = 1,
+ .parent = &per_clk[1],
+ .secondary = &sdhc2_clk[1],},
+ {
+ .name = "sdhc_ipg_clk",
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk sdhc3_clk[] = {
+ {
+ .name = "sdhc_clk",
+ .id = 2,
+ .parent = &per_clk[1],
+ .secondary = &sdhc3_clk[1],},
+ {
+ .name = "sdhc_ipg_clk",
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk cspi1_clk[] = {
+ {
+ .name = "cspi_clk",
+ .id = 0,
+ .parent = &per_clk[1],
+ .secondary = &cspi1_clk[1],},
+ {
+ .name = "cspi_ipg_clk",
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk cspi2_clk[] = {
+ {
+ .name = "cspi_clk",
+ .id = 1,
+ .parent = &per_clk[1],
+ .secondary = &cspi2_clk[1],},
+ {
+ .name = "cspi_ipg_clk",
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk cspi3_clk[] = {
+ {
+ .name = "cspi_clk",
+ .id = 2,
+ .parent = &per_clk[1],
+ .secondary = &cspi3_clk[1],},
+ {
+ .name = "cspi_ipg_clk",
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk lcdc_clk[] = {
+ {
+ .name = "lcdc_clk",
+ .parent = &per_clk[2],
+ .secondary = &lcdc_clk[1],
+ .round_rate = _clk_parent_round_rate,
+ .set_rate = _clk_parent_set_rate,},
+ {
+ .name = "lcdc_ipg_clk",
+ .parent = &ipg_clk,
+ .secondary = &lcdc_clk[2],
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_LCDC_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "lcdc_ahb_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk csi_clk[] = {
+ {
+ .name = "csi_perclk",
+ .parent = &per_clk[3],
+ .secondary = &csi_clk[1],
+ .round_rate = _clk_parent_round_rate,
+ .set_rate = _clk_parent_set_rate,},
+ {
+ .name = "csi_ahb_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk usb_clk[] = {
+ {
+ .name = "usb_clk",
+ .parent = &spll_clk,
+ .recalc = _clk_usb_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_USBOTG_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "usb_ahb_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
+ .disable = _clk_disable,}
+};
+
+static struct clk ssi1_clk[] = {
+ {
+ .name = "ssi_clk",
+ .id = 0,
+ .parent = &mpll_main_clk[1],
+ .secondary = &ssi1_clk[1],
+ .recalc = _clk_ssi1_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "ssi_ipg_clk",
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk ssi2_clk[] = {
+ {
+ .name = "ssi_clk",
+ .id = 1,
+ .parent = &mpll_main_clk[1],
+ .secondary = &ssi2_clk[1],
+ .recalc = _clk_ssi2_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "ssi_ipg_clk",
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk nfc_clk = {
+ .name = "nfc_clk",
+ .parent = &cpu_clk,
+ .recalc = _clk_nfc_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk vpu_clk = {
+ .name = "vpu_clk",
+ .parent = &mpll_main_clk[1],
+ .recalc = _clk_vpu_recalc,
+ .enable = _clk_vpu_enable,
+ .disable = _clk_vpu_disable,
+};
+
+static struct clk dma_clk = {
+ .name = "dma_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_dma_enable,
+ .disable = _clk_dma_disable,
+};
+
+static struct clk rtic_clk = {
+ .name = "rtic_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_rtic_enable,
+ .disable = _clk_rtic_disable,
+};
+
+static struct clk brom_clk = {
+ .name = "brom_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk emma_clk = {
+ .name = "emma_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_emma_enable,
+ .disable = _clk_emma_disable,
+};
+
+static struct clk slcdc_clk = {
+ .name = "slcdc_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_slcdc_enable,
+ .disable = _clk_slcdc_disable,
+};
+
+static struct clk fec_clk = {
+ .name = "fec_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_fec_enable,
+ .disable = _clk_fec_disable,
+};
+
+static struct clk emi_clk = {
+ .name = "emi_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk sahara2_clk = {
+ .name = "sahara_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_sahara2_enable,
+ .disable = _clk_sahara2_disable,
+};
+
+static struct clk ata_clk = {
+ .name = "ata_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk mstick1_clk = {
+ .name = "mstick1_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_mstick1_enable,
+ .disable = _clk_mstick1_disable,
+};
+
+static struct clk wdog_clk = {
+ .name = "wdog_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR1_WDT_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk gpio_clk = {
+ .name = "gpio_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR1,
+ .enable_shift = CCM_PCCR0_GPIO_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk i2c_clk[] = {
+ {
+ .name = "i2c_clk",
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_I2C1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "i2c_clk",
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_I2C2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk iim_clk = {
+ .name = "iim_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_IIM_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+ .name = "kpp_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_KPP_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk owire_clk = {
+ .name = "owire_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+ .name = "rtc_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_RTC_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk scc_clk = {
+ .name = "scc_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR0,
+ .enable_shift = CCM_PCCR0_SCC_OFFSET,
+ .disable = _clk_disable,
+};
+
+static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 div;
+
+ div = clk->parent->rate / rate;
+ if (clk->parent->rate % rate)
+ div++;
+
+ if (div > 8) {
+ div = 8;
+ }
+
+ return clk->parent->rate / div;
+}
+
+static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+
+ div = clk->parent->rate / rate;
+
+ if (div > 8 || div < 1 || ((clk->parent->rate / div) != rate)) {
+ return -EINVAL;
+ }
+ div--;
+
+ reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
+ reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
+ __raw_writel(reg, CCM_PCDR0);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+static void _clk_clko_recalc(struct clk *clk)
+{
+ u32 div;
+
+ div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
+ CCM_PCDR0_CLKODIV_OFFSET;
+ div++;
+
+ clk->rate = clk->parent->rate / div;
+}
+
+static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
+
+ if (parent == &ckil_clk) {
+ reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &ckih_clk) {
+ reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == mpll_clk.parent) {
+ reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == spll_clk.parent) {
+ reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &mpll_clk) {
+ reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &spll_clk) {
+ reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &cpu_clk) {
+ reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &ahb_clk) {
+ reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &ipg_clk) {
+ reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &per_clk[0]) {
+ reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &per_clk[1]) {
+ reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &per_clk[2]) {
+ reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &per_clk[3]) {
+ reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &ssi1_clk[0]) {
+ reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &ssi2_clk[0]) {
+ reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &nfc_clk) {
+ reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &mstick1_clk) {
+ reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &vpu_clk) {
+ reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else if (parent == &usb_clk[0]) {
+ reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
+ } else {
+ return -EINVAL;
+ }
+
+ __raw_writel(reg, CCM_CCSR);
+
+ return 0;
+}
+
+static int _clk_clko_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
+ __raw_writel(reg, CCM_PCDR0);
+
+ return 0;
+}
+
+static void _clk_clko_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
+ __raw_writel(reg, CCM_PCDR0);
+}
+
+static struct clk clko_clk = {
+ .name = "clko_clk",
+ .recalc = _clk_clko_recalc,
+ .set_rate = _clk_clko_set_rate,
+ .round_rate = _clk_clko_round_rate,
+ .set_parent = _clk_clko_set_parent,
+ .enable = _clk_clko_enable,
+ .disable = _clk_clko_disable,
+};
+
+static struct clk *mxc_clks[] = {
+ &ckih_clk,
+ &ckil_clk,
+ &mpll_clk,
+ &mpll_main_clk[0],
+ &mpll_main_clk[1],
+ &spll_clk,
+ &cpu_clk,
+ &ahb_clk,
+ &ipg_clk,
+ &per_clk[0],
+ &per_clk[1],
+ &per_clk[2],
+ &per_clk[3],
+ &clko_clk,
+ &uart1_clk[0],
+ &uart1_clk[1],
+ &uart2_clk[0],
+ &uart2_clk[1],
+ &uart3_clk[0],
+ &uart3_clk[1],
+ &uart4_clk[0],
+ &uart4_clk[1],
+ &uart5_clk[0],
+ &uart5_clk[1],
+ &uart6_clk[0],
+ &uart6_clk[1],
+ &gpt1_clk[0],
+ &gpt1_clk[1],
+ &gpt2_clk[0],
+ &gpt2_clk[1],
+ &gpt3_clk[0],
+ &gpt3_clk[1],
+ &gpt4_clk[0],
+ &gpt4_clk[1],
+ &gpt5_clk[0],
+ &gpt5_clk[1],
+ &gpt6_clk[0],
+ &gpt6_clk[1],
+ &pwm_clk[0],
+ &pwm_clk[1],
+ &sdhc1_clk[0],
+ &sdhc1_clk[1],
+ &sdhc2_clk[0],
+ &sdhc2_clk[1],
+ &sdhc3_clk[0],
+ &sdhc3_clk[1],
+ &cspi1_clk[0],
+ &cspi1_clk[1],
+ &cspi2_clk[0],
+ &cspi2_clk[1],
+ &cspi3_clk[0],
+ &cspi3_clk[1],
+ &lcdc_clk[0],
+ &lcdc_clk[1],
+ &lcdc_clk[2],
+ &csi_clk[0],
+ &csi_clk[1],
+ &usb_clk[0],
+ &usb_clk[1],
+ &ssi1_clk[0],
+ &ssi1_clk[1],
+ &ssi2_clk[0],
+ &ssi2_clk[1],
+ &nfc_clk,
+ &vpu_clk,
+ &dma_clk,
+ &rtic_clk,
+ &brom_clk,
+ &emma_clk,
+ &slcdc_clk,
+ &fec_clk,
+ &emi_clk,
+ &sahara2_clk,
+ &ata_clk,
+ &mstick1_clk,
+ &wdog_clk,
+ &gpio_clk,
+ &i2c_clk[0],
+ &i2c_clk[1],
+ &iim_clk,
+ &kpp_clk,
+ &owire_clk,
+ &rtc_clk,
+ &scc_clk,
+};
+
+static void probe_mxc_clocks(void)
+{
+ int i;
+
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ if (CSCR() & 0x8000) {
+ cpu_clk.parent = &mpll_main_clk[0];
+ }
+
+ if (!(CSCR() & 0x00800000)) {
+ ssi2_clk[0].parent = &spll_clk;
+ }
+
+ if (!(CSCR() & 0x00400000)) {
+ ssi1_clk[0].parent = &spll_clk;
+ }
+
+ if (!(CSCR() & 0x00200000)) {
+ vpu_clk.parent = &spll_clk;
+ }
+ } else {
+ cpu_clk.parent = &mpll_clk;
+ cpu_clk.set_parent = NULL;
+ cpu_clk.round_rate = NULL;
+ cpu_clk.set_rate = NULL;
+ ahb_clk.parent = &mpll_clk;
+
+ for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++) {
+ per_clk[i].parent = &mpll_clk;
+ }
+
+ ssi1_clk[0].parent = &mpll_clk;
+ ssi2_clk[0].parent = &mpll_clk;
+
+ vpu_clk.parent = &mpll_clk;
+ }
+}
+
+/*!
+ * Function to get timer clock rate early in boot process before clock tree is
+ * initialized.
+ *
+ * @return Clock rate for timer
+ */
+unsigned long __init clk_early_get_timer_rate(void)
+{
+ if (CSCR() & CCM_CSCR_MCU) {
+ mpll_clk.parent = &ckih_clk;
+ } else {
+ mpll_clk.parent = &ckil_clk;
+ }
+
+ /* Determine which high frequency clock source is coming in */
+ ckih_clk.rate = board_get_ckih_rate();
+
+ probe_mxc_clocks();
+
+ mpll_clk.recalc(&mpll_clk);
+ if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) {
+ mpll_main_clk[0].recalc(&mpll_main_clk[0]);
+ mpll_main_clk[1].recalc(&mpll_main_clk[1]);
+ }
+ per_clk[0].recalc(&per_clk[0]);
+ per_clk[0].enable(&per_clk[0]);
+ gpt1_clk[1].enable(&gpt1_clk[1]);
+ return per_clk[0].rate;
+}
+
+extern void propagate_rate(struct clk *tclk);
+
+int __init mxc_clocks_init(void)
+{
+ u32 cscr;
+ struct clk **clkp;
+
+ for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) {
+ if (*clkp == &mpll_main_clk[0] || *clkp == &mpll_main_clk[1]) {
+ if (cpu_is_mx27_rev(CHIP_REV_1_0) == 1)
+ continue;
+ }
+ clk_register(*clkp);
+ }
+
+ /* Turn off all possible clocks */
+ __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
+ __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
+ CCM_PCCR1);
+ spll_clk.disable(&spll_clk);
+
+ cscr = CSCR();
+ if (cscr & CCM_CSCR_MCU) {
+ mpll_clk.parent = &ckih_clk;
+ } else {
+ mpll_clk.parent = &ckil_clk;
+ }
+ if (cscr & CCM_CSCR_SP) {
+ spll_clk.parent = &ckih_clk;
+ } else {
+ spll_clk.parent = &ckil_clk;
+ }
+
+ pr_info("Clock input source is %ld\n", ckih_clk.rate);
+
+ /* This will propagate to all children and init all the clock rates */
+ propagate_rate(&ckih_clk);
+ propagate_rate(&ckil_clk);
+
+ clk_enable(&emi_clk);
+ clk_enable(&gpio_clk);
+ clk_enable(&iim_clk);
+ clk_enable(&gpt1_clk[0]);
+
+ return 0;
+}
diff -urN linux-2.6.26/arch/arm/mach-mx27/cpu.c linux-2.6.26-lab126/arch/arm/mach-mx27/cpu.c
--- linux-2.6.26/arch/arm/mach-mx27/cpu.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/cpu.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2001 Deep Blue Solutions Ltd.
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*!
+ * @file mach-mx27/cpu.c
+ *
+ * @brief This file contains the CPU initialization code.
+ *
+ * @ingroup MSL_MX27
+ */
+
+#include
+#include
+#include
+#include
+
+/*!
+ * CPU initialization. It is called by fixup_mxc_board()
+ */
+void __init mxc_cpu_init(void)
+{
+ if (!system_rev) {
+ mxc_set_system_rev(0x27, CHIP_REV_2_0);
+ }
+}
diff -urN linux-2.6.26/arch/arm/mach-mx27/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx27/crm_regs.h
--- linux-2.6.26/arch/arm/mach-mx27/crm_regs.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/crm_regs.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,283 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ARCH_ARM_MACH_MX27_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX27_CRM_REGS_H__
+
+#include
+
+#define SYSCTRL_BASE IO_ADDRESS(SYSCTRL_BASE_ADDR)
+
+/* Register offsets */
+#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
+#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
+#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
+#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
+#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
+#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
+#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
+#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
+#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
+#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
+#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
+#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
+#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
+#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
+#define MXC_CCM_PMCR0 (SYSCTRL_BASE + 0x60)
+#define MXC_CCM_DCVR0 (SYSCTRL_BASE + 0x64)
+#define MXC_CCM_DCVR1 (SYSCTRL_BASE + 0x68)
+#define MXC_CCM_DCVR2 (SYSCTRL_BASE + 0x72)
+#define MXC_CCM_DCVR3 (SYSCTRL_BASE + 0x76)
+#define MXC_CCM_PMCR0_DPTEN 0x00000001
+#define MXC_CCM_DIE 0x00000002
+#define MXC_CCM_DIM 0x0000000C
+#define MXC_CCM_DCR 0x00000200
+#define MXC_CCM_PMCR0_DRCE0 0x00000010
+#define MXC_CCM_PMCR0_DRCE1 0x00000020
+#define MXC_CCM_PMCR0_DRCE2 0x00000040
+#define MXC_CCM_PMCR0_DRCE3 0x00000080
+#define MXC_CCM_PMCR0_PTVAIM MXC_CCM_DIM
+
+#define CCM_CSCR_USB_OFFSET 28
+#define CCM_CSCR_USB_MASK (0x7 << 28)
+#define CCM_CSCR_SD_OFFSET 24
+#define CCM_CSCR_SD_MASK (0x3 << 24)
+#define CCM_CSCR_SSI2 (1 << 23)
+#define CCM_CSCR_SSI2_OFFSET 23
+#define CCM_CSCR_SSI1 (1 << 22)
+#define CCM_CSCR_SSI1_OFFSET 22
+#define CCM_CSCR_VPU (1 << 21)
+#define CCM_CSCR_VPU_OFFSET 21
+#define CCM_CSCR_MSHC (1 << 20)
+#define CCM_CSCR_SPLLRES (1 << 19)
+#define CCM_CSCR_MPLLRES (1 << 18)
+#define CCM_CSCR_SP (1 << 17)
+#define CCM_CSCR_MCU (1 << 16)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_ARM_SRC (1 << 15)
+#define CCM_CSCR_ARM_OFFSET 12
+#define CCM_CSCR_ARM_MASK (0x3 << 12)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_PRESC_OFFSET 13
+#define CCM_CSCR_PRESC_MASK (0x7 << 13)
+#define CCM_CSCR_BCLK_OFFSET 9
+#define CCM_CSCR_BCLK_MASK (0xf << 9)
+#define CCM_CSCR_IPDIV_OFFSET 8
+#define CCM_CSCR_IPDIV (1 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_AHB_OFFSET 8
+#define CCM_CSCR_AHB_MASK (0x3 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_OSC26MDIV (1 << 4)
+#define CCM_CSCR_OSC26M (1 << 3)
+#define CCM_CSCR_FPM (1 << 2)
+#define CCM_CSCR_SPEN (1 << 1)
+#define CCM_CSCR_MPEN 1
+
+#define CCM_MPCTL0_CPLM (1 << 31)
+#define CCM_MPCTL0_PD_OFFSET 26
+#define CCM_MPCTL0_PD_MASK (0xf << 26)
+#define CCM_MPCTL0_MFD_OFFSET 16
+#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
+#define CCM_MPCTL0_MFI_OFFSET 10
+#define CCM_MPCTL0_MFI_MASK (0xf << 10)
+#define CCM_MPCTL0_MFN_OFFSET 0
+#define CCM_MPCTL0_MFN_MASK 0x3ff
+
+#define CCM_MPCTL1_LF (1 << 15)
+#define CCM_MPCTL1_BRMO (1 << 6)
+
+#define CCM_SPCTL0_CPLM (1 << 31)
+#define CCM_SPCTL0_PD_OFFSET 26
+#define CCM_SPCTL0_PD_MASK (0xf << 26)
+#define CCM_SPCTL0_MFD_OFFSET 16
+#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
+#define CCM_SPCTL0_MFI_OFFSET 10
+#define CCM_SPCTL0_MFI_MASK (0xf << 10)
+#define CCM_SPCTL0_MFN_OFFSET 0
+#define CCM_SPCTL0_MFN_MASK 0x3ff
+
+#define CCM_SPCTL1_LF (1 << 15)
+#define CCM_SPCTL1_BRMO (1 << 6)
+
+#define CCM_OSC26MCTL_PEAK_OFFSET 16
+#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
+#define CCM_OSC26MCTL_AGC_OFFSET 8
+#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
+#define CCM_OSC26MCTL_ANATEST_OFFSET 0
+#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
+
+#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
+#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
+#define CCM_PCDR0_CLKO_EN 25
+#define CCM_PCDR0_CLKODIV_OFFSET 22
+#define CCM_PCDR0_CLKODIV_MASK (0x7 << 22)
+#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
+#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_VPUDIV2_OFFSET 10
+#define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10)
+#define CCM_PCDR0_NFCDIV2_OFFSET 6
+#define CCM_PCDR0_NFCDIV2_MASK (0xf << 6)
+#define CCM_PCDR0_MSHCDIV2_MASK 0x3f
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_NFCDIV_OFFSET 12
+#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
+#define CCM_PCDR0_VPUDIV_OFFSET 8
+#define CCM_PCDR0_VPUDIV_MASK (0xf << 8)
+#define CCM_PCDR0_MSHCDIV_OFFSET 0
+#define CCM_PCDR0_MSHCDIV_MASK 0x1f
+
+#define CCM_PCDR1_PERDIV4_OFFSET 24
+#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
+#define CCM_PCDR1_PERDIV3_OFFSET 16
+#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
+#define CCM_PCDR1_PERDIV2_OFFSET 8
+#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
+#define CCM_PCDR1_PERDIV1_OFFSET 0
+#define CCM_PCDR1_PERDIV1_MASK 0x3f
+
+#define CCM_PCCR0_CSPI1_OFFSET 31
+#define CCM_PCCR0_CSPI1_MASK (1 << 31)
+#define CCM_PCCR0_CSPI2_OFFSET 30
+#define CCM_PCCR0_CSPI2_MASK (1 << 30)
+#define CCM_PCCR0_CSPI3_OFFSET 29
+#define CCM_PCCR0_CSPI3_MASK (1 << 29)
+#define CCM_PCCR0_DMA_OFFSET 28
+#define CCM_PCCR0_DMA_MASK (1 << 28)
+#define CCM_PCCR0_EMMA_OFFSET 27
+#define CCM_PCCR0_EMMA_MASK (1 << 27)
+#define CCM_PCCR0_FEC_OFFSET 26
+#define CCM_PCCR0_FEC_MASK (1 << 26)
+#define CCM_PCCR0_GPIO_OFFSET 25
+#define CCM_PCCR0_GPIO_MASK (1 << 25)
+#define CCM_PCCR0_GPT1_OFFSET 24
+#define CCM_PCCR0_GPT1_MASK (1 << 24)
+#define CCM_PCCR0_GPT2_OFFSET 23
+#define CCM_PCCR0_GPT2_MASK (1 << 23)
+#define CCM_PCCR0_GPT3_OFFSET 22
+#define CCM_PCCR0_GPT3_MASK (1 << 22)
+#define CCM_PCCR0_GPT4_OFFSET 21
+#define CCM_PCCR0_GPT4_MASK (1 << 21)
+#define CCM_PCCR0_GPT5_OFFSET 20
+#define CCM_PCCR0_GPT5_MASK (1 << 20)
+#define CCM_PCCR0_GPT6_OFFSET 19
+#define CCM_PCCR0_GPT6_MASK (1 << 19)
+#define CCM_PCCR0_I2C1_OFFSET 18
+#define CCM_PCCR0_I2C1_MASK (1 << 18)
+#define CCM_PCCR0_I2C2_OFFSET 17
+#define CCM_PCCR0_I2C2_MASK (1 << 17)
+#define CCM_PCCR0_IIM_OFFSET 16
+#define CCM_PCCR0_IIM_MASK (1 << 16)
+#define CCM_PCCR0_KPP_OFFSET 15
+#define CCM_PCCR0_KPP_MASK (1 << 15)
+#define CCM_PCCR0_LCDC_OFFSET 14
+#define CCM_PCCR0_LCDC_MASK (1 << 14)
+#define CCM_PCCR0_MSHC_OFFSET 13
+#define CCM_PCCR0_MSHC_MASK (1 << 13)
+#define CCM_PCCR0_OWIRE_OFFSET 12
+#define CCM_PCCR0_OWIRE_MASK (1 << 12)
+#define CCM_PCCR0_PWM_OFFSET 11
+#define CCM_PCCR0_PWM_MASK (1 << 11)
+#define CCM_PCCR0_RTC_OFFSET 9
+#define CCM_PCCR0_RTC_MASK (1 << 9)
+#define CCM_PCCR0_RTIC_OFFSET 8
+#define CCM_PCCR0_RTIC_MASK (1 << 8)
+#define CCM_PCCR0_SAHARA_OFFSET 7
+#define CCM_PCCR0_SAHARA_MASK (1 << 7)
+#define CCM_PCCR0_SCC_OFFSET 6
+#define CCM_PCCR0_SCC_MASK (1 << 6)
+#define CCM_PCCR0_SDHC1_OFFSET 5
+#define CCM_PCCR0_SDHC1_MASK (1 << 5)
+#define CCM_PCCR0_SDHC2_OFFSET 4
+#define CCM_PCCR0_SDHC2_MASK (1 << 4)
+#define CCM_PCCR0_SDHC3_OFFSET 3
+#define CCM_PCCR0_SDHC3_MASK (1 << 3)
+#define CCM_PCCR0_SLCDC_OFFSET 2
+#define CCM_PCCR0_SLCDC_MASK (1 << 2)
+#define CCM_PCCR0_SSI1_IPG_OFFSET 1
+#define CCM_PCCR0_SSI1_IPG_MASK (1 << 1)
+#define CCM_PCCR0_SSI2_IPG_OFFSET 0
+#define CCM_PCCR0_SSI2_IPG_MASK (1 << 0)
+
+#define CCM_PCCR1_UART1_OFFSET 31
+#define CCM_PCCR1_UART1_MASK (1 << 31)
+#define CCM_PCCR1_UART2_OFFSET 30
+#define CCM_PCCR1_UART2_MASK (1 << 30)
+#define CCM_PCCR1_UART3_OFFSET 29
+#define CCM_PCCR1_UART3_MASK (1 << 29)
+#define CCM_PCCR1_UART4_OFFSET 28
+#define CCM_PCCR1_UART4_MASK (1 << 28)
+#define CCM_PCCR1_UART5_OFFSET 27
+#define CCM_PCCR1_UART5_MASK (1 << 27)
+#define CCM_PCCR1_UART6_OFFSET 26
+#define CCM_PCCR1_UART6_MASK (1 << 26)
+#define CCM_PCCR1_USBOTG_OFFSET 25
+#define CCM_PCCR1_USBOTG_MASK (1 << 25)
+#define CCM_PCCR1_WDT_OFFSET 24
+#define CCM_PCCR1_WDT_MASK (1 << 24)
+#define CCM_PCCR1_HCLK_ATA_OFFSET 23
+#define CCM_PCCR1_HCLK_ATA_MASK (1 << 23)
+#define CCM_PCCR1_HCLK_BROM_OFFSET 22
+#define CCM_PCCR1_HCLK_BROM_MASK (1 << 22)
+#define CCM_PCCR1_HCLK_CSI_OFFSET 21
+#define CCM_PCCR1_HCLK_CSI_MASK (1 << 21)
+#define CCM_PCCR1_HCLK_DMA_OFFSET 20
+#define CCM_PCCR1_HCLK_DMA_MASK (1 << 20)
+#define CCM_PCCR1_HCLK_EMI_OFFSET 19
+#define CCM_PCCR1_HCLK_EMI_MASK (1 << 19)
+#define CCM_PCCR1_HCLK_EMMA_OFFSET 18
+#define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18)
+#define CCM_PCCR1_HCLK_FEC_OFFSET 17
+#define CCM_PCCR1_HCLK_FEC_MASK (1 << 17)
+#define CCM_PCCR1_HCLK_VPU_OFFSET 16
+#define CCM_PCCR1_HCLK_VPU_MASK (1 << 16)
+#define CCM_PCCR1_HCLK_LCDC_OFFSET 15
+#define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15)
+#define CCM_PCCR1_HCLK_RTIC_OFFSET 14
+#define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14)
+#define CCM_PCCR1_HCLK_SAHARA_OFFSET 13
+#define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13)
+#define CCM_PCCR1_HCLK_SLCDC_OFFSET 12
+#define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12)
+#define CCM_PCCR1_HCLK_USBOTG_OFFSET 11
+#define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11)
+#define CCM_PCCR1_PERCLK1_OFFSET 10
+#define CCM_PCCR1_PERCLK1_MASK (1 << 10)
+#define CCM_PCCR1_PERCLK2_OFFSET 9
+#define CCM_PCCR1_PERCLK2_MASK (1 << 9)
+#define CCM_PCCR1_PERCLK3_OFFSET 8
+#define CCM_PCCR1_PERCLK3_MASK (1 << 8)
+#define CCM_PCCR1_PERCLK4_OFFSET 7
+#define CCM_PCCR1_PERCLK4_MASK (1 << 7)
+#define CCM_PCCR1_VPU_BAUD_OFFSET 6
+#define CCM_PCCR1_VPU_BAUD_MASK (1 << 6)
+#define CCM_PCCR1_SSI1_BAUD_OFFSET 5
+#define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5)
+#define CCM_PCCR1_SSI2_BAUD_OFFSET 4
+#define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4)
+#define CCM_PCCR1_NFC_BAUD_OFFSET 3
+#define CCM_PCCR1_NFC_BAUD_MASK (1 << 3)
+#define CCM_PCCR1_MSHC_BAUD_OFFSET 2
+#define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2)
+
+#define CCM_CCSR_32KSR (1 << 15)
+#define CCM_CCSR_CLKMODE1 (1 << 9)
+#define CCM_CCSR_CLKMODE0 (1 << 8)
+#define CCM_CCSR_CLKOSEL_OFFSET 0
+#define CCM_CCSR_CLKOSEL_MASK 0x1f
+
+#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
+#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
+
+#endif /* __ARCH_ARM_MACH_MX27_CRM_REGS_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx27/devices.c linux-2.6.26-lab126/arch/arm/mach-mx27/devices.c
--- linux-2.6.26/arch/arm/mach-mx27/devices.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/devices.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,697 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2006-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+
+ /*!
+ * @file mach-mx27/devices.c
+ * @brief device configurations including nor/nand/watchdog for mx27.
+ *
+ * @ingroup MSL_MX27
+ */
+
+#ifndef CONFIG_MX27_DPTC
+extern struct dptc_wp dptc_wp_allfreq[DPTC_WP_SUPPORTED];
+#endif
+
+static void mxc_nop_release(struct device *dev)
+{
+ /* Nothing */
+}
+
+#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE)
+static struct mxc_w1_config mxc_w1_data = {
+ .search_rom_accelerator = 0,
+};
+
+static struct platform_device mxc_w1_devices = {
+ .name = "mxc_w1",
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_w1_data,
+ },
+ .id = 0
+};
+
+static void mxc_init_owire(void)
+{
+ (void)platform_device_register(&mxc_w1_devices);
+}
+#else
+static inline void mxc_init_owire(void)
+{
+}
+#endif
+
+#if defined(CONFIG_RTC_MXC) || defined(CONFIG_RTC_MXC_MODULE)
+static struct resource rtc_resources[] = {
+ {
+ .start = RTC_BASE_ADDR,
+ .end = RTC_BASE_ADDR + 0x30,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MXC_INT_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct platform_device mxc_rtc_device = {
+ .name = "mxc_rtc",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ },
+ .num_resources = ARRAY_SIZE(rtc_resources),
+ .resource = rtc_resources,
+};
+static void mxc_init_rtc(void)
+{
+ (void)platform_device_register(&mxc_rtc_device);
+}
+#else
+static inline void mxc_init_rtc(void)
+{
+}
+#endif
+#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE)
+
+static struct resource wdt_resources[] = {
+ {
+ .start = WDOG1_BASE_ADDR,
+ .end = WDOG1_BASE_ADDR + 0x30,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device mxc_wdt_device = {
+ .name = "mxc_wdt",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ },
+ .num_resources = ARRAY_SIZE(wdt_resources),
+ .resource = wdt_resources,
+};
+
+static void mxc_init_wdt(void)
+{
+ (void)platform_device_register(&mxc_wdt_device);
+}
+#else
+static inline void mxc_init_wdt(void)
+{
+}
+#endif
+/*!
+ * This is platform device structure for adding SCC
+ */
+#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE)
+static struct platform_device mxc_scc_device = {
+ .name = "mxc_scc",
+ .id = 0,
+};
+
+static void mxc_init_scc(void)
+{
+ platform_device_register(&mxc_scc_device);
+}
+#else
+static inline void mxc_init_scc(void)
+{
+}
+#endif
+/* MMC device data */
+
+#if defined(CONFIG_MMC_MXC) || defined(CONFIG_MMC_MXC_MODULE)
+
+extern unsigned int sdhc_get_card_det_status(struct device *dev);
+extern int sdhc_init_card_det(int id);
+
+static struct mxc_mmc_platform_data mmc_data = {
+ .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30,
+ .min_clk = 150000,
+ .max_clk = 25000000,
+ .card_inserted_state = 0,
+ .status = sdhc_get_card_det_status,
+};
+
+/*!
+ * Resource definition for the SDHC1
+ */
+static struct resource mxcsdhc1_resources[] = {
+ [0] = {
+ .start = SDHC1_BASE_ADDR,
+ .end = SDHC1_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_SDHC1,
+ .end = MXC_INT_SDHC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*!
+ * Resource definition for the SDHC2
+ */
+static struct resource mxcsdhc2_resources[] = {
+ [0] = {
+ .start = SDHC2_BASE_ADDR,
+ .end = SDHC2_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_SDHC2,
+ .end = MXC_INT_SDHC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Device Definition for MXC SDHC1 */
+static struct platform_device mxcsdhc1_device = {
+ .name = "mxcmci",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mmc_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
+ .resource = mxcsdhc1_resources,
+};
+
+/*! Device Definition for MXC SDHC2 */
+static struct platform_device mxcsdhc2_device = {
+ .name = "mxcmci",
+ .id = 1,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mmc_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcsdhc2_resources),
+ .resource = mxcsdhc2_resources,
+};
+
+#ifdef CONFIG_MXC_SDHC3
+/*!
+ * Resource definition for the SDHC3
+ */
+static struct resource mxcsdhc3_resources[] = {
+ [0] = {
+ .start = SDHC3_BASE_ADDR,
+ .end = SDHC3_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_SDHC3,
+ .end = MXC_INT_SDHC3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = MXC_SDIO3_CARD_IRQ,
+ .end = MXC_SDIO3_CARD_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Device Definition for MXC SDHC3 */
+static struct platform_device mxcsdhc3_device = {
+ .name = "mxcmci",
+ .id = 2,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mmc_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcsdhc3_resources),
+ .resource = mxcsdhc3_resources,
+};
+#endif
+
+static inline void mxc_init_mmc(void)
+{
+ int cd_irq;
+
+ cd_irq = sdhc_init_card_det(0);
+ if (cd_irq) {
+ mxcsdhc1_device.resource[2].start = cd_irq;
+ mxcsdhc1_device.resource[2].end = cd_irq;
+ }
+ cd_irq = sdhc_init_card_det(1);
+ if (cd_irq) {
+ mxcsdhc2_device.resource[2].start = cd_irq;
+ mxcsdhc2_device.resource[2].end = cd_irq;
+ }
+
+ (void)platform_device_register(&mxcsdhc1_device);
+ (void)platform_device_register(&mxcsdhc2_device);
+#ifdef CONFIG_MXC_SDHC3
+ (void)platform_device_register(&mxcsdhc3_device);
+#endif
+}
+#else
+static inline void mxc_init_mmc(void)
+{
+}
+#endif
+
+/* SPI controller and device data */
+#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE)
+
+#ifdef CONFIG_SPI_MXC_SELECT1
+/*!
+ * Resource definition for the CSPI1
+ */
+static struct resource mxcspi1_resources[] = {
+ [0] = {
+ .start = CSPI1_BASE_ADDR,
+ .end = CSPI1_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_CSPI1,
+ .end = MXC_INT_CSPI1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Platform Data for MXC CSPI1 */
+static struct mxc_spi_master mxcspi1_data = {
+ .maxchipselect = 4,
+ .spi_version = 0,
+};
+
+/*! Device Definition for MXC CSPI1 */
+static struct platform_device mxcspi1_device = {
+ .name = "mxc_spi",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxcspi1_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcspi1_resources),
+ .resource = mxcspi1_resources,
+};
+
+#endif /* CONFIG_SPI_MXC_SELECT1 */
+
+#ifdef CONFIG_SPI_MXC_SELECT2
+/*!
+ * Resource definition for the CSPI2
+ */
+static struct resource mxcspi2_resources[] = {
+ [0] = {
+ .start = CSPI2_BASE_ADDR,
+ .end = CSPI2_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_CSPI2,
+ .end = MXC_INT_CSPI2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Platform Data for MXC CSPI2 */
+static struct mxc_spi_master mxcspi2_data = {
+ .maxchipselect = 4,
+ .spi_version = 0,
+};
+
+/*! Device Definition for MXC CSPI2 */
+static struct platform_device mxcspi2_device = {
+ .name = "mxc_spi",
+ .id = 1,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxcspi2_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcspi2_resources),
+ .resource = mxcspi2_resources,
+};
+#endif /* CONFIG_SPI_MXC_SELECT2 */
+
+#ifdef CONFIG_SPI_MXC_SELECT3
+/*!
+ * Resource definition for the CSPI3
+ */
+static struct resource mxcspi3_resources[] = {
+ [0] = {
+ .start = CSPI3_BASE_ADDR,
+ .end = CSPI3_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_CSPI3,
+ .end = MXC_INT_CSPI3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Platform Data for MXC CSPI3 */
+static struct mxc_spi_master mxcspi3_data = {
+ .maxchipselect = 4,
+ .spi_version = 0,
+};
+
+/*! Device Definition for MXC CSPI3 */
+static struct platform_device mxcspi3_device = {
+ .name = "mxc_spi",
+ .id = 2,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxcspi3_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcspi3_resources),
+ .resource = mxcspi3_resources,
+};
+#endif /* CONFIG_SPI_MXC_SELECT3 */
+
+static inline void mxc_init_spi(void)
+{
+#ifdef CONFIG_SPI_MXC_SELECT1
+ if (platform_device_register(&mxcspi1_device) < 0)
+ printk(KERN_ERR "Registering the SPI Controller_1\n");
+#endif /* CONFIG_SPI_MXC_SELECT1 */
+#ifdef CONFIG_SPI_MXC_SELECT2
+ if (platform_device_register(&mxcspi2_device) < 0)
+ printk(KERN_ERR "Registering the SPI Controller_2\n");
+#endif /* CONFIG_SPI_MXC_SELECT2 */
+#ifdef CONFIG_SPI_MXC_SELECT3
+ if (platform_device_register(&mxcspi3_device) < 0)
+ printk(KERN_ERR "Registering the SPI Controller_3\n");
+#endif /* CONFIG_SPI_MXC_SELECT3 */
+}
+#else
+static inline void mxc_init_spi(void)
+{
+}
+#endif
+
+#if defined(CONFIG_SND_MXC_PMIC) || defined(CONFIG_SND_MXC_PMIC_MODULE)
+static struct mxc_audio_platform_data mxc_audio_data;
+
+static struct platform_device mxc_alsa_device = {
+ .name = "mxc_alsa",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_audio_data,
+ },
+
+};
+
+static void mxc_init_audio(void)
+{
+ mxc_audio_data.ssi_clk[0] = clk_get(NULL, "ssi_clk.0");
+ clk_put(mxc_audio_data.ssi_clk[0]);
+ mxc_audio_data.ssi_clk[1] = clk_get(NULL, "ssi_clk.1");
+ clk_put(mxc_audio_data.ssi_clk[1]);
+ mxc_audio_data.ssi_num = 2;
+ mxc_audio_data.src_port = 0;
+ platform_device_register(&mxc_alsa_device);
+}
+#else
+
+static void mxc_init_audio(void)
+{
+}
+#endif
+
+#if defined(CONFIG_MXC_SSI) || defined(CONFIG_MXC_SSI_MODULE)
+/*!
+ * Resource definition for the SSI
+ */
+static struct resource mxcssi2_resources[] = {
+ [0] = {
+ .start = SSI2_BASE_ADDR,
+ .end = SSI2_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource mxcssi1_resources[] = {
+ [0] = {
+ .start = SSI1_BASE_ADDR,
+ .end = SSI1_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+/*! Device Definition for MXC SSI */
+static struct platform_device mxc_ssi1_device = {
+ .name = "mxc_ssi",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_audio_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcssi1_resources),
+ .resource = mxcssi1_resources,
+};
+
+static struct platform_device mxc_ssi2_device = {
+ .name = "mxc_ssi",
+ .id = 1,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_audio_data,
+ },
+ .num_resources = ARRAY_SIZE(mxcssi2_resources),
+ .resource = mxcssi2_resources,
+};
+
+static void mxc_init_ssi(void)
+{
+ platform_device_register(&mxc_ssi1_device);
+ platform_device_register(&mxc_ssi2_device);
+}
+#else
+
+static void mxc_init_ssi(void)
+{
+}
+#endif
+
+/* I2C controller and device data */
+#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE)
+
+#ifdef CONFIG_I2C_MXC_SELECT1
+/*!
+ * Resource definition for the I2C1
+ */
+static struct resource mxci2c1_resources[] = {
+ [0] = {
+ .start = I2C_BASE_ADDR,
+ .end = I2C_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_I2C,
+ .end = MXC_INT_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Platform Data for MXC I2C */
+static struct mxc_i2c_platform_data mxci2c1_data = {
+ .i2c_clk = 100000,
+};
+#endif
+
+#ifdef CONFIG_I2C_MXC_SELECT2
+/*!
+ * Resource definition for the I2C2
+ */
+static struct resource mxci2c2_resources[] = {
+ [0] = {
+ .start = I2C2_BASE_ADDR,
+ .end = I2C2_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_I2C2,
+ .end = MXC_INT_I2C2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*! Platform Data for MXC I2C */
+static struct mxc_i2c_platform_data mxci2c2_data = {
+ .i2c_clk = 100000,
+};
+#endif
+
+/*! Device Definition for MXC I2C */
+static struct platform_device mxci2c_devices[] = {
+#ifdef CONFIG_I2C_MXC_SELECT1
+ {
+ .name = "mxc_i2c",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxci2c1_data,
+ },
+ .num_resources = ARRAY_SIZE(mxci2c1_resources),
+ .resource = mxci2c1_resources,},
+#endif
+#ifdef CONFIG_I2C_MXC_SELECT2
+ {
+ .name = "mxc_i2c",
+ .id = 1,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxci2c2_data,
+ },
+ .num_resources = ARRAY_SIZE(mxci2c2_resources),
+ .resource = mxci2c2_resources,},
+#endif
+};
+
+static inline void mxc_init_i2c(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) {
+ if (platform_device_register(&mxci2c_devices[i]) < 0)
+ dev_err(&mxci2c_devices[i].dev,
+ "Unable to register I2C device\n");
+ }
+}
+#else
+static inline void mxc_init_i2c(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MXC_VPU
+/*! Platform Data for MXC VPU */
+static struct platform_device mxcvpu_device = {
+ .name = "mxc_vpu",
+ .dev = {
+ .release = mxc_nop_release,
+ },
+ .id = 0,
+};
+
+static inline void mxc_init_vpu(void)
+{
+ if (platform_device_register(&mxcvpu_device) < 0)
+ printk(KERN_ERR "Error: Registering the VPU.\n");
+}
+#else
+static inline void mxc_init_vpu(void)
+{
+}
+#endif
+
+struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = {
+ {
+ .num = 0,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR),
+ .irq = MXC_INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_INT_BASE,
+ },
+ {
+ .num = 1,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x100,
+ .irq = MXC_INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN,
+ },
+ {
+ .num = 2,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x200,
+ .irq = MXC_INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2,
+ },
+ {
+ .num = 3,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x300,
+ .irq = MXC_INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 3,
+ },
+ {
+ .num = 4,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x400,
+ .irq = MXC_INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 4,
+ },
+ {
+ .num = 5,
+ .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x500,
+ .irq = MXC_INT_GPIO,
+ .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 5,
+ },
+};
+
+#ifndef CONFIG_MX27_DPTC
+/*! Device Definition for DPTC */
+static struct platform_device mxc_dptc_device = {
+ .name = "mxc_dptc",
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &dptc_wp_allfreq,
+ },
+};
+
+static inline void mxc_init_dptc(void)
+{
+ (void)platform_device_register(&mxc_dptc_device);
+}
+#endif
+
+static int __init mxc_init_devices(void)
+{
+ mxc_init_wdt();
+ mxc_init_mmc();
+ mxc_init_spi();
+ mxc_init_i2c();
+ mxc_init_rtc();
+ mxc_init_ssi();
+ mxc_init_audio();
+ mxc_init_scc();
+ mxc_init_owire();
+ mxc_init_vpu();
+#ifndef CONFIG_MX27_DPTC
+ mxc_init_dptc();
+#endif
+
+ return 0;
+}
+
+arch_initcall(mxc_init_devices);
diff -urN linux-2.6.26/arch/arm/mach-mx27/dma.c linux-2.6.26-lab126/arch/arm/mach-mx27/dma.c
--- linux-2.6.26/arch/arm/mach-mx27/dma.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/dma.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,553 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ *@file mach-mx27/dma.c
+ *@brief This file contains the dma parameter which is depend on the platform .
+ * @ingroup DMA_MX27
+ */
+
+#include
+#include
+#include
+
+#define MXC_SOUND_PLAYBACK_CHAIN_DMA 1
+#define MXC_SOUND_CAPTURE_CHAIN_DMA 1
+
+/*!
+ * @brief the structure stored device_id and dma_info pointer
+ */
+typedef struct dma_info_entry_s {
+ mxc_dma_device_t device;
+ /* if there are two dma_info , first is for reading, another is for writing */
+ mx2_dma_info_t *info;
+} dma_info_entry_t;
+
+/*!
+ * @brief dma_info from memory to memory for dma testing
+ */
+static mx2_dma_info_t ram2ram_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 0
+};
+
+/*!
+ * @brief dma_info from 2D memory to 2D memory for dma testing
+ */
+static mx2_dma_info_t ram2d2ram2d_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .rto_en = 0,
+ .dma_chaining = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 1,.msel = 0,.W = 0x80,.X = 0x40,.Y = 0x10
+};
+
+/*!
+ * @brief dma_info from memory to 2D memory for dma testing
+ */
+static mx2_dma_info_t ram2ram2d_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x80,.Y = 0x10
+};
+
+/*!
+ * @brief dma_info from 2D memory to memory for dma testing
+ */
+static mx2_dma_info_t ram2d2ram_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x100,.Y = 0x10
+};
+
+/*!
+ * @brief dma_info with dma chaining feature for dma testing
+ */
+static mx2_dma_info_t hw_chaining_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 1,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info without dma chaining feature for dma testing
+ */
+static mx2_dma_info_t sw_chaining_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 0,
+ .burstLength = 4,.request = 0,.busuntils = 0,
+ .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for ATA recieveing
+ */
+static mx2_dma_info_t ata_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 32,.request = 29,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .per_address = (ATA_BASE_ADDR + 0x18),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for ATA transmitting
+ */
+static mx2_dma_info_t ata_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 32,.request = 28,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_32BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT,
+ .per_address = (ATA_BASE_ADDR + 0x18),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART1 recieveing
+ */
+static mx2_dma_info_t uart1_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 1,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 26,.busuntils = 8,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART1_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART1 transmitting
+ */
+static mx2_dma_info_t uart1_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 27,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART1_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART2 recieveing
+ */
+static mx2_dma_info_t uart2_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 24,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART2_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART2 transmitting
+ */
+static mx2_dma_info_t uart2_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 25,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART2_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART3 recieveing
+ */
+static mx2_dma_info_t uart3_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 22,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART3_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART3 transmitting
+ */
+static mx2_dma_info_t uart3_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 23,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART3_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART4 recieveing
+ */
+static mx2_dma_info_t uart4_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 20,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART4_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART4transmitting
+ */
+static mx2_dma_info_t uart4_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 21,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART4_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART5 recieveing
+ */
+static mx2_dma_info_t uart5_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 32,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART5_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART5 transmitting
+ */
+static mx2_dma_info_t uart5_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 33,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART5_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma_info for UART6 recieveing
+ */
+static mx2_dma_info_t uart6_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 34,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART6_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief: dma_info for UART6 transmitting
+ */
+static mx2_dma_info_t uart6_tx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 1,.request = 35,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT,
+ .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT,
+ .per_address = (UART6_BASE_ADDR + 0x40),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi1_16bit_rx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = MXC_SOUND_CAPTURE_CHAIN_DMA,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI1_RX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SSI1_BASE_ADDR + 0x08),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi1_16bit_tx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = MXC_SOUND_PLAYBACK_CHAIN_DMA,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI1_TX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SSI1_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi2_16bit_rx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = MXC_SOUND_CAPTURE_CHAIN_DMA,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI2_RX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SSI2_BASE_ADDR + 0x08),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t ssi2_16bit_tx0_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 1,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = MXC_SOUND_PLAYBACK_CHAIN_DMA,.ren = 1,
+ .burstLength = 8,.request = DMA_REQ_SSI2_TX0,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SSI2_BASE_ADDR),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc1_width1_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 16,.request = DMA_REQ_SDHC1,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC1_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc1_width4_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 0,.request = DMA_REQ_SDHC1,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC1_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc2_width1_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 16,.request = DMA_REQ_SDHC2,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC2_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t mmc2_width4_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 0,.ren = 1,
+ .burstLength = 0,.request = DMA_REQ_SDHC2,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (SDHC2_BASE_ADDR + 0x38),
+ .M2D_Valid = 0,
+};
+
+static mx2_dma_info_t csi_rx_dma_info = {
+ .dma_chan = MXC_DMA_DYNAMIC_CHANNEL,
+ .mode = 0,
+ .rto_en = 0,
+ .dir = 0,
+ .dma_chaining = 1,.ren = 1,
+ .burstLength = 64,.request = DMA_REQ_CSI_RX,.busuntils = 0,
+ .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32,
+ .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32,
+ .per_address = (CSI_BASE_ADDR + 0x10),
+ .M2D_Valid = 0,
+};
+
+/*!
+ * @brief dma info array which is actived
+ * DEVICE_ID RX/(RX&TX) TX
+ */
+static dma_info_entry_t active_dma_info[] = {
+ {MXC_DMA_TEST_RAM2RAM, &ram2ram_dma_info},
+ {MXC_DMA_TEST_RAM2D2RAM2D, &ram2d2ram2d_dma_info},
+ {MXC_DMA_TEST_RAM2RAM2D, &ram2ram2d_dma_info},
+ {MXC_DMA_TEST_RAM2D2RAM, &ram2d2ram_dma_info},
+ {MXC_DMA_TEST_HW_CHAINING, &hw_chaining_dma_info},
+ {MXC_DMA_TEST_SW_CHAINING, &sw_chaining_dma_info},
+ {MXC_DMA_ATA_RX, &ata_rx_dma_info},
+ {MXC_DMA_ATA_TX, &ata_tx_dma_info},
+ {MXC_DMA_UART1_RX, &uart1_rx_dma_info},
+ {MXC_DMA_UART1_TX, &uart1_tx_dma_info},
+ {MXC_DMA_UART2_RX, &uart2_rx_dma_info},
+ {MXC_DMA_UART2_TX, &uart2_tx_dma_info},
+ {MXC_DMA_UART3_RX, &uart3_rx_dma_info},
+ {MXC_DMA_UART3_TX, &uart3_tx_dma_info},
+ {MXC_DMA_UART4_RX, &uart4_rx_dma_info},
+ {MXC_DMA_UART4_TX, &uart4_tx_dma_info},
+ {MXC_DMA_UART5_RX, &uart5_rx_dma_info},
+ {MXC_DMA_UART5_TX, &uart5_tx_dma_info},
+ {MXC_DMA_UART6_RX, &uart6_rx_dma_info},
+ {MXC_DMA_UART6_TX, &uart6_tx_dma_info},
+ {MXC_DMA_SSI1_16BIT_RX0, &ssi1_16bit_rx0_dma_info},
+ {MXC_DMA_SSI1_16BIT_TX0, &ssi1_16bit_tx0_dma_info},
+ {MXC_DMA_SSI2_16BIT_RX0, &ssi2_16bit_rx0_dma_info},
+ {MXC_DMA_SSI2_16BIT_TX0, &ssi2_16bit_tx0_dma_info},
+ {MXC_DMA_MMC1_WIDTH_1, &mmc1_width1_dma_info},
+ {MXC_DMA_MMC1_WIDTH_4, &mmc1_width4_dma_info},
+ {MXC_DMA_MMC2_WIDTH_1, &mmc2_width1_dma_info},
+ {MXC_DMA_MMC2_WIDTH_4, &mmc2_width4_dma_info},
+ {MXC_DMA_CSI_RX, &csi_rx_dma_info},
+};
+
+/*!
+ * @brief the number of actived dma info
+ */
+static int dma_info_entrys =
+ sizeof(active_dma_info) / sizeof(active_dma_info[0]);
+
+/*!
+ * @brief get the dma info by channel_id
+ */
+mx2_dma_info_t *mxc_dma_get_info(mxc_dma_device_t channel_id)
+{
+ dma_info_entry_t *p = active_dma_info;
+ int i;
+ for (i = 0; i < dma_info_entrys; i++, p++) {
+ if (p->device == channel_id)
+ return p->info;
+ }
+ return NULL;
+}
+
+/*!
+ * @brief: scan dma parameter list . And collect information about which channels are dynamic .
+ */
+void mxc_dma_load_info(mxc_dma_channel_t * dma)
+{
+ int i, idx;
+ dma_info_entry_t *p = active_dma_info;
+
+ BUG_ON(dma == NULL);
+ BUG_ON(p == NULL);
+
+ for (i = 0; i < MXC_DMA_CHANNELS; i++) {
+ dma[i].dynamic = 1;
+ }
+
+ for (i = 0; i < dma_info_entrys; i++, p++) {
+ BUG_ON((p->info == NULL));
+
+ idx = p->info->dma_chan;
+
+ BUG_ON(((idx >= MAX_DMA_CHANNELS)
+ && (idx != MXC_DMA_DYNAMIC_CHANNEL)));
+ if ((idx < 0) || (idx == MXC_DMA_DYNAMIC_CHANNEL))
+ continue;
+ dma[idx].dynamic = 0;
+ }
+}
+
+EXPORT_SYMBOL(mxc_dma_get_info);
+EXPORT_SYMBOL(mxc_dma_load_info);
diff -urN linux-2.6.26/arch/arm/mach-mx27/dptc.c linux-2.6.26-lab126/arch/arm/mach-mx27/dptc.c
--- linux-2.6.26/arch/arm/mach-mx27/dptc.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/dptc.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file dptc.c
+ *
+ * @brief DPTC table for the Freescale Semiconductor MXC DPTC module.
+ *
+ * @ingroup PM
+ */
+
+#include
+#include
+
+struct dptc_wp dptc_wp_allfreq[DPTC_WP_SUPPORTED] = {
+ /* 532MHz */
+ /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */
+ /* wp0 */
+ {0xffe00000, 0x18e2e85b, 0xffe00000, 0x25c4688a, 1600},
+ {0xffe00000, 0x18e2e85b, 0xffe00000, 0x25c4688a, 1575},
+ {0xffe00000, 0x1902e85b, 0xffe00000, 0x25e4688a, 1550},
+ {0xffe00000, 0x1922e85b, 0xffe00000, 0x25e4688a, 1525},
+ {0xffe00000, 0x1942ec5b, 0xffe00000, 0x2604688a, 1500},
+ /* wp5 */
+ {0xffe00000, 0x1942ec5b, 0xffe00000, 0x26646c8a, 1475},
+ {0xffe00000, 0x1962ec5b, 0xffe00000, 0x26c4708b, 1450},
+ {0xffe00000, 0x1962ec5b, 0xffe00000, 0x26e4708b, 1425},
+ {0xffe00000, 0x1982f05c, 0xffe00000, 0x2704748b, 1400},
+ {0xffe00000, 0x19c2f05c, 0xffe00000, 0x2744748b, 1375},
+ /* wp10 */
+ {0xffe00000, 0x1a02f45c, 0xffe00000, 0x2784788b, 1350},
+ {0xffe00000, 0x1a42f45c, 0xffe00000, 0x27c47c8b, 1325},
+ {0xffe00000, 0x1a82f85c, 0xffe00000, 0x2824808c, 1300},
+ {0xffe00000, 0x1aa2f85c, 0xffe00000, 0x2884848c, 1275},
+ {0xffe00000, 0x1ac2fc5c, 0xffe00000, 0x28e4888c, 1250},
+ /* wp15 */
+ {0xffe00000, 0x1ae2fc5c, 0xffe00000, 0x2924888c, 1225},
+ {0xffe00000, 0x1b23005d, 0xffe00000, 0x29648c8c, 1200},
+};
diff -urN linux-2.6.26/arch/arm/mach-mx27/gpio_mux.c linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.c
--- linux-2.6.26/arch/arm/mach-mx27/gpio_mux.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,308 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup GPIO_MX27 Board GPIO and Muxing Setup
+ * @ingroup MSL_MX27
+ */
+/*!
+ * @file mach-mx27/gpio_mux.c
+ *
+ * @brief I/O Muxing control functions
+ *
+ * @ingroup GPIO_MX27
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include "gpio_mux.h"
+
+/*!
+ * This structure defines the offset of registers in gpio module.
+ */
+enum gpio_reg {
+ GPIO_GIUS = 0x20,
+ GPIO_GPR = 0x38,
+ GPIO_PUEN = 0x40,
+ GPIO_DDIR = 0x00,
+ GPIO_OCR1 = 0x04,
+ GPIO_OCR2 = 0x08,
+ GPIO_ICONFA1 = 0x0C,
+ GPIO_ICONFA2 = 0x10,
+ GPIO_ICONFB1 = 0x14,
+ GPIO_ICONFB2 = 0x18,
+};
+
+/*!
+ * This enumeration data type defines the configuration for input mode.
+ */
+typedef enum {
+ GPIO_INPUT_GPIO = 0x00,
+ GPIO_INPUT_INTR = 0x01,
+ GPIO_INPUT_LOW = 0x02,
+ GPIO_INPUT_HIGH = 0x03
+} gpio_input_cfg_t;
+
+/*!
+ * This enumeration data type defines the configuration for output mode.
+ */
+typedef enum {
+ GPIO_OUTPUT_A = 0x00,
+ GPIO_OUTPUT_B = 0x01,
+ GPIO_OUTPUT_C = 0x02,
+ GPIO_OUTPUT_DR = 0x03
+} gpio_output_cfg_t;
+
+extern struct mxc_gpio_port mxc_gpio_ports[];
+
+/*!
+ * defines a spinlock to protected the accessing to gpio pin.
+ */
+DEFINE_SPINLOCK(gpio_mux_lock);
+
+/*!
+ * This function enable or disable the pullup feature to the pin.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param en 0 if disable pullup, otherwise enable it.
+ * @return none
+ */
+static inline void _gpio_set_puen(struct mxc_gpio_port *port, u32 index,
+ bool en)
+{
+ u32 reg;
+
+ reg = __raw_readl(port->base + GPIO_PUEN);
+ if (en) {
+ reg |= 1 << index;
+ } else {
+ reg &= ~(1 << index);
+ }
+ __raw_writel(reg, port->base + GPIO_PUEN);
+}
+
+/*!
+ * This function set the input configuration A.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param config a mode as define in \b #gpio_input_cfg_t
+ * @return none
+ */
+static inline void _gpio_set_iconfa(struct mxc_gpio_port *port, u32 index,
+ gpio_input_cfg_t config)
+{
+ u32 reg, val;
+ u32 mask;
+
+ mask = 0x3 << ((index % 16) << 1);
+
+ if (index >= 16) {
+ reg = port->base + GPIO_ICONFA2;
+ val = config << ((index - 16) * 2);
+ } else {
+ reg = port->base + GPIO_ICONFA1;
+ val = config << (index * 2);
+ }
+ val |= __raw_readl(reg) & ~(mask);
+ __raw_writel(val, reg);
+}
+
+/*!
+ * This function set the input configuration B.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param config a mode as define in \b #gpio_input_cfg_t
+ * @return none
+ */
+static inline void _gpio_set_iconfb(struct mxc_gpio_port *port, u32 index,
+ gpio_input_cfg_t config)
+{
+ u32 reg, val;
+ u32 mask;
+
+ mask = 0x3 << ((index % 16) << 1);
+
+ if (index >= 16) {
+ reg = port->base + GPIO_ICONFB2;
+ val = config << ((index - 16) * 2);
+ } else {
+ reg = port->base + GPIO_ICONFB1;
+ val = config << (index * 2);
+ }
+ val |= __raw_readl(reg) & (~mask);
+ __raw_writel(val, reg);
+}
+
+/*!
+ * This function set the output configuration.
+ * @param port a pointer of gpio port
+ * @param index the index of the pin in the port
+ * @param config a mode as define in \b #gpio_output_cfg_t
+ * @return none
+ */
+static inline void _gpio_set_ocr(struct mxc_gpio_port *port, u32 index,
+ gpio_output_cfg_t config)
+{
+ u32 reg, val;
+ u32 mask;
+
+ mask = 0x3 << ((index % 16) << 1);
+ if (index >= 16) {
+ reg = port->base + GPIO_OCR2;
+ val = config << ((index - 16) * 2);
+ } else {
+ reg = port->base + GPIO_OCR1;
+ val = config << (index * 2);
+ }
+ val |= __raw_readl(reg) & (~mask);
+ __raw_writel(val, reg);
+}
+
+/*!
+ *@brief gpio_config_mux - just configure the mode of the gpio pin.
+ *@param pin a pin number as defined in \b #iomux_pin_name_t
+ *@param mode a module as define in \b #gpio_mux_mode_t;
+ * GPIO_MUX_PRIMARY set pin to work as primary function.
+ * GPIO_MUX_ALT set pin to work as alternate function.
+ * GPIO_MUX_GPIO set pin to work as output function based the data register
+ * GPIO_MUX_INPUT1 set pin to work as input function connected with A_OUT
+ * GPIO_MUX_INPUT2 set pin to work as input function connected with B_OUT
+ * GPIO_MUX_OUTPUT1 set pin to work as output function connected with A_IN
+ * GPIO_MUX_OUTPUT2 set pin to work as output function connected with B_IN
+ * GPIO_MUX_OUTPUT3 set pin to work as output function connected with C_IN
+ *@return 0 if successful, Non-zero otherwise
+ */
+
+int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode)
+{
+ unsigned long lock_flags;
+ u32 gius_reg, gpr_reg;
+ struct mxc_gpio_port *port;
+ u32 index, gpio = IOMUX_TO_GPIO(pin);
+
+ port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]);
+ index = GPIO_TO_INDEX(gpio);
+
+ pr_debug("%s: Configuring PORT %c, bit %d\n",
+ __FUNCTION__, port->num + 'A', index);
+
+ spin_lock_irqsave(&gpio_mux_lock, lock_flags);
+
+ gius_reg = __raw_readl(port->base + GPIO_GIUS);
+ gpr_reg = __raw_readl(port->base + GPIO_GPR);
+
+ switch (mode) {
+ case GPIO_MUX_PRIMARY:
+ gius_reg &= ~(1L << index);
+ gpr_reg &= ~(1L << index);
+ break;
+ case GPIO_MUX_ALT:
+ gius_reg &= ~(1L << index);
+ gpr_reg |= (1L << index);
+ break;
+ case GPIO_MUX_GPIO:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_DR);
+ break;
+ case GPIO_MUX_INPUT1:
+ gius_reg |= (1L << index);
+ _gpio_set_iconfa(port, index, GPIO_INPUT_GPIO);
+ break;
+ case GPIO_MUX_INPUT2:
+ gius_reg |= (1L << index);
+ _gpio_set_iconfb(port, index, GPIO_INPUT_GPIO);
+ break;
+ case GPIO_MUX_OUTPUT1:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_A);
+ break;
+ case GPIO_MUX_OUTPUT2:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_B);
+ break;
+ case GPIO_MUX_OUTPUT3:
+ gius_reg |= (1L << index);
+ _gpio_set_ocr(port, index, GPIO_OUTPUT_C);
+ break;
+ default:
+ spin_unlock_irqrestore(&gpio_mux_lock, lock_flags);
+ return -1;
+ }
+
+ __raw_writel(gius_reg, port->base + GPIO_GIUS);
+ __raw_writel(gpr_reg, port->base + GPIO_GPR);
+
+ spin_unlock_irqrestore(&gpio_mux_lock, lock_flags);
+ return 0;
+}
+
+/*!
+ * This function is just used to enable or disable the pull up feature .
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param en 0 if disable, Non-zero enable
+ * @return 0 if successful, Non-zero otherwise
+ */
+int gpio_set_puen(iomux_pin_name_t pin, bool en)
+{
+ unsigned long lock_flags;
+
+ struct mxc_gpio_port *port;
+ u32 index, gpio = IOMUX_TO_GPIO(pin);
+
+ port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]);
+ index = GPIO_TO_INDEX(gpio);
+
+ pr_debug("%s: Configuring output mode of PORT %c, bit %d\n",
+ __FUNCTION__, port->num + 'A', index);
+
+ spin_lock_irqsave(&gpio_mux_lock, lock_flags);
+
+ _gpio_set_puen(port, index, en);
+ spin_unlock_irqrestore(&gpio_mux_lock, lock_flags);
+ return 0;
+
+}
+
+/*!
+ * This function is just used to request a pin and configure it.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param mode a module as define in \b #gpio_mux_mode_t;
+ * @return 0 if successful, Non-zero otherwise
+ */
+int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode)
+{
+ int ret;
+ ret = mxc_request_gpio(pin);
+ if (ret == 0) {
+ ret = gpio_config_mux(pin, mode);
+ if (ret) {
+ mxc_free_gpio(pin);
+ }
+ }
+ return ret;
+}
+
+/*!
+ * This function is just used to release a pin.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @return none
+ */
+void gpio_free_mux(iomux_pin_name_t pin)
+{
+ mxc_free_gpio(pin);
+}
diff -urN linux-2.6.26/arch/arm/mach-mx27/gpio_mux.h linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.h
--- linux-2.6.26/arch/arm/mach-mx27/gpio_mux.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ *@file mach-mx27/gpio_mux.h
+ *@brief This file contains the private definition .
+ * @ingroup GPIO_MX27
+ */
+
+#ifndef __ARCH_ARM_MACH_MX27_GPIO_MUX_H__
+#define __ARCH_ARM_MACH_MX27_GPIO_MUX_H__
+
+#include "mx27_pins.h"
+
+/*!
+ * This enumeration data type defines the modes of the pin .
+ * GPIO_MUX_PRIMARY is the primary mode.
+ * GPIO_MUX_ALT is the alternate mode.
+ * GPIO_MUX_GPIO is the output mode and the signal source is data register.
+ * GPIO_MUX_INPUT1 is the input mode and the signal destination is A_OUT.
+ * GPIO_MUX_INPUT2 is the input mode and the signal destination is B_OUT.
+ * GPIO_MUX_OUTPUT1 is the output mode and the signal destination is A_IN.
+ * GPIO_MUX_OUTPUT2 is the output mode and the signal destination is B_IN.
+ * GPIO_MUX_OUTPUT3 is the output mode and the signal destination is C_IN.
+ */
+typedef enum {
+ GPIO_MUX_PRIMARY,
+ GPIO_MUX_ALT,
+ GPIO_MUX_GPIO,
+ GPIO_MUX_INPUT1,
+ GPIO_MUX_INPUT2,
+ GPIO_MUX_OUTPUT1,
+ GPIO_MUX_OUTPUT2,
+ GPIO_MUX_OUTPUT3,
+} gpio_mux_mode_t;
+
+/*!
+ * This function is just used to request a pin and configure it.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param mode a module as define in \b #gpio_mux_mode_t;
+ * @return 0 if successful, Non-zero otherwise
+ */
+extern int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
+
+/*!
+ * This function is just used to configure a pin .
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param mode a module as define in \b #gpio_mux_mode_t;
+ * @return 0 if successful, Non-zero otherwise
+ */
+extern int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
+
+/*!
+ * This function is just used to enable or disable the pull up feature .
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param en 0 if disable, Non-zero enable
+ * @return 0 if successful, Non-zero otherwise
+ */
+extern int gpio_set_puen(iomux_pin_name_t pin, bool en);
+
+/*!
+ * This function is just used to release a pin.
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @return none
+ */
+extern void gpio_free_mux(iomux_pin_name_t pin);
+
+#endif /* __ARCH_ARM_MACH_MX27_GPIO_MUX_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx27/mm.c linux-2.6.26-lab126/arch/arm/mach-mx27/mm.c
--- linux-2.6.26/arch/arm/mach-mx27/mm.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/mm.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/*!
+ * @file mach-mx27/mm.c
+ *
+ * @brief This file creates static mapping between physical to virtual memory.
+ *
+ * @ingroup Memory_MX27
+ */
+
+/*!
+ * This structure defines the MX27 memory map.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+ {
+ .virtual = AIPI_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(AIPI_BASE_ADDR),
+ .length = AIPI_SIZE,
+ .type = MT_DEVICE},
+ {
+ .virtual = SAHB1_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(SAHB1_BASE_ADDR),
+ .length = SAHB1_SIZE,
+ .type = MT_DEVICE},
+ {
+ .virtual = X_MEMC_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
+ .length = X_MEMC_SIZE,
+ .type = MT_DEVICE},
+ {
+ .virtual = CS4_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(CS4_BASE_ADDR),
+ .length = CS4_SIZE,
+ .type = MT_DEVICE}
+};
+
+/*!
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory map for
+ * the IO modules.
+ */
+void __init mxc_map_io(void)
+{
+ iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff -urN linux-2.6.26/arch/arm/mach-mx27/mx27_pins.h linux-2.6.26-lab126/arch/arm/mach-mx27/mx27_pins.h
--- linux-2.6.26/arch/arm/mach-mx27/mx27_pins.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/mx27_pins.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_MX27_PINS_H__
+#define __ASM_ARCH_MXC_MX27_PINS_H__
+
+/*!
+ * @file arch-mxc/mx27_pins.h
+ *
+ * @brief MX27 I/O Pin List
+ *
+ * @ingroup GPIO_MX27
+ */
+
+#ifndef __ASSEMBLY__
+
+#define _MX27_BUILD_PIN(gp,gi) (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I))
+
+enum iomux_pins {
+ MX27_PIN_USBH2_CLK = _MX27_BUILD_PIN(0, 0),
+ MX27_PIN_USBH2_DIR = _MX27_BUILD_PIN(0, 1),
+ MX27_PIN_USBH2_DATA7 = _MX27_BUILD_PIN(0, 2),
+ MX27_PIN_USBH2_NXT = _MX27_BUILD_PIN(0, 3),
+ MX27_PIN_USBH2_STP = _MX27_BUILD_PIN(0, 4),
+ MX27_PIN_LSCLK = _MX27_BUILD_PIN(0, 5),
+ MX27_PIN_LD0 = _MX27_BUILD_PIN(0, 6),
+ MX27_PIN_LD1 = _MX27_BUILD_PIN(0, 7),
+ MX27_PIN_LD2 = _MX27_BUILD_PIN(0, 8),
+ MX27_PIN_LD3 = _MX27_BUILD_PIN(0, 9),
+ MX27_PIN_LD4 = _MX27_BUILD_PIN(0, 10),
+ MX27_PIN_LD5 = _MX27_BUILD_PIN(0, 11),
+ MX27_PIN_LD6 = _MX27_BUILD_PIN(0, 12),
+ MX27_PIN_LD7 = _MX27_BUILD_PIN(0, 13),
+ MX27_PIN_LD8 = _MX27_BUILD_PIN(0, 14),
+ MX27_PIN_LD9 = _MX27_BUILD_PIN(0, 15),
+ MX27_PIN_LD10 = _MX27_BUILD_PIN(0, 16),
+ MX27_PIN_LD11 = _MX27_BUILD_PIN(0, 17),
+ MX27_PIN_LD12 = _MX27_BUILD_PIN(0, 18),
+ MX27_PIN_LD13 = _MX27_BUILD_PIN(0, 19),
+ MX27_PIN_LD14 = _MX27_BUILD_PIN(0, 20),
+ MX27_PIN_LD15 = _MX27_BUILD_PIN(0, 21),
+ MX27_PIN_LD16 = _MX27_BUILD_PIN(0, 22),
+ MX27_PIN_LD17 = _MX27_BUILD_PIN(0, 23),
+ MX27_PIN_REV = _MX27_BUILD_PIN(0, 24),
+ MX27_PIN_CLS = _MX27_BUILD_PIN(0, 25),
+ MX27_PIN_PS = _MX27_BUILD_PIN(0, 26),
+ MX27_PIN_SPL_SPR = _MX27_BUILD_PIN(0, 27),
+ MX27_PIN_HSYNC = _MX27_BUILD_PIN(0, 28),
+ MX27_PIN_VSYNC = _MX27_BUILD_PIN(0, 29),
+ MX27_PIN_CONTRAST = _MX27_BUILD_PIN(0, 30),
+ MX27_PIN_OE_ACD = _MX27_BUILD_PIN(0, 31),
+
+ MX27_PIN_SD2_D0 = _MX27_BUILD_PIN(1, 4),
+ MX27_PIN_SD2_D1 = _MX27_BUILD_PIN(1, 5),
+ MX27_PIN_SD2_D2 = _MX27_BUILD_PIN(1, 6),
+ MX27_PIN_SD2_D3 = _MX27_BUILD_PIN(1, 7),
+ MX27_PIN_SD2_CMD = _MX27_BUILD_PIN(1, 8),
+ MX27_PIN_SD2_CLK = _MX27_BUILD_PIN(1, 9),
+ MX27_PIN_CSI_D0 = _MX27_BUILD_PIN(1, 10),
+ MX27_PIN_CSI_D1 = _MX27_BUILD_PIN(1, 11),
+ MX27_PIN_CSI_D2 = _MX27_BUILD_PIN(1, 12),
+ MX27_PIN_CSI_D3 = _MX27_BUILD_PIN(1, 13),
+ MX27_PIN_CSI_D4 = _MX27_BUILD_PIN(1, 14),
+ MX27_PIN_CSI_MCLK = _MX27_BUILD_PIN(1, 15),
+ MX27_PIN_CSI_PIXCLK = _MX27_BUILD_PIN(1, 16),
+ MX27_PIN_CSI_D5 = _MX27_BUILD_PIN(1, 17),
+ MX27_PIN_CSI_D6 = _MX27_BUILD_PIN(1, 18),
+ MX27_PIN_CSI_D7 = _MX27_BUILD_PIN(1, 19),
+ MX27_PIN_CSI_VSYNC = _MX27_BUILD_PIN(1, 20),
+ MX27_PIN_CSI_HSYNC = _MX27_BUILD_PIN(1, 21),
+ MX27_PIN_USBH1_SUSP = _MX27_BUILD_PIN(1, 22),
+ MX27_PIN_USB_PWR = _MX27_BUILD_PIN(1, 23),
+ MX27_PIN_USB_OC_B = _MX27_BUILD_PIN(1, 24),
+ MX27_PIN_USBH1_RCV = _MX27_BUILD_PIN(1, 25),
+ MX27_PIN_USBH1_FS = _MX27_BUILD_PIN(1, 26),
+ MX27_PIN_USBH1_OE_B = _MX27_BUILD_PIN(1, 27),
+ MX27_PIN_USBH1_TXDM = _MX27_BUILD_PIN(1, 28),
+ MX27_PIN_USBH1_TXDP = _MX27_BUILD_PIN(1, 29),
+ MX27_PIN_USBH1_RXDM = _MX27_BUILD_PIN(1, 30),
+ MX27_PIN_USBH1_RXDP = _MX27_BUILD_PIN(1, 31),
+
+ MX27_PIN_I2C2_SDA = _MX27_BUILD_PIN(2, 5),
+ MX27_PIN_I2C2_SCL = _MX27_BUILD_PIN(2, 6),
+ MX27_PIN_USBOTG_DATA5 = _MX27_BUILD_PIN(2, 7),
+ MX27_PIN_USBOTG_DATA6 = _MX27_BUILD_PIN(2, 8),
+ MX27_PIN_USBOTG_DATA0 = _MX27_BUILD_PIN(2, 9),
+ MX27_PIN_USBOTG_DATA2 = _MX27_BUILD_PIN(2, 10),
+ MX27_PIN_USBOTG_DATA1 = _MX27_BUILD_PIN(2, 11),
+ MX27_PIN_USBOTG_DATA4 = _MX27_BUILD_PIN(2, 12),
+ MX27_PIN_USBOTG_DATA3 = _MX27_BUILD_PIN(2, 13),
+ MX27_PIN_TOUT = _MX27_BUILD_PIN(2, 14),
+ MX27_PIN_TIN = _MX27_BUILD_PIN(2, 15),
+ MX27_PIN_SSI4_FS = _MX27_BUILD_PIN(2, 16),
+ MX27_PIN_SSI4_RXDAT = _MX27_BUILD_PIN(2, 17),
+ MX27_PIN_SSI4_TXDAT = _MX27_BUILD_PIN(2, 18),
+ MX27_PIN_SSI4_CLK = _MX27_BUILD_PIN(2, 19),
+ MX27_PIN_SSI1_FS = _MX27_BUILD_PIN(2, 20),
+ MX27_PIN_SSI1_RXDAT = _MX27_BUILD_PIN(2, 21),
+ MX27_PIN_SSI1_TXDAT = _MX27_BUILD_PIN(2, 22),
+ MX27_PIN_SSI1_CLK = _MX27_BUILD_PIN(2, 23),
+ MX27_PIN_SSI2_FS = _MX27_BUILD_PIN(2, 24),
+ MX27_PIN_SSI2_RXDAT = _MX27_BUILD_PIN(2, 25),
+ MX27_PIN_SSI2_TXDAT = _MX27_BUILD_PIN(2, 26),
+ MX27_PIN_SSI2_CLK = _MX27_BUILD_PIN(2, 27),
+ MX27_PIN_SSI3_FS = _MX27_BUILD_PIN(2, 28),
+ MX27_PIN_SSI3_RXDAT = _MX27_BUILD_PIN(2, 29),
+ MX27_PIN_SSI3_TXDAT = _MX27_BUILD_PIN(2, 30),
+ MX27_PIN_SSI3_CLK = _MX27_BUILD_PIN(2, 31),
+
+ MX27_PIN_SD3_CMD = _MX27_BUILD_PIN(3, 0),
+ MX27_PIN_SD3_CLK = _MX27_BUILD_PIN(3, 1),
+ MX27_PIN_ATA_DATA0 = _MX27_BUILD_PIN(3, 2),
+ MX27_PIN_ATA_DATA1 = _MX27_BUILD_PIN(3, 3),
+ MX27_PIN_ATA_DATA2 = _MX27_BUILD_PIN(3, 4),
+ MX27_PIN_ATA_DATA3 = _MX27_BUILD_PIN(3, 5),
+ MX27_PIN_ATA_DATA4 = _MX27_BUILD_PIN(3, 6),
+ MX27_PIN_ATA_DATA5 = _MX27_BUILD_PIN(3, 7),
+ MX27_PIN_ATA_DATA6 = _MX27_BUILD_PIN(3, 8),
+ MX27_PIN_ATA_DATA7 = _MX27_BUILD_PIN(3, 9),
+ MX27_PIN_ATA_DATA8 = _MX27_BUILD_PIN(3, 10),
+ MX27_PIN_ATA_DATA9 = _MX27_BUILD_PIN(3, 11),
+ MX27_PIN_ATA_DATA10 = _MX27_BUILD_PIN(3, 12),
+ MX27_PIN_ATA_DATA11 = _MX27_BUILD_PIN(3, 13),
+ MX27_PIN_ATA_DATA12 = _MX27_BUILD_PIN(3, 14),
+ MX27_PIN_ATA_DATA13 = _MX27_BUILD_PIN(3, 15),
+ MX27_PIN_ATA_DATA14 = _MX27_BUILD_PIN(3, 16),
+ MX27_PIN_I2C_DATA = _MX27_BUILD_PIN(3, 17),
+ MX27_PIN_I2C_CLK = _MX27_BUILD_PIN(3, 18),
+ MX27_PIN_CSPI2_SS2 = _MX27_BUILD_PIN(3, 19),
+ MX27_PIN_CSPI2_SS1 = _MX27_BUILD_PIN(3, 20),
+ MX27_PIN_CSPI2_SS0 = _MX27_BUILD_PIN(3, 21),
+ MX27_PIN_CSPI2_SCLK = _MX27_BUILD_PIN(3, 22),
+ MX27_PIN_CSPI2_MISO = _MX27_BUILD_PIN(3, 23),
+ MX27_PIN_CSPI2_MOSI = _MX27_BUILD_PIN(3, 24),
+ MX27_PIN_CSPI1_RDY = _MX27_BUILD_PIN(3, 25),
+ MX27_PIN_CSPI1_SS2 = _MX27_BUILD_PIN(3, 26),
+ MX27_PIN_CSPI1_SS1 = _MX27_BUILD_PIN(3, 27),
+ MX27_PIN_CSPI1_SS0 = _MX27_BUILD_PIN(3, 28),
+ MX27_PIN_CSPI1_SCLK = _MX27_BUILD_PIN(3, 29),
+ MX27_PIN_CSPI1_MISO = _MX27_BUILD_PIN(3, 30),
+ MX27_PIN_CSPI1_MOSI = _MX27_BUILD_PIN(3, 31),
+
+ MX27_PIN_USBOTG_NXT = _MX27_BUILD_PIN(4, 0),
+ MX27_PIN_USBOTG_STP = _MX27_BUILD_PIN(4, 1),
+ MX27_PIN_USBOTG_DIR = _MX27_BUILD_PIN(4, 2),
+ MX27_PIN_UART2_CTS = _MX27_BUILD_PIN(4, 3),
+ MX27_PIN_UART2_RTS = _MX27_BUILD_PIN(4, 4),
+ MX27_PIN_PWMO = _MX27_BUILD_PIN(4, 5),
+ MX27_PIN_UART2_TXD = _MX27_BUILD_PIN(4, 6),
+ MX27_PIN_UART2_RXD = _MX27_BUILD_PIN(4, 7),
+ MX27_PIN_UART3_TXD = _MX27_BUILD_PIN(4, 8),
+ MX27_PIN_UART3_RXD = _MX27_BUILD_PIN(4, 9),
+ MX27_PIN_UART3_CTS = _MX27_BUILD_PIN(4, 10),
+ MX27_PIN_UART3_RTS = _MX27_BUILD_PIN(4, 11),
+ MX27_PIN_UART1_TXD = _MX27_BUILD_PIN(4, 12),
+ MX27_PIN_UART1_RXD = _MX27_BUILD_PIN(4, 13),
+ MX27_PIN_UART1_CTS = _MX27_BUILD_PIN(4, 14),
+ MX27_PIN_UART1_RTS = _MX27_BUILD_PIN(4, 15),
+ MX27_PIN_RTCK = _MX27_BUILD_PIN(4, 16),
+ MX27_PIN_RESET_OUT_B = _MX27_BUILD_PIN(4, 17),
+ MX27_PIN_SD1_D0 = _MX27_BUILD_PIN(4, 18),
+ MX27_PIN_SD1_D1 = _MX27_BUILD_PIN(4, 19),
+ MX27_PIN_SD1_D2 = _MX27_BUILD_PIN(4, 20),
+ MX27_PIN_SD1_D3 = _MX27_BUILD_PIN(4, 21),
+ MX27_PIN_SD1_CMD = _MX27_BUILD_PIN(4, 22),
+ MX27_PIN_SD1_CLK = _MX27_BUILD_PIN(4, 23),
+ MX27_PIN_USBOTG_CLK = _MX27_BUILD_PIN(4, 24),
+ MX27_PIN_USBOTG_DATA7 = _MX27_BUILD_PIN(4, 25),
+
+ MX27_PIN_NFRB = _MX27_BUILD_PIN(5, 0),
+ MX27_PIN_NFCLE = _MX27_BUILD_PIN(5, 1),
+ MX27_PIN_NFWP_B = _MX27_BUILD_PIN(5, 2),
+ MX27_PIN_NFCE_B = _MX27_BUILD_PIN(5, 3),
+ MX27_PIN_NFALE = _MX27_BUILD_PIN(5, 4),
+ MX27_PIN_NFRE_B = _MX27_BUILD_PIN(5, 5),
+ MX27_PIN_NFWE_B = _MX27_BUILD_PIN(5, 6),
+ MX27_PIN_PC_POE = _MX27_BUILD_PIN(5, 7),
+ MX27_PIN_PC_RW_B = _MX27_BUILD_PIN(5, 8),
+ MX27_PIN_IOIS16 = _MX27_BUILD_PIN(5, 9),
+ MX27_PIN_PC_RST = _MX27_BUILD_PIN(5, 10),
+ MX27_PIN_PC_BVD2 = _MX27_BUILD_PIN(5, 11),
+ MX27_PIN_PC_BVD1 = _MX27_BUILD_PIN(5, 12),
+ MX27_PIN_PC_VS2 = _MX27_BUILD_PIN(5, 13),
+ MX27_PIN_PC_VS1 = _MX27_BUILD_PIN(5, 14),
+ MX27_PIN_CLKO = _MX27_BUILD_PIN(5, 15),
+ MX27_PIN_PC_PWRON = _MX27_BUILD_PIN(5, 16),
+ MX27_PIN_PC_READY = _MX27_BUILD_PIN(5, 17),
+ MX27_PIN_PC_WAIT_B = _MX27_BUILD_PIN(5, 18),
+ MX27_PIN_PC_CD2_B = _MX27_BUILD_PIN(5, 19),
+ MX27_PIN_PC_CD1_B = _MX27_BUILD_PIN(5, 20),
+ MX27_PIN_CS4_B = _MX27_BUILD_PIN(5, 21),
+ MX27_PIN_CS5_B = _MX27_BUILD_PIN(5, 22),
+ MX27_PIN_ATA_DATA15 = _MX27_BUILD_PIN(5, 23),
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_MX27_PINS_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx27/mx27ads.c linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads.c
--- linux-2.6.26/arch/arm/mach-mx27/mx27ads.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,823 @@
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2006-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
+#include
+#include
+#include
+
+#include
+#endif
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "gpio_mux.h"
+#include "board-mx27ads.h"
+
+/*!
+ * @file mach-mx27/mx27ads.c
+ * @brief This file contains the board specific initialization routines.
+ *
+ * @ingroup MSL_MX27
+ */
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern void mxc_cpu_init(void) __init;
+extern void mxc_clocks_init(void);
+extern void mxc_cpu_common_init(void);
+extern struct sys_timer mxc_timer;
+extern void __init early_console_setup(char *);
+
+static char command_line[COMMAND_LINE_SIZE];
+static int mxc_card_status;
+int mxc_board_is_ads = 1;
+
+static void mxc_nop_release(struct device *dev)
+{
+ /* Nothing */
+}
+
+unsigned long board_get_ckih_rate(void)
+{
+ if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) {
+ return 27000000;
+ }
+ return 26000000;
+}
+
+#if defined(CONFIG_CS89x0) || defined(CONFIG_CS89x0_MODULE)
+/*! Null terminated portlist used to probe for the CS8900A device on ISA Bus
+ * Add 3 to reset the page window before probing (fixes eth probe when deployed
+ * using nand_boot)
+ */
+unsigned int netcard_portlist[] = { CS8900A_BASE_ADDRESS + 3, 0 };
+
+EXPORT_SYMBOL(netcard_portlist);
+/*!
+ * The CS8900A has 4 IRQ pins, which is software selectable, CS8900A interrupt
+ * pin 0 is used for interrupt generation.
+ */
+unsigned int cs8900_irq_map[] = { CS8900AIRQ, 0, 0, 0 };
+
+EXPORT_SYMBOL(cs8900_irq_map);
+#endif
+
+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
+unsigned int expio_intr_fec = MXC_EXP_IO_BASE + 7;
+
+EXPORT_SYMBOL(expio_intr_fec);
+#endif
+
+#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE)
+
+/*!
+ * This array is used for mapping mx27 ADS keypad scancodes to input keyboard
+ * keycodes.
+ */
+static u16 mxckpd_keycodes[] = {
+ KEY_KP9, KEY_LEFTSHIFT, KEY_0, KEY_KPASTERISK, KEY_RECORD, KEY_POWER,
+ KEY_KP8, KEY_9, KEY_8, KEY_7, KEY_KP5, KEY_VOLUMEDOWN,
+ KEY_KP7, KEY_6, KEY_5, KEY_4, KEY_KP4, KEY_VOLUMEUP,
+ KEY_KP6, KEY_3, KEY_2, KEY_1, KEY_KP3, KEY_DOWN,
+ KEY_BACK, KEY_RIGHT, KEY_ENTER, KEY_LEFT, KEY_HOME, KEY_KP2,
+ KEY_END, KEY_F2, KEY_UP, KEY_F1, KEY_F4, KEY_KP1,
+};
+
+static struct keypad_data evb_6_by_6_keypad = {
+ .rowmax = 6,
+ .colmax = 6,
+ .irq = MXC_INT_KPP,
+ .learning = 0,
+ .delay = 2,
+ .matrix = mxckpd_keycodes,
+};
+
+static struct resource mxc_kpp_resources[] = {
+ [0] = {
+ .start = MXC_INT_KPP,
+ .end = MXC_INT_KPP,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+/* mxc keypad driver */
+static struct platform_device mxc_keypad_device = {
+ .name = "mxc_keypad",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_kpp_resources),
+ .resource = mxc_kpp_resources,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &evb_6_by_6_keypad,
+ },
+};
+
+static void mxc_init_keypad(void)
+{
+ (void)platform_device_register(&mxc_keypad_device);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+/* MTD NOR flash */
+
+#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE)
+
+static struct mtd_partition mxc_nor_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 512 * 1024,
+ .offset = 0x00000000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "nor.Kernel",
+ .size = 2 * 1024 * 1024,
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0},
+ {
+ .name = "nor.userfs",
+ .size = 14 * 1024 * 1024,
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0},
+ {
+ .name = "nor.rootfs",
+ .size = 12 * 1024 * 1024,
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = MTD_WRITEABLE},
+ {
+ .name = "FIS directory",
+ .size = 12 * 1024,
+ .offset = 0x01FE0000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "Redboot config",
+ .size = MTDPART_SIZ_FULL,
+ .offset = 0x01FFF000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+};
+
+static struct flash_platform_data mxc_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+ .parts = mxc_nor_partitions,
+ .nr_parts = ARRAY_SIZE(mxc_nor_partitions),
+};
+
+static struct resource mxc_flash_resource = {
+ .start = 0xc0000000,
+ .end = 0xc0000000 + 0x02000000 - 1,
+ .flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device mxc_nor_mtd_device = {
+ .name = "mxc_nor_flash",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &mxc_flash_resource,
+};
+
+static void mxc_init_nor_mtd(void)
+{
+ (void)platform_device_register(&mxc_nor_mtd_device);
+}
+#else
+static void mxc_init_nor_mtd(void)
+{
+}
+#endif
+
+/* MTD NAND flash */
+
+#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE)
+
+static struct mtd_partition mxc_nand_partitions[4] = {
+ {
+ .name = "nand.bootloader",
+ .offset = 0,
+ .size = 1024 * 1024},
+ {
+ .name = "nand.kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 5 * 1024 * 1024},
+ {
+ .name = "nand.rootfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 22 * 1024 * 1024},
+ {
+ .name = "nand.userfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL},
+};
+
+static struct flash_platform_data mxc_nand_data = {
+ .parts = mxc_nand_partitions,
+ .nr_parts = ARRAY_SIZE(mxc_nand_partitions),
+ .width = 1,
+};
+
+static struct platform_device mxc_nand_mtd_device = {
+ .name = "mxc_nand_flash",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_nand_data,
+ },
+};
+
+static void mxc_init_nand_mtd(void)
+{
+ (void)platform_device_register(&mxc_nand_mtd_device);
+}
+#else
+static inline void mxc_init_nand_mtd(void)
+{
+}
+#endif
+
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+static const char fb_default_mode[] = "Sharp-QVGA";
+
+/* mxc lcd driver */
+static struct platform_device mxc_fb_device = {
+ .name = "mxc_sdc_fb",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &fb_default_mode,
+ .coherent_dma_mask = 0xFFFFFFFF,
+ },
+};
+
+static void mxc_init_fb(void)
+{
+ (void)platform_device_register(&mxc_fb_device);
+}
+#else
+static inline void mxc_init_fb(void)
+{
+}
+#endif
+
+#if defined(CONFIG_BACKLIGHT_MXC)
+static struct platform_device mxcbl_devices[] = {
+#if defined(CONFIG_BACKLIGHT_MXC_PMIC) || defined(CONFIG_BACKLIGHT_MXC_PMIC_MODULE)
+ {
+ .name = "mxc_pmic_bl",
+ .id = 0,
+ .dev = {
+ .platform_data = (void *)-1, /* DISP # for this backlight */
+ },
+ },
+ {
+ .name = "mxc_pmic_bl",
+ .id = 1,
+ .dev = {
+ .platform_data = (void *)0, /* DISP # for this backlight */
+ },
+ },
+#endif
+#if defined(CONFIG_BACKLIGHT_MXC_LCDC) || defined(CONFIG_BACKLIGHT_MXC_LCDC_MODULE)
+ {
+ .name = "mxc_lcdc_bl",
+ .id = 0,
+ .dev = {
+ .platform_data = (void *)3, /* DISP # for this backlight */
+ },
+ },
+#endif
+};
+static inline void mxc_init_bl(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) {
+ platform_device_register(&mxcbl_devices[i]);
+ }
+}
+#else
+static inline void mxc_init_bl(void)
+{
+}
+#endif
+
+static struct spi_board_info mxc_spi_board_info[] __initdata = {
+ {
+ .modalias = "pmic_spi",
+ .irq = IOMUX_TO_IRQ(MX27_PIN_TOUT),
+ .max_speed_hz = 4000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ },
+};
+
+#if 0
+#define MXC_CARD_DEBUG
+#endif
+
+static const int pbc_card_bit[4][3] = {
+ /* BSTAT IMR enable IMR removal */
+ {PBC_BSTAT_SD2_DET, PBC_INTR_SD2_EN, PBC_INTR_SD2_R_EN},
+ {PBC_BSTAT_SD3_DET, PBC_INTR_SD3_EN, PBC_INTR_SD3_R_EN},
+ {PBC_BSTAT_MS_DET, PBC_INTR_MS_EN, PBC_INTR_MS_R_EN},
+ {PBC_BSTAT_SD1_DET, PBC_INTR_SD1_EN, PBC_INTR_SD1_R_EN},
+};
+
+/*!
+ * Check if a SD card has been inserted or not.
+ *
+ * @param num a card number as defined in \b enum \b mxc_card_no
+ * @return 0 if a card is not present; non-zero otherwise.
+ */
+int mxc_card_detected(enum mxc_card_no num)
+{
+ u32 status;
+
+ status = __raw_readw(PBC_BSTAT1_REG);
+ return ((status & MXC_BSTAT_BIT(num)) == 0);
+}
+
+/*
+ * Check if there is any state change by reading the IMR register and the
+ * previous and current states of the board status register (offset 0x28).
+ * A state change is defined to be card insertion OR removal. So the driver
+ * may have to call the mxc_card_detected() function to see if it is card
+ * insertion or removal.
+ *
+ * @param mask current IMR value
+ * @param s0 previous status register value (offset 0x28)
+ * @param s1 current status register value (offset 0x28)
+ *
+ * @return 0 if no card status change OR the corresponding bits in the IMR
+ * (passed in as 'mask') is NOT set.
+ * A non-zero value indicates some card state changes. For example,
+ * 0b0001 means SD3 has a card state change (bit0 is set) AND its
+ * associated insertion or removal bits in IMR is SET.
+ * 0b0100 means SD1 has a card state change (bit2 is set) AND its
+ * associated insertion or removal bits in IMR is SET.
+ * 0b1001 means both MS and SD3 have state changes
+ */
+static u32 mxc_card_state_changed(u32 mask, u32 s0, u32 s1)
+{
+ u32 i, retval = 0;
+ u32 stat = (s0 ^ s1) & 0x7800;
+
+ if (stat == 0)
+ return 0;
+
+ for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) {
+ if ((stat & pbc_card_bit[i][0]) != 0 &&
+ (mask & (pbc_card_bit[i][1] | pbc_card_bit[i][2])) != 0) {
+ retval |= 1 << i;
+ }
+ }
+#ifdef MXC_CARD_DEBUG
+ printk(KERN_INFO "\nmask=%x, s0=%x, s1=%x\n", mask, s0, s1);
+ printk(KERN_INFO "retval=%x, stat=%x\n", retval, stat);
+#endif
+ return retval;
+}
+
+/*!
+ * Interrupt handler for the expio (CPLD) to deal with interrupts from
+ * FEC, external UART, CS8900 Ethernet and SD cards, etc.
+ */
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+ u32 imr, card_int, i;
+ u32 int_valid;
+ u32 expio_irq;
+ u32 stat = __raw_readw(PBC_BSTAT1_REG);
+
+ desc->chip->mask(irq); /* irq = gpio irq number */
+
+ imr = __raw_readw(PBC_INTMASK_SET_REG);
+
+ card_int = mxc_card_state_changed(imr, mxc_card_status, stat);
+ mxc_card_status = stat;
+
+ if (card_int != 0) {
+ for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) {
+ if ((card_int & (1 << i)) != 0) {
+ pr_debug("card no %d state changed\n", i);
+ }
+ }
+ }
+
+ /* Bits defined in PBC_INTSTATUS_REG at 0x2C */
+ int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr;
+ /* combined with the card interrupt valid information */
+ int_valid = (int_valid & 0x0F8E) | (card_int << PBC_INTR_SD2_EN_BIT);
+
+ if (unlikely(!int_valid)) {
+ pr_debug("\nEXPIO: Spurious interrupt:0x%0x\n\n", int_valid);
+ pr_debug("CPLD IMR(0x38)=0x%x, BSTAT1(0x28)=0x%x\n", imr, stat);
+ goto out;
+ }
+
+ expio_irq = MXC_EXP_IO_BASE;
+ for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+ struct irq_desc *d;
+ if ((int_valid & 1) == 0)
+ continue;
+ d = irq_desc + expio_irq;
+ if (unlikely(!(d->handle_irq))) {
+ printk(KERN_ERR "\nEXPIO irq: %d unhandeled\n",
+ expio_irq);
+ BUG(); /* oops */
+ }
+ d->handle_irq(expio_irq, d);
+ }
+
+ out:
+ desc->chip->ack(irq);
+ desc->chip->unmask(irq);
+}
+
+#ifdef MXC_CARD_DEBUG
+
+static irqreturn_t mxc_sd_test_handler(int irq, void *desc)
+{
+ int s = -1;
+
+ printk(KERN_INFO "%s(irq=%d) for ", __FUNCTION__, irq);
+ if (irq == EXPIO_INT_SD1_EN) {
+ printk(KERN_INFO "SD1");
+ s = MXC_CARD_SD1;
+ } else if (irq == EXPIO_INT_SD2_EN) {
+ printk(KERN_INFO "SD2");
+ s = MXC_CARD_SD2;
+ } else if (irq == EXPIO_INT_SD3_EN) {
+ printk(KERN_INFO "SD3");
+ s = MXC_CARD_SD3;
+ } else if (irq == EXPIO_INT_MS_EN) {
+ printk(KERN_INFO "MS");
+ s = MXC_CARD_MS;
+ } else {
+ printk(KERN_INFO "None!!!!");
+ }
+ if (mxc_card_detected(s)) {
+ printk(KERN_INFO " inserted\n");
+ } else {
+ printk(KERN_INFO " removed\n");
+ }
+
+ return IRQ_HANDLED;
+}
+#endif /* MXC_CARD_DEBUG */
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param irq an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+ u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+ /* mask the interrupt */
+ if (irq < EXPIO_INT_SD2_EN) {
+ __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
+ } else {
+ irq -= EXPIO_INT_SD2_EN;
+ /* clear both SDx_EN and SDx_R_EN bits */
+ __raw_writew((pbc_card_bit[irq][1] | pbc_card_bit[irq][2]),
+ PBC_INTMASK_CLEAR_REG);
+ }
+}
+
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param irq an expanded io virtual irq number
+ */
+static void expio_ack_irq(u32 irq)
+{
+ u32 expio = MXC_IRQ_TO_EXPIO(irq);
+ /* clear the interrupt status */
+ __raw_writew(1 << expio, PBC_INTSTATUS_REG);
+ /* mask the interrupt */
+ expio_mask_irq(irq);
+}
+
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param irq an expio virtual irq number
+ */
+static void expio_unmask_irq(u32 irq)
+{
+ u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+ /* unmask the interrupt */
+ if (irq < EXPIO_INT_SD2_EN) {
+ if (irq == EXPIO_INT_XUART_INTA) {
+ /* Set 8250 MCR register bit 3 - Forces the INT (A-B
+ * outputs to the active mode and sets OP2 to logic 0.
+ * This is needed to avoid spurious int caused by the
+ * internal CPLD pull-up for the interrupt pin.
+ */
+ u16 val = __raw_readw(MXC_LL_EXTUART_VADDR + 8);
+ __raw_writew(val | 0x8, MXC_LL_EXTUART_VADDR + 8);
+ }
+ __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
+ } else {
+ irq -= EXPIO_INT_SD2_EN;
+
+ if (mxc_card_detected(irq)) {
+ __raw_writew(pbc_card_bit[irq][2], PBC_INTMASK_SET_REG);
+ } else {
+ __raw_writew(pbc_card_bit[irq][1], PBC_INTMASK_SET_REG);
+ }
+ }
+}
+
+static struct irq_chip expio_irq_chip = {
+ .ack = expio_ack_irq,
+ .mask = expio_mask_irq,
+ .unmask = expio_unmask_irq,
+};
+
+static int __init mxc_expio_init(void)
+{
+ int i, ver;
+
+ ver = (__raw_readw(PBC_VERSION_REG) >> 8) & 0xFF;
+ if ((ver & 0x80) != 0) {
+ pr_info("MX27 ADS EXPIO(CPLD) hardware\n");
+ pr_info("CPLD version: 0x%x\n", ver);
+ } else {
+ mxc_board_is_ads = 0;
+ ver &= 0x0F;
+ pr_info("MX27 EVB EXPIO(CPLD) hardware\n");
+ if (ver == 0xF || ver <= MXC_CPLD_VER_1_50)
+ pr_info("Wrong CPLD version: %d\n", ver);
+ else {
+ pr_info("CPLD version: %d\n", ver);
+ }
+ }
+
+ mxc_card_status = __raw_readw(PBC_BSTAT1_REG);
+
+#ifdef MXC_CARD_DEBUG
+ for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) {
+ if (mxc_card_detected(i)) {
+ pr_info("Card %d is detected\n", 3 - i);
+ }
+ }
+#endif
+ /*
+ * Configure INT line as GPIO input
+ */
+ gpio_config_mux(MX27_PIN_TIN, GPIO_MUX_GPIO);
+ mxc_set_gpio_direction(MX27_PIN_TIN, 1);
+
+ /* disable the interrupt and clear the status */
+ __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
+ __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
+
+ for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
+ i++) {
+ set_irq_chip(i, &expio_irq_chip);
+ set_irq_handler(i, handle_level_irq);
+ set_irq_flags(i, IRQF_VALID);
+ }
+ set_irq_type(EXPIO_PARENT_INT, IRQT_HIGH);
+ set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
+
+ return 0;
+}
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+
+/*!
+ * The serial port definition structure. The fields contain:
+ * {UART, CLK, PORT, IRQ, FLAGS}
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+ {
+ .membase = (void __iomem *)(CS4_BASE_ADDR_VIRT + 0x20000),
+ .mapbase = (unsigned long)(CS4_BASE_ADDR + 0x20000),
+ .irq = EXPIO_INT_XUART_INTA,
+ .uartclk = 3686400,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+ /*.pm = serial_platform_pm, */
+ },
+ {},
+};
+
+/*!
+ * REVISIT: document me
+ */
+static struct platform_device serial_device = {
+ .name = "serial8250",
+ .id = 0,
+ .dev = {
+ .platform_data = &serial_platform_data[0],
+ },
+};
+
+/*!
+ * REVISIT: document me
+ */
+static int __init mxc_init_extuart(void)
+{
+ int value;
+ /*reset ext uart in cpld */
+ __raw_writew(PBC_BCTRL1_URST, PBC_BCTRL1_SET_REG);
+ /*delay some time for reset finish */
+ for (value = 0; value < 1000; value++) ;
+ __raw_writew(PBC_BCTRL1_URST, PBC_BCTRL1_CLEAR_REG);
+ return platform_device_register(&serial_device);
+}
+#else
+static inline int mxc_init_extuart(void)
+{
+ return 0;
+}
+#endif
+
+#if (defined(CONFIG_MXC_PMIC_MC13783) || \
+ defined(CONFIG_MXC_PMIC_MC13783_MODULE)) \
+ && (defined(CONFIG_SND_MXC_PMIC) || defined(CONFIG_SND_MXC_PMIC_MODULE))
+extern void gpio_ssi_active(int ssi_num);
+
+static void __init mxc_init_pmic_audio(void)
+{
+ struct clk *ckih_clk;
+ struct clk *cko_clk;
+
+ /* Enable 26 mhz clock on CKO1 for PMIC audio */
+ ckih_clk = clk_get(NULL, "ckih");
+ cko_clk = clk_get(NULL, "clko_clk");
+ if (IS_ERR(ckih_clk) || IS_ERR(cko_clk)) {
+ printk(KERN_ERR "Unable to set CLKO output to CKIH\n");
+ } else {
+ clk_set_parent(cko_clk, ckih_clk);
+ clk_set_rate(cko_clk, clk_get_rate(ckih_clk));
+ clk_enable(cko_clk);
+ }
+ clk_put(ckih_clk);
+ clk_put(cko_clk);
+
+ gpio_ssi_active(0);
+ gpio_ssi_active(1);
+}
+#else
+static void __inline mxc_init_pmic_audio(void)
+{
+}
+#endif
+
+/* IDE device data */
+#if defined(CONFIG_BLK_DEV_IDE_MXC) || defined(CONFIG_BLK_DEV_IDE_MXC_MODULE)
+
+/*! Platform Data for MXC IDE */
+static struct mxc_ide_platform_data mxc_ide_data = {
+ .power_drive = NULL,
+ .power_io = NULL,
+};
+
+static struct platform_device mxc_ide_device = {
+ .name = "mxc_ide",
+ .id = 0,
+ .dev = {
+ .release = mxc_nop_release,
+ .platform_data = &mxc_ide_data,
+ },
+};
+
+static inline void mxc_init_ide(void)
+{
+ if (platform_device_register(&mxc_ide_device) < 0)
+ printk(KERN_ERR "Error: Registering the ide.\n");
+}
+#else
+static inline void mxc_init_ide(void)
+{
+}
+#endif
+
+static __init void mxc_board_init(void)
+{
+ pr_info("AIPI VA base: 0x%x\n", IO_ADDRESS(AIPI_BASE_ADDR));
+ mxc_cpu_common_init();
+ mxc_clocks_init();
+ early_console_setup(saved_command_line);
+ mxc_gpio_init();
+ mxc_expio_init();
+ mxc_init_keypad();
+ mxc_init_nor_mtd();
+ mxc_init_nand_mtd();
+ mxc_init_extuart();
+ mxc_init_pmic_audio();
+#ifdef MXC_CARD_DEBUG
+ request_irq(EXPIO_INT_SD1_EN, mxc_sd_test_handler, 0, "SD_card1", NULL);
+ request_irq(EXPIO_INT_SD2_EN, mxc_sd_test_handler, 0, "SD_card2", NULL);
+ request_irq(EXPIO_INT_SD3_EN, mxc_sd_test_handler, 0, "SD_card3", NULL);
+ request_irq(EXPIO_INT_MS_EN, mxc_sd_test_handler, 0, "MS_card", NULL);
+#endif
+
+ spi_register_board_info(mxc_spi_board_info,
+ ARRAY_SIZE(mxc_spi_board_info));
+
+ mxc_init_fb();
+ mxc_init_bl();
+ mxc_init_ide();
+}
+
+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+#ifdef CONFIG_KGDB_8250
+ int i;
+ for (i = 0;
+ i <
+ (sizeof(serial_platform_data) / sizeof(serial_platform_data[0]));
+ i += 1)
+ kgdb8250_add_platform_port(i, &serial_platform_data[i]);
+#endif
+
+ mxc_cpu_init();
+ /* Store command line for use on mxc_board_init */
+ strcpy(command_line, *cmdline);
+
+#ifdef CONFIG_DISCONTIGMEM
+ do {
+ int nid;
+ mi->nr_banks = MXC_NUMNODES;
+ for (nid = 0; nid < mi->nr_banks; nid++) {
+ SET_NODE(mi, nid);
+ }
+ } while (0);
+#endif
+}
+
+EXPORT_SYMBOL(mxc_card_detected);
+EXPORT_SYMBOL(mxc_board_is_ads);
+
+/*
+ * The following uses standard kernel macros define in arch.h in order to
+ * initialize __mach_desc_MX27ADS data structure.
+ */
+/* *INDENT-OFF* */
+MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
+ /* maintainer: Freescale Semiconductor, Inc. */
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+ .phys_io = CS4_BASE_ADDR,
+ .io_pg_offst = ((CS4_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#else
+ .phys_io = AIPI_BASE_ADDR,
+ .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#endif
+ .boot_params = PHYS_OFFSET + 0x100,
+ .fixup = fixup_mxc_board,
+ .map_io = mxc_map_io,
+ .init_irq = mxc_init_irq,
+ .init_machine = mxc_board_init,
+ .timer = &mxc_timer,
+MACHINE_END
diff -urN linux-2.6.26/arch/arm/mach-mx27/mx27ads_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads_gpio.c
--- linux-2.6.26/arch/arm/mach-mx27/mx27ads_gpio.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads_gpio.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,1226 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "board-mx27ads.h"
+#include "gpio_mux.h"
+#include "crm_regs.h"
+
+static int g_uart_activated[MXC_UART_NR] = { 0, 0, 0, 0, 0, 0 };
+
+/*!
+ * @file mach-mx27/mx27ads_gpio.c
+ *
+ * @brief This file contains all the GPIO setup functions for the board.
+ *
+ * @ingroup GPIO_MX27
+ */
+
+/*!
+ * Setup GPIO for a UART port to be active
+ *
+ * @param port a UART port
+ * @param no_irda indicates if the port is used for SIR
+ */
+void gpio_uart_active(int port, int no_irda)
+{
+ if (port < 0 || port >= MXC_UART_NR) {
+ pr_info("Wrong port number: %d\n", port);
+ BUG();
+ }
+
+ if (g_uart_activated[port]) {
+ pr_info("UART %d has been activated multi-times\n", port + 1);
+ return;
+ }
+ g_uart_activated[port] = 1;
+
+ switch (port) {
+ case 0:
+ gpio_request_mux(MX27_PIN_UART1_TXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART1_RXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART1_CTS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART1_RTS, GPIO_MUX_PRIMARY);
+ break;
+ case 1:
+ gpio_request_mux(MX27_PIN_UART2_TXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART2_RXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART2_CTS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART2_RTS, GPIO_MUX_PRIMARY);
+ break;
+ case 2:
+ gpio_request_mux(MX27_PIN_UART3_TXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART3_RXD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART3_CTS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_UART3_RTS, GPIO_MUX_PRIMARY);
+
+ /* Enable IRDA in CPLD */
+ __raw_writew(PBC_BCTRL2_IRDA_EN, PBC_BCTRL2_CLEAR_REG);
+ break;
+ case 3:
+ gpio_request_mux(MX27_PIN_USBH1_TXDM, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_USBH1_RXDP, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_USBH1_TXDP, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_USBH1_FS, GPIO_MUX_ALT);
+ break;
+ case 4:
+ gpio_request_mux(MX27_PIN_CSI_D6, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_CSI_D7, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_CSI_VSYNC, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_CSI_HSYNC, GPIO_MUX_ALT);
+ break;
+ case 5:
+ gpio_request_mux(MX27_PIN_CSI_D0, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_CSI_D1, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_CSI_D2, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_CSI_D3, GPIO_MUX_ALT);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a UART port to be inactive
+ *
+ * @param port a UART port
+ * @param no_irda indicates if the port is used for SIR
+ */
+void gpio_uart_inactive(int port, int no_irda)
+{
+ if (port < 0 || port >= MXC_UART_NR) {
+ pr_info("Wrong port number: %d\n", port);
+ BUG();
+ }
+
+ if (g_uart_activated[port] == 0) {
+ pr_info("UART %d has not been activated \n", port + 1);
+ return;
+ }
+ g_uart_activated[port] = 0;
+
+ switch (port) {
+ case 0:
+ gpio_free_mux(MX27_PIN_UART1_TXD);
+ gpio_free_mux(MX27_PIN_UART1_RXD);
+ gpio_free_mux(MX27_PIN_UART1_CTS);
+ gpio_free_mux(MX27_PIN_UART1_RTS);
+ break;
+ case 1:
+ gpio_free_mux(MX27_PIN_UART2_TXD);
+ gpio_free_mux(MX27_PIN_UART2_RXD);
+ gpio_free_mux(MX27_PIN_UART2_CTS);
+ gpio_free_mux(MX27_PIN_UART2_RTS);
+ break;
+ case 2:
+ gpio_free_mux(MX27_PIN_UART3_TXD);
+ gpio_free_mux(MX27_PIN_UART3_RXD);
+ gpio_free_mux(MX27_PIN_UART3_CTS);
+ gpio_free_mux(MX27_PIN_UART3_RTS);
+
+ /* Disable IRDA in CPLD */
+ __raw_writew(PBC_BCTRL2_IRDA_EN, PBC_BCTRL2_SET_REG);
+ break;
+ case 3:
+ gpio_free_mux(MX27_PIN_USBH1_TXDM);
+ gpio_free_mux(MX27_PIN_USBH1_RXDP);
+ gpio_free_mux(MX27_PIN_USBH1_TXDP);
+ gpio_free_mux(MX27_PIN_USBH1_FS);
+ break;
+ case 4:
+ gpio_free_mux(MX27_PIN_CSI_D6);
+ gpio_free_mux(MX27_PIN_CSI_D7);
+ gpio_free_mux(MX27_PIN_CSI_VSYNC);
+ gpio_free_mux(MX27_PIN_CSI_HSYNC);
+ break;
+ case 5:
+ gpio_free_mux(MX27_PIN_CSI_D0);
+ gpio_free_mux(MX27_PIN_CSI_D1);
+ gpio_free_mux(MX27_PIN_CSI_D2);
+ gpio_free_mux(MX27_PIN_CSI_D3);
+ break;
+ default:
+ break;
+ }
+}
+
+void gpio_power_key_active(void)
+{
+}
+EXPORT_SYMBOL(gpio_power_key_active);
+
+/*!
+ * Configure the IOMUX GPR register to receive shared SDMA UART events
+ *
+ * @param port a UART port
+ */
+void config_uartdma_event(int port)
+{
+ return;
+}
+
+static int usbh1_hs_active;
+/*!
+ * Setup GPIO for USB, Total 34 signals
+ * PIN Configuration for USBOTG: High/Full speed OTG
+ * PE2,PE1,PE0,PE24,PE25 -- PRIMARY
+ PC7 - PC13 -- PRIMARY
+ PB23,PB24 -- PRIMARY
+
+ * PIN Configuration for USBH2: : High/Full/Low speed host
+ * PA0 - PA4 -- PRIMARY
+ PD19, PD20,PD21,PD22,PD23,PD24,PD26 --Alternate (SECONDARY)
+
+ * PIN Configuration for USBH1: Full/low speed host
+ * PB25 - PB31 -- PRIMARY
+ PB22 -- PRIMARY
+ */
+int gpio_usbh1_active(void)
+{
+ if (usbh1_hs_active)
+ return 0;
+
+ if (gpio_request_mux(MX27_PIN_USBH1_SUSP, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH1_RCV, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH1_FS, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH1_OE_B, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH1_TXDM, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH1_TXDP, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH1_RXDM, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH1_RXDP, GPIO_MUX_PRIMARY))
+ return -EINVAL;
+
+ __raw_writew(PBC_BCTRL3_FSH_MOD, PBC_BCTRL3_CLEAR_REG);
+ __raw_writew(PBC_BCTRL3_FSH_VBUS_EN, PBC_BCTRL3_CLEAR_REG);
+ usbh1_hs_active = 1;
+ return 0;
+}
+void gpio_usbh1_inactive(void)
+{
+ if (usbh1_hs_active == 0)
+ return;
+
+ gpio_free_mux(MX27_PIN_USBH1_SUSP);
+ gpio_free_mux(MX27_PIN_USBH1_RCV);
+ gpio_free_mux(MX27_PIN_USBH1_FS);
+ gpio_free_mux(MX27_PIN_USBH1_OE_B);
+ gpio_free_mux(MX27_PIN_USBH1_TXDM);
+ gpio_free_mux(MX27_PIN_USBH1_TXDP);
+ gpio_free_mux(MX27_PIN_USBH1_RXDM);
+ gpio_free_mux(MX27_PIN_USBH1_RXDP);
+ __raw_writew(PBC_BCTRL3_FSH_VBUS_EN, PBC_BCTRL3_SET_REG);
+
+ usbh1_hs_active = 0;
+}
+
+static int usbh2_hs_active;
+/*
+ * conflicts with CSPI1 (MC13783) and CSPI2 (Connector)
+ */
+int gpio_usbh2_active(void)
+{
+ if (usbh2_hs_active)
+ return 0;
+
+ if (gpio_set_puen(MX27_PIN_USBH2_CLK, 0) ||
+ gpio_set_puen(MX27_PIN_USBH2_DIR, 0) ||
+ gpio_set_puen(MX27_PIN_USBH2_DATA7, 0) ||
+ gpio_set_puen(MX27_PIN_USBH2_NXT, 0) ||
+ gpio_set_puen(MX27_PIN_USBH2_STP, 0) ||
+ gpio_set_puen(MX27_PIN_CSPI2_SS2, 0) ||
+ gpio_set_puen(MX27_PIN_CSPI2_SS1, 0) ||
+ gpio_set_puen(MX27_PIN_CSPI2_SS0, 0) ||
+ gpio_set_puen(MX27_PIN_CSPI2_SCLK, 0) ||
+ gpio_set_puen(MX27_PIN_CSPI2_MISO, 0) ||
+ gpio_set_puen(MX27_PIN_CSPI2_MOSI, 0) ||
+ gpio_set_puen(MX27_PIN_CSPI1_SS2, 0))
+ return -EINVAL;
+
+ if (gpio_request_mux(MX27_PIN_USBH2_CLK, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH2_DIR, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH2_DATA7, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH2_NXT, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBH2_STP, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_CSPI2_SS2, GPIO_MUX_ALT) ||
+ gpio_request_mux(MX27_PIN_CSPI2_SS1, GPIO_MUX_ALT) ||
+ gpio_request_mux(MX27_PIN_CSPI2_SS0, GPIO_MUX_ALT) ||
+ gpio_request_mux(MX27_PIN_CSPI2_SCLK, GPIO_MUX_ALT) ||
+ gpio_request_mux(MX27_PIN_CSPI2_MISO, GPIO_MUX_ALT) ||
+ gpio_request_mux(MX27_PIN_CSPI2_MOSI, GPIO_MUX_ALT) ||
+ gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_ALT))
+ return -EINVAL;
+
+ __raw_writew(PBC_BCTRL3_HSH_EN, PBC_BCTRL3_CLEAR_REG);
+ usbh2_hs_active = 1;
+ return 0;
+}
+void gpio_usbh2_inactive(void)
+{
+ if (usbh2_hs_active == 0)
+ return;
+
+ gpio_free_mux(MX27_PIN_USBH2_CLK);
+ gpio_free_mux(MX27_PIN_USBH2_DIR);
+ gpio_free_mux(MX27_PIN_USBH2_DATA7);
+ gpio_free_mux(MX27_PIN_USBH2_NXT);
+ gpio_free_mux(MX27_PIN_USBH2_STP);
+
+ gpio_free_mux(MX27_PIN_CSPI2_SS2);
+ gpio_free_mux(MX27_PIN_CSPI2_SS1);
+ gpio_free_mux(MX27_PIN_CSPI2_SS0);
+ gpio_free_mux(MX27_PIN_CSPI2_SCLK);
+ gpio_free_mux(MX27_PIN_CSPI2_MISO);
+ gpio_free_mux(MX27_PIN_CSPI2_MOSI);
+ gpio_free_mux(MX27_PIN_CSPI1_SS2);
+
+ gpio_set_puen(MX27_PIN_USBH2_CLK, 1);
+ gpio_set_puen(MX27_PIN_USBH2_DIR, 1);
+ gpio_set_puen(MX27_PIN_USBH2_DATA7, 1);
+ gpio_set_puen(MX27_PIN_USBH2_NXT, 1);
+ gpio_set_puen(MX27_PIN_USBH2_STP, 1);
+ gpio_set_puen(MX27_PIN_CSPI2_SS2, 1);
+ gpio_set_puen(MX27_PIN_CSPI2_SS1, 1);
+ gpio_set_puen(MX27_PIN_CSPI2_SS0, 1);
+ gpio_set_puen(MX27_PIN_CSPI2_SCLK, 1);
+ gpio_set_puen(MX27_PIN_CSPI2_MISO, 1);
+ gpio_set_puen(MX27_PIN_CSPI2_MOSI, 1);
+ gpio_set_puen(MX27_PIN_CSPI1_SS2, 1);
+ __raw_writew(PBC_BCTRL3_HSH_EN, PBC_BCTRL3_SET_REG);
+
+ usbh2_hs_active = 0;
+}
+
+static int usbotg_hs_active;
+int gpio_usbotg_hs_active(void)
+{
+ if (usbotg_hs_active)
+ return 0;
+
+ if (gpio_request_mux(MX27_PIN_USBOTG_DATA5, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_DATA6, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_DATA0, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_DATA2, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_DATA1, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_DATA3, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_DATA4, GPIO_MUX_PRIMARY) ||
+
+ gpio_request_mux(MX27_PIN_USBOTG_DIR, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_STP, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_NXT, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_CLK, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USBOTG_DATA7, GPIO_MUX_PRIMARY) ||
+
+ gpio_request_mux(MX27_PIN_USB_OC_B, GPIO_MUX_PRIMARY) ||
+ gpio_request_mux(MX27_PIN_USB_PWR, GPIO_MUX_PRIMARY))
+ return -EINVAL;
+
+ __raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BCTRL3_CLEAR_REG);
+ __raw_writew(PBC_BCTRL3_OTG_VBUS_EN, PBC_BCTRL3_CLEAR_REG);
+
+ usbotg_hs_active = 1;
+ return 0;
+}
+
+void gpio_usbotg_hs_inactive(void)
+{
+ if (usbotg_hs_active == 0)
+ return;
+
+ gpio_free_mux(MX27_PIN_USBOTG_DATA5);
+ gpio_free_mux(MX27_PIN_USBOTG_DATA6);
+ gpio_free_mux(MX27_PIN_USBOTG_DATA0);
+ gpio_free_mux(MX27_PIN_USBOTG_DATA2);
+ gpio_free_mux(MX27_PIN_USBOTG_DATA1);
+ gpio_free_mux(MX27_PIN_USBOTG_DATA3);
+ gpio_free_mux(MX27_PIN_USBOTG_DATA4);
+
+ gpio_free_mux(MX27_PIN_USBOTG_DIR);
+ gpio_free_mux(MX27_PIN_USBOTG_STP);
+ gpio_free_mux(MX27_PIN_USBOTG_NXT);
+ gpio_free_mux(MX27_PIN_USBOTG_CLK);
+ gpio_free_mux(MX27_PIN_USBOTG_DATA7);
+
+ gpio_free_mux(MX27_PIN_USB_OC_B);
+ gpio_free_mux(MX27_PIN_USB_PWR);
+ __raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BCTRL3_SET_REG);
+
+ usbotg_hs_active = 0;
+}
+
+int gpio_usbotg_fs_active(void)
+{
+ return gpio_usbotg_hs_active();
+}
+
+void gpio_usbotg_fs_inactive(void)
+{
+ gpio_usbotg_hs_inactive();
+}
+
+/*!
+ * end Setup GPIO for USB
+ *
+ */
+
+/************************************************************************/
+/* for i2c gpio */
+/* I2C1: PD17,PD18 -- Primary */
+/* I2C2: PC5,PC6 -- Primary */
+/************************************************************************/
+/*!
+* Setup GPIO for an I2C device to be active
+*
+* @param i2c_num an I2C device
+*/
+void gpio_i2c_active(int i2c_num)
+{
+ switch (i2c_num) {
+ case 0:
+ gpio_request_mux(MX27_PIN_I2C_CLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_I2C_DATA, GPIO_MUX_PRIMARY);
+ break;
+ case 1:
+ gpio_request_mux(MX27_PIN_I2C2_SCL, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_I2C2_SDA, GPIO_MUX_PRIMARY);
+ break;
+ default:
+ printk(KERN_ERR "gpio_i2c_active no compatible I2C adapter\n");
+ break;
+ }
+}
+
+/*!
+ * * Setup GPIO for an I2C device to be inactive
+ * *
+ * * @param i2c_num an I2C device
+ */
+void gpio_i2c_inactive(int i2c_num)
+{
+ switch (i2c_num) {
+ case 0:
+ gpio_free_mux(MX27_PIN_I2C_CLK);
+ gpio_free_mux(MX27_PIN_I2C_DATA);
+ break;
+ case 1:
+ gpio_free_mux(MX27_PIN_I2C2_SCL);
+ gpio_free_mux(MX27_PIN_I2C2_SDA);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a CSPI device to be active
+ *
+ * @param cspi_mod an CSPI device
+ */
+void gpio_spi_active(int cspi_mod)
+{
+ switch (cspi_mod) {
+ case 0:
+ /* SPI1 */
+ gpio_request_mux(MX27_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SCLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY);
+ break;
+ case 1:
+ /*SPI2 */
+ gpio_request_mux(MX27_PIN_CSPI2_MOSI, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI2_MISO, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI2_SCLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI2_SS0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI2_SS1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSPI2_SS2, GPIO_MUX_PRIMARY);
+ break;
+ case 2:
+ /*SPI3 */
+ gpio_request_mux(MX27_PIN_SD1_D0, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_SD1_CMD, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_SD1_CLK, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_SD1_D3, GPIO_MUX_ALT);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a CSPI device to be inactive
+ *
+ * @param cspi_mod a CSPI device
+ */
+void gpio_spi_inactive(int cspi_mod)
+{
+ switch (cspi_mod) {
+ case 0:
+ /* SPI1 */
+ gpio_free_mux(MX27_PIN_CSPI1_MOSI);
+ gpio_free_mux(MX27_PIN_CSPI1_MISO);
+ gpio_free_mux(MX27_PIN_CSPI1_SCLK);
+ gpio_free_mux(MX27_PIN_CSPI1_RDY);
+ gpio_free_mux(MX27_PIN_CSPI1_SS0);
+ gpio_free_mux(MX27_PIN_CSPI1_SS1);
+ gpio_free_mux(MX27_PIN_CSPI1_SS2);
+ break;
+ case 1:
+ /*SPI2 */
+ gpio_free_mux(MX27_PIN_CSPI2_MOSI);
+ gpio_free_mux(MX27_PIN_CSPI2_MISO);
+ gpio_free_mux(MX27_PIN_CSPI2_SCLK);
+ gpio_free_mux(MX27_PIN_CSPI2_SS0);
+ gpio_free_mux(MX27_PIN_CSPI2_SS1);
+ gpio_free_mux(MX27_PIN_CSPI2_SS2);
+ break;
+ case 2:
+ /*SPI3 */
+ gpio_free_mux(MX27_PIN_SD1_D0);
+ gpio_free_mux(MX27_PIN_SD1_CMD);
+ gpio_free_mux(MX27_PIN_SD1_CLK);
+ gpio_free_mux(MX27_PIN_SD1_D3);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for a nand flash device to be active
+ *
+ */
+void gpio_nand_active(void)
+{
+ unsigned long reg;
+ reg = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_FMCR);
+ reg &= ~(1 << 4);
+ __raw_writel(reg, IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_FMCR);
+
+ gpio_request_mux(MX27_PIN_NFRB, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_NFCE_B, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_NFWP_B, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_NFCLE, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_NFALE, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_NFRE_B, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_NFWE_B, GPIO_MUX_PRIMARY);
+}
+
+/*!
+ * Setup GPIO for a nand flash device to be inactive
+ *
+ */
+void gpio_nand_inactive(void)
+{
+ gpio_free_mux(MX27_PIN_NFRB);
+ gpio_free_mux(MX27_PIN_NFCE_B);
+ gpio_free_mux(MX27_PIN_NFWP_B);
+ gpio_free_mux(MX27_PIN_NFCLE);
+ gpio_free_mux(MX27_PIN_NFALE);
+ gpio_free_mux(MX27_PIN_NFRE_B);
+ gpio_free_mux(MX27_PIN_NFWE_B);
+}
+
+/*!
+ * Setup GPIO for CSI device to be active
+ *
+ */
+void gpio_sensor_active(void)
+{
+ gpio_request_mux(MX27_PIN_CSI_D0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_D1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_D2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_D3, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_D4, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_MCLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_PIXCLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_D5, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_D6, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_D7, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_VSYNC, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CSI_HSYNC, GPIO_MUX_PRIMARY);
+
+#ifdef CONFIG_MXC_CAMERA_MC521DA
+ __raw_writew(0x100, PBC_BCTRL2_SET_REG);
+#else
+ __raw_writew(0x400, PBC_BCTRL2_SET_REG);
+#endif
+}
+
+void gpio_sensor_inactive(void)
+{
+ gpio_free_mux(MX27_PIN_CSI_D0);
+ gpio_free_mux(MX27_PIN_CSI_D1);
+ gpio_free_mux(MX27_PIN_CSI_D2);
+ gpio_free_mux(MX27_PIN_CSI_D3);
+ gpio_free_mux(MX27_PIN_CSI_D4);
+ gpio_free_mux(MX27_PIN_CSI_MCLK);
+ gpio_free_mux(MX27_PIN_CSI_PIXCLK);
+ gpio_free_mux(MX27_PIN_CSI_D5);
+ gpio_free_mux(MX27_PIN_CSI_D6);
+ gpio_free_mux(MX27_PIN_CSI_D7);
+ gpio_free_mux(MX27_PIN_CSI_VSYNC);
+ gpio_free_mux(MX27_PIN_CSI_HSYNC);
+
+#ifdef CONFIG_MXC_CAMERA_MC521DA
+ __raw_writew(0x100, PBC_BCTRL2_CLEAR_REG);
+#else
+ __raw_writew(0x400, PBC_BCTRL2_CLEAR_REG);
+#endif
+}
+
+void gpio_sensor_reset(bool flag)
+{
+ u16 temp;
+
+ if (flag) {
+ temp = 0x200;
+ __raw_writew(temp, PBC_BCTRL2_CLEAR_REG);
+ } else {
+ temp = 0x200;
+ __raw_writew(temp, PBC_BCTRL2_SET_REG);
+ }
+}
+
+/*!
+ * Setup GPIO for LCDC device to be active
+ *
+ */
+void gpio_lcdc_active(void)
+{
+ gpio_request_mux(MX27_PIN_LSCLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD3, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD4, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD5, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD6, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD7, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD8, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD9, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD10, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD11, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD12, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD13, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD14, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD15, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD16, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_LD17, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_REV, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_PS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SPL_SPR, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_HSYNC, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_VSYNC, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_CONTRAST, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_OE_ACD, GPIO_MUX_PRIMARY);
+}
+
+/*!
+ * Setup GPIO for LCDC device to be inactive
+ *
+ */
+void gpio_lcdc_inactive(void)
+{
+ gpio_free_mux(MX27_PIN_LSCLK);
+ gpio_free_mux(MX27_PIN_LD0);
+ gpio_free_mux(MX27_PIN_LD1);
+ gpio_free_mux(MX27_PIN_LD2);
+ gpio_free_mux(MX27_PIN_LD3);
+ gpio_free_mux(MX27_PIN_LD4);
+ gpio_free_mux(MX27_PIN_LD5);
+ gpio_free_mux(MX27_PIN_LD6);
+ gpio_free_mux(MX27_PIN_LD7);
+ gpio_free_mux(MX27_PIN_LD8);
+ gpio_free_mux(MX27_PIN_LD9);
+ gpio_free_mux(MX27_PIN_LD10);
+ gpio_free_mux(MX27_PIN_LD11);
+ gpio_free_mux(MX27_PIN_LD12);
+ gpio_free_mux(MX27_PIN_LD13);
+ gpio_free_mux(MX27_PIN_LD14);
+ gpio_free_mux(MX27_PIN_LD15);
+ gpio_free_mux(MX27_PIN_LD16);
+ gpio_free_mux(MX27_PIN_LD17);
+ gpio_free_mux(MX27_PIN_REV);
+ gpio_free_mux(MX27_PIN_CLS);
+ gpio_free_mux(MX27_PIN_PS);
+ gpio_free_mux(MX27_PIN_SPL_SPR);
+ gpio_free_mux(MX27_PIN_HSYNC);
+ gpio_free_mux(MX27_PIN_VSYNC);
+ gpio_free_mux(MX27_PIN_CONTRAST);
+ gpio_free_mux(MX27_PIN_OE_ACD);
+}
+
+/*!
+ * Setup GPIO PA25 low to start hard reset FS453 TV encoder
+ *
+ */
+void gpio_fs453_reset_low(void)
+{
+ gpio_free_mux(MX27_PIN_CLS);
+ if (gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_GPIO)) {
+ printk(KERN_ERR "bug: request GPIO PA25 failed.\n");
+ return;
+ }
+
+ /* PA25 (CLS) as output */
+ mxc_set_gpio_direction(MX27_PIN_CLS, 0);
+ gpio_config_mux(MX27_PIN_CLS, GPIO_MUX_GPIO);
+ mxc_set_gpio_dataout(MX27_PIN_CLS, 0);
+}
+
+/*!
+ * Setup GPIO PA25 high to end hard reset FS453 TV encoder
+ *
+ */
+void gpio_fs453_reset_high(void)
+{
+ gpio_free_mux(MX27_PIN_CLS);
+ if (gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_GPIO)) {
+ printk(KERN_ERR "bug: request GPIO PA25 failed.\n");
+ return;
+ }
+
+ /* PA25 (CLS) as output */
+ mxc_set_gpio_direction(MX27_PIN_CLS, 0);
+ gpio_config_mux(MX27_PIN_CLS, GPIO_MUX_GPIO);
+ mxc_set_gpio_dataout(MX27_PIN_CLS, 1);
+}
+
+/*!
+ * This function configures the IOMux block for PMIC standard operations.
+ *
+ */
+void gpio_pmic_active(void)
+{
+ gpio_config_mux(MX27_PIN_TOUT, GPIO_MUX_GPIO);
+ mxc_set_gpio_direction(MX27_PIN_TOUT, 1);
+}
+
+/*!
+ * GPIO settings not required for keypad
+ *
+ */
+void gpio_keypad_active(void)
+{
+}
+
+/*!
+ * GPIO settings not required for keypad
+ *
+ */
+void gpio_keypad_inactive(void)
+{
+}
+
+/*!
+ * Setup GPIO for ATA device to be active
+ *
+ */
+void gpio_ata_active(void)
+{
+ gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA4, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA5, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA6, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA7, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA8, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA9, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA10, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA11, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA12, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA13, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA14, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA15, GPIO_MUX_PRIMARY);
+
+ gpio_request_mux(MX27_PIN_PC_CD1_B, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_CD2_B, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_WAIT_B, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_READY, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_PWRON, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_VS1, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_VS2, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_BVD1, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_BVD2, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_RST, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_IOIS16, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_RW_B, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_PC_POE, GPIO_MUX_ALT);
+
+ __raw_writew(PBC_BCTRL2_ATAFEC_EN | PBC_BCTRL2_ATAFEC_SEL |
+ PBC_BCTRL2_ATA_EN, PBC_BCTRL2_CLEAR_REG);
+}
+
+/*!
+ * Setup GPIO for ATA device to be inactive
+ *
+ */
+void gpio_ata_inactive(void)
+{
+ __raw_writew(PBC_BCTRL2_ATAFEC_EN | PBC_BCTRL2_ATAFEC_SEL |
+ PBC_BCTRL2_ATA_EN, PBC_BCTRL2_SET_REG);
+
+ gpio_free_mux(MX27_PIN_ATA_DATA0);
+ gpio_free_mux(MX27_PIN_ATA_DATA1);
+ gpio_free_mux(MX27_PIN_ATA_DATA2);
+ gpio_free_mux(MX27_PIN_ATA_DATA3);
+ gpio_free_mux(MX27_PIN_ATA_DATA4);
+ gpio_free_mux(MX27_PIN_ATA_DATA5);
+ gpio_free_mux(MX27_PIN_ATA_DATA6);
+ gpio_free_mux(MX27_PIN_ATA_DATA7);
+ gpio_free_mux(MX27_PIN_ATA_DATA8);
+ gpio_free_mux(MX27_PIN_ATA_DATA9);
+ gpio_free_mux(MX27_PIN_ATA_DATA10);
+ gpio_free_mux(MX27_PIN_ATA_DATA11);
+ gpio_free_mux(MX27_PIN_ATA_DATA12);
+ gpio_free_mux(MX27_PIN_ATA_DATA13);
+ gpio_free_mux(MX27_PIN_ATA_DATA14);
+ gpio_free_mux(MX27_PIN_ATA_DATA15);
+
+ gpio_free_mux(MX27_PIN_PC_CD1_B);
+ gpio_free_mux(MX27_PIN_PC_CD2_B);
+ gpio_free_mux(MX27_PIN_PC_WAIT_B);
+ gpio_free_mux(MX27_PIN_PC_READY);
+ gpio_free_mux(MX27_PIN_PC_PWRON);
+ gpio_free_mux(MX27_PIN_PC_VS1);
+ gpio_free_mux(MX27_PIN_PC_VS2);
+ gpio_free_mux(MX27_PIN_PC_BVD1);
+ gpio_free_mux(MX27_PIN_PC_BVD2);
+ gpio_free_mux(MX27_PIN_PC_RST);
+ gpio_free_mux(MX27_PIN_IOIS16);
+ gpio_free_mux(MX27_PIN_PC_RW_B);
+ gpio_free_mux(MX27_PIN_PC_POE);
+}
+
+/*!
+ * Setup GPIO for FEC device to be active
+ *
+ */
+void gpio_fec_active(void)
+{
+ gpio_request_mux(MX27_PIN_ATA_DATA15, GPIO_MUX_OUTPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA15, 0);
+ gpio_request_mux(MX27_PIN_ATA_DATA14, GPIO_MUX_OUTPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA14, 0);
+ gpio_request_mux(MX27_PIN_ATA_DATA13, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA13, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA12, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA12, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA11, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA11, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA10, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA10, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA9, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA9, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA8, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA8, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA7, GPIO_MUX_OUTPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA7, 0);
+
+ gpio_request_mux(MX27_PIN_ATA_DATA6, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_ATA_DATA5, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA5, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA4, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA4, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA3, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_INPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA2, 1);
+ gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_OUTPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA1, 0);
+ gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_OUTPUT1);
+ mxc_set_gpio_direction(MX27_PIN_ATA_DATA0, 0);
+ gpio_request_mux(MX27_PIN_SD3_CLK, GPIO_MUX_OUTPUT1);
+ mxc_set_gpio_direction(MX27_PIN_SD3_CLK, 0);
+ gpio_request_mux(MX27_PIN_SD3_CMD, GPIO_MUX_OUTPUT1);
+ mxc_set_gpio_direction(MX27_PIN_SD3_CMD, 0);
+
+ __raw_writew(PBC_BCTRL2_ATAFEC_EN, PBC_BCTRL2_CLEAR_REG);
+ __raw_writew(PBC_BCTRL2_ATAFEC_SEL, PBC_BCTRL2_SET_REG);
+}
+
+/*!
+ * Setup GPIO for FEC device to be inactive
+ *
+ */
+void gpio_fec_inactive(void)
+{
+ gpio_free_mux(MX27_PIN_ATA_DATA0);
+ gpio_free_mux(MX27_PIN_ATA_DATA1);
+ gpio_free_mux(MX27_PIN_ATA_DATA2);
+ gpio_free_mux(MX27_PIN_ATA_DATA3);
+ gpio_free_mux(MX27_PIN_ATA_DATA4);
+ gpio_free_mux(MX27_PIN_ATA_DATA5);
+ gpio_free_mux(MX27_PIN_ATA_DATA6);
+ gpio_free_mux(MX27_PIN_ATA_DATA7);
+ gpio_free_mux(MX27_PIN_ATA_DATA8);
+ gpio_free_mux(MX27_PIN_ATA_DATA9);
+ gpio_free_mux(MX27_PIN_ATA_DATA10);
+ gpio_free_mux(MX27_PIN_ATA_DATA11);
+ gpio_free_mux(MX27_PIN_ATA_DATA12);
+ gpio_free_mux(MX27_PIN_ATA_DATA13);
+ gpio_free_mux(MX27_PIN_ATA_DATA14);
+ gpio_free_mux(MX27_PIN_ATA_DATA15);
+
+ gpio_free_mux(MX27_PIN_SD3_CMD);
+ gpio_free_mux(MX27_PIN_SD3_CLK);
+}
+
+/*!
+ * Setup GPIO for SLCDC device to be active
+ *
+ */
+void gpio_slcdc_active(int type)
+{
+ switch (type) {
+ case 0:
+ gpio_request_mux(MX27_PIN_SSI3_CLK, GPIO_MUX_ALT); /* CLK */
+ gpio_request_mux(MX27_PIN_SSI3_TXDAT, GPIO_MUX_ALT); /* CS */
+ gpio_request_mux(MX27_PIN_SSI3_RXDAT, GPIO_MUX_ALT); /* RS */
+ gpio_request_mux(MX27_PIN_SSI3_FS, GPIO_MUX_ALT); /* D0 */
+ break;
+
+ case 1:
+ gpio_request_mux(MX27_PIN_SD2_D1, GPIO_MUX_GPIO); /* CLK */
+ gpio_request_mux(MX27_PIN_SD2_D2, GPIO_MUX_GPIO); /* D0 */
+ gpio_request_mux(MX27_PIN_SD2_D3, GPIO_MUX_GPIO); /* RS */
+ gpio_request_mux(MX27_PIN_SD2_CMD, GPIO_MUX_GPIO); /* CS */
+ break;
+
+ case 2:
+ gpio_request_mux(MX27_PIN_LD0, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD1, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD2, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD3, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD4, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD5, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD6, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD7, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD8, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD9, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD10, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD11, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD12, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD13, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD14, GPIO_MUX_GPIO);
+ gpio_request_mux(MX27_PIN_LD15, GPIO_MUX_GPIO);
+ break;
+
+ default:
+ break;
+ }
+
+ return;
+}
+
+/*!
+ * Setup GPIO for SLCDC device to be inactive
+ *
+ */
+void gpio_slcdc_inactive(int type)
+{
+ switch (type) {
+ case 0:
+ gpio_free_mux(MX27_PIN_SSI3_CLK); /* CLK */
+ gpio_free_mux(MX27_PIN_SSI3_TXDAT); /* CS */
+ gpio_free_mux(MX27_PIN_SSI3_RXDAT); /* RS */
+ gpio_free_mux(MX27_PIN_SSI3_FS); /* D0 */
+ break;
+
+ case 1:
+ gpio_free_mux(MX27_PIN_SD2_D1); /* CLK */
+ gpio_free_mux(MX27_PIN_SD2_D2); /* D0 */
+ gpio_free_mux(MX27_PIN_SD2_D3); /* RS */
+ gpio_free_mux(MX27_PIN_SD2_CMD); /* CS */
+ break;
+
+ case 2:
+ gpio_free_mux(MX27_PIN_LD0);
+ gpio_free_mux(MX27_PIN_LD1);
+ gpio_free_mux(MX27_PIN_LD2);
+ gpio_free_mux(MX27_PIN_LD3);
+ gpio_free_mux(MX27_PIN_LD4);
+ gpio_free_mux(MX27_PIN_LD5);
+ gpio_free_mux(MX27_PIN_LD6);
+ gpio_free_mux(MX27_PIN_LD7);
+ gpio_free_mux(MX27_PIN_LD8);
+ gpio_free_mux(MX27_PIN_LD9);
+ gpio_free_mux(MX27_PIN_LD10);
+ gpio_free_mux(MX27_PIN_LD11);
+ gpio_free_mux(MX27_PIN_LD12);
+ gpio_free_mux(MX27_PIN_LD13);
+ gpio_free_mux(MX27_PIN_LD14);
+ gpio_free_mux(MX27_PIN_LD15);
+ break;
+
+ default:
+ break;
+ }
+
+ return;
+}
+
+void gpio_ssi_active(int ssi_num)
+{
+ switch (ssi_num) {
+ case 0:
+ gpio_request_mux(MX27_PIN_SSI1_FS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SSI1_RXDAT, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SSI1_TXDAT, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SSI1_CLK, GPIO_MUX_PRIMARY);
+ gpio_set_puen(MX27_PIN_SSI1_FS, 0);
+ gpio_set_puen(MX27_PIN_SSI1_RXDAT, 0);
+ gpio_set_puen(MX27_PIN_SSI1_TXDAT, 0);
+ gpio_set_puen(MX27_PIN_SSI1_CLK, 0);
+ break;
+ case 1:
+ gpio_request_mux(MX27_PIN_SSI2_FS, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SSI2_RXDAT, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SSI2_TXDAT, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SSI2_CLK, GPIO_MUX_PRIMARY);
+ gpio_set_puen(MX27_PIN_SSI2_FS, 0);
+ gpio_set_puen(MX27_PIN_SSI2_RXDAT, 0);
+ gpio_set_puen(MX27_PIN_SSI2_TXDAT, 0);
+ gpio_set_puen(MX27_PIN_SSI2_CLK, 0);
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+/*!
+ * * Setup GPIO for a SSI port to be inactive
+ * *
+ * * @param ssi_num an SSI port num
+ */
+
+void gpio_ssi_inactive(int ssi_num)
+{
+ switch (ssi_num) {
+ case 0:
+ gpio_free_mux(MX27_PIN_SSI1_FS);
+ gpio_free_mux(MX27_PIN_SSI1_RXDAT);
+ gpio_free_mux(MX27_PIN_SSI1_TXDAT);
+ gpio_free_mux(MX27_PIN_SSI1_CLK);
+ break;
+ case 1:
+ gpio_free_mux(MX27_PIN_SSI2_FS);
+ gpio_free_mux(MX27_PIN_SSI2_RXDAT);
+ gpio_free_mux(MX27_PIN_SSI2_TXDAT);
+ gpio_free_mux(MX27_PIN_SSI2_CLK);
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+/*!
+ * Setup GPIO for SDHC to be active
+ *
+ * @param module SDHC module number
+ */
+void gpio_sdhc_active(int module)
+{
+ u16 data;
+ switch (module) {
+ case 0:
+ gpio_request_mux(MX27_PIN_SD1_CLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD1_CMD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD1_D0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD1_D1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD1_D2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD1_D3, GPIO_MUX_PRIMARY);
+ /* 22k pull up for sd1 dat3 pins */
+ data = __raw_readw(IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+ data |= 0x0c;
+ __raw_writew(data, IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+ /*mxc_clks_enable(SDHC1_CLK);
+ mxc_clks_enable(PERCLK2); */
+ break;
+ case 1:
+ gpio_request_mux(MX27_PIN_SD2_CLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD2_CMD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD2_D0, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD2_D1, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD2_D2, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD2_D3, GPIO_MUX_PRIMARY);
+ /* 22k pull up for sd2 pins */
+ data = __raw_readw(IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+ data &= ~0xfff0;
+ data |= 0xfff0;
+ __raw_writew(data, IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+ /*mxc_clks_enable(SDHC2_CLK);
+ mxc_clks_enable(PERCLK2); */
+ break;
+ case 2:
+ gpio_request_mux(MX27_PIN_SD3_CLK, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_SD3_CMD, GPIO_MUX_PRIMARY);
+ gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_ALT);
+ gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_ALT);
+ /*mxc_clks_enable(SDHC3_CLK);
+ mxc_clks_enable(PERCLK2); */
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ * Setup GPIO for SDHC1 to be inactive
+ *
+ * @param module SDHC module number
+ */
+void gpio_sdhc_inactive(int module)
+{
+ switch (module) {
+ case 0:
+ gpio_free_mux(MX27_PIN_SD1_CLK);
+ gpio_free_mux(MX27_PIN_SD1_CMD);
+ gpio_free_mux(MX27_PIN_SD1_D0);
+ gpio_free_mux(MX27_PIN_SD1_D1);
+ gpio_free_mux(MX27_PIN_SD1_D2);
+ gpio_free_mux(MX27_PIN_SD1_D3);
+ /*mxc_clks_disable(SDHC1_CLK); */
+ break;
+ case 1:
+ gpio_free_mux(MX27_PIN_SD2_CLK);
+ gpio_free_mux(MX27_PIN_SD2_CMD);
+ gpio_free_mux(MX27_PIN_SD2_D0);
+ gpio_free_mux(MX27_PIN_SD2_D1);
+ gpio_free_mux(MX27_PIN_SD2_D2);
+ gpio_free_mux(MX27_PIN_SD2_D3);
+ /*mxc_clks_disable(SDHC2_CLK); */
+ break;
+ case 2:
+ gpio_free_mux(MX27_PIN_SD3_CLK);
+ gpio_free_mux(MX27_PIN_SD3_CMD);
+ gpio_free_mux(MX27_PIN_ATA_DATA0);
+ gpio_free_mux(MX27_PIN_ATA_DATA1);
+ gpio_free_mux(MX27_PIN_ATA_DATA2);
+ gpio_free_mux(MX27_PIN_ATA_DATA3);
+ /*mxc_clks_disable(SDHC3_CLK); */
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Probe for the card. If present the GPIO data would be set.
+ */
+int sdhc_get_card_det_status(struct device *dev)
+{
+ return 0;
+}
+
+/*
+ * Return the card detect pin.
+ */
+int sdhc_init_card_det(int id)
+{
+ int ret = 0;
+ switch (id) {
+ case 0:
+ ret = EXPIO_INT_SD1_EN;
+ break;
+ case 1:
+ ret = EXPIO_INT_SD2_EN;
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
+/*
+ * Power on/off Sharp QVGA panel.
+ */
+void board_power_lcd(int on)
+{
+ if (on)
+ __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
+ else
+ __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
+}
+
+void gpio_owire_active(void)
+{
+ gpio_request_mux(MX27_PIN_RTCK, GPIO_MUX_ALT);
+}
+
+void gpio_owire_inactive(void)
+{
+ gpio_request_mux(MX27_PIN_RTCK, GPIO_MUX_PRIMARY);
+}
+
+EXPORT_SYMBOL(gpio_uart_active);
+EXPORT_SYMBOL(gpio_uart_inactive);
+EXPORT_SYMBOL(config_uartdma_event);
+EXPORT_SYMBOL(gpio_usbh1_active);
+EXPORT_SYMBOL(gpio_usbh1_inactive);
+EXPORT_SYMBOL(gpio_usbh2_active);
+EXPORT_SYMBOL(gpio_usbh2_inactive);
+EXPORT_SYMBOL(gpio_usbotg_hs_active);
+EXPORT_SYMBOL(gpio_usbotg_hs_inactive);
+EXPORT_SYMBOL(gpio_usbotg_fs_active);
+EXPORT_SYMBOL(gpio_usbotg_fs_inactive);
+EXPORT_SYMBOL(gpio_i2c_active);
+EXPORT_SYMBOL(gpio_i2c_inactive);
+EXPORT_SYMBOL(gpio_spi_active);
+EXPORT_SYMBOL(gpio_spi_inactive);
+EXPORT_SYMBOL(gpio_nand_active);
+EXPORT_SYMBOL(gpio_nand_inactive);
+EXPORT_SYMBOL(gpio_sensor_active);
+EXPORT_SYMBOL(gpio_sensor_inactive);
+EXPORT_SYMBOL(gpio_sensor_reset);
+EXPORT_SYMBOL(gpio_lcdc_active);
+EXPORT_SYMBOL(gpio_lcdc_inactive);
+EXPORT_SYMBOL(gpio_fs453_reset_low);
+EXPORT_SYMBOL(gpio_fs453_reset_high);
+EXPORT_SYMBOL(gpio_pmic_active);
+EXPORT_SYMBOL(gpio_keypad_active);
+EXPORT_SYMBOL(gpio_keypad_inactive);
+EXPORT_SYMBOL(gpio_ata_active);
+EXPORT_SYMBOL(gpio_ata_inactive);
+EXPORT_SYMBOL(gpio_fec_active);
+EXPORT_SYMBOL(gpio_fec_inactive);
+EXPORT_SYMBOL(gpio_slcdc_active);
+EXPORT_SYMBOL(gpio_slcdc_inactive);
+EXPORT_SYMBOL(gpio_ssi_active);
+EXPORT_SYMBOL(gpio_ssi_inactive);
+EXPORT_SYMBOL(gpio_sdhc_active);
+EXPORT_SYMBOL(gpio_sdhc_inactive);
+EXPORT_SYMBOL(sdhc_get_card_det_status);
+EXPORT_SYMBOL(sdhc_init_card_det);
+EXPORT_SYMBOL(board_power_lcd);
+EXPORT_SYMBOL(gpio_owire_active);
+EXPORT_SYMBOL(gpio_owire_inactive);
diff -urN linux-2.6.26/arch/arm/mach-mx27/mxc_pm.c linux-2.6.26-lab126/arch/arm/mach-mx27/mxc_pm.c
--- linux-2.6.26/arch/arm/mach-mx27/mxc_pm.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/mxc_pm.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,458 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup DPM_MX27 Power Management
+ * @ingroup MSL_MX27
+ */
+/*!
+ * @file mach-mx27/mxc_pm.c
+ *
+ * @brief This file contains the implementation of the Low-level power
+ * management driver. It modifies the registers of the PLL and clock module
+ * of the i.MX27.
+ *
+ * @ingroup DPM_MX27
+ */
+
+/*
+ * Include Files
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "crm_regs.h"
+
+/* Local defines */
+#define MAX_ARM_FREQ 400000000
+#define MAX_AHB_FREQ 133000000
+#define MAX_IPG_FREQ 66500000
+#define FREQ_COMP_TOLERANCE 100 /* tolerance percentage times 100 */
+#define MX27_LLPM_DEBUG 0
+
+/*
+ * Global variables
+ */
+#if 0
+/*!
+ * These variables hold the various clock values when the module is loaded.
+ * This is needed because these clocks are derived from MPLL and when MPLL
+ * output changes, these clocks need to be adjusted.
+ */
+static u32 perclk1, perclk2, perclk3, perclk4, nfcclk, cpuclk;
+
+/*!
+ * Compare two frequences using allowable tolerance
+ *
+ * The MX27 PLL can generate many frequencies. This function
+ * compares the generated frequency to the requested frequency
+ * and determines it they are within and acceptable tolerance.
+ *
+ * @param freq1 desired frequency
+ * @param freq2 generated frequency
+ *
+ * @return Returns 0 is frequencies are within talerance
+ * and non-zero is they are not.
+ */
+static s32 freq_equal(u32 freq1, u32 freq2)
+{
+ if (freq1 > freq2) {
+ return (freq1 - freq2) <= (freq1 / FREQ_COMP_TOLERANCE);
+ }
+ return (freq2 - freq1) <= (freq1 / FREQ_COMP_TOLERANCE);
+}
+
+/*!
+ * Select the PLL frequency based on the desired ARM frequency.
+ *
+ * The MPLL will be configured to output three frequencies, 400/333/266 MHz.
+ *
+ * @param armfreq Desired ARM frequency
+ *
+ * @return Returns one of the selected PLL frequency (400/333/266 MHz).
+ * Returns -1 on error.
+ *
+ */
+static s32 select_freq_pll(u32 armfreq)
+{
+ u32 div;
+
+ div = 266000000 / armfreq;
+ if ((div == 0) || (!freq_equal(armfreq, 266000000 / div))) {
+ div = 400000000 / armfreq;
+ if ((div == 0) || (!freq_equal(armfreq, 400000000 / div))) {
+ return -1;
+ }
+
+ return 400000000;
+ }
+
+ return 266000000;
+}
+
+/*!
+ * Check whether the desired ARM and AHB frequencies are valid.
+ *
+ * @param armfreq Desired ARM frequency
+ * @param ahbfreq Desired AHB frequency
+ *
+ * @return Returns 0 on success
+ * Return -1 on error
+ */
+static s32 mx27_pm_check_parameters(u32 armfreq, u32 ahbfreq)
+{
+ u32 ahbdiv;
+
+ /* No idea about minimum frequencies.. just a guess! */
+ if ((armfreq < 1000000) || (ahbfreq < 1000000)) {
+ printk("arm or ahb frequencies are less\n");
+ return -1;
+ }
+
+ if ((armfreq > MAX_ARM_FREQ) || (ahbfreq > MAX_AHB_FREQ)) {
+ printk("arm or ahb freq. are too much\n");
+ return -1;
+ }
+
+ /* AHB divider value is restricted to less than 8 */
+ ahbdiv = armfreq / ahbfreq;
+ if ((ahbdiv == 0) || (ahbdiv > 8)) {
+ printk("Invalid ahb frequency\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/*!
+ * Integer clock scaling
+ *
+ * Change the main ARM clock frequencies without changing the MPLL.
+ * The integer dividers (PRESC and BCLKDIV) are changed to obtain the
+ * desired frequency. Since NFC clock is derived from ARM frequency,
+ * NFCDIV is also adjusted.
+ *
+ * @param arm_freq Desired ARM frequency
+ * @param ahb_freq Desired AHB frequency
+ * @param pll_freq Current PLL frequency
+ *
+ * @return Returns 0
+ */
+static s32 mx27_pm_intscale(u32 arm_freq, u32 ahb_freq, s32 pll_freq)
+{
+ u32 pre_div, bclk_div, nfc_div;
+
+ /* Calculate ARM divider */
+ pre_div = pll_freq / arm_freq;
+ if (pre_div == 0)
+ pre_div = 1;
+
+ /* Calculate AHB divider */
+ bclk_div = arm_freq / ahb_freq;
+ if (bclk_div == 0)
+ bclk_div = 1;
+
+ if ((arm_freq / bclk_div) > ahb_freq)
+ bclk_div++;
+
+ /* NFC clock is dependent on ARM clock */
+ nfc_div = arm_freq / nfcclk;
+ if ((arm_freq / nfc_div) > nfcclk)
+ nfc_div++;
+
+ /* Adjust NFC divider */
+ mxc_set_clocks_div(NFC_CLK, nfc_div);
+
+#if MX27_LLPM_DEBUG
+ printk("DIVIDERS: PreDiv = %d BCLKDIV = %d \n", pre_div, bclk_div);
+ printk("Integer scaling\n");
+ printk("PLL = %d : ARM = %d: AHB = %d\n", pll_freq, arm_freq, ahb_freq);
+#endif
+
+ /*
+ * This part is tricky. What to adjust first (PRESC or BCLKDIV)?
+ * After trial and error, if current ARM frequency is greater than
+ * desired ARM frequency, then adjust PRESC first, else if current
+ * ARM frequency is less than desired ARM frequency, then adjust
+ * BCLKDIV first.
+ */
+ if (cpuclk > arm_freq) {
+ mxc_set_clocks_div(CPU_CLK, pre_div);
+ mxc_set_clocks_div(AHB_CLK, bclk_div);
+ } else {
+ mxc_set_clocks_div(AHB_CLK, bclk_div);
+ mxc_set_clocks_div(CPU_CLK, pre_div);
+ }
+
+ cpuclk = arm_freq;
+ mdelay(50);
+ return 0;
+}
+
+/*!
+ * Set dividers for various peripheral clocks.
+ *
+ * PERCLK1, PERCLK2, PERCLK3 and PERCLK4 are adjusted based on the MPLL
+ * output frequency.
+ *
+ * @param pll_freq Desired MPLL output frequency
+ */
+static void mx27_set_dividers(u32 pll_freq)
+{
+ s32 perdiv1, perdiv2, perdiv3, perdiv4;
+
+ perdiv1 = pll_freq / perclk1;
+ if ((pll_freq / perdiv1) > perclk1)
+ perdiv1++;
+
+ perdiv2 = pll_freq / perclk2;
+ if ((pll_freq / perdiv2) > perclk2)
+ perdiv2++;
+
+ perdiv3 = pll_freq / perclk3;
+ if ((pll_freq / perdiv3) > perclk3)
+ perdiv3++;
+
+ perdiv4 = pll_freq / perclk4;
+ if ((pll_freq / perdiv4) > perclk4)
+ perdiv4++;
+
+ mxc_set_clocks_div(PERCLK1, perdiv1);
+ mxc_set_clocks_div(PERCLK2, perdiv2);
+ mxc_set_clocks_div(PERCLK3, perdiv3);
+ mxc_set_clocks_div(PERCLK4, perdiv4);
+}
+
+/*!
+ * Change MPLL output frequency and adjust derived clocks to produce the
+ * desired frequencies.
+ *
+ * @param arm_freq Desired ARM frequency
+ * @param ahb_freq Desired AHB frequency
+ * @param org_pll Current PLL frequency
+ *
+ * @return Returns 0 on success
+ * Returns -1 on error
+ */
+static s32 mx27_pm_pllscale(u32 arm_freq, u32 ahb_freq, s32 org_pll)
+{
+ u32 mfi, mfn, mfd, pd = 1, cscr;
+ s32 pll_freq;
+
+ /* Obtain the PLL frequency for the desired ARM frequency */
+ pll_freq = select_freq_pll(arm_freq);
+ if (pll_freq == -1) {
+ return -1;
+ }
+
+ /* The MPCTL0 register values are programmed based on the oscillator */
+ cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR);
+ if ((cscr & CCM_CSCR_OSC26M) == 0) {
+ /* MPCTL0 register values are programmed for 400/266 MHz */
+ switch (pll_freq) {
+ case 400000000:
+ mfi = 7;
+ mfn = 9;
+ mfd = 12;
+ pd = 0;
+ break;
+
+ case 266000000:
+ mfi = 10;
+ mfn = 6;
+ mfd = 25;
+ break;
+
+ default:
+ return -1;
+ }
+ } else {
+ /* MPCTL0 register values are programmed for 400/266 MHz */
+ switch (pll_freq) {
+ case 400000000:
+ mfi = 12;
+ mfn = 2;
+ mfd = 3;
+ break;
+
+ case 266000000:
+ mfi = 8;
+ mfn = 10;
+ mfd = 31;
+ break;
+
+ default:
+ return -1;
+ }
+ }
+
+#if MX27_LLPM_DEBUG
+ printk("PLL scaling\n");
+ printk("PLL = %d : ARM = %d: AHB = %d\n", pll_freq, arm_freq, ahb_freq);
+#endif
+
+ /* Adjust the peripheral clock dividers for new PLL frequency */
+ mx27_set_dividers(pll_freq);
+
+ if (pll_freq > org_pll) {
+ /* Set the dividers first */
+ mx27_pm_intscale(arm_freq, ahb_freq, pll_freq);
+
+ /* Set the PLL */
+ mxc_pll_set(MCUPLL, mfi, pd, mfd, mfn);
+ mdelay(50);
+ } else {
+ /* Set the PLL first */
+ mxc_pll_set(MCUPLL, mfi, pd, mfd, mfn);
+ mdelay(50);
+
+ /* Set the dividers later */
+ mx27_pm_intscale(arm_freq, ahb_freq, pll_freq);
+ }
+
+ return 0;
+}
+#endif
+/*!
+ * Implement steps required to transition to low-power modes.
+ *
+ * @param mode The desired low-power mode. Possible values are,
+ * DOZE_MODE
+ * WAIT_MODE
+ * STOP_MODE
+ * DSM_MODE
+ */
+void mxc_pm_lowpower(s32 mode)
+{
+ u32 cscr;
+
+ local_irq_disable();
+
+ /* WAIT and DOZE execute WFI only */
+ switch (mode) {
+ case STOP_MODE:
+ case DSM_MODE:
+ /* Clear MPEN and SPEN to disable MPLL/SPLL */
+ cscr = __raw_readl(CCM_CSCR);
+ cscr &= 0xFFFFFFFC;
+ __raw_writel(cscr, CCM_CSCR);
+ break;
+ }
+
+ /* Executes WFI */
+ arch_idle();
+
+ local_irq_enable();
+}
+
+#if 0
+/*!
+ * Called to change the core frequency. This function internally decides
+ * whether to do integer scaling or pll scaling.
+ *
+ * @param arm_freq Desired ARM frequency
+ * @param ahb_freq Desired AHB frequency
+ * @param ipg_freq Desired IP frequency, constant AHB / 2 always.
+ *
+ * @return Returns 0 on success
+ * Returns -1 on error
+ */
+int mxc_pm_dvfs(unsigned long arm_freq, long ahb_freq, long ipg_freq)
+{
+ u32 divider;
+ s32 pll_freq, ret;
+ unsigned long flags;
+
+ if (mx27_pm_check_parameters(arm_freq, ahb_freq) != 0) {
+ return -1;
+ }
+
+ local_irq_save(flags);
+
+ /* Get the current PLL frequency */
+ pll_freq = mxc_pll_clock(MCUPLL);
+
+#if MX27_LLPM_DEBUG
+ printk("MCU PLL frequency is %d\n", pll_freq);
+#endif
+
+ /* Decide whether to do integer scaling or pll scaling */
+ if (arm_freq > pll_freq) {
+ /* Do PLL scaling */
+ ret = mx27_pm_pllscale(arm_freq, ahb_freq, pll_freq);
+ } else {
+ /* We need integer divider values */
+ divider = pll_freq / arm_freq;
+ if (!freq_equal(arm_freq, pll_freq / divider)) {
+ /* Do PLL scaling */
+ ret = mx27_pm_pllscale(arm_freq, ahb_freq, pll_freq);
+ } else {
+ /* Do integer scaling */
+ ret = mx27_pm_intscale(arm_freq, ahb_freq, pll_freq);
+ }
+ }
+
+ local_irq_restore(flags);
+ return ret;
+}
+#endif
+/*
+ * This API is not supported on i.MX27
+ */
+int mxc_pm_intscale(long armfreq, long ahbfreq, long ipfreq)
+{
+ return -MXC_PM_API_NOT_SUPPORTED;
+}
+
+/*
+ * This API is not supported on i.MX27
+ */
+int mxc_pm_pllscale(long armfreq, long ahbfreq, long ipfreq)
+{
+ return -MXC_PM_API_NOT_SUPPORTED;
+}
+
+/*!
+ * This function is used to load the module.
+ *
+ * @return Returns an Integer on success
+ */
+static int __init mxc_pm_init_module(void)
+{
+ printk(KERN_INFO "MX27: Power management module initialized\n");
+ return 0;
+}
+
+/*!
+ * This function is used to unload the module
+ */
+static void __exit mxc_pm_cleanup_module(void)
+{
+ printk(KERN_INFO "MX27: Power management module exit\n");
+}
+
+module_init(mxc_pm_init_module);
+module_exit(mxc_pm_cleanup_module);
+
+EXPORT_SYMBOL(mxc_pm_lowpower);
+//EXPORT_SYMBOL(mxc_pm_dvfs);
+EXPORT_SYMBOL(mxc_pm_pllscale);
+EXPORT_SYMBOL(mxc_pm_intscale);
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("i.MX27 low level PM driver");
+MODULE_LICENSE("GPL");
diff -urN linux-2.6.26/arch/arm/mach-mx27/pm.c linux-2.6.26-lab126/arch/arm/mach-mx27/pm.c
--- linux-2.6.26/arch/arm/mach-mx27/pm.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/pm.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,102 @@
+/*
+ * linux/arch/arm/mach-mx27/pm.c
+ *
+ * MX27 Power Management Routines
+ *
+ * Original code for the SA11x0:
+ * Copyright (c) 2001 Cliff Brake
+ *
+ * Modified for the PXA250 by Nicolas Pitre:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * Modified for the OMAP1510 by David Singleton:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * Cleanup 2004 for OMAP1510/1610 by Dirk Behme
+ *
+ * Modified for the MX27
+ * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include
+#include
+
+#include
+
+/*
+ * TODO: whatta save?
+ */
+
+static int mx27_suspend_enter(suspend_state_t state)
+{
+ pr_debug("Hi, from mx27_pm_enter\n");
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ mxc_pm_lowpower(STOP_MODE);
+ break;
+ case PM_SUSPEND_MEM:
+ mxc_pm_lowpower(DSM_MODE);
+ break;
+ default:
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * Called after processes are frozen, but before we shut down devices.
+ */
+static int mx27_suspend_prepare(void)
+{
+ return 0;
+}
+
+/*
+ * Called after devices are re-setup, but before processes are thawed.
+ */
+static void mx27_suspend_finish(void)
+{
+ return;
+}
+
+static int mx27_pm_valid(suspend_state_t state)
+{
+ return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
+struct platform_suspend_ops mx27_suspend_ops = {
+ .valid = mx27_pm_valid,
+ .prepare = mx27_suspend_prepare,
+ .enter = mx27_suspend_enter,
+ .finish = mx27_suspend_finish,
+};
+
+static int __init mx27_pm_init(void)
+{
+ pr_debug("Power Management for Freescale MX27\n");
+ suspend_set_ops(&mx27_suspend_ops);
+
+ return 0;
+}
+
+late_initcall(mx27_pm_init);
diff -urN linux-2.6.26/arch/arm/mach-mx27/serial.c linux-2.6.26-lab126/arch/arm/mach-mx27/serial.c
--- linux-2.6.26/arch/arm/mach-mx27/serial.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/serial.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,275 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+ * @file mach-mx27/serial.c
+ *
+ * @brief This file contains the UART initiliazation.
+ *
+ * @ingroup MSL_MX27
+ */
+#include
+#include
+#include
+#include
+#include
+#include "serial.h"
+#include "board-mx27ads.h"
+
+#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
+
+/*!
+ * This is an array where each element holds information about a UART port,
+ * like base address of the UART, interrupt numbers etc. This structure is
+ * passed to the serial_core.c file. Based on which UART is used, the core file
+ * passes back the appropriate port structure as an argument to the control
+ * functions.
+ */
+static uart_mxc_port mxc_ports[] = {
+ [0] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR),
+ .mapbase = UART1_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART1_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .ints_muxed = UART1_MUX_INTS,
+ .irqs = {UART1_INT2, UART1_INT3},
+ .mode = UART1_MODE,
+ .ir_mode = UART1_IR,
+ .enabled = UART1_ENABLED,
+ .hardware_flow = UART1_HW_FLOW,
+ .cts_threshold = UART1_UCR4_CTSTL,
+ .dma_enabled = UART1_DMA_ENABLE,
+ .dma_rxbuf_size = UART1_DMA_RXBUFSIZE,
+ .rx_threshold = UART1_UFCR_RXTL,
+ .tx_threshold = UART1_UFCR_TXTL,
+ .shared = UART1_SHARED_PERI,
+ .dma_tx_id = MXC_DMA_UART1_TX,
+ .dma_rx_id = MXC_DMA_UART1_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ .ir_tx_inv = MXC_IRDA_TX_INV,
+ .ir_rx_inv = MXC_IRDA_RX_INV,
+ },
+ [1] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR),
+ .mapbase = UART2_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART2_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .ints_muxed = UART2_MUX_INTS,
+ .irqs = {UART2_INT2, UART2_INT3},
+ .mode = UART2_MODE,
+ .ir_mode = UART2_IR,
+ .enabled = UART2_ENABLED,
+ .hardware_flow = UART2_HW_FLOW,
+ .cts_threshold = UART2_UCR4_CTSTL,
+ .dma_enabled = UART2_DMA_ENABLE,
+ .dma_rxbuf_size = UART2_DMA_RXBUFSIZE,
+ .rx_threshold = UART2_UFCR_RXTL,
+ .tx_threshold = UART2_UFCR_TXTL,
+ .shared = UART2_SHARED_PERI,
+ .dma_tx_id = MXC_DMA_UART2_TX,
+ .dma_rx_id = MXC_DMA_UART2_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ .ir_tx_inv = MXC_IRDA_TX_INV,
+ .ir_rx_inv = MXC_IRDA_RX_INV,
+ },
+ [2] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR),
+ .mapbase = UART3_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART3_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 2,
+ },
+ .ints_muxed = UART3_MUX_INTS,
+ .irqs = {UART3_INT2, UART3_INT3},
+ .mode = UART3_MODE,
+ .ir_mode = UART3_IR,
+ .enabled = UART3_ENABLED,
+ .hardware_flow = UART3_HW_FLOW,
+ .cts_threshold = UART3_UCR4_CTSTL,
+ .dma_enabled = UART3_DMA_ENABLE,
+ .dma_rxbuf_size = UART3_DMA_RXBUFSIZE,
+ .rx_threshold = UART3_UFCR_RXTL,
+ .tx_threshold = UART3_UFCR_TXTL,
+ .shared = UART3_SHARED_PERI,
+ .dma_tx_id = MXC_DMA_UART3_TX,
+ .dma_rx_id = MXC_DMA_UART3_RX,
+ .rxd_mux = MXC_UART_IR_RXDMUX,
+ .ir_tx_inv = MXC_IRDA_TX_INV,
+ .ir_rx_inv = MXC_IRDA_RX_INV,
+ },
+ [3] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART4_BASE_ADDR),
+ .mapbase = UART4_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART4_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 3,
+ },
+ .ints_muxed = UART4_MUX_INTS,
+ .irqs = {UART4_INT2, UART4_INT3},
+ .mode = UART4_MODE,
+ .ir_mode = UART4_IR,
+ .enabled = UART4_ENABLED,
+ .hardware_flow = UART4_HW_FLOW,
+ .cts_threshold = UART4_UCR4_CTSTL,
+ .dma_enabled = UART4_DMA_ENABLE,
+ .dma_rxbuf_size = UART4_DMA_RXBUFSIZE,
+ .rx_threshold = UART4_UFCR_RXTL,
+ .tx_threshold = UART4_UFCR_TXTL,
+ .shared = UART4_SHARED_PERI,
+ .dma_tx_id = MXC_DMA_UART4_TX,
+ .dma_rx_id = MXC_DMA_UART4_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ .ir_tx_inv = MXC_IRDA_TX_INV,
+ .ir_rx_inv = MXC_IRDA_RX_INV,
+ },
+ [4] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART5_BASE_ADDR),
+ .mapbase = UART5_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART5_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 4,
+ },
+ .ints_muxed = UART5_MUX_INTS,
+ .irqs = {UART5_INT2, UART5_INT3},
+ .mode = UART5_MODE,
+ .ir_mode = UART5_IR,
+ .enabled = UART5_ENABLED,
+ .hardware_flow = UART5_HW_FLOW,
+ .cts_threshold = UART5_UCR4_CTSTL,
+ .dma_enabled = UART5_DMA_ENABLE,
+ .dma_rxbuf_size = UART5_DMA_RXBUFSIZE,
+ .rx_threshold = UART5_UFCR_RXTL,
+ .tx_threshold = UART5_UFCR_TXTL,
+ .shared = UART5_SHARED_PERI,
+ .dma_tx_id = MXC_DMA_UART5_TX,
+ .dma_rx_id = MXC_DMA_UART5_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ .ir_tx_inv = MXC_IRDA_TX_INV,
+ .ir_rx_inv = MXC_IRDA_RX_INV,
+ },
+ [5] = {
+ .port = {
+ .membase = (void *)IO_ADDRESS(UART6_BASE_ADDR),
+ .mapbase = UART6_BASE_ADDR,
+ .iotype = SERIAL_IO_MEM,
+ .irq = UART6_INT1,
+ .fifosize = 32,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 5,
+ },
+ .ints_muxed = UART6_MUX_INTS,
+ .irqs = {UART6_INT2, UART6_INT3},
+ .mode = UART6_MODE,
+ .ir_mode = UART6_IR,
+ .enabled = UART6_ENABLED,
+ .hardware_flow = UART6_HW_FLOW,
+ .cts_threshold = UART6_UCR4_CTSTL,
+ .dma_enabled = UART6_DMA_ENABLE,
+ .dma_rxbuf_size = UART6_DMA_RXBUFSIZE,
+ .rx_threshold = UART6_UFCR_RXTL,
+ .tx_threshold = UART6_UFCR_TXTL,
+ .shared = UART6_SHARED_PERI,
+ .dma_tx_id = MXC_DMA_UART6_TX,
+ .dma_rx_id = MXC_DMA_UART6_RX,
+ .rxd_mux = MXC_UART_RXDMUX,
+ .ir_tx_inv = MXC_IRDA_TX_INV,
+ .ir_rx_inv = MXC_IRDA_RX_INV,
+ },
+};
+
+static struct platform_device mxc_uart_device1 = {
+ .name = "mxcintuart",
+ .id = 0,
+ .dev = {
+ .platform_data = &mxc_ports[0],
+ },
+};
+
+static struct platform_device mxc_uart_device2 = {
+ .name = "mxcintuart",
+ .id = 1,
+ .dev = {
+ .platform_data = &mxc_ports[1],
+ },
+};
+
+static struct platform_device mxc_uart_device3 = {
+ .name = "mxcintuart",
+ .id = 2,
+ .dev = {
+ .platform_data = &mxc_ports[2],
+ },
+};
+
+static struct platform_device mxc_uart_device4 = {
+ .name = "mxcintuart",
+ .id = 3,
+ .dev = {
+ .platform_data = &mxc_ports[3],
+ },
+};
+static struct platform_device mxc_uart_device5 = {
+ .name = "mxcintuart",
+ .id = 4,
+ .dev = {
+ .platform_data = &mxc_ports[4],
+ },
+};
+static struct platform_device mxc_uart_device6 = {
+ .name = "mxcintuart",
+ .id = 5,
+ .dev = {
+ .platform_data = &mxc_ports[5],
+ },
+};
+
+static int __init mxc_init_uart(void)
+{
+ /* Register all the MXC UART platform device structures */
+ platform_device_register(&mxc_uart_device1);
+ platform_device_register(&mxc_uart_device2);
+ platform_device_register(&mxc_uart_device3);
+
+ platform_device_register(&mxc_uart_device4);
+
+ platform_device_register(&mxc_uart_device5);
+ platform_device_register(&mxc_uart_device6);
+ return 0;
+}
+
+#else
+static int __init mxc_init_uart(void)
+{
+ return 0;
+}
+#endif
+
+arch_initcall(mxc_init_uart);
diff -urN linux-2.6.26/arch/arm/mach-mx27/serial.h linux-2.6.26-lab126/arch/arm/mach-mx27/serial.h
--- linux-2.6.26/arch/arm/mach-mx27/serial.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/serial.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ARCH_ARM_MACH_MX27_SERIAL_H__
+#define __ARCH_ARM_MACH_MX27_SERIAL_H__
+
+/*!
+ * @file mach-mx27/serial.h
+ *
+ * @ingroup MSL_MX27
+ */
+#include
+
+/* UART 1 configuration */
+/*!
+ * This option allows to choose either an interrupt-driven software controlled
+ * hardware flow control (set this option to 0) or hardware-driven hardware
+ * flow control (set this option to 1).
+ */
+#define UART1_HW_FLOW 1
+/*!
+ * This specifies the threshold at which the CTS pin is deasserted by the
+ * RXFIFO. Set this value in Decimal to anything from 0 to 32 for
+ * hardware-driven hardware flow control. Read the HW spec while specifying
+ * this value. When using interrupt-driven software controlled hardware
+ * flow control set this option to -1.
+ */
+#define UART1_UCR4_CTSTL 16
+/*!
+ * This is option to enable (set this option to 1) or disable DMA data transfer
+ */
+#define UART1_DMA_ENABLE 0
+/*!
+ * Specify the size of the DMA receive buffer. The buffer size should be same with
+ * sub buffer size which is defined in mxc_uart.c for all data can be transfered.
+ */
+#define UART1_DMA_RXBUFSIZE 128
+/*!
+ * Specify the MXC UART's Receive Trigger Level. This controls the threshold at
+ * which a maskable interrupt is generated by the RxFIFO. Set this value in
+ * Decimal to anything from 0 to 32. Read the HW spec while specifying this
+ * value.
+ */
+#define UART1_UFCR_RXTL 16
+/*!
+ * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at
+ * which a maskable interrupt is generated by the TxFIFO. Set this value in
+ * Decimal to anything from 0 to 32. Read the HW spec while specifying this
+ * value.
+ */
+#define UART1_UFCR_TXTL 16
+/* UART 2 configuration */
+#define UART2_HW_FLOW 1
+#define UART2_UCR4_CTSTL 16
+#define UART2_DMA_ENABLE 0
+#define UART2_DMA_RXBUFSIZE 512
+#define UART2_UFCR_RXTL 16
+#define UART2_UFCR_TXTL 16
+/* UART 3 configuration */
+#define UART3_HW_FLOW 0
+#define UART3_UCR4_CTSTL -1
+#define UART3_DMA_ENABLE 0
+#define UART3_DMA_RXBUFSIZE 512
+#define UART3_UFCR_RXTL 16
+#define UART3_UFCR_TXTL 16
+/* UART 4 configuration */
+#define UART4_HW_FLOW 1
+#define UART4_UCR4_CTSTL 16
+#define UART4_DMA_ENABLE 0
+#define UART4_DMA_RXBUFSIZE 512
+#define UART4_UFCR_RXTL 16
+#define UART4_UFCR_TXTL 16
+/* UART 5 configuration */
+#define UART5_HW_FLOW 1
+#define UART5_UCR4_CTSTL 16
+#define UART5_DMA_ENABLE 0
+#define UART5_DMA_RXBUFSIZE 512
+#define UART5_UFCR_RXTL 16
+#define UART5_UFCR_TXTL 16
+/* UART 6 configuration */
+#define UART6_HW_FLOW 1
+#define UART6_UCR4_CTSTL 16
+#define UART6_DMA_ENABLE 0
+#define UART6_DMA_RXBUFSIZE 512
+#define UART6_UFCR_RXTL 16
+#define UART6_UFCR_TXTL 16
+/*
+ * UART Chip level Configuration that a user may not have to edit. These
+ * configuration vary depending on how the UART module is integrated with
+ * the ARM core
+ */
+/*
+ * Is the MUXED interrupt output sent to the ARM core
+ */
+#define INTS_NOTMUXED 0
+#define INTS_MUXED 1
+/* UART 1 configuration */
+/*!
+ * This define specifies whether the muxed ANDed interrupt line or the
+ * individual interrupts from the UART port is integrated with the ARM core.
+ * There exists a define like this for each UART port. Valid values that can
+ * be used are \b INTS_NOTMUXED or \b INTS_MUXED.
+ */
+#define UART1_MUX_INTS INTS_MUXED
+/*!
+ * This define specifies the transmitter interrupt number or the interrupt
+ * number of the ANDed interrupt in case the interrupts are muxed. There exists
+ * a define like this for each UART port.
+ */
+#define UART1_INT1 MXC_INT_UART1
+/*!
+ * This define specifies the receiver interrupt number. If the interrupts of
+ * the UART are muxed, then we specify here a dummy value -1. There exists a
+ * define like this for each UART port.
+ */
+#define UART1_INT2 -1
+/*!
+ * This specifies the master interrupt number. If the interrupts of the UART
+ * are muxed, then we specify here a dummy value of -1. There exists a define
+ * like this for each UART port.
+ */
+#define UART1_INT3 -1
+/*!
+ * This specifies if the UART is a shared peripheral. It holds the shared
+ * peripheral number if it is shared or -1 if it is not shared. There exists
+ * a define like this for each UART port.
+ */
+#define UART1_SHARED_PERI -1
+/* UART 2 configuration */
+#define UART2_MUX_INTS INTS_MUXED
+#define UART2_INT1 MXC_INT_UART2
+#define UART2_INT2 -1
+#define UART2_INT3 -1
+#define UART2_SHARED_PERI -1
+/* UART 3 configuration */
+#define UART3_MUX_INTS INTS_MUXED
+#define UART3_INT1 MXC_INT_UART3
+#define UART3_INT2 -1
+#define UART3_INT3 -1
+#define UART3_SHARED_PERI -1
+/* UART 4 configuration */
+#define UART4_MUX_INTS INTS_MUXED
+#define UART4_INT1 MXC_INT_UART4
+#define UART4_INT2 -1
+#define UART4_INT3 -1
+#define UART4_SHARED_PERI -1
+/* UART 5 configuration */
+#define UART5_MUX_INTS INTS_MUXED
+#define UART5_INT1 MXC_INT_UART5
+#define UART5_INT2 -1
+#define UART5_INT3 -1
+#define UART5_SHARED_PERI -1
+/* UART 6 configuration */
+#define UART6_MUX_INTS INTS_MUXED
+#define UART6_INT1 MXC_INT_UART6
+#define UART6_INT2 -1
+#define UART6_INT3 -1
+#define UART6_SHARED_PERI -1
+
+#endif /* __ARCH_ARM_MACH_MX27_SERIAL_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx27/system.c linux-2.6.26-lab126/arch/arm/mach-mx27/system.c
--- linux-2.6.26/arch/arm/mach-mx27/system.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/system.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/*!
+ * @defgroup MSL_MX27 i.MX27 Machine Specific Layer (MSL)
+ */
+
+/*!
+ * @file mach-mx27/system.c
+ * @brief This file contains idle and reset functions.
+ *
+ * @ingroup MSL_MX27
+ */
+
+/*!
+ * This function puts the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks.
+ */
+ cpu_do_idle();
+}
+
+/*
+ * This function resets the system. It is called by machine_restart().
+ *
+ * @param mode indicates different kinds of resets
+ */
+void arch_reset(char mode)
+{
+ /* Assert Watchdog Reset signal */
+ mxc_wd_reset();
+}
diff -urN linux-2.6.26/arch/arm/mach-mx27/time.c linux-2.6.26-lab126/arch/arm/mach-mx27/time.c
--- linux-2.6.26/arch/arm/mach-mx27/time.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/time.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* System Timer Interrupt reconfigured to run in free-run mode.
+ * Author: Vitaly Wool
+ * Copyright 2004 MontaVista Software Inc.
+ */
+
+/*!
+ * @defgroup Timers_MX27 OS Tick Timer
+ * @ingroup MSL_MX27
+ */
+/*!
+ * @file mach-mx27/time.c
+ * @brief This file contains OS tick timer implementation.
+ *
+ * This file contains OS tick timer implementation.
+ *
+ * @ingroup Timers_MX27
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*!
+ * GPT register address definitions
+ */
+#define GPT_BASE_ADDR (IO_ADDRESS(GPT1_BASE_ADDR))
+#define MXC_GPT_GPTCR (GPT_BASE_ADDR + 0x00)
+#define MXC_GPT_GPTPR (GPT_BASE_ADDR + 0x04)
+#define MXC_GPT_GPTOCR1 (GPT_BASE_ADDR + 0x08)
+#define MXC_GPT_GPTICR1 (GPT_BASE_ADDR + 0x0C)
+#define MXC_GPT_GPTCNT (GPT_BASE_ADDR + 0x10)
+#define MXC_GPT_GPTSR (GPT_BASE_ADDR + 0x14)
+
+/*!
+ * GPT Control register bit definitions
+ */
+#define GPTCR_COMPEN (1 << 4)
+#define GPTCR_SWR (1 << 15)
+#define GPTCR_FRR (1 << 8)
+
+#define GPTCR_CLKSRC_SHIFT 1
+#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_HIGHFREQ (1 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLK32K (4 << GPTCR_CLKSRC_SHIFT)
+
+#define GPTCR_ENABLE (1 << 0)
+
+#define GPTSR_OF1 (1 << 0)
+
+extern unsigned long clk_early_get_timer_rate(void);
+
+static int mxc_gpt_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+{
+ unsigned long now, expires;
+ u32 reg;
+
+ now = __raw_readl(MXC_GPT_GPTCNT);
+ expires = now + cycles;
+ __raw_writel(expires, MXC_GPT_GPTOCR1);
+ __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
+
+ /* enable interrupt */
+ reg = __raw_readl(MXC_GPT_GPTCR);
+ reg |= GPTCR_COMPEN;
+ __raw_writel(reg, MXC_GPT_GPTCR);
+
+ return 0;
+}
+
+static void mxc_gpt_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ u32 reg;
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ panic("MXC GPT: CLOCK_EVT_MODE_PERIODIC not supported\n");
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ /* Disable interrupts */
+ reg = __raw_readl(MXC_GPT_GPTCR);
+ reg &= ~GPTCR_COMPEN;
+ __raw_writel(reg, MXC_GPT_GPTCR);
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
+}
+
+static struct clock_event_device gpt_clockevent = {
+ .name = "mxc_gpt",
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .rating = 300,
+ .shift = 32,
+ .set_next_event = mxc_gpt_set_next_event,
+ .set_mode = mxc_gpt_set_mode,
+};
+
+/*!
+ * This is the timer interrupt service routine to do required tasks.
+ * It also services the WDOG timer at the frequency of twice per WDOG
+ * timeout value. For example, if the WDOG's timeout value is 4 (2
+ * seconds since the WDOG runs at 0.5Hz), it will be serviced once
+ * every 2/2=1 second.
+ *
+ * @param irq GPT interrupt source number (not used)
+ * @param dev_id this parameter is not used
+ * @return always returns \b IRQ_HANDLED as defined in
+ * include/linux/interrupt.h.
+ */
+static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
+{
+ unsigned int gptsr;
+ u32 reg;
+
+ gptsr = __raw_readl(MXC_GPT_GPTSR);
+ if (gptsr & GPTSR_OF1) {
+ /* Disable interrupt */
+ reg = __raw_readl(MXC_GPT_GPTCR);
+ reg &= ~GPTCR_COMPEN;
+ __raw_writel(reg, MXC_GPT_GPTCR);
+ /* Clear interrupt */
+ __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
+
+ gpt_clockevent.event_handler(&gpt_clockevent);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*!
+ * The clockevents timer interrupt structure.
+ */
+static struct irqaction timer_irq = {
+ .name = "gpt-irq",
+ .flags = IRQF_DISABLED,
+ .handler = mxc_timer_interrupt,
+};
+
+static cycle_t __xipram mxc_gpt_read(void)
+{
+ return __raw_readl(MXC_GPT_GPTCNT);
+}
+
+static struct clocksource gpt_clocksrc = {
+ .name = "mxc_gpt",
+ .rating = 300,
+ .read = mxc_gpt_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 24,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_VALID_FOR_HRES,
+};
+
+/*!
+ * This function is used to initialize the GPT as a clocksource and clockevent.
+ * It is called by the start_kernel() during system startup.
+ */
+void __init mxc_init_time(void)
+{
+ int ret;
+ unsigned long rate;
+ u32 reg, div;
+
+ /* Reset GPT */
+ __raw_writel(GPTCR_SWR, MXC_GPT_GPTCR);
+ while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
+ mb();
+
+ /* Normal clk api are not yet initialized, so use early verion */
+ rate = clk_early_get_timer_rate();
+ if (rate == 0)
+ panic("MXC GPT: Can't get timer clock rate\n");
+
+#ifdef CLOCK_TICK_RATE
+ div = rate / CLOCK_TICK_RATE;
+ WARN_ON((div * CLOCK_TICK_RATE) != rate);
+#else /* Hopefully CLOCK_TICK_RATE will go away soon */
+ div = 1;
+ while ((rate / div) > 20000000) {
+ div++;
+ }
+#endif
+ rate /= div;
+ __raw_writel(div - 1, MXC_GPT_GPTPR);
+
+ reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_ENABLE;
+ __raw_writel(reg, MXC_GPT_GPTCR);
+
+ gpt_clocksrc.mult = clocksource_hz2mult(rate, gpt_clocksrc.shift);
+ ret = clocksource_register(&gpt_clocksrc);
+ if (ret < 0) {
+ goto err;
+ }
+
+ gpt_clockevent.mult = div_sc(rate, NSEC_PER_SEC, gpt_clockevent.shift);
+ gpt_clockevent.max_delta_ns = clockevent_delta2ns(-1, &gpt_clockevent);
+ gpt_clockevent.min_delta_ns = clockevent_delta2ns(1, &gpt_clockevent);
+
+ gpt_clockevent.cpumask = cpumask_of_cpu(0);
+ clockevents_register_device(&gpt_clockevent);
+
+ ret = setup_irq(MXC_INT_GPT, &timer_irq);
+ if (ret < 0) {
+ goto err;
+ }
+
+ pr_info("MXC GPT timer initialized, rate = %lu\n", rate);
+ return;
+ err:
+ panic("Unable to initialize timer\n");
+}
+
+struct sys_timer mxc_timer = {
+ .init = mxc_init_time,
+};
diff -urN linux-2.6.26/arch/arm/mach-mx27/usb.h linux-2.6.26-lab126/arch/arm/mach-mx27/usb.h
--- linux-2.6.26/arch/arm/mach-mx27/usb.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb.h 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+extern int usbotg_init(struct platform_device *pdev);
+extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
+extern int gpio_usbotg_fs_active(void);
+extern void gpio_usbotg_fs_inactive(void);
+extern int gpio_usbotg_hs_active(void);
+extern void gpio_usbotg_hs_inactive(void);
+extern struct platform_device *host_pdev_register(struct resource *res,
+ int n_res, struct fsl_usb2_platform_data *config);
+
+extern int fsl_usb_host_init(struct platform_device *pdev);
+extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
+extern int gpio_usbh1_active(void);
+extern void gpio_usbh1_inactive(void);
+extern int gpio_usbh2_active(void);
+extern void gpio_usbh2_inactive(void);
+
+/*
+ * Determine which platform_data struct to use, based on which
+ * transceiver is configured.
+ * PDATA is a pointer to it.
+ */
+#if defined(CONFIG_ISP1504_MXC)
+static struct fsl_usb2_platform_data __maybe_unused dr_1504_config;
+#define PDATA (&dr_1504_config)
+#elif defined(CONFIG_ISP1301_MXC)
+static struct fsl_usb2_platform_data __maybe_unused dr_1301_config;
+#define PDATA (&dr_1301_config)
+#elif defined(CONFIG_MC13783_MXC)
+static struct fsl_usb2_platform_data __maybe_unused dr_13783_config;
+#define PDATA (&dr_13783_config)
+#endif
+
+
+/*
+ * Used to set pdata->operating_mode before registering the platform_device.
+ * If OTG is configured, the controller operates in OTG mode,
+ * otherwise it's either host or device.
+ */
+#ifdef CONFIG_USB_OTG
+#define DR_UDC_MODE FSL_USB2_DR_OTG
+#define DR_HOST_MODE FSL_USB2_DR_OTG
+#else
+#define DR_UDC_MODE FSL_USB2_DR_DEVICE
+#define DR_HOST_MODE FSL_USB2_DR_HOST
+#endif
+
+
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+static inline void dr_register_host(struct resource *r, int rs)
+{
+ PDATA->operating_mode = DR_HOST_MODE;
+ host_pdev_register(r, rs, PDATA);
+}
+#else
+static inline void dr_register_host(struct resource *r, int rs)
+{
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET_ARC
+static struct platform_device dr_udc_device;
+
+static inline void dr_register_udc(void)
+{
+ PDATA->operating_mode = DR_UDC_MODE;
+ dr_udc_device.dev.platform_data = PDATA;
+
+ if (platform_device_register(&dr_udc_device))
+ printk(KERN_ERR "usb: can't register DR gadget\n");
+ else
+ printk(KERN_INFO "usb: DR gadget (%s) registered\n",
+ PDATA->transceiver);
+}
+#else
+static inline void dr_register_udc(void)
+{
+}
+#endif
+
+#ifdef CONFIG_USB_OTG
+static struct platform_device dr_otg_device;
+
+/*
+ * set the proper operating_mode and
+ * platform_data pointer, then register the
+ * device.
+ */
+static inline void dr_register_otg(void)
+{
+ PDATA->operating_mode = FSL_USB2_DR_OTG;
+ dr_otg_device.dev.platform_data = PDATA;
+
+ if (platform_device_register(&dr_otg_device))
+ printk(KERN_ERR "usb: can't register otg device\n");
+ else
+ printk(KERN_INFO "usb: DR OTG registered\n");
+}
+#else
+static inline void dr_register_otg(void)
+{
+}
+#endif
diff -urN linux-2.6.26/arch/arm/mach-mx27/usb_dr.c linux-2.6.26-lab126/arch/arm/mach-mx27/usb_dr.c
--- linux-2.6.26/arch/arm/mach-mx27/usb_dr.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb_dr.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,126 @@
+#define DEBUG
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "usb.h"
+
+/*
+ * platform data structs
+ * - Which one to use is determined by CONFIG options in usb.h
+ * - operating_mode plugged at run time
+ */
+static struct fsl_usb2_platform_data __maybe_unused dr_13783_config = {
+ .name = "DR",
+ .platform_init = usbotg_init,
+ .platform_uninit = usbotg_uninit,
+ .phy_mode = FSL_USB2_PHY_SERIAL,
+ .power_budget = 500, /* 500 mA max power */
+ .gpio_usb_active = gpio_usbotg_fs_active,
+ .gpio_usb_inactive = gpio_usbotg_fs_inactive,
+ .transceiver = "mc13783",
+};
+
+static struct fsl_usb2_platform_data __maybe_unused dr_1301_config = {
+ .name = "DR",
+ .platform_init = usbotg_init,
+ .platform_uninit = usbotg_uninit,
+ .phy_mode = FSL_USB2_PHY_SERIAL,
+ .power_budget = 500, /* 500 mA max power */
+ .gpio_usb_active = gpio_usbotg_fs_active,
+ .gpio_usb_inactive = gpio_usbotg_fs_inactive,
+ .transceiver = "isp1301",
+};
+
+static struct fsl_usb2_platform_data __maybe_unused dr_1504_config = {
+ .name = "DR",
+ .platform_init = usbotg_init,
+ .platform_uninit = usbotg_uninit,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+ .power_budget = 500, /* 500 mA max power */
+ .gpio_usb_active = gpio_usbotg_hs_active,
+ .gpio_usb_inactive = gpio_usbotg_hs_inactive,
+ .transceiver = "isp1504",
+};
+
+
+/*
+ * resources
+ */
+static struct resource otg_resources[] = {
+ [0] = {
+ .start = (u32)(USB_OTGREGS_BASE),
+ .end = (u32)(USB_OTGREGS_BASE + 0x1ff),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_USB3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+
+static u64 dr_udc_dmamask = ~(u32) 0;
+static void dr_udc_release(struct device *dev)
+{
+}
+
+static u64 dr_otg_dmamask = ~(u32) 0;
+static void dr_otg_release(struct device *dev)
+{
+}
+
+/*
+ * platform device structs
+ * dev.platform_data field plugged at run time
+ */
+static struct platform_device __maybe_unused dr_udc_device = {
+ .name = "fsl-usb2-udc",
+ .id = -1,
+ .dev = {
+ .release = dr_udc_release,
+ .dma_mask = &dr_udc_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .resource = otg_resources,
+ .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+static struct platform_device __maybe_unused dr_otg_device = {
+ .name = "fsl-usb2-otg",
+ .id = -1,
+ .dev = {
+ .release = dr_otg_release,
+ .dma_mask = &dr_otg_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .resource = otg_resources,
+ .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+static int __init usb_dr_init(void)
+{
+ pr_debug("%s: \n", __func__);
+
+ dr_register_otg();
+ dr_register_host(otg_resources, ARRAY_SIZE(otg_resources));
+ dr_register_udc();
+
+ return 0;
+}
+
+module_init(usb_dr_init);
diff -urN linux-2.6.26/arch/arm/mach-mx27/usb_h1.c linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h1.c
--- linux-2.6.26/arch/arm/mach-mx27/usb_h1.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h1.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "usb.h"
+
+static struct fsl_usb2_platform_data usbh1_config = {
+ .name = "Host 1",
+ .platform_init = fsl_usb_host_init,
+ .platform_uninit = fsl_usb_host_uninit,
+ .operating_mode = FSL_USB2_MPH_HOST,
+ .phy_mode = FSL_USB2_PHY_SERIAL,
+ .power_budget = 500, /* 500 mA max power */
+ .gpio_usb_active = gpio_usbh1_active,
+ .gpio_usb_inactive = gpio_usbh1_inactive,
+ .transceiver = "serial",
+};
+
+static struct resource usbh1_resources[] = {
+ [0] = {
+ .start = (u32) (USB_H1REGS_BASE),
+ .end = (u32) (USB_H1REGS_BASE + 0x1ff),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_USB1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static int __init usbh1_init(void)
+{
+ pr_debug("%s: \n", __func__);
+
+ host_pdev_register(usbh1_resources, ARRAY_SIZE(usbh1_resources),
+ &usbh1_config);
+ return 0;
+}
+module_init(usbh1_init);
diff -urN linux-2.6.26/arch/arm/mach-mx27/usb_h2.c linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h2.c
--- linux-2.6.26/arch/arm/mach-mx27/usb_h2.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h2.c 2010-08-10 04:14:09.000000000 -0400
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "usb.h"
+
+static struct fsl_usb2_platform_data usbh2_config = {
+ .name = "Host 2",
+ .platform_init = fsl_usb_host_init,
+ .platform_uninit = fsl_usb_host_uninit,
+ .operating_mode = FSL_USB2_MPH_HOST,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+ .power_budget = 500, /* 500 mA max power */
+ .gpio_usb_active = gpio_usbh2_active,
+ .gpio_usb_inactive = gpio_usbh2_inactive,
+ .transceiver = "isp1504",
+};
+
+static struct resource usbh2_resources[] = {
+ [0] = {
+ .start = (u32) (USB_H2REGS_BASE),
+ .end = (u32) (USB_H2REGS_BASE + 0x1ff),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_USB2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static int __init usbh2_init(void)
+{
+ pr_debug("%s: \n", __func__);
+
+ host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources),
+ &usbh2_config);
+ return 0;
+}
+module_init(usbh2_init);
diff -urN linux-2.6.26/arch/arm/mach-mx3/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx3/Kconfig
--- linux-2.6.26/arch/arm/mach-mx3/Kconfig 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/Kconfig 2010-08-10 04:14:16.000000000 -0400
@@ -1,12 +1,100 @@
menu "MX3 Options"
depends on ARCH_MX3
+config MX3_OPTIONS
+ bool
+ default y
+ select CPU_V6
+ select CACHE_L2X0
+ select OUTER_CACHE
+ select USB_ARCH_HAS_EHCI
+ select ARCH_HAS_EVTMON
+ select ARCH_HAS_RNGA
+
config MACH_MX31ADS
bool "Support MX31ADS platforms"
- default y
help
Include support for MX31ADS platform. This includes specific
configurations for the board and its peripherals.
+config MACH_MX31_3DS
+ bool "Support MX31/MX32 3-Stack platforms"
+ help
+ Include support for MX31/MX32 3-Stack platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MX3_DOZE_DURING_IDLE
+ bool "Enter Doze mode during idle"
+ help
+ Turning on this option will put the CPU into Doze mode during idle.
+ The default is to enter Wait mode during idle. Doze mode during
+ idle will save additional power over Wait mode.
+
+config MXC_SDMA_API
+ bool "Use SDMA API"
+ default y
+ help
+ This selects the Freescale MXC SDMA API.
+ If unsure, say N.
+
+menu "SDMA options"
+ depends on MXC_SDMA_API
+
+config SDMA_IRAM
+ bool "Use Internal RAM for SDMA transfer"
+ default n
+ help
+ Support Internal RAM as SDMA buffer or control structures
+
+config SDMA_IRAM_SIZE
+ hex "Reserved bytes of IRAM for SDMA (0x800-0x2000)"
+ range 0x800 0x2000
+ depends on SDMA_IRAM
+ default "0x1000"
+ help
+ Set the size of IRAM for SDMA. It must be multiple of 512bytes.
+endmenu
+
+config ARCH_MXC_HAS_NFC_V1
+ bool "MXC NFC Hardware Version 1"
+ depends on !(MACH_MX31ADS && XIP_KERNEL)
+ default y
+ help
+ This selects the Freescale MXC Nand Flash Controller Hardware Version 1
+ If unsure, say N.
+
+config ARCH_MXC_HAS_NFC_V2
+ bool "MXC NFC Hardware Version 2"
+ depends on !(MACH_MX31ADS && XIP_KERNEL)
+ default y
+ help
+ This selects the Freescale MXC Nand Flash Controller Hardware Version 2
+ If unsure, say N.
+
+menu "Device options"
+
+config I2C_MXC_SELECT1
+ bool "Enable I2C1 module"
+ default y
+ depends on I2C_MXC
+ help
+ Enable MX31 I2C1 module.
+
+config I2C_MXC_SELECT2
+ bool "Enable I2C2 module"
+ default n
+ depends on I2C_MXC
+ help
+ Enable MX31 I2C2 module.
+
+config I2C_MXC_SELECT3
+ bool "Enable I2C3 module"
+ default n
+ depends on I2C_MXC
+ help
+ Enable MX31 I2C3 module.
+
+endmenu
+
endmenu
diff -urN linux-2.6.26/arch/arm/mach-mx3/Makefile linux-2.6.26-lab126/arch/arm/mach-mx3/Makefile
--- linux-2.6.26/arch/arm/mach-mx3/Makefile 2008-07-13 17:51:29.000000000 -0400
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/Makefile 2010-08-10 04:14:16.000000000 -0400
@@ -4,5 +4,17 @@
# Object file lists.
-obj-y := mm.o time.o
-obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
+obj-y := system.o iomux.o cpu.o mm.o clock.o dptc.o devices.o serial.o dma.o mxc_pm.o dvfs_v2.o
+obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o mx31ads_gpio.o
+obj-$(CONFIG_MACH_MX31_3DS) += mx3_3stack.o mx3_3stack_gpio.o
+
+# power management
+obj-$(CONFIG_PM) += pm.o
+
+obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o
+obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o
+
+ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),)
+ obj-y += usb_dr.o
+endif
+
diff -urN linux-2.6.26/arch/arm/mach-mx3/board-mx31ads.h linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx31ads.h
--- linux-2.6.26/arch/arm/mach-mx3/board-mx31ads.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx31ads.h 2010-08-10 04:14:16.000000000 -0400
@@ -0,0 +1,326 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+
+#ifdef CONFIG_MACH_MX31ADS
+/*!
+ * @defgroup BRDCFG_MX31 Board Configuration Options
+ * @ingroup MSL_MX31
+ */
+
+/*!
+ * @file mach-mx3/board-mx31ads.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX31 ADS Platform.
+ *
+ * @ingroup BRDCFG_MX31
+ */
+
+/*
+ * Include Files
+ */
+#include
+
+/*!
+ * @name MXC UART EVB board level configurations
+ */
+/*! @{ */
+/*!
+ * Specifies if the Irda transmit path is inverting
+ */
+#define MXC_IRDA_TX_INV 0
+/*!
+ * Specifies if the Irda receive path is inverting
+ */
+#define MXC_IRDA_RX_INV 0
+
+/* UART 1 configuration */
+/*!
+ * This define specifies if the UART port is configured to be in DTE or
+ * DCE mode. There exists a define like this for each UART port. Valid
+ * values that can be used are \b MODE_DTE or \b MODE_DCE.
+ */
+#define UART1_MODE MODE_DCE
+/*!
+ * This define specifies if the UART is to be used for IRDA. There exists a
+ * define like this for each UART port. Valid values that can be used are
+ * \b IRDA or \b NO_IRDA.
+ */
+#define UART1_IR NO_IRDA
+/*!
+ * This define is used to enable or disable a particular UART port. If
+ * disabled, the UART will not be registered in the file system and the user
+ * will not be able to access it. There exists a define like this for each UART
+ * port. Specify a value of 1 to enable the UART and 0 to disable it.
+ */
+#define UART1_ENABLED 1
+/*! @} */
+/* UART 2 configuration */
+#define UART2_MODE MODE_DCE
+#define UART2_IR IRDA
+#ifdef CONFIG_MXC_FIR_MODULE
+#define UART2_ENABLED 0
+#else
+#define UART2_ENABLED 1
+#endif
+/* UART 3 configuration */
+#define UART3_MODE MODE_DTE
+#define UART3_IR NO_IRDA
+#define UART3_ENABLED 1
+/* UART 4 configuration */
+#define UART4_MODE MODE_DTE
+#define UART4_IR NO_IRDA
+#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */
+/* UART 5 configuration */
+#define UART5_MODE MODE_DTE
+#define UART5_IR NO_IRDA
+#define UART5_ENABLED 1
+
+#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x10000)
+#define MXC_LL_EXTUART_VADDR CS4_IO_ADDRESS(MXC_LL_EXTUART_PADDR)
+#undef MXC_LL_EXTUART_16BIT_BUS
+
+#define MXC_LL_UART_PADDR UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+/*!
+ * @name PBC Controller parameters
+ */
+/*! @{ */
+/*!
+ * Base address of PBC controller
+ */
+#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
+/* Offsets for the PBC Controller register */
+/*!
+ * PBC Board status register offset
+ */
+#define PBC_BSTAT 0x000002
+/*!
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET 0x000004
+/*!
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR 0x000006
+/*!
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET 0x000008
+/*!
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR 0x00000A
+/*!
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET 0x00000C
+/*!
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR 0x00000E
+/*!
+ * PBC Board control register 4 set address.
+ */
+#define PBC_BCTRL4_SET 0x000010
+/*!
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR 0x000012
+/*!
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1 0x000014
+/*!
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS 0x000016
+/*!
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS 0x000018
+/*!
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET 0x00001A
+/*!
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR 0x00001C
+
+/*!
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA 0x010000
+/*!
+ * External UART B.
+ */
+#define PBC_SC16C652_UARTB 0x010010
+/*!
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE 0x020000
+/*!
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE 0x021000
+/*!
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE 0x022000
+/*!
+ * External chip select 0.
+ */
+#define PBC_XCS0 0x040000
+/*!
+ * LCD Display enable.
+ */
+#define PBC_LCD_EN_B 0x060000
+/*!
+ * Code test debug enable.
+ */
+#define PBC_CODE_B 0x070000
+/*!
+ * PSRAM memory select.
+ */
+#define PBC_PSRAM_B 0x5000000
+
+/* PBC Board Status Register 1 bit definitions */
+#define PBC_BSTAT1_NF_DET 0x0001 /* NAND flash card. 0 = connected */
+#define PBC_BSTAT1_KP_ON 0x0002 /* KPP board. 0 = connected */
+#define PBC_BSTAT1_LS 0x0004 /* KPP:LightSense signal */
+#define PBC_BSTAT1_ATA_IOCS16 0x0008 /* ATA_IOCS16 signal */
+#define PBC_BSTAT1_ATA_CBLID 0x0010 /* ATA_CBLID signal */
+#define PBC_BSTAT1_ATA_DASP 0x0020 /* ATA_DASP signal */
+#define PBC_BSTAT1_PWR_RDY 0x0040 /* MC13783 power. 1 = ready */
+#define PBC_BSTAT1_SD1_WP 0x0080 /* 0 = SD1 card is write protected */
+#define PBC_BSTAT1_SD2_WP 0x0100 /* 0 = SD2 card is write protected */
+#define PBC_BSTAT1_FS1 0x0200 /* KPP:FlipSense1 signal */
+#define PBC_BSTAT1_FS2 0x0400 /* KPP:FlipSense2 signal */
+#define PBC_BSTAT1_PTT 0x0800 /* KPP:PTT signal */
+#define PBC_BSTAT1_MC13783_IN 0x1000 /* MC13783 board. 0 = connected. */
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
+#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
+#define PBC_BCTRL1_UENA 0x0004 /* Enable UART A transceiver */
+#define PBC_BCTRL1_UENB 0x0008 /* Enable UART B transceiver */
+#define PBC_BCTRL1_UENCE 0x0010 /* Enable UART CE transceiver */
+#define PBC_BCTRL1_IREN 0x0020 /* Enable the IRDA transmitter */
+#define PBC_BCTRL1_LED0 0x0040 /* Used to control LED 0 (green) */
+#define PBC_BCTRL1_LED1 0x0080 /* Used to control LED 1 (yellow) */
+#define PBC_BCTRL1_SENSOR1_ON 0x0600 /* Enable Sensor 1 */
+#define PBC_BCTRL1_SENSOR2_ON 0x3000 /* Enable Sensor 2 */
+#define PBC_BCTRL1_BEND 0x4000 /* Big Endian Select */
+#define PBC_BCTRL1_LCDON 0x8000 /* Enable the LCD */
+
+/* PBC Board Control Register 2 bit definitions */
+#define PBC_BCTRL2_USELA 0x0001 /* UART A Select, 0 = UART1, 1 = UART5 */
+#define PBC_BCTRL2_USELB 0x0002 /* UART B Select, 0 = UART3, 1 = UART5 */
+#define PBC_BCTRL2_USELC 0x0004 /* UART C Select, 0 = UART2, 1 = UART1 */
+#define PBC_BCTRL2_UMODENA 0x0008 /* UART A Modem Signals Enable, 0 = enabled */
+#define PBC_BCTRL2_UMODENC 0x0008 /* UART C Modem Signals Enable, 0 = enabled */
+#define PBC_BCTRL2_CSI_EN 0x0020 /* Enable the CSI interface, 0 = enabled */
+#define PBC_BCTRL2_ATA_EN 0x0040 /* Enable the ATA interface, 0 = enabled */
+#define PBC_BCTRL2_ATA_SEL 0x0080 /* ATA Select, 0 = group A, 1 = group B */
+#define PBC_BCTRL2_IRDA_MOD 0x0100 /* IRDA Mode (see CPLD spec) */
+#define PBC_BCTRL2_LDC_RST0 0x0200 /* LCD 0 Reset, 1 = reset signal asserted */
+#define PBC_BCTRL2_LDC_RST1 0x0400 /* LCD 1 Reset, 1 = reset signal asserted */
+#define PBC_BCTRL2_LDC_RST2 0x0800 /* LCD 2 Reset, 1 = reset signal asserted */
+#define PBC_BCTRL2_LDCIO_EN 0x1000 /* LCD GPIO Enable, 0 = enabled */
+#define PBC_BCTRL2_CT_CS 0x2000 /* Code Test Chip Select, = Code Test selected */
+#define PBC_BCTRL2_VPP_EN 0x4000 /* PCMCIA VPP Enable, 1 = power on */
+#define PBC_BCTRL2_VCC_EN 0x8000 /* PCMCIA VCC Enable, 1 = power on */
+
+/* PBC Board Control Register 3 bit definitions */
+#define PBC_BCTRL3_OTG_FS_SEL 0x0001 /* USB OTG Full Speed Select, 0 = PMIC, 1 = CPU */
+#define PBC_BCTRL3_OTG_FS_EN 0x0002 /* USB OTG Full Speed Enable, 0 = enabled */
+#define PBC_BCTRL3_FSH_SEL 0x0004 /* USB Full Speed Host Select, 0 = Group A, 1 = Group B */
+#define PBC_BCTRL3_FSH_EN 0x0008 /* USB Full Speed Host Enable, 0 = enabled */
+#define PBC_BCTRL3_HSH_SEL 0x0010 /* USB High Speed Host Select, 0 = Group A, 1 = Group B */
+#define PBC_BCTRL3_HSH_EN 0x0020 /* USB High Speed Host Enable, 0 = enabled */
+#define PBC_BCTRL3_FSH_MOD 0x0040 /* USB Full Speed Host Mode, 0 = Differential, 1 = Single ended */
+#define PBC_BCTRL3_OTG_HS_EN 0x0080 /* USB OTG High Speed Enable, 0 = enabled */
+#define PBC_BCTRL3_OTG_VBUS_EN 0x0100 /* USB OTG VBUS Regulator Enable, 0 = enabled */
+#define PBC_BCTRL3_FSH_VBUS_EN 0x0200 /* USB Full Speed Host VBUS Regulator Enable, 0 = enabled */
+#define PBC_BCTRL3_CARD1_SEL 0x0400 /* Card1 Select, 0 = SD1, 1 = MS1 */
+#define PBC_BCTRL3_CARD2_SEL 0x0800 /* Card2 Select, 0 = PCMCIA & SD2, 1 = MS2 */
+#define PBC_BCTRL3_SYNTH_RST 0x1000 /* Audio Synthesizer Reset, 0 = reset asserted */
+#define PBC_BCTRL3_VSIM_EN 0x2000 /* VSIM Regulator Enable, 1 = enabled */
+#define PBC_BCTRL3_VESIM_EN 0x4000 /* VESIM Regulator Enable, 1 = enabled */
+#define PBC_BCTRL3_SPI3_RESET 0x8000 /* CSPI3 Connector Reset, 0 = reset asserted */
+
+/* PBC Board Control Register 4 bit definitions */
+#define PBC_BCTRL4_CSI_MSB_EN 0x0001 /* CSI MSB Enable, 0 = CSI_Data[3:0] enabled */
+#define PBC_BCTRL4_REGEN_SEL 0x0002 /* Regulator Enable Select, 0 = enabled */
+#define PBC_BCTRL4_USER_OFF 0x0004 /* User Off Indication, 1 = user off confirmation */
+#define PBC_BCTRL4_VIB_EN 0x0008 /* Vibrator Enable, 1 = enabled */
+#define PBC_BCTRL4_PCMCIA_EN 0x0010 /* PCMCIA Enable, 0 = buffer enabled */
+
+#define CKIH_27MHZ_BIT_SET (1 << 4)
+
+#define PBC_INT_CS8900A 4
+/*! @} */
+
+#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
+
+/*!
+ * @name Defines Base address and IRQ used for CS8900A Ethernet Controller on MXC Boards
+ */
+/*! @{*/
+/*! This is System IRQ used by CS8900A for interrupt generation taken from platform.h */
+#define CS8900AIRQ EXPIO_INT_ENET_INT
+/*! This is I/O Base address used to access registers of CS8900A on MXC ADS */
+#define CS8900A_BASE_ADDRESS (PBC_BASE_ADDRESS + PBC_CS8900A_IOBASE + 0x300)
+/*! @} */
+
+#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX31_PIN_GPIO1_3)
+
+#define AHB_FREQ 133000000
+#define IPG_FREQ 66500000
+
+#define MXC_BD_LED1 (1 << 6)
+#define MXC_BD_LED2 (1 << 7)
+#define MXC_BD_LED_ON(led) \
+ __raw_writew(led, PBC_BASE_ADDRESS + PBC_BCTRL1_SET)
+#define MXC_BD_LED_OFF(led) \
+ __raw_writew(led, PBC_BASE_ADDRESS + PBC_BCTRL1_CLEAR)
+
+#endif /* CONFIG_MACH_MX31ADS */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx3/board-mx3_3stack.h linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx3_3stack.h
--- linux-2.6.26/arch/arm/mach-mx3/board-mx3_3stack.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx3_3stack.h 2010-08-10 04:14:16.000000000 -0400
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
+#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
+
+#ifdef CONFIG_MACH_MX31_3DS
+/*!
+ * @defgroup BRDCFG_MX31 Board Configuration Options
+ * @ingroup MSL_MX31
+ */
+
+/*!
+ * @file mach-mx3/board-mx3_3stack.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX31 3STACK Platform.
+ *
+ * @ingroup BRDCFG_MX31
+ */
+
+/*
+ * Include Files
+ */
+#include
+
+/*!
+ * @name MXC UART EVB board level configurations
+ */
+/*! @{ */
+/*!
+ * Specifies if the Irda transmit path is inverting
+ */
+#define MXC_IRDA_TX_INV 0
+/*!
+ * Specifies if the Irda receive path is inverting
+ */
+#define MXC_IRDA_RX_INV 0
+
+/* UART 1 configuration */
+/*!
+ * This define specifies if the UART port is configured to be in DTE or
+ * DCE mode. There exists a define like this for each UART port. Valid
+ * values that can be used are \b MODE_DTE or \b MODE_DCE.
+ */
+#define UART1_MODE MODE_DCE
+/*!
+ * This define specifies if the UART is to be used for IRDA. There exists a
+ * define like this for each UART port. Valid values that can be used are
+ * \b IRDA or \b NO_IRDA.
+ */
+#define UART1_IR NO_IRDA
+/*!
+ * This define is used to enable or disable a particular UART port. If
+ * disabled, the UART will not be registered in the file system and the user
+ * will not be able to access it. There exists a define like this for each UART
+ * port. Specify a value of 1 to enable the UART and 0 to disable it.
+ */
+#define UART1_ENABLED 1
+/*! @} */
+/* UART 2 configuration */
+#define UART2_MODE MODE_DCE
+#define UART2_IR NO_IRDA
+#define UART2_ENABLED 1
+/* UART 3 configuration */
+#define UART3_MODE MODE_DTE
+#define UART3_IR NO_IRDA
+#define UART3_ENABLED 1
+/* UART 4 configuration */
+#define UART4_MODE MODE_DTE
+#define UART4_IR NO_IRDA
+#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */
+/* UART 5 configuration */
+#define UART5_MODE MODE_DTE
+#define UART5_IR NO_IRDA
+#define UART5_ENABLED 0
+
+#define MXC_LL_UART_PADDR UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#define DEBUG_BASE_ADDRESS CS5_BASE_ADDR
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS
+/* External UART */
+#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x8000)
+#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000)
+
+#define BOARD_IO_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG 0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG 0x08
+/* status, interrupt */
+#define INTR_STATUS_REG 0x10
+#define INTR_MASK_REG 0x38
+#define INTR_RESET_REG 0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG 0x40
+#define MAGIC_NUMBER2_REG 0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG 0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG 0x58
+/* module reset register*/
+#define MODULE_RESET_REG 0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG 0x68
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
+
+#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4)
+
+/*! This is System IRQ used by LAN9217 */
+#define LAN9217_IRQ EXPIO_INT_ENET
+
+/*! LED definition*/
+#define MXC_BD_LED1 (1)
+#define MXC_BD_LED2 (1 << 1)
+#define MXC_BD_LED3 (1 << 2)
+#define MXC_BD_LED4 (1 << 3)
+#define MXC_BD_LED5 (1 << 4)
+#define MXC_BD_LED6 (1 << 5)
+#define MXC_BD_LED7 (1 << 6)
+#define MXC_BD_LED8 (1 << 7)
+
+#define MXC_BD_LED_ON(led)
+#define MXC_BD_LED_OFF(led)
+
+extern unsigned int sdhc_get_card_det_status(struct device *dev);
+extern int sdhc_init_card_det(int id);
+extern int sdhc_write_protect(struct device *dev);
+
+#endif /* CONFIG_MACH_MX31_3DS */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx3/clock.c linux-2.6.26-lab126/arch/arm/mach-mx3/clock.c
--- linux-2.6.26/arch/arm/mach-mx3/clock.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/clock.c 2010-08-10 04:14:16.000000000 -0400
@@ -0,0 +1,1380 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "crm_regs.h"
+
+#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
+#define PROPAGATE_RATE_DIS 2
+
+static int cpu_clk_set_wp(int wp);
+struct timer_list dptcen_timer;
+
+static void __calc_pre_post_dividers(u32 div, u32 * pre, u32 * post)
+{
+ u32 min_pre, temp_pre, old_err, err;
+
+ if (div >= 512) {
+ *pre = 8;
+ *post = 64;
+ } else if (div >= 64) {
+ min_pre = (div - 1) / 64 + 1;
+ old_err = 8;
+ for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+ err = div % temp_pre;
+ if (err == 0) {
+ *pre = temp_pre;
+ break;
+ }
+ err = temp_pre - err;
+ if (err < old_err) {
+ old_err = err;
+ *pre = temp_pre;
+ }
+ }
+ *post = (div + *pre - 1) / *pre;
+ } else if (div <= 8) {
+ *pre = div;
+ *post = 1;
+ } else {
+ *pre = 1;
+ *post = div;
+ }
+}
+
+static struct clk mcu_pll_clk;
+static struct clk mcu_main_clk;
+static struct clk usb_pll_clk;
+static struct clk serial_pll_clk;
+static struct clk ipg_clk;
+static struct clk ckih_clk;
+static struct clk ahb_clk;
+
+static int _clk_enable(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 3 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(3 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static void _clk_emi_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(3 << clk->enable_shift);
+ reg |= (1 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ signed long pd = 1; /* Pre-divider */
+ signed long mfi; /* Multiplication Factor (Integer part) */
+ signed long mfn; /* Multiplication Factor (Integer part) */
+ signed long mfd; /* Multiplication Factor (Denominator Part) */
+ signed long tmp;
+ u32 ref_freq = clk->parent->rate;
+
+ while (((ref_freq / pd) * 10) > rate) {
+ pd++;
+ }
+
+ if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) {
+ return -EINVAL;
+ }
+
+ /* the ref_freq/2 in the following is to round up */
+ mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq;
+ if (mfi < 5 || mfi > 15) {
+ return -EINVAL;
+ }
+
+ /* pick a mfd value that will work
+ * then solve for mfn */
+ mfd = ref_freq / 50000;
+
+ /*
+ * pll_freq * pd * mfd
+ * mfn = -------------------- - (mfi * mfd)
+ * 2 * ref_freq
+ */
+ /* the tmp/2 is for rounding */
+ tmp = ref_freq / 10000;
+ mfn =
+ ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
+ (mfi * mfd);
+
+ mfn = mfn & 0x3ff;
+ pd--;
+ mfd--;
+
+ /* Change the Pll value */
+ reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
+ (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
+ (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
+
+ if (clk == &mcu_pll_clk) {
+ __raw_writel(reg, MXC_CCM_MPCTL);
+ } else if (clk == &usb_pll_clk) {
+ __raw_writel(reg, MXC_CCM_UPCTL);
+ } else if (clk == &serial_pll_clk) {
+ __raw_writel(reg, MXC_CCM_SRPCTL);
+ }
+
+ clk->rate = rate;
+ return 0;
+}
+
+static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+ if ((rate < ahb_clk.rate) || (rate % ahb_clk.rate != 0)) {
+ printk(KERN_ERR "Wrong rate %lu in _clk_cpu_set_rate\n", rate);
+ return -EINVAL;
+ }
+
+ cpu_clk_set_wp(rate / ahb_clk.rate - 1);
+
+ return PROPAGATE_RATE_DIS;
+}
+
+static void _clk_pll_recalc(struct clk *clk)
+{
+ long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+ volatile unsigned long reg, ccmr;
+ s64 temp;
+ unsigned int prcs;
+
+ ccmr = __raw_readl(MXC_CCM_CCMR);
+ prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
+ if (prcs == 0x1) {
+ ref_clk = CKIL_CLK_FREQ * 1024;
+ } else {
+ ref_clk = ckih_clk.rate;
+ }
+
+ if (clk == &mcu_pll_clk) {
+ if ((ccmr & MXC_CCM_CCMR_MPE) == 0) {
+ clk->rate = ref_clk;
+ return;
+ }
+ if ((ccmr & MXC_CCM_CCMR_MDS) != 0) {
+ clk->rate = ref_clk;
+ return;
+ }
+ reg = __raw_readl(MXC_CCM_MPCTL);
+ } else if (clk == &usb_pll_clk) {
+ reg = __raw_readl(MXC_CCM_UPCTL);
+ } else if (clk == &serial_pll_clk) {
+ reg = __raw_readl(MXC_CCM_SRPCTL);
+ } else {
+ BUG();
+ }
+ pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
+ mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
+ mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
+ mfi = (mfi <= 5) ? 5 : mfi;
+ mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
+
+ if (mfn >= 0x200) {
+ mfn |= 0xFFFFFE00;
+ mfn_abs = -mfn;
+ }
+
+ ref_clk *= 2;
+ ref_clk /= pdf + 1;
+
+ temp = (u64) ref_clk *mfn_abs;
+ do_div(temp, mfd + 1);
+ if (mfn < 0)
+ temp = -temp;
+ temp = (ref_clk * mfi) + temp;
+
+ clk->rate = temp;
+}
+
+static int _clk_usb_pll_enable(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg |= MXC_CCM_CCMR_UPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+
+ /* No lock bit on MX31, so using max time from spec */
+ udelay(80);
+
+ return 0;
+}
+
+static void _clk_usb_pll_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg &= ~MXC_CCM_CCMR_UPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+static int _clk_serial_pll_enable(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg |= MXC_CCM_CCMR_SPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+
+ /* No lock bit on MX31, so using max time from spec */
+ udelay(80);
+
+ return 0;
+}
+
+static void _clk_serial_pll_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg &= ~MXC_CCM_CCMR_SPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
+#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
+#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
+
+static void _clk_mcu_main_recalc(struct clk *clk)
+{
+ u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
+
+ if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL) {
+ serial_pll_clk.recalc(&serial_pll_clk);
+ clk->rate = serial_pll_clk.rate;
+ } else {
+ mcu_pll_clk.recalc(&mcu_pll_clk);
+ clk->rate = mcu_pll_clk.rate;
+ }
+}
+
+static void _clk_cpu_recalc(struct clk *clk)
+{
+ unsigned long mcu_pdf;
+
+ mcu_pdf = PDR0(MXC_CCM_PDR0_MCU_PODF_MASK,
+ MXC_CCM_PDR0_MCU_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (mcu_pdf + 1);
+}
+
+static void _clk_hclk_recalc(struct clk *clk)
+{
+ unsigned long max_pdf;
+
+ max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
+ MXC_CCM_PDR0_MAX_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (max_pdf + 1);
+}
+
+static void _clk_ipg_recalc(struct clk *clk)
+{
+ unsigned long ipg_pdf;
+
+ ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
+ MXC_CCM_PDR0_IPG_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (ipg_pdf + 1);
+}
+
+static void _clk_nfc_recalc(struct clk *clk)
+{
+ unsigned long nfc_pdf;
+
+ nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
+ MXC_CCM_PDR0_NFC_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (nfc_pdf + 1);
+}
+
+static void _clk_hsp_recalc(struct clk *clk)
+{
+ unsigned long hsp_pdf;
+
+ hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
+ MXC_CCM_PDR0_HSP_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (hsp_pdf + 1);
+}
+
+static void _clk_usb_recalc(struct clk *clk)
+{
+ unsigned long usb_pdf, usb_prepdf;
+
+ usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
+ MXC_CCM_PDR1_USB_PODF_OFFSET);
+ usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
+ MXC_CCM_PDR1_USB_PRDF_OFFSET);
+ clk->rate = clk->parent->rate / (usb_prepdf + 1) / (usb_pdf + 1);
+}
+
+static void _clk_csi_recalc(struct clk *clk)
+{
+ u32 reg;
+ u32 pre, post;
+
+ reg = __raw_readl(MXC_CCM_PDR0);
+ pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
+ MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+ pre++;
+ post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
+ MXC_CCM_PDR0_CSI_PODF_OFFSET;
+ post++;
+ clk->rate = clk->parent->rate / (pre * post);
+}
+
+static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 pre, post;
+ u32 div = clk->parent->rate / rate;
+ if (clk->parent->rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return clk->parent->rate / (pre * post);
+}
+
+static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+
+ div = clk->parent->rate / rate;
+
+ if ((clk->parent->rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set CSI clock divider */
+ reg = __raw_readl(MXC_CCM_PDR0) &
+ ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
+ reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+ __raw_writel(reg, MXC_CCM_PDR0);
+
+ clk->rate = rate;
+ return 0;
+}
+
+static void _clk_per_recalc(struct clk *clk)
+{
+ unsigned long per_pdf;
+
+ per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
+ MXC_CCM_PDR0_PER_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (per_pdf + 1);
+}
+
+static void _clk_ssi1_recalc(struct clk *clk)
+{
+ unsigned long ssi1_pdf, ssi1_prepdf;
+
+ ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
+ MXC_CCM_PDR1_SSI1_PODF_OFFSET);
+ ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
+ MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
+}
+
+static void _clk_ssi2_recalc(struct clk *clk)
+{
+ unsigned long ssi2_pdf, ssi2_prepdf;
+
+ ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
+ MXC_CCM_PDR1_SSI2_PODF_OFFSET);
+ ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
+ MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
+}
+
+static void _clk_firi_recalc(struct clk *clk)
+{
+ unsigned long firi_pdf, firi_prepdf;
+
+ firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
+ MXC_CCM_PDR1_FIRI_PODF_OFFSET);
+ firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
+ MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
+ clk->rate = clk->parent->rate / (firi_prepdf + 1) / (firi_pdf + 1);
+}
+
+static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 pre, post;
+ u32 div = clk->parent->rate / rate;
+ if (clk->parent->rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return clk->parent->rate / (pre * post);
+
+}
+
+static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div, pre, post;
+
+ div = clk->parent->rate / rate;
+
+ if ((clk->parent->rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set FIRI clock divider */
+ reg = __raw_readl(MXC_CCM_PDR1) &
+ ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
+ reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
+ reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_PDR1);
+
+ clk->rate = rate;
+ return 0;
+}
+
+static void _clk_mbx_recalc(struct clk *clk)
+{
+ clk->rate = clk->parent->rate / 2;
+}
+
+static void _clk_mstick1_recalc(struct clk *clk)
+{
+ unsigned long msti_pdf;
+
+ msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
+ MXC_CCM_PDR2_MST1_PDF_OFFSET);
+ clk->rate = clk->parent->rate / (msti_pdf + 1);
+}
+
+static void _clk_mstick2_recalc(struct clk *clk)
+{
+ unsigned long msti_pdf;
+
+ msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
+ MXC_CCM_PDR2_MST2_PDF_OFFSET);
+ clk->rate = clk->parent->rate / (msti_pdf + 1);
+}
+
+static struct clk ckih_clk = {
+ .name = "ckih",
+ .rate = 0, /* determined later (26 or 27 MHz) */
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk ckil_clk = {
+ .name = "ckil",
+ .rate = CKIL_CLK_FREQ,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk mcu_pll_clk = {
+ .name = "mcu_pll",
+ .parent = &ckih_clk,
+ .set_rate = _clk_pll_set_rate,
+ .recalc = _clk_pll_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk mcu_main_clk = {
+ .name = "mcu_main_clk",
+ .parent = &mcu_pll_clk,
+ .recalc = _clk_mcu_main_recalc,
+};
+
+static struct clk serial_pll_clk = {
+ .name = "serial_pll",
+ .parent = &ckih_clk,
+ .set_rate = _clk_pll_set_rate,
+ .recalc = _clk_pll_recalc,
+ .enable = _clk_serial_pll_enable,
+ .disable = _clk_serial_pll_disable,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk usb_pll_clk = {
+ .name = "usb_pll",
+ .parent = &ckih_clk,
+ .set_rate = _clk_pll_set_rate,
+ .recalc = _clk_pll_recalc,
+ .enable = _clk_usb_pll_enable,
+ .disable = _clk_usb_pll_disable,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk cpu_clk = {
+ .name = "cpu_clk",
+ .parent = &mcu_main_clk,
+ .recalc = _clk_cpu_recalc,
+ .set_rate = _clk_cpu_set_rate,
+};
+
+static struct clk ahb_clk = {
+ .name = "ahb_clk",
+ .parent = &mcu_main_clk,
+ .recalc = _clk_hclk_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk per_clk = {
+ .name = "per_clk",
+ .parent = &usb_pll_clk,
+ .recalc = _clk_per_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk perclk_clk = {
+ .name = "perclk_clk",
+ .parent = &ipg_clk,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk cspi_clk[] = {
+ {
+ .name = "cspi_clk",
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "cspi_clk",
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "cspi_clk",
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk ipg_clk = {
+ .name = "ipg_clk",
+ .parent = &ahb_clk,
+ .recalc = _clk_ipg_recalc,
+ .flags = RATE_PROPAGATES,
+};
+
+static struct clk emi_clk = {
+ .name = "emi_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
+ .disable = _clk_emi_disable,
+};
+
+static struct clk gpt_clk = {
+ .name = "gpt_clk",
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk pwm_clk = {
+ .name = "pwm_clk",
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk epit_clk[] = {
+ {
+ .name = "epit_clk",
+ .id = 0,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "epit_clk",
+ .id = 1,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk nfc_clk = {
+ .name = "nfc_clk",
+ .parent = &ahb_clk,
+ .recalc = _clk_nfc_recalc,
+};
+
+static struct clk scc_clk = {
+ .name = "scc_clk",
+ .parent = &ipg_clk,
+};
+
+static struct clk ipu_clk = {
+ .name = "ipu_clk",
+ .parent = &mcu_main_clk,
+ .recalc = _clk_hsp_recalc,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+ .name = "kpp_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk wdog_clk = {
+ .name = "wdog_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
+ .disable = _clk_disable,
+};
+static struct clk rtc_clk = {
+ .name = "rtc_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk usb_clk[] = {
+ {
+ .name = "usb_clk",
+ .parent = &usb_pll_clk,
+ .recalc = _clk_usb_recalc,},
+ {
+ .name = "usb_ahb_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk csi_clk = {
+ .name = "csi_clk",
+ .parent = &serial_pll_clk,
+ .recalc = _clk_csi_recalc,
+ .round_rate = _clk_csi_round_rate,
+ .set_rate = _clk_csi_set_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk uart_clk[] = {
+ {
+ .name = "uart_clk",
+ .id = 0,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "uart_clk",
+ .id = 1,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "uart_clk",
+ .id = 2,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "uart_clk",
+ .id = 3,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "uart_clk",
+ .id = 4,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk i2c_clk[] = {
+ {
+ .name = "i2c_clk",
+ .id = 0,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "i2c_clk",
+ .id = 1,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "i2c_clk",
+ .id = 2,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk owire_clk = {
+ .name = "owire_clk",
+ .parent = &perclk_clk,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+};
+
+static struct clk sdhc_clk[] = {
+ {
+ .name = "sdhc_clk",
+ .id = 0,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "sdhc_clk",
+ .id = 1,
+ .parent = &perclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk ssi_clk[] = {
+ {
+ .name = "ssi_clk",
+ .parent = &serial_pll_clk,
+ .recalc = _clk_ssi1_recalc,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "ssi_clk",
+ .id = 1,
+ .parent = &serial_pll_clk,
+ .recalc = _clk_ssi2_recalc,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk firi_clk = {
+ .name = "firi_clk",
+ .parent = &usb_pll_clk,
+ .round_rate = _clk_firi_round_rate,
+ .set_rate = _clk_firi_set_rate,
+ .recalc = _clk_firi_recalc,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk ata_clk = {
+ .name = "ata_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk mbx_clk = {
+ .name = "mbx_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
+ .recalc = _clk_mbx_recalc,
+};
+
+static struct clk vpu_clk = {
+ .name = "vpu_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
+ .recalc = _clk_mbx_recalc,
+};
+
+static struct clk rtic_clk = {
+ .name = "rtic_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR2,
+ .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk rng_clk = {
+ .name = "rng_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk sdma_clk[] = {
+ {
+ .name = "sdma_ahb_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "sdma_ipg_clk",
+ .parent = &ipg_clk,}
+};
+
+static struct clk mpeg4_clk = {
+ .name = "mpeg4_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk vl2cc_clk = {
+ .name = "vl2cc_clk",
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk mstick_clk[] = {
+ {
+ .name = "mstick_clk",
+ .id = 0,
+ .parent = &usb_pll_clk,
+ .recalc = _clk_mstick1_recalc,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
+ .disable = _clk_disable,},
+ {
+ .name = "mstick_clk",
+ .id = 1,
+ .parent = &usb_pll_clk,
+ .recalc = _clk_mstick2_recalc,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR1,
+ .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
+ .disable = _clk_disable,},
+};
+
+static struct clk iim_clk = {
+ .name = "iim_clk",
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CGR0,
+ .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
+ .disable = _clk_disable,
+};
+
+static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 div;
+
+ div = clk->parent->rate / rate;
+ if (clk->parent->rate % rate)
+ div++;
+
+ if (div > 8) {
+ div = 16;
+ } else if (div > 4) {
+ div = 8;
+ } else if (div > 2) {
+ div = 4;
+ }
+
+ return clk->parent->rate / div;
+}
+
+static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+
+ div = clk->parent->rate / rate;
+
+ if (div == 16) {
+ div = 4;
+ } else if (div == 8) {
+ div = 3;
+ } else if (div == 4) {
+ div = 2;
+ } else if (div == 2) {
+ div = 1;
+ } else if (div == 1) {
+ div = 0;
+ } else {
+ return -EINVAL;
+ }
+
+ reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
+ reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
+ __raw_writel(reg, MXC_CCM_COSR);
+
+ return 0;
+}
+
+static void _clk_cko1_recalc(struct clk *clk)
+{
+ u32 div;
+
+ div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
+ MXC_CCM_COSR_CLKOUTDIV_OFFSET;
+
+ clk->rate = clk->parent->rate / (1 << div);
+}
+
+static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
+
+ if (parent == &mcu_main_clk) {
+ reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &ipg_clk) {
+ reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &usb_pll_clk) {
+ reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == mcu_main_clk.parent) {
+ reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &ahb_clk) {
+ reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &cpu_clk) {
+ reg |= 6 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &serial_pll_clk) {
+ reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &ckih_clk) {
+ reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &emi_clk) {
+ reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &ipu_clk) {
+ reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &nfc_clk) {
+ reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else if (parent == &uart_clk[0]) {
+ reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
+ } else {
+ return -EINVAL;
+ }
+
+ __raw_writel(reg, MXC_CCM_COSR);
+
+ return 0;
+}
+
+static int _clk_cko1_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
+ __raw_writel(reg, MXC_CCM_COSR);
+
+ return 0;
+}
+
+static void _clk_cko1_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN;
+ __raw_writel(reg, MXC_CCM_COSR);
+}
+
+static struct clk cko1_clk = {
+ .name = "cko1_clk",
+ .recalc = _clk_cko1_recalc,
+ .set_rate = _clk_cko1_set_rate,
+ .round_rate = _clk_cko1_round_rate,
+ .set_parent = _clk_cko1_set_parent,
+ .enable = _clk_cko1_enable,
+ .disable = _clk_cko1_disable,
+};
+
+static struct clk *mxc_clks[] = {
+ &ckih_clk,
+ &ckil_clk,
+ &mcu_pll_clk,
+ &usb_pll_clk,
+ &serial_pll_clk,
+ &mcu_main_clk,
+ &cpu_clk,
+ &ahb_clk,
+ &per_clk,
+ &perclk_clk,
+ &cko1_clk,
+ &emi_clk,
+ &cspi_clk[0],
+ &cspi_clk[1],
+ &cspi_clk[2],
+ &ipg_clk,
+ &gpt_clk,
+ &pwm_clk,
+ &wdog_clk,
+ &rtc_clk,
+ &epit_clk[0],
+ &epit_clk[1],
+ &nfc_clk,
+ &ipu_clk,
+ &kpp_clk,
+ &usb_clk[0],
+ &usb_clk[1],
+ &csi_clk,
+ &uart_clk[0],
+ &uart_clk[1],
+ &uart_clk[2],
+ &uart_clk[3],
+ &uart_clk[4],
+ &i2c_clk[0],
+ &i2c_clk[1],
+ &i2c_clk[2],
+ &owire_clk,
+ &sdhc_clk[0],
+ &sdhc_clk[1],
+ &ssi_clk[0],
+ &ssi_clk[1],
+ &firi_clk,
+ &ata_clk,
+ &rtic_clk,
+ &rng_clk,
+ &sdma_clk[0],
+ &sdma_clk[1],
+ &mstick_clk[0],
+ &mstick_clk[1],
+ &scc_clk,
+ &iim_clk,
+};
+
+static int cpu_curr_wp;
+static struct cpu_wp *cpu_wp_tbl;
+
+static int cpu_wp_nr;
+
+extern void propagate_rate(struct clk *tclk);
+
+int __init mxc_clocks_init(void)
+{
+ u32 reg;
+ struct clk **clkp;
+
+ for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) {
+ clk_register(*clkp);
+ }
+
+ if (cpu_is_mx31()) {
+ clk_register(&mpeg4_clk);
+ clk_register(&mbx_clk);
+ } else {
+ clk_register(&vpu_clk);
+ clk_register(&vl2cc_clk);
+ }
+
+ /* CCMR stby control */
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg |= MXC_CCM_CCMR_VSTBY | MXC_CCM_CCMR_WAMO;
+ __raw_writel(reg, MXC_CCM_CCMR);
+
+ /* Turn off all possible clocks */
+ __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0);
+ __raw_writel(0, MXC_CCM_CGR1);
+
+ reg = MXC_CCM_CGR2_EMI_MASK | /*For MX32 */
+ MXC_CCM_CGR2_IPMUX1_MASK | /*For MX32 */
+ MXC_CCM_CGR2_IPMUX2_MASK | /*For MX32 */
+ MXC_CCM_CGR2_MXCCLKENSEL_MASK | /*For MX32 */
+ MXC_CCM_CGR2_CHIKCAMPEN_MASK | /*For MX32 */
+ MXC_CCM_CGR2_OVRVPUBUSY_MASK | /*For MX32 */
+ 0x3 << 27 | /*Bit 27 and 28 are not defined for MX32,
+ but still requires to be set */
+ MXC_CCM_CGR2_APMSYSCLKSEL_MASK | MXC_CCM_CGR2_AOMENA_MASK;
+ __raw_writel(reg, MXC_CCM_CGR2);
+
+ cko1_clk.disable(&cko1_clk);
+ usb_pll_clk.disable(&usb_pll_clk);
+
+ pr_info("Clock input source is %ld\n", ckih_clk.rate);
+
+ /* This will propagate to all children and init all the clock rates */
+ propagate_rate(&ckih_clk);
+
+ clk_enable(&gpt_clk);
+ clk_enable(&emi_clk);
+ clk_enable(&iim_clk);
+
+ clk_enable(&serial_pll_clk);
+
+ cpu_curr_wp = cpu_clk.rate / ahb_clk.rate - 1;
+ cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
+
+ /* Init serial PLL according */
+ clk_set_rate(&serial_pll_clk, (cpu_wp_tbl[2].pll_rate));
+
+ if (cpu_is_mx31_rev(CHIP_REV_2_0) < 0) {
+ /* replace 399MHz wp with 266MHz one */
+ memcpy(&cpu_wp_tbl[2], &cpu_wp_tbl[1], sizeof(cpu_wp_tbl[0]));
+ }
+
+ return 0;
+}
+
+/*!
+ * Function to get timer clock rate early in boot process before clock tree is
+ * initialized.
+ *
+ * @return Clock rate for timer
+ */
+unsigned long __init clk_early_get_timer_rate(void)
+{
+ /* Determine which high frequency clock source is coming in */
+ ckih_clk.rate = board_get_ckih_rate();
+
+ mcu_main_clk.recalc(&mcu_main_clk);
+ ahb_clk.recalc(&ahb_clk);
+ ipg_clk.recalc(&ipg_clk);
+ return ipg_clk.rate;
+}
+
+#define MXC_PMCR0_DVFS_MASK (MXC_CCM_PMCR0_DVSUP_MASK | \
+ MXC_CCM_PMCR0_UDSC_MASK | \
+ MXC_CCM_PMCR0_VSCNT_MASK | \
+ MXC_CCM_PMCR0_DPVCR)
+
+#define MXC_PDR0_MAX_MCU_MASK (MXC_CCM_PDR0_MAX_PODF_MASK | \
+ MXC_CCM_PDR0_MCU_PODF_MASK | \
+ MXC_CCM_PDR0_HSP_PODF_MASK | \
+ MXC_CCM_PDR0_IPG_PODF_MASK | \
+ MXC_CCM_PDR0_NFC_PODF_MASK)
+
+static DEFINE_SPINLOCK(mxc_dfs_lock);
+
+static void dptcen_after_timeout(unsigned long ptr)
+{
+ u32 flags = 0;
+
+ spin_lock_irqsave(&mxc_dfs_lock, flags);
+
+ /*
+ * If DPTC is still active and core is running in Turbo mode
+ */
+ if (dptcen_timer.data == cpu_wp_nr - 1) {
+ dptc_resume(DPTC_GP_ID);
+ }
+ spin_unlock_irqrestore(&mxc_dfs_lock, flags);
+}
+
+/*!
+ * Setup cpu clock based on working point.
+ * @param wp cpu freq working point (0 is the slowest)
+ * @return 0 on success or error code on failure.
+ */
+static int cpu_clk_set_wp(int wp)
+{
+ struct cpu_wp *p;
+ u32 dvsup;
+ u32 pmcr0, pmcr1;
+ u32 pdr0;
+ u32 cgr2 = 0x80000000;
+ u32 vscnt = MXC_CCM_PMCR0_VSCNT_2;
+ u32 udsc = MXC_CCM_PMCR0_UDSC_DOWN;
+ u32 ipu_base = IO_ADDRESS(IPU_CTRL_BASE_ADDR);
+ u32 ipu_conf;
+
+ if (wp >= cpu_wp_nr || wp < 0) {
+ printk(KERN_ERR "Wrong wp: %d for cpu_clk_set_wp\n", wp);
+ return -EINVAL;
+ }
+ if (wp == cpu_curr_wp) {
+ return 0;
+ }
+
+ pmcr0 = __raw_readl(MXC_CCM_PMCR0);
+ pmcr1 = __raw_readl(MXC_CCM_PMCR1);
+ pdr0 = __raw_readl(MXC_CCM_PDR0);
+
+ if (!(pmcr0 & MXC_CCM_PMCR0_UPDTEN)) {
+ return -EBUSY;
+ }
+
+ if (wp > cpu_curr_wp) {
+ /* going faster */
+ if (wp == (cpu_wp_nr - 1)) {
+ /* Only update vscnt going into Turbo */
+ vscnt = MXC_CCM_PMCR0_VSCNT_8;
+ }
+ udsc = MXC_CCM_PMCR0_UDSC_UP;
+ }
+
+ p = &cpu_wp_tbl[wp];
+
+ dvsup = (cpu_wp_nr - 1 - wp) << MXC_CCM_PMCR0_DVSUP_OFFSET;
+
+ if ((mcu_main_clk.rate == 399000000) && (p->cpu_rate == 532000000)) {
+ cgr2 = __raw_readl(MXC_CCM_CGR2);
+ cgr2 &= 0x7fffffff;
+ vscnt = 0;
+ pmcr0 = (pmcr0 & ~MXC_PMCR0_DVFS_MASK) | dvsup | vscnt;
+ pr_debug("manul dvfs, dvsup = %x\n", dvsup);
+ __raw_writel(cgr2, MXC_CCM_CGR2);
+ __raw_writel(pmcr0, MXC_CCM_PMCR0);
+ udelay(100);
+ }
+
+ if (mcu_main_clk.rate == p->pll_rate) {
+ /* No pll switching and relocking needed */
+ pmcr0 |= MXC_CCM_PMCR0_DFSUP0_PDR;
+ } else {
+ /* pll switching and relocking needed */
+ pmcr0 ^= MXC_CCM_PMCR0_DFSUP1; /* flip MSB bit */
+ pmcr0 &= ~(MXC_CCM_PMCR0_DFSUP0);
+ }
+
+ pmcr0 = (pmcr0 & ~MXC_PMCR0_DVFS_MASK) | dvsup | vscnt | udsc;
+ /* also enable DVFS hardware */
+ pmcr0 |= MXC_CCM_PMCR0_DVFEN;
+
+ __raw_writel(pmcr0, MXC_CCM_PMCR0);
+
+ /* IPU and DI submodule must be on for PDR0 update to take effect */
+ if (!clk_get_usecount(&ipu_clk))
+ ipu_clk.enable(&ipu_clk);
+ ipu_conf = __raw_readl(ipu_base);
+ if (!(ipu_conf & 0x40))
+ __raw_writel(ipu_conf | 0x40, ipu_base);
+
+ __raw_writel((pdr0 & ~MXC_PDR0_MAX_MCU_MASK) | p->pdr0_reg,
+ MXC_CCM_PDR0);
+
+ if ((pmcr0 & MXC_CCM_PMCR0_DFSUP0) == MXC_CCM_PMCR0_DFSUP0_PLL) {
+ /* prevent pll restart */
+ pmcr1 |= 0x80;
+ __raw_writel(pmcr1, MXC_CCM_PMCR1);
+ /* PLL and post divider update */
+ if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL) {
+ __raw_writel(p->pll_reg, MXC_CCM_SRPCTL);
+ serial_pll_clk.rate = p->pll_rate;
+ mcu_main_clk.parent = &serial_pll_clk;
+ } else {
+ __raw_writel(p->pll_reg, MXC_CCM_MPCTL);
+ mcu_pll_clk.rate = p->pll_rate;
+ mcu_main_clk.parent = &mcu_pll_clk;
+ }
+ }
+
+ if ((cgr2 & 0x80000000) == 0x0) {
+ pr_debug("start auto dvfs\n");
+ cgr2 |= 0x80000000;
+ __raw_writel(cgr2, MXC_CCM_CGR2);
+ }
+
+ mcu_main_clk.rate = p->pll_rate;
+ cpu_clk.rate = p->cpu_rate;
+
+ cpu_curr_wp = wp;
+
+ /* Restore IPU_CONF setting */
+ __raw_writel(ipu_conf, ipu_base);
+ if (!clk_get_usecount(&ipu_clk))
+ ipu_clk.disable(&ipu_clk);
+
+ if (wp == cpu_wp_nr - 1) {
+ init_timer(&dptcen_timer);
+ dptcen_timer.expires = jiffies + 2;
+ dptcen_timer.function = dptcen_after_timeout;
+ dptcen_timer.data = wp;
+ add_timer(&dptcen_timer);
+ } else {
+ dptc_suspend(DPTC_GP_ID);
+ }
+
+ return 0;
+}
diff -urN linux-2.6.26/arch/arm/mach-mx3/cpu.c linux-2.6.26-lab126/arch/arm/mach-mx3/cpu.c
--- linux-2.6.26/arch/arm/mach-mx3/cpu.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/cpu.c 2010-08-10 04:14:16.000000000 -0400
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2001 Deep Blue Solutions Ltd.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*!
+ * @file mach-mx3/cpu.c
+ *
+ * @brief This file contains the CPU initialization code.
+ *
+ * @ingroup MSL_MX31
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*!
+ * CPU initialization. It is called by fixup_mxc_board()
+ */
+void __init mxc_cpu_init(void)
+{
+ /* Setup Peripheral Port Remap register for AVIC */
+ asm("ldr r0, =0xC0000015 \n\
+ mcr p15, 0, r0, c15, c2, 4");
+ if (!system_rev) {
+ mxc_set_system_rev(0x31, CHIP_REV_2_0);
+ }
+}
+
+/*!
+ * Post CPU init code
+ *
+ * @return 0 always
+ */
+static int __init post_cpu_init(void)
+{
+ void *l2_base;
+ volatile unsigned long aips_reg;
+
+ /* Initialize L2 cache */
+ l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K);
+ if (l2_base) {
+ l2x0_init(l2_base, 0x00030024, 0x00000000);
+ }
+
+ /*
+ * S/W workaround: Clear the off platform peripheral modules
+ * Supervisor Protect bit for SDMA to access them.
+ */
+ __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
+ __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
+ __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
+ __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
+ aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
+ aips_reg &= 0x00FFFFFF;
+ __raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
+
+ __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
+ __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
+ __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
+ __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
+ aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
+ aips_reg &= 0x00FFFFFF;
+ __raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
+
+ return 0;
+}
+
+postcore_initcall(post_cpu_init);
diff -urN linux-2.6.26/arch/arm/mach-mx3/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx3/crm_regs.h
--- linux-2.6.26/arch/arm/mach-mx3/crm_regs.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/crm_regs.h 2010-08-10 04:14:16.000000000 -0400
@@ -0,0 +1,394 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+
+#define CKIH_CLK_FREQ 26000000
+#define CKIH_CLK_FREQ_27MHZ 27000000
+#define CKIL_CLK_FREQ 32768
+
+#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
+
+/* Register addresses */
+#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
+#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04)
+#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08)
+#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10)
+#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14)
+#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18)
+#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28)
+#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30)
+#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34)
+#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38)
+#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40)
+#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44)
+#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48)
+#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50)
+#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54)
+#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58)
+#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60)
+#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64)
+
+/* Register bit definitions */
+#define MXC_CCM_CCMR_VSTBY (1 << 28)
+#define MXC_CCM_CCMR_WBEN (1 << 27)
+#define MXC_CCM_CCMR_CSCS (1 << 25)
+#define MXC_CCM_CCMR_PERCS (1 << 24)
+#define MXC_CCM_CCMR_SSI1S_OFFSET 18
+#define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18)
+#define MXC_CCM_CCMR_SSI2S_OFFSET 21
+#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21)
+#define MXC_CCM_CCMR_LPM_OFFSET 14
+#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
+#define MXC_CCM_CCMR_FIRS_OFFSET 11
+#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
+#define MXC_CCM_CCMR_WAMO (1 << 10)
+#define MXC_CCM_CCMR_UPE (1 << 9)
+#define MXC_CCM_CCMR_SPE (1 << 8)
+#define MXC_CCM_CCMR_MDS (1 << 7)
+#define MXC_CCM_CCMR_SBYCS (1 << 4)
+#define MXC_CCM_CCMR_MPE (1 << 3)
+#define MXC_CCM_CCMR_PRCS_OFFSET 1
+#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1)
+
+#define MXC_CCM_PDR0_CSI_PODF_OFFSET 26
+#define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26)
+#define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23
+#define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23)
+#define MXC_CCM_PDR0_PER_PODF_OFFSET 16
+#define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16)
+#define MXC_CCM_PDR0_HSP_PODF_OFFSET 11
+#define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11)
+#define MXC_CCM_PDR0_NFC_PODF_OFFSET 8
+#define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8)
+#define MXC_CCM_PDR0_IPG_PODF_OFFSET 6
+#define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6)
+#define MXC_CCM_PDR0_MAX_PODF_OFFSET 3
+#define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3)
+#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
+#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
+
+#define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11)
+
+#define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6)
+
+#define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3)
+
+#define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8)
+
+#define MXC_CCM_PDR0_MCU_DIV_1 0x0
+#define MXC_CCM_PDR0_MCU_DIV_2 0x1
+#define MXC_CCM_PDR0_MCU_DIV_3 0x2
+#define MXC_CCM_PDR0_MCU_DIV_4 0x3
+#define MXC_CCM_PDR0_MCU_DIV_5 0x4
+#define MXC_CCM_PDR0_MCU_DIV_6 0x5
+#define MXC_CCM_PDR0_MCU_DIV_7 0x6
+#define MXC_CCM_PDR0_MCU_DIV_8 0x7
+
+#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
+#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
+#define MXC_CCM_PDR1_USB_PODF_OFFSET 27
+#define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27)
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24)
+#define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18
+#define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18)
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15)
+#define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9
+#define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9)
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6)
+#define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0
+#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F
+
+/* Bit definitions for RCSR */
+#define MXC_CCM_RCSR_NF16B 0x80000000
+
+/* Bit definitions for both MCU, USB and SR PLL control registers */
+#define MXC_CCM_PCTL_BRM 0x80000000
+#define MXC_CCM_PCTL_PD_OFFSET 26
+#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
+#define MXC_CCM_PCTL_MFD_OFFSET 16
+#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
+#define MXC_CCM_PCTL_MFI_OFFSET 10
+#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
+#define MXC_CCM_PCTL_MFN_OFFSET 0
+#define MXC_CCM_PCTL_MFN_MASK 0x3FF
+
+#define MXC_CCM_CGR0_SD_MMC1_OFFSET 0
+#define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0)
+#define MXC_CCM_CGR0_SD_MMC2_OFFSET 2
+#define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2)
+#define MXC_CCM_CGR0_GPT_OFFSET 4
+#define MXC_CCM_CGR0_GPT_MASK (0x3 << 4)
+#define MXC_CCM_CGR0_EPIT1_OFFSET 6
+#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6)
+#define MXC_CCM_CGR0_EPIT2_OFFSET 8
+#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8)
+#define MXC_CCM_CGR0_IIM_OFFSET 10
+#define MXC_CCM_CGR0_IIM_MASK (0x3 << 10)
+#define MXC_CCM_CGR0_ATA_OFFSET 12
+#define MXC_CCM_CGR0_ATA_MASK (0x3 << 12)
+#define MXC_CCM_CGR0_SDMA_OFFSET 14
+#define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14)
+#define MXC_CCM_CGR0_CSPI3_OFFSET 16
+#define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16)
+#define MXC_CCM_CGR0_RNG_OFFSET 18
+#define MXC_CCM_CGR0_RNG_MASK (0x3 << 18)
+#define MXC_CCM_CGR0_UART1_OFFSET 20
+#define MXC_CCM_CGR0_UART1_MASK (0x3 << 20)
+#define MXC_CCM_CGR0_UART2_OFFSET 22
+#define MXC_CCM_CGR0_UART2_MASK (0x3 << 22)
+#define MXC_CCM_CGR0_SSI1_OFFSET 24
+#define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24)
+#define MXC_CCM_CGR0_I2C1_OFFSET 26
+#define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26)
+#define MXC_CCM_CGR0_I2C2_OFFSET 28
+#define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28)
+#define MXC_CCM_CGR0_I2C3_OFFSET 30
+#define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30)
+
+#define MXC_CCM_CGR1_HANTRO_OFFSET 0
+#define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0)
+#define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2
+#define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2)
+#define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4
+#define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4)
+#define MXC_CCM_CGR1_CSI_OFFSET 6
+#define MXC_CCM_CGR1_CSI_MASK (0x3 << 6)
+#define MXC_CCM_CGR1_RTC_OFFSET 8
+#define MXC_CCM_CGR1_RTC_MASK (0x3 << 8)
+#define MXC_CCM_CGR1_WDOG_OFFSET 10
+#define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10)
+#define MXC_CCM_CGR1_PWM_OFFSET 12
+#define MXC_CCM_CGR1_PWM_MASK (0x3 << 12)
+#define MXC_CCM_CGR1_SIM_OFFSET 14
+#define MXC_CCM_CGR1_SIM_MASK (0x3 << 14)
+#define MXC_CCM_CGR1_ECT_OFFSET 16
+#define MXC_CCM_CGR1_ECT_MASK (0x3 << 16)
+#define MXC_CCM_CGR1_USBOTG_OFFSET 18
+#define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18)
+#define MXC_CCM_CGR1_KPP_OFFSET 20
+#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
+#define MXC_CCM_CGR1_IPU_OFFSET 22
+#define MXC_CCM_CGR1_IPU_MASK (0x3 << 22)
+#define MXC_CCM_CGR1_UART3_OFFSET 24
+#define MXC_CCM_CGR1_UART3_MASK (0x3 << 24)
+#define MXC_CCM_CGR1_UART4_OFFSET 26
+#define MXC_CCM_CGR1_UART4_MASK (0x3 << 26)
+#define MXC_CCM_CGR1_UART5_OFFSET 28
+#define MXC_CCM_CGR1_UART5_MASK (0x3 << 28)
+#define MXC_CCM_CGR1_OWIRE_OFFSET 30
+#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30)
+
+#define MXC_CCM_CGR2_SSI2_OFFSET 0
+#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0)
+#define MXC_CCM_CGR2_CSPI1_OFFSET 2
+#define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2)
+#define MXC_CCM_CGR2_CSPI2_OFFSET 4
+#define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4)
+#define MXC_CCM_CGR2_GACC_OFFSET 6
+#define MXC_CCM_CGR2_GACC_MASK (0x3 << 6)
+#define MXC_CCM_CGR2_EMI_OFFSET 8
+#define MXC_CCM_CGR2_EMI_MASK (0x3 << 8)
+#define MXC_CCM_CGR2_RTIC_OFFSET 10
+#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10)
+#define MXC_CCM_CGR2_FIRI_OFFSET 12
+#define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12)
+#define MXC_CCM_CGR2_IPMUX1_OFFSET 14
+#define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14)
+#define MXC_CCM_CGR2_IPMUX2_OFFSET 16
+#define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16)
+
+/* These new CGR2 bits are added in MX32 */
+#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18
+#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18)
+#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20
+#define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20)
+#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22
+#define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22)
+#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24
+#define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24)
+#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25
+#define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25)
+#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26
+#define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26)
+#define MXC_CCM_CGR2_APMENA_OFFSET 30
+#define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30)
+
+/*
+ * LTR0 register offsets
+ */
+#define MXC_CCM_LTR0_DIV3CK_OFFSET 1
+#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1)
+#define MXC_CCM_LTR0_DNTHR_OFFSET 16
+#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16)
+#define MXC_CCM_LTR0_UPTHR_OFFSET 22
+#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22)
+
+/*
+ * LTR1 register offsets
+ */
+#define MXC_CCM_LTR1_PNCTHR_OFFSET 0
+#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F
+#define MXC_CCM_LTR1_UPCNT_OFFSET 6
+#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6)
+#define MXC_CCM_LTR1_DNCNT_OFFSET 14
+#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14)
+#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000
+#define MXC_CCM_LTR1_LTBRSR_OFFSET 22
+#define MXC_CCM_LTR1_LTBRSR 0x400000
+#define MXC_CCM_LTR1_LTBRSH 0x800000
+
+/*
+ * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
+ */
+#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3)
+#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << MXC_CCM_LTR2_WSW_OFFSET((x)))
+#define MXC_CCM_LTR2_EMAC_OFFSET 0
+#define MXC_CCM_LTR2_EMAC_MASK 0x1FF
+
+/*
+ * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
+ */
+#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3)
+#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << MXC_CCM_LTR3_WSW_OFFSET((x)))
+
+#define MXC_CCM_PMCR0_DFSUP1 0x80000000
+#define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31)
+#define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31)
+#define MXC_CCM_PMCR0_DFSUP0 0x40000000
+#define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30)
+#define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30)
+#define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30)
+
+#define DVSUP_TURBO 0
+#define DVSUP_HIGH 1
+#define DVSUP_MEDIUM 2
+#define DVSUP_LOW 3
+#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28)
+#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28)
+#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28)
+#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28)
+#define MXC_CCM_PMCR0_DVSUP_OFFSET 28
+#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28)
+#define MXC_CCM_PMCR0_UDSC 0x08000000
+#define MXC_CCM_PMCR0_UDSC_MASK (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_UP (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27)
+
+#define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24)
+#define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24)
+#define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24)
+#define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24)
+#define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24)
+#define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24)
+#define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24)
+#define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24)
+#define MXC_CCM_PMCR0_VSCNT_OFFSET 24
+#define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24)
+#define MXC_CCM_PMCR0_DVFEV 0x00800000
+#define MXC_CCM_PMCR0_DVFIS 0x00400000
+#define MXC_CCM_PMCR0_LBMI 0x00200000
+#define MXC_CCM_PMCR0_LBFL 0x00100000
+#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18)
+#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18)
+#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18)
+#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18)
+#define MXC_CCM_PMCR0_LBCF_OFFSET 18
+#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18)
+#define MXC_CCM_PMCR0_PTVIS 0x00020000
+#define MXC_CCM_PMCR0_UPDTEN 0x00010000
+#define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16)
+#define MXC_CCM_PMCR0_FSVAIM 0x00008000
+#define MXC_CCM_PMCR0_FSVAI_OFFSET 13
+#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13)
+#define MXC_CCM_PMCR0_DPVCR 0x00001000
+#define MXC_CCM_PMCR0_DPVV 0x00000800
+#define MXC_CCM_PMCR0_WFIM 0x00000400
+#define MXC_CCM_PMCR0_DRCE3 0x00000200
+#define MXC_CCM_PMCR0_DRCE2 0x00000100
+#define MXC_CCM_PMCR0_DRCE1 0x00000080
+#define MXC_CCM_PMCR0_DRCE0 0x00000040
+#define MXC_CCM_PMCR0_DCR 0x00000020
+#define MXC_CCM_PMCR0_DVFEN 0x00000010
+#define MXC_CCM_PMCR0_PTVAIM 0x00000008
+#define MXC_CCM_PMCR0_PTVAI_OFFSET 1
+#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1)
+#define MXC_CCM_PMCR0_DPTEN 0x00000001
+
+#define MXC_CCM_PMCR1_DVGP_OFFSET 0
+#define MXC_CCM_PMCR1_DVGP_MASK (0xF)
+
+#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7)
+#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8)
+
+#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22)
+#define MXC_CCM_DCVR_ULV_OFFSET 22
+#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12)
+#define MXC_CCM_DCVR_LLV_OFFSET 12
+#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2)
+#define MXC_CCM_DCVR_ELV_OFFSET 2
+
+#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7)
+#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7
+#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F
+#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0
+
+#define MXC_CCM_COSR_CLKOSEL_MASK 0x0F
+#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
+#define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6)
+#define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6
+#define MXC_CCM_COSR_CLKOEN (1 << 9)
+
+/*
+ * PMCR0 register offsets
+ */
+#define MXC_CCM_PMCR0_LBFL_OFFSET 20
+#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
+#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
+
+#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
diff -urN linux-2.6.26/arch/arm/mach-mx3/devices.c linux-2.6.26-lab126/arch/arm/mach-mx3/devices.c
--- linux-2.6.26/arch/arm/mach-mx3/devices.c 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.26-lab126/arch/arm/mach-mx3/devices.c 2010-08-10 04:14:16.000000000 -0400
@@ -0,0 +1,858 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+#include
+#include
+#include