%FILENAME%
vtr-9.0.0-1-x86_64.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
7695515

%ISIZE%
26121924

%MD5SUM%
490e249f4c540f3b0dc6518aaebd1fbf

%SHA256SUM%
75a15f72968861eaebf73fc37b94c7aabde369ffa18b866f4bc59e80d3440504

%PGPSIG%
iQEzBAABCgAdFiEEFRnVq6Zb9vwrc8dWek52CV2KUuQFAmhNvRcACgkQek52CV2KUuTkAwf9GlY7ExgPwozLPPE4h6PqCUcLD7VzOqI4lv2hfe1yGXGmcPaHhD1nfHTftxF6k8DwyvT/XoqCBHdc2te7ztpS4LeTaLGStgcHKAJwSaUQpw8txJfG1bqn+BUydYq5TdJYBp3SOGcTnCk1My5uoAF/5XoZAByAHEj5NiSZYfbWMcrt8OjA1Rh6qbyGTKjw9d8a8sp+cx/q23Ijn2GMuE4XigZ+n3mGfOGa87xCJLeQWQuACfs3EU6tTbJdabiAZ1oEs6C7U0Dd89w7R2mMalkELWT+u/Rj03QdQ0bwAQg90h4gNfbu8NSH9cn0a1hzM+LkqyasqPSKD+lPCLJwUTWbig==

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64

%BUILDDATE%
1749924375

%PACKAGER%
Antonio Rojas <arojas@archlinux.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

